1 /*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54 #include "opt_bce.h" 55 56 #include <dev/bce/if_bcereg.h> 57 #include <dev/bce/if_bcefw.h> 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89 #endif 90 91 /****************************************************************************/ 92 /* PCI Device ID Table */ 93 /* */ 94 /* Used by bce_probe() to identify the devices supported by this driver. */ 95 /****************************************************************************/ 96 #define BCE_DEVDESC_MAX 64 97 98 static struct bce_type bce_devs[] = { 99 /* BCM5706C Controllers and OEM boards. */ 100 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 101 "HP NC370T Multifunction Gigabit Server Adapter" }, 102 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 103 "HP NC370i Multifunction Gigabit Server Adapter" }, 104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 105 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 107 "HP NC371i Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 109 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 110 111 /* BCM5706S controllers and OEM boards. */ 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 113 "HP NC370F Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 116 117 /* BCM5708C controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 119 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 121 "HP NC373i Multifunction Gigabit Server Adapter" }, 122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 123 "HP NC374m PCIe Multifunction Adapter" }, 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 125 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 126 127 /* BCM5708S controllers and OEM boards. */ 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 129 "HP NC373m Multifunction Gigabit Server Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 131 "HP NC373i Multifunction Gigabit Server Adapter" }, 132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 133 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 135 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 136 137 /* BCM5709C controllers and OEM boards. */ 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 139 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 141 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 143 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 144 145 /* BCM5709S controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 147 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 149 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 151 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 152 153 /* BCM5716 controllers and OEM boards. */ 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 155 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 156 157 { 0, 0, 0, 0, NULL } 158 }; 159 160 161 /****************************************************************************/ 162 /* Supported Flash NVRAM device data. */ 163 /****************************************************************************/ 164 static struct flash_spec flash_table[] = 165 { 166 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 167 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 168 169 /* Slow EEPROM */ 170 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 171 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 172 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 173 "EEPROM - slow"}, 174 /* Expansion entry 0001 */ 175 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 178 "Entry 0001"}, 179 /* Saifun SA25F010 (non-buffered flash) */ 180 /* strap, cfg1, & write1 need updates */ 181 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 184 "Non-buffered flash (128kB)"}, 185 /* Saifun SA25F020 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 190 "Non-buffered flash (256kB)"}, 191 /* Expansion entry 0100 */ 192 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0100"}, 196 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 197 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 198 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 199 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 200 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 201 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 202 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 204 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 205 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 206 /* Saifun SA25F005 (non-buffered flash) */ 207 /* strap, cfg1, & write1 need updates */ 208 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 210 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 211 "Non-buffered flash (64kB)"}, 212 /* Fast EEPROM */ 213 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 214 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 215 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 216 "EEPROM - fast"}, 217 /* Expansion entry 1001 */ 218 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 221 "Entry 1001"}, 222 /* Expansion entry 1010 */ 223 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 226 "Entry 1010"}, 227 /* ATMEL AT45DB011B (buffered flash) */ 228 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 230 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 231 "Buffered flash (128kB)"}, 232 /* Expansion entry 1100 */ 233 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 236 "Entry 1100"}, 237 /* Expansion entry 1101 */ 238 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 1101"}, 242 /* Ateml Expansion entry 1110 */ 243 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 244 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 245 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 246 "Entry 1110 (Atmel)"}, 247 /* ATMEL AT45DB021B (buffered flash) */ 248 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 251 "Buffered flash (256kB)"}, 252 }; 253 254 /* 255 * The BCM5709 controllers transparently handle the 256 * differences between Atmel 264 byte pages and all 257 * flash devices which use 256 byte pages, so no 258 * logical-to-physical mapping is required in the 259 * driver. 260 */ 261 static struct flash_spec flash_5709 = { 262 .flags = BCE_NV_BUFFERED, 263 .page_bits = BCM5709_FLASH_PAGE_BITS, 264 .page_size = BCM5709_FLASH_PAGE_SIZE, 265 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 266 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 267 .name = "5709/5716 buffered flash (256kB)", 268 }; 269 270 271 /****************************************************************************/ 272 /* FreeBSD device entry points. */ 273 /****************************************************************************/ 274 static int bce_probe (device_t); 275 static int bce_attach (device_t); 276 static int bce_detach (device_t); 277 static int bce_shutdown (device_t); 278 279 280 /****************************************************************************/ 281 /* BCE Debug Data Structure Dump Routines */ 282 /****************************************************************************/ 283 #ifdef BCE_DEBUG 284 static u32 bce_reg_rd (struct bce_softc *, u32); 285 static void bce_reg_wr (struct bce_softc *, u32, u32); 286 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 287 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 288 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 289 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 290 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 291 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 292 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 293 static void bce_dump_txbd (struct bce_softc *, 294 int, struct tx_bd *); 295 static void bce_dump_rxbd (struct bce_softc *, 296 int, struct rx_bd *); 297 static void bce_dump_pgbd (struct bce_softc *, 298 int, struct rx_bd *); 299 static void bce_dump_l2fhdr (struct bce_softc *, 300 int, struct l2_fhdr *); 301 static void bce_dump_ctx (struct bce_softc *, u16); 302 static void bce_dump_ftqs (struct bce_softc *); 303 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 304 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 305 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 306 static void bce_dump_status_block (struct bce_softc *); 307 static void bce_dump_stats_block (struct bce_softc *); 308 static void bce_dump_driver_state (struct bce_softc *); 309 static void bce_dump_hw_state (struct bce_softc *); 310 static void bce_dump_shmem_state (struct bce_softc *); 311 static void bce_dump_mq_regs (struct bce_softc *); 312 static void bce_dump_bc_state (struct bce_softc *); 313 static void bce_dump_txp_state (struct bce_softc *, int); 314 static void bce_dump_rxp_state (struct bce_softc *, int); 315 static void bce_dump_tpat_state (struct bce_softc *, int); 316 static void bce_dump_cp_state (struct bce_softc *, int); 317 static void bce_dump_com_state (struct bce_softc *, int); 318 static void bce_dump_rv2p_state (struct bce_softc *); 319 static void bce_breakpoint (struct bce_softc *); 320 #endif /*BCE_DEBUG */ 321 322 323 /****************************************************************************/ 324 /* BCE Register/Memory Access Routines */ 325 /****************************************************************************/ 326 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 327 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 328 static void bce_shmem_wr (struct bce_softc *, u32, u32); 329 static u32 bce_shmem_rd (struct bce_softc *, u32); 330 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 331 static int bce_miibus_read_reg (device_t, int, int); 332 static int bce_miibus_write_reg (device_t, int, int, int); 333 static void bce_miibus_statchg (device_t); 334 335 #ifdef BCE_DEBUG 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 337 #ifdef BCE_NVRAM_WRITE_SUPPORT 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 339 #endif 340 #endif 341 342 /****************************************************************************/ 343 /* BCE NVRAM Access Routines */ 344 /****************************************************************************/ 345 static int bce_acquire_nvram_lock (struct bce_softc *); 346 static int bce_release_nvram_lock (struct bce_softc *); 347 static void bce_enable_nvram_access(struct bce_softc *); 348 static void bce_disable_nvram_access(struct bce_softc *); 349 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 350 static int bce_init_nvram (struct bce_softc *); 351 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 352 static int bce_nvram_test (struct bce_softc *); 353 #ifdef BCE_NVRAM_WRITE_SUPPORT 354 static int bce_enable_nvram_write (struct bce_softc *); 355 static void bce_disable_nvram_write(struct bce_softc *); 356 static int bce_nvram_erase_page (struct bce_softc *, u32); 357 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 358 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 359 #endif 360 361 /****************************************************************************/ 362 /* */ 363 /****************************************************************************/ 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 365 static void bce_get_media (struct bce_softc *); 366 static void bce_init_media (struct bce_softc *); 367 static u32 bce_get_rphy_link (struct bce_softc *); 368 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 369 static int bce_dma_alloc (device_t); 370 static void bce_dma_free (struct bce_softc *); 371 static void bce_release_resources (struct bce_softc *); 372 373 /****************************************************************************/ 374 /* BCE Firmware Synchronization and Load */ 375 /****************************************************************************/ 376 static void bce_fw_cap_init (struct bce_softc *); 377 static int bce_fw_sync (struct bce_softc *, u32); 378 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 379 static void bce_load_cpu_fw (struct bce_softc *, 380 struct cpu_reg *, struct fw_info *); 381 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 382 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 383 static void bce_start_rxp_cpu (struct bce_softc *); 384 static void bce_init_rxp_cpu (struct bce_softc *); 385 static void bce_init_txp_cpu (struct bce_softc *); 386 static void bce_init_tpat_cpu (struct bce_softc *); 387 static void bce_init_cp_cpu (struct bce_softc *); 388 static void bce_init_com_cpu (struct bce_softc *); 389 static void bce_init_cpus (struct bce_softc *); 390 391 static void bce_print_adapter_info (struct bce_softc *); 392 static void bce_probe_pci_caps (device_t, struct bce_softc *); 393 static void bce_stop (struct bce_softc *); 394 static int bce_reset (struct bce_softc *, u32); 395 static int bce_chipinit (struct bce_softc *); 396 static int bce_blockinit (struct bce_softc *); 397 398 static int bce_init_tx_chain (struct bce_softc *); 399 static void bce_free_tx_chain (struct bce_softc *); 400 401 static int bce_get_rx_buf (struct bce_softc *, 402 struct mbuf *, u16 *, u16 *, u32 *); 403 static int bce_init_rx_chain (struct bce_softc *); 404 static void bce_fill_rx_chain (struct bce_softc *); 405 static void bce_free_rx_chain (struct bce_softc *); 406 407 static int bce_get_pg_buf (struct bce_softc *, 408 struct mbuf *, u16 *, u16 *); 409 static int bce_init_pg_chain (struct bce_softc *); 410 static void bce_fill_pg_chain (struct bce_softc *); 411 static void bce_free_pg_chain (struct bce_softc *); 412 413 static struct mbuf *bce_tso_setup (struct bce_softc *, 414 struct mbuf **, u16 *); 415 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 416 static void bce_start_locked (struct ifnet *); 417 static void bce_start (struct ifnet *); 418 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 419 static void bce_watchdog (struct bce_softc *); 420 static int bce_ifmedia_upd (struct ifnet *); 421 static int bce_ifmedia_upd_locked (struct ifnet *); 422 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 423 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 424 static void bce_init_locked (struct bce_softc *); 425 static void bce_init (void *); 426 static void bce_mgmt_init_locked (struct bce_softc *sc); 427 428 static int bce_init_ctx (struct bce_softc *); 429 static void bce_get_mac_addr (struct bce_softc *); 430 static void bce_set_mac_addr (struct bce_softc *); 431 static void bce_phy_intr (struct bce_softc *); 432 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 433 static void bce_rx_intr (struct bce_softc *); 434 static void bce_tx_intr (struct bce_softc *); 435 static void bce_disable_intr (struct bce_softc *); 436 static void bce_enable_intr (struct bce_softc *, int); 437 438 static void bce_intr (void *); 439 static void bce_set_rx_mode (struct bce_softc *); 440 static void bce_stats_update (struct bce_softc *); 441 static void bce_tick (void *); 442 static void bce_pulse (void *); 443 static void bce_add_sysctls (struct bce_softc *); 444 445 446 /****************************************************************************/ 447 /* FreeBSD device dispatch table. */ 448 /****************************************************************************/ 449 static device_method_t bce_methods[] = { 450 /* Device interface (device_if.h) */ 451 DEVMETHOD(device_probe, bce_probe), 452 DEVMETHOD(device_attach, bce_attach), 453 DEVMETHOD(device_detach, bce_detach), 454 DEVMETHOD(device_shutdown, bce_shutdown), 455 /* Supported by device interface but not used here. */ 456 /* DEVMETHOD(device_identify, bce_identify), */ 457 /* DEVMETHOD(device_suspend, bce_suspend), */ 458 /* DEVMETHOD(device_resume, bce_resume), */ 459 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 460 461 /* MII interface (miibus_if.h) */ 462 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 463 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 464 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 465 /* Supported by MII interface but not used here. */ 466 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 467 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 468 469 DEVMETHOD_END 470 }; 471 472 static driver_t bce_driver = { 473 "bce", 474 bce_methods, 475 sizeof(struct bce_softc) 476 }; 477 478 static devclass_t bce_devclass; 479 480 MODULE_DEPEND(bce, pci, 1, 1, 1); 481 MODULE_DEPEND(bce, ether, 1, 1, 1); 482 MODULE_DEPEND(bce, miibus, 1, 1, 1); 483 484 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 485 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 486 487 488 /****************************************************************************/ 489 /* Tunable device values */ 490 /****************************************************************************/ 491 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 492 493 /* Allowable values are TRUE or FALSE */ 494 static int bce_verbose = TRUE; 495 TUNABLE_INT("hw.bce.verbose", &bce_verbose); 496 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 497 "Verbose output enable/disable"); 498 499 /* Allowable values are TRUE or FALSE */ 500 static int bce_tso_enable = TRUE; 501 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 502 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 503 "TSO Enable/Disable"); 504 505 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 506 /* ToDo: Add MSI-X support. */ 507 static int bce_msi_enable = 1; 508 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 509 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 510 "MSI-X|MSI|INTx selector"); 511 512 /* Allowable values are 1, 2, 4, 8. */ 513 static int bce_rx_pages = DEFAULT_RX_PAGES; 514 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 515 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 516 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 517 518 /* Allowable values are 1, 2, 4, 8. */ 519 static int bce_tx_pages = DEFAULT_TX_PAGES; 520 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 521 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 522 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 523 524 /* Allowable values are TRUE or FALSE. */ 525 static int bce_hdr_split = TRUE; 526 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 527 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 528 "Frame header/payload splitting Enable/Disable"); 529 530 /* Allowable values are TRUE or FALSE. */ 531 static int bce_strict_rx_mtu = FALSE; 532 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 533 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 534 &bce_strict_rx_mtu, 0, 535 "Enable/Disable strict RX frame size checking"); 536 537 /* Allowable values are 0 ... 100 */ 538 #ifdef BCE_DEBUG 539 /* Generate 1 interrupt for every transmit completion. */ 540 static int bce_tx_quick_cons_trip_int = 1; 541 #else 542 /* Generate 1 interrupt for every 20 transmit completions. */ 543 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 544 #endif 545 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 546 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 547 &bce_tx_quick_cons_trip_int, 0, 548 "Transmit BD trip point during interrupts"); 549 550 /* Allowable values are 0 ... 100 */ 551 /* Generate 1 interrupt for every transmit completion. */ 552 #ifdef BCE_DEBUG 553 static int bce_tx_quick_cons_trip = 1; 554 #else 555 /* Generate 1 interrupt for every 20 transmit completions. */ 556 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 557 #endif 558 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 559 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 560 &bce_tx_quick_cons_trip, 0, 561 "Transmit BD trip point"); 562 563 /* Allowable values are 0 ... 100 */ 564 #ifdef BCE_DEBUG 565 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 566 static int bce_tx_ticks_int = 0; 567 #else 568 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 569 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 570 #endif 571 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 572 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 573 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 574 575 /* Allowable values are 0 ... 100 */ 576 #ifdef BCE_DEBUG 577 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 578 static int bce_tx_ticks = 0; 579 #else 580 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 581 static int bce_tx_ticks = DEFAULT_TX_TICKS; 582 #endif 583 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 584 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 585 &bce_tx_ticks, 0, "Transmit ticks count"); 586 587 /* Allowable values are 1 ... 100 */ 588 #ifdef BCE_DEBUG 589 /* Generate 1 interrupt for every received frame. */ 590 static int bce_rx_quick_cons_trip_int = 1; 591 #else 592 /* Generate 1 interrupt for every 6 received frames. */ 593 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 594 #endif 595 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 596 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 597 &bce_rx_quick_cons_trip_int, 0, 598 "Receive BD trip point duirng interrupts"); 599 600 /* Allowable values are 1 ... 100 */ 601 #ifdef BCE_DEBUG 602 /* Generate 1 interrupt for every received frame. */ 603 static int bce_rx_quick_cons_trip = 1; 604 #else 605 /* Generate 1 interrupt for every 6 received frames. */ 606 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 607 #endif 608 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 609 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 610 &bce_rx_quick_cons_trip, 0, 611 "Receive BD trip point"); 612 613 /* Allowable values are 0 ... 100 */ 614 #ifdef BCE_DEBUG 615 /* Generate an int. if 0us have elapsed since the last received frame. */ 616 static int bce_rx_ticks_int = 0; 617 #else 618 /* Generate an int. if 18us have elapsed since the last received frame. */ 619 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 620 #endif 621 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 622 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 623 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 624 625 /* Allowable values are 0 ... 100 */ 626 #ifdef BCE_DEBUG 627 /* Generate an int. if 0us have elapsed since the last received frame. */ 628 static int bce_rx_ticks = 0; 629 #else 630 /* Generate an int. if 18us have elapsed since the last received frame. */ 631 static int bce_rx_ticks = DEFAULT_RX_TICKS; 632 #endif 633 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 634 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 635 &bce_rx_ticks, 0, "Receive ticks count"); 636 637 638 /****************************************************************************/ 639 /* Device probe function. */ 640 /* */ 641 /* Compares the device to the driver's list of supported devices and */ 642 /* reports back to the OS whether this is the right driver for the device. */ 643 /* */ 644 /* Returns: */ 645 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 646 /****************************************************************************/ 647 static int 648 bce_probe(device_t dev) 649 { 650 struct bce_type *t; 651 struct bce_softc *sc; 652 char *descbuf; 653 u16 vid = 0, did = 0, svid = 0, sdid = 0; 654 655 t = bce_devs; 656 657 sc = device_get_softc(dev); 658 bzero(sc, sizeof(struct bce_softc)); 659 sc->bce_unit = device_get_unit(dev); 660 sc->bce_dev = dev; 661 662 /* Get the data for the device to be probed. */ 663 vid = pci_get_vendor(dev); 664 did = pci_get_device(dev); 665 svid = pci_get_subvendor(dev); 666 sdid = pci_get_subdevice(dev); 667 668 DBPRINT(sc, BCE_EXTREME_LOAD, 669 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 670 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 671 672 /* Look through the list of known devices for a match. */ 673 while(t->bce_name != NULL) { 674 675 if ((vid == t->bce_vid) && (did == t->bce_did) && 676 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 677 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 678 679 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 680 681 if (descbuf == NULL) 682 return(ENOMEM); 683 684 /* Print out the device identity. */ 685 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 686 t->bce_name, (((pci_read_config(dev, 687 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 688 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 689 690 device_set_desc_copy(dev, descbuf); 691 free(descbuf, M_TEMP); 692 return(BUS_PROBE_DEFAULT); 693 } 694 t++; 695 } 696 697 return(ENXIO); 698 } 699 700 701 /****************************************************************************/ 702 /* PCI Capabilities Probe Function. */ 703 /* */ 704 /* Walks the PCI capabiites list for the device to find what features are */ 705 /* supported. */ 706 /* */ 707 /* Returns: */ 708 /* None. */ 709 /****************************************************************************/ 710 static void 711 bce_print_adapter_info(struct bce_softc *sc) 712 { 713 int i = 0; 714 715 DBENTER(BCE_VERBOSE_LOAD); 716 717 if (bce_verbose || bootverbose) { 718 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 719 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 720 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 721 722 723 /* Bus info. */ 724 if (sc->bce_flags & BCE_PCIE_FLAG) { 725 printf("Bus (PCIe x%d, ", sc->link_width); 726 switch (sc->link_speed) { 727 case 1: printf("2.5Gbps); "); break; 728 case 2: printf("5Gbps); "); break; 729 default: printf("Unknown link speed); "); 730 } 731 } else { 732 printf("Bus (PCI%s, %s, %dMHz); ", 733 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 734 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 735 "32-bit" : "64-bit"), sc->bus_speed_mhz); 736 } 737 738 /* Firmware version and device features. */ 739 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 740 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 741 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 742 743 if (bce_hdr_split == TRUE) { 744 printf("SPLT"); 745 i++; 746 } 747 748 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 749 if (i > 0) printf("|"); 750 printf("MSI"); i++; 751 } 752 753 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 754 if (i > 0) printf("|"); 755 printf("MSI-X"); i++; 756 } 757 758 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 759 if (i > 0) printf("|"); 760 printf("2.5G"); i++; 761 } 762 763 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 764 if (i > 0) printf("|"); 765 printf("Remote PHY(%s)", 766 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 767 "FIBER" : "TP"); i++; 768 } 769 770 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 771 if (i > 0) printf("|"); 772 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 773 } else { 774 printf(")\n"); 775 } 776 777 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 778 sc->bce_rx_quick_cons_trip_int, 779 sc->bce_rx_quick_cons_trip, 780 sc->bce_rx_ticks_int, 781 sc->bce_rx_ticks, 782 sc->bce_tx_quick_cons_trip_int, 783 sc->bce_tx_quick_cons_trip, 784 sc->bce_tx_ticks_int, 785 sc->bce_tx_ticks); 786 787 } 788 789 DBEXIT(BCE_VERBOSE_LOAD); 790 } 791 792 793 /****************************************************************************/ 794 /* PCI Capabilities Probe Function. */ 795 /* */ 796 /* Walks the PCI capabiites list for the device to find what features are */ 797 /* supported. */ 798 /* */ 799 /* Returns: */ 800 /* None. */ 801 /****************************************************************************/ 802 static void 803 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 804 { 805 u32 reg; 806 807 DBENTER(BCE_VERBOSE_LOAD); 808 809 /* Check if PCI-X capability is enabled. */ 810 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 811 if (reg != 0) 812 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 813 } 814 815 /* Check if PCIe capability is enabled. */ 816 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 817 if (reg != 0) { 818 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 819 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 820 "0x%08X\n", link_status); 821 sc->link_speed = link_status & 0xf; 822 sc->link_width = (link_status >> 4) & 0x3f; 823 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 824 sc->bce_flags |= BCE_PCIE_FLAG; 825 } 826 } 827 828 /* Check if MSI capability is enabled. */ 829 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 830 if (reg != 0) 831 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 832 } 833 834 /* Check if MSI-X capability is enabled. */ 835 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 836 if (reg != 0) 837 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 838 } 839 840 DBEXIT(BCE_VERBOSE_LOAD); 841 } 842 843 844 /****************************************************************************/ 845 /* Load and validate user tunable settings. */ 846 /* */ 847 /* Returns: */ 848 /* Nothing. */ 849 /****************************************************************************/ 850 static void 851 bce_set_tunables(struct bce_softc *sc) 852 { 853 /* Set sysctl values for RX page count. */ 854 switch (bce_rx_pages) { 855 case 1: 856 /* fall-through */ 857 case 2: 858 /* fall-through */ 859 case 4: 860 /* fall-through */ 861 case 8: 862 sc->rx_pages = bce_rx_pages; 863 break; 864 default: 865 sc->rx_pages = DEFAULT_RX_PAGES; 866 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 867 "hw.bce.rx_pages! Setting default of %d.\n", 868 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 869 } 870 871 /* ToDo: Consider allowing user setting for pg_pages. */ 872 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 873 874 /* Set sysctl values for TX page count. */ 875 switch (bce_tx_pages) { 876 case 1: 877 /* fall-through */ 878 case 2: 879 /* fall-through */ 880 case 4: 881 /* fall-through */ 882 case 8: 883 sc->tx_pages = bce_tx_pages; 884 break; 885 default: 886 sc->tx_pages = DEFAULT_TX_PAGES; 887 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 888 "hw.bce.tx_pages! Setting default of %d.\n", 889 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 890 } 891 892 /* 893 * Validate the TX trip point (i.e. the number of 894 * TX completions before a status block update is 895 * generated and an interrupt is asserted. 896 */ 897 if (bce_tx_quick_cons_trip_int <= 100) { 898 sc->bce_tx_quick_cons_trip_int = 899 bce_tx_quick_cons_trip_int; 900 } else { 901 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 902 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 903 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 904 DEFAULT_TX_QUICK_CONS_TRIP_INT); 905 sc->bce_tx_quick_cons_trip_int = 906 DEFAULT_TX_QUICK_CONS_TRIP_INT; 907 } 908 909 if (bce_tx_quick_cons_trip <= 100) { 910 sc->bce_tx_quick_cons_trip = 911 bce_tx_quick_cons_trip; 912 } else { 913 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 914 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 915 __FILE__, __LINE__, bce_tx_quick_cons_trip, 916 DEFAULT_TX_QUICK_CONS_TRIP); 917 sc->bce_tx_quick_cons_trip = 918 DEFAULT_TX_QUICK_CONS_TRIP; 919 } 920 921 /* 922 * Validate the TX ticks count (i.e. the maximum amount 923 * of time to wait after the last TX completion has 924 * occurred before a status block update is generated 925 * and an interrupt is asserted. 926 */ 927 if (bce_tx_ticks_int <= 100) { 928 sc->bce_tx_ticks_int = 929 bce_tx_ticks_int; 930 } else { 931 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 932 "hw.bce.tx_ticks_int! Setting default of %d.\n", 933 __FILE__, __LINE__, bce_tx_ticks_int, 934 DEFAULT_TX_TICKS_INT); 935 sc->bce_tx_ticks_int = 936 DEFAULT_TX_TICKS_INT; 937 } 938 939 if (bce_tx_ticks <= 100) { 940 sc->bce_tx_ticks = 941 bce_tx_ticks; 942 } else { 943 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 944 "hw.bce.tx_ticks! Setting default of %d.\n", 945 __FILE__, __LINE__, bce_tx_ticks, 946 DEFAULT_TX_TICKS); 947 sc->bce_tx_ticks = 948 DEFAULT_TX_TICKS; 949 } 950 951 /* 952 * Validate the RX trip point (i.e. the number of 953 * RX frames received before a status block update is 954 * generated and an interrupt is asserted. 955 */ 956 if (bce_rx_quick_cons_trip_int <= 100) { 957 sc->bce_rx_quick_cons_trip_int = 958 bce_rx_quick_cons_trip_int; 959 } else { 960 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 961 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 962 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 963 DEFAULT_RX_QUICK_CONS_TRIP_INT); 964 sc->bce_rx_quick_cons_trip_int = 965 DEFAULT_RX_QUICK_CONS_TRIP_INT; 966 } 967 968 if (bce_rx_quick_cons_trip <= 100) { 969 sc->bce_rx_quick_cons_trip = 970 bce_rx_quick_cons_trip; 971 } else { 972 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 973 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 974 __FILE__, __LINE__, bce_rx_quick_cons_trip, 975 DEFAULT_RX_QUICK_CONS_TRIP); 976 sc->bce_rx_quick_cons_trip = 977 DEFAULT_RX_QUICK_CONS_TRIP; 978 } 979 980 /* 981 * Validate the RX ticks count (i.e. the maximum amount 982 * of time to wait after the last RX frame has been 983 * received before a status block update is generated 984 * and an interrupt is asserted. 985 */ 986 if (bce_rx_ticks_int <= 100) { 987 sc->bce_rx_ticks_int = bce_rx_ticks_int; 988 } else { 989 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 990 "hw.bce.rx_ticks_int! Setting default of %d.\n", 991 __FILE__, __LINE__, bce_rx_ticks_int, 992 DEFAULT_RX_TICKS_INT); 993 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 994 } 995 996 if (bce_rx_ticks <= 100) { 997 sc->bce_rx_ticks = bce_rx_ticks; 998 } else { 999 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1000 "hw.bce.rx_ticks! Setting default of %d.\n", 1001 __FILE__, __LINE__, bce_rx_ticks, 1002 DEFAULT_RX_TICKS); 1003 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1004 } 1005 1006 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1007 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1008 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1009 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1010 __FILE__, __LINE__); 1011 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1012 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1013 } 1014 1015 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1016 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1017 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1018 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1019 __FILE__, __LINE__); 1020 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1021 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1022 } 1023 1024 } 1025 1026 1027 /****************************************************************************/ 1028 /* Device attach function. */ 1029 /* */ 1030 /* Allocates device resources, performs secondary chip identification, */ 1031 /* resets and initializes the hardware, and initializes driver instance */ 1032 /* variables. */ 1033 /* */ 1034 /* Returns: */ 1035 /* 0 on success, positive value on failure. */ 1036 /****************************************************************************/ 1037 static int 1038 bce_attach(device_t dev) 1039 { 1040 struct bce_softc *sc; 1041 struct ifnet *ifp; 1042 u32 val; 1043 int error, rid, rc = 0; 1044 1045 sc = device_get_softc(dev); 1046 sc->bce_dev = dev; 1047 1048 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1049 1050 sc->bce_unit = device_get_unit(dev); 1051 1052 /* Set initial device and PHY flags */ 1053 sc->bce_flags = 0; 1054 sc->bce_phy_flags = 0; 1055 1056 bce_set_tunables(sc); 1057 1058 pci_enable_busmaster(dev); 1059 1060 /* Allocate PCI memory resources. */ 1061 rid = PCIR_BAR(0); 1062 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1063 &rid, RF_ACTIVE); 1064 1065 if (sc->bce_res_mem == NULL) { 1066 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1067 __FILE__, __LINE__); 1068 rc = ENXIO; 1069 goto bce_attach_fail; 1070 } 1071 1072 /* Get various resource handles. */ 1073 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1074 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1075 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1076 1077 bce_probe_pci_caps(dev, sc); 1078 1079 rid = 1; 1080 #if 0 1081 /* Try allocating MSI-X interrupts. */ 1082 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1083 (bce_msi_enable >= 2) && 1084 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1085 &rid, RF_ACTIVE)) != NULL)) { 1086 1087 msi_needed = sc->bce_msi_count = 1; 1088 1089 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 1090 (sc->bce_msi_count != msi_needed)) { 1091 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1092 "Received = %d, error = %d\n", __FILE__, __LINE__, 1093 msi_needed, sc->bce_msi_count, error); 1094 sc->bce_msi_count = 0; 1095 pci_release_msi(dev); 1096 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1097 sc->bce_res_irq); 1098 sc->bce_res_irq = NULL; 1099 } else { 1100 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1101 __FUNCTION__); 1102 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1103 sc->bce_intr = bce_intr; 1104 } 1105 } 1106 #endif 1107 1108 /* Try allocating a MSI interrupt. */ 1109 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1110 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 1111 sc->bce_msi_count = 1; 1112 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 1113 BCE_PRINTF("%s(%d): MSI allocation failed! " 1114 "error = %d\n", __FILE__, __LINE__, error); 1115 sc->bce_msi_count = 0; 1116 pci_release_msi(dev); 1117 } else { 1118 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1119 "interrupt.\n", __FUNCTION__); 1120 sc->bce_flags |= BCE_USING_MSI_FLAG; 1121 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1122 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1123 sc->bce_irq_rid = 1; 1124 sc->bce_intr = bce_intr; 1125 } 1126 } 1127 1128 /* Try allocating a legacy interrupt. */ 1129 if (sc->bce_msi_count == 0) { 1130 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1131 __FUNCTION__); 1132 rid = 0; 1133 sc->bce_intr = bce_intr; 1134 } 1135 1136 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1137 &rid, RF_SHAREABLE | RF_ACTIVE); 1138 1139 sc->bce_irq_rid = rid; 1140 1141 /* Report any IRQ allocation errors. */ 1142 if (sc->bce_res_irq == NULL) { 1143 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1144 __FILE__, __LINE__); 1145 rc = ENXIO; 1146 goto bce_attach_fail; 1147 } 1148 1149 /* Initialize mutex for the current device instance. */ 1150 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1151 1152 /* 1153 * Configure byte swap and enable indirect register access. 1154 * Rely on CPU to do target byte swapping on big endian systems. 1155 * Access to registers outside of PCI configurtion space are not 1156 * valid until this is done. 1157 */ 1158 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1159 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1160 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1161 1162 /* Save ASIC revsion info. */ 1163 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1164 1165 /* Weed out any non-production controller revisions. */ 1166 switch(BCE_CHIP_ID(sc)) { 1167 case BCE_CHIP_ID_5706_A0: 1168 case BCE_CHIP_ID_5706_A1: 1169 case BCE_CHIP_ID_5708_A0: 1170 case BCE_CHIP_ID_5708_B0: 1171 case BCE_CHIP_ID_5709_A0: 1172 case BCE_CHIP_ID_5709_B0: 1173 case BCE_CHIP_ID_5709_B1: 1174 case BCE_CHIP_ID_5709_B2: 1175 BCE_PRINTF("%s(%d): Unsupported controller " 1176 "revision (%c%d)!\n", __FILE__, __LINE__, 1177 (((pci_read_config(dev, PCIR_REVID, 4) & 1178 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1179 PCIR_REVID, 4) & 0xf)); 1180 rc = ENODEV; 1181 goto bce_attach_fail; 1182 } 1183 1184 /* 1185 * The embedded PCIe to PCI-X bridge (EPB) 1186 * in the 5708 cannot address memory above 1187 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1188 */ 1189 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1190 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1191 else 1192 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1193 1194 /* 1195 * Find the base address for shared memory access. 1196 * Newer versions of bootcode use a signature and offset 1197 * while older versions use a fixed address. 1198 */ 1199 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1200 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1201 /* Multi-port devices use different offsets in shared memory. */ 1202 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1203 (pci_get_function(sc->bce_dev) << 2)); 1204 else 1205 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1206 1207 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1208 __FUNCTION__, sc->bce_shmem_base); 1209 1210 /* Fetch the bootcode revision. */ 1211 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1212 for (int i = 0, j = 0; i < 3; i++) { 1213 u8 num; 1214 1215 num = (u8) (val >> (24 - (i * 8))); 1216 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1217 if (num >= k || !skip0 || k == 1) { 1218 sc->bce_bc_ver[j++] = (num / k) + '0'; 1219 skip0 = 0; 1220 } 1221 } 1222 1223 if (i != 2) 1224 sc->bce_bc_ver[j++] = '.'; 1225 } 1226 1227 /* Check if any management firwmare is enabled. */ 1228 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1229 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1230 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1231 1232 /* Allow time for firmware to enter the running state. */ 1233 for (int i = 0; i < 30; i++) { 1234 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1235 if (val & BCE_CONDITION_MFW_RUN_MASK) 1236 break; 1237 DELAY(10000); 1238 } 1239 1240 /* Check if management firmware is running. */ 1241 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1242 val &= BCE_CONDITION_MFW_RUN_MASK; 1243 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1244 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1245 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1246 int i = 0; 1247 1248 /* Read the management firmware version string. */ 1249 for (int j = 0; j < 3; j++) { 1250 val = bce_reg_rd_ind(sc, addr + j * 4); 1251 val = bswap32(val); 1252 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1253 i += 4; 1254 } 1255 } else { 1256 /* May cause firmware synchronization timeouts. */ 1257 BCE_PRINTF("%s(%d): Management firmware enabled " 1258 "but not running!\n", __FILE__, __LINE__); 1259 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1260 1261 /* ToDo: Any action the driver should take? */ 1262 } 1263 } 1264 1265 /* Get PCI bus information (speed and type). */ 1266 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1267 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1268 u32 clkreg; 1269 1270 sc->bce_flags |= BCE_PCIX_FLAG; 1271 1272 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1273 1274 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1275 switch (clkreg) { 1276 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1277 sc->bus_speed_mhz = 133; 1278 break; 1279 1280 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1281 sc->bus_speed_mhz = 100; 1282 break; 1283 1284 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1285 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1286 sc->bus_speed_mhz = 66; 1287 break; 1288 1289 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1290 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1291 sc->bus_speed_mhz = 50; 1292 break; 1293 1294 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1295 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1296 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1297 sc->bus_speed_mhz = 33; 1298 break; 1299 } 1300 } else { 1301 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1302 sc->bus_speed_mhz = 66; 1303 else 1304 sc->bus_speed_mhz = 33; 1305 } 1306 1307 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1308 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1309 1310 /* Find the media type for the adapter. */ 1311 bce_get_media(sc); 1312 1313 /* Reset controller and announce to bootcode that driver is present. */ 1314 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1315 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1316 __FILE__, __LINE__); 1317 rc = ENXIO; 1318 goto bce_attach_fail; 1319 } 1320 1321 /* Initialize the controller. */ 1322 if (bce_chipinit(sc)) { 1323 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1324 __FILE__, __LINE__); 1325 rc = ENXIO; 1326 goto bce_attach_fail; 1327 } 1328 1329 /* Perform NVRAM test. */ 1330 if (bce_nvram_test(sc)) { 1331 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1332 __FILE__, __LINE__); 1333 rc = ENXIO; 1334 goto bce_attach_fail; 1335 } 1336 1337 /* Fetch the permanent Ethernet MAC address. */ 1338 bce_get_mac_addr(sc); 1339 1340 /* 1341 * Trip points control how many BDs 1342 * should be ready before generating an 1343 * interrupt while ticks control how long 1344 * a BD can sit in the chain before 1345 * generating an interrupt. Set the default 1346 * values for the RX and TX chains. 1347 */ 1348 1349 /* Not used for L2. */ 1350 sc->bce_comp_prod_trip_int = 0; 1351 sc->bce_comp_prod_trip = 0; 1352 sc->bce_com_ticks_int = 0; 1353 sc->bce_com_ticks = 0; 1354 sc->bce_cmd_ticks_int = 0; 1355 sc->bce_cmd_ticks = 0; 1356 1357 /* Update statistics once every second. */ 1358 sc->bce_stats_ticks = 1000000 & 0xffff00; 1359 1360 /* Store data needed by PHY driver for backplane applications */ 1361 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1362 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1363 1364 /* Allocate DMA memory resources. */ 1365 if (bce_dma_alloc(dev)) { 1366 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1367 __FILE__, __LINE__); 1368 rc = ENXIO; 1369 goto bce_attach_fail; 1370 } 1371 1372 /* Allocate an ifnet structure. */ 1373 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1374 if (ifp == NULL) { 1375 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1376 __FILE__, __LINE__); 1377 rc = ENXIO; 1378 goto bce_attach_fail; 1379 } 1380 1381 /* Initialize the ifnet interface. */ 1382 ifp->if_softc = sc; 1383 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1384 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1385 ifp->if_ioctl = bce_ioctl; 1386 ifp->if_start = bce_start; 1387 ifp->if_init = bce_init; 1388 ifp->if_mtu = ETHERMTU; 1389 1390 if (bce_tso_enable) { 1391 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1392 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1393 IFCAP_VLAN_HWTSO; 1394 } else { 1395 ifp->if_hwassist = BCE_IF_HWASSIST; 1396 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1397 } 1398 1399 #if __FreeBSD_version >= 800505 1400 /* 1401 * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version 1402 * so it's approximate value. 1403 */ 1404 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1405 ifp->if_capabilities |= IFCAP_LINKSTATE; 1406 #endif 1407 1408 ifp->if_capenable = ifp->if_capabilities; 1409 1410 /* 1411 * Assume standard mbuf sizes for buffer allocation. 1412 * This may change later if the MTU size is set to 1413 * something other than 1500. 1414 */ 1415 bce_get_rx_buffer_sizes(sc, 1416 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1417 1418 /* Recalculate our buffer allocation sizes. */ 1419 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1420 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1421 IFQ_SET_READY(&ifp->if_snd); 1422 1423 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1424 ifp->if_baudrate = IF_Mbps(2500ULL); 1425 else 1426 ifp->if_baudrate = IF_Mbps(1000); 1427 1428 /* Handle any special PHY initialization for SerDes PHYs. */ 1429 bce_init_media(sc); 1430 1431 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1432 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1433 bce_ifmedia_sts); 1434 /* 1435 * We can't manually override remote PHY's link and assume 1436 * PHY port configuration(Fiber or TP) is not changed after 1437 * device attach. This may not be correct though. 1438 */ 1439 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1440 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1441 ifmedia_add(&sc->bce_ifmedia, 1442 IFM_ETHER | IFM_2500_SX, 0, NULL); 1443 ifmedia_add(&sc->bce_ifmedia, 1444 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1445 } 1446 ifmedia_add(&sc->bce_ifmedia, 1447 IFM_ETHER | IFM_1000_SX, 0, NULL); 1448 ifmedia_add(&sc->bce_ifmedia, 1449 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1450 } else { 1451 ifmedia_add(&sc->bce_ifmedia, 1452 IFM_ETHER | IFM_10_T, 0, NULL); 1453 ifmedia_add(&sc->bce_ifmedia, 1454 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1455 ifmedia_add(&sc->bce_ifmedia, 1456 IFM_ETHER | IFM_100_TX, 0, NULL); 1457 ifmedia_add(&sc->bce_ifmedia, 1458 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1459 ifmedia_add(&sc->bce_ifmedia, 1460 IFM_ETHER | IFM_1000_T, 0, NULL); 1461 ifmedia_add(&sc->bce_ifmedia, 1462 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1463 } 1464 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1465 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1466 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1467 } else { 1468 /* MII child bus by attaching the PHY. */ 1469 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1470 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1471 MII_OFFSET_ANY, MIIF_DOPAUSE); 1472 if (rc != 0) { 1473 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1474 __LINE__); 1475 goto bce_attach_fail; 1476 } 1477 } 1478 1479 /* Attach to the Ethernet interface list. */ 1480 ether_ifattach(ifp, sc->eaddr); 1481 1482 #if __FreeBSD_version < 500000 1483 callout_init(&sc->bce_tick_callout); 1484 callout_init(&sc->bce_pulse_callout); 1485 #else 1486 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1487 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1488 #endif 1489 1490 /* Hookup IRQ last. */ 1491 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1492 NULL, bce_intr, sc, &sc->bce_intrhand); 1493 1494 if (rc) { 1495 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1496 __FILE__, __LINE__); 1497 bce_detach(dev); 1498 goto bce_attach_exit; 1499 } 1500 1501 /* 1502 * At this point we've acquired all the resources 1503 * we need to run so there's no turning back, we're 1504 * cleared for launch. 1505 */ 1506 1507 /* Print some important debugging info. */ 1508 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1509 1510 /* Add the supported sysctls to the kernel. */ 1511 bce_add_sysctls(sc); 1512 1513 BCE_LOCK(sc); 1514 1515 /* 1516 * The chip reset earlier notified the bootcode that 1517 * a driver is present. We now need to start our pulse 1518 * routine so that the bootcode is reminded that we're 1519 * still running. 1520 */ 1521 bce_pulse(sc); 1522 1523 bce_mgmt_init_locked(sc); 1524 BCE_UNLOCK(sc); 1525 1526 /* Finally, print some useful adapter info */ 1527 bce_print_adapter_info(sc); 1528 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1529 __FUNCTION__, sc); 1530 1531 goto bce_attach_exit; 1532 1533 bce_attach_fail: 1534 bce_release_resources(sc); 1535 1536 bce_attach_exit: 1537 1538 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1539 1540 return(rc); 1541 } 1542 1543 1544 /****************************************************************************/ 1545 /* Device detach function. */ 1546 /* */ 1547 /* Stops the controller, resets the controller, and releases resources. */ 1548 /* */ 1549 /* Returns: */ 1550 /* 0 on success, positive value on failure. */ 1551 /****************************************************************************/ 1552 static int 1553 bce_detach(device_t dev) 1554 { 1555 struct bce_softc *sc = device_get_softc(dev); 1556 struct ifnet *ifp; 1557 u32 msg; 1558 1559 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1560 1561 ifp = sc->bce_ifp; 1562 1563 /* Stop and reset the controller. */ 1564 BCE_LOCK(sc); 1565 1566 /* Stop the pulse so the bootcode can go to driver absent state. */ 1567 callout_stop(&sc->bce_pulse_callout); 1568 1569 bce_stop(sc); 1570 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1571 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1572 else 1573 msg = BCE_DRV_MSG_CODE_UNLOAD; 1574 bce_reset(sc, msg); 1575 1576 BCE_UNLOCK(sc); 1577 1578 ether_ifdetach(ifp); 1579 1580 /* If we have a child device on the MII bus remove it too. */ 1581 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1582 ifmedia_removeall(&sc->bce_ifmedia); 1583 else { 1584 bus_generic_detach(dev); 1585 device_delete_child(dev, sc->bce_miibus); 1586 } 1587 1588 /* Release all remaining resources. */ 1589 bce_release_resources(sc); 1590 1591 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1592 1593 return(0); 1594 } 1595 1596 1597 /****************************************************************************/ 1598 /* Device shutdown function. */ 1599 /* */ 1600 /* Stops and resets the controller. */ 1601 /* */ 1602 /* Returns: */ 1603 /* 0 on success, positive value on failure. */ 1604 /****************************************************************************/ 1605 static int 1606 bce_shutdown(device_t dev) 1607 { 1608 struct bce_softc *sc = device_get_softc(dev); 1609 u32 msg; 1610 1611 DBENTER(BCE_VERBOSE); 1612 1613 BCE_LOCK(sc); 1614 bce_stop(sc); 1615 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1616 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1617 else 1618 msg = BCE_DRV_MSG_CODE_UNLOAD; 1619 bce_reset(sc, msg); 1620 BCE_UNLOCK(sc); 1621 1622 DBEXIT(BCE_VERBOSE); 1623 1624 return (0); 1625 } 1626 1627 1628 #ifdef BCE_DEBUG 1629 /****************************************************************************/ 1630 /* Register read. */ 1631 /* */ 1632 /* Returns: */ 1633 /* The value of the register. */ 1634 /****************************************************************************/ 1635 static u32 1636 bce_reg_rd(struct bce_softc *sc, u32 offset) 1637 { 1638 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1639 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1640 __FUNCTION__, offset, val); 1641 return val; 1642 } 1643 1644 1645 /****************************************************************************/ 1646 /* Register write (16 bit). */ 1647 /* */ 1648 /* Returns: */ 1649 /* Nothing. */ 1650 /****************************************************************************/ 1651 static void 1652 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1653 { 1654 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1655 __FUNCTION__, offset, val); 1656 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1657 } 1658 1659 1660 /****************************************************************************/ 1661 /* Register write. */ 1662 /* */ 1663 /* Returns: */ 1664 /* Nothing. */ 1665 /****************************************************************************/ 1666 static void 1667 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1668 { 1669 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1670 __FUNCTION__, offset, val); 1671 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1672 } 1673 #endif 1674 1675 /****************************************************************************/ 1676 /* Indirect register read. */ 1677 /* */ 1678 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1679 /* configuration space. Using this mechanism avoids issues with posted */ 1680 /* reads but is much slower than memory-mapped I/O. */ 1681 /* */ 1682 /* Returns: */ 1683 /* The value of the register. */ 1684 /****************************************************************************/ 1685 static u32 1686 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1687 { 1688 device_t dev; 1689 dev = sc->bce_dev; 1690 1691 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1692 #ifdef BCE_DEBUG 1693 { 1694 u32 val; 1695 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1696 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1697 __FUNCTION__, offset, val); 1698 return val; 1699 } 1700 #else 1701 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1702 #endif 1703 } 1704 1705 1706 /****************************************************************************/ 1707 /* Indirect register write. */ 1708 /* */ 1709 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1710 /* configuration space. Using this mechanism avoids issues with posted */ 1711 /* writes but is muchh slower than memory-mapped I/O. */ 1712 /* */ 1713 /* Returns: */ 1714 /* Nothing. */ 1715 /****************************************************************************/ 1716 static void 1717 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1718 { 1719 device_t dev; 1720 dev = sc->bce_dev; 1721 1722 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1723 __FUNCTION__, offset, val); 1724 1725 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1726 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1727 } 1728 1729 1730 /****************************************************************************/ 1731 /* Shared memory write. */ 1732 /* */ 1733 /* Writes NetXtreme II shared memory region. */ 1734 /* */ 1735 /* Returns: */ 1736 /* Nothing. */ 1737 /****************************************************************************/ 1738 static void 1739 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1740 { 1741 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1742 "0x%08X\n", __FUNCTION__, val, offset); 1743 1744 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1745 } 1746 1747 1748 /****************************************************************************/ 1749 /* Shared memory read. */ 1750 /* */ 1751 /* Reads NetXtreme II shared memory region. */ 1752 /* */ 1753 /* Returns: */ 1754 /* The 32 bit value read. */ 1755 /****************************************************************************/ 1756 static u32 1757 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1758 { 1759 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1760 1761 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1762 "0x%08X\n", __FUNCTION__, val, offset); 1763 1764 return val; 1765 } 1766 1767 1768 #ifdef BCE_DEBUG 1769 /****************************************************************************/ 1770 /* Context memory read. */ 1771 /* */ 1772 /* The NetXtreme II controller uses context memory to track connection */ 1773 /* information for L2 and higher network protocols. */ 1774 /* */ 1775 /* Returns: */ 1776 /* The requested 32 bit value of context memory. */ 1777 /****************************************************************************/ 1778 static u32 1779 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1780 { 1781 u32 idx, offset, retry_cnt = 5, val; 1782 1783 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1784 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1785 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1786 1787 offset = ctx_offset + cid_addr; 1788 1789 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1790 1791 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1792 1793 for (idx = 0; idx < retry_cnt; idx++) { 1794 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1795 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1796 break; 1797 DELAY(5); 1798 } 1799 1800 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1801 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1802 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1803 __FILE__, __LINE__, cid_addr, ctx_offset); 1804 1805 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1806 } else { 1807 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1808 val = REG_RD(sc, BCE_CTX_DATA); 1809 } 1810 1811 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1812 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1813 1814 return(val); 1815 } 1816 #endif 1817 1818 1819 /****************************************************************************/ 1820 /* Context memory write. */ 1821 /* */ 1822 /* The NetXtreme II controller uses context memory to track connection */ 1823 /* information for L2 and higher network protocols. */ 1824 /* */ 1825 /* Returns: */ 1826 /* Nothing. */ 1827 /****************************************************************************/ 1828 static void 1829 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1830 { 1831 u32 idx, offset = ctx_offset + cid_addr; 1832 u32 val, retry_cnt = 5; 1833 1834 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1835 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1836 1837 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1838 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1839 __FUNCTION__, cid_addr)); 1840 1841 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1842 1843 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1844 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1845 1846 for (idx = 0; idx < retry_cnt; idx++) { 1847 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1848 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1849 break; 1850 DELAY(5); 1851 } 1852 1853 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1854 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1855 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1856 __FILE__, __LINE__, cid_addr, ctx_offset); 1857 1858 } else { 1859 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1860 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1861 } 1862 } 1863 1864 1865 /****************************************************************************/ 1866 /* PHY register read. */ 1867 /* */ 1868 /* Implements register reads on the MII bus. */ 1869 /* */ 1870 /* Returns: */ 1871 /* The value of the register. */ 1872 /****************************************************************************/ 1873 static int 1874 bce_miibus_read_reg(device_t dev, int phy, int reg) 1875 { 1876 struct bce_softc *sc; 1877 u32 val; 1878 int i; 1879 1880 sc = device_get_softc(dev); 1881 1882 /* Make sure we are accessing the correct PHY address. */ 1883 if (phy != sc->bce_phy_addr) { 1884 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1885 "for PHY read!\n", phy); 1886 return(0); 1887 } 1888 1889 /* 1890 * The 5709S PHY is an IEEE Clause 45 PHY 1891 * with special mappings to work with IEEE 1892 * Clause 22 register accesses. 1893 */ 1894 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1895 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1896 reg += 0x10; 1897 } 1898 1899 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1900 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1901 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1902 1903 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1904 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1905 1906 DELAY(40); 1907 } 1908 1909 1910 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1911 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1912 BCE_EMAC_MDIO_COMM_START_BUSY; 1913 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1914 1915 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1916 DELAY(10); 1917 1918 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1919 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1920 DELAY(5); 1921 1922 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1923 val &= BCE_EMAC_MDIO_COMM_DATA; 1924 1925 break; 1926 } 1927 } 1928 1929 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1930 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1931 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1932 val = 0x0; 1933 } else { 1934 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1935 } 1936 1937 1938 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1939 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1940 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1941 1942 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1943 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1944 1945 DELAY(40); 1946 } 1947 1948 DB_PRINT_PHY_REG(reg, val); 1949 return (val & 0xffff); 1950 1951 } 1952 1953 1954 /****************************************************************************/ 1955 /* PHY register write. */ 1956 /* */ 1957 /* Implements register writes on the MII bus. */ 1958 /* */ 1959 /* Returns: */ 1960 /* The value of the register. */ 1961 /****************************************************************************/ 1962 static int 1963 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1964 { 1965 struct bce_softc *sc; 1966 u32 val1; 1967 int i; 1968 1969 sc = device_get_softc(dev); 1970 1971 /* Make sure we are accessing the correct PHY address. */ 1972 if (phy != sc->bce_phy_addr) { 1973 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1974 "for PHY write!\n", phy); 1975 return(0); 1976 } 1977 1978 DB_PRINT_PHY_REG(reg, val); 1979 1980 /* 1981 * The 5709S PHY is an IEEE Clause 45 PHY 1982 * with special mappings to work with IEEE 1983 * Clause 22 register accesses. 1984 */ 1985 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1986 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1987 reg += 0x10; 1988 } 1989 1990 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1991 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1992 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1993 1994 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1995 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1996 1997 DELAY(40); 1998 } 1999 2000 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 2001 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 2002 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 2003 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 2004 2005 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 2006 DELAY(10); 2007 2008 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 2009 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 2010 DELAY(5); 2011 break; 2012 } 2013 } 2014 2015 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 2016 BCE_PRINTF("%s(%d): PHY write timeout!\n", 2017 __FILE__, __LINE__); 2018 2019 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 2020 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 2021 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 2022 2023 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 2024 REG_RD(sc, BCE_EMAC_MDIO_MODE); 2025 2026 DELAY(40); 2027 } 2028 2029 return 0; 2030 } 2031 2032 2033 /****************************************************************************/ 2034 /* MII bus status change. */ 2035 /* */ 2036 /* Called by the MII bus driver when the PHY establishes link to set the */ 2037 /* MAC interface registers. */ 2038 /* */ 2039 /* Returns: */ 2040 /* Nothing. */ 2041 /****************************************************************************/ 2042 static void 2043 bce_miibus_statchg(device_t dev) 2044 { 2045 struct bce_softc *sc; 2046 struct mii_data *mii; 2047 struct ifmediareq ifmr; 2048 int media_active, media_status, val; 2049 2050 sc = device_get_softc(dev); 2051 2052 DBENTER(BCE_VERBOSE_PHY); 2053 2054 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2055 bzero(&ifmr, sizeof(ifmr)); 2056 bce_ifmedia_sts_rphy(sc, &ifmr); 2057 media_active = ifmr.ifm_active; 2058 media_status = ifmr.ifm_status; 2059 } else { 2060 mii = device_get_softc(sc->bce_miibus); 2061 media_active = mii->mii_media_active; 2062 media_status = mii->mii_media_status; 2063 } 2064 2065 val = REG_RD(sc, BCE_EMAC_MODE); 2066 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2067 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2068 BCE_EMAC_MODE_25G); 2069 2070 /* Set MII or GMII interface based on the PHY speed. */ 2071 switch (IFM_SUBTYPE(media_active)) { 2072 case IFM_10_T: 2073 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2074 DBPRINT(sc, BCE_INFO_PHY, 2075 "Enabling 10Mb interface.\n"); 2076 val |= BCE_EMAC_MODE_PORT_MII_10; 2077 break; 2078 } 2079 /* fall-through */ 2080 case IFM_100_TX: 2081 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2082 val |= BCE_EMAC_MODE_PORT_MII; 2083 break; 2084 case IFM_2500_SX: 2085 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2086 val |= BCE_EMAC_MODE_25G; 2087 /* fall-through */ 2088 case IFM_1000_T: 2089 case IFM_1000_SX: 2090 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2091 val |= BCE_EMAC_MODE_PORT_GMII; 2092 break; 2093 default: 2094 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2095 "default GMII interface.\n"); 2096 val |= BCE_EMAC_MODE_PORT_GMII; 2097 } 2098 2099 /* Set half or full duplex based on PHY settings. */ 2100 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2101 DBPRINT(sc, BCE_INFO_PHY, 2102 "Setting Half-Duplex interface.\n"); 2103 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2104 } else 2105 DBPRINT(sc, BCE_INFO_PHY, 2106 "Setting Full-Duplex interface.\n"); 2107 2108 REG_WR(sc, BCE_EMAC_MODE, val); 2109 2110 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2111 DBPRINT(sc, BCE_INFO_PHY, 2112 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2113 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2114 } else { 2115 DBPRINT(sc, BCE_INFO_PHY, 2116 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2117 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2118 } 2119 2120 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2121 DBPRINT(sc, BCE_INFO_PHY, 2122 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2123 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2124 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2125 } else { 2126 DBPRINT(sc, BCE_INFO_PHY, 2127 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2128 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2129 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2130 } 2131 2132 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2133 2134 DBEXIT(BCE_VERBOSE_PHY); 2135 } 2136 2137 2138 /****************************************************************************/ 2139 /* Acquire NVRAM lock. */ 2140 /* */ 2141 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2142 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2143 /* for use by the driver. */ 2144 /* */ 2145 /* Returns: */ 2146 /* 0 on success, positive value on failure. */ 2147 /****************************************************************************/ 2148 static int 2149 bce_acquire_nvram_lock(struct bce_softc *sc) 2150 { 2151 u32 val; 2152 int j, rc = 0; 2153 2154 DBENTER(BCE_VERBOSE_NVRAM); 2155 2156 /* Request access to the flash interface. */ 2157 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2158 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2159 val = REG_RD(sc, BCE_NVM_SW_ARB); 2160 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2161 break; 2162 2163 DELAY(5); 2164 } 2165 2166 if (j >= NVRAM_TIMEOUT_COUNT) { 2167 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2168 rc = EBUSY; 2169 } 2170 2171 DBEXIT(BCE_VERBOSE_NVRAM); 2172 return (rc); 2173 } 2174 2175 2176 /****************************************************************************/ 2177 /* Release NVRAM lock. */ 2178 /* */ 2179 /* When the caller is finished accessing NVRAM the lock must be released. */ 2180 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2181 /* for use by the driver. */ 2182 /* */ 2183 /* Returns: */ 2184 /* 0 on success, positive value on failure. */ 2185 /****************************************************************************/ 2186 static int 2187 bce_release_nvram_lock(struct bce_softc *sc) 2188 { 2189 u32 val; 2190 int j, rc = 0; 2191 2192 DBENTER(BCE_VERBOSE_NVRAM); 2193 2194 /* 2195 * Relinquish nvram interface. 2196 */ 2197 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2198 2199 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2200 val = REG_RD(sc, BCE_NVM_SW_ARB); 2201 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2202 break; 2203 2204 DELAY(5); 2205 } 2206 2207 if (j >= NVRAM_TIMEOUT_COUNT) { 2208 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2209 rc = EBUSY; 2210 } 2211 2212 DBEXIT(BCE_VERBOSE_NVRAM); 2213 return (rc); 2214 } 2215 2216 2217 #ifdef BCE_NVRAM_WRITE_SUPPORT 2218 /****************************************************************************/ 2219 /* Enable NVRAM write access. */ 2220 /* */ 2221 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2222 /* */ 2223 /* Returns: */ 2224 /* 0 on success, positive value on failure. */ 2225 /****************************************************************************/ 2226 static int 2227 bce_enable_nvram_write(struct bce_softc *sc) 2228 { 2229 u32 val; 2230 int rc = 0; 2231 2232 DBENTER(BCE_VERBOSE_NVRAM); 2233 2234 val = REG_RD(sc, BCE_MISC_CFG); 2235 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2236 2237 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2238 int j; 2239 2240 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2241 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2242 2243 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2244 DELAY(5); 2245 2246 val = REG_RD(sc, BCE_NVM_COMMAND); 2247 if (val & BCE_NVM_COMMAND_DONE) 2248 break; 2249 } 2250 2251 if (j >= NVRAM_TIMEOUT_COUNT) { 2252 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2253 rc = EBUSY; 2254 } 2255 } 2256 2257 DBENTER(BCE_VERBOSE_NVRAM); 2258 return (rc); 2259 } 2260 2261 2262 /****************************************************************************/ 2263 /* Disable NVRAM write access. */ 2264 /* */ 2265 /* When the caller is finished writing to NVRAM write access must be */ 2266 /* disabled. */ 2267 /* */ 2268 /* Returns: */ 2269 /* Nothing. */ 2270 /****************************************************************************/ 2271 static void 2272 bce_disable_nvram_write(struct bce_softc *sc) 2273 { 2274 u32 val; 2275 2276 DBENTER(BCE_VERBOSE_NVRAM); 2277 2278 val = REG_RD(sc, BCE_MISC_CFG); 2279 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2280 2281 DBEXIT(BCE_VERBOSE_NVRAM); 2282 2283 } 2284 #endif 2285 2286 2287 /****************************************************************************/ 2288 /* Enable NVRAM access. */ 2289 /* */ 2290 /* Before accessing NVRAM for read or write operations the caller must */ 2291 /* enabled NVRAM access. */ 2292 /* */ 2293 /* Returns: */ 2294 /* Nothing. */ 2295 /****************************************************************************/ 2296 static void 2297 bce_enable_nvram_access(struct bce_softc *sc) 2298 { 2299 u32 val; 2300 2301 DBENTER(BCE_VERBOSE_NVRAM); 2302 2303 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2304 /* Enable both bits, even on read. */ 2305 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2306 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2307 2308 DBEXIT(BCE_VERBOSE_NVRAM); 2309 } 2310 2311 2312 /****************************************************************************/ 2313 /* Disable NVRAM access. */ 2314 /* */ 2315 /* When the caller is finished accessing NVRAM access must be disabled. */ 2316 /* */ 2317 /* Returns: */ 2318 /* Nothing. */ 2319 /****************************************************************************/ 2320 static void 2321 bce_disable_nvram_access(struct bce_softc *sc) 2322 { 2323 u32 val; 2324 2325 DBENTER(BCE_VERBOSE_NVRAM); 2326 2327 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2328 2329 /* Disable both bits, even after read. */ 2330 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2331 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2332 2333 DBEXIT(BCE_VERBOSE_NVRAM); 2334 } 2335 2336 2337 #ifdef BCE_NVRAM_WRITE_SUPPORT 2338 /****************************************************************************/ 2339 /* Erase NVRAM page before writing. */ 2340 /* */ 2341 /* Non-buffered flash parts require that a page be erased before it is */ 2342 /* written. */ 2343 /* */ 2344 /* Returns: */ 2345 /* 0 on success, positive value on failure. */ 2346 /****************************************************************************/ 2347 static int 2348 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2349 { 2350 u32 cmd; 2351 int j, rc = 0; 2352 2353 DBENTER(BCE_VERBOSE_NVRAM); 2354 2355 /* Buffered flash doesn't require an erase. */ 2356 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2357 goto bce_nvram_erase_page_exit; 2358 2359 /* Build an erase command. */ 2360 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2361 BCE_NVM_COMMAND_DOIT; 2362 2363 /* 2364 * Clear the DONE bit separately, set the NVRAM adress to erase, 2365 * and issue the erase command. 2366 */ 2367 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2368 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2369 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2370 2371 /* Wait for completion. */ 2372 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2373 u32 val; 2374 2375 DELAY(5); 2376 2377 val = REG_RD(sc, BCE_NVM_COMMAND); 2378 if (val & BCE_NVM_COMMAND_DONE) 2379 break; 2380 } 2381 2382 if (j >= NVRAM_TIMEOUT_COUNT) { 2383 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2384 rc = EBUSY; 2385 } 2386 2387 bce_nvram_erase_page_exit: 2388 DBEXIT(BCE_VERBOSE_NVRAM); 2389 return (rc); 2390 } 2391 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2392 2393 2394 /****************************************************************************/ 2395 /* Read a dword (32 bits) from NVRAM. */ 2396 /* */ 2397 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2398 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2399 /* */ 2400 /* Returns: */ 2401 /* 0 on success and the 32 bit value read, positive value on failure. */ 2402 /****************************************************************************/ 2403 static int 2404 bce_nvram_read_dword(struct bce_softc *sc, 2405 u32 offset, u8 *ret_val, u32 cmd_flags) 2406 { 2407 u32 cmd; 2408 int i, rc = 0; 2409 2410 DBENTER(BCE_EXTREME_NVRAM); 2411 2412 /* Build the command word. */ 2413 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2414 2415 /* Calculate the offset for buffered flash if translation is used. */ 2416 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2417 offset = ((offset / sc->bce_flash_info->page_size) << 2418 sc->bce_flash_info->page_bits) + 2419 (offset % sc->bce_flash_info->page_size); 2420 } 2421 2422 /* 2423 * Clear the DONE bit separately, set the address to read, 2424 * and issue the read. 2425 */ 2426 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2427 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2428 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2429 2430 /* Wait for completion. */ 2431 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2432 u32 val; 2433 2434 DELAY(5); 2435 2436 val = REG_RD(sc, BCE_NVM_COMMAND); 2437 if (val & BCE_NVM_COMMAND_DONE) { 2438 val = REG_RD(sc, BCE_NVM_READ); 2439 2440 val = bce_be32toh(val); 2441 memcpy(ret_val, &val, 4); 2442 break; 2443 } 2444 } 2445 2446 /* Check for errors. */ 2447 if (i >= NVRAM_TIMEOUT_COUNT) { 2448 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2449 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2450 rc = EBUSY; 2451 } 2452 2453 DBEXIT(BCE_EXTREME_NVRAM); 2454 return(rc); 2455 } 2456 2457 2458 #ifdef BCE_NVRAM_WRITE_SUPPORT 2459 /****************************************************************************/ 2460 /* Write a dword (32 bits) to NVRAM. */ 2461 /* */ 2462 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2463 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2464 /* enabled NVRAM write access. */ 2465 /* */ 2466 /* Returns: */ 2467 /* 0 on success, positive value on failure. */ 2468 /****************************************************************************/ 2469 static int 2470 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2471 u32 cmd_flags) 2472 { 2473 u32 cmd, val32; 2474 int j, rc = 0; 2475 2476 DBENTER(BCE_VERBOSE_NVRAM); 2477 2478 /* Build the command word. */ 2479 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2480 2481 /* Calculate the offset for buffered flash if translation is used. */ 2482 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2483 offset = ((offset / sc->bce_flash_info->page_size) << 2484 sc->bce_flash_info->page_bits) + 2485 (offset % sc->bce_flash_info->page_size); 2486 } 2487 2488 /* 2489 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2490 * set the NVRAM address to write, and issue the write command 2491 */ 2492 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2493 memcpy(&val32, val, 4); 2494 val32 = htobe32(val32); 2495 REG_WR(sc, BCE_NVM_WRITE, val32); 2496 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2497 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2498 2499 /* Wait for completion. */ 2500 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2501 DELAY(5); 2502 2503 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2504 break; 2505 } 2506 if (j >= NVRAM_TIMEOUT_COUNT) { 2507 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2508 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2509 rc = EBUSY; 2510 } 2511 2512 DBEXIT(BCE_VERBOSE_NVRAM); 2513 return (rc); 2514 } 2515 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2516 2517 2518 /****************************************************************************/ 2519 /* Initialize NVRAM access. */ 2520 /* */ 2521 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2522 /* access that device. */ 2523 /* */ 2524 /* Returns: */ 2525 /* 0 on success, positive value on failure. */ 2526 /****************************************************************************/ 2527 static int 2528 bce_init_nvram(struct bce_softc *sc) 2529 { 2530 u32 val; 2531 int j, entry_count, rc = 0; 2532 struct flash_spec *flash; 2533 2534 DBENTER(BCE_VERBOSE_NVRAM); 2535 2536 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2537 sc->bce_flash_info = &flash_5709; 2538 goto bce_init_nvram_get_flash_size; 2539 } 2540 2541 /* Determine the selected interface. */ 2542 val = REG_RD(sc, BCE_NVM_CFG1); 2543 2544 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2545 2546 /* 2547 * Flash reconfiguration is required to support additional 2548 * NVRAM devices not directly supported in hardware. 2549 * Check if the flash interface was reconfigured 2550 * by the bootcode. 2551 */ 2552 2553 if (val & 0x40000000) { 2554 /* Flash interface reconfigured by bootcode. */ 2555 2556 DBPRINT(sc,BCE_INFO_LOAD, 2557 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2558 2559 for (j = 0, flash = &flash_table[0]; j < entry_count; 2560 j++, flash++) { 2561 if ((val & FLASH_BACKUP_STRAP_MASK) == 2562 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2563 sc->bce_flash_info = flash; 2564 break; 2565 } 2566 } 2567 } else { 2568 /* Flash interface not yet reconfigured. */ 2569 u32 mask; 2570 2571 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2572 __FUNCTION__); 2573 2574 if (val & (1 << 23)) 2575 mask = FLASH_BACKUP_STRAP_MASK; 2576 else 2577 mask = FLASH_STRAP_MASK; 2578 2579 /* Look for the matching NVRAM device configuration data. */ 2580 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2581 2582 /* Check if the device matches any of the known devices. */ 2583 if ((val & mask) == (flash->strapping & mask)) { 2584 /* Found a device match. */ 2585 sc->bce_flash_info = flash; 2586 2587 /* Request access to the flash interface. */ 2588 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2589 return rc; 2590 2591 /* Reconfigure the flash interface. */ 2592 bce_enable_nvram_access(sc); 2593 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2594 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2595 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2596 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2597 bce_disable_nvram_access(sc); 2598 bce_release_nvram_lock(sc); 2599 2600 break; 2601 } 2602 } 2603 } 2604 2605 /* Check if a matching device was found. */ 2606 if (j == entry_count) { 2607 sc->bce_flash_info = NULL; 2608 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2609 __FILE__, __LINE__); 2610 DBEXIT(BCE_VERBOSE_NVRAM); 2611 return (ENODEV); 2612 } 2613 2614 bce_init_nvram_get_flash_size: 2615 /* Write the flash config data to the shared memory interface. */ 2616 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2617 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2618 if (val) 2619 sc->bce_flash_size = val; 2620 else 2621 sc->bce_flash_size = sc->bce_flash_info->total_size; 2622 2623 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2624 __FUNCTION__, sc->bce_flash_info->name, 2625 sc->bce_flash_info->total_size); 2626 2627 DBEXIT(BCE_VERBOSE_NVRAM); 2628 return rc; 2629 } 2630 2631 2632 /****************************************************************************/ 2633 /* Read an arbitrary range of data from NVRAM. */ 2634 /* */ 2635 /* Prepares the NVRAM interface for access and reads the requested data */ 2636 /* into the supplied buffer. */ 2637 /* */ 2638 /* Returns: */ 2639 /* 0 on success and the data read, positive value on failure. */ 2640 /****************************************************************************/ 2641 static int 2642 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2643 int buf_size) 2644 { 2645 int rc = 0; 2646 u32 cmd_flags, offset32, len32, extra; 2647 2648 DBENTER(BCE_VERBOSE_NVRAM); 2649 2650 if (buf_size == 0) 2651 goto bce_nvram_read_exit; 2652 2653 /* Request access to the flash interface. */ 2654 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2655 goto bce_nvram_read_exit; 2656 2657 /* Enable access to flash interface */ 2658 bce_enable_nvram_access(sc); 2659 2660 len32 = buf_size; 2661 offset32 = offset; 2662 extra = 0; 2663 2664 cmd_flags = 0; 2665 2666 if (offset32 & 3) { 2667 u8 buf[4]; 2668 u32 pre_len; 2669 2670 offset32 &= ~3; 2671 pre_len = 4 - (offset & 3); 2672 2673 if (pre_len >= len32) { 2674 pre_len = len32; 2675 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2676 } 2677 else { 2678 cmd_flags = BCE_NVM_COMMAND_FIRST; 2679 } 2680 2681 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2682 2683 if (rc) 2684 return rc; 2685 2686 memcpy(ret_buf, buf + (offset & 3), pre_len); 2687 2688 offset32 += 4; 2689 ret_buf += pre_len; 2690 len32 -= pre_len; 2691 } 2692 2693 if (len32 & 3) { 2694 extra = 4 - (len32 & 3); 2695 len32 = (len32 + 4) & ~3; 2696 } 2697 2698 if (len32 == 4) { 2699 u8 buf[4]; 2700 2701 if (cmd_flags) 2702 cmd_flags = BCE_NVM_COMMAND_LAST; 2703 else 2704 cmd_flags = BCE_NVM_COMMAND_FIRST | 2705 BCE_NVM_COMMAND_LAST; 2706 2707 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2708 2709 memcpy(ret_buf, buf, 4 - extra); 2710 } 2711 else if (len32 > 0) { 2712 u8 buf[4]; 2713 2714 /* Read the first word. */ 2715 if (cmd_flags) 2716 cmd_flags = 0; 2717 else 2718 cmd_flags = BCE_NVM_COMMAND_FIRST; 2719 2720 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2721 2722 /* Advance to the next dword. */ 2723 offset32 += 4; 2724 ret_buf += 4; 2725 len32 -= 4; 2726 2727 while (len32 > 4 && rc == 0) { 2728 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2729 2730 /* Advance to the next dword. */ 2731 offset32 += 4; 2732 ret_buf += 4; 2733 len32 -= 4; 2734 } 2735 2736 if (rc) 2737 goto bce_nvram_read_locked_exit; 2738 2739 cmd_flags = BCE_NVM_COMMAND_LAST; 2740 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2741 2742 memcpy(ret_buf, buf, 4 - extra); 2743 } 2744 2745 bce_nvram_read_locked_exit: 2746 /* Disable access to flash interface and release the lock. */ 2747 bce_disable_nvram_access(sc); 2748 bce_release_nvram_lock(sc); 2749 2750 bce_nvram_read_exit: 2751 DBEXIT(BCE_VERBOSE_NVRAM); 2752 return rc; 2753 } 2754 2755 2756 #ifdef BCE_NVRAM_WRITE_SUPPORT 2757 /****************************************************************************/ 2758 /* Write an arbitrary range of data from NVRAM. */ 2759 /* */ 2760 /* Prepares the NVRAM interface for write access and writes the requested */ 2761 /* data from the supplied buffer. The caller is responsible for */ 2762 /* calculating any appropriate CRCs. */ 2763 /* */ 2764 /* Returns: */ 2765 /* 0 on success, positive value on failure. */ 2766 /****************************************************************************/ 2767 static int 2768 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2769 int buf_size) 2770 { 2771 u32 written, offset32, len32; 2772 u8 *buf, start[4], end[4]; 2773 int rc = 0; 2774 int align_start, align_end; 2775 2776 DBENTER(BCE_VERBOSE_NVRAM); 2777 2778 buf = data_buf; 2779 offset32 = offset; 2780 len32 = buf_size; 2781 align_start = align_end = 0; 2782 2783 if ((align_start = (offset32 & 3))) { 2784 offset32 &= ~3; 2785 len32 += align_start; 2786 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2787 goto bce_nvram_write_exit; 2788 } 2789 2790 if (len32 & 3) { 2791 if ((len32 > 4) || !align_start) { 2792 align_end = 4 - (len32 & 3); 2793 len32 += align_end; 2794 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2795 end, 4))) { 2796 goto bce_nvram_write_exit; 2797 } 2798 } 2799 } 2800 2801 if (align_start || align_end) { 2802 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2803 if (buf == 0) { 2804 rc = ENOMEM; 2805 goto bce_nvram_write_exit; 2806 } 2807 2808 if (align_start) { 2809 memcpy(buf, start, 4); 2810 } 2811 2812 if (align_end) { 2813 memcpy(buf + len32 - 4, end, 4); 2814 } 2815 memcpy(buf + align_start, data_buf, buf_size); 2816 } 2817 2818 written = 0; 2819 while ((written < len32) && (rc == 0)) { 2820 u32 page_start, page_end, data_start, data_end; 2821 u32 addr, cmd_flags; 2822 int i; 2823 u8 flash_buffer[264]; 2824 2825 /* Find the page_start addr */ 2826 page_start = offset32 + written; 2827 page_start -= (page_start % sc->bce_flash_info->page_size); 2828 /* Find the page_end addr */ 2829 page_end = page_start + sc->bce_flash_info->page_size; 2830 /* Find the data_start addr */ 2831 data_start = (written == 0) ? offset32 : page_start; 2832 /* Find the data_end addr */ 2833 data_end = (page_end > offset32 + len32) ? 2834 (offset32 + len32) : page_end; 2835 2836 /* Request access to the flash interface. */ 2837 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2838 goto bce_nvram_write_exit; 2839 2840 /* Enable access to flash interface */ 2841 bce_enable_nvram_access(sc); 2842 2843 cmd_flags = BCE_NVM_COMMAND_FIRST; 2844 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2845 int j; 2846 2847 /* Read the whole page into the buffer 2848 * (non-buffer flash only) */ 2849 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2850 if (j == (sc->bce_flash_info->page_size - 4)) { 2851 cmd_flags |= BCE_NVM_COMMAND_LAST; 2852 } 2853 rc = bce_nvram_read_dword(sc, 2854 page_start + j, 2855 &flash_buffer[j], 2856 cmd_flags); 2857 2858 if (rc) 2859 goto bce_nvram_write_locked_exit; 2860 2861 cmd_flags = 0; 2862 } 2863 } 2864 2865 /* Enable writes to flash interface (unlock write-protect) */ 2866 if ((rc = bce_enable_nvram_write(sc)) != 0) 2867 goto bce_nvram_write_locked_exit; 2868 2869 /* Erase the page */ 2870 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2871 goto bce_nvram_write_locked_exit; 2872 2873 /* Re-enable the write again for the actual write */ 2874 bce_enable_nvram_write(sc); 2875 2876 /* Loop to write back the buffer data from page_start to 2877 * data_start */ 2878 i = 0; 2879 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2880 for (addr = page_start; addr < data_start; 2881 addr += 4, i += 4) { 2882 2883 rc = bce_nvram_write_dword(sc, addr, 2884 &flash_buffer[i], cmd_flags); 2885 2886 if (rc != 0) 2887 goto bce_nvram_write_locked_exit; 2888 2889 cmd_flags = 0; 2890 } 2891 } 2892 2893 /* Loop to write the new data from data_start to data_end */ 2894 for (addr = data_start; addr < data_end; addr += 4, i++) { 2895 if ((addr == page_end - 4) || 2896 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2897 (addr == data_end - 4))) { 2898 2899 cmd_flags |= BCE_NVM_COMMAND_LAST; 2900 } 2901 rc = bce_nvram_write_dword(sc, addr, buf, 2902 cmd_flags); 2903 2904 if (rc != 0) 2905 goto bce_nvram_write_locked_exit; 2906 2907 cmd_flags = 0; 2908 buf += 4; 2909 } 2910 2911 /* Loop to write back the buffer data from data_end 2912 * to page_end */ 2913 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2914 for (addr = data_end; addr < page_end; 2915 addr += 4, i += 4) { 2916 2917 if (addr == page_end-4) { 2918 cmd_flags = BCE_NVM_COMMAND_LAST; 2919 } 2920 rc = bce_nvram_write_dword(sc, addr, 2921 &flash_buffer[i], cmd_flags); 2922 2923 if (rc != 0) 2924 goto bce_nvram_write_locked_exit; 2925 2926 cmd_flags = 0; 2927 } 2928 } 2929 2930 /* Disable writes to flash interface (lock write-protect) */ 2931 bce_disable_nvram_write(sc); 2932 2933 /* Disable access to flash interface */ 2934 bce_disable_nvram_access(sc); 2935 bce_release_nvram_lock(sc); 2936 2937 /* Increment written */ 2938 written += data_end - data_start; 2939 } 2940 2941 goto bce_nvram_write_exit; 2942 2943 bce_nvram_write_locked_exit: 2944 bce_disable_nvram_write(sc); 2945 bce_disable_nvram_access(sc); 2946 bce_release_nvram_lock(sc); 2947 2948 bce_nvram_write_exit: 2949 if (align_start || align_end) 2950 free(buf, M_DEVBUF); 2951 2952 DBEXIT(BCE_VERBOSE_NVRAM); 2953 return (rc); 2954 } 2955 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2956 2957 2958 /****************************************************************************/ 2959 /* Verifies that NVRAM is accessible and contains valid data. */ 2960 /* */ 2961 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2962 /* correct. */ 2963 /* */ 2964 /* Returns: */ 2965 /* 0 on success, positive value on failure. */ 2966 /****************************************************************************/ 2967 static int 2968 bce_nvram_test(struct bce_softc *sc) 2969 { 2970 u32 buf[BCE_NVRAM_SIZE / 4]; 2971 u8 *data = (u8 *) buf; 2972 int rc = 0; 2973 u32 magic, csum; 2974 2975 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2976 2977 /* 2978 * Check that the device NVRAM is valid by reading 2979 * the magic value at offset 0. 2980 */ 2981 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2982 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2983 __FILE__, __LINE__); 2984 goto bce_nvram_test_exit; 2985 } 2986 2987 /* 2988 * Verify that offset 0 of the NVRAM contains 2989 * a valid magic number. 2990 */ 2991 magic = bce_be32toh(buf[0]); 2992 if (magic != BCE_NVRAM_MAGIC) { 2993 rc = ENODEV; 2994 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2995 "Expected: 0x%08X, Found: 0x%08X\n", 2996 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2997 goto bce_nvram_test_exit; 2998 } 2999 3000 /* 3001 * Verify that the device NVRAM includes valid 3002 * configuration data. 3003 */ 3004 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 3005 BCE_PRINTF("%s(%d): Unable to read manufacturing " 3006 "Information from NVRAM!\n", __FILE__, __LINE__); 3007 goto bce_nvram_test_exit; 3008 } 3009 3010 csum = ether_crc32_le(data, 0x100); 3011 if (csum != BCE_CRC32_RESIDUAL) { 3012 rc = ENODEV; 3013 BCE_PRINTF("%s(%d): Invalid manufacturing information " 3014 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 3015 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 3016 goto bce_nvram_test_exit; 3017 } 3018 3019 csum = ether_crc32_le(data + 0x100, 0x100); 3020 if (csum != BCE_CRC32_RESIDUAL) { 3021 rc = ENODEV; 3022 BCE_PRINTF("%s(%d): Invalid feature configuration " 3023 "information NVRAM CRC! Expected: 0x%08X, " 3024 "Found: 08%08X\n", __FILE__, __LINE__, 3025 BCE_CRC32_RESIDUAL, csum); 3026 } 3027 3028 bce_nvram_test_exit: 3029 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 3030 return rc; 3031 } 3032 3033 3034 /****************************************************************************/ 3035 /* Calculates the size of the buffers to allocate based on the MTU. */ 3036 /* */ 3037 /* Returns: */ 3038 /* Nothing. */ 3039 /****************************************************************************/ 3040 static void 3041 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 3042 { 3043 DBENTER(BCE_VERBOSE_LOAD); 3044 3045 /* Use a single allocation type when header splitting enabled. */ 3046 if (bce_hdr_split == TRUE) { 3047 sc->rx_bd_mbuf_alloc_size = MHLEN; 3048 /* Make sure offset is 16 byte aligned for hardware. */ 3049 sc->rx_bd_mbuf_align_pad = 3050 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 3051 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 3052 sc->rx_bd_mbuf_align_pad; 3053 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 3054 } else { 3055 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 3056 ETHER_CRC_LEN) > MCLBYTES) { 3057 /* Setup for jumbo RX buffer allocations. */ 3058 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 3059 sc->rx_bd_mbuf_align_pad = 3060 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3061 sc->rx_bd_mbuf_data_len = 3062 sc->rx_bd_mbuf_alloc_size - 3063 sc->rx_bd_mbuf_align_pad; 3064 } else { 3065 /* Setup for standard RX buffer allocations. */ 3066 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3067 sc->rx_bd_mbuf_align_pad = 3068 roundup2(MCLBYTES, 16) - MCLBYTES; 3069 sc->rx_bd_mbuf_data_len = 3070 sc->rx_bd_mbuf_alloc_size - 3071 sc->rx_bd_mbuf_align_pad; 3072 } 3073 } 3074 3075 // DBPRINT(sc, BCE_INFO_LOAD, 3076 DBPRINT(sc, BCE_WARN, 3077 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3078 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3079 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3080 sc->rx_bd_mbuf_align_pad); 3081 3082 DBEXIT(BCE_VERBOSE_LOAD); 3083 3084 } 3085 3086 /****************************************************************************/ 3087 /* Identifies the current media type of the controller and sets the PHY */ 3088 /* address. */ 3089 /* */ 3090 /* Returns: */ 3091 /* Nothing. */ 3092 /****************************************************************************/ 3093 static void 3094 bce_get_media(struct bce_softc *sc) 3095 { 3096 u32 val; 3097 3098 DBENTER(BCE_VERBOSE_PHY); 3099 3100 /* Assume PHY address for copper controllers. */ 3101 sc->bce_phy_addr = 1; 3102 3103 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3104 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3105 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3106 u32 strap; 3107 3108 /* 3109 * The BCM5709S is software configurable 3110 * for Copper or SerDes operation. 3111 */ 3112 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3113 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3114 "for copper.\n"); 3115 goto bce_get_media_exit; 3116 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3117 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3118 "for dual media.\n"); 3119 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3120 goto bce_get_media_exit; 3121 } 3122 3123 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3124 strap = (val & 3125 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3126 else 3127 strap = (val & 3128 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3129 3130 if (pci_get_function(sc->bce_dev) == 0) { 3131 switch (strap) { 3132 case 0x4: 3133 case 0x5: 3134 case 0x6: 3135 DBPRINT(sc, BCE_INFO_LOAD, 3136 "BCM5709 s/w configured for SerDes.\n"); 3137 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3138 break; 3139 default: 3140 DBPRINT(sc, BCE_INFO_LOAD, 3141 "BCM5709 s/w configured for Copper.\n"); 3142 break; 3143 } 3144 } else { 3145 switch (strap) { 3146 case 0x1: 3147 case 0x2: 3148 case 0x4: 3149 DBPRINT(sc, BCE_INFO_LOAD, 3150 "BCM5709 s/w configured for SerDes.\n"); 3151 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3152 break; 3153 default: 3154 DBPRINT(sc, BCE_INFO_LOAD, 3155 "BCM5709 s/w configured for Copper.\n"); 3156 break; 3157 } 3158 } 3159 3160 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3161 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3162 3163 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3164 3165 sc->bce_flags |= BCE_NO_WOL_FLAG; 3166 3167 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3168 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3169 3170 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3171 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3172 sc->bce_phy_addr = 2; 3173 3174 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3175 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3176 sc->bce_phy_flags |= 3177 BCE_PHY_2_5G_CAPABLE_FLAG; 3178 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3179 "capable adapter\n"); 3180 } 3181 } 3182 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3183 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3184 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3185 3186 bce_get_media_exit: 3187 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3188 "Using PHY address %d.\n", sc->bce_phy_addr); 3189 3190 DBEXIT(BCE_VERBOSE_PHY); 3191 } 3192 3193 3194 /****************************************************************************/ 3195 /* Performs PHY initialization required before MII drivers access the */ 3196 /* device. */ 3197 /* */ 3198 /* Returns: */ 3199 /* Nothing. */ 3200 /****************************************************************************/ 3201 static void 3202 bce_init_media(struct bce_softc *sc) 3203 { 3204 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3205 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3206 /* 3207 * Configure 5709S/5716S PHYs to use traditional IEEE 3208 * Clause 22 method. Otherwise we have no way to attach 3209 * the PHY in mii(4) layer. PHY specific configuration 3210 * is done in mii layer. 3211 */ 3212 3213 /* Select auto-negotiation MMD of the PHY. */ 3214 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3215 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3216 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3217 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3218 3219 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3220 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3221 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3222 } 3223 } 3224 3225 3226 /****************************************************************************/ 3227 /* Free any DMA memory owned by the driver. */ 3228 /* */ 3229 /* Scans through each data structre that requires DMA memory and frees */ 3230 /* the memory if allocated. */ 3231 /* */ 3232 /* Returns: */ 3233 /* Nothing. */ 3234 /****************************************************************************/ 3235 static void 3236 bce_dma_free(struct bce_softc *sc) 3237 { 3238 int i; 3239 3240 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3241 3242 /* Free, unmap, and destroy the status block. */ 3243 if (sc->status_block != NULL) { 3244 bus_dmamem_free( 3245 sc->status_tag, 3246 sc->status_block, 3247 sc->status_map); 3248 sc->status_block = NULL; 3249 } 3250 3251 if (sc->status_map != NULL) { 3252 bus_dmamap_unload( 3253 sc->status_tag, 3254 sc->status_map); 3255 bus_dmamap_destroy(sc->status_tag, 3256 sc->status_map); 3257 sc->status_map = NULL; 3258 } 3259 3260 if (sc->status_tag != NULL) { 3261 bus_dma_tag_destroy(sc->status_tag); 3262 sc->status_tag = NULL; 3263 } 3264 3265 3266 /* Free, unmap, and destroy the statistics block. */ 3267 if (sc->stats_block != NULL) { 3268 bus_dmamem_free( 3269 sc->stats_tag, 3270 sc->stats_block, 3271 sc->stats_map); 3272 sc->stats_block = NULL; 3273 } 3274 3275 if (sc->stats_map != NULL) { 3276 bus_dmamap_unload( 3277 sc->stats_tag, 3278 sc->stats_map); 3279 bus_dmamap_destroy(sc->stats_tag, 3280 sc->stats_map); 3281 sc->stats_map = NULL; 3282 } 3283 3284 if (sc->stats_tag != NULL) { 3285 bus_dma_tag_destroy(sc->stats_tag); 3286 sc->stats_tag = NULL; 3287 } 3288 3289 3290 /* Free, unmap and destroy all context memory pages. */ 3291 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3292 for (i = 0; i < sc->ctx_pages; i++ ) { 3293 if (sc->ctx_block[i] != NULL) { 3294 bus_dmamem_free( 3295 sc->ctx_tag, 3296 sc->ctx_block[i], 3297 sc->ctx_map[i]); 3298 sc->ctx_block[i] = NULL; 3299 } 3300 3301 if (sc->ctx_map[i] != NULL) { 3302 bus_dmamap_unload( 3303 sc->ctx_tag, 3304 sc->ctx_map[i]); 3305 bus_dmamap_destroy( 3306 sc->ctx_tag, 3307 sc->ctx_map[i]); 3308 sc->ctx_map[i] = NULL; 3309 } 3310 } 3311 3312 /* Destroy the context memory tag. */ 3313 if (sc->ctx_tag != NULL) { 3314 bus_dma_tag_destroy(sc->ctx_tag); 3315 sc->ctx_tag = NULL; 3316 } 3317 } 3318 3319 3320 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3321 for (i = 0; i < sc->tx_pages; i++ ) { 3322 if (sc->tx_bd_chain[i] != NULL) { 3323 bus_dmamem_free( 3324 sc->tx_bd_chain_tag, 3325 sc->tx_bd_chain[i], 3326 sc->tx_bd_chain_map[i]); 3327 sc->tx_bd_chain[i] = NULL; 3328 } 3329 3330 if (sc->tx_bd_chain_map[i] != NULL) { 3331 bus_dmamap_unload( 3332 sc->tx_bd_chain_tag, 3333 sc->tx_bd_chain_map[i]); 3334 bus_dmamap_destroy( 3335 sc->tx_bd_chain_tag, 3336 sc->tx_bd_chain_map[i]); 3337 sc->tx_bd_chain_map[i] = NULL; 3338 } 3339 } 3340 3341 /* Destroy the TX buffer descriptor tag. */ 3342 if (sc->tx_bd_chain_tag != NULL) { 3343 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3344 sc->tx_bd_chain_tag = NULL; 3345 } 3346 3347 3348 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3349 for (i = 0; i < sc->rx_pages; i++ ) { 3350 if (sc->rx_bd_chain[i] != NULL) { 3351 bus_dmamem_free( 3352 sc->rx_bd_chain_tag, 3353 sc->rx_bd_chain[i], 3354 sc->rx_bd_chain_map[i]); 3355 sc->rx_bd_chain[i] = NULL; 3356 } 3357 3358 if (sc->rx_bd_chain_map[i] != NULL) { 3359 bus_dmamap_unload( 3360 sc->rx_bd_chain_tag, 3361 sc->rx_bd_chain_map[i]); 3362 bus_dmamap_destroy( 3363 sc->rx_bd_chain_tag, 3364 sc->rx_bd_chain_map[i]); 3365 sc->rx_bd_chain_map[i] = NULL; 3366 } 3367 } 3368 3369 /* Destroy the RX buffer descriptor tag. */ 3370 if (sc->rx_bd_chain_tag != NULL) { 3371 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3372 sc->rx_bd_chain_tag = NULL; 3373 } 3374 3375 3376 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3377 if (bce_hdr_split == TRUE) { 3378 for (i = 0; i < sc->pg_pages; i++ ) { 3379 if (sc->pg_bd_chain[i] != NULL) { 3380 bus_dmamem_free( 3381 sc->pg_bd_chain_tag, 3382 sc->pg_bd_chain[i], 3383 sc->pg_bd_chain_map[i]); 3384 sc->pg_bd_chain[i] = NULL; 3385 } 3386 3387 if (sc->pg_bd_chain_map[i] != NULL) { 3388 bus_dmamap_unload( 3389 sc->pg_bd_chain_tag, 3390 sc->pg_bd_chain_map[i]); 3391 bus_dmamap_destroy( 3392 sc->pg_bd_chain_tag, 3393 sc->pg_bd_chain_map[i]); 3394 sc->pg_bd_chain_map[i] = NULL; 3395 } 3396 } 3397 3398 /* Destroy the page buffer descriptor tag. */ 3399 if (sc->pg_bd_chain_tag != NULL) { 3400 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3401 sc->pg_bd_chain_tag = NULL; 3402 } 3403 } 3404 3405 3406 /* Unload and destroy the TX mbuf maps. */ 3407 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3408 if (sc->tx_mbuf_map[i] != NULL) { 3409 bus_dmamap_unload(sc->tx_mbuf_tag, 3410 sc->tx_mbuf_map[i]); 3411 bus_dmamap_destroy(sc->tx_mbuf_tag, 3412 sc->tx_mbuf_map[i]); 3413 sc->tx_mbuf_map[i] = NULL; 3414 } 3415 } 3416 3417 /* Destroy the TX mbuf tag. */ 3418 if (sc->tx_mbuf_tag != NULL) { 3419 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3420 sc->tx_mbuf_tag = NULL; 3421 } 3422 3423 /* Unload and destroy the RX mbuf maps. */ 3424 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3425 if (sc->rx_mbuf_map[i] != NULL) { 3426 bus_dmamap_unload(sc->rx_mbuf_tag, 3427 sc->rx_mbuf_map[i]); 3428 bus_dmamap_destroy(sc->rx_mbuf_tag, 3429 sc->rx_mbuf_map[i]); 3430 sc->rx_mbuf_map[i] = NULL; 3431 } 3432 } 3433 3434 /* Destroy the RX mbuf tag. */ 3435 if (sc->rx_mbuf_tag != NULL) { 3436 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3437 sc->rx_mbuf_tag = NULL; 3438 } 3439 3440 /* Unload and destroy the page mbuf maps. */ 3441 if (bce_hdr_split == TRUE) { 3442 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3443 if (sc->pg_mbuf_map[i] != NULL) { 3444 bus_dmamap_unload(sc->pg_mbuf_tag, 3445 sc->pg_mbuf_map[i]); 3446 bus_dmamap_destroy(sc->pg_mbuf_tag, 3447 sc->pg_mbuf_map[i]); 3448 sc->pg_mbuf_map[i] = NULL; 3449 } 3450 } 3451 3452 /* Destroy the page mbuf tag. */ 3453 if (sc->pg_mbuf_tag != NULL) { 3454 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3455 sc->pg_mbuf_tag = NULL; 3456 } 3457 } 3458 3459 /* Destroy the parent tag */ 3460 if (sc->parent_tag != NULL) { 3461 bus_dma_tag_destroy(sc->parent_tag); 3462 sc->parent_tag = NULL; 3463 } 3464 3465 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3466 } 3467 3468 3469 /****************************************************************************/ 3470 /* Get DMA memory from the OS. */ 3471 /* */ 3472 /* Validates that the OS has provided DMA buffers in response to a */ 3473 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3474 /* When the callback is used the OS will return 0 for the mapping function */ 3475 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3476 /* failures back to the caller. */ 3477 /* */ 3478 /* Returns: */ 3479 /* Nothing. */ 3480 /****************************************************************************/ 3481 static void 3482 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3483 { 3484 bus_addr_t *busaddr = arg; 3485 3486 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3487 __FUNCTION__, nseg)); 3488 /* Simulate a mapping failure. */ 3489 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3490 error = ENOMEM); 3491 3492 /* ToDo: How to increment debug sim_count variable here? */ 3493 3494 /* Check for an error and signal the caller that an error occurred. */ 3495 if (error) { 3496 *busaddr = 0; 3497 } else { 3498 *busaddr = segs->ds_addr; 3499 } 3500 3501 return; 3502 } 3503 3504 3505 /****************************************************************************/ 3506 /* Allocate any DMA memory needed by the driver. */ 3507 /* */ 3508 /* Allocates DMA memory needed for the various global structures needed by */ 3509 /* hardware. */ 3510 /* */ 3511 /* Memory alignment requirements: */ 3512 /* +-----------------+----------+----------+----------+----------+ */ 3513 /* | | 5706 | 5708 | 5709 | 5716 | */ 3514 /* +-----------------+----------+----------+----------+----------+ */ 3515 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3516 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3517 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3518 /* |PG Buffers | none | none | none | none | */ 3519 /* |TX Buffers | none | none | none | none | */ 3520 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3521 /* |Context Memory | | | | | */ 3522 /* +-----------------+----------+----------+----------+----------+ */ 3523 /* */ 3524 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3525 /* */ 3526 /* Returns: */ 3527 /* 0 for success, positive value for failure. */ 3528 /****************************************************************************/ 3529 static int 3530 bce_dma_alloc(device_t dev) 3531 { 3532 struct bce_softc *sc; 3533 int i, error, rc = 0; 3534 bus_size_t max_size, max_seg_size; 3535 int max_segments; 3536 3537 sc = device_get_softc(dev); 3538 3539 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3540 3541 /* 3542 * Allocate the parent bus DMA tag appropriate for PCI. 3543 */ 3544 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3545 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3546 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3547 &sc->parent_tag)) { 3548 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3549 __FILE__, __LINE__); 3550 rc = ENOMEM; 3551 goto bce_dma_alloc_exit; 3552 } 3553 3554 /* 3555 * Create a DMA tag for the status block, allocate and clear the 3556 * memory, map the memory into DMA space, and fetch the physical 3557 * address of the block. 3558 */ 3559 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3560 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3561 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3562 0, NULL, NULL, &sc->status_tag)) { 3563 BCE_PRINTF("%s(%d): Could not allocate status block " 3564 "DMA tag!\n", __FILE__, __LINE__); 3565 rc = ENOMEM; 3566 goto bce_dma_alloc_exit; 3567 } 3568 3569 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3570 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3571 &sc->status_map)) { 3572 BCE_PRINTF("%s(%d): Could not allocate status block " 3573 "DMA memory!\n", __FILE__, __LINE__); 3574 rc = ENOMEM; 3575 goto bce_dma_alloc_exit; 3576 } 3577 3578 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3579 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3580 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3581 3582 if (error) { 3583 BCE_PRINTF("%s(%d): Could not map status block " 3584 "DMA memory!\n", __FILE__, __LINE__); 3585 rc = ENOMEM; 3586 goto bce_dma_alloc_exit; 3587 } 3588 3589 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3590 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3591 3592 /* 3593 * Create a DMA tag for the statistics block, allocate and clear the 3594 * memory, map the memory into DMA space, and fetch the physical 3595 * address of the block. 3596 */ 3597 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3598 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3599 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3600 0, NULL, NULL, &sc->stats_tag)) { 3601 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3602 "DMA tag!\n", __FILE__, __LINE__); 3603 rc = ENOMEM; 3604 goto bce_dma_alloc_exit; 3605 } 3606 3607 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3608 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3609 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3610 "DMA memory!\n", __FILE__, __LINE__); 3611 rc = ENOMEM; 3612 goto bce_dma_alloc_exit; 3613 } 3614 3615 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3616 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3617 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3618 3619 if(error) { 3620 BCE_PRINTF("%s(%d): Could not map statistics block " 3621 "DMA memory!\n", __FILE__, __LINE__); 3622 rc = ENOMEM; 3623 goto bce_dma_alloc_exit; 3624 } 3625 3626 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3627 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3628 3629 /* BCM5709 uses host memory as cache for context memory. */ 3630 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3631 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3632 if (sc->ctx_pages == 0) 3633 sc->ctx_pages = 1; 3634 3635 DBRUNIF((sc->ctx_pages > 512), 3636 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3637 __FILE__, __LINE__, sc->ctx_pages)); 3638 3639 /* 3640 * Create a DMA tag for the context pages, 3641 * allocate and clear the memory, map the 3642 * memory into DMA space, and fetch the 3643 * physical address of the block. 3644 */ 3645 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3646 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3647 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3648 0, NULL, NULL, &sc->ctx_tag)) { 3649 BCE_PRINTF("%s(%d): Could not allocate CTX " 3650 "DMA tag!\n", __FILE__, __LINE__); 3651 rc = ENOMEM; 3652 goto bce_dma_alloc_exit; 3653 } 3654 3655 for (i = 0; i < sc->ctx_pages; i++) { 3656 3657 if(bus_dmamem_alloc(sc->ctx_tag, 3658 (void **)&sc->ctx_block[i], 3659 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3660 &sc->ctx_map[i])) { 3661 BCE_PRINTF("%s(%d): Could not allocate CTX " 3662 "DMA memory!\n", __FILE__, __LINE__); 3663 rc = ENOMEM; 3664 goto bce_dma_alloc_exit; 3665 } 3666 3667 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3668 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3669 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3670 3671 if (error) { 3672 BCE_PRINTF("%s(%d): Could not map CTX " 3673 "DMA memory!\n", __FILE__, __LINE__); 3674 rc = ENOMEM; 3675 goto bce_dma_alloc_exit; 3676 } 3677 3678 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3679 "= 0x%jX\n", __FUNCTION__, i, 3680 (uintmax_t) sc->ctx_paddr[i]); 3681 } 3682 } 3683 3684 /* 3685 * Create a DMA tag for the TX buffer descriptor chain, 3686 * allocate and clear the memory, and fetch the 3687 * physical address of the block. 3688 */ 3689 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3690 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3691 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3692 NULL, NULL, &sc->tx_bd_chain_tag)) { 3693 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3694 "chain DMA tag!\n", __FILE__, __LINE__); 3695 rc = ENOMEM; 3696 goto bce_dma_alloc_exit; 3697 } 3698 3699 for (i = 0; i < sc->tx_pages; i++) { 3700 3701 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3702 (void **)&sc->tx_bd_chain[i], 3703 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3704 &sc->tx_bd_chain_map[i])) { 3705 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3706 "chain DMA memory!\n", __FILE__, __LINE__); 3707 rc = ENOMEM; 3708 goto bce_dma_alloc_exit; 3709 } 3710 3711 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3712 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3713 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3714 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3715 3716 if (error) { 3717 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3718 "chain DMA memory!\n", __FILE__, __LINE__); 3719 rc = ENOMEM; 3720 goto bce_dma_alloc_exit; 3721 } 3722 3723 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3724 "0x%jX\n", __FUNCTION__, i, 3725 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3726 } 3727 3728 /* Check the required size before mapping to conserve resources. */ 3729 if (bce_tso_enable) { 3730 max_size = BCE_TSO_MAX_SIZE; 3731 max_segments = BCE_MAX_SEGMENTS; 3732 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3733 } else { 3734 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3735 max_segments = BCE_MAX_SEGMENTS; 3736 max_seg_size = MCLBYTES; 3737 } 3738 3739 /* Create a DMA tag for TX mbufs. */ 3740 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3741 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3742 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3743 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3744 __FILE__, __LINE__); 3745 rc = ENOMEM; 3746 goto bce_dma_alloc_exit; 3747 } 3748 3749 /* Create DMA maps for the TX mbufs clusters. */ 3750 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3751 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3752 &sc->tx_mbuf_map[i])) { 3753 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3754 "map!\n", __FILE__, __LINE__); 3755 rc = ENOMEM; 3756 goto bce_dma_alloc_exit; 3757 } 3758 } 3759 3760 /* 3761 * Create a DMA tag for the RX buffer descriptor chain, 3762 * allocate and clear the memory, and fetch the physical 3763 * address of the blocks. 3764 */ 3765 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3766 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3767 sc->max_bus_addr, NULL, NULL, 3768 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3769 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3770 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3771 "DMA tag!\n", __FILE__, __LINE__); 3772 rc = ENOMEM; 3773 goto bce_dma_alloc_exit; 3774 } 3775 3776 for (i = 0; i < sc->rx_pages; i++) { 3777 3778 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3779 (void **)&sc->rx_bd_chain[i], 3780 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3781 &sc->rx_bd_chain_map[i])) { 3782 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3783 "chain DMA memory!\n", __FILE__, __LINE__); 3784 rc = ENOMEM; 3785 goto bce_dma_alloc_exit; 3786 } 3787 3788 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3789 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3790 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3791 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3792 3793 if (error) { 3794 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3795 "chain DMA memory!\n", __FILE__, __LINE__); 3796 rc = ENOMEM; 3797 goto bce_dma_alloc_exit; 3798 } 3799 3800 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3801 "0x%jX\n", __FUNCTION__, i, 3802 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3803 } 3804 3805 /* 3806 * Create a DMA tag for RX mbufs. 3807 */ 3808 if (bce_hdr_split == TRUE) 3809 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3810 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3811 else 3812 max_size = max_seg_size = MJUM9BYTES; 3813 max_segments = 1; 3814 3815 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3816 "(max size = 0x%jX max segments = %d, max segment " 3817 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, 3818 max_segments, (uintmax_t) max_seg_size); 3819 3820 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3821 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3822 max_size, max_segments, max_seg_size, 0, NULL, NULL, 3823 &sc->rx_mbuf_tag)) { 3824 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3825 __FILE__, __LINE__); 3826 rc = ENOMEM; 3827 goto bce_dma_alloc_exit; 3828 } 3829 3830 /* Create DMA maps for the RX mbuf clusters. */ 3831 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3832 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3833 &sc->rx_mbuf_map[i])) { 3834 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3835 "DMA map!\n", __FILE__, __LINE__); 3836 rc = ENOMEM; 3837 goto bce_dma_alloc_exit; 3838 } 3839 } 3840 3841 if (bce_hdr_split == TRUE) { 3842 /* 3843 * Create a DMA tag for the page buffer descriptor chain, 3844 * allocate and clear the memory, and fetch the physical 3845 * address of the blocks. 3846 */ 3847 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3848 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3849 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3850 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3851 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3852 "chain DMA tag!\n", __FILE__, __LINE__); 3853 rc = ENOMEM; 3854 goto bce_dma_alloc_exit; 3855 } 3856 3857 for (i = 0; i < sc->pg_pages; i++) { 3858 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3859 (void **)&sc->pg_bd_chain[i], 3860 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3861 &sc->pg_bd_chain_map[i])) { 3862 BCE_PRINTF("%s(%d): Could not allocate page " 3863 "descriptor chain DMA memory!\n", 3864 __FILE__, __LINE__); 3865 rc = ENOMEM; 3866 goto bce_dma_alloc_exit; 3867 } 3868 3869 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3870 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3871 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3872 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3873 3874 if (error) { 3875 BCE_PRINTF("%s(%d): Could not map page descriptor " 3876 "chain DMA memory!\n", __FILE__, __LINE__); 3877 rc = ENOMEM; 3878 goto bce_dma_alloc_exit; 3879 } 3880 3881 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3882 "0x%jX\n", __FUNCTION__, i, 3883 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3884 } 3885 3886 /* 3887 * Create a DMA tag for page mbufs. 3888 */ 3889 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3890 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3891 3892 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3893 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3894 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3895 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3896 "DMA tag!\n", __FILE__, __LINE__); 3897 rc = ENOMEM; 3898 goto bce_dma_alloc_exit; 3899 } 3900 3901 /* Create DMA maps for the page mbuf clusters. */ 3902 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3903 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3904 &sc->pg_mbuf_map[i])) { 3905 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3906 "DMA map!\n", __FILE__, __LINE__); 3907 rc = ENOMEM; 3908 goto bce_dma_alloc_exit; 3909 } 3910 } 3911 } 3912 3913 bce_dma_alloc_exit: 3914 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3915 return(rc); 3916 } 3917 3918 3919 /****************************************************************************/ 3920 /* Release all resources used by the driver. */ 3921 /* */ 3922 /* Releases all resources acquired by the driver including interrupts, */ 3923 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3924 /* */ 3925 /* Returns: */ 3926 /* Nothing. */ 3927 /****************************************************************************/ 3928 static void 3929 bce_release_resources(struct bce_softc *sc) 3930 { 3931 device_t dev; 3932 3933 DBENTER(BCE_VERBOSE_RESET); 3934 3935 dev = sc->bce_dev; 3936 3937 bce_dma_free(sc); 3938 3939 if (sc->bce_intrhand != NULL) { 3940 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3941 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3942 } 3943 3944 if (sc->bce_res_irq != NULL) { 3945 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3946 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3947 sc->bce_res_irq); 3948 } 3949 3950 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3951 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3952 pci_release_msi(dev); 3953 } 3954 3955 if (sc->bce_res_mem != NULL) { 3956 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3957 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3958 sc->bce_res_mem); 3959 } 3960 3961 if (sc->bce_ifp != NULL) { 3962 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3963 if_free(sc->bce_ifp); 3964 } 3965 3966 if (mtx_initialized(&sc->bce_mtx)) 3967 BCE_LOCK_DESTROY(sc); 3968 3969 DBEXIT(BCE_VERBOSE_RESET); 3970 } 3971 3972 3973 /****************************************************************************/ 3974 /* Firmware synchronization. */ 3975 /* */ 3976 /* Before performing certain events such as a chip reset, synchronize with */ 3977 /* the firmware first. */ 3978 /* */ 3979 /* Returns: */ 3980 /* 0 for success, positive value for failure. */ 3981 /****************************************************************************/ 3982 static int 3983 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3984 { 3985 int i, rc = 0; 3986 u32 val; 3987 3988 DBENTER(BCE_VERBOSE_RESET); 3989 3990 /* Don't waste any time if we've timed out before. */ 3991 if (sc->bce_fw_timed_out == TRUE) { 3992 rc = EBUSY; 3993 goto bce_fw_sync_exit; 3994 } 3995 3996 /* Increment the message sequence number. */ 3997 sc->bce_fw_wr_seq++; 3998 msg_data |= sc->bce_fw_wr_seq; 3999 4000 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 4001 "0x%08X\n", msg_data); 4002 4003 /* Send the message to the bootcode driver mailbox. */ 4004 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 4005 4006 /* Wait for the bootcode to acknowledge the message. */ 4007 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 4008 /* Check for a response in the bootcode firmware mailbox. */ 4009 val = bce_shmem_rd(sc, BCE_FW_MB); 4010 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 4011 break; 4012 DELAY(1000); 4013 } 4014 4015 /* If we've timed out, tell bootcode that we've stopped waiting. */ 4016 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 4017 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 4018 4019 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 4020 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 4021 4022 msg_data &= ~BCE_DRV_MSG_CODE; 4023 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 4024 4025 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 4026 4027 sc->bce_fw_timed_out = TRUE; 4028 rc = EBUSY; 4029 } 4030 4031 bce_fw_sync_exit: 4032 DBEXIT(BCE_VERBOSE_RESET); 4033 return (rc); 4034 } 4035 4036 4037 /****************************************************************************/ 4038 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 4039 /* */ 4040 /* Returns: */ 4041 /* Nothing. */ 4042 /****************************************************************************/ 4043 static void 4044 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 4045 u32 rv2p_code_len, u32 rv2p_proc) 4046 { 4047 int i; 4048 u32 val; 4049 4050 DBENTER(BCE_VERBOSE_RESET); 4051 4052 /* Set the page size used by RV2P. */ 4053 if (rv2p_proc == RV2P_PROC2) { 4054 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 4055 } 4056 4057 for (i = 0; i < rv2p_code_len; i += 8) { 4058 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 4059 rv2p_code++; 4060 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 4061 rv2p_code++; 4062 4063 if (rv2p_proc == RV2P_PROC1) { 4064 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4065 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4066 } 4067 else { 4068 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4069 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4070 } 4071 } 4072 4073 /* Reset the processor, un-stall is done later. */ 4074 if (rv2p_proc == RV2P_PROC1) { 4075 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4076 } 4077 else { 4078 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4079 } 4080 4081 DBEXIT(BCE_VERBOSE_RESET); 4082 } 4083 4084 4085 /****************************************************************************/ 4086 /* Load RISC processor firmware. */ 4087 /* */ 4088 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4089 /* associated with a particular processor. */ 4090 /* */ 4091 /* Returns: */ 4092 /* Nothing. */ 4093 /****************************************************************************/ 4094 static void 4095 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4096 struct fw_info *fw) 4097 { 4098 u32 offset; 4099 4100 DBENTER(BCE_VERBOSE_RESET); 4101 4102 bce_halt_cpu(sc, cpu_reg); 4103 4104 /* Load the Text area. */ 4105 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4106 if (fw->text) { 4107 int j; 4108 4109 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4110 REG_WR_IND(sc, offset, fw->text[j]); 4111 } 4112 } 4113 4114 /* Load the Data area. */ 4115 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4116 if (fw->data) { 4117 int j; 4118 4119 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4120 REG_WR_IND(sc, offset, fw->data[j]); 4121 } 4122 } 4123 4124 /* Load the SBSS area. */ 4125 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4126 if (fw->sbss) { 4127 int j; 4128 4129 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4130 REG_WR_IND(sc, offset, fw->sbss[j]); 4131 } 4132 } 4133 4134 /* Load the BSS area. */ 4135 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4136 if (fw->bss) { 4137 int j; 4138 4139 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4140 REG_WR_IND(sc, offset, fw->bss[j]); 4141 } 4142 } 4143 4144 /* Load the Read-Only area. */ 4145 offset = cpu_reg->spad_base + 4146 (fw->rodata_addr - cpu_reg->mips_view_base); 4147 if (fw->rodata) { 4148 int j; 4149 4150 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4151 REG_WR_IND(sc, offset, fw->rodata[j]); 4152 } 4153 } 4154 4155 /* Clear the pre-fetch instruction and set the FW start address. */ 4156 REG_WR_IND(sc, cpu_reg->inst, 0); 4157 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4158 4159 DBEXIT(BCE_VERBOSE_RESET); 4160 } 4161 4162 4163 /****************************************************************************/ 4164 /* Starts the RISC processor. */ 4165 /* */ 4166 /* Assumes the CPU starting address has already been set. */ 4167 /* */ 4168 /* Returns: */ 4169 /* Nothing. */ 4170 /****************************************************************************/ 4171 static void 4172 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4173 { 4174 u32 val; 4175 4176 DBENTER(BCE_VERBOSE_RESET); 4177 4178 /* Start the CPU. */ 4179 val = REG_RD_IND(sc, cpu_reg->mode); 4180 val &= ~cpu_reg->mode_value_halt; 4181 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4182 REG_WR_IND(sc, cpu_reg->mode, val); 4183 4184 DBEXIT(BCE_VERBOSE_RESET); 4185 } 4186 4187 4188 /****************************************************************************/ 4189 /* Halts the RISC processor. */ 4190 /* */ 4191 /* Returns: */ 4192 /* Nothing. */ 4193 /****************************************************************************/ 4194 static void 4195 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4196 { 4197 u32 val; 4198 4199 DBENTER(BCE_VERBOSE_RESET); 4200 4201 /* Halt the CPU. */ 4202 val = REG_RD_IND(sc, cpu_reg->mode); 4203 val |= cpu_reg->mode_value_halt; 4204 REG_WR_IND(sc, cpu_reg->mode, val); 4205 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4206 4207 DBEXIT(BCE_VERBOSE_RESET); 4208 } 4209 4210 4211 /****************************************************************************/ 4212 /* Initialize the RX CPU. */ 4213 /* */ 4214 /* Returns: */ 4215 /* Nothing. */ 4216 /****************************************************************************/ 4217 static void 4218 bce_start_rxp_cpu(struct bce_softc *sc) 4219 { 4220 struct cpu_reg cpu_reg; 4221 4222 DBENTER(BCE_VERBOSE_RESET); 4223 4224 cpu_reg.mode = BCE_RXP_CPU_MODE; 4225 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4226 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4227 cpu_reg.state = BCE_RXP_CPU_STATE; 4228 cpu_reg.state_value_clear = 0xffffff; 4229 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4230 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4231 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4232 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4233 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4234 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4235 cpu_reg.mips_view_base = 0x8000000; 4236 4237 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4238 bce_start_cpu(sc, &cpu_reg); 4239 4240 DBEXIT(BCE_VERBOSE_RESET); 4241 } 4242 4243 4244 /****************************************************************************/ 4245 /* Initialize the RX CPU. */ 4246 /* */ 4247 /* Returns: */ 4248 /* Nothing. */ 4249 /****************************************************************************/ 4250 static void 4251 bce_init_rxp_cpu(struct bce_softc *sc) 4252 { 4253 struct cpu_reg cpu_reg; 4254 struct fw_info fw; 4255 4256 DBENTER(BCE_VERBOSE_RESET); 4257 4258 cpu_reg.mode = BCE_RXP_CPU_MODE; 4259 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4260 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4261 cpu_reg.state = BCE_RXP_CPU_STATE; 4262 cpu_reg.state_value_clear = 0xffffff; 4263 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4264 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4265 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4266 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4267 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4268 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4269 cpu_reg.mips_view_base = 0x8000000; 4270 4271 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4272 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4273 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4274 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4275 fw.start_addr = bce_RXP_b09FwStartAddr; 4276 4277 fw.text_addr = bce_RXP_b09FwTextAddr; 4278 fw.text_len = bce_RXP_b09FwTextLen; 4279 fw.text_index = 0; 4280 fw.text = bce_RXP_b09FwText; 4281 4282 fw.data_addr = bce_RXP_b09FwDataAddr; 4283 fw.data_len = bce_RXP_b09FwDataLen; 4284 fw.data_index = 0; 4285 fw.data = bce_RXP_b09FwData; 4286 4287 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4288 fw.sbss_len = bce_RXP_b09FwSbssLen; 4289 fw.sbss_index = 0; 4290 fw.sbss = bce_RXP_b09FwSbss; 4291 4292 fw.bss_addr = bce_RXP_b09FwBssAddr; 4293 fw.bss_len = bce_RXP_b09FwBssLen; 4294 fw.bss_index = 0; 4295 fw.bss = bce_RXP_b09FwBss; 4296 4297 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4298 fw.rodata_len = bce_RXP_b09FwRodataLen; 4299 fw.rodata_index = 0; 4300 fw.rodata = bce_RXP_b09FwRodata; 4301 } else { 4302 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4303 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4304 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4305 fw.start_addr = bce_RXP_b06FwStartAddr; 4306 4307 fw.text_addr = bce_RXP_b06FwTextAddr; 4308 fw.text_len = bce_RXP_b06FwTextLen; 4309 fw.text_index = 0; 4310 fw.text = bce_RXP_b06FwText; 4311 4312 fw.data_addr = bce_RXP_b06FwDataAddr; 4313 fw.data_len = bce_RXP_b06FwDataLen; 4314 fw.data_index = 0; 4315 fw.data = bce_RXP_b06FwData; 4316 4317 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4318 fw.sbss_len = bce_RXP_b06FwSbssLen; 4319 fw.sbss_index = 0; 4320 fw.sbss = bce_RXP_b06FwSbss; 4321 4322 fw.bss_addr = bce_RXP_b06FwBssAddr; 4323 fw.bss_len = bce_RXP_b06FwBssLen; 4324 fw.bss_index = 0; 4325 fw.bss = bce_RXP_b06FwBss; 4326 4327 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4328 fw.rodata_len = bce_RXP_b06FwRodataLen; 4329 fw.rodata_index = 0; 4330 fw.rodata = bce_RXP_b06FwRodata; 4331 } 4332 4333 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4334 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4335 4336 /* Delay RXP start until initialization is complete. */ 4337 4338 DBEXIT(BCE_VERBOSE_RESET); 4339 } 4340 4341 4342 /****************************************************************************/ 4343 /* Initialize the TX CPU. */ 4344 /* */ 4345 /* Returns: */ 4346 /* Nothing. */ 4347 /****************************************************************************/ 4348 static void 4349 bce_init_txp_cpu(struct bce_softc *sc) 4350 { 4351 struct cpu_reg cpu_reg; 4352 struct fw_info fw; 4353 4354 DBENTER(BCE_VERBOSE_RESET); 4355 4356 cpu_reg.mode = BCE_TXP_CPU_MODE; 4357 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4358 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4359 cpu_reg.state = BCE_TXP_CPU_STATE; 4360 cpu_reg.state_value_clear = 0xffffff; 4361 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4362 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4363 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4364 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4365 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4366 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4367 cpu_reg.mips_view_base = 0x8000000; 4368 4369 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4370 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4371 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4372 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4373 fw.start_addr = bce_TXP_b09FwStartAddr; 4374 4375 fw.text_addr = bce_TXP_b09FwTextAddr; 4376 fw.text_len = bce_TXP_b09FwTextLen; 4377 fw.text_index = 0; 4378 fw.text = bce_TXP_b09FwText; 4379 4380 fw.data_addr = bce_TXP_b09FwDataAddr; 4381 fw.data_len = bce_TXP_b09FwDataLen; 4382 fw.data_index = 0; 4383 fw.data = bce_TXP_b09FwData; 4384 4385 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4386 fw.sbss_len = bce_TXP_b09FwSbssLen; 4387 fw.sbss_index = 0; 4388 fw.sbss = bce_TXP_b09FwSbss; 4389 4390 fw.bss_addr = bce_TXP_b09FwBssAddr; 4391 fw.bss_len = bce_TXP_b09FwBssLen; 4392 fw.bss_index = 0; 4393 fw.bss = bce_TXP_b09FwBss; 4394 4395 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4396 fw.rodata_len = bce_TXP_b09FwRodataLen; 4397 fw.rodata_index = 0; 4398 fw.rodata = bce_TXP_b09FwRodata; 4399 } else { 4400 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4401 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4402 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4403 fw.start_addr = bce_TXP_b06FwStartAddr; 4404 4405 fw.text_addr = bce_TXP_b06FwTextAddr; 4406 fw.text_len = bce_TXP_b06FwTextLen; 4407 fw.text_index = 0; 4408 fw.text = bce_TXP_b06FwText; 4409 4410 fw.data_addr = bce_TXP_b06FwDataAddr; 4411 fw.data_len = bce_TXP_b06FwDataLen; 4412 fw.data_index = 0; 4413 fw.data = bce_TXP_b06FwData; 4414 4415 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4416 fw.sbss_len = bce_TXP_b06FwSbssLen; 4417 fw.sbss_index = 0; 4418 fw.sbss = bce_TXP_b06FwSbss; 4419 4420 fw.bss_addr = bce_TXP_b06FwBssAddr; 4421 fw.bss_len = bce_TXP_b06FwBssLen; 4422 fw.bss_index = 0; 4423 fw.bss = bce_TXP_b06FwBss; 4424 4425 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4426 fw.rodata_len = bce_TXP_b06FwRodataLen; 4427 fw.rodata_index = 0; 4428 fw.rodata = bce_TXP_b06FwRodata; 4429 } 4430 4431 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4432 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4433 bce_start_cpu(sc, &cpu_reg); 4434 4435 DBEXIT(BCE_VERBOSE_RESET); 4436 } 4437 4438 4439 /****************************************************************************/ 4440 /* Initialize the TPAT CPU. */ 4441 /* */ 4442 /* Returns: */ 4443 /* Nothing. */ 4444 /****************************************************************************/ 4445 static void 4446 bce_init_tpat_cpu(struct bce_softc *sc) 4447 { 4448 struct cpu_reg cpu_reg; 4449 struct fw_info fw; 4450 4451 DBENTER(BCE_VERBOSE_RESET); 4452 4453 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4454 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4455 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4456 cpu_reg.state = BCE_TPAT_CPU_STATE; 4457 cpu_reg.state_value_clear = 0xffffff; 4458 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4459 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4460 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4461 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4462 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4463 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4464 cpu_reg.mips_view_base = 0x8000000; 4465 4466 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4467 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4468 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4469 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4470 fw.start_addr = bce_TPAT_b09FwStartAddr; 4471 4472 fw.text_addr = bce_TPAT_b09FwTextAddr; 4473 fw.text_len = bce_TPAT_b09FwTextLen; 4474 fw.text_index = 0; 4475 fw.text = bce_TPAT_b09FwText; 4476 4477 fw.data_addr = bce_TPAT_b09FwDataAddr; 4478 fw.data_len = bce_TPAT_b09FwDataLen; 4479 fw.data_index = 0; 4480 fw.data = bce_TPAT_b09FwData; 4481 4482 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4483 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4484 fw.sbss_index = 0; 4485 fw.sbss = bce_TPAT_b09FwSbss; 4486 4487 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4488 fw.bss_len = bce_TPAT_b09FwBssLen; 4489 fw.bss_index = 0; 4490 fw.bss = bce_TPAT_b09FwBss; 4491 4492 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4493 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4494 fw.rodata_index = 0; 4495 fw.rodata = bce_TPAT_b09FwRodata; 4496 } else { 4497 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4498 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4499 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4500 fw.start_addr = bce_TPAT_b06FwStartAddr; 4501 4502 fw.text_addr = bce_TPAT_b06FwTextAddr; 4503 fw.text_len = bce_TPAT_b06FwTextLen; 4504 fw.text_index = 0; 4505 fw.text = bce_TPAT_b06FwText; 4506 4507 fw.data_addr = bce_TPAT_b06FwDataAddr; 4508 fw.data_len = bce_TPAT_b06FwDataLen; 4509 fw.data_index = 0; 4510 fw.data = bce_TPAT_b06FwData; 4511 4512 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4513 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4514 fw.sbss_index = 0; 4515 fw.sbss = bce_TPAT_b06FwSbss; 4516 4517 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4518 fw.bss_len = bce_TPAT_b06FwBssLen; 4519 fw.bss_index = 0; 4520 fw.bss = bce_TPAT_b06FwBss; 4521 4522 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4523 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4524 fw.rodata_index = 0; 4525 fw.rodata = bce_TPAT_b06FwRodata; 4526 } 4527 4528 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4529 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4530 bce_start_cpu(sc, &cpu_reg); 4531 4532 DBEXIT(BCE_VERBOSE_RESET); 4533 } 4534 4535 4536 /****************************************************************************/ 4537 /* Initialize the CP CPU. */ 4538 /* */ 4539 /* Returns: */ 4540 /* Nothing. */ 4541 /****************************************************************************/ 4542 static void 4543 bce_init_cp_cpu(struct bce_softc *sc) 4544 { 4545 struct cpu_reg cpu_reg; 4546 struct fw_info fw; 4547 4548 DBENTER(BCE_VERBOSE_RESET); 4549 4550 cpu_reg.mode = BCE_CP_CPU_MODE; 4551 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4552 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4553 cpu_reg.state = BCE_CP_CPU_STATE; 4554 cpu_reg.state_value_clear = 0xffffff; 4555 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4556 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4557 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4558 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4559 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4560 cpu_reg.spad_base = BCE_CP_SCRATCH; 4561 cpu_reg.mips_view_base = 0x8000000; 4562 4563 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4564 fw.ver_major = bce_CP_b09FwReleaseMajor; 4565 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4566 fw.ver_fix = bce_CP_b09FwReleaseFix; 4567 fw.start_addr = bce_CP_b09FwStartAddr; 4568 4569 fw.text_addr = bce_CP_b09FwTextAddr; 4570 fw.text_len = bce_CP_b09FwTextLen; 4571 fw.text_index = 0; 4572 fw.text = bce_CP_b09FwText; 4573 4574 fw.data_addr = bce_CP_b09FwDataAddr; 4575 fw.data_len = bce_CP_b09FwDataLen; 4576 fw.data_index = 0; 4577 fw.data = bce_CP_b09FwData; 4578 4579 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4580 fw.sbss_len = bce_CP_b09FwSbssLen; 4581 fw.sbss_index = 0; 4582 fw.sbss = bce_CP_b09FwSbss; 4583 4584 fw.bss_addr = bce_CP_b09FwBssAddr; 4585 fw.bss_len = bce_CP_b09FwBssLen; 4586 fw.bss_index = 0; 4587 fw.bss = bce_CP_b09FwBss; 4588 4589 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4590 fw.rodata_len = bce_CP_b09FwRodataLen; 4591 fw.rodata_index = 0; 4592 fw.rodata = bce_CP_b09FwRodata; 4593 } else { 4594 fw.ver_major = bce_CP_b06FwReleaseMajor; 4595 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4596 fw.ver_fix = bce_CP_b06FwReleaseFix; 4597 fw.start_addr = bce_CP_b06FwStartAddr; 4598 4599 fw.text_addr = bce_CP_b06FwTextAddr; 4600 fw.text_len = bce_CP_b06FwTextLen; 4601 fw.text_index = 0; 4602 fw.text = bce_CP_b06FwText; 4603 4604 fw.data_addr = bce_CP_b06FwDataAddr; 4605 fw.data_len = bce_CP_b06FwDataLen; 4606 fw.data_index = 0; 4607 fw.data = bce_CP_b06FwData; 4608 4609 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4610 fw.sbss_len = bce_CP_b06FwSbssLen; 4611 fw.sbss_index = 0; 4612 fw.sbss = bce_CP_b06FwSbss; 4613 4614 fw.bss_addr = bce_CP_b06FwBssAddr; 4615 fw.bss_len = bce_CP_b06FwBssLen; 4616 fw.bss_index = 0; 4617 fw.bss = bce_CP_b06FwBss; 4618 4619 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4620 fw.rodata_len = bce_CP_b06FwRodataLen; 4621 fw.rodata_index = 0; 4622 fw.rodata = bce_CP_b06FwRodata; 4623 } 4624 4625 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4626 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4627 bce_start_cpu(sc, &cpu_reg); 4628 4629 DBEXIT(BCE_VERBOSE_RESET); 4630 } 4631 4632 4633 /****************************************************************************/ 4634 /* Initialize the COM CPU. */ 4635 /* */ 4636 /* Returns: */ 4637 /* Nothing. */ 4638 /****************************************************************************/ 4639 static void 4640 bce_init_com_cpu(struct bce_softc *sc) 4641 { 4642 struct cpu_reg cpu_reg; 4643 struct fw_info fw; 4644 4645 DBENTER(BCE_VERBOSE_RESET); 4646 4647 cpu_reg.mode = BCE_COM_CPU_MODE; 4648 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4649 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4650 cpu_reg.state = BCE_COM_CPU_STATE; 4651 cpu_reg.state_value_clear = 0xffffff; 4652 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4653 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4654 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4655 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4656 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4657 cpu_reg.spad_base = BCE_COM_SCRATCH; 4658 cpu_reg.mips_view_base = 0x8000000; 4659 4660 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4661 fw.ver_major = bce_COM_b09FwReleaseMajor; 4662 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4663 fw.ver_fix = bce_COM_b09FwReleaseFix; 4664 fw.start_addr = bce_COM_b09FwStartAddr; 4665 4666 fw.text_addr = bce_COM_b09FwTextAddr; 4667 fw.text_len = bce_COM_b09FwTextLen; 4668 fw.text_index = 0; 4669 fw.text = bce_COM_b09FwText; 4670 4671 fw.data_addr = bce_COM_b09FwDataAddr; 4672 fw.data_len = bce_COM_b09FwDataLen; 4673 fw.data_index = 0; 4674 fw.data = bce_COM_b09FwData; 4675 4676 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4677 fw.sbss_len = bce_COM_b09FwSbssLen; 4678 fw.sbss_index = 0; 4679 fw.sbss = bce_COM_b09FwSbss; 4680 4681 fw.bss_addr = bce_COM_b09FwBssAddr; 4682 fw.bss_len = bce_COM_b09FwBssLen; 4683 fw.bss_index = 0; 4684 fw.bss = bce_COM_b09FwBss; 4685 4686 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4687 fw.rodata_len = bce_COM_b09FwRodataLen; 4688 fw.rodata_index = 0; 4689 fw.rodata = bce_COM_b09FwRodata; 4690 } else { 4691 fw.ver_major = bce_COM_b06FwReleaseMajor; 4692 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4693 fw.ver_fix = bce_COM_b06FwReleaseFix; 4694 fw.start_addr = bce_COM_b06FwStartAddr; 4695 4696 fw.text_addr = bce_COM_b06FwTextAddr; 4697 fw.text_len = bce_COM_b06FwTextLen; 4698 fw.text_index = 0; 4699 fw.text = bce_COM_b06FwText; 4700 4701 fw.data_addr = bce_COM_b06FwDataAddr; 4702 fw.data_len = bce_COM_b06FwDataLen; 4703 fw.data_index = 0; 4704 fw.data = bce_COM_b06FwData; 4705 4706 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4707 fw.sbss_len = bce_COM_b06FwSbssLen; 4708 fw.sbss_index = 0; 4709 fw.sbss = bce_COM_b06FwSbss; 4710 4711 fw.bss_addr = bce_COM_b06FwBssAddr; 4712 fw.bss_len = bce_COM_b06FwBssLen; 4713 fw.bss_index = 0; 4714 fw.bss = bce_COM_b06FwBss; 4715 4716 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4717 fw.rodata_len = bce_COM_b06FwRodataLen; 4718 fw.rodata_index = 0; 4719 fw.rodata = bce_COM_b06FwRodata; 4720 } 4721 4722 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4723 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4724 bce_start_cpu(sc, &cpu_reg); 4725 4726 DBEXIT(BCE_VERBOSE_RESET); 4727 } 4728 4729 4730 /****************************************************************************/ 4731 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4732 /* */ 4733 /* Loads the firmware for each CPU and starts the CPU. */ 4734 /* */ 4735 /* Returns: */ 4736 /* Nothing. */ 4737 /****************************************************************************/ 4738 static void 4739 bce_init_cpus(struct bce_softc *sc) 4740 { 4741 DBENTER(BCE_VERBOSE_RESET); 4742 4743 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4744 4745 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4746 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4747 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4748 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4749 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4750 } else { 4751 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4752 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4753 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4754 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4755 } 4756 4757 } else { 4758 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4759 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4760 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4761 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4762 } 4763 4764 bce_init_rxp_cpu(sc); 4765 bce_init_txp_cpu(sc); 4766 bce_init_tpat_cpu(sc); 4767 bce_init_com_cpu(sc); 4768 bce_init_cp_cpu(sc); 4769 4770 DBEXIT(BCE_VERBOSE_RESET); 4771 } 4772 4773 4774 /****************************************************************************/ 4775 /* Initialize context memory. */ 4776 /* */ 4777 /* Clears the memory associated with each Context ID (CID). */ 4778 /* */ 4779 /* Returns: */ 4780 /* Nothing. */ 4781 /****************************************************************************/ 4782 static int 4783 bce_init_ctx(struct bce_softc *sc) 4784 { 4785 u32 offset, val, vcid_addr; 4786 int i, j, rc, retry_cnt; 4787 4788 rc = 0; 4789 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4790 4791 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4792 retry_cnt = CTX_INIT_RETRY_COUNT; 4793 4794 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4795 4796 /* 4797 * BCM5709 context memory may be cached 4798 * in host memory so prepare the host memory 4799 * for access. 4800 */ 4801 val = BCE_CTX_COMMAND_ENABLED | 4802 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4803 val |= (BCM_PAGE_BITS - 8) << 16; 4804 REG_WR(sc, BCE_CTX_COMMAND, val); 4805 4806 /* Wait for mem init command to complete. */ 4807 for (i = 0; i < retry_cnt; i++) { 4808 val = REG_RD(sc, BCE_CTX_COMMAND); 4809 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4810 break; 4811 DELAY(2); 4812 } 4813 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4814 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4815 __FUNCTION__); 4816 rc = EBUSY; 4817 goto init_ctx_fail; 4818 } 4819 4820 for (i = 0; i < sc->ctx_pages; i++) { 4821 /* Set the physical address of the context memory. */ 4822 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4823 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4824 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4825 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4826 BCE_ADDR_HI(sc->ctx_paddr[i])); 4827 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4828 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4829 4830 /* Verify the context memory write was successful. */ 4831 for (j = 0; j < retry_cnt; j++) { 4832 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4833 if ((val & 4834 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4835 break; 4836 DELAY(5); 4837 } 4838 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4839 BCE_PRINTF("%s(): Failed to initialize " 4840 "context page %d!\n", __FUNCTION__, i); 4841 rc = EBUSY; 4842 goto init_ctx_fail; 4843 } 4844 } 4845 } else { 4846 4847 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4848 4849 /* 4850 * For the 5706/5708, context memory is local to 4851 * the controller, so initialize the controller 4852 * context memory. 4853 */ 4854 4855 vcid_addr = GET_CID_ADDR(96); 4856 while (vcid_addr) { 4857 4858 vcid_addr -= PHY_CTX_SIZE; 4859 4860 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4861 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4862 4863 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4864 CTX_WR(sc, 0x00, offset, 0); 4865 } 4866 4867 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4868 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4869 } 4870 4871 } 4872 init_ctx_fail: 4873 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4874 return (rc); 4875 } 4876 4877 4878 /****************************************************************************/ 4879 /* Fetch the permanent MAC address of the controller. */ 4880 /* */ 4881 /* Returns: */ 4882 /* Nothing. */ 4883 /****************************************************************************/ 4884 static void 4885 bce_get_mac_addr(struct bce_softc *sc) 4886 { 4887 u32 mac_lo = 0, mac_hi = 0; 4888 4889 DBENTER(BCE_VERBOSE_RESET); 4890 4891 /* 4892 * The NetXtreme II bootcode populates various NIC 4893 * power-on and runtime configuration items in a 4894 * shared memory area. The factory configured MAC 4895 * address is available from both NVRAM and the 4896 * shared memory area so we'll read the value from 4897 * shared memory for speed. 4898 */ 4899 4900 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4901 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4902 4903 if ((mac_lo == 0) && (mac_hi == 0)) { 4904 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4905 __FILE__, __LINE__); 4906 } else { 4907 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4908 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4909 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4910 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4911 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4912 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4913 } 4914 4915 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4916 "address = %6D\n", sc->eaddr, ":"); 4917 DBEXIT(BCE_VERBOSE_RESET); 4918 } 4919 4920 4921 /****************************************************************************/ 4922 /* Program the MAC address. */ 4923 /* */ 4924 /* Returns: */ 4925 /* Nothing. */ 4926 /****************************************************************************/ 4927 static void 4928 bce_set_mac_addr(struct bce_softc *sc) 4929 { 4930 u32 val; 4931 u8 *mac_addr = sc->eaddr; 4932 4933 /* ToDo: Add support for setting multiple MAC addresses. */ 4934 4935 DBENTER(BCE_VERBOSE_RESET); 4936 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4937 "%6D\n", sc->eaddr, ":"); 4938 4939 val = (mac_addr[0] << 8) | mac_addr[1]; 4940 4941 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4942 4943 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4944 (mac_addr[4] << 8) | mac_addr[5]; 4945 4946 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4947 4948 DBEXIT(BCE_VERBOSE_RESET); 4949 } 4950 4951 4952 /****************************************************************************/ 4953 /* Stop the controller. */ 4954 /* */ 4955 /* Returns: */ 4956 /* Nothing. */ 4957 /****************************************************************************/ 4958 static void 4959 bce_stop(struct bce_softc *sc) 4960 { 4961 struct ifnet *ifp; 4962 4963 DBENTER(BCE_VERBOSE_RESET); 4964 4965 BCE_LOCK_ASSERT(sc); 4966 4967 ifp = sc->bce_ifp; 4968 4969 callout_stop(&sc->bce_tick_callout); 4970 4971 /* Disable the transmit/receive blocks. */ 4972 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4973 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4974 DELAY(20); 4975 4976 bce_disable_intr(sc); 4977 4978 /* Free RX buffers. */ 4979 if (bce_hdr_split == TRUE) { 4980 bce_free_pg_chain(sc); 4981 } 4982 bce_free_rx_chain(sc); 4983 4984 /* Free TX buffers. */ 4985 bce_free_tx_chain(sc); 4986 4987 sc->watchdog_timer = 0; 4988 4989 sc->bce_link_up = FALSE; 4990 4991 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4992 4993 DBEXIT(BCE_VERBOSE_RESET); 4994 } 4995 4996 4997 static int 4998 bce_reset(struct bce_softc *sc, u32 reset_code) 4999 { 5000 u32 val; 5001 int i, rc = 0; 5002 5003 DBENTER(BCE_VERBOSE_RESET); 5004 5005 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 5006 __FUNCTION__, reset_code); 5007 5008 /* Wait for pending PCI transactions to complete. */ 5009 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 5010 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 5011 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 5012 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 5013 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 5014 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 5015 DELAY(5); 5016 5017 /* Disable DMA */ 5018 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5019 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5020 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5021 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5022 } 5023 5024 /* Assume bootcode is running. */ 5025 sc->bce_fw_timed_out = FALSE; 5026 sc->bce_drv_cardiac_arrest = FALSE; 5027 5028 /* Give the firmware a chance to prepare for the reset. */ 5029 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 5030 if (rc) 5031 goto bce_reset_exit; 5032 5033 /* Set a firmware reminder that this is a soft reset. */ 5034 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 5035 5036 /* Dummy read to force the chip to complete all current transactions. */ 5037 val = REG_RD(sc, BCE_MISC_ID); 5038 5039 /* Chip reset. */ 5040 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5041 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 5042 REG_RD(sc, BCE_MISC_COMMAND); 5043 DELAY(5); 5044 5045 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5046 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5047 5048 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 5049 } else { 5050 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5051 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5052 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5053 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 5054 5055 /* Allow up to 30us for reset to complete. */ 5056 for (i = 0; i < 10; i++) { 5057 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5058 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5059 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5060 break; 5061 } 5062 DELAY(10); 5063 } 5064 5065 /* Check that reset completed successfully. */ 5066 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5067 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5068 BCE_PRINTF("%s(%d): Reset failed!\n", 5069 __FILE__, __LINE__); 5070 rc = EBUSY; 5071 goto bce_reset_exit; 5072 } 5073 } 5074 5075 /* Make sure byte swapping is properly configured. */ 5076 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5077 if (val != 0x01020304) { 5078 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5079 __FILE__, __LINE__); 5080 rc = ENODEV; 5081 goto bce_reset_exit; 5082 } 5083 5084 /* Just completed a reset, assume that firmware is running again. */ 5085 sc->bce_fw_timed_out = FALSE; 5086 sc->bce_drv_cardiac_arrest = FALSE; 5087 5088 /* Wait for the firmware to finish its initialization. */ 5089 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5090 if (rc) 5091 BCE_PRINTF("%s(%d): Firmware did not complete " 5092 "initialization!\n", __FILE__, __LINE__); 5093 /* Get firmware capabilities. */ 5094 bce_fw_cap_init(sc); 5095 5096 bce_reset_exit: 5097 DBEXIT(BCE_VERBOSE_RESET); 5098 return (rc); 5099 } 5100 5101 5102 static int 5103 bce_chipinit(struct bce_softc *sc) 5104 { 5105 u32 val; 5106 int rc = 0; 5107 5108 DBENTER(BCE_VERBOSE_RESET); 5109 5110 bce_disable_intr(sc); 5111 5112 /* 5113 * Initialize DMA byte/word swapping, configure the number of DMA 5114 * channels and PCI clock compensation delay. 5115 */ 5116 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5117 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5118 #if BYTE_ORDER == BIG_ENDIAN 5119 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5120 #endif 5121 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5122 DMA_READ_CHANS << 12 | 5123 DMA_WRITE_CHANS << 16; 5124 5125 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5126 5127 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5128 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5129 5130 /* 5131 * This setting resolves a problem observed on certain Intel PCI 5132 * chipsets that cannot handle multiple outstanding DMA operations. 5133 * See errata E9_5706A1_65. 5134 */ 5135 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5136 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5137 !(sc->bce_flags & BCE_PCIX_FLAG)) 5138 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5139 5140 REG_WR(sc, BCE_DMA_CONFIG, val); 5141 5142 /* Enable the RX_V2P and Context state machines before access. */ 5143 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5144 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5145 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5146 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5147 5148 /* Initialize context mapping and zero out the quick contexts. */ 5149 if ((rc = bce_init_ctx(sc)) != 0) 5150 goto bce_chipinit_exit; 5151 5152 /* Initialize the on-boards CPUs */ 5153 bce_init_cpus(sc); 5154 5155 /* Enable management frames (NC-SI) to flow to the MCP. */ 5156 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5157 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5158 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5159 } 5160 5161 /* Prepare NVRAM for access. */ 5162 if ((rc = bce_init_nvram(sc)) != 0) 5163 goto bce_chipinit_exit; 5164 5165 /* Set the kernel bypass block size */ 5166 val = REG_RD(sc, BCE_MQ_CONFIG); 5167 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5168 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5169 5170 /* Enable bins used on the 5709. */ 5171 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5172 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5173 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5174 val |= BCE_MQ_CONFIG_HALT_DIS; 5175 } 5176 5177 REG_WR(sc, BCE_MQ_CONFIG, val); 5178 5179 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5180 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5181 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5182 5183 /* Set the page size and clear the RV2P processor stall bits. */ 5184 val = (BCM_PAGE_BITS - 8) << 24; 5185 REG_WR(sc, BCE_RV2P_CONFIG, val); 5186 5187 /* Configure page size. */ 5188 val = REG_RD(sc, BCE_TBDR_CONFIG); 5189 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5190 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5191 REG_WR(sc, BCE_TBDR_CONFIG, val); 5192 5193 /* Set the perfect match control register to default. */ 5194 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5195 5196 bce_chipinit_exit: 5197 DBEXIT(BCE_VERBOSE_RESET); 5198 5199 return(rc); 5200 } 5201 5202 5203 /****************************************************************************/ 5204 /* Initialize the controller in preparation to send/receive traffic. */ 5205 /* */ 5206 /* Returns: */ 5207 /* 0 for success, positive value for failure. */ 5208 /****************************************************************************/ 5209 static int 5210 bce_blockinit(struct bce_softc *sc) 5211 { 5212 u32 reg, val; 5213 int rc = 0; 5214 5215 DBENTER(BCE_VERBOSE_RESET); 5216 5217 /* Load the hardware default MAC address. */ 5218 bce_set_mac_addr(sc); 5219 5220 /* Set the Ethernet backoff seed value */ 5221 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5222 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5223 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5224 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5225 5226 sc->last_status_idx = 0; 5227 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5228 5229 /* Set up link change interrupt generation. */ 5230 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5231 5232 /* Program the physical address of the status block. */ 5233 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5234 BCE_ADDR_LO(sc->status_block_paddr)); 5235 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5236 BCE_ADDR_HI(sc->status_block_paddr)); 5237 5238 /* Program the physical address of the statistics block. */ 5239 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5240 BCE_ADDR_LO(sc->stats_block_paddr)); 5241 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5242 BCE_ADDR_HI(sc->stats_block_paddr)); 5243 5244 /* Program various host coalescing parameters. */ 5245 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5246 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 5247 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5248 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 5249 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 5250 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 5251 REG_WR(sc, BCE_HC_TX_TICKS, 5252 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5253 REG_WR(sc, BCE_HC_RX_TICKS, 5254 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5255 REG_WR(sc, BCE_HC_COM_TICKS, 5256 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 5257 REG_WR(sc, BCE_HC_CMD_TICKS, 5258 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 5259 REG_WR(sc, BCE_HC_STATS_TICKS, 5260 (sc->bce_stats_ticks & 0xffff00)); 5261 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5262 5263 /* Configure the Host Coalescing block. */ 5264 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5265 BCE_HC_CONFIG_COLLECT_STATS; 5266 5267 #if 0 5268 /* ToDo: Add MSI-X support. */ 5269 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5270 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5271 BCE_HC_SB_CONFIG_1; 5272 5273 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5274 5275 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5276 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5277 5278 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5279 (sc->tx_quick_cons_trip_int << 16) | 5280 sc->tx_quick_cons_trip); 5281 5282 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5283 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5284 5285 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5286 } 5287 5288 /* 5289 * Tell the HC block to automatically set the 5290 * INT_MASK bit after an MSI/MSI-X interrupt 5291 * is generated so the driver doesn't have to. 5292 */ 5293 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5294 val |= BCE_HC_CONFIG_ONE_SHOT; 5295 5296 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5297 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5298 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5299 #endif 5300 5301 REG_WR(sc, BCE_HC_CONFIG, val); 5302 5303 /* Clear the internal statistics counters. */ 5304 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5305 5306 /* Verify that bootcode is running. */ 5307 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5308 5309 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5310 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5311 __FILE__, __LINE__); 5312 reg = 0); 5313 5314 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5315 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5316 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5317 "Expected: 08%08X\n", __FILE__, __LINE__, 5318 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5319 BCE_DEV_INFO_SIGNATURE_MAGIC); 5320 rc = ENODEV; 5321 goto bce_blockinit_exit; 5322 } 5323 5324 /* Enable DMA */ 5325 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5326 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5327 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5328 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5329 } 5330 5331 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5332 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5333 BCE_DRV_MSG_CODE_RESET); 5334 5335 /* Enable link state change interrupt generation. */ 5336 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5337 5338 /* Enable the RXP. */ 5339 bce_start_rxp_cpu(sc); 5340 5341 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5342 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5343 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5344 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5345 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5346 } 5347 5348 /* Enable all remaining blocks in the MAC. */ 5349 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5350 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5351 BCE_MISC_ENABLE_DEFAULT_XI); 5352 else 5353 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5354 BCE_MISC_ENABLE_DEFAULT); 5355 5356 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5357 DELAY(20); 5358 5359 /* Save the current host coalescing block settings. */ 5360 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5361 5362 bce_blockinit_exit: 5363 DBEXIT(BCE_VERBOSE_RESET); 5364 5365 return (rc); 5366 } 5367 5368 5369 /****************************************************************************/ 5370 /* Encapsulate an mbuf into the rx_bd chain. */ 5371 /* */ 5372 /* Returns: */ 5373 /* 0 for success, positive value for failure. */ 5374 /****************************************************************************/ 5375 static int 5376 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5377 u16 *chain_prod, u32 *prod_bseq) 5378 { 5379 bus_dmamap_t map; 5380 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 5381 struct mbuf *m_new = NULL; 5382 struct rx_bd *rxbd; 5383 int nsegs, error, rc = 0; 5384 #ifdef BCE_DEBUG 5385 u16 debug_chain_prod = *chain_prod; 5386 #endif 5387 5388 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5389 5390 /* Make sure the inputs are valid. */ 5391 DBRUNIF((*chain_prod > MAX_RX_BD_ALLOC), 5392 BCE_PRINTF("%s(%d): RX producer out of range: " 5393 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5394 *chain_prod, (u16) MAX_RX_BD_ALLOC)); 5395 5396 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5397 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5398 *prod, *chain_prod, *prod_bseq); 5399 5400 /* Update some debug statistic counters */ 5401 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5402 sc->rx_low_watermark = sc->free_rx_bd); 5403 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5404 sc->rx_empty_count++); 5405 5406 /* Check whether this is a new mbuf allocation. */ 5407 if (m == NULL) { 5408 5409 /* Simulate an mbuf allocation failure. */ 5410 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5411 sc->mbuf_alloc_failed_count++; 5412 sc->mbuf_alloc_failed_sim_count++; 5413 rc = ENOBUFS; 5414 goto bce_get_rx_buf_exit); 5415 5416 /* This is a new mbuf allocation. */ 5417 if (bce_hdr_split == TRUE) 5418 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5419 else 5420 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 5421 sc->rx_bd_mbuf_alloc_size); 5422 5423 if (m_new == NULL) { 5424 sc->mbuf_alloc_failed_count++; 5425 rc = ENOBUFS; 5426 goto bce_get_rx_buf_exit; 5427 } 5428 5429 DBRUN(sc->debug_rx_mbuf_alloc++); 5430 } else { 5431 /* Reuse an existing mbuf. */ 5432 m_new = m; 5433 } 5434 5435 /* Make sure we have a valid packet header. */ 5436 M_ASSERTPKTHDR(m_new); 5437 5438 /* Initialize the mbuf size and pad if necessary for alignment. */ 5439 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5440 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5441 5442 /* ToDo: Consider calling m_fragment() to test error handling. */ 5443 5444 /* Map the mbuf cluster into device memory. */ 5445 map = sc->rx_mbuf_map[*chain_prod]; 5446 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5447 segs, &nsegs, BUS_DMA_NOWAIT); 5448 5449 /* Handle any mapping errors. */ 5450 if (error) { 5451 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5452 "chain (%d)!\n", __FILE__, __LINE__, error); 5453 5454 sc->dma_map_addr_rx_failed_count++; 5455 m_freem(m_new); 5456 5457 DBRUN(sc->debug_rx_mbuf_alloc--); 5458 5459 rc = ENOBUFS; 5460 goto bce_get_rx_buf_exit; 5461 } 5462 5463 /* All mbufs must map to a single segment. */ 5464 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5465 __FUNCTION__, nsegs)); 5466 5467 /* Setup the rx_bd for the segment. */ 5468 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5469 5470 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5471 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5472 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5473 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5474 *prod_bseq += segs[0].ds_len; 5475 5476 /* Save the mbuf and update our counter. */ 5477 sc->rx_mbuf_ptr[*chain_prod] = m_new; 5478 sc->free_rx_bd -= nsegs; 5479 5480 DBRUNMSG(BCE_INSANE_RECV, 5481 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5482 5483 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5484 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", 5485 __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5486 5487 bce_get_rx_buf_exit: 5488 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5489 5490 return(rc); 5491 } 5492 5493 5494 /****************************************************************************/ 5495 /* Encapsulate an mbuf cluster into the page chain. */ 5496 /* */ 5497 /* Returns: */ 5498 /* 0 for success, positive value for failure. */ 5499 /****************************************************************************/ 5500 static int 5501 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5502 u16 *prod_idx) 5503 { 5504 bus_dmamap_t map; 5505 bus_addr_t busaddr; 5506 struct mbuf *m_new = NULL; 5507 struct rx_bd *pgbd; 5508 int error, rc = 0; 5509 #ifdef BCE_DEBUG 5510 u16 debug_prod_idx = *prod_idx; 5511 #endif 5512 5513 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5514 5515 /* Make sure the inputs are valid. */ 5516 DBRUNIF((*prod_idx > MAX_PG_BD_ALLOC), 5517 BCE_PRINTF("%s(%d): page producer out of range: " 5518 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5519 *prod_idx, (u16) MAX_PG_BD_ALLOC)); 5520 5521 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5522 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5523 5524 /* Update counters if we've hit a new low or run out of pages. */ 5525 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5526 sc->pg_low_watermark = sc->free_pg_bd); 5527 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5528 5529 /* Check whether this is a new mbuf allocation. */ 5530 if (m == NULL) { 5531 5532 /* Simulate an mbuf allocation failure. */ 5533 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5534 sc->mbuf_alloc_failed_count++; 5535 sc->mbuf_alloc_failed_sim_count++; 5536 rc = ENOBUFS; 5537 goto bce_get_pg_buf_exit); 5538 5539 /* This is a new mbuf allocation. */ 5540 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5541 if (m_new == NULL) { 5542 sc->mbuf_alloc_failed_count++; 5543 rc = ENOBUFS; 5544 goto bce_get_pg_buf_exit; 5545 } 5546 5547 DBRUN(sc->debug_pg_mbuf_alloc++); 5548 } else { 5549 /* Reuse an existing mbuf. */ 5550 m_new = m; 5551 m_new->m_data = m_new->m_ext.ext_buf; 5552 } 5553 5554 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5555 5556 /* ToDo: Consider calling m_fragment() to test error handling. */ 5557 5558 /* Map the mbuf cluster into device memory. */ 5559 map = sc->pg_mbuf_map[*prod_idx]; 5560 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5561 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, 5562 &busaddr, BUS_DMA_NOWAIT); 5563 5564 /* Handle any mapping errors. */ 5565 if (error) { 5566 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5567 __FILE__, __LINE__); 5568 5569 m_freem(m_new); 5570 DBRUN(sc->debug_pg_mbuf_alloc--); 5571 5572 rc = ENOBUFS; 5573 goto bce_get_pg_buf_exit; 5574 } 5575 5576 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5577 5578 /* 5579 * The page chain uses the same rx_bd data structure 5580 * as the receive chain but doesn't require a byte sequence (bseq). 5581 */ 5582 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5583 5584 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5585 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5586 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5587 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5588 5589 /* Save the mbuf and update our counter. */ 5590 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5591 sc->free_pg_bd--; 5592 5593 DBRUNMSG(BCE_INSANE_RECV, 5594 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5595 5596 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5597 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5598 5599 bce_get_pg_buf_exit: 5600 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5601 5602 return(rc); 5603 } 5604 5605 5606 /****************************************************************************/ 5607 /* Initialize the TX context memory. */ 5608 /* */ 5609 /* Returns: */ 5610 /* Nothing */ 5611 /****************************************************************************/ 5612 static void 5613 bce_init_tx_context(struct bce_softc *sc) 5614 { 5615 u32 val; 5616 5617 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5618 5619 /* Initialize the context ID for an L2 TX chain. */ 5620 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5621 /* Set the CID type to support an L2 connection. */ 5622 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5623 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5624 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5625 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5626 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5627 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5628 5629 /* Point the hardware to the first page in the chain. */ 5630 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5631 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5632 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5633 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5634 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5635 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5636 } else { 5637 /* Set the CID type to support an L2 connection. */ 5638 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5639 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5640 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5641 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5642 5643 /* Point the hardware to the first page in the chain. */ 5644 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5645 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5646 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5647 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5648 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5649 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5650 } 5651 5652 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5653 } 5654 5655 5656 /****************************************************************************/ 5657 /* Allocate memory and initialize the TX data structures. */ 5658 /* */ 5659 /* Returns: */ 5660 /* 0 for success, positive value for failure. */ 5661 /****************************************************************************/ 5662 static int 5663 bce_init_tx_chain(struct bce_softc *sc) 5664 { 5665 struct tx_bd *txbd; 5666 int i, rc = 0; 5667 5668 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5669 5670 /* Set the initial TX producer/consumer indices. */ 5671 sc->tx_prod = 0; 5672 sc->tx_cons = 0; 5673 sc->tx_prod_bseq = 0; 5674 sc->used_tx_bd = 0; 5675 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5676 DBRUN(sc->tx_hi_watermark = 0); 5677 DBRUN(sc->tx_full_count = 0); 5678 5679 /* 5680 * The NetXtreme II supports a linked-list structre called 5681 * a Buffer Descriptor Chain (or BD chain). A BD chain 5682 * consists of a series of 1 or more chain pages, each of which 5683 * consists of a fixed number of BD entries. 5684 * The last BD entry on each page is a pointer to the next page 5685 * in the chain, and the last pointer in the BD chain 5686 * points back to the beginning of the chain. 5687 */ 5688 5689 /* Set the TX next pointer chain entries. */ 5690 for (i = 0; i < sc->tx_pages; i++) { 5691 int j; 5692 5693 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5694 5695 /* Check if we've reached the last page. */ 5696 if (i == (sc->tx_pages - 1)) 5697 j = 0; 5698 else 5699 j = i + 1; 5700 5701 txbd->tx_bd_haddr_hi = 5702 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5703 txbd->tx_bd_haddr_lo = 5704 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5705 } 5706 5707 bce_init_tx_context(sc); 5708 5709 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5710 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5711 5712 return(rc); 5713 } 5714 5715 5716 /****************************************************************************/ 5717 /* Free memory and clear the TX data structures. */ 5718 /* */ 5719 /* Returns: */ 5720 /* Nothing. */ 5721 /****************************************************************************/ 5722 static void 5723 bce_free_tx_chain(struct bce_softc *sc) 5724 { 5725 int i; 5726 5727 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5728 5729 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5730 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5731 if (sc->tx_mbuf_ptr[i] != NULL) { 5732 if (sc->tx_mbuf_map[i] != NULL) 5733 bus_dmamap_sync(sc->tx_mbuf_tag, 5734 sc->tx_mbuf_map[i], 5735 BUS_DMASYNC_POSTWRITE); 5736 m_freem(sc->tx_mbuf_ptr[i]); 5737 sc->tx_mbuf_ptr[i] = NULL; 5738 DBRUN(sc->debug_tx_mbuf_alloc--); 5739 } 5740 } 5741 5742 /* Clear each TX chain page. */ 5743 for (i = 0; i < sc->tx_pages; i++) 5744 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5745 5746 sc->used_tx_bd = 0; 5747 5748 /* Check if we lost any mbufs in the process. */ 5749 DBRUNIF((sc->debug_tx_mbuf_alloc), 5750 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5751 "from tx chain!\n", __FILE__, __LINE__, 5752 sc->debug_tx_mbuf_alloc)); 5753 5754 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5755 } 5756 5757 5758 /****************************************************************************/ 5759 /* Initialize the RX context memory. */ 5760 /* */ 5761 /* Returns: */ 5762 /* Nothing */ 5763 /****************************************************************************/ 5764 static void 5765 bce_init_rx_context(struct bce_softc *sc) 5766 { 5767 u32 val; 5768 5769 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5770 5771 /* Init the type, size, and BD cache levels for the RX context. */ 5772 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5773 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5774 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5775 5776 /* 5777 * Set the level for generating pause frames 5778 * when the number of available rx_bd's gets 5779 * too low (the low watermark) and the level 5780 * when pause frames can be stopped (the high 5781 * watermark). 5782 */ 5783 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5784 u32 lo_water, hi_water; 5785 5786 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5787 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5788 } else { 5789 lo_water = 0; 5790 } 5791 5792 if (lo_water >= USABLE_RX_BD_ALLOC) { 5793 lo_water = 0; 5794 } 5795 5796 hi_water = USABLE_RX_BD_ALLOC / 4; 5797 5798 if (hi_water <= lo_water) { 5799 lo_water = 0; 5800 } 5801 5802 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5803 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5804 5805 if (hi_water > 0xf) 5806 hi_water = 0xf; 5807 else if (hi_water == 0) 5808 lo_water = 0; 5809 5810 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5811 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5812 } 5813 5814 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5815 5816 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5817 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5818 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5819 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5820 } 5821 5822 /* Point the hardware to the first page in the chain. */ 5823 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5824 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5825 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5826 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5827 5828 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5829 } 5830 5831 5832 /****************************************************************************/ 5833 /* Allocate memory and initialize the RX data structures. */ 5834 /* */ 5835 /* Returns: */ 5836 /* 0 for success, positive value for failure. */ 5837 /****************************************************************************/ 5838 static int 5839 bce_init_rx_chain(struct bce_softc *sc) 5840 { 5841 struct rx_bd *rxbd; 5842 int i, rc = 0; 5843 5844 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5845 BCE_VERBOSE_CTX); 5846 5847 /* Initialize the RX producer and consumer indices. */ 5848 sc->rx_prod = 0; 5849 sc->rx_cons = 0; 5850 sc->rx_prod_bseq = 0; 5851 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5852 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5853 5854 /* Initialize the RX next pointer chain entries. */ 5855 for (i = 0; i < sc->rx_pages; i++) { 5856 int j; 5857 5858 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5859 5860 /* Check if we've reached the last page. */ 5861 if (i == (sc->rx_pages - 1)) 5862 j = 0; 5863 else 5864 j = i + 1; 5865 5866 /* Setup the chain page pointers. */ 5867 rxbd->rx_bd_haddr_hi = 5868 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5869 rxbd->rx_bd_haddr_lo = 5870 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5871 } 5872 5873 /* Fill up the RX chain. */ 5874 bce_fill_rx_chain(sc); 5875 5876 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5877 DBRUN(sc->rx_empty_count = 0); 5878 for (i = 0; i < sc->rx_pages; i++) { 5879 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5880 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5881 } 5882 5883 bce_init_rx_context(sc); 5884 5885 DBRUNMSG(BCE_EXTREME_RECV, 5886 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5887 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5888 BCE_VERBOSE_CTX); 5889 5890 /* ToDo: Are there possible failure modes here? */ 5891 5892 return(rc); 5893 } 5894 5895 5896 /****************************************************************************/ 5897 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5898 /* occurs. */ 5899 /* */ 5900 /* Returns: */ 5901 /* Nothing */ 5902 /****************************************************************************/ 5903 static void 5904 bce_fill_rx_chain(struct bce_softc *sc) 5905 { 5906 u16 prod, prod_idx; 5907 u32 prod_bseq; 5908 5909 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5910 BCE_VERBOSE_CTX); 5911 5912 /* Get the RX chain producer indices. */ 5913 prod = sc->rx_prod; 5914 prod_bseq = sc->rx_prod_bseq; 5915 5916 /* Keep filling the RX chain until it's full. */ 5917 while (sc->free_rx_bd > 0) { 5918 prod_idx = RX_CHAIN_IDX(prod); 5919 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5920 /* Bail out if we can't add an mbuf to the chain. */ 5921 break; 5922 } 5923 prod = NEXT_RX_BD(prod); 5924 } 5925 5926 /* Save the RX chain producer indices. */ 5927 sc->rx_prod = prod; 5928 sc->rx_prod_bseq = prod_bseq; 5929 5930 /* We should never end up pointing to a next page pointer. */ 5931 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5932 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5933 __FUNCTION__, sc->rx_prod)); 5934 5935 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5936 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5937 BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); 5938 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + 5939 BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); 5940 5941 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5942 BCE_VERBOSE_CTX); 5943 } 5944 5945 5946 /****************************************************************************/ 5947 /* Free memory and clear the RX data structures. */ 5948 /* */ 5949 /* Returns: */ 5950 /* Nothing. */ 5951 /****************************************************************************/ 5952 static void 5953 bce_free_rx_chain(struct bce_softc *sc) 5954 { 5955 int i; 5956 5957 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5958 5959 /* Free any mbufs still in the RX mbuf chain. */ 5960 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5961 if (sc->rx_mbuf_ptr[i] != NULL) { 5962 if (sc->rx_mbuf_map[i] != NULL) 5963 bus_dmamap_sync(sc->rx_mbuf_tag, 5964 sc->rx_mbuf_map[i], 5965 BUS_DMASYNC_POSTREAD); 5966 m_freem(sc->rx_mbuf_ptr[i]); 5967 sc->rx_mbuf_ptr[i] = NULL; 5968 DBRUN(sc->debug_rx_mbuf_alloc--); 5969 } 5970 } 5971 5972 /* Clear each RX chain page. */ 5973 for (i = 0; i < sc->rx_pages; i++) 5974 if (sc->rx_bd_chain[i] != NULL) { 5975 bzero((char *)sc->rx_bd_chain[i], 5976 BCE_RX_CHAIN_PAGE_SZ); 5977 } 5978 5979 sc->free_rx_bd = sc->max_rx_bd; 5980 5981 /* Check if we lost any mbufs in the process. */ 5982 DBRUNIF((sc->debug_rx_mbuf_alloc), 5983 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5984 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5985 5986 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5987 } 5988 5989 5990 /****************************************************************************/ 5991 /* Allocate memory and initialize the page data structures. */ 5992 /* Assumes that bce_init_rx_chain() has not already been called. */ 5993 /* */ 5994 /* Returns: */ 5995 /* 0 for success, positive value for failure. */ 5996 /****************************************************************************/ 5997 static int 5998 bce_init_pg_chain(struct bce_softc *sc) 5999 { 6000 struct rx_bd *pgbd; 6001 int i, rc = 0; 6002 u32 val; 6003 6004 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6005 BCE_VERBOSE_CTX); 6006 6007 /* Initialize the page producer and consumer indices. */ 6008 sc->pg_prod = 0; 6009 sc->pg_cons = 0; 6010 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 6011 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 6012 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 6013 DBRUN(sc->pg_empty_count = 0); 6014 6015 /* Initialize the page next pointer chain entries. */ 6016 for (i = 0; i < sc->pg_pages; i++) { 6017 int j; 6018 6019 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 6020 6021 /* Check if we've reached the last page. */ 6022 if (i == (sc->pg_pages - 1)) 6023 j = 0; 6024 else 6025 j = i + 1; 6026 6027 /* Setup the chain page pointers. */ 6028 pgbd->rx_bd_haddr_hi = 6029 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 6030 pgbd->rx_bd_haddr_lo = 6031 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 6032 } 6033 6034 /* Setup the MQ BIN mapping for host_pg_bidx. */ 6035 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 6036 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 6037 6038 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 6039 6040 /* Configure the rx_bd and page chain mbuf cluster size. */ 6041 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 6042 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 6043 6044 /* Configure the context reserved for jumbo support. */ 6045 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 6046 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 6047 6048 /* Point the hardware to the first page in the page chain. */ 6049 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 6050 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 6051 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 6052 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 6053 6054 /* Fill up the page chain. */ 6055 bce_fill_pg_chain(sc); 6056 6057 for (i = 0; i < sc->pg_pages; i++) { 6058 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6059 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6060 } 6061 6062 DBRUNMSG(BCE_EXTREME_RECV, 6063 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6064 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6065 BCE_VERBOSE_CTX); 6066 return(rc); 6067 } 6068 6069 6070 /****************************************************************************/ 6071 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 6072 /* occurs. */ 6073 /* */ 6074 /* Returns: */ 6075 /* Nothing */ 6076 /****************************************************************************/ 6077 static void 6078 bce_fill_pg_chain(struct bce_softc *sc) 6079 { 6080 u16 prod, prod_idx; 6081 6082 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6083 BCE_VERBOSE_CTX); 6084 6085 /* Get the page chain prodcuer index. */ 6086 prod = sc->pg_prod; 6087 6088 /* Keep filling the page chain until it's full. */ 6089 while (sc->free_pg_bd > 0) { 6090 prod_idx = PG_CHAIN_IDX(prod); 6091 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 6092 /* Bail out if we can't add an mbuf to the chain. */ 6093 break; 6094 } 6095 prod = NEXT_PG_BD(prod); 6096 } 6097 6098 /* Save the page chain producer index. */ 6099 sc->pg_prod = prod; 6100 6101 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6102 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6103 __FUNCTION__, sc->pg_prod)); 6104 6105 /* 6106 * Write the mailbox and tell the chip about 6107 * the new rx_bd's in the page chain. 6108 */ 6109 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 6110 BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); 6111 6112 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6113 BCE_VERBOSE_CTX); 6114 } 6115 6116 6117 /****************************************************************************/ 6118 /* Free memory and clear the RX data structures. */ 6119 /* */ 6120 /* Returns: */ 6121 /* Nothing. */ 6122 /****************************************************************************/ 6123 static void 6124 bce_free_pg_chain(struct bce_softc *sc) 6125 { 6126 int i; 6127 6128 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6129 6130 /* Free any mbufs still in the mbuf page chain. */ 6131 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6132 if (sc->pg_mbuf_ptr[i] != NULL) { 6133 if (sc->pg_mbuf_map[i] != NULL) 6134 bus_dmamap_sync(sc->pg_mbuf_tag, 6135 sc->pg_mbuf_map[i], 6136 BUS_DMASYNC_POSTREAD); 6137 m_freem(sc->pg_mbuf_ptr[i]); 6138 sc->pg_mbuf_ptr[i] = NULL; 6139 DBRUN(sc->debug_pg_mbuf_alloc--); 6140 } 6141 } 6142 6143 /* Clear each page chain pages. */ 6144 for (i = 0; i < sc->pg_pages; i++) 6145 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6146 6147 sc->free_pg_bd = sc->max_pg_bd; 6148 6149 /* Check if we lost any mbufs in the process. */ 6150 DBRUNIF((sc->debug_pg_mbuf_alloc), 6151 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6152 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6153 6154 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6155 } 6156 6157 6158 static u32 6159 bce_get_rphy_link(struct bce_softc *sc) 6160 { 6161 u32 advertise, link; 6162 int fdpx; 6163 6164 advertise = 0; 6165 fdpx = 0; 6166 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6167 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6168 else 6169 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6170 if (link & BCE_NETLINK_ANEG_ENB) 6171 advertise |= BCE_NETLINK_ANEG_ENB; 6172 if (link & BCE_NETLINK_SPEED_10HALF) 6173 advertise |= BCE_NETLINK_SPEED_10HALF; 6174 if (link & BCE_NETLINK_SPEED_10FULL) { 6175 advertise |= BCE_NETLINK_SPEED_10FULL; 6176 fdpx++; 6177 } 6178 if (link & BCE_NETLINK_SPEED_100HALF) 6179 advertise |= BCE_NETLINK_SPEED_100HALF; 6180 if (link & BCE_NETLINK_SPEED_100FULL) { 6181 advertise |= BCE_NETLINK_SPEED_100FULL; 6182 fdpx++; 6183 } 6184 if (link & BCE_NETLINK_SPEED_1000HALF) 6185 advertise |= BCE_NETLINK_SPEED_1000HALF; 6186 if (link & BCE_NETLINK_SPEED_1000FULL) { 6187 advertise |= BCE_NETLINK_SPEED_1000FULL; 6188 fdpx++; 6189 } 6190 if (link & BCE_NETLINK_SPEED_2500HALF) 6191 advertise |= BCE_NETLINK_SPEED_2500HALF; 6192 if (link & BCE_NETLINK_SPEED_2500FULL) { 6193 advertise |= BCE_NETLINK_SPEED_2500FULL; 6194 fdpx++; 6195 } 6196 if (fdpx) 6197 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6198 BCE_NETLINK_FC_PAUSE_ASYM; 6199 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6200 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6201 BCE_NETLINK_ETH_AT_WIRESPEED; 6202 6203 return (advertise); 6204 } 6205 6206 6207 /****************************************************************************/ 6208 /* Set media options. */ 6209 /* */ 6210 /* Returns: */ 6211 /* 0 for success, positive value for failure. */ 6212 /****************************************************************************/ 6213 static int 6214 bce_ifmedia_upd(struct ifnet *ifp) 6215 { 6216 struct bce_softc *sc = ifp->if_softc; 6217 int error; 6218 6219 DBENTER(BCE_VERBOSE); 6220 6221 BCE_LOCK(sc); 6222 error = bce_ifmedia_upd_locked(ifp); 6223 BCE_UNLOCK(sc); 6224 6225 DBEXIT(BCE_VERBOSE); 6226 return (error); 6227 } 6228 6229 6230 /****************************************************************************/ 6231 /* Set media options. */ 6232 /* */ 6233 /* Returns: */ 6234 /* Nothing. */ 6235 /****************************************************************************/ 6236 static int 6237 bce_ifmedia_upd_locked(struct ifnet *ifp) 6238 { 6239 struct bce_softc *sc = ifp->if_softc; 6240 struct mii_data *mii; 6241 struct mii_softc *miisc; 6242 struct ifmedia *ifm; 6243 u32 link; 6244 int error, fdx; 6245 6246 DBENTER(BCE_VERBOSE_PHY); 6247 6248 error = 0; 6249 BCE_LOCK_ASSERT(sc); 6250 6251 sc->bce_link_up = FALSE; 6252 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6253 ifm = &sc->bce_ifmedia; 6254 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6255 return (EINVAL); 6256 link = 0; 6257 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6258 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6259 case IFM_AUTO: 6260 /* 6261 * Check advertised link of remote PHY by reading 6262 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6263 * Always use the same link type of remote PHY. 6264 */ 6265 link = bce_get_rphy_link(sc); 6266 break; 6267 case IFM_2500_SX: 6268 if ((sc->bce_phy_flags & 6269 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6270 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6271 return (EINVAL); 6272 /* 6273 * XXX 6274 * Have to enable forced 2.5Gbps configuration. 6275 */ 6276 if (fdx != 0) 6277 link |= BCE_NETLINK_SPEED_2500FULL; 6278 else 6279 link |= BCE_NETLINK_SPEED_2500HALF; 6280 break; 6281 case IFM_1000_SX: 6282 if ((sc->bce_phy_flags & 6283 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6284 return (EINVAL); 6285 /* 6286 * XXX 6287 * Have to disable 2.5Gbps configuration. 6288 */ 6289 if (fdx != 0) 6290 link = BCE_NETLINK_SPEED_1000FULL; 6291 else 6292 link = BCE_NETLINK_SPEED_1000HALF; 6293 break; 6294 case IFM_1000_T: 6295 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6296 return (EINVAL); 6297 if (fdx != 0) 6298 link = BCE_NETLINK_SPEED_1000FULL; 6299 else 6300 link = BCE_NETLINK_SPEED_1000HALF; 6301 break; 6302 case IFM_100_TX: 6303 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6304 return (EINVAL); 6305 if (fdx != 0) 6306 link = BCE_NETLINK_SPEED_100FULL; 6307 else 6308 link = BCE_NETLINK_SPEED_100HALF; 6309 break; 6310 case IFM_10_T: 6311 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6312 return (EINVAL); 6313 if (fdx != 0) 6314 link = BCE_NETLINK_SPEED_10FULL; 6315 else 6316 link = BCE_NETLINK_SPEED_10HALF; 6317 break; 6318 default: 6319 return (EINVAL); 6320 } 6321 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6322 /* 6323 * XXX 6324 * Advertise pause capability for full-duplex media. 6325 */ 6326 if (fdx != 0) 6327 link |= BCE_NETLINK_FC_PAUSE_SYM | 6328 BCE_NETLINK_FC_PAUSE_ASYM; 6329 if ((sc->bce_phy_flags & 6330 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6331 link |= BCE_NETLINK_PHY_APP_REMOTE | 6332 BCE_NETLINK_ETH_AT_WIRESPEED; 6333 } 6334 6335 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6336 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6337 } else { 6338 mii = device_get_softc(sc->bce_miibus); 6339 6340 /* Make sure the MII bus has been enumerated. */ 6341 if (mii) { 6342 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6343 PHY_RESET(miisc); 6344 error = mii_mediachg(mii); 6345 } 6346 } 6347 6348 DBEXIT(BCE_VERBOSE_PHY); 6349 return (error); 6350 } 6351 6352 6353 static void 6354 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6355 { 6356 struct ifnet *ifp; 6357 u32 link; 6358 6359 ifp = sc->bce_ifp; 6360 BCE_LOCK_ASSERT(sc); 6361 6362 ifmr->ifm_status = IFM_AVALID; 6363 ifmr->ifm_active = IFM_ETHER; 6364 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6365 /* XXX Handle heart beat status? */ 6366 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6367 ifmr->ifm_status |= IFM_ACTIVE; 6368 else { 6369 ifmr->ifm_active |= IFM_NONE; 6370 ifp->if_baudrate = 0; 6371 return; 6372 } 6373 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6374 case BCE_LINK_STATUS_10HALF: 6375 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6376 ifp->if_baudrate = IF_Mbps(10UL); 6377 break; 6378 case BCE_LINK_STATUS_10FULL: 6379 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6380 ifp->if_baudrate = IF_Mbps(10UL); 6381 break; 6382 case BCE_LINK_STATUS_100HALF: 6383 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6384 ifp->if_baudrate = IF_Mbps(100UL); 6385 break; 6386 case BCE_LINK_STATUS_100FULL: 6387 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6388 ifp->if_baudrate = IF_Mbps(100UL); 6389 break; 6390 case BCE_LINK_STATUS_1000HALF: 6391 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6392 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6393 else 6394 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6395 ifp->if_baudrate = IF_Mbps(1000UL); 6396 break; 6397 case BCE_LINK_STATUS_1000FULL: 6398 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6399 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6400 else 6401 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6402 ifp->if_baudrate = IF_Mbps(1000UL); 6403 break; 6404 case BCE_LINK_STATUS_2500HALF: 6405 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6406 ifmr->ifm_active |= IFM_NONE; 6407 return; 6408 } else 6409 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6410 ifp->if_baudrate = IF_Mbps(2500UL); 6411 break; 6412 case BCE_LINK_STATUS_2500FULL: 6413 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6414 ifmr->ifm_active |= IFM_NONE; 6415 return; 6416 } else 6417 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6418 ifp->if_baudrate = IF_Mbps(2500UL); 6419 break; 6420 default: 6421 ifmr->ifm_active |= IFM_NONE; 6422 return; 6423 } 6424 6425 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6426 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6427 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6428 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6429 } 6430 6431 6432 /****************************************************************************/ 6433 /* Reports current media status. */ 6434 /* */ 6435 /* Returns: */ 6436 /* Nothing. */ 6437 /****************************************************************************/ 6438 static void 6439 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6440 { 6441 struct bce_softc *sc = ifp->if_softc; 6442 struct mii_data *mii; 6443 6444 DBENTER(BCE_VERBOSE_PHY); 6445 6446 BCE_LOCK(sc); 6447 6448 if ((ifp->if_flags & IFF_UP) == 0) { 6449 BCE_UNLOCK(sc); 6450 return; 6451 } 6452 6453 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6454 bce_ifmedia_sts_rphy(sc, ifmr); 6455 else { 6456 mii = device_get_softc(sc->bce_miibus); 6457 mii_pollstat(mii); 6458 ifmr->ifm_active = mii->mii_media_active; 6459 ifmr->ifm_status = mii->mii_media_status; 6460 } 6461 6462 BCE_UNLOCK(sc); 6463 6464 DBEXIT(BCE_VERBOSE_PHY); 6465 } 6466 6467 6468 /****************************************************************************/ 6469 /* Handles PHY generated interrupt events. */ 6470 /* */ 6471 /* Returns: */ 6472 /* Nothing. */ 6473 /****************************************************************************/ 6474 static void 6475 bce_phy_intr(struct bce_softc *sc) 6476 { 6477 u32 new_link_state, old_link_state; 6478 6479 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6480 6481 DBRUN(sc->phy_interrupts++); 6482 6483 new_link_state = sc->status_block->status_attn_bits & 6484 STATUS_ATTN_BITS_LINK_STATE; 6485 old_link_state = sc->status_block->status_attn_bits_ack & 6486 STATUS_ATTN_BITS_LINK_STATE; 6487 6488 /* Handle any changes if the link state has changed. */ 6489 if (new_link_state != old_link_state) { 6490 6491 /* Update the status_attn_bits_ack field. */ 6492 if (new_link_state) { 6493 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6494 STATUS_ATTN_BITS_LINK_STATE); 6495 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6496 __FUNCTION__); 6497 } else { 6498 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6499 STATUS_ATTN_BITS_LINK_STATE); 6500 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6501 __FUNCTION__); 6502 } 6503 6504 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6505 if (new_link_state) { 6506 if (bootverbose) 6507 if_printf(sc->bce_ifp, "link UP\n"); 6508 if_link_state_change(sc->bce_ifp, 6509 LINK_STATE_UP); 6510 } else { 6511 if (bootverbose) 6512 if_printf(sc->bce_ifp, "link DOWN\n"); 6513 if_link_state_change(sc->bce_ifp, 6514 LINK_STATE_DOWN); 6515 } 6516 } 6517 /* 6518 * Assume link is down and allow 6519 * tick routine to update the state 6520 * based on the actual media state. 6521 */ 6522 sc->bce_link_up = FALSE; 6523 callout_stop(&sc->bce_tick_callout); 6524 bce_tick(sc); 6525 } 6526 6527 /* Acknowledge the link change interrupt. */ 6528 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6529 6530 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6531 } 6532 6533 6534 /****************************************************************************/ 6535 /* Reads the receive consumer value from the status block (skipping over */ 6536 /* chain page pointer if necessary). */ 6537 /* */ 6538 /* Returns: */ 6539 /* hw_cons */ 6540 /****************************************************************************/ 6541 static inline u16 6542 bce_get_hw_rx_cons(struct bce_softc *sc) 6543 { 6544 u16 hw_cons; 6545 6546 rmb(); 6547 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6548 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6549 hw_cons++; 6550 6551 return hw_cons; 6552 } 6553 6554 /****************************************************************************/ 6555 /* Handles received frame interrupt events. */ 6556 /* */ 6557 /* Returns: */ 6558 /* Nothing. */ 6559 /****************************************************************************/ 6560 static void 6561 bce_rx_intr(struct bce_softc *sc) 6562 { 6563 struct ifnet *ifp = sc->bce_ifp; 6564 struct l2_fhdr *l2fhdr; 6565 struct ether_vlan_header *vh; 6566 unsigned int pkt_len; 6567 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6568 u32 status; 6569 unsigned int rem_len; 6570 u16 sw_pg_cons, sw_pg_cons_idx; 6571 6572 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6573 DBRUN(sc->interrupts_rx++); 6574 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6575 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6576 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6577 6578 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6579 for (int i = 0; i < sc->rx_pages; i++) 6580 bus_dmamap_sync(sc->rx_bd_chain_tag, 6581 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6582 6583 /* Prepare the page chain pages to be accessed by the host CPU. */ 6584 if (bce_hdr_split == TRUE) { 6585 for (int i = 0; i < sc->pg_pages; i++) 6586 bus_dmamap_sync(sc->pg_bd_chain_tag, 6587 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6588 } 6589 6590 /* Get the hardware's view of the RX consumer index. */ 6591 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6592 6593 /* Get working copies of the driver's view of the consumer indices. */ 6594 sw_rx_cons = sc->rx_cons; 6595 sw_pg_cons = sc->pg_cons; 6596 6597 /* Update some debug statistics counters */ 6598 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6599 sc->rx_low_watermark = sc->free_rx_bd); 6600 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6601 sc->rx_empty_count++); 6602 6603 /* Scan through the receive chain as long as there is work to do */ 6604 /* ToDo: Consider setting a limit on the number of packets processed. */ 6605 rmb(); 6606 while (sw_rx_cons != hw_rx_cons) { 6607 struct mbuf *m0; 6608 6609 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6610 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6611 6612 /* Unmap the mbuf from DMA space. */ 6613 bus_dmamap_sync(sc->rx_mbuf_tag, 6614 sc->rx_mbuf_map[sw_rx_cons_idx], 6615 BUS_DMASYNC_POSTREAD); 6616 bus_dmamap_unload(sc->rx_mbuf_tag, 6617 sc->rx_mbuf_map[sw_rx_cons_idx]); 6618 6619 /* Remove the mbuf from the RX chain. */ 6620 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6621 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6622 DBRUN(sc->debug_rx_mbuf_alloc--); 6623 sc->free_rx_bd++; 6624 6625 if(m0 == NULL) { 6626 DBPRINT(sc, BCE_EXTREME_RECV, 6627 "%s(): Oops! Empty mbuf pointer " 6628 "found in sc->rx_mbuf_ptr[0x%04X]!\n", 6629 __FUNCTION__, sw_rx_cons_idx); 6630 goto bce_rx_int_next_rx; 6631 } 6632 6633 /* 6634 * Frames received on the NetXteme II are prepended 6635 * with an l2_fhdr structure which provides status 6636 * information about the received frame (including 6637 * VLAN tags and checksum info). The frames are 6638 * also automatically adjusted to word align the IP 6639 * header (i.e. two null bytes are inserted before 6640 * the Ethernet header). As a result the data 6641 * DMA'd by the controller into the mbuf looks 6642 * like this: 6643 * 6644 * +---------+-----+---------------------+-----+ 6645 * | l2_fhdr | pad | packet data | FCS | 6646 * +---------+-----+---------------------+-----+ 6647 * 6648 * The l2_fhdr needs to be checked and skipped and 6649 * the FCS needs to be stripped before sending the 6650 * packet up the stack. 6651 */ 6652 l2fhdr = mtod(m0, struct l2_fhdr *); 6653 6654 /* Get the packet data + FCS length and the status. */ 6655 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6656 status = l2fhdr->l2_fhdr_status; 6657 6658 /* 6659 * Skip over the l2_fhdr and pad, resulting in the 6660 * following data in the mbuf: 6661 * +---------------------+-----+ 6662 * | packet data | FCS | 6663 * +---------------------+-----+ 6664 */ 6665 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6666 6667 /* 6668 * When split header mode is used, an ethernet frame 6669 * may be split across the receive chain and the 6670 * page chain. If that occurs an mbuf cluster must be 6671 * reassembled from the individual mbuf pieces. 6672 */ 6673 if (bce_hdr_split == TRUE) { 6674 /* 6675 * Check whether the received frame fits in a single 6676 * mbuf or not (i.e. packet data + FCS <= 6677 * sc->rx_bd_mbuf_data_len bytes). 6678 */ 6679 if (pkt_len > m0->m_len) { 6680 /* 6681 * The received frame is larger than a single mbuf. 6682 * If the frame was a TCP frame then only the TCP 6683 * header is placed in the mbuf, the remaining 6684 * payload (including FCS) is placed in the page 6685 * chain, the SPLIT flag is set, and the header 6686 * length is placed in the IP checksum field. 6687 * If the frame is not a TCP frame then the mbuf 6688 * is filled and the remaining bytes are placed 6689 * in the page chain. 6690 */ 6691 6692 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6693 "packet.\n", __FUNCTION__); 6694 DBRUN(sc->split_header_frames_rcvd++); 6695 6696 /* 6697 * When the page chain is enabled and the TCP 6698 * header has been split from the TCP payload, 6699 * the ip_xsum structure will reflect the length 6700 * of the TCP header, not the IP checksum. Set 6701 * the packet length of the mbuf accordingly. 6702 */ 6703 if (status & L2_FHDR_STATUS_SPLIT) { 6704 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6705 DBRUN(sc->split_header_tcp_frames_rcvd++); 6706 } 6707 6708 rem_len = pkt_len - m0->m_len; 6709 6710 /* Pull mbufs off the page chain for any remaining data. */ 6711 while (rem_len > 0) { 6712 struct mbuf *m_pg; 6713 6714 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6715 6716 /* Remove the mbuf from the page chain. */ 6717 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6718 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6719 DBRUN(sc->debug_pg_mbuf_alloc--); 6720 sc->free_pg_bd++; 6721 6722 /* Unmap the page chain mbuf from DMA space. */ 6723 bus_dmamap_sync(sc->pg_mbuf_tag, 6724 sc->pg_mbuf_map[sw_pg_cons_idx], 6725 BUS_DMASYNC_POSTREAD); 6726 bus_dmamap_unload(sc->pg_mbuf_tag, 6727 sc->pg_mbuf_map[sw_pg_cons_idx]); 6728 6729 /* Adjust the mbuf length. */ 6730 if (rem_len < m_pg->m_len) { 6731 /* The mbuf chain is complete. */ 6732 m_pg->m_len = rem_len; 6733 rem_len = 0; 6734 } else { 6735 /* More packet data is waiting. */ 6736 rem_len -= m_pg->m_len; 6737 } 6738 6739 /* Concatenate the mbuf cluster to the mbuf. */ 6740 m_cat(m0, m_pg); 6741 6742 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6743 } 6744 6745 /* Set the total packet length. */ 6746 m0->m_pkthdr.len = pkt_len; 6747 6748 } else { 6749 /* 6750 * The received packet is small and fits in a 6751 * single mbuf (i.e. the l2_fhdr + pad + packet + 6752 * FCS <= MHLEN). In other words, the packet is 6753 * 154 bytes or less in size. 6754 */ 6755 6756 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6757 "packet.\n", __FUNCTION__); 6758 6759 /* Set the total packet length. */ 6760 m0->m_pkthdr.len = m0->m_len = pkt_len; 6761 } 6762 } else 6763 /* Set the total packet length. */ 6764 m0->m_pkthdr.len = m0->m_len = pkt_len; 6765 6766 /* Remove the trailing Ethernet FCS. */ 6767 m_adj(m0, -ETHER_CRC_LEN); 6768 6769 /* Check that the resulting mbuf chain is valid. */ 6770 DBRUN(m_sanity(m0, FALSE)); 6771 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6772 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6773 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6774 m_print(m0, 128)); 6775 6776 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6777 sc->l2fhdr_error_sim_count++; 6778 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6779 6780 /* Check the received frame for errors. */ 6781 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6782 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6783 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6784 6785 /* Log the error and release the mbuf. */ 6786 ifp->if_ierrors++; 6787 sc->l2fhdr_error_count++; 6788 6789 m_freem(m0); 6790 m0 = NULL; 6791 goto bce_rx_int_next_rx; 6792 } 6793 6794 /* Send the packet to the appropriate interface. */ 6795 m0->m_pkthdr.rcvif = ifp; 6796 6797 /* Assume no hardware checksum. */ 6798 m0->m_pkthdr.csum_flags = 0; 6799 6800 /* Validate the checksum if offload enabled. */ 6801 if (ifp->if_capenable & IFCAP_RXCSUM) { 6802 6803 /* Check for an IP datagram. */ 6804 if (!(status & L2_FHDR_STATUS_SPLIT) && 6805 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6806 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6807 DBRUN(sc->csum_offload_ip++); 6808 /* Check if the IP checksum is valid. */ 6809 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6810 m0->m_pkthdr.csum_flags |= 6811 CSUM_IP_VALID; 6812 } 6813 6814 /* Check for a valid TCP/UDP frame. */ 6815 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6816 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6817 6818 /* Check for a good TCP/UDP checksum. */ 6819 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6820 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6821 DBRUN(sc->csum_offload_tcp_udp++); 6822 m0->m_pkthdr.csum_data = 6823 l2fhdr->l2_fhdr_tcp_udp_xsum; 6824 m0->m_pkthdr.csum_flags |= 6825 (CSUM_DATA_VALID 6826 | CSUM_PSEUDO_HDR); 6827 } 6828 } 6829 } 6830 6831 /* Attach the VLAN tag. */ 6832 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6833 DBRUN(sc->vlan_tagged_frames_rcvd++); 6834 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6835 DBRUN(sc->vlan_tagged_frames_stripped++); 6836 #if __FreeBSD_version < 700000 6837 VLAN_INPUT_TAG(ifp, m0, 6838 l2fhdr->l2_fhdr_vlan_tag, continue); 6839 #else 6840 m0->m_pkthdr.ether_vtag = 6841 l2fhdr->l2_fhdr_vlan_tag; 6842 m0->m_flags |= M_VLANTAG; 6843 #endif 6844 } else { 6845 /* 6846 * bce(4) controllers can't disable VLAN 6847 * tag stripping if management firmware 6848 * (ASF/IPMI/UMP) is running. So we always 6849 * strip VLAN tag and manually reconstruct 6850 * the VLAN frame by appending stripped 6851 * VLAN tag in driver if VLAN tag stripping 6852 * was disabled. 6853 * 6854 * TODO: LLC SNAP handling. 6855 */ 6856 bcopy(mtod(m0, uint8_t *), 6857 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6858 ETHER_ADDR_LEN * 2); 6859 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6860 vh = mtod(m0, struct ether_vlan_header *); 6861 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6862 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6863 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6864 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6865 } 6866 } 6867 6868 /* Increment received packet statistics. */ 6869 ifp->if_ipackets++; 6870 6871 bce_rx_int_next_rx: 6872 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6873 6874 /* If we have a packet, pass it up the stack */ 6875 if (m0) { 6876 /* Make sure we don't lose our place when we release the lock. */ 6877 sc->rx_cons = sw_rx_cons; 6878 sc->pg_cons = sw_pg_cons; 6879 6880 BCE_UNLOCK(sc); 6881 (*ifp->if_input)(ifp, m0); 6882 BCE_LOCK(sc); 6883 6884 /* Recover our place. */ 6885 sw_rx_cons = sc->rx_cons; 6886 sw_pg_cons = sc->pg_cons; 6887 } 6888 6889 /* Refresh hw_cons to see if there's new work */ 6890 if (sw_rx_cons == hw_rx_cons) 6891 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6892 } 6893 6894 /* No new packets. Refill the page chain. */ 6895 if (bce_hdr_split == TRUE) { 6896 sc->pg_cons = sw_pg_cons; 6897 bce_fill_pg_chain(sc); 6898 } 6899 6900 /* No new packets. Refill the RX chain. */ 6901 sc->rx_cons = sw_rx_cons; 6902 bce_fill_rx_chain(sc); 6903 6904 /* Prepare the page chain pages to be accessed by the NIC. */ 6905 for (int i = 0; i < sc->rx_pages; i++) 6906 bus_dmamap_sync(sc->rx_bd_chain_tag, 6907 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6908 6909 if (bce_hdr_split == TRUE) { 6910 for (int i = 0; i < sc->pg_pages; i++) 6911 bus_dmamap_sync(sc->pg_bd_chain_tag, 6912 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6913 } 6914 6915 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6916 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6917 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6918 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6919 } 6920 6921 6922 /****************************************************************************/ 6923 /* Reads the transmit consumer value from the status block (skipping over */ 6924 /* chain page pointer if necessary). */ 6925 /* */ 6926 /* Returns: */ 6927 /* hw_cons */ 6928 /****************************************************************************/ 6929 static inline u16 6930 bce_get_hw_tx_cons(struct bce_softc *sc) 6931 { 6932 u16 hw_cons; 6933 6934 mb(); 6935 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6936 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6937 hw_cons++; 6938 6939 return hw_cons; 6940 } 6941 6942 6943 /****************************************************************************/ 6944 /* Handles transmit completion interrupt events. */ 6945 /* */ 6946 /* Returns: */ 6947 /* Nothing. */ 6948 /****************************************************************************/ 6949 static void 6950 bce_tx_intr(struct bce_softc *sc) 6951 { 6952 struct ifnet *ifp = sc->bce_ifp; 6953 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6954 6955 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6956 DBRUN(sc->interrupts_tx++); 6957 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6958 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6959 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6960 6961 BCE_LOCK_ASSERT(sc); 6962 6963 /* Get the hardware's view of the TX consumer index. */ 6964 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6965 sw_tx_cons = sc->tx_cons; 6966 6967 /* Prevent speculative reads of the status block. */ 6968 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6969 BUS_SPACE_BARRIER_READ); 6970 6971 /* Cycle through any completed TX chain page entries. */ 6972 while (sw_tx_cons != hw_tx_cons) { 6973 #ifdef BCE_DEBUG 6974 struct tx_bd *txbd = NULL; 6975 #endif 6976 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6977 6978 DBPRINT(sc, BCE_INFO_SEND, 6979 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6980 "sw_tx_chain_cons = 0x%04X\n", 6981 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6982 6983 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6984 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6985 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6986 (int) MAX_TX_BD_ALLOC); 6987 bce_breakpoint(sc)); 6988 6989 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6990 [TX_IDX(sw_tx_chain_cons)]); 6991 6992 DBRUNIF((txbd == NULL), 6993 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6994 __FILE__, __LINE__, sw_tx_chain_cons); 6995 bce_breakpoint(sc)); 6996 6997 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6998 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6999 7000 /* 7001 * Free the associated mbuf. Remember 7002 * that only the last tx_bd of a packet 7003 * has an mbuf pointer and DMA map. 7004 */ 7005 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 7006 7007 /* Validate that this is the last tx_bd. */ 7008 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 7009 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 7010 "txmbuf == NULL!\n", __FILE__, __LINE__); 7011 bce_breakpoint(sc)); 7012 7013 DBRUNMSG(BCE_INFO_SEND, 7014 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 7015 "from tx_bd[0x%04X]\n", __FUNCTION__, 7016 sw_tx_chain_cons)); 7017 7018 /* Unmap the mbuf. */ 7019 bus_dmamap_unload(sc->tx_mbuf_tag, 7020 sc->tx_mbuf_map[sw_tx_chain_cons]); 7021 7022 /* Free the mbuf. */ 7023 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 7024 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 7025 DBRUN(sc->debug_tx_mbuf_alloc--); 7026 7027 ifp->if_opackets++; 7028 } 7029 7030 sc->used_tx_bd--; 7031 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 7032 7033 /* Refresh hw_cons to see if there's new work. */ 7034 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 7035 7036 /* Prevent speculative reads of the status block. */ 7037 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7038 BUS_SPACE_BARRIER_READ); 7039 } 7040 7041 /* Clear the TX timeout timer. */ 7042 sc->watchdog_timer = 0; 7043 7044 /* Clear the tx hardware queue full flag. */ 7045 if (sc->used_tx_bd < sc->max_tx_bd) { 7046 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 7047 DBPRINT(sc, BCE_INFO_SEND, 7048 "%s(): Open TX chain! %d/%d (used/total)\n", 7049 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 7050 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7051 } 7052 7053 sc->tx_cons = sw_tx_cons; 7054 7055 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 7056 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 7057 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 7058 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 7059 } 7060 7061 7062 /****************************************************************************/ 7063 /* Disables interrupt generation. */ 7064 /* */ 7065 /* Returns: */ 7066 /* Nothing. */ 7067 /****************************************************************************/ 7068 static void 7069 bce_disable_intr(struct bce_softc *sc) 7070 { 7071 DBENTER(BCE_VERBOSE_INTR); 7072 7073 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7074 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 7075 7076 DBEXIT(BCE_VERBOSE_INTR); 7077 } 7078 7079 7080 /****************************************************************************/ 7081 /* Enables interrupt generation. */ 7082 /* */ 7083 /* Returns: */ 7084 /* Nothing. */ 7085 /****************************************************************************/ 7086 static void 7087 bce_enable_intr(struct bce_softc *sc, int coal_now) 7088 { 7089 DBENTER(BCE_VERBOSE_INTR); 7090 7091 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7092 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 7093 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 7094 7095 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7096 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 7097 7098 /* Force an immediate interrupt (whether there is new data or not). */ 7099 if (coal_now) 7100 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 7101 7102 DBEXIT(BCE_VERBOSE_INTR); 7103 } 7104 7105 7106 /****************************************************************************/ 7107 /* Handles controller initialization. */ 7108 /* */ 7109 /* Returns: */ 7110 /* Nothing. */ 7111 /****************************************************************************/ 7112 static void 7113 bce_init_locked(struct bce_softc *sc) 7114 { 7115 struct ifnet *ifp; 7116 u32 ether_mtu = 0; 7117 7118 DBENTER(BCE_VERBOSE_RESET); 7119 7120 BCE_LOCK_ASSERT(sc); 7121 7122 ifp = sc->bce_ifp; 7123 7124 /* Check if the driver is still running and bail out if it is. */ 7125 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7126 goto bce_init_locked_exit; 7127 7128 bce_stop(sc); 7129 7130 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 7131 BCE_PRINTF("%s(%d): Controller reset failed!\n", 7132 __FILE__, __LINE__); 7133 goto bce_init_locked_exit; 7134 } 7135 7136 if (bce_chipinit(sc)) { 7137 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 7138 __FILE__, __LINE__); 7139 goto bce_init_locked_exit; 7140 } 7141 7142 if (bce_blockinit(sc)) { 7143 BCE_PRINTF("%s(%d): Block initialization failed!\n", 7144 __FILE__, __LINE__); 7145 goto bce_init_locked_exit; 7146 } 7147 7148 /* Load our MAC address. */ 7149 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 7150 bce_set_mac_addr(sc); 7151 7152 if (bce_hdr_split == FALSE) 7153 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7154 /* 7155 * Calculate and program the hardware Ethernet MTU 7156 * size. Be generous on the receive if we have room 7157 * and allowed by the user. 7158 */ 7159 if (bce_strict_rx_mtu == TRUE) 7160 ether_mtu = ifp->if_mtu; 7161 else { 7162 if (bce_hdr_split == TRUE) { 7163 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + 7164 sc->pg_bd_mbuf_alloc_size)) 7165 ether_mtu = sc->rx_bd_mbuf_data_len + 7166 sc->pg_bd_mbuf_alloc_size; 7167 else 7168 ether_mtu = ifp->if_mtu; 7169 } else { 7170 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 7171 ether_mtu = sc->rx_bd_mbuf_data_len; 7172 else 7173 ether_mtu = ifp->if_mtu; 7174 } 7175 } 7176 7177 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7178 7179 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7180 __FUNCTION__, ether_mtu); 7181 7182 /* Program the mtu, enabling jumbo frame support if necessary. */ 7183 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7184 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7185 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7186 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7187 else 7188 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7189 7190 /* Program appropriate promiscuous/multicast filtering. */ 7191 bce_set_rx_mode(sc); 7192 7193 if (bce_hdr_split == TRUE) { 7194 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 7195 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 7196 7197 /* Init page buffer descriptor chain. */ 7198 bce_init_pg_chain(sc); 7199 } 7200 7201 /* Init RX buffer descriptor chain. */ 7202 bce_init_rx_chain(sc); 7203 7204 /* Init TX buffer descriptor chain. */ 7205 bce_init_tx_chain(sc); 7206 7207 /* Enable host interrupts. */ 7208 bce_enable_intr(sc, 1); 7209 7210 bce_ifmedia_upd_locked(ifp); 7211 7212 /* Let the OS know the driver is up and running. */ 7213 ifp->if_drv_flags |= IFF_DRV_RUNNING; 7214 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7215 7216 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7217 7218 bce_init_locked_exit: 7219 DBEXIT(BCE_VERBOSE_RESET); 7220 } 7221 7222 7223 /****************************************************************************/ 7224 /* Initialize the controller just enough so that any management firmware */ 7225 /* running on the device will continue to operate correctly. */ 7226 /* */ 7227 /* Returns: */ 7228 /* Nothing. */ 7229 /****************************************************************************/ 7230 static void 7231 bce_mgmt_init_locked(struct bce_softc *sc) 7232 { 7233 struct ifnet *ifp; 7234 7235 DBENTER(BCE_VERBOSE_RESET); 7236 7237 BCE_LOCK_ASSERT(sc); 7238 7239 /* Bail out if management firmware is not running. */ 7240 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7241 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7242 "No management firmware running...\n"); 7243 goto bce_mgmt_init_locked_exit; 7244 } 7245 7246 ifp = sc->bce_ifp; 7247 7248 /* Enable all critical blocks in the MAC. */ 7249 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7250 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7251 DELAY(20); 7252 7253 bce_ifmedia_upd_locked(ifp); 7254 7255 bce_mgmt_init_locked_exit: 7256 DBEXIT(BCE_VERBOSE_RESET); 7257 } 7258 7259 7260 /****************************************************************************/ 7261 /* Handles controller initialization when called from an unlocked routine. */ 7262 /* */ 7263 /* Returns: */ 7264 /* Nothing. */ 7265 /****************************************************************************/ 7266 static void 7267 bce_init(void *xsc) 7268 { 7269 struct bce_softc *sc = xsc; 7270 7271 DBENTER(BCE_VERBOSE_RESET); 7272 7273 BCE_LOCK(sc); 7274 bce_init_locked(sc); 7275 BCE_UNLOCK(sc); 7276 7277 DBEXIT(BCE_VERBOSE_RESET); 7278 } 7279 7280 7281 /****************************************************************************/ 7282 /* Modifies an mbuf for TSO on the hardware. */ 7283 /* */ 7284 /* Returns: */ 7285 /* Pointer to a modified mbuf. */ 7286 /****************************************************************************/ 7287 static struct mbuf * 7288 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7289 { 7290 struct mbuf *m; 7291 struct ether_header *eh; 7292 struct ip *ip; 7293 struct tcphdr *th; 7294 u16 etype; 7295 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7296 7297 DBRUN(sc->tso_frames_requested++); 7298 7299 /* Controller may modify mbuf chains. */ 7300 if (M_WRITABLE(*m_head) == 0) { 7301 m = m_dup(*m_head, M_DONTWAIT); 7302 m_freem(*m_head); 7303 if (m == NULL) { 7304 sc->mbuf_alloc_failed_count++; 7305 *m_head = NULL; 7306 return (NULL); 7307 } 7308 *m_head = m; 7309 } 7310 7311 /* 7312 * For TSO the controller needs two pieces of info, 7313 * the MSS and the IP+TCP options length. 7314 */ 7315 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7316 if (m == NULL) { 7317 *m_head = NULL; 7318 return (NULL); 7319 } 7320 eh = mtod(m, struct ether_header *); 7321 etype = ntohs(eh->ether_type); 7322 7323 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7324 switch (etype) { 7325 case ETHERTYPE_IP: 7326 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7327 /* TSO only supported for TCP protocol. */ 7328 if (ip->ip_p != IPPROTO_TCP) { 7329 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7330 __FILE__, __LINE__); 7331 m_freem(*m_head); 7332 *m_head = NULL; 7333 return (NULL); 7334 } 7335 7336 /* Get IP header length in bytes (min 20) */ 7337 ip_hlen = ip->ip_hl << 2; 7338 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7339 sizeof(struct tcphdr)); 7340 if (m == NULL) { 7341 *m_head = NULL; 7342 return (NULL); 7343 } 7344 7345 /* Get the TCP header length in bytes (min 20) */ 7346 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7347 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7348 tcp_hlen = (th->th_off << 2); 7349 7350 /* Make sure all IP/TCP options live in the same buffer. */ 7351 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7352 tcp_hlen); 7353 if (m == NULL) { 7354 *m_head = NULL; 7355 return (NULL); 7356 } 7357 7358 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7359 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7360 ip_len = ip->ip_len; 7361 ip->ip_len = 0; 7362 ip->ip_sum = 0; 7363 break; 7364 case ETHERTYPE_IPV6: 7365 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7366 __FILE__, __LINE__); 7367 m_freem(*m_head); 7368 *m_head = NULL; 7369 return (NULL); 7370 /* NOT REACHED */ 7371 default: 7372 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7373 __FILE__, __LINE__); 7374 m_freem(*m_head); 7375 *m_head = NULL; 7376 return (NULL); 7377 } 7378 7379 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7380 7381 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7382 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7383 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7384 tcp_hlen, ip_len); 7385 7386 /* Set the LSO flag in the TX BD */ 7387 *flags |= TX_BD_FLAGS_SW_LSO; 7388 7389 /* Set the length of IP + TCP options (in 32 bit words) */ 7390 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7391 sizeof(struct tcphdr)) >> 2) << 8); 7392 7393 DBRUN(sc->tso_frames_completed++); 7394 return (*m_head); 7395 } 7396 7397 7398 /****************************************************************************/ 7399 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7400 /* memory visible to the controller. */ 7401 /* */ 7402 /* Returns: */ 7403 /* 0 for success, positive value for failure. */ 7404 /* Modified: */ 7405 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7406 /****************************************************************************/ 7407 static int 7408 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7409 { 7410 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7411 bus_dmamap_t map; 7412 struct tx_bd *txbd = NULL; 7413 struct mbuf *m0; 7414 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7415 u32 prod_bseq; 7416 7417 #ifdef BCE_DEBUG 7418 u16 debug_prod; 7419 #endif 7420 7421 int i, error, nsegs, rc = 0; 7422 7423 DBENTER(BCE_VERBOSE_SEND); 7424 7425 /* Make sure we have room in the TX chain. */ 7426 if (sc->used_tx_bd >= sc->max_tx_bd) 7427 goto bce_tx_encap_exit; 7428 7429 /* Transfer any checksum offload flags to the bd. */ 7430 m0 = *m_head; 7431 if (m0->m_pkthdr.csum_flags) { 7432 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7433 m0 = bce_tso_setup(sc, m_head, &flags); 7434 if (m0 == NULL) { 7435 DBRUN(sc->tso_frames_failed++); 7436 goto bce_tx_encap_exit; 7437 } 7438 mss = htole16(m0->m_pkthdr.tso_segsz); 7439 } else { 7440 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7441 flags |= TX_BD_FLAGS_IP_CKSUM; 7442 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7443 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7444 } 7445 } 7446 7447 /* Transfer any VLAN tags to the bd. */ 7448 if (m0->m_flags & M_VLANTAG) { 7449 flags |= TX_BD_FLAGS_VLAN_TAG; 7450 vlan_tag = m0->m_pkthdr.ether_vtag; 7451 } 7452 7453 /* Map the mbuf into DMAable memory. */ 7454 prod = sc->tx_prod; 7455 chain_prod = TX_CHAIN_IDX(prod); 7456 map = sc->tx_mbuf_map[chain_prod]; 7457 7458 /* Map the mbuf into our DMA address space. */ 7459 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7460 segs, &nsegs, BUS_DMA_NOWAIT); 7461 7462 /* Check if the DMA mapping was successful */ 7463 if (error == EFBIG) { 7464 sc->mbuf_frag_count++; 7465 7466 /* Try to defrag the mbuf. */ 7467 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 7468 if (m0 == NULL) { 7469 /* Defrag was unsuccessful */ 7470 m_freem(*m_head); 7471 *m_head = NULL; 7472 sc->mbuf_alloc_failed_count++; 7473 rc = ENOBUFS; 7474 goto bce_tx_encap_exit; 7475 } 7476 7477 /* Defrag was successful, try mapping again */ 7478 *m_head = m0; 7479 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7480 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7481 7482 /* Still getting an error after a defrag. */ 7483 if (error == ENOMEM) { 7484 /* Insufficient DMA buffers available. */ 7485 sc->dma_map_addr_tx_failed_count++; 7486 rc = error; 7487 goto bce_tx_encap_exit; 7488 } else if (error != 0) { 7489 /* Release it and return an error. */ 7490 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7491 "TX chain!\n", __FILE__, __LINE__); 7492 m_freem(m0); 7493 *m_head = NULL; 7494 sc->dma_map_addr_tx_failed_count++; 7495 rc = ENOBUFS; 7496 goto bce_tx_encap_exit; 7497 } 7498 } else if (error == ENOMEM) { 7499 /* Insufficient DMA buffers available. */ 7500 sc->dma_map_addr_tx_failed_count++; 7501 rc = error; 7502 goto bce_tx_encap_exit; 7503 } else if (error != 0) { 7504 m_freem(m0); 7505 *m_head = NULL; 7506 sc->dma_map_addr_tx_failed_count++; 7507 rc = error; 7508 goto bce_tx_encap_exit; 7509 } 7510 7511 /* Make sure there's room in the chain */ 7512 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7513 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7514 rc = ENOBUFS; 7515 goto bce_tx_encap_exit; 7516 } 7517 7518 /* prod points to an empty tx_bd at this point. */ 7519 prod_bseq = sc->tx_prod_bseq; 7520 7521 #ifdef BCE_DEBUG 7522 debug_prod = chain_prod; 7523 #endif 7524 7525 DBPRINT(sc, BCE_INFO_SEND, 7526 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7527 "prod_bseq = 0x%08X\n", 7528 __FUNCTION__, prod, chain_prod, prod_bseq); 7529 7530 /* 7531 * Cycle through each mbuf segment that makes up 7532 * the outgoing frame, gathering the mapping info 7533 * for that segment and creating a tx_bd for 7534 * the mbuf. 7535 */ 7536 for (i = 0; i < nsegs ; i++) { 7537 7538 chain_prod = TX_CHAIN_IDX(prod); 7539 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7540 [TX_IDX(chain_prod)]; 7541 7542 txbd->tx_bd_haddr_lo = 7543 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7544 txbd->tx_bd_haddr_hi = 7545 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7546 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7547 htole16(segs[i].ds_len); 7548 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7549 txbd->tx_bd_flags = htole16(flags); 7550 prod_bseq += segs[i].ds_len; 7551 if (i == 0) 7552 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7553 prod = NEXT_TX_BD(prod); 7554 } 7555 7556 /* Set the END flag on the last TX buffer descriptor. */ 7557 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7558 7559 DBRUNMSG(BCE_EXTREME_SEND, 7560 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7561 7562 /* 7563 * Ensure that the mbuf pointer for this transmission 7564 * is placed at the array index of the last 7565 * descriptor in this chain. This is done 7566 * because a single map is used for all 7567 * segments of the mbuf and we don't want to 7568 * unload the map before all of the segments 7569 * have been freed. 7570 */ 7571 sc->tx_mbuf_ptr[chain_prod] = m0; 7572 sc->used_tx_bd += nsegs; 7573 7574 /* Update some debug statistic counters */ 7575 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7576 sc->tx_hi_watermark = sc->used_tx_bd); 7577 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7578 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7579 7580 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7581 7582 /* prod points to the next free tx_bd at this point. */ 7583 sc->tx_prod = prod; 7584 sc->tx_prod_bseq = prod_bseq; 7585 7586 /* Tell the chip about the waiting TX frames. */ 7587 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7588 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7589 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7590 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7591 7592 bce_tx_encap_exit: 7593 DBEXIT(BCE_VERBOSE_SEND); 7594 return(rc); 7595 } 7596 7597 7598 /****************************************************************************/ 7599 /* Main transmit routine when called from another routine with a lock. */ 7600 /* */ 7601 /* Returns: */ 7602 /* Nothing. */ 7603 /****************************************************************************/ 7604 static void 7605 bce_start_locked(struct ifnet *ifp) 7606 { 7607 struct bce_softc *sc = ifp->if_softc; 7608 struct mbuf *m_head = NULL; 7609 int count = 0; 7610 u16 tx_prod, tx_chain_prod; 7611 7612 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7613 7614 BCE_LOCK_ASSERT(sc); 7615 7616 /* prod points to the next free tx_bd. */ 7617 tx_prod = sc->tx_prod; 7618 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7619 7620 DBPRINT(sc, BCE_INFO_SEND, 7621 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7622 "tx_prod_bseq = 0x%08X\n", 7623 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7624 7625 /* If there's no link or the transmit queue is empty then just exit. */ 7626 if (sc->bce_link_up == FALSE) { 7627 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7628 __FUNCTION__); 7629 goto bce_start_locked_exit; 7630 } 7631 7632 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7633 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7634 __FUNCTION__); 7635 goto bce_start_locked_exit; 7636 } 7637 7638 /* 7639 * Keep adding entries while there is space in the ring. 7640 */ 7641 while (sc->used_tx_bd < sc->max_tx_bd) { 7642 7643 /* Check for any frames to send. */ 7644 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7645 7646 /* Stop when the transmit queue is empty. */ 7647 if (m_head == NULL) 7648 break; 7649 7650 /* 7651 * Pack the data into the transmit ring. If we 7652 * don't have room, place the mbuf back at the 7653 * head of the queue and set the OACTIVE flag 7654 * to wait for the NIC to drain the chain. 7655 */ 7656 if (bce_tx_encap(sc, &m_head)) { 7657 if (m_head != NULL) 7658 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7659 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7660 DBPRINT(sc, BCE_INFO_SEND, 7661 "TX chain is closed for business! Total " 7662 "tx_bd used = %d\n", sc->used_tx_bd); 7663 break; 7664 } 7665 7666 count++; 7667 7668 /* Send a copy of the frame to any BPF listeners. */ 7669 ETHER_BPF_MTAP(ifp, m_head); 7670 } 7671 7672 /* Exit if no packets were dequeued. */ 7673 if (count == 0) { 7674 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7675 "dequeued\n", __FUNCTION__); 7676 goto bce_start_locked_exit; 7677 } 7678 7679 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7680 "send queue.\n", __FUNCTION__, count); 7681 7682 /* Set the tx timeout. */ 7683 sc->watchdog_timer = BCE_TX_TIMEOUT; 7684 7685 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7686 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7687 7688 bce_start_locked_exit: 7689 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7690 return; 7691 } 7692 7693 7694 /****************************************************************************/ 7695 /* Main transmit routine when called from another routine without a lock. */ 7696 /* */ 7697 /* Returns: */ 7698 /* Nothing. */ 7699 /****************************************************************************/ 7700 static void 7701 bce_start(struct ifnet *ifp) 7702 { 7703 struct bce_softc *sc = ifp->if_softc; 7704 7705 DBENTER(BCE_VERBOSE_SEND); 7706 7707 BCE_LOCK(sc); 7708 bce_start_locked(ifp); 7709 BCE_UNLOCK(sc); 7710 7711 DBEXIT(BCE_VERBOSE_SEND); 7712 } 7713 7714 7715 /****************************************************************************/ 7716 /* Handles any IOCTL calls from the operating system. */ 7717 /* */ 7718 /* Returns: */ 7719 /* 0 for success, positive value for failure. */ 7720 /****************************************************************************/ 7721 static int 7722 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7723 { 7724 struct bce_softc *sc = ifp->if_softc; 7725 struct ifreq *ifr = (struct ifreq *) data; 7726 struct mii_data *mii; 7727 int mask, error = 0; 7728 7729 DBENTER(BCE_VERBOSE_MISC); 7730 7731 switch(command) { 7732 7733 /* Set the interface MTU. */ 7734 case SIOCSIFMTU: 7735 /* Check that the MTU setting is supported. */ 7736 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7737 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7738 error = EINVAL; 7739 break; 7740 } 7741 7742 DBPRINT(sc, BCE_INFO_MISC, 7743 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7744 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7745 7746 BCE_LOCK(sc); 7747 ifp->if_mtu = ifr->ifr_mtu; 7748 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7749 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7750 bce_init_locked(sc); 7751 } 7752 BCE_UNLOCK(sc); 7753 break; 7754 7755 /* Set interface flags. */ 7756 case SIOCSIFFLAGS: 7757 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7758 7759 BCE_LOCK(sc); 7760 7761 /* Check if the interface is up. */ 7762 if (ifp->if_flags & IFF_UP) { 7763 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7764 /* Change promiscuous/multicast flags as necessary. */ 7765 bce_set_rx_mode(sc); 7766 } else { 7767 /* Start the HW */ 7768 bce_init_locked(sc); 7769 } 7770 } else { 7771 /* The interface is down, check if driver is running. */ 7772 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7773 bce_stop(sc); 7774 7775 /* If MFW is running, restart the controller a bit. */ 7776 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7777 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7778 bce_chipinit(sc); 7779 bce_mgmt_init_locked(sc); 7780 } 7781 } 7782 } 7783 7784 BCE_UNLOCK(sc); 7785 break; 7786 7787 /* Add/Delete multicast address */ 7788 case SIOCADDMULTI: 7789 case SIOCDELMULTI: 7790 DBPRINT(sc, BCE_VERBOSE_MISC, 7791 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7792 7793 BCE_LOCK(sc); 7794 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7795 bce_set_rx_mode(sc); 7796 BCE_UNLOCK(sc); 7797 7798 break; 7799 7800 /* Set/Get Interface media */ 7801 case SIOCSIFMEDIA: 7802 case SIOCGIFMEDIA: 7803 DBPRINT(sc, BCE_VERBOSE_MISC, 7804 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7805 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7806 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7807 command); 7808 else { 7809 mii = device_get_softc(sc->bce_miibus); 7810 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7811 command); 7812 } 7813 break; 7814 7815 /* Set interface capability */ 7816 case SIOCSIFCAP: 7817 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7818 DBPRINT(sc, BCE_INFO_MISC, 7819 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7820 7821 /* Toggle the TX checksum capabilities enable flag. */ 7822 if (mask & IFCAP_TXCSUM && 7823 ifp->if_capabilities & IFCAP_TXCSUM) { 7824 ifp->if_capenable ^= IFCAP_TXCSUM; 7825 if (IFCAP_TXCSUM & ifp->if_capenable) 7826 ifp->if_hwassist |= BCE_IF_HWASSIST; 7827 else 7828 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7829 } 7830 7831 /* Toggle the RX checksum capabilities enable flag. */ 7832 if (mask & IFCAP_RXCSUM && 7833 ifp->if_capabilities & IFCAP_RXCSUM) 7834 ifp->if_capenable ^= IFCAP_RXCSUM; 7835 7836 /* Toggle the TSO capabilities enable flag. */ 7837 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7838 ifp->if_capabilities & IFCAP_TSO4) { 7839 ifp->if_capenable ^= IFCAP_TSO4; 7840 if (IFCAP_TSO4 & ifp->if_capenable) 7841 ifp->if_hwassist |= CSUM_TSO; 7842 else 7843 ifp->if_hwassist &= ~CSUM_TSO; 7844 } 7845 7846 if (mask & IFCAP_VLAN_HWCSUM && 7847 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7848 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7849 7850 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7851 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7852 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7853 /* 7854 * Don't actually disable VLAN tag stripping as 7855 * management firmware (ASF/IPMI/UMP) requires the 7856 * feature. If VLAN tag stripping is disabled driver 7857 * will manually reconstruct the VLAN frame by 7858 * appending stripped VLAN tag. 7859 */ 7860 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7861 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7862 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7863 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7864 == 0) 7865 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7866 } 7867 VLAN_CAPABILITIES(ifp); 7868 break; 7869 default: 7870 /* We don't know how to handle the IOCTL, pass it on. */ 7871 error = ether_ioctl(ifp, command, data); 7872 break; 7873 } 7874 7875 DBEXIT(BCE_VERBOSE_MISC); 7876 return(error); 7877 } 7878 7879 7880 /****************************************************************************/ 7881 /* Transmit timeout handler. */ 7882 /* */ 7883 /* Returns: */ 7884 /* Nothing. */ 7885 /****************************************************************************/ 7886 static void 7887 bce_watchdog(struct bce_softc *sc) 7888 { 7889 DBENTER(BCE_EXTREME_SEND); 7890 7891 BCE_LOCK_ASSERT(sc); 7892 7893 /* If the watchdog timer hasn't expired then just exit. */ 7894 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7895 goto bce_watchdog_exit; 7896 7897 /* If pause frames are active then don't reset the hardware. */ 7898 /* ToDo: Should we reset the timer here? */ 7899 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7900 goto bce_watchdog_exit; 7901 7902 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7903 __FILE__, __LINE__); 7904 7905 DBRUNMSG(BCE_INFO, 7906 bce_dump_driver_state(sc); 7907 bce_dump_status_block(sc); 7908 bce_dump_stats_block(sc); 7909 bce_dump_ftqs(sc); 7910 bce_dump_txp_state(sc, 0); 7911 bce_dump_rxp_state(sc, 0); 7912 bce_dump_tpat_state(sc, 0); 7913 bce_dump_cp_state(sc, 0); 7914 bce_dump_com_state(sc, 0)); 7915 7916 DBRUN(bce_breakpoint(sc)); 7917 7918 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7919 7920 bce_init_locked(sc); 7921 sc->bce_ifp->if_oerrors++; 7922 7923 bce_watchdog_exit: 7924 DBEXIT(BCE_EXTREME_SEND); 7925 } 7926 7927 7928 /* 7929 * Interrupt handler. 7930 */ 7931 /****************************************************************************/ 7932 /* Main interrupt entry point. Verifies that the controller generated the */ 7933 /* interrupt and then calls a separate routine for handle the various */ 7934 /* interrupt causes (PHY, TX, RX). */ 7935 /* */ 7936 /* Returns: */ 7937 /* 0 for success, positive value for failure. */ 7938 /****************************************************************************/ 7939 static void 7940 bce_intr(void *xsc) 7941 { 7942 struct bce_softc *sc; 7943 struct ifnet *ifp; 7944 u32 status_attn_bits; 7945 u16 hw_rx_cons, hw_tx_cons; 7946 7947 sc = xsc; 7948 ifp = sc->bce_ifp; 7949 7950 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7951 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7952 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7953 7954 BCE_LOCK(sc); 7955 7956 DBRUN(sc->interrupts_generated++); 7957 7958 /* Synchnorize before we read from interface's status block */ 7959 bus_dmamap_sync(sc->status_tag, sc->status_map, 7960 BUS_DMASYNC_POSTREAD); 7961 7962 /* 7963 * If the hardware status block index 7964 * matches the last value read by the 7965 * driver and we haven't asserted our 7966 * interrupt then there's nothing to do. 7967 */ 7968 if ((sc->status_block->status_idx == sc->last_status_idx) && 7969 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7970 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7971 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7972 __FUNCTION__); 7973 goto bce_intr_exit; 7974 } 7975 7976 /* Ack the interrupt and stop others from occuring. */ 7977 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7978 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7979 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7980 7981 /* Check if the hardware has finished any work. */ 7982 hw_rx_cons = bce_get_hw_rx_cons(sc); 7983 hw_tx_cons = bce_get_hw_tx_cons(sc); 7984 7985 /* Keep processing data as long as there is work to do. */ 7986 for (;;) { 7987 7988 status_attn_bits = sc->status_block->status_attn_bits; 7989 7990 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7991 BCE_PRINTF("Simulating unexpected status attention " 7992 "bit set."); 7993 sc->unexpected_attention_sim_count++; 7994 status_attn_bits = status_attn_bits | 7995 STATUS_ATTN_BITS_PARITY_ERROR); 7996 7997 /* Was it a link change interrupt? */ 7998 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7999 (sc->status_block->status_attn_bits_ack & 8000 STATUS_ATTN_BITS_LINK_STATE)) { 8001 bce_phy_intr(sc); 8002 8003 /* Clear transient updates during link state change. */ 8004 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 8005 BCE_HC_COMMAND_COAL_NOW_WO_INT); 8006 REG_RD(sc, BCE_HC_COMMAND); 8007 } 8008 8009 /* If any other attention is asserted, the chip is toast. */ 8010 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 8011 (sc->status_block->status_attn_bits_ack & 8012 ~STATUS_ATTN_BITS_LINK_STATE))) { 8013 8014 sc->unexpected_attention_count++; 8015 8016 BCE_PRINTF("%s(%d): Fatal attention detected: " 8017 "0x%08X\n", __FILE__, __LINE__, 8018 sc->status_block->status_attn_bits); 8019 8020 DBRUNMSG(BCE_FATAL, 8021 if (unexpected_attention_sim_control == 0) 8022 bce_breakpoint(sc)); 8023 8024 bce_init_locked(sc); 8025 goto bce_intr_exit; 8026 } 8027 8028 /* Check for any completed RX frames. */ 8029 if (hw_rx_cons != sc->hw_rx_cons) 8030 bce_rx_intr(sc); 8031 8032 /* Check for any completed TX frames. */ 8033 if (hw_tx_cons != sc->hw_tx_cons) 8034 bce_tx_intr(sc); 8035 8036 /* Save status block index value for the next interrupt. */ 8037 sc->last_status_idx = sc->status_block->status_idx; 8038 8039 /* 8040 * Prevent speculative reads from getting 8041 * ahead of the status block. 8042 */ 8043 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 8044 BUS_SPACE_BARRIER_READ); 8045 8046 /* 8047 * If there's no work left then exit the 8048 * interrupt service routine. 8049 */ 8050 hw_rx_cons = bce_get_hw_rx_cons(sc); 8051 hw_tx_cons = bce_get_hw_tx_cons(sc); 8052 8053 if ((hw_rx_cons == sc->hw_rx_cons) && 8054 (hw_tx_cons == sc->hw_tx_cons)) 8055 break; 8056 8057 } 8058 8059 bus_dmamap_sync(sc->status_tag, sc->status_map, 8060 BUS_DMASYNC_PREREAD); 8061 8062 /* Re-enable interrupts. */ 8063 bce_enable_intr(sc, 0); 8064 8065 /* Handle any frames that arrived while handling the interrupt. */ 8066 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 8067 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 8068 bce_start_locked(ifp); 8069 8070 bce_intr_exit: 8071 BCE_UNLOCK(sc); 8072 8073 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 8074 } 8075 8076 8077 /****************************************************************************/ 8078 /* Programs the various packet receive modes (broadcast and multicast). */ 8079 /* */ 8080 /* Returns: */ 8081 /* Nothing. */ 8082 /****************************************************************************/ 8083 static void 8084 bce_set_rx_mode(struct bce_softc *sc) 8085 { 8086 struct ifnet *ifp; 8087 struct ifmultiaddr *ifma; 8088 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 8089 u32 rx_mode, sort_mode; 8090 int h, i; 8091 8092 DBENTER(BCE_VERBOSE_MISC); 8093 8094 BCE_LOCK_ASSERT(sc); 8095 8096 ifp = sc->bce_ifp; 8097 8098 /* Initialize receive mode default settings. */ 8099 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 8100 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 8101 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 8102 8103 /* 8104 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 8105 * be enbled. 8106 */ 8107 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 8108 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 8109 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 8110 8111 /* 8112 * Check for promiscuous, all multicast, or selected 8113 * multicast address filtering. 8114 */ 8115 if (ifp->if_flags & IFF_PROMISC) { 8116 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 8117 8118 /* Enable promiscuous mode. */ 8119 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 8120 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 8121 } else if (ifp->if_flags & IFF_ALLMULTI) { 8122 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 8123 8124 /* Enable all multicast addresses. */ 8125 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 8126 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 8127 } 8128 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 8129 } else { 8130 /* Accept one or more multicast(s). */ 8131 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 8132 8133 if_maddr_rlock(ifp); 8134 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 8135 if (ifma->ifma_addr->sa_family != AF_LINK) 8136 continue; 8137 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 8138 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 8139 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 8140 } 8141 if_maddr_runlock(ifp); 8142 8143 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 8144 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 8145 8146 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 8147 } 8148 8149 /* Only make changes if the recive mode has actually changed. */ 8150 if (rx_mode != sc->rx_mode) { 8151 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 8152 "0x%08X\n", rx_mode); 8153 8154 sc->rx_mode = rx_mode; 8155 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 8156 } 8157 8158 /* Disable and clear the exisitng sort before enabling a new sort. */ 8159 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 8160 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 8161 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8162 8163 DBEXIT(BCE_VERBOSE_MISC); 8164 } 8165 8166 8167 /****************************************************************************/ 8168 /* Called periodically to updates statistics from the controllers */ 8169 /* statistics block. */ 8170 /* */ 8171 /* Returns: */ 8172 /* Nothing. */ 8173 /****************************************************************************/ 8174 static void 8175 bce_stats_update(struct bce_softc *sc) 8176 { 8177 struct ifnet *ifp; 8178 struct statistics_block *stats; 8179 8180 DBENTER(BCE_EXTREME_MISC); 8181 8182 ifp = sc->bce_ifp; 8183 8184 stats = (struct statistics_block *) sc->stats_block; 8185 8186 /* 8187 * Certain controllers don't report 8188 * carrier sense errors correctly. 8189 * See errata E11_5708CA0_1165. 8190 */ 8191 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8192 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8193 ifp->if_oerrors += 8194 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 8195 8196 /* 8197 * Update the sysctl statistics from the 8198 * hardware statistics. 8199 */ 8200 sc->stat_IfHCInOctets = 8201 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8202 (u64) stats->stat_IfHCInOctets_lo; 8203 8204 sc->stat_IfHCInBadOctets = 8205 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8206 (u64) stats->stat_IfHCInBadOctets_lo; 8207 8208 sc->stat_IfHCOutOctets = 8209 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8210 (u64) stats->stat_IfHCOutOctets_lo; 8211 8212 sc->stat_IfHCOutBadOctets = 8213 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8214 (u64) stats->stat_IfHCOutBadOctets_lo; 8215 8216 sc->stat_IfHCInUcastPkts = 8217 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8218 (u64) stats->stat_IfHCInUcastPkts_lo; 8219 8220 sc->stat_IfHCInMulticastPkts = 8221 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8222 (u64) stats->stat_IfHCInMulticastPkts_lo; 8223 8224 sc->stat_IfHCInBroadcastPkts = 8225 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8226 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8227 8228 sc->stat_IfHCOutUcastPkts = 8229 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8230 (u64) stats->stat_IfHCOutUcastPkts_lo; 8231 8232 sc->stat_IfHCOutMulticastPkts = 8233 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8234 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8235 8236 sc->stat_IfHCOutBroadcastPkts = 8237 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8238 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8239 8240 /* ToDo: Preserve counters beyond 32 bits? */ 8241 /* ToDo: Read the statistics from auto-clear regs? */ 8242 8243 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8244 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8245 8246 sc->stat_Dot3StatsCarrierSenseErrors = 8247 stats->stat_Dot3StatsCarrierSenseErrors; 8248 8249 sc->stat_Dot3StatsFCSErrors = 8250 stats->stat_Dot3StatsFCSErrors; 8251 8252 sc->stat_Dot3StatsAlignmentErrors = 8253 stats->stat_Dot3StatsAlignmentErrors; 8254 8255 sc->stat_Dot3StatsSingleCollisionFrames = 8256 stats->stat_Dot3StatsSingleCollisionFrames; 8257 8258 sc->stat_Dot3StatsMultipleCollisionFrames = 8259 stats->stat_Dot3StatsMultipleCollisionFrames; 8260 8261 sc->stat_Dot3StatsDeferredTransmissions = 8262 stats->stat_Dot3StatsDeferredTransmissions; 8263 8264 sc->stat_Dot3StatsExcessiveCollisions = 8265 stats->stat_Dot3StatsExcessiveCollisions; 8266 8267 sc->stat_Dot3StatsLateCollisions = 8268 stats->stat_Dot3StatsLateCollisions; 8269 8270 sc->stat_EtherStatsCollisions = 8271 stats->stat_EtherStatsCollisions; 8272 8273 sc->stat_EtherStatsFragments = 8274 stats->stat_EtherStatsFragments; 8275 8276 sc->stat_EtherStatsJabbers = 8277 stats->stat_EtherStatsJabbers; 8278 8279 sc->stat_EtherStatsUndersizePkts = 8280 stats->stat_EtherStatsUndersizePkts; 8281 8282 sc->stat_EtherStatsOversizePkts = 8283 stats->stat_EtherStatsOversizePkts; 8284 8285 sc->stat_EtherStatsPktsRx64Octets = 8286 stats->stat_EtherStatsPktsRx64Octets; 8287 8288 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8289 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8290 8291 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8292 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8293 8294 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8295 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8296 8297 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8298 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8299 8300 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8301 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8302 8303 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8304 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8305 8306 sc->stat_EtherStatsPktsTx64Octets = 8307 stats->stat_EtherStatsPktsTx64Octets; 8308 8309 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8310 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8311 8312 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8313 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8314 8315 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8316 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8317 8318 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8319 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8320 8321 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8322 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8323 8324 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8325 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8326 8327 sc->stat_XonPauseFramesReceived = 8328 stats->stat_XonPauseFramesReceived; 8329 8330 sc->stat_XoffPauseFramesReceived = 8331 stats->stat_XoffPauseFramesReceived; 8332 8333 sc->stat_OutXonSent = 8334 stats->stat_OutXonSent; 8335 8336 sc->stat_OutXoffSent = 8337 stats->stat_OutXoffSent; 8338 8339 sc->stat_FlowControlDone = 8340 stats->stat_FlowControlDone; 8341 8342 sc->stat_MacControlFramesReceived = 8343 stats->stat_MacControlFramesReceived; 8344 8345 sc->stat_XoffStateEntered = 8346 stats->stat_XoffStateEntered; 8347 8348 sc->stat_IfInFramesL2FilterDiscards = 8349 stats->stat_IfInFramesL2FilterDiscards; 8350 8351 sc->stat_IfInRuleCheckerDiscards = 8352 stats->stat_IfInRuleCheckerDiscards; 8353 8354 sc->stat_IfInFTQDiscards = 8355 stats->stat_IfInFTQDiscards; 8356 8357 sc->stat_IfInMBUFDiscards = 8358 stats->stat_IfInMBUFDiscards; 8359 8360 sc->stat_IfInRuleCheckerP4Hit = 8361 stats->stat_IfInRuleCheckerP4Hit; 8362 8363 sc->stat_CatchupInRuleCheckerDiscards = 8364 stats->stat_CatchupInRuleCheckerDiscards; 8365 8366 sc->stat_CatchupInFTQDiscards = 8367 stats->stat_CatchupInFTQDiscards; 8368 8369 sc->stat_CatchupInMBUFDiscards = 8370 stats->stat_CatchupInMBUFDiscards; 8371 8372 sc->stat_CatchupInRuleCheckerP4Hit = 8373 stats->stat_CatchupInRuleCheckerP4Hit; 8374 8375 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8376 8377 /* 8378 * Update the interface statistics from the 8379 * hardware statistics. 8380 */ 8381 ifp->if_collisions = 8382 (u_long) sc->stat_EtherStatsCollisions; 8383 8384 /* ToDo: This method loses soft errors. */ 8385 ifp->if_ierrors = 8386 (u_long) sc->stat_EtherStatsUndersizePkts + 8387 (u_long) sc->stat_EtherStatsOversizePkts + 8388 (u_long) sc->stat_IfInMBUFDiscards + 8389 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8390 (u_long) sc->stat_Dot3StatsFCSErrors + 8391 (u_long) sc->stat_IfInRuleCheckerDiscards + 8392 (u_long) sc->stat_IfInFTQDiscards + 8393 (u_long) sc->com_no_buffers; 8394 8395 /* ToDo: This method loses soft errors. */ 8396 ifp->if_oerrors = 8397 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8398 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8399 (u_long) sc->stat_Dot3StatsLateCollisions; 8400 8401 /* ToDo: Add additional statistics? */ 8402 8403 DBEXIT(BCE_EXTREME_MISC); 8404 } 8405 8406 8407 /****************************************************************************/ 8408 /* Periodic function to notify the bootcode that the driver is still */ 8409 /* present. */ 8410 /* */ 8411 /* Returns: */ 8412 /* Nothing. */ 8413 /****************************************************************************/ 8414 static void 8415 bce_pulse(void *xsc) 8416 { 8417 struct bce_softc *sc = xsc; 8418 u32 msg; 8419 8420 DBENTER(BCE_EXTREME_MISC); 8421 8422 BCE_LOCK_ASSERT(sc); 8423 8424 /* Tell the firmware that the driver is still running. */ 8425 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8426 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8427 8428 /* Update the bootcode condition. */ 8429 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8430 8431 /* Report whether the bootcode still knows the driver is running. */ 8432 if (bce_verbose || bootverbose) { 8433 if (sc->bce_drv_cardiac_arrest == FALSE) { 8434 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8435 sc->bce_drv_cardiac_arrest = TRUE; 8436 BCE_PRINTF("%s(): Warning: bootcode " 8437 "thinks driver is absent! " 8438 "(bc_state = 0x%08X)\n", 8439 __FUNCTION__, sc->bc_state); 8440 } 8441 } else { 8442 /* 8443 * Not supported by all bootcode versions. 8444 * (v5.0.11+ and v5.2.1+) Older bootcode 8445 * will require the driver to reset the 8446 * controller to clear this condition. 8447 */ 8448 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8449 sc->bce_drv_cardiac_arrest = FALSE; 8450 BCE_PRINTF("%s(): Bootcode found the " 8451 "driver pulse! (bc_state = 0x%08X)\n", 8452 __FUNCTION__, sc->bc_state); 8453 } 8454 } 8455 } 8456 8457 8458 /* Schedule the next pulse. */ 8459 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8460 8461 DBEXIT(BCE_EXTREME_MISC); 8462 } 8463 8464 8465 /****************************************************************************/ 8466 /* Periodic function to perform maintenance tasks. */ 8467 /* */ 8468 /* Returns: */ 8469 /* Nothing. */ 8470 /****************************************************************************/ 8471 static void 8472 bce_tick(void *xsc) 8473 { 8474 struct bce_softc *sc = xsc; 8475 struct mii_data *mii; 8476 struct ifnet *ifp; 8477 struct ifmediareq ifmr; 8478 8479 ifp = sc->bce_ifp; 8480 8481 DBENTER(BCE_EXTREME_MISC); 8482 8483 BCE_LOCK_ASSERT(sc); 8484 8485 /* Schedule the next tick. */ 8486 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8487 8488 /* Update the statistics from the hardware statistics block. */ 8489 bce_stats_update(sc); 8490 8491 /* 8492 * ToDo: This is a safety measure. Need to re-evaluate 8493 * high level processing logic and eliminate this code. 8494 */ 8495 /* Top off the receive and page chains. */ 8496 if (bce_hdr_split == TRUE) 8497 bce_fill_pg_chain(sc); 8498 bce_fill_rx_chain(sc); 8499 8500 /* Check that chip hasn't hung. */ 8501 bce_watchdog(sc); 8502 8503 /* If link is up already up then we're done. */ 8504 if (sc->bce_link_up == TRUE) 8505 goto bce_tick_exit; 8506 8507 /* Link is down. Check what the PHY's doing. */ 8508 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8509 bzero(&ifmr, sizeof(ifmr)); 8510 bce_ifmedia_sts_rphy(sc, &ifmr); 8511 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8512 (IFM_ACTIVE | IFM_AVALID)) { 8513 sc->bce_link_up = TRUE; 8514 bce_miibus_statchg(sc->bce_dev); 8515 } 8516 } else { 8517 mii = device_get_softc(sc->bce_miibus); 8518 mii_tick(mii); 8519 /* Check if the link has come up. */ 8520 if ((mii->mii_media_status & IFM_ACTIVE) && 8521 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8522 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8523 __FUNCTION__); 8524 sc->bce_link_up = TRUE; 8525 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8526 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8527 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8528 (bce_verbose || bootverbose)) 8529 BCE_PRINTF("Gigabit link up!\n"); 8530 } 8531 8532 } 8533 if (sc->bce_link_up == TRUE) { 8534 /* Now that link is up, handle any outstanding TX traffic. */ 8535 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8536 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8537 "pending TX traffic.\n", __FUNCTION__); 8538 bce_start_locked(ifp); 8539 } 8540 } 8541 8542 bce_tick_exit: 8543 DBEXIT(BCE_EXTREME_MISC); 8544 return; 8545 } 8546 8547 static void 8548 bce_fw_cap_init(struct bce_softc *sc) 8549 { 8550 u32 ack, cap, link; 8551 8552 ack = 0; 8553 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8554 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8555 BCE_FW_CAP_SIGNATURE_MAGIC) 8556 return; 8557 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8558 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8559 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8560 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8561 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8562 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8563 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8564 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8565 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8566 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8567 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8568 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8569 BCE_FW_CAP_REMOTE_PHY_CAP; 8570 } 8571 8572 if (ack != 0) 8573 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8574 } 8575 8576 8577 #ifdef BCE_DEBUG 8578 /****************************************************************************/ 8579 /* Allows the driver state to be dumped through the sysctl interface. */ 8580 /* */ 8581 /* Returns: */ 8582 /* 0 for success, positive value for failure. */ 8583 /****************************************************************************/ 8584 static int 8585 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8586 { 8587 int error; 8588 int result; 8589 struct bce_softc *sc; 8590 8591 result = -1; 8592 error = sysctl_handle_int(oidp, &result, 0, req); 8593 8594 if (error || !req->newptr) 8595 return (error); 8596 8597 if (result == 1) { 8598 sc = (struct bce_softc *)arg1; 8599 bce_dump_driver_state(sc); 8600 } 8601 8602 return error; 8603 } 8604 8605 8606 /****************************************************************************/ 8607 /* Allows the hardware state to be dumped through the sysctl interface. */ 8608 /* */ 8609 /* Returns: */ 8610 /* 0 for success, positive value for failure. */ 8611 /****************************************************************************/ 8612 static int 8613 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8614 { 8615 int error; 8616 int result; 8617 struct bce_softc *sc; 8618 8619 result = -1; 8620 error = sysctl_handle_int(oidp, &result, 0, req); 8621 8622 if (error || !req->newptr) 8623 return (error); 8624 8625 if (result == 1) { 8626 sc = (struct bce_softc *)arg1; 8627 bce_dump_hw_state(sc); 8628 } 8629 8630 return error; 8631 } 8632 8633 8634 /****************************************************************************/ 8635 /* Allows the status block to be dumped through the sysctl interface. */ 8636 /* */ 8637 /* Returns: */ 8638 /* 0 for success, positive value for failure. */ 8639 /****************************************************************************/ 8640 static int 8641 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8642 { 8643 int error; 8644 int result; 8645 struct bce_softc *sc; 8646 8647 result = -1; 8648 error = sysctl_handle_int(oidp, &result, 0, req); 8649 8650 if (error || !req->newptr) 8651 return (error); 8652 8653 if (result == 1) { 8654 sc = (struct bce_softc *)arg1; 8655 bce_dump_status_block(sc); 8656 } 8657 8658 return error; 8659 } 8660 8661 8662 /****************************************************************************/ 8663 /* Allows the stats block to be dumped through the sysctl interface. */ 8664 /* */ 8665 /* Returns: */ 8666 /* 0 for success, positive value for failure. */ 8667 /****************************************************************************/ 8668 static int 8669 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8670 { 8671 int error; 8672 int result; 8673 struct bce_softc *sc; 8674 8675 result = -1; 8676 error = sysctl_handle_int(oidp, &result, 0, req); 8677 8678 if (error || !req->newptr) 8679 return (error); 8680 8681 if (result == 1) { 8682 sc = (struct bce_softc *)arg1; 8683 bce_dump_stats_block(sc); 8684 } 8685 8686 return error; 8687 } 8688 8689 8690 /****************************************************************************/ 8691 /* Allows the stat counters to be cleared without unloading/reloading the */ 8692 /* driver. */ 8693 /* */ 8694 /* Returns: */ 8695 /* 0 for success, positive value for failure. */ 8696 /****************************************************************************/ 8697 static int 8698 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8699 { 8700 int error; 8701 int result; 8702 struct bce_softc *sc; 8703 8704 result = -1; 8705 error = sysctl_handle_int(oidp, &result, 0, req); 8706 8707 if (error || !req->newptr) 8708 return (error); 8709 8710 if (result == 1) { 8711 sc = (struct bce_softc *)arg1; 8712 struct statistics_block *stats; 8713 8714 stats = (struct statistics_block *) sc->stats_block; 8715 bzero(stats, sizeof(struct statistics_block)); 8716 8717 /* Clear the internal H/W statistics counters. */ 8718 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8719 8720 /* Reset the driver maintained statistics. */ 8721 sc->interrupts_rx = 8722 sc->interrupts_tx = 0; 8723 sc->tso_frames_requested = 8724 sc->tso_frames_completed = 8725 sc->tso_frames_failed = 0; 8726 sc->rx_empty_count = 8727 sc->tx_full_count = 0; 8728 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8729 sc->tx_hi_watermark = 0; 8730 sc->l2fhdr_error_count = 8731 sc->l2fhdr_error_sim_count = 0; 8732 sc->mbuf_alloc_failed_count = 8733 sc->mbuf_alloc_failed_sim_count = 0; 8734 sc->dma_map_addr_rx_failed_count = 8735 sc->dma_map_addr_tx_failed_count = 0; 8736 sc->mbuf_frag_count = 0; 8737 sc->csum_offload_tcp_udp = 8738 sc->csum_offload_ip = 0; 8739 sc->vlan_tagged_frames_rcvd = 8740 sc->vlan_tagged_frames_stripped = 0; 8741 sc->split_header_frames_rcvd = 8742 sc->split_header_tcp_frames_rcvd = 0; 8743 8744 /* Clear firmware maintained statistics. */ 8745 REG_WR_IND(sc, 0x120084, 0); 8746 } 8747 8748 return error; 8749 } 8750 8751 8752 /****************************************************************************/ 8753 /* Allows the shared memory contents to be dumped through the sysctl . */ 8754 /* interface. */ 8755 /* */ 8756 /* Returns: */ 8757 /* 0 for success, positive value for failure. */ 8758 /****************************************************************************/ 8759 static int 8760 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8761 { 8762 int error; 8763 int result; 8764 struct bce_softc *sc; 8765 8766 result = -1; 8767 error = sysctl_handle_int(oidp, &result, 0, req); 8768 8769 if (error || !req->newptr) 8770 return (error); 8771 8772 if (result == 1) { 8773 sc = (struct bce_softc *)arg1; 8774 bce_dump_shmem_state(sc); 8775 } 8776 8777 return error; 8778 } 8779 8780 8781 /****************************************************************************/ 8782 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8783 /* */ 8784 /* Returns: */ 8785 /* 0 for success, positive value for failure. */ 8786 /****************************************************************************/ 8787 static int 8788 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8789 { 8790 int error; 8791 int result; 8792 struct bce_softc *sc; 8793 8794 result = -1; 8795 error = sysctl_handle_int(oidp, &result, 0, req); 8796 8797 if (error || !req->newptr) 8798 return (error); 8799 8800 if (result == 1) { 8801 sc = (struct bce_softc *)arg1; 8802 bce_dump_bc_state(sc); 8803 } 8804 8805 return error; 8806 } 8807 8808 8809 /****************************************************************************/ 8810 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8811 /* */ 8812 /* Returns: */ 8813 /* 0 for success, positive value for failure. */ 8814 /****************************************************************************/ 8815 static int 8816 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8817 { 8818 int error; 8819 int result; 8820 struct bce_softc *sc; 8821 8822 result = -1; 8823 error = sysctl_handle_int(oidp, &result, 0, req); 8824 8825 if (error || !req->newptr) 8826 return (error); 8827 8828 if (result == 1) { 8829 sc = (struct bce_softc *)arg1; 8830 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8831 } 8832 8833 return error; 8834 } 8835 8836 8837 /****************************************************************************/ 8838 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8839 /* */ 8840 /* Returns: */ 8841 /* 0 for success, positive value for failure. */ 8842 /****************************************************************************/ 8843 static int 8844 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8845 { 8846 int error; 8847 int result; 8848 struct bce_softc *sc; 8849 8850 result = -1; 8851 error = sysctl_handle_int(oidp, &result, 0, req); 8852 8853 if (error || !req->newptr) 8854 return (error); 8855 8856 if (result == 1) { 8857 sc = (struct bce_softc *)arg1; 8858 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8859 } 8860 8861 return error; 8862 } 8863 8864 8865 /****************************************************************************/ 8866 /* Provides a sysctl interface to allow dumping the TX chain. */ 8867 /* */ 8868 /* Returns: */ 8869 /* 0 for success, positive value for failure. */ 8870 /****************************************************************************/ 8871 static int 8872 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8873 { 8874 int error; 8875 int result; 8876 struct bce_softc *sc; 8877 8878 result = -1; 8879 error = sysctl_handle_int(oidp, &result, 0, req); 8880 8881 if (error || !req->newptr) 8882 return (error); 8883 8884 if (result == 1) { 8885 sc = (struct bce_softc *)arg1; 8886 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8887 } 8888 8889 return error; 8890 } 8891 8892 8893 /****************************************************************************/ 8894 /* Provides a sysctl interface to allow dumping the page chain. */ 8895 /* */ 8896 /* Returns: */ 8897 /* 0 for success, positive value for failure. */ 8898 /****************************************************************************/ 8899 static int 8900 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8901 { 8902 int error; 8903 int result; 8904 struct bce_softc *sc; 8905 8906 result = -1; 8907 error = sysctl_handle_int(oidp, &result, 0, req); 8908 8909 if (error || !req->newptr) 8910 return (error); 8911 8912 if (result == 1) { 8913 sc = (struct bce_softc *)arg1; 8914 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8915 } 8916 8917 return error; 8918 } 8919 8920 /****************************************************************************/ 8921 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8922 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8923 /* */ 8924 /* Returns: */ 8925 /* 0 for success, positive value for failure. */ 8926 /****************************************************************************/ 8927 static int 8928 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8929 { 8930 struct bce_softc *sc = (struct bce_softc *)arg1; 8931 int error; 8932 u32 result; 8933 u32 val[1]; 8934 u8 *data = (u8 *) val; 8935 8936 result = -1; 8937 error = sysctl_handle_int(oidp, &result, 0, req); 8938 if (error || (req->newptr == NULL)) 8939 return (error); 8940 8941 error = bce_nvram_read(sc, result, data, 4); 8942 8943 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8944 8945 return (error); 8946 } 8947 8948 8949 /****************************************************************************/ 8950 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8951 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8952 /* */ 8953 /* Returns: */ 8954 /* 0 for success, positive value for failure. */ 8955 /****************************************************************************/ 8956 static int 8957 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8958 { 8959 struct bce_softc *sc = (struct bce_softc *)arg1; 8960 int error; 8961 u32 val, result; 8962 8963 result = -1; 8964 error = sysctl_handle_int(oidp, &result, 0, req); 8965 if (error || (req->newptr == NULL)) 8966 return (error); 8967 8968 /* Make sure the register is accessible. */ 8969 if (result < 0x8000) { 8970 val = REG_RD(sc, result); 8971 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8972 } else if (result < 0x0280000) { 8973 val = REG_RD_IND(sc, result); 8974 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8975 } 8976 8977 return (error); 8978 } 8979 8980 8981 /****************************************************************************/ 8982 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8983 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8984 /* */ 8985 /* Returns: */ 8986 /* 0 for success, positive value for failure. */ 8987 /****************************************************************************/ 8988 static int 8989 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8990 { 8991 struct bce_softc *sc; 8992 device_t dev; 8993 int error, result; 8994 u16 val; 8995 8996 result = -1; 8997 error = sysctl_handle_int(oidp, &result, 0, req); 8998 if (error || (req->newptr == NULL)) 8999 return (error); 9000 9001 /* Make sure the register is accessible. */ 9002 if (result < 0x20) { 9003 sc = (struct bce_softc *)arg1; 9004 dev = sc->bce_dev; 9005 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 9006 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 9007 } 9008 return (error); 9009 } 9010 9011 9012 /****************************************************************************/ 9013 /* Provides a sysctl interface for dumping the nvram contents. */ 9014 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9015 /* */ 9016 /* Returns: */ 9017 /* 0 for success, positive errno for failure. */ 9018 /****************************************************************************/ 9019 static int 9020 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 9021 { 9022 struct bce_softc *sc = (struct bce_softc *)arg1; 9023 int error, i; 9024 9025 if (sc->nvram_buf == NULL) 9026 sc->nvram_buf = malloc(sc->bce_flash_size, 9027 M_TEMP, M_ZERO | M_WAITOK); 9028 9029 error = 0; 9030 if (req->oldlen == sc->bce_flash_size) { 9031 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 9032 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 9033 } 9034 9035 if (error == 0) 9036 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 9037 9038 return error; 9039 } 9040 9041 #ifdef BCE_NVRAM_WRITE_SUPPORT 9042 /****************************************************************************/ 9043 /* Provides a sysctl interface for writing to nvram. */ 9044 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9045 /* */ 9046 /* Returns: */ 9047 /* 0 for success, positive errno for failure. */ 9048 /****************************************************************************/ 9049 static int 9050 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 9051 { 9052 struct bce_softc *sc = (struct bce_softc *)arg1; 9053 int error; 9054 9055 if (sc->nvram_buf == NULL) 9056 sc->nvram_buf = malloc(sc->bce_flash_size, 9057 M_TEMP, M_ZERO | M_WAITOK); 9058 else 9059 bzero(sc->nvram_buf, sc->bce_flash_size); 9060 9061 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 9062 if (error == 0) 9063 return (error); 9064 9065 if (req->newlen == sc->bce_flash_size) 9066 error = bce_nvram_write(sc, 0, sc->nvram_buf, 9067 sc->bce_flash_size); 9068 9069 9070 return error; 9071 } 9072 #endif 9073 9074 9075 /****************************************************************************/ 9076 /* Provides a sysctl interface to allow reading a CID. */ 9077 /* */ 9078 /* Returns: */ 9079 /* 0 for success, positive value for failure. */ 9080 /****************************************************************************/ 9081 static int 9082 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 9083 { 9084 struct bce_softc *sc; 9085 int error, result; 9086 9087 result = -1; 9088 error = sysctl_handle_int(oidp, &result, 0, req); 9089 if (error || (req->newptr == NULL)) 9090 return (error); 9091 9092 /* Make sure the register is accessible. */ 9093 if (result <= TX_CID) { 9094 sc = (struct bce_softc *)arg1; 9095 bce_dump_ctx(sc, result); 9096 } 9097 9098 return (error); 9099 } 9100 9101 9102 /****************************************************************************/ 9103 /* Provides a sysctl interface to forcing the driver to dump state and */ 9104 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9105 /* */ 9106 /* Returns: */ 9107 /* 0 for success, positive value for failure. */ 9108 /****************************************************************************/ 9109 static int 9110 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 9111 { 9112 int error; 9113 int result; 9114 struct bce_softc *sc; 9115 9116 result = -1; 9117 error = sysctl_handle_int(oidp, &result, 0, req); 9118 9119 if (error || !req->newptr) 9120 return (error); 9121 9122 if (result == 1) { 9123 sc = (struct bce_softc *)arg1; 9124 bce_breakpoint(sc); 9125 } 9126 9127 return error; 9128 } 9129 #endif 9130 9131 /****************************************************************************/ 9132 /* Adds any sysctl parameters for tuning or debugging purposes. */ 9133 /* */ 9134 /* Returns: */ 9135 /* 0 for success, positive value for failure. */ 9136 /****************************************************************************/ 9137 static void 9138 bce_add_sysctls(struct bce_softc *sc) 9139 { 9140 struct sysctl_ctx_list *ctx; 9141 struct sysctl_oid_list *children; 9142 9143 DBENTER(BCE_VERBOSE_MISC); 9144 9145 ctx = device_get_sysctl_ctx(sc->bce_dev); 9146 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 9147 9148 #ifdef BCE_DEBUG 9149 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9150 "l2fhdr_error_sim_control", 9151 CTLFLAG_RW, &l2fhdr_error_sim_control, 9152 0, "Debug control to force l2fhdr errors"); 9153 9154 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9155 "l2fhdr_error_sim_count", 9156 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 9157 0, "Number of simulated l2_fhdr errors"); 9158 #endif 9159 9160 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9161 "l2fhdr_error_count", 9162 CTLFLAG_RD, &sc->l2fhdr_error_count, 9163 0, "Number of l2_fhdr errors"); 9164 9165 #ifdef BCE_DEBUG 9166 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9167 "mbuf_alloc_failed_sim_control", 9168 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 9169 0, "Debug control to force mbuf allocation failures"); 9170 9171 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9172 "mbuf_alloc_failed_sim_count", 9173 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 9174 0, "Number of simulated mbuf cluster allocation failures"); 9175 #endif 9176 9177 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9178 "mbuf_alloc_failed_count", 9179 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 9180 0, "Number of mbuf allocation failures"); 9181 9182 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9183 "mbuf_frag_count", 9184 CTLFLAG_RD, &sc->mbuf_frag_count, 9185 0, "Number of fragmented mbufs"); 9186 9187 #ifdef BCE_DEBUG 9188 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9189 "dma_map_addr_failed_sim_control", 9190 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9191 0, "Debug control to force DMA mapping failures"); 9192 9193 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9194 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9195 "dma_map_addr_failed_sim_count", 9196 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9197 0, "Number of simulated DMA mapping failures"); 9198 9199 #endif 9200 9201 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9202 "dma_map_addr_rx_failed_count", 9203 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9204 0, "Number of RX DMA mapping failures"); 9205 9206 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9207 "dma_map_addr_tx_failed_count", 9208 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9209 0, "Number of TX DMA mapping failures"); 9210 9211 #ifdef BCE_DEBUG 9212 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9213 "unexpected_attention_sim_control", 9214 CTLFLAG_RW, &unexpected_attention_sim_control, 9215 0, "Debug control to simulate unexpected attentions"); 9216 9217 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9218 "unexpected_attention_sim_count", 9219 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9220 0, "Number of simulated unexpected attentions"); 9221 #endif 9222 9223 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9224 "unexpected_attention_count", 9225 CTLFLAG_RW, &sc->unexpected_attention_count, 9226 0, "Number of unexpected attentions"); 9227 9228 #ifdef BCE_DEBUG 9229 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9230 "debug_bootcode_running_failure", 9231 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9232 0, "Debug control to force bootcode running failures"); 9233 9234 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9235 "rx_low_watermark", 9236 CTLFLAG_RD, &sc->rx_low_watermark, 9237 0, "Lowest level of free rx_bd's"); 9238 9239 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9240 "rx_empty_count", 9241 CTLFLAG_RD, &sc->rx_empty_count, 9242 "Number of times the RX chain was empty"); 9243 9244 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9245 "tx_hi_watermark", 9246 CTLFLAG_RD, &sc->tx_hi_watermark, 9247 0, "Highest level of used tx_bd's"); 9248 9249 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9250 "tx_full_count", 9251 CTLFLAG_RD, &sc->tx_full_count, 9252 "Number of times the TX chain was full"); 9253 9254 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9255 "tso_frames_requested", 9256 CTLFLAG_RD, &sc->tso_frames_requested, 9257 "Number of TSO frames requested"); 9258 9259 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9260 "tso_frames_completed", 9261 CTLFLAG_RD, &sc->tso_frames_completed, 9262 "Number of TSO frames completed"); 9263 9264 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9265 "tso_frames_failed", 9266 CTLFLAG_RD, &sc->tso_frames_failed, 9267 "Number of TSO frames failed"); 9268 9269 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9270 "csum_offload_ip", 9271 CTLFLAG_RD, &sc->csum_offload_ip, 9272 "Number of IP checksum offload frames"); 9273 9274 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9275 "csum_offload_tcp_udp", 9276 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9277 "Number of TCP/UDP checksum offload frames"); 9278 9279 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9280 "vlan_tagged_frames_rcvd", 9281 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9282 "Number of VLAN tagged frames received"); 9283 9284 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9285 "vlan_tagged_frames_stripped", 9286 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9287 "Number of VLAN tagged frames stripped"); 9288 9289 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9290 "interrupts_rx", 9291 CTLFLAG_RD, &sc->interrupts_rx, 9292 "Number of RX interrupts"); 9293 9294 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9295 "interrupts_tx", 9296 CTLFLAG_RD, &sc->interrupts_tx, 9297 "Number of TX interrupts"); 9298 9299 if (bce_hdr_split == TRUE) { 9300 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9301 "split_header_frames_rcvd", 9302 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9303 "Number of split header frames received"); 9304 9305 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9306 "split_header_tcp_frames_rcvd", 9307 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9308 "Number of split header TCP frames received"); 9309 } 9310 9311 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9312 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 9313 (void *)sc, 0, 9314 bce_sysctl_nvram_dump, "S", ""); 9315 9316 #ifdef BCE_NVRAM_WRITE_SUPPORT 9317 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9318 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 9319 (void *)sc, 0, 9320 bce_sysctl_nvram_write, "S", ""); 9321 #endif 9322 #endif /* BCE_DEBUG */ 9323 9324 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9325 "stat_IfHcInOctets", 9326 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9327 "Bytes received"); 9328 9329 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9330 "stat_IfHCInBadOctets", 9331 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9332 "Bad bytes received"); 9333 9334 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9335 "stat_IfHCOutOctets", 9336 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9337 "Bytes sent"); 9338 9339 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9340 "stat_IfHCOutBadOctets", 9341 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9342 "Bad bytes sent"); 9343 9344 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9345 "stat_IfHCInUcastPkts", 9346 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9347 "Unicast packets received"); 9348 9349 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9350 "stat_IfHCInMulticastPkts", 9351 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9352 "Multicast packets received"); 9353 9354 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9355 "stat_IfHCInBroadcastPkts", 9356 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9357 "Broadcast packets received"); 9358 9359 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9360 "stat_IfHCOutUcastPkts", 9361 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9362 "Unicast packets sent"); 9363 9364 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9365 "stat_IfHCOutMulticastPkts", 9366 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9367 "Multicast packets sent"); 9368 9369 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9370 "stat_IfHCOutBroadcastPkts", 9371 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9372 "Broadcast packets sent"); 9373 9374 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9375 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9376 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9377 0, "Internal MAC transmit errors"); 9378 9379 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9380 "stat_Dot3StatsCarrierSenseErrors", 9381 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9382 0, "Carrier sense errors"); 9383 9384 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9385 "stat_Dot3StatsFCSErrors", 9386 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9387 0, "Frame check sequence errors"); 9388 9389 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9390 "stat_Dot3StatsAlignmentErrors", 9391 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9392 0, "Alignment errors"); 9393 9394 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9395 "stat_Dot3StatsSingleCollisionFrames", 9396 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9397 0, "Single Collision Frames"); 9398 9399 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9400 "stat_Dot3StatsMultipleCollisionFrames", 9401 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9402 0, "Multiple Collision Frames"); 9403 9404 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9405 "stat_Dot3StatsDeferredTransmissions", 9406 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9407 0, "Deferred Transmissions"); 9408 9409 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9410 "stat_Dot3StatsExcessiveCollisions", 9411 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9412 0, "Excessive Collisions"); 9413 9414 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9415 "stat_Dot3StatsLateCollisions", 9416 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9417 0, "Late Collisions"); 9418 9419 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9420 "stat_EtherStatsCollisions", 9421 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9422 0, "Collisions"); 9423 9424 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9425 "stat_EtherStatsFragments", 9426 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9427 0, "Fragments"); 9428 9429 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9430 "stat_EtherStatsJabbers", 9431 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9432 0, "Jabbers"); 9433 9434 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9435 "stat_EtherStatsUndersizePkts", 9436 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9437 0, "Undersize packets"); 9438 9439 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9440 "stat_EtherStatsOversizePkts", 9441 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9442 0, "stat_EtherStatsOversizePkts"); 9443 9444 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9445 "stat_EtherStatsPktsRx64Octets", 9446 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9447 0, "Bytes received in 64 byte packets"); 9448 9449 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9450 "stat_EtherStatsPktsRx65Octetsto127Octets", 9451 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9452 0, "Bytes received in 65 to 127 byte packets"); 9453 9454 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9455 "stat_EtherStatsPktsRx128Octetsto255Octets", 9456 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9457 0, "Bytes received in 128 to 255 byte packets"); 9458 9459 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9460 "stat_EtherStatsPktsRx256Octetsto511Octets", 9461 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9462 0, "Bytes received in 256 to 511 byte packets"); 9463 9464 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9465 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9466 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9467 0, "Bytes received in 512 to 1023 byte packets"); 9468 9469 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9470 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9471 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9472 0, "Bytes received in 1024 t0 1522 byte packets"); 9473 9474 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9475 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9476 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9477 0, "Bytes received in 1523 to 9022 byte packets"); 9478 9479 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9480 "stat_EtherStatsPktsTx64Octets", 9481 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9482 0, "Bytes sent in 64 byte packets"); 9483 9484 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9485 "stat_EtherStatsPktsTx65Octetsto127Octets", 9486 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9487 0, "Bytes sent in 65 to 127 byte packets"); 9488 9489 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9490 "stat_EtherStatsPktsTx128Octetsto255Octets", 9491 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9492 0, "Bytes sent in 128 to 255 byte packets"); 9493 9494 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9495 "stat_EtherStatsPktsTx256Octetsto511Octets", 9496 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9497 0, "Bytes sent in 256 to 511 byte packets"); 9498 9499 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9500 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9501 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9502 0, "Bytes sent in 512 to 1023 byte packets"); 9503 9504 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9505 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9506 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9507 0, "Bytes sent in 1024 to 1522 byte packets"); 9508 9509 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9510 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9511 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9512 0, "Bytes sent in 1523 to 9022 byte packets"); 9513 9514 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9515 "stat_XonPauseFramesReceived", 9516 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9517 0, "XON pause frames receved"); 9518 9519 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9520 "stat_XoffPauseFramesReceived", 9521 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9522 0, "XOFF pause frames received"); 9523 9524 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9525 "stat_OutXonSent", 9526 CTLFLAG_RD, &sc->stat_OutXonSent, 9527 0, "XON pause frames sent"); 9528 9529 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9530 "stat_OutXoffSent", 9531 CTLFLAG_RD, &sc->stat_OutXoffSent, 9532 0, "XOFF pause frames sent"); 9533 9534 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9535 "stat_FlowControlDone", 9536 CTLFLAG_RD, &sc->stat_FlowControlDone, 9537 0, "Flow control done"); 9538 9539 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9540 "stat_MacControlFramesReceived", 9541 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9542 0, "MAC control frames received"); 9543 9544 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9545 "stat_XoffStateEntered", 9546 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9547 0, "XOFF state entered"); 9548 9549 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9550 "stat_IfInFramesL2FilterDiscards", 9551 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9552 0, "Received L2 packets discarded"); 9553 9554 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9555 "stat_IfInRuleCheckerDiscards", 9556 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9557 0, "Received packets discarded by rule"); 9558 9559 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9560 "stat_IfInFTQDiscards", 9561 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9562 0, "Received packet FTQ discards"); 9563 9564 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9565 "stat_IfInMBUFDiscards", 9566 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9567 0, "Received packets discarded due to lack " 9568 "of controller buffer memory"); 9569 9570 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9571 "stat_IfInRuleCheckerP4Hit", 9572 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9573 0, "Received packets rule checker hits"); 9574 9575 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9576 "stat_CatchupInRuleCheckerDiscards", 9577 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9578 0, "Received packets discarded in Catchup path"); 9579 9580 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9581 "stat_CatchupInFTQDiscards", 9582 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9583 0, "Received packets discarded in FTQ in Catchup path"); 9584 9585 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9586 "stat_CatchupInMBUFDiscards", 9587 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9588 0, "Received packets discarded in controller " 9589 "buffer memory in Catchup path"); 9590 9591 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9592 "stat_CatchupInRuleCheckerP4Hit", 9593 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9594 0, "Received packets rule checker hits in Catchup path"); 9595 9596 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9597 "com_no_buffers", 9598 CTLFLAG_RD, &sc->com_no_buffers, 9599 0, "Valid packets received but no RX buffers available"); 9600 9601 #ifdef BCE_DEBUG 9602 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9603 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9604 (void *)sc, 0, 9605 bce_sysctl_driver_state, "I", "Drive state information"); 9606 9607 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9608 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9609 (void *)sc, 0, 9610 bce_sysctl_hw_state, "I", "Hardware state information"); 9611 9612 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9613 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9614 (void *)sc, 0, 9615 bce_sysctl_status_block, "I", "Dump status block"); 9616 9617 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9618 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9619 (void *)sc, 0, 9620 bce_sysctl_stats_block, "I", "Dump statistics block"); 9621 9622 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9623 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9624 (void *)sc, 0, 9625 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9626 9627 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9628 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9629 (void *)sc, 0, 9630 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9631 9632 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9633 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9634 (void *)sc, 0, 9635 bce_sysctl_bc_state, "I", "Bootcode state information"); 9636 9637 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9638 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9639 (void *)sc, 0, 9640 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9641 9642 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9643 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9644 (void *)sc, 0, 9645 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9646 9647 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9648 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9649 (void *)sc, 0, 9650 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9651 9652 if (bce_hdr_split == TRUE) { 9653 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9654 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9655 (void *)sc, 0, 9656 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9657 } 9658 9659 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9660 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9661 (void *)sc, 0, 9662 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9663 9664 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9665 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9666 (void *)sc, 0, 9667 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9668 9669 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9670 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9671 (void *)sc, 0, 9672 bce_sysctl_reg_read, "I", "Register read"); 9673 9674 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9675 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9676 (void *)sc, 0, 9677 bce_sysctl_nvram_read, "I", "NVRAM read"); 9678 9679 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9680 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9681 (void *)sc, 0, 9682 bce_sysctl_phy_read, "I", "PHY register read"); 9683 9684 #endif 9685 9686 DBEXIT(BCE_VERBOSE_MISC); 9687 } 9688 9689 9690 /****************************************************************************/ 9691 /* BCE Debug Routines */ 9692 /****************************************************************************/ 9693 #ifdef BCE_DEBUG 9694 9695 /****************************************************************************/ 9696 /* Freezes the controller to allow for a cohesive state dump. */ 9697 /* */ 9698 /* Returns: */ 9699 /* Nothing. */ 9700 /****************************************************************************/ 9701 static __attribute__ ((noinline)) void 9702 bce_freeze_controller(struct bce_softc *sc) 9703 { 9704 u32 val; 9705 val = REG_RD(sc, BCE_MISC_COMMAND); 9706 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9707 REG_WR(sc, BCE_MISC_COMMAND, val); 9708 } 9709 9710 9711 /****************************************************************************/ 9712 /* Unfreezes the controller after a freeze operation. This may not always */ 9713 /* work and the controller will require a reset! */ 9714 /* */ 9715 /* Returns: */ 9716 /* Nothing. */ 9717 /****************************************************************************/ 9718 static __attribute__ ((noinline)) void 9719 bce_unfreeze_controller(struct bce_softc *sc) 9720 { 9721 u32 val; 9722 val = REG_RD(sc, BCE_MISC_COMMAND); 9723 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9724 REG_WR(sc, BCE_MISC_COMMAND, val); 9725 } 9726 9727 9728 /****************************************************************************/ 9729 /* Prints out Ethernet frame information from an mbuf. */ 9730 /* */ 9731 /* Partially decode an Ethernet frame to look at some important headers. */ 9732 /* */ 9733 /* Returns: */ 9734 /* Nothing. */ 9735 /****************************************************************************/ 9736 static __attribute__ ((noinline)) void 9737 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9738 { 9739 struct ether_vlan_header *eh; 9740 u16 etype; 9741 int ehlen; 9742 struct ip *ip; 9743 struct tcphdr *th; 9744 struct udphdr *uh; 9745 struct arphdr *ah; 9746 9747 BCE_PRINTF( 9748 "-----------------------------" 9749 " Frame Decode " 9750 "-----------------------------\n"); 9751 9752 eh = mtod(m, struct ether_vlan_header *); 9753 9754 /* Handle VLAN encapsulation if present. */ 9755 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9756 etype = ntohs(eh->evl_proto); 9757 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9758 } else { 9759 etype = ntohs(eh->evl_encap_proto); 9760 ehlen = ETHER_HDR_LEN; 9761 } 9762 9763 /* ToDo: Add VLAN output. */ 9764 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9765 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9766 9767 switch (etype) { 9768 case ETHERTYPE_IP: 9769 ip = (struct ip *)(m->m_data + ehlen); 9770 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9771 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9772 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9773 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9774 9775 switch (ip->ip_p) { 9776 case IPPROTO_TCP: 9777 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9778 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9779 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9780 ntohs(th->th_dport), ntohs(th->th_sport), 9781 (th->th_off << 2), th->th_flags, 9782 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9783 "\02SYN\01FIN", ntohs(th->th_sum)); 9784 break; 9785 case IPPROTO_UDP: 9786 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9787 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9788 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9789 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9790 ntohs(uh->uh_sum)); 9791 break; 9792 case IPPROTO_ICMP: 9793 BCE_PRINTF("icmp:\n"); 9794 break; 9795 default: 9796 BCE_PRINTF("----: Other IP protocol.\n"); 9797 } 9798 break; 9799 case ETHERTYPE_IPV6: 9800 BCE_PRINTF("ipv6: No decode supported.\n"); 9801 break; 9802 case ETHERTYPE_ARP: 9803 BCE_PRINTF("-arp: "); 9804 ah = (struct arphdr *) (m->m_data + ehlen); 9805 switch (ntohs(ah->ar_op)) { 9806 case ARPOP_REVREQUEST: 9807 printf("reverse ARP request\n"); 9808 break; 9809 case ARPOP_REVREPLY: 9810 printf("reverse ARP reply\n"); 9811 break; 9812 case ARPOP_REQUEST: 9813 printf("ARP request\n"); 9814 break; 9815 case ARPOP_REPLY: 9816 printf("ARP reply\n"); 9817 break; 9818 default: 9819 printf("other ARP operation\n"); 9820 } 9821 break; 9822 default: 9823 BCE_PRINTF("----: Other protocol.\n"); 9824 } 9825 9826 BCE_PRINTF( 9827 "-----------------------------" 9828 "--------------" 9829 "-----------------------------\n"); 9830 } 9831 9832 9833 /****************************************************************************/ 9834 /* Prints out information about an mbuf. */ 9835 /* */ 9836 /* Returns: */ 9837 /* Nothing. */ 9838 /****************************************************************************/ 9839 static __attribute__ ((noinline)) void 9840 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9841 { 9842 struct mbuf *mp = m; 9843 9844 if (m == NULL) { 9845 BCE_PRINTF("mbuf: null pointer\n"); 9846 return; 9847 } 9848 9849 while (mp) { 9850 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9851 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9852 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9853 9854 if (mp->m_flags & M_PKTHDR) { 9855 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9856 "csum_flags = %b\n", mp->m_pkthdr.len, 9857 mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" 9858 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9859 "\22M_PROMISC\23M_NOFREE", 9860 mp->m_pkthdr.csum_flags, 9861 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 9862 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9863 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9864 "\14CSUM_PSEUDO_HDR"); 9865 } 9866 9867 if (mp->m_flags & M_EXT) { 9868 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9869 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9870 switch (mp->m_ext.ext_type) { 9871 case EXT_CLUSTER: 9872 printf("EXT_CLUSTER\n"); break; 9873 case EXT_SFBUF: 9874 printf("EXT_SFBUF\n"); break; 9875 case EXT_JUMBO9: 9876 printf("EXT_JUMBO9\n"); break; 9877 case EXT_JUMBO16: 9878 printf("EXT_JUMBO16\n"); break; 9879 case EXT_PACKET: 9880 printf("EXT_PACKET\n"); break; 9881 case EXT_MBUF: 9882 printf("EXT_MBUF\n"); break; 9883 case EXT_NET_DRV: 9884 printf("EXT_NET_DRV\n"); break; 9885 case EXT_MOD_TYPE: 9886 printf("EXT_MDD_TYPE\n"); break; 9887 case EXT_DISPOSABLE: 9888 printf("EXT_DISPOSABLE\n"); break; 9889 case EXT_EXTREF: 9890 printf("EXT_EXTREF\n"); break; 9891 default: 9892 printf("UNKNOWN\n"); 9893 } 9894 } 9895 9896 mp = mp->m_next; 9897 } 9898 } 9899 9900 9901 /****************************************************************************/ 9902 /* Prints out the mbufs in the TX mbuf chain. */ 9903 /* */ 9904 /* Returns: */ 9905 /* Nothing. */ 9906 /****************************************************************************/ 9907 static __attribute__ ((noinline)) void 9908 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9909 { 9910 struct mbuf *m; 9911 9912 BCE_PRINTF( 9913 "----------------------------" 9914 " tx mbuf data " 9915 "----------------------------\n"); 9916 9917 for (int i = 0; i < count; i++) { 9918 m = sc->tx_mbuf_ptr[chain_prod]; 9919 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9920 bce_dump_mbuf(sc, m); 9921 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9922 } 9923 9924 BCE_PRINTF( 9925 "----------------------------" 9926 "----------------" 9927 "----------------------------\n"); 9928 } 9929 9930 9931 /****************************************************************************/ 9932 /* Prints out the mbufs in the RX mbuf chain. */ 9933 /* */ 9934 /* Returns: */ 9935 /* Nothing. */ 9936 /****************************************************************************/ 9937 static __attribute__ ((noinline)) void 9938 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9939 { 9940 struct mbuf *m; 9941 9942 BCE_PRINTF( 9943 "----------------------------" 9944 " rx mbuf data " 9945 "----------------------------\n"); 9946 9947 for (int i = 0; i < count; i++) { 9948 m = sc->rx_mbuf_ptr[chain_prod]; 9949 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9950 bce_dump_mbuf(sc, m); 9951 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9952 } 9953 9954 9955 BCE_PRINTF( 9956 "----------------------------" 9957 "----------------" 9958 "----------------------------\n"); 9959 } 9960 9961 9962 /****************************************************************************/ 9963 /* Prints out the mbufs in the mbuf page chain. */ 9964 /* */ 9965 /* Returns: */ 9966 /* Nothing. */ 9967 /****************************************************************************/ 9968 static __attribute__ ((noinline)) void 9969 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9970 { 9971 struct mbuf *m; 9972 9973 BCE_PRINTF( 9974 "----------------------------" 9975 " pg mbuf data " 9976 "----------------------------\n"); 9977 9978 for (int i = 0; i < count; i++) { 9979 m = sc->pg_mbuf_ptr[chain_prod]; 9980 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9981 bce_dump_mbuf(sc, m); 9982 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9983 } 9984 9985 9986 BCE_PRINTF( 9987 "----------------------------" 9988 "----------------" 9989 "----------------------------\n"); 9990 } 9991 9992 9993 /****************************************************************************/ 9994 /* Prints out a tx_bd structure. */ 9995 /* */ 9996 /* Returns: */ 9997 /* Nothing. */ 9998 /****************************************************************************/ 9999 static __attribute__ ((noinline)) void 10000 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 10001 { 10002 int i = 0; 10003 10004 if (idx > MAX_TX_BD_ALLOC) 10005 /* Index out of range. */ 10006 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 10007 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 10008 /* TX Chain page pointer. */ 10009 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10010 "pointer\n", idx, txbd->tx_bd_haddr_hi, 10011 txbd->tx_bd_haddr_lo); 10012 else { 10013 /* Normal tx_bd entry. */ 10014 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 10015 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 10016 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 10017 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 10018 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 10019 10020 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 10021 if (i>0) 10022 printf("|"); 10023 printf("CONN_FAULT"); 10024 i++; 10025 } 10026 10027 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 10028 if (i>0) 10029 printf("|"); 10030 printf("TCP_UDP_CKSUM"); 10031 i++; 10032 } 10033 10034 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 10035 if (i>0) 10036 printf("|"); 10037 printf("IP_CKSUM"); 10038 i++; 10039 } 10040 10041 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 10042 if (i>0) 10043 printf("|"); 10044 printf("VLAN"); 10045 i++; 10046 } 10047 10048 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 10049 if (i>0) 10050 printf("|"); 10051 printf("COAL_NOW"); 10052 i++; 10053 } 10054 10055 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 10056 if (i>0) 10057 printf("|"); 10058 printf("DONT_GEN_CRC"); 10059 i++; 10060 } 10061 10062 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 10063 if (i>0) 10064 printf("|"); 10065 printf("START"); 10066 i++; 10067 } 10068 10069 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 10070 if (i>0) 10071 printf("|"); 10072 printf("END"); 10073 i++; 10074 } 10075 10076 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 10077 if (i>0) 10078 printf("|"); 10079 printf("LSO"); 10080 i++; 10081 } 10082 10083 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 10084 if (i>0) 10085 printf("|"); 10086 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 10087 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 10088 } 10089 10090 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 10091 if (i>0) 10092 printf("|"); 10093 printf("SW_FLAGS"); 10094 i++; 10095 } 10096 10097 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 10098 if (i>0) 10099 printf("|"); 10100 printf("SNAP)"); 10101 } else { 10102 printf(")\n"); 10103 } 10104 } 10105 } 10106 10107 10108 /****************************************************************************/ 10109 /* Prints out a rx_bd structure. */ 10110 /* */ 10111 /* Returns: */ 10112 /* Nothing. */ 10113 /****************************************************************************/ 10114 static __attribute__ ((noinline)) void 10115 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 10116 { 10117 if (idx > MAX_RX_BD_ALLOC) 10118 /* Index out of range. */ 10119 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 10120 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 10121 /* RX Chain page pointer. */ 10122 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10123 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 10124 rxbd->rx_bd_haddr_lo); 10125 else 10126 /* Normal rx_bd entry. */ 10127 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 10128 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 10129 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 10130 rxbd->rx_bd_flags); 10131 } 10132 10133 10134 /****************************************************************************/ 10135 /* Prints out a rx_bd structure in the page chain. */ 10136 /* */ 10137 /* Returns: */ 10138 /* Nothing. */ 10139 /****************************************************************************/ 10140 static __attribute__ ((noinline)) void 10141 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 10142 { 10143 if (idx > MAX_PG_BD_ALLOC) 10144 /* Index out of range. */ 10145 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 10146 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 10147 /* Page Chain page pointer. */ 10148 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 10149 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 10150 else 10151 /* Normal rx_bd entry. */ 10152 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 10153 "flags = 0x%08X\n", idx, 10154 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 10155 pgbd->rx_bd_len, pgbd->rx_bd_flags); 10156 } 10157 10158 10159 /****************************************************************************/ 10160 /* Prints out a l2_fhdr structure. */ 10161 /* */ 10162 /* Returns: */ 10163 /* Nothing. */ 10164 /****************************************************************************/ 10165 static __attribute__ ((noinline)) void 10166 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 10167 { 10168 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 10169 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 10170 "tcp_udp_xsum = 0x%04X\n", idx, 10171 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 10172 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 10173 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 10174 } 10175 10176 10177 /****************************************************************************/ 10178 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 10179 /* */ 10180 /* Returns: */ 10181 /* Nothing. */ 10182 /****************************************************************************/ 10183 static __attribute__ ((noinline)) void 10184 bce_dump_ctx(struct bce_softc *sc, u16 cid) 10185 { 10186 if (cid > TX_CID) { 10187 BCE_PRINTF(" Unknown CID\n"); 10188 return; 10189 } 10190 10191 BCE_PRINTF( 10192 "----------------------------" 10193 " CTX Data " 10194 "----------------------------\n"); 10195 10196 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 10197 10198 if (cid == RX_CID) { 10199 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 10200 "producer index\n", 10201 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10202 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10203 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10204 BCE_L2CTX_RX_HOST_BSEQ)); 10205 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10206 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10207 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10208 "descriptor address\n", 10209 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10210 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10211 "descriptor address\n", 10212 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10213 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10214 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10215 BCE_L2CTX_RX_NX_BDIDX)); 10216 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10217 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10218 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10219 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10220 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10221 BCE_L2CTX_RX_PG_BUF_SIZE)); 10222 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10223 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10224 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10225 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10226 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10227 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10228 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10229 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10230 BCE_L2CTX_RX_NX_PG_BDIDX)); 10231 } else if (cid == TX_CID) { 10232 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10233 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10234 CTX_RD(sc, GET_CID_ADDR(cid), 10235 BCE_L2CTX_TX_TYPE_XI)); 10236 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10237 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10238 BCE_L2CTX_TX_CMD_TYPE_XI)); 10239 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10240 "h/w buffer descriptor address\n", 10241 CTX_RD(sc, GET_CID_ADDR(cid), 10242 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10243 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10244 "h/w buffer descriptor address\n", 10245 CTX_RD(sc, GET_CID_ADDR(cid), 10246 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10247 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10248 "host producer index\n", 10249 CTX_RD(sc, GET_CID_ADDR(cid), 10250 BCE_L2CTX_TX_HOST_BIDX_XI)); 10251 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10252 "host byte sequence\n", 10253 CTX_RD(sc, GET_CID_ADDR(cid), 10254 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10255 } else { 10256 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10257 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10258 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10259 CTX_RD(sc, GET_CID_ADDR(cid), 10260 BCE_L2CTX_TX_CMD_TYPE)); 10261 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10262 "h/w buffer descriptor address\n", 10263 CTX_RD(sc, GET_CID_ADDR(cid), 10264 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10265 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10266 "h/w buffer descriptor address\n", 10267 CTX_RD(sc, GET_CID_ADDR(cid), 10268 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10269 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10270 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10271 BCE_L2CTX_TX_HOST_BIDX)); 10272 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10273 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10274 BCE_L2CTX_TX_HOST_BSEQ)); 10275 } 10276 } 10277 10278 BCE_PRINTF( 10279 "----------------------------" 10280 " Raw CTX " 10281 "----------------------------\n"); 10282 10283 for (int i = 0x0; i < 0x300; i += 0x10) { 10284 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10285 CTX_RD(sc, GET_CID_ADDR(cid), i), 10286 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10287 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10288 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10289 } 10290 10291 10292 BCE_PRINTF( 10293 "----------------------------" 10294 "----------------" 10295 "----------------------------\n"); 10296 } 10297 10298 10299 /****************************************************************************/ 10300 /* Prints out the FTQ data. */ 10301 /* */ 10302 /* Returns: */ 10303 /* Nothing. */ 10304 /****************************************************************************/ 10305 static __attribute__ ((noinline)) void 10306 bce_dump_ftqs(struct bce_softc *sc) 10307 { 10308 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10309 10310 BCE_PRINTF( 10311 "----------------------------" 10312 " FTQ Data " 10313 "----------------------------\n"); 10314 10315 BCE_PRINTF(" FTQ Command Control Depth_Now " 10316 "Max_Depth Valid_Cnt \n"); 10317 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10318 "---------- ----------\n"); 10319 10320 /* Setup the generic statistic counters for the FTQ valid count. */ 10321 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10322 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10323 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10324 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10325 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10326 10327 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10328 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10329 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10330 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10331 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10332 10333 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10334 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10335 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10336 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10337 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10338 10339 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10340 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10341 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10342 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10343 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10344 10345 /* Input queue to the Receive Lookup state machine */ 10346 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10347 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10348 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10349 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10350 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10351 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10352 cmd, ctl, cur_depth, max_depth, valid_cnt); 10353 10354 /* Input queue to the Receive Processor */ 10355 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10356 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10357 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10358 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10359 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10360 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10361 cmd, ctl, cur_depth, max_depth, valid_cnt); 10362 10363 /* Input queue to the Recevie Processor */ 10364 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10365 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10366 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10367 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10368 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10369 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10370 cmd, ctl, cur_depth, max_depth, valid_cnt); 10371 10372 /* Input queue to the Receive Virtual to Physical state machine */ 10373 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10374 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10375 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10376 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10377 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10378 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10379 cmd, ctl, cur_depth, max_depth, valid_cnt); 10380 10381 /* Input queue to the Recevie Virtual to Physical state machine */ 10382 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10383 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10384 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10385 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10386 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10387 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10388 cmd, ctl, cur_depth, max_depth, valid_cnt); 10389 10390 /* Input queue to the Receive Virtual to Physical state machine */ 10391 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10392 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10393 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10394 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10395 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10396 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10397 cmd, ctl, cur_depth, max_depth, valid_cnt); 10398 10399 /* Input queue to the Receive DMA state machine */ 10400 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10401 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10402 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10403 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10404 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10405 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10406 cmd, ctl, cur_depth, max_depth, valid_cnt); 10407 10408 /* Input queue to the Transmit Scheduler state machine */ 10409 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10410 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10411 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10412 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10413 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10414 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10415 cmd, ctl, cur_depth, max_depth, valid_cnt); 10416 10417 /* Input queue to the Transmit Buffer Descriptor state machine */ 10418 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10419 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10420 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10421 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10422 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10423 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10424 cmd, ctl, cur_depth, max_depth, valid_cnt); 10425 10426 /* Input queue to the Transmit Processor */ 10427 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10428 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10429 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10430 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10431 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10432 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10433 cmd, ctl, cur_depth, max_depth, valid_cnt); 10434 10435 /* Input queue to the Transmit DMA state machine */ 10436 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10437 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10438 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10439 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10440 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10441 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10442 cmd, ctl, cur_depth, max_depth, valid_cnt); 10443 10444 /* Input queue to the Transmit Patch-Up Processor */ 10445 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10446 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10447 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10448 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10449 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10450 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10451 cmd, ctl, cur_depth, max_depth, valid_cnt); 10452 10453 /* Input queue to the Transmit Assembler state machine */ 10454 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10455 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10456 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10457 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10458 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10459 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10460 cmd, ctl, cur_depth, max_depth, valid_cnt); 10461 10462 /* Input queue to the Completion Processor */ 10463 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10464 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10465 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10466 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10467 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10468 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10469 cmd, ctl, cur_depth, max_depth, valid_cnt); 10470 10471 /* Input queue to the Completion Processor */ 10472 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10473 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10474 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10475 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10476 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10477 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10478 cmd, ctl, cur_depth, max_depth, valid_cnt); 10479 10480 /* Input queue to the Completion Processor */ 10481 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10482 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10483 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10484 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10485 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10486 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10487 cmd, ctl, cur_depth, max_depth, valid_cnt); 10488 10489 /* Setup the generic statistic counters for the FTQ valid count. */ 10490 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10491 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10492 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10493 10494 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10495 val = val | 10496 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10497 24); 10498 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10499 10500 /* Input queue to the Management Control Processor */ 10501 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10502 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10503 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10504 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10505 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10506 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10507 cmd, ctl, cur_depth, max_depth, valid_cnt); 10508 10509 /* Input queue to the Command Processor */ 10510 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10511 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10512 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10513 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10514 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10515 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10516 cmd, ctl, cur_depth, max_depth, valid_cnt); 10517 10518 /* Input queue to the Completion Scheduler state machine */ 10519 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10520 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10521 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10522 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10523 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10524 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10525 cmd, ctl, cur_depth, max_depth, valid_cnt); 10526 10527 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10528 /* Input queue to the RV2P Command Scheduler */ 10529 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10530 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10531 cur_depth = (ctl & 0xFFC00000) >> 22; 10532 max_depth = (ctl & 0x003FF000) >> 12; 10533 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10534 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10535 cmd, ctl, cur_depth, max_depth, valid_cnt); 10536 } 10537 10538 BCE_PRINTF( 10539 "----------------------------" 10540 "----------------" 10541 "----------------------------\n"); 10542 } 10543 10544 10545 /****************************************************************************/ 10546 /* Prints out the TX chain. */ 10547 /* */ 10548 /* Returns: */ 10549 /* Nothing. */ 10550 /****************************************************************************/ 10551 static __attribute__ ((noinline)) void 10552 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10553 { 10554 struct tx_bd *txbd; 10555 10556 /* First some info about the tx_bd chain structure. */ 10557 BCE_PRINTF( 10558 "----------------------------" 10559 " tx_bd chain " 10560 "----------------------------\n"); 10561 10562 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10563 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10564 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10565 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10566 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10567 10568 BCE_PRINTF( 10569 "----------------------------" 10570 " tx_bd data " 10571 "----------------------------\n"); 10572 10573 /* Now print out a decoded list of TX buffer descriptors. */ 10574 for (int i = 0; i < count; i++) { 10575 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10576 bce_dump_txbd(sc, tx_prod, txbd); 10577 tx_prod++; 10578 } 10579 10580 BCE_PRINTF( 10581 "----------------------------" 10582 "----------------" 10583 "----------------------------\n"); 10584 } 10585 10586 10587 /****************************************************************************/ 10588 /* Prints out the RX chain. */ 10589 /* */ 10590 /* Returns: */ 10591 /* Nothing. */ 10592 /****************************************************************************/ 10593 static __attribute__ ((noinline)) void 10594 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10595 { 10596 struct rx_bd *rxbd; 10597 10598 /* First some info about the rx_bd chain structure. */ 10599 BCE_PRINTF( 10600 "----------------------------" 10601 " rx_bd chain " 10602 "----------------------------\n"); 10603 10604 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10605 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10606 10607 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10608 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10609 10610 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10611 10612 BCE_PRINTF( 10613 "----------------------------" 10614 " rx_bd data " 10615 "----------------------------\n"); 10616 10617 /* Now print out the rx_bd's themselves. */ 10618 for (int i = 0; i < count; i++) { 10619 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10620 bce_dump_rxbd(sc, rx_prod, rxbd); 10621 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10622 } 10623 10624 BCE_PRINTF( 10625 "----------------------------" 10626 "----------------" 10627 "----------------------------\n"); 10628 } 10629 10630 10631 /****************************************************************************/ 10632 /* Prints out the page chain. */ 10633 /* */ 10634 /* Returns: */ 10635 /* Nothing. */ 10636 /****************************************************************************/ 10637 static __attribute__ ((noinline)) void 10638 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10639 { 10640 struct rx_bd *pgbd; 10641 10642 /* First some info about the page chain structure. */ 10643 BCE_PRINTF( 10644 "----------------------------" 10645 " page chain " 10646 "----------------------------\n"); 10647 10648 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10649 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10650 10651 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10652 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10653 10654 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10655 10656 BCE_PRINTF( 10657 "----------------------------" 10658 " page data " 10659 "----------------------------\n"); 10660 10661 /* Now print out the rx_bd's themselves. */ 10662 for (int i = 0; i < count; i++) { 10663 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10664 bce_dump_pgbd(sc, pg_prod, pgbd); 10665 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10666 } 10667 10668 BCE_PRINTF( 10669 "----------------------------" 10670 "----------------" 10671 "----------------------------\n"); 10672 } 10673 10674 10675 #define BCE_PRINT_RX_CONS(arg) \ 10676 if (sblk->status_rx_quick_consumer_index##arg) \ 10677 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10678 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10679 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10680 arg); 10681 10682 10683 #define BCE_PRINT_TX_CONS(arg) \ 10684 if (sblk->status_tx_quick_consumer_index##arg) \ 10685 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10686 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10687 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10688 arg); 10689 10690 /****************************************************************************/ 10691 /* Prints out the status block from host memory. */ 10692 /* */ 10693 /* Returns: */ 10694 /* Nothing. */ 10695 /****************************************************************************/ 10696 static __attribute__ ((noinline)) void 10697 bce_dump_status_block(struct bce_softc *sc) 10698 { 10699 struct status_block *sblk; 10700 10701 sblk = sc->status_block; 10702 10703 BCE_PRINTF( 10704 "----------------------------" 10705 " Status Block " 10706 "----------------------------\n"); 10707 10708 /* Theses indices are used for normal L2 drivers. */ 10709 BCE_PRINTF(" 0x%08X - attn_bits\n", 10710 sblk->status_attn_bits); 10711 10712 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10713 sblk->status_attn_bits_ack); 10714 10715 BCE_PRINT_RX_CONS(0); 10716 BCE_PRINT_TX_CONS(0) 10717 10718 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10719 10720 /* Theses indices are not used for normal L2 drivers. */ 10721 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10722 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10723 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10724 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10725 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10726 10727 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10728 10729 if (sblk->status_completion_producer_index || 10730 sblk->status_cmd_consumer_index) 10731 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10732 sblk->status_completion_producer_index, 10733 sblk->status_cmd_consumer_index); 10734 10735 BCE_PRINTF( 10736 "----------------------------" 10737 "----------------" 10738 "----------------------------\n"); 10739 } 10740 10741 10742 #define BCE_PRINT_64BIT_STAT(arg) \ 10743 if (sblk->arg##_lo || sblk->arg##_hi) \ 10744 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10745 sblk->arg##_lo, #arg); 10746 10747 #define BCE_PRINT_32BIT_STAT(arg) \ 10748 if (sblk->arg) \ 10749 BCE_PRINTF(" 0x%08X : %s\n", \ 10750 sblk->arg, #arg); 10751 10752 /****************************************************************************/ 10753 /* Prints out the statistics block from host memory. */ 10754 /* */ 10755 /* Returns: */ 10756 /* Nothing. */ 10757 /****************************************************************************/ 10758 static __attribute__ ((noinline)) void 10759 bce_dump_stats_block(struct bce_softc *sc) 10760 { 10761 struct statistics_block *sblk; 10762 10763 sblk = sc->stats_block; 10764 10765 BCE_PRINTF( 10766 "---------------" 10767 " Stats Block (All Stats Not Shown Are 0) " 10768 "---------------\n"); 10769 10770 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10771 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10772 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10773 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10774 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10775 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10776 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10777 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10778 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10779 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10780 BCE_PRINT_32BIT_STAT( 10781 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10782 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10783 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10784 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10785 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10786 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10787 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10788 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10789 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10790 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10791 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10792 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10793 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10794 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10795 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10796 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10797 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10798 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10799 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10800 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10801 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10802 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10803 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10804 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10805 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10806 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10807 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10808 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10809 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10810 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10811 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10812 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10813 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10814 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10815 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10816 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10817 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10818 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10819 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10820 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10821 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10822 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10823 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10824 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10825 10826 BCE_PRINTF( 10827 "----------------------------" 10828 "----------------" 10829 "----------------------------\n"); 10830 } 10831 10832 10833 /****************************************************************************/ 10834 /* Prints out a summary of the driver state. */ 10835 /* */ 10836 /* Returns: */ 10837 /* Nothing. */ 10838 /****************************************************************************/ 10839 static __attribute__ ((noinline)) void 10840 bce_dump_driver_state(struct bce_softc *sc) 10841 { 10842 u32 val_hi, val_lo; 10843 10844 BCE_PRINTF( 10845 "-----------------------------" 10846 " Driver State " 10847 "-----------------------------\n"); 10848 10849 val_hi = BCE_ADDR_HI(sc); 10850 val_lo = BCE_ADDR_LO(sc); 10851 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10852 "address\n", val_hi, val_lo); 10853 10854 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10855 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10856 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10857 "address\n", val_hi, val_lo); 10858 10859 val_hi = BCE_ADDR_HI(sc->status_block); 10860 val_lo = BCE_ADDR_LO(sc->status_block); 10861 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10862 "virtual address\n", val_hi, val_lo); 10863 10864 val_hi = BCE_ADDR_HI(sc->stats_block); 10865 val_lo = BCE_ADDR_LO(sc->stats_block); 10866 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10867 "virtual address\n", val_hi, val_lo); 10868 10869 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10870 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10871 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10872 "virtual adddress\n", val_hi, val_lo); 10873 10874 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10875 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10876 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10877 "virtual address\n", val_hi, val_lo); 10878 10879 if (bce_hdr_split == TRUE) { 10880 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10881 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10882 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10883 "virtual address\n", val_hi, val_lo); 10884 } 10885 10886 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10887 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10888 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10889 "virtual address\n", val_hi, val_lo); 10890 10891 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10892 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10893 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10894 "virtual address\n", val_hi, val_lo); 10895 10896 if (bce_hdr_split == TRUE) { 10897 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10898 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10899 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10900 "virtual address\n", val_hi, val_lo); 10901 } 10902 10903 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10904 "h/w intrs\n", 10905 (long long unsigned int) sc->interrupts_generated); 10906 10907 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10908 "rx interrupts handled\n", 10909 (long long unsigned int) sc->interrupts_rx); 10910 10911 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10912 "tx interrupts handled\n", 10913 (long long unsigned int) sc->interrupts_tx); 10914 10915 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10916 "phy interrupts handled\n", 10917 (long long unsigned int) sc->phy_interrupts); 10918 10919 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10920 "status block index\n", sc->last_status_idx); 10921 10922 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10923 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10924 10925 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10926 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10927 10928 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10929 "byte seq index\n", sc->tx_prod_bseq); 10930 10931 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10932 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10933 10934 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10935 "tx_bd's\n", sc->used_tx_bd); 10936 10937 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10938 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10939 10940 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10941 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10942 10943 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10944 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10945 10946 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10947 "byte seq index\n", sc->rx_prod_bseq); 10948 10949 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10950 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10951 10952 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10953 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10954 10955 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10956 "rx_bd's\n", sc->free_rx_bd); 10957 10958 if (bce_hdr_split == TRUE) { 10959 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10960 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10961 10962 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10963 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10964 10965 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10966 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10967 } 10968 10969 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10970 "rx_bd's\n", sc->free_pg_bd); 10971 10972 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10973 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10974 10975 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10976 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10977 10978 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10979 "bce mac flags\n", sc->bce_flags); 10980 10981 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10982 "bce phy flags\n", sc->bce_phy_flags); 10983 10984 BCE_PRINTF( 10985 "----------------------------" 10986 "----------------" 10987 "----------------------------\n"); 10988 } 10989 10990 10991 /****************************************************************************/ 10992 /* Prints out the hardware state through a summary of important register, */ 10993 /* followed by a complete register dump. */ 10994 /* */ 10995 /* Returns: */ 10996 /* Nothing. */ 10997 /****************************************************************************/ 10998 static __attribute__ ((noinline)) void 10999 bce_dump_hw_state(struct bce_softc *sc) 11000 { 11001 u32 val; 11002 11003 BCE_PRINTF( 11004 "----------------------------" 11005 " Hardware State " 11006 "----------------------------\n"); 11007 11008 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11009 11010 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 11011 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 11012 val, BCE_MISC_ENABLE_STATUS_BITS); 11013 11014 val = REG_RD(sc, BCE_DMA_STATUS); 11015 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 11016 val, BCE_DMA_STATUS); 11017 11018 val = REG_RD(sc, BCE_CTX_STATUS); 11019 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 11020 val, BCE_CTX_STATUS); 11021 11022 val = REG_RD(sc, BCE_EMAC_STATUS); 11023 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 11024 val, BCE_EMAC_STATUS); 11025 11026 val = REG_RD(sc, BCE_RPM_STATUS); 11027 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 11028 val, BCE_RPM_STATUS); 11029 11030 /* ToDo: Create a #define for this constant. */ 11031 val = REG_RD(sc, 0x2004); 11032 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 11033 val, 0x2004); 11034 11035 val = REG_RD(sc, BCE_RV2P_STATUS); 11036 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 11037 val, BCE_RV2P_STATUS); 11038 11039 /* ToDo: Create a #define for this constant. */ 11040 val = REG_RD(sc, 0x2c04); 11041 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 11042 val, 0x2c04); 11043 11044 val = REG_RD(sc, BCE_TBDR_STATUS); 11045 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 11046 val, BCE_TBDR_STATUS); 11047 11048 val = REG_RD(sc, BCE_TDMA_STATUS); 11049 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 11050 val, BCE_TDMA_STATUS); 11051 11052 val = REG_RD(sc, BCE_HC_STATUS); 11053 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 11054 val, BCE_HC_STATUS); 11055 11056 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11057 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11058 val, BCE_TXP_CPU_STATE); 11059 11060 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11061 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11062 val, BCE_TPAT_CPU_STATE); 11063 11064 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11065 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11066 val, BCE_RXP_CPU_STATE); 11067 11068 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11069 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11070 val, BCE_COM_CPU_STATE); 11071 11072 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 11073 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 11074 val, BCE_MCP_CPU_STATE); 11075 11076 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11077 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11078 val, BCE_CP_CPU_STATE); 11079 11080 BCE_PRINTF( 11081 "----------------------------" 11082 "----------------" 11083 "----------------------------\n"); 11084 11085 BCE_PRINTF( 11086 "----------------------------" 11087 " Register Dump " 11088 "----------------------------\n"); 11089 11090 for (int i = 0x400; i < 0x8000; i += 0x10) { 11091 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11092 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11093 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11094 } 11095 11096 BCE_PRINTF( 11097 "----------------------------" 11098 "----------------" 11099 "----------------------------\n"); 11100 } 11101 11102 11103 /****************************************************************************/ 11104 /* Prints out the contentst of shared memory which is used for host driver */ 11105 /* to bootcode firmware communication. */ 11106 /* */ 11107 /* Returns: */ 11108 /* Nothing. */ 11109 /****************************************************************************/ 11110 static __attribute__ ((noinline)) void 11111 bce_dump_shmem_state(struct bce_softc *sc) 11112 { 11113 BCE_PRINTF( 11114 "----------------------------" 11115 " Hardware State " 11116 "----------------------------\n"); 11117 11118 BCE_PRINTF("0x%08X - Shared memory base address\n", 11119 sc->bce_shmem_base); 11120 BCE_PRINTF("%s - bootcode version\n", 11121 sc->bce_bc_ver); 11122 11123 BCE_PRINTF( 11124 "----------------------------" 11125 " Shared Mem " 11126 "----------------------------\n"); 11127 11128 for (int i = 0x0; i < 0x200; i += 0x10) { 11129 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11130 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 11131 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 11132 } 11133 11134 BCE_PRINTF( 11135 "----------------------------" 11136 "----------------" 11137 "----------------------------\n"); 11138 } 11139 11140 11141 /****************************************************************************/ 11142 /* Prints out the mailbox queue registers. */ 11143 /* */ 11144 /* Returns: */ 11145 /* Nothing. */ 11146 /****************************************************************************/ 11147 static __attribute__ ((noinline)) void 11148 bce_dump_mq_regs(struct bce_softc *sc) 11149 { 11150 BCE_PRINTF( 11151 "----------------------------" 11152 " MQ Regs " 11153 "----------------------------\n"); 11154 11155 BCE_PRINTF( 11156 "----------------------------" 11157 "----------------" 11158 "----------------------------\n"); 11159 11160 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 11161 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11162 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11163 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11164 } 11165 11166 BCE_PRINTF( 11167 "----------------------------" 11168 "----------------" 11169 "----------------------------\n"); 11170 } 11171 11172 11173 /****************************************************************************/ 11174 /* Prints out the bootcode state. */ 11175 /* */ 11176 /* Returns: */ 11177 /* Nothing. */ 11178 /****************************************************************************/ 11179 static __attribute__ ((noinline)) void 11180 bce_dump_bc_state(struct bce_softc *sc) 11181 { 11182 u32 val; 11183 11184 BCE_PRINTF( 11185 "----------------------------" 11186 " Bootcode State " 11187 "----------------------------\n"); 11188 11189 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11190 11191 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 11192 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 11193 val, BCE_BC_RESET_TYPE); 11194 11195 val = bce_shmem_rd(sc, BCE_BC_STATE); 11196 BCE_PRINTF("0x%08X - (0x%06X) state\n", 11197 val, BCE_BC_STATE); 11198 11199 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 11200 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 11201 val, BCE_BC_STATE_CONDITION); 11202 11203 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 11204 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 11205 val, BCE_BC_STATE_DEBUG_CMD); 11206 11207 BCE_PRINTF( 11208 "----------------------------" 11209 "----------------" 11210 "----------------------------\n"); 11211 } 11212 11213 11214 /****************************************************************************/ 11215 /* Prints out the TXP processor state. */ 11216 /* */ 11217 /* Returns: */ 11218 /* Nothing. */ 11219 /****************************************************************************/ 11220 static __attribute__ ((noinline)) void 11221 bce_dump_txp_state(struct bce_softc *sc, int regs) 11222 { 11223 u32 val; 11224 u32 fw_version[3]; 11225 11226 BCE_PRINTF( 11227 "----------------------------" 11228 " TXP State " 11229 "----------------------------\n"); 11230 11231 for (int i = 0; i < 3; i++) 11232 fw_version[i] = htonl(REG_RD_IND(sc, 11233 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11234 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11235 11236 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11237 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11238 val, BCE_TXP_CPU_MODE); 11239 11240 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11241 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11242 val, BCE_TXP_CPU_STATE); 11243 11244 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11245 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11246 val, BCE_TXP_CPU_EVENT_MASK); 11247 11248 if (regs) { 11249 BCE_PRINTF( 11250 "----------------------------" 11251 " Register Dump " 11252 "----------------------------\n"); 11253 11254 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11255 /* Skip the big blank spaces */ 11256 if (i < 0x454000 && i > 0x5ffff) 11257 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11258 "0x%08X 0x%08X\n", i, 11259 REG_RD_IND(sc, i), 11260 REG_RD_IND(sc, i + 0x4), 11261 REG_RD_IND(sc, i + 0x8), 11262 REG_RD_IND(sc, i + 0xC)); 11263 } 11264 } 11265 11266 BCE_PRINTF( 11267 "----------------------------" 11268 "----------------" 11269 "----------------------------\n"); 11270 } 11271 11272 11273 /****************************************************************************/ 11274 /* Prints out the RXP processor state. */ 11275 /* */ 11276 /* Returns: */ 11277 /* Nothing. */ 11278 /****************************************************************************/ 11279 static __attribute__ ((noinline)) void 11280 bce_dump_rxp_state(struct bce_softc *sc, int regs) 11281 { 11282 u32 val; 11283 u32 fw_version[3]; 11284 11285 BCE_PRINTF( 11286 "----------------------------" 11287 " RXP State " 11288 "----------------------------\n"); 11289 11290 for (int i = 0; i < 3; i++) 11291 fw_version[i] = htonl(REG_RD_IND(sc, 11292 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11293 11294 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11295 11296 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11297 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11298 val, BCE_RXP_CPU_MODE); 11299 11300 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11301 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11302 val, BCE_RXP_CPU_STATE); 11303 11304 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11305 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11306 val, BCE_RXP_CPU_EVENT_MASK); 11307 11308 if (regs) { 11309 BCE_PRINTF( 11310 "----------------------------" 11311 " Register Dump " 11312 "----------------------------\n"); 11313 11314 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11315 /* Skip the big blank sapces */ 11316 if (i < 0xc5400 && i > 0xdffff) 11317 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11318 "0x%08X 0x%08X\n", i, 11319 REG_RD_IND(sc, i), 11320 REG_RD_IND(sc, i + 0x4), 11321 REG_RD_IND(sc, i + 0x8), 11322 REG_RD_IND(sc, i + 0xC)); 11323 } 11324 } 11325 11326 BCE_PRINTF( 11327 "----------------------------" 11328 "----------------" 11329 "----------------------------\n"); 11330 } 11331 11332 11333 /****************************************************************************/ 11334 /* Prints out the TPAT processor state. */ 11335 /* */ 11336 /* Returns: */ 11337 /* Nothing. */ 11338 /****************************************************************************/ 11339 static __attribute__ ((noinline)) void 11340 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11341 { 11342 u32 val; 11343 u32 fw_version[3]; 11344 11345 BCE_PRINTF( 11346 "----------------------------" 11347 " TPAT State " 11348 "----------------------------\n"); 11349 11350 for (int i = 0; i < 3; i++) 11351 fw_version[i] = htonl(REG_RD_IND(sc, 11352 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11353 11354 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11355 11356 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11357 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11358 val, BCE_TPAT_CPU_MODE); 11359 11360 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11361 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11362 val, BCE_TPAT_CPU_STATE); 11363 11364 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11365 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11366 val, BCE_TPAT_CPU_EVENT_MASK); 11367 11368 if (regs) { 11369 BCE_PRINTF( 11370 "----------------------------" 11371 " Register Dump " 11372 "----------------------------\n"); 11373 11374 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11375 /* Skip the big blank spaces */ 11376 if (i < 0x854000 && i > 0x9ffff) 11377 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11378 "0x%08X 0x%08X\n", i, 11379 REG_RD_IND(sc, i), 11380 REG_RD_IND(sc, i + 0x4), 11381 REG_RD_IND(sc, i + 0x8), 11382 REG_RD_IND(sc, i + 0xC)); 11383 } 11384 } 11385 11386 BCE_PRINTF( 11387 "----------------------------" 11388 "----------------" 11389 "----------------------------\n"); 11390 } 11391 11392 11393 /****************************************************************************/ 11394 /* Prints out the Command Procesor (CP) state. */ 11395 /* */ 11396 /* Returns: */ 11397 /* Nothing. */ 11398 /****************************************************************************/ 11399 static __attribute__ ((noinline)) void 11400 bce_dump_cp_state(struct bce_softc *sc, int regs) 11401 { 11402 u32 val; 11403 u32 fw_version[3]; 11404 11405 BCE_PRINTF( 11406 "----------------------------" 11407 " CP State " 11408 "----------------------------\n"); 11409 11410 for (int i = 0; i < 3; i++) 11411 fw_version[i] = htonl(REG_RD_IND(sc, 11412 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11413 11414 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11415 11416 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11417 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11418 val, BCE_CP_CPU_MODE); 11419 11420 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11421 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11422 val, BCE_CP_CPU_STATE); 11423 11424 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11425 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11426 BCE_CP_CPU_EVENT_MASK); 11427 11428 if (regs) { 11429 BCE_PRINTF( 11430 "----------------------------" 11431 " Register Dump " 11432 "----------------------------\n"); 11433 11434 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11435 /* Skip the big blank spaces */ 11436 if (i < 0x185400 && i > 0x19ffff) 11437 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11438 "0x%08X 0x%08X\n", i, 11439 REG_RD_IND(sc, i), 11440 REG_RD_IND(sc, i + 0x4), 11441 REG_RD_IND(sc, i + 0x8), 11442 REG_RD_IND(sc, i + 0xC)); 11443 } 11444 } 11445 11446 BCE_PRINTF( 11447 "----------------------------" 11448 "----------------" 11449 "----------------------------\n"); 11450 } 11451 11452 11453 /****************************************************************************/ 11454 /* Prints out the Completion Procesor (COM) state. */ 11455 /* */ 11456 /* Returns: */ 11457 /* Nothing. */ 11458 /****************************************************************************/ 11459 static __attribute__ ((noinline)) void 11460 bce_dump_com_state(struct bce_softc *sc, int regs) 11461 { 11462 u32 val; 11463 u32 fw_version[4]; 11464 11465 BCE_PRINTF( 11466 "----------------------------" 11467 " COM State " 11468 "----------------------------\n"); 11469 11470 for (int i = 0; i < 3; i++) 11471 fw_version[i] = htonl(REG_RD_IND(sc, 11472 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11473 11474 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11475 11476 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11477 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11478 val, BCE_COM_CPU_MODE); 11479 11480 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11481 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11482 val, BCE_COM_CPU_STATE); 11483 11484 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11485 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11486 BCE_COM_CPU_EVENT_MASK); 11487 11488 if (regs) { 11489 BCE_PRINTF( 11490 "----------------------------" 11491 " Register Dump " 11492 "----------------------------\n"); 11493 11494 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11495 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11496 "0x%08X 0x%08X\n", i, 11497 REG_RD_IND(sc, i), 11498 REG_RD_IND(sc, i + 0x4), 11499 REG_RD_IND(sc, i + 0x8), 11500 REG_RD_IND(sc, i + 0xC)); 11501 } 11502 } 11503 11504 BCE_PRINTF( 11505 "----------------------------" 11506 "----------------" 11507 "----------------------------\n"); 11508 } 11509 11510 11511 /****************************************************************************/ 11512 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11513 /* */ 11514 /* Returns: */ 11515 /* Nothing. */ 11516 /****************************************************************************/ 11517 static __attribute__ ((noinline)) void 11518 bce_dump_rv2p_state(struct bce_softc *sc) 11519 { 11520 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11521 11522 BCE_PRINTF( 11523 "----------------------------" 11524 " RV2P State " 11525 "----------------------------\n"); 11526 11527 /* Stall the RV2P processors. */ 11528 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11529 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11530 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11531 11532 /* Read the firmware version. */ 11533 val = 0x00000001; 11534 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11535 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11536 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11537 BCE_RV2P_INSTR_HIGH_HIGH; 11538 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11539 fw_ver_high, fw_ver_low); 11540 11541 val = 0x00000001; 11542 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11543 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11544 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11545 BCE_RV2P_INSTR_HIGH_HIGH; 11546 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11547 fw_ver_high, fw_ver_low); 11548 11549 /* Resume the RV2P processors. */ 11550 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11551 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11552 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11553 11554 /* Fetch the program counter value. */ 11555 val = 0x68007800; 11556 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11557 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11558 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11559 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11560 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11561 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11562 11563 /* Fetch the program counter value again to see if it is advancing. */ 11564 val = 0x68007800; 11565 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11566 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11567 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11568 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11569 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11570 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11571 11572 BCE_PRINTF( 11573 "----------------------------" 11574 "----------------" 11575 "----------------------------\n"); 11576 } 11577 11578 11579 /****************************************************************************/ 11580 /* Prints out the driver state and then enters the debugger. */ 11581 /* */ 11582 /* Returns: */ 11583 /* Nothing. */ 11584 /****************************************************************************/ 11585 static __attribute__ ((noinline)) void 11586 bce_breakpoint(struct bce_softc *sc) 11587 { 11588 11589 /* 11590 * Unreachable code to silence compiler warnings 11591 * about unused functions. 11592 */ 11593 if (0) { 11594 bce_freeze_controller(sc); 11595 bce_unfreeze_controller(sc); 11596 bce_dump_enet(sc, NULL); 11597 bce_dump_txbd(sc, 0, NULL); 11598 bce_dump_rxbd(sc, 0, NULL); 11599 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11600 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11601 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11602 bce_dump_l2fhdr(sc, 0, NULL); 11603 bce_dump_ctx(sc, RX_CID); 11604 bce_dump_ftqs(sc); 11605 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11606 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11607 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11608 bce_dump_status_block(sc); 11609 bce_dump_stats_block(sc); 11610 bce_dump_driver_state(sc); 11611 bce_dump_hw_state(sc); 11612 bce_dump_bc_state(sc); 11613 bce_dump_txp_state(sc, 0); 11614 bce_dump_rxp_state(sc, 0); 11615 bce_dump_tpat_state(sc, 0); 11616 bce_dump_cp_state(sc, 0); 11617 bce_dump_com_state(sc, 0); 11618 bce_dump_rv2p_state(sc); 11619 bce_dump_pgbd(sc, 0, NULL); 11620 } 11621 11622 bce_dump_status_block(sc); 11623 bce_dump_driver_state(sc); 11624 11625 /* Call the debugger. */ 11626 breakpoint(); 11627 11628 return; 11629 } 11630 #endif 11631 11632