1 /*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54 #include "opt_bce.h" 55 56 #include <dev/bce/if_bcereg.h> 57 #include <dev/bce/if_bcefw.h> 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89 #endif 90 91 /****************************************************************************/ 92 /* BCE Build Time Options */ 93 /****************************************************************************/ 94 /* #define BCE_NVRAM_WRITE_SUPPORT 1 */ 95 96 97 /****************************************************************************/ 98 /* PCI Device ID Table */ 99 /* */ 100 /* Used by bce_probe() to identify the devices supported by this driver. */ 101 /****************************************************************************/ 102 #define BCE_DEVDESC_MAX 64 103 104 static struct bce_type bce_devs[] = { 105 /* BCM5706C Controllers and OEM boards. */ 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 107 "HP NC370T Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 109 "HP NC370i Multifunction Gigabit Server Adapter" }, 110 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 111 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 113 "HP NC371i Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 116 117 /* BCM5706S controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 119 "HP NC370F Multifunction Gigabit Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 121 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 122 123 /* BCM5708C controllers and OEM boards. */ 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 125 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 126 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 127 "HP NC373i Multifunction Gigabit Server Adapter" }, 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 129 "HP NC374m PCIe Multifunction Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 131 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 132 133 /* BCM5708S controllers and OEM boards. */ 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 135 "HP NC373m Multifunction Gigabit Server Adapter" }, 136 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 137 "HP NC373i Multifunction Gigabit Server Adapter" }, 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 139 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 141 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 142 143 /* BCM5709C controllers and OEM boards. */ 144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 145 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 147 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 149 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 150 151 /* BCM5709S controllers and OEM boards. */ 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 153 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 155 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 157 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 158 159 /* BCM5716 controllers and OEM boards. */ 160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 161 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 162 163 { 0, 0, 0, 0, NULL } 164 }; 165 166 167 /****************************************************************************/ 168 /* Supported Flash NVRAM device data. */ 169 /****************************************************************************/ 170 static struct flash_spec flash_table[] = 171 { 172 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 173 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 174 175 /* Slow EEPROM */ 176 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 177 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 178 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 179 "EEPROM - slow"}, 180 /* Expansion entry 0001 */ 181 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 184 "Entry 0001"}, 185 /* Saifun SA25F010 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 190 "Non-buffered flash (128kB)"}, 191 /* Saifun SA25F020 (non-buffered flash) */ 192 /* strap, cfg1, & write1 need updates */ 193 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 195 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 196 "Non-buffered flash (256kB)"}, 197 /* Expansion entry 0100 */ 198 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 199 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 200 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 201 "Entry 0100"}, 202 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 203 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 204 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 205 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 206 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 207 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 208 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 210 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 211 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 212 /* Saifun SA25F005 (non-buffered flash) */ 213 /* strap, cfg1, & write1 need updates */ 214 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 215 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 216 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 217 "Non-buffered flash (64kB)"}, 218 /* Fast EEPROM */ 219 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 220 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 221 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 222 "EEPROM - fast"}, 223 /* Expansion entry 1001 */ 224 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 225 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 226 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 227 "Entry 1001"}, 228 /* Expansion entry 1010 */ 229 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 230 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 231 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 232 "Entry 1010"}, 233 /* ATMEL AT45DB011B (buffered flash) */ 234 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 235 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 236 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 237 "Buffered flash (128kB)"}, 238 /* Expansion entry 1100 */ 239 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 240 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 241 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 242 "Entry 1100"}, 243 /* Expansion entry 1101 */ 244 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 245 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 246 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 247 "Entry 1101"}, 248 /* Ateml Expansion entry 1110 */ 249 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 250 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 251 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 252 "Entry 1110 (Atmel)"}, 253 /* ATMEL AT45DB021B (buffered flash) */ 254 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 255 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 256 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 257 "Buffered flash (256kB)"}, 258 }; 259 260 /* 261 * The BCM5709 controllers transparently handle the 262 * differences between Atmel 264 byte pages and all 263 * flash devices which use 256 byte pages, so no 264 * logical-to-physical mapping is required in the 265 * driver. 266 */ 267 static struct flash_spec flash_5709 = { 268 .flags = BCE_NV_BUFFERED, 269 .page_bits = BCM5709_FLASH_PAGE_BITS, 270 .page_size = BCM5709_FLASH_PAGE_SIZE, 271 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 272 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 273 .name = "5709/5716 buffered flash (256kB)", 274 }; 275 276 277 /****************************************************************************/ 278 /* FreeBSD device entry points. */ 279 /****************************************************************************/ 280 static int bce_probe (device_t); 281 static int bce_attach (device_t); 282 static int bce_detach (device_t); 283 static int bce_shutdown (device_t); 284 285 286 /****************************************************************************/ 287 /* BCE Debug Data Structure Dump Routines */ 288 /****************************************************************************/ 289 #ifdef BCE_DEBUG 290 static u32 bce_reg_rd (struct bce_softc *, u32); 291 static void bce_reg_wr (struct bce_softc *, u32, u32); 292 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 293 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 294 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 295 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 296 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 297 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 298 #ifdef BCE_JUMBO_HDRSPLIT 299 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 300 #endif 301 static void bce_dump_txbd (struct bce_softc *, 302 int, struct tx_bd *); 303 static void bce_dump_rxbd (struct bce_softc *, 304 int, struct rx_bd *); 305 #ifdef BCE_JUMBO_HDRSPLIT 306 static void bce_dump_pgbd (struct bce_softc *, 307 int, struct rx_bd *); 308 #endif 309 static void bce_dump_l2fhdr (struct bce_softc *, 310 int, struct l2_fhdr *); 311 static void bce_dump_ctx (struct bce_softc *, u16); 312 static void bce_dump_ftqs (struct bce_softc *); 313 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 314 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 315 #ifdef BCE_JUMBO_HDRSPLIT 316 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 317 #endif 318 static void bce_dump_status_block (struct bce_softc *); 319 static void bce_dump_stats_block (struct bce_softc *); 320 static void bce_dump_driver_state (struct bce_softc *); 321 static void bce_dump_hw_state (struct bce_softc *); 322 static void bce_dump_mq_regs (struct bce_softc *); 323 static void bce_dump_bc_state (struct bce_softc *); 324 static void bce_dump_txp_state (struct bce_softc *, int); 325 static void bce_dump_rxp_state (struct bce_softc *, int); 326 static void bce_dump_tpat_state (struct bce_softc *, int); 327 static void bce_dump_cp_state (struct bce_softc *, int); 328 static void bce_dump_com_state (struct bce_softc *, int); 329 static void bce_dump_rv2p_state (struct bce_softc *); 330 static void bce_breakpoint (struct bce_softc *); 331 #endif 332 333 334 /****************************************************************************/ 335 /* BCE Register/Memory Access Routines */ 336 /****************************************************************************/ 337 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 338 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 339 static void bce_shmem_wr (struct bce_softc *, u32, u32); 340 static u32 bce_shmem_rd (struct bce_softc *, u32); 341 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 342 static int bce_miibus_read_reg (device_t, int, int); 343 static int bce_miibus_write_reg (device_t, int, int, int); 344 static void bce_miibus_statchg (device_t); 345 346 347 /****************************************************************************/ 348 /* BCE NVRAM Access Routines */ 349 /****************************************************************************/ 350 static int bce_acquire_nvram_lock (struct bce_softc *); 351 static int bce_release_nvram_lock (struct bce_softc *); 352 static void bce_enable_nvram_access (struct bce_softc *); 353 static void bce_disable_nvram_access (struct bce_softc *); 354 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 355 static int bce_init_nvram (struct bce_softc *); 356 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 357 static int bce_nvram_test (struct bce_softc *); 358 #ifdef BCE_NVRAM_WRITE_SUPPORT 359 static int bce_enable_nvram_write (struct bce_softc *); 360 static void bce_disable_nvram_write (struct bce_softc *); 361 static int bce_nvram_erase_page (struct bce_softc *, u32); 362 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 363 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 364 #endif 365 366 /****************************************************************************/ 367 /* */ 368 /****************************************************************************/ 369 static void bce_get_media (struct bce_softc *); 370 static void bce_init_media (struct bce_softc *); 371 static void bce_dma_map_addr (void *, 372 bus_dma_segment_t *, int, int); 373 static int bce_dma_alloc (device_t); 374 static void bce_dma_free (struct bce_softc *); 375 static void bce_release_resources (struct bce_softc *); 376 377 /****************************************************************************/ 378 /* BCE Firmware Synchronization and Load */ 379 /****************************************************************************/ 380 static int bce_fw_sync (struct bce_softc *, u32); 381 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 382 static void bce_load_cpu_fw (struct bce_softc *, 383 struct cpu_reg *, struct fw_info *); 384 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 385 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 386 static void bce_start_rxp_cpu (struct bce_softc *); 387 static void bce_init_rxp_cpu (struct bce_softc *); 388 static void bce_init_txp_cpu (struct bce_softc *); 389 static void bce_init_tpat_cpu (struct bce_softc *); 390 static void bce_init_cp_cpu (struct bce_softc *); 391 static void bce_init_com_cpu (struct bce_softc *); 392 static void bce_init_cpus (struct bce_softc *); 393 394 static void bce_print_adapter_info (struct bce_softc *); 395 static void bce_probe_pci_caps (device_t, struct bce_softc *); 396 static void bce_stop (struct bce_softc *); 397 static int bce_reset (struct bce_softc *, u32); 398 static int bce_chipinit (struct bce_softc *); 399 static int bce_blockinit (struct bce_softc *); 400 401 static int bce_init_tx_chain (struct bce_softc *); 402 static void bce_free_tx_chain (struct bce_softc *); 403 404 static int bce_get_rx_buf (struct bce_softc *, 405 struct mbuf *, u16 *, u16 *, u32 *); 406 static int bce_init_rx_chain (struct bce_softc *); 407 static void bce_fill_rx_chain (struct bce_softc *); 408 static void bce_free_rx_chain (struct bce_softc *); 409 410 #ifdef BCE_JUMBO_HDRSPLIT 411 static int bce_get_pg_buf (struct bce_softc *, 412 struct mbuf *, u16 *, u16 *); 413 static int bce_init_pg_chain (struct bce_softc *); 414 static void bce_fill_pg_chain (struct bce_softc *); 415 static void bce_free_pg_chain (struct bce_softc *); 416 #endif 417 418 static struct mbuf *bce_tso_setup (struct bce_softc *, 419 struct mbuf **, u16 *); 420 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 421 static void bce_start_locked (struct ifnet *); 422 static void bce_start (struct ifnet *); 423 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 424 static void bce_watchdog (struct bce_softc *); 425 static int bce_ifmedia_upd (struct ifnet *); 426 static void bce_ifmedia_upd_locked (struct ifnet *); 427 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 428 static void bce_init_locked (struct bce_softc *); 429 static void bce_init (void *); 430 static void bce_mgmt_init_locked (struct bce_softc *sc); 431 432 static void bce_init_ctx (struct bce_softc *); 433 static void bce_get_mac_addr (struct bce_softc *); 434 static void bce_set_mac_addr (struct bce_softc *); 435 static void bce_phy_intr (struct bce_softc *); 436 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 437 static void bce_rx_intr (struct bce_softc *); 438 static void bce_tx_intr (struct bce_softc *); 439 static void bce_disable_intr (struct bce_softc *); 440 static void bce_enable_intr (struct bce_softc *, int); 441 442 static void bce_intr (void *); 443 static void bce_set_rx_mode (struct bce_softc *); 444 static void bce_stats_update (struct bce_softc *); 445 static void bce_tick (void *); 446 static void bce_pulse (void *); 447 static void bce_add_sysctls (struct bce_softc *); 448 449 450 /****************************************************************************/ 451 /* FreeBSD device dispatch table. */ 452 /****************************************************************************/ 453 static device_method_t bce_methods[] = { 454 /* Device interface (device_if.h) */ 455 DEVMETHOD(device_probe, bce_probe), 456 DEVMETHOD(device_attach, bce_attach), 457 DEVMETHOD(device_detach, bce_detach), 458 DEVMETHOD(device_shutdown, bce_shutdown), 459 /* Supported by device interface but not used here. */ 460 /* DEVMETHOD(device_identify, bce_identify), */ 461 /* DEVMETHOD(device_suspend, bce_suspend), */ 462 /* DEVMETHOD(device_resume, bce_resume), */ 463 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 464 465 /* Bus interface (bus_if.h) */ 466 DEVMETHOD(bus_print_child, bus_generic_print_child), 467 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 468 469 /* MII interface (miibus_if.h) */ 470 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 471 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 472 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 473 /* Supported by MII interface but not used here. */ 474 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 475 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 476 477 { 0, 0 } 478 }; 479 480 static driver_t bce_driver = { 481 "bce", 482 bce_methods, 483 sizeof(struct bce_softc) 484 }; 485 486 static devclass_t bce_devclass; 487 488 MODULE_DEPEND(bce, pci, 1, 1, 1); 489 MODULE_DEPEND(bce, ether, 1, 1, 1); 490 MODULE_DEPEND(bce, miibus, 1, 1, 1); 491 492 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 493 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 494 495 496 /****************************************************************************/ 497 /* Tunable device values */ 498 /****************************************************************************/ 499 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 500 501 /* Allowable values are TRUE or FALSE */ 502 static int bce_tso_enable = TRUE; 503 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 504 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 505 "TSO Enable/Disable"); 506 507 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 508 /* ToDo: Add MSI-X support. */ 509 static int bce_msi_enable = 1; 510 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 511 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 512 "MSI-X|MSI|INTx selector"); 513 514 /* ToDo: Add tunable to enable/disable strict MTU handling. */ 515 /* Currently allows "loose" RX MTU checking (i.e. sets the */ 516 /* H/W RX MTU to the size of the largest receive buffer, or */ 517 /* 2048 bytes). This will cause a UNH failure but is more */ 518 /* desireable from a functional perspective. */ 519 520 521 /****************************************************************************/ 522 /* Device probe function. */ 523 /* */ 524 /* Compares the device to the driver's list of supported devices and */ 525 /* reports back to the OS whether this is the right driver for the device. */ 526 /* */ 527 /* Returns: */ 528 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 529 /****************************************************************************/ 530 static int 531 bce_probe(device_t dev) 532 { 533 struct bce_type *t; 534 struct bce_softc *sc; 535 char *descbuf; 536 u16 vid = 0, did = 0, svid = 0, sdid = 0; 537 538 t = bce_devs; 539 540 sc = device_get_softc(dev); 541 bzero(sc, sizeof(struct bce_softc)); 542 sc->bce_unit = device_get_unit(dev); 543 sc->bce_dev = dev; 544 545 /* Get the data for the device to be probed. */ 546 vid = pci_get_vendor(dev); 547 did = pci_get_device(dev); 548 svid = pci_get_subvendor(dev); 549 sdid = pci_get_subdevice(dev); 550 551 DBPRINT(sc, BCE_EXTREME_LOAD, 552 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 553 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 554 555 /* Look through the list of known devices for a match. */ 556 while(t->bce_name != NULL) { 557 558 if ((vid == t->bce_vid) && (did == t->bce_did) && 559 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 560 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 561 562 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 563 564 if (descbuf == NULL) 565 return(ENOMEM); 566 567 /* Print out the device identity. */ 568 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 569 t->bce_name, (((pci_read_config(dev, 570 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 571 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 572 573 device_set_desc_copy(dev, descbuf); 574 free(descbuf, M_TEMP); 575 return(BUS_PROBE_DEFAULT); 576 } 577 t++; 578 } 579 580 return(ENXIO); 581 } 582 583 584 /****************************************************************************/ 585 /* PCI Capabilities Probe Function. */ 586 /* */ 587 /* Walks the PCI capabiites list for the device to find what features are */ 588 /* supported. */ 589 /* */ 590 /* Returns: */ 591 /* None. */ 592 /****************************************************************************/ 593 static void 594 bce_print_adapter_info(struct bce_softc *sc) 595 { 596 int i = 0; 597 598 DBENTER(BCE_VERBOSE_LOAD); 599 600 if (bootverbose) { 601 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 602 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 603 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 604 605 606 /* Bus info. */ 607 if (sc->bce_flags & BCE_PCIE_FLAG) { 608 printf("Bus (PCIe x%d, ", sc->link_width); 609 switch (sc->link_speed) { 610 case 1: printf("2.5Gbps); "); break; 611 case 2: printf("5Gbps); "); break; 612 default: printf("Unknown link speed); "); 613 } 614 } else { 615 printf("Bus (PCI%s, %s, %dMHz); ", 616 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 617 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 618 "32-bit" : "64-bit"), sc->bus_speed_mhz); 619 } 620 621 /* Firmware version and device features. */ 622 printf("B/C (%s); Flags (", sc->bce_bc_ver); 623 624 #ifdef BCE_JUMBO_HDRSPLIT 625 printf("SPLT"); 626 i++; 627 #endif 628 629 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 630 if (i > 0) printf("|"); 631 printf("MSI"); i++; 632 } 633 634 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 635 if (i > 0) printf("|"); 636 printf("MSI-X"); i++; 637 } 638 639 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 640 if (i > 0) printf("|"); 641 printf("2.5G"); i++; 642 } 643 644 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 645 if (i > 0) printf("|"); 646 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 647 } else { 648 printf(")\n"); 649 } 650 } 651 652 DBEXIT(BCE_VERBOSE_LOAD); 653 } 654 655 656 /****************************************************************************/ 657 /* PCI Capabilities Probe Function. */ 658 /* */ 659 /* Walks the PCI capabiites list for the device to find what features are */ 660 /* supported. */ 661 /* */ 662 /* Returns: */ 663 /* None. */ 664 /****************************************************************************/ 665 static void 666 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 667 { 668 u32 reg; 669 670 DBENTER(BCE_VERBOSE_LOAD); 671 672 /* Check if PCI-X capability is enabled. */ 673 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 674 if (reg != 0) 675 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 676 } 677 678 /* Check if PCIe capability is enabled. */ 679 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 680 if (reg != 0) { 681 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 682 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 683 "0x%08X\n", link_status); 684 sc->link_speed = link_status & 0xf; 685 sc->link_width = (link_status >> 4) & 0x3f; 686 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 687 sc->bce_flags |= BCE_PCIE_FLAG; 688 } 689 } 690 691 /* Check if MSI capability is enabled. */ 692 if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { 693 if (reg != 0) 694 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 695 } 696 697 /* Check if MSI-X capability is enabled. */ 698 if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { 699 if (reg != 0) 700 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 701 } 702 703 DBEXIT(BCE_VERBOSE_LOAD); 704 } 705 706 707 /****************************************************************************/ 708 /* Device attach function. */ 709 /* */ 710 /* Allocates device resources, performs secondary chip identification, */ 711 /* resets and initializes the hardware, and initializes driver instance */ 712 /* variables. */ 713 /* */ 714 /* Returns: */ 715 /* 0 on success, positive value on failure. */ 716 /****************************************************************************/ 717 static int 718 bce_attach(device_t dev) 719 { 720 struct bce_softc *sc; 721 struct ifnet *ifp; 722 u32 val; 723 int error, rid, rc = 0; 724 725 sc = device_get_softc(dev); 726 sc->bce_dev = dev; 727 728 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 729 730 sc->bce_unit = device_get_unit(dev); 731 732 /* Set initial device and PHY flags */ 733 sc->bce_flags = 0; 734 sc->bce_phy_flags = 0; 735 736 pci_enable_busmaster(dev); 737 738 /* Allocate PCI memory resources. */ 739 rid = PCIR_BAR(0); 740 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 741 &rid, RF_ACTIVE); 742 743 if (sc->bce_res_mem == NULL) { 744 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 745 __FILE__, __LINE__); 746 rc = ENXIO; 747 goto bce_attach_fail; 748 } 749 750 /* Get various resource handles. */ 751 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 752 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 753 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 754 755 bce_probe_pci_caps(dev, sc); 756 757 rid = 1; 758 #if 0 759 /* Try allocating MSI-X interrupts. */ 760 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 761 (bce_msi_enable >= 2) && 762 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 763 &rid, RF_ACTIVE)) != NULL)) { 764 765 msi_needed = sc->bce_msi_count = 1; 766 767 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 768 (sc->bce_msi_count != msi_needed)) { 769 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 770 "Received = %d, error = %d\n", __FILE__, __LINE__, 771 msi_needed, sc->bce_msi_count, error); 772 sc->bce_msi_count = 0; 773 pci_release_msi(dev); 774 bus_release_resource(dev, SYS_RES_MEMORY, rid, 775 sc->bce_res_irq); 776 sc->bce_res_irq = NULL; 777 } else { 778 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 779 __FUNCTION__); 780 sc->bce_flags |= BCE_USING_MSIX_FLAG; 781 sc->bce_intr = bce_intr; 782 } 783 } 784 #endif 785 786 /* Try allocating a MSI interrupt. */ 787 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 788 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 789 sc->bce_msi_count = 1; 790 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 791 BCE_PRINTF("%s(%d): MSI allocation failed! " 792 "error = %d\n", __FILE__, __LINE__, error); 793 sc->bce_msi_count = 0; 794 pci_release_msi(dev); 795 } else { 796 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 797 "interrupt.\n", __FUNCTION__); 798 sc->bce_flags |= BCE_USING_MSI_FLAG; 799 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 800 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 801 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 802 sc->bce_irq_rid = 1; 803 sc->bce_intr = bce_intr; 804 } 805 } 806 807 /* Try allocating a legacy interrupt. */ 808 if (sc->bce_msi_count == 0) { 809 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 810 __FUNCTION__); 811 rid = 0; 812 sc->bce_intr = bce_intr; 813 } 814 815 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 816 &rid, RF_SHAREABLE | RF_ACTIVE); 817 818 sc->bce_irq_rid = rid; 819 820 /* Report any IRQ allocation errors. */ 821 if (sc->bce_res_irq == NULL) { 822 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 823 __FILE__, __LINE__); 824 rc = ENXIO; 825 goto bce_attach_fail; 826 } 827 828 /* Initialize mutex for the current device instance. */ 829 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 830 831 /* 832 * Configure byte swap and enable indirect register access. 833 * Rely on CPU to do target byte swapping on big endian systems. 834 * Access to registers outside of PCI configurtion space are not 835 * valid until this is done. 836 */ 837 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 838 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 839 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 840 841 /* Save ASIC revsion info. */ 842 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 843 844 /* Weed out any non-production controller revisions. */ 845 switch(BCE_CHIP_ID(sc)) { 846 case BCE_CHIP_ID_5706_A0: 847 case BCE_CHIP_ID_5706_A1: 848 case BCE_CHIP_ID_5708_A0: 849 case BCE_CHIP_ID_5708_B0: 850 case BCE_CHIP_ID_5709_A0: 851 case BCE_CHIP_ID_5709_B0: 852 case BCE_CHIP_ID_5709_B1: 853 case BCE_CHIP_ID_5709_B2: 854 BCE_PRINTF("%s(%d): Unsupported controller " 855 "revision (%c%d)!\n", __FILE__, __LINE__, 856 (((pci_read_config(dev, PCIR_REVID, 4) & 857 0xf0) >> 4) + 'A'), (pci_read_config(dev, 858 PCIR_REVID, 4) & 0xf)); 859 rc = ENODEV; 860 goto bce_attach_fail; 861 } 862 863 /* 864 * The embedded PCIe to PCI-X bridge (EPB) 865 * in the 5708 cannot address memory above 866 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 867 */ 868 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 869 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 870 else 871 sc->max_bus_addr = BUS_SPACE_MAXADDR; 872 873 /* 874 * Find the base address for shared memory access. 875 * Newer versions of bootcode use a signature and offset 876 * while older versions use a fixed address. 877 */ 878 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 879 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 880 /* Multi-port devices use different offsets in shared memory. */ 881 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 882 (pci_get_function(sc->bce_dev) << 2)); 883 else 884 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 885 886 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 887 __FUNCTION__, sc->bce_shmem_base); 888 889 /* Fetch the bootcode revision. */ 890 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 891 for (int i = 0, j = 0; i < 3; i++) { 892 u8 num; 893 894 num = (u8) (val >> (24 - (i * 8))); 895 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 896 if (num >= k || !skip0 || k == 1) { 897 sc->bce_bc_ver[j++] = (num / k) + '0'; 898 skip0 = 0; 899 } 900 } 901 902 if (i != 2) 903 sc->bce_bc_ver[j++] = '.'; 904 } 905 906 /* Check if any management firwmare is enabled. */ 907 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 908 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 909 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 910 911 /* Allow time for firmware to enter the running state. */ 912 for (int i = 0; i < 30; i++) { 913 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 914 if (val & BCE_CONDITION_MFW_RUN_MASK) 915 break; 916 DELAY(10000); 917 } 918 919 /* Check if management firmware is running. */ 920 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 921 val &= BCE_CONDITION_MFW_RUN_MASK; 922 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 923 (val != BCE_CONDITION_MFW_RUN_NONE)) { 924 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 925 int i = 0; 926 927 /* Read the management firmware version string. */ 928 for (int j = 0; j < 3; j++) { 929 val = bce_reg_rd_ind(sc, addr + j * 4); 930 val = bswap32(val); 931 memcpy(&sc->bce_mfw_ver[i], &val, 4); 932 i += 4; 933 } 934 } else { 935 /* May cause firmware synchronization timeouts. */ 936 BCE_PRINTF("%s(%d): Management firmware enabled " 937 "but not running!\n", __FILE__, __LINE__); 938 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 939 940 /* ToDo: Any action the driver should take? */ 941 } 942 } 943 944 /* Get PCI bus information (speed and type). */ 945 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 946 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 947 u32 clkreg; 948 949 sc->bce_flags |= BCE_PCIX_FLAG; 950 951 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 952 953 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 954 switch (clkreg) { 955 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 956 sc->bus_speed_mhz = 133; 957 break; 958 959 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 960 sc->bus_speed_mhz = 100; 961 break; 962 963 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 964 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 965 sc->bus_speed_mhz = 66; 966 break; 967 968 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 969 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 970 sc->bus_speed_mhz = 50; 971 break; 972 973 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 974 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 975 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 976 sc->bus_speed_mhz = 33; 977 break; 978 } 979 } else { 980 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 981 sc->bus_speed_mhz = 66; 982 else 983 sc->bus_speed_mhz = 33; 984 } 985 986 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 987 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 988 989 /* Reset controller and announce to bootcode that driver is present. */ 990 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 991 BCE_PRINTF("%s(%d): Controller reset failed!\n", 992 __FILE__, __LINE__); 993 rc = ENXIO; 994 goto bce_attach_fail; 995 } 996 997 /* Initialize the controller. */ 998 if (bce_chipinit(sc)) { 999 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1000 __FILE__, __LINE__); 1001 rc = ENXIO; 1002 goto bce_attach_fail; 1003 } 1004 1005 /* Perform NVRAM test. */ 1006 if (bce_nvram_test(sc)) { 1007 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1008 __FILE__, __LINE__); 1009 rc = ENXIO; 1010 goto bce_attach_fail; 1011 } 1012 1013 /* Fetch the permanent Ethernet MAC address. */ 1014 bce_get_mac_addr(sc); 1015 1016 /* 1017 * Trip points control how many BDs 1018 * should be ready before generating an 1019 * interrupt while ticks control how long 1020 * a BD can sit in the chain before 1021 * generating an interrupt. Set the default 1022 * values for the RX and TX chains. 1023 */ 1024 1025 #ifdef BCE_DEBUG 1026 /* Force more frequent interrupts. */ 1027 sc->bce_tx_quick_cons_trip_int = 1; 1028 sc->bce_tx_quick_cons_trip = 1; 1029 sc->bce_tx_ticks_int = 0; 1030 sc->bce_tx_ticks = 0; 1031 1032 sc->bce_rx_quick_cons_trip_int = 1; 1033 sc->bce_rx_quick_cons_trip = 1; 1034 sc->bce_rx_ticks_int = 0; 1035 sc->bce_rx_ticks = 0; 1036 #else 1037 /* Improve throughput at the expense of increased latency. */ 1038 sc->bce_tx_quick_cons_trip_int = 20; 1039 sc->bce_tx_quick_cons_trip = 20; 1040 sc->bce_tx_ticks_int = 80; 1041 sc->bce_tx_ticks = 80; 1042 1043 sc->bce_rx_quick_cons_trip_int = 6; 1044 sc->bce_rx_quick_cons_trip = 6; 1045 sc->bce_rx_ticks_int = 18; 1046 sc->bce_rx_ticks = 18; 1047 #endif 1048 1049 /* Not used for L2. */ 1050 sc->bce_comp_prod_trip_int = 0; 1051 sc->bce_comp_prod_trip = 0; 1052 sc->bce_com_ticks_int = 0; 1053 sc->bce_com_ticks = 0; 1054 sc->bce_cmd_ticks_int = 0; 1055 sc->bce_cmd_ticks = 0; 1056 1057 /* Update statistics once every second. */ 1058 sc->bce_stats_ticks = 1000000 & 0xffff00; 1059 1060 /* Find the media type for the adapter. */ 1061 bce_get_media(sc); 1062 1063 /* Store data needed by PHY driver for backplane applications */ 1064 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1065 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1066 1067 /* Allocate DMA memory resources. */ 1068 if (bce_dma_alloc(dev)) { 1069 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1070 __FILE__, __LINE__); 1071 rc = ENXIO; 1072 goto bce_attach_fail; 1073 } 1074 1075 /* Allocate an ifnet structure. */ 1076 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1077 if (ifp == NULL) { 1078 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1079 __FILE__, __LINE__); 1080 rc = ENXIO; 1081 goto bce_attach_fail; 1082 } 1083 1084 /* Initialize the ifnet interface. */ 1085 ifp->if_softc = sc; 1086 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1087 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1088 ifp->if_ioctl = bce_ioctl; 1089 ifp->if_start = bce_start; 1090 ifp->if_init = bce_init; 1091 ifp->if_mtu = ETHERMTU; 1092 1093 if (bce_tso_enable) { 1094 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1095 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1096 IFCAP_VLAN_HWTSO; 1097 } else { 1098 ifp->if_hwassist = BCE_IF_HWASSIST; 1099 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1100 } 1101 1102 ifp->if_capenable = ifp->if_capabilities; 1103 1104 /* 1105 * Assume standard mbuf sizes for buffer allocation. 1106 * This may change later if the MTU size is set to 1107 * something other than 1500. 1108 */ 1109 #ifdef BCE_JUMBO_HDRSPLIT 1110 sc->rx_bd_mbuf_alloc_size = MHLEN; 1111 /* Make sure offset is 16 byte aligned for hardware. */ 1112 sc->rx_bd_mbuf_align_pad = 1113 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 1114 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1115 sc->rx_bd_mbuf_align_pad; 1116 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 1117 #else 1118 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 1119 sc->rx_bd_mbuf_align_pad = 1120 roundup2(MCLBYTES, 16) - MCLBYTES; 1121 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1122 sc->rx_bd_mbuf_align_pad; 1123 #endif 1124 1125 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 1126 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1127 IFQ_SET_READY(&ifp->if_snd); 1128 1129 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1130 ifp->if_baudrate = IF_Mbps(2500ULL); 1131 else 1132 ifp->if_baudrate = IF_Mbps(1000); 1133 1134 /* Handle any special PHY initialization for SerDes PHYs. */ 1135 bce_init_media(sc); 1136 1137 /* MII child bus by probing the PHY. */ 1138 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 1139 bce_ifmedia_sts)) { 1140 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n", 1141 __FILE__, __LINE__); 1142 rc = ENXIO; 1143 goto bce_attach_fail; 1144 } 1145 1146 /* Attach to the Ethernet interface list. */ 1147 ether_ifattach(ifp, sc->eaddr); 1148 1149 #if __FreeBSD_version < 500000 1150 callout_init(&sc->bce_tick_callout); 1151 callout_init(&sc->bce_pulse_callout); 1152 #else 1153 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1154 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1155 #endif 1156 1157 /* Hookup IRQ last. */ 1158 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1159 NULL, bce_intr, sc, &sc->bce_intrhand); 1160 1161 if (rc) { 1162 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1163 __FILE__, __LINE__); 1164 bce_detach(dev); 1165 goto bce_attach_exit; 1166 } 1167 1168 /* 1169 * At this point we've acquired all the resources 1170 * we need to run so there's no turning back, we're 1171 * cleared for launch. 1172 */ 1173 1174 /* Print some important debugging info. */ 1175 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1176 1177 /* Add the supported sysctls to the kernel. */ 1178 bce_add_sysctls(sc); 1179 1180 BCE_LOCK(sc); 1181 1182 /* 1183 * The chip reset earlier notified the bootcode that 1184 * a driver is present. We now need to start our pulse 1185 * routine so that the bootcode is reminded that we're 1186 * still running. 1187 */ 1188 bce_pulse(sc); 1189 1190 bce_mgmt_init_locked(sc); 1191 BCE_UNLOCK(sc); 1192 1193 /* Finally, print some useful adapter info */ 1194 bce_print_adapter_info(sc); 1195 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1196 __FUNCTION__, sc); 1197 1198 goto bce_attach_exit; 1199 1200 bce_attach_fail: 1201 bce_release_resources(sc); 1202 1203 bce_attach_exit: 1204 1205 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1206 1207 return(rc); 1208 } 1209 1210 1211 /****************************************************************************/ 1212 /* Device detach function. */ 1213 /* */ 1214 /* Stops the controller, resets the controller, and releases resources. */ 1215 /* */ 1216 /* Returns: */ 1217 /* 0 on success, positive value on failure. */ 1218 /****************************************************************************/ 1219 static int 1220 bce_detach(device_t dev) 1221 { 1222 struct bce_softc *sc = device_get_softc(dev); 1223 struct ifnet *ifp; 1224 u32 msg; 1225 1226 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1227 1228 ifp = sc->bce_ifp; 1229 1230 /* Stop and reset the controller. */ 1231 BCE_LOCK(sc); 1232 1233 /* Stop the pulse so the bootcode can go to driver absent state. */ 1234 callout_stop(&sc->bce_pulse_callout); 1235 1236 bce_stop(sc); 1237 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1238 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1239 else 1240 msg = BCE_DRV_MSG_CODE_UNLOAD; 1241 bce_reset(sc, msg); 1242 1243 BCE_UNLOCK(sc); 1244 1245 ether_ifdetach(ifp); 1246 1247 /* If we have a child device on the MII bus remove it too. */ 1248 bus_generic_detach(dev); 1249 device_delete_child(dev, sc->bce_miibus); 1250 1251 /* Release all remaining resources. */ 1252 bce_release_resources(sc); 1253 1254 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1255 1256 return(0); 1257 } 1258 1259 1260 /****************************************************************************/ 1261 /* Device shutdown function. */ 1262 /* */ 1263 /* Stops and resets the controller. */ 1264 /* */ 1265 /* Returns: */ 1266 /* 0 on success, positive value on failure. */ 1267 /****************************************************************************/ 1268 static int 1269 bce_shutdown(device_t dev) 1270 { 1271 struct bce_softc *sc = device_get_softc(dev); 1272 u32 msg; 1273 1274 DBENTER(BCE_VERBOSE); 1275 1276 BCE_LOCK(sc); 1277 bce_stop(sc); 1278 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1279 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1280 else 1281 msg = BCE_DRV_MSG_CODE_UNLOAD; 1282 bce_reset(sc, msg); 1283 BCE_UNLOCK(sc); 1284 1285 DBEXIT(BCE_VERBOSE); 1286 1287 return (0); 1288 } 1289 1290 1291 #ifdef BCE_DEBUG 1292 /****************************************************************************/ 1293 /* Register read. */ 1294 /* */ 1295 /* Returns: */ 1296 /* The value of the register. */ 1297 /****************************************************************************/ 1298 static u32 1299 bce_reg_rd(struct bce_softc *sc, u32 offset) 1300 { 1301 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1302 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1303 __FUNCTION__, offset, val); 1304 return val; 1305 } 1306 1307 1308 /****************************************************************************/ 1309 /* Register write (16 bit). */ 1310 /* */ 1311 /* Returns: */ 1312 /* Nothing. */ 1313 /****************************************************************************/ 1314 static void 1315 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1316 { 1317 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1318 __FUNCTION__, offset, val); 1319 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1320 } 1321 1322 1323 /****************************************************************************/ 1324 /* Register write. */ 1325 /* */ 1326 /* Returns: */ 1327 /* Nothing. */ 1328 /****************************************************************************/ 1329 static void 1330 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1331 { 1332 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1333 __FUNCTION__, offset, val); 1334 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1335 } 1336 #endif 1337 1338 /****************************************************************************/ 1339 /* Indirect register read. */ 1340 /* */ 1341 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1342 /* configuration space. Using this mechanism avoids issues with posted */ 1343 /* reads but is much slower than memory-mapped I/O. */ 1344 /* */ 1345 /* Returns: */ 1346 /* The value of the register. */ 1347 /****************************************************************************/ 1348 static u32 1349 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1350 { 1351 device_t dev; 1352 dev = sc->bce_dev; 1353 1354 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1355 #ifdef BCE_DEBUG 1356 { 1357 u32 val; 1358 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1359 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1360 __FUNCTION__, offset, val); 1361 return val; 1362 } 1363 #else 1364 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1365 #endif 1366 } 1367 1368 1369 /****************************************************************************/ 1370 /* Indirect register write. */ 1371 /* */ 1372 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1373 /* configuration space. Using this mechanism avoids issues with posted */ 1374 /* writes but is muchh slower than memory-mapped I/O. */ 1375 /* */ 1376 /* Returns: */ 1377 /* Nothing. */ 1378 /****************************************************************************/ 1379 static void 1380 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1381 { 1382 device_t dev; 1383 dev = sc->bce_dev; 1384 1385 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1386 __FUNCTION__, offset, val); 1387 1388 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1389 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1390 } 1391 1392 1393 /****************************************************************************/ 1394 /* Shared memory write. */ 1395 /* */ 1396 /* Writes NetXtreme II shared memory region. */ 1397 /* */ 1398 /* Returns: */ 1399 /* Nothing. */ 1400 /****************************************************************************/ 1401 static void 1402 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1403 { 1404 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1405 "0x%08X\n", __FUNCTION__, val, offset); 1406 1407 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1408 } 1409 1410 1411 /****************************************************************************/ 1412 /* Shared memory read. */ 1413 /* */ 1414 /* Reads NetXtreme II shared memory region. */ 1415 /* */ 1416 /* Returns: */ 1417 /* The 32 bit value read. */ 1418 /****************************************************************************/ 1419 static u32 1420 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1421 { 1422 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1423 1424 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1425 "0x%08X\n", __FUNCTION__, val, offset); 1426 1427 return val; 1428 } 1429 1430 1431 #ifdef BCE_DEBUG 1432 /****************************************************************************/ 1433 /* Context memory read. */ 1434 /* */ 1435 /* The NetXtreme II controller uses context memory to track connection */ 1436 /* information for L2 and higher network protocols. */ 1437 /* */ 1438 /* Returns: */ 1439 /* The requested 32 bit value of context memory. */ 1440 /****************************************************************************/ 1441 static u32 1442 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1443 { 1444 u32 idx, offset, retry_cnt = 5, val; 1445 1446 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1447 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1448 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1449 1450 offset = ctx_offset + cid_addr; 1451 1452 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1453 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1454 1455 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1456 1457 for (idx = 0; idx < retry_cnt; idx++) { 1458 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1459 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1460 break; 1461 DELAY(5); 1462 } 1463 1464 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1465 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1466 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1467 __FILE__, __LINE__, cid_addr, ctx_offset); 1468 1469 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1470 } else { 1471 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1472 val = REG_RD(sc, BCE_CTX_DATA); 1473 } 1474 1475 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1476 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1477 1478 return(val); 1479 } 1480 #endif 1481 1482 1483 /****************************************************************************/ 1484 /* Context memory write. */ 1485 /* */ 1486 /* The NetXtreme II controller uses context memory to track connection */ 1487 /* information for L2 and higher network protocols. */ 1488 /* */ 1489 /* Returns: */ 1490 /* Nothing. */ 1491 /****************************************************************************/ 1492 static void 1493 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1494 { 1495 u32 idx, offset = ctx_offset + cid_addr; 1496 u32 val, retry_cnt = 5; 1497 1498 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1499 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1500 1501 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1502 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1503 __FUNCTION__, cid_addr)); 1504 1505 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1506 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1507 1508 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1509 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1510 1511 for (idx = 0; idx < retry_cnt; idx++) { 1512 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1513 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1514 break; 1515 DELAY(5); 1516 } 1517 1518 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1519 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1520 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1521 __FILE__, __LINE__, cid_addr, ctx_offset); 1522 1523 } else { 1524 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1525 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1526 } 1527 } 1528 1529 1530 /****************************************************************************/ 1531 /* PHY register read. */ 1532 /* */ 1533 /* Implements register reads on the MII bus. */ 1534 /* */ 1535 /* Returns: */ 1536 /* The value of the register. */ 1537 /****************************************************************************/ 1538 static int 1539 bce_miibus_read_reg(device_t dev, int phy, int reg) 1540 { 1541 struct bce_softc *sc; 1542 u32 val; 1543 int i; 1544 1545 sc = device_get_softc(dev); 1546 1547 /* Make sure we are accessing the correct PHY address. */ 1548 if (phy != sc->bce_phy_addr) { 1549 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1550 "for PHY read!\n", phy); 1551 return(0); 1552 } 1553 1554 /* 1555 * The 5709S PHY is an IEEE Clause 45 PHY 1556 * with special mappings to work with IEEE 1557 * Clause 22 register accesses. 1558 */ 1559 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1560 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1561 reg += 0x10; 1562 } 1563 1564 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1565 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1566 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1567 1568 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1569 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1570 1571 DELAY(40); 1572 } 1573 1574 1575 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1576 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1577 BCE_EMAC_MDIO_COMM_START_BUSY; 1578 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1579 1580 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1581 DELAY(10); 1582 1583 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1584 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1585 DELAY(5); 1586 1587 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1588 val &= BCE_EMAC_MDIO_COMM_DATA; 1589 1590 break; 1591 } 1592 } 1593 1594 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1595 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1596 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1597 val = 0x0; 1598 } else { 1599 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1600 } 1601 1602 1603 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1604 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1605 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1606 1607 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1608 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1609 1610 DELAY(40); 1611 } 1612 1613 DB_PRINT_PHY_REG(reg, val); 1614 return (val & 0xffff); 1615 1616 } 1617 1618 1619 /****************************************************************************/ 1620 /* PHY register write. */ 1621 /* */ 1622 /* Implements register writes on the MII bus. */ 1623 /* */ 1624 /* Returns: */ 1625 /* The value of the register. */ 1626 /****************************************************************************/ 1627 static int 1628 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1629 { 1630 struct bce_softc *sc; 1631 u32 val1; 1632 int i; 1633 1634 sc = device_get_softc(dev); 1635 1636 /* Make sure we are accessing the correct PHY address. */ 1637 if (phy != sc->bce_phy_addr) { 1638 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1639 "for PHY write!\n", phy); 1640 return(0); 1641 } 1642 1643 DB_PRINT_PHY_REG(reg, val); 1644 1645 /* 1646 * The 5709S PHY is an IEEE Clause 45 PHY 1647 * with special mappings to work with IEEE 1648 * Clause 22 register accesses. 1649 */ 1650 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1651 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1652 reg += 0x10; 1653 } 1654 1655 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1656 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1657 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1658 1659 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1660 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1661 1662 DELAY(40); 1663 } 1664 1665 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1666 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1667 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1668 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1669 1670 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1671 DELAY(10); 1672 1673 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1674 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1675 DELAY(5); 1676 break; 1677 } 1678 } 1679 1680 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1681 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1682 __FILE__, __LINE__); 1683 1684 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1685 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1686 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1687 1688 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1689 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1690 1691 DELAY(40); 1692 } 1693 1694 return 0; 1695 } 1696 1697 1698 /****************************************************************************/ 1699 /* MII bus status change. */ 1700 /* */ 1701 /* Called by the MII bus driver when the PHY establishes link to set the */ 1702 /* MAC interface registers. */ 1703 /* */ 1704 /* Returns: */ 1705 /* Nothing. */ 1706 /****************************************************************************/ 1707 static void 1708 bce_miibus_statchg(device_t dev) 1709 { 1710 struct bce_softc *sc; 1711 struct mii_data *mii; 1712 int val; 1713 1714 sc = device_get_softc(dev); 1715 1716 DBENTER(BCE_VERBOSE_PHY); 1717 1718 mii = device_get_softc(sc->bce_miibus); 1719 1720 val = REG_RD(sc, BCE_EMAC_MODE); 1721 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1722 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1723 BCE_EMAC_MODE_25G); 1724 1725 /* Set MII or GMII interface based on the PHY speed. */ 1726 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1727 case IFM_10_T: 1728 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 1729 DBPRINT(sc, BCE_INFO_PHY, 1730 "Enabling 10Mb interface.\n"); 1731 val |= BCE_EMAC_MODE_PORT_MII_10; 1732 break; 1733 } 1734 /* fall-through */ 1735 case IFM_100_TX: 1736 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 1737 val |= BCE_EMAC_MODE_PORT_MII; 1738 break; 1739 case IFM_2500_SX: 1740 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 1741 val |= BCE_EMAC_MODE_25G; 1742 /* fall-through */ 1743 case IFM_1000_T: 1744 case IFM_1000_SX: 1745 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 1746 val |= BCE_EMAC_MODE_PORT_GMII; 1747 break; 1748 default: 1749 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 1750 "default GMII interface.\n"); 1751 val |= BCE_EMAC_MODE_PORT_GMII; 1752 } 1753 1754 /* Set half or full duplex based on PHY settings. */ 1755 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1756 DBPRINT(sc, BCE_INFO_PHY, 1757 "Setting Half-Duplex interface.\n"); 1758 val |= BCE_EMAC_MODE_HALF_DUPLEX; 1759 } else 1760 DBPRINT(sc, BCE_INFO_PHY, 1761 "Setting Full-Duplex interface.\n"); 1762 1763 REG_WR(sc, BCE_EMAC_MODE, val); 1764 1765 /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */ 1766 if (mii->mii_media_active & IFM_FLAG0) { 1767 DBPRINT(sc, BCE_INFO_PHY, 1768 "%s(): Enabling RX flow control.\n", __FUNCTION__); 1769 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1770 } else { 1771 DBPRINT(sc, BCE_INFO_PHY, 1772 "%s(): Disabling RX flow control.\n", __FUNCTION__); 1773 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1774 } 1775 1776 if (mii->mii_media_active & IFM_FLAG1) { 1777 DBPRINT(sc, BCE_INFO_PHY, 1778 "%s(): Enabling TX flow control.\n", __FUNCTION__); 1779 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1780 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 1781 } else { 1782 DBPRINT(sc, BCE_INFO_PHY, 1783 "%s(): Disabling TX flow control.\n", __FUNCTION__); 1784 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1785 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 1786 } 1787 1788 /* ToDo: Update watermarks in bce_init_rx_context(). */ 1789 1790 DBEXIT(BCE_VERBOSE_PHY); 1791 } 1792 1793 1794 /****************************************************************************/ 1795 /* Acquire NVRAM lock. */ 1796 /* */ 1797 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1798 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1799 /* for use by the driver. */ 1800 /* */ 1801 /* Returns: */ 1802 /* 0 on success, positive value on failure. */ 1803 /****************************************************************************/ 1804 static int 1805 bce_acquire_nvram_lock(struct bce_softc *sc) 1806 { 1807 u32 val; 1808 int j, rc = 0; 1809 1810 DBENTER(BCE_VERBOSE_NVRAM); 1811 1812 /* Request access to the flash interface. */ 1813 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1814 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1815 val = REG_RD(sc, BCE_NVM_SW_ARB); 1816 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1817 break; 1818 1819 DELAY(5); 1820 } 1821 1822 if (j >= NVRAM_TIMEOUT_COUNT) { 1823 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1824 rc = EBUSY; 1825 } 1826 1827 DBEXIT(BCE_VERBOSE_NVRAM); 1828 return (rc); 1829 } 1830 1831 1832 /****************************************************************************/ 1833 /* Release NVRAM lock. */ 1834 /* */ 1835 /* When the caller is finished accessing NVRAM the lock must be released. */ 1836 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1837 /* for use by the driver. */ 1838 /* */ 1839 /* Returns: */ 1840 /* 0 on success, positive value on failure. */ 1841 /****************************************************************************/ 1842 static int 1843 bce_release_nvram_lock(struct bce_softc *sc) 1844 { 1845 u32 val; 1846 int j, rc = 0; 1847 1848 DBENTER(BCE_VERBOSE_NVRAM); 1849 1850 /* 1851 * Relinquish nvram interface. 1852 */ 1853 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1854 1855 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1856 val = REG_RD(sc, BCE_NVM_SW_ARB); 1857 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1858 break; 1859 1860 DELAY(5); 1861 } 1862 1863 if (j >= NVRAM_TIMEOUT_COUNT) { 1864 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 1865 rc = EBUSY; 1866 } 1867 1868 DBEXIT(BCE_VERBOSE_NVRAM); 1869 return (rc); 1870 } 1871 1872 1873 #ifdef BCE_NVRAM_WRITE_SUPPORT 1874 /****************************************************************************/ 1875 /* Enable NVRAM write access. */ 1876 /* */ 1877 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1878 /* */ 1879 /* Returns: */ 1880 /* 0 on success, positive value on failure. */ 1881 /****************************************************************************/ 1882 static int 1883 bce_enable_nvram_write(struct bce_softc *sc) 1884 { 1885 u32 val; 1886 int rc = 0; 1887 1888 DBENTER(BCE_VERBOSE_NVRAM); 1889 1890 val = REG_RD(sc, BCE_MISC_CFG); 1891 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1892 1893 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 1894 int j; 1895 1896 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1897 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1898 1899 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1900 DELAY(5); 1901 1902 val = REG_RD(sc, BCE_NVM_COMMAND); 1903 if (val & BCE_NVM_COMMAND_DONE) 1904 break; 1905 } 1906 1907 if (j >= NVRAM_TIMEOUT_COUNT) { 1908 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1909 rc = EBUSY; 1910 } 1911 } 1912 1913 DBENTER(BCE_VERBOSE_NVRAM); 1914 return (rc); 1915 } 1916 1917 1918 /****************************************************************************/ 1919 /* Disable NVRAM write access. */ 1920 /* */ 1921 /* When the caller is finished writing to NVRAM write access must be */ 1922 /* disabled. */ 1923 /* */ 1924 /* Returns: */ 1925 /* Nothing. */ 1926 /****************************************************************************/ 1927 static void 1928 bce_disable_nvram_write(struct bce_softc *sc) 1929 { 1930 u32 val; 1931 1932 DBENTER(BCE_VERBOSE_NVRAM); 1933 1934 val = REG_RD(sc, BCE_MISC_CFG); 1935 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1936 1937 DBEXIT(BCE_VERBOSE_NVRAM); 1938 1939 } 1940 #endif 1941 1942 1943 /****************************************************************************/ 1944 /* Enable NVRAM access. */ 1945 /* */ 1946 /* Before accessing NVRAM for read or write operations the caller must */ 1947 /* enabled NVRAM access. */ 1948 /* */ 1949 /* Returns: */ 1950 /* Nothing. */ 1951 /****************************************************************************/ 1952 static void 1953 bce_enable_nvram_access(struct bce_softc *sc) 1954 { 1955 u32 val; 1956 1957 DBENTER(BCE_VERBOSE_NVRAM); 1958 1959 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1960 /* Enable both bits, even on read. */ 1961 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 1962 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1963 1964 DBEXIT(BCE_VERBOSE_NVRAM); 1965 } 1966 1967 1968 /****************************************************************************/ 1969 /* Disable NVRAM access. */ 1970 /* */ 1971 /* When the caller is finished accessing NVRAM access must be disabled. */ 1972 /* */ 1973 /* Returns: */ 1974 /* Nothing. */ 1975 /****************************************************************************/ 1976 static void 1977 bce_disable_nvram_access(struct bce_softc *sc) 1978 { 1979 u32 val; 1980 1981 DBENTER(BCE_VERBOSE_NVRAM); 1982 1983 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1984 1985 /* Disable both bits, even after read. */ 1986 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 1987 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 1988 1989 DBEXIT(BCE_VERBOSE_NVRAM); 1990 } 1991 1992 1993 #ifdef BCE_NVRAM_WRITE_SUPPORT 1994 /****************************************************************************/ 1995 /* Erase NVRAM page before writing. */ 1996 /* */ 1997 /* Non-buffered flash parts require that a page be erased before it is */ 1998 /* written. */ 1999 /* */ 2000 /* Returns: */ 2001 /* 0 on success, positive value on failure. */ 2002 /****************************************************************************/ 2003 static int 2004 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2005 { 2006 u32 cmd; 2007 int j, rc = 0; 2008 2009 DBENTER(BCE_VERBOSE_NVRAM); 2010 2011 /* Buffered flash doesn't require an erase. */ 2012 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2013 goto bce_nvram_erase_page_exit; 2014 2015 /* Build an erase command. */ 2016 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2017 BCE_NVM_COMMAND_DOIT; 2018 2019 /* 2020 * Clear the DONE bit separately, set the NVRAM adress to erase, 2021 * and issue the erase command. 2022 */ 2023 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2024 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2025 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2026 2027 /* Wait for completion. */ 2028 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2029 u32 val; 2030 2031 DELAY(5); 2032 2033 val = REG_RD(sc, BCE_NVM_COMMAND); 2034 if (val & BCE_NVM_COMMAND_DONE) 2035 break; 2036 } 2037 2038 if (j >= NVRAM_TIMEOUT_COUNT) { 2039 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2040 rc = EBUSY; 2041 } 2042 2043 bce_nvram_erase_page_exit: 2044 DBEXIT(BCE_VERBOSE_NVRAM); 2045 return (rc); 2046 } 2047 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2048 2049 2050 /****************************************************************************/ 2051 /* Read a dword (32 bits) from NVRAM. */ 2052 /* */ 2053 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2054 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2055 /* */ 2056 /* Returns: */ 2057 /* 0 on success and the 32 bit value read, positive value on failure. */ 2058 /****************************************************************************/ 2059 static int 2060 bce_nvram_read_dword(struct bce_softc *sc, 2061 u32 offset, u8 *ret_val, u32 cmd_flags) 2062 { 2063 u32 cmd; 2064 int i, rc = 0; 2065 2066 DBENTER(BCE_EXTREME_NVRAM); 2067 2068 /* Build the command word. */ 2069 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2070 2071 /* Calculate the offset for buffered flash if translation is used. */ 2072 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2073 offset = ((offset / sc->bce_flash_info->page_size) << 2074 sc->bce_flash_info->page_bits) + 2075 (offset % sc->bce_flash_info->page_size); 2076 } 2077 2078 /* 2079 * Clear the DONE bit separately, set the address to read, 2080 * and issue the read. 2081 */ 2082 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2083 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2084 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2085 2086 /* Wait for completion. */ 2087 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2088 u32 val; 2089 2090 DELAY(5); 2091 2092 val = REG_RD(sc, BCE_NVM_COMMAND); 2093 if (val & BCE_NVM_COMMAND_DONE) { 2094 val = REG_RD(sc, BCE_NVM_READ); 2095 2096 val = bce_be32toh(val); 2097 memcpy(ret_val, &val, 4); 2098 break; 2099 } 2100 } 2101 2102 /* Check for errors. */ 2103 if (i >= NVRAM_TIMEOUT_COUNT) { 2104 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2105 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2106 rc = EBUSY; 2107 } 2108 2109 DBEXIT(BCE_EXTREME_NVRAM); 2110 return(rc); 2111 } 2112 2113 2114 #ifdef BCE_NVRAM_WRITE_SUPPORT 2115 /****************************************************************************/ 2116 /* Write a dword (32 bits) to NVRAM. */ 2117 /* */ 2118 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2119 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2120 /* enabled NVRAM write access. */ 2121 /* */ 2122 /* Returns: */ 2123 /* 0 on success, positive value on failure. */ 2124 /****************************************************************************/ 2125 static int 2126 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2127 u32 cmd_flags) 2128 { 2129 u32 cmd, val32; 2130 int j, rc = 0; 2131 2132 DBENTER(BCE_VERBOSE_NVRAM); 2133 2134 /* Build the command word. */ 2135 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2136 2137 /* Calculate the offset for buffered flash if translation is used. */ 2138 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2139 offset = ((offset / sc->bce_flash_info->page_size) << 2140 sc->bce_flash_info->page_bits) + 2141 (offset % sc->bce_flash_info->page_size); 2142 } 2143 2144 /* 2145 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2146 * set the NVRAM address to write, and issue the write command 2147 */ 2148 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2149 memcpy(&val32, val, 4); 2150 val32 = htobe32(val32); 2151 REG_WR(sc, BCE_NVM_WRITE, val32); 2152 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2153 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2154 2155 /* Wait for completion. */ 2156 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2157 DELAY(5); 2158 2159 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2160 break; 2161 } 2162 if (j >= NVRAM_TIMEOUT_COUNT) { 2163 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2164 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2165 rc = EBUSY; 2166 } 2167 2168 DBEXIT(BCE_VERBOSE_NVRAM); 2169 return (rc); 2170 } 2171 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2172 2173 2174 /****************************************************************************/ 2175 /* Initialize NVRAM access. */ 2176 /* */ 2177 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2178 /* access that device. */ 2179 /* */ 2180 /* Returns: */ 2181 /* 0 on success, positive value on failure. */ 2182 /****************************************************************************/ 2183 static int 2184 bce_init_nvram(struct bce_softc *sc) 2185 { 2186 u32 val; 2187 int j, entry_count, rc = 0; 2188 struct flash_spec *flash; 2189 2190 DBENTER(BCE_VERBOSE_NVRAM); 2191 2192 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2193 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2194 sc->bce_flash_info = &flash_5709; 2195 goto bce_init_nvram_get_flash_size; 2196 } 2197 2198 /* Determine the selected interface. */ 2199 val = REG_RD(sc, BCE_NVM_CFG1); 2200 2201 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2202 2203 /* 2204 * Flash reconfiguration is required to support additional 2205 * NVRAM devices not directly supported in hardware. 2206 * Check if the flash interface was reconfigured 2207 * by the bootcode. 2208 */ 2209 2210 if (val & 0x40000000) { 2211 /* Flash interface reconfigured by bootcode. */ 2212 2213 DBPRINT(sc,BCE_INFO_LOAD, 2214 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2215 2216 for (j = 0, flash = &flash_table[0]; j < entry_count; 2217 j++, flash++) { 2218 if ((val & FLASH_BACKUP_STRAP_MASK) == 2219 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2220 sc->bce_flash_info = flash; 2221 break; 2222 } 2223 } 2224 } else { 2225 /* Flash interface not yet reconfigured. */ 2226 u32 mask; 2227 2228 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2229 __FUNCTION__); 2230 2231 if (val & (1 << 23)) 2232 mask = FLASH_BACKUP_STRAP_MASK; 2233 else 2234 mask = FLASH_STRAP_MASK; 2235 2236 /* Look for the matching NVRAM device configuration data. */ 2237 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2238 2239 /* Check if the device matches any of the known devices. */ 2240 if ((val & mask) == (flash->strapping & mask)) { 2241 /* Found a device match. */ 2242 sc->bce_flash_info = flash; 2243 2244 /* Request access to the flash interface. */ 2245 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2246 return rc; 2247 2248 /* Reconfigure the flash interface. */ 2249 bce_enable_nvram_access(sc); 2250 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2251 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2252 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2253 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2254 bce_disable_nvram_access(sc); 2255 bce_release_nvram_lock(sc); 2256 2257 break; 2258 } 2259 } 2260 } 2261 2262 /* Check if a matching device was found. */ 2263 if (j == entry_count) { 2264 sc->bce_flash_info = NULL; 2265 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2266 __FILE__, __LINE__); 2267 rc = ENODEV; 2268 } 2269 2270 bce_init_nvram_get_flash_size: 2271 /* Write the flash config data to the shared memory interface. */ 2272 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2273 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2274 if (val) 2275 sc->bce_flash_size = val; 2276 else 2277 sc->bce_flash_size = sc->bce_flash_info->total_size; 2278 2279 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2280 __FUNCTION__, sc->bce_flash_info->name, 2281 sc->bce_flash_info->total_size); 2282 2283 DBEXIT(BCE_VERBOSE_NVRAM); 2284 return rc; 2285 } 2286 2287 2288 /****************************************************************************/ 2289 /* Read an arbitrary range of data from NVRAM. */ 2290 /* */ 2291 /* Prepares the NVRAM interface for access and reads the requested data */ 2292 /* into the supplied buffer. */ 2293 /* */ 2294 /* Returns: */ 2295 /* 0 on success and the data read, positive value on failure. */ 2296 /****************************************************************************/ 2297 static int 2298 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2299 int buf_size) 2300 { 2301 int rc = 0; 2302 u32 cmd_flags, offset32, len32, extra; 2303 2304 DBENTER(BCE_VERBOSE_NVRAM); 2305 2306 if (buf_size == 0) 2307 goto bce_nvram_read_exit; 2308 2309 /* Request access to the flash interface. */ 2310 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2311 goto bce_nvram_read_exit; 2312 2313 /* Enable access to flash interface */ 2314 bce_enable_nvram_access(sc); 2315 2316 len32 = buf_size; 2317 offset32 = offset; 2318 extra = 0; 2319 2320 cmd_flags = 0; 2321 2322 if (offset32 & 3) { 2323 u8 buf[4]; 2324 u32 pre_len; 2325 2326 offset32 &= ~3; 2327 pre_len = 4 - (offset & 3); 2328 2329 if (pre_len >= len32) { 2330 pre_len = len32; 2331 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2332 } 2333 else { 2334 cmd_flags = BCE_NVM_COMMAND_FIRST; 2335 } 2336 2337 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2338 2339 if (rc) 2340 return rc; 2341 2342 memcpy(ret_buf, buf + (offset & 3), pre_len); 2343 2344 offset32 += 4; 2345 ret_buf += pre_len; 2346 len32 -= pre_len; 2347 } 2348 2349 if (len32 & 3) { 2350 extra = 4 - (len32 & 3); 2351 len32 = (len32 + 4) & ~3; 2352 } 2353 2354 if (len32 == 4) { 2355 u8 buf[4]; 2356 2357 if (cmd_flags) 2358 cmd_flags = BCE_NVM_COMMAND_LAST; 2359 else 2360 cmd_flags = BCE_NVM_COMMAND_FIRST | 2361 BCE_NVM_COMMAND_LAST; 2362 2363 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2364 2365 memcpy(ret_buf, buf, 4 - extra); 2366 } 2367 else if (len32 > 0) { 2368 u8 buf[4]; 2369 2370 /* Read the first word. */ 2371 if (cmd_flags) 2372 cmd_flags = 0; 2373 else 2374 cmd_flags = BCE_NVM_COMMAND_FIRST; 2375 2376 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2377 2378 /* Advance to the next dword. */ 2379 offset32 += 4; 2380 ret_buf += 4; 2381 len32 -= 4; 2382 2383 while (len32 > 4 && rc == 0) { 2384 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2385 2386 /* Advance to the next dword. */ 2387 offset32 += 4; 2388 ret_buf += 4; 2389 len32 -= 4; 2390 } 2391 2392 if (rc) 2393 goto bce_nvram_read_locked_exit; 2394 2395 cmd_flags = BCE_NVM_COMMAND_LAST; 2396 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2397 2398 memcpy(ret_buf, buf, 4 - extra); 2399 } 2400 2401 bce_nvram_read_locked_exit: 2402 /* Disable access to flash interface and release the lock. */ 2403 bce_disable_nvram_access(sc); 2404 bce_release_nvram_lock(sc); 2405 2406 bce_nvram_read_exit: 2407 DBEXIT(BCE_VERBOSE_NVRAM); 2408 return rc; 2409 } 2410 2411 2412 #ifdef BCE_NVRAM_WRITE_SUPPORT 2413 /****************************************************************************/ 2414 /* Write an arbitrary range of data from NVRAM. */ 2415 /* */ 2416 /* Prepares the NVRAM interface for write access and writes the requested */ 2417 /* data from the supplied buffer. The caller is responsible for */ 2418 /* calculating any appropriate CRCs. */ 2419 /* */ 2420 /* Returns: */ 2421 /* 0 on success, positive value on failure. */ 2422 /****************************************************************************/ 2423 static int 2424 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2425 int buf_size) 2426 { 2427 u32 written, offset32, len32; 2428 u8 *buf, start[4], end[4]; 2429 int rc = 0; 2430 int align_start, align_end; 2431 2432 DBENTER(BCE_VERBOSE_NVRAM); 2433 2434 buf = data_buf; 2435 offset32 = offset; 2436 len32 = buf_size; 2437 align_start = align_end = 0; 2438 2439 if ((align_start = (offset32 & 3))) { 2440 offset32 &= ~3; 2441 len32 += align_start; 2442 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2443 goto bce_nvram_write_exit; 2444 } 2445 2446 if (len32 & 3) { 2447 if ((len32 > 4) || !align_start) { 2448 align_end = 4 - (len32 & 3); 2449 len32 += align_end; 2450 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2451 end, 4))) { 2452 goto bce_nvram_write_exit; 2453 } 2454 } 2455 } 2456 2457 if (align_start || align_end) { 2458 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2459 if (buf == 0) { 2460 rc = ENOMEM; 2461 goto bce_nvram_write_exit; 2462 } 2463 2464 if (align_start) { 2465 memcpy(buf, start, 4); 2466 } 2467 2468 if (align_end) { 2469 memcpy(buf + len32 - 4, end, 4); 2470 } 2471 memcpy(buf + align_start, data_buf, buf_size); 2472 } 2473 2474 written = 0; 2475 while ((written < len32) && (rc == 0)) { 2476 u32 page_start, page_end, data_start, data_end; 2477 u32 addr, cmd_flags; 2478 int i; 2479 u8 flash_buffer[264]; 2480 2481 /* Find the page_start addr */ 2482 page_start = offset32 + written; 2483 page_start -= (page_start % sc->bce_flash_info->page_size); 2484 /* Find the page_end addr */ 2485 page_end = page_start + sc->bce_flash_info->page_size; 2486 /* Find the data_start addr */ 2487 data_start = (written == 0) ? offset32 : page_start; 2488 /* Find the data_end addr */ 2489 data_end = (page_end > offset32 + len32) ? 2490 (offset32 + len32) : page_end; 2491 2492 /* Request access to the flash interface. */ 2493 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2494 goto bce_nvram_write_exit; 2495 2496 /* Enable access to flash interface */ 2497 bce_enable_nvram_access(sc); 2498 2499 cmd_flags = BCE_NVM_COMMAND_FIRST; 2500 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2501 int j; 2502 2503 /* Read the whole page into the buffer 2504 * (non-buffer flash only) */ 2505 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2506 if (j == (sc->bce_flash_info->page_size - 4)) { 2507 cmd_flags |= BCE_NVM_COMMAND_LAST; 2508 } 2509 rc = bce_nvram_read_dword(sc, 2510 page_start + j, 2511 &flash_buffer[j], 2512 cmd_flags); 2513 2514 if (rc) 2515 goto bce_nvram_write_locked_exit; 2516 2517 cmd_flags = 0; 2518 } 2519 } 2520 2521 /* Enable writes to flash interface (unlock write-protect) */ 2522 if ((rc = bce_enable_nvram_write(sc)) != 0) 2523 goto bce_nvram_write_locked_exit; 2524 2525 /* Erase the page */ 2526 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2527 goto bce_nvram_write_locked_exit; 2528 2529 /* Re-enable the write again for the actual write */ 2530 bce_enable_nvram_write(sc); 2531 2532 /* Loop to write back the buffer data from page_start to 2533 * data_start */ 2534 i = 0; 2535 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2536 for (addr = page_start; addr < data_start; 2537 addr += 4, i += 4) { 2538 2539 rc = bce_nvram_write_dword(sc, addr, 2540 &flash_buffer[i], cmd_flags); 2541 2542 if (rc != 0) 2543 goto bce_nvram_write_locked_exit; 2544 2545 cmd_flags = 0; 2546 } 2547 } 2548 2549 /* Loop to write the new data from data_start to data_end */ 2550 for (addr = data_start; addr < data_end; addr += 4, i++) { 2551 if ((addr == page_end - 4) || 2552 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2553 (addr == data_end - 4))) { 2554 2555 cmd_flags |= BCE_NVM_COMMAND_LAST; 2556 } 2557 rc = bce_nvram_write_dword(sc, addr, buf, 2558 cmd_flags); 2559 2560 if (rc != 0) 2561 goto bce_nvram_write_locked_exit; 2562 2563 cmd_flags = 0; 2564 buf += 4; 2565 } 2566 2567 /* Loop to write back the buffer data from data_end 2568 * to page_end */ 2569 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2570 for (addr = data_end; addr < page_end; 2571 addr += 4, i += 4) { 2572 2573 if (addr == page_end-4) { 2574 cmd_flags = BCE_NVM_COMMAND_LAST; 2575 } 2576 rc = bce_nvram_write_dword(sc, addr, 2577 &flash_buffer[i], cmd_flags); 2578 2579 if (rc != 0) 2580 goto bce_nvram_write_locked_exit; 2581 2582 cmd_flags = 0; 2583 } 2584 } 2585 2586 /* Disable writes to flash interface (lock write-protect) */ 2587 bce_disable_nvram_write(sc); 2588 2589 /* Disable access to flash interface */ 2590 bce_disable_nvram_access(sc); 2591 bce_release_nvram_lock(sc); 2592 2593 /* Increment written */ 2594 written += data_end - data_start; 2595 } 2596 2597 goto bce_nvram_write_exit; 2598 2599 bce_nvram_write_locked_exit: 2600 bce_disable_nvram_write(sc); 2601 bce_disable_nvram_access(sc); 2602 bce_release_nvram_lock(sc); 2603 2604 bce_nvram_write_exit: 2605 if (align_start || align_end) 2606 free(buf, M_DEVBUF); 2607 2608 DBEXIT(BCE_VERBOSE_NVRAM); 2609 return (rc); 2610 } 2611 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2612 2613 2614 /****************************************************************************/ 2615 /* Verifies that NVRAM is accessible and contains valid data. */ 2616 /* */ 2617 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2618 /* correct. */ 2619 /* */ 2620 /* Returns: */ 2621 /* 0 on success, positive value on failure. */ 2622 /****************************************************************************/ 2623 static int 2624 bce_nvram_test(struct bce_softc *sc) 2625 { 2626 u32 buf[BCE_NVRAM_SIZE / 4]; 2627 u8 *data = (u8 *) buf; 2628 int rc = 0; 2629 u32 magic, csum; 2630 2631 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2632 2633 /* 2634 * Check that the device NVRAM is valid by reading 2635 * the magic value at offset 0. 2636 */ 2637 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2638 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2639 __FILE__, __LINE__); 2640 goto bce_nvram_test_exit; 2641 } 2642 2643 /* 2644 * Verify that offset 0 of the NVRAM contains 2645 * a valid magic number. 2646 */ 2647 magic = bce_be32toh(buf[0]); 2648 if (magic != BCE_NVRAM_MAGIC) { 2649 rc = ENODEV; 2650 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2651 "Expected: 0x%08X, Found: 0x%08X\n", 2652 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2653 goto bce_nvram_test_exit; 2654 } 2655 2656 /* 2657 * Verify that the device NVRAM includes valid 2658 * configuration data. 2659 */ 2660 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2661 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2662 "Information from NVRAM!\n", __FILE__, __LINE__); 2663 goto bce_nvram_test_exit; 2664 } 2665 2666 csum = ether_crc32_le(data, 0x100); 2667 if (csum != BCE_CRC32_RESIDUAL) { 2668 rc = ENODEV; 2669 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2670 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2671 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2672 goto bce_nvram_test_exit; 2673 } 2674 2675 csum = ether_crc32_le(data + 0x100, 0x100); 2676 if (csum != BCE_CRC32_RESIDUAL) { 2677 rc = ENODEV; 2678 BCE_PRINTF("%s(%d): Invalid feature configuration " 2679 "information NVRAM CRC! Expected: 0x%08X, " 2680 "Found: 08%08X\n", __FILE__, __LINE__, 2681 BCE_CRC32_RESIDUAL, csum); 2682 } 2683 2684 bce_nvram_test_exit: 2685 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2686 return rc; 2687 } 2688 2689 2690 /****************************************************************************/ 2691 /* Identifies the current media type of the controller and sets the PHY */ 2692 /* address. */ 2693 /* */ 2694 /* Returns: */ 2695 /* Nothing. */ 2696 /****************************************************************************/ 2697 static void 2698 bce_get_media(struct bce_softc *sc) 2699 { 2700 u32 val; 2701 2702 DBENTER(BCE_VERBOSE_PHY); 2703 2704 /* Assume PHY address for copper controllers. */ 2705 sc->bce_phy_addr = 1; 2706 2707 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2708 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 2709 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2710 u32 strap; 2711 2712 /* 2713 * The BCM5709S is software configurable 2714 * for Copper or SerDes operation. 2715 */ 2716 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2717 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 2718 "for copper.\n"); 2719 goto bce_get_media_exit; 2720 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2721 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 2722 "for dual media.\n"); 2723 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2724 goto bce_get_media_exit; 2725 } 2726 2727 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2728 strap = (val & 2729 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2730 else 2731 strap = (val & 2732 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 2733 2734 if (pci_get_function(sc->bce_dev) == 0) { 2735 switch (strap) { 2736 case 0x4: 2737 case 0x5: 2738 case 0x6: 2739 DBPRINT(sc, BCE_INFO_LOAD, 2740 "BCM5709 s/w configured for SerDes.\n"); 2741 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2742 break; 2743 default: 2744 DBPRINT(sc, BCE_INFO_LOAD, 2745 "BCM5709 s/w configured for Copper.\n"); 2746 break; 2747 } 2748 } else { 2749 switch (strap) { 2750 case 0x1: 2751 case 0x2: 2752 case 0x4: 2753 DBPRINT(sc, BCE_INFO_LOAD, 2754 "BCM5709 s/w configured for SerDes.\n"); 2755 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2756 break; 2757 default: 2758 DBPRINT(sc, BCE_INFO_LOAD, 2759 "BCM5709 s/w configured for Copper.\n"); 2760 break; 2761 } 2762 } 2763 2764 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 2765 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2766 2767 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 2768 2769 sc->bce_flags |= BCE_NO_WOL_FLAG; 2770 2771 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 2772 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 2773 2774 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2775 /* 5708S/09S/16S use a separate PHY for SerDes. */ 2776 sc->bce_phy_addr = 2; 2777 2778 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 2779 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 2780 sc->bce_phy_flags |= 2781 BCE_PHY_2_5G_CAPABLE_FLAG; 2782 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 2783 "capable adapter\n"); 2784 } 2785 } 2786 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 2787 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 2788 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 2789 2790 bce_get_media_exit: 2791 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 2792 "Using PHY address %d.\n", sc->bce_phy_addr); 2793 2794 DBEXIT(BCE_VERBOSE_PHY); 2795 } 2796 2797 2798 /****************************************************************************/ 2799 /* Performs PHY initialization required before MII drivers access the */ 2800 /* device. */ 2801 /* */ 2802 /* Returns: */ 2803 /* Nothing. */ 2804 /****************************************************************************/ 2805 static void 2806 bce_init_media(struct bce_softc *sc) 2807 { 2808 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 2809 /* 2810 * Configure 5709S/5716S PHYs to use traditional IEEE 2811 * Clause 22 method. Otherwise we have no way to attach 2812 * the PHY in mii(4) layer. PHY specific configuration 2813 * is done in mii layer. 2814 */ 2815 2816 /* Select auto-negotiation MMD of the PHY. */ 2817 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 2818 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 2819 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 2820 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 2821 2822 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 2823 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 2824 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 2825 } 2826 } 2827 2828 2829 /****************************************************************************/ 2830 /* Free any DMA memory owned by the driver. */ 2831 /* */ 2832 /* Scans through each data structre that requires DMA memory and frees */ 2833 /* the memory if allocated. */ 2834 /* */ 2835 /* Returns: */ 2836 /* Nothing. */ 2837 /****************************************************************************/ 2838 static void 2839 bce_dma_free(struct bce_softc *sc) 2840 { 2841 int i; 2842 2843 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 2844 2845 /* Free, unmap, and destroy the status block. */ 2846 if (sc->status_block != NULL) { 2847 bus_dmamem_free( 2848 sc->status_tag, 2849 sc->status_block, 2850 sc->status_map); 2851 sc->status_block = NULL; 2852 } 2853 2854 if (sc->status_map != NULL) { 2855 bus_dmamap_unload( 2856 sc->status_tag, 2857 sc->status_map); 2858 bus_dmamap_destroy(sc->status_tag, 2859 sc->status_map); 2860 sc->status_map = NULL; 2861 } 2862 2863 if (sc->status_tag != NULL) { 2864 bus_dma_tag_destroy(sc->status_tag); 2865 sc->status_tag = NULL; 2866 } 2867 2868 2869 /* Free, unmap, and destroy the statistics block. */ 2870 if (sc->stats_block != NULL) { 2871 bus_dmamem_free( 2872 sc->stats_tag, 2873 sc->stats_block, 2874 sc->stats_map); 2875 sc->stats_block = NULL; 2876 } 2877 2878 if (sc->stats_map != NULL) { 2879 bus_dmamap_unload( 2880 sc->stats_tag, 2881 sc->stats_map); 2882 bus_dmamap_destroy(sc->stats_tag, 2883 sc->stats_map); 2884 sc->stats_map = NULL; 2885 } 2886 2887 if (sc->stats_tag != NULL) { 2888 bus_dma_tag_destroy(sc->stats_tag); 2889 sc->stats_tag = NULL; 2890 } 2891 2892 2893 /* Free, unmap and destroy all context memory pages. */ 2894 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2895 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2896 for (i = 0; i < sc->ctx_pages; i++ ) { 2897 if (sc->ctx_block[i] != NULL) { 2898 bus_dmamem_free( 2899 sc->ctx_tag, 2900 sc->ctx_block[i], 2901 sc->ctx_map[i]); 2902 sc->ctx_block[i] = NULL; 2903 } 2904 2905 if (sc->ctx_map[i] != NULL) { 2906 bus_dmamap_unload( 2907 sc->ctx_tag, 2908 sc->ctx_map[i]); 2909 bus_dmamap_destroy( 2910 sc->ctx_tag, 2911 sc->ctx_map[i]); 2912 sc->ctx_map[i] = NULL; 2913 } 2914 } 2915 2916 /* Destroy the context memory tag. */ 2917 if (sc->ctx_tag != NULL) { 2918 bus_dma_tag_destroy(sc->ctx_tag); 2919 sc->ctx_tag = NULL; 2920 } 2921 } 2922 2923 2924 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2925 for (i = 0; i < TX_PAGES; i++ ) { 2926 if (sc->tx_bd_chain[i] != NULL) { 2927 bus_dmamem_free( 2928 sc->tx_bd_chain_tag, 2929 sc->tx_bd_chain[i], 2930 sc->tx_bd_chain_map[i]); 2931 sc->tx_bd_chain[i] = NULL; 2932 } 2933 2934 if (sc->tx_bd_chain_map[i] != NULL) { 2935 bus_dmamap_unload( 2936 sc->tx_bd_chain_tag, 2937 sc->tx_bd_chain_map[i]); 2938 bus_dmamap_destroy( 2939 sc->tx_bd_chain_tag, 2940 sc->tx_bd_chain_map[i]); 2941 sc->tx_bd_chain_map[i] = NULL; 2942 } 2943 } 2944 2945 /* Destroy the TX buffer descriptor tag. */ 2946 if (sc->tx_bd_chain_tag != NULL) { 2947 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2948 sc->tx_bd_chain_tag = NULL; 2949 } 2950 2951 2952 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2953 for (i = 0; i < RX_PAGES; i++ ) { 2954 if (sc->rx_bd_chain[i] != NULL) { 2955 bus_dmamem_free( 2956 sc->rx_bd_chain_tag, 2957 sc->rx_bd_chain[i], 2958 sc->rx_bd_chain_map[i]); 2959 sc->rx_bd_chain[i] = NULL; 2960 } 2961 2962 if (sc->rx_bd_chain_map[i] != NULL) { 2963 bus_dmamap_unload( 2964 sc->rx_bd_chain_tag, 2965 sc->rx_bd_chain_map[i]); 2966 bus_dmamap_destroy( 2967 sc->rx_bd_chain_tag, 2968 sc->rx_bd_chain_map[i]); 2969 sc->rx_bd_chain_map[i] = NULL; 2970 } 2971 } 2972 2973 /* Destroy the RX buffer descriptor tag. */ 2974 if (sc->rx_bd_chain_tag != NULL) { 2975 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2976 sc->rx_bd_chain_tag = NULL; 2977 } 2978 2979 2980 #ifdef BCE_JUMBO_HDRSPLIT 2981 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 2982 for (i = 0; i < PG_PAGES; i++ ) { 2983 if (sc->pg_bd_chain[i] != NULL) { 2984 bus_dmamem_free( 2985 sc->pg_bd_chain_tag, 2986 sc->pg_bd_chain[i], 2987 sc->pg_bd_chain_map[i]); 2988 sc->pg_bd_chain[i] = NULL; 2989 } 2990 2991 if (sc->pg_bd_chain_map[i] != NULL) { 2992 bus_dmamap_unload( 2993 sc->pg_bd_chain_tag, 2994 sc->pg_bd_chain_map[i]); 2995 bus_dmamap_destroy( 2996 sc->pg_bd_chain_tag, 2997 sc->pg_bd_chain_map[i]); 2998 sc->pg_bd_chain_map[i] = NULL; 2999 } 3000 } 3001 3002 /* Destroy the page buffer descriptor tag. */ 3003 if (sc->pg_bd_chain_tag != NULL) { 3004 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3005 sc->pg_bd_chain_tag = NULL; 3006 } 3007 #endif 3008 3009 3010 /* Unload and destroy the TX mbuf maps. */ 3011 for (i = 0; i < TOTAL_TX_BD; i++) { 3012 if (sc->tx_mbuf_map[i] != NULL) { 3013 bus_dmamap_unload(sc->tx_mbuf_tag, 3014 sc->tx_mbuf_map[i]); 3015 bus_dmamap_destroy(sc->tx_mbuf_tag, 3016 sc->tx_mbuf_map[i]); 3017 sc->tx_mbuf_map[i] = NULL; 3018 } 3019 } 3020 3021 /* Destroy the TX mbuf tag. */ 3022 if (sc->tx_mbuf_tag != NULL) { 3023 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3024 sc->tx_mbuf_tag = NULL; 3025 } 3026 3027 /* Unload and destroy the RX mbuf maps. */ 3028 for (i = 0; i < TOTAL_RX_BD; i++) { 3029 if (sc->rx_mbuf_map[i] != NULL) { 3030 bus_dmamap_unload(sc->rx_mbuf_tag, 3031 sc->rx_mbuf_map[i]); 3032 bus_dmamap_destroy(sc->rx_mbuf_tag, 3033 sc->rx_mbuf_map[i]); 3034 sc->rx_mbuf_map[i] = NULL; 3035 } 3036 } 3037 3038 /* Destroy the RX mbuf tag. */ 3039 if (sc->rx_mbuf_tag != NULL) { 3040 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3041 sc->rx_mbuf_tag = NULL; 3042 } 3043 3044 #ifdef BCE_JUMBO_HDRSPLIT 3045 /* Unload and destroy the page mbuf maps. */ 3046 for (i = 0; i < TOTAL_PG_BD; i++) { 3047 if (sc->pg_mbuf_map[i] != NULL) { 3048 bus_dmamap_unload(sc->pg_mbuf_tag, 3049 sc->pg_mbuf_map[i]); 3050 bus_dmamap_destroy(sc->pg_mbuf_tag, 3051 sc->pg_mbuf_map[i]); 3052 sc->pg_mbuf_map[i] = NULL; 3053 } 3054 } 3055 3056 /* Destroy the page mbuf tag. */ 3057 if (sc->pg_mbuf_tag != NULL) { 3058 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3059 sc->pg_mbuf_tag = NULL; 3060 } 3061 #endif 3062 3063 /* Destroy the parent tag */ 3064 if (sc->parent_tag != NULL) { 3065 bus_dma_tag_destroy(sc->parent_tag); 3066 sc->parent_tag = NULL; 3067 } 3068 3069 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3070 } 3071 3072 3073 /****************************************************************************/ 3074 /* Get DMA memory from the OS. */ 3075 /* */ 3076 /* Validates that the OS has provided DMA buffers in response to a */ 3077 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3078 /* When the callback is used the OS will return 0 for the mapping function */ 3079 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3080 /* failures back to the caller. */ 3081 /* */ 3082 /* Returns: */ 3083 /* Nothing. */ 3084 /****************************************************************************/ 3085 static void 3086 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3087 { 3088 bus_addr_t *busaddr = arg; 3089 3090 /* Simulate a mapping failure. */ 3091 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3092 error = ENOMEM); 3093 3094 /* ToDo: How to increment debug sim_count variable here? */ 3095 3096 /* Check for an error and signal the caller that an error occurred. */ 3097 if (error) { 3098 *busaddr = 0; 3099 } else { 3100 *busaddr = segs->ds_addr; 3101 } 3102 3103 return; 3104 } 3105 3106 3107 /****************************************************************************/ 3108 /* Allocate any DMA memory needed by the driver. */ 3109 /* */ 3110 /* Allocates DMA memory needed for the various global structures needed by */ 3111 /* hardware. */ 3112 /* */ 3113 /* Memory alignment requirements: */ 3114 /* +-----------------+----------+----------+----------+----------+ */ 3115 /* | | 5706 | 5708 | 5709 | 5716 | */ 3116 /* +-----------------+----------+----------+----------+----------+ */ 3117 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3118 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3119 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3120 /* |PG Buffers | none | none | none | none | */ 3121 /* |TX Buffers | none | none | none | none | */ 3122 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3123 /* |Context Memory | | | | | */ 3124 /* +-----------------+----------+----------+----------+----------+ */ 3125 /* */ 3126 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3127 /* */ 3128 /* Returns: */ 3129 /* 0 for success, positive value for failure. */ 3130 /****************************************************************************/ 3131 static int 3132 bce_dma_alloc(device_t dev) 3133 { 3134 struct bce_softc *sc; 3135 int i, error, rc = 0; 3136 bus_size_t max_size, max_seg_size; 3137 int max_segments; 3138 3139 sc = device_get_softc(dev); 3140 3141 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3142 3143 /* 3144 * Allocate the parent bus DMA tag appropriate for PCI. 3145 */ 3146 if (bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY, 3147 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3148 MAXBSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE_32BIT, 3149 0, NULL, NULL, &sc->parent_tag)) { 3150 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3151 __FILE__, __LINE__); 3152 rc = ENOMEM; 3153 goto bce_dma_alloc_exit; 3154 } 3155 3156 /* 3157 * Create a DMA tag for the status block, allocate and clear the 3158 * memory, map the memory into DMA space, and fetch the physical 3159 * address of the block. 3160 */ 3161 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3162 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3163 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3164 0, NULL, NULL, &sc->status_tag)) { 3165 BCE_PRINTF("%s(%d): Could not allocate status block " 3166 "DMA tag!\n", __FILE__, __LINE__); 3167 rc = ENOMEM; 3168 goto bce_dma_alloc_exit; 3169 } 3170 3171 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3172 BUS_DMA_NOWAIT, &sc->status_map)) { 3173 BCE_PRINTF("%s(%d): Could not allocate status block " 3174 "DMA memory!\n", __FILE__, __LINE__); 3175 rc = ENOMEM; 3176 goto bce_dma_alloc_exit; 3177 } 3178 3179 bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 3180 3181 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3182 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3183 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3184 3185 if (error) { 3186 BCE_PRINTF("%s(%d): Could not map status block " 3187 "DMA memory!\n", __FILE__, __LINE__); 3188 rc = ENOMEM; 3189 goto bce_dma_alloc_exit; 3190 } 3191 3192 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3193 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3194 3195 /* 3196 * Create a DMA tag for the statistics block, allocate and clear the 3197 * memory, map the memory into DMA space, and fetch the physical 3198 * address of the block. 3199 */ 3200 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3201 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3202 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3203 0, NULL, NULL, &sc->stats_tag)) { 3204 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3205 "DMA tag!\n", __FILE__, __LINE__); 3206 rc = ENOMEM; 3207 goto bce_dma_alloc_exit; 3208 } 3209 3210 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3211 BUS_DMA_NOWAIT, &sc->stats_map)) { 3212 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3213 "DMA memory!\n", __FILE__, __LINE__); 3214 rc = ENOMEM; 3215 goto bce_dma_alloc_exit; 3216 } 3217 3218 bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 3219 3220 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3221 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3222 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3223 3224 if(error) { 3225 BCE_PRINTF("%s(%d): Could not map statistics block " 3226 "DMA memory!\n", __FILE__, __LINE__); 3227 rc = ENOMEM; 3228 goto bce_dma_alloc_exit; 3229 } 3230 3231 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3232 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3233 3234 /* BCM5709 uses host memory as cache for context memory. */ 3235 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3236 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3237 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3238 if (sc->ctx_pages == 0) 3239 sc->ctx_pages = 1; 3240 3241 DBRUNIF((sc->ctx_pages > 512), 3242 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3243 __FILE__, __LINE__, sc->ctx_pages)); 3244 3245 /* 3246 * Create a DMA tag for the context pages, 3247 * allocate and clear the memory, map the 3248 * memory into DMA space, and fetch the 3249 * physical address of the block. 3250 */ 3251 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3252 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3253 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3254 0, NULL, NULL, &sc->ctx_tag)) { 3255 BCE_PRINTF("%s(%d): Could not allocate CTX " 3256 "DMA tag!\n", __FILE__, __LINE__); 3257 rc = ENOMEM; 3258 goto bce_dma_alloc_exit; 3259 } 3260 3261 for (i = 0; i < sc->ctx_pages; i++) { 3262 3263 if(bus_dmamem_alloc(sc->ctx_tag, 3264 (void **)&sc->ctx_block[i], 3265 BUS_DMA_NOWAIT, 3266 &sc->ctx_map[i])) { 3267 BCE_PRINTF("%s(%d): Could not allocate CTX " 3268 "DMA memory!\n", __FILE__, __LINE__); 3269 rc = ENOMEM; 3270 goto bce_dma_alloc_exit; 3271 } 3272 3273 bzero((char *)sc->ctx_block[i], BCM_PAGE_SIZE); 3274 3275 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3276 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3277 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3278 3279 if (error) { 3280 BCE_PRINTF("%s(%d): Could not map CTX " 3281 "DMA memory!\n", __FILE__, __LINE__); 3282 rc = ENOMEM; 3283 goto bce_dma_alloc_exit; 3284 } 3285 3286 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3287 "= 0x%jX\n", __FUNCTION__, i, 3288 (uintmax_t) sc->ctx_paddr[i]); 3289 } 3290 } 3291 3292 /* 3293 * Create a DMA tag for the TX buffer descriptor chain, 3294 * allocate and clear the memory, and fetch the 3295 * physical address of the block. 3296 */ 3297 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3298 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3299 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3300 NULL, NULL, &sc->tx_bd_chain_tag)) { 3301 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3302 "chain DMA tag!\n", __FILE__, __LINE__); 3303 rc = ENOMEM; 3304 goto bce_dma_alloc_exit; 3305 } 3306 3307 for (i = 0; i < TX_PAGES; i++) { 3308 3309 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3310 (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT, 3311 &sc->tx_bd_chain_map[i])) { 3312 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3313 "chain DMA memory!\n", __FILE__, __LINE__); 3314 rc = ENOMEM; 3315 goto bce_dma_alloc_exit; 3316 } 3317 3318 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3319 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3320 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3321 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3322 3323 if (error) { 3324 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3325 "chain DMA memory!\n", __FILE__, __LINE__); 3326 rc = ENOMEM; 3327 goto bce_dma_alloc_exit; 3328 } 3329 3330 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3331 "0x%jX\n", __FUNCTION__, i, 3332 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3333 } 3334 3335 /* Check the required size before mapping to conserve resources. */ 3336 if (bce_tso_enable) { 3337 max_size = BCE_TSO_MAX_SIZE; 3338 max_segments = BCE_MAX_SEGMENTS; 3339 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3340 } else { 3341 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3342 max_segments = BCE_MAX_SEGMENTS; 3343 max_seg_size = MCLBYTES; 3344 } 3345 3346 /* Create a DMA tag for TX mbufs. */ 3347 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3348 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3349 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3350 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3351 __FILE__, __LINE__); 3352 rc = ENOMEM; 3353 goto bce_dma_alloc_exit; 3354 } 3355 3356 /* Create DMA maps for the TX mbufs clusters. */ 3357 for (i = 0; i < TOTAL_TX_BD; i++) { 3358 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3359 &sc->tx_mbuf_map[i])) { 3360 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3361 "map!\n", __FILE__, __LINE__); 3362 rc = ENOMEM; 3363 goto bce_dma_alloc_exit; 3364 } 3365 } 3366 3367 /* 3368 * Create a DMA tag for the RX buffer descriptor chain, 3369 * allocate and clear the memory, and fetch the physical 3370 * address of the blocks. 3371 */ 3372 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3373 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3374 sc->max_bus_addr, NULL, NULL, 3375 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3376 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3377 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3378 "DMA tag!\n", __FILE__, __LINE__); 3379 rc = ENOMEM; 3380 goto bce_dma_alloc_exit; 3381 } 3382 3383 for (i = 0; i < RX_PAGES; i++) { 3384 3385 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3386 (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT, 3387 &sc->rx_bd_chain_map[i])) { 3388 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3389 "chain DMA memory!\n", __FILE__, __LINE__); 3390 rc = ENOMEM; 3391 goto bce_dma_alloc_exit; 3392 } 3393 3394 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3395 3396 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3397 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3398 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3399 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3400 3401 if (error) { 3402 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3403 "chain DMA memory!\n", __FILE__, __LINE__); 3404 rc = ENOMEM; 3405 goto bce_dma_alloc_exit; 3406 } 3407 3408 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3409 "0x%jX\n", __FUNCTION__, i, 3410 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3411 } 3412 3413 /* 3414 * Create a DMA tag for RX mbufs. 3415 */ 3416 #ifdef BCE_JUMBO_HDRSPLIT 3417 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3418 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3419 #else 3420 max_size = max_seg_size = MJUM9BYTES; 3421 #endif 3422 max_segments = 1; 3423 3424 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3425 "(max size = 0x%jX max segments = %d, max segment " 3426 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, 3427 max_segments, (uintmax_t) max_seg_size); 3428 3429 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3430 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3431 max_segments, max_seg_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3432 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3433 __FILE__, __LINE__); 3434 rc = ENOMEM; 3435 goto bce_dma_alloc_exit; 3436 } 3437 3438 /* Create DMA maps for the RX mbuf clusters. */ 3439 for (i = 0; i < TOTAL_RX_BD; i++) { 3440 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3441 &sc->rx_mbuf_map[i])) { 3442 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3443 "DMA map!\n", __FILE__, __LINE__); 3444 rc = ENOMEM; 3445 goto bce_dma_alloc_exit; 3446 } 3447 } 3448 3449 #ifdef BCE_JUMBO_HDRSPLIT 3450 /* 3451 * Create a DMA tag for the page buffer descriptor chain, 3452 * allocate and clear the memory, and fetch the physical 3453 * address of the blocks. 3454 */ 3455 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3456 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3457 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3458 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3459 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3460 "chain DMA tag!\n", __FILE__, __LINE__); 3461 rc = ENOMEM; 3462 goto bce_dma_alloc_exit; 3463 } 3464 3465 for (i = 0; i < PG_PAGES; i++) { 3466 3467 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3468 (void **)&sc->pg_bd_chain[i], BUS_DMA_NOWAIT, 3469 &sc->pg_bd_chain_map[i])) { 3470 BCE_PRINTF("%s(%d): Could not allocate page " 3471 "descriptor chain DMA memory!\n", 3472 __FILE__, __LINE__); 3473 rc = ENOMEM; 3474 goto bce_dma_alloc_exit; 3475 } 3476 3477 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 3478 3479 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3480 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3481 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3482 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3483 3484 if (error) { 3485 BCE_PRINTF("%s(%d): Could not map page descriptor " 3486 "chain DMA memory!\n", __FILE__, __LINE__); 3487 rc = ENOMEM; 3488 goto bce_dma_alloc_exit; 3489 } 3490 3491 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3492 "0x%jX\n", __FUNCTION__, i, 3493 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3494 } 3495 3496 /* 3497 * Create a DMA tag for page mbufs. 3498 */ 3499 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3500 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3501 3502 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3503 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3504 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3505 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3506 "DMA tag!\n", __FILE__, __LINE__); 3507 rc = ENOMEM; 3508 goto bce_dma_alloc_exit; 3509 } 3510 3511 /* Create DMA maps for the page mbuf clusters. */ 3512 for (i = 0; i < TOTAL_PG_BD; i++) { 3513 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3514 &sc->pg_mbuf_map[i])) { 3515 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3516 "DMA map!\n", __FILE__, __LINE__); 3517 rc = ENOMEM; 3518 goto bce_dma_alloc_exit; 3519 } 3520 } 3521 #endif 3522 3523 bce_dma_alloc_exit: 3524 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3525 return(rc); 3526 } 3527 3528 3529 /****************************************************************************/ 3530 /* Release all resources used by the driver. */ 3531 /* */ 3532 /* Releases all resources acquired by the driver including interrupts, */ 3533 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3534 /* */ 3535 /* Returns: */ 3536 /* Nothing. */ 3537 /****************************************************************************/ 3538 static void 3539 bce_release_resources(struct bce_softc *sc) 3540 { 3541 device_t dev; 3542 3543 DBENTER(BCE_VERBOSE_RESET); 3544 3545 dev = sc->bce_dev; 3546 3547 bce_dma_free(sc); 3548 3549 if (sc->bce_intrhand != NULL) { 3550 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3551 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3552 } 3553 3554 if (sc->bce_res_irq != NULL) { 3555 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3556 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3557 sc->bce_res_irq); 3558 } 3559 3560 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3561 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3562 pci_release_msi(dev); 3563 } 3564 3565 if (sc->bce_res_mem != NULL) { 3566 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3567 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3568 sc->bce_res_mem); 3569 } 3570 3571 if (sc->bce_ifp != NULL) { 3572 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3573 if_free(sc->bce_ifp); 3574 } 3575 3576 if (mtx_initialized(&sc->bce_mtx)) 3577 BCE_LOCK_DESTROY(sc); 3578 3579 DBEXIT(BCE_VERBOSE_RESET); 3580 } 3581 3582 3583 /****************************************************************************/ 3584 /* Firmware synchronization. */ 3585 /* */ 3586 /* Before performing certain events such as a chip reset, synchronize with */ 3587 /* the firmware first. */ 3588 /* */ 3589 /* Returns: */ 3590 /* 0 for success, positive value for failure. */ 3591 /****************************************************************************/ 3592 static int 3593 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3594 { 3595 int i, rc = 0; 3596 u32 val; 3597 3598 DBENTER(BCE_VERBOSE_RESET); 3599 3600 /* Don't waste any time if we've timed out before. */ 3601 if (sc->bce_fw_timed_out == TRUE) { 3602 rc = EBUSY; 3603 goto bce_fw_sync_exit; 3604 } 3605 3606 /* Increment the message sequence number. */ 3607 sc->bce_fw_wr_seq++; 3608 msg_data |= sc->bce_fw_wr_seq; 3609 3610 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3611 "0x%08X\n", msg_data); 3612 3613 /* Send the message to the bootcode driver mailbox. */ 3614 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3615 3616 /* Wait for the bootcode to acknowledge the message. */ 3617 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3618 /* Check for a response in the bootcode firmware mailbox. */ 3619 val = bce_shmem_rd(sc, BCE_FW_MB); 3620 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3621 break; 3622 DELAY(1000); 3623 } 3624 3625 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3626 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3627 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3628 3629 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3630 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3631 3632 msg_data &= ~BCE_DRV_MSG_CODE; 3633 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3634 3635 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3636 3637 sc->bce_fw_timed_out = TRUE; 3638 rc = EBUSY; 3639 } 3640 3641 bce_fw_sync_exit: 3642 DBEXIT(BCE_VERBOSE_RESET); 3643 return (rc); 3644 } 3645 3646 3647 /****************************************************************************/ 3648 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3649 /* */ 3650 /* Returns: */ 3651 /* Nothing. */ 3652 /****************************************************************************/ 3653 static void 3654 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3655 u32 rv2p_code_len, u32 rv2p_proc) 3656 { 3657 int i; 3658 u32 val; 3659 3660 DBENTER(BCE_VERBOSE_RESET); 3661 3662 /* Set the page size used by RV2P. */ 3663 if (rv2p_proc == RV2P_PROC2) { 3664 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3665 } 3666 3667 for (i = 0; i < rv2p_code_len; i += 8) { 3668 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3669 rv2p_code++; 3670 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3671 rv2p_code++; 3672 3673 if (rv2p_proc == RV2P_PROC1) { 3674 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3675 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3676 } 3677 else { 3678 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3679 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3680 } 3681 } 3682 3683 /* Reset the processor, un-stall is done later. */ 3684 if (rv2p_proc == RV2P_PROC1) { 3685 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3686 } 3687 else { 3688 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3689 } 3690 3691 DBEXIT(BCE_VERBOSE_RESET); 3692 } 3693 3694 3695 /****************************************************************************/ 3696 /* Load RISC processor firmware. */ 3697 /* */ 3698 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3699 /* associated with a particular processor. */ 3700 /* */ 3701 /* Returns: */ 3702 /* Nothing. */ 3703 /****************************************************************************/ 3704 static void 3705 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3706 struct fw_info *fw) 3707 { 3708 u32 offset; 3709 3710 DBENTER(BCE_VERBOSE_RESET); 3711 3712 bce_halt_cpu(sc, cpu_reg); 3713 3714 /* Load the Text area. */ 3715 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 3716 if (fw->text) { 3717 int j; 3718 3719 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 3720 REG_WR_IND(sc, offset, fw->text[j]); 3721 } 3722 } 3723 3724 /* Load the Data area. */ 3725 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 3726 if (fw->data) { 3727 int j; 3728 3729 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 3730 REG_WR_IND(sc, offset, fw->data[j]); 3731 } 3732 } 3733 3734 /* Load the SBSS area. */ 3735 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 3736 if (fw->sbss) { 3737 int j; 3738 3739 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 3740 REG_WR_IND(sc, offset, fw->sbss[j]); 3741 } 3742 } 3743 3744 /* Load the BSS area. */ 3745 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 3746 if (fw->bss) { 3747 int j; 3748 3749 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 3750 REG_WR_IND(sc, offset, fw->bss[j]); 3751 } 3752 } 3753 3754 /* Load the Read-Only area. */ 3755 offset = cpu_reg->spad_base + 3756 (fw->rodata_addr - cpu_reg->mips_view_base); 3757 if (fw->rodata) { 3758 int j; 3759 3760 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 3761 REG_WR_IND(sc, offset, fw->rodata[j]); 3762 } 3763 } 3764 3765 /* Clear the pre-fetch instruction and set the FW start address. */ 3766 REG_WR_IND(sc, cpu_reg->inst, 0); 3767 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 3768 3769 DBEXIT(BCE_VERBOSE_RESET); 3770 } 3771 3772 3773 /****************************************************************************/ 3774 /* Starts the RISC processor. */ 3775 /* */ 3776 /* Assumes the CPU starting address has already been set. */ 3777 /* */ 3778 /* Returns: */ 3779 /* Nothing. */ 3780 /****************************************************************************/ 3781 static void 3782 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 3783 { 3784 u32 val; 3785 3786 DBENTER(BCE_VERBOSE_RESET); 3787 3788 /* Start the CPU. */ 3789 val = REG_RD_IND(sc, cpu_reg->mode); 3790 val &= ~cpu_reg->mode_value_halt; 3791 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3792 REG_WR_IND(sc, cpu_reg->mode, val); 3793 3794 DBEXIT(BCE_VERBOSE_RESET); 3795 } 3796 3797 3798 /****************************************************************************/ 3799 /* Halts the RISC processor. */ 3800 /* */ 3801 /* Returns: */ 3802 /* Nothing. */ 3803 /****************************************************************************/ 3804 static void 3805 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 3806 { 3807 u32 val; 3808 3809 DBENTER(BCE_VERBOSE_RESET); 3810 3811 /* Halt the CPU. */ 3812 val = REG_RD_IND(sc, cpu_reg->mode); 3813 val |= cpu_reg->mode_value_halt; 3814 REG_WR_IND(sc, cpu_reg->mode, val); 3815 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3816 3817 DBEXIT(BCE_VERBOSE_RESET); 3818 } 3819 3820 3821 /****************************************************************************/ 3822 /* Initialize the RX CPU. */ 3823 /* */ 3824 /* Returns: */ 3825 /* Nothing. */ 3826 /****************************************************************************/ 3827 static void 3828 bce_start_rxp_cpu(struct bce_softc *sc) 3829 { 3830 struct cpu_reg cpu_reg; 3831 3832 DBENTER(BCE_VERBOSE_RESET); 3833 3834 cpu_reg.mode = BCE_RXP_CPU_MODE; 3835 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3836 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3837 cpu_reg.state = BCE_RXP_CPU_STATE; 3838 cpu_reg.state_value_clear = 0xffffff; 3839 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3840 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3841 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3842 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3843 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3844 cpu_reg.spad_base = BCE_RXP_SCRATCH; 3845 cpu_reg.mips_view_base = 0x8000000; 3846 3847 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 3848 bce_start_cpu(sc, &cpu_reg); 3849 3850 DBEXIT(BCE_VERBOSE_RESET); 3851 } 3852 3853 3854 /****************************************************************************/ 3855 /* Initialize the RX CPU. */ 3856 /* */ 3857 /* Returns: */ 3858 /* Nothing. */ 3859 /****************************************************************************/ 3860 static void 3861 bce_init_rxp_cpu(struct bce_softc *sc) 3862 { 3863 struct cpu_reg cpu_reg; 3864 struct fw_info fw; 3865 3866 DBENTER(BCE_VERBOSE_RESET); 3867 3868 cpu_reg.mode = BCE_RXP_CPU_MODE; 3869 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3870 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3871 cpu_reg.state = BCE_RXP_CPU_STATE; 3872 cpu_reg.state_value_clear = 0xffffff; 3873 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3874 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3875 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3876 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3877 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3878 cpu_reg.spad_base = BCE_RXP_SCRATCH; 3879 cpu_reg.mips_view_base = 0x8000000; 3880 3881 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3882 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3883 fw.ver_major = bce_RXP_b09FwReleaseMajor; 3884 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 3885 fw.ver_fix = bce_RXP_b09FwReleaseFix; 3886 fw.start_addr = bce_RXP_b09FwStartAddr; 3887 3888 fw.text_addr = bce_RXP_b09FwTextAddr; 3889 fw.text_len = bce_RXP_b09FwTextLen; 3890 fw.text_index = 0; 3891 fw.text = bce_RXP_b09FwText; 3892 3893 fw.data_addr = bce_RXP_b09FwDataAddr; 3894 fw.data_len = bce_RXP_b09FwDataLen; 3895 fw.data_index = 0; 3896 fw.data = bce_RXP_b09FwData; 3897 3898 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 3899 fw.sbss_len = bce_RXP_b09FwSbssLen; 3900 fw.sbss_index = 0; 3901 fw.sbss = bce_RXP_b09FwSbss; 3902 3903 fw.bss_addr = bce_RXP_b09FwBssAddr; 3904 fw.bss_len = bce_RXP_b09FwBssLen; 3905 fw.bss_index = 0; 3906 fw.bss = bce_RXP_b09FwBss; 3907 3908 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 3909 fw.rodata_len = bce_RXP_b09FwRodataLen; 3910 fw.rodata_index = 0; 3911 fw.rodata = bce_RXP_b09FwRodata; 3912 } else { 3913 fw.ver_major = bce_RXP_b06FwReleaseMajor; 3914 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 3915 fw.ver_fix = bce_RXP_b06FwReleaseFix; 3916 fw.start_addr = bce_RXP_b06FwStartAddr; 3917 3918 fw.text_addr = bce_RXP_b06FwTextAddr; 3919 fw.text_len = bce_RXP_b06FwTextLen; 3920 fw.text_index = 0; 3921 fw.text = bce_RXP_b06FwText; 3922 3923 fw.data_addr = bce_RXP_b06FwDataAddr; 3924 fw.data_len = bce_RXP_b06FwDataLen; 3925 fw.data_index = 0; 3926 fw.data = bce_RXP_b06FwData; 3927 3928 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 3929 fw.sbss_len = bce_RXP_b06FwSbssLen; 3930 fw.sbss_index = 0; 3931 fw.sbss = bce_RXP_b06FwSbss; 3932 3933 fw.bss_addr = bce_RXP_b06FwBssAddr; 3934 fw.bss_len = bce_RXP_b06FwBssLen; 3935 fw.bss_index = 0; 3936 fw.bss = bce_RXP_b06FwBss; 3937 3938 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 3939 fw.rodata_len = bce_RXP_b06FwRodataLen; 3940 fw.rodata_index = 0; 3941 fw.rodata = bce_RXP_b06FwRodata; 3942 } 3943 3944 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 3945 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3946 3947 /* Delay RXP start until initialization is complete. */ 3948 3949 DBEXIT(BCE_VERBOSE_RESET); 3950 } 3951 3952 3953 /****************************************************************************/ 3954 /* Initialize the TX CPU. */ 3955 /* */ 3956 /* Returns: */ 3957 /* Nothing. */ 3958 /****************************************************************************/ 3959 static void 3960 bce_init_txp_cpu(struct bce_softc *sc) 3961 { 3962 struct cpu_reg cpu_reg; 3963 struct fw_info fw; 3964 3965 DBENTER(BCE_VERBOSE_RESET); 3966 3967 cpu_reg.mode = BCE_TXP_CPU_MODE; 3968 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 3969 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 3970 cpu_reg.state = BCE_TXP_CPU_STATE; 3971 cpu_reg.state_value_clear = 0xffffff; 3972 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 3973 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 3974 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 3975 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 3976 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 3977 cpu_reg.spad_base = BCE_TXP_SCRATCH; 3978 cpu_reg.mips_view_base = 0x8000000; 3979 3980 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3981 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3982 fw.ver_major = bce_TXP_b09FwReleaseMajor; 3983 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 3984 fw.ver_fix = bce_TXP_b09FwReleaseFix; 3985 fw.start_addr = bce_TXP_b09FwStartAddr; 3986 3987 fw.text_addr = bce_TXP_b09FwTextAddr; 3988 fw.text_len = bce_TXP_b09FwTextLen; 3989 fw.text_index = 0; 3990 fw.text = bce_TXP_b09FwText; 3991 3992 fw.data_addr = bce_TXP_b09FwDataAddr; 3993 fw.data_len = bce_TXP_b09FwDataLen; 3994 fw.data_index = 0; 3995 fw.data = bce_TXP_b09FwData; 3996 3997 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 3998 fw.sbss_len = bce_TXP_b09FwSbssLen; 3999 fw.sbss_index = 0; 4000 fw.sbss = bce_TXP_b09FwSbss; 4001 4002 fw.bss_addr = bce_TXP_b09FwBssAddr; 4003 fw.bss_len = bce_TXP_b09FwBssLen; 4004 fw.bss_index = 0; 4005 fw.bss = bce_TXP_b09FwBss; 4006 4007 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4008 fw.rodata_len = bce_TXP_b09FwRodataLen; 4009 fw.rodata_index = 0; 4010 fw.rodata = bce_TXP_b09FwRodata; 4011 } else { 4012 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4013 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4014 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4015 fw.start_addr = bce_TXP_b06FwStartAddr; 4016 4017 fw.text_addr = bce_TXP_b06FwTextAddr; 4018 fw.text_len = bce_TXP_b06FwTextLen; 4019 fw.text_index = 0; 4020 fw.text = bce_TXP_b06FwText; 4021 4022 fw.data_addr = bce_TXP_b06FwDataAddr; 4023 fw.data_len = bce_TXP_b06FwDataLen; 4024 fw.data_index = 0; 4025 fw.data = bce_TXP_b06FwData; 4026 4027 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4028 fw.sbss_len = bce_TXP_b06FwSbssLen; 4029 fw.sbss_index = 0; 4030 fw.sbss = bce_TXP_b06FwSbss; 4031 4032 fw.bss_addr = bce_TXP_b06FwBssAddr; 4033 fw.bss_len = bce_TXP_b06FwBssLen; 4034 fw.bss_index = 0; 4035 fw.bss = bce_TXP_b06FwBss; 4036 4037 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4038 fw.rodata_len = bce_TXP_b06FwRodataLen; 4039 fw.rodata_index = 0; 4040 fw.rodata = bce_TXP_b06FwRodata; 4041 } 4042 4043 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4044 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4045 bce_start_cpu(sc, &cpu_reg); 4046 4047 DBEXIT(BCE_VERBOSE_RESET); 4048 } 4049 4050 4051 /****************************************************************************/ 4052 /* Initialize the TPAT CPU. */ 4053 /* */ 4054 /* Returns: */ 4055 /* Nothing. */ 4056 /****************************************************************************/ 4057 static void 4058 bce_init_tpat_cpu(struct bce_softc *sc) 4059 { 4060 struct cpu_reg cpu_reg; 4061 struct fw_info fw; 4062 4063 DBENTER(BCE_VERBOSE_RESET); 4064 4065 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4066 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4067 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4068 cpu_reg.state = BCE_TPAT_CPU_STATE; 4069 cpu_reg.state_value_clear = 0xffffff; 4070 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4071 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4072 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4073 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4074 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4075 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4076 cpu_reg.mips_view_base = 0x8000000; 4077 4078 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4079 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4080 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4081 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4082 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4083 fw.start_addr = bce_TPAT_b09FwStartAddr; 4084 4085 fw.text_addr = bce_TPAT_b09FwTextAddr; 4086 fw.text_len = bce_TPAT_b09FwTextLen; 4087 fw.text_index = 0; 4088 fw.text = bce_TPAT_b09FwText; 4089 4090 fw.data_addr = bce_TPAT_b09FwDataAddr; 4091 fw.data_len = bce_TPAT_b09FwDataLen; 4092 fw.data_index = 0; 4093 fw.data = bce_TPAT_b09FwData; 4094 4095 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4096 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4097 fw.sbss_index = 0; 4098 fw.sbss = bce_TPAT_b09FwSbss; 4099 4100 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4101 fw.bss_len = bce_TPAT_b09FwBssLen; 4102 fw.bss_index = 0; 4103 fw.bss = bce_TPAT_b09FwBss; 4104 4105 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4106 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4107 fw.rodata_index = 0; 4108 fw.rodata = bce_TPAT_b09FwRodata; 4109 } else { 4110 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4111 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4112 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4113 fw.start_addr = bce_TPAT_b06FwStartAddr; 4114 4115 fw.text_addr = bce_TPAT_b06FwTextAddr; 4116 fw.text_len = bce_TPAT_b06FwTextLen; 4117 fw.text_index = 0; 4118 fw.text = bce_TPAT_b06FwText; 4119 4120 fw.data_addr = bce_TPAT_b06FwDataAddr; 4121 fw.data_len = bce_TPAT_b06FwDataLen; 4122 fw.data_index = 0; 4123 fw.data = bce_TPAT_b06FwData; 4124 4125 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4126 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4127 fw.sbss_index = 0; 4128 fw.sbss = bce_TPAT_b06FwSbss; 4129 4130 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4131 fw.bss_len = bce_TPAT_b06FwBssLen; 4132 fw.bss_index = 0; 4133 fw.bss = bce_TPAT_b06FwBss; 4134 4135 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4136 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4137 fw.rodata_index = 0; 4138 fw.rodata = bce_TPAT_b06FwRodata; 4139 } 4140 4141 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4142 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4143 bce_start_cpu(sc, &cpu_reg); 4144 4145 DBEXIT(BCE_VERBOSE_RESET); 4146 } 4147 4148 4149 /****************************************************************************/ 4150 /* Initialize the CP CPU. */ 4151 /* */ 4152 /* Returns: */ 4153 /* Nothing. */ 4154 /****************************************************************************/ 4155 static void 4156 bce_init_cp_cpu(struct bce_softc *sc) 4157 { 4158 struct cpu_reg cpu_reg; 4159 struct fw_info fw; 4160 4161 DBENTER(BCE_VERBOSE_RESET); 4162 4163 cpu_reg.mode = BCE_CP_CPU_MODE; 4164 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4165 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4166 cpu_reg.state = BCE_CP_CPU_STATE; 4167 cpu_reg.state_value_clear = 0xffffff; 4168 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4169 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4170 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4171 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4172 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4173 cpu_reg.spad_base = BCE_CP_SCRATCH; 4174 cpu_reg.mips_view_base = 0x8000000; 4175 4176 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4177 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4178 fw.ver_major = bce_CP_b09FwReleaseMajor; 4179 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4180 fw.ver_fix = bce_CP_b09FwReleaseFix; 4181 fw.start_addr = bce_CP_b09FwStartAddr; 4182 4183 fw.text_addr = bce_CP_b09FwTextAddr; 4184 fw.text_len = bce_CP_b09FwTextLen; 4185 fw.text_index = 0; 4186 fw.text = bce_CP_b09FwText; 4187 4188 fw.data_addr = bce_CP_b09FwDataAddr; 4189 fw.data_len = bce_CP_b09FwDataLen; 4190 fw.data_index = 0; 4191 fw.data = bce_CP_b09FwData; 4192 4193 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4194 fw.sbss_len = bce_CP_b09FwSbssLen; 4195 fw.sbss_index = 0; 4196 fw.sbss = bce_CP_b09FwSbss; 4197 4198 fw.bss_addr = bce_CP_b09FwBssAddr; 4199 fw.bss_len = bce_CP_b09FwBssLen; 4200 fw.bss_index = 0; 4201 fw.bss = bce_CP_b09FwBss; 4202 4203 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4204 fw.rodata_len = bce_CP_b09FwRodataLen; 4205 fw.rodata_index = 0; 4206 fw.rodata = bce_CP_b09FwRodata; 4207 } else { 4208 fw.ver_major = bce_CP_b06FwReleaseMajor; 4209 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4210 fw.ver_fix = bce_CP_b06FwReleaseFix; 4211 fw.start_addr = bce_CP_b06FwStartAddr; 4212 4213 fw.text_addr = bce_CP_b06FwTextAddr; 4214 fw.text_len = bce_CP_b06FwTextLen; 4215 fw.text_index = 0; 4216 fw.text = bce_CP_b06FwText; 4217 4218 fw.data_addr = bce_CP_b06FwDataAddr; 4219 fw.data_len = bce_CP_b06FwDataLen; 4220 fw.data_index = 0; 4221 fw.data = bce_CP_b06FwData; 4222 4223 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4224 fw.sbss_len = bce_CP_b06FwSbssLen; 4225 fw.sbss_index = 0; 4226 fw.sbss = bce_CP_b06FwSbss; 4227 4228 fw.bss_addr = bce_CP_b06FwBssAddr; 4229 fw.bss_len = bce_CP_b06FwBssLen; 4230 fw.bss_index = 0; 4231 fw.bss = bce_CP_b06FwBss; 4232 4233 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4234 fw.rodata_len = bce_CP_b06FwRodataLen; 4235 fw.rodata_index = 0; 4236 fw.rodata = bce_CP_b06FwRodata; 4237 } 4238 4239 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4240 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4241 bce_start_cpu(sc, &cpu_reg); 4242 4243 DBEXIT(BCE_VERBOSE_RESET); 4244 } 4245 4246 4247 /****************************************************************************/ 4248 /* Initialize the COM CPU. */ 4249 /* */ 4250 /* Returns: */ 4251 /* Nothing. */ 4252 /****************************************************************************/ 4253 static void 4254 bce_init_com_cpu(struct bce_softc *sc) 4255 { 4256 struct cpu_reg cpu_reg; 4257 struct fw_info fw; 4258 4259 DBENTER(BCE_VERBOSE_RESET); 4260 4261 cpu_reg.mode = BCE_COM_CPU_MODE; 4262 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4263 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4264 cpu_reg.state = BCE_COM_CPU_STATE; 4265 cpu_reg.state_value_clear = 0xffffff; 4266 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4267 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4268 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4269 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4270 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4271 cpu_reg.spad_base = BCE_COM_SCRATCH; 4272 cpu_reg.mips_view_base = 0x8000000; 4273 4274 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4275 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4276 fw.ver_major = bce_COM_b09FwReleaseMajor; 4277 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4278 fw.ver_fix = bce_COM_b09FwReleaseFix; 4279 fw.start_addr = bce_COM_b09FwStartAddr; 4280 4281 fw.text_addr = bce_COM_b09FwTextAddr; 4282 fw.text_len = bce_COM_b09FwTextLen; 4283 fw.text_index = 0; 4284 fw.text = bce_COM_b09FwText; 4285 4286 fw.data_addr = bce_COM_b09FwDataAddr; 4287 fw.data_len = bce_COM_b09FwDataLen; 4288 fw.data_index = 0; 4289 fw.data = bce_COM_b09FwData; 4290 4291 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4292 fw.sbss_len = bce_COM_b09FwSbssLen; 4293 fw.sbss_index = 0; 4294 fw.sbss = bce_COM_b09FwSbss; 4295 4296 fw.bss_addr = bce_COM_b09FwBssAddr; 4297 fw.bss_len = bce_COM_b09FwBssLen; 4298 fw.bss_index = 0; 4299 fw.bss = bce_COM_b09FwBss; 4300 4301 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4302 fw.rodata_len = bce_COM_b09FwRodataLen; 4303 fw.rodata_index = 0; 4304 fw.rodata = bce_COM_b09FwRodata; 4305 } else { 4306 fw.ver_major = bce_COM_b06FwReleaseMajor; 4307 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4308 fw.ver_fix = bce_COM_b06FwReleaseFix; 4309 fw.start_addr = bce_COM_b06FwStartAddr; 4310 4311 fw.text_addr = bce_COM_b06FwTextAddr; 4312 fw.text_len = bce_COM_b06FwTextLen; 4313 fw.text_index = 0; 4314 fw.text = bce_COM_b06FwText; 4315 4316 fw.data_addr = bce_COM_b06FwDataAddr; 4317 fw.data_len = bce_COM_b06FwDataLen; 4318 fw.data_index = 0; 4319 fw.data = bce_COM_b06FwData; 4320 4321 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4322 fw.sbss_len = bce_COM_b06FwSbssLen; 4323 fw.sbss_index = 0; 4324 fw.sbss = bce_COM_b06FwSbss; 4325 4326 fw.bss_addr = bce_COM_b06FwBssAddr; 4327 fw.bss_len = bce_COM_b06FwBssLen; 4328 fw.bss_index = 0; 4329 fw.bss = bce_COM_b06FwBss; 4330 4331 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4332 fw.rodata_len = bce_COM_b06FwRodataLen; 4333 fw.rodata_index = 0; 4334 fw.rodata = bce_COM_b06FwRodata; 4335 } 4336 4337 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4338 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4339 bce_start_cpu(sc, &cpu_reg); 4340 4341 DBEXIT(BCE_VERBOSE_RESET); 4342 } 4343 4344 4345 /****************************************************************************/ 4346 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4347 /* */ 4348 /* Loads the firmware for each CPU and starts the CPU. */ 4349 /* */ 4350 /* Returns: */ 4351 /* Nothing. */ 4352 /****************************************************************************/ 4353 static void 4354 bce_init_cpus(struct bce_softc *sc) 4355 { 4356 DBENTER(BCE_VERBOSE_RESET); 4357 4358 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4359 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4360 4361 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4362 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4363 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4364 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4365 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4366 } else { 4367 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4368 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4369 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4370 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4371 } 4372 4373 } else { 4374 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4375 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4376 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4377 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4378 } 4379 4380 bce_init_rxp_cpu(sc); 4381 bce_init_txp_cpu(sc); 4382 bce_init_tpat_cpu(sc); 4383 bce_init_com_cpu(sc); 4384 bce_init_cp_cpu(sc); 4385 4386 DBEXIT(BCE_VERBOSE_RESET); 4387 } 4388 4389 4390 /****************************************************************************/ 4391 /* Initialize context memory. */ 4392 /* */ 4393 /* Clears the memory associated with each Context ID (CID). */ 4394 /* */ 4395 /* Returns: */ 4396 /* Nothing. */ 4397 /****************************************************************************/ 4398 static void 4399 bce_init_ctx(struct bce_softc *sc) 4400 { 4401 4402 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4403 4404 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4405 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4406 int i, retry_cnt = CTX_INIT_RETRY_COUNT; 4407 u32 val; 4408 4409 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4410 4411 /* 4412 * BCM5709 context memory may be cached 4413 * in host memory so prepare the host memory 4414 * for access. 4415 */ 4416 val = BCE_CTX_COMMAND_ENABLED | 4417 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4418 val |= (BCM_PAGE_BITS - 8) << 16; 4419 REG_WR(sc, BCE_CTX_COMMAND, val); 4420 4421 /* Wait for mem init command to complete. */ 4422 for (i = 0; i < retry_cnt; i++) { 4423 val = REG_RD(sc, BCE_CTX_COMMAND); 4424 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4425 break; 4426 DELAY(2); 4427 } 4428 4429 /* ToDo: Consider returning an error here. */ 4430 DBRUNIF((val & BCE_CTX_COMMAND_MEM_INIT), 4431 BCE_PRINTF("%s(): Context memory initialization " 4432 "failed!\n", __FUNCTION__)); 4433 4434 for (i = 0; i < sc->ctx_pages; i++) { 4435 int j; 4436 4437 /* Set the physical address of the context memory. */ 4438 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4439 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4440 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4441 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4442 BCE_ADDR_HI(sc->ctx_paddr[i])); 4443 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4444 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4445 4446 /* Verify the context memory write was successful. */ 4447 for (j = 0; j < retry_cnt; j++) { 4448 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4449 if ((val & 4450 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4451 break; 4452 DELAY(5); 4453 } 4454 4455 /* ToDo: Consider returning an error here. */ 4456 DBRUNIF((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ), 4457 BCE_PRINTF("%s(): Failed to initialize " 4458 "context page %d!\n", __FUNCTION__, i)); 4459 } 4460 } else { 4461 u32 vcid_addr, offset; 4462 4463 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4464 4465 /* 4466 * For the 5706/5708, context memory is local to 4467 * the controller, so initialize the controller 4468 * context memory. 4469 */ 4470 4471 vcid_addr = GET_CID_ADDR(96); 4472 while (vcid_addr) { 4473 4474 vcid_addr -= PHY_CTX_SIZE; 4475 4476 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4477 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4478 4479 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4480 CTX_WR(sc, 0x00, offset, 0); 4481 } 4482 4483 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4484 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4485 } 4486 4487 } 4488 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4489 } 4490 4491 4492 /****************************************************************************/ 4493 /* Fetch the permanent MAC address of the controller. */ 4494 /* */ 4495 /* Returns: */ 4496 /* Nothing. */ 4497 /****************************************************************************/ 4498 static void 4499 bce_get_mac_addr(struct bce_softc *sc) 4500 { 4501 u32 mac_lo = 0, mac_hi = 0; 4502 4503 DBENTER(BCE_VERBOSE_RESET); 4504 4505 /* 4506 * The NetXtreme II bootcode populates various NIC 4507 * power-on and runtime configuration items in a 4508 * shared memory area. The factory configured MAC 4509 * address is available from both NVRAM and the 4510 * shared memory area so we'll read the value from 4511 * shared memory for speed. 4512 */ 4513 4514 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4515 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4516 4517 if ((mac_lo == 0) && (mac_hi == 0)) { 4518 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4519 __FILE__, __LINE__); 4520 } else { 4521 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4522 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4523 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4524 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4525 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4526 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4527 } 4528 4529 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4530 "address = %6D\n", sc->eaddr, ":"); 4531 DBEXIT(BCE_VERBOSE_RESET); 4532 } 4533 4534 4535 /****************************************************************************/ 4536 /* Program the MAC address. */ 4537 /* */ 4538 /* Returns: */ 4539 /* Nothing. */ 4540 /****************************************************************************/ 4541 static void 4542 bce_set_mac_addr(struct bce_softc *sc) 4543 { 4544 u32 val; 4545 u8 *mac_addr = sc->eaddr; 4546 4547 /* ToDo: Add support for setting multiple MAC addresses. */ 4548 4549 DBENTER(BCE_VERBOSE_RESET); 4550 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4551 "%6D\n", sc->eaddr, ":"); 4552 4553 val = (mac_addr[0] << 8) | mac_addr[1]; 4554 4555 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4556 4557 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4558 (mac_addr[4] << 8) | mac_addr[5]; 4559 4560 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4561 4562 DBEXIT(BCE_VERBOSE_RESET); 4563 } 4564 4565 4566 /****************************************************************************/ 4567 /* Stop the controller. */ 4568 /* */ 4569 /* Returns: */ 4570 /* Nothing. */ 4571 /****************************************************************************/ 4572 static void 4573 bce_stop(struct bce_softc *sc) 4574 { 4575 struct ifnet *ifp; 4576 struct ifmedia_entry *ifm; 4577 struct mii_data *mii = NULL; 4578 int mtmp, itmp; 4579 4580 DBENTER(BCE_VERBOSE_RESET); 4581 4582 BCE_LOCK_ASSERT(sc); 4583 4584 ifp = sc->bce_ifp; 4585 4586 mii = device_get_softc(sc->bce_miibus); 4587 4588 callout_stop(&sc->bce_tick_callout); 4589 4590 /* Disable the transmit/receive blocks. */ 4591 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4592 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4593 DELAY(20); 4594 4595 bce_disable_intr(sc); 4596 4597 /* Free RX buffers. */ 4598 #ifdef BCE_JUMBO_HDRSPLIT 4599 bce_free_pg_chain(sc); 4600 #endif 4601 bce_free_rx_chain(sc); 4602 4603 /* Free TX buffers. */ 4604 bce_free_tx_chain(sc); 4605 4606 /* 4607 * Isolate/power down the PHY, but leave the media selection 4608 * unchanged so that things will be put back to normal when 4609 * we bring the interface back up. 4610 */ 4611 4612 itmp = ifp->if_flags; 4613 ifp->if_flags |= IFF_UP; 4614 4615 /* If we are called from bce_detach(), mii is already NULL. */ 4616 if (mii != NULL) { 4617 ifm = mii->mii_media.ifm_cur; 4618 mtmp = ifm->ifm_media; 4619 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4620 mii_mediachg(mii); 4621 ifm->ifm_media = mtmp; 4622 } 4623 4624 ifp->if_flags = itmp; 4625 sc->watchdog_timer = 0; 4626 4627 sc->bce_link_up = FALSE; 4628 4629 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4630 4631 DBEXIT(BCE_VERBOSE_RESET); 4632 } 4633 4634 4635 static int 4636 bce_reset(struct bce_softc *sc, u32 reset_code) 4637 { 4638 u32 val; 4639 int i, rc = 0; 4640 4641 DBENTER(BCE_VERBOSE_RESET); 4642 4643 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4644 __FUNCTION__, reset_code); 4645 4646 /* Wait for pending PCI transactions to complete. */ 4647 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4648 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4649 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4650 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4651 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4652 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4653 DELAY(5); 4654 4655 /* Disable DMA */ 4656 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4657 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4658 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4659 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4660 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4661 } 4662 4663 /* Assume bootcode is running. */ 4664 sc->bce_fw_timed_out = FALSE; 4665 sc->bce_drv_cardiac_arrest = FALSE; 4666 4667 /* Give the firmware a chance to prepare for the reset. */ 4668 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4669 if (rc) 4670 goto bce_reset_exit; 4671 4672 /* Set a firmware reminder that this is a soft reset. */ 4673 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4674 4675 /* Dummy read to force the chip to complete all current transactions. */ 4676 val = REG_RD(sc, BCE_MISC_ID); 4677 4678 /* Chip reset. */ 4679 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4680 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4681 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4682 REG_RD(sc, BCE_MISC_COMMAND); 4683 DELAY(5); 4684 4685 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4686 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4687 4688 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4689 } else { 4690 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4691 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4692 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4693 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4694 4695 /* Allow up to 30us for reset to complete. */ 4696 for (i = 0; i < 10; i++) { 4697 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4698 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4699 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4700 break; 4701 } 4702 DELAY(10); 4703 } 4704 4705 /* Check that reset completed successfully. */ 4706 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4707 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4708 BCE_PRINTF("%s(%d): Reset failed!\n", 4709 __FILE__, __LINE__); 4710 rc = EBUSY; 4711 goto bce_reset_exit; 4712 } 4713 } 4714 4715 /* Make sure byte swapping is properly configured. */ 4716 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4717 if (val != 0x01020304) { 4718 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4719 __FILE__, __LINE__); 4720 rc = ENODEV; 4721 goto bce_reset_exit; 4722 } 4723 4724 /* Just completed a reset, assume that firmware is running again. */ 4725 sc->bce_fw_timed_out = FALSE; 4726 sc->bce_drv_cardiac_arrest = FALSE; 4727 4728 /* Wait for the firmware to finish its initialization. */ 4729 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4730 if (rc) 4731 BCE_PRINTF("%s(%d): Firmware did not complete " 4732 "initialization!\n", __FILE__, __LINE__); 4733 4734 bce_reset_exit: 4735 DBEXIT(BCE_VERBOSE_RESET); 4736 return (rc); 4737 } 4738 4739 4740 static int 4741 bce_chipinit(struct bce_softc *sc) 4742 { 4743 u32 val; 4744 int rc = 0; 4745 4746 DBENTER(BCE_VERBOSE_RESET); 4747 4748 bce_disable_intr(sc); 4749 4750 /* 4751 * Initialize DMA byte/word swapping, configure the number of DMA 4752 * channels and PCI clock compensation delay. 4753 */ 4754 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 4755 BCE_DMA_CONFIG_DATA_WORD_SWAP | 4756 #if BYTE_ORDER == BIG_ENDIAN 4757 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 4758 #endif 4759 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 4760 DMA_READ_CHANS << 12 | 4761 DMA_WRITE_CHANS << 16; 4762 4763 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 4764 4765 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 4766 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 4767 4768 /* 4769 * This setting resolves a problem observed on certain Intel PCI 4770 * chipsets that cannot handle multiple outstanding DMA operations. 4771 * See errata E9_5706A1_65. 4772 */ 4773 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 4774 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 4775 !(sc->bce_flags & BCE_PCIX_FLAG)) 4776 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 4777 4778 REG_WR(sc, BCE_DMA_CONFIG, val); 4779 4780 /* Enable the RX_V2P and Context state machines before access. */ 4781 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4782 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 4783 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 4784 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 4785 4786 /* Initialize context mapping and zero out the quick contexts. */ 4787 bce_init_ctx(sc); 4788 4789 /* Initialize the on-boards CPUs */ 4790 bce_init_cpus(sc); 4791 4792 /* Enable management frames (NC-SI) to flow to the MCP. */ 4793 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 4794 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 4795 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 4796 } 4797 4798 /* Prepare NVRAM for access. */ 4799 if (bce_init_nvram(sc)) { 4800 rc = ENODEV; 4801 goto bce_chipinit_exit; 4802 } 4803 4804 /* Set the kernel bypass block size */ 4805 val = REG_RD(sc, BCE_MQ_CONFIG); 4806 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4807 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 4808 4809 /* Enable bins used on the 5709. */ 4810 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4811 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4812 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 4813 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 4814 val |= BCE_MQ_CONFIG_HALT_DIS; 4815 } 4816 4817 REG_WR(sc, BCE_MQ_CONFIG, val); 4818 4819 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 4820 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 4821 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 4822 4823 /* Set the page size and clear the RV2P processor stall bits. */ 4824 val = (BCM_PAGE_BITS - 8) << 24; 4825 REG_WR(sc, BCE_RV2P_CONFIG, val); 4826 4827 /* Configure page size. */ 4828 val = REG_RD(sc, BCE_TBDR_CONFIG); 4829 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 4830 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 4831 REG_WR(sc, BCE_TBDR_CONFIG, val); 4832 4833 /* Set the perfect match control register to default. */ 4834 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 4835 4836 bce_chipinit_exit: 4837 DBEXIT(BCE_VERBOSE_RESET); 4838 4839 return(rc); 4840 } 4841 4842 4843 /****************************************************************************/ 4844 /* Initialize the controller in preparation to send/receive traffic. */ 4845 /* */ 4846 /* Returns: */ 4847 /* 0 for success, positive value for failure. */ 4848 /****************************************************************************/ 4849 static int 4850 bce_blockinit(struct bce_softc *sc) 4851 { 4852 u32 reg, val; 4853 int rc = 0; 4854 4855 DBENTER(BCE_VERBOSE_RESET); 4856 4857 /* Load the hardware default MAC address. */ 4858 bce_set_mac_addr(sc); 4859 4860 /* Set the Ethernet backoff seed value */ 4861 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 4862 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 4863 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 4864 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 4865 4866 sc->last_status_idx = 0; 4867 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 4868 4869 /* Set up link change interrupt generation. */ 4870 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 4871 4872 /* Program the physical address of the status block. */ 4873 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 4874 BCE_ADDR_LO(sc->status_block_paddr)); 4875 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 4876 BCE_ADDR_HI(sc->status_block_paddr)); 4877 4878 /* Program the physical address of the statistics block. */ 4879 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 4880 BCE_ADDR_LO(sc->stats_block_paddr)); 4881 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 4882 BCE_ADDR_HI(sc->stats_block_paddr)); 4883 4884 /* Program various host coalescing parameters. */ 4885 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4886 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 4887 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4888 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 4889 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 4890 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 4891 REG_WR(sc, BCE_HC_TX_TICKS, 4892 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 4893 REG_WR(sc, BCE_HC_RX_TICKS, 4894 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 4895 REG_WR(sc, BCE_HC_COM_TICKS, 4896 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 4897 REG_WR(sc, BCE_HC_CMD_TICKS, 4898 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 4899 REG_WR(sc, BCE_HC_STATS_TICKS, 4900 (sc->bce_stats_ticks & 0xffff00)); 4901 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 4902 4903 /* Configure the Host Coalescing block. */ 4904 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 4905 BCE_HC_CONFIG_COLLECT_STATS; 4906 4907 #if 0 4908 /* ToDo: Add MSI-X support. */ 4909 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 4910 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 4911 BCE_HC_SB_CONFIG_1; 4912 4913 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 4914 4915 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 4916 BCE_HC_SB_CONFIG_1_ONE_SHOT); 4917 4918 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 4919 (sc->tx_quick_cons_trip_int << 16) | 4920 sc->tx_quick_cons_trip); 4921 4922 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 4923 (sc->tx_ticks_int << 16) | sc->tx_ticks); 4924 4925 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4926 } 4927 4928 /* 4929 * Tell the HC block to automatically set the 4930 * INT_MASK bit after an MSI/MSI-X interrupt 4931 * is generated so the driver doesn't have to. 4932 */ 4933 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 4934 val |= BCE_HC_CONFIG_ONE_SHOT; 4935 4936 /* Set the MSI-X status blocks to 128 byte boundaries. */ 4937 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 4938 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4939 #endif 4940 4941 REG_WR(sc, BCE_HC_CONFIG, val); 4942 4943 /* Clear the internal statistics counters. */ 4944 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 4945 4946 /* Verify that bootcode is running. */ 4947 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 4948 4949 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 4950 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 4951 __FILE__, __LINE__); 4952 reg = 0); 4953 4954 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 4955 BCE_DEV_INFO_SIGNATURE_MAGIC) { 4956 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 4957 "Expected: 08%08X\n", __FILE__, __LINE__, 4958 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 4959 BCE_DEV_INFO_SIGNATURE_MAGIC); 4960 rc = ENODEV; 4961 goto bce_blockinit_exit; 4962 } 4963 4964 /* Enable DMA */ 4965 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4966 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4967 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4968 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4969 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4970 } 4971 4972 /* Allow bootcode to apply additional fixes before enabling MAC. */ 4973 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 4974 BCE_DRV_MSG_CODE_RESET); 4975 4976 /* Enable link state change interrupt generation. */ 4977 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 4978 4979 /* Enable the RXP. */ 4980 bce_start_rxp_cpu(sc); 4981 4982 /* Disable management frames (NC-SI) from flowing to the MCP. */ 4983 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 4984 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 4985 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 4986 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 4987 } 4988 4989 /* Enable all remaining blocks in the MAC. */ 4990 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4991 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 4992 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4993 BCE_MISC_ENABLE_DEFAULT_XI); 4994 else 4995 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4996 BCE_MISC_ENABLE_DEFAULT); 4997 4998 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4999 DELAY(20); 5000 5001 /* Save the current host coalescing block settings. */ 5002 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5003 5004 bce_blockinit_exit: 5005 DBEXIT(BCE_VERBOSE_RESET); 5006 5007 return (rc); 5008 } 5009 5010 5011 /****************************************************************************/ 5012 /* Encapsulate an mbuf into the rx_bd chain. */ 5013 /* */ 5014 /* Returns: */ 5015 /* 0 for success, positive value for failure. */ 5016 /****************************************************************************/ 5017 static int 5018 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5019 u16 *chain_prod, u32 *prod_bseq) 5020 { 5021 bus_dmamap_t map; 5022 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 5023 struct mbuf *m_new = NULL; 5024 struct rx_bd *rxbd; 5025 int nsegs, error, rc = 0; 5026 #ifdef BCE_DEBUG 5027 u16 debug_chain_prod = *chain_prod; 5028 #endif 5029 5030 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5031 5032 /* Make sure the inputs are valid. */ 5033 DBRUNIF((*chain_prod > MAX_RX_BD), 5034 BCE_PRINTF("%s(%d): RX producer out of range: " 5035 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5036 *chain_prod, (u16) MAX_RX_BD)); 5037 5038 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5039 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5040 *prod, *chain_prod, *prod_bseq); 5041 5042 /* Update some debug statistic counters */ 5043 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5044 sc->rx_low_watermark = sc->free_rx_bd); 5045 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5046 sc->rx_empty_count++); 5047 5048 /* Check whether this is a new mbuf allocation. */ 5049 if (m == NULL) { 5050 5051 /* Simulate an mbuf allocation failure. */ 5052 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5053 sc->mbuf_alloc_failed_count++; 5054 sc->mbuf_alloc_failed_sim_count++; 5055 rc = ENOBUFS; 5056 goto bce_get_rx_buf_exit); 5057 5058 /* This is a new mbuf allocation. */ 5059 #ifdef BCE_JUMBO_HDRSPLIT 5060 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5061 #else 5062 if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES) 5063 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 5064 else 5065 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 5066 sc->rx_bd_mbuf_alloc_size); 5067 #endif 5068 5069 if (m_new == NULL) { 5070 sc->mbuf_alloc_failed_count++; 5071 rc = ENOBUFS; 5072 goto bce_get_rx_buf_exit; 5073 } 5074 5075 DBRUN(sc->debug_rx_mbuf_alloc++); 5076 } else { 5077 /* Reuse an existing mbuf. */ 5078 m_new = m; 5079 } 5080 5081 /* Make sure we have a valid packet header. */ 5082 M_ASSERTPKTHDR(m_new); 5083 5084 /* Initialize the mbuf size and pad if necessary for alignment. */ 5085 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5086 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5087 5088 /* ToDo: Consider calling m_fragment() to test error handling. */ 5089 5090 /* Map the mbuf cluster into device memory. */ 5091 map = sc->rx_mbuf_map[*chain_prod]; 5092 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5093 segs, &nsegs, BUS_DMA_NOWAIT); 5094 5095 /* Handle any mapping errors. */ 5096 if (error) { 5097 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5098 "chain (%d)!\n", __FILE__, __LINE__, error); 5099 5100 sc->dma_map_addr_rx_failed_count++; 5101 m_freem(m_new); 5102 5103 DBRUN(sc->debug_rx_mbuf_alloc--); 5104 5105 rc = ENOBUFS; 5106 goto bce_get_rx_buf_exit; 5107 } 5108 5109 /* All mbufs must map to a single segment. */ 5110 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5111 __FUNCTION__, nsegs)); 5112 5113 /* Setup the rx_bd for the segment. */ 5114 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5115 5116 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5117 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5118 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5119 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5120 *prod_bseq += segs[0].ds_len; 5121 5122 /* Save the mbuf and update our counter. */ 5123 sc->rx_mbuf_ptr[*chain_prod] = m_new; 5124 sc->free_rx_bd -= nsegs; 5125 5126 DBRUNMSG(BCE_INSANE_RECV, 5127 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5128 5129 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5130 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", 5131 __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5132 5133 bce_get_rx_buf_exit: 5134 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5135 5136 return(rc); 5137 } 5138 5139 5140 #ifdef BCE_JUMBO_HDRSPLIT 5141 /****************************************************************************/ 5142 /* Encapsulate an mbuf cluster into the page chain. */ 5143 /* */ 5144 /* Returns: */ 5145 /* 0 for success, positive value for failure. */ 5146 /****************************************************************************/ 5147 static int 5148 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5149 u16 *prod_idx) 5150 { 5151 bus_dmamap_t map; 5152 bus_addr_t busaddr; 5153 struct mbuf *m_new = NULL; 5154 struct rx_bd *pgbd; 5155 int error, rc = 0; 5156 #ifdef BCE_DEBUG 5157 u16 debug_prod_idx = *prod_idx; 5158 #endif 5159 5160 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5161 5162 /* Make sure the inputs are valid. */ 5163 DBRUNIF((*prod_idx > MAX_PG_BD), 5164 BCE_PRINTF("%s(%d): page producer out of range: " 5165 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5166 *prod_idx, (u16) MAX_PG_BD)); 5167 5168 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5169 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5170 5171 /* Update counters if we've hit a new low or run out of pages. */ 5172 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5173 sc->pg_low_watermark = sc->free_pg_bd); 5174 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5175 5176 /* Check whether this is a new mbuf allocation. */ 5177 if (m == NULL) { 5178 5179 /* Simulate an mbuf allocation failure. */ 5180 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5181 sc->mbuf_alloc_failed_count++; 5182 sc->mbuf_alloc_failed_sim_count++; 5183 rc = ENOBUFS; 5184 goto bce_get_pg_buf_exit); 5185 5186 /* This is a new mbuf allocation. */ 5187 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5188 if (m_new == NULL) { 5189 sc->mbuf_alloc_failed_count++; 5190 rc = ENOBUFS; 5191 goto bce_get_pg_buf_exit; 5192 } 5193 5194 DBRUN(sc->debug_pg_mbuf_alloc++); 5195 } else { 5196 /* Reuse an existing mbuf. */ 5197 m_new = m; 5198 m_new->m_data = m_new->m_ext.ext_buf; 5199 } 5200 5201 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5202 5203 /* ToDo: Consider calling m_fragment() to test error handling. */ 5204 5205 /* Map the mbuf cluster into device memory. */ 5206 map = sc->pg_mbuf_map[*prod_idx]; 5207 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5208 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, 5209 &busaddr, BUS_DMA_NOWAIT); 5210 5211 /* Handle any mapping errors. */ 5212 if (error) { 5213 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5214 __FILE__, __LINE__); 5215 5216 m_freem(m_new); 5217 DBRUN(sc->debug_pg_mbuf_alloc--); 5218 5219 rc = ENOBUFS; 5220 goto bce_get_pg_buf_exit; 5221 } 5222 5223 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5224 5225 /* 5226 * The page chain uses the same rx_bd data structure 5227 * as the receive chain but doesn't require a byte sequence (bseq). 5228 */ 5229 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5230 5231 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5232 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5233 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5234 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5235 5236 /* Save the mbuf and update our counter. */ 5237 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5238 sc->free_pg_bd--; 5239 5240 DBRUNMSG(BCE_INSANE_RECV, 5241 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5242 5243 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5244 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5245 5246 bce_get_pg_buf_exit: 5247 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5248 5249 return(rc); 5250 } 5251 #endif /* BCE_JUMBO_HDRSPLIT */ 5252 5253 5254 /****************************************************************************/ 5255 /* Initialize the TX context memory. */ 5256 /* */ 5257 /* Returns: */ 5258 /* Nothing */ 5259 /****************************************************************************/ 5260 static void 5261 bce_init_tx_context(struct bce_softc *sc) 5262 { 5263 u32 val; 5264 5265 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5266 5267 /* Initialize the context ID for an L2 TX chain. */ 5268 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5269 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5270 /* Set the CID type to support an L2 connection. */ 5271 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5272 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5273 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5274 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5275 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5276 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5277 5278 /* Point the hardware to the first page in the chain. */ 5279 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5280 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5281 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5282 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5283 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5284 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5285 } else { 5286 /* Set the CID type to support an L2 connection. */ 5287 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5288 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5289 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5290 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5291 5292 /* Point the hardware to the first page in the chain. */ 5293 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5294 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5295 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5296 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5297 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5298 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5299 } 5300 5301 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5302 } 5303 5304 5305 /****************************************************************************/ 5306 /* Allocate memory and initialize the TX data structures. */ 5307 /* */ 5308 /* Returns: */ 5309 /* 0 for success, positive value for failure. */ 5310 /****************************************************************************/ 5311 static int 5312 bce_init_tx_chain(struct bce_softc *sc) 5313 { 5314 struct tx_bd *txbd; 5315 int i, rc = 0; 5316 5317 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5318 5319 /* Set the initial TX producer/consumer indices. */ 5320 sc->tx_prod = 0; 5321 sc->tx_cons = 0; 5322 sc->tx_prod_bseq = 0; 5323 sc->used_tx_bd = 0; 5324 sc->max_tx_bd = USABLE_TX_BD; 5325 DBRUN(sc->tx_hi_watermark = 0); 5326 DBRUN(sc->tx_full_count = 0); 5327 5328 /* 5329 * The NetXtreme II supports a linked-list structre called 5330 * a Buffer Descriptor Chain (or BD chain). A BD chain 5331 * consists of a series of 1 or more chain pages, each of which 5332 * consists of a fixed number of BD entries. 5333 * The last BD entry on each page is a pointer to the next page 5334 * in the chain, and the last pointer in the BD chain 5335 * points back to the beginning of the chain. 5336 */ 5337 5338 /* Set the TX next pointer chain entries. */ 5339 for (i = 0; i < TX_PAGES; i++) { 5340 int j; 5341 5342 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5343 5344 /* Check if we've reached the last page. */ 5345 if (i == (TX_PAGES - 1)) 5346 j = 0; 5347 else 5348 j = i + 1; 5349 5350 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5351 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5352 } 5353 5354 bce_init_tx_context(sc); 5355 5356 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 5357 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5358 5359 return(rc); 5360 } 5361 5362 5363 /****************************************************************************/ 5364 /* Free memory and clear the TX data structures. */ 5365 /* */ 5366 /* Returns: */ 5367 /* Nothing. */ 5368 /****************************************************************************/ 5369 static void 5370 bce_free_tx_chain(struct bce_softc *sc) 5371 { 5372 int i; 5373 5374 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5375 5376 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5377 for (i = 0; i < TOTAL_TX_BD; i++) { 5378 if (sc->tx_mbuf_ptr[i] != NULL) { 5379 if (sc->tx_mbuf_map[i] != NULL) 5380 bus_dmamap_sync(sc->tx_mbuf_tag, 5381 sc->tx_mbuf_map[i], 5382 BUS_DMASYNC_POSTWRITE); 5383 m_freem(sc->tx_mbuf_ptr[i]); 5384 sc->tx_mbuf_ptr[i] = NULL; 5385 DBRUN(sc->debug_tx_mbuf_alloc--); 5386 } 5387 } 5388 5389 /* Clear each TX chain page. */ 5390 for (i = 0; i < TX_PAGES; i++) 5391 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5392 5393 sc->used_tx_bd = 0; 5394 5395 /* Check if we lost any mbufs in the process. */ 5396 DBRUNIF((sc->debug_tx_mbuf_alloc), 5397 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5398 "from tx chain!\n", __FILE__, __LINE__, 5399 sc->debug_tx_mbuf_alloc)); 5400 5401 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5402 } 5403 5404 5405 /****************************************************************************/ 5406 /* Initialize the RX context memory. */ 5407 /* */ 5408 /* Returns: */ 5409 /* Nothing */ 5410 /****************************************************************************/ 5411 static void 5412 bce_init_rx_context(struct bce_softc *sc) 5413 { 5414 u32 val; 5415 5416 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5417 5418 /* Init the type, size, and BD cache levels for the RX context. */ 5419 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5420 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5421 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5422 5423 /* 5424 * Set the level for generating pause frames 5425 * when the number of available rx_bd's gets 5426 * too low (the low watermark) and the level 5427 * when pause frames can be stopped (the high 5428 * watermark). 5429 */ 5430 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5431 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5432 u32 lo_water, hi_water; 5433 5434 if (sc->bce_flags && BCE_USING_TX_FLOW_CONTROL) { 5435 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5436 } else { 5437 lo_water = 0; 5438 } 5439 5440 if (lo_water >= USABLE_RX_BD) { 5441 lo_water = 0; 5442 } 5443 5444 hi_water = USABLE_RX_BD / 4; 5445 5446 if (hi_water <= lo_water) { 5447 lo_water = 0; 5448 } 5449 5450 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5451 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5452 5453 if (hi_water > 0xf) 5454 hi_water = 0xf; 5455 else if (hi_water == 0) 5456 lo_water = 0; 5457 5458 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5459 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5460 } 5461 5462 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5463 5464 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5465 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5466 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5467 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5468 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5469 } 5470 5471 /* Point the hardware to the first page in the chain. */ 5472 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5473 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5474 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5475 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5476 5477 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5478 } 5479 5480 5481 /****************************************************************************/ 5482 /* Allocate memory and initialize the RX data structures. */ 5483 /* */ 5484 /* Returns: */ 5485 /* 0 for success, positive value for failure. */ 5486 /****************************************************************************/ 5487 static int 5488 bce_init_rx_chain(struct bce_softc *sc) 5489 { 5490 struct rx_bd *rxbd; 5491 int i, rc = 0; 5492 5493 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5494 BCE_VERBOSE_CTX); 5495 5496 /* Initialize the RX producer and consumer indices. */ 5497 sc->rx_prod = 0; 5498 sc->rx_cons = 0; 5499 sc->rx_prod_bseq = 0; 5500 sc->free_rx_bd = USABLE_RX_BD; 5501 sc->max_rx_bd = USABLE_RX_BD; 5502 5503 /* Initialize the RX next pointer chain entries. */ 5504 for (i = 0; i < RX_PAGES; i++) { 5505 int j; 5506 5507 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5508 5509 /* Check if we've reached the last page. */ 5510 if (i == (RX_PAGES - 1)) 5511 j = 0; 5512 else 5513 j = i + 1; 5514 5515 /* Setup the chain page pointers. */ 5516 rxbd->rx_bd_haddr_hi = 5517 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5518 rxbd->rx_bd_haddr_lo = 5519 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5520 } 5521 5522 /* Fill up the RX chain. */ 5523 bce_fill_rx_chain(sc); 5524 5525 DBRUN(sc->rx_low_watermark = USABLE_RX_BD); 5526 DBRUN(sc->rx_empty_count = 0); 5527 for (i = 0; i < RX_PAGES; i++) { 5528 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5529 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5530 } 5531 5532 bce_init_rx_context(sc); 5533 5534 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD)); 5535 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5536 BCE_VERBOSE_CTX); 5537 5538 /* ToDo: Are there possible failure modes here? */ 5539 5540 return(rc); 5541 } 5542 5543 5544 /****************************************************************************/ 5545 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5546 /* occurs. */ 5547 /* */ 5548 /* Returns: */ 5549 /* Nothing */ 5550 /****************************************************************************/ 5551 static void 5552 bce_fill_rx_chain(struct bce_softc *sc) 5553 { 5554 u16 prod, prod_idx; 5555 u32 prod_bseq; 5556 5557 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5558 BCE_VERBOSE_CTX); 5559 5560 /* Get the RX chain producer indices. */ 5561 prod = sc->rx_prod; 5562 prod_bseq = sc->rx_prod_bseq; 5563 5564 /* Keep filling the RX chain until it's full. */ 5565 while (sc->free_rx_bd > 0) { 5566 prod_idx = RX_CHAIN_IDX(prod); 5567 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5568 /* Bail out if we can't add an mbuf to the chain. */ 5569 break; 5570 } 5571 prod = NEXT_RX_BD(prod); 5572 } 5573 5574 /* Save the RX chain producer indices. */ 5575 sc->rx_prod = prod; 5576 sc->rx_prod_bseq = prod_bseq; 5577 5578 /* We should never end up pointing to a next page pointer. */ 5579 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5580 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5581 __FUNCTION__, sc->rx_prod)); 5582 5583 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5584 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5585 BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); 5586 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + 5587 BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); 5588 5589 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5590 BCE_VERBOSE_CTX); 5591 } 5592 5593 5594 /****************************************************************************/ 5595 /* Free memory and clear the RX data structures. */ 5596 /* */ 5597 /* Returns: */ 5598 /* Nothing. */ 5599 /****************************************************************************/ 5600 static void 5601 bce_free_rx_chain(struct bce_softc *sc) 5602 { 5603 int i; 5604 5605 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5606 5607 /* Free any mbufs still in the RX mbuf chain. */ 5608 for (i = 0; i < TOTAL_RX_BD; i++) { 5609 if (sc->rx_mbuf_ptr[i] != NULL) { 5610 if (sc->rx_mbuf_map[i] != NULL) 5611 bus_dmamap_sync(sc->rx_mbuf_tag, 5612 sc->rx_mbuf_map[i], 5613 BUS_DMASYNC_POSTREAD); 5614 m_freem(sc->rx_mbuf_ptr[i]); 5615 sc->rx_mbuf_ptr[i] = NULL; 5616 DBRUN(sc->debug_rx_mbuf_alloc--); 5617 } 5618 } 5619 5620 /* Clear each RX chain page. */ 5621 for (i = 0; i < RX_PAGES; i++) 5622 if (sc->rx_bd_chain[i] != NULL) { 5623 bzero((char *)sc->rx_bd_chain[i], 5624 BCE_RX_CHAIN_PAGE_SZ); 5625 } 5626 5627 sc->free_rx_bd = sc->max_rx_bd; 5628 5629 /* Check if we lost any mbufs in the process. */ 5630 DBRUNIF((sc->debug_rx_mbuf_alloc), 5631 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5632 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5633 5634 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5635 } 5636 5637 5638 #ifdef BCE_JUMBO_HDRSPLIT 5639 /****************************************************************************/ 5640 /* Allocate memory and initialize the page data structures. */ 5641 /* Assumes that bce_init_rx_chain() has not already been called. */ 5642 /* */ 5643 /* Returns: */ 5644 /* 0 for success, positive value for failure. */ 5645 /****************************************************************************/ 5646 static int 5647 bce_init_pg_chain(struct bce_softc *sc) 5648 { 5649 struct rx_bd *pgbd; 5650 int i, rc = 0; 5651 u32 val; 5652 5653 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5654 BCE_VERBOSE_CTX); 5655 5656 /* Initialize the page producer and consumer indices. */ 5657 sc->pg_prod = 0; 5658 sc->pg_cons = 0; 5659 sc->free_pg_bd = USABLE_PG_BD; 5660 sc->max_pg_bd = USABLE_PG_BD; 5661 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5662 DBRUN(sc->pg_empty_count = 0); 5663 5664 /* Initialize the page next pointer chain entries. */ 5665 for (i = 0; i < PG_PAGES; i++) { 5666 int j; 5667 5668 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5669 5670 /* Check if we've reached the last page. */ 5671 if (i == (PG_PAGES - 1)) 5672 j = 0; 5673 else 5674 j = i + 1; 5675 5676 /* Setup the chain page pointers. */ 5677 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5678 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5679 } 5680 5681 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5682 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5683 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 5684 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5685 5686 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5687 5688 /* Configure the rx_bd and page chain mbuf cluster size. */ 5689 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5690 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5691 5692 /* Configure the context reserved for jumbo support. */ 5693 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5694 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5695 5696 /* Point the hardware to the first page in the page chain. */ 5697 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5698 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5699 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5700 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5701 5702 /* Fill up the page chain. */ 5703 bce_fill_pg_chain(sc); 5704 5705 for (i = 0; i < PG_PAGES; i++) { 5706 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5707 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5708 } 5709 5710 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD)); 5711 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5712 BCE_VERBOSE_CTX); 5713 return(rc); 5714 } 5715 5716 5717 /****************************************************************************/ 5718 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 5719 /* occurs. */ 5720 /* */ 5721 /* Returns: */ 5722 /* Nothing */ 5723 /****************************************************************************/ 5724 static void 5725 bce_fill_pg_chain(struct bce_softc *sc) 5726 { 5727 u16 prod, prod_idx; 5728 5729 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5730 BCE_VERBOSE_CTX); 5731 5732 /* Get the page chain prodcuer index. */ 5733 prod = sc->pg_prod; 5734 5735 /* Keep filling the page chain until it's full. */ 5736 while (sc->free_pg_bd > 0) { 5737 prod_idx = PG_CHAIN_IDX(prod); 5738 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 5739 /* Bail out if we can't add an mbuf to the chain. */ 5740 break; 5741 } 5742 prod = NEXT_PG_BD(prod); 5743 } 5744 5745 /* Save the page chain producer index. */ 5746 sc->pg_prod = prod; 5747 5748 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5749 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5750 __FUNCTION__, sc->pg_prod)); 5751 5752 /* 5753 * Write the mailbox and tell the chip about 5754 * the new rx_bd's in the page chain. 5755 */ 5756 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5757 BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); 5758 5759 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5760 BCE_VERBOSE_CTX); 5761 } 5762 5763 5764 /****************************************************************************/ 5765 /* Free memory and clear the RX data structures. */ 5766 /* */ 5767 /* Returns: */ 5768 /* Nothing. */ 5769 /****************************************************************************/ 5770 static void 5771 bce_free_pg_chain(struct bce_softc *sc) 5772 { 5773 int i; 5774 5775 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5776 5777 /* Free any mbufs still in the mbuf page chain. */ 5778 for (i = 0; i < TOTAL_PG_BD; i++) { 5779 if (sc->pg_mbuf_ptr[i] != NULL) { 5780 if (sc->pg_mbuf_map[i] != NULL) 5781 bus_dmamap_sync(sc->pg_mbuf_tag, 5782 sc->pg_mbuf_map[i], 5783 BUS_DMASYNC_POSTREAD); 5784 m_freem(sc->pg_mbuf_ptr[i]); 5785 sc->pg_mbuf_ptr[i] = NULL; 5786 DBRUN(sc->debug_pg_mbuf_alloc--); 5787 } 5788 } 5789 5790 /* Clear each page chain pages. */ 5791 for (i = 0; i < PG_PAGES; i++) 5792 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 5793 5794 sc->free_pg_bd = sc->max_pg_bd; 5795 5796 /* Check if we lost any mbufs in the process. */ 5797 DBRUNIF((sc->debug_pg_mbuf_alloc), 5798 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 5799 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 5800 5801 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5802 } 5803 #endif /* BCE_JUMBO_HDRSPLIT */ 5804 5805 5806 /****************************************************************************/ 5807 /* Set media options. */ 5808 /* */ 5809 /* Returns: */ 5810 /* 0 for success, positive value for failure. */ 5811 /****************************************************************************/ 5812 static int 5813 bce_ifmedia_upd(struct ifnet *ifp) 5814 { 5815 struct bce_softc *sc = ifp->if_softc; 5816 5817 DBENTER(BCE_VERBOSE); 5818 5819 BCE_LOCK(sc); 5820 bce_ifmedia_upd_locked(ifp); 5821 BCE_UNLOCK(sc); 5822 5823 DBEXIT(BCE_VERBOSE); 5824 return (0); 5825 } 5826 5827 5828 /****************************************************************************/ 5829 /* Set media options. */ 5830 /* */ 5831 /* Returns: */ 5832 /* Nothing. */ 5833 /****************************************************************************/ 5834 static void 5835 bce_ifmedia_upd_locked(struct ifnet *ifp) 5836 { 5837 struct bce_softc *sc = ifp->if_softc; 5838 struct mii_data *mii; 5839 5840 DBENTER(BCE_VERBOSE_PHY); 5841 5842 BCE_LOCK_ASSERT(sc); 5843 5844 mii = device_get_softc(sc->bce_miibus); 5845 5846 /* Make sure the MII bus has been enumerated. */ 5847 if (mii) { 5848 sc->bce_link_up = FALSE; 5849 if (mii->mii_instance) { 5850 struct mii_softc *miisc; 5851 5852 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5853 mii_phy_reset(miisc); 5854 } 5855 mii_mediachg(mii); 5856 } 5857 5858 DBEXIT(BCE_VERBOSE_PHY); 5859 } 5860 5861 5862 /****************************************************************************/ 5863 /* Reports current media status. */ 5864 /* */ 5865 /* Returns: */ 5866 /* Nothing. */ 5867 /****************************************************************************/ 5868 static void 5869 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5870 { 5871 struct bce_softc *sc = ifp->if_softc; 5872 struct mii_data *mii; 5873 5874 DBENTER(BCE_VERBOSE_PHY); 5875 5876 BCE_LOCK(sc); 5877 5878 mii = device_get_softc(sc->bce_miibus); 5879 5880 mii_pollstat(mii); 5881 ifmr->ifm_active = mii->mii_media_active; 5882 ifmr->ifm_status = mii->mii_media_status; 5883 5884 BCE_UNLOCK(sc); 5885 5886 DBEXIT(BCE_VERBOSE_PHY); 5887 } 5888 5889 5890 /****************************************************************************/ 5891 /* Handles PHY generated interrupt events. */ 5892 /* */ 5893 /* Returns: */ 5894 /* Nothing. */ 5895 /****************************************************************************/ 5896 static void 5897 bce_phy_intr(struct bce_softc *sc) 5898 { 5899 u32 new_link_state, old_link_state; 5900 5901 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5902 5903 DBRUN(sc->phy_interrupts++); 5904 5905 new_link_state = sc->status_block->status_attn_bits & 5906 STATUS_ATTN_BITS_LINK_STATE; 5907 old_link_state = sc->status_block->status_attn_bits_ack & 5908 STATUS_ATTN_BITS_LINK_STATE; 5909 5910 /* Handle any changes if the link state has changed. */ 5911 if (new_link_state != old_link_state) { 5912 5913 /* Update the status_attn_bits_ack field. */ 5914 if (new_link_state) { 5915 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 5916 STATUS_ATTN_BITS_LINK_STATE); 5917 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 5918 __FUNCTION__); 5919 } 5920 else { 5921 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 5922 STATUS_ATTN_BITS_LINK_STATE); 5923 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 5924 __FUNCTION__); 5925 } 5926 5927 /* 5928 * Assume link is down and allow 5929 * tick routine to update the state 5930 * based on the actual media state. 5931 */ 5932 sc->bce_link_up = FALSE; 5933 callout_stop(&sc->bce_tick_callout); 5934 bce_tick(sc); 5935 } 5936 5937 /* Acknowledge the link change interrupt. */ 5938 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 5939 5940 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5941 } 5942 5943 5944 /****************************************************************************/ 5945 /* Reads the receive consumer value from the status block (skipping over */ 5946 /* chain page pointer if necessary). */ 5947 /* */ 5948 /* Returns: */ 5949 /* hw_cons */ 5950 /****************************************************************************/ 5951 static inline u16 5952 bce_get_hw_rx_cons(struct bce_softc *sc) 5953 { 5954 u16 hw_cons; 5955 5956 rmb(); 5957 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 5958 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5959 hw_cons++; 5960 5961 return hw_cons; 5962 } 5963 5964 /****************************************************************************/ 5965 /* Handles received frame interrupt events. */ 5966 /* */ 5967 /* Returns: */ 5968 /* Nothing. */ 5969 /****************************************************************************/ 5970 static void 5971 bce_rx_intr(struct bce_softc *sc) 5972 { 5973 struct ifnet *ifp = sc->bce_ifp; 5974 struct l2_fhdr *l2fhdr; 5975 struct ether_vlan_header *vh; 5976 unsigned int pkt_len; 5977 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 5978 u32 status; 5979 #ifdef BCE_JUMBO_HDRSPLIT 5980 unsigned int rem_len; 5981 u16 sw_pg_cons, sw_pg_cons_idx; 5982 #endif 5983 5984 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 5985 DBRUN(sc->interrupts_rx++); 5986 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 5987 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 5988 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 5989 5990 /* Prepare the RX chain pages to be accessed by the host CPU. */ 5991 for (int i = 0; i < RX_PAGES; i++) 5992 bus_dmamap_sync(sc->rx_bd_chain_tag, 5993 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 5994 5995 #ifdef BCE_JUMBO_HDRSPLIT 5996 /* Prepare the page chain pages to be accessed by the host CPU. */ 5997 for (int i = 0; i < PG_PAGES; i++) 5998 bus_dmamap_sync(sc->pg_bd_chain_tag, 5999 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6000 #endif 6001 6002 /* Get the hardware's view of the RX consumer index. */ 6003 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6004 6005 /* Get working copies of the driver's view of the consumer indices. */ 6006 sw_rx_cons = sc->rx_cons; 6007 6008 #ifdef BCE_JUMBO_HDRSPLIT 6009 sw_pg_cons = sc->pg_cons; 6010 #endif 6011 6012 /* Update some debug statistics counters */ 6013 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6014 sc->rx_low_watermark = sc->free_rx_bd); 6015 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6016 sc->rx_empty_count++); 6017 6018 /* Scan through the receive chain as long as there is work to do */ 6019 /* ToDo: Consider setting a limit on the number of packets processed. */ 6020 rmb(); 6021 while (sw_rx_cons != hw_rx_cons) { 6022 struct mbuf *m0; 6023 6024 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6025 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6026 6027 /* Unmap the mbuf from DMA space. */ 6028 bus_dmamap_sync(sc->rx_mbuf_tag, 6029 sc->rx_mbuf_map[sw_rx_cons_idx], 6030 BUS_DMASYNC_POSTREAD); 6031 bus_dmamap_unload(sc->rx_mbuf_tag, 6032 sc->rx_mbuf_map[sw_rx_cons_idx]); 6033 6034 /* Remove the mbuf from the RX chain. */ 6035 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6036 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6037 DBRUN(sc->debug_rx_mbuf_alloc--); 6038 sc->free_rx_bd++; 6039 6040 if(m0 == NULL) { 6041 DBPRINT(sc, BCE_EXTREME_RECV, 6042 "%s(): Oops! Empty mbuf pointer " 6043 "found in sc->rx_mbuf_ptr[0x%04X]!\n", 6044 __FUNCTION__, sw_rx_cons_idx); 6045 goto bce_rx_int_next_rx; 6046 } 6047 6048 /* 6049 * Frames received on the NetXteme II are prepended 6050 * with an l2_fhdr structure which provides status 6051 * information about the received frame (including 6052 * VLAN tags and checksum info). The frames are 6053 * also automatically adjusted to align the IP 6054 * header (i.e. two null bytes are inserted before 6055 * the Ethernet header). As a result the data 6056 * DMA'd by the controller into the mbuf looks 6057 * like this: 6058 * 6059 * +---------+-----+---------------------+-----+ 6060 * | l2_fhdr | pad | packet data | FCS | 6061 * +---------+-----+---------------------+-----+ 6062 * 6063 * The l2_fhdr needs to be checked and skipped and 6064 * the FCS needs to be stripped before sending the 6065 * packet up the stack. 6066 */ 6067 l2fhdr = mtod(m0, struct l2_fhdr *); 6068 6069 /* Get the packet data + FCS length and the status. */ 6070 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6071 status = l2fhdr->l2_fhdr_status; 6072 6073 /* 6074 * Skip over the l2_fhdr and pad, resulting in the 6075 * following data in the mbuf: 6076 * +---------------------+-----+ 6077 * | packet data | FCS | 6078 * +---------------------+-----+ 6079 */ 6080 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6081 6082 #ifdef BCE_JUMBO_HDRSPLIT 6083 /* 6084 * Check whether the received frame fits in a single 6085 * mbuf or not (i.e. packet data + FCS <= 6086 * sc->rx_bd_mbuf_data_len bytes). 6087 */ 6088 if (pkt_len > m0->m_len) { 6089 /* 6090 * The received frame is larger than a single mbuf. 6091 * If the frame was a TCP frame then only the TCP 6092 * header is placed in the mbuf, the remaining 6093 * payload (including FCS) is placed in the page 6094 * chain, the SPLIT flag is set, and the header 6095 * length is placed in the IP checksum field. 6096 * If the frame is not a TCP frame then the mbuf 6097 * is filled and the remaining bytes are placed 6098 * in the page chain. 6099 */ 6100 6101 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6102 "packet.\n", __FUNCTION__); 6103 6104 /* 6105 * When the page chain is enabled and the TCP 6106 * header has been split from the TCP payload, 6107 * the ip_xsum structure will reflect the length 6108 * of the TCP header, not the IP checksum. Set 6109 * the packet length of the mbuf accordingly. 6110 */ 6111 if (status & L2_FHDR_STATUS_SPLIT) 6112 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6113 6114 rem_len = pkt_len - m0->m_len; 6115 6116 /* Pull mbufs off the page chain for the remaining data. */ 6117 while (rem_len > 0) { 6118 struct mbuf *m_pg; 6119 6120 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6121 6122 /* Remove the mbuf from the page chain. */ 6123 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6124 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6125 DBRUN(sc->debug_pg_mbuf_alloc--); 6126 sc->free_pg_bd++; 6127 6128 /* Unmap the page chain mbuf from DMA space. */ 6129 bus_dmamap_sync(sc->pg_mbuf_tag, 6130 sc->pg_mbuf_map[sw_pg_cons_idx], 6131 BUS_DMASYNC_POSTREAD); 6132 bus_dmamap_unload(sc->pg_mbuf_tag, 6133 sc->pg_mbuf_map[sw_pg_cons_idx]); 6134 6135 /* Adjust the mbuf length. */ 6136 if (rem_len < m_pg->m_len) { 6137 /* The mbuf chain is complete. */ 6138 m_pg->m_len = rem_len; 6139 rem_len = 0; 6140 } else { 6141 /* More packet data is waiting. */ 6142 rem_len -= m_pg->m_len; 6143 } 6144 6145 /* Concatenate the mbuf cluster to the mbuf. */ 6146 m_cat(m0, m_pg); 6147 6148 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6149 } 6150 6151 /* Set the total packet length. */ 6152 m0->m_pkthdr.len = pkt_len; 6153 6154 } else { 6155 /* 6156 * The received packet is small and fits in a 6157 * single mbuf (i.e. the l2_fhdr + pad + packet + 6158 * FCS <= MHLEN). In other words, the packet is 6159 * 154 bytes or less in size. 6160 */ 6161 6162 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6163 "packet.\n", __FUNCTION__); 6164 6165 /* Set the total packet length. */ 6166 m0->m_pkthdr.len = m0->m_len = pkt_len; 6167 } 6168 #else 6169 /* Set the total packet length. */ 6170 m0->m_pkthdr.len = m0->m_len = pkt_len; 6171 #endif 6172 6173 /* Remove the trailing Ethernet FCS. */ 6174 m_adj(m0, -ETHER_CRC_LEN); 6175 6176 /* Check that the resulting mbuf chain is valid. */ 6177 DBRUN(m_sanity(m0, FALSE)); 6178 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6179 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6180 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6181 m_print(m0, 128)); 6182 6183 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6184 sc->l2fhdr_error_sim_count++; 6185 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6186 6187 /* Check the received frame for errors. */ 6188 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6189 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6190 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6191 6192 /* Log the error and release the mbuf. */ 6193 ifp->if_ierrors++; 6194 sc->l2fhdr_error_count++; 6195 6196 m_freem(m0); 6197 m0 = NULL; 6198 goto bce_rx_int_next_rx; 6199 } 6200 6201 /* Send the packet to the appropriate interface. */ 6202 m0->m_pkthdr.rcvif = ifp; 6203 6204 /* Assume no hardware checksum. */ 6205 m0->m_pkthdr.csum_flags = 0; 6206 6207 /* Validate the checksum if offload enabled. */ 6208 if (ifp->if_capenable & IFCAP_RXCSUM) { 6209 6210 /* Check for an IP datagram. */ 6211 if (!(status & L2_FHDR_STATUS_SPLIT) && 6212 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6213 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6214 DBRUN(sc->csum_offload_ip++); 6215 /* Check if the IP checksum is valid. */ 6216 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6217 m0->m_pkthdr.csum_flags |= 6218 CSUM_IP_VALID; 6219 } 6220 6221 /* Check for a valid TCP/UDP frame. */ 6222 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6223 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6224 6225 /* Check for a good TCP/UDP checksum. */ 6226 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6227 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6228 DBRUN(sc->csum_offload_tcp_udp++); 6229 m0->m_pkthdr.csum_data = 6230 l2fhdr->l2_fhdr_tcp_udp_xsum; 6231 m0->m_pkthdr.csum_flags |= 6232 (CSUM_DATA_VALID 6233 | CSUM_PSEUDO_HDR); 6234 } 6235 } 6236 } 6237 6238 /* Attach the VLAN tag. */ 6239 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6240 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6241 #if __FreeBSD_version < 700000 6242 VLAN_INPUT_TAG(ifp, m0, 6243 l2fhdr->l2_fhdr_vlan_tag, continue); 6244 #else 6245 m0->m_pkthdr.ether_vtag = 6246 l2fhdr->l2_fhdr_vlan_tag; 6247 m0->m_flags |= M_VLANTAG; 6248 #endif 6249 } else { 6250 /* 6251 * bce(4) controllers can't disable VLAN 6252 * tag stripping if management firmware 6253 * (ASF/IPMI/UMP) is running. So we always 6254 * strip VLAN tag and manually reconstruct 6255 * the VLAN frame by appending stripped 6256 * VLAN tag in driver if VLAN tag stripping 6257 * was disabled. 6258 * 6259 * TODO: LLC SNAP handling. 6260 */ 6261 bcopy(mtod(m0, uint8_t *), 6262 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6263 ETHER_ADDR_LEN * 2); 6264 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6265 vh = mtod(m0, struct ether_vlan_header *); 6266 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6267 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6268 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6269 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6270 } 6271 } 6272 6273 /* Increment received packet statistics. */ 6274 ifp->if_ipackets++; 6275 6276 bce_rx_int_next_rx: 6277 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6278 6279 /* If we have a packet, pass it up the stack */ 6280 if (m0) { 6281 /* Make sure we don't lose our place when we release the lock. */ 6282 sc->rx_cons = sw_rx_cons; 6283 #ifdef BCE_JUMBO_HDRSPLIT 6284 sc->pg_cons = sw_pg_cons; 6285 #endif 6286 6287 BCE_UNLOCK(sc); 6288 (*ifp->if_input)(ifp, m0); 6289 BCE_LOCK(sc); 6290 6291 /* Recover our place. */ 6292 sw_rx_cons = sc->rx_cons; 6293 #ifdef BCE_JUMBO_HDRSPLIT 6294 sw_pg_cons = sc->pg_cons; 6295 #endif 6296 } 6297 6298 /* Refresh hw_cons to see if there's new work */ 6299 if (sw_rx_cons == hw_rx_cons) 6300 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6301 } 6302 6303 #ifdef BCE_JUMBO_HDRSPLIT 6304 /* No new packets. Refill the page chain. */ 6305 sc->pg_cons = sw_pg_cons; 6306 bce_fill_pg_chain(sc); 6307 #endif 6308 6309 /* No new packets. Refill the RX chain. */ 6310 sc->rx_cons = sw_rx_cons; 6311 bce_fill_rx_chain(sc); 6312 6313 /* Prepare the page chain pages to be accessed by the NIC. */ 6314 for (int i = 0; i < RX_PAGES; i++) 6315 bus_dmamap_sync(sc->rx_bd_chain_tag, 6316 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6317 6318 #ifdef BCE_JUMBO_HDRSPLIT 6319 for (int i = 0; i < PG_PAGES; i++) 6320 bus_dmamap_sync(sc->pg_bd_chain_tag, 6321 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6322 #endif 6323 6324 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6325 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6326 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6327 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6328 } 6329 6330 6331 /****************************************************************************/ 6332 /* Reads the transmit consumer value from the status block (skipping over */ 6333 /* chain page pointer if necessary). */ 6334 /* */ 6335 /* Returns: */ 6336 /* hw_cons */ 6337 /****************************************************************************/ 6338 static inline u16 6339 bce_get_hw_tx_cons(struct bce_softc *sc) 6340 { 6341 u16 hw_cons; 6342 6343 mb(); 6344 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6345 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6346 hw_cons++; 6347 6348 return hw_cons; 6349 } 6350 6351 6352 /****************************************************************************/ 6353 /* Handles transmit completion interrupt events. */ 6354 /* */ 6355 /* Returns: */ 6356 /* Nothing. */ 6357 /****************************************************************************/ 6358 static void 6359 bce_tx_intr(struct bce_softc *sc) 6360 { 6361 struct ifnet *ifp = sc->bce_ifp; 6362 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6363 6364 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6365 DBRUN(sc->interrupts_tx++); 6366 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6367 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6368 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6369 6370 BCE_LOCK_ASSERT(sc); 6371 6372 /* Get the hardware's view of the TX consumer index. */ 6373 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6374 sw_tx_cons = sc->tx_cons; 6375 6376 /* Prevent speculative reads of the status block. */ 6377 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6378 BUS_SPACE_BARRIER_READ); 6379 6380 /* Cycle through any completed TX chain page entries. */ 6381 while (sw_tx_cons != hw_tx_cons) { 6382 #ifdef BCE_DEBUG 6383 struct tx_bd *txbd = NULL; 6384 #endif 6385 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6386 6387 DBPRINT(sc, BCE_INFO_SEND, 6388 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6389 "sw_tx_chain_cons = 0x%04X\n", 6390 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6391 6392 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 6393 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6394 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6395 (int) MAX_TX_BD); 6396 bce_breakpoint(sc)); 6397 6398 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6399 [TX_IDX(sw_tx_chain_cons)]); 6400 6401 DBRUNIF((txbd == NULL), 6402 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6403 __FILE__, __LINE__, sw_tx_chain_cons); 6404 bce_breakpoint(sc)); 6405 6406 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6407 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6408 6409 /* 6410 * Free the associated mbuf. Remember 6411 * that only the last tx_bd of a packet 6412 * has an mbuf pointer and DMA map. 6413 */ 6414 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6415 6416 /* Validate that this is the last tx_bd. */ 6417 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6418 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6419 "txmbuf == NULL!\n", __FILE__, __LINE__); 6420 bce_breakpoint(sc)); 6421 6422 DBRUNMSG(BCE_INFO_SEND, 6423 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6424 "from tx_bd[0x%04X]\n", __FUNCTION__, 6425 sw_tx_chain_cons)); 6426 6427 /* Unmap the mbuf. */ 6428 bus_dmamap_unload(sc->tx_mbuf_tag, 6429 sc->tx_mbuf_map[sw_tx_chain_cons]); 6430 6431 /* Free the mbuf. */ 6432 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6433 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6434 DBRUN(sc->debug_tx_mbuf_alloc--); 6435 6436 ifp->if_opackets++; 6437 } 6438 6439 sc->used_tx_bd--; 6440 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6441 6442 /* Refresh hw_cons to see if there's new work. */ 6443 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6444 6445 /* Prevent speculative reads of the status block. */ 6446 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6447 BUS_SPACE_BARRIER_READ); 6448 } 6449 6450 /* Clear the TX timeout timer. */ 6451 sc->watchdog_timer = 0; 6452 6453 /* Clear the tx hardware queue full flag. */ 6454 if (sc->used_tx_bd < sc->max_tx_bd) { 6455 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6456 DBPRINT(sc, BCE_INFO_SEND, 6457 "%s(): Open TX chain! %d/%d (used/total)\n", 6458 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6459 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6460 } 6461 6462 sc->tx_cons = sw_tx_cons; 6463 6464 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6465 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6466 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6467 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6468 } 6469 6470 6471 /****************************************************************************/ 6472 /* Disables interrupt generation. */ 6473 /* */ 6474 /* Returns: */ 6475 /* Nothing. */ 6476 /****************************************************************************/ 6477 static void 6478 bce_disable_intr(struct bce_softc *sc) 6479 { 6480 DBENTER(BCE_VERBOSE_INTR); 6481 6482 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6483 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6484 6485 DBEXIT(BCE_VERBOSE_INTR); 6486 } 6487 6488 6489 /****************************************************************************/ 6490 /* Enables interrupt generation. */ 6491 /* */ 6492 /* Returns: */ 6493 /* Nothing. */ 6494 /****************************************************************************/ 6495 static void 6496 bce_enable_intr(struct bce_softc *sc, int coal_now) 6497 { 6498 DBENTER(BCE_VERBOSE_INTR); 6499 6500 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6501 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6502 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6503 6504 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6505 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6506 6507 /* Force an immediate interrupt (whether there is new data or not). */ 6508 if (coal_now) 6509 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6510 6511 DBEXIT(BCE_VERBOSE_INTR); 6512 } 6513 6514 6515 /****************************************************************************/ 6516 /* Handles controller initialization. */ 6517 /* */ 6518 /* Returns: */ 6519 /* Nothing. */ 6520 /****************************************************************************/ 6521 static void 6522 bce_init_locked(struct bce_softc *sc) 6523 { 6524 struct ifnet *ifp; 6525 u32 ether_mtu = 0; 6526 6527 DBENTER(BCE_VERBOSE_RESET); 6528 6529 BCE_LOCK_ASSERT(sc); 6530 6531 ifp = sc->bce_ifp; 6532 6533 /* Check if the driver is still running and bail out if it is. */ 6534 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6535 goto bce_init_locked_exit; 6536 6537 bce_stop(sc); 6538 6539 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6540 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6541 __FILE__, __LINE__); 6542 goto bce_init_locked_exit; 6543 } 6544 6545 if (bce_chipinit(sc)) { 6546 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6547 __FILE__, __LINE__); 6548 goto bce_init_locked_exit; 6549 } 6550 6551 if (bce_blockinit(sc)) { 6552 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6553 __FILE__, __LINE__); 6554 goto bce_init_locked_exit; 6555 } 6556 6557 /* Load our MAC address. */ 6558 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6559 bce_set_mac_addr(sc); 6560 6561 /* 6562 * Calculate and program the hardware Ethernet MTU 6563 * size. Be generous on the receive if we have room. 6564 */ 6565 #ifdef BCE_JUMBO_HDRSPLIT 6566 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + 6567 sc->pg_bd_mbuf_alloc_size)) 6568 ether_mtu = sc->rx_bd_mbuf_data_len + 6569 sc->pg_bd_mbuf_alloc_size; 6570 #else 6571 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6572 ether_mtu = sc->rx_bd_mbuf_data_len; 6573 #endif 6574 else 6575 ether_mtu = ifp->if_mtu; 6576 6577 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6578 6579 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 6580 __FUNCTION__, ether_mtu); 6581 6582 /* Program the mtu, enabling jumbo frame support if necessary. */ 6583 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6584 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6585 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6586 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6587 else 6588 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6589 6590 DBPRINT(sc, BCE_INFO_LOAD, 6591 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, " 6592 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 6593 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 6594 sc->rx_bd_mbuf_align_pad); 6595 6596 /* Program appropriate promiscuous/multicast filtering. */ 6597 bce_set_rx_mode(sc); 6598 6599 #ifdef BCE_JUMBO_HDRSPLIT 6600 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6601 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6602 6603 /* Init page buffer descriptor chain. */ 6604 bce_init_pg_chain(sc); 6605 #endif 6606 6607 /* Init RX buffer descriptor chain. */ 6608 bce_init_rx_chain(sc); 6609 6610 /* Init TX buffer descriptor chain. */ 6611 bce_init_tx_chain(sc); 6612 6613 /* Enable host interrupts. */ 6614 bce_enable_intr(sc, 1); 6615 6616 bce_ifmedia_upd_locked(ifp); 6617 6618 /* Let the OS know the driver is up and running. */ 6619 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6620 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6621 6622 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6623 6624 bce_init_locked_exit: 6625 DBEXIT(BCE_VERBOSE_RESET); 6626 } 6627 6628 6629 /****************************************************************************/ 6630 /* Initialize the controller just enough so that any management firmware */ 6631 /* running on the device will continue to operate correctly. */ 6632 /* */ 6633 /* Returns: */ 6634 /* Nothing. */ 6635 /****************************************************************************/ 6636 static void 6637 bce_mgmt_init_locked(struct bce_softc *sc) 6638 { 6639 struct ifnet *ifp; 6640 6641 DBENTER(BCE_VERBOSE_RESET); 6642 6643 BCE_LOCK_ASSERT(sc); 6644 6645 /* Bail out if management firmware is not running. */ 6646 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6647 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6648 "No management firmware running...\n"); 6649 goto bce_mgmt_init_locked_exit; 6650 } 6651 6652 ifp = sc->bce_ifp; 6653 6654 /* Enable all critical blocks in the MAC. */ 6655 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6656 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6657 DELAY(20); 6658 6659 bce_ifmedia_upd_locked(ifp); 6660 6661 bce_mgmt_init_locked_exit: 6662 DBEXIT(BCE_VERBOSE_RESET); 6663 } 6664 6665 6666 /****************************************************************************/ 6667 /* Handles controller initialization when called from an unlocked routine. */ 6668 /* */ 6669 /* Returns: */ 6670 /* Nothing. */ 6671 /****************************************************************************/ 6672 static void 6673 bce_init(void *xsc) 6674 { 6675 struct bce_softc *sc = xsc; 6676 6677 DBENTER(BCE_VERBOSE_RESET); 6678 6679 BCE_LOCK(sc); 6680 bce_init_locked(sc); 6681 BCE_UNLOCK(sc); 6682 6683 DBEXIT(BCE_VERBOSE_RESET); 6684 } 6685 6686 6687 /****************************************************************************/ 6688 /* Modifies an mbuf for TSO on the hardware. */ 6689 /* */ 6690 /* Returns: */ 6691 /* Pointer to a modified mbuf. */ 6692 /****************************************************************************/ 6693 static struct mbuf * 6694 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 6695 { 6696 struct mbuf *m; 6697 struct ether_header *eh; 6698 struct ip *ip; 6699 struct tcphdr *th; 6700 u16 etype; 6701 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 6702 6703 DBRUN(sc->tso_frames_requested++); 6704 6705 /* Controller may modify mbuf chains. */ 6706 if (M_WRITABLE(*m_head) == 0) { 6707 m = m_dup(*m_head, M_DONTWAIT); 6708 m_freem(*m_head); 6709 if (m == NULL) { 6710 sc->mbuf_alloc_failed_count++; 6711 *m_head = NULL; 6712 return (NULL); 6713 } 6714 *m_head = m; 6715 } 6716 6717 /* 6718 * For TSO the controller needs two pieces of info, 6719 * the MSS and the IP+TCP options length. 6720 */ 6721 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 6722 if (m == NULL) { 6723 *m_head = NULL; 6724 return (NULL); 6725 } 6726 eh = mtod(m, struct ether_header *); 6727 etype = ntohs(eh->ether_type); 6728 6729 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 6730 switch (etype) { 6731 case ETHERTYPE_IP: 6732 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 6733 /* TSO only supported for TCP protocol. */ 6734 if (ip->ip_p != IPPROTO_TCP) { 6735 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 6736 __FILE__, __LINE__); 6737 m_freem(*m_head); 6738 *m_head = NULL; 6739 return (NULL); 6740 } 6741 6742 /* Get IP header length in bytes (min 20) */ 6743 ip_hlen = ip->ip_hl << 2; 6744 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 6745 sizeof(struct tcphdr)); 6746 if (m == NULL) { 6747 *m_head = NULL; 6748 return (NULL); 6749 } 6750 6751 /* Get the TCP header length in bytes (min 20) */ 6752 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 6753 tcp_hlen = (th->th_off << 2); 6754 6755 /* Make sure all IP/TCP options live in the same buffer. */ 6756 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 6757 tcp_hlen); 6758 if (m == NULL) { 6759 *m_head = NULL; 6760 return (NULL); 6761 } 6762 6763 /* IP header length and checksum will be calc'd by hardware */ 6764 ip_len = ip->ip_len; 6765 ip->ip_len = 0; 6766 ip->ip_sum = 0; 6767 break; 6768 case ETHERTYPE_IPV6: 6769 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 6770 __FILE__, __LINE__); 6771 m_freem(*m_head); 6772 *m_head = NULL; 6773 return (NULL); 6774 /* NOT REACHED */ 6775 default: 6776 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 6777 __FILE__, __LINE__); 6778 m_freem(*m_head); 6779 *m_head = NULL; 6780 return (NULL); 6781 } 6782 6783 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 6784 6785 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 6786 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 6787 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 6788 tcp_hlen, ip_len); 6789 6790 /* Set the LSO flag in the TX BD */ 6791 *flags |= TX_BD_FLAGS_SW_LSO; 6792 6793 /* Set the length of IP + TCP options (in 32 bit words) */ 6794 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 6795 sizeof(struct tcphdr)) >> 2) << 8); 6796 6797 DBRUN(sc->tso_frames_completed++); 6798 return (*m_head); 6799 } 6800 6801 6802 /****************************************************************************/ 6803 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 6804 /* memory visible to the controller. */ 6805 /* */ 6806 /* Returns: */ 6807 /* 0 for success, positive value for failure. */ 6808 /* Modified: */ 6809 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 6810 /****************************************************************************/ 6811 static int 6812 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 6813 { 6814 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 6815 bus_dmamap_t map; 6816 struct tx_bd *txbd = NULL; 6817 struct mbuf *m0; 6818 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 6819 u32 prod_bseq; 6820 6821 #ifdef BCE_DEBUG 6822 u16 debug_prod; 6823 #endif 6824 6825 int i, error, nsegs, rc = 0; 6826 6827 DBENTER(BCE_VERBOSE_SEND); 6828 6829 /* Make sure we have room in the TX chain. */ 6830 if (sc->used_tx_bd >= sc->max_tx_bd) 6831 goto bce_tx_encap_exit; 6832 6833 /* Transfer any checksum offload flags to the bd. */ 6834 m0 = *m_head; 6835 if (m0->m_pkthdr.csum_flags) { 6836 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 6837 m0 = bce_tso_setup(sc, m_head, &flags); 6838 if (m0 == NULL) { 6839 DBRUN(sc->tso_frames_failed++); 6840 goto bce_tx_encap_exit; 6841 } 6842 mss = htole16(m0->m_pkthdr.tso_segsz); 6843 } else { 6844 if (m0->m_pkthdr.csum_flags & CSUM_IP) 6845 flags |= TX_BD_FLAGS_IP_CKSUM; 6846 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 6847 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 6848 } 6849 } 6850 6851 /* Transfer any VLAN tags to the bd. */ 6852 if (m0->m_flags & M_VLANTAG) { 6853 flags |= TX_BD_FLAGS_VLAN_TAG; 6854 vlan_tag = m0->m_pkthdr.ether_vtag; 6855 } 6856 6857 /* Map the mbuf into DMAable memory. */ 6858 prod = sc->tx_prod; 6859 chain_prod = TX_CHAIN_IDX(prod); 6860 map = sc->tx_mbuf_map[chain_prod]; 6861 6862 /* Map the mbuf into our DMA address space. */ 6863 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 6864 segs, &nsegs, BUS_DMA_NOWAIT); 6865 6866 /* Check if the DMA mapping was successful */ 6867 if (error == EFBIG) { 6868 sc->mbuf_frag_count++; 6869 6870 /* Try to defrag the mbuf. */ 6871 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 6872 if (m0 == NULL) { 6873 /* Defrag was unsuccessful */ 6874 m_freem(*m_head); 6875 *m_head = NULL; 6876 sc->mbuf_alloc_failed_count++; 6877 rc = ENOBUFS; 6878 goto bce_tx_encap_exit; 6879 } 6880 6881 /* Defrag was successful, try mapping again */ 6882 *m_head = m0; 6883 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 6884 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 6885 6886 /* Still getting an error after a defrag. */ 6887 if (error == ENOMEM) { 6888 /* Insufficient DMA buffers available. */ 6889 sc->dma_map_addr_tx_failed_count++; 6890 rc = error; 6891 goto bce_tx_encap_exit; 6892 } else if (error != 0) { 6893 /* Release it and return an error. */ 6894 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 6895 "TX chain!\n", __FILE__, __LINE__); 6896 m_freem(m0); 6897 *m_head = NULL; 6898 sc->dma_map_addr_tx_failed_count++; 6899 rc = ENOBUFS; 6900 goto bce_tx_encap_exit; 6901 } 6902 } else if (error == ENOMEM) { 6903 /* Insufficient DMA buffers available. */ 6904 sc->dma_map_addr_tx_failed_count++; 6905 rc = error; 6906 goto bce_tx_encap_exit; 6907 } else if (error != 0) { 6908 m_freem(m0); 6909 *m_head = NULL; 6910 sc->dma_map_addr_tx_failed_count++; 6911 rc = error; 6912 goto bce_tx_encap_exit; 6913 } 6914 6915 /* Make sure there's room in the chain */ 6916 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 6917 bus_dmamap_unload(sc->tx_mbuf_tag, map); 6918 rc = ENOBUFS; 6919 goto bce_tx_encap_exit; 6920 } 6921 6922 /* prod points to an empty tx_bd at this point. */ 6923 prod_bseq = sc->tx_prod_bseq; 6924 6925 #ifdef BCE_DEBUG 6926 debug_prod = chain_prod; 6927 #endif 6928 6929 DBPRINT(sc, BCE_INFO_SEND, 6930 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 6931 "prod_bseq = 0x%08X\n", 6932 __FUNCTION__, prod, chain_prod, prod_bseq); 6933 6934 /* 6935 * Cycle through each mbuf segment that makes up 6936 * the outgoing frame, gathering the mapping info 6937 * for that segment and creating a tx_bd for 6938 * the mbuf. 6939 */ 6940 for (i = 0; i < nsegs ; i++) { 6941 6942 chain_prod = TX_CHAIN_IDX(prod); 6943 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 6944 [TX_IDX(chain_prod)]; 6945 6946 txbd->tx_bd_haddr_lo = 6947 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 6948 txbd->tx_bd_haddr_hi = 6949 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 6950 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 6951 htole16(segs[i].ds_len); 6952 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 6953 txbd->tx_bd_flags = htole16(flags); 6954 prod_bseq += segs[i].ds_len; 6955 if (i == 0) 6956 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 6957 prod = NEXT_TX_BD(prod); 6958 } 6959 6960 /* Set the END flag on the last TX buffer descriptor. */ 6961 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 6962 6963 DBRUNMSG(BCE_EXTREME_SEND, 6964 bce_dump_tx_chain(sc, debug_prod, nsegs)); 6965 6966 /* 6967 * Ensure that the mbuf pointer for this transmission 6968 * is placed at the array index of the last 6969 * descriptor in this chain. This is done 6970 * because a single map is used for all 6971 * segments of the mbuf and we don't want to 6972 * unload the map before all of the segments 6973 * have been freed. 6974 */ 6975 sc->tx_mbuf_ptr[chain_prod] = m0; 6976 sc->used_tx_bd += nsegs; 6977 6978 /* Update some debug statistic counters */ 6979 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 6980 sc->tx_hi_watermark = sc->used_tx_bd); 6981 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 6982 DBRUNIF(sc->debug_tx_mbuf_alloc++); 6983 6984 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 6985 6986 /* prod points to the next free tx_bd at this point. */ 6987 sc->tx_prod = prod; 6988 sc->tx_prod_bseq = prod_bseq; 6989 6990 /* Tell the chip about the waiting TX frames. */ 6991 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 6992 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 6993 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 6994 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 6995 6996 bce_tx_encap_exit: 6997 DBEXIT(BCE_VERBOSE_SEND); 6998 return(rc); 6999 } 7000 7001 7002 /****************************************************************************/ 7003 /* Main transmit routine when called from another routine with a lock. */ 7004 /* */ 7005 /* Returns: */ 7006 /* Nothing. */ 7007 /****************************************************************************/ 7008 static void 7009 bce_start_locked(struct ifnet *ifp) 7010 { 7011 struct bce_softc *sc = ifp->if_softc; 7012 struct mbuf *m_head = NULL; 7013 int count = 0; 7014 u16 tx_prod, tx_chain_prod; 7015 7016 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7017 7018 BCE_LOCK_ASSERT(sc); 7019 7020 /* prod points to the next free tx_bd. */ 7021 tx_prod = sc->tx_prod; 7022 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7023 7024 DBPRINT(sc, BCE_INFO_SEND, 7025 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7026 "tx_prod_bseq = 0x%08X\n", 7027 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7028 7029 /* If there's no link or the transmit queue is empty then just exit. */ 7030 if (sc->bce_link_up == FALSE) { 7031 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7032 __FUNCTION__); 7033 goto bce_start_locked_exit; 7034 } 7035 7036 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7037 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7038 __FUNCTION__); 7039 goto bce_start_locked_exit; 7040 } 7041 7042 /* 7043 * Keep adding entries while there is space in the ring. 7044 */ 7045 while (sc->used_tx_bd < sc->max_tx_bd) { 7046 7047 /* Check for any frames to send. */ 7048 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7049 7050 /* Stop when the transmit queue is empty. */ 7051 if (m_head == NULL) 7052 break; 7053 7054 /* 7055 * Pack the data into the transmit ring. If we 7056 * don't have room, place the mbuf back at the 7057 * head of the queue and set the OACTIVE flag 7058 * to wait for the NIC to drain the chain. 7059 */ 7060 if (bce_tx_encap(sc, &m_head)) { 7061 if (m_head != NULL) 7062 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7063 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7064 DBPRINT(sc, BCE_INFO_SEND, 7065 "TX chain is closed for business! Total " 7066 "tx_bd used = %d\n", sc->used_tx_bd); 7067 break; 7068 } 7069 7070 count++; 7071 7072 /* Send a copy of the frame to any BPF listeners. */ 7073 ETHER_BPF_MTAP(ifp, m_head); 7074 } 7075 7076 /* Exit if no packets were dequeued. */ 7077 if (count == 0) { 7078 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7079 "dequeued\n", __FUNCTION__); 7080 goto bce_start_locked_exit; 7081 } 7082 7083 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7084 "send queue.\n", __FUNCTION__, count); 7085 7086 /* Set the tx timeout. */ 7087 sc->watchdog_timer = BCE_TX_TIMEOUT; 7088 7089 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7090 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7091 7092 bce_start_locked_exit: 7093 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7094 return; 7095 } 7096 7097 7098 /****************************************************************************/ 7099 /* Main transmit routine when called from another routine without a lock. */ 7100 /* */ 7101 /* Returns: */ 7102 /* Nothing. */ 7103 /****************************************************************************/ 7104 static void 7105 bce_start(struct ifnet *ifp) 7106 { 7107 struct bce_softc *sc = ifp->if_softc; 7108 7109 DBENTER(BCE_VERBOSE_SEND); 7110 7111 BCE_LOCK(sc); 7112 bce_start_locked(ifp); 7113 BCE_UNLOCK(sc); 7114 7115 DBEXIT(BCE_VERBOSE_SEND); 7116 } 7117 7118 7119 /****************************************************************************/ 7120 /* Handles any IOCTL calls from the operating system. */ 7121 /* */ 7122 /* Returns: */ 7123 /* 0 for success, positive value for failure. */ 7124 /****************************************************************************/ 7125 static int 7126 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7127 { 7128 struct bce_softc *sc = ifp->if_softc; 7129 struct ifreq *ifr = (struct ifreq *) data; 7130 struct mii_data *mii; 7131 int mask, error = 0, reinit; 7132 7133 DBENTER(BCE_VERBOSE_MISC); 7134 7135 switch(command) { 7136 7137 /* Set the interface MTU. */ 7138 case SIOCSIFMTU: 7139 /* Check that the MTU setting is supported. */ 7140 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7141 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7142 error = EINVAL; 7143 break; 7144 } 7145 7146 DBPRINT(sc, BCE_INFO_MISC, 7147 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7148 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7149 7150 BCE_LOCK(sc); 7151 ifp->if_mtu = ifr->ifr_mtu; 7152 reinit = 0; 7153 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7154 /* 7155 * Because allocation size is used in RX 7156 * buffer allocation, stop controller if 7157 * it is already running. 7158 */ 7159 bce_stop(sc); 7160 reinit = 1; 7161 } 7162 #ifdef BCE_JUMBO_HDRSPLIT 7163 /* No buffer allocation size changes are necessary. */ 7164 #else 7165 /* Recalculate our buffer allocation sizes. */ 7166 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 7167 ETHER_CRC_LEN) > MCLBYTES) { 7168 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 7169 sc->rx_bd_mbuf_align_pad = 7170 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 7171 sc->rx_bd_mbuf_data_len = 7172 sc->rx_bd_mbuf_alloc_size - 7173 sc->rx_bd_mbuf_align_pad; 7174 } else { 7175 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 7176 sc->rx_bd_mbuf_align_pad = 7177 roundup2(MCLBYTES, 16) - MCLBYTES; 7178 sc->rx_bd_mbuf_data_len = 7179 sc->rx_bd_mbuf_alloc_size - 7180 sc->rx_bd_mbuf_align_pad; 7181 } 7182 #endif 7183 7184 if (reinit != 0) 7185 bce_init_locked(sc); 7186 BCE_UNLOCK(sc); 7187 break; 7188 7189 /* Set interface flags. */ 7190 case SIOCSIFFLAGS: 7191 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7192 7193 BCE_LOCK(sc); 7194 7195 /* Check if the interface is up. */ 7196 if (ifp->if_flags & IFF_UP) { 7197 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7198 /* Change promiscuous/multicast flags as necessary. */ 7199 bce_set_rx_mode(sc); 7200 } else { 7201 /* Start the HW */ 7202 bce_init_locked(sc); 7203 } 7204 } else { 7205 /* The interface is down, check if driver is running. */ 7206 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7207 bce_stop(sc); 7208 7209 /* If MFW is running, restart the controller a bit. */ 7210 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7211 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7212 bce_chipinit(sc); 7213 bce_mgmt_init_locked(sc); 7214 } 7215 } 7216 } 7217 7218 BCE_UNLOCK(sc); 7219 break; 7220 7221 /* Add/Delete multicast address */ 7222 case SIOCADDMULTI: 7223 case SIOCDELMULTI: 7224 DBPRINT(sc, BCE_VERBOSE_MISC, 7225 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7226 7227 BCE_LOCK(sc); 7228 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7229 bce_set_rx_mode(sc); 7230 BCE_UNLOCK(sc); 7231 7232 break; 7233 7234 /* Set/Get Interface media */ 7235 case SIOCSIFMEDIA: 7236 case SIOCGIFMEDIA: 7237 DBPRINT(sc, BCE_VERBOSE_MISC, 7238 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7239 7240 mii = device_get_softc(sc->bce_miibus); 7241 error = ifmedia_ioctl(ifp, ifr, 7242 &mii->mii_media, command); 7243 break; 7244 7245 /* Set interface capability */ 7246 case SIOCSIFCAP: 7247 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7248 DBPRINT(sc, BCE_INFO_MISC, 7249 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7250 7251 /* Toggle the TX checksum capabilities enable flag. */ 7252 if (mask & IFCAP_TXCSUM && 7253 ifp->if_capabilities & IFCAP_TXCSUM) { 7254 ifp->if_capenable ^= IFCAP_TXCSUM; 7255 if (IFCAP_TXCSUM & ifp->if_capenable) 7256 ifp->if_hwassist |= BCE_IF_HWASSIST; 7257 else 7258 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7259 } 7260 7261 /* Toggle the RX checksum capabilities enable flag. */ 7262 if (mask & IFCAP_RXCSUM && 7263 ifp->if_capabilities & IFCAP_RXCSUM) 7264 ifp->if_capenable ^= IFCAP_RXCSUM; 7265 7266 /* Toggle the TSO capabilities enable flag. */ 7267 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7268 ifp->if_capabilities & IFCAP_TSO4) { 7269 ifp->if_capenable ^= IFCAP_TSO4; 7270 if (IFCAP_TSO4 & ifp->if_capenable) 7271 ifp->if_hwassist |= CSUM_TSO; 7272 else 7273 ifp->if_hwassist &= ~CSUM_TSO; 7274 } 7275 7276 if (mask & IFCAP_VLAN_HWCSUM && 7277 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7278 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7279 7280 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7281 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7282 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7283 /* 7284 * Don't actually disable VLAN tag stripping as 7285 * management firmware (ASF/IPMI/UMP) requires the 7286 * feature. If VLAN tag stripping is disabled driver 7287 * will manually reconstruct the VLAN frame by 7288 * appending stripped VLAN tag. 7289 */ 7290 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7291 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7292 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7293 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7294 == 0) 7295 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7296 } 7297 VLAN_CAPABILITIES(ifp); 7298 break; 7299 default: 7300 /* We don't know how to handle the IOCTL, pass it on. */ 7301 error = ether_ioctl(ifp, command, data); 7302 break; 7303 } 7304 7305 DBEXIT(BCE_VERBOSE_MISC); 7306 return(error); 7307 } 7308 7309 7310 /****************************************************************************/ 7311 /* Transmit timeout handler. */ 7312 /* */ 7313 /* Returns: */ 7314 /* Nothing. */ 7315 /****************************************************************************/ 7316 static void 7317 bce_watchdog(struct bce_softc *sc) 7318 { 7319 DBENTER(BCE_EXTREME_SEND); 7320 7321 BCE_LOCK_ASSERT(sc); 7322 7323 /* If the watchdog timer hasn't expired then just exit. */ 7324 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7325 goto bce_watchdog_exit; 7326 7327 /* If pause frames are active then don't reset the hardware. */ 7328 /* ToDo: Should we reset the timer here? */ 7329 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7330 goto bce_watchdog_exit; 7331 7332 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7333 __FILE__, __LINE__); 7334 7335 DBRUNMSG(BCE_INFO, 7336 bce_dump_driver_state(sc); 7337 bce_dump_status_block(sc); 7338 bce_dump_stats_block(sc); 7339 bce_dump_ftqs(sc); 7340 bce_dump_txp_state(sc, 0); 7341 bce_dump_rxp_state(sc, 0); 7342 bce_dump_tpat_state(sc, 0); 7343 bce_dump_cp_state(sc, 0); 7344 bce_dump_com_state(sc, 0)); 7345 7346 DBRUN(bce_breakpoint(sc)); 7347 7348 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7349 7350 bce_init_locked(sc); 7351 sc->bce_ifp->if_oerrors++; 7352 7353 bce_watchdog_exit: 7354 DBEXIT(BCE_EXTREME_SEND); 7355 } 7356 7357 7358 /* 7359 * Interrupt handler. 7360 */ 7361 /****************************************************************************/ 7362 /* Main interrupt entry point. Verifies that the controller generated the */ 7363 /* interrupt and then calls a separate routine for handle the various */ 7364 /* interrupt causes (PHY, TX, RX). */ 7365 /* */ 7366 /* Returns: */ 7367 /* 0 for success, positive value for failure. */ 7368 /****************************************************************************/ 7369 static void 7370 bce_intr(void *xsc) 7371 { 7372 struct bce_softc *sc; 7373 struct ifnet *ifp; 7374 u32 status_attn_bits; 7375 u16 hw_rx_cons, hw_tx_cons; 7376 7377 sc = xsc; 7378 ifp = sc->bce_ifp; 7379 7380 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7381 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7382 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7383 7384 BCE_LOCK(sc); 7385 7386 DBRUN(sc->interrupts_generated++); 7387 7388 /* Synchnorize before we read from interface's status block */ 7389 bus_dmamap_sync(sc->status_tag, sc->status_map, 7390 BUS_DMASYNC_POSTREAD); 7391 7392 /* 7393 * If the hardware status block index 7394 * matches the last value read by the 7395 * driver and we haven't asserted our 7396 * interrupt then there's nothing to do. 7397 */ 7398 if ((sc->status_block->status_idx == sc->last_status_idx) && 7399 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7400 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7401 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7402 __FUNCTION__); 7403 goto bce_intr_exit; 7404 } 7405 7406 /* Ack the interrupt and stop others from occuring. */ 7407 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7408 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7409 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7410 7411 /* Check if the hardware has finished any work. */ 7412 hw_rx_cons = bce_get_hw_rx_cons(sc); 7413 hw_tx_cons = bce_get_hw_tx_cons(sc); 7414 7415 /* Keep processing data as long as there is work to do. */ 7416 for (;;) { 7417 7418 status_attn_bits = sc->status_block->status_attn_bits; 7419 7420 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7421 BCE_PRINTF("Simulating unexpected status attention " 7422 "bit set."); 7423 sc->unexpected_attention_sim_count++; 7424 status_attn_bits = status_attn_bits | 7425 STATUS_ATTN_BITS_PARITY_ERROR); 7426 7427 /* Was it a link change interrupt? */ 7428 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7429 (sc->status_block->status_attn_bits_ack & 7430 STATUS_ATTN_BITS_LINK_STATE)) { 7431 bce_phy_intr(sc); 7432 7433 /* Clear transient updates during link state change. */ 7434 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7435 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7436 REG_RD(sc, BCE_HC_COMMAND); 7437 } 7438 7439 /* If any other attention is asserted, the chip is toast. */ 7440 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7441 (sc->status_block->status_attn_bits_ack & 7442 ~STATUS_ATTN_BITS_LINK_STATE))) { 7443 7444 sc->unexpected_attention_count++; 7445 7446 BCE_PRINTF("%s(%d): Fatal attention detected: " 7447 "0x%08X\n", __FILE__, __LINE__, 7448 sc->status_block->status_attn_bits); 7449 7450 DBRUNMSG(BCE_FATAL, 7451 if (unexpected_attention_sim_control == 0) 7452 bce_breakpoint(sc)); 7453 7454 bce_init_locked(sc); 7455 goto bce_intr_exit; 7456 } 7457 7458 /* Check for any completed RX frames. */ 7459 if (hw_rx_cons != sc->hw_rx_cons) 7460 bce_rx_intr(sc); 7461 7462 /* Check for any completed TX frames. */ 7463 if (hw_tx_cons != sc->hw_tx_cons) 7464 bce_tx_intr(sc); 7465 7466 /* Save status block index value for the next interrupt. */ 7467 sc->last_status_idx = sc->status_block->status_idx; 7468 7469 /* 7470 * Prevent speculative reads from getting 7471 * ahead of the status block. 7472 */ 7473 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7474 BUS_SPACE_BARRIER_READ); 7475 7476 /* 7477 * If there's no work left then exit the 7478 * interrupt service routine. 7479 */ 7480 hw_rx_cons = bce_get_hw_rx_cons(sc); 7481 hw_tx_cons = bce_get_hw_tx_cons(sc); 7482 7483 if ((hw_rx_cons == sc->hw_rx_cons) && 7484 (hw_tx_cons == sc->hw_tx_cons)) 7485 break; 7486 7487 } 7488 7489 bus_dmamap_sync(sc->status_tag, sc->status_map, 7490 BUS_DMASYNC_PREREAD); 7491 7492 /* Re-enable interrupts. */ 7493 bce_enable_intr(sc, 0); 7494 7495 /* Handle any frames that arrived while handling the interrupt. */ 7496 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7497 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7498 bce_start_locked(ifp); 7499 7500 bce_intr_exit: 7501 BCE_UNLOCK(sc); 7502 7503 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7504 } 7505 7506 7507 /****************************************************************************/ 7508 /* Programs the various packet receive modes (broadcast and multicast). */ 7509 /* */ 7510 /* Returns: */ 7511 /* Nothing. */ 7512 /****************************************************************************/ 7513 static void 7514 bce_set_rx_mode(struct bce_softc *sc) 7515 { 7516 struct ifnet *ifp; 7517 struct ifmultiaddr *ifma; 7518 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7519 u32 rx_mode, sort_mode; 7520 int h, i; 7521 7522 DBENTER(BCE_VERBOSE_MISC); 7523 7524 BCE_LOCK_ASSERT(sc); 7525 7526 ifp = sc->bce_ifp; 7527 7528 /* Initialize receive mode default settings. */ 7529 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7530 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7531 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7532 7533 /* 7534 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7535 * be enbled. 7536 */ 7537 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7538 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7539 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7540 7541 /* 7542 * Check for promiscuous, all multicast, or selected 7543 * multicast address filtering. 7544 */ 7545 if (ifp->if_flags & IFF_PROMISC) { 7546 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7547 7548 /* Enable promiscuous mode. */ 7549 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7550 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7551 } else if (ifp->if_flags & IFF_ALLMULTI) { 7552 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7553 7554 /* Enable all multicast addresses. */ 7555 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7556 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7557 } 7558 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7559 } else { 7560 /* Accept one or more multicast(s). */ 7561 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7562 7563 if_maddr_rlock(ifp); 7564 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7565 if (ifma->ifma_addr->sa_family != AF_LINK) 7566 continue; 7567 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7568 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7569 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7570 } 7571 if_maddr_runlock(ifp); 7572 7573 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7574 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7575 7576 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7577 } 7578 7579 /* Only make changes if the recive mode has actually changed. */ 7580 if (rx_mode != sc->rx_mode) { 7581 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7582 "0x%08X\n", rx_mode); 7583 7584 sc->rx_mode = rx_mode; 7585 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7586 } 7587 7588 /* Disable and clear the exisitng sort before enabling a new sort. */ 7589 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7590 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7591 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7592 7593 DBEXIT(BCE_VERBOSE_MISC); 7594 } 7595 7596 7597 /****************************************************************************/ 7598 /* Called periodically to updates statistics from the controllers */ 7599 /* statistics block. */ 7600 /* */ 7601 /* Returns: */ 7602 /* Nothing. */ 7603 /****************************************************************************/ 7604 static void 7605 bce_stats_update(struct bce_softc *sc) 7606 { 7607 struct ifnet *ifp; 7608 struct statistics_block *stats; 7609 7610 DBENTER(BCE_EXTREME_MISC); 7611 7612 ifp = sc->bce_ifp; 7613 7614 stats = (struct statistics_block *) sc->stats_block; 7615 7616 /* 7617 * Certain controllers don't report 7618 * carrier sense errors correctly. 7619 * See errata E11_5708CA0_1165. 7620 */ 7621 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7622 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7623 ifp->if_oerrors += 7624 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7625 7626 /* 7627 * Update the sysctl statistics from the 7628 * hardware statistics. 7629 */ 7630 sc->stat_IfHCInOctets = 7631 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7632 (u64) stats->stat_IfHCInOctets_lo; 7633 7634 sc->stat_IfHCInBadOctets = 7635 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7636 (u64) stats->stat_IfHCInBadOctets_lo; 7637 7638 sc->stat_IfHCOutOctets = 7639 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7640 (u64) stats->stat_IfHCOutOctets_lo; 7641 7642 sc->stat_IfHCOutBadOctets = 7643 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7644 (u64) stats->stat_IfHCOutBadOctets_lo; 7645 7646 sc->stat_IfHCInUcastPkts = 7647 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7648 (u64) stats->stat_IfHCInUcastPkts_lo; 7649 7650 sc->stat_IfHCInMulticastPkts = 7651 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7652 (u64) stats->stat_IfHCInMulticastPkts_lo; 7653 7654 sc->stat_IfHCInBroadcastPkts = 7655 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7656 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7657 7658 sc->stat_IfHCOutUcastPkts = 7659 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7660 (u64) stats->stat_IfHCOutUcastPkts_lo; 7661 7662 sc->stat_IfHCOutMulticastPkts = 7663 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7664 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7665 7666 sc->stat_IfHCOutBroadcastPkts = 7667 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7668 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7669 7670 /* ToDo: Preserve counters beyond 32 bits? */ 7671 /* ToDo: Read the statistics from auto-clear regs? */ 7672 7673 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7674 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7675 7676 sc->stat_Dot3StatsCarrierSenseErrors = 7677 stats->stat_Dot3StatsCarrierSenseErrors; 7678 7679 sc->stat_Dot3StatsFCSErrors = 7680 stats->stat_Dot3StatsFCSErrors; 7681 7682 sc->stat_Dot3StatsAlignmentErrors = 7683 stats->stat_Dot3StatsAlignmentErrors; 7684 7685 sc->stat_Dot3StatsSingleCollisionFrames = 7686 stats->stat_Dot3StatsSingleCollisionFrames; 7687 7688 sc->stat_Dot3StatsMultipleCollisionFrames = 7689 stats->stat_Dot3StatsMultipleCollisionFrames; 7690 7691 sc->stat_Dot3StatsDeferredTransmissions = 7692 stats->stat_Dot3StatsDeferredTransmissions; 7693 7694 sc->stat_Dot3StatsExcessiveCollisions = 7695 stats->stat_Dot3StatsExcessiveCollisions; 7696 7697 sc->stat_Dot3StatsLateCollisions = 7698 stats->stat_Dot3StatsLateCollisions; 7699 7700 sc->stat_EtherStatsCollisions = 7701 stats->stat_EtherStatsCollisions; 7702 7703 sc->stat_EtherStatsFragments = 7704 stats->stat_EtherStatsFragments; 7705 7706 sc->stat_EtherStatsJabbers = 7707 stats->stat_EtherStatsJabbers; 7708 7709 sc->stat_EtherStatsUndersizePkts = 7710 stats->stat_EtherStatsUndersizePkts; 7711 7712 sc->stat_EtherStatsOversizePkts = 7713 stats->stat_EtherStatsOversizePkts; 7714 7715 sc->stat_EtherStatsPktsRx64Octets = 7716 stats->stat_EtherStatsPktsRx64Octets; 7717 7718 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 7719 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 7720 7721 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 7722 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 7723 7724 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 7725 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 7726 7727 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 7728 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 7729 7730 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 7731 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 7732 7733 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 7734 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 7735 7736 sc->stat_EtherStatsPktsTx64Octets = 7737 stats->stat_EtherStatsPktsTx64Octets; 7738 7739 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 7740 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 7741 7742 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 7743 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 7744 7745 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 7746 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 7747 7748 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 7749 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 7750 7751 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 7752 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 7753 7754 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 7755 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 7756 7757 sc->stat_XonPauseFramesReceived = 7758 stats->stat_XonPauseFramesReceived; 7759 7760 sc->stat_XoffPauseFramesReceived = 7761 stats->stat_XoffPauseFramesReceived; 7762 7763 sc->stat_OutXonSent = 7764 stats->stat_OutXonSent; 7765 7766 sc->stat_OutXoffSent = 7767 stats->stat_OutXoffSent; 7768 7769 sc->stat_FlowControlDone = 7770 stats->stat_FlowControlDone; 7771 7772 sc->stat_MacControlFramesReceived = 7773 stats->stat_MacControlFramesReceived; 7774 7775 sc->stat_XoffStateEntered = 7776 stats->stat_XoffStateEntered; 7777 7778 sc->stat_IfInFramesL2FilterDiscards = 7779 stats->stat_IfInFramesL2FilterDiscards; 7780 7781 sc->stat_IfInRuleCheckerDiscards = 7782 stats->stat_IfInRuleCheckerDiscards; 7783 7784 sc->stat_IfInFTQDiscards = 7785 stats->stat_IfInFTQDiscards; 7786 7787 sc->stat_IfInMBUFDiscards = 7788 stats->stat_IfInMBUFDiscards; 7789 7790 sc->stat_IfInRuleCheckerP4Hit = 7791 stats->stat_IfInRuleCheckerP4Hit; 7792 7793 sc->stat_CatchupInRuleCheckerDiscards = 7794 stats->stat_CatchupInRuleCheckerDiscards; 7795 7796 sc->stat_CatchupInFTQDiscards = 7797 stats->stat_CatchupInFTQDiscards; 7798 7799 sc->stat_CatchupInMBUFDiscards = 7800 stats->stat_CatchupInMBUFDiscards; 7801 7802 sc->stat_CatchupInRuleCheckerP4Hit = 7803 stats->stat_CatchupInRuleCheckerP4Hit; 7804 7805 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 7806 7807 /* 7808 * Update the interface statistics from the 7809 * hardware statistics. 7810 */ 7811 ifp->if_collisions = 7812 (u_long) sc->stat_EtherStatsCollisions; 7813 7814 /* ToDo: This method loses soft errors. */ 7815 ifp->if_ierrors = 7816 (u_long) sc->stat_EtherStatsUndersizePkts + 7817 (u_long) sc->stat_EtherStatsOversizePkts + 7818 (u_long) sc->stat_IfInMBUFDiscards + 7819 (u_long) sc->stat_Dot3StatsAlignmentErrors + 7820 (u_long) sc->stat_Dot3StatsFCSErrors + 7821 (u_long) sc->stat_IfInRuleCheckerDiscards + 7822 (u_long) sc->stat_IfInFTQDiscards + 7823 (u_long) sc->com_no_buffers; 7824 7825 /* ToDo: This method loses soft errors. */ 7826 ifp->if_oerrors = 7827 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 7828 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 7829 (u_long) sc->stat_Dot3StatsLateCollisions; 7830 7831 /* ToDo: Add additional statistics? */ 7832 7833 DBEXIT(BCE_EXTREME_MISC); 7834 } 7835 7836 7837 /****************************************************************************/ 7838 /* Periodic function to notify the bootcode that the driver is still */ 7839 /* present. */ 7840 /* */ 7841 /* Returns: */ 7842 /* Nothing. */ 7843 /****************************************************************************/ 7844 static void 7845 bce_pulse(void *xsc) 7846 { 7847 struct bce_softc *sc = xsc; 7848 u32 msg; 7849 7850 DBENTER(BCE_EXTREME_MISC); 7851 7852 BCE_LOCK_ASSERT(sc); 7853 7854 /* Tell the firmware that the driver is still running. */ 7855 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 7856 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 7857 7858 /* Update the bootcode condition. */ 7859 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 7860 7861 /* Report whether the bootcode still knows the driver is running. */ 7862 if (bootverbose) { 7863 if (sc->bce_drv_cardiac_arrest == FALSE) { 7864 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 7865 sc->bce_drv_cardiac_arrest = TRUE; 7866 BCE_PRINTF("%s(): Warning: bootcode " 7867 "thinks driver is absent! " 7868 "(bc_state = 0x%08X)\n", 7869 __FUNCTION__, sc->bc_state); 7870 } 7871 } else { 7872 /* 7873 * Not supported by all bootcode versions. 7874 * (v5.0.11+ and v5.2.1+) Older bootcode 7875 * will require the driver to reset the 7876 * controller to clear this condition. 7877 */ 7878 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 7879 sc->bce_drv_cardiac_arrest = FALSE; 7880 BCE_PRINTF("%s(): Bootcode found the " 7881 "driver pulse! (bc_state = 0x%08X)\n", 7882 __FUNCTION__, sc->bc_state); 7883 } 7884 } 7885 } 7886 7887 7888 /* Schedule the next pulse. */ 7889 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 7890 7891 DBEXIT(BCE_EXTREME_MISC); 7892 } 7893 7894 7895 /****************************************************************************/ 7896 /* Periodic function to perform maintenance tasks. */ 7897 /* */ 7898 /* Returns: */ 7899 /* Nothing. */ 7900 /****************************************************************************/ 7901 static void 7902 bce_tick(void *xsc) 7903 { 7904 struct bce_softc *sc = xsc; 7905 struct mii_data *mii; 7906 struct ifnet *ifp; 7907 7908 ifp = sc->bce_ifp; 7909 7910 DBENTER(BCE_EXTREME_MISC); 7911 7912 BCE_LOCK_ASSERT(sc); 7913 7914 /* Schedule the next tick. */ 7915 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7916 7917 /* Update the statistics from the hardware statistics block. */ 7918 bce_stats_update(sc); 7919 7920 /* Top off the receive and page chains. */ 7921 #ifdef BCE_JUMBO_HDRSPLIT 7922 bce_fill_pg_chain(sc); 7923 #endif 7924 bce_fill_rx_chain(sc); 7925 7926 /* Check that chip hasn't hung. */ 7927 bce_watchdog(sc); 7928 7929 /* If link is up already up then we're done. */ 7930 if (sc->bce_link_up == TRUE) 7931 goto bce_tick_exit; 7932 7933 /* Link is down. Check what the PHY's doing. */ 7934 mii = device_get_softc(sc->bce_miibus); 7935 mii_tick(mii); 7936 7937 /* Check if the link has come up. */ 7938 if ((mii->mii_media_status & IFM_ACTIVE) && 7939 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 7940 DBPRINT(sc, BCE_VERBOSE_MISC, 7941 "%s(): Link up!\n", __FUNCTION__); 7942 sc->bce_link_up = TRUE; 7943 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 7944 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 7945 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 7946 bootverbose) 7947 BCE_PRINTF("Gigabit link up!\n"); 7948 7949 /* Now that link is up, handle any outstanding TX traffic. */ 7950 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7951 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 7952 "pending TX traffic.\n", __FUNCTION__); 7953 bce_start_locked(ifp); 7954 } 7955 } 7956 7957 bce_tick_exit: 7958 DBEXIT(BCE_EXTREME_MISC); 7959 return; 7960 } 7961 7962 7963 #ifdef BCE_DEBUG 7964 /****************************************************************************/ 7965 /* Allows the driver state to be dumped through the sysctl interface. */ 7966 /* */ 7967 /* Returns: */ 7968 /* 0 for success, positive value for failure. */ 7969 /****************************************************************************/ 7970 static int 7971 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 7972 { 7973 int error; 7974 int result; 7975 struct bce_softc *sc; 7976 7977 result = -1; 7978 error = sysctl_handle_int(oidp, &result, 0, req); 7979 7980 if (error || !req->newptr) 7981 return (error); 7982 7983 if (result == 1) { 7984 sc = (struct bce_softc *)arg1; 7985 bce_dump_driver_state(sc); 7986 } 7987 7988 return error; 7989 } 7990 7991 7992 /****************************************************************************/ 7993 /* Allows the hardware state to be dumped through the sysctl interface. */ 7994 /* */ 7995 /* Returns: */ 7996 /* 0 for success, positive value for failure. */ 7997 /****************************************************************************/ 7998 static int 7999 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8000 { 8001 int error; 8002 int result; 8003 struct bce_softc *sc; 8004 8005 result = -1; 8006 error = sysctl_handle_int(oidp, &result, 0, req); 8007 8008 if (error || !req->newptr) 8009 return (error); 8010 8011 if (result == 1) { 8012 sc = (struct bce_softc *)arg1; 8013 bce_dump_hw_state(sc); 8014 } 8015 8016 return error; 8017 } 8018 8019 8020 /****************************************************************************/ 8021 /* Allows the status block to be dumped through the sysctl interface. */ 8022 /* */ 8023 /* Returns: */ 8024 /* 0 for success, positive value for failure. */ 8025 /****************************************************************************/ 8026 static int 8027 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8028 { 8029 int error; 8030 int result; 8031 struct bce_softc *sc; 8032 8033 result = -1; 8034 error = sysctl_handle_int(oidp, &result, 0, req); 8035 8036 if (error || !req->newptr) 8037 return (error); 8038 8039 if (result == 1) { 8040 sc = (struct bce_softc *)arg1; 8041 bce_dump_status_block(sc); 8042 } 8043 8044 return error; 8045 } 8046 8047 8048 /****************************************************************************/ 8049 /* Allows the stats block to be dumped through the sysctl interface. */ 8050 /* */ 8051 /* Returns: */ 8052 /* 0 for success, positive value for failure. */ 8053 /****************************************************************************/ 8054 static int 8055 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8056 { 8057 int error; 8058 int result; 8059 struct bce_softc *sc; 8060 8061 result = -1; 8062 error = sysctl_handle_int(oidp, &result, 0, req); 8063 8064 if (error || !req->newptr) 8065 return (error); 8066 8067 if (result == 1) { 8068 sc = (struct bce_softc *)arg1; 8069 bce_dump_stats_block(sc); 8070 } 8071 8072 return error; 8073 } 8074 8075 8076 /****************************************************************************/ 8077 /* Allows the stat counters to be cleared without unloading/reloading the */ 8078 /* driver. */ 8079 /* */ 8080 /* Returns: */ 8081 /* 0 for success, positive value for failure. */ 8082 /****************************************************************************/ 8083 static int 8084 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8085 { 8086 int error; 8087 int result; 8088 struct bce_softc *sc; 8089 8090 result = -1; 8091 error = sysctl_handle_int(oidp, &result, 0, req); 8092 8093 if (error || !req->newptr) 8094 return (error); 8095 8096 if (result == 1) { 8097 sc = (struct bce_softc *)arg1; 8098 8099 /* Clear the internal H/W statistics counters. */ 8100 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8101 8102 /* Reset the driver maintained statistics. */ 8103 sc->interrupts_rx = 8104 sc->interrupts_tx = 0; 8105 sc->tso_frames_requested = 8106 sc->tso_frames_completed = 8107 sc->tso_frames_failed = 0; 8108 sc->rx_empty_count = 8109 sc->tx_full_count = 0; 8110 sc->rx_low_watermark = USABLE_RX_BD; 8111 sc->tx_hi_watermark = 0; 8112 sc->l2fhdr_error_count = 8113 sc->l2fhdr_error_sim_count = 0; 8114 sc->mbuf_alloc_failed_count = 8115 sc->mbuf_alloc_failed_sim_count = 0; 8116 sc->dma_map_addr_rx_failed_count = 8117 sc->dma_map_addr_tx_failed_count = 0; 8118 sc->mbuf_frag_count = 0; 8119 sc->csum_offload_tcp_udp = 8120 sc->csum_offload_ip = 0; 8121 sc->vlan_tagged_frames_rcvd = 8122 sc->vlan_tagged_frames_stripped = 0; 8123 8124 /* Clear firmware maintained statistics. */ 8125 REG_WR_IND(sc, 0x120084, 0); 8126 } 8127 8128 return error; 8129 } 8130 8131 8132 /****************************************************************************/ 8133 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8134 /* */ 8135 /* Returns: */ 8136 /* 0 for success, positive value for failure. */ 8137 /****************************************************************************/ 8138 static int 8139 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8140 { 8141 int error; 8142 int result; 8143 struct bce_softc *sc; 8144 8145 result = -1; 8146 error = sysctl_handle_int(oidp, &result, 0, req); 8147 8148 if (error || !req->newptr) 8149 return (error); 8150 8151 if (result == 1) { 8152 sc = (struct bce_softc *)arg1; 8153 bce_dump_bc_state(sc); 8154 } 8155 8156 return error; 8157 } 8158 8159 8160 /****************************************************************************/ 8161 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8162 /* */ 8163 /* Returns: */ 8164 /* 0 for success, positive value for failure. */ 8165 /****************************************************************************/ 8166 static int 8167 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8168 { 8169 int error; 8170 int result; 8171 struct bce_softc *sc; 8172 8173 result = -1; 8174 error = sysctl_handle_int(oidp, &result, 0, req); 8175 8176 if (error || !req->newptr) 8177 return (error); 8178 8179 if (result == 1) { 8180 sc = (struct bce_softc *)arg1; 8181 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD); 8182 } 8183 8184 return error; 8185 } 8186 8187 8188 /****************************************************************************/ 8189 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8190 /* */ 8191 /* Returns: */ 8192 /* 0 for success, positive value for failure. */ 8193 /****************************************************************************/ 8194 static int 8195 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8196 { 8197 int error; 8198 int result; 8199 struct bce_softc *sc; 8200 8201 result = -1; 8202 error = sysctl_handle_int(oidp, &result, 0, req); 8203 8204 if (error || !req->newptr) 8205 return (error); 8206 8207 if (result == 1) { 8208 sc = (struct bce_softc *)arg1; 8209 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 8210 } 8211 8212 return error; 8213 } 8214 8215 8216 /****************************************************************************/ 8217 /* Provides a sysctl interface to allow dumping the TX chain. */ 8218 /* */ 8219 /* Returns: */ 8220 /* 0 for success, positive value for failure. */ 8221 /****************************************************************************/ 8222 static int 8223 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8224 { 8225 int error; 8226 int result; 8227 struct bce_softc *sc; 8228 8229 result = -1; 8230 error = sysctl_handle_int(oidp, &result, 0, req); 8231 8232 if (error || !req->newptr) 8233 return (error); 8234 8235 if (result == 1) { 8236 sc = (struct bce_softc *)arg1; 8237 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD); 8238 } 8239 8240 return error; 8241 } 8242 8243 8244 #ifdef BCE_JUMBO_HDRSPLIT 8245 /****************************************************************************/ 8246 /* Provides a sysctl interface to allow dumping the page chain. */ 8247 /* */ 8248 /* Returns: */ 8249 /* 0 for success, positive value for failure. */ 8250 /****************************************************************************/ 8251 static int 8252 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8253 { 8254 int error; 8255 int result; 8256 struct bce_softc *sc; 8257 8258 result = -1; 8259 error = sysctl_handle_int(oidp, &result, 0, req); 8260 8261 if (error || !req->newptr) 8262 return (error); 8263 8264 if (result == 1) { 8265 sc = (struct bce_softc *)arg1; 8266 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD); 8267 } 8268 8269 return error; 8270 } 8271 #endif 8272 8273 /****************************************************************************/ 8274 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8275 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8276 /* */ 8277 /* Returns: */ 8278 /* 0 for success, positive value for failure. */ 8279 /****************************************************************************/ 8280 static int 8281 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8282 { 8283 struct bce_softc *sc = (struct bce_softc *)arg1; 8284 int error; 8285 u32 result; 8286 u32 val[1]; 8287 u8 *data = (u8 *) val; 8288 8289 result = -1; 8290 error = sysctl_handle_int(oidp, &result, 0, req); 8291 if (error || (req->newptr == NULL)) 8292 return (error); 8293 8294 bce_nvram_read(sc, result, data, 4); 8295 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8296 8297 return (error); 8298 } 8299 8300 8301 /****************************************************************************/ 8302 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8303 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8304 /* */ 8305 /* Returns: */ 8306 /* 0 for success, positive value for failure. */ 8307 /****************************************************************************/ 8308 static int 8309 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8310 { 8311 struct bce_softc *sc = (struct bce_softc *)arg1; 8312 int error; 8313 u32 val, result; 8314 8315 result = -1; 8316 error = sysctl_handle_int(oidp, &result, 0, req); 8317 if (error || (req->newptr == NULL)) 8318 return (error); 8319 8320 /* Make sure the register is accessible. */ 8321 if (result < 0x8000) { 8322 val = REG_RD(sc, result); 8323 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8324 } else if (result < 0x0280000) { 8325 val = REG_RD_IND(sc, result); 8326 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8327 } 8328 8329 return (error); 8330 } 8331 8332 8333 /****************************************************************************/ 8334 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8335 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8336 /* */ 8337 /* Returns: */ 8338 /* 0 for success, positive value for failure. */ 8339 /****************************************************************************/ 8340 static int 8341 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8342 { 8343 struct bce_softc *sc; 8344 device_t dev; 8345 int error, result; 8346 u16 val; 8347 8348 result = -1; 8349 error = sysctl_handle_int(oidp, &result, 0, req); 8350 if (error || (req->newptr == NULL)) 8351 return (error); 8352 8353 /* Make sure the register is accessible. */ 8354 if (result < 0x20) { 8355 sc = (struct bce_softc *)arg1; 8356 dev = sc->bce_dev; 8357 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8358 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8359 } 8360 return (error); 8361 } 8362 8363 8364 /****************************************************************************/ 8365 /* Provides a sysctl interface to allow reading a CID. */ 8366 /* */ 8367 /* Returns: */ 8368 /* 0 for success, positive value for failure. */ 8369 /****************************************************************************/ 8370 static int 8371 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8372 { 8373 struct bce_softc *sc; 8374 int error, result; 8375 8376 result = -1; 8377 error = sysctl_handle_int(oidp, &result, 0, req); 8378 if (error || (req->newptr == NULL)) 8379 return (error); 8380 8381 /* Make sure the register is accessible. */ 8382 if (result <= TX_CID) { 8383 sc = (struct bce_softc *)arg1; 8384 bce_dump_ctx(sc, result); 8385 } 8386 8387 return (error); 8388 } 8389 8390 8391 /****************************************************************************/ 8392 /* Provides a sysctl interface to forcing the driver to dump state and */ 8393 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8394 /* */ 8395 /* Returns: */ 8396 /* 0 for success, positive value for failure. */ 8397 /****************************************************************************/ 8398 static int 8399 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8400 { 8401 int error; 8402 int result; 8403 struct bce_softc *sc; 8404 8405 result = -1; 8406 error = sysctl_handle_int(oidp, &result, 0, req); 8407 8408 if (error || !req->newptr) 8409 return (error); 8410 8411 if (result == 1) { 8412 sc = (struct bce_softc *)arg1; 8413 bce_breakpoint(sc); 8414 } 8415 8416 return error; 8417 } 8418 #endif 8419 8420 8421 /****************************************************************************/ 8422 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8423 /* */ 8424 /* Returns: */ 8425 /* 0 for success, positive value for failure. */ 8426 /****************************************************************************/ 8427 static void 8428 bce_add_sysctls(struct bce_softc *sc) 8429 { 8430 struct sysctl_ctx_list *ctx; 8431 struct sysctl_oid_list *children; 8432 8433 DBENTER(BCE_VERBOSE_MISC); 8434 8435 ctx = device_get_sysctl_ctx(sc->bce_dev); 8436 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8437 8438 #ifdef BCE_DEBUG 8439 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8440 "l2fhdr_error_sim_control", 8441 CTLFLAG_RW, &l2fhdr_error_sim_control, 8442 0, "Debug control to force l2fhdr errors"); 8443 8444 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8445 "l2fhdr_error_sim_count", 8446 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8447 0, "Number of simulated l2_fhdr errors"); 8448 #endif 8449 8450 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8451 "l2fhdr_error_count", 8452 CTLFLAG_RD, &sc->l2fhdr_error_count, 8453 0, "Number of l2_fhdr errors"); 8454 8455 #ifdef BCE_DEBUG 8456 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8457 "mbuf_alloc_failed_sim_control", 8458 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8459 0, "Debug control to force mbuf allocation failures"); 8460 8461 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8462 "mbuf_alloc_failed_sim_count", 8463 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8464 0, "Number of simulated mbuf cluster allocation failures"); 8465 #endif 8466 8467 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8468 "mbuf_alloc_failed_count", 8469 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8470 0, "Number of mbuf allocation failures"); 8471 8472 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8473 "mbuf_frag_count", 8474 CTLFLAG_RD, &sc->mbuf_frag_count, 8475 0, "Number of fragmented mbufs"); 8476 8477 #ifdef BCE_DEBUG 8478 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8479 "dma_map_addr_failed_sim_control", 8480 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8481 0, "Debug control to force DMA mapping failures"); 8482 8483 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 8484 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8485 "dma_map_addr_failed_sim_count", 8486 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 8487 0, "Number of simulated DMA mapping failures"); 8488 8489 #endif 8490 8491 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8492 "dma_map_addr_rx_failed_count", 8493 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 8494 0, "Number of RX DMA mapping failures"); 8495 8496 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8497 "dma_map_addr_tx_failed_count", 8498 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 8499 0, "Number of TX DMA mapping failures"); 8500 8501 #ifdef BCE_DEBUG 8502 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8503 "unexpected_attention_sim_control", 8504 CTLFLAG_RW, &unexpected_attention_sim_control, 8505 0, "Debug control to simulate unexpected attentions"); 8506 8507 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8508 "unexpected_attention_sim_count", 8509 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 8510 0, "Number of simulated unexpected attentions"); 8511 #endif 8512 8513 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8514 "unexpected_attention_count", 8515 CTLFLAG_RW, &sc->unexpected_attention_count, 8516 0, "Number of unexpected attentions"); 8517 8518 #ifdef BCE_DEBUG 8519 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8520 "debug_bootcode_running_failure", 8521 CTLFLAG_RW, &bootcode_running_failure_sim_control, 8522 0, "Debug control to force bootcode running failures"); 8523 8524 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8525 "rx_low_watermark", 8526 CTLFLAG_RD, &sc->rx_low_watermark, 8527 0, "Lowest level of free rx_bd's"); 8528 8529 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8530 "rx_empty_count", 8531 CTLFLAG_RD, &sc->rx_empty_count, 8532 0, "Number of times the RX chain was empty"); 8533 8534 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8535 "tx_hi_watermark", 8536 CTLFLAG_RD, &sc->tx_hi_watermark, 8537 0, "Highest level of used tx_bd's"); 8538 8539 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8540 "tx_full_count", 8541 CTLFLAG_RD, &sc->tx_full_count, 8542 0, "Number of times the TX chain was full"); 8543 8544 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8545 "tso_frames_requested", 8546 CTLFLAG_RD, &sc->tso_frames_requested, 8547 0, "Number of TSO frames requested"); 8548 8549 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8550 "tso_frames_completed", 8551 CTLFLAG_RD, &sc->tso_frames_completed, 8552 0, "Number of TSO frames completed"); 8553 8554 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8555 "tso_frames_failed", 8556 CTLFLAG_RD, &sc->tso_frames_failed, 8557 0, "Number of TSO frames failed"); 8558 8559 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8560 "csum_offload_ip", 8561 CTLFLAG_RD, &sc->csum_offload_ip, 8562 0, "Number of IP checksum offload frames"); 8563 8564 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8565 "csum_offload_tcp_udp", 8566 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 8567 0, "Number of TCP/UDP checksum offload frames"); 8568 8569 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8570 "vlan_tagged_frames_rcvd", 8571 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 8572 0, "Number of VLAN tagged frames received"); 8573 8574 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8575 "vlan_tagged_frames_stripped", 8576 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 8577 0, "Number of VLAN tagged frames stripped"); 8578 8579 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8580 "interrupts_rx", 8581 CTLFLAG_RD, &sc->interrupts_rx, 8582 0, "Number of RX interrupts"); 8583 8584 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8585 "interrupts_tx", 8586 CTLFLAG_RD, &sc->interrupts_tx, 8587 0, "Number of TX interrupts"); 8588 #endif 8589 8590 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8591 "stat_IfHcInOctets", 8592 CTLFLAG_RD, &sc->stat_IfHCInOctets, 8593 "Bytes received"); 8594 8595 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8596 "stat_IfHCInBadOctets", 8597 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 8598 "Bad bytes received"); 8599 8600 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8601 "stat_IfHCOutOctets", 8602 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 8603 "Bytes sent"); 8604 8605 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8606 "stat_IfHCOutBadOctets", 8607 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 8608 "Bad bytes sent"); 8609 8610 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8611 "stat_IfHCInUcastPkts", 8612 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 8613 "Unicast packets received"); 8614 8615 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8616 "stat_IfHCInMulticastPkts", 8617 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 8618 "Multicast packets received"); 8619 8620 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8621 "stat_IfHCInBroadcastPkts", 8622 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 8623 "Broadcast packets received"); 8624 8625 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8626 "stat_IfHCOutUcastPkts", 8627 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 8628 "Unicast packets sent"); 8629 8630 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8631 "stat_IfHCOutMulticastPkts", 8632 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 8633 "Multicast packets sent"); 8634 8635 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8636 "stat_IfHCOutBroadcastPkts", 8637 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 8638 "Broadcast packets sent"); 8639 8640 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8641 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 8642 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 8643 0, "Internal MAC transmit errors"); 8644 8645 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8646 "stat_Dot3StatsCarrierSenseErrors", 8647 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 8648 0, "Carrier sense errors"); 8649 8650 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8651 "stat_Dot3StatsFCSErrors", 8652 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 8653 0, "Frame check sequence errors"); 8654 8655 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8656 "stat_Dot3StatsAlignmentErrors", 8657 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 8658 0, "Alignment errors"); 8659 8660 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8661 "stat_Dot3StatsSingleCollisionFrames", 8662 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 8663 0, "Single Collision Frames"); 8664 8665 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8666 "stat_Dot3StatsMultipleCollisionFrames", 8667 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 8668 0, "Multiple Collision Frames"); 8669 8670 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8671 "stat_Dot3StatsDeferredTransmissions", 8672 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 8673 0, "Deferred Transmissions"); 8674 8675 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8676 "stat_Dot3StatsExcessiveCollisions", 8677 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 8678 0, "Excessive Collisions"); 8679 8680 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8681 "stat_Dot3StatsLateCollisions", 8682 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 8683 0, "Late Collisions"); 8684 8685 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8686 "stat_EtherStatsCollisions", 8687 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 8688 0, "Collisions"); 8689 8690 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8691 "stat_EtherStatsFragments", 8692 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 8693 0, "Fragments"); 8694 8695 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8696 "stat_EtherStatsJabbers", 8697 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 8698 0, "Jabbers"); 8699 8700 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8701 "stat_EtherStatsUndersizePkts", 8702 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 8703 0, "Undersize packets"); 8704 8705 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8706 "stat_EtherStatsOversizePkts", 8707 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 8708 0, "stat_EtherStatsOversizePkts"); 8709 8710 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8711 "stat_EtherStatsPktsRx64Octets", 8712 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 8713 0, "Bytes received in 64 byte packets"); 8714 8715 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8716 "stat_EtherStatsPktsRx65Octetsto127Octets", 8717 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 8718 0, "Bytes received in 65 to 127 byte packets"); 8719 8720 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8721 "stat_EtherStatsPktsRx128Octetsto255Octets", 8722 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 8723 0, "Bytes received in 128 to 255 byte packets"); 8724 8725 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8726 "stat_EtherStatsPktsRx256Octetsto511Octets", 8727 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 8728 0, "Bytes received in 256 to 511 byte packets"); 8729 8730 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8731 "stat_EtherStatsPktsRx512Octetsto1023Octets", 8732 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 8733 0, "Bytes received in 512 to 1023 byte packets"); 8734 8735 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8736 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 8737 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 8738 0, "Bytes received in 1024 t0 1522 byte packets"); 8739 8740 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8741 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 8742 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 8743 0, "Bytes received in 1523 to 9022 byte packets"); 8744 8745 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8746 "stat_EtherStatsPktsTx64Octets", 8747 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 8748 0, "Bytes sent in 64 byte packets"); 8749 8750 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8751 "stat_EtherStatsPktsTx65Octetsto127Octets", 8752 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 8753 0, "Bytes sent in 65 to 127 byte packets"); 8754 8755 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8756 "stat_EtherStatsPktsTx128Octetsto255Octets", 8757 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 8758 0, "Bytes sent in 128 to 255 byte packets"); 8759 8760 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8761 "stat_EtherStatsPktsTx256Octetsto511Octets", 8762 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 8763 0, "Bytes sent in 256 to 511 byte packets"); 8764 8765 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8766 "stat_EtherStatsPktsTx512Octetsto1023Octets", 8767 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 8768 0, "Bytes sent in 512 to 1023 byte packets"); 8769 8770 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8771 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 8772 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 8773 0, "Bytes sent in 1024 to 1522 byte packets"); 8774 8775 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8776 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 8777 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 8778 0, "Bytes sent in 1523 to 9022 byte packets"); 8779 8780 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8781 "stat_XonPauseFramesReceived", 8782 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 8783 0, "XON pause frames receved"); 8784 8785 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8786 "stat_XoffPauseFramesReceived", 8787 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 8788 0, "XOFF pause frames received"); 8789 8790 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8791 "stat_OutXonSent", 8792 CTLFLAG_RD, &sc->stat_OutXonSent, 8793 0, "XON pause frames sent"); 8794 8795 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8796 "stat_OutXoffSent", 8797 CTLFLAG_RD, &sc->stat_OutXoffSent, 8798 0, "XOFF pause frames sent"); 8799 8800 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8801 "stat_FlowControlDone", 8802 CTLFLAG_RD, &sc->stat_FlowControlDone, 8803 0, "Flow control done"); 8804 8805 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8806 "stat_MacControlFramesReceived", 8807 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 8808 0, "MAC control frames received"); 8809 8810 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8811 "stat_XoffStateEntered", 8812 CTLFLAG_RD, &sc->stat_XoffStateEntered, 8813 0, "XOFF state entered"); 8814 8815 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8816 "stat_IfInFramesL2FilterDiscards", 8817 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 8818 0, "Received L2 packets discarded"); 8819 8820 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8821 "stat_IfInRuleCheckerDiscards", 8822 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 8823 0, "Received packets discarded by rule"); 8824 8825 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8826 "stat_IfInFTQDiscards", 8827 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 8828 0, "Received packet FTQ discards"); 8829 8830 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8831 "stat_IfInMBUFDiscards", 8832 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 8833 0, "Received packets discarded due to lack " 8834 "of controller buffer memory"); 8835 8836 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8837 "stat_IfInRuleCheckerP4Hit", 8838 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 8839 0, "Received packets rule checker hits"); 8840 8841 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8842 "stat_CatchupInRuleCheckerDiscards", 8843 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 8844 0, "Received packets discarded in Catchup path"); 8845 8846 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8847 "stat_CatchupInFTQDiscards", 8848 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 8849 0, "Received packets discarded in FTQ in Catchup path"); 8850 8851 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8852 "stat_CatchupInMBUFDiscards", 8853 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 8854 0, "Received packets discarded in controller " 8855 "buffer memory in Catchup path"); 8856 8857 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8858 "stat_CatchupInRuleCheckerP4Hit", 8859 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 8860 0, "Received packets rule checker hits in Catchup path"); 8861 8862 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8863 "com_no_buffers", 8864 CTLFLAG_RD, &sc->com_no_buffers, 8865 0, "Valid packets received but no RX buffers available"); 8866 8867 #ifdef BCE_DEBUG 8868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8869 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 8870 (void *)sc, 0, 8871 bce_sysctl_driver_state, "I", "Drive state information"); 8872 8873 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8874 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 8875 (void *)sc, 0, 8876 bce_sysctl_hw_state, "I", "Hardware state information"); 8877 8878 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8879 "status_block", CTLTYPE_INT | CTLFLAG_RW, 8880 (void *)sc, 0, 8881 bce_sysctl_status_block, "I", "Dump status block"); 8882 8883 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8884 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 8885 (void *)sc, 0, 8886 bce_sysctl_stats_block, "I", "Dump statistics block"); 8887 8888 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8889 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 8890 (void *)sc, 0, 8891 bce_sysctl_stats_clear, "I", "Clear statistics block"); 8892 8893 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8894 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 8895 (void *)sc, 0, 8896 bce_sysctl_bc_state, "I", "Bootcode state information"); 8897 8898 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8899 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 8900 (void *)sc, 0, 8901 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 8902 8903 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8904 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 8905 (void *)sc, 0, 8906 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 8907 8908 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8909 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 8910 (void *)sc, 0, 8911 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 8912 8913 #ifdef BCE_JUMBO_HDRSPLIT 8914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8915 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 8916 (void *)sc, 0, 8917 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 8918 #endif 8919 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8920 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 8921 (void *)sc, 0, 8922 bce_sysctl_dump_ctx, "I", "Dump context memory"); 8923 8924 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8925 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 8926 (void *)sc, 0, 8927 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 8928 8929 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8930 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 8931 (void *)sc, 0, 8932 bce_sysctl_reg_read, "I", "Register read"); 8933 8934 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8935 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 8936 (void *)sc, 0, 8937 bce_sysctl_nvram_read, "I", "NVRAM read"); 8938 8939 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8940 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 8941 (void *)sc, 0, 8942 bce_sysctl_phy_read, "I", "PHY register read"); 8943 8944 #endif 8945 8946 DBEXIT(BCE_VERBOSE_MISC); 8947 } 8948 8949 8950 /****************************************************************************/ 8951 /* BCE Debug Routines */ 8952 /****************************************************************************/ 8953 #ifdef BCE_DEBUG 8954 8955 /****************************************************************************/ 8956 /* Freezes the controller to allow for a cohesive state dump. */ 8957 /* */ 8958 /* Returns: */ 8959 /* Nothing. */ 8960 /****************************************************************************/ 8961 static __attribute__ ((noinline)) void 8962 bce_freeze_controller(struct bce_softc *sc) 8963 { 8964 u32 val; 8965 val = REG_RD(sc, BCE_MISC_COMMAND); 8966 val |= BCE_MISC_COMMAND_DISABLE_ALL; 8967 REG_WR(sc, BCE_MISC_COMMAND, val); 8968 } 8969 8970 8971 /****************************************************************************/ 8972 /* Unfreezes the controller after a freeze operation. This may not always */ 8973 /* work and the controller will require a reset! */ 8974 /* */ 8975 /* Returns: */ 8976 /* Nothing. */ 8977 /****************************************************************************/ 8978 static __attribute__ ((noinline)) void 8979 bce_unfreeze_controller(struct bce_softc *sc) 8980 { 8981 u32 val; 8982 val = REG_RD(sc, BCE_MISC_COMMAND); 8983 val |= BCE_MISC_COMMAND_ENABLE_ALL; 8984 REG_WR(sc, BCE_MISC_COMMAND, val); 8985 } 8986 8987 8988 /****************************************************************************/ 8989 /* Prints out Ethernet frame information from an mbuf. */ 8990 /* */ 8991 /* Partially decode an Ethernet frame to look at some important headers. */ 8992 /* */ 8993 /* Returns: */ 8994 /* Nothing. */ 8995 /****************************************************************************/ 8996 static __attribute__ ((noinline)) void 8997 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 8998 { 8999 struct ether_vlan_header *eh; 9000 u16 etype; 9001 int ehlen; 9002 struct ip *ip; 9003 struct tcphdr *th; 9004 struct udphdr *uh; 9005 struct arphdr *ah; 9006 9007 BCE_PRINTF( 9008 "-----------------------------" 9009 " Frame Decode " 9010 "-----------------------------\n"); 9011 9012 eh = mtod(m, struct ether_vlan_header *); 9013 9014 /* Handle VLAN encapsulation if present. */ 9015 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9016 etype = ntohs(eh->evl_proto); 9017 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9018 } else { 9019 etype = ntohs(eh->evl_encap_proto); 9020 ehlen = ETHER_HDR_LEN; 9021 } 9022 9023 /* ToDo: Add VLAN output. */ 9024 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9025 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9026 9027 switch (etype) { 9028 case ETHERTYPE_IP: 9029 ip = (struct ip *)(m->m_data + ehlen); 9030 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9031 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9032 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9033 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9034 9035 switch (ip->ip_p) { 9036 case IPPROTO_TCP: 9037 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9038 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9039 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9040 ntohs(th->th_dport), ntohs(th->th_sport), 9041 (th->th_off << 2), th->th_flags, 9042 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9043 "\02SYN\01FIN", ntohs(th->th_sum)); 9044 break; 9045 case IPPROTO_UDP: 9046 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9047 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9048 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9049 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9050 ntohs(uh->uh_sum)); 9051 break; 9052 case IPPROTO_ICMP: 9053 BCE_PRINTF("icmp:\n"); 9054 break; 9055 default: 9056 BCE_PRINTF("----: Other IP protocol.\n"); 9057 } 9058 break; 9059 case ETHERTYPE_IPV6: 9060 BCE_PRINTF("ipv6: No decode supported.\n"); 9061 break; 9062 case ETHERTYPE_ARP: 9063 BCE_PRINTF("-arp: "); 9064 ah = (struct arphdr *) (m->m_data + ehlen); 9065 switch (ntohs(ah->ar_op)) { 9066 case ARPOP_REVREQUEST: 9067 printf("reverse ARP request\n"); 9068 break; 9069 case ARPOP_REVREPLY: 9070 printf("reverse ARP reply\n"); 9071 break; 9072 case ARPOP_REQUEST: 9073 printf("ARP request\n"); 9074 break; 9075 case ARPOP_REPLY: 9076 printf("ARP reply\n"); 9077 break; 9078 default: 9079 printf("other ARP operation\n"); 9080 } 9081 break; 9082 default: 9083 BCE_PRINTF("----: Other protocol.\n"); 9084 } 9085 9086 BCE_PRINTF( 9087 "-----------------------------" 9088 "--------------" 9089 "-----------------------------\n"); 9090 } 9091 9092 9093 /****************************************************************************/ 9094 /* Prints out information about an mbuf. */ 9095 /* */ 9096 /* Returns: */ 9097 /* Nothing. */ 9098 /****************************************************************************/ 9099 static __attribute__ ((noinline)) void 9100 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9101 { 9102 struct mbuf *mp = m; 9103 9104 if (m == NULL) { 9105 BCE_PRINTF("mbuf: null pointer\n"); 9106 return; 9107 } 9108 9109 while (mp) { 9110 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9111 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9112 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9113 9114 if (mp->m_flags & M_PKTHDR) { 9115 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9116 "csum_flags = %b\n", mp->m_pkthdr.len, 9117 mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" 9118 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9119 "\22M_PROMISC\23M_NOFREE", 9120 mp->m_pkthdr.csum_flags, 9121 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 9122 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9123 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9124 "\14CSUM_PSEUDO_HDR"); 9125 } 9126 9127 if (mp->m_flags & M_EXT) { 9128 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9129 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9130 switch (mp->m_ext.ext_type) { 9131 case EXT_CLUSTER: 9132 printf("EXT_CLUSTER\n"); break; 9133 case EXT_SFBUF: 9134 printf("EXT_SFBUF\n"); break; 9135 case EXT_JUMBO9: 9136 printf("EXT_JUMBO9\n"); break; 9137 case EXT_JUMBO16: 9138 printf("EXT_JUMBO16\n"); break; 9139 case EXT_PACKET: 9140 printf("EXT_PACKET\n"); break; 9141 case EXT_MBUF: 9142 printf("EXT_MBUF\n"); break; 9143 case EXT_NET_DRV: 9144 printf("EXT_NET_DRV\n"); break; 9145 case EXT_MOD_TYPE: 9146 printf("EXT_MDD_TYPE\n"); break; 9147 case EXT_DISPOSABLE: 9148 printf("EXT_DISPOSABLE\n"); break; 9149 case EXT_EXTREF: 9150 printf("EXT_EXTREF\n"); break; 9151 default: 9152 printf("UNKNOWN\n"); 9153 } 9154 } 9155 9156 mp = mp->m_next; 9157 } 9158 } 9159 9160 9161 /****************************************************************************/ 9162 /* Prints out the mbufs in the TX mbuf chain. */ 9163 /* */ 9164 /* Returns: */ 9165 /* Nothing. */ 9166 /****************************************************************************/ 9167 static __attribute__ ((noinline)) void 9168 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9169 { 9170 struct mbuf *m; 9171 9172 BCE_PRINTF( 9173 "----------------------------" 9174 " tx mbuf data " 9175 "----------------------------\n"); 9176 9177 for (int i = 0; i < count; i++) { 9178 m = sc->tx_mbuf_ptr[chain_prod]; 9179 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9180 bce_dump_mbuf(sc, m); 9181 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9182 } 9183 9184 BCE_PRINTF( 9185 "----------------------------" 9186 "----------------" 9187 "----------------------------\n"); 9188 } 9189 9190 9191 /****************************************************************************/ 9192 /* Prints out the mbufs in the RX mbuf chain. */ 9193 /* */ 9194 /* Returns: */ 9195 /* Nothing. */ 9196 /****************************************************************************/ 9197 static __attribute__ ((noinline)) void 9198 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9199 { 9200 struct mbuf *m; 9201 9202 BCE_PRINTF( 9203 "----------------------------" 9204 " rx mbuf data " 9205 "----------------------------\n"); 9206 9207 for (int i = 0; i < count; i++) { 9208 m = sc->rx_mbuf_ptr[chain_prod]; 9209 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9210 bce_dump_mbuf(sc, m); 9211 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9212 } 9213 9214 9215 BCE_PRINTF( 9216 "----------------------------" 9217 "----------------" 9218 "----------------------------\n"); 9219 } 9220 9221 9222 #ifdef BCE_JUMBO_HDRSPLIT 9223 /****************************************************************************/ 9224 /* Prints out the mbufs in the mbuf page chain. */ 9225 /* */ 9226 /* Returns: */ 9227 /* Nothing. */ 9228 /****************************************************************************/ 9229 static __attribute__ ((noinline)) void 9230 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9231 { 9232 struct mbuf *m; 9233 9234 BCE_PRINTF( 9235 "----------------------------" 9236 " pg mbuf data " 9237 "----------------------------\n"); 9238 9239 for (int i = 0; i < count; i++) { 9240 m = sc->pg_mbuf_ptr[chain_prod]; 9241 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9242 bce_dump_mbuf(sc, m); 9243 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9244 } 9245 9246 9247 BCE_PRINTF( 9248 "----------------------------" 9249 "----------------" 9250 "----------------------------\n"); 9251 } 9252 #endif 9253 9254 9255 /****************************************************************************/ 9256 /* Prints out a tx_bd structure. */ 9257 /* */ 9258 /* Returns: */ 9259 /* Nothing. */ 9260 /****************************************************************************/ 9261 static __attribute__ ((noinline)) void 9262 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9263 { 9264 int i = 0; 9265 9266 if (idx > MAX_TX_BD) 9267 /* Index out of range. */ 9268 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9269 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9270 /* TX Chain page pointer. */ 9271 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9272 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9273 txbd->tx_bd_haddr_lo); 9274 else { 9275 /* Normal tx_bd entry. */ 9276 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9277 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9278 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9279 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9280 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9281 9282 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9283 if (i>0) 9284 printf("|"); 9285 printf("CONN_FAULT"); 9286 i++; 9287 } 9288 9289 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9290 if (i>0) 9291 printf("|"); 9292 printf("TCP_UDP_CKSUM"); 9293 i++; 9294 } 9295 9296 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9297 if (i>0) 9298 printf("|"); 9299 printf("IP_CKSUM"); 9300 i++; 9301 } 9302 9303 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9304 if (i>0) 9305 printf("|"); 9306 printf("VLAN"); 9307 i++; 9308 } 9309 9310 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9311 if (i>0) 9312 printf("|"); 9313 printf("COAL_NOW"); 9314 i++; 9315 } 9316 9317 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9318 if (i>0) 9319 printf("|"); 9320 printf("DONT_GEN_CRC"); 9321 i++; 9322 } 9323 9324 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9325 if (i>0) 9326 printf("|"); 9327 printf("START"); 9328 i++; 9329 } 9330 9331 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9332 if (i>0) 9333 printf("|"); 9334 printf("END"); 9335 i++; 9336 } 9337 9338 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9339 if (i>0) 9340 printf("|"); 9341 printf("LSO"); 9342 i++; 9343 } 9344 9345 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9346 if (i>0) 9347 printf("|"); 9348 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9349 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9350 } 9351 9352 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9353 if (i>0) 9354 printf("|"); 9355 printf("SW_FLAGS"); 9356 i++; 9357 } 9358 9359 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9360 if (i>0) 9361 printf("|"); 9362 printf("SNAP)"); 9363 } else { 9364 printf(")\n"); 9365 } 9366 } 9367 } 9368 9369 9370 /****************************************************************************/ 9371 /* Prints out a rx_bd structure. */ 9372 /* */ 9373 /* Returns: */ 9374 /* Nothing. */ 9375 /****************************************************************************/ 9376 static __attribute__ ((noinline)) void 9377 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9378 { 9379 if (idx > MAX_RX_BD) 9380 /* Index out of range. */ 9381 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9382 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9383 /* RX Chain page pointer. */ 9384 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9385 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9386 rxbd->rx_bd_haddr_lo); 9387 else 9388 /* Normal rx_bd entry. */ 9389 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9390 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9391 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9392 rxbd->rx_bd_flags); 9393 } 9394 9395 9396 #ifdef BCE_JUMBO_HDRSPLIT 9397 /****************************************************************************/ 9398 /* Prints out a rx_bd structure in the page chain. */ 9399 /* */ 9400 /* Returns: */ 9401 /* Nothing. */ 9402 /****************************************************************************/ 9403 static __attribute__ ((noinline)) void 9404 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9405 { 9406 if (idx > MAX_PG_BD) 9407 /* Index out of range. */ 9408 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9409 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9410 /* Page Chain page pointer. */ 9411 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9412 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9413 else 9414 /* Normal rx_bd entry. */ 9415 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9416 "flags = 0x%08X\n", idx, 9417 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9418 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9419 } 9420 #endif 9421 9422 9423 /****************************************************************************/ 9424 /* Prints out a l2_fhdr structure. */ 9425 /* */ 9426 /* Returns: */ 9427 /* Nothing. */ 9428 /****************************************************************************/ 9429 static __attribute__ ((noinline)) void 9430 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9431 { 9432 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9433 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9434 "tcp_udp_xsum = 0x%04X\n", idx, 9435 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9436 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9437 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9438 } 9439 9440 9441 /****************************************************************************/ 9442 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9443 /* */ 9444 /* Returns: */ 9445 /* Nothing. */ 9446 /****************************************************************************/ 9447 static __attribute__ ((noinline)) void 9448 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9449 { 9450 if (cid > TX_CID) { 9451 BCE_PRINTF(" Unknown CID\n"); 9452 return; 9453 } 9454 9455 BCE_PRINTF( 9456 "----------------------------" 9457 " CTX Data " 9458 "----------------------------\n"); 9459 9460 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9461 9462 if (cid == RX_CID) { 9463 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9464 "producer index\n", 9465 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9466 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 9467 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9468 BCE_L2CTX_RX_HOST_BSEQ)); 9469 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9470 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9471 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9472 "descriptor address\n", 9473 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9474 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9475 "descriptor address\n", 9476 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 9477 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 9478 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9479 BCE_L2CTX_RX_NX_BDIDX)); 9480 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 9481 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9482 BCE_L2CTX_RX_HOST_PG_BDIDX)); 9483 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 9484 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 9485 BCE_L2CTX_RX_PG_BUF_SIZE)); 9486 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 9487 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9488 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 9489 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 9490 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9491 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 9492 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 9493 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9494 BCE_L2CTX_RX_NX_PG_BDIDX)); 9495 } else if (cid == TX_CID) { 9496 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9497 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9498 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 9499 CTX_RD(sc, GET_CID_ADDR(cid), 9500 BCE_L2CTX_TX_TYPE_XI)); 9501 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 9502 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 9503 BCE_L2CTX_TX_CMD_TYPE_XI)); 9504 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 9505 "h/w buffer descriptor address\n", 9506 CTX_RD(sc, GET_CID_ADDR(cid), 9507 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 9508 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 9509 "h/w buffer descriptor address\n", 9510 CTX_RD(sc, GET_CID_ADDR(cid), 9511 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 9512 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 9513 "host producer index\n", 9514 CTX_RD(sc, GET_CID_ADDR(cid), 9515 BCE_L2CTX_TX_HOST_BIDX_XI)); 9516 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 9517 "host byte sequence\n", 9518 CTX_RD(sc, GET_CID_ADDR(cid), 9519 BCE_L2CTX_TX_HOST_BSEQ_XI)); 9520 } else { 9521 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 9522 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 9523 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 9524 CTX_RD(sc, GET_CID_ADDR(cid), 9525 BCE_L2CTX_TX_CMD_TYPE)); 9526 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 9527 "h/w buffer descriptor address\n", 9528 CTX_RD(sc, GET_CID_ADDR(cid), 9529 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 9530 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 9531 "h/w buffer descriptor address\n", 9532 CTX_RD(sc, GET_CID_ADDR(cid), 9533 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 9534 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 9535 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9536 BCE_L2CTX_TX_HOST_BIDX)); 9537 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 9538 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9539 BCE_L2CTX_TX_HOST_BSEQ)); 9540 } 9541 } 9542 9543 BCE_PRINTF( 9544 "----------------------------" 9545 " Raw CTX " 9546 "----------------------------\n"); 9547 9548 for (int i = 0x0; i < 0x300; i += 0x10) { 9549 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 9550 CTX_RD(sc, GET_CID_ADDR(cid), i), 9551 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 9552 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 9553 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 9554 } 9555 9556 9557 BCE_PRINTF( 9558 "----------------------------" 9559 "----------------" 9560 "----------------------------\n"); 9561 } 9562 9563 9564 /****************************************************************************/ 9565 /* Prints out the FTQ data. */ 9566 /* */ 9567 /* Returns: */ 9568 /* Nothing. */ 9569 /****************************************************************************/ 9570 static __attribute__ ((noinline)) void 9571 bce_dump_ftqs(struct bce_softc *sc) 9572 { 9573 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 9574 9575 BCE_PRINTF( 9576 "----------------------------" 9577 " FTQ Data " 9578 "----------------------------\n"); 9579 9580 BCE_PRINTF(" FTQ Command Control Depth_Now " 9581 "Max_Depth Valid_Cnt \n"); 9582 BCE_PRINTF(" ------- ---------- ---------- ---------- " 9583 "---------- ----------\n"); 9584 9585 /* Setup the generic statistic counters for the FTQ valid count. */ 9586 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 9587 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 9588 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 9589 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 9590 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9591 9592 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 9593 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 9594 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 9595 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 9596 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 9597 9598 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 9599 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 9600 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 9601 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 9602 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 9603 9604 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 9605 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 9606 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 9607 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 9608 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 9609 9610 /* Input queue to the Receive Lookup state machine */ 9611 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 9612 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 9613 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 9614 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 9615 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 9616 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9617 cmd, ctl, cur_depth, max_depth, valid_cnt); 9618 9619 /* Input queue to the Receive Processor */ 9620 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 9621 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 9622 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 9623 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 9624 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 9625 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9626 cmd, ctl, cur_depth, max_depth, valid_cnt); 9627 9628 /* Input queue to the Recevie Processor */ 9629 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 9630 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 9631 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 9632 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 9633 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 9634 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9635 cmd, ctl, cur_depth, max_depth, valid_cnt); 9636 9637 /* Input queue to the Receive Virtual to Physical state machine */ 9638 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 9639 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 9640 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 9641 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 9642 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 9643 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9644 cmd, ctl, cur_depth, max_depth, valid_cnt); 9645 9646 /* Input queue to the Recevie Virtual to Physical state machine */ 9647 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 9648 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 9649 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 9650 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 9651 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 9652 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9653 cmd, ctl, cur_depth, max_depth, valid_cnt); 9654 9655 /* Input queue to the Receive Virtual to Physical state machine */ 9656 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 9657 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 9658 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 9659 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 9660 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 9661 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9662 cmd, ctl, cur_depth, max_depth, valid_cnt); 9663 9664 /* Input queue to the Receive DMA state machine */ 9665 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 9666 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 9667 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 9668 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 9669 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 9670 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9671 cmd, ctl, cur_depth, max_depth, valid_cnt); 9672 9673 /* Input queue to the Transmit Scheduler state machine */ 9674 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 9675 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 9676 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 9677 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 9678 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 9679 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9680 cmd, ctl, cur_depth, max_depth, valid_cnt); 9681 9682 /* Input queue to the Transmit Buffer Descriptor state machine */ 9683 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 9684 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 9685 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 9686 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 9687 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 9688 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9689 cmd, ctl, cur_depth, max_depth, valid_cnt); 9690 9691 /* Input queue to the Transmit Processor */ 9692 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 9693 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 9694 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 9695 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 9696 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 9697 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9698 cmd, ctl, cur_depth, max_depth, valid_cnt); 9699 9700 /* Input queue to the Transmit DMA state machine */ 9701 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 9702 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 9703 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 9704 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 9705 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 9706 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9707 cmd, ctl, cur_depth, max_depth, valid_cnt); 9708 9709 /* Input queue to the Transmit Patch-Up Processor */ 9710 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 9711 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 9712 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 9713 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 9714 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 9715 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9716 cmd, ctl, cur_depth, max_depth, valid_cnt); 9717 9718 /* Input queue to the Transmit Assembler state machine */ 9719 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 9720 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 9721 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 9722 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 9723 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 9724 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9725 cmd, ctl, cur_depth, max_depth, valid_cnt); 9726 9727 /* Input queue to the Completion Processor */ 9728 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 9729 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 9730 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 9731 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 9732 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 9733 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9734 cmd, ctl, cur_depth, max_depth, valid_cnt); 9735 9736 /* Input queue to the Completion Processor */ 9737 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 9738 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 9739 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 9740 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 9741 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 9742 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9743 cmd, ctl, cur_depth, max_depth, valid_cnt); 9744 9745 /* Input queue to the Completion Processor */ 9746 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 9747 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 9748 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 9749 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 9750 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 9751 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9752 cmd, ctl, cur_depth, max_depth, valid_cnt); 9753 9754 /* Setup the generic statistic counters for the FTQ valid count. */ 9755 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 9756 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 9757 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 9758 9759 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9760 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 9761 val = val | 9762 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 9763 24); 9764 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9765 9766 /* Input queue to the Management Control Processor */ 9767 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 9768 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 9769 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9770 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9771 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 9772 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9773 cmd, ctl, cur_depth, max_depth, valid_cnt); 9774 9775 /* Input queue to the Command Processor */ 9776 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 9777 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 9778 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9779 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9780 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 9781 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9782 cmd, ctl, cur_depth, max_depth, valid_cnt); 9783 9784 /* Input queue to the Completion Scheduler state machine */ 9785 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 9786 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 9787 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 9788 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 9789 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 9790 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9791 cmd, ctl, cur_depth, max_depth, valid_cnt); 9792 9793 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9794 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9795 /* Input queue to the RV2P Command Scheduler */ 9796 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 9797 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 9798 cur_depth = (ctl & 0xFFC00000) >> 22; 9799 max_depth = (ctl & 0x003FF000) >> 12; 9800 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 9801 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9802 cmd, ctl, cur_depth, max_depth, valid_cnt); 9803 } 9804 9805 BCE_PRINTF( 9806 "----------------------------" 9807 "----------------" 9808 "----------------------------\n"); 9809 } 9810 9811 9812 /****************************************************************************/ 9813 /* Prints out the TX chain. */ 9814 /* */ 9815 /* Returns: */ 9816 /* Nothing. */ 9817 /****************************************************************************/ 9818 static __attribute__ ((noinline)) void 9819 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 9820 { 9821 struct tx_bd *txbd; 9822 9823 /* First some info about the tx_bd chain structure. */ 9824 BCE_PRINTF( 9825 "----------------------------" 9826 " tx_bd chain " 9827 "----------------------------\n"); 9828 9829 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 9830 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 9831 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 9832 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 9833 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 9834 9835 BCE_PRINTF( 9836 "----------------------------" 9837 " tx_bd data " 9838 "----------------------------\n"); 9839 9840 /* Now print out a decoded list of TX buffer descriptors. */ 9841 for (int i = 0; i < count; i++) { 9842 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 9843 bce_dump_txbd(sc, tx_prod, txbd); 9844 tx_prod++; 9845 } 9846 9847 BCE_PRINTF( 9848 "----------------------------" 9849 "----------------" 9850 "----------------------------\n"); 9851 } 9852 9853 9854 /****************************************************************************/ 9855 /* Prints out the RX chain. */ 9856 /* */ 9857 /* Returns: */ 9858 /* Nothing. */ 9859 /****************************************************************************/ 9860 static __attribute__ ((noinline)) void 9861 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 9862 { 9863 struct rx_bd *rxbd; 9864 9865 /* First some info about the rx_bd chain structure. */ 9866 BCE_PRINTF( 9867 "----------------------------" 9868 " rx_bd chain " 9869 "----------------------------\n"); 9870 9871 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 9872 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 9873 9874 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9875 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 9876 9877 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 9878 9879 BCE_PRINTF( 9880 "----------------------------" 9881 " rx_bd data " 9882 "----------------------------\n"); 9883 9884 /* Now print out the rx_bd's themselves. */ 9885 for (int i = 0; i < count; i++) { 9886 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 9887 bce_dump_rxbd(sc, rx_prod, rxbd); 9888 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 9889 } 9890 9891 BCE_PRINTF( 9892 "----------------------------" 9893 "----------------" 9894 "----------------------------\n"); 9895 } 9896 9897 9898 #ifdef BCE_JUMBO_HDRSPLIT 9899 /****************************************************************************/ 9900 /* Prints out the page chain. */ 9901 /* */ 9902 /* Returns: */ 9903 /* Nothing. */ 9904 /****************************************************************************/ 9905 static __attribute__ ((noinline)) void 9906 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 9907 { 9908 struct rx_bd *pgbd; 9909 9910 /* First some info about the page chain structure. */ 9911 BCE_PRINTF( 9912 "----------------------------" 9913 " page chain " 9914 "----------------------------\n"); 9915 9916 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 9917 (u32) BCM_PAGE_SIZE, (u32) PG_PAGES); 9918 9919 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9920 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 9921 9922 BCE_PRINTF("total rx_bd = 0x%08X, max_pg_bd = 0x%08X\n", 9923 (u32) TOTAL_PG_BD, (u32) MAX_PG_BD); 9924 9925 BCE_PRINTF( 9926 "----------------------------" 9927 " page data " 9928 "----------------------------\n"); 9929 9930 /* Now print out the rx_bd's themselves. */ 9931 for (int i = 0; i < count; i++) { 9932 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 9933 bce_dump_pgbd(sc, pg_prod, pgbd); 9934 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 9935 } 9936 9937 BCE_PRINTF( 9938 "----------------------------" 9939 "----------------" 9940 "----------------------------\n"); 9941 } 9942 #endif 9943 9944 9945 #define BCE_PRINT_RX_CONS(arg) \ 9946 if (sblk->status_rx_quick_consumer_index##arg) \ 9947 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 9948 sblk->status_rx_quick_consumer_index##arg, (u16) \ 9949 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 9950 arg); 9951 9952 9953 #define BCE_PRINT_TX_CONS(arg) \ 9954 if (sblk->status_tx_quick_consumer_index##arg) \ 9955 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 9956 sblk->status_tx_quick_consumer_index##arg, (u16) \ 9957 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 9958 arg); 9959 9960 /****************************************************************************/ 9961 /* Prints out the status block from host memory. */ 9962 /* */ 9963 /* Returns: */ 9964 /* Nothing. */ 9965 /****************************************************************************/ 9966 static __attribute__ ((noinline)) void 9967 bce_dump_status_block(struct bce_softc *sc) 9968 { 9969 struct status_block *sblk; 9970 9971 sblk = sc->status_block; 9972 9973 BCE_PRINTF( 9974 "----------------------------" 9975 " Status Block " 9976 "----------------------------\n"); 9977 9978 /* Theses indices are used for normal L2 drivers. */ 9979 BCE_PRINTF(" 0x%08X - attn_bits\n", 9980 sblk->status_attn_bits); 9981 9982 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 9983 sblk->status_attn_bits_ack); 9984 9985 BCE_PRINT_RX_CONS(0); 9986 BCE_PRINT_TX_CONS(0) 9987 9988 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 9989 9990 /* Theses indices are not used for normal L2 drivers. */ 9991 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 9992 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 9993 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 9994 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 9995 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 9996 9997 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 9998 9999 if (sblk->status_completion_producer_index || 10000 sblk->status_cmd_consumer_index) 10001 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10002 sblk->status_completion_producer_index, 10003 sblk->status_cmd_consumer_index); 10004 10005 BCE_PRINTF( 10006 "----------------------------" 10007 "----------------" 10008 "----------------------------\n"); 10009 } 10010 10011 10012 #define BCE_PRINT_64BIT_STAT(arg) \ 10013 if (sblk->arg##_lo || sblk->arg##_hi) \ 10014 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10015 sblk->arg##_lo, #arg); 10016 10017 #define BCE_PRINT_32BIT_STAT(arg) \ 10018 if (sblk->arg) \ 10019 BCE_PRINTF(" 0x%08X : %s\n", \ 10020 sblk->arg, #arg); 10021 10022 /****************************************************************************/ 10023 /* Prints out the statistics block from host memory. */ 10024 /* */ 10025 /* Returns: */ 10026 /* Nothing. */ 10027 /****************************************************************************/ 10028 static __attribute__ ((noinline)) void 10029 bce_dump_stats_block(struct bce_softc *sc) 10030 { 10031 struct statistics_block *sblk; 10032 10033 sblk = sc->stats_block; 10034 10035 BCE_PRINTF( 10036 "---------------" 10037 " Stats Block (All Stats Not Shown Are 0) " 10038 "---------------\n"); 10039 10040 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10041 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10042 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10043 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10044 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10045 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10046 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10047 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10048 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10049 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10050 BCE_PRINT_32BIT_STAT( 10051 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10052 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10053 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10054 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10055 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10056 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10057 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10058 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10059 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10060 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10061 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10062 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10063 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10064 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10065 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10066 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10067 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10068 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10069 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10070 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10071 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10072 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10073 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10074 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10075 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10076 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10077 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10078 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10079 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10080 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10081 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10082 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10083 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10084 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10085 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10086 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10087 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10088 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10089 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10090 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10091 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10092 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10093 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10094 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10095 10096 BCE_PRINTF( 10097 "----------------------------" 10098 "----------------" 10099 "----------------------------\n"); 10100 } 10101 10102 10103 /****************************************************************************/ 10104 /* Prints out a summary of the driver state. */ 10105 /* */ 10106 /* Returns: */ 10107 /* Nothing. */ 10108 /****************************************************************************/ 10109 static __attribute__ ((noinline)) void 10110 bce_dump_driver_state(struct bce_softc *sc) 10111 { 10112 u32 val_hi, val_lo; 10113 10114 BCE_PRINTF( 10115 "-----------------------------" 10116 " Driver State " 10117 "-----------------------------\n"); 10118 10119 val_hi = BCE_ADDR_HI(sc); 10120 val_lo = BCE_ADDR_LO(sc); 10121 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10122 "address\n", val_hi, val_lo); 10123 10124 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10125 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10126 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10127 "address\n", val_hi, val_lo); 10128 10129 val_hi = BCE_ADDR_HI(sc->status_block); 10130 val_lo = BCE_ADDR_LO(sc->status_block); 10131 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10132 "virtual address\n", val_hi, val_lo); 10133 10134 val_hi = BCE_ADDR_HI(sc->stats_block); 10135 val_lo = BCE_ADDR_LO(sc->stats_block); 10136 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10137 "virtual address\n", val_hi, val_lo); 10138 10139 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10140 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10141 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10142 "virtual adddress\n", val_hi, val_lo); 10143 10144 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10145 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10146 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10147 "virtual address\n", val_hi, val_lo); 10148 10149 #ifdef BCE_JUMBO_HDRSPLIT 10150 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10151 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10152 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10153 "virtual address\n", val_hi, val_lo); 10154 #endif 10155 10156 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10157 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10158 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10159 "virtual address\n", val_hi, val_lo); 10160 10161 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10162 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10163 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10164 "virtual address\n", val_hi, val_lo); 10165 10166 #ifdef BCE_JUMBO_HDRSPLIT 10167 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10168 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10169 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10170 "virtual address\n", val_hi, val_lo); 10171 #endif 10172 10173 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) " 10174 "h/w intrs\n", sc->interrupts_generated); 10175 10176 BCE_PRINTF(" 0x%08X - (sc->interrupts_rx) " 10177 "rx interrupts handled\n", sc->interrupts_rx); 10178 10179 BCE_PRINTF(" 0x%08X - (sc->interrupts_tx) " 10180 "tx interrupts handled\n", sc->interrupts_tx); 10181 10182 BCE_PRINTF(" 0x%08X - (sc->phy_interrupts) " 10183 "phy interrupts handled\n", sc->phy_interrupts); 10184 10185 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10186 "status block index\n", sc->last_status_idx); 10187 10188 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10189 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10190 10191 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10192 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10193 10194 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10195 "byte seq index\n", sc->tx_prod_bseq); 10196 10197 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10198 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10199 10200 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10201 "tx_bd's\n", sc->used_tx_bd); 10202 10203 BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi " 10204 "watermark\n", sc->tx_hi_watermark, sc->max_tx_bd); 10205 10206 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10207 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10208 10209 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10210 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10211 10212 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10213 "byte seq index\n", sc->rx_prod_bseq); 10214 10215 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10216 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10217 10218 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10219 "rx_bd's\n", sc->free_rx_bd); 10220 10221 #ifdef BCE_JUMBO_HDRSPLIT 10222 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10223 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10224 10225 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10226 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10227 10228 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10229 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10230 10231 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10232 "rx_bd's\n", sc->free_pg_bd); 10233 10234 BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low " 10235 "watermark\n", sc->pg_low_watermark, sc->max_pg_bd); 10236 #endif 10237 10238 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10239 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10240 10241 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10242 "bce mac flags\n", sc->bce_flags); 10243 10244 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10245 "bce phy flags\n", sc->bce_phy_flags); 10246 10247 BCE_PRINTF( 10248 "----------------------------" 10249 "----------------" 10250 "----------------------------\n"); 10251 } 10252 10253 10254 /****************************************************************************/ 10255 /* Prints out the hardware state through a summary of important register, */ 10256 /* followed by a complete register dump. */ 10257 /* */ 10258 /* Returns: */ 10259 /* Nothing. */ 10260 /****************************************************************************/ 10261 static __attribute__ ((noinline)) void 10262 bce_dump_hw_state(struct bce_softc *sc) 10263 { 10264 u32 val; 10265 10266 BCE_PRINTF( 10267 "----------------------------" 10268 " Hardware State " 10269 "----------------------------\n"); 10270 10271 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10272 10273 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10274 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10275 val, BCE_MISC_ENABLE_STATUS_BITS); 10276 10277 val = REG_RD(sc, BCE_DMA_STATUS); 10278 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10279 val, BCE_DMA_STATUS); 10280 10281 val = REG_RD(sc, BCE_CTX_STATUS); 10282 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10283 val, BCE_CTX_STATUS); 10284 10285 val = REG_RD(sc, BCE_EMAC_STATUS); 10286 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10287 val, BCE_EMAC_STATUS); 10288 10289 val = REG_RD(sc, BCE_RPM_STATUS); 10290 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10291 val, BCE_RPM_STATUS); 10292 10293 /* ToDo: Create a #define for this constant. */ 10294 val = REG_RD(sc, 0x2004); 10295 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10296 val, 0x2004); 10297 10298 val = REG_RD(sc, BCE_RV2P_STATUS); 10299 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10300 val, BCE_RV2P_STATUS); 10301 10302 /* ToDo: Create a #define for this constant. */ 10303 val = REG_RD(sc, 0x2c04); 10304 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10305 val, 0x2c04); 10306 10307 val = REG_RD(sc, BCE_TBDR_STATUS); 10308 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10309 val, BCE_TBDR_STATUS); 10310 10311 val = REG_RD(sc, BCE_TDMA_STATUS); 10312 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10313 val, BCE_TDMA_STATUS); 10314 10315 val = REG_RD(sc, BCE_HC_STATUS); 10316 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10317 val, BCE_HC_STATUS); 10318 10319 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10320 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10321 val, BCE_TXP_CPU_STATE); 10322 10323 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10324 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10325 val, BCE_TPAT_CPU_STATE); 10326 10327 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10328 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10329 val, BCE_RXP_CPU_STATE); 10330 10331 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10332 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10333 val, BCE_COM_CPU_STATE); 10334 10335 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10336 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10337 val, BCE_MCP_CPU_STATE); 10338 10339 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10340 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10341 val, BCE_CP_CPU_STATE); 10342 10343 BCE_PRINTF( 10344 "----------------------------" 10345 "----------------" 10346 "----------------------------\n"); 10347 10348 BCE_PRINTF( 10349 "----------------------------" 10350 " Register Dump " 10351 "----------------------------\n"); 10352 10353 for (int i = 0x400; i < 0x8000; i += 0x10) { 10354 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10355 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10356 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10357 } 10358 10359 BCE_PRINTF( 10360 "----------------------------" 10361 "----------------" 10362 "----------------------------\n"); 10363 } 10364 10365 10366 /****************************************************************************/ 10367 /* Prints out the mailbox queue registers. */ 10368 /* */ 10369 /* Returns: */ 10370 /* Nothing. */ 10371 /****************************************************************************/ 10372 static __attribute__ ((noinline)) void 10373 bce_dump_mq_regs(struct bce_softc *sc) 10374 { 10375 BCE_PRINTF( 10376 "----------------------------" 10377 " MQ Regs " 10378 "----------------------------\n"); 10379 10380 BCE_PRINTF( 10381 "----------------------------" 10382 "----------------" 10383 "----------------------------\n"); 10384 10385 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10386 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10387 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10388 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10389 } 10390 10391 BCE_PRINTF( 10392 "----------------------------" 10393 "----------------" 10394 "----------------------------\n"); 10395 } 10396 10397 10398 /****************************************************************************/ 10399 /* Prints out the bootcode state. */ 10400 /* */ 10401 /* Returns: */ 10402 /* Nothing. */ 10403 /****************************************************************************/ 10404 static __attribute__ ((noinline)) void 10405 bce_dump_bc_state(struct bce_softc *sc) 10406 { 10407 u32 val; 10408 10409 BCE_PRINTF( 10410 "----------------------------" 10411 " Bootcode State " 10412 "----------------------------\n"); 10413 10414 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10415 10416 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10417 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10418 val, BCE_BC_RESET_TYPE); 10419 10420 val = bce_shmem_rd(sc, BCE_BC_STATE); 10421 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10422 val, BCE_BC_STATE); 10423 10424 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10425 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10426 val, BCE_BC_STATE_CONDITION); 10427 10428 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10429 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10430 val, BCE_BC_STATE_DEBUG_CMD); 10431 10432 BCE_PRINTF( 10433 "----------------------------" 10434 "----------------" 10435 "----------------------------\n"); 10436 } 10437 10438 10439 /****************************************************************************/ 10440 /* Prints out the TXP processor state. */ 10441 /* */ 10442 /* Returns: */ 10443 /* Nothing. */ 10444 /****************************************************************************/ 10445 static __attribute__ ((noinline)) void 10446 bce_dump_txp_state(struct bce_softc *sc, int regs) 10447 { 10448 u32 val; 10449 u32 fw_version[3]; 10450 10451 BCE_PRINTF( 10452 "----------------------------" 10453 " TXP State " 10454 "----------------------------\n"); 10455 10456 for (int i = 0; i < 3; i++) 10457 fw_version[i] = htonl(REG_RD_IND(sc, 10458 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10459 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10460 10461 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10462 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 10463 val, BCE_TXP_CPU_MODE); 10464 10465 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10466 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10467 val, BCE_TXP_CPU_STATE); 10468 10469 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10470 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 10471 val, BCE_TXP_CPU_EVENT_MASK); 10472 10473 if (regs) { 10474 BCE_PRINTF( 10475 "----------------------------" 10476 " Register Dump " 10477 "----------------------------\n"); 10478 10479 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10480 /* Skip the big blank spaces */ 10481 if (i < 0x454000 && i > 0x5ffff) 10482 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10483 "0x%08X 0x%08X\n", i, 10484 REG_RD_IND(sc, i), 10485 REG_RD_IND(sc, i + 0x4), 10486 REG_RD_IND(sc, i + 0x8), 10487 REG_RD_IND(sc, i + 0xC)); 10488 } 10489 } 10490 10491 BCE_PRINTF( 10492 "----------------------------" 10493 "----------------" 10494 "----------------------------\n"); 10495 } 10496 10497 10498 /****************************************************************************/ 10499 /* Prints out the RXP processor state. */ 10500 /* */ 10501 /* Returns: */ 10502 /* Nothing. */ 10503 /****************************************************************************/ 10504 static __attribute__ ((noinline)) void 10505 bce_dump_rxp_state(struct bce_softc *sc, int regs) 10506 { 10507 u32 val; 10508 u32 fw_version[3]; 10509 10510 BCE_PRINTF( 10511 "----------------------------" 10512 " RXP State " 10513 "----------------------------\n"); 10514 10515 for (int i = 0; i < 3; i++) 10516 fw_version[i] = htonl(REG_RD_IND(sc, 10517 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10518 10519 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10520 10521 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10522 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 10523 val, BCE_RXP_CPU_MODE); 10524 10525 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10526 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10527 val, BCE_RXP_CPU_STATE); 10528 10529 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10530 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 10531 val, BCE_RXP_CPU_EVENT_MASK); 10532 10533 if (regs) { 10534 BCE_PRINTF( 10535 "----------------------------" 10536 " Register Dump " 10537 "----------------------------\n"); 10538 10539 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 10540 /* Skip the big blank sapces */ 10541 if (i < 0xc5400 && i > 0xdffff) 10542 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10543 "0x%08X 0x%08X\n", i, 10544 REG_RD_IND(sc, i), 10545 REG_RD_IND(sc, i + 0x4), 10546 REG_RD_IND(sc, i + 0x8), 10547 REG_RD_IND(sc, i + 0xC)); 10548 } 10549 } 10550 10551 BCE_PRINTF( 10552 "----------------------------" 10553 "----------------" 10554 "----------------------------\n"); 10555 } 10556 10557 10558 /****************************************************************************/ 10559 /* Prints out the TPAT processor state. */ 10560 /* */ 10561 /* Returns: */ 10562 /* Nothing. */ 10563 /****************************************************************************/ 10564 static __attribute__ ((noinline)) void 10565 bce_dump_tpat_state(struct bce_softc *sc, int regs) 10566 { 10567 u32 val; 10568 u32 fw_version[3]; 10569 10570 BCE_PRINTF( 10571 "----------------------------" 10572 " TPAT State " 10573 "----------------------------\n"); 10574 10575 for (int i = 0; i < 3; i++) 10576 fw_version[i] = htonl(REG_RD_IND(sc, 10577 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 10578 10579 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10580 10581 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 10582 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 10583 val, BCE_TPAT_CPU_MODE); 10584 10585 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10586 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10587 val, BCE_TPAT_CPU_STATE); 10588 10589 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 10590 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 10591 val, BCE_TPAT_CPU_EVENT_MASK); 10592 10593 if (regs) { 10594 BCE_PRINTF( 10595 "----------------------------" 10596 " Register Dump " 10597 "----------------------------\n"); 10598 10599 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 10600 /* Skip the big blank spaces */ 10601 if (i < 0x854000 && i > 0x9ffff) 10602 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10603 "0x%08X 0x%08X\n", i, 10604 REG_RD_IND(sc, i), 10605 REG_RD_IND(sc, i + 0x4), 10606 REG_RD_IND(sc, i + 0x8), 10607 REG_RD_IND(sc, i + 0xC)); 10608 } 10609 } 10610 10611 BCE_PRINTF( 10612 "----------------------------" 10613 "----------------" 10614 "----------------------------\n"); 10615 } 10616 10617 10618 /****************************************************************************/ 10619 /* Prints out the Command Procesor (CP) state. */ 10620 /* */ 10621 /* Returns: */ 10622 /* Nothing. */ 10623 /****************************************************************************/ 10624 static __attribute__ ((noinline)) void 10625 bce_dump_cp_state(struct bce_softc *sc, int regs) 10626 { 10627 u32 val; 10628 u32 fw_version[3]; 10629 10630 BCE_PRINTF( 10631 "----------------------------" 10632 " CP State " 10633 "----------------------------\n"); 10634 10635 for (int i = 0; i < 3; i++) 10636 fw_version[i] = htonl(REG_RD_IND(sc, 10637 (BCE_CP_SCRATCH + 0x10 + i * 4))); 10638 10639 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10640 10641 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 10642 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 10643 val, BCE_CP_CPU_MODE); 10644 10645 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10646 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10647 val, BCE_CP_CPU_STATE); 10648 10649 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 10650 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 10651 BCE_CP_CPU_EVENT_MASK); 10652 10653 if (regs) { 10654 BCE_PRINTF( 10655 "----------------------------" 10656 " Register Dump " 10657 "----------------------------\n"); 10658 10659 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 10660 /* Skip the big blank spaces */ 10661 if (i < 0x185400 && i > 0x19ffff) 10662 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10663 "0x%08X 0x%08X\n", i, 10664 REG_RD_IND(sc, i), 10665 REG_RD_IND(sc, i + 0x4), 10666 REG_RD_IND(sc, i + 0x8), 10667 REG_RD_IND(sc, i + 0xC)); 10668 } 10669 } 10670 10671 BCE_PRINTF( 10672 "----------------------------" 10673 "----------------" 10674 "----------------------------\n"); 10675 } 10676 10677 10678 /****************************************************************************/ 10679 /* Prints out the Completion Procesor (COM) state. */ 10680 /* */ 10681 /* Returns: */ 10682 /* Nothing. */ 10683 /****************************************************************************/ 10684 static __attribute__ ((noinline)) void 10685 bce_dump_com_state(struct bce_softc *sc, int regs) 10686 { 10687 u32 val; 10688 u32 fw_version[4]; 10689 10690 BCE_PRINTF( 10691 "----------------------------" 10692 " COM State " 10693 "----------------------------\n"); 10694 10695 for (int i = 0; i < 3; i++) 10696 fw_version[i] = htonl(REG_RD_IND(sc, 10697 (BCE_COM_SCRATCH + 0x10 + i * 4))); 10698 10699 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10700 10701 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 10702 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 10703 val, BCE_COM_CPU_MODE); 10704 10705 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10706 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10707 val, BCE_COM_CPU_STATE); 10708 10709 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 10710 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 10711 BCE_COM_CPU_EVENT_MASK); 10712 10713 if (regs) { 10714 BCE_PRINTF( 10715 "----------------------------" 10716 " Register Dump " 10717 "----------------------------\n"); 10718 10719 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 10720 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10721 "0x%08X 0x%08X\n", i, 10722 REG_RD_IND(sc, i), 10723 REG_RD_IND(sc, i + 0x4), 10724 REG_RD_IND(sc, i + 0x8), 10725 REG_RD_IND(sc, i + 0xC)); 10726 } 10727 } 10728 10729 BCE_PRINTF( 10730 "----------------------------" 10731 "----------------" 10732 "----------------------------\n"); 10733 } 10734 10735 10736 /****************************************************************************/ 10737 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 10738 /* */ 10739 /* Returns: */ 10740 /* Nothing. */ 10741 /****************************************************************************/ 10742 static __attribute__ ((noinline)) void 10743 bce_dump_rv2p_state(struct bce_softc *sc) 10744 { 10745 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 10746 10747 BCE_PRINTF( 10748 "----------------------------" 10749 " RV2P State " 10750 "----------------------------\n"); 10751 10752 /* Stall the RV2P processors. */ 10753 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 10754 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 10755 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 10756 10757 /* Read the firmware version. */ 10758 val = 0x00000001; 10759 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 10760 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 10761 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 10762 BCE_RV2P_INSTR_HIGH_HIGH; 10763 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 10764 fw_ver_high, fw_ver_low); 10765 10766 val = 0x00000001; 10767 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 10768 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 10769 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 10770 BCE_RV2P_INSTR_HIGH_HIGH; 10771 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 10772 fw_ver_high, fw_ver_low); 10773 10774 /* Resume the RV2P processors. */ 10775 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 10776 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 10777 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 10778 10779 /* Fetch the program counter value. */ 10780 val = 0x68007800; 10781 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 10782 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 10783 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 10784 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 10785 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 10786 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 10787 10788 /* Fetch the program counter value again to see if it is advancing. */ 10789 val = 0x68007800; 10790 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 10791 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 10792 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 10793 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 10794 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 10795 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 10796 10797 BCE_PRINTF( 10798 "----------------------------" 10799 "----------------" 10800 "----------------------------\n"); 10801 } 10802 10803 10804 /****************************************************************************/ 10805 /* Prints out the driver state and then enters the debugger. */ 10806 /* */ 10807 /* Returns: */ 10808 /* Nothing. */ 10809 /****************************************************************************/ 10810 static __attribute__ ((noinline)) void 10811 bce_breakpoint(struct bce_softc *sc) 10812 { 10813 10814 /* 10815 * Unreachable code to silence compiler warnings 10816 * about unused functions. 10817 */ 10818 if (0) { 10819 bce_freeze_controller(sc); 10820 bce_unfreeze_controller(sc); 10821 bce_dump_enet(sc, NULL); 10822 bce_dump_txbd(sc, 0, NULL); 10823 bce_dump_rxbd(sc, 0, NULL); 10824 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 10825 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 10826 bce_dump_l2fhdr(sc, 0, NULL); 10827 bce_dump_ctx(sc, RX_CID); 10828 bce_dump_ftqs(sc); 10829 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 10830 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD); 10831 bce_dump_status_block(sc); 10832 bce_dump_stats_block(sc); 10833 bce_dump_driver_state(sc); 10834 bce_dump_hw_state(sc); 10835 bce_dump_bc_state(sc); 10836 bce_dump_txp_state(sc, 0); 10837 bce_dump_rxp_state(sc, 0); 10838 bce_dump_tpat_state(sc, 0); 10839 bce_dump_cp_state(sc, 0); 10840 bce_dump_com_state(sc, 0); 10841 bce_dump_rv2p_state(sc); 10842 10843 #ifdef BCE_JUMBO_HDRSPLIT 10844 bce_dump_pgbd(sc, 0, NULL); 10845 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD); 10846 bce_dump_pg_chain(sc, 0, USABLE_PG_BD); 10847 #endif 10848 } 10849 10850 bce_dump_status_block(sc); 10851 bce_dump_driver_state(sc); 10852 10853 /* Call the debugger. */ 10854 breakpoint(); 10855 10856 return; 10857 } 10858 #endif 10859 10860