1 /*- 2 * Copyright (c) 2006-2007 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5708C B1, B2 38 * 39 * The following controllers are not supported by this driver: 40 * BCM5706C A0, A1 41 * BCM5706S A0, A1, A2, A3 42 * BCM5708C A0, B0 43 * BCM5708S A0, B0, B1, B2 44 */ 45 46 #include "opt_bce.h" 47 48 #include <dev/bce/if_bcereg.h> 49 #include <dev/bce/if_bcefw.h> 50 51 /****************************************************************************/ 52 /* BCE Debug Options */ 53 /****************************************************************************/ 54 #ifdef BCE_DEBUG 55 u32 bce_debug = BCE_WARN; 56 57 /* 0 = Never */ 58 /* 1 = 1 in 2,147,483,648 */ 59 /* 256 = 1 in 8,388,608 */ 60 /* 2048 = 1 in 1,048,576 */ 61 /* 65536 = 1 in 32,768 */ 62 /* 1048576 = 1 in 2,048 */ 63 /* 268435456 = 1 in 8 */ 64 /* 536870912 = 1 in 4 */ 65 /* 1073741824 = 1 in 2 */ 66 67 /* Controls how often the l2_fhdr frame error check will fail. */ 68 int bce_debug_l2fhdr_status_check = 0; 69 70 /* Controls how often the unexpected attention check will fail. */ 71 int bce_debug_unexpected_attention = 0; 72 73 /* Controls how often to simulate an mbuf allocation failure. */ 74 int bce_debug_mbuf_allocation_failure = 0; 75 76 /* Controls how often to simulate a DMA mapping failure. */ 77 int bce_debug_dma_map_addr_failure = 0; 78 79 /* Controls how often to simulate a bootcode failure. */ 80 int bce_debug_bootcode_running_failure = 0; 81 #endif 82 83 84 /****************************************************************************/ 85 /* PCI Device ID Table */ 86 /* */ 87 /* Used by bce_probe() to identify the devices supported by this driver. */ 88 /****************************************************************************/ 89 #define BCE_DEVDESC_MAX 64 90 91 static struct bce_type bce_devs[] = { 92 /* BCM5706C Controllers and OEM boards. */ 93 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 94 "HP NC370T Multifunction Gigabit Server Adapter" }, 95 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 96 "HP NC370i Multifunction Gigabit Server Adapter" }, 97 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 98 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 99 100 /* BCM5706S controllers and OEM boards. */ 101 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 102 "HP NC370F Multifunction Gigabit Server Adapter" }, 103 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 104 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 105 106 /* BCM5708C controllers and OEM boards. */ 107 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 108 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 109 110 /* BCM5708S controllers and OEM boards. */ 111 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 112 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 113 { 0, 0, 0, 0, NULL } 114 }; 115 116 117 /****************************************************************************/ 118 /* Supported Flash NVRAM device data. */ 119 /****************************************************************************/ 120 static struct flash_spec flash_table[] = 121 { 122 /* Slow EEPROM */ 123 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 124 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 125 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 126 "EEPROM - slow"}, 127 /* Expansion entry 0001 */ 128 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 129 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 130 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 131 "Entry 0001"}, 132 /* Saifun SA25F010 (non-buffered flash) */ 133 /* strap, cfg1, & write1 need updates */ 134 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 135 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 136 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 137 "Non-buffered flash (128kB)"}, 138 /* Saifun SA25F020 (non-buffered flash) */ 139 /* strap, cfg1, & write1 need updates */ 140 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 141 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 142 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 143 "Non-buffered flash (256kB)"}, 144 /* Expansion entry 0100 */ 145 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 146 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 147 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 148 "Entry 0100"}, 149 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 150 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 151 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 152 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 153 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 154 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 155 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 156 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 157 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 158 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 159 /* Saifun SA25F005 (non-buffered flash) */ 160 /* strap, cfg1, & write1 need updates */ 161 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 162 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 163 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 164 "Non-buffered flash (64kB)"}, 165 /* Fast EEPROM */ 166 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 167 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 168 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 169 "EEPROM - fast"}, 170 /* Expansion entry 1001 */ 171 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 172 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 173 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 174 "Entry 1001"}, 175 /* Expansion entry 1010 */ 176 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 177 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 179 "Entry 1010"}, 180 /* ATMEL AT45DB011B (buffered flash) */ 181 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 182 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 183 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 184 "Buffered flash (128kB)"}, 185 /* Expansion entry 1100 */ 186 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 187 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 188 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 189 "Entry 1100"}, 190 /* Expansion entry 1101 */ 191 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 192 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 193 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 194 "Entry 1101"}, 195 /* Ateml Expansion entry 1110 */ 196 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 197 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 198 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 199 "Entry 1110 (Atmel)"}, 200 /* ATMEL AT45DB021B (buffered flash) */ 201 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 202 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 203 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 204 "Buffered flash (256kB)"}, 205 }; 206 207 208 /****************************************************************************/ 209 /* FreeBSD device entry points. */ 210 /****************************************************************************/ 211 static int bce_probe (device_t); 212 static int bce_attach (device_t); 213 static int bce_detach (device_t); 214 static void bce_shutdown (device_t); 215 216 217 /****************************************************************************/ 218 /* BCE Debug Data Structure Dump Routines */ 219 /****************************************************************************/ 220 #ifdef BCE_DEBUG 221 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 222 static void bce_dump_tx_mbuf_chain (struct bce_softc *, int, int); 223 static void bce_dump_rx_mbuf_chain (struct bce_softc *, int, int); 224 static void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *); 225 static void bce_dump_rxbd (struct bce_softc *, int, struct rx_bd *); 226 static void bce_dump_l2fhdr (struct bce_softc *, int, struct l2_fhdr *); 227 static void bce_dump_tx_chain (struct bce_softc *, int, int); 228 static void bce_dump_rx_chain (struct bce_softc *, int, int); 229 static void bce_dump_status_block (struct bce_softc *); 230 static void bce_dump_stats_block (struct bce_softc *); 231 static void bce_dump_driver_state (struct bce_softc *); 232 static void bce_dump_hw_state (struct bce_softc *); 233 static void bce_dump_bc_state (struct bce_softc *); 234 static void bce_breakpoint (struct bce_softc *); 235 #endif 236 237 238 /****************************************************************************/ 239 /* BCE Register/Memory Access Routines */ 240 /****************************************************************************/ 241 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 242 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 243 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 244 static int bce_miibus_read_reg (device_t, int, int); 245 static int bce_miibus_write_reg (device_t, int, int, int); 246 static void bce_miibus_statchg (device_t); 247 248 249 /****************************************************************************/ 250 /* BCE NVRAM Access Routines */ 251 /****************************************************************************/ 252 static int bce_acquire_nvram_lock (struct bce_softc *); 253 static int bce_release_nvram_lock (struct bce_softc *); 254 static void bce_enable_nvram_access (struct bce_softc *); 255 static void bce_disable_nvram_access(struct bce_softc *); 256 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 257 static int bce_init_nvram (struct bce_softc *); 258 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 259 static int bce_nvram_test (struct bce_softc *); 260 #ifdef BCE_NVRAM_WRITE_SUPPORT 261 static int bce_enable_nvram_write (struct bce_softc *); 262 static void bce_disable_nvram_write (struct bce_softc *); 263 static int bce_nvram_erase_page (struct bce_softc *, u32); 264 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 265 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 266 #endif 267 268 /****************************************************************************/ 269 /* */ 270 /****************************************************************************/ 271 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 272 static int bce_dma_alloc (device_t); 273 static void bce_dma_free (struct bce_softc *); 274 static void bce_release_resources (struct bce_softc *); 275 276 /****************************************************************************/ 277 /* BCE Firmware Synchronization and Load */ 278 /****************************************************************************/ 279 static int bce_fw_sync (struct bce_softc *, u32); 280 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 281 static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *); 282 static void bce_init_cpus (struct bce_softc *); 283 284 static void bce_stop (struct bce_softc *); 285 static int bce_reset (struct bce_softc *, u32); 286 static int bce_chipinit (struct bce_softc *); 287 static int bce_blockinit (struct bce_softc *); 288 static int bce_get_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *); 289 290 static int bce_init_tx_chain (struct bce_softc *); 291 static void bce_fill_rx_chain (struct bce_softc *); 292 static int bce_init_rx_chain (struct bce_softc *); 293 static void bce_free_rx_chain (struct bce_softc *); 294 static void bce_free_tx_chain (struct bce_softc *); 295 296 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 297 static void bce_start_locked (struct ifnet *); 298 static void bce_start (struct ifnet *); 299 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 300 static void bce_watchdog (struct bce_softc *); 301 static int bce_ifmedia_upd (struct ifnet *); 302 static void bce_ifmedia_upd_locked (struct ifnet *); 303 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 304 static void bce_init_locked (struct bce_softc *); 305 static void bce_init (void *); 306 static void bce_mgmt_init_locked (struct bce_softc *sc); 307 308 static void bce_init_context (struct bce_softc *); 309 static void bce_get_mac_addr (struct bce_softc *); 310 static void bce_set_mac_addr (struct bce_softc *); 311 static void bce_phy_intr (struct bce_softc *); 312 static void bce_rx_intr (struct bce_softc *); 313 static void bce_tx_intr (struct bce_softc *); 314 static void bce_disable_intr (struct bce_softc *); 315 static void bce_enable_intr (struct bce_softc *); 316 317 #ifdef DEVICE_POLLING 318 static void bce_poll_locked (struct ifnet *, enum poll_cmd, int); 319 static void bce_poll (struct ifnet *, enum poll_cmd, int); 320 #endif 321 static void bce_intr (void *); 322 static void bce_set_rx_mode (struct bce_softc *); 323 static void bce_stats_update (struct bce_softc *); 324 static void bce_tick (void *); 325 static void bce_pulse (void *); 326 static void bce_add_sysctls (struct bce_softc *); 327 328 329 /****************************************************************************/ 330 /* FreeBSD device dispatch table. */ 331 /****************************************************************************/ 332 static device_method_t bce_methods[] = { 333 /* Device interface */ 334 DEVMETHOD(device_probe, bce_probe), 335 DEVMETHOD(device_attach, bce_attach), 336 DEVMETHOD(device_detach, bce_detach), 337 DEVMETHOD(device_shutdown, bce_shutdown), 338 339 /* bus interface */ 340 DEVMETHOD(bus_print_child, bus_generic_print_child), 341 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 342 343 /* MII interface */ 344 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 345 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 346 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 347 348 { 0, 0 } 349 }; 350 351 static driver_t bce_driver = { 352 "bce", 353 bce_methods, 354 sizeof(struct bce_softc) 355 }; 356 357 static devclass_t bce_devclass; 358 359 MODULE_DEPEND(bce, pci, 1, 1, 1); 360 MODULE_DEPEND(bce, ether, 1, 1, 1); 361 MODULE_DEPEND(bce, miibus, 1, 1, 1); 362 363 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 364 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 365 366 367 /****************************************************************************/ 368 /* Tunable device values */ 369 /****************************************************************************/ 370 static int bce_tso_enable = TRUE; 371 static int bce_msi_enable = 1; 372 373 /* Allowable values are TRUE or FALSE */ 374 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 375 /* Allowable values are 0 (IRQ only) and 1 (IRQ or MSI) */ 376 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 377 378 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 379 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 380 "TSO Enable/Disable"); 381 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 382 "MSI | INTx selector"); 383 384 /****************************************************************************/ 385 /* Device probe function. */ 386 /* */ 387 /* Compares the device to the driver's list of supported devices and */ 388 /* reports back to the OS whether this is the right driver for the device. */ 389 /* */ 390 /* Returns: */ 391 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 392 /****************************************************************************/ 393 static int 394 bce_probe(device_t dev) 395 { 396 struct bce_type *t; 397 struct bce_softc *sc; 398 char *descbuf; 399 u16 vid = 0, did = 0, svid = 0, sdid = 0; 400 401 t = bce_devs; 402 403 sc = device_get_softc(dev); 404 bzero(sc, sizeof(struct bce_softc)); 405 sc->bce_unit = device_get_unit(dev); 406 sc->bce_dev = dev; 407 408 /* Get the data for the device to be probed. */ 409 vid = pci_get_vendor(dev); 410 did = pci_get_device(dev); 411 svid = pci_get_subvendor(dev); 412 sdid = pci_get_subdevice(dev); 413 414 DBPRINT(sc, BCE_VERBOSE_LOAD, 415 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 416 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 417 418 /* Look through the list of known devices for a match. */ 419 while(t->bce_name != NULL) { 420 421 if ((vid == t->bce_vid) && (did == t->bce_did) && 422 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 423 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 424 425 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 426 427 if (descbuf == NULL) 428 return(ENOMEM); 429 430 /* Print out the device identity. */ 431 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 432 t->bce_name, 433 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 434 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 435 436 device_set_desc_copy(dev, descbuf); 437 free(descbuf, M_TEMP); 438 return(BUS_PROBE_DEFAULT); 439 } 440 t++; 441 } 442 443 return(ENXIO); 444 } 445 446 447 /****************************************************************************/ 448 /* Device attach function. */ 449 /* */ 450 /* Allocates device resources, performs secondary chip identification, */ 451 /* resets and initializes the hardware, and initializes driver instance */ 452 /* variables. */ 453 /* */ 454 /* Returns: */ 455 /* 0 on success, positive value on failure. */ 456 /****************************************************************************/ 457 static int 458 bce_attach(device_t dev) 459 { 460 struct bce_softc *sc; 461 struct ifnet *ifp; 462 u32 val; 463 int count, mbuf, rid, rc = 0; 464 465 sc = device_get_softc(dev); 466 sc->bce_dev = dev; 467 468 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 469 470 mbuf = device_get_unit(dev); 471 472 /* Set initial device and PHY flags */ 473 sc->bce_flags = 0; 474 sc->bce_phy_flags = 0; 475 476 sc->bce_unit = mbuf; 477 478 pci_enable_busmaster(dev); 479 480 /* Allocate PCI memory resources. */ 481 rid = PCIR_BAR(0); 482 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 483 &rid, RF_ACTIVE | PCI_RF_DENSE); 484 485 if (sc->bce_res_mem == NULL) { 486 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 487 __FILE__, __LINE__); 488 rc = ENXIO; 489 goto bce_attach_fail; 490 } 491 492 /* Get various resource handles. */ 493 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 494 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 495 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 496 497 /* If MSI is enabled in the driver, get the vector count. */ 498 count = bce_msi_enable ? pci_msi_count(dev) : 0; 499 500 /* Allocate PCI IRQ resources. */ 501 if (count == 1 && pci_alloc_msi(dev, &count) == 0 && count == 1) { 502 rid = 1; 503 sc->bce_flags |= BCE_USING_MSI_FLAG; 504 DBPRINT(sc, BCE_VERBOSE_LOAD, 505 "Allocating %d MSI interrupt(s)\n", count); 506 } else { 507 rid = 0; 508 DBPRINT(sc, BCE_VERBOSE_LOAD, "Allocating IRQ interrupt\n"); 509 } 510 511 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 512 RF_SHAREABLE | RF_ACTIVE); 513 514 if (sc->bce_res_irq == NULL) { 515 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 516 __FILE__, __LINE__); 517 rc = ENXIO; 518 goto bce_attach_fail; 519 } 520 521 /* Initialize mutex for the current device instance. */ 522 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 523 524 /* 525 * Configure byte swap and enable indirect register access. 526 * Rely on CPU to do target byte swapping on big endian systems. 527 * Access to registers outside of PCI configurtion space are not 528 * valid until this is done. 529 */ 530 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 531 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 532 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 533 534 /* Save ASIC revsion info. */ 535 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 536 537 /* Weed out any non-production controller revisions. */ 538 switch(BCE_CHIP_ID(sc)) { 539 case BCE_CHIP_ID_5706_A0: 540 case BCE_CHIP_ID_5706_A1: 541 case BCE_CHIP_ID_5708_A0: 542 case BCE_CHIP_ID_5708_B0: 543 BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n", 544 __FILE__, __LINE__, 545 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 546 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 547 rc = ENODEV; 548 goto bce_attach_fail; 549 } 550 551 /* 552 * The embedded PCIe to PCI-X bridge (EPB) 553 * in the 5708 cannot address memory above 554 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 555 */ 556 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 557 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 558 else 559 sc->max_bus_addr = BUS_SPACE_MAXADDR; 560 561 /* 562 * Find the base address for shared memory access. 563 * Newer versions of bootcode use a signature and offset 564 * while older versions use a fixed address. 565 */ 566 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 567 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 568 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0); 569 else 570 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 571 572 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 573 __FUNCTION__, sc->bce_shmem_base); 574 575 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base + 576 BCE_DEV_INFO_BC_REV); 577 DBPRINT(sc, BCE_INFO_FIRMWARE, "%s(): bce_fw_ver = 0x%08X\n", 578 __FUNCTION__, sc->bce_fw_ver); 579 580 /* Check if any management firmware is running. */ 581 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE); 582 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED)) { 583 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 584 DBPRINT(sc, BCE_INFO_LOAD, "%s(): BCE_MFW_ENABLE_FLAG\n", 585 __FUNCTION__); 586 } 587 588 /* Get PCI bus information (speed and type). */ 589 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 590 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 591 u32 clkreg; 592 593 sc->bce_flags |= BCE_PCIX_FLAG; 594 595 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 596 597 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 598 switch (clkreg) { 599 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 600 sc->bus_speed_mhz = 133; 601 break; 602 603 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 604 sc->bus_speed_mhz = 100; 605 break; 606 607 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 608 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 609 sc->bus_speed_mhz = 66; 610 break; 611 612 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 613 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 614 sc->bus_speed_mhz = 50; 615 break; 616 617 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 618 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 619 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 620 sc->bus_speed_mhz = 33; 621 break; 622 } 623 } else { 624 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 625 sc->bus_speed_mhz = 66; 626 else 627 sc->bus_speed_mhz = 33; 628 } 629 630 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 631 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 632 633 /* Reset the controller and announce to bootcode that driver is present. */ 634 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 635 BCE_PRINTF("%s(%d): Controller reset failed!\n", 636 __FILE__, __LINE__); 637 rc = ENXIO; 638 goto bce_attach_fail; 639 } 640 641 /* Initialize the controller. */ 642 if (bce_chipinit(sc)) { 643 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 644 __FILE__, __LINE__); 645 rc = ENXIO; 646 goto bce_attach_fail; 647 } 648 649 /* Perform NVRAM test. */ 650 if (bce_nvram_test(sc)) { 651 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 652 __FILE__, __LINE__); 653 rc = ENXIO; 654 goto bce_attach_fail; 655 } 656 657 /* Fetch the permanent Ethernet MAC address. */ 658 bce_get_mac_addr(sc); 659 660 /* 661 * Trip points control how many BDs 662 * should be ready before generating an 663 * interrupt while ticks control how long 664 * a BD can sit in the chain before 665 * generating an interrupt. Set the default 666 * values for the RX and TX chains. 667 */ 668 669 #ifdef BCE_DEBUG 670 /* Force more frequent interrupts. */ 671 sc->bce_tx_quick_cons_trip_int = 1; 672 sc->bce_tx_quick_cons_trip = 1; 673 sc->bce_tx_ticks_int = 0; 674 sc->bce_tx_ticks = 0; 675 676 sc->bce_rx_quick_cons_trip_int = 1; 677 sc->bce_rx_quick_cons_trip = 1; 678 sc->bce_rx_ticks_int = 0; 679 sc->bce_rx_ticks = 0; 680 #else 681 /* Improve throughput at the expense of increased latency. */ 682 sc->bce_tx_quick_cons_trip_int = 20; 683 sc->bce_tx_quick_cons_trip = 20; 684 sc->bce_tx_ticks_int = 80; 685 sc->bce_tx_ticks = 80; 686 687 sc->bce_rx_quick_cons_trip_int = 6; 688 sc->bce_rx_quick_cons_trip = 6; 689 sc->bce_rx_ticks_int = 18; 690 sc->bce_rx_ticks = 18; 691 #endif 692 693 /* Update statistics once every second. */ 694 sc->bce_stats_ticks = 1000000 & 0xffff00; 695 696 /* 697 * The SerDes based NetXtreme II controllers 698 * that support 2.5Gb operation (currently 699 * 5708S) use a PHY at address 2, otherwise 700 * the PHY is present at address 1. 701 */ 702 sc->bce_phy_addr = 1; 703 704 if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) { 705 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 706 sc->bce_flags |= BCE_NO_WOL_FLAG; 707 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 708 sc->bce_phy_addr = 2; 709 val = REG_RD_IND(sc, sc->bce_shmem_base + 710 BCE_SHARED_HW_CFG_CONFIG); 711 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 712 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG; 713 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb capable adapter\n"); 714 } 715 } 716 } 717 718 /* Store data needed by PHY driver for backplane applications */ 719 sc->bce_shared_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 720 BCE_SHARED_HW_CFG_CONFIG); 721 sc->bce_port_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 722 BCE_SHARED_HW_CFG_CONFIG); 723 724 /* Allocate DMA memory resources. */ 725 if (bce_dma_alloc(dev)) { 726 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 727 __FILE__, __LINE__); 728 rc = ENXIO; 729 goto bce_attach_fail; 730 } 731 732 /* Allocate an ifnet structure. */ 733 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 734 if (ifp == NULL) { 735 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 736 __FILE__, __LINE__); 737 rc = ENXIO; 738 goto bce_attach_fail; 739 } 740 741 /* Initialize the ifnet interface. */ 742 ifp->if_softc = sc; 743 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 744 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 745 ifp->if_ioctl = bce_ioctl; 746 ifp->if_start = bce_start; 747 ifp->if_init = bce_init; 748 ifp->if_mtu = ETHERMTU; 749 750 if (bce_tso_enable) { 751 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 752 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4; 753 } else { 754 ifp->if_hwassist = BCE_IF_HWASSIST; 755 ifp->if_capabilities = BCE_IF_CAPABILITIES; 756 } 757 758 ifp->if_capenable = ifp->if_capabilities; 759 760 /* Assume a standard 1500 byte MTU size for mbuf allocations. */ 761 sc->mbuf_alloc_size = MCLBYTES; 762 #ifdef DEVICE_POLLING 763 ifp->if_capabilities |= IFCAP_POLLING; 764 #endif 765 766 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 767 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 768 IFQ_SET_READY(&ifp->if_snd); 769 770 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 771 ifp->if_baudrate = IF_Mbps(2500ULL); 772 else 773 ifp->if_baudrate = IF_Mbps(1000); 774 775 /* Check for an MII child bus by probing the PHY. */ 776 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 777 bce_ifmedia_sts)) { 778 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n", 779 __FILE__, __LINE__); 780 rc = ENXIO; 781 goto bce_attach_fail; 782 } 783 784 /* Attach to the Ethernet interface list. */ 785 ether_ifattach(ifp, sc->eaddr); 786 787 #if __FreeBSD_version < 500000 788 callout_init(&sc->bce_tick_callout); 789 callout_init(&sc->bce_pulse_callout); 790 #else 791 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 792 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 793 #endif 794 795 /* Hookup IRQ last. */ 796 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, NULL, 797 bce_intr, sc, &sc->bce_intrhand); 798 799 if (rc) { 800 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 801 __FILE__, __LINE__); 802 bce_detach(dev); 803 goto bce_attach_exit; 804 } 805 806 /* 807 * At this point we've acquired all the resources 808 * we need to run so there's no turning back, we're 809 * cleared for launch. 810 */ 811 812 /* Print some important debugging info. */ 813 DBRUN(BCE_INFO, bce_dump_driver_state(sc)); 814 815 /* Add the supported sysctls to the kernel. */ 816 bce_add_sysctls(sc); 817 818 BCE_LOCK(sc); 819 /* 820 * The chip reset earlier notified the bootcode that 821 * a driver is present. We now need to start our pulse 822 * routine so that the bootcode is reminded that we're 823 * still running. 824 */ 825 bce_pulse(sc); 826 827 bce_mgmt_init_locked(sc); 828 BCE_UNLOCK(sc); 829 830 /* Finally, print some useful adapter info */ 831 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 832 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A', 833 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 834 printf("Bus (PCI%s, %s, %dMHz); ", 835 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 836 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), 837 sc->bus_speed_mhz); 838 printf("F/W (0x%08X); Flags( ", sc->bce_fw_ver); 839 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 840 printf("MFW "); 841 if (sc->bce_flags & BCE_USING_MSI_FLAG) 842 printf("MSI "); 843 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 844 printf("2.5G "); 845 printf(")\n"); 846 847 goto bce_attach_exit; 848 849 bce_attach_fail: 850 bce_release_resources(sc); 851 852 bce_attach_exit: 853 854 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 855 856 return(rc); 857 } 858 859 860 /****************************************************************************/ 861 /* Device detach function. */ 862 /* */ 863 /* Stops the controller, resets the controller, and releases resources. */ 864 /* */ 865 /* Returns: */ 866 /* 0 on success, positive value on failure. */ 867 /****************************************************************************/ 868 static int 869 bce_detach(device_t dev) 870 { 871 struct bce_softc *sc = device_get_softc(dev); 872 struct ifnet *ifp; 873 u32 msg; 874 875 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 876 877 ifp = sc->bce_ifp; 878 879 #ifdef DEVICE_POLLING 880 if (ifp->if_capenable & IFCAP_POLLING) 881 ether_poll_deregister(ifp); 882 #endif 883 884 /* Stop the pulse so the bootcode can go to driver absent state. */ 885 callout_stop(&sc->bce_pulse_callout); 886 887 /* Stop and reset the controller. */ 888 BCE_LOCK(sc); 889 bce_stop(sc); 890 if (sc->bce_flags & BCE_NO_WOL_FLAG) 891 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 892 else 893 msg = BCE_DRV_MSG_CODE_UNLOAD; 894 bce_reset(sc, msg); 895 BCE_UNLOCK(sc); 896 897 ether_ifdetach(ifp); 898 899 /* If we have a child device on the MII bus remove it too. */ 900 bus_generic_detach(dev); 901 device_delete_child(dev, sc->bce_miibus); 902 903 /* Release all remaining resources. */ 904 bce_release_resources(sc); 905 906 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 907 908 return(0); 909 } 910 911 912 /****************************************************************************/ 913 /* Device shutdown function. */ 914 /* */ 915 /* Stops and resets the controller. */ 916 /* */ 917 /* Returns: */ 918 /* Nothing */ 919 /****************************************************************************/ 920 static void 921 bce_shutdown(device_t dev) 922 { 923 struct bce_softc *sc = device_get_softc(dev); 924 u32 msg; 925 926 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Entering %s()\n", __FUNCTION__); 927 928 BCE_LOCK(sc); 929 bce_stop(sc); 930 if (sc->bce_flags & BCE_NO_WOL_FLAG) 931 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 932 else 933 msg = BCE_DRV_MSG_CODE_UNLOAD; 934 bce_reset(sc, msg); 935 BCE_UNLOCK(sc); 936 937 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Exiting %s()\n", __FUNCTION__); 938 } 939 940 941 /****************************************************************************/ 942 /* Indirect register read. */ 943 /* */ 944 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 945 /* configuration space. Using this mechanism avoids issues with posted */ 946 /* reads but is much slower than memory-mapped I/O. */ 947 /* */ 948 /* Returns: */ 949 /* The value of the register. */ 950 /****************************************************************************/ 951 static u32 952 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 953 { 954 device_t dev; 955 dev = sc->bce_dev; 956 957 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 958 #ifdef BCE_DEBUG 959 { 960 u32 val; 961 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 962 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 963 __FUNCTION__, offset, val); 964 return val; 965 } 966 #else 967 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 968 #endif 969 } 970 971 972 /****************************************************************************/ 973 /* Indirect register write. */ 974 /* */ 975 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 976 /* configuration space. Using this mechanism avoids issues with posted */ 977 /* writes but is muchh slower than memory-mapped I/O. */ 978 /* */ 979 /* Returns: */ 980 /* Nothing. */ 981 /****************************************************************************/ 982 static void 983 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 984 { 985 device_t dev; 986 dev = sc->bce_dev; 987 988 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 989 __FUNCTION__, offset, val); 990 991 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 992 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 993 } 994 995 996 /****************************************************************************/ 997 /* Context memory write. */ 998 /* */ 999 /* The NetXtreme II controller uses context memory to track connection */ 1000 /* information for L2 and higher network protocols. */ 1001 /* */ 1002 /* Returns: */ 1003 /* Nothing. */ 1004 /****************************************************************************/ 1005 static void 1006 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 offset, u32 val) 1007 { 1008 1009 DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1010 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val); 1011 1012 offset += cid_addr; 1013 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1014 REG_WR(sc, BCE_CTX_DATA, val); 1015 } 1016 1017 1018 /****************************************************************************/ 1019 /* PHY register read. */ 1020 /* */ 1021 /* Implements register reads on the MII bus. */ 1022 /* */ 1023 /* Returns: */ 1024 /* The value of the register. */ 1025 /****************************************************************************/ 1026 static int 1027 bce_miibus_read_reg(device_t dev, int phy, int reg) 1028 { 1029 struct bce_softc *sc; 1030 u32 val; 1031 int i; 1032 1033 sc = device_get_softc(dev); 1034 1035 /* Make sure we are accessing the correct PHY address. */ 1036 if (phy != sc->bce_phy_addr) { 1037 DBPRINT(sc, BCE_EXCESSIVE_PHY, "Invalid PHY address %d for PHY read!\n", phy); 1038 return(0); 1039 } 1040 1041 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1042 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1043 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1044 1045 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1046 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1047 1048 DELAY(40); 1049 } 1050 1051 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1052 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1053 BCE_EMAC_MDIO_COMM_START_BUSY; 1054 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1055 1056 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1057 DELAY(10); 1058 1059 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1060 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1061 DELAY(5); 1062 1063 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1064 val &= BCE_EMAC_MDIO_COMM_DATA; 1065 1066 break; 1067 } 1068 } 1069 1070 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1071 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n", 1072 __FILE__, __LINE__, phy, reg); 1073 val = 0x0; 1074 } else { 1075 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1076 } 1077 1078 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1079 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1080 1081 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1082 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1083 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1084 1085 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1086 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1087 1088 DELAY(40); 1089 } 1090 1091 return (val & 0xffff); 1092 1093 } 1094 1095 1096 /****************************************************************************/ 1097 /* PHY register write. */ 1098 /* */ 1099 /* Implements register writes on the MII bus. */ 1100 /* */ 1101 /* Returns: */ 1102 /* The value of the register. */ 1103 /****************************************************************************/ 1104 static int 1105 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1106 { 1107 struct bce_softc *sc; 1108 u32 val1; 1109 int i; 1110 1111 sc = device_get_softc(dev); 1112 1113 /* Make sure we are accessing the correct PHY address. */ 1114 if (phy != sc->bce_phy_addr) { 1115 DBPRINT(sc, BCE_EXCESSIVE_PHY, "Invalid PHY address %d for PHY write!\n", phy); 1116 return(0); 1117 } 1118 1119 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1120 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1121 1122 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1123 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1124 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1125 1126 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1127 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1128 1129 DELAY(40); 1130 } 1131 1132 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1133 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1134 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1135 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1136 1137 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1138 DELAY(10); 1139 1140 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1141 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1142 DELAY(5); 1143 break; 1144 } 1145 } 1146 1147 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1148 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1149 __FILE__, __LINE__); 1150 1151 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1152 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1153 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1154 1155 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1156 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1157 1158 DELAY(40); 1159 } 1160 1161 return 0; 1162 } 1163 1164 1165 /****************************************************************************/ 1166 /* MII bus status change. */ 1167 /* */ 1168 /* Called by the MII bus driver when the PHY establishes link to set the */ 1169 /* MAC interface registers. */ 1170 /* */ 1171 /* Returns: */ 1172 /* Nothing. */ 1173 /****************************************************************************/ 1174 static void 1175 bce_miibus_statchg(device_t dev) 1176 { 1177 struct bce_softc *sc; 1178 struct mii_data *mii; 1179 int val; 1180 1181 sc = device_get_softc(dev); 1182 1183 mii = device_get_softc(sc->bce_miibus); 1184 1185 val = REG_RD(sc, BCE_EMAC_MODE); 1186 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1187 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1188 BCE_EMAC_MODE_25G); 1189 1190 /* Set MII or GMII interface based on the speed negotiated by the PHY. */ 1191 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1192 case IFM_10_T: 1193 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 1194 DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n"); 1195 val |= BCE_EMAC_MODE_PORT_MII_10; 1196 break; 1197 } 1198 /* fall-through */ 1199 case IFM_100_TX: 1200 DBPRINT(sc, BCE_INFO, "Enabling MII interface.\n"); 1201 val |= BCE_EMAC_MODE_PORT_MII; 1202 break; 1203 case IFM_2500_SX: 1204 DBPRINT(sc, BCE_INFO, "Enabling 2.5G MAC mode.\n"); 1205 val |= BCE_EMAC_MODE_25G; 1206 /* fall-through */ 1207 case IFM_1000_T: 1208 case IFM_1000_SX: 1209 DBPRINT(sc, BCE_INFO, "Enabling GMII interface.\n"); 1210 val |= BCE_EMAC_MODE_PORT_GMII; 1211 break; 1212 default: 1213 DBPRINT(sc, BCE_INFO, "Enabling default GMII interface.\n"); 1214 val |= BCE_EMAC_MODE_PORT_GMII; 1215 } 1216 1217 /* Set half or full duplex based on the duplicity negotiated by the PHY. */ 1218 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1219 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n"); 1220 val |= BCE_EMAC_MODE_HALF_DUPLEX; 1221 } else 1222 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n"); 1223 1224 REG_WR(sc, BCE_EMAC_MODE, val); 1225 1226 #if 0 1227 /* Todo: Enable flow control support in brgphy and bge. */ 1228 /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */ 1229 if (mii->mii_media_active & IFM_FLAG0) 1230 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1231 if (mii->mii_media_active & IFM_FLAG1) 1232 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1233 #endif 1234 1235 } 1236 1237 1238 /****************************************************************************/ 1239 /* Acquire NVRAM lock. */ 1240 /* */ 1241 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1242 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1243 /* for use by the driver. */ 1244 /* */ 1245 /* Returns: */ 1246 /* 0 on success, positive value on failure. */ 1247 /****************************************************************************/ 1248 static int 1249 bce_acquire_nvram_lock(struct bce_softc *sc) 1250 { 1251 u32 val; 1252 int j; 1253 1254 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Acquiring NVRAM lock.\n"); 1255 1256 /* Request access to the flash interface. */ 1257 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1258 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1259 val = REG_RD(sc, BCE_NVM_SW_ARB); 1260 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1261 break; 1262 1263 DELAY(5); 1264 } 1265 1266 if (j >= NVRAM_TIMEOUT_COUNT) { 1267 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1268 return EBUSY; 1269 } 1270 1271 return 0; 1272 } 1273 1274 1275 /****************************************************************************/ 1276 /* Release NVRAM lock. */ 1277 /* */ 1278 /* When the caller is finished accessing NVRAM the lock must be released. */ 1279 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1280 /* for use by the driver. */ 1281 /* */ 1282 /* Returns: */ 1283 /* 0 on success, positive value on failure. */ 1284 /****************************************************************************/ 1285 static int 1286 bce_release_nvram_lock(struct bce_softc *sc) 1287 { 1288 int j; 1289 u32 val; 1290 1291 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Releasing NVRAM lock.\n"); 1292 1293 /* 1294 * Relinquish nvram interface. 1295 */ 1296 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1297 1298 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1299 val = REG_RD(sc, BCE_NVM_SW_ARB); 1300 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1301 break; 1302 1303 DELAY(5); 1304 } 1305 1306 if (j >= NVRAM_TIMEOUT_COUNT) { 1307 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n"); 1308 return EBUSY; 1309 } 1310 1311 return 0; 1312 } 1313 1314 1315 #ifdef BCE_NVRAM_WRITE_SUPPORT 1316 /****************************************************************************/ 1317 /* Enable NVRAM write access. */ 1318 /* */ 1319 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1320 /* */ 1321 /* Returns: */ 1322 /* 0 on success, positive value on failure. */ 1323 /****************************************************************************/ 1324 static int 1325 bce_enable_nvram_write(struct bce_softc *sc) 1326 { 1327 u32 val; 1328 1329 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Enabling NVRAM write.\n"); 1330 1331 val = REG_RD(sc, BCE_MISC_CFG); 1332 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1333 1334 if (!sc->bce_flash_info->buffered) { 1335 int j; 1336 1337 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1338 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1339 1340 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1341 DELAY(5); 1342 1343 val = REG_RD(sc, BCE_NVM_COMMAND); 1344 if (val & BCE_NVM_COMMAND_DONE) 1345 break; 1346 } 1347 1348 if (j >= NVRAM_TIMEOUT_COUNT) { 1349 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1350 return EBUSY; 1351 } 1352 } 1353 return 0; 1354 } 1355 1356 1357 /****************************************************************************/ 1358 /* Disable NVRAM write access. */ 1359 /* */ 1360 /* When the caller is finished writing to NVRAM write access must be */ 1361 /* disabled. */ 1362 /* */ 1363 /* Returns: */ 1364 /* Nothing. */ 1365 /****************************************************************************/ 1366 static void 1367 bce_disable_nvram_write(struct bce_softc *sc) 1368 { 1369 u32 val; 1370 1371 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Disabling NVRAM write.\n"); 1372 1373 val = REG_RD(sc, BCE_MISC_CFG); 1374 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1375 } 1376 #endif 1377 1378 1379 /****************************************************************************/ 1380 /* Enable NVRAM access. */ 1381 /* */ 1382 /* Before accessing NVRAM for read or write operations the caller must */ 1383 /* enabled NVRAM access. */ 1384 /* */ 1385 /* Returns: */ 1386 /* Nothing. */ 1387 /****************************************************************************/ 1388 static void 1389 bce_enable_nvram_access(struct bce_softc *sc) 1390 { 1391 u32 val; 1392 1393 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Enabling NVRAM access.\n"); 1394 1395 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1396 /* Enable both bits, even on read. */ 1397 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1398 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1399 } 1400 1401 1402 /****************************************************************************/ 1403 /* Disable NVRAM access. */ 1404 /* */ 1405 /* When the caller is finished accessing NVRAM access must be disabled. */ 1406 /* */ 1407 /* Returns: */ 1408 /* Nothing. */ 1409 /****************************************************************************/ 1410 static void 1411 bce_disable_nvram_access(struct bce_softc *sc) 1412 { 1413 u32 val; 1414 1415 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Disabling NVRAM access.\n"); 1416 1417 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1418 1419 /* Disable both bits, even after read. */ 1420 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1421 val & ~(BCE_NVM_ACCESS_ENABLE_EN | 1422 BCE_NVM_ACCESS_ENABLE_WR_EN)); 1423 } 1424 1425 1426 #ifdef BCE_NVRAM_WRITE_SUPPORT 1427 /****************************************************************************/ 1428 /* Erase NVRAM page before writing. */ 1429 /* */ 1430 /* Non-buffered flash parts require that a page be erased before it is */ 1431 /* written. */ 1432 /* */ 1433 /* Returns: */ 1434 /* 0 on success, positive value on failure. */ 1435 /****************************************************************************/ 1436 static int 1437 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 1438 { 1439 u32 cmd; 1440 int j; 1441 1442 /* Buffered flash doesn't require an erase. */ 1443 if (sc->bce_flash_info->buffered) 1444 return 0; 1445 1446 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Erasing NVRAM page.\n"); 1447 1448 /* Build an erase command. */ 1449 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 1450 BCE_NVM_COMMAND_DOIT; 1451 1452 /* 1453 * Clear the DONE bit separately, set the NVRAM adress to erase, 1454 * and issue the erase command. 1455 */ 1456 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1457 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1458 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1459 1460 /* Wait for completion. */ 1461 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1462 u32 val; 1463 1464 DELAY(5); 1465 1466 val = REG_RD(sc, BCE_NVM_COMMAND); 1467 if (val & BCE_NVM_COMMAND_DONE) 1468 break; 1469 } 1470 1471 if (j >= NVRAM_TIMEOUT_COUNT) { 1472 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 1473 return EBUSY; 1474 } 1475 1476 return 0; 1477 } 1478 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1479 1480 1481 /****************************************************************************/ 1482 /* Read a dword (32 bits) from NVRAM. */ 1483 /* */ 1484 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1485 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1486 /* */ 1487 /* Returns: */ 1488 /* 0 on success and the 32 bit value read, positive value on failure. */ 1489 /****************************************************************************/ 1490 static int 1491 bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val, 1492 u32 cmd_flags) 1493 { 1494 u32 cmd; 1495 int i, rc = 0; 1496 1497 /* Build the command word. */ 1498 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 1499 1500 /* Calculate the offset for buffered flash. */ 1501 if (sc->bce_flash_info->buffered) { 1502 offset = ((offset / sc->bce_flash_info->page_size) << 1503 sc->bce_flash_info->page_bits) + 1504 (offset % sc->bce_flash_info->page_size); 1505 } 1506 1507 /* 1508 * Clear the DONE bit separately, set the address to read, 1509 * and issue the read. 1510 */ 1511 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1512 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1513 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1514 1515 /* Wait for completion. */ 1516 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1517 u32 val; 1518 1519 DELAY(5); 1520 1521 val = REG_RD(sc, BCE_NVM_COMMAND); 1522 if (val & BCE_NVM_COMMAND_DONE) { 1523 val = REG_RD(sc, BCE_NVM_READ); 1524 1525 val = bce_be32toh(val); 1526 memcpy(ret_val, &val, 4); 1527 break; 1528 } 1529 } 1530 1531 /* Check for errors. */ 1532 if (i >= NVRAM_TIMEOUT_COUNT) { 1533 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n", 1534 __FILE__, __LINE__, offset); 1535 rc = EBUSY; 1536 } 1537 1538 return(rc); 1539 } 1540 1541 1542 #ifdef BCE_NVRAM_WRITE_SUPPORT 1543 /****************************************************************************/ 1544 /* Write a dword (32 bits) to NVRAM. */ 1545 /* */ 1546 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1547 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1548 /* enabled NVRAM write access. */ 1549 /* */ 1550 /* Returns: */ 1551 /* 0 on success, positive value on failure. */ 1552 /****************************************************************************/ 1553 static int 1554 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 1555 u32 cmd_flags) 1556 { 1557 u32 cmd, val32; 1558 int j; 1559 1560 /* Build the command word. */ 1561 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 1562 1563 /* Calculate the offset for buffered flash. */ 1564 if (sc->bce_flash_info->buffered) { 1565 offset = ((offset / sc->bce_flash_info->page_size) << 1566 sc->bce_flash_info->page_bits) + 1567 (offset % sc->bce_flash_info->page_size); 1568 } 1569 1570 /* 1571 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1572 * set the NVRAM address to write, and issue the write command 1573 */ 1574 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1575 memcpy(&val32, val, 4); 1576 val32 = htobe32(val32); 1577 REG_WR(sc, BCE_NVM_WRITE, val32); 1578 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1579 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1580 1581 /* Wait for completion. */ 1582 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1583 DELAY(5); 1584 1585 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 1586 break; 1587 } 1588 if (j >= NVRAM_TIMEOUT_COUNT) { 1589 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n", 1590 __FILE__, __LINE__, offset); 1591 return EBUSY; 1592 } 1593 1594 return 0; 1595 } 1596 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1597 1598 1599 /****************************************************************************/ 1600 /* Initialize NVRAM access. */ 1601 /* */ 1602 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1603 /* access that device. */ 1604 /* */ 1605 /* Returns: */ 1606 /* 0 on success, positive value on failure. */ 1607 /****************************************************************************/ 1608 static int 1609 bce_init_nvram(struct bce_softc *sc) 1610 { 1611 u32 val; 1612 int j, entry_count, rc; 1613 struct flash_spec *flash; 1614 1615 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Entering %s()\n", __FUNCTION__); 1616 1617 /* Determine the selected interface. */ 1618 val = REG_RD(sc, BCE_NVM_CFG1); 1619 1620 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1621 1622 rc = 0; 1623 1624 /* 1625 * Flash reconfiguration is required to support additional 1626 * NVRAM devices not directly supported in hardware. 1627 * Check if the flash interface was reconfigured 1628 * by the bootcode. 1629 */ 1630 1631 if (val & 0x40000000) { 1632 /* Flash interface reconfigured by bootcode. */ 1633 1634 DBPRINT(sc,BCE_INFO_LOAD, 1635 "bce_init_nvram(): Flash WAS reconfigured.\n"); 1636 1637 for (j = 0, flash = &flash_table[0]; j < entry_count; 1638 j++, flash++) { 1639 if ((val & FLASH_BACKUP_STRAP_MASK) == 1640 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1641 sc->bce_flash_info = flash; 1642 break; 1643 } 1644 } 1645 } else { 1646 /* Flash interface not yet reconfigured. */ 1647 u32 mask; 1648 1649 DBPRINT(sc,BCE_INFO_LOAD, 1650 "bce_init_nvram(): Flash was NOT reconfigured.\n"); 1651 1652 if (val & (1 << 23)) 1653 mask = FLASH_BACKUP_STRAP_MASK; 1654 else 1655 mask = FLASH_STRAP_MASK; 1656 1657 /* Look for the matching NVRAM device configuration data. */ 1658 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 1659 1660 /* Check if the device matches any of the known devices. */ 1661 if ((val & mask) == (flash->strapping & mask)) { 1662 /* Found a device match. */ 1663 sc->bce_flash_info = flash; 1664 1665 /* Request access to the flash interface. */ 1666 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1667 return rc; 1668 1669 /* Reconfigure the flash interface. */ 1670 bce_enable_nvram_access(sc); 1671 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 1672 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 1673 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 1674 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 1675 bce_disable_nvram_access(sc); 1676 bce_release_nvram_lock(sc); 1677 1678 break; 1679 } 1680 } 1681 } 1682 1683 /* Check if a matching device was found. */ 1684 if (j == entry_count) { 1685 sc->bce_flash_info = NULL; 1686 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 1687 __FILE__, __LINE__); 1688 rc = ENODEV; 1689 } 1690 1691 /* Write the flash config data to the shared memory interface. */ 1692 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2); 1693 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 1694 if (val) 1695 sc->bce_flash_size = val; 1696 else 1697 sc->bce_flash_size = sc->bce_flash_info->total_size; 1698 1699 DBPRINT(sc, BCE_INFO_LOAD, "bce_init_nvram() flash->total_size = 0x%08X\n", 1700 sc->bce_flash_info->total_size); 1701 1702 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Exiting %s()\n", __FUNCTION__); 1703 1704 return rc; 1705 } 1706 1707 1708 /****************************************************************************/ 1709 /* Read an arbitrary range of data from NVRAM. */ 1710 /* */ 1711 /* Prepares the NVRAM interface for access and reads the requested data */ 1712 /* into the supplied buffer. */ 1713 /* */ 1714 /* Returns: */ 1715 /* 0 on success and the data read, positive value on failure. */ 1716 /****************************************************************************/ 1717 static int 1718 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 1719 int buf_size) 1720 { 1721 int rc = 0; 1722 u32 cmd_flags, offset32, len32, extra; 1723 1724 if (buf_size == 0) 1725 return 0; 1726 1727 /* Request access to the flash interface. */ 1728 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1729 return rc; 1730 1731 /* Enable access to flash interface */ 1732 bce_enable_nvram_access(sc); 1733 1734 len32 = buf_size; 1735 offset32 = offset; 1736 extra = 0; 1737 1738 cmd_flags = 0; 1739 1740 if (offset32 & 3) { 1741 u8 buf[4]; 1742 u32 pre_len; 1743 1744 offset32 &= ~3; 1745 pre_len = 4 - (offset & 3); 1746 1747 if (pre_len >= len32) { 1748 pre_len = len32; 1749 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 1750 } 1751 else { 1752 cmd_flags = BCE_NVM_COMMAND_FIRST; 1753 } 1754 1755 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1756 1757 if (rc) 1758 return rc; 1759 1760 memcpy(ret_buf, buf + (offset & 3), pre_len); 1761 1762 offset32 += 4; 1763 ret_buf += pre_len; 1764 len32 -= pre_len; 1765 } 1766 1767 if (len32 & 3) { 1768 extra = 4 - (len32 & 3); 1769 len32 = (len32 + 4) & ~3; 1770 } 1771 1772 if (len32 == 4) { 1773 u8 buf[4]; 1774 1775 if (cmd_flags) 1776 cmd_flags = BCE_NVM_COMMAND_LAST; 1777 else 1778 cmd_flags = BCE_NVM_COMMAND_FIRST | 1779 BCE_NVM_COMMAND_LAST; 1780 1781 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1782 1783 memcpy(ret_buf, buf, 4 - extra); 1784 } 1785 else if (len32 > 0) { 1786 u8 buf[4]; 1787 1788 /* Read the first word. */ 1789 if (cmd_flags) 1790 cmd_flags = 0; 1791 else 1792 cmd_flags = BCE_NVM_COMMAND_FIRST; 1793 1794 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1795 1796 /* Advance to the next dword. */ 1797 offset32 += 4; 1798 ret_buf += 4; 1799 len32 -= 4; 1800 1801 while (len32 > 4 && rc == 0) { 1802 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 1803 1804 /* Advance to the next dword. */ 1805 offset32 += 4; 1806 ret_buf += 4; 1807 len32 -= 4; 1808 } 1809 1810 if (rc) 1811 return rc; 1812 1813 cmd_flags = BCE_NVM_COMMAND_LAST; 1814 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1815 1816 memcpy(ret_buf, buf, 4 - extra); 1817 } 1818 1819 /* Disable access to flash interface and release the lock. */ 1820 bce_disable_nvram_access(sc); 1821 bce_release_nvram_lock(sc); 1822 1823 return rc; 1824 } 1825 1826 1827 #ifdef BCE_NVRAM_WRITE_SUPPORT 1828 /****************************************************************************/ 1829 /* Write an arbitrary range of data from NVRAM. */ 1830 /* */ 1831 /* Prepares the NVRAM interface for write access and writes the requested */ 1832 /* data from the supplied buffer. The caller is responsible for */ 1833 /* calculating any appropriate CRCs. */ 1834 /* */ 1835 /* Returns: */ 1836 /* 0 on success, positive value on failure. */ 1837 /****************************************************************************/ 1838 static int 1839 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 1840 int buf_size) 1841 { 1842 u32 written, offset32, len32; 1843 u8 *buf, start[4], end[4]; 1844 int rc = 0; 1845 int align_start, align_end; 1846 1847 buf = data_buf; 1848 offset32 = offset; 1849 len32 = buf_size; 1850 align_start = align_end = 0; 1851 1852 if ((align_start = (offset32 & 3))) { 1853 offset32 &= ~3; 1854 len32 += align_start; 1855 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 1856 return rc; 1857 } 1858 1859 if (len32 & 3) { 1860 if ((len32 > 4) || !align_start) { 1861 align_end = 4 - (len32 & 3); 1862 len32 += align_end; 1863 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 1864 end, 4))) { 1865 return rc; 1866 } 1867 } 1868 } 1869 1870 if (align_start || align_end) { 1871 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1872 if (buf == 0) 1873 return ENOMEM; 1874 if (align_start) { 1875 memcpy(buf, start, 4); 1876 } 1877 if (align_end) { 1878 memcpy(buf + len32 - 4, end, 4); 1879 } 1880 memcpy(buf + align_start, data_buf, buf_size); 1881 } 1882 1883 written = 0; 1884 while ((written < len32) && (rc == 0)) { 1885 u32 page_start, page_end, data_start, data_end; 1886 u32 addr, cmd_flags; 1887 int i; 1888 u8 flash_buffer[264]; 1889 1890 /* Find the page_start addr */ 1891 page_start = offset32 + written; 1892 page_start -= (page_start % sc->bce_flash_info->page_size); 1893 /* Find the page_end addr */ 1894 page_end = page_start + sc->bce_flash_info->page_size; 1895 /* Find the data_start addr */ 1896 data_start = (written == 0) ? offset32 : page_start; 1897 /* Find the data_end addr */ 1898 data_end = (page_end > offset32 + len32) ? 1899 (offset32 + len32) : page_end; 1900 1901 /* Request access to the flash interface. */ 1902 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1903 goto nvram_write_end; 1904 1905 /* Enable access to flash interface */ 1906 bce_enable_nvram_access(sc); 1907 1908 cmd_flags = BCE_NVM_COMMAND_FIRST; 1909 if (sc->bce_flash_info->buffered == 0) { 1910 int j; 1911 1912 /* Read the whole page into the buffer 1913 * (non-buffer flash only) */ 1914 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 1915 if (j == (sc->bce_flash_info->page_size - 4)) { 1916 cmd_flags |= BCE_NVM_COMMAND_LAST; 1917 } 1918 rc = bce_nvram_read_dword(sc, 1919 page_start + j, 1920 &flash_buffer[j], 1921 cmd_flags); 1922 1923 if (rc) 1924 goto nvram_write_end; 1925 1926 cmd_flags = 0; 1927 } 1928 } 1929 1930 /* Enable writes to flash interface (unlock write-protect) */ 1931 if ((rc = bce_enable_nvram_write(sc)) != 0) 1932 goto nvram_write_end; 1933 1934 /* Erase the page */ 1935 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 1936 goto nvram_write_end; 1937 1938 /* Re-enable the write again for the actual write */ 1939 bce_enable_nvram_write(sc); 1940 1941 /* Loop to write back the buffer data from page_start to 1942 * data_start */ 1943 i = 0; 1944 if (sc->bce_flash_info->buffered == 0) { 1945 for (addr = page_start; addr < data_start; 1946 addr += 4, i += 4) { 1947 1948 rc = bce_nvram_write_dword(sc, addr, 1949 &flash_buffer[i], cmd_flags); 1950 1951 if (rc != 0) 1952 goto nvram_write_end; 1953 1954 cmd_flags = 0; 1955 } 1956 } 1957 1958 /* Loop to write the new data from data_start to data_end */ 1959 for (addr = data_start; addr < data_end; addr += 4, i++) { 1960 if ((addr == page_end - 4) || 1961 ((sc->bce_flash_info->buffered) && 1962 (addr == data_end - 4))) { 1963 1964 cmd_flags |= BCE_NVM_COMMAND_LAST; 1965 } 1966 rc = bce_nvram_write_dword(sc, addr, buf, 1967 cmd_flags); 1968 1969 if (rc != 0) 1970 goto nvram_write_end; 1971 1972 cmd_flags = 0; 1973 buf += 4; 1974 } 1975 1976 /* Loop to write back the buffer data from data_end 1977 * to page_end */ 1978 if (sc->bce_flash_info->buffered == 0) { 1979 for (addr = data_end; addr < page_end; 1980 addr += 4, i += 4) { 1981 1982 if (addr == page_end-4) { 1983 cmd_flags = BCE_NVM_COMMAND_LAST; 1984 } 1985 rc = bce_nvram_write_dword(sc, addr, 1986 &flash_buffer[i], cmd_flags); 1987 1988 if (rc != 0) 1989 goto nvram_write_end; 1990 1991 cmd_flags = 0; 1992 } 1993 } 1994 1995 /* Disable writes to flash interface (lock write-protect) */ 1996 bce_disable_nvram_write(sc); 1997 1998 /* Disable access to flash interface */ 1999 bce_disable_nvram_access(sc); 2000 bce_release_nvram_lock(sc); 2001 2002 /* Increment written */ 2003 written += data_end - data_start; 2004 } 2005 2006 nvram_write_end: 2007 if (align_start || align_end) 2008 free(buf, M_DEVBUF); 2009 2010 return rc; 2011 } 2012 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2013 2014 2015 /****************************************************************************/ 2016 /* Verifies that NVRAM is accessible and contains valid data. */ 2017 /* */ 2018 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2019 /* correct. */ 2020 /* */ 2021 /* Returns: */ 2022 /* 0 on success, positive value on failure. */ 2023 /****************************************************************************/ 2024 static int 2025 bce_nvram_test(struct bce_softc *sc) 2026 { 2027 u32 buf[BCE_NVRAM_SIZE / 4]; 2028 u8 *data = (u8 *) buf; 2029 int rc = 0; 2030 u32 magic, csum; 2031 2032 2033 /* 2034 * Check that the device NVRAM is valid by reading 2035 * the magic value at offset 0. 2036 */ 2037 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) 2038 goto bce_nvram_test_done; 2039 2040 2041 magic = bce_be32toh(buf[0]); 2042 if (magic != BCE_NVRAM_MAGIC) { 2043 rc = ENODEV; 2044 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, " 2045 "Found: 0x%08X\n", 2046 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2047 goto bce_nvram_test_done; 2048 } 2049 2050 /* 2051 * Verify that the device NVRAM includes valid 2052 * configuration data. 2053 */ 2054 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) 2055 goto bce_nvram_test_done; 2056 2057 csum = ether_crc32_le(data, 0x100); 2058 if (csum != BCE_CRC32_RESIDUAL) { 2059 rc = ENODEV; 2060 BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! " 2061 "Expected: 0x%08X, Found: 0x%08X\n", 2062 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2063 goto bce_nvram_test_done; 2064 } 2065 2066 csum = ether_crc32_le(data + 0x100, 0x100); 2067 if (csum != BCE_CRC32_RESIDUAL) { 2068 BCE_PRINTF("%s(%d): Invalid Feature Configuration Information " 2069 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2070 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2071 rc = ENODEV; 2072 } 2073 2074 bce_nvram_test_done: 2075 return rc; 2076 } 2077 2078 2079 /****************************************************************************/ 2080 /* Free any DMA memory owned by the driver. */ 2081 /* */ 2082 /* Scans through each data structre that requires DMA memory and frees */ 2083 /* the memory if allocated. */ 2084 /* */ 2085 /* Returns: */ 2086 /* Nothing. */ 2087 /****************************************************************************/ 2088 static void 2089 bce_dma_free(struct bce_softc *sc) 2090 { 2091 int i; 2092 2093 DBPRINT(sc,BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2094 2095 /* Destroy the status block. */ 2096 if (sc->status_block != NULL) 2097 bus_dmamem_free( 2098 sc->status_tag, 2099 sc->status_block, 2100 sc->status_map); 2101 2102 if (sc->status_map != NULL) { 2103 bus_dmamap_unload( 2104 sc->status_tag, 2105 sc->status_map); 2106 bus_dmamap_destroy(sc->status_tag, 2107 sc->status_map); 2108 } 2109 2110 if (sc->status_tag != NULL) 2111 bus_dma_tag_destroy(sc->status_tag); 2112 2113 2114 /* Destroy the statistics block. */ 2115 if (sc->stats_block != NULL) 2116 bus_dmamem_free( 2117 sc->stats_tag, 2118 sc->stats_block, 2119 sc->stats_map); 2120 2121 if (sc->stats_map != NULL) { 2122 bus_dmamap_unload( 2123 sc->stats_tag, 2124 sc->stats_map); 2125 bus_dmamap_destroy(sc->stats_tag, 2126 sc->stats_map); 2127 } 2128 2129 if (sc->stats_tag != NULL) 2130 bus_dma_tag_destroy(sc->stats_tag); 2131 2132 2133 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2134 for (i = 0; i < TX_PAGES; i++ ) { 2135 if (sc->tx_bd_chain[i] != NULL) 2136 bus_dmamem_free( 2137 sc->tx_bd_chain_tag, 2138 sc->tx_bd_chain[i], 2139 sc->tx_bd_chain_map[i]); 2140 2141 if (sc->tx_bd_chain_map[i] != NULL) { 2142 bus_dmamap_unload( 2143 sc->tx_bd_chain_tag, 2144 sc->tx_bd_chain_map[i]); 2145 bus_dmamap_destroy( 2146 sc->tx_bd_chain_tag, 2147 sc->tx_bd_chain_map[i]); 2148 } 2149 2150 } 2151 2152 /* Destroy the TX buffer descriptor tag. */ 2153 if (sc->tx_bd_chain_tag != NULL) 2154 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2155 2156 2157 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2158 for (i = 0; i < RX_PAGES; i++ ) { 2159 if (sc->rx_bd_chain[i] != NULL) 2160 bus_dmamem_free( 2161 sc->rx_bd_chain_tag, 2162 sc->rx_bd_chain[i], 2163 sc->rx_bd_chain_map[i]); 2164 2165 if (sc->rx_bd_chain_map[i] != NULL) { 2166 bus_dmamap_unload( 2167 sc->rx_bd_chain_tag, 2168 sc->rx_bd_chain_map[i]); 2169 bus_dmamap_destroy( 2170 sc->rx_bd_chain_tag, 2171 sc->rx_bd_chain_map[i]); 2172 } 2173 } 2174 2175 /* Destroy the RX buffer descriptor tag. */ 2176 if (sc->rx_bd_chain_tag != NULL) 2177 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2178 2179 2180 /* Unload and destroy the TX mbuf maps. */ 2181 for (i = 0; i < TOTAL_TX_BD; i++) { 2182 if (sc->tx_mbuf_map[i] != NULL) { 2183 bus_dmamap_unload(sc->tx_mbuf_tag, 2184 sc->tx_mbuf_map[i]); 2185 bus_dmamap_destroy(sc->tx_mbuf_tag, 2186 sc->tx_mbuf_map[i]); 2187 } 2188 } 2189 2190 /* Destroy the TX mbuf tag. */ 2191 if (sc->tx_mbuf_tag != NULL) 2192 bus_dma_tag_destroy(sc->tx_mbuf_tag); 2193 2194 2195 /* Unload and destroy the RX mbuf maps. */ 2196 for (i = 0; i < TOTAL_RX_BD; i++) { 2197 if (sc->rx_mbuf_map[i] != NULL) { 2198 bus_dmamap_unload(sc->rx_mbuf_tag, 2199 sc->rx_mbuf_map[i]); 2200 bus_dmamap_destroy(sc->rx_mbuf_tag, 2201 sc->rx_mbuf_map[i]); 2202 } 2203 } 2204 2205 /* Destroy the RX mbuf tag. */ 2206 if (sc->rx_mbuf_tag != NULL) 2207 bus_dma_tag_destroy(sc->rx_mbuf_tag); 2208 2209 2210 /* Destroy the parent tag */ 2211 if (sc->parent_tag != NULL) 2212 bus_dma_tag_destroy(sc->parent_tag); 2213 2214 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2215 2216 } 2217 2218 2219 /****************************************************************************/ 2220 /* Get DMA memory from the OS. */ 2221 /* */ 2222 /* Validates that the OS has provided DMA buffers in response to a */ 2223 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 2224 /* When the callback is used the OS will return 0 for the mapping function */ 2225 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 2226 /* failures back to the caller. */ 2227 /* */ 2228 /* Returns: */ 2229 /* Nothing. */ 2230 /****************************************************************************/ 2231 static void 2232 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2233 { 2234 bus_addr_t *busaddr = arg; 2235 2236 /* Simulate a mapping failure. */ 2237 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure), 2238 printf("bce: %s(%d): Simulating DMA mapping error.\n", 2239 __FILE__, __LINE__); 2240 error = ENOMEM); 2241 2242 /* Check for an error and signal the caller that an error occurred. */ 2243 if (error) { 2244 printf("bce %s(%d): DMA mapping error! error = %d, " 2245 "nseg = %d\n", __FILE__, __LINE__, error, nseg); 2246 *busaddr = 0; 2247 return; 2248 } 2249 2250 *busaddr = segs->ds_addr; 2251 return; 2252 } 2253 2254 2255 /****************************************************************************/ 2256 /* Allocate any DMA memory needed by the driver. */ 2257 /* */ 2258 /* Allocates DMA memory needed for the various global structures needed by */ 2259 /* hardware. */ 2260 /* */ 2261 /* Returns: */ 2262 /* 0 for success, positive value for failure. */ 2263 /****************************************************************************/ 2264 static int 2265 bce_dma_alloc(device_t dev) 2266 { 2267 struct bce_softc *sc; 2268 int i, error, rc = 0; 2269 bus_addr_t busaddr; 2270 bus_size_t max_size, max_seg_size; 2271 int max_segments; 2272 2273 sc = device_get_softc(dev); 2274 2275 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2276 2277 /* 2278 * Allocate the parent bus DMA tag appropriate for PCI. 2279 */ 2280 if (bus_dma_tag_create(NULL, 2281 1, 2282 BCE_DMA_BOUNDARY, 2283 sc->max_bus_addr, 2284 BUS_SPACE_MAXADDR, 2285 NULL, NULL, 2286 MAXBSIZE, 2287 BUS_SPACE_UNRESTRICTED, 2288 BUS_SPACE_MAXSIZE_32BIT, 2289 0, 2290 NULL, NULL, 2291 &sc->parent_tag)) { 2292 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 2293 __FILE__, __LINE__); 2294 rc = ENOMEM; 2295 goto bce_dma_alloc_exit; 2296 } 2297 2298 /* 2299 * Create a DMA tag for the status block, allocate and clear the 2300 * memory, map the memory into DMA space, and fetch the physical 2301 * address of the block. 2302 */ 2303 if (bus_dma_tag_create(sc->parent_tag, 2304 BCE_DMA_ALIGN, 2305 BCE_DMA_BOUNDARY, 2306 sc->max_bus_addr, 2307 BUS_SPACE_MAXADDR, 2308 NULL, NULL, 2309 BCE_STATUS_BLK_SZ, 2310 1, 2311 BCE_STATUS_BLK_SZ, 2312 0, 2313 NULL, NULL, 2314 &sc->status_tag)) { 2315 BCE_PRINTF("%s(%d): Could not allocate status block DMA tag!\n", 2316 __FILE__, __LINE__); 2317 rc = ENOMEM; 2318 goto bce_dma_alloc_exit; 2319 } 2320 2321 if(bus_dmamem_alloc(sc->status_tag, 2322 (void **)&sc->status_block, 2323 BUS_DMA_NOWAIT, 2324 &sc->status_map)) { 2325 BCE_PRINTF("%s(%d): Could not allocate status block DMA memory!\n", 2326 __FILE__, __LINE__); 2327 rc = ENOMEM; 2328 goto bce_dma_alloc_exit; 2329 } 2330 2331 bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 2332 2333 error = bus_dmamap_load(sc->status_tag, 2334 sc->status_map, 2335 sc->status_block, 2336 BCE_STATUS_BLK_SZ, 2337 bce_dma_map_addr, 2338 &busaddr, 2339 BUS_DMA_NOWAIT); 2340 2341 if (error) { 2342 BCE_PRINTF("%s(%d): Could not map status block DMA memory!\n", 2343 __FILE__, __LINE__); 2344 rc = ENOMEM; 2345 goto bce_dma_alloc_exit; 2346 } 2347 2348 sc->status_block_paddr = busaddr; 2349 /* DRC - Fix for 64 bit addresses. */ 2350 DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n", 2351 (u32) sc->status_block_paddr); 2352 2353 /* 2354 * Create a DMA tag for the statistics block, allocate and clear the 2355 * memory, map the memory into DMA space, and fetch the physical 2356 * address of the block. 2357 */ 2358 if (bus_dma_tag_create(sc->parent_tag, 2359 BCE_DMA_ALIGN, 2360 BCE_DMA_BOUNDARY, 2361 sc->max_bus_addr, 2362 BUS_SPACE_MAXADDR, 2363 NULL, NULL, 2364 BCE_STATS_BLK_SZ, 2365 1, 2366 BCE_STATS_BLK_SZ, 2367 0, 2368 NULL, NULL, 2369 &sc->stats_tag)) { 2370 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA tag!\n", 2371 __FILE__, __LINE__); 2372 rc = ENOMEM; 2373 goto bce_dma_alloc_exit; 2374 } 2375 2376 if (bus_dmamem_alloc(sc->stats_tag, 2377 (void **)&sc->stats_block, 2378 BUS_DMA_NOWAIT, 2379 &sc->stats_map)) { 2380 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA memory!\n", 2381 __FILE__, __LINE__); 2382 rc = ENOMEM; 2383 goto bce_dma_alloc_exit; 2384 } 2385 2386 bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 2387 2388 error = bus_dmamap_load(sc->stats_tag, 2389 sc->stats_map, 2390 sc->stats_block, 2391 BCE_STATS_BLK_SZ, 2392 bce_dma_map_addr, 2393 &busaddr, 2394 BUS_DMA_NOWAIT); 2395 2396 if(error) { 2397 BCE_PRINTF("%s(%d): Could not map statistics block DMA memory!\n", 2398 __FILE__, __LINE__); 2399 rc = ENOMEM; 2400 goto bce_dma_alloc_exit; 2401 } 2402 2403 sc->stats_block_paddr = busaddr; 2404 /* DRC - Fix for 64 bit address. */ 2405 DBPRINT(sc,BCE_INFO, "stats_block_paddr = 0x%08X\n", 2406 (u32) sc->stats_block_paddr); 2407 2408 /* 2409 * Create a DMA tag for the TX buffer descriptor chain, 2410 * allocate and clear the memory, and fetch the 2411 * physical address of the block. 2412 */ 2413 if(bus_dma_tag_create(sc->parent_tag, 2414 BCM_PAGE_SIZE, 2415 BCE_DMA_BOUNDARY, 2416 sc->max_bus_addr, 2417 BUS_SPACE_MAXADDR, 2418 NULL, NULL, 2419 BCE_TX_CHAIN_PAGE_SZ, 2420 1, 2421 BCE_TX_CHAIN_PAGE_SZ, 2422 0, 2423 NULL, NULL, 2424 &sc->tx_bd_chain_tag)) { 2425 BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain DMA tag!\n", 2426 __FILE__, __LINE__); 2427 rc = ENOMEM; 2428 goto bce_dma_alloc_exit; 2429 } 2430 2431 for (i = 0; i < TX_PAGES; i++) { 2432 2433 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 2434 (void **)&sc->tx_bd_chain[i], 2435 BUS_DMA_NOWAIT, 2436 &sc->tx_bd_chain_map[i])) { 2437 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 2438 "chain DMA memory!\n", __FILE__, __LINE__); 2439 rc = ENOMEM; 2440 goto bce_dma_alloc_exit; 2441 } 2442 2443 error = bus_dmamap_load(sc->tx_bd_chain_tag, 2444 sc->tx_bd_chain_map[i], 2445 sc->tx_bd_chain[i], 2446 BCE_TX_CHAIN_PAGE_SZ, 2447 bce_dma_map_addr, 2448 &busaddr, 2449 BUS_DMA_NOWAIT); 2450 2451 if (error) { 2452 BCE_PRINTF("%s(%d): Could not map TX descriptor chain DMA memory!\n", 2453 __FILE__, __LINE__); 2454 rc = ENOMEM; 2455 goto bce_dma_alloc_exit; 2456 } 2457 2458 sc->tx_bd_chain_paddr[i] = busaddr; 2459 /* DRC - Fix for 64 bit systems. */ 2460 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2461 i, (u32) sc->tx_bd_chain_paddr[i]); 2462 } 2463 2464 /* Check the required size before mapping to conserve resources. */ 2465 if (bce_tso_enable) { 2466 max_size = BCE_TSO_MAX_SIZE; 2467 max_segments = BCE_MAX_SEGMENTS; 2468 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 2469 } else { 2470 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 2471 max_segments = BCE_MAX_SEGMENTS; 2472 max_seg_size = MCLBYTES; 2473 } 2474 2475 /* Create a DMA tag for TX mbufs. */ 2476 if (bus_dma_tag_create(sc->parent_tag, 2477 1, 2478 BCE_DMA_BOUNDARY, 2479 sc->max_bus_addr, 2480 BUS_SPACE_MAXADDR, 2481 NULL, NULL, 2482 max_size, 2483 max_segments, 2484 max_seg_size, 2485 0, 2486 NULL, NULL, 2487 &sc->tx_mbuf_tag)) { 2488 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 2489 __FILE__, __LINE__); 2490 rc = ENOMEM; 2491 goto bce_dma_alloc_exit; 2492 } 2493 2494 /* Create DMA maps for the TX mbufs clusters. */ 2495 for (i = 0; i < TOTAL_TX_BD; i++) { 2496 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 2497 &sc->tx_mbuf_map[i])) { 2498 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA map!\n", 2499 __FILE__, __LINE__); 2500 rc = ENOMEM; 2501 goto bce_dma_alloc_exit; 2502 } 2503 } 2504 2505 /* 2506 * Create a DMA tag for the RX buffer descriptor chain, 2507 * allocate and clear the memory, and fetch the physical 2508 * address of the blocks. 2509 */ 2510 if (bus_dma_tag_create(sc->parent_tag, 2511 BCM_PAGE_SIZE, 2512 BCE_DMA_BOUNDARY, 2513 BUS_SPACE_MAXADDR, 2514 sc->max_bus_addr, 2515 NULL, NULL, 2516 BCE_RX_CHAIN_PAGE_SZ, 2517 1, 2518 BCE_RX_CHAIN_PAGE_SZ, 2519 0, 2520 NULL, NULL, 2521 &sc->rx_bd_chain_tag)) { 2522 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain DMA tag!\n", 2523 __FILE__, __LINE__); 2524 rc = ENOMEM; 2525 goto bce_dma_alloc_exit; 2526 } 2527 2528 for (i = 0; i < RX_PAGES; i++) { 2529 2530 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 2531 (void **)&sc->rx_bd_chain[i], 2532 BUS_DMA_NOWAIT, 2533 &sc->rx_bd_chain_map[i])) { 2534 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 2535 "DMA memory!\n", __FILE__, __LINE__); 2536 rc = ENOMEM; 2537 goto bce_dma_alloc_exit; 2538 } 2539 2540 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 2541 2542 error = bus_dmamap_load(sc->rx_bd_chain_tag, 2543 sc->rx_bd_chain_map[i], 2544 sc->rx_bd_chain[i], 2545 BCE_RX_CHAIN_PAGE_SZ, 2546 bce_dma_map_addr, 2547 &busaddr, 2548 BUS_DMA_NOWAIT); 2549 2550 if (error) { 2551 BCE_PRINTF("%s(%d): Could not map RX descriptor chain DMA memory!\n", 2552 __FILE__, __LINE__); 2553 rc = ENOMEM; 2554 goto bce_dma_alloc_exit; 2555 } 2556 2557 sc->rx_bd_chain_paddr[i] = busaddr; 2558 /* DRC - Fix for 64 bit systems. */ 2559 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2560 i, (u32) sc->rx_bd_chain_paddr[i]); 2561 } 2562 2563 /* 2564 * Create a DMA tag for RX mbufs. 2565 */ 2566 if (bus_dma_tag_create(sc->parent_tag, 2567 1, 2568 BCE_DMA_BOUNDARY, 2569 sc->max_bus_addr, 2570 BUS_SPACE_MAXADDR, 2571 NULL, NULL, 2572 MJUM9BYTES, 2573 BCE_MAX_SEGMENTS, 2574 MJUM9BYTES, 2575 0, 2576 NULL, NULL, 2577 &sc->rx_mbuf_tag)) { 2578 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 2579 __FILE__, __LINE__); 2580 rc = ENOMEM; 2581 goto bce_dma_alloc_exit; 2582 } 2583 2584 /* Create DMA maps for the RX mbuf clusters. */ 2585 for (i = 0; i < TOTAL_RX_BD; i++) { 2586 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 2587 &sc->rx_mbuf_map[i])) { 2588 BCE_PRINTF("%s(%d): Unable to create RX mbuf DMA map!\n", 2589 __FILE__, __LINE__); 2590 rc = ENOMEM; 2591 goto bce_dma_alloc_exit; 2592 } 2593 } 2594 2595 bce_dma_alloc_exit: 2596 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2597 2598 return(rc); 2599 } 2600 2601 2602 /****************************************************************************/ 2603 /* Release all resources used by the driver. */ 2604 /* */ 2605 /* Releases all resources acquired by the driver including interrupts, */ 2606 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2607 /* */ 2608 /* Returns: */ 2609 /* Nothing. */ 2610 /****************************************************************************/ 2611 static void 2612 bce_release_resources(struct bce_softc *sc) 2613 { 2614 device_t dev; 2615 2616 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2617 2618 dev = sc->bce_dev; 2619 2620 bce_dma_free(sc); 2621 2622 if (sc->bce_intrhand != NULL) { 2623 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 2624 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 2625 } 2626 2627 if (sc->bce_res_irq != NULL) { 2628 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 2629 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0, 2630 sc->bce_res_irq); 2631 } 2632 2633 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 2634 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI vector.\n"); 2635 pci_release_msi(dev); 2636 } 2637 2638 if (sc->bce_res_mem != NULL) { 2639 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 2640 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bce_res_mem); 2641 } 2642 2643 if (sc->bce_ifp != NULL) { 2644 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 2645 if_free(sc->bce_ifp); 2646 } 2647 2648 if (mtx_initialized(&sc->bce_mtx)) 2649 BCE_LOCK_DESTROY(sc); 2650 2651 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2652 2653 } 2654 2655 2656 /****************************************************************************/ 2657 /* Firmware synchronization. */ 2658 /* */ 2659 /* Before performing certain events such as a chip reset, synchronize with */ 2660 /* the firmware first. */ 2661 /* */ 2662 /* Returns: */ 2663 /* 0 for success, positive value for failure. */ 2664 /****************************************************************************/ 2665 static int 2666 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 2667 { 2668 int i, rc = 0; 2669 u32 val; 2670 2671 /* Don't waste any time if we've timed out before. */ 2672 if (sc->bce_fw_timed_out) { 2673 rc = EBUSY; 2674 goto bce_fw_sync_exit; 2675 } 2676 2677 /* Increment the message sequence number. */ 2678 sc->bce_fw_wr_seq++; 2679 msg_data |= sc->bce_fw_wr_seq; 2680 2681 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data); 2682 2683 /* Send the message to the bootcode driver mailbox. */ 2684 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2685 2686 /* Wait for the bootcode to acknowledge the message. */ 2687 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2688 /* Check for a response in the bootcode firmware mailbox. */ 2689 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB); 2690 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 2691 break; 2692 DELAY(1000); 2693 } 2694 2695 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2696 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 2697 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 2698 2699 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 2700 "msg_data = 0x%08X\n", 2701 __FILE__, __LINE__, msg_data); 2702 2703 msg_data &= ~BCE_DRV_MSG_CODE; 2704 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 2705 2706 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2707 2708 sc->bce_fw_timed_out = 1; 2709 rc = EBUSY; 2710 } 2711 2712 bce_fw_sync_exit: 2713 return (rc); 2714 } 2715 2716 2717 /****************************************************************************/ 2718 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2719 /* */ 2720 /* Returns: */ 2721 /* Nothing. */ 2722 /****************************************************************************/ 2723 static void 2724 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 2725 u32 rv2p_code_len, u32 rv2p_proc) 2726 { 2727 int i; 2728 u32 val; 2729 2730 for (i = 0; i < rv2p_code_len; i += 8) { 2731 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 2732 rv2p_code++; 2733 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 2734 rv2p_code++; 2735 2736 if (rv2p_proc == RV2P_PROC1) { 2737 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 2738 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 2739 } 2740 else { 2741 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 2742 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 2743 } 2744 } 2745 2746 /* Reset the processor, un-stall is done later. */ 2747 if (rv2p_proc == RV2P_PROC1) { 2748 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 2749 } 2750 else { 2751 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 2752 } 2753 } 2754 2755 2756 /****************************************************************************/ 2757 /* Load RISC processor firmware. */ 2758 /* */ 2759 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 2760 /* associated with a particular processor. */ 2761 /* */ 2762 /* Returns: */ 2763 /* Nothing. */ 2764 /****************************************************************************/ 2765 static void 2766 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 2767 struct fw_info *fw) 2768 { 2769 u32 offset; 2770 u32 val; 2771 2772 /* Halt the CPU. */ 2773 val = REG_RD_IND(sc, cpu_reg->mode); 2774 val |= cpu_reg->mode_value_halt; 2775 REG_WR_IND(sc, cpu_reg->mode, val); 2776 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2777 2778 /* Load the Text area. */ 2779 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2780 if (fw->text) { 2781 int j; 2782 2783 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 2784 REG_WR_IND(sc, offset, fw->text[j]); 2785 } 2786 } 2787 2788 /* Load the Data area. */ 2789 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2790 if (fw->data) { 2791 int j; 2792 2793 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 2794 REG_WR_IND(sc, offset, fw->data[j]); 2795 } 2796 } 2797 2798 /* Load the SBSS area. */ 2799 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2800 if (fw->sbss) { 2801 int j; 2802 2803 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 2804 REG_WR_IND(sc, offset, fw->sbss[j]); 2805 } 2806 } 2807 2808 /* Load the BSS area. */ 2809 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2810 if (fw->bss) { 2811 int j; 2812 2813 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 2814 REG_WR_IND(sc, offset, fw->bss[j]); 2815 } 2816 } 2817 2818 /* Load the Read-Only area. */ 2819 offset = cpu_reg->spad_base + 2820 (fw->rodata_addr - cpu_reg->mips_view_base); 2821 if (fw->rodata) { 2822 int j; 2823 2824 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 2825 REG_WR_IND(sc, offset, fw->rodata[j]); 2826 } 2827 } 2828 2829 /* Clear the pre-fetch instruction. */ 2830 REG_WR_IND(sc, cpu_reg->inst, 0); 2831 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2832 2833 /* Start the CPU. */ 2834 val = REG_RD_IND(sc, cpu_reg->mode); 2835 val &= ~cpu_reg->mode_value_halt; 2836 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2837 REG_WR_IND(sc, cpu_reg->mode, val); 2838 } 2839 2840 2841 /****************************************************************************/ 2842 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2843 /* */ 2844 /* Loads the firmware for each CPU and starts the CPU. */ 2845 /* */ 2846 /* Returns: */ 2847 /* Nothing. */ 2848 /****************************************************************************/ 2849 static void 2850 bce_init_cpus(struct bce_softc *sc) 2851 { 2852 struct cpu_reg cpu_reg; 2853 struct fw_info fw; 2854 2855 /* Initialize the RV2P processor. */ 2856 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1); 2857 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2); 2858 2859 /* Initialize the RX Processor. */ 2860 cpu_reg.mode = BCE_RXP_CPU_MODE; 2861 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 2862 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 2863 cpu_reg.state = BCE_RXP_CPU_STATE; 2864 cpu_reg.state_value_clear = 0xffffff; 2865 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 2866 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 2867 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 2868 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 2869 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 2870 cpu_reg.spad_base = BCE_RXP_SCRATCH; 2871 cpu_reg.mips_view_base = 0x8000000; 2872 2873 fw.ver_major = bce_RXP_b06FwReleaseMajor; 2874 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 2875 fw.ver_fix = bce_RXP_b06FwReleaseFix; 2876 fw.start_addr = bce_RXP_b06FwStartAddr; 2877 2878 fw.text_addr = bce_RXP_b06FwTextAddr; 2879 fw.text_len = bce_RXP_b06FwTextLen; 2880 fw.text_index = 0; 2881 fw.text = bce_RXP_b06FwText; 2882 2883 fw.data_addr = bce_RXP_b06FwDataAddr; 2884 fw.data_len = bce_RXP_b06FwDataLen; 2885 fw.data_index = 0; 2886 fw.data = bce_RXP_b06FwData; 2887 2888 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 2889 fw.sbss_len = bce_RXP_b06FwSbssLen; 2890 fw.sbss_index = 0; 2891 fw.sbss = bce_RXP_b06FwSbss; 2892 2893 fw.bss_addr = bce_RXP_b06FwBssAddr; 2894 fw.bss_len = bce_RXP_b06FwBssLen; 2895 fw.bss_index = 0; 2896 fw.bss = bce_RXP_b06FwBss; 2897 2898 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 2899 fw.rodata_len = bce_RXP_b06FwRodataLen; 2900 fw.rodata_index = 0; 2901 fw.rodata = bce_RXP_b06FwRodata; 2902 2903 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 2904 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2905 2906 /* Initialize the TX Processor. */ 2907 cpu_reg.mode = BCE_TXP_CPU_MODE; 2908 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 2909 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 2910 cpu_reg.state = BCE_TXP_CPU_STATE; 2911 cpu_reg.state_value_clear = 0xffffff; 2912 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 2913 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 2914 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 2915 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 2916 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 2917 cpu_reg.spad_base = BCE_TXP_SCRATCH; 2918 cpu_reg.mips_view_base = 0x8000000; 2919 2920 fw.ver_major = bce_TXP_b06FwReleaseMajor; 2921 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 2922 fw.ver_fix = bce_TXP_b06FwReleaseFix; 2923 fw.start_addr = bce_TXP_b06FwStartAddr; 2924 2925 fw.text_addr = bce_TXP_b06FwTextAddr; 2926 fw.text_len = bce_TXP_b06FwTextLen; 2927 fw.text_index = 0; 2928 fw.text = bce_TXP_b06FwText; 2929 2930 fw.data_addr = bce_TXP_b06FwDataAddr; 2931 fw.data_len = bce_TXP_b06FwDataLen; 2932 fw.data_index = 0; 2933 fw.data = bce_TXP_b06FwData; 2934 2935 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 2936 fw.sbss_len = bce_TXP_b06FwSbssLen; 2937 fw.sbss_index = 0; 2938 fw.sbss = bce_TXP_b06FwSbss; 2939 2940 fw.bss_addr = bce_TXP_b06FwBssAddr; 2941 fw.bss_len = bce_TXP_b06FwBssLen; 2942 fw.bss_index = 0; 2943 fw.bss = bce_TXP_b06FwBss; 2944 2945 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 2946 fw.rodata_len = bce_TXP_b06FwRodataLen; 2947 fw.rodata_index = 0; 2948 fw.rodata = bce_TXP_b06FwRodata; 2949 2950 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 2951 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2952 2953 /* Initialize the TX Patch-up Processor. */ 2954 cpu_reg.mode = BCE_TPAT_CPU_MODE; 2955 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 2956 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 2957 cpu_reg.state = BCE_TPAT_CPU_STATE; 2958 cpu_reg.state_value_clear = 0xffffff; 2959 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 2960 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 2961 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 2962 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 2963 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 2964 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 2965 cpu_reg.mips_view_base = 0x8000000; 2966 2967 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 2968 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 2969 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 2970 fw.start_addr = bce_TPAT_b06FwStartAddr; 2971 2972 fw.text_addr = bce_TPAT_b06FwTextAddr; 2973 fw.text_len = bce_TPAT_b06FwTextLen; 2974 fw.text_index = 0; 2975 fw.text = bce_TPAT_b06FwText; 2976 2977 fw.data_addr = bce_TPAT_b06FwDataAddr; 2978 fw.data_len = bce_TPAT_b06FwDataLen; 2979 fw.data_index = 0; 2980 fw.data = bce_TPAT_b06FwData; 2981 2982 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 2983 fw.sbss_len = bce_TPAT_b06FwSbssLen; 2984 fw.sbss_index = 0; 2985 fw.sbss = bce_TPAT_b06FwSbss; 2986 2987 fw.bss_addr = bce_TPAT_b06FwBssAddr; 2988 fw.bss_len = bce_TPAT_b06FwBssLen; 2989 fw.bss_index = 0; 2990 fw.bss = bce_TPAT_b06FwBss; 2991 2992 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 2993 fw.rodata_len = bce_TPAT_b06FwRodataLen; 2994 fw.rodata_index = 0; 2995 fw.rodata = bce_TPAT_b06FwRodata; 2996 2997 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 2998 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2999 3000 /* Initialize the Completion Processor. */ 3001 cpu_reg.mode = BCE_COM_CPU_MODE; 3002 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 3003 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 3004 cpu_reg.state = BCE_COM_CPU_STATE; 3005 cpu_reg.state_value_clear = 0xffffff; 3006 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 3007 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 3008 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 3009 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 3010 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 3011 cpu_reg.spad_base = BCE_COM_SCRATCH; 3012 cpu_reg.mips_view_base = 0x8000000; 3013 3014 fw.ver_major = bce_COM_b06FwReleaseMajor; 3015 fw.ver_minor = bce_COM_b06FwReleaseMinor; 3016 fw.ver_fix = bce_COM_b06FwReleaseFix; 3017 fw.start_addr = bce_COM_b06FwStartAddr; 3018 3019 fw.text_addr = bce_COM_b06FwTextAddr; 3020 fw.text_len = bce_COM_b06FwTextLen; 3021 fw.text_index = 0; 3022 fw.text = bce_COM_b06FwText; 3023 3024 fw.data_addr = bce_COM_b06FwDataAddr; 3025 fw.data_len = bce_COM_b06FwDataLen; 3026 fw.data_index = 0; 3027 fw.data = bce_COM_b06FwData; 3028 3029 fw.sbss_addr = bce_COM_b06FwSbssAddr; 3030 fw.sbss_len = bce_COM_b06FwSbssLen; 3031 fw.sbss_index = 0; 3032 fw.sbss = bce_COM_b06FwSbss; 3033 3034 fw.bss_addr = bce_COM_b06FwBssAddr; 3035 fw.bss_len = bce_COM_b06FwBssLen; 3036 fw.bss_index = 0; 3037 fw.bss = bce_COM_b06FwBss; 3038 3039 fw.rodata_addr = bce_COM_b06FwRodataAddr; 3040 fw.rodata_len = bce_COM_b06FwRodataLen; 3041 fw.rodata_index = 0; 3042 fw.rodata = bce_COM_b06FwRodata; 3043 3044 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 3045 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3046 } 3047 3048 3049 /****************************************************************************/ 3050 /* Initialize context memory. */ 3051 /* */ 3052 /* Clears the memory associated with each Context ID (CID). */ 3053 /* */ 3054 /* Returns: */ 3055 /* Nothing. */ 3056 /****************************************************************************/ 3057 static void 3058 bce_init_context(struct bce_softc *sc) 3059 { 3060 u32 vcid; 3061 3062 vcid = 96; 3063 while (vcid) { 3064 u32 vcid_addr, pcid_addr, offset; 3065 3066 vcid--; 3067 3068 vcid_addr = GET_CID_ADDR(vcid); 3069 pcid_addr = vcid_addr; 3070 3071 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0x00); 3072 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 3073 3074 /* Zero out the context. */ 3075 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 3076 CTX_WR(sc, 0x00, offset, 0); 3077 } 3078 3079 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 3080 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 3081 } 3082 } 3083 3084 3085 /****************************************************************************/ 3086 /* Fetch the permanent MAC address of the controller. */ 3087 /* */ 3088 /* Returns: */ 3089 /* Nothing. */ 3090 /****************************************************************************/ 3091 static void 3092 bce_get_mac_addr(struct bce_softc *sc) 3093 { 3094 u32 mac_lo = 0, mac_hi = 0; 3095 3096 /* 3097 * The NetXtreme II bootcode populates various NIC 3098 * power-on and runtime configuration items in a 3099 * shared memory area. The factory configured MAC 3100 * address is available from both NVRAM and the 3101 * shared memory area so we'll read the value from 3102 * shared memory for speed. 3103 */ 3104 3105 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + 3106 BCE_PORT_HW_CFG_MAC_UPPER); 3107 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + 3108 BCE_PORT_HW_CFG_MAC_LOWER); 3109 3110 if ((mac_lo == 0) && (mac_hi == 0)) { 3111 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 3112 __FILE__, __LINE__); 3113 } else { 3114 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3115 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3116 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3117 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3118 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3119 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3120 } 3121 3122 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet address = %6D\n", sc->eaddr, ":"); 3123 } 3124 3125 3126 /****************************************************************************/ 3127 /* Program the MAC address. */ 3128 /* */ 3129 /* Returns: */ 3130 /* Nothing. */ 3131 /****************************************************************************/ 3132 static void 3133 bce_set_mac_addr(struct bce_softc *sc) 3134 { 3135 u32 val; 3136 u8 *mac_addr = sc->eaddr; 3137 3138 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = %6D\n", sc->eaddr, ":"); 3139 3140 val = (mac_addr[0] << 8) | mac_addr[1]; 3141 3142 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 3143 3144 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3145 (mac_addr[4] << 8) | mac_addr[5]; 3146 3147 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 3148 } 3149 3150 3151 /****************************************************************************/ 3152 /* Stop the controller. */ 3153 /* */ 3154 /* Returns: */ 3155 /* Nothing. */ 3156 /****************************************************************************/ 3157 static void 3158 bce_stop(struct bce_softc *sc) 3159 { 3160 struct ifnet *ifp; 3161 struct ifmedia_entry *ifm; 3162 struct mii_data *mii = NULL; 3163 int mtmp, itmp; 3164 3165 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3166 3167 BCE_LOCK_ASSERT(sc); 3168 3169 ifp = sc->bce_ifp; 3170 3171 mii = device_get_softc(sc->bce_miibus); 3172 3173 callout_stop(&sc->bce_tick_callout); 3174 3175 /* Disable the transmit/receive blocks. */ 3176 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3177 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3178 DELAY(20); 3179 3180 bce_disable_intr(sc); 3181 3182 /* Free RX buffers. */ 3183 bce_free_rx_chain(sc); 3184 3185 /* Free TX buffers. */ 3186 bce_free_tx_chain(sc); 3187 3188 /* 3189 * Isolate/power down the PHY, but leave the media selection 3190 * unchanged so that things will be put back to normal when 3191 * we bring the interface back up. 3192 */ 3193 3194 itmp = ifp->if_flags; 3195 ifp->if_flags |= IFF_UP; 3196 3197 /* If we are called from bce_detach(), mii is already NULL. */ 3198 if (mii != NULL) { 3199 ifm = mii->mii_media.ifm_cur; 3200 mtmp = ifm->ifm_media; 3201 ifm->ifm_media = IFM_ETHER | IFM_NONE; 3202 mii_mediachg(mii); 3203 ifm->ifm_media = mtmp; 3204 } 3205 3206 ifp->if_flags = itmp; 3207 sc->watchdog_timer = 0; 3208 3209 sc->bce_link = 0; 3210 3211 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3212 3213 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3214 } 3215 3216 3217 static int 3218 bce_reset(struct bce_softc *sc, u32 reset_code) 3219 { 3220 u32 val; 3221 int i, rc = 0; 3222 3223 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 3224 __FUNCTION__, reset_code); 3225 3226 /* Wait for pending PCI transactions to complete. */ 3227 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 3228 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3229 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3230 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3231 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3232 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3233 DELAY(5); 3234 3235 /* Assume bootcode is running. */ 3236 sc->bce_fw_timed_out = 0; 3237 3238 /* Give the firmware a chance to prepare for the reset. */ 3239 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 3240 if (rc) 3241 goto bce_reset_exit; 3242 3243 /* Set a firmware reminder that this is a soft reset. */ 3244 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE, 3245 BCE_DRV_RESET_SIGNATURE_MAGIC); 3246 3247 /* Dummy read to force the chip to complete all current transactions. */ 3248 val = REG_RD(sc, BCE_MISC_ID); 3249 3250 /* Chip reset. */ 3251 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3252 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3253 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3254 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 3255 3256 /* Allow up to 30us for reset to complete. */ 3257 for (i = 0; i < 10; i++) { 3258 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 3259 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3260 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3261 break; 3262 } 3263 DELAY(10); 3264 } 3265 3266 /* Check that reset completed successfully. */ 3267 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3268 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3269 BCE_PRINTF("%s(%d): Reset failed!\n", 3270 __FILE__, __LINE__); 3271 rc = EBUSY; 3272 goto bce_reset_exit; 3273 } 3274 3275 /* Make sure byte swapping is properly configured. */ 3276 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 3277 if (val != 0x01020304) { 3278 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 3279 __FILE__, __LINE__); 3280 rc = ENODEV; 3281 goto bce_reset_exit; 3282 } 3283 3284 /* Just completed a reset, assume that firmware is running again. */ 3285 sc->bce_fw_timed_out = 0; 3286 3287 /* Wait for the firmware to finish its initialization. */ 3288 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 3289 if (rc) 3290 BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n", 3291 __FILE__, __LINE__); 3292 3293 bce_reset_exit: 3294 return (rc); 3295 } 3296 3297 3298 static int 3299 bce_chipinit(struct bce_softc *sc) 3300 { 3301 u32 val; 3302 int rc = 0; 3303 3304 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3305 3306 /* Make sure the interrupt is not active. */ 3307 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 3308 3309 /* 3310 * Initialize DMA byte/word swapping, configure the number of DMA 3311 * channels and PCI clock compensation delay. 3312 */ 3313 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 3314 BCE_DMA_CONFIG_DATA_WORD_SWAP | 3315 #if BYTE_ORDER == BIG_ENDIAN 3316 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 3317 #endif 3318 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 3319 DMA_READ_CHANS << 12 | 3320 DMA_WRITE_CHANS << 16; 3321 3322 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3323 3324 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3325 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 3326 3327 /* 3328 * This setting resolves a problem observed on certain Intel PCI 3329 * chipsets that cannot handle multiple outstanding DMA operations. 3330 * See errata E9_5706A1_65. 3331 */ 3332 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 3333 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 3334 !(sc->bce_flags & BCE_PCIX_FLAG)) 3335 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 3336 3337 REG_WR(sc, BCE_DMA_CONFIG, val); 3338 3339 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3340 if (sc->bce_flags & BCE_PCIX_FLAG) { 3341 u16 val; 3342 3343 val = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2); 3344 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, val & ~0x2, 2); 3345 } 3346 3347 /* Enable the RX_V2P and Context state machines before access. */ 3348 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 3349 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3350 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3351 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3352 3353 /* Initialize context mapping and zero out the quick contexts. */ 3354 bce_init_context(sc); 3355 3356 /* Initialize the on-boards CPUs */ 3357 bce_init_cpus(sc); 3358 3359 /* Prepare NVRAM for access. */ 3360 if (bce_init_nvram(sc)) { 3361 rc = ENODEV; 3362 goto bce_chipinit_exit; 3363 } 3364 3365 /* Set the kernel bypass block size */ 3366 val = REG_RD(sc, BCE_MQ_CONFIG); 3367 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3368 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3369 REG_WR(sc, BCE_MQ_CONFIG, val); 3370 3371 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 3372 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 3373 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 3374 3375 /* Set the page size and clear the RV2P processor stall bits. */ 3376 val = (BCM_PAGE_BITS - 8) << 24; 3377 REG_WR(sc, BCE_RV2P_CONFIG, val); 3378 3379 /* Configure page size. */ 3380 val = REG_RD(sc, BCE_TBDR_CONFIG); 3381 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 3382 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3383 REG_WR(sc, BCE_TBDR_CONFIG, val); 3384 3385 bce_chipinit_exit: 3386 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3387 3388 return(rc); 3389 } 3390 3391 3392 /****************************************************************************/ 3393 /* Initialize the controller in preparation to send/receive traffic. */ 3394 /* */ 3395 /* Returns: */ 3396 /* 0 for success, positive value for failure. */ 3397 /****************************************************************************/ 3398 static int 3399 bce_blockinit(struct bce_softc *sc) 3400 { 3401 u32 reg, val; 3402 int rc = 0; 3403 3404 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3405 3406 /* Load the hardware default MAC address. */ 3407 bce_set_mac_addr(sc); 3408 3409 /* Set the Ethernet backoff seed value */ 3410 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 3411 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 3412 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3413 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 3414 3415 sc->last_status_idx = 0; 3416 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 3417 3418 /* Set up link change interrupt generation. */ 3419 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 3420 3421 /* Program the physical address of the status block. */ 3422 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 3423 BCE_ADDR_LO(sc->status_block_paddr)); 3424 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 3425 BCE_ADDR_HI(sc->status_block_paddr)); 3426 3427 /* Program the physical address of the statistics block. */ 3428 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 3429 BCE_ADDR_LO(sc->stats_block_paddr)); 3430 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 3431 BCE_ADDR_HI(sc->stats_block_paddr)); 3432 3433 /* Program various host coalescing parameters. */ 3434 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 3435 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 3436 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 3437 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 3438 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 3439 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 3440 REG_WR(sc, BCE_HC_TX_TICKS, 3441 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 3442 REG_WR(sc, BCE_HC_RX_TICKS, 3443 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 3444 REG_WR(sc, BCE_HC_COM_TICKS, 3445 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 3446 REG_WR(sc, BCE_HC_CMD_TICKS, 3447 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 3448 REG_WR(sc, BCE_HC_STATS_TICKS, 3449 (sc->bce_stats_ticks & 0xffff00)); 3450 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 3451 0xbb8); /* 3ms */ 3452 REG_WR(sc, BCE_HC_CONFIG, 3453 (BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 3454 BCE_HC_CONFIG_COLLECT_STATS)); 3455 3456 /* Clear the internal statistics counters. */ 3457 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 3458 3459 /* Verify that bootcode is running. */ 3460 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE); 3461 3462 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure), 3463 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 3464 __FILE__, __LINE__); 3465 reg = 0); 3466 3467 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3468 BCE_DEV_INFO_SIGNATURE_MAGIC) { 3469 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 3470 "Expected: 08%08X\n", __FILE__, __LINE__, 3471 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 3472 BCE_DEV_INFO_SIGNATURE_MAGIC); 3473 rc = ENODEV; 3474 goto bce_blockinit_exit; 3475 } 3476 3477 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3478 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET); 3479 3480 /* Enable link state change interrupt generation. */ 3481 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3482 3483 /* Enable all remaining blocks in the MAC. */ 3484 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff); 3485 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 3486 DELAY(20); 3487 3488 bce_blockinit_exit: 3489 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3490 3491 return (rc); 3492 } 3493 3494 3495 /****************************************************************************/ 3496 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3497 /* */ 3498 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3499 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3500 /* necessary. */ 3501 /* */ 3502 /* Todo: Consider writing the hardware mailboxes here to make rx_bd's */ 3503 /* available to the hardware as soon as possible. */ 3504 /* */ 3505 /* Returns: */ 3506 /* 0 for success, positive value for failure. */ 3507 /****************************************************************************/ 3508 static int 3509 bce_get_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, u16 *chain_prod, 3510 u32 *prod_bseq) 3511 { 3512 bus_dmamap_t map; 3513 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 3514 struct mbuf *m_new = NULL; 3515 struct rx_bd *rxbd; 3516 int i, nsegs, error, rc = 0; 3517 #ifdef BCE_DEBUG 3518 u16 debug_chain_prod = *chain_prod; 3519 #endif 3520 3521 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Entering %s()\n", 3522 __FUNCTION__); 3523 3524 /* Make sure the inputs are valid. */ 3525 DBRUNIF((*chain_prod > MAX_RX_BD), 3526 BCE_PRINTF("%s(%d): RX producer out of range: 0x%04X > 0x%04X\n", 3527 __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD)); 3528 3529 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, " 3530 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3531 3532 /* Check whether this is a new mbuf allocation. */ 3533 if (m == NULL) { 3534 3535 /* Simulate an mbuf allocation failure. */ 3536 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure), 3537 sc->mbuf_alloc_failed++; 3538 sc->mbuf_sim_alloc_failed++; 3539 rc = ENOBUFS; 3540 goto bce_get_buf_exit); 3541 3542 /* This is a new mbuf allocation. */ 3543 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3544 if (m_new == NULL) { 3545 3546 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf header allocation failed!\n", 3547 __FILE__, __LINE__); 3548 3549 sc->mbuf_alloc_failed++; 3550 3551 rc = ENOBUFS; 3552 goto bce_get_buf_exit; 3553 } 3554 3555 DBRUNIF(1, sc->rx_mbuf_alloc++); 3556 3557 /* Simulate an mbuf cluster allocation failure. */ 3558 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure), 3559 m_freem(m_new); 3560 sc->rx_mbuf_alloc--; 3561 sc->mbuf_alloc_failed++; 3562 sc->mbuf_sim_alloc_failed++; 3563 rc = ENOBUFS; 3564 goto bce_get_buf_exit); 3565 3566 /* Attach a cluster to the mbuf. */ 3567 m_cljget(m_new, M_DONTWAIT, sc->mbuf_alloc_size); 3568 if (!(m_new->m_flags & M_EXT)) { 3569 3570 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf chain allocation failed!\n", 3571 __FILE__, __LINE__); 3572 3573 m_freem(m_new); 3574 DBRUNIF(1, sc->rx_mbuf_alloc--); 3575 3576 sc->mbuf_alloc_failed++; 3577 rc = ENOBUFS; 3578 goto bce_get_buf_exit; 3579 } 3580 3581 /* Initialize the mbuf cluster. */ 3582 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3583 } else { 3584 /* Reuse an existing mbuf. */ 3585 m_new = m; 3586 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3587 m_new->m_data = m_new->m_ext.ext_buf; 3588 } 3589 3590 /* Map the mbuf cluster into device memory. */ 3591 map = sc->rx_mbuf_map[*chain_prod]; 3592 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 3593 segs, &nsegs, BUS_DMA_NOWAIT); 3594 3595 /* Handle any mapping errors. */ 3596 if (error) { 3597 BCE_PRINTF("%s(%d): Error mapping mbuf into RX chain!\n", 3598 __FILE__, __LINE__); 3599 3600 m_freem(m_new); 3601 DBRUNIF(1, sc->rx_mbuf_alloc--); 3602 3603 rc = ENOBUFS; 3604 goto bce_get_buf_exit; 3605 } 3606 3607 /* Make sure there is room in the receive chain. */ 3608 if (nsegs > sc->free_rx_bd) { 3609 bus_dmamap_unload(sc->rx_mbuf_tag, map); 3610 3611 m_freem(m_new); 3612 DBRUNIF(1, sc->rx_mbuf_alloc--); 3613 3614 rc = EFBIG; 3615 goto bce_get_buf_exit; 3616 } 3617 3618 #ifdef BCE_DEBUG 3619 /* Track the distribution of buffer segments. */ 3620 sc->rx_mbuf_segs[nsegs]++; 3621 #endif 3622 3623 /* Update some debug statistic counters */ 3624 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3625 sc->rx_low_watermark = sc->free_rx_bd); 3626 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 3627 3628 /* Setup the rx_bd for the first segment. */ 3629 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3630 3631 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 3632 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 3633 rxbd->rx_bd_len = htole32(segs[0].ds_len); 3634 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3635 *prod_bseq += segs[0].ds_len; 3636 3637 for (i = 1; i < nsegs; i++) { 3638 3639 *prod = NEXT_RX_BD(*prod); 3640 *chain_prod = RX_CHAIN_IDX(*prod); 3641 3642 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3643 3644 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 3645 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 3646 rxbd->rx_bd_len = htole32(segs[i].ds_len); 3647 rxbd->rx_bd_flags = 0; 3648 *prod_bseq += segs[i].ds_len; 3649 } 3650 3651 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3652 3653 /* Save the mbuf and update our counter. */ 3654 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3655 sc->free_rx_bd -= nsegs; 3656 3657 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 3658 nsegs)); 3659 3660 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, " 3661 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3662 3663 bce_get_buf_exit: 3664 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Exiting %s()\n", 3665 __FUNCTION__); 3666 3667 return(rc); 3668 } 3669 3670 3671 /****************************************************************************/ 3672 /* Allocate memory and initialize the TX data structures. */ 3673 /* */ 3674 /* Returns: */ 3675 /* 0 for success, positive value for failure. */ 3676 /****************************************************************************/ 3677 static int 3678 bce_init_tx_chain(struct bce_softc *sc) 3679 { 3680 struct tx_bd *txbd; 3681 u32 val; 3682 int i, rc = 0; 3683 3684 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3685 3686 /* Set the initial TX producer/consumer indices. */ 3687 sc->tx_prod = 0; 3688 sc->tx_cons = 0; 3689 sc->tx_prod_bseq = 0; 3690 sc->used_tx_bd = 0; 3691 sc->max_tx_bd = USABLE_TX_BD; 3692 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3693 DBRUNIF(1, sc->tx_full_count = 0); 3694 3695 /* 3696 * The NetXtreme II supports a linked-list structre called 3697 * a Buffer Descriptor Chain (or BD chain). A BD chain 3698 * consists of a series of 1 or more chain pages, each of which 3699 * consists of a fixed number of BD entries. 3700 * The last BD entry on each page is a pointer to the next page 3701 * in the chain, and the last pointer in the BD chain 3702 * points back to the beginning of the chain. 3703 */ 3704 3705 /* Set the TX next pointer chain entries. */ 3706 for (i = 0; i < TX_PAGES; i++) { 3707 int j; 3708 3709 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3710 3711 /* Check if we've reached the last page. */ 3712 if (i == (TX_PAGES - 1)) 3713 j = 0; 3714 else 3715 j = i + 1; 3716 3717 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 3718 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 3719 } 3720 3721 /* Initialize the context ID for an L2 TX chain. */ 3722 val = BCE_L2CTX_TYPE_TYPE_L2; 3723 val |= BCE_L2CTX_TYPE_SIZE_L2; 3724 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val); 3725 3726 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3727 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val); 3728 3729 /* Point the hardware to the first page in the chain. */ 3730 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 3731 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val); 3732 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 3733 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val); 3734 3735 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3736 3737 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3738 3739 return(rc); 3740 } 3741 3742 3743 /****************************************************************************/ 3744 /* Free memory and clear the TX data structures. */ 3745 /* */ 3746 /* Returns: */ 3747 /* Nothing. */ 3748 /****************************************************************************/ 3749 static void 3750 bce_free_tx_chain(struct bce_softc *sc) 3751 { 3752 int i; 3753 3754 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3755 3756 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3757 for (i = 0; i < TOTAL_TX_BD; i++) { 3758 if (sc->tx_mbuf_ptr[i] != NULL) { 3759 if (sc->tx_mbuf_map != NULL) 3760 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i], 3761 BUS_DMASYNC_POSTWRITE); 3762 m_freem(sc->tx_mbuf_ptr[i]); 3763 sc->tx_mbuf_ptr[i] = NULL; 3764 DBRUNIF(1, sc->tx_mbuf_alloc--); 3765 } 3766 } 3767 3768 /* Clear each TX chain page. */ 3769 for (i = 0; i < TX_PAGES; i++) 3770 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 3771 3772 sc->used_tx_bd = 0; 3773 3774 /* Check if we lost any mbufs in the process. */ 3775 DBRUNIF((sc->tx_mbuf_alloc), 3776 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 3777 "from tx chain!\n", 3778 __FILE__, __LINE__, sc->tx_mbuf_alloc)); 3779 3780 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3781 } 3782 3783 3784 /****************************************************************************/ 3785 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 3786 /* occurs. */ 3787 /* */ 3788 /* Returns: */ 3789 /* Nothing */ 3790 /****************************************************************************/ 3791 static void 3792 bce_fill_rx_chain(struct bce_softc *sc) 3793 { 3794 u16 prod, chain_prod; 3795 u32 prod_bseq; 3796 #ifdef BCE_DEBUG 3797 int rx_mbuf_alloc_before, free_rx_bd_before; 3798 #endif 3799 3800 DBPRINT(sc, BCE_EXCESSIVE_RECV, "Entering %s()\n", __FUNCTION__); 3801 3802 prod = sc->rx_prod; 3803 prod_bseq = sc->rx_prod_bseq; 3804 3805 #ifdef BCE_DEBUG 3806 rx_mbuf_alloc_before = sc->rx_mbuf_alloc; 3807 free_rx_bd_before = sc->free_rx_bd; 3808 #endif 3809 3810 /* Keep filling the RX chain until it's full. */ 3811 while (sc->free_rx_bd > 0) { 3812 chain_prod = RX_CHAIN_IDX(prod); 3813 if (bce_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3814 /* Bail out if we can't add an mbuf to the chain. */ 3815 break; 3816 } 3817 prod = NEXT_RX_BD(prod); 3818 } 3819 3820 #if 0 3821 DBRUNIF((sc->rx_mbuf_alloc - rx_mbuf_alloc_before), 3822 BCE_PRINTF("%s(): Installed %d mbufs in %d rx_bd entries.\n", 3823 __FUNCTION__, (sc->rx_mbuf_alloc - rx_mbuf_alloc_before), 3824 (free_rx_bd_before - sc->free_rx_bd))); 3825 #endif 3826 3827 /* Save the RX chain producer index. */ 3828 sc->rx_prod = prod; 3829 sc->rx_prod_bseq = prod_bseq; 3830 3831 /* Tell the chip about the waiting rx_bd's. */ 3832 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); 3833 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3834 3835 DBPRINT(sc, BCE_EXCESSIVE_RECV, "Exiting %s()\n", __FUNCTION__); 3836 3837 } 3838 3839 3840 /****************************************************************************/ 3841 /* Allocate memory and initialize the RX data structures. */ 3842 /* */ 3843 /* Returns: */ 3844 /* 0 for success, positive value for failure. */ 3845 /****************************************************************************/ 3846 static int 3847 bce_init_rx_chain(struct bce_softc *sc) 3848 { 3849 struct rx_bd *rxbd; 3850 int i, rc = 0; 3851 u32 val; 3852 3853 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3854 3855 /* Initialize the RX producer and consumer indices. */ 3856 sc->rx_prod = 0; 3857 sc->rx_cons = 0; 3858 sc->rx_prod_bseq = 0; 3859 sc->free_rx_bd = USABLE_RX_BD; 3860 sc->max_rx_bd = USABLE_RX_BD; 3861 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3862 DBRUNIF(1, sc->rx_empty_count = 0); 3863 3864 /* Initialize the RX next pointer chain entries. */ 3865 for (i = 0; i < RX_PAGES; i++) { 3866 int j; 3867 3868 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3869 3870 /* Check if we've reached the last page. */ 3871 if (i == (RX_PAGES - 1)) 3872 j = 0; 3873 else 3874 j = i + 1; 3875 3876 /* Setup the chain page pointers. */ 3877 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 3878 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 3879 } 3880 3881 /* Initialize the context ID for an L2 RX chain. */ 3882 val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3883 val |= BCE_L2CTX_CTX_TYPE_SIZE_L2; 3884 val |= 0x02 << 8; 3885 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val); 3886 3887 /* Point the hardware to the first page in the chain. */ 3888 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 3889 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val); 3890 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 3891 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val); 3892 3893 3894 /* Fill up the RX chain. */ 3895 bce_fill_rx_chain(sc); 3896 3897 3898 for (i = 0; i < RX_PAGES; i++) { 3899 bus_dmamap_sync( 3900 sc->rx_bd_chain_tag, 3901 sc->rx_bd_chain_map[i], 3902 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3903 } 3904 3905 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3906 3907 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3908 3909 return(rc); 3910 } 3911 3912 3913 /****************************************************************************/ 3914 /* Free memory and clear the RX data structures. */ 3915 /* */ 3916 /* Returns: */ 3917 /* Nothing. */ 3918 /****************************************************************************/ 3919 static void 3920 bce_free_rx_chain(struct bce_softc *sc) 3921 { 3922 int i; 3923 #ifdef BCE_DEBUG 3924 int rx_mbuf_alloc_before; 3925 #endif 3926 3927 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3928 3929 #ifdef BCE_DEBUG 3930 rx_mbuf_alloc_before = sc->rx_mbuf_alloc; 3931 #endif 3932 3933 /* Free any mbufs still in the RX mbuf chain. */ 3934 for (i = 0; i < TOTAL_RX_BD; i++) { 3935 if (sc->rx_mbuf_ptr[i] != NULL) { 3936 if (sc->rx_mbuf_map[i] != NULL) 3937 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i], 3938 BUS_DMASYNC_POSTREAD); 3939 m_freem(sc->rx_mbuf_ptr[i]); 3940 sc->rx_mbuf_ptr[i] = NULL; 3941 DBRUNIF(1, sc->rx_mbuf_alloc--); 3942 } 3943 } 3944 3945 DBRUNIF((rx_mbuf_alloc_before - sc->rx_mbuf_alloc), 3946 BCE_PRINTF("%s(): Released %d mbufs.\n", 3947 __FUNCTION__, (rx_mbuf_alloc_before - sc->rx_mbuf_alloc))); 3948 3949 /* Clear each RX chain page. */ 3950 for (i = 0; i < RX_PAGES; i++) 3951 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3952 3953 sc->free_rx_bd = sc->max_rx_bd; 3954 3955 /* Check if we lost any mbufs in the process. */ 3956 DBRUNIF((sc->rx_mbuf_alloc), 3957 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs from rx chain!\n", 3958 __FILE__, __LINE__, sc->rx_mbuf_alloc)); 3959 3960 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3961 } 3962 3963 3964 /****************************************************************************/ 3965 /* Set media options. */ 3966 /* */ 3967 /* Returns: */ 3968 /* 0 for success, positive value for failure. */ 3969 /****************************************************************************/ 3970 static int 3971 bce_ifmedia_upd(struct ifnet *ifp) 3972 { 3973 struct bce_softc *sc; 3974 3975 sc = ifp->if_softc; 3976 BCE_LOCK(sc); 3977 bce_ifmedia_upd_locked(ifp); 3978 BCE_UNLOCK(sc); 3979 return (0); 3980 } 3981 3982 3983 /****************************************************************************/ 3984 /* Set media options. */ 3985 /* */ 3986 /* Returns: */ 3987 /* Nothing. */ 3988 /****************************************************************************/ 3989 static void 3990 bce_ifmedia_upd_locked(struct ifnet *ifp) 3991 { 3992 struct bce_softc *sc; 3993 struct mii_data *mii; 3994 struct ifmedia *ifm; 3995 3996 sc = ifp->if_softc; 3997 ifm = &sc->bce_ifmedia; 3998 BCE_LOCK_ASSERT(sc); 3999 4000 mii = device_get_softc(sc->bce_miibus); 4001 4002 /* Make sure the MII bus has been enumerated. */ 4003 if (mii) { 4004 sc->bce_link = 0; 4005 if (mii->mii_instance) { 4006 struct mii_softc *miisc; 4007 4008 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4009 mii_phy_reset(miisc); 4010 } 4011 mii_mediachg(mii); 4012 } 4013 } 4014 4015 4016 /****************************************************************************/ 4017 /* Reports current media status. */ 4018 /* */ 4019 /* Returns: */ 4020 /* Nothing. */ 4021 /****************************************************************************/ 4022 static void 4023 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4024 { 4025 struct bce_softc *sc; 4026 struct mii_data *mii; 4027 4028 sc = ifp->if_softc; 4029 4030 BCE_LOCK(sc); 4031 4032 mii = device_get_softc(sc->bce_miibus); 4033 4034 mii_pollstat(mii); 4035 ifmr->ifm_active = mii->mii_media_active; 4036 ifmr->ifm_status = mii->mii_media_status; 4037 4038 BCE_UNLOCK(sc); 4039 } 4040 4041 4042 /****************************************************************************/ 4043 /* Handles PHY generated interrupt events. */ 4044 /* */ 4045 /* Returns: */ 4046 /* Nothing. */ 4047 /****************************************************************************/ 4048 static void 4049 bce_phy_intr(struct bce_softc *sc) 4050 { 4051 u32 new_link_state, old_link_state; 4052 4053 new_link_state = sc->status_block->status_attn_bits & 4054 STATUS_ATTN_BITS_LINK_STATE; 4055 old_link_state = sc->status_block->status_attn_bits_ack & 4056 STATUS_ATTN_BITS_LINK_STATE; 4057 4058 /* Handle any changes if the link state has changed. */ 4059 if (new_link_state != old_link_state) { 4060 4061 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 4062 4063 sc->bce_link = 0; 4064 callout_stop(&sc->bce_tick_callout); 4065 bce_tick(sc); 4066 4067 /* Update the status_attn_bits_ack field in the status block. */ 4068 if (new_link_state) { 4069 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 4070 STATUS_ATTN_BITS_LINK_STATE); 4071 DBPRINT(sc, BCE_INFO_MISC, "Link is now UP.\n"); 4072 } 4073 else { 4074 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 4075 STATUS_ATTN_BITS_LINK_STATE); 4076 DBPRINT(sc, BCE_INFO_MISC, "Link is now DOWN.\n"); 4077 } 4078 4079 } 4080 4081 /* Acknowledge the link change interrupt. */ 4082 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 4083 } 4084 4085 4086 /****************************************************************************/ 4087 /* Handles received frame interrupt events. */ 4088 /* */ 4089 /* Returns: */ 4090 /* Nothing. */ 4091 /****************************************************************************/ 4092 static void 4093 bce_rx_intr(struct bce_softc *sc) 4094 { 4095 struct status_block *sblk = sc->status_block; 4096 struct ifnet *ifp = sc->bce_ifp; 4097 u16 hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod; 4098 u32 sw_prod_bseq; 4099 struct l2_fhdr *l2fhdr; 4100 4101 DBRUNIF(1, sc->rx_interrupts++); 4102 4103 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4104 for (int i = 0; i < RX_PAGES; i++) 4105 bus_dmamap_sync(sc->rx_bd_chain_tag, 4106 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE); 4107 4108 /* Get the hardware's view of the RX consumer index. */ 4109 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4110 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4111 hw_cons++; 4112 4113 /* Get working copies of the driver's view of the RX indices. */ 4114 sw_cons = sc->rx_cons; 4115 sw_prod = sc->rx_prod; 4116 sw_prod_bseq = sc->rx_prod_bseq; 4117 4118 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4119 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4120 __FUNCTION__, sw_prod, sw_cons, sw_prod_bseq); 4121 4122 /* Prevent speculative reads from getting ahead of the status block. */ 4123 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4124 BUS_SPACE_BARRIER_READ); 4125 4126 /* Update some debug statistics counters */ 4127 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4128 sc->rx_low_watermark = sc->free_rx_bd); 4129 DBRUNIF((sc->free_rx_bd == USABLE_RX_BD), sc->rx_empty_count++); 4130 4131 /* Scan through the receive chain as long as there is work to do */ 4132 while (sw_cons != hw_cons) { 4133 struct mbuf *m; 4134 struct rx_bd *rxbd; 4135 unsigned int len; 4136 u32 status; 4137 4138 /* Clear the mbuf pointer. */ 4139 m = NULL; 4140 4141 /* Convert the producer/consumer indices to an actual rx_bd index. */ 4142 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4143 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4144 4145 /* Get the used rx_bd. */ 4146 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4147 sc->free_rx_bd++; 4148 4149 DBRUN(BCE_VERBOSE_RECV, 4150 BCE_PRINTF("%s(): ", __FUNCTION__); 4151 bce_dump_rxbd(sc, sw_chain_cons, rxbd)); 4152 4153 #ifdef DEVICE_POLLING 4154 if (ifp->if_capenable & IFCAP_POLLING) { 4155 if (sc->bce_rxcycles <= 0) 4156 break; 4157 sc->bce_rxcycles--; 4158 } 4159 #endif 4160 4161 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4162 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4163 4164 /* Validate that this is the last rx_bd. */ 4165 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)), 4166 BCE_PRINTF("%s(%d): Unexpected mbuf found in rx_bd[0x%04X]!\n", 4167 __FILE__, __LINE__, sw_chain_cons); 4168 bce_breakpoint(sc)); 4169 4170 /* 4171 * ToDo: If the received packet is small enough 4172 * to fit into a single, non-M_EXT mbuf, 4173 * allocate a new mbuf here, copy the data to 4174 * that mbuf, and recycle the mapped jumbo frame. 4175 */ 4176 4177 /* Unmap the mbuf from DMA space. */ 4178 bus_dmamap_sync(sc->rx_mbuf_tag, 4179 sc->rx_mbuf_map[sw_chain_cons], 4180 BUS_DMASYNC_POSTREAD); 4181 bus_dmamap_unload(sc->rx_mbuf_tag, 4182 sc->rx_mbuf_map[sw_chain_cons]); 4183 4184 /* Remove the mbuf from the RX chain. */ 4185 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4186 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4187 4188 /* 4189 * Frames received on the NetXteme II are prepended 4190 * with an l2_fhdr structure which provides status 4191 * information about the received frame (including 4192 * VLAN tags and checksum info). The frames are also 4193 * automatically adjusted to align the IP header 4194 * (i.e. two null bytes are inserted before the 4195 * Ethernet header). 4196 */ 4197 l2fhdr = mtod(m, struct l2_fhdr *); 4198 4199 len = l2fhdr->l2_fhdr_pkt_len; 4200 status = l2fhdr->l2_fhdr_status; 4201 4202 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check), 4203 BCE_PRINTF("Simulating l2_fhdr status error.\n"); 4204 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4205 4206 /* Watch for unusual sized frames. */ 4207 DBRUNIF(((len < BCE_MIN_MTU) || (len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 4208 BCE_PRINTF("%s(%d): Unusual frame size found. " 4209 "Min(%d), Actual(%d), Max(%d)\n", 4210 __FILE__, __LINE__, (int) BCE_MIN_MTU, 4211 len, (int) BCE_MAX_JUMBO_ETHER_MTU_VLAN); 4212 bce_dump_mbuf(sc, m); 4213 bce_breakpoint(sc)); 4214 4215 len -= ETHER_CRC_LEN; 4216 4217 /* Check the received frame for errors. */ 4218 if (status & (L2_FHDR_ERRORS_BAD_CRC | 4219 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 4220 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 4221 4222 /* Log the error and release the mbuf. */ 4223 ifp->if_ierrors++; 4224 DBRUNIF(1, sc->l2fhdr_status_errors++); 4225 4226 /* Todo: Reuse the mbuf to improve performance. */ 4227 4228 m_freem(m); 4229 m = NULL; 4230 goto bce_rx_int_next_rx; 4231 } 4232 4233 /* Skip over the l2_fhdr when passing the data up the stack. */ 4234 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4235 4236 /* Adjust the packet length to match the received data. */ 4237 m->m_pkthdr.len = m->m_len = len; 4238 4239 /* Send the packet to the appropriate interface. */ 4240 m->m_pkthdr.rcvif = ifp; 4241 4242 DBRUN(BCE_VERBOSE_RECV, 4243 struct ether_header *eh; 4244 eh = mtod(m, struct ether_header *); 4245 BCE_PRINTF("%s(): to: %6D, from: %6D, type: 0x%04X\n", 4246 __FUNCTION__, eh->ether_dhost, ":", 4247 eh->ether_shost, ":", htons(eh->ether_type))); 4248 4249 /* Validate the checksum if offload enabled. */ 4250 if (ifp->if_capenable & IFCAP_RXCSUM) { 4251 4252 /* Check for an IP datagram. */ 4253 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4254 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4255 4256 /* Check if the IP checksum is valid. */ 4257 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4258 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4259 else 4260 DBPRINT(sc, BCE_WARN_SEND, 4261 "%s(): Invalid IP checksum = 0x%04X!\n", 4262 __FUNCTION__, l2fhdr->l2_fhdr_ip_xsum); 4263 } 4264 4265 /* Check for a valid TCP/UDP frame. */ 4266 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4267 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4268 4269 /* Check for a good TCP/UDP checksum. */ 4270 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 4271 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4272 m->m_pkthdr.csum_data = 4273 l2fhdr->l2_fhdr_tcp_udp_xsum; 4274 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID 4275 | CSUM_PSEUDO_HDR); 4276 } else 4277 DBPRINT(sc, BCE_WARN_SEND, 4278 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n", 4279 __FUNCTION__, l2fhdr->l2_fhdr_tcp_udp_xsum); 4280 } 4281 } 4282 4283 4284 /* 4285 * If we received a packet with a vlan tag, 4286 * attach that information to the packet. 4287 */ 4288 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 4289 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): VLAN tag = 0x%04X\n", 4290 __FUNCTION__, l2fhdr->l2_fhdr_vlan_tag); 4291 #if __FreeBSD_version < 700000 4292 VLAN_INPUT_TAG(ifp, m, l2fhdr->l2_fhdr_vlan_tag, continue); 4293 #else 4294 m->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag; 4295 m->m_flags |= M_VLANTAG; 4296 #endif 4297 } 4298 4299 /* Pass the mbuf off to the upper layers. */ 4300 ifp->if_ipackets++; 4301 4302 bce_rx_int_next_rx: 4303 sw_prod = NEXT_RX_BD(sw_prod); 4304 } 4305 4306 sw_cons = NEXT_RX_BD(sw_cons); 4307 4308 /* If we have a packet, pass it up the stack */ 4309 if (m) { 4310 /* Make sure we don't lose our place when we release the lock. */ 4311 sc->rx_cons = sw_cons; 4312 4313 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(): Passing received frame up.\n", 4314 __FUNCTION__); 4315 BCE_UNLOCK(sc); 4316 (*ifp->if_input)(ifp, m); 4317 DBRUNIF(1, sc->rx_mbuf_alloc--); 4318 BCE_LOCK(sc); 4319 4320 /* Recover our place. */ 4321 sw_cons = sc->rx_cons; 4322 } 4323 4324 /* Refresh hw_cons to see if there's new work */ 4325 if (sw_cons == hw_cons) { 4326 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4327 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4328 hw_cons++; 4329 } 4330 4331 /* Prevent speculative reads from getting ahead of the status block. */ 4332 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4333 BUS_SPACE_BARRIER_READ); 4334 } 4335 4336 /* No new packets to process. Refill the RX chain and exit. */ 4337 sc->rx_cons = sw_cons; 4338 bce_fill_rx_chain(sc); 4339 4340 for (int i = 0; i < RX_PAGES; i++) 4341 bus_dmamap_sync(sc->rx_bd_chain_tag, 4342 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 4343 4344 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4345 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4346 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4347 } 4348 4349 4350 /****************************************************************************/ 4351 /* Handles transmit completion interrupt events. */ 4352 /* */ 4353 /* Returns: */ 4354 /* Nothing. */ 4355 /****************************************************************************/ 4356 static void 4357 bce_tx_intr(struct bce_softc *sc) 4358 { 4359 struct status_block *sblk = sc->status_block; 4360 struct ifnet *ifp = sc->bce_ifp; 4361 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4362 4363 BCE_LOCK_ASSERT(sc); 4364 4365 DBRUNIF(1, sc->tx_interrupts++); 4366 4367 /* Get the hardware's view of the TX consumer index. */ 4368 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4369 4370 /* Skip to the next entry if this is a chain page pointer. */ 4371 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4372 hw_tx_cons++; 4373 4374 sw_tx_cons = sc->tx_cons; 4375 4376 /* Prevent speculative reads from getting ahead of the status block. */ 4377 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4378 BUS_SPACE_BARRIER_READ); 4379 4380 /* Cycle through any completed TX chain page entries. */ 4381 while (sw_tx_cons != hw_tx_cons) { 4382 #ifdef BCE_DEBUG 4383 struct tx_bd *txbd = NULL; 4384 #endif 4385 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4386 4387 DBPRINT(sc, BCE_INFO_SEND, 4388 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 4389 "sw_tx_chain_cons = 0x%04X\n", 4390 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4391 4392 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4393 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 4394 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 4395 (int) MAX_TX_BD); 4396 bce_breakpoint(sc)); 4397 4398 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 4399 [TX_IDX(sw_tx_chain_cons)]); 4400 4401 DBRUNIF((txbd == NULL), 4402 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 4403 __FILE__, __LINE__, sw_tx_chain_cons); 4404 bce_breakpoint(sc)); 4405 4406 DBRUN(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 4407 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4408 4409 /* 4410 * Free the associated mbuf. Remember 4411 * that only the last tx_bd of a packet 4412 * has an mbuf pointer and DMA map. 4413 */ 4414 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 4415 4416 /* Validate that this is the last tx_bd. */ 4417 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 4418 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 4419 "txmbuf == NULL!\n", __FILE__, __LINE__); 4420 bce_breakpoint(sc)); 4421 4422 DBRUN(BCE_INFO_SEND, 4423 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 4424 "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons)); 4425 4426 /* Unmap the mbuf. */ 4427 bus_dmamap_unload(sc->tx_mbuf_tag, 4428 sc->tx_mbuf_map[sw_tx_chain_cons]); 4429 4430 /* Free the mbuf. */ 4431 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 4432 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 4433 DBRUNIF(1, sc->tx_mbuf_alloc--); 4434 4435 ifp->if_opackets++; 4436 } 4437 4438 sc->used_tx_bd--; 4439 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4440 4441 /* Refresh hw_cons to see if there's new work. */ 4442 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4443 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4444 hw_tx_cons++; 4445 4446 /* Prevent speculative reads from getting ahead of the status block. */ 4447 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4448 BUS_SPACE_BARRIER_READ); 4449 } 4450 4451 /* Clear the TX timeout timer. */ 4452 sc->watchdog_timer = 0; 4453 4454 /* Clear the tx hardware queue full flag. */ 4455 if (sc->used_tx_bd < sc->max_tx_bd) { 4456 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 4457 DBPRINT(sc, BCE_INFO_SEND, 4458 "%s(): Open TX chain! %d/%d (used/total)\n", 4459 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 4460 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4461 } 4462 4463 sc->tx_cons = sw_tx_cons; 4464 } 4465 4466 4467 /****************************************************************************/ 4468 /* Disables interrupt generation. */ 4469 /* */ 4470 /* Returns: */ 4471 /* Nothing. */ 4472 /****************************************************************************/ 4473 static void 4474 bce_disable_intr(struct bce_softc *sc) 4475 { 4476 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4477 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 4478 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 4479 } 4480 4481 4482 /****************************************************************************/ 4483 /* Enables interrupt generation. */ 4484 /* */ 4485 /* Returns: */ 4486 /* Nothing. */ 4487 /****************************************************************************/ 4488 static void 4489 bce_enable_intr(struct bce_softc *sc) 4490 { 4491 u32 val; 4492 4493 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4494 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 4495 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4496 4497 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4498 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4499 4500 val = REG_RD(sc, BCE_HC_COMMAND); 4501 REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW); 4502 } 4503 4504 4505 /****************************************************************************/ 4506 /* Handles controller initialization. */ 4507 /* */ 4508 /* Returns: */ 4509 /* Nothing. */ 4510 /****************************************************************************/ 4511 static void 4512 bce_init_locked(struct bce_softc *sc) 4513 { 4514 struct ifnet *ifp; 4515 u32 ether_mtu; 4516 4517 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4518 4519 BCE_LOCK_ASSERT(sc); 4520 4521 ifp = sc->bce_ifp; 4522 4523 /* Check if the driver is still running and bail out if it is. */ 4524 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4525 goto bce_init_locked_exit; 4526 4527 bce_stop(sc); 4528 4529 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 4530 BCE_PRINTF("%s(%d): Controller reset failed!\n", 4531 __FILE__, __LINE__); 4532 goto bce_init_locked_exit; 4533 } 4534 4535 if (bce_chipinit(sc)) { 4536 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 4537 __FILE__, __LINE__); 4538 goto bce_init_locked_exit; 4539 } 4540 4541 if (bce_blockinit(sc)) { 4542 BCE_PRINTF("%s(%d): Block initialization failed!\n", 4543 __FILE__, __LINE__); 4544 goto bce_init_locked_exit; 4545 } 4546 4547 /* Load our MAC address. */ 4548 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 4549 bce_set_mac_addr(sc); 4550 4551 /* Calculate and program the Ethernet MTU size. */ 4552 ether_mtu = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ifp->if_mtu + 4553 ETHER_CRC_LEN; 4554 4555 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting mtu = %d\n",__FUNCTION__, ether_mtu); 4556 4557 /* 4558 * Program the mtu, enabling jumbo frame 4559 * support if necessary. Also set the mbuf 4560 * allocation count for RX frames. 4561 */ 4562 if (ether_mtu > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 4563 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 4564 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4565 sc->mbuf_alloc_size = MJUM9BYTES; 4566 } else { 4567 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 4568 sc->mbuf_alloc_size = MCLBYTES; 4569 } 4570 4571 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4572 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4573 4574 DBPRINT(sc, BCE_INFO_RECV, 4575 "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4576 "max_frame_size = %d\n", 4577 __FUNCTION__, (int) MCLBYTES, sc->mbuf_alloc_size, sc->max_frame_size); 4578 4579 /* Program appropriate promiscuous/multicast filtering. */ 4580 bce_set_rx_mode(sc); 4581 4582 /* Init RX buffer descriptor chain. */ 4583 bce_init_rx_chain(sc); 4584 4585 /* Init TX buffer descriptor chain. */ 4586 bce_init_tx_chain(sc); 4587 4588 #ifdef DEVICE_POLLING 4589 /* Disable interrupts if we are polling. */ 4590 if (ifp->if_capenable & IFCAP_POLLING) { 4591 bce_disable_intr(sc); 4592 4593 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4594 (1 << 16) | sc->bce_rx_quick_cons_trip); 4595 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4596 (1 << 16) | sc->bce_tx_quick_cons_trip); 4597 } else 4598 #endif 4599 /* Enable host interrupts. */ 4600 bce_enable_intr(sc); 4601 4602 bce_ifmedia_upd_locked(ifp); 4603 4604 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4605 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4606 4607 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 4608 4609 bce_init_locked_exit: 4610 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4611 4612 return; 4613 } 4614 4615 4616 /****************************************************************************/ 4617 /* Initialize the controller just enough so that any management firmware */ 4618 /* running on the device will continue to operate correctly. */ 4619 /* */ 4620 /* Returns: */ 4621 /* Nothing. */ 4622 /****************************************************************************/ 4623 static void 4624 bce_mgmt_init_locked(struct bce_softc *sc) 4625 { 4626 struct ifnet *ifp; 4627 4628 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4629 4630 BCE_LOCK_ASSERT(sc); 4631 4632 /* Bail out if management firmware is not running. */ 4633 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 4634 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 4635 "No management firmware running...\n"); 4636 goto bce_mgmt_init_locked_exit; 4637 } 4638 4639 ifp = sc->bce_ifp; 4640 4641 /* Enable all critical blocks in the MAC. */ 4642 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff); 4643 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4644 DELAY(20); 4645 4646 bce_ifmedia_upd_locked(ifp); 4647 bce_mgmt_init_locked_exit: 4648 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4649 4650 return; 4651 } 4652 4653 4654 /****************************************************************************/ 4655 /* Handles controller initialization when called from an unlocked routine. */ 4656 /* */ 4657 /* Returns: */ 4658 /* Nothing. */ 4659 /****************************************************************************/ 4660 static void 4661 bce_init(void *xsc) 4662 { 4663 struct bce_softc *sc = xsc; 4664 4665 BCE_LOCK(sc); 4666 bce_init_locked(sc); 4667 BCE_UNLOCK(sc); 4668 } 4669 4670 4671 /****************************************************************************/ 4672 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4673 /* memory visible to the controller. */ 4674 /* */ 4675 /* Returns: */ 4676 /* 0 for success, positive value for failure. */ 4677 /* Modified: */ 4678 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 4679 /****************************************************************************/ 4680 static int 4681 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 4682 { 4683 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 4684 bus_dmamap_t map; 4685 struct tx_bd *txbd = NULL; 4686 struct mbuf *m0; 4687 struct ether_vlan_header *eh; 4688 struct ip *ip; 4689 struct tcphdr *th; 4690 u16 prod, chain_prod, etype, mss = 0, vlan_tag = 0, flags = 0; 4691 u32 prod_bseq; 4692 int hdr_len = 0, e_hlen = 0, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 4693 4694 4695 #ifdef BCE_DEBUG 4696 u16 debug_prod; 4697 #endif 4698 int i, error, nsegs, rc = 0; 4699 4700 /* Transfer any checksum offload flags to the bd. */ 4701 m0 = *m_head; 4702 if (m0->m_pkthdr.csum_flags) { 4703 if (m0->m_pkthdr.csum_flags & CSUM_IP) 4704 flags |= TX_BD_FLAGS_IP_CKSUM; 4705 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 4706 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4707 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 4708 /* For TSO the controller needs two pieces of info, */ 4709 /* the MSS and the IP+TCP options length. */ 4710 mss = htole16(m0->m_pkthdr.tso_segsz); 4711 4712 /* Map the header and find the Ethernet type & header length */ 4713 eh = mtod(m0, struct ether_vlan_header *); 4714 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 4715 etype = ntohs(eh->evl_proto); 4716 e_hlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4717 } else { 4718 etype = ntohs(eh->evl_encap_proto); 4719 e_hlen = ETHER_HDR_LEN; 4720 } 4721 4722 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 4723 switch (etype) { 4724 case ETHERTYPE_IP: 4725 ip = (struct ip *)(m0->m_data + e_hlen); 4726 4727 /* TSO only supported for TCP protocol */ 4728 if (ip->ip_p != IPPROTO_TCP) { 4729 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 4730 __FILE__, __LINE__); 4731 goto bce_tx_encap_skip_tso; 4732 } 4733 4734 /* Get IP header length in bytes (min 20) */ 4735 ip_hlen = ip->ip_hl << 2; 4736 4737 /* Get the TCP header length in bytes (min 20) */ 4738 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 4739 tcp_hlen = (th->th_off << 2); 4740 4741 /* IP header length and checksum will be calc'd by hardware */ 4742 ip_len = ip->ip_len; 4743 ip->ip_len = 0; 4744 ip->ip_sum = 0; 4745 break; 4746 case ETHERTYPE_IPV6: 4747 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 4748 __FILE__, __LINE__); 4749 goto bce_tx_encap_skip_tso; 4750 default: 4751 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 4752 __FILE__, __LINE__); 4753 goto bce_tx_encap_skip_tso; 4754 } 4755 4756 hdr_len = e_hlen + ip_hlen + tcp_hlen; 4757 4758 DBPRINT(sc, BCE_EXCESSIVE_SEND, 4759 "%s(): hdr_len = %d, e_hlen = %d, ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 4760 __FUNCTION__, hdr_len, e_hlen, ip_hlen, tcp_hlen, ip_len); 4761 4762 /* Set the LSO flag in the TX BD */ 4763 flags |= TX_BD_FLAGS_SW_LSO; 4764 /* Set the length of IP + TCP options (in 32 bit words) */ 4765 flags |= (((ip_hlen + tcp_hlen - 40) >> 2) << 8); 4766 4767 bce_tx_encap_skip_tso: 4768 DBRUNIF(1, sc->requested_tso_frames++); 4769 } 4770 } 4771 4772 /* Transfer any VLAN tags to the bd. */ 4773 if (m0->m_flags & M_VLANTAG) { 4774 flags |= TX_BD_FLAGS_VLAN_TAG; 4775 vlan_tag = m0->m_pkthdr.ether_vtag; 4776 } 4777 4778 /* Map the mbuf into DMAable memory. */ 4779 prod = sc->tx_prod; 4780 chain_prod = TX_CHAIN_IDX(prod); 4781 map = sc->tx_mbuf_map[chain_prod]; 4782 4783 /* Map the mbuf into our DMA address space. */ 4784 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4785 segs, &nsegs, BUS_DMA_NOWAIT); 4786 4787 /* Check if the DMA mapping was successful */ 4788 if (error == EFBIG) { 4789 4790 /* The mbuf is too fragmented for our DMA mapping. */ 4791 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n", 4792 __FUNCTION__, nsegs); 4793 DBRUNIF(1, bce_dump_mbuf(sc, m0);); 4794 4795 /* Try to defrag the mbuf. */ 4796 m0 = m_defrag(*m_head, M_DONTWAIT); 4797 if (m0 == NULL) { 4798 /* Defrag was unsuccessful */ 4799 m_freem(*m_head); 4800 *m_head = NULL; 4801 sc->mbuf_alloc_failed++; 4802 return (ENOBUFS); 4803 } 4804 4805 /* Defrag was successful, try mapping again */ 4806 *m_head = m0; 4807 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4808 segs, &nsegs, BUS_DMA_NOWAIT); 4809 4810 /* Still getting an error after a defrag. */ 4811 if (error == ENOMEM) { 4812 /* Insufficient DMA buffers available. */ 4813 sc->tx_dma_map_failures++; 4814 return (error); 4815 } else if (error != 0) { 4816 /* Still can't map the mbuf, release it and return an error. */ 4817 BCE_PRINTF( 4818 "%s(%d): Unknown error mapping mbuf into TX chain!\n", 4819 __FILE__, __LINE__); 4820 m_freem(m0); 4821 *m_head = NULL; 4822 sc->tx_dma_map_failures++; 4823 return (ENOBUFS); 4824 } 4825 } else if (error == ENOMEM) { 4826 /* Insufficient DMA buffers available. */ 4827 sc->tx_dma_map_failures++; 4828 return (error); 4829 } else if (error != 0) { 4830 m_freem(m0); 4831 *m_head = NULL; 4832 sc->tx_dma_map_failures++; 4833 return (error); 4834 } 4835 4836 /* Make sure there's room in the chain */ 4837 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 4838 bus_dmamap_unload(sc->tx_mbuf_tag, map); 4839 return (ENOBUFS); 4840 } 4841 4842 /* prod points to an empty tx_bd at this point. */ 4843 prod_bseq = sc->tx_prod_bseq; 4844 4845 #ifdef BCE_DEBUG 4846 debug_prod = chain_prod; 4847 #endif 4848 4849 DBPRINT(sc, BCE_INFO_SEND, 4850 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4851 "prod_bseq = 0x%08X\n", 4852 __FUNCTION__, prod, chain_prod, prod_bseq); 4853 4854 /* 4855 * Cycle through each mbuf segment that makes up 4856 * the outgoing frame, gathering the mapping info 4857 * for that segment and creating a tx_bd to for 4858 * the mbuf. 4859 */ 4860 for (i = 0; i < nsegs ; i++) { 4861 4862 chain_prod = TX_CHAIN_IDX(prod); 4863 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4864 4865 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 4866 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 4867 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | htole16(segs[i].ds_len); 4868 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4869 txbd->tx_bd_flags = htole16(flags); 4870 prod_bseq += segs[i].ds_len; 4871 if (i == 0) 4872 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4873 prod = NEXT_TX_BD(prod); 4874 } 4875 4876 /* Set the END flag on the last TX buffer descriptor. */ 4877 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4878 4879 DBRUN(BCE_EXCESSIVE_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs)); 4880 4881 DBPRINT(sc, BCE_INFO_SEND, 4882 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4883 "prod_bseq = 0x%08X\n", 4884 __FUNCTION__, prod, chain_prod, prod_bseq); 4885 4886 /* 4887 * Ensure that the mbuf pointer for this transmission 4888 * is placed at the array index of the last 4889 * descriptor in this chain. This is done 4890 * because a single map is used for all 4891 * segments of the mbuf and we don't want to 4892 * unload the map before all of the segments 4893 * have been freed. 4894 */ 4895 sc->tx_mbuf_ptr[chain_prod] = m0; 4896 sc->used_tx_bd += nsegs; 4897 4898 /* Update some debug statistic counters */ 4899 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4900 sc->tx_hi_watermark = sc->used_tx_bd); 4901 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 4902 DBRUNIF(1, sc->tx_mbuf_alloc++); 4903 4904 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs)); 4905 4906 /* prod points to the next free tx_bd at this point. */ 4907 sc->tx_prod = prod; 4908 sc->tx_prod_bseq = prod_bseq; 4909 4910 return(rc); 4911 } 4912 4913 4914 /****************************************************************************/ 4915 /* Main transmit routine when called from another routine with a lock. */ 4916 /* */ 4917 /* Returns: */ 4918 /* Nothing. */ 4919 /****************************************************************************/ 4920 static void 4921 bce_start_locked(struct ifnet *ifp) 4922 { 4923 struct bce_softc *sc = ifp->if_softc; 4924 struct mbuf *m_head = NULL; 4925 int count = 0; 4926 u16 tx_prod, tx_chain_prod; 4927 4928 /* If there's no link or the transmit queue is empty then just exit. */ 4929 if (!sc->bce_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 4930 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link or transmit queue empty.\n", 4931 __FUNCTION__); 4932 goto bce_start_locked_exit; 4933 } 4934 4935 /* prod points to the next free tx_bd. */ 4936 tx_prod = sc->tx_prod; 4937 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4938 4939 DBPRINT(sc, BCE_INFO_SEND, 4940 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, " 4941 "tx_prod_bseq = 0x%08X\n", 4942 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4943 4944 /* 4945 * Keep adding entries while there is space in the ring. 4946 */ 4947 while (sc->used_tx_bd < sc->max_tx_bd) { 4948 4949 /* Check for any frames to send. */ 4950 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4951 if (m_head == NULL) 4952 break; 4953 4954 /* 4955 * Pack the data into the transmit ring. If we 4956 * don't have room, place the mbuf back at the 4957 * head of the queue and set the OACTIVE flag 4958 * to wait for the NIC to drain the chain. 4959 */ 4960 if (bce_tx_encap(sc, &m_head)) { 4961 if (m_head != NULL) 4962 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4963 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4964 DBPRINT(sc, BCE_INFO_SEND, 4965 "TX chain is closed for business! Total tx_bd used = %d\n", 4966 sc->used_tx_bd); 4967 break; 4968 } 4969 4970 count++; 4971 4972 /* Send a copy of the frame to any BPF listeners. */ 4973 ETHER_BPF_MTAP(ifp, m_head); 4974 } 4975 4976 if (count == 0) { 4977 /* no packets were dequeued */ 4978 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n", 4979 __FUNCTION__); 4980 goto bce_start_locked_exit; 4981 } 4982 4983 /* Update the driver's counters. */ 4984 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4985 4986 DBPRINT(sc, BCE_INFO_SEND, 4987 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 4988 "tx_prod_bseq = 0x%08X\n", 4989 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4990 4991 /* Start the transmit. */ 4992 REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4993 REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4994 4995 /* Set the tx timeout. */ 4996 sc->watchdog_timer = BCE_TX_TIMEOUT; 4997 4998 bce_start_locked_exit: 4999 return; 5000 } 5001 5002 5003 /****************************************************************************/ 5004 /* Main transmit routine when called from another routine without a lock. */ 5005 /* */ 5006 /* Returns: */ 5007 /* Nothing. */ 5008 /****************************************************************************/ 5009 static void 5010 bce_start(struct ifnet *ifp) 5011 { 5012 struct bce_softc *sc = ifp->if_softc; 5013 5014 BCE_LOCK(sc); 5015 bce_start_locked(ifp); 5016 BCE_UNLOCK(sc); 5017 } 5018 5019 5020 /****************************************************************************/ 5021 /* Handles any IOCTL calls from the operating system. */ 5022 /* */ 5023 /* Returns: */ 5024 /* 0 for success, positive value for failure. */ 5025 /****************************************************************************/ 5026 static int 5027 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5028 { 5029 struct bce_softc *sc = ifp->if_softc; 5030 struct ifreq *ifr = (struct ifreq *) data; 5031 struct mii_data *mii; 5032 int mask, error = 0; 5033 5034 switch(command) { 5035 5036 /* Set the interface MTU. */ 5037 case SIOCSIFMTU: 5038 /* Check that the MTU setting is supported. */ 5039 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 5040 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 5041 error = EINVAL; 5042 break; 5043 } 5044 5045 DBPRINT(sc, BCE_INFO_MISC, 5046 "SIOCSIFMTU: Changing MTU from %d to %d\n", 5047 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 5048 5049 BCE_LOCK(sc); 5050 ifp->if_mtu = ifr->ifr_mtu; 5051 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5052 bce_init_locked(sc); 5053 BCE_UNLOCK(sc); 5054 break; 5055 5056 /* Set interface flags. */ 5057 case SIOCSIFFLAGS: 5058 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 5059 5060 BCE_LOCK(sc); 5061 5062 /* Check if the interface is up. */ 5063 if (ifp->if_flags & IFF_UP) { 5064 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5065 /* Change promiscuous/multicast flags as necessary. */ 5066 bce_set_rx_mode(sc); 5067 } else { 5068 /* Start the HW */ 5069 bce_init_locked(sc); 5070 } 5071 } else { 5072 /* The interface is down, check if driver is running. */ 5073 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5074 bce_stop(sc); 5075 5076 /* If MFW is running, restart the controller a bit. */ 5077 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5078 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 5079 bce_chipinit(sc); 5080 bce_mgmt_init_locked(sc); 5081 } 5082 } 5083 } 5084 5085 BCE_UNLOCK(sc); 5086 error = 0; 5087 5088 break; 5089 5090 /* Add/Delete multicast address */ 5091 case SIOCADDMULTI: 5092 case SIOCDELMULTI: 5093 DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCADDMULTI/SIOCDELMULTI\n"); 5094 5095 BCE_LOCK(sc); 5096 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5097 bce_set_rx_mode(sc); 5098 error = 0; 5099 } 5100 BCE_UNLOCK(sc); 5101 5102 break; 5103 5104 /* Set/Get Interface media */ 5105 case SIOCSIFMEDIA: 5106 case SIOCGIFMEDIA: 5107 DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 5108 5109 mii = device_get_softc(sc->bce_miibus); 5110 error = ifmedia_ioctl(ifp, ifr, 5111 &mii->mii_media, command); 5112 break; 5113 5114 /* Set interface capability */ 5115 case SIOCSIFCAP: 5116 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5117 DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 5118 5119 #ifdef DEVICE_POLLING 5120 if (mask & IFCAP_POLLING) { 5121 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5122 5123 /* Setup the poll routine to call. */ 5124 error = ether_poll_register(bce_poll, ifp); 5125 if (error) { 5126 BCE_PRINTF("%s(%d): Error registering poll function!\n", 5127 __FILE__, __LINE__); 5128 goto bce_ioctl_exit; 5129 } 5130 5131 /* Clear the interrupt. */ 5132 BCE_LOCK(sc); 5133 bce_disable_intr(sc); 5134 5135 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5136 (1 << 16) | sc->bce_rx_quick_cons_trip); 5137 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5138 (1 << 16) | sc->bce_tx_quick_cons_trip); 5139 5140 ifp->if_capenable |= IFCAP_POLLING; 5141 BCE_UNLOCK(sc); 5142 } else { 5143 /* Clear the poll routine. */ 5144 error = ether_poll_deregister(ifp); 5145 5146 /* Enable interrupt even in error case */ 5147 BCE_LOCK(sc); 5148 bce_enable_intr(sc); 5149 5150 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5151 (sc->bce_tx_quick_cons_trip_int << 16) | 5152 sc->bce_tx_quick_cons_trip); 5153 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5154 (sc->bce_rx_quick_cons_trip_int << 16) | 5155 sc->bce_rx_quick_cons_trip); 5156 5157 ifp->if_capenable &= ~IFCAP_POLLING; 5158 BCE_UNLOCK(sc); 5159 } 5160 } 5161 #endif /*DEVICE_POLLING */ 5162 5163 /* Toggle the TX checksum capabilites enable flag. */ 5164 if (mask & IFCAP_TXCSUM) { 5165 ifp->if_capenable ^= IFCAP_TXCSUM; 5166 if (IFCAP_TXCSUM & ifp->if_capenable) 5167 ifp->if_hwassist = BCE_IF_HWASSIST; 5168 else 5169 ifp->if_hwassist = 0; 5170 } 5171 5172 /* Toggle the RX checksum capabilities enable flag. */ 5173 if (mask & IFCAP_RXCSUM) { 5174 ifp->if_capenable ^= IFCAP_RXCSUM; 5175 if (IFCAP_RXCSUM & ifp->if_capenable) 5176 ifp->if_hwassist = BCE_IF_HWASSIST; 5177 else 5178 ifp->if_hwassist = 0; 5179 } 5180 5181 /* Toggle the TSO capabilities enable flag. */ 5182 if (bce_tso_enable && (mask & IFCAP_TSO4)) { 5183 ifp->if_capenable ^= IFCAP_TSO4; 5184 if (IFCAP_RXCSUM & ifp->if_capenable) 5185 ifp->if_hwassist = BCE_IF_HWASSIST; 5186 else 5187 ifp->if_hwassist = 0; 5188 } 5189 5190 /* Toggle VLAN_MTU capabilities enable flag. */ 5191 if (mask & IFCAP_VLAN_MTU) { 5192 BCE_PRINTF("%s(%d): Changing VLAN_MTU not supported.\n", 5193 __FILE__, __LINE__); 5194 } 5195 5196 /* Toggle VLANHWTAG capabilities enabled flag. */ 5197 if (mask & IFCAP_VLAN_HWTAGGING) { 5198 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 5199 BCE_PRINTF("%s(%d): Cannot change VLAN_HWTAGGING while " 5200 "management firmware (ASF/IPMI/UMP) is running!\n", 5201 __FILE__, __LINE__); 5202 else 5203 BCE_PRINTF("%s(%d): Changing VLAN_HWTAGGING not supported!\n", 5204 __FILE__, __LINE__); 5205 } 5206 5207 break; 5208 default: 5209 /* We don't know how to handle the IOCTL, pass it on. */ 5210 error = ether_ioctl(ifp, command, data); 5211 break; 5212 } 5213 5214 #ifdef DEVICE_POLLING 5215 bce_ioctl_exit: 5216 #endif 5217 return(error); 5218 } 5219 5220 5221 /****************************************************************************/ 5222 /* Transmit timeout handler. */ 5223 /* */ 5224 /* Returns: */ 5225 /* Nothing. */ 5226 /****************************************************************************/ 5227 static void 5228 bce_watchdog(struct bce_softc *sc) 5229 { 5230 5231 BCE_LOCK_ASSERT(sc); 5232 5233 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 5234 return; 5235 5236 /* 5237 * If we are in this routine because of pause frames, then 5238 * don't reset the hardware. 5239 */ 5240 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 5241 return; 5242 5243 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 5244 __FILE__, __LINE__); 5245 5246 DBRUN(BCE_VERBOSE_SEND, 5247 bce_dump_driver_state(sc); 5248 bce_dump_status_block(sc)); 5249 5250 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */ 5251 5252 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5253 5254 bce_init_locked(sc); 5255 sc->bce_ifp->if_oerrors++; 5256 5257 } 5258 5259 5260 #ifdef DEVICE_POLLING 5261 static void 5262 bce_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 5263 { 5264 struct bce_softc *sc = ifp->if_softc; 5265 5266 BCE_LOCK_ASSERT(sc); 5267 5268 sc->bce_rxcycles = count; 5269 5270 bus_dmamap_sync(sc->status_tag, sc->status_map, 5271 BUS_DMASYNC_POSTWRITE); 5272 5273 /* Check for any completed RX frames. */ 5274 if (sc->status_block->status_rx_quick_consumer_index0 != 5275 sc->hw_rx_cons) 5276 bce_rx_intr(sc); 5277 5278 /* Check for any completed TX frames. */ 5279 if (sc->status_block->status_tx_quick_consumer_index0 != 5280 sc->hw_tx_cons) 5281 bce_tx_intr(sc); 5282 5283 /* Check for new frames to transmit. */ 5284 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5285 bce_start_locked(ifp); 5286 5287 } 5288 5289 5290 static void 5291 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 5292 { 5293 struct bce_softc *sc = ifp->if_softc; 5294 5295 BCE_LOCK(sc); 5296 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5297 bce_poll_locked(ifp, cmd, count); 5298 BCE_UNLOCK(sc); 5299 } 5300 #endif /* DEVICE_POLLING */ 5301 5302 5303 #if 0 5304 static inline int 5305 bce_has_work(struct bce_softc *sc) 5306 { 5307 struct status_block *stat = sc->status_block; 5308 5309 if ((stat->status_rx_quick_consumer_index0 != sc->hw_rx_cons) || 5310 (stat->status_tx_quick_consumer_index0 != sc->hw_tx_cons)) 5311 return 1; 5312 5313 if (((stat->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) != 5314 bp->link_up) 5315 return 1; 5316 5317 return 0; 5318 } 5319 #endif 5320 5321 5322 /* 5323 * Interrupt handler. 5324 */ 5325 /****************************************************************************/ 5326 /* Main interrupt entry point. Verifies that the controller generated the */ 5327 /* interrupt and then calls a separate routine for handle the various */ 5328 /* interrupt causes (PHY, TX, RX). */ 5329 /* */ 5330 /* Returns: */ 5331 /* 0 for success, positive value for failure. */ 5332 /****************************************************************************/ 5333 static void 5334 bce_intr(void *xsc) 5335 { 5336 struct bce_softc *sc; 5337 struct ifnet *ifp; 5338 u32 status_attn_bits; 5339 5340 sc = xsc; 5341 ifp = sc->bce_ifp; 5342 5343 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 5344 BCE_LOCK(sc); 5345 5346 DBRUNIF(1, sc->interrupts_generated++); 5347 5348 #ifdef DEVICE_POLLING 5349 if (ifp->if_capenable & IFCAP_POLLING) { 5350 DBPRINT(sc, BCE_INFO_MISC, "Polling enabled!\n"); 5351 goto bce_intr_exit; 5352 } 5353 #endif 5354 5355 bus_dmamap_sync(sc->status_tag, sc->status_map, 5356 BUS_DMASYNC_POSTWRITE); 5357 5358 /* 5359 * If the hardware status block index 5360 * matches the last value read by the 5361 * driver and we haven't asserted our 5362 * interrupt then there's nothing to do. 5363 */ 5364 if ((sc->status_block->status_idx == sc->last_status_idx) && 5365 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) 5366 goto bce_intr_exit; 5367 5368 /* Ack the interrupt and stop others from occuring. */ 5369 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5370 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5371 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5372 5373 /* Keep processing data as long as there is work to do. */ 5374 for (;;) { 5375 5376 status_attn_bits = sc->status_block->status_attn_bits; 5377 5378 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention), 5379 BCE_PRINTF("Simulating unexpected status attention bit set."); 5380 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR); 5381 5382 /* Was it a link change interrupt? */ 5383 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5384 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) 5385 bce_phy_intr(sc); 5386 5387 /* If any other attention is asserted then the chip is toast. */ 5388 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5389 (sc->status_block->status_attn_bits_ack & 5390 ~STATUS_ATTN_BITS_LINK_STATE))) { 5391 5392 DBRUN(1, sc->unexpected_attentions++); 5393 5394 BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n", 5395 __FILE__, __LINE__, sc->status_block->status_attn_bits); 5396 5397 DBRUN(BCE_FATAL, 5398 if (bce_debug_unexpected_attention == 0) 5399 bce_breakpoint(sc)); 5400 5401 bce_init_locked(sc); 5402 goto bce_intr_exit; 5403 } 5404 5405 /* Check for any completed RX frames. */ 5406 if (sc->status_block->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5407 bce_rx_intr(sc); 5408 5409 /* Check for any completed TX frames. */ 5410 if (sc->status_block->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5411 bce_tx_intr(sc); 5412 5413 /* Save the status block index value for use during the next interrupt. */ 5414 sc->last_status_idx = sc->status_block->status_idx; 5415 5416 /* Prevent speculative reads from getting ahead of the status block. */ 5417 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 5418 BUS_SPACE_BARRIER_READ); 5419 5420 /* If there's no work left then exit the interrupt service routine. */ 5421 if ((sc->status_block->status_rx_quick_consumer_index0 == sc->hw_rx_cons) && 5422 (sc->status_block->status_tx_quick_consumer_index0 == sc->hw_tx_cons)) 5423 break; 5424 5425 } 5426 5427 bus_dmamap_sync(sc->status_tag, sc->status_map, 5428 BUS_DMASYNC_PREWRITE); 5429 5430 /* Re-enable interrupts. */ 5431 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5432 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5433 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5434 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5435 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5436 5437 /* Handle any frames that arrived while handling the interrupt. */ 5438 if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5439 bce_start_locked(ifp); 5440 5441 bce_intr_exit: 5442 BCE_UNLOCK(sc); 5443 } 5444 5445 5446 /****************************************************************************/ 5447 /* Programs the various packet receive modes (broadcast and multicast). */ 5448 /* */ 5449 /* Returns: */ 5450 /* Nothing. */ 5451 /****************************************************************************/ 5452 static void 5453 bce_set_rx_mode(struct bce_softc *sc) 5454 { 5455 struct ifnet *ifp; 5456 struct ifmultiaddr *ifma; 5457 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5458 u32 rx_mode, sort_mode; 5459 int h, i; 5460 5461 BCE_LOCK_ASSERT(sc); 5462 5463 ifp = sc->bce_ifp; 5464 5465 /* Initialize receive mode default settings. */ 5466 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 5467 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 5468 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 5469 5470 /* 5471 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5472 * be enbled. 5473 */ 5474 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 5475 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 5476 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 5477 5478 /* 5479 * Check for promiscuous, all multicast, or selected 5480 * multicast address filtering. 5481 */ 5482 if (ifp->if_flags & IFF_PROMISC) { 5483 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 5484 5485 /* Enable promiscuous mode. */ 5486 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 5487 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 5488 } else if (ifp->if_flags & IFF_ALLMULTI) { 5489 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 5490 5491 /* Enable all multicast addresses. */ 5492 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 5493 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 5494 } 5495 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 5496 } else { 5497 /* Accept one or more multicast(s). */ 5498 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 5499 5500 IF_ADDR_LOCK(ifp); 5501 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 5502 if (ifma->ifma_addr->sa_family != AF_LINK) 5503 continue; 5504 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 5505 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 5506 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5507 } 5508 IF_ADDR_UNLOCK(ifp); 5509 5510 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5511 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 5512 5513 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 5514 } 5515 5516 /* Only make changes if the recive mode has actually changed. */ 5517 if (rx_mode != sc->rx_mode) { 5518 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: 0x%08X\n", 5519 rx_mode); 5520 5521 sc->rx_mode = rx_mode; 5522 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 5523 } 5524 5525 /* Disable and clear the exisitng sort before enabling a new sort. */ 5526 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 5527 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 5528 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 5529 } 5530 5531 5532 /****************************************************************************/ 5533 /* Called periodically to updates statistics from the controllers */ 5534 /* statistics block. */ 5535 /* */ 5536 /* Returns: */ 5537 /* Nothing. */ 5538 /****************************************************************************/ 5539 static void 5540 bce_stats_update(struct bce_softc *sc) 5541 { 5542 struct ifnet *ifp; 5543 struct statistics_block *stats; 5544 5545 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 5546 5547 ifp = sc->bce_ifp; 5548 5549 stats = (struct statistics_block *) sc->stats_block; 5550 5551 /* 5552 * Update the interface statistics from the 5553 * hardware statistics. 5554 */ 5555 ifp->if_collisions = (u_long) stats->stat_EtherStatsCollisions; 5556 5557 ifp->if_ierrors = (u_long) stats->stat_EtherStatsUndersizePkts + 5558 (u_long) stats->stat_EtherStatsOverrsizePkts + 5559 (u_long) stats->stat_IfInMBUFDiscards + 5560 (u_long) stats->stat_Dot3StatsAlignmentErrors + 5561 (u_long) stats->stat_Dot3StatsFCSErrors; 5562 5563 ifp->if_oerrors = (u_long) stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5564 (u_long) stats->stat_Dot3StatsExcessiveCollisions + 5565 (u_long) stats->stat_Dot3StatsLateCollisions; 5566 5567 /* 5568 * Certain controllers don't report 5569 * carrier sense errors correctly. 5570 * See errata E11_5708CA0_1165. 5571 */ 5572 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5573 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 5574 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5575 5576 /* 5577 * Update the sysctl statistics from the 5578 * hardware statistics. 5579 */ 5580 sc->stat_IfHCInOctets = 5581 ((u64) stats->stat_IfHCInOctets_hi << 32) + 5582 (u64) stats->stat_IfHCInOctets_lo; 5583 5584 sc->stat_IfHCInBadOctets = 5585 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 5586 (u64) stats->stat_IfHCInBadOctets_lo; 5587 5588 sc->stat_IfHCOutOctets = 5589 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 5590 (u64) stats->stat_IfHCOutOctets_lo; 5591 5592 sc->stat_IfHCOutBadOctets = 5593 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 5594 (u64) stats->stat_IfHCOutBadOctets_lo; 5595 5596 sc->stat_IfHCInUcastPkts = 5597 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 5598 (u64) stats->stat_IfHCInUcastPkts_lo; 5599 5600 sc->stat_IfHCInMulticastPkts = 5601 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 5602 (u64) stats->stat_IfHCInMulticastPkts_lo; 5603 5604 sc->stat_IfHCInBroadcastPkts = 5605 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5606 (u64) stats->stat_IfHCInBroadcastPkts_lo; 5607 5608 sc->stat_IfHCOutUcastPkts = 5609 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 5610 (u64) stats->stat_IfHCOutUcastPkts_lo; 5611 5612 sc->stat_IfHCOutMulticastPkts = 5613 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5614 (u64) stats->stat_IfHCOutMulticastPkts_lo; 5615 5616 sc->stat_IfHCOutBroadcastPkts = 5617 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5618 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 5619 5620 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5621 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5622 5623 sc->stat_Dot3StatsCarrierSenseErrors = 5624 stats->stat_Dot3StatsCarrierSenseErrors; 5625 5626 sc->stat_Dot3StatsFCSErrors = 5627 stats->stat_Dot3StatsFCSErrors; 5628 5629 sc->stat_Dot3StatsAlignmentErrors = 5630 stats->stat_Dot3StatsAlignmentErrors; 5631 5632 sc->stat_Dot3StatsSingleCollisionFrames = 5633 stats->stat_Dot3StatsSingleCollisionFrames; 5634 5635 sc->stat_Dot3StatsMultipleCollisionFrames = 5636 stats->stat_Dot3StatsMultipleCollisionFrames; 5637 5638 sc->stat_Dot3StatsDeferredTransmissions = 5639 stats->stat_Dot3StatsDeferredTransmissions; 5640 5641 sc->stat_Dot3StatsExcessiveCollisions = 5642 stats->stat_Dot3StatsExcessiveCollisions; 5643 5644 sc->stat_Dot3StatsLateCollisions = 5645 stats->stat_Dot3StatsLateCollisions; 5646 5647 sc->stat_EtherStatsCollisions = 5648 stats->stat_EtherStatsCollisions; 5649 5650 sc->stat_EtherStatsFragments = 5651 stats->stat_EtherStatsFragments; 5652 5653 sc->stat_EtherStatsJabbers = 5654 stats->stat_EtherStatsJabbers; 5655 5656 sc->stat_EtherStatsUndersizePkts = 5657 stats->stat_EtherStatsUndersizePkts; 5658 5659 sc->stat_EtherStatsOverrsizePkts = 5660 stats->stat_EtherStatsOverrsizePkts; 5661 5662 sc->stat_EtherStatsPktsRx64Octets = 5663 stats->stat_EtherStatsPktsRx64Octets; 5664 5665 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5666 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5667 5668 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5669 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5670 5671 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5672 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5673 5674 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5675 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5676 5677 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5678 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5679 5680 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5681 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5682 5683 sc->stat_EtherStatsPktsTx64Octets = 5684 stats->stat_EtherStatsPktsTx64Octets; 5685 5686 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5687 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5688 5689 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5690 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5691 5692 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5693 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5694 5695 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5696 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5697 5698 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5699 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5700 5701 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5702 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5703 5704 sc->stat_XonPauseFramesReceived = 5705 stats->stat_XonPauseFramesReceived; 5706 5707 sc->stat_XoffPauseFramesReceived = 5708 stats->stat_XoffPauseFramesReceived; 5709 5710 sc->stat_OutXonSent = 5711 stats->stat_OutXonSent; 5712 5713 sc->stat_OutXoffSent = 5714 stats->stat_OutXoffSent; 5715 5716 sc->stat_FlowControlDone = 5717 stats->stat_FlowControlDone; 5718 5719 sc->stat_MacControlFramesReceived = 5720 stats->stat_MacControlFramesReceived; 5721 5722 sc->stat_XoffStateEntered = 5723 stats->stat_XoffStateEntered; 5724 5725 sc->stat_IfInFramesL2FilterDiscards = 5726 stats->stat_IfInFramesL2FilterDiscards; 5727 5728 sc->stat_IfInRuleCheckerDiscards = 5729 stats->stat_IfInRuleCheckerDiscards; 5730 5731 sc->stat_IfInFTQDiscards = 5732 stats->stat_IfInFTQDiscards; 5733 5734 sc->stat_IfInMBUFDiscards = 5735 stats->stat_IfInMBUFDiscards; 5736 5737 sc->stat_IfInRuleCheckerP4Hit = 5738 stats->stat_IfInRuleCheckerP4Hit; 5739 5740 sc->stat_CatchupInRuleCheckerDiscards = 5741 stats->stat_CatchupInRuleCheckerDiscards; 5742 5743 sc->stat_CatchupInFTQDiscards = 5744 stats->stat_CatchupInFTQDiscards; 5745 5746 sc->stat_CatchupInMBUFDiscards = 5747 stats->stat_CatchupInMBUFDiscards; 5748 5749 sc->stat_CatchupInRuleCheckerP4Hit = 5750 stats->stat_CatchupInRuleCheckerP4Hit; 5751 5752 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 5753 5754 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __FUNCTION__); 5755 } 5756 5757 5758 /****************************************************************************/ 5759 /* Periodic function to notify the bootcode that the driver is still */ 5760 /* present. */ 5761 /* */ 5762 /* Returns: */ 5763 /* Nothing. */ 5764 /****************************************************************************/ 5765 static void 5766 bce_pulse(void *xsc) 5767 { 5768 struct bce_softc *sc = xsc; 5769 u32 msg; 5770 5771 DBPRINT(sc, BCE_EXCESSIVE_MISC, "pulse\n"); 5772 5773 BCE_LOCK_ASSERT(sc); 5774 5775 /* Tell the firmware that the driver is still running. */ 5776 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 5777 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg); 5778 5779 /* Schedule the next pulse. */ 5780 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 5781 5782 return; 5783 } 5784 5785 5786 /****************************************************************************/ 5787 /* Periodic function to perform maintenance tasks. */ 5788 /* */ 5789 /* Returns: */ 5790 /* Nothing. */ 5791 /****************************************************************************/ 5792 static void 5793 bce_tick(void *xsc) 5794 { 5795 struct bce_softc *sc = xsc; 5796 struct mii_data *mii; 5797 struct ifnet *ifp; 5798 5799 ifp = sc->bce_ifp; 5800 5801 BCE_LOCK_ASSERT(sc); 5802 5803 /* Update the statistics from the hardware statistics block. */ 5804 bce_stats_update(sc); 5805 5806 /* Check that chip hasn't hung. */ 5807 bce_watchdog(sc); 5808 5809 /* Schedule the next tick. */ 5810 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 5811 5812 /* If link is up already up then we're done. */ 5813 if (sc->bce_link) 5814 goto bce_tick_locked_exit; 5815 5816 mii = device_get_softc(sc->bce_miibus); 5817 mii_tick(mii); 5818 5819 /* Check if the link has come up. */ 5820 if (!sc->bce_link && mii->mii_media_status & IFM_ACTIVE && 5821 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5822 sc->bce_link++; 5823 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 5824 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) && 5825 bootverbose) 5826 BCE_PRINTF("Gigabit link up\n"); 5827 /* Now that link is up, handle any outstanding TX traffic. */ 5828 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5829 bce_start_locked(ifp); 5830 } 5831 5832 bce_tick_locked_exit: 5833 return; 5834 } 5835 5836 5837 #ifdef BCE_DEBUG 5838 /****************************************************************************/ 5839 /* Allows the driver state to be dumped through the sysctl interface. */ 5840 /* */ 5841 /* Returns: */ 5842 /* 0 for success, positive value for failure. */ 5843 /****************************************************************************/ 5844 static int 5845 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 5846 { 5847 int error; 5848 int result; 5849 struct bce_softc *sc; 5850 5851 result = -1; 5852 error = sysctl_handle_int(oidp, &result, 0, req); 5853 5854 if (error || !req->newptr) 5855 return (error); 5856 5857 if (result == 1) { 5858 sc = (struct bce_softc *)arg1; 5859 bce_dump_driver_state(sc); 5860 } 5861 5862 return error; 5863 } 5864 5865 5866 /****************************************************************************/ 5867 /* Allows the hardware state to be dumped through the sysctl interface. */ 5868 /* */ 5869 /* Returns: */ 5870 /* 0 for success, positive value for failure. */ 5871 /****************************************************************************/ 5872 static int 5873 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 5874 { 5875 int error; 5876 int result; 5877 struct bce_softc *sc; 5878 5879 result = -1; 5880 error = sysctl_handle_int(oidp, &result, 0, req); 5881 5882 if (error || !req->newptr) 5883 return (error); 5884 5885 if (result == 1) { 5886 sc = (struct bce_softc *)arg1; 5887 bce_dump_hw_state(sc); 5888 } 5889 5890 return error; 5891 } 5892 5893 5894 /****************************************************************************/ 5895 /* Allows the bootcode state to be dumped through the sysctl interface. */ 5896 /* */ 5897 /* Returns: */ 5898 /* 0 for success, positive value for failure. */ 5899 /****************************************************************************/ 5900 static int 5901 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 5902 { 5903 int error; 5904 int result; 5905 struct bce_softc *sc; 5906 5907 result = -1; 5908 error = sysctl_handle_int(oidp, &result, 0, req); 5909 5910 if (error || !req->newptr) 5911 return (error); 5912 5913 if (result == 1) { 5914 sc = (struct bce_softc *)arg1; 5915 bce_dump_bc_state(sc); 5916 } 5917 5918 return error; 5919 } 5920 5921 5922 /****************************************************************************/ 5923 /* Provides a sysctl interface to allow dumping the RX chain. */ 5924 /* */ 5925 /* Returns: */ 5926 /* 0 for success, positive value for failure. */ 5927 /****************************************************************************/ 5928 static int 5929 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS) 5930 { 5931 int error; 5932 int result; 5933 struct bce_softc *sc; 5934 5935 result = -1; 5936 error = sysctl_handle_int(oidp, &result, 0, req); 5937 5938 if (error || !req->newptr) 5939 return (error); 5940 5941 if (result == 1) { 5942 sc = (struct bce_softc *)arg1; 5943 bce_dump_rx_chain(sc, 0, sc->max_rx_bd); 5944 } 5945 5946 return error; 5947 } 5948 5949 5950 /****************************************************************************/ 5951 /* Provides a sysctl interface to allow dumping the TX chain. */ 5952 /* */ 5953 /* Returns: */ 5954 /* 0 for success, positive value for failure. */ 5955 /****************************************************************************/ 5956 static int 5957 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 5958 { 5959 int error; 5960 int result; 5961 struct bce_softc *sc; 5962 5963 result = -1; 5964 error = sysctl_handle_int(oidp, &result, 0, req); 5965 5966 if (error || !req->newptr) 5967 return (error); 5968 5969 if (result == 1) { 5970 sc = (struct bce_softc *)arg1; 5971 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 5972 } 5973 5974 return error; 5975 } 5976 5977 5978 /****************************************************************************/ 5979 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 5980 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 5981 /* */ 5982 /* Returns: */ 5983 /* 0 for success, positive value for failure. */ 5984 /****************************************************************************/ 5985 static int 5986 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5987 { 5988 struct bce_softc *sc; 5989 int error; 5990 u32 val, result; 5991 5992 result = -1; 5993 error = sysctl_handle_int(oidp, &result, 0, req); 5994 if (error || (req->newptr == NULL)) 5995 return (error); 5996 5997 /* Make sure the register is accessible. */ 5998 if (result < 0x8000) { 5999 sc = (struct bce_softc *)arg1; 6000 val = REG_RD(sc, result); 6001 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 6002 } else if (result < 0x0280000) { 6003 sc = (struct bce_softc *)arg1; 6004 val = REG_RD_IND(sc, result); 6005 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 6006 } 6007 6008 return (error); 6009 } 6010 6011 6012 /****************************************************************************/ 6013 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 6014 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 6015 /* */ 6016 /* Returns: */ 6017 /* 0 for success, positive value for failure. */ 6018 /****************************************************************************/ 6019 static int 6020 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 6021 { 6022 struct bce_softc *sc; 6023 device_t dev; 6024 int error, result; 6025 u16 val; 6026 6027 result = -1; 6028 error = sysctl_handle_int(oidp, &result, 0, req); 6029 if (error || (req->newptr == NULL)) 6030 return (error); 6031 6032 /* Make sure the register is accessible. */ 6033 if (result < 0x20) { 6034 sc = (struct bce_softc *)arg1; 6035 dev = sc->bce_dev; 6036 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 6037 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 6038 } 6039 return (error); 6040 } 6041 6042 6043 /****************************************************************************/ 6044 /* Provides a sysctl interface to forcing the driver to dump state and */ 6045 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 6046 /* */ 6047 /* Returns: */ 6048 /* 0 for success, positive value for failure. */ 6049 /****************************************************************************/ 6050 static int 6051 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 6052 { 6053 int error; 6054 int result; 6055 struct bce_softc *sc; 6056 6057 result = -1; 6058 error = sysctl_handle_int(oidp, &result, 0, req); 6059 6060 if (error || !req->newptr) 6061 return (error); 6062 6063 if (result == 1) { 6064 sc = (struct bce_softc *)arg1; 6065 bce_breakpoint(sc); 6066 } 6067 6068 return error; 6069 } 6070 #endif 6071 6072 6073 /****************************************************************************/ 6074 /* Adds any sysctl parameters for tuning or debugging purposes. */ 6075 /* */ 6076 /* Returns: */ 6077 /* 0 for success, positive value for failure. */ 6078 /****************************************************************************/ 6079 static void 6080 bce_add_sysctls(struct bce_softc *sc) 6081 { 6082 struct sysctl_ctx_list *ctx; 6083 struct sysctl_oid_list *children; 6084 6085 ctx = device_get_sysctl_ctx(sc->bce_dev); 6086 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 6087 6088 #ifdef BCE_DEBUG 6089 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6090 "rx_low_watermark", 6091 CTLFLAG_RD, &sc->rx_low_watermark, 6092 0, "Lowest level of free rx_bd's"); 6093 6094 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6095 "rx_empty_count", 6096 CTLFLAG_RD, &sc->rx_empty_count, 6097 0, "Number of times the RX chain was empty"); 6098 6099 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6100 "tx_hi_watermark", 6101 CTLFLAG_RD, &sc->tx_hi_watermark, 6102 0, "Highest level of used tx_bd's"); 6103 6104 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6105 "tx_full_count", 6106 CTLFLAG_RD, &sc->tx_full_count, 6107 0, "Number of times the TX chain was full"); 6108 6109 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6110 "l2fhdr_status_errors", 6111 CTLFLAG_RD, &sc->l2fhdr_status_errors, 6112 0, "l2_fhdr status errors"); 6113 6114 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6115 "unexpected_attentions", 6116 CTLFLAG_RD, &sc->unexpected_attentions, 6117 0, "unexpected attentions"); 6118 6119 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6120 "lost_status_block_updates", 6121 CTLFLAG_RD, &sc->lost_status_block_updates, 6122 0, "lost status block updates"); 6123 6124 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6125 "mbuf_sim_alloc_failed", 6126 CTLFLAG_RD, &sc->mbuf_sim_alloc_failed, 6127 0, "mbuf cluster simulated allocation failures"); 6128 6129 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6130 "requested_tso_frames", 6131 CTLFLAG_RD, &sc->requested_tso_frames, 6132 0, "The number of TSO frames received"); 6133 6134 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6135 "rx_mbuf_segs[1]", 6136 CTLFLAG_RD, &sc->rx_mbuf_segs[1], 6137 0, "mbuf cluster with 1 segment"); 6138 6139 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6140 "rx_mbuf_segs[2]", 6141 CTLFLAG_RD, &sc->rx_mbuf_segs[2], 6142 0, "mbuf cluster with 2 segments"); 6143 6144 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6145 "rx_mbuf_segs[3]", 6146 CTLFLAG_RD, &sc->rx_mbuf_segs[3], 6147 0, "mbuf cluster with 3 segments"); 6148 6149 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6150 "rx_mbuf_segs[4]", 6151 CTLFLAG_RD, &sc->rx_mbuf_segs[4], 6152 0, "mbuf cluster with 4 segments"); 6153 6154 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6155 "rx_mbuf_segs[5]", 6156 CTLFLAG_RD, &sc->rx_mbuf_segs[5], 6157 0, "mbuf cluster with 5 segments"); 6158 6159 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6160 "rx_mbuf_segs[6]", 6161 CTLFLAG_RD, &sc->rx_mbuf_segs[6], 6162 0, "mbuf cluster with 6 segments"); 6163 6164 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6165 "rx_mbuf_segs[7]", 6166 CTLFLAG_RD, &sc->rx_mbuf_segs[7], 6167 0, "mbuf cluster with 7 segments"); 6168 6169 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6170 "rx_mbuf_segs[8]", 6171 CTLFLAG_RD, &sc->rx_mbuf_segs[8], 6172 0, "mbuf cluster with 8 segments"); 6173 6174 #endif 6175 6176 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6177 "mbuf_alloc_failed", 6178 CTLFLAG_RD, &sc->mbuf_alloc_failed, 6179 0, "mbuf cluster allocation failures"); 6180 6181 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6182 "tx_dma_map_failures", 6183 CTLFLAG_RD, &sc->tx_dma_map_failures, 6184 0, "tx dma mapping failures"); 6185 6186 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6187 "stat_IfHcInOctets", 6188 CTLFLAG_RD, &sc->stat_IfHCInOctets, 6189 "Bytes received"); 6190 6191 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6192 "stat_IfHCInBadOctets", 6193 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 6194 "Bad bytes received"); 6195 6196 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6197 "stat_IfHCOutOctets", 6198 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 6199 "Bytes sent"); 6200 6201 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6202 "stat_IfHCOutBadOctets", 6203 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 6204 "Bad bytes sent"); 6205 6206 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6207 "stat_IfHCInUcastPkts", 6208 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 6209 "Unicast packets received"); 6210 6211 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6212 "stat_IfHCInMulticastPkts", 6213 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 6214 "Multicast packets received"); 6215 6216 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6217 "stat_IfHCInBroadcastPkts", 6218 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 6219 "Broadcast packets received"); 6220 6221 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6222 "stat_IfHCOutUcastPkts", 6223 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 6224 "Unicast packets sent"); 6225 6226 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6227 "stat_IfHCOutMulticastPkts", 6228 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 6229 "Multicast packets sent"); 6230 6231 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6232 "stat_IfHCOutBroadcastPkts", 6233 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 6234 "Broadcast packets sent"); 6235 6236 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6237 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 6238 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 6239 0, "Internal MAC transmit errors"); 6240 6241 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6242 "stat_Dot3StatsCarrierSenseErrors", 6243 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 6244 0, "Carrier sense errors"); 6245 6246 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6247 "stat_Dot3StatsFCSErrors", 6248 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 6249 0, "Frame check sequence errors"); 6250 6251 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6252 "stat_Dot3StatsAlignmentErrors", 6253 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 6254 0, "Alignment errors"); 6255 6256 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6257 "stat_Dot3StatsSingleCollisionFrames", 6258 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 6259 0, "Single Collision Frames"); 6260 6261 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6262 "stat_Dot3StatsMultipleCollisionFrames", 6263 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 6264 0, "Multiple Collision Frames"); 6265 6266 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6267 "stat_Dot3StatsDeferredTransmissions", 6268 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 6269 0, "Deferred Transmissions"); 6270 6271 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6272 "stat_Dot3StatsExcessiveCollisions", 6273 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 6274 0, "Excessive Collisions"); 6275 6276 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6277 "stat_Dot3StatsLateCollisions", 6278 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 6279 0, "Late Collisions"); 6280 6281 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6282 "stat_EtherStatsCollisions", 6283 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 6284 0, "Collisions"); 6285 6286 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6287 "stat_EtherStatsFragments", 6288 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 6289 0, "Fragments"); 6290 6291 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6292 "stat_EtherStatsJabbers", 6293 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 6294 0, "Jabbers"); 6295 6296 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6297 "stat_EtherStatsUndersizePkts", 6298 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 6299 0, "Undersize packets"); 6300 6301 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6302 "stat_EtherStatsOverrsizePkts", 6303 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts, 6304 0, "stat_EtherStatsOverrsizePkts"); 6305 6306 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6307 "stat_EtherStatsPktsRx64Octets", 6308 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 6309 0, "Bytes received in 64 byte packets"); 6310 6311 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6312 "stat_EtherStatsPktsRx65Octetsto127Octets", 6313 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 6314 0, "Bytes received in 65 to 127 byte packets"); 6315 6316 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6317 "stat_EtherStatsPktsRx128Octetsto255Octets", 6318 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 6319 0, "Bytes received in 128 to 255 byte packets"); 6320 6321 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6322 "stat_EtherStatsPktsRx256Octetsto511Octets", 6323 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 6324 0, "Bytes received in 256 to 511 byte packets"); 6325 6326 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6327 "stat_EtherStatsPktsRx512Octetsto1023Octets", 6328 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 6329 0, "Bytes received in 512 to 1023 byte packets"); 6330 6331 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6332 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 6333 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 6334 0, "Bytes received in 1024 t0 1522 byte packets"); 6335 6336 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6337 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 6338 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 6339 0, "Bytes received in 1523 to 9022 byte packets"); 6340 6341 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6342 "stat_EtherStatsPktsTx64Octets", 6343 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 6344 0, "Bytes sent in 64 byte packets"); 6345 6346 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6347 "stat_EtherStatsPktsTx65Octetsto127Octets", 6348 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 6349 0, "Bytes sent in 65 to 127 byte packets"); 6350 6351 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6352 "stat_EtherStatsPktsTx128Octetsto255Octets", 6353 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 6354 0, "Bytes sent in 128 to 255 byte packets"); 6355 6356 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6357 "stat_EtherStatsPktsTx256Octetsto511Octets", 6358 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 6359 0, "Bytes sent in 256 to 511 byte packets"); 6360 6361 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6362 "stat_EtherStatsPktsTx512Octetsto1023Octets", 6363 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 6364 0, "Bytes sent in 512 to 1023 byte packets"); 6365 6366 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6367 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 6368 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 6369 0, "Bytes sent in 1024 to 1522 byte packets"); 6370 6371 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6372 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 6373 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 6374 0, "Bytes sent in 1523 to 9022 byte packets"); 6375 6376 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6377 "stat_XonPauseFramesReceived", 6378 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 6379 0, "XON pause frames receved"); 6380 6381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6382 "stat_XoffPauseFramesReceived", 6383 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 6384 0, "XOFF pause frames received"); 6385 6386 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6387 "stat_OutXonSent", 6388 CTLFLAG_RD, &sc->stat_OutXonSent, 6389 0, "XON pause frames sent"); 6390 6391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6392 "stat_OutXoffSent", 6393 CTLFLAG_RD, &sc->stat_OutXoffSent, 6394 0, "XOFF pause frames sent"); 6395 6396 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6397 "stat_FlowControlDone", 6398 CTLFLAG_RD, &sc->stat_FlowControlDone, 6399 0, "Flow control done"); 6400 6401 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6402 "stat_MacControlFramesReceived", 6403 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 6404 0, "MAC control frames received"); 6405 6406 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6407 "stat_XoffStateEntered", 6408 CTLFLAG_RD, &sc->stat_XoffStateEntered, 6409 0, "XOFF state entered"); 6410 6411 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6412 "stat_IfInFramesL2FilterDiscards", 6413 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 6414 0, "Received L2 packets discarded"); 6415 6416 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6417 "stat_IfInRuleCheckerDiscards", 6418 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 6419 0, "Received packets discarded by rule"); 6420 6421 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6422 "stat_IfInFTQDiscards", 6423 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 6424 0, "Received packet FTQ discards"); 6425 6426 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6427 "stat_IfInMBUFDiscards", 6428 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 6429 0, "Received packets discarded due to lack of controller buffer memory"); 6430 6431 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6432 "stat_IfInRuleCheckerP4Hit", 6433 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 6434 0, "Received packets rule checker hits"); 6435 6436 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6437 "stat_CatchupInRuleCheckerDiscards", 6438 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 6439 0, "Received packets discarded in Catchup path"); 6440 6441 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6442 "stat_CatchupInFTQDiscards", 6443 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 6444 0, "Received packets discarded in FTQ in Catchup path"); 6445 6446 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6447 "stat_CatchupInMBUFDiscards", 6448 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 6449 0, "Received packets discarded in controller buffer memory in Catchup path"); 6450 6451 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6452 "stat_CatchupInRuleCheckerP4Hit", 6453 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 6454 0, "Received packets rule checker hits in Catchup path"); 6455 6456 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6457 "com_no_buffers", 6458 CTLFLAG_RD, &sc->com_no_buffers, 6459 0, "Valid packets received but no RX buffers available"); 6460 6461 #ifdef BCE_DEBUG 6462 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6463 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 6464 (void *)sc, 0, 6465 bce_sysctl_driver_state, "I", "Drive state information"); 6466 6467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6468 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 6469 (void *)sc, 0, 6470 bce_sysctl_hw_state, "I", "Hardware state information"); 6471 6472 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6473 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 6474 (void *)sc, 0, 6475 bce_sysctl_bc_state, "I", "Bootcode state information"); 6476 6477 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6478 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW, 6479 (void *)sc, 0, 6480 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain"); 6481 6482 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6483 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 6484 (void *)sc, 0, 6485 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 6486 6487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6488 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 6489 (void *)sc, 0, 6490 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 6491 6492 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6493 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 6494 (void *)sc, 0, 6495 bce_sysctl_reg_read, "I", "Register read"); 6496 6497 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6498 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 6499 (void *)sc, 0, 6500 bce_sysctl_phy_read, "I", "PHY register read"); 6501 6502 #endif 6503 6504 } 6505 6506 6507 /****************************************************************************/ 6508 /* BCE Debug Routines */ 6509 /****************************************************************************/ 6510 #ifdef BCE_DEBUG 6511 6512 /****************************************************************************/ 6513 /* Freezes the controller to allow for a cohesive state dump. */ 6514 /* */ 6515 /* Returns: */ 6516 /* Nothing. */ 6517 /****************************************************************************/ 6518 static void 6519 bce_freeze_controller(struct bce_softc *sc) 6520 { 6521 u32 val; 6522 val = REG_RD(sc, BCE_MISC_COMMAND); 6523 val |= BCE_MISC_COMMAND_DISABLE_ALL; 6524 REG_WR(sc, BCE_MISC_COMMAND, val); 6525 6526 } 6527 6528 6529 /****************************************************************************/ 6530 /* Unfreezes the controller after a freeze operation. This may not always */ 6531 /* work and the controller will require a reset! */ 6532 /* */ 6533 /* Returns: */ 6534 /* Nothing. */ 6535 /****************************************************************************/ 6536 static void 6537 bce_unfreeze_controller(struct bce_softc *sc) 6538 { 6539 u32 val; 6540 val = REG_RD(sc, BCE_MISC_COMMAND); 6541 val |= BCE_MISC_COMMAND_ENABLE_ALL; 6542 REG_WR(sc, BCE_MISC_COMMAND, val); 6543 6544 } 6545 6546 /****************************************************************************/ 6547 /* Prints out information about an mbuf. */ 6548 /* */ 6549 /* Returns: */ 6550 /* Nothing. */ 6551 /****************************************************************************/ 6552 static void 6553 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 6554 { 6555 u32 val_hi, val_lo; 6556 struct mbuf *mp = m; 6557 6558 if (m == NULL) { 6559 BCE_PRINTF("mbuf: null pointer\n"); 6560 return; 6561 } 6562 6563 while (mp) { 6564 val_hi = BCE_ADDR_HI(mp); 6565 val_lo = BCE_ADDR_LO(mp); 6566 BCE_PRINTF("mbuf: vaddr = 0x%08X:%08X, m_len = %d, m_flags = ( ", 6567 val_hi, val_lo, mp->m_len); 6568 6569 if (mp->m_flags & M_EXT) 6570 printf("M_EXT "); 6571 if (mp->m_flags & M_PKTHDR) 6572 printf("M_PKTHDR "); 6573 if (mp->m_flags & M_EOR) 6574 printf("M_EOR "); 6575 if (mp->m_flags & M_RDONLY) 6576 printf("M_RDONLY "); 6577 6578 val_hi = BCE_ADDR_HI(mp->m_data); 6579 val_lo = BCE_ADDR_LO(mp->m_data); 6580 printf(") m_data = 0x%08X:%08X\n", 6581 val_hi, val_lo); 6582 6583 if (mp->m_flags & M_PKTHDR) { 6584 BCE_PRINTF("- m_pkthdr: flags = ( "); 6585 if (mp->m_flags & M_BCAST) 6586 printf("M_BCAST "); 6587 if (mp->m_flags & M_MCAST) 6588 printf("M_MCAST "); 6589 if (mp->m_flags & M_FRAG) 6590 printf("M_FRAG "); 6591 if (mp->m_flags & M_FIRSTFRAG) 6592 printf("M_FIRSTFRAG "); 6593 if (mp->m_flags & M_LASTFRAG) 6594 printf("M_LASTFRAG "); 6595 if (mp->m_flags & M_VLANTAG) 6596 printf("M_VLANTAG "); 6597 if (mp->m_flags & M_PROMISC) 6598 printf("M_PROMISC "); 6599 printf(") csum_flags = ( "); 6600 if (mp->m_pkthdr.csum_flags & CSUM_IP) 6601 printf("CSUM_IP "); 6602 if (mp->m_pkthdr.csum_flags & CSUM_TCP) 6603 printf("CSUM_TCP "); 6604 if (mp->m_pkthdr.csum_flags & CSUM_UDP) 6605 printf("CSUM_UDP "); 6606 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS) 6607 printf("CSUM_IP_FRAGS "); 6608 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT) 6609 printf("CSUM_FRAGMENT "); 6610 if (mp->m_pkthdr.csum_flags & CSUM_TSO) 6611 printf("CSUM_TSO "); 6612 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED) 6613 printf("CSUM_IP_CHECKED "); 6614 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID) 6615 printf("CSUM_IP_VALID "); 6616 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID) 6617 printf("CSUM_DATA_VALID "); 6618 printf(")\n"); 6619 } 6620 6621 if (mp->m_flags & M_EXT) { 6622 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf); 6623 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf); 6624 BCE_PRINTF("- m_ext: vaddr = 0x%08X:%08X, ext_size = %d, type = ", 6625 val_hi, val_lo, mp->m_ext.ext_size); 6626 switch (mp->m_ext.ext_type) { 6627 case EXT_CLUSTER: printf("EXT_CLUSTER\n"); break; 6628 case EXT_SFBUF: printf("EXT_SFBUF\n"); break; 6629 case EXT_JUMBO9: printf("EXT_JUMBO9\n"); break; 6630 case EXT_JUMBO16: printf("EXT_JUMBO16\n"); break; 6631 case EXT_PACKET: printf("EXT_PACKET\n"); break; 6632 case EXT_MBUF: printf("EXT_MBUF\n"); break; 6633 case EXT_NET_DRV: printf("EXT_NET_DRV\n"); break; 6634 case EXT_MOD_TYPE: printf("EXT_MDD_TYPE\n"); break; 6635 case EXT_DISPOSABLE: printf("EXT_DISPOSABLE\n"); break; 6636 case EXT_EXTREF: printf("EXT_EXTREF\n"); break; 6637 default: printf("UNKNOWN\n"); 6638 } 6639 } 6640 6641 mp = mp->m_next; 6642 } 6643 } 6644 6645 6646 /****************************************************************************/ 6647 /* Prints out the mbufs in the TX mbuf chain. */ 6648 /* */ 6649 /* Returns: */ 6650 /* Nothing. */ 6651 /****************************************************************************/ 6652 static void 6653 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6654 { 6655 struct mbuf *m; 6656 6657 BCE_PRINTF( 6658 "----------------------------" 6659 " tx mbuf data " 6660 "----------------------------\n"); 6661 6662 for (int i = 0; i < count; i++) { 6663 m = sc->tx_mbuf_ptr[chain_prod]; 6664 BCE_PRINTF("txmbuf[%d]\n", chain_prod); 6665 bce_dump_mbuf(sc, m); 6666 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 6667 } 6668 6669 BCE_PRINTF( 6670 "----------------------------" 6671 "----------------" 6672 "----------------------------\n"); 6673 } 6674 6675 6676 /****************************************************************************/ 6677 /* Prints out the mbufs in the RX mbuf chain. */ 6678 /* */ 6679 /* Returns: */ 6680 /* Nothing. */ 6681 /****************************************************************************/ 6682 static void 6683 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6684 { 6685 struct mbuf *m; 6686 6687 BCE_PRINTF( 6688 "----------------------------" 6689 " rx mbuf data " 6690 "----------------------------\n"); 6691 6692 for (int i = 0; i < count; i++) { 6693 m = sc->rx_mbuf_ptr[chain_prod]; 6694 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 6695 bce_dump_mbuf(sc, m); 6696 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6697 } 6698 6699 6700 BCE_PRINTF( 6701 "----------------------------" 6702 "----------------" 6703 "----------------------------\n"); 6704 } 6705 6706 6707 /****************************************************************************/ 6708 /* Prints out a tx_bd structure. */ 6709 /* */ 6710 /* Returns: */ 6711 /* Nothing. */ 6712 /****************************************************************************/ 6713 static void 6714 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 6715 { 6716 if (idx > MAX_TX_BD) 6717 /* Index out of range. */ 6718 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6719 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6720 /* TX Chain page pointer. */ 6721 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6722 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo); 6723 else { 6724 /* Normal tx_bd entry. */ 6725 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6726 "vlan tag= 0x%04X, flags = 0x%04X (", idx, 6727 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6728 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6729 txbd->tx_bd_flags); 6730 6731 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) 6732 printf(" CONN_FAULT"); 6733 6734 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) 6735 printf(" TCP_UDP_CKSUM"); 6736 6737 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) 6738 printf(" IP_CKSUM"); 6739 6740 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) 6741 printf(" VLAN"); 6742 6743 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) 6744 printf(" COAL_NOW"); 6745 6746 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) 6747 printf(" DONT_GEN_CRC"); 6748 6749 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) 6750 printf(" START"); 6751 6752 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) 6753 printf(" END"); 6754 6755 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) 6756 printf(" LSO"); 6757 6758 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) 6759 printf(" OPTION_WORD"); 6760 6761 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) 6762 printf(" FLAGS"); 6763 6764 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) 6765 printf(" SNAP"); 6766 6767 printf(" )\n"); 6768 } 6769 6770 } 6771 6772 6773 /****************************************************************************/ 6774 /* Prints out a rx_bd structure. */ 6775 /* */ 6776 /* Returns: */ 6777 /* Nothing. */ 6778 /****************************************************************************/ 6779 static void 6780 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 6781 { 6782 if (idx > MAX_RX_BD) 6783 /* Index out of range. */ 6784 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6785 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6786 /* TX Chain page pointer. */ 6787 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6788 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo); 6789 else 6790 /* Normal tx_bd entry. */ 6791 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6792 "flags = 0x%08X\n", idx, 6793 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6794 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6795 } 6796 6797 6798 /****************************************************************************/ 6799 /* Prints out a l2_fhdr structure. */ 6800 /* */ 6801 /* Returns: */ 6802 /* Nothing. */ 6803 /****************************************************************************/ 6804 static void 6805 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6806 { 6807 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%08X, " 6808 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6809 "tcp_udp_xsum = 0x%04X\n", idx, 6810 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6811 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6812 l2fhdr->l2_fhdr_tcp_udp_xsum); 6813 } 6814 6815 6816 /****************************************************************************/ 6817 /* Prints out the TX chain. */ 6818 /* */ 6819 /* Returns: */ 6820 /* Nothing. */ 6821 /****************************************************************************/ 6822 static void 6823 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count) 6824 { 6825 struct tx_bd *txbd; 6826 6827 /* First some info about the tx_bd chain structure. */ 6828 BCE_PRINTF( 6829 "----------------------------" 6830 " tx_bd chain " 6831 "----------------------------\n"); 6832 6833 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 6834 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 6835 6836 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6837 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 6838 6839 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 6840 6841 BCE_PRINTF( 6842 "----------------------------" 6843 " tx_bd data " 6844 "----------------------------\n"); 6845 6846 /* Now print out the tx_bd's themselves. */ 6847 for (int i = 0; i < count; i++) { 6848 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6849 bce_dump_txbd(sc, tx_prod, txbd); 6850 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6851 } 6852 6853 BCE_PRINTF( 6854 "----------------------------" 6855 "----------------" 6856 "----------------------------\n"); 6857 } 6858 6859 6860 /****************************************************************************/ 6861 /* Prints out the RX chain. */ 6862 /* */ 6863 /* Returns: */ 6864 /* Nothing. */ 6865 /****************************************************************************/ 6866 static void 6867 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count) 6868 { 6869 struct rx_bd *rxbd; 6870 6871 /* First some info about the tx_bd chain structure. */ 6872 BCE_PRINTF( 6873 "----------------------------" 6874 " rx_bd chain " 6875 "----------------------------\n"); 6876 6877 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 6878 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 6879 6880 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6881 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 6882 6883 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 6884 6885 BCE_PRINTF( 6886 "----------------------------" 6887 " rx_bd data " 6888 "----------------------------\n"); 6889 6890 /* Now print out the rx_bd's themselves. */ 6891 for (int i = 0; i < count; i++) { 6892 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6893 bce_dump_rxbd(sc, rx_prod, rxbd); 6894 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6895 } 6896 6897 BCE_PRINTF( 6898 "----------------------------" 6899 "----------------" 6900 "----------------------------\n"); 6901 } 6902 6903 6904 /****************************************************************************/ 6905 /* Prints out the status block from host memory. */ 6906 /* */ 6907 /* Returns: */ 6908 /* Nothing. */ 6909 /****************************************************************************/ 6910 static void 6911 bce_dump_status_block(struct bce_softc *sc) 6912 { 6913 struct status_block *sblk; 6914 6915 sblk = sc->status_block; 6916 6917 BCE_PRINTF( 6918 "----------------------------" 6919 " Status Block " 6920 "----------------------------\n"); 6921 6922 BCE_PRINTF(" 0x%08X - attn_bits\n", 6923 sblk->status_attn_bits); 6924 6925 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 6926 sblk->status_attn_bits_ack); 6927 6928 BCE_PRINTF("0x%04X(0x%04X) - rx_cons0\n", 6929 sblk->status_rx_quick_consumer_index0, 6930 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0)); 6931 6932 BCE_PRINTF("0x%04X(0x%04X) - tx_cons0\n", 6933 sblk->status_tx_quick_consumer_index0, 6934 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0)); 6935 6936 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 6937 6938 /* Theses indices are not used for normal L2 drivers. */ 6939 if (sblk->status_rx_quick_consumer_index1) 6940 BCE_PRINTF("0x%04X(0x%04X) - rx_cons1\n", 6941 sblk->status_rx_quick_consumer_index1, 6942 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1)); 6943 6944 if (sblk->status_tx_quick_consumer_index1) 6945 BCE_PRINTF("0x%04X(0x%04X) - tx_cons1\n", 6946 sblk->status_tx_quick_consumer_index1, 6947 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1)); 6948 6949 if (sblk->status_rx_quick_consumer_index2) 6950 BCE_PRINTF("0x%04X(0x%04X)- rx_cons2\n", 6951 sblk->status_rx_quick_consumer_index2, 6952 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2)); 6953 6954 if (sblk->status_tx_quick_consumer_index2) 6955 BCE_PRINTF("0x%04X(0x%04X) - tx_cons2\n", 6956 sblk->status_tx_quick_consumer_index2, 6957 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2)); 6958 6959 if (sblk->status_rx_quick_consumer_index3) 6960 BCE_PRINTF("0x%04X(0x%04X) - rx_cons3\n", 6961 sblk->status_rx_quick_consumer_index3, 6962 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3)); 6963 6964 if (sblk->status_tx_quick_consumer_index3) 6965 BCE_PRINTF("0x%04X(0x%04X) - tx_cons3\n", 6966 sblk->status_tx_quick_consumer_index3, 6967 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3)); 6968 6969 if (sblk->status_rx_quick_consumer_index4 || 6970 sblk->status_rx_quick_consumer_index5) 6971 BCE_PRINTF("rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6972 sblk->status_rx_quick_consumer_index4, 6973 sblk->status_rx_quick_consumer_index5); 6974 6975 if (sblk->status_rx_quick_consumer_index6 || 6976 sblk->status_rx_quick_consumer_index7) 6977 BCE_PRINTF("rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6978 sblk->status_rx_quick_consumer_index6, 6979 sblk->status_rx_quick_consumer_index7); 6980 6981 if (sblk->status_rx_quick_consumer_index8 || 6982 sblk->status_rx_quick_consumer_index9) 6983 BCE_PRINTF("rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6984 sblk->status_rx_quick_consumer_index8, 6985 sblk->status_rx_quick_consumer_index9); 6986 6987 if (sblk->status_rx_quick_consumer_index10 || 6988 sblk->status_rx_quick_consumer_index11) 6989 BCE_PRINTF("rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6990 sblk->status_rx_quick_consumer_index10, 6991 sblk->status_rx_quick_consumer_index11); 6992 6993 if (sblk->status_rx_quick_consumer_index12 || 6994 sblk->status_rx_quick_consumer_index13) 6995 BCE_PRINTF("rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6996 sblk->status_rx_quick_consumer_index12, 6997 sblk->status_rx_quick_consumer_index13); 6998 6999 if (sblk->status_rx_quick_consumer_index14 || 7000 sblk->status_rx_quick_consumer_index15) 7001 BCE_PRINTF("rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 7002 sblk->status_rx_quick_consumer_index14, 7003 sblk->status_rx_quick_consumer_index15); 7004 7005 if (sblk->status_completion_producer_index || 7006 sblk->status_cmd_consumer_index) 7007 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 7008 sblk->status_completion_producer_index, 7009 sblk->status_cmd_consumer_index); 7010 7011 BCE_PRINTF( 7012 "----------------------------" 7013 "----------------" 7014 "----------------------------\n"); 7015 } 7016 7017 7018 /****************************************************************************/ 7019 /* Prints out the statistics block from host memory. */ 7020 /* */ 7021 /* Returns: */ 7022 /* Nothing. */ 7023 /****************************************************************************/ 7024 static void 7025 bce_dump_stats_block(struct bce_softc *sc) 7026 { 7027 struct statistics_block *sblk; 7028 7029 sblk = sc->stats_block; 7030 7031 BCE_PRINTF( 7032 "---------------" 7033 " Stats Block (All Stats Not Shown Are 0) " 7034 "---------------\n"); 7035 7036 if (sblk->stat_IfHCInOctets_hi 7037 || sblk->stat_IfHCInOctets_lo) 7038 BCE_PRINTF("0x%08X:%08X : " 7039 "IfHcInOctets\n", 7040 sblk->stat_IfHCInOctets_hi, 7041 sblk->stat_IfHCInOctets_lo); 7042 7043 if (sblk->stat_IfHCInBadOctets_hi 7044 || sblk->stat_IfHCInBadOctets_lo) 7045 BCE_PRINTF("0x%08X:%08X : " 7046 "IfHcInBadOctets\n", 7047 sblk->stat_IfHCInBadOctets_hi, 7048 sblk->stat_IfHCInBadOctets_lo); 7049 7050 if (sblk->stat_IfHCOutOctets_hi 7051 || sblk->stat_IfHCOutOctets_lo) 7052 BCE_PRINTF("0x%08X:%08X : " 7053 "IfHcOutOctets\n", 7054 sblk->stat_IfHCOutOctets_hi, 7055 sblk->stat_IfHCOutOctets_lo); 7056 7057 if (sblk->stat_IfHCOutBadOctets_hi 7058 || sblk->stat_IfHCOutBadOctets_lo) 7059 BCE_PRINTF("0x%08X:%08X : " 7060 "IfHcOutBadOctets\n", 7061 sblk->stat_IfHCOutBadOctets_hi, 7062 sblk->stat_IfHCOutBadOctets_lo); 7063 7064 if (sblk->stat_IfHCInUcastPkts_hi 7065 || sblk->stat_IfHCInUcastPkts_lo) 7066 BCE_PRINTF("0x%08X:%08X : " 7067 "IfHcInUcastPkts\n", 7068 sblk->stat_IfHCInUcastPkts_hi, 7069 sblk->stat_IfHCInUcastPkts_lo); 7070 7071 if (sblk->stat_IfHCInBroadcastPkts_hi 7072 || sblk->stat_IfHCInBroadcastPkts_lo) 7073 BCE_PRINTF("0x%08X:%08X : " 7074 "IfHcInBroadcastPkts\n", 7075 sblk->stat_IfHCInBroadcastPkts_hi, 7076 sblk->stat_IfHCInBroadcastPkts_lo); 7077 7078 if (sblk->stat_IfHCInMulticastPkts_hi 7079 || sblk->stat_IfHCInMulticastPkts_lo) 7080 BCE_PRINTF("0x%08X:%08X : " 7081 "IfHcInMulticastPkts\n", 7082 sblk->stat_IfHCInMulticastPkts_hi, 7083 sblk->stat_IfHCInMulticastPkts_lo); 7084 7085 if (sblk->stat_IfHCOutUcastPkts_hi 7086 || sblk->stat_IfHCOutUcastPkts_lo) 7087 BCE_PRINTF("0x%08X:%08X : " 7088 "IfHcOutUcastPkts\n", 7089 sblk->stat_IfHCOutUcastPkts_hi, 7090 sblk->stat_IfHCOutUcastPkts_lo); 7091 7092 if (sblk->stat_IfHCOutBroadcastPkts_hi 7093 || sblk->stat_IfHCOutBroadcastPkts_lo) 7094 BCE_PRINTF("0x%08X:%08X : " 7095 "IfHcOutBroadcastPkts\n", 7096 sblk->stat_IfHCOutBroadcastPkts_hi, 7097 sblk->stat_IfHCOutBroadcastPkts_lo); 7098 7099 if (sblk->stat_IfHCOutMulticastPkts_hi 7100 || sblk->stat_IfHCOutMulticastPkts_lo) 7101 BCE_PRINTF("0x%08X:%08X : " 7102 "IfHcOutMulticastPkts\n", 7103 sblk->stat_IfHCOutMulticastPkts_hi, 7104 sblk->stat_IfHCOutMulticastPkts_lo); 7105 7106 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 7107 BCE_PRINTF(" 0x%08X : " 7108 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 7109 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 7110 7111 if (sblk->stat_Dot3StatsCarrierSenseErrors) 7112 BCE_PRINTF(" 0x%08X : Dot3StatsCarrierSenseErrors\n", 7113 sblk->stat_Dot3StatsCarrierSenseErrors); 7114 7115 if (sblk->stat_Dot3StatsFCSErrors) 7116 BCE_PRINTF(" 0x%08X : Dot3StatsFCSErrors\n", 7117 sblk->stat_Dot3StatsFCSErrors); 7118 7119 if (sblk->stat_Dot3StatsAlignmentErrors) 7120 BCE_PRINTF(" 0x%08X : Dot3StatsAlignmentErrors\n", 7121 sblk->stat_Dot3StatsAlignmentErrors); 7122 7123 if (sblk->stat_Dot3StatsSingleCollisionFrames) 7124 BCE_PRINTF(" 0x%08X : Dot3StatsSingleCollisionFrames\n", 7125 sblk->stat_Dot3StatsSingleCollisionFrames); 7126 7127 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 7128 BCE_PRINTF(" 0x%08X : Dot3StatsMultipleCollisionFrames\n", 7129 sblk->stat_Dot3StatsMultipleCollisionFrames); 7130 7131 if (sblk->stat_Dot3StatsDeferredTransmissions) 7132 BCE_PRINTF(" 0x%08X : Dot3StatsDeferredTransmissions\n", 7133 sblk->stat_Dot3StatsDeferredTransmissions); 7134 7135 if (sblk->stat_Dot3StatsExcessiveCollisions) 7136 BCE_PRINTF(" 0x%08X : Dot3StatsExcessiveCollisions\n", 7137 sblk->stat_Dot3StatsExcessiveCollisions); 7138 7139 if (sblk->stat_Dot3StatsLateCollisions) 7140 BCE_PRINTF(" 0x%08X : Dot3StatsLateCollisions\n", 7141 sblk->stat_Dot3StatsLateCollisions); 7142 7143 if (sblk->stat_EtherStatsCollisions) 7144 BCE_PRINTF(" 0x%08X : EtherStatsCollisions\n", 7145 sblk->stat_EtherStatsCollisions); 7146 7147 if (sblk->stat_EtherStatsFragments) 7148 BCE_PRINTF(" 0x%08X : EtherStatsFragments\n", 7149 sblk->stat_EtherStatsFragments); 7150 7151 if (sblk->stat_EtherStatsJabbers) 7152 BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n", 7153 sblk->stat_EtherStatsJabbers); 7154 7155 if (sblk->stat_EtherStatsUndersizePkts) 7156 BCE_PRINTF(" 0x%08X : EtherStatsUndersizePkts\n", 7157 sblk->stat_EtherStatsUndersizePkts); 7158 7159 if (sblk->stat_EtherStatsOverrsizePkts) 7160 BCE_PRINTF(" 0x%08X : EtherStatsOverrsizePkts\n", 7161 sblk->stat_EtherStatsOverrsizePkts); 7162 7163 if (sblk->stat_EtherStatsPktsRx64Octets) 7164 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx64Octets\n", 7165 sblk->stat_EtherStatsPktsRx64Octets); 7166 7167 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 7168 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 7169 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 7170 7171 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 7172 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx128Octetsto255Octets\n", 7173 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 7174 7175 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 7176 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx256Octetsto511Octets\n", 7177 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 7178 7179 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 7180 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx512Octetsto1023Octets\n", 7181 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 7182 7183 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 7184 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1024Octetsto1522Octets\n", 7185 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 7186 7187 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 7188 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1523Octetsto9022Octets\n", 7189 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 7190 7191 if (sblk->stat_EtherStatsPktsTx64Octets) 7192 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx64Octets\n", 7193 sblk->stat_EtherStatsPktsTx64Octets); 7194 7195 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 7196 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 7197 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 7198 7199 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 7200 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx128Octetsto255Octets\n", 7201 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 7202 7203 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 7204 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx256Octetsto511Octets\n", 7205 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 7206 7207 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 7208 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx512Octetsto1023Octets\n", 7209 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 7210 7211 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 7212 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1024Octetsto1522Octets\n", 7213 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 7214 7215 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 7216 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1523Octetsto9022Octets\n", 7217 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 7218 7219 if (sblk->stat_XonPauseFramesReceived) 7220 BCE_PRINTF(" 0x%08X : XonPauseFramesReceived\n", 7221 sblk->stat_XonPauseFramesReceived); 7222 7223 if (sblk->stat_XoffPauseFramesReceived) 7224 BCE_PRINTF(" 0x%08X : XoffPauseFramesReceived\n", 7225 sblk->stat_XoffPauseFramesReceived); 7226 7227 if (sblk->stat_OutXonSent) 7228 BCE_PRINTF(" 0x%08X : OutXonSent\n", 7229 sblk->stat_OutXonSent); 7230 7231 if (sblk->stat_OutXoffSent) 7232 BCE_PRINTF(" 0x%08X : OutXoffSent\n", 7233 sblk->stat_OutXoffSent); 7234 7235 if (sblk->stat_FlowControlDone) 7236 BCE_PRINTF(" 0x%08X : FlowControlDone\n", 7237 sblk->stat_FlowControlDone); 7238 7239 if (sblk->stat_MacControlFramesReceived) 7240 BCE_PRINTF(" 0x%08X : MacControlFramesReceived\n", 7241 sblk->stat_MacControlFramesReceived); 7242 7243 if (sblk->stat_XoffStateEntered) 7244 BCE_PRINTF(" 0x%08X : XoffStateEntered\n", 7245 sblk->stat_XoffStateEntered); 7246 7247 if (sblk->stat_IfInFramesL2FilterDiscards) 7248 BCE_PRINTF(" 0x%08X : IfInFramesL2FilterDiscards\n", 7249 sblk->stat_IfInFramesL2FilterDiscards); 7250 7251 if (sblk->stat_IfInRuleCheckerDiscards) 7252 BCE_PRINTF(" 0x%08X : IfInRuleCheckerDiscards\n", 7253 sblk->stat_IfInRuleCheckerDiscards); 7254 7255 if (sblk->stat_IfInFTQDiscards) 7256 BCE_PRINTF(" 0x%08X : IfInFTQDiscards\n", 7257 sblk->stat_IfInFTQDiscards); 7258 7259 if (sblk->stat_IfInMBUFDiscards) 7260 BCE_PRINTF(" 0x%08X : IfInMBUFDiscards\n", 7261 sblk->stat_IfInMBUFDiscards); 7262 7263 if (sblk->stat_IfInRuleCheckerP4Hit) 7264 BCE_PRINTF(" 0x%08X : IfInRuleCheckerP4Hit\n", 7265 sblk->stat_IfInRuleCheckerP4Hit); 7266 7267 if (sblk->stat_CatchupInRuleCheckerDiscards) 7268 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerDiscards\n", 7269 sblk->stat_CatchupInRuleCheckerDiscards); 7270 7271 if (sblk->stat_CatchupInFTQDiscards) 7272 BCE_PRINTF(" 0x%08X : CatchupInFTQDiscards\n", 7273 sblk->stat_CatchupInFTQDiscards); 7274 7275 if (sblk->stat_CatchupInMBUFDiscards) 7276 BCE_PRINTF(" 0x%08X : CatchupInMBUFDiscards\n", 7277 sblk->stat_CatchupInMBUFDiscards); 7278 7279 if (sblk->stat_CatchupInRuleCheckerP4Hit) 7280 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerP4Hit\n", 7281 sblk->stat_CatchupInRuleCheckerP4Hit); 7282 7283 BCE_PRINTF( 7284 "----------------------------" 7285 "----------------" 7286 "----------------------------\n"); 7287 } 7288 7289 7290 /****************************************************************************/ 7291 /* Prints out a summary of the driver state. */ 7292 /* */ 7293 /* Returns: */ 7294 /* Nothing. */ 7295 /****************************************************************************/ 7296 static void 7297 bce_dump_driver_state(struct bce_softc *sc) 7298 { 7299 u32 val_hi, val_lo; 7300 7301 BCE_PRINTF( 7302 "-----------------------------" 7303 " Driver State " 7304 "-----------------------------\n"); 7305 7306 val_hi = BCE_ADDR_HI(sc); 7307 val_lo = BCE_ADDR_LO(sc); 7308 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual address\n", 7309 val_hi, val_lo); 7310 7311 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 7312 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 7313 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual address\n", 7314 val_hi, val_lo); 7315 7316 val_hi = BCE_ADDR_HI(sc->status_block); 7317 val_lo = BCE_ADDR_LO(sc->status_block); 7318 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block virtual address\n", 7319 val_hi, val_lo); 7320 7321 val_hi = BCE_ADDR_HI(sc->stats_block); 7322 val_lo = BCE_ADDR_LO(sc->stats_block); 7323 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block virtual address\n", 7324 val_hi, val_lo); 7325 7326 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 7327 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 7328 BCE_PRINTF( 7329 "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain virtual adddress\n", 7330 val_hi, val_lo); 7331 7332 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 7333 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 7334 BCE_PRINTF( 7335 "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain virtual address\n", 7336 val_hi, val_lo); 7337 7338 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 7339 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 7340 BCE_PRINTF( 7341 "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 7342 val_hi, val_lo); 7343 7344 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 7345 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 7346 BCE_PRINTF( 7347 "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 7348 val_hi, val_lo); 7349 7350 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) h/w intrs\n", 7351 sc->interrupts_generated); 7352 7353 BCE_PRINTF(" 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 7354 sc->rx_interrupts); 7355 7356 BCE_PRINTF(" 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 7357 sc->tx_interrupts); 7358 7359 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) status block index\n", 7360 sc->last_status_idx); 7361 7362 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer index\n", 7363 sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 7364 7365 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer index\n", 7366 sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 7367 7368 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 7369 sc->tx_prod_bseq); 7370 7371 BCE_PRINTF(" 0x%08X - (sc->tx_mbuf_alloc) tx mbufs allocated\n", 7372 sc->tx_mbuf_alloc); 7373 7374 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 7375 sc->used_tx_bd); 7376 7377 BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 7378 sc->tx_hi_watermark, sc->max_tx_bd); 7379 7380 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer index\n", 7381 sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 7382 7383 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer index\n", 7384 sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 7385 7386 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 7387 sc->rx_prod_bseq); 7388 7389 BCE_PRINTF(" 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 7390 sc->rx_mbuf_alloc); 7391 7392 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 7393 sc->free_rx_bd); 7394 7395 BCE_PRINTF("0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 7396 sc->rx_low_watermark, sc->max_rx_bd); 7397 7398 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed) " 7399 "mbuf alloc failures\n", 7400 sc->mbuf_alloc_failed); 7401 7402 BCE_PRINTF(" 0x%08X - (sc->mbuf_sim_alloc_failed) " 7403 "simulated mbuf alloc failures\n", 7404 sc->mbuf_sim_alloc_failed); 7405 7406 BCE_PRINTF( 7407 "----------------------------" 7408 "----------------" 7409 "----------------------------\n"); 7410 } 7411 7412 7413 /****************************************************************************/ 7414 /* Prints out the hardware state through a summary of important register, */ 7415 /* followed by a complete register dump. */ 7416 /* */ 7417 /* Returns: */ 7418 /* Nothing. */ 7419 /****************************************************************************/ 7420 static void 7421 bce_dump_hw_state(struct bce_softc *sc) 7422 { 7423 u32 val1; 7424 7425 BCE_PRINTF( 7426 "----------------------------" 7427 " Hardware State " 7428 "----------------------------\n"); 7429 7430 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver); 7431 7432 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 7433 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 7434 val1, BCE_MISC_ENABLE_STATUS_BITS); 7435 7436 val1 = REG_RD(sc, BCE_DMA_STATUS); 7437 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", val1, BCE_DMA_STATUS); 7438 7439 val1 = REG_RD(sc, BCE_CTX_STATUS); 7440 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", val1, BCE_CTX_STATUS); 7441 7442 val1 = REG_RD(sc, BCE_EMAC_STATUS); 7443 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", val1, BCE_EMAC_STATUS); 7444 7445 val1 = REG_RD(sc, BCE_RPM_STATUS); 7446 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", val1, BCE_RPM_STATUS); 7447 7448 val1 = REG_RD(sc, BCE_TBDR_STATUS); 7449 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", val1, BCE_TBDR_STATUS); 7450 7451 val1 = REG_RD(sc, BCE_TDMA_STATUS); 7452 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", val1, BCE_TDMA_STATUS); 7453 7454 val1 = REG_RD(sc, BCE_HC_STATUS); 7455 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS); 7456 7457 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 7458 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val1, BCE_TXP_CPU_STATE); 7459 7460 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 7461 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val1, BCE_TPAT_CPU_STATE); 7462 7463 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 7464 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val1, BCE_RXP_CPU_STATE); 7465 7466 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE); 7467 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val1, BCE_COM_CPU_STATE); 7468 7469 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 7470 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", val1, BCE_MCP_CPU_STATE); 7471 7472 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE); 7473 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val1, BCE_CP_CPU_STATE); 7474 7475 BCE_PRINTF( 7476 "----------------------------" 7477 "----------------" 7478 "----------------------------\n"); 7479 7480 BCE_PRINTF( 7481 "----------------------------" 7482 " Register Dump " 7483 "----------------------------\n"); 7484 7485 for (int i = 0x400; i < 0x8000; i += 0x10) 7486 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7487 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 7488 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 7489 7490 BCE_PRINTF( 7491 "----------------------------" 7492 "----------------" 7493 "----------------------------\n"); 7494 } 7495 7496 7497 /****************************************************************************/ 7498 /* Prints out the bootcode state. */ 7499 /* */ 7500 /* Returns: */ 7501 /* Nothing. */ 7502 /****************************************************************************/ 7503 static void 7504 bce_dump_bc_state(struct bce_softc *sc) 7505 { 7506 u32 val; 7507 7508 BCE_PRINTF( 7509 "----------------------------" 7510 " Bootcode State " 7511 "----------------------------\n"); 7512 7513 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver); 7514 7515 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_RESET_TYPE); 7516 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 7517 val, BCE_BC_RESET_TYPE); 7518 7519 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE); 7520 BCE_PRINTF("0x%08X - (0x%06X) state\n", 7521 val, BCE_BC_STATE); 7522 7523 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_CONDITION); 7524 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 7525 val, BCE_BC_CONDITION); 7526 7527 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE_DEBUG_CMD); 7528 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 7529 val, BCE_BC_STATE_DEBUG_CMD); 7530 7531 BCE_PRINTF( 7532 "----------------------------" 7533 "----------------" 7534 "----------------------------\n"); 7535 } 7536 7537 7538 /****************************************************************************/ 7539 /* Prints out the TXP state. */ 7540 /* */ 7541 /* Returns: */ 7542 /* Nothing. */ 7543 /****************************************************************************/ 7544 static void 7545 bce_dump_txp_state(struct bce_softc *sc) 7546 { 7547 u32 val1; 7548 7549 BCE_PRINTF( 7550 "----------------------------" 7551 " TXP State " 7552 "----------------------------\n"); 7553 7554 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 7555 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", val1, BCE_TXP_CPU_MODE); 7556 7557 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 7558 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val1, BCE_TXP_CPU_STATE); 7559 7560 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 7561 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", val1, BCE_TXP_CPU_EVENT_MASK); 7562 7563 BCE_PRINTF( 7564 "----------------------------" 7565 " Register Dump " 7566 "----------------------------\n"); 7567 7568 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 7569 /* Skip the big blank spaces */ 7570 if (i < 0x454000 && i > 0x5ffff) 7571 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7572 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 7573 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 7574 } 7575 7576 BCE_PRINTF( 7577 "----------------------------" 7578 "----------------" 7579 "----------------------------\n"); 7580 } 7581 7582 7583 /****************************************************************************/ 7584 /* Prints out the RXP state. */ 7585 /* */ 7586 /* Returns: */ 7587 /* Nothing. */ 7588 /****************************************************************************/ 7589 static void 7590 bce_dump_rxp_state(struct bce_softc *sc) 7591 { 7592 u32 val1; 7593 7594 BCE_PRINTF( 7595 "----------------------------" 7596 " RXP State " 7597 "----------------------------\n"); 7598 7599 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 7600 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", val1, BCE_RXP_CPU_MODE); 7601 7602 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 7603 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val1, BCE_RXP_CPU_STATE); 7604 7605 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 7606 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", val1, BCE_RXP_CPU_EVENT_MASK); 7607 7608 BCE_PRINTF( 7609 "----------------------------" 7610 " Register Dump " 7611 "----------------------------\n"); 7612 7613 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 7614 /* Skip the big blank sapces */ 7615 if (i < 0xc5400 && i > 0xdffff) 7616 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7617 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 7618 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 7619 } 7620 7621 BCE_PRINTF( 7622 "----------------------------" 7623 "----------------" 7624 "----------------------------\n"); 7625 } 7626 7627 7628 /****************************************************************************/ 7629 /* Prints out the TPAT state. */ 7630 /* */ 7631 /* Returns: */ 7632 /* Nothing. */ 7633 /****************************************************************************/ 7634 static void 7635 bce_dump_tpat_state(struct bce_softc *sc) 7636 { 7637 u32 val1; 7638 7639 BCE_PRINTF( 7640 "----------------------------" 7641 " TPAT State " 7642 "----------------------------\n"); 7643 7644 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 7645 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", val1, BCE_TPAT_CPU_MODE); 7646 7647 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 7648 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val1, BCE_TPAT_CPU_STATE); 7649 7650 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 7651 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", val1, BCE_TPAT_CPU_EVENT_MASK); 7652 7653 BCE_PRINTF( 7654 "----------------------------" 7655 " Register Dump " 7656 "----------------------------\n"); 7657 7658 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 7659 /* Skip the big blank spaces */ 7660 if (i < 0x854000 && i > 0x9ffff) 7661 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7662 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 7663 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 7664 } 7665 7666 BCE_PRINTF( 7667 "----------------------------" 7668 "----------------" 7669 "----------------------------\n"); 7670 } 7671 7672 7673 /****************************************************************************/ 7674 /* Prints out the driver state and then enters the debugger. */ 7675 /* */ 7676 /* Returns: */ 7677 /* Nothing. */ 7678 /****************************************************************************/ 7679 static void 7680 bce_breakpoint(struct bce_softc *sc) 7681 { 7682 7683 /* Unreachable code to shut the compiler up about unused functions. */ 7684 if (0) { 7685 bce_freeze_controller(sc); 7686 bce_unfreeze_controller(sc); 7687 bce_dump_txbd(sc, 0, NULL); 7688 bce_dump_rxbd(sc, 0, NULL); 7689 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 7690 bce_dump_rx_mbuf_chain(sc, 0, sc->max_rx_bd); 7691 bce_dump_l2fhdr(sc, 0, NULL); 7692 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 7693 bce_dump_rx_chain(sc, 0, sc->max_rx_bd); 7694 bce_dump_status_block(sc); 7695 bce_dump_stats_block(sc); 7696 bce_dump_driver_state(sc); 7697 bce_dump_hw_state(sc); 7698 bce_dump_bc_state(sc); 7699 bce_dump_txp_state(sc); 7700 bce_dump_rxp_state(sc); 7701 bce_dump_tpat_state(sc); 7702 } 7703 7704 /* bce_freeze_controller(sc); */ 7705 bce_dump_driver_state(sc); 7706 bce_dump_status_block(sc); 7707 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD); 7708 bce_dump_hw_state(sc); 7709 bce_dump_txp_state(sc); 7710 /* bce_unfreeze_controller(sc); */ 7711 7712 /* Call the debugger. */ 7713 breakpoint(); 7714 7715 return; 7716 } 7717 #endif 7718 7719