xref: /freebsd/sys/dev/bce/if_bce.c (revision b3aaa0cc21c63d388230c7ef2a80abd631ff20d5)
1 /*-
2  * Copyright (c) 2006-2008 Broadcom Corporation
3  *	David Christensen <davidch@broadcom.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written consent.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28  * THE POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33 
34 /*
35  * The following controllers are supported by this driver:
36  *   BCM5706C A2, A3
37  *   BCM5706S A2, A3
38  *   BCM5708C B1, B2
39  *   BCM5708S B1, B2
40  *   BCM5709C A1, C0
41  *   BCM5716  C0
42  *
43  * The following controllers are not supported by this driver:
44  *   BCM5706C A0, A1 (pre-production)
45  *   BCM5706S A0, A1 (pre-production)
46  *   BCM5708C A0, B0 (pre-production)
47  *   BCM5708S A0, B0 (pre-production)
48  *   BCM5709C A0  B0, B1, B2 (pre-production)
49  *   BCM5709S A0, A1, B0, B1, B2, C0 (pre-production)
50  */
51 
52 #include "opt_bce.h"
53 
54 #include <dev/bce/if_bcereg.h>
55 #include <dev/bce/if_bcefw.h>
56 
57 /****************************************************************************/
58 /* BCE Debug Options                                                        */
59 /****************************************************************************/
60 #ifdef BCE_DEBUG
61 	u32 bce_debug = BCE_WARN;
62 
63 	/*          0 = Never              */
64 	/*          1 = 1 in 2,147,483,648 */
65 	/*        256 = 1 in     8,388,608 */
66 	/*       2048 = 1 in     1,048,576 */
67 	/*      65536 = 1 in        32,768 */
68 	/*    1048576 = 1 in         2,048 */
69 	/*  268435456 =	1 in             8 */
70 	/*  536870912 = 1 in             4 */
71 	/* 1073741824 = 1 in             2 */
72 
73 	/* Controls how often the l2_fhdr frame error check will fail. */
74 	int bce_debug_l2fhdr_status_check = 0;
75 
76 	/* Controls how often the unexpected attention check will fail. */
77 	int bce_debug_unexpected_attention = 0;
78 
79 	/* Controls how often to simulate an mbuf allocation failure. */
80 	int bce_debug_mbuf_allocation_failure = 0;
81 
82 	/* Controls how often to simulate a DMA mapping failure. */
83 	int bce_debug_dma_map_addr_failure = 0;
84 
85 	/* Controls how often to simulate a bootcode failure. */
86 	int bce_debug_bootcode_running_failure = 0;
87 #endif
88 
89 /****************************************************************************/
90 /* BCE Build Time Options                                                   */
91 /****************************************************************************/
92 #define BCE_USE_SPLIT_HEADER 1
93 /* #define BCE_NVRAM_WRITE_SUPPORT 1 */
94 
95 
96 /****************************************************************************/
97 /* PCI Device ID Table                                                      */
98 /*                                                                          */
99 /* Used by bce_probe() to identify the devices supported by this driver.    */
100 /****************************************************************************/
101 #define BCE_DEVDESC_MAX		64
102 
103 static struct bce_type bce_devs[] = {
104 	/* BCM5706C Controllers and OEM boards. */
105 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
106 		"HP NC370T Multifunction Gigabit Server Adapter" },
107 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
108 		"HP NC370i Multifunction Gigabit Server Adapter" },
109 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
110 		"HP NC380T PCIe DP Multifunc Gig Server Adapter" },
111 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
112 		"HP NC371i Multifunction Gigabit Server Adapter" },
113 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
114 		"Broadcom NetXtreme II BCM5706 1000Base-T" },
115 
116 	/* BCM5706S controllers and OEM boards. */
117 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
118 		"HP NC370F Multifunction Gigabit Server Adapter" },
119 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
120 		"Broadcom NetXtreme II BCM5706 1000Base-SX" },
121 
122 	/* BCM5708C controllers and OEM boards. */
123 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
124 		"HP NC373T PCIe Multifunction Gig Server Adapter" },
125 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
126 		"HP NC373i Multifunction Gigabit Server Adapter" },
127 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
128 		"HP NC374m PCIe Multifunction Adapter" },
129 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
130 		"Broadcom NetXtreme II BCM5708 1000Base-T" },
131 
132 	/* BCM5708S controllers and OEM boards. */
133 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
134 		"HP NC373m Multifunction Gigabit Server Adapter" },
135 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
136 		"HP NC373i Multifunction Gigabit Server Adapter" },
137 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
138 		"HP NC373F PCIe Multifunc Giga Server Adapter" },
139 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
140 		"Broadcom NetXtreme II BCM5708 1000Base-SX" },
141 
142 	/* BCM5709C controllers and OEM boards. */
143 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
144 		"HP NC382i DP Multifunction Gigabit Server Adapter" },
145 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
146 		"HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
147 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
148 		"Broadcom NetXtreme II BCM5709 1000Base-T" },
149 
150 	/* BCM5709S controllers and OEM boards. */
151 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
152 		"HP NC382m DP 1GbE Multifunction BL-c Adapter" },
153 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
154 		"HP NC382i DP Multifunction Gigabit Server Adapter" },
155 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
156 		"Broadcom NetXtreme II BCM5709 1000Base-SX" },
157 
158 	/* BCM5716 controllers and OEM boards. */
159 	{ BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
160 		"Broadcom NetXtreme II BCM5716 1000Base-T" },
161 
162 	{ 0, 0, 0, 0, NULL }
163 };
164 
165 
166 /****************************************************************************/
167 /* Supported Flash NVRAM device data.                                       */
168 /****************************************************************************/
169 static struct flash_spec flash_table[] =
170 {
171 #define BUFFERED_FLAGS		(BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
172 #define NONBUFFERED_FLAGS	(BCE_NV_WREN)
173 
174 	/* Slow EEPROM */
175 	{0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
176 	 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
177 	 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
178 	 "EEPROM - slow"},
179 	/* Expansion entry 0001 */
180 	{0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
181 	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
182 	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
183 	 "Entry 0001"},
184 	/* Saifun SA25F010 (non-buffered flash) */
185 	/* strap, cfg1, & write1 need updates */
186 	{0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
187 	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
188 	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
189 	 "Non-buffered flash (128kB)"},
190 	/* Saifun SA25F020 (non-buffered flash) */
191 	/* strap, cfg1, & write1 need updates */
192 	{0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
193 	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
195 	 "Non-buffered flash (256kB)"},
196 	/* Expansion entry 0100 */
197 	{0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
198 	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
199 	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 	 "Entry 0100"},
201 	/* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
202 	{0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
203 	 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
204 	 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
205 	 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
206 	/* Entry 0110: ST M45PE20 (non-buffered flash)*/
207 	{0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
208 	 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
209 	 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
210 	 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
211 	/* Saifun SA25F005 (non-buffered flash) */
212 	/* strap, cfg1, & write1 need updates */
213 	{0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
214 	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
215 	 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
216 	 "Non-buffered flash (64kB)"},
217 	/* Fast EEPROM */
218 	{0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
219 	 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
220 	 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
221 	 "EEPROM - fast"},
222 	/* Expansion entry 1001 */
223 	{0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
224 	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225 	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
226 	 "Entry 1001"},
227 	/* Expansion entry 1010 */
228 	{0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
229 	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
230 	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
231 	 "Entry 1010"},
232 	/* ATMEL AT45DB011B (buffered flash) */
233 	{0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
234 	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
235 	 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
236 	 "Buffered flash (128kB)"},
237 	/* Expansion entry 1100 */
238 	{0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
239 	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
240 	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
241 	 "Entry 1100"},
242 	/* Expansion entry 1101 */
243 	{0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
244 	 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
245 	 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
246 	 "Entry 1101"},
247 	/* Ateml Expansion entry 1110 */
248 	{0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
249 	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
250 	 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
251 	 "Entry 1110 (Atmel)"},
252 	/* ATMEL AT45DB021B (buffered flash) */
253 	{0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
254 	 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
255 	 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
256 	 "Buffered flash (256kB)"},
257 };
258 
259 /*
260  * The BCM5709 controllers transparently handle the
261  * differences between Atmel 264 byte pages and all
262  * flash devices which use 256 byte pages, so no
263  * logical-to-physical mapping is required in the
264  * driver.
265  */
266 static struct flash_spec flash_5709 = {
267 	.flags		= BCE_NV_BUFFERED,
268 	.page_bits	= BCM5709_FLASH_PAGE_BITS,
269 	.page_size	= BCM5709_FLASH_PAGE_SIZE,
270 	.addr_mask	= BCM5709_FLASH_BYTE_ADDR_MASK,
271 	.total_size	= BUFFERED_FLASH_TOTAL_SIZE * 2,
272 	.name		= "5709/5716 buffered flash (256kB)",
273 };
274 
275 
276 /****************************************************************************/
277 /* FreeBSD device entry points.                                             */
278 /****************************************************************************/
279 static int  bce_probe				(device_t);
280 static int  bce_attach				(device_t);
281 static int  bce_detach				(device_t);
282 static int  bce_shutdown			(device_t);
283 
284 
285 /****************************************************************************/
286 /* BCE Debug Data Structure Dump Routines                                   */
287 /****************************************************************************/
288 #ifdef BCE_DEBUG
289 static u32	bce_reg_rd				(struct bce_softc *, u32);
290 static void	bce_reg_wr				(struct bce_softc *, u32, u32);
291 static void	bce_reg_wr16			(struct bce_softc *, u32, u16);
292 static u32  bce_ctx_rd				(struct bce_softc *, u32, u32);
293 static void bce_dump_enet           (struct bce_softc *, struct mbuf *);
294 static void bce_dump_mbuf 			(struct bce_softc *, struct mbuf *);
295 static void bce_dump_tx_mbuf_chain	(struct bce_softc *, u16, int);
296 static void bce_dump_rx_mbuf_chain	(struct bce_softc *, u16, int);
297 #ifdef BCE_USE_SPLIT_HEADER
298 static void bce_dump_pg_mbuf_chain	(struct bce_softc *, u16, int);
299 #endif
300 static void bce_dump_txbd			(struct bce_softc *, int, struct tx_bd *);
301 static void bce_dump_rxbd			(struct bce_softc *, int, struct rx_bd *);
302 #ifdef BCE_USE_SPLIT_HEADER
303 static void bce_dump_pgbd			(struct bce_softc *, int, struct rx_bd *);
304 #endif
305 static void bce_dump_l2fhdr			(struct bce_softc *, int, struct l2_fhdr *);
306 static void bce_dump_ctx			(struct bce_softc *, u16);
307 static void bce_dump_ftqs			(struct bce_softc *);
308 static void bce_dump_tx_chain		(struct bce_softc *, u16, int);
309 static void bce_dump_rx_chain		(struct bce_softc *, u16, int);
310 #ifdef BCE_USE_SPLIT_HEADER
311 static void bce_dump_pg_chain		(struct bce_softc *, u16, int);
312 #endif
313 static void bce_dump_status_block	(struct bce_softc *);
314 static void bce_dump_stats_block	(struct bce_softc *);
315 static void bce_dump_driver_state	(struct bce_softc *);
316 static void bce_dump_hw_state		(struct bce_softc *);
317 static void bce_dump_mq_regs        (struct bce_softc *);
318 static void bce_dump_bc_state		(struct bce_softc *);
319 static void bce_dump_txp_state		(struct bce_softc *, int);
320 static void bce_dump_rxp_state		(struct bce_softc *, int);
321 static void bce_dump_tpat_state		(struct bce_softc *, int);
322 static void bce_dump_cp_state		(struct bce_softc *, int);
323 static void bce_dump_com_state		(struct bce_softc *, int);
324 static void bce_breakpoint			(struct bce_softc *);
325 #endif
326 
327 
328 /****************************************************************************/
329 /* BCE Register/Memory Access Routines                                      */
330 /****************************************************************************/
331 static u32  bce_reg_rd_ind			(struct bce_softc *, u32);
332 static void bce_reg_wr_ind			(struct bce_softc *, u32, u32);
333 static void bce_ctx_wr				(struct bce_softc *, u32, u32, u32);
334 static int  bce_miibus_read_reg		(device_t, int, int);
335 static int  bce_miibus_write_reg	(device_t, int, int, int);
336 static void bce_miibus_statchg		(device_t);
337 
338 
339 /****************************************************************************/
340 /* BCE NVRAM Access Routines                                                */
341 /****************************************************************************/
342 static int  bce_acquire_nvram_lock	(struct bce_softc *);
343 static int  bce_release_nvram_lock	(struct bce_softc *);
344 static void bce_enable_nvram_access	(struct bce_softc *);
345 static void	bce_disable_nvram_access(struct bce_softc *);
346 static int  bce_nvram_read_dword	(struct bce_softc *, u32, u8 *, u32);
347 static int  bce_init_nvram			(struct bce_softc *);
348 static int  bce_nvram_read			(struct bce_softc *, u32, u8 *, int);
349 static int  bce_nvram_test			(struct bce_softc *);
350 #ifdef BCE_NVRAM_WRITE_SUPPORT
351 static int  bce_enable_nvram_write	(struct bce_softc *);
352 static void bce_disable_nvram_write	(struct bce_softc *);
353 static int  bce_nvram_erase_page	(struct bce_softc *, u32);
354 static int  bce_nvram_write_dword	(struct bce_softc *, u32, u8 *, u32);
355 static int  bce_nvram_write			(struct bce_softc *, u32, u8 *, int);
356 #endif
357 
358 /****************************************************************************/
359 /*                                                                          */
360 /****************************************************************************/
361 static void bce_get_media			(struct bce_softc *);
362 static void bce_dma_map_addr		(void *, bus_dma_segment_t *, int, int);
363 static int  bce_dma_alloc			(device_t);
364 static void bce_dma_free			(struct bce_softc *);
365 static void bce_release_resources	(struct bce_softc *);
366 
367 /****************************************************************************/
368 /* BCE Firmware Synchronization and Load                                    */
369 /****************************************************************************/
370 static int  bce_fw_sync				(struct bce_softc *, u32);
371 static void bce_load_rv2p_fw		(struct bce_softc *, u32 *, u32, u32);
372 static void bce_load_cpu_fw			(struct bce_softc *, struct cpu_reg *, struct fw_info *);
373 static void bce_init_rxp_cpu		(struct bce_softc *);
374 static void bce_init_txp_cpu 		(struct bce_softc *);
375 static void bce_init_tpat_cpu		(struct bce_softc *);
376 static void bce_init_cp_cpu		  	(struct bce_softc *);
377 static void bce_init_com_cpu	  	(struct bce_softc *);
378 static void bce_init_cpus			(struct bce_softc *);
379 
380 static void	bce_print_adapter_info	(struct bce_softc *);
381 static void bce_probe_pci_caps		(device_t, struct bce_softc *);
382 static void bce_stop				(struct bce_softc *);
383 static int  bce_reset				(struct bce_softc *, u32);
384 static int  bce_chipinit 			(struct bce_softc *);
385 static int  bce_blockinit 			(struct bce_softc *);
386 
387 static int  bce_init_tx_chain		(struct bce_softc *);
388 static void bce_free_tx_chain		(struct bce_softc *);
389 
390 static int  bce_get_rx_buf			(struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *);
391 static int  bce_init_rx_chain		(struct bce_softc *);
392 static void bce_fill_rx_chain		(struct bce_softc *);
393 static void bce_free_rx_chain		(struct bce_softc *);
394 
395 #ifdef BCE_USE_SPLIT_HEADER
396 static int  bce_get_pg_buf			(struct bce_softc *, struct mbuf *, u16 *, u16 *);
397 static int  bce_init_pg_chain		(struct bce_softc *);
398 static void bce_fill_pg_chain		(struct bce_softc *);
399 static void bce_free_pg_chain		(struct bce_softc *);
400 #endif
401 
402 static int  bce_tx_encap			(struct bce_softc *, struct mbuf **);
403 static void bce_start_locked		(struct ifnet *);
404 static void bce_start				(struct ifnet *);
405 static int  bce_ioctl				(struct ifnet *, u_long, caddr_t);
406 static void bce_watchdog			(struct bce_softc *);
407 static int  bce_ifmedia_upd			(struct ifnet *);
408 static void bce_ifmedia_upd_locked	(struct ifnet *);
409 static void bce_ifmedia_sts			(struct ifnet *, struct ifmediareq *);
410 static void bce_init_locked			(struct bce_softc *);
411 static void bce_init				(void *);
412 static void bce_mgmt_init_locked	(struct bce_softc *sc);
413 
414 static void bce_init_ctx			(struct bce_softc *);
415 static void bce_get_mac_addr		(struct bce_softc *);
416 static void bce_set_mac_addr		(struct bce_softc *);
417 static void bce_phy_intr			(struct bce_softc *);
418 static inline u16 bce_get_hw_rx_cons(struct bce_softc *);
419 static void bce_rx_intr				(struct bce_softc *);
420 static void bce_tx_intr				(struct bce_softc *);
421 static void bce_disable_intr		(struct bce_softc *);
422 static void bce_enable_intr			(struct bce_softc *, int);
423 
424 static void bce_intr				(void *);
425 static void bce_set_rx_mode			(struct bce_softc *);
426 static void bce_stats_update		(struct bce_softc *);
427 static void bce_tick				(void *);
428 static void bce_pulse				(void *);
429 static void bce_add_sysctls			(struct bce_softc *);
430 
431 
432 /****************************************************************************/
433 /* FreeBSD device dispatch table.                                           */
434 /****************************************************************************/
435 static device_method_t bce_methods[] = {
436 	/* Device interface (device_if.h) */
437 	DEVMETHOD(device_probe,		bce_probe),
438 	DEVMETHOD(device_attach,	bce_attach),
439 	DEVMETHOD(device_detach,	bce_detach),
440 	DEVMETHOD(device_shutdown,	bce_shutdown),
441 /* Supported by device interface but not used here. */
442 /*	DEVMETHOD(device_identify,	bce_identify),      */
443 /*	DEVMETHOD(device_suspend,	bce_suspend),       */
444 /*	DEVMETHOD(device_resume,	bce_resume),        */
445 /*	DEVMETHOD(device_quiesce,	bce_quiesce),       */
446 
447 	/* Bus interface (bus_if.h) */
448 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
449 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
450 
451 	/* MII interface (miibus_if.h) */
452 	DEVMETHOD(miibus_readreg,	bce_miibus_read_reg),
453 	DEVMETHOD(miibus_writereg,	bce_miibus_write_reg),
454 	DEVMETHOD(miibus_statchg,	bce_miibus_statchg),
455 /* Supported by MII interface but not used here.       */
456 /*	DEVMETHOD(miibus_linkchg,	bce_miibus_linkchg),   */
457 /*	DEVMETHOD(miibus_mediainit,	bce_miibus_mediainit), */
458 
459 	{ 0, 0 }
460 };
461 
462 static driver_t bce_driver = {
463 	"bce",
464 	bce_methods,
465 	sizeof(struct bce_softc)
466 };
467 
468 static devclass_t bce_devclass;
469 
470 MODULE_DEPEND(bce, pci, 1, 1, 1);
471 MODULE_DEPEND(bce, ether, 1, 1, 1);
472 MODULE_DEPEND(bce, miibus, 1, 1, 1);
473 
474 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
475 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
476 
477 
478 /****************************************************************************/
479 /* Tunable device values                                                    */
480 /****************************************************************************/
481 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
482 
483 /* Allowable values are TRUE or FALSE */
484 static int bce_tso_enable = TRUE;
485 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
486 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
487 "TSO Enable/Disable");
488 
489 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
490 /* ToDo: Add MSI-X support. */
491 static int bce_msi_enable = 1;
492 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
493 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
494 "MSI-X|MSI|INTx selector");
495 
496 /* ToDo: Add tunable to enable/disable strict MTU handling. */
497 /* Currently allows "loose" RX MTU checking (i.e. sets the  */
498 /* H/W RX MTU to the size of the largest receive buffer, or */
499 /* 2048 bytes).                                             */
500 
501 
502 /****************************************************************************/
503 /* Device probe function.                                                   */
504 /*                                                                          */
505 /* Compares the device to the driver's list of supported devices and        */
506 /* reports back to the OS whether this is the right driver for the device.  */
507 /*                                                                          */
508 /* Returns:                                                                 */
509 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
510 /****************************************************************************/
511 static int
512 bce_probe(device_t dev)
513 {
514 	struct bce_type *t;
515 	struct bce_softc *sc;
516 	char *descbuf;
517 	u16 vid = 0, did = 0, svid = 0, sdid = 0;
518 
519 	t = bce_devs;
520 
521 	sc = device_get_softc(dev);
522 	bzero(sc, sizeof(struct bce_softc));
523 	sc->bce_unit = device_get_unit(dev);
524 	sc->bce_dev = dev;
525 
526 	/* Get the data for the device to be probed. */
527 	vid  = pci_get_vendor(dev);
528 	did  = pci_get_device(dev);
529 	svid = pci_get_subvendor(dev);
530 	sdid = pci_get_subdevice(dev);
531 
532 	DBPRINT(sc, BCE_EXTREME_LOAD,
533 		"%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
534 		"SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
535 
536 	/* Look through the list of known devices for a match. */
537 	while(t->bce_name != NULL) {
538 
539 		if ((vid == t->bce_vid) && (did == t->bce_did) &&
540 			((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
541 			((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
542 
543 			descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
544 
545 			if (descbuf == NULL)
546 				return(ENOMEM);
547 
548 			/* Print out the device identity. */
549 			snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
550 				t->bce_name,
551 			    (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
552 			    (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
553 
554 			device_set_desc_copy(dev, descbuf);
555 			free(descbuf, M_TEMP);
556 			return(BUS_PROBE_DEFAULT);
557 		}
558 		t++;
559 	}
560 
561 	return(ENXIO);
562 }
563 
564 
565 /****************************************************************************/
566 /* PCI Capabilities Probe Function.                                         */
567 /*                                                                          */
568 /* Walks the PCI capabiites list for the device to find what features are   */
569 /* supported.                                                               */
570 /*                                                                          */
571 /* Returns:                                                                 */
572 /*   None.                                                                  */
573 /****************************************************************************/
574 static void
575 bce_print_adapter_info(struct bce_softc *sc)
576 {
577 	DBENTER(BCE_VERBOSE_LOAD);
578 
579 	BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
580 	printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
581 		((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
582 
583 	/* Bus info. */
584 	if (sc->bce_flags & BCE_PCIE_FLAG) {
585 		printf("Bus (PCIe x%d, ", sc->link_width);
586 		switch (sc->link_speed) {
587 			case 1: printf("2.5Gbps); "); break;
588 			case 2:	printf("5Gbps); "); break;
589 			default: printf("Unknown link speed); ");
590 		}
591 	} else {
592 		printf("Bus (PCI%s, %s, %dMHz); ",
593 			((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
594 			((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
595 			sc->bus_speed_mhz);
596 	}
597 
598 	/* Firmware version and device features. */
599 	printf("F/W (0x%08X); Flags( ", sc->bce_fw_ver);
600 #ifdef BCE_USE_SPLIT_HEADER
601 	printf("SPLT ");
602 #endif
603 	if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
604 		printf("MFW ");
605 	if (sc->bce_flags & BCE_USING_MSI_FLAG)
606 		printf("MSI ");
607 	if (sc->bce_flags & BCE_USING_MSIX_FLAG)
608 		printf("MSI-X ");
609 	if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
610 		printf("2.5G ");
611 	printf(")\n");
612 
613 	DBEXIT(BCE_VERBOSE_LOAD);
614 }
615 
616 
617 /****************************************************************************/
618 /* PCI Capabilities Probe Function.                                         */
619 /*                                                                          */
620 /* Walks the PCI capabiites list for the device to find what features are   */
621 /* supported.                                                               */
622 /*                                                                          */
623 /* Returns:                                                                 */
624 /*   None.                                                                  */
625 /****************************************************************************/
626 static void
627 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
628 {
629 	u32 reg;
630 
631 	DBENTER(BCE_VERBOSE_LOAD);
632 
633 	/* Check if PCI-X capability is enabled. */
634 	if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0) {
635 		if (reg != 0)
636 			sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
637 	}
638 
639 	/* Check if PCIe capability is enabled. */
640 	if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
641 		if (reg != 0) {
642 			u16 link_status = pci_read_config(dev, reg + 0x12, 2);
643 			DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = 0x%08X\n",
644 				link_status);
645 			sc->link_speed = link_status & 0xf;
646 			sc->link_width = (link_status >> 4) & 0x3f;
647 			sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
648 			sc->bce_flags |= BCE_PCIE_FLAG;
649 		}
650 	}
651 
652 	/* Check if MSI capability is enabled. */
653 	if (pci_find_extcap(dev, PCIY_MSI, &reg) == 0) {
654 		if (reg != 0)
655 			sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
656 	}
657 
658 	/* Check if MSI-X capability is enabled. */
659 	if (pci_find_extcap(dev, PCIY_MSIX, &reg) == 0) {
660 		if (reg != 0)
661 			sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
662 	}
663 
664 	DBEXIT(BCE_VERBOSE_LOAD);
665 }
666 
667 
668 /****************************************************************************/
669 /* Device attach function.                                                  */
670 /*                                                                          */
671 /* Allocates device resources, performs secondary chip identification,      */
672 /* resets and initializes the hardware, and initializes driver instance     */
673 /* variables.                                                               */
674 /*                                                                          */
675 /* Returns:                                                                 */
676 /*   0 on success, positive value on failure.                               */
677 /****************************************************************************/
678 static int
679 bce_attach(device_t dev)
680 {
681 	struct bce_softc *sc;
682 	struct ifnet *ifp;
683 	u32 val;
684 	int error, rid, rc = 0;
685 
686 	sc = device_get_softc(dev);
687 	sc->bce_dev = dev;
688 
689 	DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
690 
691 	sc->bce_unit = device_get_unit(dev);
692 
693 	/* Set initial device and PHY flags */
694 	sc->bce_flags = 0;
695 	sc->bce_phy_flags = 0;
696 
697 	pci_enable_busmaster(dev);
698 
699 	/* Allocate PCI memory resources. */
700 	rid = PCIR_BAR(0);
701 	sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
702 		&rid, RF_ACTIVE);
703 
704 	if (sc->bce_res_mem == NULL) {
705 		BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
706 			__FILE__, __LINE__);
707 		rc = ENXIO;
708 		goto bce_attach_fail;
709 	}
710 
711 	/* Get various resource handles. */
712 	sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
713 	sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
714 	sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
715 
716 	bce_probe_pci_caps(dev, sc);
717 
718 	rid = 1;
719 #if 0
720 	/* Try allocating MSI-X interrupts. */
721 	if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
722 		(bce_msi_enable >= 2) &&
723 		((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
724 		&rid, RF_ACTIVE)) != NULL)) {
725 
726 		msi_needed = sc->bce_msi_count = 1;
727 
728 		if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) ||
729 			(sc->bce_msi_count != msi_needed)) {
730 			BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
731 				"Received = %d, error = %d\n", __FILE__, __LINE__,
732 				msi_needed, sc->bce_msi_count, error);
733 			sc->bce_msi_count = 0;
734 			pci_release_msi(dev);
735 			bus_release_resource(dev, SYS_RES_MEMORY, rid,
736 				sc->bce_res_irq);
737 			sc->bce_res_irq = NULL;
738 		} else {
739 			DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
740 				__FUNCTION__);
741 			sc->bce_flags |= BCE_USING_MSIX_FLAG;
742 			sc->bce_intr = bce_intr;
743 		}
744 	}
745 #endif
746 
747 	/* Try allocating a MSI interrupt. */
748 	if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
749 		(bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) {
750 		sc->bce_msi_count = 1;
751 		if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) {
752 			BCE_PRINTF("%s(%d): MSI allocation failed! error = %d\n",
753 				__FILE__, __LINE__, error);
754 			sc->bce_msi_count = 0;
755 			pci_release_msi(dev);
756 		} else {
757 			DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI interrupt.\n",
758 				__FUNCTION__);
759 			sc->bce_flags |= BCE_USING_MSI_FLAG;
760 			if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
761 				(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
762 				sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
763 			sc->bce_irq_rid = 1;
764 			sc->bce_intr = bce_intr;
765 		}
766 	}
767 
768 	/* Try allocating a legacy interrupt. */
769 	if (sc->bce_msi_count == 0) {
770 		DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
771 			__FUNCTION__);
772 		rid = 0;
773 		sc->bce_intr = bce_intr;
774 	}
775 
776 	sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
777 		&rid, RF_SHAREABLE | RF_ACTIVE);
778 
779 	sc->bce_irq_rid = rid;
780 
781 	/* Report any IRQ allocation errors. */
782 	if (sc->bce_res_irq == NULL) {
783 		BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
784 			__FILE__, __LINE__);
785 		rc = ENXIO;
786 		goto bce_attach_fail;
787 	}
788 
789 	/* Initialize mutex for the current device instance. */
790 	BCE_LOCK_INIT(sc, device_get_nameunit(dev));
791 
792 	/*
793 	 * Configure byte swap and enable indirect register access.
794 	 * Rely on CPU to do target byte swapping on big endian systems.
795 	 * Access to registers outside of PCI configurtion space are not
796 	 * valid until this is done.
797 	 */
798 	pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
799 			       BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
800 			       BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
801 
802 	/* Save ASIC revsion info. */
803 	sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
804 
805 	/* Weed out any non-production controller revisions. */
806 	switch(BCE_CHIP_ID(sc)) {
807 		case BCE_CHIP_ID_5706_A0:
808 		case BCE_CHIP_ID_5706_A1:
809 		case BCE_CHIP_ID_5708_A0:
810 		case BCE_CHIP_ID_5708_B0:
811 		case BCE_CHIP_ID_5709_A0:
812 		case BCE_CHIP_ID_5709_B0:
813 		case BCE_CHIP_ID_5709_B1:
814 		case BCE_CHIP_ID_5709_B2:
815 			BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n",
816 				__FILE__, __LINE__,
817 				(((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
818 			    (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
819 			rc = ENODEV;
820 			goto bce_attach_fail;
821 	}
822 
823 	/*
824 	 * The embedded PCIe to PCI-X bridge (EPB)
825 	 * in the 5708 cannot address memory above
826 	 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
827 	 */
828 	if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
829 		sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
830 	else
831 		sc->max_bus_addr = BUS_SPACE_MAXADDR;
832 
833 	/*
834 	 * Find the base address for shared memory access.
835 	 * Newer versions of bootcode use a signature and offset
836 	 * while older versions use a fixed address.
837 	 */
838 	val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
839 	if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
840 		/* Multi-port devices use different offsets in shared memory. */
841 		sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
842 			(pci_get_function(sc->bce_dev) << 2));
843 	else
844 		sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
845 
846 	DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
847 		__FUNCTION__, sc->bce_shmem_base);
848 
849 	/* Fetch the bootcode revision. */
850 	sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base +
851 		BCE_DEV_INFO_BC_REV);
852 
853 	/* Check if any management firmware is running. */
854 	val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
855 	if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED))
856 		sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
857 
858 	/* Get PCI bus information (speed and type). */
859 	val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
860 	if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
861 		u32 clkreg;
862 
863 		sc->bce_flags |= BCE_PCIX_FLAG;
864 
865 		clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
866 
867 		clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
868 		switch (clkreg) {
869 		case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
870 			sc->bus_speed_mhz = 133;
871 			break;
872 
873 		case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
874 			sc->bus_speed_mhz = 100;
875 			break;
876 
877 		case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
878 		case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
879 			sc->bus_speed_mhz = 66;
880 			break;
881 
882 		case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
883 		case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
884 			sc->bus_speed_mhz = 50;
885 			break;
886 
887 		case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
888 		case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
889 		case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
890 			sc->bus_speed_mhz = 33;
891 			break;
892 		}
893 	} else {
894 		if (val & BCE_PCICFG_MISC_STATUS_M66EN)
895 			sc->bus_speed_mhz = 66;
896 		else
897 			sc->bus_speed_mhz = 33;
898 	}
899 
900 	if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
901 		sc->bce_flags |= BCE_PCI_32BIT_FLAG;
902 
903 	/* Reset the controller and announce to bootcode that driver is present. */
904 	if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
905 		BCE_PRINTF("%s(%d): Controller reset failed!\n",
906 			__FILE__, __LINE__);
907 		rc = ENXIO;
908 		goto bce_attach_fail;
909 	}
910 
911 	/* Initialize the controller. */
912 	if (bce_chipinit(sc)) {
913 		BCE_PRINTF("%s(%d): Controller initialization failed!\n",
914 			__FILE__, __LINE__);
915 		rc = ENXIO;
916 		goto bce_attach_fail;
917 	}
918 
919 	/* Perform NVRAM test. */
920 	if (bce_nvram_test(sc)) {
921 		BCE_PRINTF("%s(%d): NVRAM test failed!\n",
922 			__FILE__, __LINE__);
923 		rc = ENXIO;
924 		goto bce_attach_fail;
925 	}
926 
927 	/* Fetch the permanent Ethernet MAC address. */
928 	bce_get_mac_addr(sc);
929 
930 	/*
931 	 * Trip points control how many BDs
932 	 * should be ready before generating an
933 	 * interrupt while ticks control how long
934 	 * a BD can sit in the chain before
935 	 * generating an interrupt.  Set the default
936 	 * values for the RX and TX chains.
937 	 */
938 
939 #ifdef BCE_DEBUG
940 	/* Force more frequent interrupts. */
941 	sc->bce_tx_quick_cons_trip_int = 1;
942 	sc->bce_tx_quick_cons_trip     = 1;
943 	sc->bce_tx_ticks_int           = 0;
944 	sc->bce_tx_ticks               = 0;
945 
946 	sc->bce_rx_quick_cons_trip_int = 1;
947 	sc->bce_rx_quick_cons_trip     = 1;
948 	sc->bce_rx_ticks_int           = 0;
949 	sc->bce_rx_ticks               = 0;
950 #else
951 	/* Improve throughput at the expense of increased latency. */
952 	sc->bce_tx_quick_cons_trip_int = 20;
953 	sc->bce_tx_quick_cons_trip     = 20;
954 	sc->bce_tx_ticks_int           = 80;
955 	sc->bce_tx_ticks               = 80;
956 
957 	sc->bce_rx_quick_cons_trip_int = 6;
958 	sc->bce_rx_quick_cons_trip     = 6;
959 	sc->bce_rx_ticks_int           = 18;
960 	sc->bce_rx_ticks               = 18;
961 #endif
962 
963 	/* Update statistics once every second. */
964 	sc->bce_stats_ticks = 1000000 & 0xffff00;
965 
966 	/* Find the media type for the adapter. */
967 	bce_get_media(sc);
968 
969 	/* Store data needed by PHY driver for backplane applications */
970 	sc->bce_shared_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base +
971 		BCE_SHARED_HW_CFG_CONFIG);
972 	sc->bce_port_hw_cfg   = REG_RD_IND(sc, sc->bce_shmem_base +
973 		BCE_PORT_HW_CFG_CONFIG);
974 
975 	/* Allocate DMA memory resources. */
976 	if (bce_dma_alloc(dev)) {
977 		BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
978 		    __FILE__, __LINE__);
979 		rc = ENXIO;
980 		goto bce_attach_fail;
981 	}
982 
983 	/* Allocate an ifnet structure. */
984 	ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
985 	if (ifp == NULL) {
986 		BCE_PRINTF("%s(%d): Interface allocation failed!\n",
987 			__FILE__, __LINE__);
988 		rc = ENXIO;
989 		goto bce_attach_fail;
990 	}
991 
992 	/* Initialize the ifnet interface. */
993 	ifp->if_softc        = sc;
994 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
995 	ifp->if_flags        = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
996 	ifp->if_ioctl        = bce_ioctl;
997 	ifp->if_start        = bce_start;
998 	ifp->if_init         = bce_init;
999 	ifp->if_mtu          = ETHERMTU;
1000 
1001 	if (bce_tso_enable) {
1002 		ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1003 		ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4;
1004 	} else {
1005 		ifp->if_hwassist = BCE_IF_HWASSIST;
1006 		ifp->if_capabilities = BCE_IF_CAPABILITIES;
1007 	}
1008 
1009 	ifp->if_capenable    = ifp->if_capabilities;
1010 
1011 	/*
1012 	 * Assume standard mbuf sizes for buffer allocation.
1013 	 * This may change later if the MTU size is set to
1014 	 * something other than 1500.
1015 	 */
1016 #ifdef BCE_USE_SPLIT_HEADER
1017 	sc->rx_bd_mbuf_alloc_size = MHLEN;
1018 	/* Make sure offset is 16 byte aligned for hardware. */
1019 	sc->rx_bd_mbuf_align_pad  = roundup2((MSIZE - MHLEN), 16) -
1020 		(MSIZE - MHLEN);
1021 	sc->rx_bd_mbuf_data_len   = sc->rx_bd_mbuf_alloc_size -
1022 		sc->rx_bd_mbuf_align_pad;
1023 	sc->pg_bd_mbuf_alloc_size = MCLBYTES;
1024 #else
1025 	sc->rx_bd_mbuf_alloc_size = MCLBYTES;
1026 	sc->rx_bd_mbuf_align_pad  = roundup2(MCLBYTES, 16) - MCLBYTES;
1027 	sc->rx_bd_mbuf_data_len   = sc->rx_bd_mbuf_alloc_size -
1028 		sc->rx_bd_mbuf_align_pad;
1029 #endif
1030 
1031 	ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD;
1032 	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1033 	IFQ_SET_READY(&ifp->if_snd);
1034 
1035 	if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1036 		ifp->if_baudrate = IF_Mbps(2500ULL);
1037 	else
1038 		ifp->if_baudrate = IF_Mbps(1000);
1039 
1040 	/* Check for an MII child bus by probing the PHY. */
1041 	if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd,
1042 		bce_ifmedia_sts)) {
1043 		BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n",
1044 			__FILE__, __LINE__);
1045 		rc = ENXIO;
1046 		goto bce_attach_fail;
1047 	}
1048 
1049 	/* Attach to the Ethernet interface list. */
1050 	ether_ifattach(ifp, sc->eaddr);
1051 
1052 #if __FreeBSD_version < 500000
1053 	callout_init(&sc->bce_tick_callout);
1054 	callout_init(&sc->bce_pulse_callout);
1055 #else
1056 	callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1057 	callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1058 #endif
1059 
1060 	/* Hookup IRQ last. */
1061 	rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1062 		NULL, bce_intr, sc, &sc->bce_intrhand);
1063 
1064 	if (rc) {
1065 		BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1066 			__FILE__, __LINE__);
1067 		bce_detach(dev);
1068 		goto bce_attach_exit;
1069 	}
1070 
1071 	/*
1072 	 * At this point we've acquired all the resources
1073 	 * we need to run so there's no turning back, we're
1074 	 * cleared for launch.
1075 	 */
1076 
1077 	/* Print some important debugging info. */
1078 	DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1079 
1080 	/* Add the supported sysctls to the kernel. */
1081 	bce_add_sysctls(sc);
1082 
1083 	BCE_LOCK(sc);
1084 
1085 	/*
1086 	 * The chip reset earlier notified the bootcode that
1087 	 * a driver is present.  We now need to start our pulse
1088 	 * routine so that the bootcode is reminded that we're
1089 	 * still running.
1090 	 */
1091 	bce_pulse(sc);
1092 
1093 	bce_mgmt_init_locked(sc);
1094 	BCE_UNLOCK(sc);
1095 
1096 	/* Finally, print some useful adapter info */
1097 	bce_print_adapter_info(sc);
1098 	DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1099 		__FUNCTION__, sc);
1100 
1101 	goto bce_attach_exit;
1102 
1103 bce_attach_fail:
1104 	bce_release_resources(sc);
1105 
1106 bce_attach_exit:
1107 
1108 	DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1109 
1110 	return(rc);
1111 }
1112 
1113 
1114 /****************************************************************************/
1115 /* Device detach function.                                                  */
1116 /*                                                                          */
1117 /* Stops the controller, resets the controller, and releases resources.     */
1118 /*                                                                          */
1119 /* Returns:                                                                 */
1120 /*   0 on success, positive value on failure.                               */
1121 /****************************************************************************/
1122 static int
1123 bce_detach(device_t dev)
1124 {
1125 	struct bce_softc *sc = device_get_softc(dev);
1126 	struct ifnet *ifp;
1127 	u32 msg;
1128 
1129 	DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1130 
1131 	ifp = sc->bce_ifp;
1132 
1133 	/* Stop and reset the controller. */
1134 	BCE_LOCK(sc);
1135 
1136 	/* Stop the pulse so the bootcode can go to driver absent state. */
1137 	callout_stop(&sc->bce_pulse_callout);
1138 
1139 	bce_stop(sc);
1140 	if (sc->bce_flags & BCE_NO_WOL_FLAG)
1141 		msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1142 	else
1143 		msg = BCE_DRV_MSG_CODE_UNLOAD;
1144 	bce_reset(sc, msg);
1145 
1146 	BCE_UNLOCK(sc);
1147 
1148 	ether_ifdetach(ifp);
1149 
1150 	/* If we have a child device on the MII bus remove it too. */
1151 	bus_generic_detach(dev);
1152 	device_delete_child(dev, sc->bce_miibus);
1153 
1154 	/* Release all remaining resources. */
1155 	bce_release_resources(sc);
1156 
1157 	DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1158 
1159 	return(0);
1160 }
1161 
1162 
1163 /****************************************************************************/
1164 /* Device shutdown function.                                                */
1165 /*                                                                          */
1166 /* Stops and resets the controller.                                         */
1167 /*                                                                          */
1168 /* Returns:                                                                 */
1169 /*   0 on success, positive value on failure.                               */
1170 /****************************************************************************/
1171 static int
1172 bce_shutdown(device_t dev)
1173 {
1174 	struct bce_softc *sc = device_get_softc(dev);
1175 	u32 msg;
1176 
1177 	DBENTER(BCE_VERBOSE);
1178 
1179 	BCE_LOCK(sc);
1180 	bce_stop(sc);
1181 	if (sc->bce_flags & BCE_NO_WOL_FLAG)
1182 		msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1183 	else
1184 		msg = BCE_DRV_MSG_CODE_UNLOAD;
1185 	bce_reset(sc, msg);
1186 	BCE_UNLOCK(sc);
1187 
1188 	DBEXIT(BCE_VERBOSE);
1189 
1190 	return (0);
1191 }
1192 
1193 
1194 #ifdef BCE_DEBUG
1195 /****************************************************************************/
1196 /* Register read.                                                           */
1197 /*                                                                          */
1198 /* Returns:                                                                 */
1199 /*   The value of the register.                                             */
1200 /****************************************************************************/
1201 static u32
1202 bce_reg_rd(struct bce_softc *sc, u32 offset)
1203 {
1204 	u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset);
1205 	DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1206 		__FUNCTION__, offset, val);
1207 	return val;
1208 }
1209 
1210 
1211 /****************************************************************************/
1212 /* Register write (16 bit).                                                 */
1213 /*                                                                          */
1214 /* Returns:                                                                 */
1215 /*   Nothing.                                                               */
1216 /****************************************************************************/
1217 static void
1218 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1219 {
1220 	DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1221 		__FUNCTION__, offset, val);
1222 	bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val);
1223 }
1224 
1225 
1226 /****************************************************************************/
1227 /* Register write.                                                          */
1228 /*                                                                          */
1229 /* Returns:                                                                 */
1230 /*   Nothing.                                                               */
1231 /****************************************************************************/
1232 static void
1233 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1234 {
1235 	DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1236 		__FUNCTION__, offset, val);
1237 	bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val);
1238 }
1239 #endif
1240 
1241 /****************************************************************************/
1242 /* Indirect register read.                                                  */
1243 /*                                                                          */
1244 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1245 /* configuration space.  Using this mechanism avoids issues with posted     */
1246 /* reads but is much slower than memory-mapped I/O.                         */
1247 /*                                                                          */
1248 /* Returns:                                                                 */
1249 /*   The value of the register.                                             */
1250 /****************************************************************************/
1251 static u32
1252 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1253 {
1254 	device_t dev;
1255 	dev = sc->bce_dev;
1256 
1257 	pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1258 #ifdef BCE_DEBUG
1259 	{
1260 		u32 val;
1261 		val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1262 		DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1263 			__FUNCTION__, offset, val);
1264 		return val;
1265 	}
1266 #else
1267 	return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1268 #endif
1269 }
1270 
1271 
1272 /****************************************************************************/
1273 /* Indirect register write.                                                 */
1274 /*                                                                          */
1275 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1276 /* configuration space.  Using this mechanism avoids issues with posted     */
1277 /* writes but is muchh slower than memory-mapped I/O.                       */
1278 /*                                                                          */
1279 /* Returns:                                                                 */
1280 /*   Nothing.                                                               */
1281 /****************************************************************************/
1282 static void
1283 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1284 {
1285 	device_t dev;
1286 	dev = sc->bce_dev;
1287 
1288 	DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1289 		__FUNCTION__, offset, val);
1290 
1291 	pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1292 	pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1293 }
1294 
1295 
1296 #ifdef BCE_DEBUG
1297 /****************************************************************************/
1298 /* Context memory read.                                                     */
1299 /*                                                                          */
1300 /* The NetXtreme II controller uses context memory to track connection      */
1301 /* information for L2 and higher network protocols.                         */
1302 /*                                                                          */
1303 /* Returns:                                                                 */
1304 /*   The requested 32 bit value of context memory.                          */
1305 /****************************************************************************/
1306 static u32
1307 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1308 {
1309 	u32 idx, offset, retry_cnt = 5, val;
1310 
1311 	DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1312 		BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1313 			__FUNCTION__, cid_addr));
1314 
1315 	offset = ctx_offset + cid_addr;
1316 
1317 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
1318 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
1319 
1320 		REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1321 
1322 		for (idx = 0; idx < retry_cnt; idx++) {
1323 			val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1324 			if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1325 				break;
1326 			DELAY(5);
1327 		}
1328 
1329 		if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1330 			BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1331 				"cid_addr = 0x%08X, offset = 0x%08X!\n",
1332 				__FILE__, __LINE__, cid_addr, ctx_offset);
1333 
1334 		val = REG_RD(sc, BCE_CTX_CTX_DATA);
1335 	} else {
1336 		REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1337 		val = REG_RD(sc, BCE_CTX_DATA);
1338 	}
1339 
1340 	DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1341 		"val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1342 
1343 	return(val);
1344 }
1345 #endif
1346 
1347 
1348 /****************************************************************************/
1349 /* Context memory write.                                                    */
1350 /*                                                                          */
1351 /* The NetXtreme II controller uses context memory to track connection      */
1352 /* information for L2 and higher network protocols.                         */
1353 /*                                                                          */
1354 /* Returns:                                                                 */
1355 /*   Nothing.                                                               */
1356 /****************************************************************************/
1357 static void
1358 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1359 {
1360 	u32 idx, offset = ctx_offset + cid_addr;
1361 	u32 val, retry_cnt = 5;
1362 
1363 	DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1364 		"val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1365 
1366 	DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1367 		BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1368 			__FUNCTION__, cid_addr));
1369 
1370 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
1371 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
1372 
1373 		REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1374 		REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1375 
1376 		for (idx = 0; idx < retry_cnt; idx++) {
1377 			val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1378 			if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1379 				break;
1380 			DELAY(5);
1381 		}
1382 
1383 		if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1384 			BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1385 				"cid_addr = 0x%08X, offset = 0x%08X!\n",
1386 				__FILE__, __LINE__, cid_addr, ctx_offset);
1387 
1388 	} else {
1389 		REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1390 		REG_WR(sc, BCE_CTX_DATA, ctx_val);
1391 	}
1392 }
1393 
1394 
1395 /****************************************************************************/
1396 /* PHY register read.                                                       */
1397 /*                                                                          */
1398 /* Implements register reads on the MII bus.                                */
1399 /*                                                                          */
1400 /* Returns:                                                                 */
1401 /*   The value of the register.                                             */
1402 /****************************************************************************/
1403 static int
1404 bce_miibus_read_reg(device_t dev, int phy, int reg)
1405 {
1406 	struct bce_softc *sc;
1407 	u32 val;
1408 	int i;
1409 
1410 	sc = device_get_softc(dev);
1411 
1412 	/* Make sure we are accessing the correct PHY address. */
1413 	if (phy != sc->bce_phy_addr) {
1414 		DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY read!\n", phy);
1415 		return(0);
1416 	}
1417 
1418 	if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1419 		val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1420 		val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1421 
1422 		REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1423 		REG_RD(sc, BCE_EMAC_MDIO_MODE);
1424 
1425 		DELAY(40);
1426 	}
1427 
1428 
1429 	val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1430 		BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1431 		BCE_EMAC_MDIO_COMM_START_BUSY;
1432 	REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1433 
1434 	for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1435 		DELAY(10);
1436 
1437 		val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1438 		if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1439 			DELAY(5);
1440 
1441 			val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1442 			val &= BCE_EMAC_MDIO_COMM_DATA;
1443 
1444 			break;
1445 		}
1446 	}
1447 
1448 	if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1449 		BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1450 			__FILE__, __LINE__, phy, reg);
1451 		val = 0x0;
1452 	} else {
1453 		val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1454 	}
1455 
1456 
1457 	if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1458 		val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1459 		val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1460 
1461 		REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1462 		REG_RD(sc, BCE_EMAC_MDIO_MODE);
1463 
1464 		DELAY(40);
1465 	}
1466 
1467 	DB_PRINT_PHY_REG(reg, val);
1468 	return (val & 0xffff);
1469 
1470 }
1471 
1472 
1473 /****************************************************************************/
1474 /* PHY register write.                                                      */
1475 /*                                                                          */
1476 /* Implements register writes on the MII bus.                               */
1477 /*                                                                          */
1478 /* Returns:                                                                 */
1479 /*   The value of the register.                                             */
1480 /****************************************************************************/
1481 static int
1482 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1483 {
1484 	struct bce_softc *sc;
1485 	u32 val1;
1486 	int i;
1487 
1488 	sc = device_get_softc(dev);
1489 
1490 	/* Make sure we are accessing the correct PHY address. */
1491 	if (phy != sc->bce_phy_addr) {
1492 		DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY write!\n", phy);
1493 		return(0);
1494 	}
1495 
1496 	DB_PRINT_PHY_REG(reg, val);
1497 
1498 	if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1499 		val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1500 		val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1501 
1502 		REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1503 		REG_RD(sc, BCE_EMAC_MDIO_MODE);
1504 
1505 		DELAY(40);
1506 	}
1507 
1508 	val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1509 		BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1510 		BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1511 	REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1512 
1513 	for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1514 		DELAY(10);
1515 
1516 		val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1517 		if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1518 			DELAY(5);
1519 			break;
1520 		}
1521 	}
1522 
1523 	if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1524 		BCE_PRINTF("%s(%d): PHY write timeout!\n",
1525 			__FILE__, __LINE__);
1526 
1527 	if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1528 		val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1529 		val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1530 
1531 		REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1532 		REG_RD(sc, BCE_EMAC_MDIO_MODE);
1533 
1534 		DELAY(40);
1535 	}
1536 
1537 	return 0;
1538 }
1539 
1540 
1541 /****************************************************************************/
1542 /* MII bus status change.                                                   */
1543 /*                                                                          */
1544 /* Called by the MII bus driver when the PHY establishes link to set the    */
1545 /* MAC interface registers.                                                 */
1546 /*                                                                          */
1547 /* Returns:                                                                 */
1548 /*   Nothing.                                                               */
1549 /****************************************************************************/
1550 static void
1551 bce_miibus_statchg(device_t dev)
1552 {
1553 	struct bce_softc *sc;
1554 	struct mii_data *mii;
1555 	int val;
1556 
1557 	sc = device_get_softc(dev);
1558 
1559 	DBENTER(BCE_VERBOSE_PHY);
1560 
1561 	mii = device_get_softc(sc->bce_miibus);
1562 
1563 	val = REG_RD(sc, BCE_EMAC_MODE);
1564 	val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
1565 		BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
1566 		BCE_EMAC_MODE_25G);
1567 
1568 	/* Set MII or GMII interface based on the speed negotiated by the PHY. */
1569 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
1570 	case IFM_10_T:
1571 		if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1572 			DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n");
1573 			val |= BCE_EMAC_MODE_PORT_MII_10;
1574 			break;
1575 		}
1576 		/* fall-through */
1577 	case IFM_100_TX:
1578 		DBPRINT(sc, BCE_INFO, "Enabling MII interface.\n");
1579 		val |= BCE_EMAC_MODE_PORT_MII;
1580 		break;
1581 	case IFM_2500_SX:
1582 		DBPRINT(sc, BCE_INFO, "Enabling 2.5G MAC mode.\n");
1583 		val |= BCE_EMAC_MODE_25G;
1584 		/* fall-through */
1585 	case IFM_1000_T:
1586 	case IFM_1000_SX:
1587 		DBPRINT(sc, BCE_INFO, "Enabling GMII interface.\n");
1588 		val |= BCE_EMAC_MODE_PORT_GMII;
1589 		break;
1590 	default:
1591 		DBPRINT(sc, BCE_INFO, "Unknown speed, enabling default GMII "
1592 			"interface.\n");
1593 		val |= BCE_EMAC_MODE_PORT_GMII;
1594 	}
1595 
1596 	/* Set half or full duplex based on the duplicity negotiated by the PHY. */
1597 	if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
1598 		DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1599 		val |= BCE_EMAC_MODE_HALF_DUPLEX;
1600 	} else
1601 		DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1602 
1603 	REG_WR(sc, BCE_EMAC_MODE, val);
1604 
1605 #if 0
1606 	/* ToDo: Enable flow control support in brgphy and bge. */
1607 	/* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */
1608 	if (mii->mii_media_active & IFM_FLAG0)
1609 		BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
1610 	if (mii->mii_media_active & IFM_FLAG1)
1611 		BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
1612 #endif
1613 
1614 	DBEXIT(BCE_VERBOSE_PHY);
1615 }
1616 
1617 
1618 /****************************************************************************/
1619 /* Acquire NVRAM lock.                                                      */
1620 /*                                                                          */
1621 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1622 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1623 /* for use by the driver.                                                   */
1624 /*                                                                          */
1625 /* Returns:                                                                 */
1626 /*   0 on success, positive value on failure.                               */
1627 /****************************************************************************/
1628 static int
1629 bce_acquire_nvram_lock(struct bce_softc *sc)
1630 {
1631 	u32 val;
1632 	int j, rc = 0;
1633 
1634 	DBENTER(BCE_VERBOSE_NVRAM);
1635 
1636 	/* Request access to the flash interface. */
1637 	REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1638 	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1639 		val = REG_RD(sc, BCE_NVM_SW_ARB);
1640 		if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1641 			break;
1642 
1643 		DELAY(5);
1644 	}
1645 
1646 	if (j >= NVRAM_TIMEOUT_COUNT) {
1647 		DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1648 		rc = EBUSY;
1649 	}
1650 
1651 	DBEXIT(BCE_VERBOSE_NVRAM);
1652 	return (rc);
1653 }
1654 
1655 
1656 /****************************************************************************/
1657 /* Release NVRAM lock.                                                      */
1658 /*                                                                          */
1659 /* When the caller is finished accessing NVRAM the lock must be released.   */
1660 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1661 /* for use by the driver.                                                   */
1662 /*                                                                          */
1663 /* Returns:                                                                 */
1664 /*   0 on success, positive value on failure.                               */
1665 /****************************************************************************/
1666 static int
1667 bce_release_nvram_lock(struct bce_softc *sc)
1668 {
1669 	u32 val;
1670 	int j, rc = 0;
1671 
1672 	DBENTER(BCE_VERBOSE_NVRAM);
1673 
1674 	/*
1675 	 * Relinquish nvram interface.
1676 	 */
1677 	REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1678 
1679 	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1680 		val = REG_RD(sc, BCE_NVM_SW_ARB);
1681 		if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1682 			break;
1683 
1684 		DELAY(5);
1685 	}
1686 
1687 	if (j >= NVRAM_TIMEOUT_COUNT) {
1688 		DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
1689 		rc = EBUSY;
1690 	}
1691 
1692 	DBEXIT(BCE_VERBOSE_NVRAM);
1693 	return (rc);
1694 }
1695 
1696 
1697 #ifdef BCE_NVRAM_WRITE_SUPPORT
1698 /****************************************************************************/
1699 /* Enable NVRAM write access.                                               */
1700 /*                                                                          */
1701 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
1702 /*                                                                          */
1703 /* Returns:                                                                 */
1704 /*   0 on success, positive value on failure.                               */
1705 /****************************************************************************/
1706 static int
1707 bce_enable_nvram_write(struct bce_softc *sc)
1708 {
1709 	u32 val;
1710 	int rc = 0;
1711 
1712 	DBENTER(BCE_VERBOSE_NVRAM);
1713 
1714 	val = REG_RD(sc, BCE_MISC_CFG);
1715 	REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1716 
1717 	if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
1718 		int j;
1719 
1720 		REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1721 		REG_WR(sc, BCE_NVM_COMMAND,	BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1722 
1723 		for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1724 			DELAY(5);
1725 
1726 			val = REG_RD(sc, BCE_NVM_COMMAND);
1727 			if (val & BCE_NVM_COMMAND_DONE)
1728 				break;
1729 		}
1730 
1731 		if (j >= NVRAM_TIMEOUT_COUNT) {
1732 			DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1733 			rc = EBUSY;
1734 		}
1735 	}
1736 
1737 	DBENTER(BCE_VERBOSE_NVRAM);
1738 	return (rc);
1739 }
1740 
1741 
1742 /****************************************************************************/
1743 /* Disable NVRAM write access.                                              */
1744 /*                                                                          */
1745 /* When the caller is finished writing to NVRAM write access must be        */
1746 /* disabled.                                                                */
1747 /*                                                                          */
1748 /* Returns:                                                                 */
1749 /*   Nothing.                                                               */
1750 /****************************************************************************/
1751 static void
1752 bce_disable_nvram_write(struct bce_softc *sc)
1753 {
1754 	u32 val;
1755 
1756 	DBENTER(BCE_VERBOSE_NVRAM);
1757 
1758 	val = REG_RD(sc, BCE_MISC_CFG);
1759 	REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1760 
1761 	DBEXIT(BCE_VERBOSE_NVRAM);
1762 
1763 }
1764 #endif
1765 
1766 
1767 /****************************************************************************/
1768 /* Enable NVRAM access.                                                     */
1769 /*                                                                          */
1770 /* Before accessing NVRAM for read or write operations the caller must      */
1771 /* enabled NVRAM access.                                                    */
1772 /*                                                                          */
1773 /* Returns:                                                                 */
1774 /*   Nothing.                                                               */
1775 /****************************************************************************/
1776 static void
1777 bce_enable_nvram_access(struct bce_softc *sc)
1778 {
1779 	u32 val;
1780 
1781 	DBENTER(BCE_VERBOSE_NVRAM);
1782 
1783 	val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1784 	/* Enable both bits, even on read. */
1785 	REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1786 	       val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1787 
1788 	DBEXIT(BCE_VERBOSE_NVRAM);
1789 }
1790 
1791 
1792 /****************************************************************************/
1793 /* Disable NVRAM access.                                                    */
1794 /*                                                                          */
1795 /* When the caller is finished accessing NVRAM access must be disabled.     */
1796 /*                                                                          */
1797 /* Returns:                                                                 */
1798 /*   Nothing.                                                               */
1799 /****************************************************************************/
1800 static void
1801 bce_disable_nvram_access(struct bce_softc *sc)
1802 {
1803 	u32 val;
1804 
1805 	DBENTER(BCE_VERBOSE_NVRAM);
1806 
1807 	val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1808 
1809 	/* Disable both bits, even after read. */
1810 	REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1811 		val & ~(BCE_NVM_ACCESS_ENABLE_EN |
1812 			BCE_NVM_ACCESS_ENABLE_WR_EN));
1813 
1814 	DBEXIT(BCE_VERBOSE_NVRAM);
1815 }
1816 
1817 
1818 #ifdef BCE_NVRAM_WRITE_SUPPORT
1819 /****************************************************************************/
1820 /* Erase NVRAM page before writing.                                         */
1821 /*                                                                          */
1822 /* Non-buffered flash parts require that a page be erased before it is      */
1823 /* written.                                                                 */
1824 /*                                                                          */
1825 /* Returns:                                                                 */
1826 /*   0 on success, positive value on failure.                               */
1827 /****************************************************************************/
1828 static int
1829 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
1830 {
1831 	u32 cmd;
1832 	int j, rc = 0;
1833 
1834 	DBENTER(BCE_VERBOSE_NVRAM);
1835 
1836 	/* Buffered flash doesn't require an erase. */
1837 	if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
1838 		goto bce_nvram_erase_page_exit;
1839 
1840 	/* Build an erase command. */
1841 	cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
1842 	      BCE_NVM_COMMAND_DOIT;
1843 
1844 	/*
1845 	 * Clear the DONE bit separately, set the NVRAM adress to erase,
1846 	 * and issue the erase command.
1847 	 */
1848 	REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1849 	REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1850 	REG_WR(sc, BCE_NVM_COMMAND, cmd);
1851 
1852 	/* Wait for completion. */
1853 	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1854 		u32 val;
1855 
1856 		DELAY(5);
1857 
1858 		val = REG_RD(sc, BCE_NVM_COMMAND);
1859 		if (val & BCE_NVM_COMMAND_DONE)
1860 			break;
1861 	}
1862 
1863 	if (j >= NVRAM_TIMEOUT_COUNT) {
1864 		DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
1865 		rc = EBUSY;
1866 	}
1867 
1868 bce_nvram_erase_page_exit:
1869 	DBEXIT(BCE_VERBOSE_NVRAM);
1870 	return (rc);
1871 }
1872 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1873 
1874 
1875 /****************************************************************************/
1876 /* Read a dword (32 bits) from NVRAM.                                       */
1877 /*                                                                          */
1878 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1879 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1880 /*                                                                          */
1881 /* Returns:                                                                 */
1882 /*   0 on success and the 32 bit value read, positive value on failure.     */
1883 /****************************************************************************/
1884 static int
1885 bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val,
1886 							u32 cmd_flags)
1887 {
1888 	u32 cmd;
1889 	int i, rc = 0;
1890 
1891 	DBENTER(BCE_EXTREME_NVRAM);
1892 
1893 	/* Build the command word. */
1894 	cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1895 
1896 	/* Calculate the offset for buffered flash if translation is used. */
1897 	if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1898 		offset = ((offset / sc->bce_flash_info->page_size) <<
1899 			   sc->bce_flash_info->page_bits) +
1900 			  (offset % sc->bce_flash_info->page_size);
1901 	}
1902 
1903 	/*
1904 	 * Clear the DONE bit separately, set the address to read,
1905 	 * and issue the read.
1906 	 */
1907 	REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1908 	REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1909 	REG_WR(sc, BCE_NVM_COMMAND, cmd);
1910 
1911 	/* Wait for completion. */
1912 	for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1913 		u32 val;
1914 
1915 		DELAY(5);
1916 
1917 		val = REG_RD(sc, BCE_NVM_COMMAND);
1918 		if (val & BCE_NVM_COMMAND_DONE) {
1919 			val = REG_RD(sc, BCE_NVM_READ);
1920 
1921 			val = bce_be32toh(val);
1922 			memcpy(ret_val, &val, 4);
1923 			break;
1924 		}
1925 	}
1926 
1927 	/* Check for errors. */
1928 	if (i >= NVRAM_TIMEOUT_COUNT) {
1929 		BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n",
1930 			__FILE__, __LINE__, offset);
1931 		rc = EBUSY;
1932 	}
1933 
1934 	DBEXIT(BCE_EXTREME_NVRAM);
1935 	return(rc);
1936 }
1937 
1938 
1939 #ifdef BCE_NVRAM_WRITE_SUPPORT
1940 /****************************************************************************/
1941 /* Write a dword (32 bits) to NVRAM.                                        */
1942 /*                                                                          */
1943 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
1944 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
1945 /* enabled NVRAM write access.                                              */
1946 /*                                                                          */
1947 /* Returns:                                                                 */
1948 /*   0 on success, positive value on failure.                               */
1949 /****************************************************************************/
1950 static int
1951 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
1952 	u32 cmd_flags)
1953 {
1954 	u32 cmd, val32;
1955 	int j, rc = 0;
1956 
1957 	DBENTER(BCE_VERBOSE_NVRAM);
1958 
1959 	/* Build the command word. */
1960 	cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
1961 
1962 	/* Calculate the offset for buffered flash if translation is used. */
1963 	if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1964 		offset = ((offset / sc->bce_flash_info->page_size) <<
1965 			  sc->bce_flash_info->page_bits) +
1966 			 (offset % sc->bce_flash_info->page_size);
1967 	}
1968 
1969 	/*
1970 	 * Clear the DONE bit separately, convert NVRAM data to big-endian,
1971 	 * set the NVRAM address to write, and issue the write command
1972 	 */
1973 	REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1974 	memcpy(&val32, val, 4);
1975 	val32 = htobe32(val32);
1976 	REG_WR(sc, BCE_NVM_WRITE, val32);
1977 	REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1978 	REG_WR(sc, BCE_NVM_COMMAND, cmd);
1979 
1980 	/* Wait for completion. */
1981 	for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1982 		DELAY(5);
1983 
1984 		if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
1985 			break;
1986 	}
1987 	if (j >= NVRAM_TIMEOUT_COUNT) {
1988 		BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n",
1989 			__FILE__, __LINE__, offset);
1990 		rc = EBUSY;
1991 	}
1992 
1993 	DBEXIT(BCE_VERBOSE_NVRAM);
1994 	return (rc);
1995 }
1996 #endif /* BCE_NVRAM_WRITE_SUPPORT */
1997 
1998 
1999 /****************************************************************************/
2000 /* Initialize NVRAM access.                                                 */
2001 /*                                                                          */
2002 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2003 /* access that device.                                                      */
2004 /*                                                                          */
2005 /* Returns:                                                                 */
2006 /*   0 on success, positive value on failure.                               */
2007 /****************************************************************************/
2008 static int
2009 bce_init_nvram(struct bce_softc *sc)
2010 {
2011 	u32 val;
2012 	int j, entry_count, rc = 0;
2013 	struct flash_spec *flash;
2014 
2015 	DBENTER(BCE_VERBOSE_NVRAM);
2016 
2017 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
2018 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
2019 		sc->bce_flash_info = &flash_5709;
2020 		goto bce_init_nvram_get_flash_size;
2021 	}
2022 
2023 	/* Determine the selected interface. */
2024 	val = REG_RD(sc, BCE_NVM_CFG1);
2025 
2026 	entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2027 
2028 	/*
2029 	 * Flash reconfiguration is required to support additional
2030 	 * NVRAM devices not directly supported in hardware.
2031 	 * Check if the flash interface was reconfigured
2032 	 * by the bootcode.
2033 	 */
2034 
2035 	if (val & 0x40000000) {
2036 		/* Flash interface reconfigured by bootcode. */
2037 
2038 		DBPRINT(sc,BCE_INFO_LOAD,
2039 			"bce_init_nvram(): Flash WAS reconfigured.\n");
2040 
2041 		for (j = 0, flash = &flash_table[0]; j < entry_count;
2042 		     j++, flash++) {
2043 			if ((val & FLASH_BACKUP_STRAP_MASK) ==
2044 			    (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2045 				sc->bce_flash_info = flash;
2046 				break;
2047 			}
2048 		}
2049 	} else {
2050 		/* Flash interface not yet reconfigured. */
2051 		u32 mask;
2052 
2053 		DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2054 			__FUNCTION__);
2055 
2056 		if (val & (1 << 23))
2057 			mask = FLASH_BACKUP_STRAP_MASK;
2058 		else
2059 			mask = FLASH_STRAP_MASK;
2060 
2061 		/* Look for the matching NVRAM device configuration data. */
2062 		for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2063 
2064 			/* Check if the device matches any of the known devices. */
2065 			if ((val & mask) == (flash->strapping & mask)) {
2066 				/* Found a device match. */
2067 				sc->bce_flash_info = flash;
2068 
2069 				/* Request access to the flash interface. */
2070 				if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2071 					return rc;
2072 
2073 				/* Reconfigure the flash interface. */
2074 				bce_enable_nvram_access(sc);
2075 				REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2076 				REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2077 				REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2078 				REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2079 				bce_disable_nvram_access(sc);
2080 				bce_release_nvram_lock(sc);
2081 
2082 				break;
2083 			}
2084 		}
2085 	}
2086 
2087 	/* Check if a matching device was found. */
2088 	if (j == entry_count) {
2089 		sc->bce_flash_info = NULL;
2090 		BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2091 			__FILE__, __LINE__);
2092 		rc = ENODEV;
2093 	}
2094 
2095 bce_init_nvram_get_flash_size:
2096 	/* Write the flash config data to the shared memory interface. */
2097 	val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2);
2098 	val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2099 	if (val)
2100 		sc->bce_flash_size = val;
2101 	else
2102 		sc->bce_flash_size = sc->bce_flash_info->total_size;
2103 
2104 	DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2105 		__FUNCTION__, sc->bce_flash_info->name,
2106 		sc->bce_flash_info->total_size);
2107 
2108 	DBEXIT(BCE_VERBOSE_NVRAM);
2109 	return rc;
2110 }
2111 
2112 
2113 /****************************************************************************/
2114 /* Read an arbitrary range of data from NVRAM.                              */
2115 /*                                                                          */
2116 /* Prepares the NVRAM interface for access and reads the requested data     */
2117 /* into the supplied buffer.                                                */
2118 /*                                                                          */
2119 /* Returns:                                                                 */
2120 /*   0 on success and the data read, positive value on failure.             */
2121 /****************************************************************************/
2122 static int
2123 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2124 	int buf_size)
2125 {
2126 	int rc = 0;
2127 	u32 cmd_flags, offset32, len32, extra;
2128 
2129 	DBENTER(BCE_VERBOSE_NVRAM);
2130 
2131 	if (buf_size == 0)
2132 		goto bce_nvram_read_exit;
2133 
2134 	/* Request access to the flash interface. */
2135 	if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2136 		goto bce_nvram_read_exit;
2137 
2138 	/* Enable access to flash interface */
2139 	bce_enable_nvram_access(sc);
2140 
2141 	len32 = buf_size;
2142 	offset32 = offset;
2143 	extra = 0;
2144 
2145 	cmd_flags = 0;
2146 
2147 	if (offset32 & 3) {
2148 		u8 buf[4];
2149 		u32 pre_len;
2150 
2151 		offset32 &= ~3;
2152 		pre_len = 4 - (offset & 3);
2153 
2154 		if (pre_len >= len32) {
2155 			pre_len = len32;
2156 			cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2157 		}
2158 		else {
2159 			cmd_flags = BCE_NVM_COMMAND_FIRST;
2160 		}
2161 
2162 		rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2163 
2164 		if (rc)
2165 			return rc;
2166 
2167 		memcpy(ret_buf, buf + (offset & 3), pre_len);
2168 
2169 		offset32 += 4;
2170 		ret_buf += pre_len;
2171 		len32 -= pre_len;
2172 	}
2173 
2174 	if (len32 & 3) {
2175 		extra = 4 - (len32 & 3);
2176 		len32 = (len32 + 4) & ~3;
2177 	}
2178 
2179 	if (len32 == 4) {
2180 		u8 buf[4];
2181 
2182 		if (cmd_flags)
2183 			cmd_flags = BCE_NVM_COMMAND_LAST;
2184 		else
2185 			cmd_flags = BCE_NVM_COMMAND_FIRST |
2186 				    BCE_NVM_COMMAND_LAST;
2187 
2188 		rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2189 
2190 		memcpy(ret_buf, buf, 4 - extra);
2191 	}
2192 	else if (len32 > 0) {
2193 		u8 buf[4];
2194 
2195 		/* Read the first word. */
2196 		if (cmd_flags)
2197 			cmd_flags = 0;
2198 		else
2199 			cmd_flags = BCE_NVM_COMMAND_FIRST;
2200 
2201 		rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2202 
2203 		/* Advance to the next dword. */
2204 		offset32 += 4;
2205 		ret_buf += 4;
2206 		len32 -= 4;
2207 
2208 		while (len32 > 4 && rc == 0) {
2209 			rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2210 
2211 			/* Advance to the next dword. */
2212 			offset32 += 4;
2213 			ret_buf += 4;
2214 			len32 -= 4;
2215 		}
2216 
2217 		if (rc)
2218 			goto bce_nvram_read_locked_exit;
2219 
2220 		cmd_flags = BCE_NVM_COMMAND_LAST;
2221 		rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2222 
2223 		memcpy(ret_buf, buf, 4 - extra);
2224 	}
2225 
2226 bce_nvram_read_locked_exit:
2227 	/* Disable access to flash interface and release the lock. */
2228 	bce_disable_nvram_access(sc);
2229 	bce_release_nvram_lock(sc);
2230 
2231 bce_nvram_read_exit:
2232 	DBEXIT(BCE_VERBOSE_NVRAM);
2233 	return rc;
2234 }
2235 
2236 
2237 #ifdef BCE_NVRAM_WRITE_SUPPORT
2238 /****************************************************************************/
2239 /* Write an arbitrary range of data from NVRAM.                             */
2240 /*                                                                          */
2241 /* Prepares the NVRAM interface for write access and writes the requested   */
2242 /* data from the supplied buffer.  The caller is responsible for            */
2243 /* calculating any appropriate CRCs.                                        */
2244 /*                                                                          */
2245 /* Returns:                                                                 */
2246 /*   0 on success, positive value on failure.                               */
2247 /****************************************************************************/
2248 static int
2249 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2250 	int buf_size)
2251 {
2252 	u32 written, offset32, len32;
2253 	u8 *buf, start[4], end[4];
2254 	int rc = 0;
2255 	int align_start, align_end;
2256 
2257 	DBENTER(BCE_VERBOSE_NVRAM);
2258 
2259 	buf = data_buf;
2260 	offset32 = offset;
2261 	len32 = buf_size;
2262 	align_start = align_end = 0;
2263 
2264 	if ((align_start = (offset32 & 3))) {
2265 		offset32 &= ~3;
2266 		len32 += align_start;
2267 		if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2268 			goto bce_nvram_write_exit;
2269 	}
2270 
2271 	if (len32 & 3) {
2272 	       	if ((len32 > 4) || !align_start) {
2273 			align_end = 4 - (len32 & 3);
2274 			len32 += align_end;
2275 			if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2276 				end, 4))) {
2277 				goto bce_nvram_write_exit;
2278 			}
2279 		}
2280 	}
2281 
2282 	if (align_start || align_end) {
2283 		buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2284 		if (buf == 0) {
2285 			rc = ENOMEM;
2286 			goto bce_nvram_write_exit;
2287 		}
2288 
2289 		if (align_start) {
2290 			memcpy(buf, start, 4);
2291 		}
2292 
2293 		if (align_end) {
2294 			memcpy(buf + len32 - 4, end, 4);
2295 		}
2296 		memcpy(buf + align_start, data_buf, buf_size);
2297 	}
2298 
2299 	written = 0;
2300 	while ((written < len32) && (rc == 0)) {
2301 		u32 page_start, page_end, data_start, data_end;
2302 		u32 addr, cmd_flags;
2303 		int i;
2304 		u8 flash_buffer[264];
2305 
2306 	    /* Find the page_start addr */
2307 		page_start = offset32 + written;
2308 		page_start -= (page_start % sc->bce_flash_info->page_size);
2309 		/* Find the page_end addr */
2310 		page_end = page_start + sc->bce_flash_info->page_size;
2311 		/* Find the data_start addr */
2312 		data_start = (written == 0) ? offset32 : page_start;
2313 		/* Find the data_end addr */
2314 		data_end = (page_end > offset32 + len32) ?
2315 			(offset32 + len32) : page_end;
2316 
2317 		/* Request access to the flash interface. */
2318 		if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2319 			goto bce_nvram_write_exit;
2320 
2321 		/* Enable access to flash interface */
2322 		bce_enable_nvram_access(sc);
2323 
2324 		cmd_flags = BCE_NVM_COMMAND_FIRST;
2325 		if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2326 			int j;
2327 
2328 			/* Read the whole page into the buffer
2329 			 * (non-buffer flash only) */
2330 			for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2331 				if (j == (sc->bce_flash_info->page_size - 4)) {
2332 					cmd_flags |= BCE_NVM_COMMAND_LAST;
2333 				}
2334 				rc = bce_nvram_read_dword(sc,
2335 					page_start + j,
2336 					&flash_buffer[j],
2337 					cmd_flags);
2338 
2339 				if (rc)
2340 					goto bce_nvram_write_locked_exit;
2341 
2342 				cmd_flags = 0;
2343 			}
2344 		}
2345 
2346 		/* Enable writes to flash interface (unlock write-protect) */
2347 		if ((rc = bce_enable_nvram_write(sc)) != 0)
2348 			goto bce_nvram_write_locked_exit;
2349 
2350 		/* Erase the page */
2351 		if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2352 			goto bce_nvram_write_locked_exit;
2353 
2354 		/* Re-enable the write again for the actual write */
2355 		bce_enable_nvram_write(sc);
2356 
2357 		/* Loop to write back the buffer data from page_start to
2358 		 * data_start */
2359 		i = 0;
2360 		if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2361 			for (addr = page_start; addr < data_start;
2362 				addr += 4, i += 4) {
2363 
2364 				rc = bce_nvram_write_dword(sc, addr,
2365 					&flash_buffer[i], cmd_flags);
2366 
2367 				if (rc != 0)
2368 					goto bce_nvram_write_locked_exit;
2369 
2370 				cmd_flags = 0;
2371 			}
2372 		}
2373 
2374 		/* Loop to write the new data from data_start to data_end */
2375 		for (addr = data_start; addr < data_end; addr += 4, i++) {
2376 			if ((addr == page_end - 4) ||
2377 				((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2378 				(addr == data_end - 4))) {
2379 
2380 				cmd_flags |= BCE_NVM_COMMAND_LAST;
2381 			}
2382 			rc = bce_nvram_write_dword(sc, addr, buf,
2383 				cmd_flags);
2384 
2385 			if (rc != 0)
2386 				goto bce_nvram_write_locked_exit;
2387 
2388 			cmd_flags = 0;
2389 			buf += 4;
2390 		}
2391 
2392 		/* Loop to write back the buffer data from data_end
2393 		 * to page_end */
2394 		if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2395 			for (addr = data_end; addr < page_end;
2396 				addr += 4, i += 4) {
2397 
2398 				if (addr == page_end-4) {
2399 					cmd_flags = BCE_NVM_COMMAND_LAST;
2400                 		}
2401 				rc = bce_nvram_write_dword(sc, addr,
2402 					&flash_buffer[i], cmd_flags);
2403 
2404 				if (rc != 0)
2405 					goto bce_nvram_write_locked_exit;
2406 
2407 				cmd_flags = 0;
2408 			}
2409 		}
2410 
2411 		/* Disable writes to flash interface (lock write-protect) */
2412 		bce_disable_nvram_write(sc);
2413 
2414 		/* Disable access to flash interface */
2415 		bce_disable_nvram_access(sc);
2416 		bce_release_nvram_lock(sc);
2417 
2418 		/* Increment written */
2419 		written += data_end - data_start;
2420 	}
2421 
2422 	goto bce_nvram_write_exit;
2423 
2424 bce_nvram_write_locked_exit:
2425 		bce_disable_nvram_write(sc);
2426 		bce_disable_nvram_access(sc);
2427 		bce_release_nvram_lock(sc);
2428 
2429 bce_nvram_write_exit:
2430 	if (align_start || align_end)
2431 		free(buf, M_DEVBUF);
2432 
2433 	DBEXIT(BCE_VERBOSE_NVRAM);
2434 	return (rc);
2435 }
2436 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2437 
2438 
2439 /****************************************************************************/
2440 /* Verifies that NVRAM is accessible and contains valid data.               */
2441 /*                                                                          */
2442 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2443 /* correct.                                                                 */
2444 /*                                                                          */
2445 /* Returns:                                                                 */
2446 /*   0 on success, positive value on failure.                               */
2447 /****************************************************************************/
2448 static int
2449 bce_nvram_test(struct bce_softc *sc)
2450 {
2451 	u32 buf[BCE_NVRAM_SIZE / 4];
2452 	u8 *data = (u8 *) buf;
2453 	int rc = 0;
2454 	u32 magic, csum;
2455 
2456 	DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2457 
2458 	/*
2459 	 * Check that the device NVRAM is valid by reading
2460 	 * the magic value at offset 0.
2461 	 */
2462 	if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2463 		BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", __FILE__, __LINE__);
2464 		goto bce_nvram_test_exit;
2465 	}
2466 
2467 	/*
2468 	 * Verify that offset 0 of the NVRAM contains
2469 	 * a valid magic number.
2470 	 */
2471     magic = bce_be32toh(buf[0]);
2472 	if (magic != BCE_NVRAM_MAGIC) {
2473 		rc = ENODEV;
2474 		BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, "
2475 			"Found: 0x%08X\n",
2476 			__FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2477 		goto bce_nvram_test_exit;
2478 	}
2479 
2480 	/*
2481 	 * Verify that the device NVRAM includes valid
2482 	 * configuration data.
2483 	 */
2484 	if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2485 		BCE_PRINTF("%s(%d): Unable to read Manufacturing Information from "
2486 			"NVRAM!\n", __FILE__, __LINE__);
2487 		goto bce_nvram_test_exit;
2488 	}
2489 
2490 	csum = ether_crc32_le(data, 0x100);
2491 	if (csum != BCE_CRC32_RESIDUAL) {
2492 		rc = ENODEV;
2493 		BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! "
2494 			"Expected: 0x%08X, Found: 0x%08X\n",
2495 			__FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2496 		goto bce_nvram_test_exit;
2497 	}
2498 
2499 	csum = ether_crc32_le(data + 0x100, 0x100);
2500 	if (csum != BCE_CRC32_RESIDUAL) {
2501 		rc = ENODEV;
2502 		BCE_PRINTF("%s(%d): Invalid Feature Configuration Information "
2503 			"NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
2504 			__FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2505 	}
2506 
2507 bce_nvram_test_exit:
2508 	DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2509 	return rc;
2510 }
2511 
2512 
2513 /****************************************************************************/
2514 /* Identifies the current media type of the controller and sets the PHY     */
2515 /* address.                                                                 */
2516 /*                                                                          */
2517 /* Returns:                                                                 */
2518 /*   Nothing.                                                               */
2519 /****************************************************************************/
2520 static void
2521 bce_get_media(struct bce_softc *sc)
2522 {
2523 	u32 val;
2524 
2525 	DBENTER(BCE_VERBOSE);
2526 
2527 	/* Assume PHY address for copper controllers. */
2528 	sc->bce_phy_addr = 1;
2529 
2530 	if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2531  		u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
2532 		u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
2533 		u32 strap;
2534 
2535 		/*
2536 		 * The BCM5709S is software configurable
2537 		 * for Copper or SerDes operation.
2538 		 */
2539 		if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
2540 			DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for copper.\n");
2541 			goto bce_get_media_exit;
2542 		} else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
2543 			DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for dual media.\n");
2544 			sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2545 			goto bce_get_media_exit;
2546 		}
2547 
2548 		if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
2549 			strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
2550 		else
2551 			strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
2552 
2553 		if (pci_get_function(sc->bce_dev) == 0) {
2554 			switch (strap) {
2555 			case 0x4:
2556 			case 0x5:
2557 			case 0x6:
2558 				DBPRINT(sc, BCE_INFO_LOAD,
2559 					"BCM5709 s/w configured for SerDes.\n");
2560 				sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2561 			default:
2562 				DBPRINT(sc, BCE_INFO_LOAD,
2563 					"BCM5709 s/w configured for Copper.\n");
2564 			}
2565 		} else {
2566 			switch (strap) {
2567 			case 0x1:
2568 			case 0x2:
2569 			case 0x4:
2570 				DBPRINT(sc, BCE_INFO_LOAD,
2571 					"BCM5709 s/w configured for SerDes.\n");
2572 				sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2573 			default:
2574 				DBPRINT(sc, BCE_INFO_LOAD,
2575 					"BCM5709 s/w configured for Copper.\n");
2576 			}
2577 		}
2578 
2579 	} else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
2580 		sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2581 
2582 	if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2583 		sc->bce_flags |= BCE_NO_WOL_FLAG;
2584 		if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2585 			sc->bce_phy_addr = 2;
2586 			val = REG_RD_IND(sc, sc->bce_shmem_base +
2587 				 BCE_SHARED_HW_CFG_CONFIG);
2588 			if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
2589 				sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2590 				DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb capable adapter\n");
2591 			}
2592 		}
2593 	} else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2594 		   (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
2595 		sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2596 
2597 bce_get_media_exit:
2598 	DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
2599 		"Using PHY address %d.\n", sc->bce_phy_addr);
2600 
2601 	DBEXIT(BCE_VERBOSE);
2602 }
2603 
2604 
2605 /****************************************************************************/
2606 /* Free any DMA memory owned by the driver.                                 */
2607 /*                                                                          */
2608 /* Scans through each data structre that requires DMA memory and frees      */
2609 /* the memory if allocated.                                                 */
2610 /*                                                                          */
2611 /* Returns:                                                                 */
2612 /*   Nothing.                                                               */
2613 /****************************************************************************/
2614 static void
2615 bce_dma_free(struct bce_softc *sc)
2616 {
2617 	int i;
2618 
2619 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
2620 
2621 	/* Free, unmap, and destroy the status block. */
2622 	if (sc->status_block != NULL) {
2623 		bus_dmamem_free(
2624 			sc->status_tag,
2625 		    sc->status_block,
2626 		    sc->status_map);
2627 		sc->status_block = NULL;
2628 	}
2629 
2630 	if (sc->status_map != NULL) {
2631 		bus_dmamap_unload(
2632 			sc->status_tag,
2633 		    sc->status_map);
2634 		bus_dmamap_destroy(sc->status_tag,
2635 		    sc->status_map);
2636 		sc->status_map = NULL;
2637 	}
2638 
2639 	if (sc->status_tag != NULL) {
2640 		bus_dma_tag_destroy(sc->status_tag);
2641 		sc->status_tag = NULL;
2642 	}
2643 
2644 
2645 	/* Free, unmap, and destroy the statistics block. */
2646 	if (sc->stats_block != NULL) {
2647 		bus_dmamem_free(
2648 			sc->stats_tag,
2649 		    sc->stats_block,
2650 		    sc->stats_map);
2651 		sc->stats_block = NULL;
2652 	}
2653 
2654 	if (sc->stats_map != NULL) {
2655 		bus_dmamap_unload(
2656 			sc->stats_tag,
2657 		    sc->stats_map);
2658 		bus_dmamap_destroy(sc->stats_tag,
2659 		    sc->stats_map);
2660 		sc->stats_map = NULL;
2661 	}
2662 
2663 	if (sc->stats_tag != NULL) {
2664 		bus_dma_tag_destroy(sc->stats_tag);
2665 		sc->stats_tag = NULL;
2666 	}
2667 
2668 
2669 	/* Free, unmap and destroy all context memory pages. */
2670 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
2671 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
2672 		for (i = 0; i < sc->ctx_pages; i++ ) {
2673 			if (sc->ctx_block[i] != NULL) {
2674 				bus_dmamem_free(
2675 					sc->ctx_tag,
2676 				    sc->ctx_block[i],
2677 				    sc->ctx_map[i]);
2678 				sc->ctx_block[i] = NULL;
2679 			}
2680 
2681 			if (sc->ctx_map[i] != NULL) {
2682 				bus_dmamap_unload(
2683 					sc->ctx_tag,
2684 		    		sc->ctx_map[i]);
2685 				bus_dmamap_destroy(
2686 					sc->ctx_tag,
2687 				    sc->ctx_map[i]);
2688 				sc->ctx_map[i] = NULL;
2689 			}
2690 		}
2691 
2692 		/* Destroy the context memory tag. */
2693 		if (sc->ctx_tag != NULL) {
2694 			bus_dma_tag_destroy(sc->ctx_tag);
2695 			sc->ctx_tag = NULL;
2696 		}
2697 	}
2698 
2699 
2700 	/* Free, unmap and destroy all TX buffer descriptor chain pages. */
2701 	for (i = 0; i < TX_PAGES; i++ ) {
2702 		if (sc->tx_bd_chain[i] != NULL) {
2703 			bus_dmamem_free(
2704 				sc->tx_bd_chain_tag,
2705 			    sc->tx_bd_chain[i],
2706 			    sc->tx_bd_chain_map[i]);
2707 			sc->tx_bd_chain[i] = NULL;
2708 		}
2709 
2710 		if (sc->tx_bd_chain_map[i] != NULL) {
2711 			bus_dmamap_unload(
2712 				sc->tx_bd_chain_tag,
2713 		    	sc->tx_bd_chain_map[i]);
2714 			bus_dmamap_destroy(
2715 				sc->tx_bd_chain_tag,
2716 			    sc->tx_bd_chain_map[i]);
2717 			sc->tx_bd_chain_map[i] = NULL;
2718 		}
2719 	}
2720 
2721 	/* Destroy the TX buffer descriptor tag. */
2722 	if (sc->tx_bd_chain_tag != NULL) {
2723 		bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2724 		sc->tx_bd_chain_tag = NULL;
2725 	}
2726 
2727 
2728 	/* Free, unmap and destroy all RX buffer descriptor chain pages. */
2729 	for (i = 0; i < RX_PAGES; i++ ) {
2730 		if (sc->rx_bd_chain[i] != NULL) {
2731 			bus_dmamem_free(
2732 				sc->rx_bd_chain_tag,
2733 			    sc->rx_bd_chain[i],
2734 			    sc->rx_bd_chain_map[i]);
2735 			sc->rx_bd_chain[i] = NULL;
2736 		}
2737 
2738 		if (sc->rx_bd_chain_map[i] != NULL) {
2739 			bus_dmamap_unload(
2740 				sc->rx_bd_chain_tag,
2741 		    	sc->rx_bd_chain_map[i]);
2742 			bus_dmamap_destroy(
2743 				sc->rx_bd_chain_tag,
2744 			    sc->rx_bd_chain_map[i]);
2745 			sc->rx_bd_chain_map[i] = NULL;
2746 		}
2747 	}
2748 
2749 	/* Destroy the RX buffer descriptor tag. */
2750 	if (sc->rx_bd_chain_tag != NULL) {
2751 		bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2752 		sc->rx_bd_chain_tag = NULL;
2753 	}
2754 
2755 
2756 #ifdef BCE_USE_SPLIT_HEADER
2757 	/* Free, unmap and destroy all page buffer descriptor chain pages. */
2758 	for (i = 0; i < PG_PAGES; i++ ) {
2759 		if (sc->pg_bd_chain[i] != NULL) {
2760 			bus_dmamem_free(
2761 				sc->pg_bd_chain_tag,
2762 			    sc->pg_bd_chain[i],
2763 			    sc->pg_bd_chain_map[i]);
2764 			sc->pg_bd_chain[i] = NULL;
2765 		}
2766 
2767 		if (sc->pg_bd_chain_map[i] != NULL) {
2768 			bus_dmamap_unload(
2769 				sc->pg_bd_chain_tag,
2770 		    	sc->pg_bd_chain_map[i]);
2771 			bus_dmamap_destroy(
2772 				sc->pg_bd_chain_tag,
2773 			    sc->pg_bd_chain_map[i]);
2774 			sc->pg_bd_chain_map[i] = NULL;
2775 		}
2776 	}
2777 
2778 	/* Destroy the page buffer descriptor tag. */
2779 	if (sc->pg_bd_chain_tag != NULL) {
2780 		bus_dma_tag_destroy(sc->pg_bd_chain_tag);
2781 		sc->pg_bd_chain_tag = NULL;
2782 	}
2783 #endif
2784 
2785 
2786 	/* Unload and destroy the TX mbuf maps. */
2787 	for (i = 0; i < TOTAL_TX_BD; i++) {
2788 		if (sc->tx_mbuf_map[i] != NULL) {
2789 			bus_dmamap_unload(sc->tx_mbuf_tag,
2790 				sc->tx_mbuf_map[i]);
2791 			bus_dmamap_destroy(sc->tx_mbuf_tag,
2792 	 			sc->tx_mbuf_map[i]);
2793 			sc->tx_mbuf_map[i] = NULL;
2794 		}
2795 	}
2796 
2797 	/* Destroy the TX mbuf tag. */
2798 	if (sc->tx_mbuf_tag != NULL) {
2799 		bus_dma_tag_destroy(sc->tx_mbuf_tag);
2800 		sc->tx_mbuf_tag = NULL;
2801 	}
2802 
2803 	/* Unload and destroy the RX mbuf maps. */
2804 	for (i = 0; i < TOTAL_RX_BD; i++) {
2805 		if (sc->rx_mbuf_map[i] != NULL) {
2806 			bus_dmamap_unload(sc->rx_mbuf_tag,
2807 				sc->rx_mbuf_map[i]);
2808 			bus_dmamap_destroy(sc->rx_mbuf_tag,
2809 	 			sc->rx_mbuf_map[i]);
2810 			sc->rx_mbuf_map[i] = NULL;
2811 		}
2812 	}
2813 
2814 	/* Destroy the RX mbuf tag. */
2815 	if (sc->rx_mbuf_tag != NULL) {
2816 		bus_dma_tag_destroy(sc->rx_mbuf_tag);
2817 		sc->rx_mbuf_tag = NULL;
2818 	}
2819 
2820 #ifdef BCE_USE_SPLIT_HEADER
2821 	/* Unload and destroy the page mbuf maps. */
2822 	for (i = 0; i < TOTAL_PG_BD; i++) {
2823 		if (sc->pg_mbuf_map[i] != NULL) {
2824 			bus_dmamap_unload(sc->pg_mbuf_tag,
2825 				sc->pg_mbuf_map[i]);
2826 			bus_dmamap_destroy(sc->pg_mbuf_tag,
2827 	 			sc->pg_mbuf_map[i]);
2828 			sc->pg_mbuf_map[i] = NULL;
2829 		}
2830 	}
2831 
2832 	/* Destroy the page mbuf tag. */
2833 	if (sc->pg_mbuf_tag != NULL) {
2834 		bus_dma_tag_destroy(sc->pg_mbuf_tag);
2835 		sc->pg_mbuf_tag = NULL;
2836 	}
2837 #endif
2838 
2839 	/* Destroy the parent tag */
2840 	if (sc->parent_tag != NULL) {
2841 		bus_dma_tag_destroy(sc->parent_tag);
2842 		sc->parent_tag = NULL;
2843 	}
2844 
2845 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
2846 }
2847 
2848 
2849 /****************************************************************************/
2850 /* Get DMA memory from the OS.                                              */
2851 /*                                                                          */
2852 /* Validates that the OS has provided DMA buffers in response to a          */
2853 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2854 /* When the callback is used the OS will return 0 for the mapping function  */
2855 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2856 /* failures back to the caller.                                             */
2857 /*                                                                          */
2858 /* Returns:                                                                 */
2859 /*   Nothing.                                                               */
2860 /****************************************************************************/
2861 static void
2862 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2863 {
2864 	bus_addr_t *busaddr = arg;
2865 
2866 	/* Simulate a mapping failure. */
2867 	DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2868 		printf("bce: %s(%d): Simulating DMA mapping error.\n",
2869 			__FILE__, __LINE__);
2870 		error = ENOMEM);
2871 
2872 	/* Check for an error and signal the caller that an error occurred. */
2873 	if (error) {
2874 		printf("bce %s(%d): DMA mapping error! error = %d, "
2875 		    "nseg = %d\n", __FILE__, __LINE__, error, nseg);
2876 		*busaddr = 0;
2877 		return;
2878 	}
2879 
2880 	*busaddr = segs->ds_addr;
2881 	return;
2882 }
2883 
2884 
2885 /****************************************************************************/
2886 /* Allocate any DMA memory needed by the driver.                            */
2887 /*                                                                          */
2888 /* Allocates DMA memory needed for the various global structures needed by  */
2889 /* hardware.                                                                */
2890 /*                                                                          */
2891 /* Memory alignment requirements:                                           */
2892 /* +-----------------+----------+----------+----------+----------+          */
2893 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
2894 /* +-----------------+----------+----------+----------+----------+          */
2895 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
2896 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
2897 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
2898 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
2899 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
2900 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
2901 /* +-----------------+----------+----------+----------+----------+          */
2902 /*                                                                          */
2903 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2904 /*                                                                          */
2905 /* Returns:                                                                 */
2906 /*   0 for success, positive value for failure.                             */
2907 /****************************************************************************/
2908 static int
2909 bce_dma_alloc(device_t dev)
2910 {
2911 	struct bce_softc *sc;
2912 	int i, error, rc = 0;
2913 	bus_size_t max_size, max_seg_size;
2914 	int max_segments;
2915 
2916 	sc = device_get_softc(dev);
2917 
2918 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
2919 
2920 	/*
2921 	 * Allocate the parent bus DMA tag appropriate for PCI.
2922 	 */
2923 	if (bus_dma_tag_create(NULL,
2924 			1,
2925 			BCE_DMA_BOUNDARY,
2926 			sc->max_bus_addr,
2927 			BUS_SPACE_MAXADDR,
2928 			NULL, NULL,
2929 			MAXBSIZE,
2930 			BUS_SPACE_UNRESTRICTED,
2931 			BUS_SPACE_MAXSIZE_32BIT,
2932 			0,
2933 			NULL, NULL,
2934 			&sc->parent_tag)) {
2935 		BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
2936 			__FILE__, __LINE__);
2937 		rc = ENOMEM;
2938 		goto bce_dma_alloc_exit;
2939 	}
2940 
2941 	/*
2942 	 * Create a DMA tag for the status block, allocate and clear the
2943 	 * memory, map the memory into DMA space, and fetch the physical
2944 	 * address of the block.
2945 	 */
2946 	if (bus_dma_tag_create(sc->parent_tag,
2947 	    	BCE_DMA_ALIGN,
2948 	    	BCE_DMA_BOUNDARY,
2949 	    	sc->max_bus_addr,
2950 	    	BUS_SPACE_MAXADDR,
2951 	    	NULL, NULL,
2952 	    	BCE_STATUS_BLK_SZ,
2953 	    	1,
2954 	    	BCE_STATUS_BLK_SZ,
2955 	    	0,
2956 	    	NULL, NULL,
2957 	    	&sc->status_tag)) {
2958 		BCE_PRINTF("%s(%d): Could not allocate status block DMA tag!\n",
2959 			__FILE__, __LINE__);
2960 		rc = ENOMEM;
2961 		goto bce_dma_alloc_exit;
2962 	}
2963 
2964 	if(bus_dmamem_alloc(sc->status_tag,
2965 	    	(void **)&sc->status_block,
2966 	    	BUS_DMA_NOWAIT,
2967 	    	&sc->status_map)) {
2968 		BCE_PRINTF("%s(%d): Could not allocate status block DMA memory!\n",
2969 			__FILE__, __LINE__);
2970 		rc = ENOMEM;
2971 		goto bce_dma_alloc_exit;
2972 	}
2973 
2974 	bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ);
2975 
2976 	error = bus_dmamap_load(sc->status_tag,
2977 	    	sc->status_map,
2978 	    	sc->status_block,
2979 	    	BCE_STATUS_BLK_SZ,
2980 	    	bce_dma_map_addr,
2981 	    	&sc->status_block_paddr,
2982 	    	BUS_DMA_NOWAIT);
2983 
2984 	if (error) {
2985 		BCE_PRINTF("%s(%d): Could not map status block DMA memory!\n",
2986 			__FILE__, __LINE__);
2987 		rc = ENOMEM;
2988 		goto bce_dma_alloc_exit;
2989 	}
2990 
2991 	DBPRINT(sc, BCE_INFO, "%s(): status_block_paddr = 0x%jX\n",
2992 		__FUNCTION__, (uintmax_t) sc->status_block_paddr);
2993 
2994 	/*
2995 	 * Create a DMA tag for the statistics block, allocate and clear the
2996 	 * memory, map the memory into DMA space, and fetch the physical
2997 	 * address of the block.
2998 	 */
2999 	if (bus_dma_tag_create(sc->parent_tag,
3000 	    	BCE_DMA_ALIGN,
3001 	    	BCE_DMA_BOUNDARY,
3002 	    	sc->max_bus_addr,
3003 	    	BUS_SPACE_MAXADDR,
3004 	    	NULL, NULL,
3005 	    	BCE_STATS_BLK_SZ,
3006 	    	1,
3007 	    	BCE_STATS_BLK_SZ,
3008 	    	0,
3009 	    	NULL, NULL,
3010 	    	&sc->stats_tag)) {
3011 		BCE_PRINTF("%s(%d): Could not allocate statistics block DMA tag!\n",
3012 			__FILE__, __LINE__);
3013 		rc = ENOMEM;
3014 		goto bce_dma_alloc_exit;
3015 	}
3016 
3017 	if (bus_dmamem_alloc(sc->stats_tag,
3018 	    	(void **)&sc->stats_block,
3019 	    	BUS_DMA_NOWAIT,
3020 	    	&sc->stats_map)) {
3021 		BCE_PRINTF("%s(%d): Could not allocate statistics block DMA memory!\n",
3022 			__FILE__, __LINE__);
3023 		rc = ENOMEM;
3024 		goto bce_dma_alloc_exit;
3025 	}
3026 
3027 	bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ);
3028 
3029 	error = bus_dmamap_load(sc->stats_tag,
3030 	    	sc->stats_map,
3031 	    	sc->stats_block,
3032 	    	BCE_STATS_BLK_SZ,
3033 	    	bce_dma_map_addr,
3034 	    	&sc->stats_block_paddr,
3035 	    	BUS_DMA_NOWAIT);
3036 
3037 	if(error) {
3038 		BCE_PRINTF("%s(%d): Could not map statistics block DMA memory!\n",
3039 			__FILE__, __LINE__);
3040 		rc = ENOMEM;
3041 		goto bce_dma_alloc_exit;
3042 	}
3043 
3044 	DBPRINT(sc, BCE_INFO, "%s(): stats_block_paddr = 0x%jX\n",
3045 		__FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3046 
3047 	/* BCM5709 uses host memory as cache for context memory. */
3048 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3049 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3050 		sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3051 		if (sc->ctx_pages == 0)
3052 			sc->ctx_pages = 1;
3053 
3054 		DBRUNIF((sc->ctx_pages > 512),
3055 			BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3056 				__FILE__, __LINE__, sc->ctx_pages));
3057 
3058 		/*
3059 		 * Create a DMA tag for the context pages,
3060 		 * allocate and clear the memory, map the
3061 		 * memory into DMA space, and fetch the
3062 		 * physical address of the block.
3063 		 */
3064 		if(bus_dma_tag_create(sc->parent_tag,
3065 			BCM_PAGE_SIZE,
3066 		    BCE_DMA_BOUNDARY,
3067 			sc->max_bus_addr,
3068 			BUS_SPACE_MAXADDR,
3069 			NULL, NULL,
3070 			BCM_PAGE_SIZE,
3071 			1,
3072 			BCM_PAGE_SIZE,
3073 			0,
3074 			NULL, NULL,
3075 			&sc->ctx_tag)) {
3076 			BCE_PRINTF("%s(%d): Could not allocate CTX DMA tag!\n",
3077 				__FILE__, __LINE__);
3078 			rc = ENOMEM;
3079 			goto bce_dma_alloc_exit;
3080 		}
3081 
3082 		for (i = 0; i < sc->ctx_pages; i++) {
3083 
3084 			if(bus_dmamem_alloc(sc->ctx_tag,
3085 		    		(void **)&sc->ctx_block[i],
3086 	    		BUS_DMA_NOWAIT,
3087 		    	&sc->ctx_map[i])) {
3088 				BCE_PRINTF("%s(%d): Could not allocate CTX "
3089 					"DMA memory!\n", __FILE__, __LINE__);
3090 				rc = ENOMEM;
3091 				goto bce_dma_alloc_exit;
3092 			}
3093 
3094 			bzero((char *)sc->ctx_block[i], BCM_PAGE_SIZE);
3095 
3096 			error = bus_dmamap_load(sc->ctx_tag,
3097 	    		sc->ctx_map[i],
3098 	    		sc->ctx_block[i],
3099 		    	BCM_PAGE_SIZE,
3100 		    	bce_dma_map_addr,
3101 	    		&sc->ctx_paddr[i],
3102 	    		BUS_DMA_NOWAIT);
3103 
3104 			if (error) {
3105 				BCE_PRINTF("%s(%d): Could not map CTX DMA memory!\n",
3106 					__FILE__, __LINE__);
3107 				rc = ENOMEM;
3108 				goto bce_dma_alloc_exit;
3109 			}
3110 
3111 			DBPRINT(sc, BCE_INFO, "%s(): ctx_paddr[%d] = 0x%jX\n",
3112 				__FUNCTION__, i, (uintmax_t) sc->ctx_paddr[i]);
3113 		}
3114 	}
3115 
3116 	/*
3117 	 * Create a DMA tag for the TX buffer descriptor chain,
3118 	 * allocate and clear the  memory, and fetch the
3119 	 * physical address of the block.
3120 	 */
3121 	if(bus_dma_tag_create(sc->parent_tag,
3122 			BCM_PAGE_SIZE,
3123 		    BCE_DMA_BOUNDARY,
3124 			sc->max_bus_addr,
3125 			BUS_SPACE_MAXADDR,
3126 			NULL, NULL,
3127 			BCE_TX_CHAIN_PAGE_SZ,
3128 			1,
3129 			BCE_TX_CHAIN_PAGE_SZ,
3130 			0,
3131 			NULL, NULL,
3132 			&sc->tx_bd_chain_tag)) {
3133 		BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain DMA tag!\n",
3134 			__FILE__, __LINE__);
3135 		rc = ENOMEM;
3136 		goto bce_dma_alloc_exit;
3137 	}
3138 
3139 	for (i = 0; i < TX_PAGES; i++) {
3140 
3141 		if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3142 	    		(void **)&sc->tx_bd_chain[i],
3143 	    		BUS_DMA_NOWAIT,
3144 		    	&sc->tx_bd_chain_map[i])) {
3145 			BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3146 				"chain DMA memory!\n", __FILE__, __LINE__);
3147 			rc = ENOMEM;
3148 			goto bce_dma_alloc_exit;
3149 		}
3150 
3151 		error = bus_dmamap_load(sc->tx_bd_chain_tag,
3152 	    		sc->tx_bd_chain_map[i],
3153 	    		sc->tx_bd_chain[i],
3154 		    	BCE_TX_CHAIN_PAGE_SZ,
3155 		    	bce_dma_map_addr,
3156 	    		&sc->tx_bd_chain_paddr[i],
3157 	    		BUS_DMA_NOWAIT);
3158 
3159 		if (error) {
3160 			BCE_PRINTF("%s(%d): Could not map TX descriptor chain DMA memory!\n",
3161 				__FILE__, __LINE__);
3162 			rc = ENOMEM;
3163 			goto bce_dma_alloc_exit;
3164 		}
3165 
3166 		DBPRINT(sc, BCE_INFO, "%s(): tx_bd_chain_paddr[%d] = 0x%jX\n",
3167 			__FUNCTION__, i, (uintmax_t) sc->tx_bd_chain_paddr[i]);
3168 	}
3169 
3170 	/* Check the required size before mapping to conserve resources. */
3171 	if (bce_tso_enable) {
3172 		max_size     = BCE_TSO_MAX_SIZE;
3173 		max_segments = BCE_MAX_SEGMENTS;
3174 		max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3175 	} else {
3176 		max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3177 		max_segments = BCE_MAX_SEGMENTS;
3178 		max_seg_size = MCLBYTES;
3179 	}
3180 
3181 	/* Create a DMA tag for TX mbufs. */
3182 	if (bus_dma_tag_create(sc->parent_tag,
3183 			1,
3184 			BCE_DMA_BOUNDARY,
3185 			sc->max_bus_addr,
3186 			BUS_SPACE_MAXADDR,
3187 			NULL, NULL,
3188 			max_size,
3189 			max_segments,
3190 			max_seg_size,
3191 			0,
3192 			NULL, NULL,
3193 			&sc->tx_mbuf_tag)) {
3194 		BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3195 			__FILE__, __LINE__);
3196 		rc = ENOMEM;
3197 		goto bce_dma_alloc_exit;
3198 	}
3199 
3200 	/* Create DMA maps for the TX mbufs clusters. */
3201 	for (i = 0; i < TOTAL_TX_BD; i++) {
3202 		if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3203 			&sc->tx_mbuf_map[i])) {
3204 			BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA map!\n",
3205 				__FILE__, __LINE__);
3206 			rc = ENOMEM;
3207 			goto bce_dma_alloc_exit;
3208 		}
3209 	}
3210 
3211 	/*
3212 	 * Create a DMA tag for the RX buffer descriptor chain,
3213 	 * allocate and clear the memory, and fetch the physical
3214 	 * address of the blocks.
3215 	 */
3216 	if (bus_dma_tag_create(sc->parent_tag,
3217 			BCM_PAGE_SIZE,
3218 			BCE_DMA_BOUNDARY,
3219 			BUS_SPACE_MAXADDR,
3220 			sc->max_bus_addr,
3221 			NULL, NULL,
3222 			BCE_RX_CHAIN_PAGE_SZ,
3223 			1,
3224 			BCE_RX_CHAIN_PAGE_SZ,
3225 			0,
3226 			NULL, NULL,
3227 			&sc->rx_bd_chain_tag)) {
3228 		BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain DMA tag!\n",
3229 			__FILE__, __LINE__);
3230 		rc = ENOMEM;
3231 		goto bce_dma_alloc_exit;
3232 	}
3233 
3234 	for (i = 0; i < RX_PAGES; i++) {
3235 
3236 		if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3237 	    		(void **)&sc->rx_bd_chain[i],
3238 	    		BUS_DMA_NOWAIT,
3239 		    	&sc->rx_bd_chain_map[i])) {
3240 			BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3241 				"DMA memory!\n", __FILE__, __LINE__);
3242 			rc = ENOMEM;
3243 			goto bce_dma_alloc_exit;
3244 		}
3245 
3246 		bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3247 
3248 		error = bus_dmamap_load(sc->rx_bd_chain_tag,
3249 	    		sc->rx_bd_chain_map[i],
3250 	    		sc->rx_bd_chain[i],
3251 		    	BCE_RX_CHAIN_PAGE_SZ,
3252 		    	bce_dma_map_addr,
3253 	    		&sc->rx_bd_chain_paddr[i],
3254 	    		BUS_DMA_NOWAIT);
3255 
3256 		if (error) {
3257 			BCE_PRINTF("%s(%d): Could not map RX descriptor chain DMA memory!\n",
3258 				__FILE__, __LINE__);
3259 			rc = ENOMEM;
3260 			goto bce_dma_alloc_exit;
3261 		}
3262 
3263 		DBPRINT(sc, BCE_INFO, "%s(): rx_bd_chain_paddr[%d] = 0x%jX\n",
3264 			__FUNCTION__, i, (uintmax_t) sc->rx_bd_chain_paddr[i]);
3265 	}
3266 
3267 	/*
3268 	 * Create a DMA tag for RX mbufs.
3269 	 */
3270 #ifdef BCE_USE_SPLIT_HEADER
3271 	max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3272 		MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3273 #else
3274 	max_size = max_seg_size = MJUM9BYTES;
3275 #endif
3276 
3277 	if (bus_dma_tag_create(sc->parent_tag,
3278 			1,
3279 			BCE_DMA_BOUNDARY,
3280 			sc->max_bus_addr,
3281 			BUS_SPACE_MAXADDR,
3282 			NULL, NULL,
3283 			max_size,
3284 			1,
3285 			max_seg_size,
3286 			0,
3287 			NULL, NULL,
3288 	    	&sc->rx_mbuf_tag)) {
3289 		BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3290 			__FILE__, __LINE__);
3291 		rc = ENOMEM;
3292 		goto bce_dma_alloc_exit;
3293 	}
3294 
3295 	/* Create DMA maps for the RX mbuf clusters. */
3296 	for (i = 0; i < TOTAL_RX_BD; i++) {
3297 		if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3298 				&sc->rx_mbuf_map[i])) {
3299 			BCE_PRINTF("%s(%d): Unable to create RX mbuf DMA map!\n",
3300 				__FILE__, __LINE__);
3301 			rc = ENOMEM;
3302 			goto bce_dma_alloc_exit;
3303 		}
3304 	}
3305 
3306 #ifdef BCE_USE_SPLIT_HEADER
3307 	/*
3308 	 * Create a DMA tag for the page buffer descriptor chain,
3309 	 * allocate and clear the memory, and fetch the physical
3310 	 * address of the blocks.
3311 	 */
3312 	if (bus_dma_tag_create(sc->parent_tag,
3313 			BCM_PAGE_SIZE,
3314 			BCE_DMA_BOUNDARY,
3315 			BUS_SPACE_MAXADDR,
3316 			sc->max_bus_addr,
3317 			NULL, NULL,
3318 			BCE_PG_CHAIN_PAGE_SZ,
3319 			1,
3320 			BCE_PG_CHAIN_PAGE_SZ,
3321 			0,
3322 			NULL, NULL,
3323 			&sc->pg_bd_chain_tag)) {
3324 		BCE_PRINTF("%s(%d): Could not allocate page descriptor chain DMA tag!\n",
3325 			__FILE__, __LINE__);
3326 		rc = ENOMEM;
3327 		goto bce_dma_alloc_exit;
3328 	}
3329 
3330 	for (i = 0; i < PG_PAGES; i++) {
3331 
3332 		if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3333 	    		(void **)&sc->pg_bd_chain[i],
3334 	    		BUS_DMA_NOWAIT,
3335 		    	&sc->pg_bd_chain_map[i])) {
3336 			BCE_PRINTF("%s(%d): Could not allocate page descriptor chain "
3337 				"DMA memory!\n", __FILE__, __LINE__);
3338 			rc = ENOMEM;
3339 			goto bce_dma_alloc_exit;
3340 		}
3341 
3342 		bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
3343 
3344 		error = bus_dmamap_load(sc->pg_bd_chain_tag,
3345 	    		sc->pg_bd_chain_map[i],
3346 	    		sc->pg_bd_chain[i],
3347 		    	BCE_PG_CHAIN_PAGE_SZ,
3348 		    	bce_dma_map_addr,
3349 	    		&sc->pg_bd_chain_paddr[i],
3350 	    		BUS_DMA_NOWAIT);
3351 
3352 		if (error) {
3353 			BCE_PRINTF("%s(%d): Could not map page descriptor chain DMA memory!\n",
3354 				__FILE__, __LINE__);
3355 			rc = ENOMEM;
3356 			goto bce_dma_alloc_exit;
3357 		}
3358 
3359 		DBPRINT(sc, BCE_INFO, "%s(): pg_bd_chain_paddr[%d] = 0x%jX\n",
3360 			__FUNCTION__, i, (uintmax_t) sc->pg_bd_chain_paddr[i]);
3361 	}
3362 
3363 	/*
3364 	 * Create a DMA tag for page mbufs.
3365 	 */
3366 	max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ?
3367 		MCLBYTES : sc->pg_bd_mbuf_alloc_size);
3368 
3369 	if (bus_dma_tag_create(sc->parent_tag,
3370 			1,
3371 			BCE_DMA_BOUNDARY,
3372 			sc->max_bus_addr,
3373 			BUS_SPACE_MAXADDR,
3374 			NULL, NULL,
3375 			max_size,
3376 			1,
3377 			max_seg_size,
3378 			0,
3379 			NULL, NULL,
3380 	    	&sc->pg_mbuf_tag)) {
3381 		BCE_PRINTF("%s(%d): Could not allocate page mbuf DMA tag!\n",
3382 			__FILE__, __LINE__);
3383 		rc = ENOMEM;
3384 		goto bce_dma_alloc_exit;
3385 	}
3386 
3387 	/* Create DMA maps for the page mbuf clusters. */
3388 	for (i = 0; i < TOTAL_PG_BD; i++) {
3389 		if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3390 				&sc->pg_mbuf_map[i])) {
3391 			BCE_PRINTF("%s(%d): Unable to create page mbuf DMA map!\n",
3392 				__FILE__, __LINE__);
3393 			rc = ENOMEM;
3394 			goto bce_dma_alloc_exit;
3395 		}
3396 	}
3397 #endif
3398 
3399 bce_dma_alloc_exit:
3400 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3401 	return(rc);
3402 }
3403 
3404 
3405 /****************************************************************************/
3406 /* Release all resources used by the driver.                                */
3407 /*                                                                          */
3408 /* Releases all resources acquired by the driver including interrupts,      */
3409 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3410 /*                                                                          */
3411 /* Returns:                                                                 */
3412 /*   Nothing.                                                               */
3413 /****************************************************************************/
3414 static void
3415 bce_release_resources(struct bce_softc *sc)
3416 {
3417 	device_t dev;
3418 
3419 	DBENTER(BCE_VERBOSE_RESET);
3420 
3421 	dev = sc->bce_dev;
3422 
3423 	bce_dma_free(sc);
3424 
3425 	if (sc->bce_intrhand != NULL) {
3426 		DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3427 		bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3428 	}
3429 
3430 	if (sc->bce_res_irq != NULL) {
3431 		DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3432 		bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
3433 			sc->bce_res_irq);
3434 	}
3435 
3436 	if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3437 		DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3438 		pci_release_msi(dev);
3439 	}
3440 
3441 	if (sc->bce_res_mem != NULL) {
3442 		DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3443 		bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bce_res_mem);
3444 	}
3445 
3446 	if (sc->bce_ifp != NULL) {
3447 		DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3448 		if_free(sc->bce_ifp);
3449 	}
3450 
3451 	if (mtx_initialized(&sc->bce_mtx))
3452 		BCE_LOCK_DESTROY(sc);
3453 
3454 	DBEXIT(BCE_VERBOSE_RESET);
3455 }
3456 
3457 
3458 /****************************************************************************/
3459 /* Firmware synchronization.                                                */
3460 /*                                                                          */
3461 /* Before performing certain events such as a chip reset, synchronize with  */
3462 /* the firmware first.                                                      */
3463 /*                                                                          */
3464 /* Returns:                                                                 */
3465 /*   0 for success, positive value for failure.                             */
3466 /****************************************************************************/
3467 static int
3468 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3469 {
3470 	int i, rc = 0;
3471 	u32 val;
3472 
3473 	DBENTER(BCE_VERBOSE_RESET);
3474 
3475 	/* Don't waste any time if we've timed out before. */
3476 	if (sc->bce_fw_timed_out) {
3477 		rc = EBUSY;
3478 		goto bce_fw_sync_exit;
3479 	}
3480 
3481 	/* Increment the message sequence number. */
3482 	sc->bce_fw_wr_seq++;
3483 	msg_data |= sc->bce_fw_wr_seq;
3484 
3485  	DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = 0x%08X\n",
3486  		msg_data);
3487 
3488 	/* Send the message to the bootcode driver mailbox. */
3489 	REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
3490 
3491 	/* Wait for the bootcode to acknowledge the message. */
3492 	for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3493 		/* Check for a response in the bootcode firmware mailbox. */
3494 		val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
3495 		if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3496 			break;
3497 		DELAY(1000);
3498 	}
3499 
3500 	/* If we've timed out, tell the bootcode that we've stopped waiting. */
3501 	if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
3502 		((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
3503 
3504 		BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3505 			"msg_data = 0x%08X\n",
3506 			__FILE__, __LINE__, msg_data);
3507 
3508 		msg_data &= ~BCE_DRV_MSG_CODE;
3509 		msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
3510 
3511 		REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
3512 
3513 		sc->bce_fw_timed_out = 1;
3514 		rc = EBUSY;
3515 	}
3516 
3517 bce_fw_sync_exit:
3518 	DBEXIT(BCE_VERBOSE_RESET);
3519 	return (rc);
3520 }
3521 
3522 
3523 /****************************************************************************/
3524 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
3525 /*                                                                          */
3526 /* Returns:                                                                 */
3527 /*   Nothing.                                                               */
3528 /****************************************************************************/
3529 static void
3530 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code,
3531 	u32 rv2p_code_len, u32 rv2p_proc)
3532 {
3533 	int i;
3534 	u32 val;
3535 
3536 	DBENTER(BCE_VERBOSE_RESET);
3537 
3538 	/* Set the page size used by RV2P. */
3539 	if (rv2p_proc == RV2P_PROC2) {
3540 		BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
3541 	}
3542 
3543 	for (i = 0; i < rv2p_code_len; i += 8) {
3544 		REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
3545 		rv2p_code++;
3546 		REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
3547 		rv2p_code++;
3548 
3549 		if (rv2p_proc == RV2P_PROC1) {
3550 			val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
3551 			REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
3552 		}
3553 		else {
3554 			val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
3555 			REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
3556 		}
3557 	}
3558 
3559 	/* Reset the processor, un-stall is done later. */
3560 	if (rv2p_proc == RV2P_PROC1) {
3561 		REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
3562 	}
3563 	else {
3564 		REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
3565 	}
3566 
3567 	DBEXIT(BCE_VERBOSE_RESET);
3568 }
3569 
3570 
3571 /****************************************************************************/
3572 /* Load RISC processor firmware.                                            */
3573 /*                                                                          */
3574 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
3575 /* associated with a particular processor.                                  */
3576 /*                                                                          */
3577 /* Returns:                                                                 */
3578 /*   Nothing.                                                               */
3579 /****************************************************************************/
3580 static void
3581 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
3582 	struct fw_info *fw)
3583 {
3584 	u32 offset;
3585 	u32 val;
3586 
3587 	DBENTER(BCE_VERBOSE_RESET);
3588 
3589 	/* Halt the CPU. */
3590 	val = REG_RD_IND(sc, cpu_reg->mode);
3591 	val |= cpu_reg->mode_value_halt;
3592 	REG_WR_IND(sc, cpu_reg->mode, val);
3593 	REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3594 
3595 	/* Load the Text area. */
3596 	offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3597 	if (fw->text) {
3598 		int j;
3599 
3600 		for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3601 			REG_WR_IND(sc, offset, fw->text[j]);
3602 	        }
3603 	}
3604 
3605 	/* Load the Data area. */
3606 	offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3607 	if (fw->data) {
3608 		int j;
3609 
3610 		for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3611 			REG_WR_IND(sc, offset, fw->data[j]);
3612 		}
3613 	}
3614 
3615 	/* Load the SBSS area. */
3616 	offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3617 	if (fw->sbss) {
3618 		int j;
3619 
3620 		for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3621 			REG_WR_IND(sc, offset, fw->sbss[j]);
3622 		}
3623 	}
3624 
3625 	/* Load the BSS area. */
3626 	offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3627 	if (fw->bss) {
3628 		int j;
3629 
3630 		for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3631 			REG_WR_IND(sc, offset, fw->bss[j]);
3632 		}
3633 	}
3634 
3635 	/* Load the Read-Only area. */
3636 	offset = cpu_reg->spad_base +
3637 		(fw->rodata_addr - cpu_reg->mips_view_base);
3638 	if (fw->rodata) {
3639 		int j;
3640 
3641 		for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3642 			REG_WR_IND(sc, offset, fw->rodata[j]);
3643 		}
3644 	}
3645 
3646 	/* Clear the pre-fetch instruction. */
3647 	REG_WR_IND(sc, cpu_reg->inst, 0);
3648 	REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
3649 
3650 	/* Start the CPU. */
3651 	val = REG_RD_IND(sc, cpu_reg->mode);
3652 	val &= ~cpu_reg->mode_value_halt;
3653 	REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3654 	REG_WR_IND(sc, cpu_reg->mode, val);
3655 
3656 	DBEXIT(BCE_VERBOSE_RESET);
3657 }
3658 
3659 
3660 /****************************************************************************/
3661 /* Initialize the RX CPU.                                                   */
3662 /*                                                                          */
3663 /* Returns:                                                                 */
3664 /*   Nothing.                                                               */
3665 /****************************************************************************/
3666 static void
3667 bce_init_rxp_cpu(struct bce_softc *sc)
3668 {
3669 	struct cpu_reg cpu_reg;
3670 	struct fw_info fw;
3671 
3672 	DBENTER(BCE_VERBOSE_RESET);
3673 
3674 	cpu_reg.mode = BCE_RXP_CPU_MODE;
3675 	cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
3676 	cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
3677 	cpu_reg.state = BCE_RXP_CPU_STATE;
3678 	cpu_reg.state_value_clear = 0xffffff;
3679 	cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
3680 	cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
3681 	cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
3682 	cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
3683 	cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
3684 	cpu_reg.spad_base = BCE_RXP_SCRATCH;
3685 	cpu_reg.mips_view_base = 0x8000000;
3686 
3687 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3688 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3689  		fw.ver_major = bce_RXP_b09FwReleaseMajor;
3690 		fw.ver_minor = bce_RXP_b09FwReleaseMinor;
3691 		fw.ver_fix = bce_RXP_b09FwReleaseFix;
3692 		fw.start_addr = bce_RXP_b09FwStartAddr;
3693 
3694 		fw.text_addr = bce_RXP_b09FwTextAddr;
3695 		fw.text_len = bce_RXP_b09FwTextLen;
3696 		fw.text_index = 0;
3697 		fw.text = bce_RXP_b09FwText;
3698 
3699 		fw.data_addr = bce_RXP_b09FwDataAddr;
3700 		fw.data_len = bce_RXP_b09FwDataLen;
3701 		fw.data_index = 0;
3702 		fw.data = bce_RXP_b09FwData;
3703 
3704 		fw.sbss_addr = bce_RXP_b09FwSbssAddr;
3705 		fw.sbss_len = bce_RXP_b09FwSbssLen;
3706 		fw.sbss_index = 0;
3707 		fw.sbss = bce_RXP_b09FwSbss;
3708 
3709 		fw.bss_addr = bce_RXP_b09FwBssAddr;
3710 		fw.bss_len = bce_RXP_b09FwBssLen;
3711 		fw.bss_index = 0;
3712 		fw.bss = bce_RXP_b09FwBss;
3713 
3714 		fw.rodata_addr = bce_RXP_b09FwRodataAddr;
3715 		fw.rodata_len = bce_RXP_b09FwRodataLen;
3716 		fw.rodata_index = 0;
3717 		fw.rodata = bce_RXP_b09FwRodata;
3718 	} else {
3719 		fw.ver_major = bce_RXP_b06FwReleaseMajor;
3720 		fw.ver_minor = bce_RXP_b06FwReleaseMinor;
3721 		fw.ver_fix = bce_RXP_b06FwReleaseFix;
3722 		fw.start_addr = bce_RXP_b06FwStartAddr;
3723 
3724 		fw.text_addr = bce_RXP_b06FwTextAddr;
3725 		fw.text_len = bce_RXP_b06FwTextLen;
3726 		fw.text_index = 0;
3727 		fw.text = bce_RXP_b06FwText;
3728 
3729 		fw.data_addr = bce_RXP_b06FwDataAddr;
3730 		fw.data_len = bce_RXP_b06FwDataLen;
3731 		fw.data_index = 0;
3732 		fw.data = bce_RXP_b06FwData;
3733 
3734 		fw.sbss_addr = bce_RXP_b06FwSbssAddr;
3735 		fw.sbss_len = bce_RXP_b06FwSbssLen;
3736 		fw.sbss_index = 0;
3737 		fw.sbss = bce_RXP_b06FwSbss;
3738 
3739 		fw.bss_addr = bce_RXP_b06FwBssAddr;
3740 		fw.bss_len = bce_RXP_b06FwBssLen;
3741 		fw.bss_index = 0;
3742 		fw.bss = bce_RXP_b06FwBss;
3743 
3744 		fw.rodata_addr = bce_RXP_b06FwRodataAddr;
3745 		fw.rodata_len = bce_RXP_b06FwRodataLen;
3746 		fw.rodata_index = 0;
3747 		fw.rodata = bce_RXP_b06FwRodata;
3748 	}
3749 
3750 	DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
3751 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
3752 
3753 	DBEXIT(BCE_VERBOSE_RESET);
3754 }
3755 
3756 
3757 /****************************************************************************/
3758 /* Initialize the TX CPU.                                                   */
3759 /*                                                                          */
3760 /* Returns:                                                                 */
3761 /*   Nothing.                                                               */
3762 /****************************************************************************/
3763 static void
3764 bce_init_txp_cpu(struct bce_softc *sc)
3765 {
3766 	struct cpu_reg cpu_reg;
3767 	struct fw_info fw;
3768 
3769 	DBENTER(BCE_VERBOSE_RESET);
3770 
3771 	cpu_reg.mode = BCE_TXP_CPU_MODE;
3772 	cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
3773 	cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
3774 	cpu_reg.state = BCE_TXP_CPU_STATE;
3775 	cpu_reg.state_value_clear = 0xffffff;
3776 	cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
3777 	cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
3778 	cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
3779 	cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
3780 	cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
3781 	cpu_reg.spad_base = BCE_TXP_SCRATCH;
3782 	cpu_reg.mips_view_base = 0x8000000;
3783 
3784 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3785 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3786 		fw.ver_major = bce_TXP_b09FwReleaseMajor;
3787 		fw.ver_minor = bce_TXP_b09FwReleaseMinor;
3788 		fw.ver_fix = bce_TXP_b09FwReleaseFix;
3789 		fw.start_addr = bce_TXP_b09FwStartAddr;
3790 
3791 		fw.text_addr = bce_TXP_b09FwTextAddr;
3792 		fw.text_len = bce_TXP_b09FwTextLen;
3793 		fw.text_index = 0;
3794 		fw.text = bce_TXP_b09FwText;
3795 
3796 		fw.data_addr = bce_TXP_b09FwDataAddr;
3797 		fw.data_len = bce_TXP_b09FwDataLen;
3798 		fw.data_index = 0;
3799 		fw.data = bce_TXP_b09FwData;
3800 
3801 		fw.sbss_addr = bce_TXP_b09FwSbssAddr;
3802 		fw.sbss_len = bce_TXP_b09FwSbssLen;
3803 		fw.sbss_index = 0;
3804 		fw.sbss = bce_TXP_b09FwSbss;
3805 
3806 		fw.bss_addr = bce_TXP_b09FwBssAddr;
3807 		fw.bss_len = bce_TXP_b09FwBssLen;
3808 		fw.bss_index = 0;
3809 		fw.bss = bce_TXP_b09FwBss;
3810 
3811 		fw.rodata_addr = bce_TXP_b09FwRodataAddr;
3812 		fw.rodata_len = bce_TXP_b09FwRodataLen;
3813 		fw.rodata_index = 0;
3814 		fw.rodata = bce_TXP_b09FwRodata;
3815 	} else {
3816 		fw.ver_major = bce_TXP_b06FwReleaseMajor;
3817 		fw.ver_minor = bce_TXP_b06FwReleaseMinor;
3818 		fw.ver_fix = bce_TXP_b06FwReleaseFix;
3819 		fw.start_addr = bce_TXP_b06FwStartAddr;
3820 
3821 		fw.text_addr = bce_TXP_b06FwTextAddr;
3822 		fw.text_len = bce_TXP_b06FwTextLen;
3823 		fw.text_index = 0;
3824 		fw.text = bce_TXP_b06FwText;
3825 
3826 		fw.data_addr = bce_TXP_b06FwDataAddr;
3827 		fw.data_len = bce_TXP_b06FwDataLen;
3828 		fw.data_index = 0;
3829 		fw.data = bce_TXP_b06FwData;
3830 
3831 		fw.sbss_addr = bce_TXP_b06FwSbssAddr;
3832 		fw.sbss_len = bce_TXP_b06FwSbssLen;
3833 		fw.sbss_index = 0;
3834 		fw.sbss = bce_TXP_b06FwSbss;
3835 
3836 		fw.bss_addr = bce_TXP_b06FwBssAddr;
3837 		fw.bss_len = bce_TXP_b06FwBssLen;
3838 		fw.bss_index = 0;
3839 		fw.bss = bce_TXP_b06FwBss;
3840 
3841 		fw.rodata_addr = bce_TXP_b06FwRodataAddr;
3842 		fw.rodata_len = bce_TXP_b06FwRodataLen;
3843 		fw.rodata_index = 0;
3844 		fw.rodata = bce_TXP_b06FwRodata;
3845 	}
3846 
3847 	DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
3848 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
3849 
3850 	DBEXIT(BCE_VERBOSE_RESET);
3851 }
3852 
3853 
3854 /****************************************************************************/
3855 /* Initialize the TPAT CPU.                                                 */
3856 /*                                                                          */
3857 /* Returns:                                                                 */
3858 /*   Nothing.                                                               */
3859 /****************************************************************************/
3860 static void
3861 bce_init_tpat_cpu(struct bce_softc *sc)
3862 {
3863 	struct cpu_reg cpu_reg;
3864 	struct fw_info fw;
3865 
3866 	DBENTER(BCE_VERBOSE_RESET);
3867 
3868 	cpu_reg.mode = BCE_TPAT_CPU_MODE;
3869 	cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
3870 	cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
3871 	cpu_reg.state = BCE_TPAT_CPU_STATE;
3872 	cpu_reg.state_value_clear = 0xffffff;
3873 	cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
3874 	cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
3875 	cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
3876 	cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
3877 	cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
3878 	cpu_reg.spad_base = BCE_TPAT_SCRATCH;
3879 	cpu_reg.mips_view_base = 0x8000000;
3880 
3881 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3882 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3883 		fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3884 		fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3885 		fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3886 		fw.start_addr = bce_TPAT_b09FwStartAddr;
3887 
3888 		fw.text_addr = bce_TPAT_b09FwTextAddr;
3889 		fw.text_len = bce_TPAT_b09FwTextLen;
3890 		fw.text_index = 0;
3891 		fw.text = bce_TPAT_b09FwText;
3892 
3893 		fw.data_addr = bce_TPAT_b09FwDataAddr;
3894 		fw.data_len = bce_TPAT_b09FwDataLen;
3895 		fw.data_index = 0;
3896 		fw.data = bce_TPAT_b09FwData;
3897 
3898 		fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3899 		fw.sbss_len = bce_TPAT_b09FwSbssLen;
3900 		fw.sbss_index = 0;
3901 		fw.sbss = bce_TPAT_b09FwSbss;
3902 
3903 		fw.bss_addr = bce_TPAT_b09FwBssAddr;
3904 		fw.bss_len = bce_TPAT_b09FwBssLen;
3905 		fw.bss_index = 0;
3906 		fw.bss = bce_TPAT_b09FwBss;
3907 
3908 		fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3909 		fw.rodata_len = bce_TPAT_b09FwRodataLen;
3910 		fw.rodata_index = 0;
3911 		fw.rodata = bce_TPAT_b09FwRodata;
3912 	} else {
3913 		fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3914 		fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3915 		fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3916 		fw.start_addr = bce_TPAT_b06FwStartAddr;
3917 
3918 		fw.text_addr = bce_TPAT_b06FwTextAddr;
3919 		fw.text_len = bce_TPAT_b06FwTextLen;
3920 		fw.text_index = 0;
3921 		fw.text = bce_TPAT_b06FwText;
3922 
3923 		fw.data_addr = bce_TPAT_b06FwDataAddr;
3924 		fw.data_len = bce_TPAT_b06FwDataLen;
3925 		fw.data_index = 0;
3926 		fw.data = bce_TPAT_b06FwData;
3927 
3928 		fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3929 		fw.sbss_len = bce_TPAT_b06FwSbssLen;
3930 		fw.sbss_index = 0;
3931 		fw.sbss = bce_TPAT_b06FwSbss;
3932 
3933 		fw.bss_addr = bce_TPAT_b06FwBssAddr;
3934 		fw.bss_len = bce_TPAT_b06FwBssLen;
3935 		fw.bss_index = 0;
3936 		fw.bss = bce_TPAT_b06FwBss;
3937 
3938 		fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3939 		fw.rodata_len = bce_TPAT_b06FwRodataLen;
3940 		fw.rodata_index = 0;
3941 		fw.rodata = bce_TPAT_b06FwRodata;
3942 	}
3943 
3944 	DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3945 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
3946 
3947 	DBEXIT(BCE_VERBOSE_RESET);
3948 }
3949 
3950 
3951 /****************************************************************************/
3952 /* Initialize the CP CPU.                                                   */
3953 /*                                                                          */
3954 /* Returns:                                                                 */
3955 /*   Nothing.                                                               */
3956 /****************************************************************************/
3957 static void
3958 bce_init_cp_cpu(struct bce_softc *sc)
3959 {
3960 	struct cpu_reg cpu_reg;
3961 	struct fw_info fw;
3962 
3963 	DBENTER(BCE_VERBOSE_RESET);
3964 
3965 	cpu_reg.mode = BCE_CP_CPU_MODE;
3966 	cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3967 	cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3968 	cpu_reg.state = BCE_CP_CPU_STATE;
3969 	cpu_reg.state_value_clear = 0xffffff;
3970 	cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3971 	cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3972 	cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3973 	cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3974 	cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3975 	cpu_reg.spad_base = BCE_CP_SCRATCH;
3976 	cpu_reg.mips_view_base = 0x8000000;
3977 
3978 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3979 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3980 		fw.ver_major = bce_CP_b09FwReleaseMajor;
3981 		fw.ver_minor = bce_CP_b09FwReleaseMinor;
3982 		fw.ver_fix = bce_CP_b09FwReleaseFix;
3983 		fw.start_addr = bce_CP_b09FwStartAddr;
3984 
3985 		fw.text_addr = bce_CP_b09FwTextAddr;
3986 		fw.text_len = bce_CP_b09FwTextLen;
3987 		fw.text_index = 0;
3988 		fw.text = bce_CP_b09FwText;
3989 
3990 		fw.data_addr = bce_CP_b09FwDataAddr;
3991 		fw.data_len = bce_CP_b09FwDataLen;
3992 		fw.data_index = 0;
3993 		fw.data = bce_CP_b09FwData;
3994 
3995 		fw.sbss_addr = bce_CP_b09FwSbssAddr;
3996 		fw.sbss_len = bce_CP_b09FwSbssLen;
3997 		fw.sbss_index = 0;
3998 		fw.sbss = bce_CP_b09FwSbss;
3999 
4000 		fw.bss_addr = bce_CP_b09FwBssAddr;
4001 		fw.bss_len = bce_CP_b09FwBssLen;
4002 		fw.bss_index = 0;
4003 		fw.bss = bce_CP_b09FwBss;
4004 
4005 		fw.rodata_addr = bce_CP_b09FwRodataAddr;
4006 		fw.rodata_len = bce_CP_b09FwRodataLen;
4007 		fw.rodata_index = 0;
4008 		fw.rodata = bce_CP_b09FwRodata;
4009 	} else {
4010 		fw.ver_major = bce_CP_b06FwReleaseMajor;
4011 		fw.ver_minor = bce_CP_b06FwReleaseMinor;
4012 		fw.ver_fix = bce_CP_b06FwReleaseFix;
4013 		fw.start_addr = bce_CP_b06FwStartAddr;
4014 
4015 		fw.text_addr = bce_CP_b06FwTextAddr;
4016 		fw.text_len = bce_CP_b06FwTextLen;
4017 		fw.text_index = 0;
4018 		fw.text = bce_CP_b06FwText;
4019 
4020 		fw.data_addr = bce_CP_b06FwDataAddr;
4021 		fw.data_len = bce_CP_b06FwDataLen;
4022 		fw.data_index = 0;
4023 		fw.data = bce_CP_b06FwData;
4024 
4025 		fw.sbss_addr = bce_CP_b06FwSbssAddr;
4026 		fw.sbss_len = bce_CP_b06FwSbssLen;
4027 		fw.sbss_index = 0;
4028 		fw.sbss = bce_CP_b06FwSbss;
4029 
4030 		fw.bss_addr = bce_CP_b06FwBssAddr;
4031 		fw.bss_len = bce_CP_b06FwBssLen;
4032 		fw.bss_index = 0;
4033 		fw.bss = bce_CP_b06FwBss;
4034 
4035 		fw.rodata_addr = bce_CP_b06FwRodataAddr;
4036 		fw.rodata_len = bce_CP_b06FwRodataLen;
4037 		fw.rodata_index = 0;
4038 		fw.rodata = bce_CP_b06FwRodata;
4039 	}
4040 
4041 	DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4042 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
4043 
4044 	DBEXIT(BCE_VERBOSE_RESET);
4045 }
4046 
4047 
4048 /****************************************************************************/
4049 /* Initialize the COM CPU.                                                 */
4050 /*                                                                          */
4051 /* Returns:                                                                 */
4052 /*   Nothing.                                                               */
4053 /****************************************************************************/
4054 static void
4055 bce_init_com_cpu(struct bce_softc *sc)
4056 {
4057 	struct cpu_reg cpu_reg;
4058 	struct fw_info fw;
4059 
4060 	DBENTER(BCE_VERBOSE_RESET);
4061 
4062 	cpu_reg.mode = BCE_COM_CPU_MODE;
4063 	cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4064 	cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4065 	cpu_reg.state = BCE_COM_CPU_STATE;
4066 	cpu_reg.state_value_clear = 0xffffff;
4067 	cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4068 	cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4069 	cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4070 	cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4071 	cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4072 	cpu_reg.spad_base = BCE_COM_SCRATCH;
4073 	cpu_reg.mips_view_base = 0x8000000;
4074 
4075 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4076 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4077 		fw.ver_major = bce_COM_b09FwReleaseMajor;
4078 		fw.ver_minor = bce_COM_b09FwReleaseMinor;
4079 		fw.ver_fix = bce_COM_b09FwReleaseFix;
4080 		fw.start_addr = bce_COM_b09FwStartAddr;
4081 
4082 		fw.text_addr = bce_COM_b09FwTextAddr;
4083 		fw.text_len = bce_COM_b09FwTextLen;
4084 		fw.text_index = 0;
4085 		fw.text = bce_COM_b09FwText;
4086 
4087 		fw.data_addr = bce_COM_b09FwDataAddr;
4088 		fw.data_len = bce_COM_b09FwDataLen;
4089 		fw.data_index = 0;
4090 		fw.data = bce_COM_b09FwData;
4091 
4092 		fw.sbss_addr = bce_COM_b09FwSbssAddr;
4093 		fw.sbss_len = bce_COM_b09FwSbssLen;
4094 		fw.sbss_index = 0;
4095 		fw.sbss = bce_COM_b09FwSbss;
4096 
4097 		fw.bss_addr = bce_COM_b09FwBssAddr;
4098 		fw.bss_len = bce_COM_b09FwBssLen;
4099 		fw.bss_index = 0;
4100 		fw.bss = bce_COM_b09FwBss;
4101 
4102 		fw.rodata_addr = bce_COM_b09FwRodataAddr;
4103 		fw.rodata_len = bce_COM_b09FwRodataLen;
4104 		fw.rodata_index = 0;
4105 		fw.rodata = bce_COM_b09FwRodata;
4106 	} else {
4107 		fw.ver_major = bce_COM_b06FwReleaseMajor;
4108 		fw.ver_minor = bce_COM_b06FwReleaseMinor;
4109 		fw.ver_fix = bce_COM_b06FwReleaseFix;
4110 		fw.start_addr = bce_COM_b06FwStartAddr;
4111 
4112 		fw.text_addr = bce_COM_b06FwTextAddr;
4113 		fw.text_len = bce_COM_b06FwTextLen;
4114 		fw.text_index = 0;
4115 		fw.text = bce_COM_b06FwText;
4116 
4117 		fw.data_addr = bce_COM_b06FwDataAddr;
4118 		fw.data_len = bce_COM_b06FwDataLen;
4119 		fw.data_index = 0;
4120 		fw.data = bce_COM_b06FwData;
4121 
4122 		fw.sbss_addr = bce_COM_b06FwSbssAddr;
4123 		fw.sbss_len = bce_COM_b06FwSbssLen;
4124 		fw.sbss_index = 0;
4125 		fw.sbss = bce_COM_b06FwSbss;
4126 
4127 		fw.bss_addr = bce_COM_b06FwBssAddr;
4128 		fw.bss_len = bce_COM_b06FwBssLen;
4129 		fw.bss_index = 0;
4130 		fw.bss = bce_COM_b06FwBss;
4131 
4132 		fw.rodata_addr = bce_COM_b06FwRodataAddr;
4133 		fw.rodata_len = bce_COM_b06FwRodataLen;
4134 		fw.rodata_index = 0;
4135 		fw.rodata = bce_COM_b06FwRodata;
4136 	}
4137 
4138 	DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4139 	bce_load_cpu_fw(sc, &cpu_reg, &fw);
4140 
4141 	DBEXIT(BCE_VERBOSE_RESET);
4142 }
4143 
4144 
4145 /****************************************************************************/
4146 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4147 /*                                                                          */
4148 /* Loads the firmware for each CPU and starts the CPU.                      */
4149 /*                                                                          */
4150 /* Returns:                                                                 */
4151 /*   Nothing.                                                               */
4152 /****************************************************************************/
4153 static void
4154 bce_init_cpus(struct bce_softc *sc)
4155 {
4156 	DBENTER(BCE_VERBOSE_RESET);
4157 
4158 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4159 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4160 		bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, sizeof(bce_xi_rv2p_proc1),
4161 			RV2P_PROC1);
4162 		bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, sizeof(bce_xi_rv2p_proc2),
4163 			RV2P_PROC2);
4164 	} else {
4165 		bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1),
4166 			RV2P_PROC1);
4167 		bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2),
4168 			RV2P_PROC2);
4169 	}
4170 
4171 	bce_init_rxp_cpu(sc);
4172 	bce_init_txp_cpu(sc);
4173 	bce_init_tpat_cpu(sc);
4174 	bce_init_com_cpu(sc);
4175 	bce_init_cp_cpu(sc);
4176 
4177 	DBEXIT(BCE_VERBOSE_RESET);
4178 }
4179 
4180 
4181 /****************************************************************************/
4182 /* Initialize context memory.                                               */
4183 /*                                                                          */
4184 /* Clears the memory associated with each Context ID (CID).                 */
4185 /*                                                                          */
4186 /* Returns:                                                                 */
4187 /*   Nothing.                                                               */
4188 /****************************************************************************/
4189 static void
4190 bce_init_ctx(struct bce_softc *sc)
4191 {
4192 
4193 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4194 
4195 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4196 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4197 		/* DRC: Replace this constant value with a #define. */
4198 		int i, retry_cnt = 10;
4199 		u32 val;
4200 
4201 		DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4202 
4203 		/*
4204 		 * BCM5709 context memory may be cached
4205 		 * in host memory so prepare the host memory
4206 		 * for access.
4207 		 */
4208 		val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4209 		val |= (BCM_PAGE_BITS - 8) << 16;
4210 		REG_WR(sc, BCE_CTX_COMMAND, val);
4211 
4212 		/* Wait for mem init command to complete. */
4213 		for (i = 0; i < retry_cnt; i++) {
4214 			val = REG_RD(sc, BCE_CTX_COMMAND);
4215 			if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4216 				break;
4217 			DELAY(2);
4218 		}
4219 
4220 		/* ToDo: Consider returning an error here. */
4221 		DBRUNIF((val & BCE_CTX_COMMAND_MEM_INIT),
4222 			BCE_PRINTF("%s(): Context memory initialization failed!\n",
4223 			__FUNCTION__));
4224 
4225 		for (i = 0; i < sc->ctx_pages; i++) {
4226 			int j;
4227 
4228 			/* Set the physical address of the context memory cache. */
4229 			REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4230 				BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4231 				BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4232 			REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4233 				BCE_ADDR_HI(sc->ctx_paddr[i]));
4234 			REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4235 				BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4236 
4237 			/* Verify that the context memory write was successful. */
4238 			for (j = 0; j < retry_cnt; j++) {
4239 				val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4240 				if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4241 					break;
4242 				DELAY(5);
4243 			}
4244 
4245 			/* ToDo: Consider returning an error here. */
4246 			DBRUNIF((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ),
4247 				BCE_PRINTF("%s(): Failed to initialize context page %d!\n",
4248 				__FUNCTION__, i));
4249 		}
4250 	} else {
4251 		u32 vcid_addr, offset;
4252 
4253 		DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4254 
4255 		/*
4256 		 * For the 5706/5708, context memory is local to
4257 		 * the controller, so initialize the controller
4258 		 * context memory.
4259 		 */
4260 
4261 		vcid_addr = GET_CID_ADDR(96);
4262 		while (vcid_addr) {
4263 
4264 			vcid_addr -= PHY_CTX_SIZE;
4265 
4266 			REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4267 			REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4268 
4269             for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4270                 CTX_WR(sc, 0x00, offset, 0);
4271             }
4272 
4273 			REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4274 			REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4275 		}
4276 
4277 	}
4278 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4279 }
4280 
4281 
4282 /****************************************************************************/
4283 /* Fetch the permanent MAC address of the controller.                       */
4284 /*                                                                          */
4285 /* Returns:                                                                 */
4286 /*   Nothing.                                                               */
4287 /****************************************************************************/
4288 static void
4289 bce_get_mac_addr(struct bce_softc *sc)
4290 {
4291 	u32 mac_lo = 0, mac_hi = 0;
4292 
4293 	DBENTER(BCE_VERBOSE_RESET);
4294 	/*
4295 	 * The NetXtreme II bootcode populates various NIC
4296 	 * power-on and runtime configuration items in a
4297 	 * shared memory area.  The factory configured MAC
4298 	 * address is available from both NVRAM and the
4299 	 * shared memory area so we'll read the value from
4300 	 * shared memory for speed.
4301 	 */
4302 
4303 	mac_hi = REG_RD_IND(sc, sc->bce_shmem_base +
4304 		BCE_PORT_HW_CFG_MAC_UPPER);
4305 	mac_lo = REG_RD_IND(sc, sc->bce_shmem_base +
4306 		BCE_PORT_HW_CFG_MAC_LOWER);
4307 
4308 	if ((mac_lo == 0) && (mac_hi == 0)) {
4309 		BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4310 			__FILE__, __LINE__);
4311 	} else {
4312 		sc->eaddr[0] = (u_char)(mac_hi >> 8);
4313 		sc->eaddr[1] = (u_char)(mac_hi >> 0);
4314 		sc->eaddr[2] = (u_char)(mac_lo >> 24);
4315 		sc->eaddr[3] = (u_char)(mac_lo >> 16);
4316 		sc->eaddr[4] = (u_char)(mac_lo >> 8);
4317 		sc->eaddr[5] = (u_char)(mac_lo >> 0);
4318 	}
4319 
4320 	DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
4321 	DBEXIT(BCE_VERBOSE_RESET);
4322 }
4323 
4324 
4325 /****************************************************************************/
4326 /* Program the MAC address.                                                 */
4327 /*                                                                          */
4328 /* Returns:                                                                 */
4329 /*   Nothing.                                                               */
4330 /****************************************************************************/
4331 static void
4332 bce_set_mac_addr(struct bce_softc *sc)
4333 {
4334 	u32 val;
4335 	u8 *mac_addr = sc->eaddr;
4336 
4337 	/* ToDo: Add support for setting multiple MAC addresses. */
4338 
4339 	DBENTER(BCE_VERBOSE_RESET);
4340 	DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = %6D\n", sc->eaddr, ":");
4341 
4342 	val = (mac_addr[0] << 8) | mac_addr[1];
4343 
4344 	REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4345 
4346 	val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4347 		(mac_addr[4] << 8) | mac_addr[5];
4348 
4349 	REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4350 
4351 	DBEXIT(BCE_VERBOSE_RESET);
4352 }
4353 
4354 
4355 /****************************************************************************/
4356 /* Stop the controller.                                                     */
4357 /*                                                                          */
4358 /* Returns:                                                                 */
4359 /*   Nothing.                                                               */
4360 /****************************************************************************/
4361 static void
4362 bce_stop(struct bce_softc *sc)
4363 {
4364 	struct ifnet *ifp;
4365 	struct ifmedia_entry *ifm;
4366 	struct mii_data *mii = NULL;
4367 	int mtmp, itmp;
4368 
4369 	DBENTER(BCE_VERBOSE_RESET);
4370 
4371 	BCE_LOCK_ASSERT(sc);
4372 
4373 	ifp = sc->bce_ifp;
4374 
4375 	mii = device_get_softc(sc->bce_miibus);
4376 
4377 	callout_stop(&sc->bce_tick_callout);
4378 
4379 	/* Disable the transmit/receive blocks. */
4380 	REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4381 	REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4382 	DELAY(20);
4383 
4384 	bce_disable_intr(sc);
4385 
4386 	/* Free RX buffers. */
4387 #ifdef BCE_USE_SPLIT_HEADER
4388 	bce_free_pg_chain(sc);
4389 #endif
4390 	bce_free_rx_chain(sc);
4391 
4392 	/* Free TX buffers. */
4393 	bce_free_tx_chain(sc);
4394 
4395 	/*
4396 	 * Isolate/power down the PHY, but leave the media selection
4397 	 * unchanged so that things will be put back to normal when
4398 	 * we bring the interface back up.
4399 	 */
4400 
4401 	itmp = ifp->if_flags;
4402 	ifp->if_flags |= IFF_UP;
4403 
4404 	/* If we are called from bce_detach(), mii is already NULL. */
4405 	if (mii != NULL) {
4406 		ifm = mii->mii_media.ifm_cur;
4407 		mtmp = ifm->ifm_media;
4408 		ifm->ifm_media = IFM_ETHER | IFM_NONE;
4409 		mii_mediachg(mii);
4410 		ifm->ifm_media = mtmp;
4411 	}
4412 
4413 	ifp->if_flags = itmp;
4414 	sc->watchdog_timer = 0;
4415 
4416 	sc->bce_link = 0;
4417 
4418 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4419 
4420 	DBEXIT(BCE_VERBOSE_RESET);
4421 }
4422 
4423 
4424 static int
4425 bce_reset(struct bce_softc *sc, u32 reset_code)
4426 {
4427 	u32 val;
4428 	int i, rc = 0;
4429 
4430 	DBENTER(BCE_VERBOSE_RESET);
4431 
4432 	DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4433 		__FUNCTION__, reset_code);
4434 
4435 	/* Wait for pending PCI transactions to complete. */
4436 	REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4437 	       BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4438 	       BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4439 	       BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4440 	       BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4441 	val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4442 	DELAY(5);
4443 
4444 	/* Disable DMA */
4445 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4446 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4447 		val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4448 		val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4449 		REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4450 	}
4451 
4452 	/* Assume bootcode is running. */
4453 	sc->bce_fw_timed_out = 0;
4454 
4455 	/* Give the firmware a chance to prepare for the reset. */
4456 	rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
4457 	if (rc)
4458 		goto bce_reset_exit;
4459 
4460 	/* Set a firmware reminder that this is a soft reset. */
4461 	REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
4462 		   BCE_DRV_RESET_SIGNATURE_MAGIC);
4463 
4464 	/* Dummy read to force the chip to complete all current transactions. */
4465 	val = REG_RD(sc, BCE_MISC_ID);
4466 
4467 	/* Chip reset. */
4468 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4469 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4470 		REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
4471 		REG_RD(sc, BCE_MISC_COMMAND);
4472 		DELAY(5);
4473 
4474 		val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4475 		      BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4476 
4477 		pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
4478 	} else {
4479 		val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4480 			BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4481 			BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4482 		REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
4483 
4484 		/* Allow up to 30us for reset to complete. */
4485 		for (i = 0; i < 10; i++) {
4486 			val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
4487 			if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4488 				BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
4489 				break;
4490 			}
4491 			DELAY(10);
4492 		}
4493 
4494 		/* Check that reset completed successfully. */
4495 		if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4496 			BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4497 			BCE_PRINTF("%s(%d): Reset failed!\n",
4498 				__FILE__, __LINE__);
4499 			rc = EBUSY;
4500 			goto bce_reset_exit;
4501 		}
4502 	}
4503 
4504 	/* Make sure byte swapping is properly configured. */
4505 	val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
4506 	if (val != 0x01020304) {
4507 		BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
4508 			__FILE__, __LINE__);
4509 		rc = ENODEV;
4510 		goto bce_reset_exit;
4511 	}
4512 
4513 	/* Just completed a reset, assume that firmware is running again. */
4514 	sc->bce_fw_timed_out = 0;
4515 
4516 	/* Wait for the firmware to finish its initialization. */
4517 	rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
4518 	if (rc)
4519 		BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n",
4520 			__FILE__, __LINE__);
4521 
4522 bce_reset_exit:
4523 	DBEXIT(BCE_VERBOSE_RESET);
4524 	return (rc);
4525 }
4526 
4527 
4528 static int
4529 bce_chipinit(struct bce_softc *sc)
4530 {
4531 	u32 val;
4532 	int rc = 0;
4533 
4534 	DBENTER(BCE_VERBOSE_RESET);
4535 
4536 	bce_disable_intr(sc);
4537 
4538 	/*
4539 	 * Initialize DMA byte/word swapping, configure the number of DMA
4540 	 * channels and PCI clock compensation delay.
4541 	 */
4542 	val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
4543 	      BCE_DMA_CONFIG_DATA_WORD_SWAP |
4544 #if BYTE_ORDER == BIG_ENDIAN
4545 	      BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
4546 #endif
4547 	      BCE_DMA_CONFIG_CNTL_WORD_SWAP |
4548 	      DMA_READ_CHANS << 12 |
4549 	      DMA_WRITE_CHANS << 16;
4550 
4551 	val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
4552 
4553 	if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
4554 		val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
4555 
4556 	/*
4557 	 * This setting resolves a problem observed on certain Intel PCI
4558 	 * chipsets that cannot handle multiple outstanding DMA operations.
4559 	 * See errata E9_5706A1_65.
4560 	 */
4561 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
4562 	    (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
4563 	    !(sc->bce_flags & BCE_PCIX_FLAG))
4564 		val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
4565 
4566 	REG_WR(sc, BCE_DMA_CONFIG, val);
4567 
4568 	/* Enable the RX_V2P and Context state machines before access. */
4569 	REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4570 	       BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4571 	       BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4572 	       BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4573 
4574 	/* Initialize context mapping and zero out the quick contexts. */
4575 	bce_init_ctx(sc);
4576 
4577 	/* Initialize the on-boards CPUs */
4578 	bce_init_cpus(sc);
4579 
4580 	/* Prepare NVRAM for access. */
4581 	if (bce_init_nvram(sc)) {
4582 		rc = ENODEV;
4583 		goto bce_chipinit_exit;
4584 	}
4585 
4586 	/* Set the kernel bypass block size */
4587 	val = REG_RD(sc, BCE_MQ_CONFIG);
4588 	val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4589 	val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4590 
4591 	/* Enable bins used on the 5709. */
4592 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4593 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4594 		val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
4595 		if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
4596 			val |= BCE_MQ_CONFIG_HALT_DIS;
4597 	}
4598 
4599 	REG_WR(sc, BCE_MQ_CONFIG, val);
4600 
4601 	val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4602 	REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
4603 	REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
4604 
4605 	/* Set the page size and clear the RV2P processor stall bits. */
4606 	val = (BCM_PAGE_BITS - 8) << 24;
4607 	REG_WR(sc, BCE_RV2P_CONFIG, val);
4608 
4609 	/* Configure page size. */
4610 	val = REG_RD(sc, BCE_TBDR_CONFIG);
4611 	val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
4612 	val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4613 	REG_WR(sc, BCE_TBDR_CONFIG, val);
4614 
4615 	/* Set the perfect match control register to default. */
4616 	REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
4617 
4618 bce_chipinit_exit:
4619 	DBEXIT(BCE_VERBOSE_RESET);
4620 
4621 	return(rc);
4622 }
4623 
4624 
4625 /****************************************************************************/
4626 /* Initialize the controller in preparation to send/receive traffic.        */
4627 /*                                                                          */
4628 /* Returns:                                                                 */
4629 /*   0 for success, positive value for failure.                             */
4630 /****************************************************************************/
4631 static int
4632 bce_blockinit(struct bce_softc *sc)
4633 {
4634 	u32 reg, val;
4635 	int rc = 0;
4636 
4637 	DBENTER(BCE_VERBOSE_RESET);
4638 
4639 	/* Load the hardware default MAC address. */
4640 	bce_set_mac_addr(sc);
4641 
4642 	/* Set the Ethernet backoff seed value */
4643 	val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
4644 	      (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
4645 	      (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
4646 	REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
4647 
4648 	sc->last_status_idx = 0;
4649 	sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
4650 
4651 	/* Set up link change interrupt generation. */
4652 	REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
4653 
4654 	/* Program the physical address of the status block. */
4655 	REG_WR(sc, BCE_HC_STATUS_ADDR_L,
4656 		BCE_ADDR_LO(sc->status_block_paddr));
4657 	REG_WR(sc, BCE_HC_STATUS_ADDR_H,
4658 		BCE_ADDR_HI(sc->status_block_paddr));
4659 
4660 	/* Program the physical address of the statistics block. */
4661 	REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
4662 		BCE_ADDR_LO(sc->stats_block_paddr));
4663 	REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
4664 		BCE_ADDR_HI(sc->stats_block_paddr));
4665 
4666 	/* Program various host coalescing parameters. */
4667 	REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4668 		(sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip);
4669 	REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4670 		(sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip);
4671 	REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
4672 		(sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
4673 	REG_WR(sc, BCE_HC_TX_TICKS,
4674 		(sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
4675 	REG_WR(sc, BCE_HC_RX_TICKS,
4676 		(sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
4677 	REG_WR(sc, BCE_HC_COM_TICKS,
4678 		(sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
4679 	REG_WR(sc, BCE_HC_CMD_TICKS,
4680 		(sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
4681 	REG_WR(sc, BCE_HC_STATS_TICKS,
4682 		(sc->bce_stats_ticks & 0xffff00));
4683 	REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4684 
4685 	/* Configure the Host Coalescing block. */
4686 	val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
4687 		      BCE_HC_CONFIG_COLLECT_STATS;
4688 
4689 #if 0
4690 	/* ToDo: Add MSI-X support. */
4691 	if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
4692 		u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
4693 			   BCE_HC_SB_CONFIG_1;
4694 
4695 		REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
4696 
4697 		REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
4698 			BCE_HC_SB_CONFIG_1_ONE_SHOT);
4699 
4700 		REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
4701 			(sc->tx_quick_cons_trip_int << 16) |
4702 			 sc->tx_quick_cons_trip);
4703 
4704 		REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
4705 			(sc->tx_ticks_int << 16) | sc->tx_ticks);
4706 
4707 		val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
4708 	}
4709 
4710 	/*
4711 	 * Tell the HC block to automatically set the
4712 	 * INT_MASK bit after an MSI/MSI-X interrupt
4713 	 * is generated so the driver doesn't have to.
4714 	 */
4715 	if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
4716 		val |= BCE_HC_CONFIG_ONE_SHOT;
4717 
4718 	/* Set the MSI-X status blocks to 128 byte boundaries. */
4719 	if (sc->bce_flags & BCE_USING_MSIX_FLAG)
4720 		val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
4721 #endif
4722 
4723 	REG_WR(sc, BCE_HC_CONFIG, val);
4724 
4725 	/* Clear the internal statistics counters. */
4726 	REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
4727 
4728 	/* Verify that bootcode is running. */
4729 	reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
4730 
4731 	DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
4732 		BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
4733 			__FILE__, __LINE__);
4734 		reg = 0);
4735 
4736 	if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
4737 	    BCE_DEV_INFO_SIGNATURE_MAGIC) {
4738 		BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
4739 			"Expected: 08%08X\n", __FILE__, __LINE__,
4740 			(reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
4741 			BCE_DEV_INFO_SIGNATURE_MAGIC);
4742 		rc = ENODEV;
4743 		goto bce_blockinit_exit;
4744 	}
4745 
4746 	/* Enable DMA */
4747 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4748 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4749 		val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4750 		val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4751 		REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4752 	}
4753 
4754 	/* Allow bootcode to apply any additional fixes before enabling MAC. */
4755 	rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
4756 
4757 	/* Enable link state change interrupt generation. */
4758 	REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
4759 
4760 	/* Enable all remaining blocks in the MAC. */
4761 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)	||
4762 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
4763 		REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT_XI);
4764 	else
4765 		REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4766 
4767 	REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4768 	DELAY(20);
4769 
4770 	/* Save the current host coalescing block settings. */
4771 	sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
4772 
4773 bce_blockinit_exit:
4774 	DBEXIT(BCE_VERBOSE_RESET);
4775 
4776 	return (rc);
4777 }
4778 
4779 
4780 /****************************************************************************/
4781 /* Encapsulate an mbuf into the rx_bd chain.                                */
4782 /*                                                                          */
4783 /* Returns:                                                                 */
4784 /*   0 for success, positive value for failure.                             */
4785 /****************************************************************************/
4786 static int
4787 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
4788 	u16 *chain_prod, u32 *prod_bseq)
4789 {
4790 	bus_dmamap_t map;
4791 	bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4792 	struct mbuf *m_new = NULL;
4793 	struct rx_bd *rxbd;
4794 	int nsegs, error, rc = 0;
4795 #ifdef BCE_DEBUG
4796 	u16 debug_chain_prod = *chain_prod;
4797 #endif
4798 
4799 	DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
4800 
4801 	/* Make sure the inputs are valid. */
4802 	DBRUNIF((*chain_prod > MAX_RX_BD),
4803 		BCE_PRINTF("%s(%d): RX producer out of range: 0x%04X > 0x%04X\n",
4804 		__FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD));
4805 
4806 	DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
4807 		"prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq);
4808 
4809 	/* Update some debug statistic counters */
4810 	DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4811 		sc->rx_low_watermark = sc->free_rx_bd);
4812 	DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
4813 
4814 	/* Check whether this is a new mbuf allocation. */
4815 	if (m == NULL) {
4816 
4817 		/* Simulate an mbuf allocation failure. */
4818 		DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
4819 			sc->mbuf_alloc_failed++;
4820 			sc->debug_mbuf_sim_alloc_failed++;
4821 			rc = ENOBUFS;
4822 			goto bce_get_rx_buf_exit);
4823 
4824 		/* This is a new mbuf allocation. */
4825 #ifdef BCE_USE_SPLIT_HEADER
4826 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
4827 #else
4828 		if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES)
4829 			m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
4830 		else
4831 			m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, sc->rx_bd_mbuf_alloc_size);
4832 #endif
4833 
4834 		if (m_new == NULL) {
4835 			sc->mbuf_alloc_failed++;
4836 			rc = ENOBUFS;
4837 			goto bce_get_rx_buf_exit;
4838 		}
4839 
4840 		DBRUN(sc->debug_rx_mbuf_alloc++);
4841 	} else {
4842 		/* Reuse an existing mbuf. */
4843 		m_new = m;
4844 	}
4845 
4846 	/* Make sure we have a valid packet header. */
4847 	M_ASSERTPKTHDR(m_new);
4848 
4849 	/* Initialize the mbuf size and pad if necessary for alignment. */
4850 	m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
4851 	m_adj(m_new, sc->rx_bd_mbuf_align_pad);
4852 
4853 	/* ToDo: Consider calling m_fragment() to test error handling. */
4854 
4855 	/* Map the mbuf cluster into device memory. */
4856 	map = sc->rx_mbuf_map[*chain_prod];
4857 	error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new,
4858 	    segs, &nsegs, BUS_DMA_NOWAIT);
4859 
4860 	/* Handle any mapping errors. */
4861 	if (error) {
4862 		BCE_PRINTF("%s(%d): Error mapping mbuf into RX chain (%d)!\n",
4863 			__FILE__, __LINE__, error);
4864 
4865 		m_freem(m_new);
4866 		DBRUN(sc->debug_rx_mbuf_alloc--);
4867 
4868 		rc = ENOBUFS;
4869 		goto bce_get_rx_buf_exit;
4870 	}
4871 
4872 	/* All mbufs must map to a single segment. */
4873 	KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
4874 		 __FUNCTION__, nsegs));
4875 
4876 	/* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */
4877 
4878 	/* Setup the rx_bd for the segment. */
4879 	rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
4880 
4881 	rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
4882 	rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
4883 	rxbd->rx_bd_len       = htole32(segs[0].ds_len);
4884 	rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
4885 	*prod_bseq += segs[0].ds_len;
4886 
4887 	/* Save the mbuf and update our counter. */
4888 	sc->rx_mbuf_ptr[*chain_prod] = m_new;
4889 	sc->free_rx_bd -= nsegs;
4890 
4891 	DBRUNMSG(BCE_INSANE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod,
4892 		nsegs));
4893 
4894 	DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
4895 		"prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq);
4896 
4897 bce_get_rx_buf_exit:
4898 	DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
4899 
4900 	return(rc);
4901 }
4902 
4903 
4904 #ifdef BCE_USE_SPLIT_HEADER
4905 /****************************************************************************/
4906 /* Encapsulate an mbuf cluster into the page chain.                        */
4907 /*                                                                          */
4908 /* Returns:                                                                 */
4909 /*   0 for success, positive value for failure.                             */
4910 /****************************************************************************/
4911 static int
4912 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
4913 	u16 *prod_idx)
4914 {
4915 	bus_dmamap_t map;
4916 	bus_addr_t busaddr;
4917 	struct mbuf *m_new = NULL;
4918 	struct rx_bd *pgbd;
4919 	int error, rc = 0;
4920 #ifdef BCE_DEBUG
4921 	u16 debug_prod_idx = *prod_idx;
4922 #endif
4923 
4924 	DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
4925 
4926 	/* Make sure the inputs are valid. */
4927 	DBRUNIF((*prod_idx > MAX_PG_BD),
4928 		BCE_PRINTF("%s(%d): page producer out of range: 0x%04X > 0x%04X\n",
4929 		__FILE__, __LINE__, *prod_idx, (u16) MAX_PG_BD));
4930 
4931 	DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
4932 		"chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
4933 
4934 	/* Update counters if we've hit a new low or run out of pages. */
4935 	DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
4936 		sc->pg_low_watermark = sc->free_pg_bd);
4937 	DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
4938 
4939 	/* Check whether this is a new mbuf allocation. */
4940 	if (m == NULL) {
4941 
4942 		/* Simulate an mbuf allocation failure. */
4943 		DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
4944 			sc->mbuf_alloc_failed++;
4945 			sc->debug_mbuf_sim_alloc_failed++;
4946 			rc = ENOBUFS;
4947 			goto bce_get_pg_buf_exit);
4948 
4949 		/* This is a new mbuf allocation. */
4950 		m_new = m_getcl(M_DONTWAIT, MT_DATA, 0);
4951 		if (m_new == NULL) {
4952 			sc->mbuf_alloc_failed++;
4953 			rc = ENOBUFS;
4954 			goto bce_get_pg_buf_exit;
4955 		}
4956 
4957 		DBRUN(sc->debug_pg_mbuf_alloc++);
4958 	} else {
4959 		/* Reuse an existing mbuf. */
4960 		m_new = m;
4961 		m_new->m_data = m_new->m_ext.ext_buf;
4962 	}
4963 
4964 	m_new->m_len = sc->pg_bd_mbuf_alloc_size;
4965 
4966 	/* ToDo: Consider calling m_fragment() to test error handling. */
4967 
4968 	/* Map the mbuf cluster into device memory. */
4969 	map = sc->pg_mbuf_map[*prod_idx];
4970 	error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *),
4971 	    sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, &busaddr, BUS_DMA_NOWAIT);
4972 
4973 	/* Handle any mapping errors. */
4974 	if (error) {
4975 		BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
4976 			__FILE__, __LINE__);
4977 
4978 		m_freem(m_new);
4979 		DBRUN(sc->debug_pg_mbuf_alloc--);
4980 
4981 		rc = ENOBUFS;
4982 		goto bce_get_pg_buf_exit;
4983 	}
4984 
4985 	/* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */
4986 
4987 	/*
4988 	 * The page chain uses the same rx_bd data structure
4989 	 * as the receive chain but doesn't require a byte sequence (bseq).
4990 	 */
4991 	pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
4992 
4993 	pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(busaddr));
4994 	pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(busaddr));
4995 	pgbd->rx_bd_len       = htole32(sc->pg_bd_mbuf_alloc_size);
4996 	pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
4997 
4998 	/* Save the mbuf and update our counter. */
4999 	sc->pg_mbuf_ptr[*prod_idx] = m_new;
5000 	sc->free_pg_bd--;
5001 
5002 	DBRUNMSG(BCE_INSANE_RECV, bce_dump_pg_mbuf_chain(sc, debug_prod_idx,
5003 		1));
5004 
5005 	DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5006 		"prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5007 
5008 bce_get_pg_buf_exit:
5009 	DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5010 
5011 	return(rc);
5012 }
5013 #endif /* BCE_USE_SPLIT_HEADER */
5014 
5015 /****************************************************************************/
5016 /* Initialize the TX context memory.                                        */
5017 /*                                                                          */
5018 /* Returns:                                                                 */
5019 /*   Nothing                                                                */
5020 /****************************************************************************/
5021 static void
5022 bce_init_tx_context(struct bce_softc *sc)
5023 {
5024 	u32 val;
5025 
5026 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5027 
5028 	/* Initialize the context ID for an L2 TX chain. */
5029 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
5030 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
5031 		/* Set the CID type to support an L2 connection. */
5032 		val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5033 		CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5034 		val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5035 		CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
5036 
5037 		/* Point the hardware to the first page in the chain. */
5038 		val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5039 		CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5040 		val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5041 		CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5042 	} else {
5043 		/* Set the CID type to support an L2 connection. */
5044 		val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5045 		CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5046 		val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5047 		CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5048 
5049 		/* Point the hardware to the first page in the chain. */
5050 		val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5051 		CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5052 		val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5053 		CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5054 	}
5055 
5056 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5057 }
5058 
5059 
5060 /****************************************************************************/
5061 /* Allocate memory and initialize the TX data structures.                   */
5062 /*                                                                          */
5063 /* Returns:                                                                 */
5064 /*   0 for success, positive value for failure.                             */
5065 /****************************************************************************/
5066 static int
5067 bce_init_tx_chain(struct bce_softc *sc)
5068 {
5069 	struct tx_bd *txbd;
5070 	int i, rc = 0;
5071 
5072 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5073 
5074 	/* Set the initial TX producer/consumer indices. */
5075 	sc->tx_prod        = 0;
5076 	sc->tx_cons        = 0;
5077 	sc->tx_prod_bseq   = 0;
5078 	sc->used_tx_bd     = 0;
5079 	sc->max_tx_bd      = USABLE_TX_BD;
5080 	DBRUN(sc->tx_hi_watermark = USABLE_TX_BD);
5081 	DBRUN(sc->tx_full_count = 0);
5082 
5083 	/*
5084 	 * The NetXtreme II supports a linked-list structre called
5085 	 * a Buffer Descriptor Chain (or BD chain).  A BD chain
5086 	 * consists of a series of 1 or more chain pages, each of which
5087 	 * consists of a fixed number of BD entries.
5088 	 * The last BD entry on each page is a pointer to the next page
5089 	 * in the chain, and the last pointer in the BD chain
5090 	 * points back to the beginning of the chain.
5091 	 */
5092 
5093 	/* Set the TX next pointer chain entries. */
5094 	for (i = 0; i < TX_PAGES; i++) {
5095 		int j;
5096 
5097 		txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5098 
5099 		/* Check if we've reached the last page. */
5100 		if (i == (TX_PAGES - 1))
5101 			j = 0;
5102 		else
5103 			j = i + 1;
5104 
5105 		txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5106 		txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5107 	}
5108 
5109 	bce_init_tx_context(sc);
5110 
5111 	DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
5112 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5113 
5114 	return(rc);
5115 }
5116 
5117 
5118 /****************************************************************************/
5119 /* Free memory and clear the TX data structures.                            */
5120 /*                                                                          */
5121 /* Returns:                                                                 */
5122 /*   Nothing.                                                               */
5123 /****************************************************************************/
5124 static void
5125 bce_free_tx_chain(struct bce_softc *sc)
5126 {
5127 	int i;
5128 
5129 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5130 
5131 	/* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5132 	for (i = 0; i < TOTAL_TX_BD; i++) {
5133 		if (sc->tx_mbuf_ptr[i] != NULL) {
5134 			if (sc->tx_mbuf_map[i] != NULL)
5135 				bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i],
5136 					BUS_DMASYNC_POSTWRITE);
5137 			m_freem(sc->tx_mbuf_ptr[i]);
5138 			sc->tx_mbuf_ptr[i] = NULL;
5139 			DBRUN(sc->debug_tx_mbuf_alloc--);
5140 		}
5141 	}
5142 
5143 	/* Clear each TX chain page. */
5144 	for (i = 0; i < TX_PAGES; i++)
5145 		bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5146 
5147 	sc->used_tx_bd     = 0;
5148 
5149 	/* Check if we lost any mbufs in the process. */
5150 	DBRUNIF((sc->debug_tx_mbuf_alloc),
5151 		BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5152 			"from tx chain!\n",
5153 			__FILE__, __LINE__, sc->debug_tx_mbuf_alloc));
5154 
5155 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5156 }
5157 
5158 
5159 /****************************************************************************/
5160 /* Initialize the RX context memory.                                        */
5161 /*                                                                          */
5162 /* Returns:                                                                 */
5163 /*   Nothing                                                                */
5164 /****************************************************************************/
5165 static void
5166 bce_init_rx_context(struct bce_softc *sc)
5167 {
5168 	u32 val;
5169 
5170 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5171 
5172 	/* Initialize the type, size, and BD cache levels for the RX context. */
5173 	val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5174 		BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5175 		(0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5176 
5177 	/*
5178 	 * Set the level for generating pause frames
5179 	 * when the number of available rx_bd's gets
5180 	 * too low (the low watermark) and the level
5181 	 * when pause frames can be stopped (the high
5182 	 * watermark).
5183 	 */
5184 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
5185 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
5186 		u32 lo_water, hi_water;
5187 
5188 		lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5189 		hi_water = USABLE_RX_BD / 4;
5190 
5191 		lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5192 		hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5193 
5194 		if (hi_water > 0xf)
5195 			hi_water = 0xf;
5196 		else if (hi_water == 0)
5197 			lo_water = 0;
5198 		val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5199 			(hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5200 	}
5201 
5202  	CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5203 
5204 	/* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5205 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
5206 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
5207 		val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5208 		REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5209 	}
5210 
5211 	/* Point the hardware to the first page in the chain. */
5212 	val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5213 	CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5214 	val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5215 	CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5216 
5217 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5218 }
5219 
5220 
5221 /****************************************************************************/
5222 /* Allocate memory and initialize the RX data structures.                   */
5223 /*                                                                          */
5224 /* Returns:                                                                 */
5225 /*   0 for success, positive value for failure.                             */
5226 /****************************************************************************/
5227 static int
5228 bce_init_rx_chain(struct bce_softc *sc)
5229 {
5230 	struct rx_bd *rxbd;
5231 	int i, rc = 0;
5232 
5233 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5234 		BCE_VERBOSE_CTX);
5235 
5236 	/* Initialize the RX producer and consumer indices. */
5237 	sc->rx_prod        = 0;
5238 	sc->rx_cons        = 0;
5239 	sc->rx_prod_bseq   = 0;
5240 	sc->free_rx_bd     = USABLE_RX_BD;
5241 	sc->max_rx_bd      = USABLE_RX_BD;
5242 	DBRUN(sc->rx_low_watermark = sc->max_rx_bd);
5243 	DBRUN(sc->rx_empty_count = 0);
5244 
5245 	/* Initialize the RX next pointer chain entries. */
5246 	for (i = 0; i < RX_PAGES; i++) {
5247 		int j;
5248 
5249 		rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5250 
5251 		/* Check if we've reached the last page. */
5252 		if (i == (RX_PAGES - 1))
5253 			j = 0;
5254 		else
5255 			j = i + 1;
5256 
5257 		/* Setup the chain page pointers. */
5258 		rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5259 		rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5260 	}
5261 
5262 /* Fill up the RX chain. */
5263 	bce_fill_rx_chain(sc);
5264 
5265 	for (i = 0; i < RX_PAGES; i++) {
5266 		bus_dmamap_sync(
5267 			sc->rx_bd_chain_tag,
5268 	    	sc->rx_bd_chain_map[i],
5269 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5270 	}
5271 
5272 	bce_init_rx_context(sc);
5273 
5274 	DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD));
5275 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5276 		BCE_VERBOSE_CTX);
5277 	/* ToDo: Are there possible failure modes here? */
5278 	return(rc);
5279 }
5280 
5281 
5282 /****************************************************************************/
5283 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5284 /* occurs.                                                                  */
5285 /*                                                                          */
5286 /* Returns:                                                                 */
5287 /*   Nothing                                                                */
5288 /****************************************************************************/
5289 static void
5290 bce_fill_rx_chain(struct bce_softc *sc)
5291 {
5292 	u16 prod, prod_idx;
5293 	u32 prod_bseq;
5294 
5295 	DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5296 		BCE_VERBOSE_CTX);
5297 
5298 	/* Get the RX chain producer indices. */
5299 	prod      = sc->rx_prod;
5300 	prod_bseq = sc->rx_prod_bseq;
5301 
5302 	/* Keep filling the RX chain until it's full. */
5303 	while (sc->free_rx_bd > 0) {
5304 		prod_idx = RX_CHAIN_IDX(prod);
5305 		if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) {
5306 			/* Bail out if we can't add an mbuf to the chain. */
5307 			break;
5308 		}
5309 		prod = NEXT_RX_BD(prod);
5310 	}
5311 
5312 	/* Save the RX chain producer indices. */
5313 	sc->rx_prod      = prod;
5314 	sc->rx_prod_bseq = prod_bseq;
5315 
5316 	DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5317 		BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5318 		__FUNCTION__, sc->rx_prod));
5319 
5320 	/* Write the mailbox and tell the chip about the waiting rx_bd's. */
5321 	REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
5322 		sc->rx_prod);
5323 	REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
5324 		sc->rx_prod_bseq);
5325 
5326 	DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5327 		BCE_VERBOSE_CTX);
5328 }
5329 
5330 
5331 /****************************************************************************/
5332 /* Free memory and clear the RX data structures.                            */
5333 /*                                                                          */
5334 /* Returns:                                                                 */
5335 /*   Nothing.                                                               */
5336 /****************************************************************************/
5337 static void
5338 bce_free_rx_chain(struct bce_softc *sc)
5339 {
5340 	int i;
5341 
5342 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5343 
5344 	/* Free any mbufs still in the RX mbuf chain. */
5345 	for (i = 0; i < TOTAL_RX_BD; i++) {
5346 		if (sc->rx_mbuf_ptr[i] != NULL) {
5347 			if (sc->rx_mbuf_map[i] != NULL)
5348 				bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i],
5349 					BUS_DMASYNC_POSTREAD);
5350 			m_freem(sc->rx_mbuf_ptr[i]);
5351 			sc->rx_mbuf_ptr[i] = NULL;
5352 			DBRUN(sc->debug_rx_mbuf_alloc--);
5353 		}
5354 	}
5355 
5356 	/* Clear each RX chain page. */
5357 	for (i = 0; i < RX_PAGES; i++)
5358 		bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
5359 
5360 	sc->free_rx_bd = sc->max_rx_bd;
5361 
5362 	/* Check if we lost any mbufs in the process. */
5363 	DBRUNIF((sc->debug_rx_mbuf_alloc),
5364 		BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5365 			__FUNCTION__, sc->debug_rx_mbuf_alloc));
5366 
5367 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5368 }
5369 
5370 
5371 #ifdef BCE_USE_SPLIT_HEADER
5372 /****************************************************************************/
5373 /* Allocate memory and initialize the page data structures.                 */
5374 /* Assumes that bce_init_rx_chain() has not already been called.            */
5375 /*                                                                          */
5376 /* Returns:                                                                 */
5377 /*   0 for success, positive value for failure.                             */
5378 /****************************************************************************/
5379 static int
5380 bce_init_pg_chain(struct bce_softc *sc)
5381 {
5382 	struct rx_bd *pgbd;
5383 	int i, rc = 0;
5384 	u32 val;
5385 
5386 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5387 		BCE_VERBOSE_CTX);
5388 
5389 	/* Initialize the page producer and consumer indices. */
5390 	sc->pg_prod        = 0;
5391 	sc->pg_cons        = 0;
5392 	sc->free_pg_bd     = USABLE_PG_BD;
5393 	sc->max_pg_bd      = USABLE_PG_BD;
5394 	DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5395 	DBRUN(sc->pg_empty_count = 0);
5396 
5397 	/* Initialize the page next pointer chain entries. */
5398 	for (i = 0; i < PG_PAGES; i++) {
5399 		int j;
5400 
5401 		pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5402 
5403 		/* Check if we've reached the last page. */
5404 		if (i == (PG_PAGES - 1))
5405 			j = 0;
5406 		else
5407 			j = i + 1;
5408 
5409 		/* Setup the chain page pointers. */
5410 		pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
5411 		pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
5412 	}
5413 
5414 	/* Setup the MQ BIN mapping for host_pg_bidx. */
5415 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)	||
5416 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
5417 		REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
5418 
5419 	CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
5420 
5421 	/* Configure the rx_bd and page chain mbuf cluster size. */
5422 	val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size;
5423 	CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
5424 
5425 	/* Configure the context reserved for jumbo support. */
5426 	CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
5427 		BCE_L2CTX_RX_RBDC_JUMBO_KEY);
5428 
5429 	/* Point the hardware to the first page in the page chain. */
5430 	val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
5431 	CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
5432 	val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
5433 	CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
5434 
5435 	/* Fill up the page chain. */
5436 	bce_fill_pg_chain(sc);
5437 
5438 	for (i = 0; i < PG_PAGES; i++) {
5439 		bus_dmamap_sync(
5440 			sc->pg_bd_chain_tag,
5441 	    	sc->pg_bd_chain_map[i],
5442 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5443 	}
5444 
5445 	DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD));
5446 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5447 		BCE_VERBOSE_CTX);
5448 	return(rc);
5449 }
5450 
5451 
5452 /****************************************************************************/
5453 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
5454 /* occurs.                                                                  */
5455 /*                                                                          */
5456 /* Returns:                                                                 */
5457 /*   Nothing                                                                */
5458 /****************************************************************************/
5459 static void
5460 bce_fill_pg_chain(struct bce_softc *sc)
5461 {
5462 	u16 prod, prod_idx;
5463 
5464 	DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5465 		BCE_VERBOSE_CTX);
5466 
5467 	/* Get the page chain prodcuer index. */
5468 	prod = sc->pg_prod;
5469 
5470 	/* Keep filling the page chain until it's full. */
5471 	while (sc->free_pg_bd > 0) {
5472 		prod_idx = PG_CHAIN_IDX(prod);
5473 		if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) {
5474 			/* Bail out if we can't add an mbuf to the chain. */
5475 			break;
5476 		}
5477 		prod = NEXT_PG_BD(prod);
5478 	}
5479 
5480 	/* Save the page chain producer index. */
5481 	sc->pg_prod = prod;
5482 
5483 	DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5484 		BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
5485 		__FUNCTION__, sc->pg_prod));
5486 
5487 	/*
5488 	 * Write the mailbox and tell the chip about
5489 	 * the new rx_bd's in the page chain.
5490 	 */
5491 	REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX,
5492 		sc->pg_prod);
5493 
5494 	DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5495 		BCE_VERBOSE_CTX);
5496 }
5497 
5498 
5499 /****************************************************************************/
5500 /* Free memory and clear the RX data structures.                            */
5501 /*                                                                          */
5502 /* Returns:                                                                 */
5503 /*   Nothing.                                                               */
5504 /****************************************************************************/
5505 static void
5506 bce_free_pg_chain(struct bce_softc *sc)
5507 {
5508 	int i;
5509 
5510 	DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5511 
5512 	/* Free any mbufs still in the mbuf page chain. */
5513 	for (i = 0; i < TOTAL_PG_BD; i++) {
5514 		if (sc->pg_mbuf_ptr[i] != NULL) {
5515 			if (sc->pg_mbuf_map[i] != NULL)
5516 				bus_dmamap_sync(sc->pg_mbuf_tag, sc->pg_mbuf_map[i],
5517 					BUS_DMASYNC_POSTREAD);
5518 			m_freem(sc->pg_mbuf_ptr[i]);
5519 			sc->pg_mbuf_ptr[i] = NULL;
5520 			DBRUN(sc->debug_pg_mbuf_alloc--);
5521 		}
5522 	}
5523 
5524 	/* Clear each page chain pages. */
5525 	for (i = 0; i < PG_PAGES; i++)
5526 		bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
5527 
5528 	sc->free_pg_bd = sc->max_pg_bd;
5529 
5530 	/* Check if we lost any mbufs in the process. */
5531 	DBRUNIF((sc->debug_pg_mbuf_alloc),
5532 		BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
5533 			__FUNCTION__, sc->debug_pg_mbuf_alloc));
5534 
5535 	DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5536 }
5537 #endif /* BCE_USE_SPLIT_HEADER */
5538 
5539 
5540 /****************************************************************************/
5541 /* Set media options.                                                       */
5542 /*                                                                          */
5543 /* Returns:                                                                 */
5544 /*   0 for success, positive value for failure.                             */
5545 /****************************************************************************/
5546 static int
5547 bce_ifmedia_upd(struct ifnet *ifp)
5548 {
5549 	struct bce_softc *sc = ifp->if_softc;
5550 
5551 	DBENTER(BCE_VERBOSE);
5552 
5553 	BCE_LOCK(sc);
5554 	bce_ifmedia_upd_locked(ifp);
5555 	BCE_UNLOCK(sc);
5556 
5557 	DBEXIT(BCE_VERBOSE);
5558 	return (0);
5559 }
5560 
5561 
5562 /****************************************************************************/
5563 /* Set media options.                                                       */
5564 /*                                                                          */
5565 /* Returns:                                                                 */
5566 /*   Nothing.                                                               */
5567 /****************************************************************************/
5568 static void
5569 bce_ifmedia_upd_locked(struct ifnet *ifp)
5570 {
5571 	struct bce_softc *sc = ifp->if_softc;
5572 	struct mii_data *mii;
5573 
5574 	DBENTER(BCE_VERBOSE);
5575 
5576 	BCE_LOCK_ASSERT(sc);
5577 
5578 	mii = device_get_softc(sc->bce_miibus);
5579 
5580 	/* Make sure the MII bus has been enumerated. */
5581 	if (mii) {
5582 		sc->bce_link = 0;
5583 		if (mii->mii_instance) {
5584 			struct mii_softc *miisc;
5585 
5586 			LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5587 				mii_phy_reset(miisc);
5588 		}
5589 		mii_mediachg(mii);
5590 	}
5591 
5592 	DBEXIT(BCE_VERBOSE);
5593 }
5594 
5595 
5596 /****************************************************************************/
5597 /* Reports current media status.                                            */
5598 /*                                                                          */
5599 /* Returns:                                                                 */
5600 /*   Nothing.                                                               */
5601 /****************************************************************************/
5602 static void
5603 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5604 {
5605 	struct bce_softc *sc = ifp->if_softc;
5606 	struct mii_data *mii;
5607 
5608 	DBENTER(BCE_VERBOSE);
5609 
5610 	BCE_LOCK(sc);
5611 
5612 	mii = device_get_softc(sc->bce_miibus);
5613 
5614 	mii_pollstat(mii);
5615 	ifmr->ifm_active = mii->mii_media_active;
5616 	ifmr->ifm_status = mii->mii_media_status;
5617 
5618 	BCE_UNLOCK(sc);
5619 
5620 	DBEXIT(BCE_VERBOSE);
5621 }
5622 
5623 
5624 /****************************************************************************/
5625 /* Handles PHY generated interrupt events.                                  */
5626 /*                                                                          */
5627 /* Returns:                                                                 */
5628 /*   Nothing.                                                               */
5629 /****************************************************************************/
5630 static void
5631 bce_phy_intr(struct bce_softc *sc)
5632 {
5633 	u32 new_link_state, old_link_state;
5634 
5635 	DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
5636 
5637 	new_link_state = sc->status_block->status_attn_bits &
5638 		STATUS_ATTN_BITS_LINK_STATE;
5639 	old_link_state = sc->status_block->status_attn_bits_ack &
5640 		STATUS_ATTN_BITS_LINK_STATE;
5641 
5642 	/* Handle any changes if the link state has changed. */
5643 	if (new_link_state != old_link_state) {
5644 
5645 		/* Update the status_attn_bits_ack field in the status block. */
5646 		if (new_link_state) {
5647 			REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
5648 				STATUS_ATTN_BITS_LINK_STATE);
5649 			DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
5650 				__FUNCTION__);
5651 		}
5652 		else {
5653 			REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
5654 				STATUS_ATTN_BITS_LINK_STATE);
5655 			DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
5656 				__FUNCTION__);
5657 		}
5658 
5659 		/*
5660 		 * Assume link is down and allow
5661 		 * tick routine to update the state
5662 		 * based on the actual media state.
5663 		 */
5664 		sc->bce_link = 0;
5665 		callout_stop(&sc->bce_tick_callout);
5666 		bce_tick(sc);
5667 	}
5668 
5669 	/* Acknowledge the link change interrupt. */
5670 	REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
5671 
5672 	DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
5673 }
5674 
5675 
5676 /****************************************************************************/
5677 /* Reads the receive consumer value from the status block (skipping over    */
5678 /* chain page pointer if necessary).                                        */
5679 /*                                                                          */
5680 /* Returns:                                                                 */
5681 /*   hw_cons                                                                */
5682 /****************************************************************************/
5683 static inline u16
5684 bce_get_hw_rx_cons(struct bce_softc *sc)
5685 {
5686 	u16 hw_cons;
5687 
5688 	rmb();
5689 	hw_cons = sc->status_block->status_rx_quick_consumer_index0;
5690 	if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
5691 		hw_cons++;
5692 
5693 	return hw_cons;
5694 }
5695 
5696 /****************************************************************************/
5697 /* Handles received frame interrupt events.                                 */
5698 /*                                                                          */
5699 /* Returns:                                                                 */
5700 /*   Nothing.                                                               */
5701 /****************************************************************************/
5702 static void
5703 bce_rx_intr(struct bce_softc *sc)
5704 {
5705 	struct ifnet *ifp = sc->bce_ifp;
5706 	struct l2_fhdr *l2fhdr;
5707 	unsigned int pkt_len;
5708 	u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
5709 	u32 status;
5710 #ifdef BCE_USE_SPLIT_HEADER
5711 	unsigned int rem_len;
5712 	u16 sw_pg_cons, sw_pg_cons_idx;
5713 #endif
5714 
5715 	DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
5716 	DBRUN(sc->rx_interrupts++);
5717 	DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
5718 		"rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
5719 		__FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
5720 
5721 	/* Prepare the RX chain pages to be accessed by the host CPU. */
5722 	for (int i = 0; i < RX_PAGES; i++)
5723 		bus_dmamap_sync(sc->rx_bd_chain_tag,
5724 		    sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE);
5725 
5726 #ifdef BCE_USE_SPLIT_HEADER
5727 	/* Prepare the page chain pages to be accessed by the host CPU. */
5728 	for (int i = 0; i < PG_PAGES; i++)
5729 		bus_dmamap_sync(sc->pg_bd_chain_tag,
5730 		    sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTWRITE);
5731 #endif
5732 
5733 	/* Get the hardware's view of the RX consumer index. */
5734 	hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
5735 
5736 	/* Get working copies of the driver's view of the consumer indices. */
5737 	sw_rx_cons = sc->rx_cons;
5738 #ifdef BCE_USE_SPLIT_HEADER
5739 	sw_pg_cons = sc->pg_cons;
5740 #endif
5741 
5742 	/* Update some debug statistics counters */
5743 	DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5744 		sc->rx_low_watermark = sc->free_rx_bd);
5745 	DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
5746 
5747 	/* Scan through the receive chain as long as there is work to do */
5748 	/* ToDo: Consider setting a limit on the number of packets processed. */
5749 	rmb();
5750 	while (sw_rx_cons != hw_rx_cons) {
5751 		struct mbuf *m0;
5752 
5753 		/* Convert the producer/consumer indices to an actual rx_bd index. */
5754 		sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
5755 
5756 		/* Unmap the mbuf from DMA space. */
5757 		bus_dmamap_sync(sc->rx_mbuf_tag,
5758 		    sc->rx_mbuf_map[sw_rx_cons_idx],
5759 	    	BUS_DMASYNC_POSTREAD);
5760 		bus_dmamap_unload(sc->rx_mbuf_tag,
5761 		    sc->rx_mbuf_map[sw_rx_cons_idx]);
5762 
5763 		/* Remove the mbuf from the RX chain. */
5764 		m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
5765 		sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
5766 		DBRUN(sc->debug_rx_mbuf_alloc--);
5767 		sc->free_rx_bd++;
5768 
5769 		/*
5770 		 * Frames received on the NetXteme II are prepended
5771 		 * with an l2_fhdr structure which provides status
5772 		 * information about the received frame (including
5773 		 * VLAN tags and checksum info).  The frames are also
5774 		 * automatically adjusted to align the IP header
5775 		 * (i.e. two null bytes are inserted before the
5776 		 * Ethernet header).  As a result the data DMA'd by
5777 		 * the controller into the mbuf is as follows:
5778 		 * +---------+-----+---------------------+-----+
5779 		 * | l2_fhdr | pad | packet data         | FCS |
5780 		 * +---------+-----+---------------------+-----+
5781 		 * The l2_fhdr needs to be checked and skipped and
5782 		 * the FCS needs to be stripped before sending the
5783 		 * packet up the stack.
5784 		 */
5785 		l2fhdr  = mtod(m0, struct l2_fhdr *);
5786 
5787 		/* Get the packet data + FCS length and the status. */
5788 		pkt_len = l2fhdr->l2_fhdr_pkt_len;
5789 		status  = l2fhdr->l2_fhdr_status;
5790 
5791 		/*
5792 		 * Skip over the l2_fhdr and pad, resulting in the
5793 		 * following data in the mbuf:
5794 		 * +---------------------+-----+
5795 		 * | packet data         | FCS |
5796 		 * +---------------------+-----+
5797 		 */
5798 		m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
5799 
5800 #ifdef BCE_USE_SPLIT_HEADER
5801 		/*
5802 		 * Check whether the received frame fits in a single
5803 		 * mbuf or not (i.e. packet data + FCS <=
5804 		 * sc->rx_bd_mbuf_data_len bytes).
5805 		 */
5806 		if (pkt_len > m0->m_len) {
5807 			/*
5808 			 * The received frame is larger than a single mbuf.
5809 			 * If the frame was a TCP frame then only the TCP
5810 			 * header is placed in the mbuf, the remaining
5811 			 * payload (including FCS) is placed in the page
5812 			 * chain, the SPLIT flag is set, and the header
5813 			 * length is placed in the IP checksum field.
5814 			 * If the frame is not a TCP frame then the mbuf
5815 			 * is filled and the remaining bytes are placed
5816 			 * in the page chain.
5817 			 */
5818 
5819 			DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large packet.\n",
5820 				__FUNCTION__);
5821 
5822 			/*
5823 			 * When the page chain is enabled and the TCP
5824 			 * header has been split from the TCP payload,
5825 			 * the ip_xsum structure will reflect the length
5826 			 * of the TCP header, not the IP checksum.  Set
5827 			 * the packet length of the mbuf accordingly.
5828 			 */
5829 		 	if (status & L2_FHDR_STATUS_SPLIT)
5830 				m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
5831 
5832 			rem_len = pkt_len - m0->m_len;
5833 
5834 			/* Pull mbufs off the page chain for the remaining data. */
5835 			while (rem_len > 0) {
5836 				struct mbuf *m_pg;
5837 
5838 				sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
5839 
5840 				/* Remove the mbuf from the page chain. */
5841 				m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
5842 				sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
5843 				DBRUN(sc->debug_pg_mbuf_alloc--);
5844 				sc->free_pg_bd++;
5845 
5846 				/* Unmap the page chain mbuf from DMA space. */
5847 				bus_dmamap_sync(sc->pg_mbuf_tag,
5848 					sc->pg_mbuf_map[sw_pg_cons_idx],
5849 					BUS_DMASYNC_POSTREAD);
5850 				bus_dmamap_unload(sc->pg_mbuf_tag,
5851 					sc->pg_mbuf_map[sw_pg_cons_idx]);
5852 
5853 				/* Adjust the mbuf length. */
5854 				if (rem_len < m_pg->m_len) {
5855 					/* The mbuf chain is complete. */
5856 					m_pg->m_len = rem_len;
5857 					rem_len = 0;
5858 				} else {
5859 					/* More packet data is waiting. */
5860 					rem_len -= m_pg->m_len;
5861 				}
5862 
5863 				/* Concatenate the mbuf cluster to the mbuf. */
5864 				m_cat(m0, m_pg);
5865 
5866 				sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
5867 			}
5868 
5869 			/* Set the total packet length. */
5870 			m0->m_pkthdr.len = pkt_len;
5871 
5872 		} else {
5873 			/*
5874 			 * The received packet is small and fits in a
5875 			 * single mbuf (i.e. the l2_fhdr + pad + packet +
5876 			 * FCS <= MHLEN).  In other words, the packet is
5877 			 * 154 bytes or less in size.
5878 			 */
5879 
5880 			DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small packet.\n",
5881 				__FUNCTION__);
5882 
5883 			/* Set the total packet length. */
5884 			m0->m_pkthdr.len = m0->m_len = pkt_len;
5885 		}
5886 #endif
5887 
5888 		/* Remove the trailing Ethernet FCS. */
5889 		m_adj(m0, -ETHER_CRC_LEN);
5890 
5891 		/* Check that the resulting mbuf chain is valid. */
5892 		DBRUN(m_sanity(m0, FALSE));
5893 		DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
5894 			(m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
5895 			BCE_PRINTF("Invalid Ethernet frame size!\n");
5896 			m_print(m0, 128));
5897 
5898 		DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
5899 			BCE_PRINTF("Simulating l2_fhdr status error.\n");
5900 			status = status | L2_FHDR_ERRORS_PHY_DECODE);
5901 
5902 		/* Check the received frame for errors. */
5903 		if (status & (L2_FHDR_ERRORS_BAD_CRC |
5904 			L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
5905 			L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
5906 
5907 			/* Log the error and release the mbuf. */
5908 			ifp->if_ierrors++;
5909 			DBRUN(sc->l2fhdr_status_errors++);
5910 
5911 			m_freem(m0);
5912 			m0 = NULL;
5913 			goto bce_rx_int_next_rx;
5914 		}
5915 
5916 		/* Send the packet to the appropriate interface. */
5917 		m0->m_pkthdr.rcvif = ifp;
5918 
5919 		/* Assume no hardware checksum. */
5920 		m0->m_pkthdr.csum_flags = 0;
5921 
5922 		/* Validate the checksum if offload enabled. */
5923 		if (ifp->if_capenable & IFCAP_RXCSUM) {
5924 
5925 			/* Check for an IP datagram. */
5926 		 	if (!(status & L2_FHDR_STATUS_SPLIT) &&
5927 				(status & L2_FHDR_STATUS_IP_DATAGRAM)) {
5928 				m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
5929 
5930 				/* Check if the IP checksum is valid. */
5931 				if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
5932 					m0->m_pkthdr.csum_flags |= CSUM_IP_VALID;
5933 			}
5934 
5935 			/* Check for a valid TCP/UDP frame. */
5936 			if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
5937 				L2_FHDR_STATUS_UDP_DATAGRAM)) {
5938 
5939 				/* Check for a good TCP/UDP checksum. */
5940 				if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
5941 					      L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
5942 					m0->m_pkthdr.csum_data =
5943 					    l2fhdr->l2_fhdr_tcp_udp_xsum;
5944 					m0->m_pkthdr.csum_flags |= (CSUM_DATA_VALID
5945 						| CSUM_PSEUDO_HDR);
5946 				}
5947 			}
5948 		}
5949 
5950 		/*
5951 		 * If we received a packet with a vlan tag,
5952 		 * attach that information to the packet.
5953 		 */
5954 		if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
5955 #if __FreeBSD_version < 700000
5956 			VLAN_INPUT_TAG(ifp, m0, l2fhdr->l2_fhdr_vlan_tag, continue);
5957 #else
5958 			m0->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag;
5959 			m0->m_flags |= M_VLANTAG;
5960 #endif
5961 		}
5962 
5963 		/* Pass the mbuf off to the upper layers. */
5964 		ifp->if_ipackets++;
5965 
5966 bce_rx_int_next_rx:
5967 		sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
5968 
5969 		/* If we have a packet, pass it up the stack */
5970 		if (m0) {
5971 			/* Make sure we don't lose our place when we release the lock. */
5972 			sc->rx_cons = sw_rx_cons;
5973 #ifdef BCE_USE_SPLIT_HEADER
5974 			sc->pg_cons = sw_pg_cons;
5975 #endif
5976 
5977 			BCE_UNLOCK(sc);
5978 			(*ifp->if_input)(ifp, m0);
5979 			BCE_LOCK(sc);
5980 
5981 			/* Recover our place. */
5982 			sw_rx_cons = sc->rx_cons;
5983 #ifdef BCE_USE_SPLIT_HEADER
5984 			sw_pg_cons = sc->pg_cons;
5985 #endif
5986 		}
5987 
5988 		/* Refresh hw_cons to see if there's new work */
5989 		if (sw_rx_cons == hw_rx_cons)
5990 			hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
5991 	}
5992 
5993 	/* No new packets to process.  Refill the RX and page chains and exit. */
5994 #ifdef BCE_USE_SPLIT_HEADER
5995 	sc->pg_cons = sw_pg_cons;
5996 	bce_fill_pg_chain(sc);
5997 #endif
5998 
5999 	sc->rx_cons = sw_rx_cons;
6000 	bce_fill_rx_chain(sc);
6001 
6002 	for (int i = 0; i < RX_PAGES; i++)
6003 		bus_dmamap_sync(sc->rx_bd_chain_tag,
6004 		    sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6005 
6006 #ifdef BCE_USE_SPLIT_HEADER
6007 	for (int i = 0; i < PG_PAGES; i++)
6008 		bus_dmamap_sync(sc->pg_bd_chain_tag,
6009 		    sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6010 #endif
6011 
6012 	DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6013 		"rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6014 		__FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6015 	DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6016 }
6017 
6018 
6019 /****************************************************************************/
6020 /* Reads the transmit consumer value from the status block (skipping over   */
6021 /* chain page pointer if necessary).                                        */
6022 /*                                                                          */
6023 /* Returns:                                                                 */
6024 /*   hw_cons                                                                */
6025 /****************************************************************************/
6026 static inline u16
6027 bce_get_hw_tx_cons(struct bce_softc *sc)
6028 {
6029 	u16 hw_cons;
6030 
6031 	mb();
6032 	hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6033 	if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6034 		hw_cons++;
6035 
6036 	return hw_cons;
6037 }
6038 
6039 
6040 /****************************************************************************/
6041 /* Handles transmit completion interrupt events.                            */
6042 /*                                                                          */
6043 /* Returns:                                                                 */
6044 /*   Nothing.                                                               */
6045 /****************************************************************************/
6046 static void
6047 bce_tx_intr(struct bce_softc *sc)
6048 {
6049 	struct ifnet *ifp = sc->bce_ifp;
6050 	u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6051 
6052 	DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6053 	DBRUN(sc->tx_interrupts++);
6054 	DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6055 		"tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6056 		__FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6057 
6058 	BCE_LOCK_ASSERT(sc);
6059 
6060 	/* Get the hardware's view of the TX consumer index. */
6061 	hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6062 	sw_tx_cons = sc->tx_cons;
6063 
6064 	/* Prevent speculative reads from getting ahead of the status block. */
6065 	bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6066 		BUS_SPACE_BARRIER_READ);
6067 
6068 	/* Cycle through any completed TX chain page entries. */
6069 	while (sw_tx_cons != hw_tx_cons) {
6070 #ifdef BCE_DEBUG
6071 		struct tx_bd *txbd = NULL;
6072 #endif
6073 		sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6074 
6075 		DBPRINT(sc, BCE_INFO_SEND,
6076 			"%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6077 			"sw_tx_chain_cons = 0x%04X\n",
6078 			__FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6079 
6080 		DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
6081 			BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6082 				" 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6083 				(int) MAX_TX_BD);
6084 			bce_breakpoint(sc));
6085 
6086 		DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6087 				[TX_IDX(sw_tx_chain_cons)]);
6088 
6089 		DBRUNIF((txbd == NULL),
6090 			BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6091 				__FILE__, __LINE__, sw_tx_chain_cons);
6092 			bce_breakpoint(sc));
6093 
6094 		DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6095 			bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6096 
6097 		/*
6098 		 * Free the associated mbuf. Remember
6099 		 * that only the last tx_bd of a packet
6100 		 * has an mbuf pointer and DMA map.
6101 		 */
6102 		if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6103 
6104 			/* Validate that this is the last tx_bd. */
6105 			DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6106 				BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6107 				"txmbuf == NULL!\n", __FILE__, __LINE__);
6108 				bce_breakpoint(sc));
6109 
6110 			DBRUNMSG(BCE_INFO_SEND,
6111 				BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6112 					"from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons));
6113 
6114 			/* Unmap the mbuf. */
6115 			bus_dmamap_unload(sc->tx_mbuf_tag,
6116 			    sc->tx_mbuf_map[sw_tx_chain_cons]);
6117 
6118 			/* Free the mbuf. */
6119 			m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6120 			sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6121 			DBRUN(sc->debug_tx_mbuf_alloc--);
6122 
6123 			ifp->if_opackets++;
6124 		}
6125 
6126 		sc->used_tx_bd--;
6127 		sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
6128 
6129 		/* Refresh hw_cons to see if there's new work. */
6130 		hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6131 
6132 		/* Prevent speculative reads from getting ahead of the status block. */
6133 		bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6134 			BUS_SPACE_BARRIER_READ);
6135 	}
6136 
6137 	/* Clear the TX timeout timer. */
6138 	sc->watchdog_timer = 0;
6139 
6140 	/* Clear the tx hardware queue full flag. */
6141 	if (sc->used_tx_bd < sc->max_tx_bd) {
6142 		DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
6143 			DBPRINT(sc, BCE_INFO_SEND,
6144 				"%s(): Open TX chain! %d/%d (used/total)\n",
6145 				__FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
6146 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6147 	}
6148 
6149 	sc->tx_cons = sw_tx_cons;
6150 
6151 	DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
6152 		"tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6153 		__FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6154 	DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6155 }
6156 
6157 
6158 /****************************************************************************/
6159 /* Disables interrupt generation.                                           */
6160 /*                                                                          */
6161 /* Returns:                                                                 */
6162 /*   Nothing.                                                               */
6163 /****************************************************************************/
6164 static void
6165 bce_disable_intr(struct bce_softc *sc)
6166 {
6167 	DBENTER(BCE_VERBOSE_INTR);
6168 
6169 	REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
6170 	REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
6171 
6172 	DBEXIT(BCE_VERBOSE_INTR);
6173 }
6174 
6175 
6176 /****************************************************************************/
6177 /* Enables interrupt generation.                                            */
6178 /*                                                                          */
6179 /* Returns:                                                                 */
6180 /*   Nothing.                                                               */
6181 /****************************************************************************/
6182 static void
6183 bce_enable_intr(struct bce_softc *sc, int coal_now)
6184 {
6185 	DBENTER(BCE_VERBOSE_INTR);
6186 
6187 	REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6188 	       BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
6189 	       BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
6190 
6191 	REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6192 	       BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
6193 
6194 	/* Force an immediate interrupt (whether there is new data or not). */
6195 	if (coal_now)
6196 		REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
6197 
6198 	DBEXIT(BCE_VERBOSE_INTR);
6199 }
6200 
6201 
6202 /****************************************************************************/
6203 /* Handles controller initialization.                                       */
6204 /*                                                                          */
6205 /* Returns:                                                                 */
6206 /*   Nothing.                                                               */
6207 /****************************************************************************/
6208 static void
6209 bce_init_locked(struct bce_softc *sc)
6210 {
6211 	struct ifnet *ifp;
6212 	u32 ether_mtu = 0;
6213 
6214 	DBENTER(BCE_VERBOSE_RESET);
6215 
6216 	BCE_LOCK_ASSERT(sc);
6217 
6218 	ifp = sc->bce_ifp;
6219 
6220 	/* Check if the driver is still running and bail out if it is. */
6221 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6222 		goto bce_init_locked_exit;
6223 
6224 	bce_stop(sc);
6225 
6226 	if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
6227 		BCE_PRINTF("%s(%d): Controller reset failed!\n",
6228 			__FILE__, __LINE__);
6229 		goto bce_init_locked_exit;
6230 	}
6231 
6232 	if (bce_chipinit(sc)) {
6233 		BCE_PRINTF("%s(%d): Controller initialization failed!\n",
6234 			__FILE__, __LINE__);
6235 		goto bce_init_locked_exit;
6236 	}
6237 
6238 	if (bce_blockinit(sc)) {
6239 		BCE_PRINTF("%s(%d): Block initialization failed!\n",
6240 			__FILE__, __LINE__);
6241 		goto bce_init_locked_exit;
6242 	}
6243 
6244 	/* Load our MAC address. */
6245 	bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
6246 	bce_set_mac_addr(sc);
6247 
6248 	/*
6249 	 * Calculate and program the hardware Ethernet MTU
6250 	 * size. Be generous on the receive if we have room.
6251 	 */
6252 #ifdef BCE_USE_SPLIT_HEADER
6253 	if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + sc->pg_bd_mbuf_alloc_size))
6254 		ether_mtu = sc->rx_bd_mbuf_data_len + sc->pg_bd_mbuf_alloc_size;
6255 #else
6256 	if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
6257 		ether_mtu = sc->rx_bd_mbuf_data_len;
6258 #endif
6259 	else
6260 		ether_mtu = ifp->if_mtu;
6261 
6262 	ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
6263 
6264 	DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", __FUNCTION__,
6265 		ether_mtu);
6266 
6267 	/* Program the mtu, enabling jumbo frame support if necessary. */
6268 	if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
6269 		REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
6270 			min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
6271 			BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
6272 	else
6273 		REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
6274 
6275 	DBPRINT(sc, BCE_INFO_LOAD,
6276 		"%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, "
6277 		"rx_bd_mbuf_align_pad = %d, pg_bd_mbuf_alloc_size = %d\n",
6278 		__FUNCTION__, sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
6279 		sc->rx_bd_mbuf_align_pad, sc->pg_bd_mbuf_alloc_size);
6280 
6281 	/* Program appropriate promiscuous/multicast filtering. */
6282 	bce_set_rx_mode(sc);
6283 
6284 #ifdef BCE_USE_SPLIT_HEADER
6285 	/* Init page buffer descriptor chain. */
6286 	bce_init_pg_chain(sc);
6287 #endif
6288 
6289 	/* Init RX buffer descriptor chain. */
6290 	bce_init_rx_chain(sc);
6291 
6292 	/* Init TX buffer descriptor chain. */
6293 	bce_init_tx_chain(sc);
6294 
6295 	/* Enable host interrupts. */
6296 	bce_enable_intr(sc, 1);
6297 
6298 	bce_ifmedia_upd_locked(ifp);
6299 
6300 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
6301 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6302 
6303 	callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
6304 
6305 bce_init_locked_exit:
6306 	DBEXIT(BCE_VERBOSE_RESET);
6307 }
6308 
6309 
6310 /****************************************************************************/
6311 /* Initialize the controller just enough so that any management firmware    */
6312 /* running on the device will continue to operate correctly.                */
6313 /*                                                                          */
6314 /* Returns:                                                                 */
6315 /*   Nothing.                                                               */
6316 /****************************************************************************/
6317 static void
6318 bce_mgmt_init_locked(struct bce_softc *sc)
6319 {
6320 	struct ifnet *ifp;
6321 
6322 	DBENTER(BCE_VERBOSE_RESET);
6323 
6324 	BCE_LOCK_ASSERT(sc);
6325 
6326 	/* Bail out if management firmware is not running. */
6327 	if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
6328 		DBPRINT(sc, BCE_VERBOSE_SPECIAL,
6329 			"No management firmware running...\n");
6330 		goto bce_mgmt_init_locked_exit;
6331 	}
6332 
6333 	ifp = sc->bce_ifp;
6334 
6335 	/* Enable all critical blocks in the MAC. */
6336 	REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
6337 	REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
6338 	DELAY(20);
6339 
6340 	bce_ifmedia_upd_locked(ifp);
6341 
6342 bce_mgmt_init_locked_exit:
6343 	DBEXIT(BCE_VERBOSE_RESET);
6344 }
6345 
6346 
6347 /****************************************************************************/
6348 /* Handles controller initialization when called from an unlocked routine.  */
6349 /*                                                                          */
6350 /* Returns:                                                                 */
6351 /*   Nothing.                                                               */
6352 /****************************************************************************/
6353 static void
6354 bce_init(void *xsc)
6355 {
6356 	struct bce_softc *sc = xsc;
6357 
6358 	DBENTER(BCE_VERBOSE_RESET);
6359 
6360 	BCE_LOCK(sc);
6361 	bce_init_locked(sc);
6362 	BCE_UNLOCK(sc);
6363 
6364 	DBEXIT(BCE_VERBOSE_RESET);
6365 }
6366 
6367 
6368 /****************************************************************************/
6369 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
6370 /* memory visible to the controller.                                        */
6371 /*                                                                          */
6372 /* Returns:                                                                 */
6373 /*   0 for success, positive value for failure.                             */
6374 /* Modified:                                                                */
6375 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
6376 /****************************************************************************/
6377 static int
6378 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
6379 {
6380 	bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
6381 	bus_dmamap_t map;
6382 	struct tx_bd *txbd = NULL;
6383 	struct mbuf *m0;
6384 	struct ether_vlan_header *eh;
6385 	struct ip *ip;
6386 	struct tcphdr *th;
6387 	u16 prod, chain_prod, etype, mss = 0, vlan_tag = 0, flags = 0;
6388 	u32 prod_bseq;
6389 	int hdr_len = 0, e_hlen = 0, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
6390 
6391 #ifdef BCE_DEBUG
6392 	u16 debug_prod;
6393 #endif
6394 	int i, error, nsegs, rc = 0;
6395 
6396 	DBENTER(BCE_VERBOSE_SEND);
6397 	DBPRINT(sc, BCE_INFO_SEND,
6398 		"%s(enter): tx_prod = 0x%04X, tx_chain_prod = %04X, "
6399 		"tx_prod_bseq = 0x%08X\n",
6400 		__FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod),
6401 		sc->tx_prod_bseq);
6402 
6403 	/* Transfer any checksum offload flags to the bd. */
6404 	m0 = *m_head;
6405 	if (m0->m_pkthdr.csum_flags) {
6406 		if (m0->m_pkthdr.csum_flags & CSUM_IP)
6407 			flags |= TX_BD_FLAGS_IP_CKSUM;
6408 		if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
6409 			flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6410 		if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
6411 			/* For TSO the controller needs two pieces of info, */
6412 			/* the MSS and the IP+TCP options length.           */
6413 			mss = htole16(m0->m_pkthdr.tso_segsz);
6414 
6415 			/* Map the header and find the Ethernet type & header length */
6416 			eh = mtod(m0, struct ether_vlan_header *);
6417 			if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
6418 				etype = ntohs(eh->evl_proto);
6419 				e_hlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
6420 			} else {
6421 				etype = ntohs(eh->evl_encap_proto);
6422 				e_hlen = ETHER_HDR_LEN;
6423 			}
6424 
6425 			/* Check for supported TSO Ethernet types (only IPv4 for now) */
6426 			switch (etype) {
6427 				case ETHERTYPE_IP:
6428 					ip = (struct ip *)(m0->m_data + e_hlen);
6429 
6430 					/* TSO only supported for TCP protocol */
6431 					if (ip->ip_p != IPPROTO_TCP) {
6432 						BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
6433 							__FILE__, __LINE__);
6434 						goto bce_tx_encap_skip_tso;
6435 					}
6436 
6437 					/* Get IP header length in bytes (min 20) */
6438 					ip_hlen = ip->ip_hl << 2;
6439 
6440 					/* Get the TCP header length in bytes (min 20) */
6441 					th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
6442 					tcp_hlen = (th->th_off << 2);
6443 
6444 					/* IP header length and checksum will be calc'd by hardware */
6445 					ip_len = ip->ip_len;
6446 					ip->ip_len = 0;
6447 					ip->ip_sum = 0;
6448 					break;
6449 				case ETHERTYPE_IPV6:
6450 					BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
6451 						__FILE__, __LINE__);
6452 					goto bce_tx_encap_skip_tso;
6453 				default:
6454 					BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
6455 						__FILE__, __LINE__);
6456 					goto bce_tx_encap_skip_tso;
6457 			}
6458 
6459 			hdr_len = e_hlen + ip_hlen + tcp_hlen;
6460 
6461 			DBPRINT(sc, BCE_EXTREME_SEND,
6462 				"%s(): hdr_len = %d, e_hlen = %d, ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
6463 				 __FUNCTION__, hdr_len, e_hlen, ip_hlen, tcp_hlen, ip_len);
6464 
6465 			/* Set the LSO flag in the TX BD */
6466 			flags |= TX_BD_FLAGS_SW_LSO;
6467 			/* Set the length of IP + TCP options (in 32 bit words) */
6468 			flags |= (((ip_hlen + tcp_hlen - 40) >> 2) << 8);
6469 
6470 bce_tx_encap_skip_tso:
6471 			DBRUN(sc->requested_tso_frames++);
6472 		}
6473 	}
6474 
6475 	/* Transfer any VLAN tags to the bd. */
6476 	if (m0->m_flags & M_VLANTAG) {
6477 		flags |= TX_BD_FLAGS_VLAN_TAG;
6478 		vlan_tag = m0->m_pkthdr.ether_vtag;
6479 	}
6480 
6481 	/* Map the mbuf into DMAable memory. */
6482 	prod = sc->tx_prod;
6483 	chain_prod = TX_CHAIN_IDX(prod);
6484 	map = sc->tx_mbuf_map[chain_prod];
6485 
6486 	/* Map the mbuf into our DMA address space. */
6487 	error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6488 	    segs, &nsegs, BUS_DMA_NOWAIT);
6489 
6490 	/* Check if the DMA mapping was successful */
6491 	if (error == EFBIG) {
6492 
6493 		/* The mbuf is too fragmented for our DMA mapping. */
6494    		DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n",
6495 			__FUNCTION__, nsegs);
6496 		DBRUN(bce_dump_mbuf(sc, m0););
6497 
6498 		/* Try to defrag the mbuf. */
6499 		m0 = m_defrag(*m_head, M_DONTWAIT);
6500 		if (m0 == NULL) {
6501 			/* Defrag was unsuccessful */
6502 			m_freem(*m_head);
6503 			*m_head = NULL;
6504 			sc->mbuf_alloc_failed++;
6505 			rc = ENOBUFS;
6506 			goto bce_tx_encap_exit;
6507 		}
6508 
6509 		/* Defrag was successful, try mapping again */
6510 		*m_head = m0;
6511 		error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6512 		    segs, &nsegs, BUS_DMA_NOWAIT);
6513 
6514 		/* Still getting an error after a defrag. */
6515 		if (error == ENOMEM) {
6516 			/* Insufficient DMA buffers available. */
6517 			sc->tx_dma_map_failures++;
6518 			rc = error;
6519 			goto bce_tx_encap_exit;
6520 		} else if (error != 0) {
6521 			/* Still can't map the mbuf, release it and return an error. */
6522 			BCE_PRINTF(
6523 			    "%s(%d): Unknown error mapping mbuf into TX chain!\n",
6524 			    __FILE__, __LINE__);
6525 			m_freem(m0);
6526 			*m_head = NULL;
6527 			sc->tx_dma_map_failures++;
6528 			rc = ENOBUFS;
6529 			goto bce_tx_encap_exit;
6530 		}
6531 	} else if (error == ENOMEM) {
6532 		/* Insufficient DMA buffers available. */
6533 		sc->tx_dma_map_failures++;
6534 		rc = error;
6535 		goto bce_tx_encap_exit;
6536 	} else if (error != 0) {
6537 		m_freem(m0);
6538 		*m_head = NULL;
6539 		sc->tx_dma_map_failures++;
6540 		rc = error;
6541 		goto bce_tx_encap_exit;
6542 	}
6543 
6544 	/* Make sure there's room in the chain */
6545 	if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
6546 		bus_dmamap_unload(sc->tx_mbuf_tag, map);
6547 		rc = ENOBUFS;
6548 		goto bce_tx_encap_exit;
6549 	}
6550 
6551 	/* prod points to an empty tx_bd at this point. */
6552 	prod_bseq  = sc->tx_prod_bseq;
6553 
6554 #ifdef BCE_DEBUG
6555 	debug_prod = chain_prod;
6556 #endif
6557 
6558 	DBPRINT(sc, BCE_INFO_SEND,
6559 		"%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
6560 		"prod_bseq = 0x%08X\n",
6561 		__FUNCTION__, prod, chain_prod, prod_bseq);
6562 
6563 	/*
6564 	 * Cycle through each mbuf segment that makes up
6565 	 * the outgoing frame, gathering the mapping info
6566 	 * for that segment and creating a tx_bd for
6567 	 * the mbuf.
6568 	 */
6569 	for (i = 0; i < nsegs ; i++) {
6570 
6571 		chain_prod = TX_CHAIN_IDX(prod);
6572 		txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
6573 
6574 		txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
6575 		txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
6576 		txbd->tx_bd_mss_nbytes = htole32(mss << 16) | htole16(segs[i].ds_len);
6577 		txbd->tx_bd_vlan_tag = htole16(vlan_tag);
6578 		txbd->tx_bd_flags = htole16(flags);
6579 		prod_bseq += segs[i].ds_len;
6580 		if (i == 0)
6581 			txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
6582 		prod = NEXT_TX_BD(prod);
6583 	}
6584 
6585 	/* Set the END flag on the last TX buffer descriptor. */
6586 	txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
6587 
6588 	DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs));
6589 
6590 	DBPRINT(sc, BCE_INFO_SEND,
6591 		"%s( end ): prod = 0x%04X, chain_prod = 0x%04X, "
6592 		"prod_bseq = 0x%08X\n",
6593 		__FUNCTION__, prod, chain_prod, prod_bseq);
6594 
6595 	/*
6596 	 * Ensure that the mbuf pointer for this transmission
6597 	 * is placed at the array index of the last
6598 	 * descriptor in this chain.  This is done
6599 	 * because a single map is used for all
6600 	 * segments of the mbuf and we don't want to
6601 	 * unload the map before all of the segments
6602 	 * have been freed.
6603 	 */
6604 	sc->tx_mbuf_ptr[chain_prod] = m0;
6605 	sc->used_tx_bd += nsegs;
6606 
6607 	/* Update some debug statistic counters */
6608 	DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
6609 		sc->tx_hi_watermark = sc->used_tx_bd);
6610 	DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
6611 	DBRUNIF(sc->debug_tx_mbuf_alloc++);
6612 
6613 	DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
6614 
6615 	/* prod points to the next free tx_bd at this point. */
6616 	sc->tx_prod = prod;
6617 	sc->tx_prod_bseq = prod_bseq;
6618 
6619 	DBPRINT(sc, BCE_INFO_SEND,
6620 		"%s(exit): prod = 0x%04X, chain_prod = %04X, "
6621 		"prod_bseq = 0x%08X\n",
6622 		__FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod),
6623 		sc->tx_prod_bseq);
6624 
6625 bce_tx_encap_exit:
6626 	DBEXIT(BCE_VERBOSE_SEND);
6627 	return(rc);
6628 }
6629 
6630 
6631 /****************************************************************************/
6632 /* Main transmit routine when called from another routine with a lock.      */
6633 /*                                                                          */
6634 /* Returns:                                                                 */
6635 /*   Nothing.                                                               */
6636 /****************************************************************************/
6637 static void
6638 bce_start_locked(struct ifnet *ifp)
6639 {
6640 	struct bce_softc *sc = ifp->if_softc;
6641 	struct mbuf *m_head = NULL;
6642 	int count = 0;
6643 	u16 tx_prod, tx_chain_prod;
6644 
6645 	DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
6646 
6647 	BCE_LOCK_ASSERT(sc);
6648 
6649 	/* prod points to the next free tx_bd. */
6650 	tx_prod = sc->tx_prod;
6651 	tx_chain_prod = TX_CHAIN_IDX(tx_prod);
6652 
6653 	DBPRINT(sc, BCE_INFO_SEND,
6654 		"%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
6655 		"tx_prod_bseq = 0x%08X\n",
6656 		__FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
6657 
6658 	/* If there's no link or the transmit queue is empty then just exit. */
6659 	if (!sc->bce_link) {
6660 		DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
6661 			__FUNCTION__);
6662 		goto bce_start_locked_exit;
6663 	}
6664 
6665 	if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
6666 		DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
6667 			__FUNCTION__);
6668 		goto bce_start_locked_exit;
6669 	}
6670 
6671 	/*
6672 	 * Keep adding entries while there is space in the ring.
6673 	 */
6674 	while (sc->used_tx_bd < sc->max_tx_bd) {
6675 
6676 		/* Check for any frames to send. */
6677 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
6678 
6679 		/* Stop when the transmit queue is empty. */
6680 		if (m_head == NULL)
6681 			break;
6682 
6683 		/*
6684 		 * Pack the data into the transmit ring. If we
6685 		 * don't have room, place the mbuf back at the
6686 		 * head of the queue and set the OACTIVE flag
6687 		 * to wait for the NIC to drain the chain.
6688 		 */
6689 		if (bce_tx_encap(sc, &m_head)) {
6690 			/* No room, put the frame back on the transmit queue. */
6691 			if (m_head != NULL)
6692 				IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
6693 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
6694 			DBPRINT(sc, BCE_INFO_SEND,
6695 				"TX chain is closed for business! Total tx_bd used = %d\n",
6696 				sc->used_tx_bd);
6697 			break;
6698 		}
6699 
6700 		count++;
6701 
6702 		/* Send a copy of the frame to any BPF listeners. */
6703 		ETHER_BPF_MTAP(ifp, m_head);
6704 	}
6705 
6706 	/* Exit if no packets were dequeued. */
6707 	if (count == 0) {
6708 		DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n",
6709 			__FUNCTION__);
6710 		goto bce_start_locked_exit;
6711 	}
6712 
6713 	DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into send queue.\n",
6714 		__FUNCTION__, count);
6715 
6716 	REG_WR(sc, BCE_MQ_COMMAND, REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
6717 
6718 	/* Write the mailbox and tell the chip about the waiting tx_bd's. */
6719 	DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; "
6720 		"BCE_L2MQ_TX_HOST_BIDX = 0x%08X, sc->tx_prod = 0x%04X\n",
6721 		__FUNCTION__,
6722 		MB_GET_CID_ADDR(TX_CID), BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
6723 	REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
6724 	DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; "
6725 		"BCE_L2MQ_TX_HOST_BSEQ = 0x%08X, sc->tx_prod_bseq = 0x%04X\n",
6726 		__FUNCTION__,
6727 		MB_GET_CID_ADDR(TX_CID), BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
6728 	REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
6729 
6730 	/* Set the tx timeout. */
6731 	sc->watchdog_timer = BCE_TX_TIMEOUT;
6732 
6733 	DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
6734 	DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
6735 
6736 bce_start_locked_exit:
6737 	DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
6738 	return;
6739 }
6740 
6741 
6742 /****************************************************************************/
6743 /* Main transmit routine when called from another routine without a lock.   */
6744 /*                                                                          */
6745 /* Returns:                                                                 */
6746 /*   Nothing.                                                               */
6747 /****************************************************************************/
6748 static void
6749 bce_start(struct ifnet *ifp)
6750 {
6751 	struct bce_softc *sc = ifp->if_softc;
6752 
6753 	DBENTER(BCE_VERBOSE_SEND);
6754 
6755 	BCE_LOCK(sc);
6756 	bce_start_locked(ifp);
6757 	BCE_UNLOCK(sc);
6758 
6759 	DBEXIT(BCE_VERBOSE_SEND);
6760 }
6761 
6762 
6763 /****************************************************************************/
6764 /* Handles any IOCTL calls from the operating system.                       */
6765 /*                                                                          */
6766 /* Returns:                                                                 */
6767 /*   0 for success, positive value for failure.                             */
6768 /****************************************************************************/
6769 static int
6770 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
6771 {
6772 	struct bce_softc *sc = ifp->if_softc;
6773 	struct ifreq *ifr = (struct ifreq *) data;
6774 	struct mii_data *mii;
6775 	int mask, error = 0;
6776 
6777 	DBENTER(BCE_VERBOSE_MISC);
6778 
6779 	switch(command) {
6780 
6781 		/* Set the interface MTU. */
6782 		case SIOCSIFMTU:
6783 			/* Check that the MTU setting is supported. */
6784 			if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
6785 				(ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
6786 				error = EINVAL;
6787 				break;
6788 			}
6789 
6790 			DBPRINT(sc, BCE_INFO_MISC,
6791 				"SIOCSIFMTU: Changing MTU from %d to %d\n",
6792 				(int) ifp->if_mtu, (int) ifr->ifr_mtu);
6793 
6794 			BCE_LOCK(sc);
6795 			ifp->if_mtu = ifr->ifr_mtu;
6796 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
6797 #ifdef BCE_USE_SPLIT_HEADER
6798 			/* No buffer allocation size changes are necessary. */
6799 #else
6800 			/* Recalculate our buffer allocation sizes. */
6801 			if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN) > MCLBYTES) {
6802 				sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
6803 				sc->rx_bd_mbuf_align_pad  = roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
6804 				sc->rx_bd_mbuf_data_len   = sc->rx_bd_mbuf_alloc_size -
6805 					sc->rx_bd_mbuf_align_pad;
6806 			} else {
6807 				sc->rx_bd_mbuf_alloc_size = MCLBYTES;
6808 				sc->rx_bd_mbuf_align_pad  = roundup2(MCLBYTES, 16) - MCLBYTES;
6809 				sc->rx_bd_mbuf_data_len   = sc->rx_bd_mbuf_alloc_size -
6810 					sc->rx_bd_mbuf_align_pad;
6811 			}
6812 #endif
6813 
6814 			bce_init_locked(sc);
6815 			BCE_UNLOCK(sc);
6816 			break;
6817 
6818 		/* Set interface flags. */
6819 		case SIOCSIFFLAGS:
6820 			DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
6821 
6822 			BCE_LOCK(sc);
6823 
6824 			/* Check if the interface is up. */
6825 			if (ifp->if_flags & IFF_UP) {
6826 				if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
6827 					/* Change promiscuous/multicast flags as necessary. */
6828 					bce_set_rx_mode(sc);
6829 				} else {
6830 					/* Start the HW */
6831 					bce_init_locked(sc);
6832 				}
6833 			} else {
6834 				/* The interface is down, check if driver is running. */
6835 				if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
6836 					bce_stop(sc);
6837 
6838 					/* If MFW is running, restart the controller a bit. */
6839 					if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
6840 						bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
6841 						bce_chipinit(sc);
6842 						bce_mgmt_init_locked(sc);
6843 					}
6844 				}
6845 			}
6846 
6847 			BCE_UNLOCK(sc);
6848 			error = 0;
6849 
6850 			break;
6851 
6852 		/* Add/Delete multicast address */
6853 		case SIOCADDMULTI:
6854 		case SIOCDELMULTI:
6855 			DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCADDMULTI/SIOCDELMULTI\n");
6856 
6857 			BCE_LOCK(sc);
6858 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
6859 				bce_set_rx_mode(sc);
6860 				error = 0;
6861 			}
6862 			BCE_UNLOCK(sc);
6863 
6864 			break;
6865 
6866 		/* Set/Get Interface media */
6867 		case SIOCSIFMEDIA:
6868 		case SIOCGIFMEDIA:
6869 			DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
6870 
6871 			mii = device_get_softc(sc->bce_miibus);
6872 			error = ifmedia_ioctl(ifp, ifr,
6873 			    &mii->mii_media, command);
6874 			break;
6875 
6876 		/* Set interface capability */
6877 		case SIOCSIFCAP:
6878 			mask = ifr->ifr_reqcap ^ ifp->if_capenable;
6879 			DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
6880 
6881 			/* Toggle the TX checksum capabilites enable flag. */
6882 			if (mask & IFCAP_TXCSUM) {
6883 				ifp->if_capenable ^= IFCAP_TXCSUM;
6884 				if (IFCAP_TXCSUM & ifp->if_capenable)
6885 					ifp->if_hwassist = BCE_IF_HWASSIST;
6886 				else
6887 					ifp->if_hwassist = 0;
6888 			}
6889 
6890 			/* Toggle the RX checksum capabilities enable flag. */
6891 			if (mask & IFCAP_RXCSUM) {
6892 				ifp->if_capenable ^= IFCAP_RXCSUM;
6893 				if (IFCAP_RXCSUM & ifp->if_capenable)
6894 					ifp->if_hwassist = BCE_IF_HWASSIST;
6895 				else
6896 					ifp->if_hwassist = 0;
6897 			}
6898 
6899 			/* Toggle the TSO capabilities enable flag. */
6900 			if (bce_tso_enable && (mask & IFCAP_TSO4)) {
6901 				ifp->if_capenable ^= IFCAP_TSO4;
6902 				if (IFCAP_RXCSUM & ifp->if_capenable)
6903 					ifp->if_hwassist = BCE_IF_HWASSIST;
6904 				else
6905 					ifp->if_hwassist = 0;
6906 			}
6907 
6908 			/* Toggle VLAN_MTU capabilities enable flag. */
6909 			if (mask & IFCAP_VLAN_MTU) {
6910 				BCE_PRINTF("%s(%d): Changing VLAN_MTU not supported.\n",
6911 					__FILE__, __LINE__);
6912 			}
6913 
6914 			/* Toggle VLANHWTAG capabilities enabled flag. */
6915 			if (mask & IFCAP_VLAN_HWTAGGING) {
6916 				if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
6917 					BCE_PRINTF("%s(%d): Cannot change VLAN_HWTAGGING while "
6918 						"management firmware (ASF/IPMI/UMP) is running!\n",
6919 						__FILE__, __LINE__);
6920 				else
6921 					BCE_PRINTF("%s(%d): Changing VLAN_HWTAGGING not supported!\n",
6922 						__FILE__, __LINE__);
6923 			}
6924 
6925 			break;
6926 		default:
6927 			/* We don't know how to handle the IOCTL, pass it on. */
6928 			error = ether_ioctl(ifp, command, data);
6929 			break;
6930 	}
6931 
6932 	DBEXIT(BCE_VERBOSE_MISC);
6933 	return(error);
6934 }
6935 
6936 
6937 /****************************************************************************/
6938 /* Transmit timeout handler.                                                */
6939 /*                                                                          */
6940 /* Returns:                                                                 */
6941 /*   Nothing.                                                               */
6942 /****************************************************************************/
6943 static void
6944 bce_watchdog(struct bce_softc *sc)
6945 {
6946 	DBENTER(BCE_EXTREME_SEND);
6947 
6948 	BCE_LOCK_ASSERT(sc);
6949 
6950 	/* If the watchdog timer hasn't expired then just exit. */
6951 	if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
6952 		goto bce_watchdog_exit;
6953 
6954 	/* If pause frames are active then don't reset the hardware. */
6955 	/* ToDo: Should we reset the timer here? */
6956 	if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
6957 		goto bce_watchdog_exit;
6958 
6959 	BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
6960 		__FILE__, __LINE__);
6961 
6962 	DBRUNMSG(BCE_INFO,
6963 		bce_dump_driver_state(sc);
6964 		bce_dump_status_block(sc);
6965 		bce_dump_stats_block(sc);
6966 		bce_dump_ftqs(sc);
6967 		bce_dump_txp_state(sc, 0);
6968 		bce_dump_rxp_state(sc, 0);
6969 		bce_dump_tpat_state(sc, 0);
6970 		bce_dump_cp_state(sc, 0);
6971 		bce_dump_com_state(sc, 0));
6972 
6973 	DBRUN(bce_breakpoint(sc));
6974 
6975 	sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
6976 
6977 	bce_init_locked(sc);
6978 	sc->bce_ifp->if_oerrors++;
6979 
6980 bce_watchdog_exit:
6981 	DBEXIT(BCE_EXTREME_SEND);
6982 }
6983 
6984 
6985 /*
6986  * Interrupt handler.
6987  */
6988 /****************************************************************************/
6989 /* Main interrupt entry point.  Verifies that the controller generated the  */
6990 /* interrupt and then calls a separate routine for handle the various       */
6991 /* interrupt causes (PHY, TX, RX).                                          */
6992 /*                                                                          */
6993 /* Returns:                                                                 */
6994 /*   0 for success, positive value for failure.                             */
6995 /****************************************************************************/
6996 static void
6997 bce_intr(void *xsc)
6998 {
6999 	struct bce_softc *sc;
7000 	struct ifnet *ifp;
7001 	u32 status_attn_bits;
7002 	u16 hw_rx_cons, hw_tx_cons;
7003 
7004 	sc = xsc;
7005 	ifp = sc->bce_ifp;
7006 
7007 	DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7008 	DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7009 
7010 	BCE_LOCK(sc);
7011 
7012 	DBRUN(sc->interrupts_generated++);
7013 
7014 	bus_dmamap_sync(sc->status_tag, sc->status_map,
7015 	    BUS_DMASYNC_POSTWRITE);
7016 
7017 	/*
7018 	 * If the hardware status block index
7019 	 * matches the last value read by the
7020 	 * driver and we haven't asserted our
7021 	 * interrupt then there's nothing to do.
7022 	 */
7023 	if ((sc->status_block->status_idx == sc->last_status_idx) &&
7024 		(REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7025 			DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7026 				__FUNCTION__);
7027 			goto bce_intr_exit;
7028 	}
7029 
7030 	/* Ack the interrupt and stop others from occuring. */
7031 	REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7032 		BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7033 		BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7034 
7035 	/* Check if the hardware has finished any work. */
7036 	hw_rx_cons = bce_get_hw_rx_cons(sc);
7037 	hw_tx_cons = bce_get_hw_tx_cons(sc);
7038 
7039 	/* Keep processing data as long as there is work to do. */
7040 	for (;;) {
7041 
7042 		status_attn_bits = sc->status_block->status_attn_bits;
7043 
7044 		DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
7045 			BCE_PRINTF("Simulating unexpected status attention bit set.");
7046 			status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR);
7047 
7048 		/* Was it a link change interrupt? */
7049 		if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7050 			(sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
7051 			bce_phy_intr(sc);
7052 
7053 			/* Clear any transient status updates during link state change. */
7054 			REG_WR(sc, BCE_HC_COMMAND,
7055 				sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
7056 			REG_RD(sc, BCE_HC_COMMAND);
7057 		}
7058 
7059 		/* If any other attention is asserted then the chip is toast. */
7060 		if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7061 			(sc->status_block->status_attn_bits_ack &
7062 			~STATUS_ATTN_BITS_LINK_STATE))) {
7063 
7064 			DBRUN(sc->unexpected_attentions++);
7065 
7066 			BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n",
7067 				__FILE__, __LINE__, sc->status_block->status_attn_bits);
7068 
7069 			DBRUNMSG(BCE_FATAL,
7070 				if (bce_debug_unexpected_attention == 0)
7071 					bce_breakpoint(sc));
7072 
7073 			bce_init_locked(sc);
7074 			goto bce_intr_exit;
7075 		}
7076 
7077 		/* Check for any completed RX frames. */
7078 		if (hw_rx_cons != sc->hw_rx_cons)
7079 			bce_rx_intr(sc);
7080 
7081 		/* Check for any completed TX frames. */
7082 		if (hw_tx_cons != sc->hw_tx_cons)
7083 			bce_tx_intr(sc);
7084 
7085 		/* Save the status block index value for use during the next interrupt. */
7086 		sc->last_status_idx = sc->status_block->status_idx;
7087 
7088 		/* Prevent speculative reads from getting ahead of the status block. */
7089 		bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7090 			BUS_SPACE_BARRIER_READ);
7091 
7092 		/* If there's no work left then exit the interrupt service routine. */
7093 		hw_rx_cons = bce_get_hw_rx_cons(sc);
7094 		hw_tx_cons = bce_get_hw_tx_cons(sc);
7095 
7096 		if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
7097 			break;
7098 
7099 	}
7100 
7101 	bus_dmamap_sync(sc->status_tag,	sc->status_map,
7102 	    BUS_DMASYNC_PREWRITE);
7103 
7104 	/* Re-enable interrupts. */
7105 	bce_enable_intr(sc, 0);
7106 
7107 	/* Handle any frames that arrived while handling the interrupt. */
7108 	if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
7109 		bce_start_locked(ifp);
7110 
7111 bce_intr_exit:
7112 	BCE_UNLOCK(sc);
7113 
7114 	DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7115 }
7116 
7117 
7118 /****************************************************************************/
7119 /* Programs the various packet receive modes (broadcast and multicast).     */
7120 /*                                                                          */
7121 /* Returns:                                                                 */
7122 /*   Nothing.                                                               */
7123 /****************************************************************************/
7124 static void
7125 bce_set_rx_mode(struct bce_softc *sc)
7126 {
7127 	struct ifnet *ifp;
7128 	struct ifmultiaddr *ifma;
7129 	u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
7130 	u32 rx_mode, sort_mode;
7131 	int h, i;
7132 
7133 	DBENTER(BCE_VERBOSE_MISC);
7134 
7135 	BCE_LOCK_ASSERT(sc);
7136 
7137 	ifp = sc->bce_ifp;
7138 
7139 	/* Initialize receive mode default settings. */
7140 	rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
7141 			    BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
7142 	sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
7143 
7144 	/*
7145 	 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
7146 	 * be enbled.
7147 	 */
7148 	if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
7149 		(!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
7150 		rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
7151 
7152 	/*
7153 	 * Check for promiscuous, all multicast, or selected
7154 	 * multicast address filtering.
7155 	 */
7156 	if (ifp->if_flags & IFF_PROMISC) {
7157 		DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
7158 
7159 		/* Enable promiscuous mode. */
7160 		rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
7161 		sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
7162 	} else if (ifp->if_flags & IFF_ALLMULTI) {
7163 		DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
7164 
7165 		/* Enable all multicast addresses. */
7166 		for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
7167 			REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff);
7168        	}
7169 		sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
7170 	} else {
7171 		/* Accept one or more multicast(s). */
7172 		DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
7173 
7174 		IF_ADDR_LOCK(ifp);
7175 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
7176 			if (ifma->ifma_addr->sa_family != AF_LINK)
7177 				continue;
7178 			h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
7179 			    ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
7180 			    hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
7181 		}
7182 		IF_ADDR_UNLOCK(ifp);
7183 
7184 		for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
7185 			REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
7186 
7187 		sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
7188 	}
7189 
7190 	/* Only make changes if the recive mode has actually changed. */
7191 	if (rx_mode != sc->rx_mode) {
7192 		DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: 0x%08X\n",
7193 			rx_mode);
7194 
7195 		sc->rx_mode = rx_mode;
7196 		REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
7197 	}
7198 
7199 	/* Disable and clear the exisitng sort before enabling a new sort. */
7200 	REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
7201 	REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
7202 	REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
7203 
7204 	DBEXIT(BCE_VERBOSE_MISC);
7205 }
7206 
7207 
7208 /****************************************************************************/
7209 /* Called periodically to updates statistics from the controllers           */
7210 /* statistics block.                                                        */
7211 /*                                                                          */
7212 /* Returns:                                                                 */
7213 /*   Nothing.                                                               */
7214 /****************************************************************************/
7215 static void
7216 bce_stats_update(struct bce_softc *sc)
7217 {
7218 	struct ifnet *ifp;
7219 	struct statistics_block *stats;
7220 
7221 	DBENTER(BCE_EXTREME_MISC);
7222 
7223 	ifp = sc->bce_ifp;
7224 
7225 	stats = (struct statistics_block *) sc->stats_block;
7226 
7227 	/*
7228 	 * Certain controllers don't report
7229 	 * carrier sense errors correctly.
7230 	 * See errata E11_5708CA0_1165.
7231 	 */
7232 	if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
7233 	    !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
7234 		ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
7235 
7236 	/*
7237 	 * Update the sysctl statistics from the
7238 	 * hardware statistics.
7239 	 */
7240 	sc->stat_IfHCInOctets =
7241 		((u64) stats->stat_IfHCInOctets_hi << 32) +
7242 		 (u64) stats->stat_IfHCInOctets_lo;
7243 
7244 	sc->stat_IfHCInBadOctets =
7245 		((u64) stats->stat_IfHCInBadOctets_hi << 32) +
7246 		 (u64) stats->stat_IfHCInBadOctets_lo;
7247 
7248 	sc->stat_IfHCOutOctets =
7249 		((u64) stats->stat_IfHCOutOctets_hi << 32) +
7250 		 (u64) stats->stat_IfHCOutOctets_lo;
7251 
7252 	sc->stat_IfHCOutBadOctets =
7253 		((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
7254 		 (u64) stats->stat_IfHCOutBadOctets_lo;
7255 
7256 	sc->stat_IfHCInUcastPkts =
7257 		((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
7258 		 (u64) stats->stat_IfHCInUcastPkts_lo;
7259 
7260 	sc->stat_IfHCInMulticastPkts =
7261 		((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
7262 		 (u64) stats->stat_IfHCInMulticastPkts_lo;
7263 
7264 	sc->stat_IfHCInBroadcastPkts =
7265 		((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
7266 		 (u64) stats->stat_IfHCInBroadcastPkts_lo;
7267 
7268 	sc->stat_IfHCOutUcastPkts =
7269 		((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
7270 		 (u64) stats->stat_IfHCOutUcastPkts_lo;
7271 
7272 	sc->stat_IfHCOutMulticastPkts =
7273 		((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
7274 		 (u64) stats->stat_IfHCOutMulticastPkts_lo;
7275 
7276 	sc->stat_IfHCOutBroadcastPkts =
7277 		((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
7278 		 (u64) stats->stat_IfHCOutBroadcastPkts_lo;
7279 
7280 	sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
7281 		stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
7282 
7283 	sc->stat_Dot3StatsCarrierSenseErrors =
7284 		stats->stat_Dot3StatsCarrierSenseErrors;
7285 
7286 	sc->stat_Dot3StatsFCSErrors =
7287 		stats->stat_Dot3StatsFCSErrors;
7288 
7289 	sc->stat_Dot3StatsAlignmentErrors =
7290 		stats->stat_Dot3StatsAlignmentErrors;
7291 
7292 	sc->stat_Dot3StatsSingleCollisionFrames =
7293 		stats->stat_Dot3StatsSingleCollisionFrames;
7294 
7295 	sc->stat_Dot3StatsMultipleCollisionFrames =
7296 		stats->stat_Dot3StatsMultipleCollisionFrames;
7297 
7298 	sc->stat_Dot3StatsDeferredTransmissions =
7299 		stats->stat_Dot3StatsDeferredTransmissions;
7300 
7301 	sc->stat_Dot3StatsExcessiveCollisions =
7302 		stats->stat_Dot3StatsExcessiveCollisions;
7303 
7304 	sc->stat_Dot3StatsLateCollisions =
7305 		stats->stat_Dot3StatsLateCollisions;
7306 
7307 	sc->stat_EtherStatsCollisions =
7308 		stats->stat_EtherStatsCollisions;
7309 
7310 	sc->stat_EtherStatsFragments =
7311 		stats->stat_EtherStatsFragments;
7312 
7313 	sc->stat_EtherStatsJabbers =
7314 		stats->stat_EtherStatsJabbers;
7315 
7316 	sc->stat_EtherStatsUndersizePkts =
7317 		stats->stat_EtherStatsUndersizePkts;
7318 
7319 	sc->stat_EtherStatsOverrsizePkts =
7320 		stats->stat_EtherStatsOverrsizePkts;
7321 
7322 	sc->stat_EtherStatsPktsRx64Octets =
7323 		stats->stat_EtherStatsPktsRx64Octets;
7324 
7325 	sc->stat_EtherStatsPktsRx65Octetsto127Octets =
7326 		stats->stat_EtherStatsPktsRx65Octetsto127Octets;
7327 
7328 	sc->stat_EtherStatsPktsRx128Octetsto255Octets =
7329 		stats->stat_EtherStatsPktsRx128Octetsto255Octets;
7330 
7331 	sc->stat_EtherStatsPktsRx256Octetsto511Octets =
7332 		stats->stat_EtherStatsPktsRx256Octetsto511Octets;
7333 
7334 	sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
7335 		stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
7336 
7337 	sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
7338 		stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
7339 
7340 	sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
7341 		stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
7342 
7343 	sc->stat_EtherStatsPktsTx64Octets =
7344 		stats->stat_EtherStatsPktsTx64Octets;
7345 
7346 	sc->stat_EtherStatsPktsTx65Octetsto127Octets =
7347 		stats->stat_EtherStatsPktsTx65Octetsto127Octets;
7348 
7349 	sc->stat_EtherStatsPktsTx128Octetsto255Octets =
7350 		stats->stat_EtherStatsPktsTx128Octetsto255Octets;
7351 
7352 	sc->stat_EtherStatsPktsTx256Octetsto511Octets =
7353 		stats->stat_EtherStatsPktsTx256Octetsto511Octets;
7354 
7355 	sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
7356 		stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
7357 
7358 	sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
7359 		stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
7360 
7361 	sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
7362 		stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
7363 
7364 	sc->stat_XonPauseFramesReceived =
7365 		stats->stat_XonPauseFramesReceived;
7366 
7367 	sc->stat_XoffPauseFramesReceived =
7368 		stats->stat_XoffPauseFramesReceived;
7369 
7370 	sc->stat_OutXonSent =
7371 		stats->stat_OutXonSent;
7372 
7373 	sc->stat_OutXoffSent =
7374 		stats->stat_OutXoffSent;
7375 
7376 	sc->stat_FlowControlDone =
7377 		stats->stat_FlowControlDone;
7378 
7379 	sc->stat_MacControlFramesReceived =
7380 		stats->stat_MacControlFramesReceived;
7381 
7382 	sc->stat_XoffStateEntered =
7383 		stats->stat_XoffStateEntered;
7384 
7385 	sc->stat_IfInFramesL2FilterDiscards =
7386 		stats->stat_IfInFramesL2FilterDiscards;
7387 
7388 	sc->stat_IfInRuleCheckerDiscards =
7389 		stats->stat_IfInRuleCheckerDiscards;
7390 
7391 	sc->stat_IfInFTQDiscards =
7392 		stats->stat_IfInFTQDiscards;
7393 
7394 	sc->stat_IfInMBUFDiscards =
7395 		stats->stat_IfInMBUFDiscards;
7396 
7397 	sc->stat_IfInRuleCheckerP4Hit =
7398 		stats->stat_IfInRuleCheckerP4Hit;
7399 
7400 	sc->stat_CatchupInRuleCheckerDiscards =
7401 		stats->stat_CatchupInRuleCheckerDiscards;
7402 
7403 	sc->stat_CatchupInFTQDiscards =
7404 		stats->stat_CatchupInFTQDiscards;
7405 
7406 	sc->stat_CatchupInMBUFDiscards =
7407 		stats->stat_CatchupInMBUFDiscards;
7408 
7409 	sc->stat_CatchupInRuleCheckerP4Hit =
7410 		stats->stat_CatchupInRuleCheckerP4Hit;
7411 
7412 	sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
7413 
7414 	/*
7415 	 * Update the interface statistics from the
7416 	 * hardware statistics.
7417 	 */
7418 	ifp->if_collisions =
7419 		(u_long) sc->stat_EtherStatsCollisions;
7420 
7421 	/* ToDo: This method loses soft errors. */
7422 	ifp->if_ierrors =
7423 		(u_long) sc->stat_EtherStatsUndersizePkts +
7424 		(u_long) sc->stat_EtherStatsOverrsizePkts +
7425 		(u_long) sc->stat_IfInMBUFDiscards +
7426 		(u_long) sc->stat_Dot3StatsAlignmentErrors +
7427 		(u_long) sc->stat_Dot3StatsFCSErrors +
7428 		(u_long) sc->stat_IfInRuleCheckerDiscards +
7429 		(u_long) sc->stat_IfInFTQDiscards +
7430 		(u_long) sc->com_no_buffers;
7431 
7432 	/* ToDo: This method loses soft errors. */
7433 	ifp->if_oerrors =
7434 		(u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
7435 		(u_long) sc->stat_Dot3StatsExcessiveCollisions +
7436 		(u_long) sc->stat_Dot3StatsLateCollisions;
7437 
7438 	/* ToDo: Add additional statistics. */
7439 
7440 	DBEXIT(BCE_EXTREME_MISC);
7441 }
7442 
7443 
7444 /****************************************************************************/
7445 /* Periodic function to notify the bootcode that the driver is still        */
7446 /* present.                                                                 */
7447 /*                                                                          */
7448 /* Returns:                                                                 */
7449 /*   Nothing.                                                               */
7450 /****************************************************************************/
7451 static void
7452 bce_pulse(void *xsc)
7453 {
7454 	struct bce_softc *sc = xsc;
7455 	u32 msg;
7456 
7457 	DBENTER(BCE_EXTREME_MISC);
7458 
7459 	BCE_LOCK_ASSERT(sc);
7460 
7461 	/* Tell the firmware that the driver is still running. */
7462 	msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
7463 	REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
7464 
7465 	/* Schedule the next pulse. */
7466 	callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
7467 
7468 	DBEXIT(BCE_EXTREME_MISC);
7469 }
7470 
7471 
7472 /****************************************************************************/
7473 /* Periodic function to perform maintenance tasks.                          */
7474 /*                                                                          */
7475 /* Returns:                                                                 */
7476 /*   Nothing.                                                               */
7477 /****************************************************************************/
7478 static void
7479 bce_tick(void *xsc)
7480 {
7481 	struct bce_softc *sc = xsc;
7482 	struct mii_data *mii;
7483 	struct ifnet *ifp;
7484 
7485 	ifp = sc->bce_ifp;
7486 
7487 	DBENTER(BCE_EXTREME_MISC);
7488 
7489 	BCE_LOCK_ASSERT(sc);
7490 
7491 	/* Schedule the next tick. */
7492 	callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7493 
7494 	/* Update the statistics from the hardware statistics block. */
7495 	bce_stats_update(sc);
7496 
7497 	/* Top off the receive and page chains. */
7498 #ifdef BCE_USE_SPLIT_HEADER
7499 	bce_fill_pg_chain(sc);
7500 #endif
7501 	bce_fill_rx_chain(sc);
7502 
7503 	/* Check that chip hasn't hung. */
7504 	bce_watchdog(sc);
7505 
7506 	/* If link is up already up then we're done. */
7507 	if (sc->bce_link)
7508 		goto bce_tick_exit;
7509 
7510 	/* Link is down.  Check what the PHY's doing. */
7511 	mii = device_get_softc(sc->bce_miibus);
7512 	mii_tick(mii);
7513 
7514 	/* Check if the link has come up. */
7515 	if ((mii->mii_media_status & IFM_ACTIVE) &&
7516 	    (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
7517 		DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", __FUNCTION__);
7518 		sc->bce_link++;
7519 		if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
7520 		    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) &&
7521 		    bootverbose)
7522 			BCE_PRINTF("Gigabit link up!\n");
7523 		/* Now that link is up, handle any outstanding TX traffic. */
7524 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7525 			DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found pending TX traffic.\n",
7526 				 __FUNCTION__);
7527 			bce_start_locked(ifp);
7528 		}
7529 	}
7530 
7531 bce_tick_exit:
7532 	DBEXIT(BCE_EXTREME_MISC);
7533 	return;
7534 }
7535 
7536 
7537 #ifdef BCE_DEBUG
7538 /****************************************************************************/
7539 /* Allows the driver state to be dumped through the sysctl interface.       */
7540 /*                                                                          */
7541 /* Returns:                                                                 */
7542 /*   0 for success, positive value for failure.                             */
7543 /****************************************************************************/
7544 static int
7545 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
7546 {
7547         int error;
7548         int result;
7549         struct bce_softc *sc;
7550 
7551         result = -1;
7552         error = sysctl_handle_int(oidp, &result, 0, req);
7553 
7554         if (error || !req->newptr)
7555                 return (error);
7556 
7557         if (result == 1) {
7558                 sc = (struct bce_softc *)arg1;
7559                 bce_dump_driver_state(sc);
7560         }
7561 
7562         return error;
7563 }
7564 
7565 
7566 /****************************************************************************/
7567 /* Allows the hardware state to be dumped through the sysctl interface.     */
7568 /*                                                                          */
7569 /* Returns:                                                                 */
7570 /*   0 for success, positive value for failure.                             */
7571 /****************************************************************************/
7572 static int
7573 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
7574 {
7575         int error;
7576         int result;
7577         struct bce_softc *sc;
7578 
7579         result = -1;
7580         error = sysctl_handle_int(oidp, &result, 0, req);
7581 
7582         if (error || !req->newptr)
7583                 return (error);
7584 
7585         if (result == 1) {
7586                 sc = (struct bce_softc *)arg1;
7587                 bce_dump_hw_state(sc);
7588         }
7589 
7590         return error;
7591 }
7592 
7593 
7594 /****************************************************************************/
7595 /* Allows the bootcode state to be dumped through the sysctl interface.     */
7596 /*                                                                          */
7597 /* Returns:                                                                 */
7598 /*   0 for success, positive value for failure.                             */
7599 /****************************************************************************/
7600 static int
7601 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
7602 {
7603         int error;
7604         int result;
7605         struct bce_softc *sc;
7606 
7607         result = -1;
7608         error = sysctl_handle_int(oidp, &result, 0, req);
7609 
7610         if (error || !req->newptr)
7611                 return (error);
7612 
7613         if (result == 1) {
7614                 sc = (struct bce_softc *)arg1;
7615                 bce_dump_bc_state(sc);
7616         }
7617 
7618         return error;
7619 }
7620 
7621 
7622 /****************************************************************************/
7623 /* Provides a sysctl interface to allow dumping the RX chain.               */
7624 /*                                                                          */
7625 /* Returns:                                                                 */
7626 /*   0 for success, positive value for failure.                             */
7627 /****************************************************************************/
7628 static int
7629 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
7630 {
7631         int error;
7632         int result;
7633         struct bce_softc *sc;
7634 
7635         result = -1;
7636         error = sysctl_handle_int(oidp, &result, 0, req);
7637 
7638         if (error || !req->newptr)
7639                 return (error);
7640 
7641         if (result == 1) {
7642                 sc = (struct bce_softc *)arg1;
7643                 bce_dump_rx_chain(sc, 0, TOTAL_RX_BD);
7644         }
7645 
7646         return error;
7647 }
7648 
7649 
7650 /****************************************************************************/
7651 /* Provides a sysctl interface to allow dumping the TX chain.               */
7652 /*                                                                          */
7653 /* Returns:                                                                 */
7654 /*   0 for success, positive value for failure.                             */
7655 /****************************************************************************/
7656 static int
7657 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
7658 {
7659         int error;
7660         int result;
7661         struct bce_softc *sc;
7662 
7663         result = -1;
7664         error = sysctl_handle_int(oidp, &result, 0, req);
7665 
7666         if (error || !req->newptr)
7667                 return (error);
7668 
7669         if (result == 1) {
7670                 sc = (struct bce_softc *)arg1;
7671                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
7672         }
7673 
7674         return error;
7675 }
7676 
7677 
7678 #ifdef BCE_USE_SPLIT_HEADER
7679 /****************************************************************************/
7680 /* Provides a sysctl interface to allow dumping the page chain.             */
7681 /*                                                                          */
7682 /* Returns:                                                                 */
7683 /*   0 for success, positive value for failure.                             */
7684 /****************************************************************************/
7685 static int
7686 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
7687 {
7688         int error;
7689         int result;
7690         struct bce_softc *sc;
7691 
7692         result = -1;
7693         error = sysctl_handle_int(oidp, &result, 0, req);
7694 
7695         if (error || !req->newptr)
7696                 return (error);
7697 
7698         if (result == 1) {
7699                 sc = (struct bce_softc *)arg1;
7700                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD);
7701         }
7702 
7703         return error;
7704 }
7705 #endif
7706 
7707 /****************************************************************************/
7708 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
7709 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
7710 /*                                                                          */
7711 /* Returns:                                                                 */
7712 /*   0 for success, positive value for failure.                             */
7713 /****************************************************************************/
7714 static int
7715 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
7716 {
7717 	struct bce_softc *sc = (struct bce_softc *)arg1;
7718 	int error;
7719 	u32 result;
7720 	u32 val[1];
7721 	u8 *data = (u8 *) val;
7722 
7723 	result = -1;
7724 	error = sysctl_handle_int(oidp, &result, 0, req);
7725 	if (error || (req->newptr == NULL))
7726 		return (error);
7727 
7728 	bce_nvram_read(sc, result, data, 4);
7729 	BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
7730 
7731 	return (error);
7732 }
7733 
7734 
7735 /****************************************************************************/
7736 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
7737 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
7738 /*                                                                          */
7739 /* Returns:                                                                 */
7740 /*   0 for success, positive value for failure.                             */
7741 /****************************************************************************/
7742 static int
7743 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
7744 {
7745 	struct bce_softc *sc = (struct bce_softc *)arg1;
7746 	int error;
7747 	u32 val, result;
7748 
7749 	result = -1;
7750 	error = sysctl_handle_int(oidp, &result, 0, req);
7751 	if (error || (req->newptr == NULL))
7752 		return (error);
7753 
7754 	/* Make sure the register is accessible. */
7755 	if (result < 0x8000) {
7756 		val = REG_RD(sc, result);
7757 		BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
7758 	} else if (result < 0x0280000) {
7759 		val = REG_RD_IND(sc, result);
7760 		BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
7761 	}
7762 
7763 	return (error);
7764 }
7765 
7766 
7767 /****************************************************************************/
7768 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
7769 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
7770 /*                                                                          */
7771 /* Returns:                                                                 */
7772 /*   0 for success, positive value for failure.                             */
7773 /****************************************************************************/
7774 static int
7775 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
7776 {
7777 	struct bce_softc *sc;
7778 	device_t dev;
7779 	int error, result;
7780 	u16 val;
7781 
7782 	result = -1;
7783 	error = sysctl_handle_int(oidp, &result, 0, req);
7784 	if (error || (req->newptr == NULL))
7785 		return (error);
7786 
7787 	/* Make sure the register is accessible. */
7788 	if (result < 0x20) {
7789 		sc = (struct bce_softc *)arg1;
7790 		dev = sc->bce_dev;
7791 		val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
7792 		BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
7793 	}
7794 	return (error);
7795 }
7796 
7797 
7798 /****************************************************************************/
7799 /* Provides a sysctl interface to allow reading a CID.                      */
7800 /*                                                                          */
7801 /* Returns:                                                                 */
7802 /*   0 for success, positive value for failure.                             */
7803 /****************************************************************************/
7804 static int
7805 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
7806 {
7807 	struct bce_softc *sc;
7808 	int error;
7809 	u16 result;
7810 
7811 	result = -1;
7812 	error = sysctl_handle_int(oidp, &result, 0, req);
7813 	if (error || (req->newptr == NULL))
7814 		return (error);
7815 
7816 	/* Make sure the register is accessible. */
7817 	if (result <= TX_CID) {
7818 		sc = (struct bce_softc *)arg1;
7819 		bce_dump_ctx(sc, result);
7820 	}
7821 
7822 	return (error);
7823 }
7824 
7825 
7826  /****************************************************************************/
7827 /* Provides a sysctl interface to forcing the driver to dump state and      */
7828 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
7829 /*                                                                          */
7830 /* Returns:                                                                 */
7831 /*   0 for success, positive value for failure.                             */
7832 /****************************************************************************/
7833 static int
7834 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
7835 {
7836         int error;
7837         int result;
7838         struct bce_softc *sc;
7839 
7840         result = -1;
7841         error = sysctl_handle_int(oidp, &result, 0, req);
7842 
7843         if (error || !req->newptr)
7844                 return (error);
7845 
7846         if (result == 1) {
7847                 sc = (struct bce_softc *)arg1;
7848                 bce_breakpoint(sc);
7849         }
7850 
7851         return error;
7852 }
7853 #endif
7854 
7855 
7856 /****************************************************************************/
7857 /* Adds any sysctl parameters for tuning or debugging purposes.             */
7858 /*                                                                          */
7859 /* Returns:                                                                 */
7860 /*   0 for success, positive value for failure.                             */
7861 /****************************************************************************/
7862 static void
7863 bce_add_sysctls(struct bce_softc *sc)
7864 {
7865 	struct sysctl_ctx_list *ctx;
7866 	struct sysctl_oid_list *children;
7867 
7868 	DBENTER(BCE_VERBOSE_MISC);
7869 
7870 	ctx = device_get_sysctl_ctx(sc->bce_dev);
7871 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
7872 
7873 #ifdef BCE_DEBUG
7874 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7875 		"rx_low_watermark",
7876 		CTLFLAG_RD, &sc->rx_low_watermark,
7877 		0, "Lowest level of free rx_bd's");
7878 
7879 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7880 		"rx_empty_count",
7881 		CTLFLAG_RD, &sc->rx_empty_count,
7882 		0, "Number of times the RX chain was empty");
7883 
7884 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7885 		"tx_hi_watermark",
7886 		CTLFLAG_RD, &sc->tx_hi_watermark,
7887 		0, "Highest level of used tx_bd's");
7888 
7889 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7890 		"tx_full_count",
7891 		CTLFLAG_RD, &sc->tx_full_count,
7892 		0, "Number of times the TX chain was full");
7893 
7894 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7895 		"l2fhdr_status_errors",
7896 		CTLFLAG_RD, &sc->l2fhdr_status_errors,
7897 		0, "l2_fhdr status errors");
7898 
7899 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7900 		"unexpected_attentions",
7901 		CTLFLAG_RD, &sc->unexpected_attentions,
7902 		0, "Unexpected attentions");
7903 
7904 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7905 		"lost_status_block_updates",
7906 		CTLFLAG_RD, &sc->lost_status_block_updates,
7907 		0, "Lost status block updates");
7908 
7909 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7910 		"debug_mbuf_sim_alloc_failed",
7911 		CTLFLAG_RD, &sc->debug_mbuf_sim_alloc_failed,
7912 		0, "Simulated mbuf cluster allocation failures");
7913 
7914 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7915 		"requested_tso_frames",
7916 		CTLFLAG_RD, &sc->requested_tso_frames,
7917 		0, "Number of TSO frames received");
7918 
7919 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7920 		"rx_interrupts",
7921 		CTLFLAG_RD, &sc->rx_interrupts,
7922 		0, "Number of RX interrupts");
7923 
7924 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7925 		"tx_interrupts",
7926 		CTLFLAG_RD, &sc->tx_interrupts,
7927 		0, "Number of TX interrupts");
7928 
7929 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7930 		"rx_intr_time",
7931 		CTLFLAG_RD, &sc->rx_intr_time,
7932 		"RX interrupt time");
7933 
7934 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7935 		"tx_intr_time",
7936 		CTLFLAG_RD, &sc->tx_intr_time,
7937 		"TX interrupt time");
7938 #endif
7939 
7940 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7941 		"mbuf_alloc_failed",
7942 		CTLFLAG_RD, &sc->mbuf_alloc_failed,
7943 		0, "mbuf cluster allocation failures");
7944 
7945 	SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7946 		"tx_dma_map_failures",
7947 		CTLFLAG_RD, &sc->tx_dma_map_failures,
7948 		0, "tx dma mapping failures");
7949 
7950 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7951 		"stat_IfHcInOctets",
7952 		CTLFLAG_RD, &sc->stat_IfHCInOctets,
7953 		"Bytes received");
7954 
7955 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7956 		"stat_IfHCInBadOctets",
7957 		CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
7958 		"Bad bytes received");
7959 
7960 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7961 		"stat_IfHCOutOctets",
7962 		CTLFLAG_RD, &sc->stat_IfHCOutOctets,
7963 		"Bytes sent");
7964 
7965 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7966 		"stat_IfHCOutBadOctets",
7967 		CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
7968 		"Bad bytes sent");
7969 
7970 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7971 		"stat_IfHCInUcastPkts",
7972 		CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
7973 		"Unicast packets received");
7974 
7975 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7976 		"stat_IfHCInMulticastPkts",
7977 		CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
7978 		"Multicast packets received");
7979 
7980 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7981 		"stat_IfHCInBroadcastPkts",
7982 		CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
7983 		"Broadcast packets received");
7984 
7985 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7986 		"stat_IfHCOutUcastPkts",
7987 		CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
7988 		"Unicast packets sent");
7989 
7990 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7991 		"stat_IfHCOutMulticastPkts",
7992 		CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
7993 		"Multicast packets sent");
7994 
7995 	SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7996 		"stat_IfHCOutBroadcastPkts",
7997 		CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
7998 		"Broadcast packets sent");
7999 
8000 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8001 		"stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
8002 		CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
8003 		0, "Internal MAC transmit errors");
8004 
8005 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8006 		"stat_Dot3StatsCarrierSenseErrors",
8007 		CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
8008 		0, "Carrier sense errors");
8009 
8010 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8011 		"stat_Dot3StatsFCSErrors",
8012 		CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
8013 		0, "Frame check sequence errors");
8014 
8015 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8016 		"stat_Dot3StatsAlignmentErrors",
8017 		CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
8018 		0, "Alignment errors");
8019 
8020 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8021 		"stat_Dot3StatsSingleCollisionFrames",
8022 		CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
8023 		0, "Single Collision Frames");
8024 
8025 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8026 		"stat_Dot3StatsMultipleCollisionFrames",
8027 		CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
8028 		0, "Multiple Collision Frames");
8029 
8030 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8031 		"stat_Dot3StatsDeferredTransmissions",
8032 		CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
8033 		0, "Deferred Transmissions");
8034 
8035 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8036 		"stat_Dot3StatsExcessiveCollisions",
8037 		CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
8038 		0, "Excessive Collisions");
8039 
8040 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8041 		"stat_Dot3StatsLateCollisions",
8042 		CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
8043 		0, "Late Collisions");
8044 
8045 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8046 		"stat_EtherStatsCollisions",
8047 		CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
8048 		0, "Collisions");
8049 
8050 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8051 		"stat_EtherStatsFragments",
8052 		CTLFLAG_RD, &sc->stat_EtherStatsFragments,
8053 		0, "Fragments");
8054 
8055 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8056 		"stat_EtherStatsJabbers",
8057 		CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
8058 		0, "Jabbers");
8059 
8060 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8061 		"stat_EtherStatsUndersizePkts",
8062 		CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
8063 		0, "Undersize packets");
8064 
8065 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8066 		"stat_EtherStatsOverrsizePkts",
8067 		CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
8068 		0, "stat_EtherStatsOverrsizePkts");
8069 
8070 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8071 		"stat_EtherStatsPktsRx64Octets",
8072 		CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
8073 		0, "Bytes received in 64 byte packets");
8074 
8075 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8076 		"stat_EtherStatsPktsRx65Octetsto127Octets",
8077 		CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
8078 		0, "Bytes received in 65 to 127 byte packets");
8079 
8080 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8081 		"stat_EtherStatsPktsRx128Octetsto255Octets",
8082 		CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
8083 		0, "Bytes received in 128 to 255 byte packets");
8084 
8085 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8086 		"stat_EtherStatsPktsRx256Octetsto511Octets",
8087 		CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
8088 		0, "Bytes received in 256 to 511 byte packets");
8089 
8090 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8091 		"stat_EtherStatsPktsRx512Octetsto1023Octets",
8092 		CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
8093 		0, "Bytes received in 512 to 1023 byte packets");
8094 
8095 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8096 		"stat_EtherStatsPktsRx1024Octetsto1522Octets",
8097 		CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
8098 		0, "Bytes received in 1024 t0 1522 byte packets");
8099 
8100 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8101 		"stat_EtherStatsPktsRx1523Octetsto9022Octets",
8102 		CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
8103 		0, "Bytes received in 1523 to 9022 byte packets");
8104 
8105 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8106 		"stat_EtherStatsPktsTx64Octets",
8107 		CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
8108 		0, "Bytes sent in 64 byte packets");
8109 
8110 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8111 		"stat_EtherStatsPktsTx65Octetsto127Octets",
8112 		CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
8113 		0, "Bytes sent in 65 to 127 byte packets");
8114 
8115 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8116 		"stat_EtherStatsPktsTx128Octetsto255Octets",
8117 		CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
8118 		0, "Bytes sent in 128 to 255 byte packets");
8119 
8120 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8121 		"stat_EtherStatsPktsTx256Octetsto511Octets",
8122 		CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
8123 		0, "Bytes sent in 256 to 511 byte packets");
8124 
8125 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8126 		"stat_EtherStatsPktsTx512Octetsto1023Octets",
8127 		CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
8128 		0, "Bytes sent in 512 to 1023 byte packets");
8129 
8130 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8131 		"stat_EtherStatsPktsTx1024Octetsto1522Octets",
8132 		CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
8133 		0, "Bytes sent in 1024 to 1522 byte packets");
8134 
8135 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8136 		"stat_EtherStatsPktsTx1523Octetsto9022Octets",
8137 		CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
8138 		0, "Bytes sent in 1523 to 9022 byte packets");
8139 
8140 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8141 		"stat_XonPauseFramesReceived",
8142 		CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
8143 		0, "XON pause frames receved");
8144 
8145 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8146 		"stat_XoffPauseFramesReceived",
8147 		CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
8148 		0, "XOFF pause frames received");
8149 
8150 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8151 		"stat_OutXonSent",
8152 		CTLFLAG_RD, &sc->stat_OutXonSent,
8153 		0, "XON pause frames sent");
8154 
8155 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8156 		"stat_OutXoffSent",
8157 		CTLFLAG_RD, &sc->stat_OutXoffSent,
8158 		0, "XOFF pause frames sent");
8159 
8160 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8161 		"stat_FlowControlDone",
8162 		CTLFLAG_RD, &sc->stat_FlowControlDone,
8163 		0, "Flow control done");
8164 
8165 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8166 		"stat_MacControlFramesReceived",
8167 		CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
8168 		0, "MAC control frames received");
8169 
8170 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8171 		"stat_XoffStateEntered",
8172 		CTLFLAG_RD, &sc->stat_XoffStateEntered,
8173 		0, "XOFF state entered");
8174 
8175 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8176 		"stat_IfInFramesL2FilterDiscards",
8177 		CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
8178 		0, "Received L2 packets discarded");
8179 
8180 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8181 		"stat_IfInRuleCheckerDiscards",
8182 		CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
8183 		0, "Received packets discarded by rule");
8184 
8185 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8186 		"stat_IfInFTQDiscards",
8187 		CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
8188 		0, "Received packet FTQ discards");
8189 
8190 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8191 		"stat_IfInMBUFDiscards",
8192 		CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
8193 		0, "Received packets discarded due to lack of controller buffer memory");
8194 
8195 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8196 		"stat_IfInRuleCheckerP4Hit",
8197 		CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
8198 		0, "Received packets rule checker hits");
8199 
8200 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8201 		"stat_CatchupInRuleCheckerDiscards",
8202 		CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
8203 		0, "Received packets discarded in Catchup path");
8204 
8205 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8206 		"stat_CatchupInFTQDiscards",
8207 		CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
8208 		0, "Received packets discarded in FTQ in Catchup path");
8209 
8210 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8211 		"stat_CatchupInMBUFDiscards",
8212 		CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
8213 		0, "Received packets discarded in controller buffer memory in Catchup path");
8214 
8215 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8216 		"stat_CatchupInRuleCheckerP4Hit",
8217 		CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
8218 		0, "Received packets rule checker hits in Catchup path");
8219 
8220 	SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8221 		"com_no_buffers",
8222 		CTLFLAG_RD, &sc->com_no_buffers,
8223 		0, "Valid packets received but no RX buffers available");
8224 
8225 #ifdef BCE_DEBUG
8226 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8227 		"driver_state", CTLTYPE_INT | CTLFLAG_RW,
8228 		(void *)sc, 0,
8229 		bce_sysctl_driver_state, "I", "Drive state information");
8230 
8231 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8232 		"hw_state", CTLTYPE_INT | CTLFLAG_RW,
8233 		(void *)sc, 0,
8234 		bce_sysctl_hw_state, "I", "Hardware state information");
8235 
8236 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8237 		"bc_state", CTLTYPE_INT | CTLFLAG_RW,
8238 		(void *)sc, 0,
8239 		bce_sysctl_bc_state, "I", "Bootcode state information");
8240 
8241 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8242 		"dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
8243 		(void *)sc, 0,
8244 		bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
8245 
8246 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8247 		"dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
8248 		(void *)sc, 0,
8249 		bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
8250 
8251 #ifdef BCE_USE_SPLIT_HEADER
8252 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8253 		"dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
8254 		(void *)sc, 0,
8255 		bce_sysctl_dump_pg_chain, "I", "Dump page chain");
8256 #endif
8257 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8258 		"dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
8259 		(void *)sc, 0,
8260 		bce_sysctl_dump_ctx, "I", "Dump context memory");
8261 
8262 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8263 		"breakpoint", CTLTYPE_INT | CTLFLAG_RW,
8264 		(void *)sc, 0,
8265 		bce_sysctl_breakpoint, "I", "Driver breakpoint");
8266 
8267 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8268 		"reg_read", CTLTYPE_INT | CTLFLAG_RW,
8269 		(void *)sc, 0,
8270 		bce_sysctl_reg_read, "I", "Register read");
8271 
8272 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8273 		"nvram_read", CTLTYPE_INT | CTLFLAG_RW,
8274 		(void *)sc, 0,
8275 		bce_sysctl_nvram_read, "I", "NVRAM read");
8276 
8277 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8278 		"phy_read", CTLTYPE_INT | CTLFLAG_RW,
8279 		(void *)sc, 0,
8280 		bce_sysctl_phy_read, "I", "PHY register read");
8281 
8282 #endif
8283 
8284 	DBEXIT(BCE_VERBOSE_MISC);
8285 }
8286 
8287 
8288 /****************************************************************************/
8289 /* BCE Debug Routines                                                       */
8290 /****************************************************************************/
8291 #ifdef BCE_DEBUG
8292 
8293 /****************************************************************************/
8294 /* Freezes the controller to allow for a cohesive state dump.               */
8295 /*                                                                          */
8296 /* Returns:                                                                 */
8297 /*   Nothing.                                                               */
8298 /****************************************************************************/
8299 static void
8300 bce_freeze_controller(struct bce_softc *sc)
8301 {
8302 	u32 val;
8303 	val = REG_RD(sc, BCE_MISC_COMMAND);
8304 	val |= BCE_MISC_COMMAND_DISABLE_ALL;
8305 	REG_WR(sc, BCE_MISC_COMMAND, val);
8306 }
8307 
8308 
8309 /****************************************************************************/
8310 /* Unfreezes the controller after a freeze operation.  This may not always  */
8311 /* work and the controller will require a reset!                            */
8312 /*                                                                          */
8313 /* Returns:                                                                 */
8314 /*   Nothing.                                                               */
8315 /****************************************************************************/
8316 static void
8317 bce_unfreeze_controller(struct bce_softc *sc)
8318 {
8319 	u32 val;
8320 	val = REG_RD(sc, BCE_MISC_COMMAND);
8321 	val |= BCE_MISC_COMMAND_ENABLE_ALL;
8322 	REG_WR(sc, BCE_MISC_COMMAND, val);
8323 }
8324 
8325 
8326 /****************************************************************************/
8327 /* Prints out Ethernet frame information from an mbuf.                      */
8328 /*                                                                          */
8329 /* Partially decode an Ethernet frame to look at some important headers.    */
8330 /*                                                                          */
8331 /* Returns:                                                                 */
8332 /*   Nothing.                                                               */
8333 /****************************************************************************/
8334 static void
8335 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
8336 {
8337 	struct ether_vlan_header *eh;
8338 	u16 etype;
8339 	int ehlen;
8340 	struct ip *ip;
8341 	struct tcphdr *th;
8342 	struct udphdr *uh;
8343 	struct arphdr *ah;
8344 
8345 		BCE_PRINTF(
8346 			"-----------------------------"
8347 			" Frame Decode "
8348 			"-----------------------------\n");
8349 
8350 	eh = mtod(m, struct ether_vlan_header *);
8351 
8352 	/* Handle VLAN encapsulation if present. */
8353 	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
8354 		etype = ntohs(eh->evl_proto);
8355 		ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
8356 	} else {
8357 		etype = ntohs(eh->evl_encap_proto);
8358 		ehlen = ETHER_HDR_LEN;
8359 	}
8360 
8361 	/* ToDo: Add VLAN output. */
8362 	BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
8363 		eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
8364 
8365 	switch (etype) {
8366 		case ETHERTYPE_IP:
8367 			ip = (struct ip *)(m->m_data + ehlen);
8368 			BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, len = %d bytes, "
8369 				"protocol = 0x%02X, xsum = 0x%04X\n",
8370 				ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
8371 				ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
8372 
8373 			switch (ip->ip_p) {
8374 				case IPPROTO_TCP:
8375 					th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
8376 					BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = %d bytes, "
8377 						"flags = 0x%b, csum = 0x%04X\n",
8378 						ntohs(th->th_dport), ntohs(th->th_sport), (th->th_off << 2),
8379 						th->th_flags, "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST\02SYN\01FIN",
8380 						ntohs(th->th_sum));
8381 					break;
8382 				case IPPROTO_UDP:
8383         		    uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
8384 					BCE_PRINTF("-udp: dest = %d, src = %d, len = %d bytes, "
8385 						"csum = 0x%04X\n", ntohs(uh->uh_dport), ntohs(uh->uh_sport),
8386 						ntohs(uh->uh_ulen), ntohs(uh->uh_sum));
8387 					break;
8388 				case IPPROTO_ICMP:
8389 					BCE_PRINTF("icmp:\n");
8390 					break;
8391 				default:
8392 					BCE_PRINTF("----: Other IP protocol.\n");
8393 			}
8394 			break;
8395 		case ETHERTYPE_IPV6:
8396 			BCE_PRINTF("ipv6: No decode supported.\n");
8397 			break;
8398 		case ETHERTYPE_ARP:
8399 			BCE_PRINTF("-arp: ");
8400 			ah = (struct arphdr *) (m->m_data + ehlen);
8401 			switch (ntohs(ah->ar_op)) {
8402 				case ARPOP_REVREQUEST:
8403 					printf("reverse ARP request\n");
8404 					break;
8405 				case ARPOP_REVREPLY:
8406 					printf("reverse ARP reply\n");
8407 					break;
8408 				case ARPOP_REQUEST:
8409 					printf("ARP request\n");
8410 					break;
8411 				case ARPOP_REPLY:
8412 					printf("ARP reply\n");
8413 					break;
8414 				default:
8415 					printf("other ARP operation\n");
8416 			}
8417 			break;
8418 		default:
8419 			BCE_PRINTF("----: Other protocol.\n");
8420 	}
8421 
8422 	BCE_PRINTF(
8423 		"-----------------------------"
8424 		"--------------"
8425 		"-----------------------------\n");
8426 }
8427 
8428 
8429 /****************************************************************************/
8430 /* Prints out information about an mbuf.                                    */
8431 /*                                                                          */
8432 /* Returns:                                                                 */
8433 /*   Nothing.                                                               */
8434 /****************************************************************************/
8435 static __attribute__ ((noinline)) void
8436 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
8437 {
8438 	struct mbuf *mp = m;
8439 
8440 	if (m == NULL) {
8441 		BCE_PRINTF("mbuf: null pointer\n");
8442 		return;
8443 	}
8444 
8445 	while (mp) {
8446 		BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, m_data = %p\n",
8447 			mp, mp->m_len, mp->m_flags,
8448 			"\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY",
8449 			mp->m_data);
8450 
8451 		if (mp->m_flags & M_PKTHDR) {
8452 			BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, csum_flags = %b\n",
8453 				mp->m_pkthdr.len, mp->m_flags,
8454 				"\20\12M_BCAST\13M_MCAST\14M_FRAG\15M_FIRSTFRAG"
8455 				"\16M_LASTFRAG\21M_VLANTAG\22M_PROMISC\23M_NOFREE",
8456 				mp->m_pkthdr.csum_flags,
8457 				"\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
8458 				"\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
8459 				"\12CSUM_IP_VALID\13CSUM_DATA_VALID\14CSUM_PSEUDO_HDR");
8460 		}
8461 
8462 		if (mp->m_flags & M_EXT) {
8463 			BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
8464 				mp->m_ext.ext_buf, mp->m_ext.ext_size);
8465 			switch (mp->m_ext.ext_type) {
8466 				case EXT_CLUSTER:    printf("EXT_CLUSTER\n"); break;
8467 				case EXT_SFBUF:      printf("EXT_SFBUF\n"); break;
8468 				case EXT_JUMBO9:     printf("EXT_JUMBO9\n"); break;
8469 				case EXT_JUMBO16:    printf("EXT_JUMBO16\n"); break;
8470 				case EXT_PACKET:     printf("EXT_PACKET\n"); break;
8471 				case EXT_MBUF:       printf("EXT_MBUF\n"); break;
8472 				case EXT_NET_DRV:    printf("EXT_NET_DRV\n"); break;
8473 				case EXT_MOD_TYPE:   printf("EXT_MDD_TYPE\n"); break;
8474 				case EXT_DISPOSABLE: printf("EXT_DISPOSABLE\n"); break;
8475 				case EXT_EXTREF:     printf("EXT_EXTREF\n"); break;
8476 				default:             printf("UNKNOWN\n");
8477 			}
8478 		}
8479 
8480 		mp = mp->m_next;
8481 	}
8482 }
8483 
8484 
8485 /****************************************************************************/
8486 /* Prints out the mbufs in the TX mbuf chain.                               */
8487 /*                                                                          */
8488 /* Returns:                                                                 */
8489 /*   Nothing.                                                               */
8490 /****************************************************************************/
8491 static __attribute__ ((noinline)) void
8492 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
8493 {
8494 	struct mbuf *m;
8495 
8496 	BCE_PRINTF(
8497 		"----------------------------"
8498 		"  tx mbuf data  "
8499 		"----------------------------\n");
8500 
8501 	for (int i = 0; i < count; i++) {
8502 	 	m = sc->tx_mbuf_ptr[chain_prod];
8503 		BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
8504 		bce_dump_mbuf(sc, m);
8505 		chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
8506 	}
8507 
8508 	BCE_PRINTF(
8509 		"----------------------------"
8510 		"----------------"
8511 		"----------------------------\n");
8512 }
8513 
8514 
8515 /****************************************************************************/
8516 /* Prints out the mbufs in the RX mbuf chain.                               */
8517 /*                                                                          */
8518 /* Returns:                                                                 */
8519 /*   Nothing.                                                               */
8520 /****************************************************************************/
8521 static __attribute__ ((noinline)) void
8522 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
8523 {
8524 	struct mbuf *m;
8525 
8526 	BCE_PRINTF(
8527 		"----------------------------"
8528 		"  rx mbuf data  "
8529 		"----------------------------\n");
8530 
8531 	for (int i = 0; i < count; i++) {
8532 	 	m = sc->rx_mbuf_ptr[chain_prod];
8533 		BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
8534 		bce_dump_mbuf(sc, m);
8535 		chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
8536 	}
8537 
8538 
8539 	BCE_PRINTF(
8540 		"----------------------------"
8541 		"----------------"
8542 		"----------------------------\n");
8543 }
8544 
8545 
8546 #ifdef BCE_USE_SPLIT_HEADER
8547 /****************************************************************************/
8548 /* Prints out the mbufs in the mbuf page chain.                             */
8549 /*                                                                          */
8550 /* Returns:                                                                 */
8551 /*   Nothing.                                                               */
8552 /****************************************************************************/
8553 static __attribute__ ((noinline)) void
8554 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
8555 {
8556 	struct mbuf *m;
8557 
8558 	BCE_PRINTF(
8559 		"----------------------------"
8560 		"  pg mbuf data  "
8561 		"----------------------------\n");
8562 
8563 	for (int i = 0; i < count; i++) {
8564 	 	m = sc->pg_mbuf_ptr[chain_prod];
8565 		BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
8566 		bce_dump_mbuf(sc, m);
8567 		chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
8568 	}
8569 
8570 
8571 	BCE_PRINTF(
8572 		"----------------------------"
8573 		"----------------"
8574 		"----------------------------\n");
8575 }
8576 #endif
8577 
8578 
8579 /****************************************************************************/
8580 /* Prints out a tx_bd structure.                                            */
8581 /*                                                                          */
8582 /* Returns:                                                                 */
8583 /*   Nothing.                                                               */
8584 /****************************************************************************/
8585 static __attribute__ ((noinline)) void
8586 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
8587 {
8588 	if (idx > MAX_TX_BD)
8589 		/* Index out of range. */
8590 		BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
8591 	else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
8592 		/* TX Chain page pointer. */
8593 		BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
8594 			idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
8595 	else {
8596 			/* Normal tx_bd entry. */
8597 			BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
8598 				"vlan tag= 0x%04X, flags = 0x%04X (", idx,
8599 				txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
8600 				txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag,
8601 				txbd->tx_bd_flags);
8602 
8603 			if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
8604 				printf(" CONN_FAULT");
8605 
8606 			if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
8607 				printf(" TCP_UDP_CKSUM");
8608 
8609 			if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
8610 				printf(" IP_CKSUM");
8611 
8612 			if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
8613 				printf("  VLAN");
8614 
8615 			if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
8616 				printf(" COAL_NOW");
8617 
8618 			if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
8619 				printf(" DONT_GEN_CRC");
8620 
8621 			if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
8622 				printf(" START");
8623 
8624 			if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
8625 				printf(" END");
8626 
8627 			if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
8628 				printf(" LSO");
8629 
8630 			if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
8631 				printf(" OPTION_WORD");
8632 
8633 			if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
8634 				printf(" FLAGS");
8635 
8636 			if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
8637 				printf(" SNAP");
8638 
8639 			printf(" )\n");
8640 		}
8641 
8642 }
8643 
8644 
8645 /****************************************************************************/
8646 /* Prints out a rx_bd structure.                                            */
8647 /*                                                                          */
8648 /* Returns:                                                                 */
8649 /*   Nothing.                                                               */
8650 /****************************************************************************/
8651 static __attribute__ ((noinline)) void
8652 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
8653 {
8654 	if (idx > MAX_RX_BD)
8655 		/* Index out of range. */
8656 		BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
8657 	else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
8658 		/* RX Chain page pointer. */
8659 		BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
8660 			idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
8661 	else
8662 		/* Normal rx_bd entry. */
8663 		BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
8664 			"flags = 0x%08X\n", idx,
8665 			rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
8666 			rxbd->rx_bd_len, rxbd->rx_bd_flags);
8667 }
8668 
8669 
8670 #ifdef BCE_USE_SPLIT_HEADER
8671 /****************************************************************************/
8672 /* Prints out a rx_bd structure in the page chain.                          */
8673 /*                                                                          */
8674 /* Returns:                                                                 */
8675 /*   Nothing.                                                               */
8676 /****************************************************************************/
8677 static __attribute__ ((noinline)) void
8678 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
8679 {
8680 	if (idx > MAX_PG_BD)
8681 		/* Index out of range. */
8682 		BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
8683 	else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
8684 		/* Page Chain page pointer. */
8685 		BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
8686 			idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
8687 	else
8688 		/* Normal rx_bd entry. */
8689 		BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
8690 			"flags = 0x%08X\n", idx,
8691 			pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
8692 			pgbd->rx_bd_len, pgbd->rx_bd_flags);
8693 }
8694 #endif
8695 
8696 
8697 /****************************************************************************/
8698 /* Prints out a l2_fhdr structure.                                          */
8699 /*                                                                          */
8700 /* Returns:                                                                 */
8701 /*   Nothing.                                                               */
8702 /****************************************************************************/
8703 static __attribute__ ((noinline)) void
8704 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
8705 {
8706 	BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
8707 		"pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
8708 		"tcp_udp_xsum = 0x%04X\n", idx,
8709 		l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
8710 		l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
8711 		l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
8712 }
8713 
8714 
8715 /****************************************************************************/
8716 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
8717 /*                                                                          */
8718 /* Returns:                                                                 */
8719 /*   Nothing.                                                               */
8720 /****************************************************************************/
8721 static __attribute__ ((noinline)) void
8722 bce_dump_ctx(struct bce_softc *sc, u16 cid)
8723 {
8724 	if (cid <= TX_CID) {
8725 		BCE_PRINTF(
8726 			"----------------------------"
8727 			"    CTX Data    "
8728 			"----------------------------\n");
8729 
8730 		BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
8731 
8732 		if (cid == RX_CID) {
8733 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
8734 				"producer index\n",
8735 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
8736 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host byte sequence\n",
8737 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BSEQ));
8738 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
8739 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
8740 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
8741 				"descriptor address\n",
8742  				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
8743 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
8744 				"descriptor address\n",
8745 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
8746 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer index\n",
8747 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDIDX));
8748 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
8749 				"producer index\n",
8750 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_PG_BDIDX));
8751 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
8752 				"buffer size\n",
8753 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_PG_BUF_SIZE));
8754 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
8755 				"chain address\n",
8756 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
8757 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
8758 				"chain address\n",
8759 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
8760 			BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
8761 				"consumer index\n",
8762 				CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_PG_BDIDX));
8763 		} else if (cid == TX_CID) {
8764 			if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
8765 				(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
8766 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
8767 					CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE_XI));
8768 				BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx cmd\n",
8769 					CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_CMD_TYPE_XI));
8770 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) h/w buffer "
8771 					"descriptor address\n",	CTX_RD(sc,
8772 					GET_CID_ADDR(cid), BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
8773 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) h/w buffer "
8774 					"descriptor address\n", CTX_RD(sc,
8775 					GET_CID_ADDR(cid), BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
8776 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) host producer "
8777 					"index\n", CTX_RD(sc, GET_CID_ADDR(cid),
8778 					BCE_L2CTX_TX_HOST_BIDX_XI));
8779 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) host byte "
8780 					"sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
8781 					BCE_L2CTX_TX_HOST_BSEQ_XI));
8782 			} else {
8783 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
8784 					CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
8785 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
8786 					CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_CMD_TYPE));
8787 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) h/w buffer "
8788 					"descriptor address\n", CTX_RD(sc, GET_CID_ADDR(cid),
8789 					BCE_L2CTX_TX_TBDR_BHADDR_HI));
8790 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) h/w buffer "
8791 					"descriptor address\n", CTX_RD(sc, GET_CID_ADDR(cid),
8792 					BCE_L2CTX_TX_TBDR_BHADDR_LO));
8793 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host producer "
8794 					"index\n", CTX_RD(sc, GET_CID_ADDR(cid),
8795 					BCE_L2CTX_TX_HOST_BIDX));
8796 				BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
8797 					"sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
8798 					BCE_L2CTX_TX_HOST_BSEQ));
8799 			}
8800 		} else
8801 			BCE_PRINTF(" Unknown CID\n");
8802 
8803 		BCE_PRINTF(
8804 			"----------------------------"
8805 			"    Raw CTX     "
8806 			"----------------------------\n");
8807 
8808 		for (int i = 0x0; i < 0x300; i += 0x10) {
8809 			BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
8810 				CTX_RD(sc, GET_CID_ADDR(cid), i),
8811 				CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
8812 				CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
8813 				CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
8814 		}
8815 
8816 
8817 		BCE_PRINTF(
8818 			"----------------------------"
8819 			"----------------"
8820 			"----------------------------\n");
8821 	}
8822 }
8823 
8824 
8825 /****************************************************************************/
8826 /* Prints out the FTQ data.                                                 */
8827 /*                                                                          */
8828 /* Returns:                                                                */
8829 /*   Nothing.                                                               */
8830 /****************************************************************************/
8831 static __attribute__ ((noinline)) void
8832 bce_dump_ftqs(struct bce_softc *sc)
8833 {
8834 	u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
8835 
8836 	BCE_PRINTF(
8837 		"----------------------------"
8838 		"    FTQ Data    "
8839 		"----------------------------\n");
8840 
8841 	BCE_PRINTF("   FTQ    Command    Control   Depth_Now  Max_Depth  Valid_Cnt \n");
8842 	BCE_PRINTF(" ------- ---------- ---------- ---------- ---------- ----------\n");
8843 
8844 	/* Setup the generic statistic counters for the FTQ valid count. */
8845 	val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
8846 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
8847 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
8848 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
8849 	REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
8850 
8851 	val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
8852 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
8853 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
8854 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
8855 	REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
8856 
8857 	val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
8858 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
8859 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
8860 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
8861 	REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
8862 
8863 	val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
8864 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
8865 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
8866 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
8867 	REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
8868 
8869 	/* Input queue to the Receive Lookup state machine */
8870 	cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
8871 	ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
8872 	cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
8873 	max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
8874 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
8875 	BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8876 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8877 
8878 	/* Input queue to the Receive Processor */
8879 	cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
8880 	ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
8881 	cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
8882 	max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
8883 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
8884 	BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8885 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8886 
8887 	/* Input queue to the Recevie Processor */
8888 	cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
8889 	ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
8890 	cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
8891 	max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
8892 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
8893 	BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8894 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8895 
8896 	/* Input queue to the Receive Virtual to Physical state machine */
8897 	cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
8898 	ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
8899 	cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
8900 	max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
8901 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
8902 	BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8903 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8904 
8905 	/* Input queue to the Recevie Virtual to Physical state machine */
8906 	cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
8907 	ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
8908 	cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
8909 	max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
8910 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
8911 	BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8912 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8913 
8914 	/* Input queue to the Receive Virtual to Physical state machine */
8915 	cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
8916 	ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
8917 	cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
8918 	max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
8919 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
8920 	BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8921 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8922 
8923 	/* Input queue to the Receive DMA state machine */
8924 	cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
8925 	ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
8926 	cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
8927 	max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
8928 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
8929 	BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8930 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8931 
8932 	/* Input queue to the Transmit Scheduler state machine */
8933 	cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
8934 	ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
8935 	cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
8936 	max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
8937 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
8938 	BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8939 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8940 
8941 	/* Input queue to the Transmit Buffer Descriptor state machine */
8942 	cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
8943 	ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
8944 	cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
8945 	max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
8946 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
8947 	BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8948 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8949 
8950 	/* Input queue to the Transmit Processor */
8951 	cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
8952 	ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
8953 	cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
8954 	max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
8955 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
8956 	BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8957 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8958 
8959 	/* Input queue to the Transmit DMA state machine */
8960 	cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
8961 	ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
8962 	cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
8963 	max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
8964 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
8965 	BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8966 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8967 
8968 	/* Input queue to the Transmit Patch-Up Processor */
8969 	cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
8970 	ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
8971 	cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
8972 	max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
8973 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
8974 	BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8975 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8976 
8977 	/* Input queue to the Transmit Assembler state machine */
8978 	cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
8979 	ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
8980 	cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
8981 	max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
8982 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
8983 	BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8984 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8985 
8986 	/* Input queue to the Completion Processor */
8987 	cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
8988 	ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
8989 	cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
8990 	max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
8991 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
8992 	BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8993 		cmd, ctl, cur_depth, max_depth, valid_cnt);
8994 
8995 	/* Input queue to the Completion Processor */
8996 	cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
8997 	ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
8998 	cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
8999 	max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
9000 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
9001 	BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9002 		cmd, ctl, cur_depth, max_depth, valid_cnt);
9003 
9004 	/* Input queue to the Completion Processor */
9005 	cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
9006 	ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
9007 	cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
9008 	max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
9009 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
9010 	BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9011 		cmd, ctl, cur_depth, max_depth, valid_cnt);
9012 
9013 	/* Setup the generic statistic counters for the FTQ valid count. */
9014 	val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
9015 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
9016 		(BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
9017 
9018 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)	||
9019 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
9020 		val = val | (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 24);
9021 		REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
9022 
9023 	/* Input queue to the Management Control Processor */
9024 	cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
9025 	ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
9026 	cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
9027 	max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
9028 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
9029 	BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9030 		cmd, ctl, cur_depth, max_depth, valid_cnt);
9031 
9032 	/* Input queue to the Command Processor */
9033 	cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
9034 	ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
9035 	cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
9036 	max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
9037 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
9038 	BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9039 		cmd, ctl, cur_depth, max_depth, valid_cnt);
9040 
9041 	/* Input queue to the Completion Scheduler state machine */
9042 	cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
9043 	ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
9044 	cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
9045 	max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
9046 	valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
9047 	BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9048 		cmd, ctl, cur_depth, max_depth, valid_cnt);
9049 
9050 	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
9051 		(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
9052 		/* Input queue to the Receive Virtual to Physical Command Scheduler */
9053 		cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
9054 		ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
9055 		cur_depth = (ctl & 0xFFC00000) >> 22;
9056 		max_depth = (ctl & 0x003FF000) >> 12;
9057 		valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
9058 		BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9059 			cmd, ctl, cur_depth, max_depth, valid_cnt);
9060 	}
9061 
9062 	BCE_PRINTF(
9063 		"----------------------------"
9064 		"----------------"
9065 		"----------------------------\n");
9066 }
9067 
9068 
9069 /****************************************************************************/
9070 /* Prints out the TX chain.                                                 */
9071 /*                                                                          */
9072 /* Returns:                                                                 */
9073 /*   Nothing.                                                               */
9074 /****************************************************************************/
9075 static __attribute__ ((noinline)) void
9076 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
9077 {
9078 	struct tx_bd *txbd;
9079 
9080 	/* First some info about the tx_bd chain structure. */
9081 	BCE_PRINTF(
9082 		"----------------------------"
9083 		"  tx_bd  chain  "
9084 		"----------------------------\n");
9085 
9086 	BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
9087 		(u32) BCM_PAGE_SIZE, (u32) TX_PAGES);
9088 
9089 	BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
9090 		(u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
9091 
9092 	BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD);
9093 
9094 	BCE_PRINTF(
9095 		"----------------------------"
9096 		"   tx_bd data   "
9097 		"----------------------------\n");
9098 
9099 	/* Now print out the tx_bd's themselves. */
9100 	for (int i = 0; i < count; i++) {
9101 	 	txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
9102 		bce_dump_txbd(sc, tx_prod, txbd);
9103 		tx_prod = NEXT_TX_BD(tx_prod);
9104 	}
9105 
9106 	BCE_PRINTF(
9107 		"----------------------------"
9108 		"----------------"
9109 		"----------------------------\n");
9110 }
9111 
9112 
9113 /****************************************************************************/
9114 /* Prints out the RX chain.                                                 */
9115 /*                                                                          */
9116 /* Returns:                                                                 */
9117 /*   Nothing.                                                               */
9118 /****************************************************************************/
9119 static __attribute__ ((noinline)) void
9120 bce_dump_rx_chain(struct bce_softc *sc, u16 rx_prod, int count)
9121 {
9122 	struct rx_bd *rxbd;
9123 
9124 	/* First some info about the rx_bd chain structure. */
9125 	BCE_PRINTF(
9126 		"----------------------------"
9127 		"  rx_bd  chain  "
9128 		"----------------------------\n");
9129 
9130 	BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
9131 		(u32) BCM_PAGE_SIZE, (u32) RX_PAGES);
9132 
9133 	BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
9134 		(u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
9135 
9136 	BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD);
9137 
9138 	BCE_PRINTF(
9139 		"----------------------------"
9140 		"   rx_bd data   "
9141 		"----------------------------\n");
9142 
9143 	/* Now print out the rx_bd's themselves. */
9144 	for (int i = 0; i < count; i++) {
9145 		rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
9146 		bce_dump_rxbd(sc, rx_prod, rxbd);
9147 		rx_prod = RX_CHAIN_IDX(rx_prod + 1);
9148 	}
9149 
9150 	BCE_PRINTF(
9151 		"----------------------------"
9152 		"----------------"
9153 		"----------------------------\n");
9154 }
9155 
9156 
9157 #ifdef BCE_USE_SPLIT_HEADER
9158 /****************************************************************************/
9159 /* Prints out the page chain.                                               */
9160 /*                                                                          */
9161 /* Returns:                                                                 */
9162 /*   Nothing.                                                               */
9163 /****************************************************************************/
9164 static __attribute__ ((noinline)) void
9165 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
9166 {
9167 	struct rx_bd *pgbd;
9168 
9169 	/* First some info about the page chain structure. */
9170 	BCE_PRINTF(
9171 		"----------------------------"
9172 		"   page chain   "
9173 		"----------------------------\n");
9174 
9175 	BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
9176 		(u32) BCM_PAGE_SIZE, (u32) PG_PAGES);
9177 
9178 	BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
9179 		(u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
9180 
9181 	BCE_PRINTF("total rx_bd    = 0x%08X, max_pg_bd             = 0x%08X\n",
9182 		(u32) TOTAL_PG_BD, (u32) MAX_PG_BD);
9183 
9184 	BCE_PRINTF(
9185 		"----------------------------"
9186 		"   page data    "
9187 		"----------------------------\n");
9188 
9189 	/* Now print out the rx_bd's themselves. */
9190 	for (int i = 0; i < count; i++) {
9191 		pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
9192 		bce_dump_pgbd(sc, pg_prod, pgbd);
9193 		pg_prod = PG_CHAIN_IDX(pg_prod + 1);
9194 	}
9195 
9196 	BCE_PRINTF(
9197 		"----------------------------"
9198 		"----------------"
9199 		"----------------------------\n");
9200 }
9201 #endif
9202 
9203 
9204 /****************************************************************************/
9205 /* Prints out the status block from host memory.                            */
9206 /*                                                                          */
9207 /* Returns:                                                                 */
9208 /*   Nothing.                                                               */
9209 /****************************************************************************/
9210 static __attribute__ ((noinline)) void
9211 bce_dump_status_block(struct bce_softc *sc)
9212 {
9213 	struct status_block *sblk;
9214 
9215 	sblk = sc->status_block;
9216 
9217    	BCE_PRINTF(
9218 		"----------------------------"
9219 		"  Status Block  "
9220 		"----------------------------\n");
9221 
9222 	BCE_PRINTF("    0x%08X - attn_bits\n",
9223 		sblk->status_attn_bits);
9224 
9225 	BCE_PRINTF("    0x%08X - attn_bits_ack\n",
9226 		sblk->status_attn_bits_ack);
9227 
9228 	BCE_PRINTF("0x%04X(0x%04X) - rx_cons0\n",
9229 		sblk->status_rx_quick_consumer_index0,
9230 		(u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
9231 
9232 	BCE_PRINTF("0x%04X(0x%04X) - tx_cons0\n",
9233 		sblk->status_tx_quick_consumer_index0,
9234 		(u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
9235 
9236 	BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
9237 
9238 	/* Theses indices are not used for normal L2 drivers. */
9239 	if (sblk->status_rx_quick_consumer_index1)
9240 		BCE_PRINTF("0x%04X(0x%04X) - rx_cons1\n",
9241 			sblk->status_rx_quick_consumer_index1,
9242 			(u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
9243 
9244 	if (sblk->status_tx_quick_consumer_index1)
9245 		BCE_PRINTF("0x%04X(0x%04X) - tx_cons1\n",
9246 			sblk->status_tx_quick_consumer_index1,
9247 			(u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
9248 
9249 	if (sblk->status_rx_quick_consumer_index2)
9250 		BCE_PRINTF("0x%04X(0x%04X)- rx_cons2\n",
9251 			sblk->status_rx_quick_consumer_index2,
9252 			(u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
9253 
9254 	if (sblk->status_tx_quick_consumer_index2)
9255 		BCE_PRINTF("0x%04X(0x%04X) - tx_cons2\n",
9256 			sblk->status_tx_quick_consumer_index2,
9257 			(u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
9258 
9259 	if (sblk->status_rx_quick_consumer_index3)
9260 		BCE_PRINTF("0x%04X(0x%04X) - rx_cons3\n",
9261 			sblk->status_rx_quick_consumer_index3,
9262 			(u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
9263 
9264 	if (sblk->status_tx_quick_consumer_index3)
9265 		BCE_PRINTF("0x%04X(0x%04X) - tx_cons3\n",
9266 			sblk->status_tx_quick_consumer_index3,
9267 			(u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
9268 
9269 	if (sblk->status_rx_quick_consumer_index4 ||
9270 		sblk->status_rx_quick_consumer_index5)
9271 		BCE_PRINTF("rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
9272 			sblk->status_rx_quick_consumer_index4,
9273 			sblk->status_rx_quick_consumer_index5);
9274 
9275 	if (sblk->status_rx_quick_consumer_index6 ||
9276 		sblk->status_rx_quick_consumer_index7)
9277 		BCE_PRINTF("rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
9278 			sblk->status_rx_quick_consumer_index6,
9279 			sblk->status_rx_quick_consumer_index7);
9280 
9281 	if (sblk->status_rx_quick_consumer_index8 ||
9282 		sblk->status_rx_quick_consumer_index9)
9283 		BCE_PRINTF("rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
9284 			sblk->status_rx_quick_consumer_index8,
9285 			sblk->status_rx_quick_consumer_index9);
9286 
9287 	if (sblk->status_rx_quick_consumer_index10 ||
9288 		sblk->status_rx_quick_consumer_index11)
9289 		BCE_PRINTF("rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
9290 			sblk->status_rx_quick_consumer_index10,
9291 			sblk->status_rx_quick_consumer_index11);
9292 
9293 	if (sblk->status_rx_quick_consumer_index12 ||
9294 		sblk->status_rx_quick_consumer_index13)
9295 		BCE_PRINTF("rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
9296 			sblk->status_rx_quick_consumer_index12,
9297 			sblk->status_rx_quick_consumer_index13);
9298 
9299 	if (sblk->status_rx_quick_consumer_index14 ||
9300 		sblk->status_rx_quick_consumer_index15)
9301 		BCE_PRINTF("rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
9302 			sblk->status_rx_quick_consumer_index14,
9303 			sblk->status_rx_quick_consumer_index15);
9304 
9305 	if (sblk->status_completion_producer_index ||
9306 		sblk->status_cmd_consumer_index)
9307 		BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
9308 			sblk->status_completion_producer_index,
9309 			sblk->status_cmd_consumer_index);
9310 
9311 	BCE_PRINTF(
9312 		"----------------------------"
9313 		"----------------"
9314 		"----------------------------\n");
9315 }
9316 
9317 
9318 /****************************************************************************/
9319 /* Prints out the statistics block from host memory.                        */
9320 /*                                                                          */
9321 /* Returns:                                                                 */
9322 /*   Nothing.                                                               */
9323 /****************************************************************************/
9324 static __attribute__ ((noinline)) void
9325 bce_dump_stats_block(struct bce_softc *sc)
9326 {
9327 	struct statistics_block *sblk;
9328 
9329 	sblk = sc->stats_block;
9330 
9331 	BCE_PRINTF(
9332 		"---------------"
9333 		" Stats Block  (All Stats Not Shown Are 0) "
9334 		"---------------\n");
9335 
9336 	if (sblk->stat_IfHCInOctets_hi
9337 		|| sblk->stat_IfHCInOctets_lo)
9338 		BCE_PRINTF("0x%08X:%08X : "
9339 			"IfHcInOctets\n",
9340 			sblk->stat_IfHCInOctets_hi,
9341 			sblk->stat_IfHCInOctets_lo);
9342 
9343 	if (sblk->stat_IfHCInBadOctets_hi
9344 		|| sblk->stat_IfHCInBadOctets_lo)
9345 		BCE_PRINTF("0x%08X:%08X : "
9346 			"IfHcInBadOctets\n",
9347 			sblk->stat_IfHCInBadOctets_hi,
9348 			sblk->stat_IfHCInBadOctets_lo);
9349 
9350 	if (sblk->stat_IfHCOutOctets_hi
9351 		|| sblk->stat_IfHCOutOctets_lo)
9352 		BCE_PRINTF("0x%08X:%08X : "
9353 			"IfHcOutOctets\n",
9354 			sblk->stat_IfHCOutOctets_hi,
9355 			sblk->stat_IfHCOutOctets_lo);
9356 
9357 	if (sblk->stat_IfHCOutBadOctets_hi
9358 		|| sblk->stat_IfHCOutBadOctets_lo)
9359 		BCE_PRINTF("0x%08X:%08X : "
9360 			"IfHcOutBadOctets\n",
9361 			sblk->stat_IfHCOutBadOctets_hi,
9362 			sblk->stat_IfHCOutBadOctets_lo);
9363 
9364 	if (sblk->stat_IfHCInUcastPkts_hi
9365 		|| sblk->stat_IfHCInUcastPkts_lo)
9366 		BCE_PRINTF("0x%08X:%08X : "
9367 			"IfHcInUcastPkts\n",
9368 			sblk->stat_IfHCInUcastPkts_hi,
9369 			sblk->stat_IfHCInUcastPkts_lo);
9370 
9371 	if (sblk->stat_IfHCInBroadcastPkts_hi
9372 		|| sblk->stat_IfHCInBroadcastPkts_lo)
9373 		BCE_PRINTF("0x%08X:%08X : "
9374 			"IfHcInBroadcastPkts\n",
9375 			sblk->stat_IfHCInBroadcastPkts_hi,
9376 			sblk->stat_IfHCInBroadcastPkts_lo);
9377 
9378 	if (sblk->stat_IfHCInMulticastPkts_hi
9379 		|| sblk->stat_IfHCInMulticastPkts_lo)
9380 		BCE_PRINTF("0x%08X:%08X : "
9381 			"IfHcInMulticastPkts\n",
9382 			sblk->stat_IfHCInMulticastPkts_hi,
9383 			sblk->stat_IfHCInMulticastPkts_lo);
9384 
9385 	if (sblk->stat_IfHCOutUcastPkts_hi
9386 		|| sblk->stat_IfHCOutUcastPkts_lo)
9387 		BCE_PRINTF("0x%08X:%08X : "
9388 			"IfHcOutUcastPkts\n",
9389 			sblk->stat_IfHCOutUcastPkts_hi,
9390 			sblk->stat_IfHCOutUcastPkts_lo);
9391 
9392 	if (sblk->stat_IfHCOutBroadcastPkts_hi
9393 		|| sblk->stat_IfHCOutBroadcastPkts_lo)
9394 		BCE_PRINTF("0x%08X:%08X : "
9395 			"IfHcOutBroadcastPkts\n",
9396 			sblk->stat_IfHCOutBroadcastPkts_hi,
9397 			sblk->stat_IfHCOutBroadcastPkts_lo);
9398 
9399 	if (sblk->stat_IfHCOutMulticastPkts_hi
9400 		|| sblk->stat_IfHCOutMulticastPkts_lo)
9401 		BCE_PRINTF("0x%08X:%08X : "
9402 			"IfHcOutMulticastPkts\n",
9403 			sblk->stat_IfHCOutMulticastPkts_hi,
9404 			sblk->stat_IfHCOutMulticastPkts_lo);
9405 
9406 	if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors)
9407 		BCE_PRINTF("         0x%08X : "
9408 			"emac_tx_stat_dot3statsinternalmactransmiterrors\n",
9409 			sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
9410 
9411 	if (sblk->stat_Dot3StatsCarrierSenseErrors)
9412 		BCE_PRINTF("         0x%08X : Dot3StatsCarrierSenseErrors\n",
9413 			sblk->stat_Dot3StatsCarrierSenseErrors);
9414 
9415 	if (sblk->stat_Dot3StatsFCSErrors)
9416 		BCE_PRINTF("         0x%08X : Dot3StatsFCSErrors\n",
9417 			sblk->stat_Dot3StatsFCSErrors);
9418 
9419 	if (sblk->stat_Dot3StatsAlignmentErrors)
9420 		BCE_PRINTF("         0x%08X : Dot3StatsAlignmentErrors\n",
9421 			sblk->stat_Dot3StatsAlignmentErrors);
9422 
9423 	if (sblk->stat_Dot3StatsSingleCollisionFrames)
9424 		BCE_PRINTF("         0x%08X : Dot3StatsSingleCollisionFrames\n",
9425 			sblk->stat_Dot3StatsSingleCollisionFrames);
9426 
9427 	if (sblk->stat_Dot3StatsMultipleCollisionFrames)
9428 		BCE_PRINTF("         0x%08X : Dot3StatsMultipleCollisionFrames\n",
9429 			sblk->stat_Dot3StatsMultipleCollisionFrames);
9430 
9431 	if (sblk->stat_Dot3StatsDeferredTransmissions)
9432 		BCE_PRINTF("         0x%08X : Dot3StatsDeferredTransmissions\n",
9433 			sblk->stat_Dot3StatsDeferredTransmissions);
9434 
9435 	if (sblk->stat_Dot3StatsExcessiveCollisions)
9436 		BCE_PRINTF("         0x%08X : Dot3StatsExcessiveCollisions\n",
9437 			sblk->stat_Dot3StatsExcessiveCollisions);
9438 
9439 	if (sblk->stat_Dot3StatsLateCollisions)
9440 		BCE_PRINTF("         0x%08X : Dot3StatsLateCollisions\n",
9441 			sblk->stat_Dot3StatsLateCollisions);
9442 
9443 	if (sblk->stat_EtherStatsCollisions)
9444 		BCE_PRINTF("         0x%08X : EtherStatsCollisions\n",
9445 			sblk->stat_EtherStatsCollisions);
9446 
9447 	if (sblk->stat_EtherStatsFragments)
9448 		BCE_PRINTF("         0x%08X : EtherStatsFragments\n",
9449 			sblk->stat_EtherStatsFragments);
9450 
9451 	if (sblk->stat_EtherStatsJabbers)
9452 		BCE_PRINTF("         0x%08X : EtherStatsJabbers\n",
9453 			sblk->stat_EtherStatsJabbers);
9454 
9455 	if (sblk->stat_EtherStatsUndersizePkts)
9456 		BCE_PRINTF("         0x%08X : EtherStatsUndersizePkts\n",
9457 			sblk->stat_EtherStatsUndersizePkts);
9458 
9459 	if (sblk->stat_EtherStatsOverrsizePkts)
9460 		BCE_PRINTF("         0x%08X : EtherStatsOverrsizePkts\n",
9461 			sblk->stat_EtherStatsOverrsizePkts);
9462 
9463 	if (sblk->stat_EtherStatsPktsRx64Octets)
9464 		BCE_PRINTF("         0x%08X : EtherStatsPktsRx64Octets\n",
9465 			sblk->stat_EtherStatsPktsRx64Octets);
9466 
9467 	if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets)
9468 		BCE_PRINTF("         0x%08X : EtherStatsPktsRx65Octetsto127Octets\n",
9469 			sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
9470 
9471 	if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets)
9472 		BCE_PRINTF("         0x%08X : EtherStatsPktsRx128Octetsto255Octets\n",
9473 			sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
9474 
9475 	if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets)
9476 		BCE_PRINTF("         0x%08X : EtherStatsPktsRx256Octetsto511Octets\n",
9477 			sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
9478 
9479 	if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets)
9480 		BCE_PRINTF("         0x%08X : EtherStatsPktsRx512Octetsto1023Octets\n",
9481 			sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
9482 
9483 	if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets)
9484 		BCE_PRINTF("         0x%08X : EtherStatsPktsRx1024Octetsto1522Octets\n",
9485 			sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
9486 
9487 	if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets)
9488 		BCE_PRINTF("         0x%08X : EtherStatsPktsRx1523Octetsto9022Octets\n",
9489 			sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
9490 
9491 	if (sblk->stat_EtherStatsPktsTx64Octets)
9492 		BCE_PRINTF("         0x%08X : EtherStatsPktsTx64Octets\n",
9493 			sblk->stat_EtherStatsPktsTx64Octets);
9494 
9495 	if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets)
9496 		BCE_PRINTF("         0x%08X : EtherStatsPktsTx65Octetsto127Octets\n",
9497 			sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
9498 
9499 	if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets)
9500 		BCE_PRINTF("         0x%08X : EtherStatsPktsTx128Octetsto255Octets\n",
9501 			sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
9502 
9503 	if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets)
9504 		BCE_PRINTF("         0x%08X : EtherStatsPktsTx256Octetsto511Octets\n",
9505 			sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
9506 
9507 	if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets)
9508 		BCE_PRINTF("         0x%08X : EtherStatsPktsTx512Octetsto1023Octets\n",
9509 			sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
9510 
9511 	if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets)
9512 		BCE_PRINTF("         0x%08X : EtherStatsPktsTx1024Octetsto1522Octets\n",
9513 			sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
9514 
9515 	if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets)
9516 		BCE_PRINTF("         0x%08X : EtherStatsPktsTx1523Octetsto9022Octets\n",
9517 			sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
9518 
9519 	if (sblk->stat_XonPauseFramesReceived)
9520 		BCE_PRINTF("         0x%08X : XonPauseFramesReceived\n",
9521 			sblk->stat_XonPauseFramesReceived);
9522 
9523 	if (sblk->stat_XoffPauseFramesReceived)
9524 	   BCE_PRINTF("          0x%08X : XoffPauseFramesReceived\n",
9525 			sblk->stat_XoffPauseFramesReceived);
9526 
9527 	if (sblk->stat_OutXonSent)
9528 		BCE_PRINTF("         0x%08X : OutXonSent\n",
9529 			sblk->stat_OutXonSent);
9530 
9531 	if (sblk->stat_OutXoffSent)
9532 		BCE_PRINTF("         0x%08X : OutXoffSent\n",
9533 			sblk->stat_OutXoffSent);
9534 
9535 	if (sblk->stat_FlowControlDone)
9536 		BCE_PRINTF("         0x%08X : FlowControlDone\n",
9537 			sblk->stat_FlowControlDone);
9538 
9539 	if (sblk->stat_MacControlFramesReceived)
9540 		BCE_PRINTF("         0x%08X : MacControlFramesReceived\n",
9541 			sblk->stat_MacControlFramesReceived);
9542 
9543 	if (sblk->stat_XoffStateEntered)
9544 		BCE_PRINTF("         0x%08X : XoffStateEntered\n",
9545 			sblk->stat_XoffStateEntered);
9546 
9547 	if (sblk->stat_IfInFramesL2FilterDiscards)
9548 		BCE_PRINTF("         0x%08X : IfInFramesL2FilterDiscards\n",
9549 			sblk->stat_IfInFramesL2FilterDiscards);
9550 
9551 	if (sblk->stat_IfInRuleCheckerDiscards)
9552 		BCE_PRINTF("         0x%08X : IfInRuleCheckerDiscards\n",
9553 			sblk->stat_IfInRuleCheckerDiscards);
9554 
9555 	if (sblk->stat_IfInFTQDiscards)
9556 		BCE_PRINTF("         0x%08X : IfInFTQDiscards\n",
9557 			sblk->stat_IfInFTQDiscards);
9558 
9559 	if (sblk->stat_IfInMBUFDiscards)
9560 		BCE_PRINTF("         0x%08X : IfInMBUFDiscards\n",
9561 			sblk->stat_IfInMBUFDiscards);
9562 
9563 	if (sblk->stat_IfInRuleCheckerP4Hit)
9564 		BCE_PRINTF("         0x%08X : IfInRuleCheckerP4Hit\n",
9565 			sblk->stat_IfInRuleCheckerP4Hit);
9566 
9567 	if (sblk->stat_CatchupInRuleCheckerDiscards)
9568 		BCE_PRINTF("         0x%08X : CatchupInRuleCheckerDiscards\n",
9569 			sblk->stat_CatchupInRuleCheckerDiscards);
9570 
9571 	if (sblk->stat_CatchupInFTQDiscards)
9572 		BCE_PRINTF("         0x%08X : CatchupInFTQDiscards\n",
9573 			sblk->stat_CatchupInFTQDiscards);
9574 
9575 	if (sblk->stat_CatchupInMBUFDiscards)
9576 		BCE_PRINTF("         0x%08X : CatchupInMBUFDiscards\n",
9577 			sblk->stat_CatchupInMBUFDiscards);
9578 
9579 	if (sblk->stat_CatchupInRuleCheckerP4Hit)
9580 		BCE_PRINTF("         0x%08X : CatchupInRuleCheckerP4Hit\n",
9581 			sblk->stat_CatchupInRuleCheckerP4Hit);
9582 
9583 	BCE_PRINTF(
9584 		"----------------------------"
9585 		"----------------"
9586 		"----------------------------\n");
9587 }
9588 
9589 
9590 /****************************************************************************/
9591 /* Prints out a summary of the driver state.                                */
9592 /*                                                                          */
9593 /* Returns:                                                                 */
9594 /*   Nothing.                                                               */
9595 /****************************************************************************/
9596 static __attribute__ ((noinline)) void
9597 bce_dump_driver_state(struct bce_softc *sc)
9598 {
9599 	u32 val_hi, val_lo;
9600 
9601 	BCE_PRINTF(
9602 		"-----------------------------"
9603 		" Driver State "
9604 		"-----------------------------\n");
9605 
9606 	val_hi = BCE_ADDR_HI(sc);
9607 	val_lo = BCE_ADDR_LO(sc);
9608 	BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual address\n",
9609 		val_hi, val_lo);
9610 
9611 	val_hi = BCE_ADDR_HI(sc->bce_vhandle);
9612 	val_lo = BCE_ADDR_LO(sc->bce_vhandle);
9613 	BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual address\n",
9614 		val_hi, val_lo);
9615 
9616 	val_hi = BCE_ADDR_HI(sc->status_block);
9617 	val_lo = BCE_ADDR_LO(sc->status_block);
9618 	BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block virtual address\n",
9619 		val_hi, val_lo);
9620 
9621 	val_hi = BCE_ADDR_HI(sc->stats_block);
9622 	val_lo = BCE_ADDR_LO(sc->stats_block);
9623 	BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block virtual address\n",
9624 		val_hi, val_lo);
9625 
9626 	val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
9627 	val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
9628 	BCE_PRINTF(
9629 		"0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain virtual adddress\n",
9630 		val_hi, val_lo);
9631 
9632 	val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
9633 	val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
9634 	BCE_PRINTF(
9635 		"0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain virtual address\n",
9636 		val_hi, val_lo);
9637 
9638 #ifdef BCE_USE_SPLIT_HEADER
9639 	val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
9640 	val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
9641 	BCE_PRINTF(
9642 		"0x%08X:%08X - (sc->pg_bd_chain) page chain virtual address\n",
9643 		val_hi, val_lo);
9644 #endif
9645 
9646 	val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
9647 	val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
9648 	BCE_PRINTF(
9649 		"0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n",
9650 		val_hi, val_lo);
9651 
9652 	val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
9653 	val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
9654 	BCE_PRINTF(
9655 		"0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n",
9656 		val_hi, val_lo);
9657 
9658 #ifdef BCE_USE_SPLIT_HEADER
9659 	val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
9660 	val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
9661 	BCE_PRINTF(
9662 		"0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain virtual address\n",
9663 		val_hi, val_lo);
9664 #endif
9665 
9666 	BCE_PRINTF("         0x%08X - (sc->interrupts_generated) h/w intrs\n",
9667 		sc->interrupts_generated);
9668 
9669 	BCE_PRINTF("         0x%08X - (sc->rx_interrupts) rx interrupts handled\n",
9670 		sc->rx_interrupts);
9671 
9672 	BCE_PRINTF("         0x%08X - (sc->tx_interrupts) tx interrupts handled\n",
9673 		sc->tx_interrupts);
9674 
9675 	BCE_PRINTF("         0x%08X - (sc->last_status_idx) status block index\n",
9676 		sc->last_status_idx);
9677 
9678 	BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer index\n",
9679 		sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
9680 
9681 	BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer index\n",
9682 		sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
9683 
9684 	BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n",
9685 		sc->tx_prod_bseq);
9686 
9687 	BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx mbufs allocated\n",
9688 		sc->debug_tx_mbuf_alloc);
9689 
9690 	BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
9691 		sc->used_tx_bd);
9692 
9693 	BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
9694 		sc->tx_hi_watermark, sc->max_tx_bd);
9695 
9696 	BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer index\n",
9697 		sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
9698 
9699 	BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer index\n",
9700 		sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
9701 
9702 	BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n",
9703 		sc->rx_prod_bseq);
9704 
9705 	BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx mbufs allocated\n",
9706 		sc->debug_rx_mbuf_alloc);
9707 
9708 	BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free rx_bd's\n",
9709 		sc->free_rx_bd);
9710 
9711 #ifdef BCE_USE_SPLIT_HEADER
9712 	BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer index\n",
9713 		sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
9714 
9715 	BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer index\n",
9716 		sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
9717 
9718 	BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page mbufs allocated\n",
9719 		sc->debug_pg_mbuf_alloc);
9720 
9721 	BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page rx_bd's\n",
9722 		sc->free_pg_bd);
9723 
9724 	BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low watermark\n",
9725 		sc->pg_low_watermark, sc->max_pg_bd);
9726 #endif
9727 
9728 	BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed) "
9729 		"mbuf alloc failures\n",
9730 		sc->mbuf_alloc_failed);
9731 
9732 	BCE_PRINTF("         0x%08X - (sc->debug_mbuf_sim_alloc_failed) "
9733 		"simulated mbuf alloc failures\n",
9734 		sc->debug_mbuf_sim_alloc_failed);
9735 
9736 	BCE_PRINTF("         0x%08X - (sc->bce_flags) bce mac flags\n",
9737 		sc->bce_flags);
9738 
9739 	BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) bce phy flags\n",
9740 		sc->bce_phy_flags);
9741 
9742 	BCE_PRINTF(
9743 		"----------------------------"
9744 		"----------------"
9745 		"----------------------------\n");
9746 }
9747 
9748 
9749 /****************************************************************************/
9750 /* Prints out the hardware state through a summary of important register,   */
9751 /* followed by a complete register dump.                                    */
9752 /*                                                                          */
9753 /* Returns:                                                                 */
9754 /*   Nothing.                                                               */
9755 /****************************************************************************/
9756 static __attribute__ ((noinline)) void
9757 bce_dump_hw_state(struct bce_softc *sc)
9758 {
9759 	u32 val;
9760 
9761 	BCE_PRINTF(
9762 		"----------------------------"
9763 		" Hardware State "
9764 		"----------------------------\n");
9765 
9766 	BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver);
9767 
9768 	val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
9769 	BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
9770 		val, BCE_MISC_ENABLE_STATUS_BITS);
9771 
9772 	val = REG_RD(sc, BCE_DMA_STATUS);
9773 	BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", val, BCE_DMA_STATUS);
9774 
9775 	val = REG_RD(sc, BCE_CTX_STATUS);
9776 	BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", val, BCE_CTX_STATUS);
9777 
9778 	val = REG_RD(sc, BCE_EMAC_STATUS);
9779 	BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", val, BCE_EMAC_STATUS);
9780 
9781 	val = REG_RD(sc, BCE_RPM_STATUS);
9782 	BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", val, BCE_RPM_STATUS);
9783 
9784 	val = REG_RD(sc, 0x2004);
9785 	BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", val, 0x2004);
9786 
9787 	val = REG_RD(sc, BCE_RV2P_STATUS);
9788 	BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", val, BCE_RV2P_STATUS);
9789 
9790 	val = REG_RD(sc, 0x2c04);
9791 	BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", val, 0x2c04);
9792 
9793 	val = REG_RD(sc, BCE_TBDR_STATUS);
9794 	BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", val, BCE_TBDR_STATUS);
9795 
9796 	val = REG_RD(sc, BCE_TDMA_STATUS);
9797 	BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", val, BCE_TDMA_STATUS);
9798 
9799 	val = REG_RD(sc, BCE_HC_STATUS);
9800 	BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", val, BCE_HC_STATUS);
9801 
9802 	val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
9803 	BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val, BCE_TXP_CPU_STATE);
9804 
9805 	val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
9806 	BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val, BCE_TPAT_CPU_STATE);
9807 
9808 	val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
9809 	BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val, BCE_RXP_CPU_STATE);
9810 
9811 	val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
9812 	BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE);
9813 
9814 	val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
9815 	BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", val, BCE_MCP_CPU_STATE);
9816 
9817 	val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
9818 	BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE);
9819 
9820 	BCE_PRINTF(
9821 		"----------------------------"
9822 		"----------------"
9823 		"----------------------------\n");
9824 
9825 	BCE_PRINTF(
9826 		"----------------------------"
9827 		" Register  Dump "
9828 		"----------------------------\n");
9829 
9830 	for (int i = 0x400; i < 0x8000; i += 0x10) {
9831 		BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9832 			i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
9833 			REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
9834 	}
9835 
9836 	BCE_PRINTF(
9837 		"----------------------------"
9838 		"----------------"
9839 		"----------------------------\n");
9840 }
9841 
9842 
9843 /****************************************************************************/
9844 /* Prints out the mailbox queue registers.                                  */
9845 /*                                                                          */
9846 /* Returns:                                                                 */
9847 /*   Nothing.                                                               */
9848 /****************************************************************************/
9849 static __attribute__ ((noinline)) void
9850 bce_dump_mq_regs(struct bce_softc *sc)
9851 {
9852 	BCE_PRINTF(
9853 		"----------------------------"
9854 		"    MQ Regs     "
9855 		"----------------------------\n");
9856 
9857 	BCE_PRINTF(
9858 		"----------------------------"
9859 		"----------------"
9860 		"----------------------------\n");
9861 
9862 	for (int i = 0x3c00; i < 0x4000; i += 0x10) {
9863 		BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9864 			i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
9865 			REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
9866 	}
9867 
9868 	BCE_PRINTF(
9869 		"----------------------------"
9870 		"----------------"
9871 		"----------------------------\n");
9872 }
9873 
9874 
9875 /****************************************************************************/
9876 /* Prints out the bootcode state.                                           */
9877 /*                                                                          */
9878 /* Returns:                                                                 */
9879 /*   Nothing.                                                               */
9880 /****************************************************************************/
9881 static __attribute__ ((noinline)) void
9882 bce_dump_bc_state(struct bce_softc *sc)
9883 {
9884 	u32 val;
9885 
9886 	BCE_PRINTF(
9887 		"----------------------------"
9888 		" Bootcode State "
9889 		"----------------------------\n");
9890 
9891 	BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver);
9892 
9893 	val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_RESET_TYPE);
9894 	BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
9895 		val, BCE_BC_RESET_TYPE);
9896 
9897 	val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE);
9898 	BCE_PRINTF("0x%08X - (0x%06X) state\n",
9899 		val, BCE_BC_STATE);
9900 
9901 	val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_CONDITION);
9902 	BCE_PRINTF("0x%08X - (0x%06X) condition\n",
9903 		val, BCE_BC_CONDITION);
9904 
9905 	val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE_DEBUG_CMD);
9906 	BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
9907 		val, BCE_BC_STATE_DEBUG_CMD);
9908 
9909 	BCE_PRINTF(
9910 		"----------------------------"
9911 		"----------------"
9912 		"----------------------------\n");
9913 }
9914 
9915 
9916 /****************************************************************************/
9917 /* Prints out the TXP processor state.                                      */
9918 /*                                                                          */
9919 /* Returns:                                                                 */
9920 /*   Nothing.                                                               */
9921 /****************************************************************************/
9922 static __attribute__ ((noinline)) void
9923 bce_dump_txp_state(struct bce_softc *sc, int regs)
9924 {
9925 	u32 val;
9926 	u32 fw_version[3];
9927 
9928 	BCE_PRINTF(
9929 		"----------------------------"
9930 		"   TXP  State   "
9931 		"----------------------------\n");
9932 
9933 	for (int i = 0; i < 3; i++)
9934 		fw_version[i] = htonl(REG_RD_IND(sc,
9935 			(BCE_TXP_SCRATCH + 0x10 + i * 4)));
9936 	BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
9937 
9938 	val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
9939 	BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", val, BCE_TXP_CPU_MODE);
9940 
9941 	val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
9942 	BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val, BCE_TXP_CPU_STATE);
9943 
9944 	val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
9945 	BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", val,
9946 		BCE_TXP_CPU_EVENT_MASK);
9947 
9948 	if (regs) {
9949 		BCE_PRINTF(
9950 			"----------------------------"
9951 			" Register  Dump "
9952 			"----------------------------\n");
9953 
9954 		for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
9955 			/* Skip the big blank spaces */
9956 			if (i < 0x454000 && i > 0x5ffff)
9957 				BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9958 					i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
9959 					REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
9960 		}
9961 	}
9962 
9963 	BCE_PRINTF(
9964 		"----------------------------"
9965 		"----------------"
9966 		"----------------------------\n");
9967 }
9968 
9969 
9970 /****************************************************************************/
9971 /* Prints out the RXP processor state.                                      */
9972 /*                                                                          */
9973 /* Returns:                                                                 */
9974 /*   Nothing.                                                               */
9975 /****************************************************************************/
9976 static __attribute__ ((noinline)) void
9977 bce_dump_rxp_state(struct bce_softc *sc, int regs)
9978 {
9979 	u32 val;
9980 	u32 fw_version[3];
9981 
9982 	BCE_PRINTF(
9983 		"----------------------------"
9984 		"   RXP  State   "
9985 		"----------------------------\n");
9986 
9987 	for (int i = 0; i < 3; i++)
9988 		fw_version[i] = htonl(REG_RD_IND(sc,
9989 			(BCE_RXP_SCRATCH + 0x10 + i * 4)));
9990 	BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
9991 
9992 	val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
9993 	BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", val, BCE_RXP_CPU_MODE);
9994 
9995 	val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
9996 	BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val, BCE_RXP_CPU_STATE);
9997 
9998 	val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
9999 	BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", val,
10000 		BCE_RXP_CPU_EVENT_MASK);
10001 
10002 	if (regs) {
10003 		BCE_PRINTF(
10004 			"----------------------------"
10005 			" Register  Dump "
10006 			"----------------------------\n");
10007 
10008 		for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
10009 			/* Skip the big blank sapces */
10010 			if (i < 0xc5400 && i > 0xdffff)
10011 				BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10012 	 				i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
10013 					REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
10014 		}
10015 	}
10016 
10017 	BCE_PRINTF(
10018 		"----------------------------"
10019 		"----------------"
10020 		"----------------------------\n");
10021 }
10022 
10023 
10024 /****************************************************************************/
10025 /* Prints out the TPAT processor state.                                     */
10026 /*                                                                          */
10027 /* Returns:                                                                 */
10028 /*   Nothing.                                                               */
10029 /****************************************************************************/
10030 static __attribute__ ((noinline)) void
10031 bce_dump_tpat_state(struct bce_softc *sc, int regs)
10032 {
10033 	u32 val;
10034 	u32 fw_version[3];
10035 
10036 	BCE_PRINTF(
10037 		"----------------------------"
10038 		"   TPAT State   "
10039 		"----------------------------\n");
10040 
10041 	for (int i = 0; i < 3; i++)
10042 		fw_version[i] = htonl(REG_RD_IND(sc,
10043 			(BCE_TPAT_SCRATCH + 0x410 + i * 4)));
10044 	BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10045 
10046 	val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
10047 	BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", val, BCE_TPAT_CPU_MODE);
10048 
10049 	val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
10050 	BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val, BCE_TPAT_CPU_STATE);
10051 
10052 	val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
10053 	BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", val,
10054 		BCE_TPAT_CPU_EVENT_MASK);
10055 
10056 	if (regs) {
10057 		BCE_PRINTF(
10058 			"----------------------------"
10059 			" Register  Dump "
10060 			"----------------------------\n");
10061 
10062 		for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
10063 			/* Skip the big blank spaces */
10064 			if (i < 0x854000 && i > 0x9ffff)
10065 				BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10066 					i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
10067 					REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
10068 		}
10069 	}
10070 
10071 	BCE_PRINTF(
10072 		"----------------------------"
10073 		"----------------"
10074 		"----------------------------\n");
10075 }
10076 
10077 
10078 /****************************************************************************/
10079 /* Prints out the Command Procesor (CP) state.                              */
10080 /*                                                                          */
10081 /* Returns:                                                                 */
10082 /*   Nothing.                                                               */
10083 /****************************************************************************/
10084 static __attribute__ ((noinline)) void
10085 bce_dump_cp_state(struct bce_softc *sc, int regs)
10086 {
10087 	u32 val;
10088 	u32 fw_version[3];
10089 
10090 	BCE_PRINTF(
10091 		"----------------------------"
10092 		"    CP State    "
10093 		"----------------------------\n");
10094 
10095 	for (int i = 0; i < 3; i++)
10096 		fw_version[i] = htonl(REG_RD_IND(sc,
10097 			(BCE_CP_SCRATCH + 0x10 + i * 4)));
10098 	BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10099 
10100 	val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
10101 	BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", val, BCE_CP_CPU_MODE);
10102 
10103 	val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
10104 	BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE);
10105 
10106 	val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
10107 	BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
10108 		BCE_CP_CPU_EVENT_MASK);
10109 
10110 	if (regs) {
10111 		BCE_PRINTF(
10112 			"----------------------------"
10113 			" Register  Dump "
10114 			"----------------------------\n");
10115 
10116 		for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
10117 			/* Skip the big blank spaces */
10118 			if (i < 0x185400 && i > 0x19ffff)
10119 				BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10120 					i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
10121 					REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
10122 		}
10123 	}
10124 
10125 	BCE_PRINTF(
10126 		"----------------------------"
10127 		"----------------"
10128 		"----------------------------\n");
10129 }
10130 
10131 
10132 /****************************************************************************/
10133 /* Prints out the Completion Procesor (COM) state.                          */
10134 /*                                                                          */
10135 /* Returns:                                                                 */
10136 /*   Nothing.                                                               */
10137 /****************************************************************************/
10138 static __attribute__ ((noinline)) void
10139 bce_dump_com_state(struct bce_softc *sc, int regs)
10140 {
10141 	u32 val;
10142 	u32 fw_version[3];
10143 
10144 	BCE_PRINTF(
10145 		"----------------------------"
10146 		"   COM State    "
10147 		"----------------------------\n");
10148 
10149 	for (int i = 0; i < 3; i++)
10150 		fw_version[i] = htonl(REG_RD_IND(sc,
10151 			(BCE_COM_SCRATCH + 0x10 + i * 4)));
10152 	BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10153 
10154 	val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
10155 	BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", val, BCE_COM_CPU_MODE);
10156 
10157 	val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
10158 	BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE);
10159 
10160 	val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
10161 	BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
10162 		BCE_COM_CPU_EVENT_MASK);
10163 
10164 	if (regs) {
10165 		BCE_PRINTF(
10166 			"----------------------------"
10167 			" Register  Dump "
10168 			"----------------------------\n");
10169 
10170 		for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
10171 			BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10172 				i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
10173 				REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
10174 		}
10175 	}
10176 
10177 	BCE_PRINTF(
10178 		"----------------------------"
10179 		"----------------"
10180 		"----------------------------\n");
10181 }
10182 
10183 
10184 /****************************************************************************/
10185 /* Prints out the driver state and then enters the debugger.                */
10186 /*                                                                          */
10187 /* Returns:                                                                 */
10188 /*   Nothing.                                                               */
10189 /****************************************************************************/
10190 static void
10191 bce_breakpoint(struct bce_softc *sc)
10192 {
10193 
10194 	/*
10195 	 * Unreachable code to silence compiler warnings
10196 	 * about unused functions.
10197 	 */
10198 	if (0) {
10199 		bce_freeze_controller(sc);
10200 		bce_unfreeze_controller(sc);
10201 		bce_dump_enet(sc, NULL);
10202    		bce_dump_txbd(sc, 0, NULL);
10203 		bce_dump_rxbd(sc, 0, NULL);
10204 		bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD);
10205 		bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
10206 		bce_dump_l2fhdr(sc, 0, NULL);
10207 		bce_dump_ctx(sc, RX_CID);
10208 		bce_dump_ftqs(sc);
10209 		bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
10210 		bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
10211 		bce_dump_status_block(sc);
10212 		bce_dump_stats_block(sc);
10213 		bce_dump_driver_state(sc);
10214 		bce_dump_hw_state(sc);
10215 		bce_dump_bc_state(sc);
10216 		bce_dump_txp_state(sc, 0);
10217 		bce_dump_rxp_state(sc, 0);
10218 		bce_dump_tpat_state(sc, 0);
10219 		bce_dump_cp_state(sc, 0);
10220 		bce_dump_com_state(sc, 0);
10221 #ifdef BCE_USE_SPLIT_HEADER
10222 		bce_dump_pgbd(sc, 0, NULL);
10223 		bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD);
10224 		bce_dump_pg_chain(sc, 0, USABLE_PG_BD);
10225 #endif
10226 	}
10227 
10228 	bce_dump_status_block(sc);
10229 	bce_dump_driver_state(sc);
10230 
10231 	/* Call the debugger. */
10232 	breakpoint();
10233 
10234 	return;
10235 }
10236 #endif
10237 
10238