1 /*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54 #include "opt_bce.h" 55 56 #include <dev/bce/if_bcereg.h> 57 #include <dev/bce/if_bcefw.h> 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89 #endif 90 91 /****************************************************************************/ 92 /* PCI Device ID Table */ 93 /* */ 94 /* Used by bce_probe() to identify the devices supported by this driver. */ 95 /****************************************************************************/ 96 #define BCE_DEVDESC_MAX 64 97 98 static struct bce_type bce_devs[] = { 99 /* BCM5706C Controllers and OEM boards. */ 100 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 101 "HP NC370T Multifunction Gigabit Server Adapter" }, 102 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 103 "HP NC370i Multifunction Gigabit Server Adapter" }, 104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 105 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 107 "HP NC371i Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 109 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 110 111 /* BCM5706S controllers and OEM boards. */ 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 113 "HP NC370F Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 116 117 /* BCM5708C controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 119 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 121 "HP NC373i Multifunction Gigabit Server Adapter" }, 122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 123 "HP NC374m PCIe Multifunction Adapter" }, 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 125 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 126 127 /* BCM5708S controllers and OEM boards. */ 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 129 "HP NC373m Multifunction Gigabit Server Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 131 "HP NC373i Multifunction Gigabit Server Adapter" }, 132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 133 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 135 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 136 137 /* BCM5709C controllers and OEM boards. */ 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 139 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 141 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 143 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 144 145 /* BCM5709S controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 147 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 149 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 151 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 152 153 /* BCM5716 controllers and OEM boards. */ 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 155 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 156 157 { 0, 0, 0, 0, NULL } 158 }; 159 160 161 /****************************************************************************/ 162 /* Supported Flash NVRAM device data. */ 163 /****************************************************************************/ 164 static struct flash_spec flash_table[] = 165 { 166 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 167 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 168 169 /* Slow EEPROM */ 170 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 171 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 172 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 173 "EEPROM - slow"}, 174 /* Expansion entry 0001 */ 175 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 178 "Entry 0001"}, 179 /* Saifun SA25F010 (non-buffered flash) */ 180 /* strap, cfg1, & write1 need updates */ 181 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 184 "Non-buffered flash (128kB)"}, 185 /* Saifun SA25F020 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 190 "Non-buffered flash (256kB)"}, 191 /* Expansion entry 0100 */ 192 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0100"}, 196 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 197 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 198 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 199 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 200 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 201 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 202 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 204 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 205 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 206 /* Saifun SA25F005 (non-buffered flash) */ 207 /* strap, cfg1, & write1 need updates */ 208 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 210 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 211 "Non-buffered flash (64kB)"}, 212 /* Fast EEPROM */ 213 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 214 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 215 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 216 "EEPROM - fast"}, 217 /* Expansion entry 1001 */ 218 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 221 "Entry 1001"}, 222 /* Expansion entry 1010 */ 223 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 226 "Entry 1010"}, 227 /* ATMEL AT45DB011B (buffered flash) */ 228 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 230 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 231 "Buffered flash (128kB)"}, 232 /* Expansion entry 1100 */ 233 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 236 "Entry 1100"}, 237 /* Expansion entry 1101 */ 238 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 1101"}, 242 /* Ateml Expansion entry 1110 */ 243 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 244 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 245 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 246 "Entry 1110 (Atmel)"}, 247 /* ATMEL AT45DB021B (buffered flash) */ 248 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 251 "Buffered flash (256kB)"}, 252 }; 253 254 /* 255 * The BCM5709 controllers transparently handle the 256 * differences between Atmel 264 byte pages and all 257 * flash devices which use 256 byte pages, so no 258 * logical-to-physical mapping is required in the 259 * driver. 260 */ 261 static struct flash_spec flash_5709 = { 262 .flags = BCE_NV_BUFFERED, 263 .page_bits = BCM5709_FLASH_PAGE_BITS, 264 .page_size = BCM5709_FLASH_PAGE_SIZE, 265 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 266 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 267 .name = "5709/5716 buffered flash (256kB)", 268 }; 269 270 271 /****************************************************************************/ 272 /* FreeBSD device entry points. */ 273 /****************************************************************************/ 274 static int bce_probe (device_t); 275 static int bce_attach (device_t); 276 static int bce_detach (device_t); 277 static int bce_shutdown (device_t); 278 279 280 /****************************************************************************/ 281 /* BCE Debug Data Structure Dump Routines */ 282 /****************************************************************************/ 283 #ifdef BCE_DEBUG 284 static u32 bce_reg_rd (struct bce_softc *, u32); 285 static void bce_reg_wr (struct bce_softc *, u32, u32); 286 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 287 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 288 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 289 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 290 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 291 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 292 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 293 static void bce_dump_txbd (struct bce_softc *, 294 int, struct tx_bd *); 295 static void bce_dump_rxbd (struct bce_softc *, 296 int, struct rx_bd *); 297 static void bce_dump_pgbd (struct bce_softc *, 298 int, struct rx_bd *); 299 static void bce_dump_l2fhdr (struct bce_softc *, 300 int, struct l2_fhdr *); 301 static void bce_dump_ctx (struct bce_softc *, u16); 302 static void bce_dump_ftqs (struct bce_softc *); 303 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 304 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 305 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 306 static void bce_dump_status_block (struct bce_softc *); 307 static void bce_dump_stats_block (struct bce_softc *); 308 static void bce_dump_driver_state (struct bce_softc *); 309 static void bce_dump_hw_state (struct bce_softc *); 310 static void bce_dump_shmem_state (struct bce_softc *); 311 static void bce_dump_mq_regs (struct bce_softc *); 312 static void bce_dump_bc_state (struct bce_softc *); 313 static void bce_dump_txp_state (struct bce_softc *, int); 314 static void bce_dump_rxp_state (struct bce_softc *, int); 315 static void bce_dump_tpat_state (struct bce_softc *, int); 316 static void bce_dump_cp_state (struct bce_softc *, int); 317 static void bce_dump_com_state (struct bce_softc *, int); 318 static void bce_dump_rv2p_state (struct bce_softc *); 319 static void bce_breakpoint (struct bce_softc *); 320 #endif /*BCE_DEBUG */ 321 322 323 /****************************************************************************/ 324 /* BCE Register/Memory Access Routines */ 325 /****************************************************************************/ 326 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 327 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 328 static void bce_shmem_wr (struct bce_softc *, u32, u32); 329 static u32 bce_shmem_rd (struct bce_softc *, u32); 330 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 331 static int bce_miibus_read_reg (device_t, int, int); 332 static int bce_miibus_write_reg (device_t, int, int, int); 333 static void bce_miibus_statchg (device_t); 334 335 #ifdef BCE_DEBUG 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 337 #ifdef BCE_NVRAM_WRITE_SUPPORT 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 339 #endif 340 #endif 341 342 /****************************************************************************/ 343 /* BCE NVRAM Access Routines */ 344 /****************************************************************************/ 345 static int bce_acquire_nvram_lock (struct bce_softc *); 346 static int bce_release_nvram_lock (struct bce_softc *); 347 static void bce_enable_nvram_access(struct bce_softc *); 348 static void bce_disable_nvram_access(struct bce_softc *); 349 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 350 static int bce_init_nvram (struct bce_softc *); 351 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 352 static int bce_nvram_test (struct bce_softc *); 353 #ifdef BCE_NVRAM_WRITE_SUPPORT 354 static int bce_enable_nvram_write (struct bce_softc *); 355 static void bce_disable_nvram_write(struct bce_softc *); 356 static int bce_nvram_erase_page (struct bce_softc *, u32); 357 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 358 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 359 #endif 360 361 /****************************************************************************/ 362 /* */ 363 /****************************************************************************/ 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 365 static void bce_get_media (struct bce_softc *); 366 static void bce_init_media (struct bce_softc *); 367 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 368 static int bce_dma_alloc (device_t); 369 static void bce_dma_free (struct bce_softc *); 370 static void bce_release_resources (struct bce_softc *); 371 372 /****************************************************************************/ 373 /* BCE Firmware Synchronization and Load */ 374 /****************************************************************************/ 375 static int bce_fw_sync (struct bce_softc *, u32); 376 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 377 static void bce_load_cpu_fw (struct bce_softc *, 378 struct cpu_reg *, struct fw_info *); 379 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 380 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 381 static void bce_start_rxp_cpu (struct bce_softc *); 382 static void bce_init_rxp_cpu (struct bce_softc *); 383 static void bce_init_txp_cpu (struct bce_softc *); 384 static void bce_init_tpat_cpu (struct bce_softc *); 385 static void bce_init_cp_cpu (struct bce_softc *); 386 static void bce_init_com_cpu (struct bce_softc *); 387 static void bce_init_cpus (struct bce_softc *); 388 389 static void bce_print_adapter_info (struct bce_softc *); 390 static void bce_probe_pci_caps (device_t, struct bce_softc *); 391 static void bce_stop (struct bce_softc *); 392 static int bce_reset (struct bce_softc *, u32); 393 static int bce_chipinit (struct bce_softc *); 394 static int bce_blockinit (struct bce_softc *); 395 396 static int bce_init_tx_chain (struct bce_softc *); 397 static void bce_free_tx_chain (struct bce_softc *); 398 399 static int bce_get_rx_buf (struct bce_softc *, 400 struct mbuf *, u16 *, u16 *, u32 *); 401 static int bce_init_rx_chain (struct bce_softc *); 402 static void bce_fill_rx_chain (struct bce_softc *); 403 static void bce_free_rx_chain (struct bce_softc *); 404 405 static int bce_get_pg_buf (struct bce_softc *, 406 struct mbuf *, u16 *, u16 *); 407 static int bce_init_pg_chain (struct bce_softc *); 408 static void bce_fill_pg_chain (struct bce_softc *); 409 static void bce_free_pg_chain (struct bce_softc *); 410 411 static struct mbuf *bce_tso_setup (struct bce_softc *, 412 struct mbuf **, u16 *); 413 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 414 static void bce_start_locked (struct ifnet *); 415 static void bce_start (struct ifnet *); 416 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 417 static void bce_watchdog (struct bce_softc *); 418 static int bce_ifmedia_upd (struct ifnet *); 419 static int bce_ifmedia_upd_locked (struct ifnet *); 420 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 421 static void bce_init_locked (struct bce_softc *); 422 static void bce_init (void *); 423 static void bce_mgmt_init_locked (struct bce_softc *sc); 424 425 static int bce_init_ctx (struct bce_softc *); 426 static void bce_get_mac_addr (struct bce_softc *); 427 static void bce_set_mac_addr (struct bce_softc *); 428 static void bce_phy_intr (struct bce_softc *); 429 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 430 static void bce_rx_intr (struct bce_softc *); 431 static void bce_tx_intr (struct bce_softc *); 432 static void bce_disable_intr (struct bce_softc *); 433 static void bce_enable_intr (struct bce_softc *, int); 434 435 static void bce_intr (void *); 436 static void bce_set_rx_mode (struct bce_softc *); 437 static void bce_stats_update (struct bce_softc *); 438 static void bce_tick (void *); 439 static void bce_pulse (void *); 440 static void bce_add_sysctls (struct bce_softc *); 441 442 443 /****************************************************************************/ 444 /* FreeBSD device dispatch table. */ 445 /****************************************************************************/ 446 static device_method_t bce_methods[] = { 447 /* Device interface (device_if.h) */ 448 DEVMETHOD(device_probe, bce_probe), 449 DEVMETHOD(device_attach, bce_attach), 450 DEVMETHOD(device_detach, bce_detach), 451 DEVMETHOD(device_shutdown, bce_shutdown), 452 /* Supported by device interface but not used here. */ 453 /* DEVMETHOD(device_identify, bce_identify), */ 454 /* DEVMETHOD(device_suspend, bce_suspend), */ 455 /* DEVMETHOD(device_resume, bce_resume), */ 456 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 457 458 /* Bus interface (bus_if.h) */ 459 DEVMETHOD(bus_print_child, bus_generic_print_child), 460 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 461 462 /* MII interface (miibus_if.h) */ 463 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 464 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 465 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 466 /* Supported by MII interface but not used here. */ 467 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 468 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 469 470 { 0, 0 } 471 }; 472 473 static driver_t bce_driver = { 474 "bce", 475 bce_methods, 476 sizeof(struct bce_softc) 477 }; 478 479 static devclass_t bce_devclass; 480 481 MODULE_DEPEND(bce, pci, 1, 1, 1); 482 MODULE_DEPEND(bce, ether, 1, 1, 1); 483 MODULE_DEPEND(bce, miibus, 1, 1, 1); 484 485 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 486 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 487 488 489 /****************************************************************************/ 490 /* Tunable device values */ 491 /****************************************************************************/ 492 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 493 494 /* Allowable values are TRUE or FALSE */ 495 static int bce_verbose = TRUE; 496 TUNABLE_INT("hw.bce.verbose", &bce_verbose); 497 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 498 "Verbose output enable/disable"); 499 500 /* Allowable values are TRUE or FALSE */ 501 static int bce_tso_enable = TRUE; 502 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 503 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 504 "TSO Enable/Disable"); 505 506 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 507 /* ToDo: Add MSI-X support. */ 508 static int bce_msi_enable = 1; 509 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 510 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 511 "MSI-X|MSI|INTx selector"); 512 513 /* Allowable values are 1, 2, 4, 8. */ 514 static int bce_rx_pages = DEFAULT_RX_PAGES; 515 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 516 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 517 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 518 519 /* Allowable values are 1, 2, 4, 8. */ 520 static int bce_tx_pages = DEFAULT_TX_PAGES; 521 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 522 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 523 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 524 525 /* Allowable values are TRUE or FALSE. */ 526 static int bce_hdr_split = TRUE; 527 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 528 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 529 "Frame header/payload splitting Enable/Disable"); 530 531 /* Allowable values are TRUE or FALSE. */ 532 static int bce_strict_rx_mtu = FALSE; 533 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 534 SYSCTL_UINT(_hw_bce, OID_AUTO, loose_rx_mtu, CTLFLAG_RDTUN, 535 &bce_strict_rx_mtu, 0, 536 "Enable/Disable strict RX frame size checking"); 537 538 /* Allowable values are 0 ... 100 */ 539 #ifdef BCE_DEBUG 540 /* Generate 1 interrupt for every transmit completion. */ 541 static int bce_tx_quick_cons_trip_int = 1; 542 #else 543 /* Generate 1 interrupt for every 20 transmit completions. */ 544 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 545 #endif 546 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 547 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 548 &bce_tx_quick_cons_trip_int, 0, 549 "Transmit BD trip point during interrupts"); 550 551 /* Allowable values are 0 ... 100 */ 552 /* Generate 1 interrupt for every transmit completion. */ 553 #ifdef BCE_DEBUG 554 static int bce_tx_quick_cons_trip = 1; 555 #else 556 /* Generate 1 interrupt for every 20 transmit completions. */ 557 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 558 #endif 559 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 560 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 561 &bce_tx_quick_cons_trip, 0, 562 "Transmit BD trip point"); 563 564 /* Allowable values are 0 ... 100 */ 565 #ifdef BCE_DEBUG 566 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 567 static int bce_tx_ticks_int = 0; 568 #else 569 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 570 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 571 #endif 572 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 573 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 574 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 575 576 /* Allowable values are 0 ... 100 */ 577 #ifdef BCE_DEBUG 578 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 579 static int bce_tx_ticks = 0; 580 #else 581 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 582 static int bce_tx_ticks = DEFAULT_TX_TICKS; 583 #endif 584 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 585 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 586 &bce_tx_ticks, 0, "Transmit ticks count"); 587 588 /* Allowable values are 1 ... 100 */ 589 #ifdef BCE_DEBUG 590 /* Generate 1 interrupt for every received frame. */ 591 static int bce_rx_quick_cons_trip_int = 1; 592 #else 593 /* Generate 1 interrupt for every 6 received frames. */ 594 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 595 #endif 596 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 597 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 598 &bce_rx_quick_cons_trip_int, 0, 599 "Receive BD trip point duirng interrupts"); 600 601 /* Allowable values are 1 ... 100 */ 602 #ifdef BCE_DEBUG 603 /* Generate 1 interrupt for every received frame. */ 604 static int bce_rx_quick_cons_trip = 1; 605 #else 606 /* Generate 1 interrupt for every 6 received frames. */ 607 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 608 #endif 609 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 610 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 611 &bce_rx_quick_cons_trip, 0, 612 "Receive BD trip point"); 613 614 /* Allowable values are 0 ... 100 */ 615 #ifdef BCE_DEBUG 616 /* Generate an int. if 0us have elapsed since the last received frame. */ 617 static int bce_rx_ticks_int = 0; 618 #else 619 /* Generate an int. if 18us have elapsed since the last received frame. */ 620 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 621 #endif 622 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 623 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 624 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 625 626 /* Allowable values are 0 ... 100 */ 627 #ifdef BCE_DEBUG 628 /* Generate an int. if 0us have elapsed since the last received frame. */ 629 static int bce_rx_ticks = 0; 630 #else 631 /* Generate an int. if 18us have elapsed since the last received frame. */ 632 static int bce_rx_ticks = DEFAULT_RX_TICKS; 633 #endif 634 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 635 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 636 &bce_rx_ticks, 0, "Receive ticks count"); 637 638 639 /****************************************************************************/ 640 /* Device probe function. */ 641 /* */ 642 /* Compares the device to the driver's list of supported devices and */ 643 /* reports back to the OS whether this is the right driver for the device. */ 644 /* */ 645 /* Returns: */ 646 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 647 /****************************************************************************/ 648 static int 649 bce_probe(device_t dev) 650 { 651 struct bce_type *t; 652 struct bce_softc *sc; 653 char *descbuf; 654 u16 vid = 0, did = 0, svid = 0, sdid = 0; 655 656 t = bce_devs; 657 658 sc = device_get_softc(dev); 659 bzero(sc, sizeof(struct bce_softc)); 660 sc->bce_unit = device_get_unit(dev); 661 sc->bce_dev = dev; 662 663 /* Get the data for the device to be probed. */ 664 vid = pci_get_vendor(dev); 665 did = pci_get_device(dev); 666 svid = pci_get_subvendor(dev); 667 sdid = pci_get_subdevice(dev); 668 669 DBPRINT(sc, BCE_EXTREME_LOAD, 670 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 671 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 672 673 /* Look through the list of known devices for a match. */ 674 while(t->bce_name != NULL) { 675 676 if ((vid == t->bce_vid) && (did == t->bce_did) && 677 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 678 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 679 680 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 681 682 if (descbuf == NULL) 683 return(ENOMEM); 684 685 /* Print out the device identity. */ 686 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 687 t->bce_name, (((pci_read_config(dev, 688 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 689 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 690 691 device_set_desc_copy(dev, descbuf); 692 free(descbuf, M_TEMP); 693 return(BUS_PROBE_DEFAULT); 694 } 695 t++; 696 } 697 698 return(ENXIO); 699 } 700 701 702 /****************************************************************************/ 703 /* PCI Capabilities Probe Function. */ 704 /* */ 705 /* Walks the PCI capabiites list for the device to find what features are */ 706 /* supported. */ 707 /* */ 708 /* Returns: */ 709 /* None. */ 710 /****************************************************************************/ 711 static void 712 bce_print_adapter_info(struct bce_softc *sc) 713 { 714 int i = 0; 715 716 DBENTER(BCE_VERBOSE_LOAD); 717 718 if (bce_verbose || bootverbose) { 719 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 720 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 721 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 722 723 724 /* Bus info. */ 725 if (sc->bce_flags & BCE_PCIE_FLAG) { 726 printf("Bus (PCIe x%d, ", sc->link_width); 727 switch (sc->link_speed) { 728 case 1: printf("2.5Gbps); "); break; 729 case 2: printf("5Gbps); "); break; 730 default: printf("Unknown link speed); "); 731 } 732 } else { 733 printf("Bus (PCI%s, %s, %dMHz); ", 734 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 735 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 736 "32-bit" : "64-bit"), sc->bus_speed_mhz); 737 } 738 739 /* Firmware version and device features. */ 740 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 741 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 742 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 743 744 if (bce_hdr_split == TRUE) { 745 printf("SPLT"); 746 i++; 747 } 748 749 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 750 if (i > 0) printf("|"); 751 printf("MSI"); i++; 752 } 753 754 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 755 if (i > 0) printf("|"); 756 printf("MSI-X"); i++; 757 } 758 759 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 760 if (i > 0) printf("|"); 761 printf("2.5G"); i++; 762 } 763 764 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 765 if (i > 0) printf("|"); 766 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 767 } else { 768 printf(")\n"); 769 } 770 771 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 772 sc->bce_rx_quick_cons_trip_int, 773 sc->bce_rx_quick_cons_trip, 774 sc->bce_rx_ticks_int, 775 sc->bce_rx_ticks, 776 sc->bce_tx_quick_cons_trip_int, 777 sc->bce_tx_quick_cons_trip, 778 sc->bce_tx_ticks_int, 779 sc->bce_tx_ticks); 780 781 } 782 783 DBEXIT(BCE_VERBOSE_LOAD); 784 } 785 786 787 /****************************************************************************/ 788 /* PCI Capabilities Probe Function. */ 789 /* */ 790 /* Walks the PCI capabiites list for the device to find what features are */ 791 /* supported. */ 792 /* */ 793 /* Returns: */ 794 /* None. */ 795 /****************************************************************************/ 796 static void 797 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 798 { 799 u32 reg; 800 801 DBENTER(BCE_VERBOSE_LOAD); 802 803 /* Check if PCI-X capability is enabled. */ 804 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 805 if (reg != 0) 806 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 807 } 808 809 /* Check if PCIe capability is enabled. */ 810 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 811 if (reg != 0) { 812 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 813 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 814 "0x%08X\n", link_status); 815 sc->link_speed = link_status & 0xf; 816 sc->link_width = (link_status >> 4) & 0x3f; 817 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 818 sc->bce_flags |= BCE_PCIE_FLAG; 819 } 820 } 821 822 /* Check if MSI capability is enabled. */ 823 if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { 824 if (reg != 0) 825 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 826 } 827 828 /* Check if MSI-X capability is enabled. */ 829 if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { 830 if (reg != 0) 831 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 832 } 833 834 DBEXIT(BCE_VERBOSE_LOAD); 835 } 836 837 838 /****************************************************************************/ 839 /* Load and validate user tunable settings. */ 840 /* */ 841 /* Returns: */ 842 /* Nothing. */ 843 /****************************************************************************/ 844 static void 845 bce_set_tunables(struct bce_softc *sc) 846 { 847 /* Set sysctl values for RX page count. */ 848 switch (bce_rx_pages) { 849 case 1: 850 /* fall-through */ 851 case 2: 852 /* fall-through */ 853 case 4: 854 /* fall-through */ 855 case 8: 856 sc->rx_pages = bce_rx_pages; 857 break; 858 default: 859 sc->rx_pages = DEFAULT_RX_PAGES; 860 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 861 "hw.bce.rx_pages! Setting default of %d.\n", 862 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 863 } 864 865 /* ToDo: Consider allowing user setting for pg_pages. */ 866 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 867 868 /* Set sysctl values for TX page count. */ 869 switch (bce_tx_pages) { 870 case 1: 871 /* fall-through */ 872 case 2: 873 /* fall-through */ 874 case 4: 875 /* fall-through */ 876 case 8: 877 sc->tx_pages = bce_tx_pages; 878 break; 879 default: 880 sc->tx_pages = DEFAULT_TX_PAGES; 881 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 882 "hw.bce.tx_pages! Setting default of %d.\n", 883 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 884 } 885 886 /* 887 * Validate the TX trip point (i.e. the number of 888 * TX completions before a status block update is 889 * generated and an interrupt is asserted. 890 */ 891 if (bce_tx_quick_cons_trip_int <= 100) { 892 sc->bce_tx_quick_cons_trip_int = 893 bce_tx_quick_cons_trip_int; 894 } else { 895 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 896 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 897 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 898 DEFAULT_TX_QUICK_CONS_TRIP_INT); 899 sc->bce_tx_quick_cons_trip_int = 900 DEFAULT_TX_QUICK_CONS_TRIP_INT; 901 } 902 903 if (bce_tx_quick_cons_trip <= 100) { 904 sc->bce_tx_quick_cons_trip = 905 bce_tx_quick_cons_trip; 906 } else { 907 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 908 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 909 __FILE__, __LINE__, bce_tx_quick_cons_trip, 910 DEFAULT_TX_QUICK_CONS_TRIP); 911 sc->bce_tx_quick_cons_trip = 912 DEFAULT_TX_QUICK_CONS_TRIP; 913 } 914 915 /* 916 * Validate the TX ticks count (i.e. the maximum amount 917 * of time to wait after the last TX completion has 918 * occurred before a status block update is generated 919 * and an interrupt is asserted. 920 */ 921 if (bce_tx_ticks_int <= 100) { 922 sc->bce_tx_ticks_int = 923 bce_tx_ticks_int; 924 } else { 925 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 926 "hw.bce.tx_ticks_int! Setting default of %d.\n", 927 __FILE__, __LINE__, bce_tx_ticks_int, 928 DEFAULT_TX_TICKS_INT); 929 sc->bce_tx_ticks_int = 930 DEFAULT_TX_TICKS_INT; 931 } 932 933 if (bce_tx_ticks <= 100) { 934 sc->bce_tx_ticks = 935 bce_tx_ticks; 936 } else { 937 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 938 "hw.bce.tx_ticks! Setting default of %d.\n", 939 __FILE__, __LINE__, bce_tx_ticks, 940 DEFAULT_TX_TICKS); 941 sc->bce_tx_ticks = 942 DEFAULT_TX_TICKS; 943 } 944 945 /* 946 * Validate the RX trip point (i.e. the number of 947 * RX frames received before a status block update is 948 * generated and an interrupt is asserted. 949 */ 950 if (bce_rx_quick_cons_trip_int <= 100) { 951 sc->bce_rx_quick_cons_trip_int = 952 bce_rx_quick_cons_trip_int; 953 } else { 954 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 955 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 956 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 957 DEFAULT_RX_QUICK_CONS_TRIP_INT); 958 sc->bce_rx_quick_cons_trip_int = 959 DEFAULT_RX_QUICK_CONS_TRIP_INT; 960 } 961 962 if (bce_rx_quick_cons_trip <= 100) { 963 sc->bce_rx_quick_cons_trip = 964 bce_rx_quick_cons_trip; 965 } else { 966 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 967 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 968 __FILE__, __LINE__, bce_rx_quick_cons_trip, 969 DEFAULT_RX_QUICK_CONS_TRIP); 970 sc->bce_rx_quick_cons_trip = 971 DEFAULT_RX_QUICK_CONS_TRIP; 972 } 973 974 /* 975 * Validate the RX ticks count (i.e. the maximum amount 976 * of time to wait after the last RX frame has been 977 * received before a status block update is generated 978 * and an interrupt is asserted. 979 */ 980 if (bce_rx_ticks_int <= 100) { 981 sc->bce_rx_ticks_int = bce_rx_ticks_int; 982 } else { 983 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 984 "hw.bce.rx_ticks_int! Setting default of %d.\n", 985 __FILE__, __LINE__, bce_rx_ticks_int, 986 DEFAULT_RX_TICKS_INT); 987 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 988 } 989 990 if (bce_rx_ticks <= 100) { 991 sc->bce_rx_ticks = bce_rx_ticks; 992 } else { 993 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 994 "hw.bce.rx_ticks! Setting default of %d.\n", 995 __FILE__, __LINE__, bce_rx_ticks, 996 DEFAULT_RX_TICKS); 997 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 998 } 999 1000 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1001 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1002 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1003 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1004 __FILE__, __LINE__); 1005 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1006 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1007 } 1008 1009 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1010 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1011 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1012 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1013 __FILE__, __LINE__); 1014 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1015 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1016 } 1017 1018 } 1019 1020 1021 /****************************************************************************/ 1022 /* Device attach function. */ 1023 /* */ 1024 /* Allocates device resources, performs secondary chip identification, */ 1025 /* resets and initializes the hardware, and initializes driver instance */ 1026 /* variables. */ 1027 /* */ 1028 /* Returns: */ 1029 /* 0 on success, positive value on failure. */ 1030 /****************************************************************************/ 1031 static int 1032 bce_attach(device_t dev) 1033 { 1034 struct bce_softc *sc; 1035 struct ifnet *ifp; 1036 u32 val; 1037 int error, rid, rc = 0; 1038 1039 sc = device_get_softc(dev); 1040 sc->bce_dev = dev; 1041 1042 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1043 1044 sc->bce_unit = device_get_unit(dev); 1045 1046 /* Set initial device and PHY flags */ 1047 sc->bce_flags = 0; 1048 sc->bce_phy_flags = 0; 1049 1050 bce_set_tunables(sc); 1051 1052 pci_enable_busmaster(dev); 1053 1054 /* Allocate PCI memory resources. */ 1055 rid = PCIR_BAR(0); 1056 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1057 &rid, RF_ACTIVE); 1058 1059 if (sc->bce_res_mem == NULL) { 1060 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1061 __FILE__, __LINE__); 1062 rc = ENXIO; 1063 goto bce_attach_fail; 1064 } 1065 1066 /* Get various resource handles. */ 1067 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1068 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1069 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1070 1071 bce_probe_pci_caps(dev, sc); 1072 1073 rid = 1; 1074 #if 0 1075 /* Try allocating MSI-X interrupts. */ 1076 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1077 (bce_msi_enable >= 2) && 1078 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1079 &rid, RF_ACTIVE)) != NULL)) { 1080 1081 msi_needed = sc->bce_msi_count = 1; 1082 1083 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 1084 (sc->bce_msi_count != msi_needed)) { 1085 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1086 "Received = %d, error = %d\n", __FILE__, __LINE__, 1087 msi_needed, sc->bce_msi_count, error); 1088 sc->bce_msi_count = 0; 1089 pci_release_msi(dev); 1090 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1091 sc->bce_res_irq); 1092 sc->bce_res_irq = NULL; 1093 } else { 1094 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1095 __FUNCTION__); 1096 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1097 sc->bce_intr = bce_intr; 1098 } 1099 } 1100 #endif 1101 1102 /* Try allocating a MSI interrupt. */ 1103 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1104 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 1105 sc->bce_msi_count = 1; 1106 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 1107 BCE_PRINTF("%s(%d): MSI allocation failed! " 1108 "error = %d\n", __FILE__, __LINE__, error); 1109 sc->bce_msi_count = 0; 1110 pci_release_msi(dev); 1111 } else { 1112 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1113 "interrupt.\n", __FUNCTION__); 1114 sc->bce_flags |= BCE_USING_MSI_FLAG; 1115 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1116 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 1117 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1118 sc->bce_irq_rid = 1; 1119 sc->bce_intr = bce_intr; 1120 } 1121 } 1122 1123 /* Try allocating a legacy interrupt. */ 1124 if (sc->bce_msi_count == 0) { 1125 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1126 __FUNCTION__); 1127 rid = 0; 1128 sc->bce_intr = bce_intr; 1129 } 1130 1131 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1132 &rid, RF_SHAREABLE | RF_ACTIVE); 1133 1134 sc->bce_irq_rid = rid; 1135 1136 /* Report any IRQ allocation errors. */ 1137 if (sc->bce_res_irq == NULL) { 1138 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1139 __FILE__, __LINE__); 1140 rc = ENXIO; 1141 goto bce_attach_fail; 1142 } 1143 1144 /* Initialize mutex for the current device instance. */ 1145 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1146 1147 /* 1148 * Configure byte swap and enable indirect register access. 1149 * Rely on CPU to do target byte swapping on big endian systems. 1150 * Access to registers outside of PCI configurtion space are not 1151 * valid until this is done. 1152 */ 1153 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1154 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1155 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1156 1157 /* Save ASIC revsion info. */ 1158 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1159 1160 /* Weed out any non-production controller revisions. */ 1161 switch(BCE_CHIP_ID(sc)) { 1162 case BCE_CHIP_ID_5706_A0: 1163 case BCE_CHIP_ID_5706_A1: 1164 case BCE_CHIP_ID_5708_A0: 1165 case BCE_CHIP_ID_5708_B0: 1166 case BCE_CHIP_ID_5709_A0: 1167 case BCE_CHIP_ID_5709_B0: 1168 case BCE_CHIP_ID_5709_B1: 1169 case BCE_CHIP_ID_5709_B2: 1170 BCE_PRINTF("%s(%d): Unsupported controller " 1171 "revision (%c%d)!\n", __FILE__, __LINE__, 1172 (((pci_read_config(dev, PCIR_REVID, 4) & 1173 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1174 PCIR_REVID, 4) & 0xf)); 1175 rc = ENODEV; 1176 goto bce_attach_fail; 1177 } 1178 1179 /* 1180 * The embedded PCIe to PCI-X bridge (EPB) 1181 * in the 5708 cannot address memory above 1182 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1183 */ 1184 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1185 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1186 else 1187 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1188 1189 /* 1190 * Find the base address for shared memory access. 1191 * Newer versions of bootcode use a signature and offset 1192 * while older versions use a fixed address. 1193 */ 1194 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1195 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1196 /* Multi-port devices use different offsets in shared memory. */ 1197 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1198 (pci_get_function(sc->bce_dev) << 2)); 1199 else 1200 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1201 1202 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1203 __FUNCTION__, sc->bce_shmem_base); 1204 1205 /* Fetch the bootcode revision. */ 1206 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1207 for (int i = 0, j = 0; i < 3; i++) { 1208 u8 num; 1209 1210 num = (u8) (val >> (24 - (i * 8))); 1211 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1212 if (num >= k || !skip0 || k == 1) { 1213 sc->bce_bc_ver[j++] = (num / k) + '0'; 1214 skip0 = 0; 1215 } 1216 } 1217 1218 if (i != 2) 1219 sc->bce_bc_ver[j++] = '.'; 1220 } 1221 1222 /* Check if any management firwmare is enabled. */ 1223 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1224 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1225 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1226 1227 /* Allow time for firmware to enter the running state. */ 1228 for (int i = 0; i < 30; i++) { 1229 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1230 if (val & BCE_CONDITION_MFW_RUN_MASK) 1231 break; 1232 DELAY(10000); 1233 } 1234 1235 /* Check if management firmware is running. */ 1236 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1237 val &= BCE_CONDITION_MFW_RUN_MASK; 1238 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1239 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1240 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1241 int i = 0; 1242 1243 /* Read the management firmware version string. */ 1244 for (int j = 0; j < 3; j++) { 1245 val = bce_reg_rd_ind(sc, addr + j * 4); 1246 val = bswap32(val); 1247 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1248 i += 4; 1249 } 1250 } else { 1251 /* May cause firmware synchronization timeouts. */ 1252 BCE_PRINTF("%s(%d): Management firmware enabled " 1253 "but not running!\n", __FILE__, __LINE__); 1254 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1255 1256 /* ToDo: Any action the driver should take? */ 1257 } 1258 } 1259 1260 /* Get PCI bus information (speed and type). */ 1261 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1262 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1263 u32 clkreg; 1264 1265 sc->bce_flags |= BCE_PCIX_FLAG; 1266 1267 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1268 1269 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1270 switch (clkreg) { 1271 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1272 sc->bus_speed_mhz = 133; 1273 break; 1274 1275 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1276 sc->bus_speed_mhz = 100; 1277 break; 1278 1279 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1280 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1281 sc->bus_speed_mhz = 66; 1282 break; 1283 1284 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1285 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1286 sc->bus_speed_mhz = 50; 1287 break; 1288 1289 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1290 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1291 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1292 sc->bus_speed_mhz = 33; 1293 break; 1294 } 1295 } else { 1296 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1297 sc->bus_speed_mhz = 66; 1298 else 1299 sc->bus_speed_mhz = 33; 1300 } 1301 1302 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1303 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1304 1305 /* Reset controller and announce to bootcode that driver is present. */ 1306 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1307 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1308 __FILE__, __LINE__); 1309 rc = ENXIO; 1310 goto bce_attach_fail; 1311 } 1312 1313 /* Initialize the controller. */ 1314 if (bce_chipinit(sc)) { 1315 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1316 __FILE__, __LINE__); 1317 rc = ENXIO; 1318 goto bce_attach_fail; 1319 } 1320 1321 /* Perform NVRAM test. */ 1322 if (bce_nvram_test(sc)) { 1323 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1324 __FILE__, __LINE__); 1325 rc = ENXIO; 1326 goto bce_attach_fail; 1327 } 1328 1329 /* Fetch the permanent Ethernet MAC address. */ 1330 bce_get_mac_addr(sc); 1331 1332 /* 1333 * Trip points control how many BDs 1334 * should be ready before generating an 1335 * interrupt while ticks control how long 1336 * a BD can sit in the chain before 1337 * generating an interrupt. Set the default 1338 * values for the RX and TX chains. 1339 */ 1340 1341 /* Not used for L2. */ 1342 sc->bce_comp_prod_trip_int = 0; 1343 sc->bce_comp_prod_trip = 0; 1344 sc->bce_com_ticks_int = 0; 1345 sc->bce_com_ticks = 0; 1346 sc->bce_cmd_ticks_int = 0; 1347 sc->bce_cmd_ticks = 0; 1348 1349 /* Update statistics once every second. */ 1350 sc->bce_stats_ticks = 1000000 & 0xffff00; 1351 1352 /* Find the media type for the adapter. */ 1353 bce_get_media(sc); 1354 1355 /* Store data needed by PHY driver for backplane applications */ 1356 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1357 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1358 1359 /* Allocate DMA memory resources. */ 1360 if (bce_dma_alloc(dev)) { 1361 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1362 __FILE__, __LINE__); 1363 rc = ENXIO; 1364 goto bce_attach_fail; 1365 } 1366 1367 /* Allocate an ifnet structure. */ 1368 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1369 if (ifp == NULL) { 1370 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1371 __FILE__, __LINE__); 1372 rc = ENXIO; 1373 goto bce_attach_fail; 1374 } 1375 1376 /* Initialize the ifnet interface. */ 1377 ifp->if_softc = sc; 1378 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1379 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1380 ifp->if_ioctl = bce_ioctl; 1381 ifp->if_start = bce_start; 1382 ifp->if_init = bce_init; 1383 ifp->if_mtu = ETHERMTU; 1384 1385 if (bce_tso_enable) { 1386 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1387 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1388 IFCAP_VLAN_HWTSO; 1389 } else { 1390 ifp->if_hwassist = BCE_IF_HWASSIST; 1391 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1392 } 1393 1394 ifp->if_capenable = ifp->if_capabilities; 1395 1396 /* 1397 * Assume standard mbuf sizes for buffer allocation. 1398 * This may change later if the MTU size is set to 1399 * something other than 1500. 1400 */ 1401 bce_get_rx_buffer_sizes(sc, 1402 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1403 1404 /* Recalculate our buffer allocation sizes. */ 1405 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1406 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1407 IFQ_SET_READY(&ifp->if_snd); 1408 1409 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1410 ifp->if_baudrate = IF_Mbps(2500ULL); 1411 else 1412 ifp->if_baudrate = IF_Mbps(1000); 1413 1414 /* Handle any special PHY initialization for SerDes PHYs. */ 1415 bce_init_media(sc); 1416 1417 /* MII child bus by attaching the PHY. */ 1418 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1419 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1420 MII_OFFSET_ANY, MIIF_DOPAUSE); 1421 if (rc != 0) { 1422 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1423 __LINE__); 1424 goto bce_attach_fail; 1425 } 1426 1427 /* Attach to the Ethernet interface list. */ 1428 ether_ifattach(ifp, sc->eaddr); 1429 1430 #if __FreeBSD_version < 500000 1431 callout_init(&sc->bce_tick_callout); 1432 callout_init(&sc->bce_pulse_callout); 1433 #else 1434 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1435 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1436 #endif 1437 1438 /* Hookup IRQ last. */ 1439 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1440 NULL, bce_intr, sc, &sc->bce_intrhand); 1441 1442 if (rc) { 1443 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1444 __FILE__, __LINE__); 1445 bce_detach(dev); 1446 goto bce_attach_exit; 1447 } 1448 1449 /* 1450 * At this point we've acquired all the resources 1451 * we need to run so there's no turning back, we're 1452 * cleared for launch. 1453 */ 1454 1455 /* Print some important debugging info. */ 1456 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1457 1458 /* Add the supported sysctls to the kernel. */ 1459 bce_add_sysctls(sc); 1460 1461 BCE_LOCK(sc); 1462 1463 /* 1464 * The chip reset earlier notified the bootcode that 1465 * a driver is present. We now need to start our pulse 1466 * routine so that the bootcode is reminded that we're 1467 * still running. 1468 */ 1469 bce_pulse(sc); 1470 1471 bce_mgmt_init_locked(sc); 1472 BCE_UNLOCK(sc); 1473 1474 /* Finally, print some useful adapter info */ 1475 bce_print_adapter_info(sc); 1476 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1477 __FUNCTION__, sc); 1478 1479 goto bce_attach_exit; 1480 1481 bce_attach_fail: 1482 bce_release_resources(sc); 1483 1484 bce_attach_exit: 1485 1486 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1487 1488 return(rc); 1489 } 1490 1491 1492 /****************************************************************************/ 1493 /* Device detach function. */ 1494 /* */ 1495 /* Stops the controller, resets the controller, and releases resources. */ 1496 /* */ 1497 /* Returns: */ 1498 /* 0 on success, positive value on failure. */ 1499 /****************************************************************************/ 1500 static int 1501 bce_detach(device_t dev) 1502 { 1503 struct bce_softc *sc = device_get_softc(dev); 1504 struct ifnet *ifp; 1505 u32 msg; 1506 1507 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1508 1509 ifp = sc->bce_ifp; 1510 1511 /* Stop and reset the controller. */ 1512 BCE_LOCK(sc); 1513 1514 /* Stop the pulse so the bootcode can go to driver absent state. */ 1515 callout_stop(&sc->bce_pulse_callout); 1516 1517 bce_stop(sc); 1518 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1519 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1520 else 1521 msg = BCE_DRV_MSG_CODE_UNLOAD; 1522 bce_reset(sc, msg); 1523 1524 BCE_UNLOCK(sc); 1525 1526 ether_ifdetach(ifp); 1527 1528 /* If we have a child device on the MII bus remove it too. */ 1529 bus_generic_detach(dev); 1530 device_delete_child(dev, sc->bce_miibus); 1531 1532 /* Release all remaining resources. */ 1533 bce_release_resources(sc); 1534 1535 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1536 1537 return(0); 1538 } 1539 1540 1541 /****************************************************************************/ 1542 /* Device shutdown function. */ 1543 /* */ 1544 /* Stops and resets the controller. */ 1545 /* */ 1546 /* Returns: */ 1547 /* 0 on success, positive value on failure. */ 1548 /****************************************************************************/ 1549 static int 1550 bce_shutdown(device_t dev) 1551 { 1552 struct bce_softc *sc = device_get_softc(dev); 1553 u32 msg; 1554 1555 DBENTER(BCE_VERBOSE); 1556 1557 BCE_LOCK(sc); 1558 bce_stop(sc); 1559 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1560 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1561 else 1562 msg = BCE_DRV_MSG_CODE_UNLOAD; 1563 bce_reset(sc, msg); 1564 BCE_UNLOCK(sc); 1565 1566 DBEXIT(BCE_VERBOSE); 1567 1568 return (0); 1569 } 1570 1571 1572 #ifdef BCE_DEBUG 1573 /****************************************************************************/ 1574 /* Register read. */ 1575 /* */ 1576 /* Returns: */ 1577 /* The value of the register. */ 1578 /****************************************************************************/ 1579 static u32 1580 bce_reg_rd(struct bce_softc *sc, u32 offset) 1581 { 1582 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1583 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1584 __FUNCTION__, offset, val); 1585 return val; 1586 } 1587 1588 1589 /****************************************************************************/ 1590 /* Register write (16 bit). */ 1591 /* */ 1592 /* Returns: */ 1593 /* Nothing. */ 1594 /****************************************************************************/ 1595 static void 1596 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1597 { 1598 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1599 __FUNCTION__, offset, val); 1600 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1601 } 1602 1603 1604 /****************************************************************************/ 1605 /* Register write. */ 1606 /* */ 1607 /* Returns: */ 1608 /* Nothing. */ 1609 /****************************************************************************/ 1610 static void 1611 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1612 { 1613 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1614 __FUNCTION__, offset, val); 1615 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1616 } 1617 #endif 1618 1619 /****************************************************************************/ 1620 /* Indirect register read. */ 1621 /* */ 1622 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1623 /* configuration space. Using this mechanism avoids issues with posted */ 1624 /* reads but is much slower than memory-mapped I/O. */ 1625 /* */ 1626 /* Returns: */ 1627 /* The value of the register. */ 1628 /****************************************************************************/ 1629 static u32 1630 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1631 { 1632 device_t dev; 1633 dev = sc->bce_dev; 1634 1635 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1636 #ifdef BCE_DEBUG 1637 { 1638 u32 val; 1639 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1640 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1641 __FUNCTION__, offset, val); 1642 return val; 1643 } 1644 #else 1645 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1646 #endif 1647 } 1648 1649 1650 /****************************************************************************/ 1651 /* Indirect register write. */ 1652 /* */ 1653 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1654 /* configuration space. Using this mechanism avoids issues with posted */ 1655 /* writes but is muchh slower than memory-mapped I/O. */ 1656 /* */ 1657 /* Returns: */ 1658 /* Nothing. */ 1659 /****************************************************************************/ 1660 static void 1661 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1662 { 1663 device_t dev; 1664 dev = sc->bce_dev; 1665 1666 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1667 __FUNCTION__, offset, val); 1668 1669 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1670 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1671 } 1672 1673 1674 /****************************************************************************/ 1675 /* Shared memory write. */ 1676 /* */ 1677 /* Writes NetXtreme II shared memory region. */ 1678 /* */ 1679 /* Returns: */ 1680 /* Nothing. */ 1681 /****************************************************************************/ 1682 static void 1683 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1684 { 1685 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1686 "0x%08X\n", __FUNCTION__, val, offset); 1687 1688 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1689 } 1690 1691 1692 /****************************************************************************/ 1693 /* Shared memory read. */ 1694 /* */ 1695 /* Reads NetXtreme II shared memory region. */ 1696 /* */ 1697 /* Returns: */ 1698 /* The 32 bit value read. */ 1699 /****************************************************************************/ 1700 static u32 1701 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1702 { 1703 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1704 1705 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1706 "0x%08X\n", __FUNCTION__, val, offset); 1707 1708 return val; 1709 } 1710 1711 1712 #ifdef BCE_DEBUG 1713 /****************************************************************************/ 1714 /* Context memory read. */ 1715 /* */ 1716 /* The NetXtreme II controller uses context memory to track connection */ 1717 /* information for L2 and higher network protocols. */ 1718 /* */ 1719 /* Returns: */ 1720 /* The requested 32 bit value of context memory. */ 1721 /****************************************************************************/ 1722 static u32 1723 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1724 { 1725 u32 idx, offset, retry_cnt = 5, val; 1726 1727 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1728 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1729 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1730 1731 offset = ctx_offset + cid_addr; 1732 1733 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1734 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1735 1736 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1737 1738 for (idx = 0; idx < retry_cnt; idx++) { 1739 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1740 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1741 break; 1742 DELAY(5); 1743 } 1744 1745 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1746 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1747 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1748 __FILE__, __LINE__, cid_addr, ctx_offset); 1749 1750 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1751 } else { 1752 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1753 val = REG_RD(sc, BCE_CTX_DATA); 1754 } 1755 1756 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1757 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1758 1759 return(val); 1760 } 1761 #endif 1762 1763 1764 /****************************************************************************/ 1765 /* Context memory write. */ 1766 /* */ 1767 /* The NetXtreme II controller uses context memory to track connection */ 1768 /* information for L2 and higher network protocols. */ 1769 /* */ 1770 /* Returns: */ 1771 /* Nothing. */ 1772 /****************************************************************************/ 1773 static void 1774 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1775 { 1776 u32 idx, offset = ctx_offset + cid_addr; 1777 u32 val, retry_cnt = 5; 1778 1779 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1780 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1781 1782 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1783 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1784 __FUNCTION__, cid_addr)); 1785 1786 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1787 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1788 1789 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1790 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1791 1792 for (idx = 0; idx < retry_cnt; idx++) { 1793 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1794 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1795 break; 1796 DELAY(5); 1797 } 1798 1799 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1800 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1801 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1802 __FILE__, __LINE__, cid_addr, ctx_offset); 1803 1804 } else { 1805 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1806 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1807 } 1808 } 1809 1810 1811 /****************************************************************************/ 1812 /* PHY register read. */ 1813 /* */ 1814 /* Implements register reads on the MII bus. */ 1815 /* */ 1816 /* Returns: */ 1817 /* The value of the register. */ 1818 /****************************************************************************/ 1819 static int 1820 bce_miibus_read_reg(device_t dev, int phy, int reg) 1821 { 1822 struct bce_softc *sc; 1823 u32 val; 1824 int i; 1825 1826 sc = device_get_softc(dev); 1827 1828 /* Make sure we are accessing the correct PHY address. */ 1829 if (phy != sc->bce_phy_addr) { 1830 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1831 "for PHY read!\n", phy); 1832 return(0); 1833 } 1834 1835 /* 1836 * The 5709S PHY is an IEEE Clause 45 PHY 1837 * with special mappings to work with IEEE 1838 * Clause 22 register accesses. 1839 */ 1840 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1841 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1842 reg += 0x10; 1843 } 1844 1845 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1846 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1847 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1848 1849 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1850 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1851 1852 DELAY(40); 1853 } 1854 1855 1856 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1857 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1858 BCE_EMAC_MDIO_COMM_START_BUSY; 1859 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1860 1861 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1862 DELAY(10); 1863 1864 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1865 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1866 DELAY(5); 1867 1868 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1869 val &= BCE_EMAC_MDIO_COMM_DATA; 1870 1871 break; 1872 } 1873 } 1874 1875 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1876 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1877 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1878 val = 0x0; 1879 } else { 1880 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1881 } 1882 1883 1884 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1885 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1886 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1887 1888 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1889 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1890 1891 DELAY(40); 1892 } 1893 1894 DB_PRINT_PHY_REG(reg, val); 1895 return (val & 0xffff); 1896 1897 } 1898 1899 1900 /****************************************************************************/ 1901 /* PHY register write. */ 1902 /* */ 1903 /* Implements register writes on the MII bus. */ 1904 /* */ 1905 /* Returns: */ 1906 /* The value of the register. */ 1907 /****************************************************************************/ 1908 static int 1909 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1910 { 1911 struct bce_softc *sc; 1912 u32 val1; 1913 int i; 1914 1915 sc = device_get_softc(dev); 1916 1917 /* Make sure we are accessing the correct PHY address. */ 1918 if (phy != sc->bce_phy_addr) { 1919 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1920 "for PHY write!\n", phy); 1921 return(0); 1922 } 1923 1924 DB_PRINT_PHY_REG(reg, val); 1925 1926 /* 1927 * The 5709S PHY is an IEEE Clause 45 PHY 1928 * with special mappings to work with IEEE 1929 * Clause 22 register accesses. 1930 */ 1931 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1932 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1933 reg += 0x10; 1934 } 1935 1936 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1937 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1938 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1939 1940 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1941 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1942 1943 DELAY(40); 1944 } 1945 1946 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1947 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1948 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1949 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1950 1951 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1952 DELAY(10); 1953 1954 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1955 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1956 DELAY(5); 1957 break; 1958 } 1959 } 1960 1961 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1962 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1963 __FILE__, __LINE__); 1964 1965 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1966 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1967 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1968 1969 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1970 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1971 1972 DELAY(40); 1973 } 1974 1975 return 0; 1976 } 1977 1978 1979 /****************************************************************************/ 1980 /* MII bus status change. */ 1981 /* */ 1982 /* Called by the MII bus driver when the PHY establishes link to set the */ 1983 /* MAC interface registers. */ 1984 /* */ 1985 /* Returns: */ 1986 /* Nothing. */ 1987 /****************************************************************************/ 1988 static void 1989 bce_miibus_statchg(device_t dev) 1990 { 1991 struct bce_softc *sc; 1992 struct mii_data *mii; 1993 int val; 1994 1995 sc = device_get_softc(dev); 1996 1997 DBENTER(BCE_VERBOSE_PHY); 1998 1999 mii = device_get_softc(sc->bce_miibus); 2000 2001 val = REG_RD(sc, BCE_EMAC_MODE); 2002 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2003 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2004 BCE_EMAC_MODE_25G); 2005 2006 /* Set MII or GMII interface based on the PHY speed. */ 2007 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2008 case IFM_10_T: 2009 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2010 DBPRINT(sc, BCE_INFO_PHY, 2011 "Enabling 10Mb interface.\n"); 2012 val |= BCE_EMAC_MODE_PORT_MII_10; 2013 break; 2014 } 2015 /* fall-through */ 2016 case IFM_100_TX: 2017 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2018 val |= BCE_EMAC_MODE_PORT_MII; 2019 break; 2020 case IFM_2500_SX: 2021 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2022 val |= BCE_EMAC_MODE_25G; 2023 /* fall-through */ 2024 case IFM_1000_T: 2025 case IFM_1000_SX: 2026 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2027 val |= BCE_EMAC_MODE_PORT_GMII; 2028 break; 2029 default: 2030 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2031 "default GMII interface.\n"); 2032 val |= BCE_EMAC_MODE_PORT_GMII; 2033 } 2034 2035 /* Set half or full duplex based on PHY settings. */ 2036 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 2037 DBPRINT(sc, BCE_INFO_PHY, 2038 "Setting Half-Duplex interface.\n"); 2039 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2040 } else 2041 DBPRINT(sc, BCE_INFO_PHY, 2042 "Setting Full-Duplex interface.\n"); 2043 2044 REG_WR(sc, BCE_EMAC_MODE, val); 2045 2046 if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) { 2047 DBPRINT(sc, BCE_INFO_PHY, 2048 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2049 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2050 } else { 2051 DBPRINT(sc, BCE_INFO_PHY, 2052 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2053 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2054 } 2055 2056 if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) { 2057 DBPRINT(sc, BCE_INFO_PHY, 2058 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2059 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2060 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2061 } else { 2062 DBPRINT(sc, BCE_INFO_PHY, 2063 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2064 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2065 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2066 } 2067 2068 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2069 2070 DBEXIT(BCE_VERBOSE_PHY); 2071 } 2072 2073 2074 /****************************************************************************/ 2075 /* Acquire NVRAM lock. */ 2076 /* */ 2077 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2078 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2079 /* for use by the driver. */ 2080 /* */ 2081 /* Returns: */ 2082 /* 0 on success, positive value on failure. */ 2083 /****************************************************************************/ 2084 static int 2085 bce_acquire_nvram_lock(struct bce_softc *sc) 2086 { 2087 u32 val; 2088 int j, rc = 0; 2089 2090 DBENTER(BCE_VERBOSE_NVRAM); 2091 2092 /* Request access to the flash interface. */ 2093 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2094 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2095 val = REG_RD(sc, BCE_NVM_SW_ARB); 2096 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2097 break; 2098 2099 DELAY(5); 2100 } 2101 2102 if (j >= NVRAM_TIMEOUT_COUNT) { 2103 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2104 rc = EBUSY; 2105 } 2106 2107 DBEXIT(BCE_VERBOSE_NVRAM); 2108 return (rc); 2109 } 2110 2111 2112 /****************************************************************************/ 2113 /* Release NVRAM lock. */ 2114 /* */ 2115 /* When the caller is finished accessing NVRAM the lock must be released. */ 2116 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2117 /* for use by the driver. */ 2118 /* */ 2119 /* Returns: */ 2120 /* 0 on success, positive value on failure. */ 2121 /****************************************************************************/ 2122 static int 2123 bce_release_nvram_lock(struct bce_softc *sc) 2124 { 2125 u32 val; 2126 int j, rc = 0; 2127 2128 DBENTER(BCE_VERBOSE_NVRAM); 2129 2130 /* 2131 * Relinquish nvram interface. 2132 */ 2133 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2134 2135 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2136 val = REG_RD(sc, BCE_NVM_SW_ARB); 2137 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2138 break; 2139 2140 DELAY(5); 2141 } 2142 2143 if (j >= NVRAM_TIMEOUT_COUNT) { 2144 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2145 rc = EBUSY; 2146 } 2147 2148 DBEXIT(BCE_VERBOSE_NVRAM); 2149 return (rc); 2150 } 2151 2152 2153 #ifdef BCE_NVRAM_WRITE_SUPPORT 2154 /****************************************************************************/ 2155 /* Enable NVRAM write access. */ 2156 /* */ 2157 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2158 /* */ 2159 /* Returns: */ 2160 /* 0 on success, positive value on failure. */ 2161 /****************************************************************************/ 2162 static int 2163 bce_enable_nvram_write(struct bce_softc *sc) 2164 { 2165 u32 val; 2166 int rc = 0; 2167 2168 DBENTER(BCE_VERBOSE_NVRAM); 2169 2170 val = REG_RD(sc, BCE_MISC_CFG); 2171 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2172 2173 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2174 int j; 2175 2176 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2177 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2178 2179 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2180 DELAY(5); 2181 2182 val = REG_RD(sc, BCE_NVM_COMMAND); 2183 if (val & BCE_NVM_COMMAND_DONE) 2184 break; 2185 } 2186 2187 if (j >= NVRAM_TIMEOUT_COUNT) { 2188 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2189 rc = EBUSY; 2190 } 2191 } 2192 2193 DBENTER(BCE_VERBOSE_NVRAM); 2194 return (rc); 2195 } 2196 2197 2198 /****************************************************************************/ 2199 /* Disable NVRAM write access. */ 2200 /* */ 2201 /* When the caller is finished writing to NVRAM write access must be */ 2202 /* disabled. */ 2203 /* */ 2204 /* Returns: */ 2205 /* Nothing. */ 2206 /****************************************************************************/ 2207 static void 2208 bce_disable_nvram_write(struct bce_softc *sc) 2209 { 2210 u32 val; 2211 2212 DBENTER(BCE_VERBOSE_NVRAM); 2213 2214 val = REG_RD(sc, BCE_MISC_CFG); 2215 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2216 2217 DBEXIT(BCE_VERBOSE_NVRAM); 2218 2219 } 2220 #endif 2221 2222 2223 /****************************************************************************/ 2224 /* Enable NVRAM access. */ 2225 /* */ 2226 /* Before accessing NVRAM for read or write operations the caller must */ 2227 /* enabled NVRAM access. */ 2228 /* */ 2229 /* Returns: */ 2230 /* Nothing. */ 2231 /****************************************************************************/ 2232 static void 2233 bce_enable_nvram_access(struct bce_softc *sc) 2234 { 2235 u32 val; 2236 2237 DBENTER(BCE_VERBOSE_NVRAM); 2238 2239 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2240 /* Enable both bits, even on read. */ 2241 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2242 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2243 2244 DBEXIT(BCE_VERBOSE_NVRAM); 2245 } 2246 2247 2248 /****************************************************************************/ 2249 /* Disable NVRAM access. */ 2250 /* */ 2251 /* When the caller is finished accessing NVRAM access must be disabled. */ 2252 /* */ 2253 /* Returns: */ 2254 /* Nothing. */ 2255 /****************************************************************************/ 2256 static void 2257 bce_disable_nvram_access(struct bce_softc *sc) 2258 { 2259 u32 val; 2260 2261 DBENTER(BCE_VERBOSE_NVRAM); 2262 2263 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2264 2265 /* Disable both bits, even after read. */ 2266 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2267 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2268 2269 DBEXIT(BCE_VERBOSE_NVRAM); 2270 } 2271 2272 2273 #ifdef BCE_NVRAM_WRITE_SUPPORT 2274 /****************************************************************************/ 2275 /* Erase NVRAM page before writing. */ 2276 /* */ 2277 /* Non-buffered flash parts require that a page be erased before it is */ 2278 /* written. */ 2279 /* */ 2280 /* Returns: */ 2281 /* 0 on success, positive value on failure. */ 2282 /****************************************************************************/ 2283 static int 2284 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2285 { 2286 u32 cmd; 2287 int j, rc = 0; 2288 2289 DBENTER(BCE_VERBOSE_NVRAM); 2290 2291 /* Buffered flash doesn't require an erase. */ 2292 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2293 goto bce_nvram_erase_page_exit; 2294 2295 /* Build an erase command. */ 2296 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2297 BCE_NVM_COMMAND_DOIT; 2298 2299 /* 2300 * Clear the DONE bit separately, set the NVRAM adress to erase, 2301 * and issue the erase command. 2302 */ 2303 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2304 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2305 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2306 2307 /* Wait for completion. */ 2308 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2309 u32 val; 2310 2311 DELAY(5); 2312 2313 val = REG_RD(sc, BCE_NVM_COMMAND); 2314 if (val & BCE_NVM_COMMAND_DONE) 2315 break; 2316 } 2317 2318 if (j >= NVRAM_TIMEOUT_COUNT) { 2319 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2320 rc = EBUSY; 2321 } 2322 2323 bce_nvram_erase_page_exit: 2324 DBEXIT(BCE_VERBOSE_NVRAM); 2325 return (rc); 2326 } 2327 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2328 2329 2330 /****************************************************************************/ 2331 /* Read a dword (32 bits) from NVRAM. */ 2332 /* */ 2333 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2334 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2335 /* */ 2336 /* Returns: */ 2337 /* 0 on success and the 32 bit value read, positive value on failure. */ 2338 /****************************************************************************/ 2339 static int 2340 bce_nvram_read_dword(struct bce_softc *sc, 2341 u32 offset, u8 *ret_val, u32 cmd_flags) 2342 { 2343 u32 cmd; 2344 int i, rc = 0; 2345 2346 DBENTER(BCE_EXTREME_NVRAM); 2347 2348 /* Build the command word. */ 2349 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2350 2351 /* Calculate the offset for buffered flash if translation is used. */ 2352 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2353 offset = ((offset / sc->bce_flash_info->page_size) << 2354 sc->bce_flash_info->page_bits) + 2355 (offset % sc->bce_flash_info->page_size); 2356 } 2357 2358 /* 2359 * Clear the DONE bit separately, set the address to read, 2360 * and issue the read. 2361 */ 2362 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2363 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2364 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2365 2366 /* Wait for completion. */ 2367 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2368 u32 val; 2369 2370 DELAY(5); 2371 2372 val = REG_RD(sc, BCE_NVM_COMMAND); 2373 if (val & BCE_NVM_COMMAND_DONE) { 2374 val = REG_RD(sc, BCE_NVM_READ); 2375 2376 val = bce_be32toh(val); 2377 memcpy(ret_val, &val, 4); 2378 break; 2379 } 2380 } 2381 2382 /* Check for errors. */ 2383 if (i >= NVRAM_TIMEOUT_COUNT) { 2384 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2385 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2386 rc = EBUSY; 2387 } 2388 2389 DBEXIT(BCE_EXTREME_NVRAM); 2390 return(rc); 2391 } 2392 2393 2394 #ifdef BCE_NVRAM_WRITE_SUPPORT 2395 /****************************************************************************/ 2396 /* Write a dword (32 bits) to NVRAM. */ 2397 /* */ 2398 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2399 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2400 /* enabled NVRAM write access. */ 2401 /* */ 2402 /* Returns: */ 2403 /* 0 on success, positive value on failure. */ 2404 /****************************************************************************/ 2405 static int 2406 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2407 u32 cmd_flags) 2408 { 2409 u32 cmd, val32; 2410 int j, rc = 0; 2411 2412 DBENTER(BCE_VERBOSE_NVRAM); 2413 2414 /* Build the command word. */ 2415 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2416 2417 /* Calculate the offset for buffered flash if translation is used. */ 2418 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2419 offset = ((offset / sc->bce_flash_info->page_size) << 2420 sc->bce_flash_info->page_bits) + 2421 (offset % sc->bce_flash_info->page_size); 2422 } 2423 2424 /* 2425 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2426 * set the NVRAM address to write, and issue the write command 2427 */ 2428 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2429 memcpy(&val32, val, 4); 2430 val32 = htobe32(val32); 2431 REG_WR(sc, BCE_NVM_WRITE, val32); 2432 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2433 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2434 2435 /* Wait for completion. */ 2436 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2437 DELAY(5); 2438 2439 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2440 break; 2441 } 2442 if (j >= NVRAM_TIMEOUT_COUNT) { 2443 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2444 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2445 rc = EBUSY; 2446 } 2447 2448 DBEXIT(BCE_VERBOSE_NVRAM); 2449 return (rc); 2450 } 2451 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2452 2453 2454 /****************************************************************************/ 2455 /* Initialize NVRAM access. */ 2456 /* */ 2457 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2458 /* access that device. */ 2459 /* */ 2460 /* Returns: */ 2461 /* 0 on success, positive value on failure. */ 2462 /****************************************************************************/ 2463 static int 2464 bce_init_nvram(struct bce_softc *sc) 2465 { 2466 u32 val; 2467 int j, entry_count, rc = 0; 2468 struct flash_spec *flash; 2469 2470 DBENTER(BCE_VERBOSE_NVRAM); 2471 2472 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2473 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2474 sc->bce_flash_info = &flash_5709; 2475 goto bce_init_nvram_get_flash_size; 2476 } 2477 2478 /* Determine the selected interface. */ 2479 val = REG_RD(sc, BCE_NVM_CFG1); 2480 2481 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2482 2483 /* 2484 * Flash reconfiguration is required to support additional 2485 * NVRAM devices not directly supported in hardware. 2486 * Check if the flash interface was reconfigured 2487 * by the bootcode. 2488 */ 2489 2490 if (val & 0x40000000) { 2491 /* Flash interface reconfigured by bootcode. */ 2492 2493 DBPRINT(sc,BCE_INFO_LOAD, 2494 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2495 2496 for (j = 0, flash = &flash_table[0]; j < entry_count; 2497 j++, flash++) { 2498 if ((val & FLASH_BACKUP_STRAP_MASK) == 2499 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2500 sc->bce_flash_info = flash; 2501 break; 2502 } 2503 } 2504 } else { 2505 /* Flash interface not yet reconfigured. */ 2506 u32 mask; 2507 2508 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2509 __FUNCTION__); 2510 2511 if (val & (1 << 23)) 2512 mask = FLASH_BACKUP_STRAP_MASK; 2513 else 2514 mask = FLASH_STRAP_MASK; 2515 2516 /* Look for the matching NVRAM device configuration data. */ 2517 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2518 2519 /* Check if the device matches any of the known devices. */ 2520 if ((val & mask) == (flash->strapping & mask)) { 2521 /* Found a device match. */ 2522 sc->bce_flash_info = flash; 2523 2524 /* Request access to the flash interface. */ 2525 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2526 return rc; 2527 2528 /* Reconfigure the flash interface. */ 2529 bce_enable_nvram_access(sc); 2530 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2531 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2532 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2533 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2534 bce_disable_nvram_access(sc); 2535 bce_release_nvram_lock(sc); 2536 2537 break; 2538 } 2539 } 2540 } 2541 2542 /* Check if a matching device was found. */ 2543 if (j == entry_count) { 2544 sc->bce_flash_info = NULL; 2545 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2546 __FILE__, __LINE__); 2547 DBEXIT(BCE_VERBOSE_NVRAM); 2548 return (ENODEV); 2549 } 2550 2551 bce_init_nvram_get_flash_size: 2552 /* Write the flash config data to the shared memory interface. */ 2553 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2554 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2555 if (val) 2556 sc->bce_flash_size = val; 2557 else 2558 sc->bce_flash_size = sc->bce_flash_info->total_size; 2559 2560 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2561 __FUNCTION__, sc->bce_flash_info->name, 2562 sc->bce_flash_info->total_size); 2563 2564 DBEXIT(BCE_VERBOSE_NVRAM); 2565 return rc; 2566 } 2567 2568 2569 /****************************************************************************/ 2570 /* Read an arbitrary range of data from NVRAM. */ 2571 /* */ 2572 /* Prepares the NVRAM interface for access and reads the requested data */ 2573 /* into the supplied buffer. */ 2574 /* */ 2575 /* Returns: */ 2576 /* 0 on success and the data read, positive value on failure. */ 2577 /****************************************************************************/ 2578 static int 2579 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2580 int buf_size) 2581 { 2582 int rc = 0; 2583 u32 cmd_flags, offset32, len32, extra; 2584 2585 DBENTER(BCE_VERBOSE_NVRAM); 2586 2587 if (buf_size == 0) 2588 goto bce_nvram_read_exit; 2589 2590 /* Request access to the flash interface. */ 2591 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2592 goto bce_nvram_read_exit; 2593 2594 /* Enable access to flash interface */ 2595 bce_enable_nvram_access(sc); 2596 2597 len32 = buf_size; 2598 offset32 = offset; 2599 extra = 0; 2600 2601 cmd_flags = 0; 2602 2603 if (offset32 & 3) { 2604 u8 buf[4]; 2605 u32 pre_len; 2606 2607 offset32 &= ~3; 2608 pre_len = 4 - (offset & 3); 2609 2610 if (pre_len >= len32) { 2611 pre_len = len32; 2612 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2613 } 2614 else { 2615 cmd_flags = BCE_NVM_COMMAND_FIRST; 2616 } 2617 2618 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2619 2620 if (rc) 2621 return rc; 2622 2623 memcpy(ret_buf, buf + (offset & 3), pre_len); 2624 2625 offset32 += 4; 2626 ret_buf += pre_len; 2627 len32 -= pre_len; 2628 } 2629 2630 if (len32 & 3) { 2631 extra = 4 - (len32 & 3); 2632 len32 = (len32 + 4) & ~3; 2633 } 2634 2635 if (len32 == 4) { 2636 u8 buf[4]; 2637 2638 if (cmd_flags) 2639 cmd_flags = BCE_NVM_COMMAND_LAST; 2640 else 2641 cmd_flags = BCE_NVM_COMMAND_FIRST | 2642 BCE_NVM_COMMAND_LAST; 2643 2644 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2645 2646 memcpy(ret_buf, buf, 4 - extra); 2647 } 2648 else if (len32 > 0) { 2649 u8 buf[4]; 2650 2651 /* Read the first word. */ 2652 if (cmd_flags) 2653 cmd_flags = 0; 2654 else 2655 cmd_flags = BCE_NVM_COMMAND_FIRST; 2656 2657 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2658 2659 /* Advance to the next dword. */ 2660 offset32 += 4; 2661 ret_buf += 4; 2662 len32 -= 4; 2663 2664 while (len32 > 4 && rc == 0) { 2665 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2666 2667 /* Advance to the next dword. */ 2668 offset32 += 4; 2669 ret_buf += 4; 2670 len32 -= 4; 2671 } 2672 2673 if (rc) 2674 goto bce_nvram_read_locked_exit; 2675 2676 cmd_flags = BCE_NVM_COMMAND_LAST; 2677 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2678 2679 memcpy(ret_buf, buf, 4 - extra); 2680 } 2681 2682 bce_nvram_read_locked_exit: 2683 /* Disable access to flash interface and release the lock. */ 2684 bce_disable_nvram_access(sc); 2685 bce_release_nvram_lock(sc); 2686 2687 bce_nvram_read_exit: 2688 DBEXIT(BCE_VERBOSE_NVRAM); 2689 return rc; 2690 } 2691 2692 2693 #ifdef BCE_NVRAM_WRITE_SUPPORT 2694 /****************************************************************************/ 2695 /* Write an arbitrary range of data from NVRAM. */ 2696 /* */ 2697 /* Prepares the NVRAM interface for write access and writes the requested */ 2698 /* data from the supplied buffer. The caller is responsible for */ 2699 /* calculating any appropriate CRCs. */ 2700 /* */ 2701 /* Returns: */ 2702 /* 0 on success, positive value on failure. */ 2703 /****************************************************************************/ 2704 static int 2705 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2706 int buf_size) 2707 { 2708 u32 written, offset32, len32; 2709 u8 *buf, start[4], end[4]; 2710 int rc = 0; 2711 int align_start, align_end; 2712 2713 DBENTER(BCE_VERBOSE_NVRAM); 2714 2715 buf = data_buf; 2716 offset32 = offset; 2717 len32 = buf_size; 2718 align_start = align_end = 0; 2719 2720 if ((align_start = (offset32 & 3))) { 2721 offset32 &= ~3; 2722 len32 += align_start; 2723 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2724 goto bce_nvram_write_exit; 2725 } 2726 2727 if (len32 & 3) { 2728 if ((len32 > 4) || !align_start) { 2729 align_end = 4 - (len32 & 3); 2730 len32 += align_end; 2731 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2732 end, 4))) { 2733 goto bce_nvram_write_exit; 2734 } 2735 } 2736 } 2737 2738 if (align_start || align_end) { 2739 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2740 if (buf == 0) { 2741 rc = ENOMEM; 2742 goto bce_nvram_write_exit; 2743 } 2744 2745 if (align_start) { 2746 memcpy(buf, start, 4); 2747 } 2748 2749 if (align_end) { 2750 memcpy(buf + len32 - 4, end, 4); 2751 } 2752 memcpy(buf + align_start, data_buf, buf_size); 2753 } 2754 2755 written = 0; 2756 while ((written < len32) && (rc == 0)) { 2757 u32 page_start, page_end, data_start, data_end; 2758 u32 addr, cmd_flags; 2759 int i; 2760 u8 flash_buffer[264]; 2761 2762 /* Find the page_start addr */ 2763 page_start = offset32 + written; 2764 page_start -= (page_start % sc->bce_flash_info->page_size); 2765 /* Find the page_end addr */ 2766 page_end = page_start + sc->bce_flash_info->page_size; 2767 /* Find the data_start addr */ 2768 data_start = (written == 0) ? offset32 : page_start; 2769 /* Find the data_end addr */ 2770 data_end = (page_end > offset32 + len32) ? 2771 (offset32 + len32) : page_end; 2772 2773 /* Request access to the flash interface. */ 2774 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2775 goto bce_nvram_write_exit; 2776 2777 /* Enable access to flash interface */ 2778 bce_enable_nvram_access(sc); 2779 2780 cmd_flags = BCE_NVM_COMMAND_FIRST; 2781 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2782 int j; 2783 2784 /* Read the whole page into the buffer 2785 * (non-buffer flash only) */ 2786 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2787 if (j == (sc->bce_flash_info->page_size - 4)) { 2788 cmd_flags |= BCE_NVM_COMMAND_LAST; 2789 } 2790 rc = bce_nvram_read_dword(sc, 2791 page_start + j, 2792 &flash_buffer[j], 2793 cmd_flags); 2794 2795 if (rc) 2796 goto bce_nvram_write_locked_exit; 2797 2798 cmd_flags = 0; 2799 } 2800 } 2801 2802 /* Enable writes to flash interface (unlock write-protect) */ 2803 if ((rc = bce_enable_nvram_write(sc)) != 0) 2804 goto bce_nvram_write_locked_exit; 2805 2806 /* Erase the page */ 2807 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2808 goto bce_nvram_write_locked_exit; 2809 2810 /* Re-enable the write again for the actual write */ 2811 bce_enable_nvram_write(sc); 2812 2813 /* Loop to write back the buffer data from page_start to 2814 * data_start */ 2815 i = 0; 2816 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2817 for (addr = page_start; addr < data_start; 2818 addr += 4, i += 4) { 2819 2820 rc = bce_nvram_write_dword(sc, addr, 2821 &flash_buffer[i], cmd_flags); 2822 2823 if (rc != 0) 2824 goto bce_nvram_write_locked_exit; 2825 2826 cmd_flags = 0; 2827 } 2828 } 2829 2830 /* Loop to write the new data from data_start to data_end */ 2831 for (addr = data_start; addr < data_end; addr += 4, i++) { 2832 if ((addr == page_end - 4) || 2833 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2834 (addr == data_end - 4))) { 2835 2836 cmd_flags |= BCE_NVM_COMMAND_LAST; 2837 } 2838 rc = bce_nvram_write_dword(sc, addr, buf, 2839 cmd_flags); 2840 2841 if (rc != 0) 2842 goto bce_nvram_write_locked_exit; 2843 2844 cmd_flags = 0; 2845 buf += 4; 2846 } 2847 2848 /* Loop to write back the buffer data from data_end 2849 * to page_end */ 2850 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2851 for (addr = data_end; addr < page_end; 2852 addr += 4, i += 4) { 2853 2854 if (addr == page_end-4) { 2855 cmd_flags = BCE_NVM_COMMAND_LAST; 2856 } 2857 rc = bce_nvram_write_dword(sc, addr, 2858 &flash_buffer[i], cmd_flags); 2859 2860 if (rc != 0) 2861 goto bce_nvram_write_locked_exit; 2862 2863 cmd_flags = 0; 2864 } 2865 } 2866 2867 /* Disable writes to flash interface (lock write-protect) */ 2868 bce_disable_nvram_write(sc); 2869 2870 /* Disable access to flash interface */ 2871 bce_disable_nvram_access(sc); 2872 bce_release_nvram_lock(sc); 2873 2874 /* Increment written */ 2875 written += data_end - data_start; 2876 } 2877 2878 goto bce_nvram_write_exit; 2879 2880 bce_nvram_write_locked_exit: 2881 bce_disable_nvram_write(sc); 2882 bce_disable_nvram_access(sc); 2883 bce_release_nvram_lock(sc); 2884 2885 bce_nvram_write_exit: 2886 if (align_start || align_end) 2887 free(buf, M_DEVBUF); 2888 2889 DBEXIT(BCE_VERBOSE_NVRAM); 2890 return (rc); 2891 } 2892 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2893 2894 2895 /****************************************************************************/ 2896 /* Verifies that NVRAM is accessible and contains valid data. */ 2897 /* */ 2898 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2899 /* correct. */ 2900 /* */ 2901 /* Returns: */ 2902 /* 0 on success, positive value on failure. */ 2903 /****************************************************************************/ 2904 static int 2905 bce_nvram_test(struct bce_softc *sc) 2906 { 2907 u32 buf[BCE_NVRAM_SIZE / 4]; 2908 u8 *data = (u8 *) buf; 2909 int rc = 0; 2910 u32 magic, csum; 2911 2912 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2913 2914 /* 2915 * Check that the device NVRAM is valid by reading 2916 * the magic value at offset 0. 2917 */ 2918 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2919 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2920 __FILE__, __LINE__); 2921 goto bce_nvram_test_exit; 2922 } 2923 2924 /* 2925 * Verify that offset 0 of the NVRAM contains 2926 * a valid magic number. 2927 */ 2928 magic = bce_be32toh(buf[0]); 2929 if (magic != BCE_NVRAM_MAGIC) { 2930 rc = ENODEV; 2931 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2932 "Expected: 0x%08X, Found: 0x%08X\n", 2933 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2934 goto bce_nvram_test_exit; 2935 } 2936 2937 /* 2938 * Verify that the device NVRAM includes valid 2939 * configuration data. 2940 */ 2941 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2942 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2943 "Information from NVRAM!\n", __FILE__, __LINE__); 2944 goto bce_nvram_test_exit; 2945 } 2946 2947 csum = ether_crc32_le(data, 0x100); 2948 if (csum != BCE_CRC32_RESIDUAL) { 2949 rc = ENODEV; 2950 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2951 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2952 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2953 goto bce_nvram_test_exit; 2954 } 2955 2956 csum = ether_crc32_le(data + 0x100, 0x100); 2957 if (csum != BCE_CRC32_RESIDUAL) { 2958 rc = ENODEV; 2959 BCE_PRINTF("%s(%d): Invalid feature configuration " 2960 "information NVRAM CRC! Expected: 0x%08X, " 2961 "Found: 08%08X\n", __FILE__, __LINE__, 2962 BCE_CRC32_RESIDUAL, csum); 2963 } 2964 2965 bce_nvram_test_exit: 2966 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2967 return rc; 2968 } 2969 2970 2971 /****************************************************************************/ 2972 /* Calculates the size of the buffers to allocate based on the MTU. */ 2973 /* */ 2974 /* Returns: */ 2975 /* Nothing. */ 2976 /****************************************************************************/ 2977 static void 2978 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 2979 { 2980 DBENTER(BCE_VERBOSE_LOAD); 2981 2982 /* Use a single allocation type when header splitting enabled. */ 2983 if (bce_hdr_split == TRUE) { 2984 sc->rx_bd_mbuf_alloc_size = MHLEN; 2985 /* Make sure offset is 16 byte aligned for hardware. */ 2986 sc->rx_bd_mbuf_align_pad = 2987 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 2988 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 2989 sc->rx_bd_mbuf_align_pad; 2990 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 2991 } else { 2992 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2993 ETHER_CRC_LEN) > MCLBYTES) { 2994 /* Setup for jumbo RX buffer allocations. */ 2995 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 2996 sc->rx_bd_mbuf_align_pad = 2997 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 2998 sc->rx_bd_mbuf_data_len = 2999 sc->rx_bd_mbuf_alloc_size - 3000 sc->rx_bd_mbuf_align_pad; 3001 } else { 3002 /* Setup for standard RX buffer allocations. */ 3003 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3004 sc->rx_bd_mbuf_align_pad = 3005 roundup2(MCLBYTES, 16) - MCLBYTES; 3006 sc->rx_bd_mbuf_data_len = 3007 sc->rx_bd_mbuf_alloc_size - 3008 sc->rx_bd_mbuf_align_pad; 3009 } 3010 } 3011 3012 // DBPRINT(sc, BCE_INFO_LOAD, 3013 DBPRINT(sc, BCE_WARN, 3014 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3015 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3016 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3017 sc->rx_bd_mbuf_align_pad); 3018 3019 DBEXIT(BCE_VERBOSE_LOAD); 3020 3021 } 3022 3023 /****************************************************************************/ 3024 /* Identifies the current media type of the controller and sets the PHY */ 3025 /* address. */ 3026 /* */ 3027 /* Returns: */ 3028 /* Nothing. */ 3029 /****************************************************************************/ 3030 static void 3031 bce_get_media(struct bce_softc *sc) 3032 { 3033 u32 val; 3034 3035 DBENTER(BCE_VERBOSE_PHY); 3036 3037 /* Assume PHY address for copper controllers. */ 3038 sc->bce_phy_addr = 1; 3039 3040 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3041 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3042 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3043 u32 strap; 3044 3045 /* 3046 * The BCM5709S is software configurable 3047 * for Copper or SerDes operation. 3048 */ 3049 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3050 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3051 "for copper.\n"); 3052 goto bce_get_media_exit; 3053 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3054 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3055 "for dual media.\n"); 3056 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3057 goto bce_get_media_exit; 3058 } 3059 3060 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3061 strap = (val & 3062 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3063 else 3064 strap = (val & 3065 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3066 3067 if (pci_get_function(sc->bce_dev) == 0) { 3068 switch (strap) { 3069 case 0x4: 3070 case 0x5: 3071 case 0x6: 3072 DBPRINT(sc, BCE_INFO_LOAD, 3073 "BCM5709 s/w configured for SerDes.\n"); 3074 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3075 break; 3076 default: 3077 DBPRINT(sc, BCE_INFO_LOAD, 3078 "BCM5709 s/w configured for Copper.\n"); 3079 break; 3080 } 3081 } else { 3082 switch (strap) { 3083 case 0x1: 3084 case 0x2: 3085 case 0x4: 3086 DBPRINT(sc, BCE_INFO_LOAD, 3087 "BCM5709 s/w configured for SerDes.\n"); 3088 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3089 break; 3090 default: 3091 DBPRINT(sc, BCE_INFO_LOAD, 3092 "BCM5709 s/w configured for Copper.\n"); 3093 break; 3094 } 3095 } 3096 3097 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3098 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3099 3100 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3101 3102 sc->bce_flags |= BCE_NO_WOL_FLAG; 3103 3104 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3105 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3106 3107 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3108 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3109 sc->bce_phy_addr = 2; 3110 3111 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3112 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3113 sc->bce_phy_flags |= 3114 BCE_PHY_2_5G_CAPABLE_FLAG; 3115 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3116 "capable adapter\n"); 3117 } 3118 } 3119 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3120 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3121 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3122 3123 bce_get_media_exit: 3124 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3125 "Using PHY address %d.\n", sc->bce_phy_addr); 3126 3127 DBEXIT(BCE_VERBOSE_PHY); 3128 } 3129 3130 3131 /****************************************************************************/ 3132 /* Performs PHY initialization required before MII drivers access the */ 3133 /* device. */ 3134 /* */ 3135 /* Returns: */ 3136 /* Nothing. */ 3137 /****************************************************************************/ 3138 static void 3139 bce_init_media(struct bce_softc *sc) 3140 { 3141 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 3142 /* 3143 * Configure 5709S/5716S PHYs to use traditional IEEE 3144 * Clause 22 method. Otherwise we have no way to attach 3145 * the PHY in mii(4) layer. PHY specific configuration 3146 * is done in mii layer. 3147 */ 3148 3149 /* Select auto-negotiation MMD of the PHY. */ 3150 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3151 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3152 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3153 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3154 3155 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3156 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3157 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3158 } 3159 } 3160 3161 3162 /****************************************************************************/ 3163 /* Free any DMA memory owned by the driver. */ 3164 /* */ 3165 /* Scans through each data structre that requires DMA memory and frees */ 3166 /* the memory if allocated. */ 3167 /* */ 3168 /* Returns: */ 3169 /* Nothing. */ 3170 /****************************************************************************/ 3171 static void 3172 bce_dma_free(struct bce_softc *sc) 3173 { 3174 int i; 3175 3176 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3177 3178 /* Free, unmap, and destroy the status block. */ 3179 if (sc->status_block != NULL) { 3180 bus_dmamem_free( 3181 sc->status_tag, 3182 sc->status_block, 3183 sc->status_map); 3184 sc->status_block = NULL; 3185 } 3186 3187 if (sc->status_map != NULL) { 3188 bus_dmamap_unload( 3189 sc->status_tag, 3190 sc->status_map); 3191 bus_dmamap_destroy(sc->status_tag, 3192 sc->status_map); 3193 sc->status_map = NULL; 3194 } 3195 3196 if (sc->status_tag != NULL) { 3197 bus_dma_tag_destroy(sc->status_tag); 3198 sc->status_tag = NULL; 3199 } 3200 3201 3202 /* Free, unmap, and destroy the statistics block. */ 3203 if (sc->stats_block != NULL) { 3204 bus_dmamem_free( 3205 sc->stats_tag, 3206 sc->stats_block, 3207 sc->stats_map); 3208 sc->stats_block = NULL; 3209 } 3210 3211 if (sc->stats_map != NULL) { 3212 bus_dmamap_unload( 3213 sc->stats_tag, 3214 sc->stats_map); 3215 bus_dmamap_destroy(sc->stats_tag, 3216 sc->stats_map); 3217 sc->stats_map = NULL; 3218 } 3219 3220 if (sc->stats_tag != NULL) { 3221 bus_dma_tag_destroy(sc->stats_tag); 3222 sc->stats_tag = NULL; 3223 } 3224 3225 3226 /* Free, unmap and destroy all context memory pages. */ 3227 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3228 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3229 for (i = 0; i < sc->ctx_pages; i++ ) { 3230 if (sc->ctx_block[i] != NULL) { 3231 bus_dmamem_free( 3232 sc->ctx_tag, 3233 sc->ctx_block[i], 3234 sc->ctx_map[i]); 3235 sc->ctx_block[i] = NULL; 3236 } 3237 3238 if (sc->ctx_map[i] != NULL) { 3239 bus_dmamap_unload( 3240 sc->ctx_tag, 3241 sc->ctx_map[i]); 3242 bus_dmamap_destroy( 3243 sc->ctx_tag, 3244 sc->ctx_map[i]); 3245 sc->ctx_map[i] = NULL; 3246 } 3247 } 3248 3249 /* Destroy the context memory tag. */ 3250 if (sc->ctx_tag != NULL) { 3251 bus_dma_tag_destroy(sc->ctx_tag); 3252 sc->ctx_tag = NULL; 3253 } 3254 } 3255 3256 3257 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3258 for (i = 0; i < sc->tx_pages; i++ ) { 3259 if (sc->tx_bd_chain[i] != NULL) { 3260 bus_dmamem_free( 3261 sc->tx_bd_chain_tag, 3262 sc->tx_bd_chain[i], 3263 sc->tx_bd_chain_map[i]); 3264 sc->tx_bd_chain[i] = NULL; 3265 } 3266 3267 if (sc->tx_bd_chain_map[i] != NULL) { 3268 bus_dmamap_unload( 3269 sc->tx_bd_chain_tag, 3270 sc->tx_bd_chain_map[i]); 3271 bus_dmamap_destroy( 3272 sc->tx_bd_chain_tag, 3273 sc->tx_bd_chain_map[i]); 3274 sc->tx_bd_chain_map[i] = NULL; 3275 } 3276 } 3277 3278 /* Destroy the TX buffer descriptor tag. */ 3279 if (sc->tx_bd_chain_tag != NULL) { 3280 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3281 sc->tx_bd_chain_tag = NULL; 3282 } 3283 3284 3285 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3286 for (i = 0; i < sc->rx_pages; i++ ) { 3287 if (sc->rx_bd_chain[i] != NULL) { 3288 bus_dmamem_free( 3289 sc->rx_bd_chain_tag, 3290 sc->rx_bd_chain[i], 3291 sc->rx_bd_chain_map[i]); 3292 sc->rx_bd_chain[i] = NULL; 3293 } 3294 3295 if (sc->rx_bd_chain_map[i] != NULL) { 3296 bus_dmamap_unload( 3297 sc->rx_bd_chain_tag, 3298 sc->rx_bd_chain_map[i]); 3299 bus_dmamap_destroy( 3300 sc->rx_bd_chain_tag, 3301 sc->rx_bd_chain_map[i]); 3302 sc->rx_bd_chain_map[i] = NULL; 3303 } 3304 } 3305 3306 /* Destroy the RX buffer descriptor tag. */ 3307 if (sc->rx_bd_chain_tag != NULL) { 3308 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3309 sc->rx_bd_chain_tag = NULL; 3310 } 3311 3312 3313 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3314 if (bce_hdr_split == TRUE) { 3315 for (i = 0; i < sc->pg_pages; i++ ) { 3316 if (sc->pg_bd_chain[i] != NULL) { 3317 bus_dmamem_free( 3318 sc->pg_bd_chain_tag, 3319 sc->pg_bd_chain[i], 3320 sc->pg_bd_chain_map[i]); 3321 sc->pg_bd_chain[i] = NULL; 3322 } 3323 3324 if (sc->pg_bd_chain_map[i] != NULL) { 3325 bus_dmamap_unload( 3326 sc->pg_bd_chain_tag, 3327 sc->pg_bd_chain_map[i]); 3328 bus_dmamap_destroy( 3329 sc->pg_bd_chain_tag, 3330 sc->pg_bd_chain_map[i]); 3331 sc->pg_bd_chain_map[i] = NULL; 3332 } 3333 } 3334 3335 /* Destroy the page buffer descriptor tag. */ 3336 if (sc->pg_bd_chain_tag != NULL) { 3337 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3338 sc->pg_bd_chain_tag = NULL; 3339 } 3340 } 3341 3342 3343 /* Unload and destroy the TX mbuf maps. */ 3344 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3345 if (sc->tx_mbuf_map[i] != NULL) { 3346 bus_dmamap_unload(sc->tx_mbuf_tag, 3347 sc->tx_mbuf_map[i]); 3348 bus_dmamap_destroy(sc->tx_mbuf_tag, 3349 sc->tx_mbuf_map[i]); 3350 sc->tx_mbuf_map[i] = NULL; 3351 } 3352 } 3353 3354 /* Destroy the TX mbuf tag. */ 3355 if (sc->tx_mbuf_tag != NULL) { 3356 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3357 sc->tx_mbuf_tag = NULL; 3358 } 3359 3360 /* Unload and destroy the RX mbuf maps. */ 3361 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3362 if (sc->rx_mbuf_map[i] != NULL) { 3363 bus_dmamap_unload(sc->rx_mbuf_tag, 3364 sc->rx_mbuf_map[i]); 3365 bus_dmamap_destroy(sc->rx_mbuf_tag, 3366 sc->rx_mbuf_map[i]); 3367 sc->rx_mbuf_map[i] = NULL; 3368 } 3369 } 3370 3371 /* Destroy the RX mbuf tag. */ 3372 if (sc->rx_mbuf_tag != NULL) { 3373 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3374 sc->rx_mbuf_tag = NULL; 3375 } 3376 3377 /* Unload and destroy the page mbuf maps. */ 3378 if (bce_hdr_split == TRUE) { 3379 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3380 if (sc->pg_mbuf_map[i] != NULL) { 3381 bus_dmamap_unload(sc->pg_mbuf_tag, 3382 sc->pg_mbuf_map[i]); 3383 bus_dmamap_destroy(sc->pg_mbuf_tag, 3384 sc->pg_mbuf_map[i]); 3385 sc->pg_mbuf_map[i] = NULL; 3386 } 3387 } 3388 3389 /* Destroy the page mbuf tag. */ 3390 if (sc->pg_mbuf_tag != NULL) { 3391 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3392 sc->pg_mbuf_tag = NULL; 3393 } 3394 } 3395 3396 /* Destroy the parent tag */ 3397 if (sc->parent_tag != NULL) { 3398 bus_dma_tag_destroy(sc->parent_tag); 3399 sc->parent_tag = NULL; 3400 } 3401 3402 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3403 } 3404 3405 3406 /****************************************************************************/ 3407 /* Get DMA memory from the OS. */ 3408 /* */ 3409 /* Validates that the OS has provided DMA buffers in response to a */ 3410 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3411 /* When the callback is used the OS will return 0 for the mapping function */ 3412 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3413 /* failures back to the caller. */ 3414 /* */ 3415 /* Returns: */ 3416 /* Nothing. */ 3417 /****************************************************************************/ 3418 static void 3419 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3420 { 3421 bus_addr_t *busaddr = arg; 3422 3423 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3424 __FUNCTION__, nseg)); 3425 /* Simulate a mapping failure. */ 3426 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3427 error = ENOMEM); 3428 3429 /* ToDo: How to increment debug sim_count variable here? */ 3430 3431 /* Check for an error and signal the caller that an error occurred. */ 3432 if (error) { 3433 *busaddr = 0; 3434 } else { 3435 *busaddr = segs->ds_addr; 3436 } 3437 3438 return; 3439 } 3440 3441 3442 /****************************************************************************/ 3443 /* Allocate any DMA memory needed by the driver. */ 3444 /* */ 3445 /* Allocates DMA memory needed for the various global structures needed by */ 3446 /* hardware. */ 3447 /* */ 3448 /* Memory alignment requirements: */ 3449 /* +-----------------+----------+----------+----------+----------+ */ 3450 /* | | 5706 | 5708 | 5709 | 5716 | */ 3451 /* +-----------------+----------+----------+----------+----------+ */ 3452 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3453 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3454 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3455 /* |PG Buffers | none | none | none | none | */ 3456 /* |TX Buffers | none | none | none | none | */ 3457 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3458 /* |Context Memory | | | | | */ 3459 /* +-----------------+----------+----------+----------+----------+ */ 3460 /* */ 3461 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3462 /* */ 3463 /* Returns: */ 3464 /* 0 for success, positive value for failure. */ 3465 /****************************************************************************/ 3466 static int 3467 bce_dma_alloc(device_t dev) 3468 { 3469 struct bce_softc *sc; 3470 int i, error, rc = 0; 3471 bus_size_t max_size, max_seg_size; 3472 int max_segments; 3473 3474 sc = device_get_softc(dev); 3475 3476 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3477 3478 /* 3479 * Allocate the parent bus DMA tag appropriate for PCI. 3480 */ 3481 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3482 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3483 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3484 &sc->parent_tag)) { 3485 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3486 __FILE__, __LINE__); 3487 rc = ENOMEM; 3488 goto bce_dma_alloc_exit; 3489 } 3490 3491 /* 3492 * Create a DMA tag for the status block, allocate and clear the 3493 * memory, map the memory into DMA space, and fetch the physical 3494 * address of the block. 3495 */ 3496 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3497 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3498 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3499 0, NULL, NULL, &sc->status_tag)) { 3500 BCE_PRINTF("%s(%d): Could not allocate status block " 3501 "DMA tag!\n", __FILE__, __LINE__); 3502 rc = ENOMEM; 3503 goto bce_dma_alloc_exit; 3504 } 3505 3506 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3507 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3508 &sc->status_map)) { 3509 BCE_PRINTF("%s(%d): Could not allocate status block " 3510 "DMA memory!\n", __FILE__, __LINE__); 3511 rc = ENOMEM; 3512 goto bce_dma_alloc_exit; 3513 } 3514 3515 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3516 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3517 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3518 3519 if (error) { 3520 BCE_PRINTF("%s(%d): Could not map status block " 3521 "DMA memory!\n", __FILE__, __LINE__); 3522 rc = ENOMEM; 3523 goto bce_dma_alloc_exit; 3524 } 3525 3526 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3527 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3528 3529 /* 3530 * Create a DMA tag for the statistics block, allocate and clear the 3531 * memory, map the memory into DMA space, and fetch the physical 3532 * address of the block. 3533 */ 3534 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3535 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3536 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3537 0, NULL, NULL, &sc->stats_tag)) { 3538 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3539 "DMA tag!\n", __FILE__, __LINE__); 3540 rc = ENOMEM; 3541 goto bce_dma_alloc_exit; 3542 } 3543 3544 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3545 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3546 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3547 "DMA memory!\n", __FILE__, __LINE__); 3548 rc = ENOMEM; 3549 goto bce_dma_alloc_exit; 3550 } 3551 3552 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3553 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3554 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3555 3556 if(error) { 3557 BCE_PRINTF("%s(%d): Could not map statistics block " 3558 "DMA memory!\n", __FILE__, __LINE__); 3559 rc = ENOMEM; 3560 goto bce_dma_alloc_exit; 3561 } 3562 3563 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3564 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3565 3566 /* BCM5709 uses host memory as cache for context memory. */ 3567 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3568 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3569 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3570 if (sc->ctx_pages == 0) 3571 sc->ctx_pages = 1; 3572 3573 DBRUNIF((sc->ctx_pages > 512), 3574 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3575 __FILE__, __LINE__, sc->ctx_pages)); 3576 3577 /* 3578 * Create a DMA tag for the context pages, 3579 * allocate and clear the memory, map the 3580 * memory into DMA space, and fetch the 3581 * physical address of the block. 3582 */ 3583 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3584 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3585 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3586 0, NULL, NULL, &sc->ctx_tag)) { 3587 BCE_PRINTF("%s(%d): Could not allocate CTX " 3588 "DMA tag!\n", __FILE__, __LINE__); 3589 rc = ENOMEM; 3590 goto bce_dma_alloc_exit; 3591 } 3592 3593 for (i = 0; i < sc->ctx_pages; i++) { 3594 3595 if(bus_dmamem_alloc(sc->ctx_tag, 3596 (void **)&sc->ctx_block[i], 3597 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3598 &sc->ctx_map[i])) { 3599 BCE_PRINTF("%s(%d): Could not allocate CTX " 3600 "DMA memory!\n", __FILE__, __LINE__); 3601 rc = ENOMEM; 3602 goto bce_dma_alloc_exit; 3603 } 3604 3605 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3606 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3607 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3608 3609 if (error) { 3610 BCE_PRINTF("%s(%d): Could not map CTX " 3611 "DMA memory!\n", __FILE__, __LINE__); 3612 rc = ENOMEM; 3613 goto bce_dma_alloc_exit; 3614 } 3615 3616 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3617 "= 0x%jX\n", __FUNCTION__, i, 3618 (uintmax_t) sc->ctx_paddr[i]); 3619 } 3620 } 3621 3622 /* 3623 * Create a DMA tag for the TX buffer descriptor chain, 3624 * allocate and clear the memory, and fetch the 3625 * physical address of the block. 3626 */ 3627 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3628 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3629 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3630 NULL, NULL, &sc->tx_bd_chain_tag)) { 3631 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3632 "chain DMA tag!\n", __FILE__, __LINE__); 3633 rc = ENOMEM; 3634 goto bce_dma_alloc_exit; 3635 } 3636 3637 for (i = 0; i < sc->tx_pages; i++) { 3638 3639 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3640 (void **)&sc->tx_bd_chain[i], 3641 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3642 &sc->tx_bd_chain_map[i])) { 3643 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3644 "chain DMA memory!\n", __FILE__, __LINE__); 3645 rc = ENOMEM; 3646 goto bce_dma_alloc_exit; 3647 } 3648 3649 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3650 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3651 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3652 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3653 3654 if (error) { 3655 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3656 "chain DMA memory!\n", __FILE__, __LINE__); 3657 rc = ENOMEM; 3658 goto bce_dma_alloc_exit; 3659 } 3660 3661 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3662 "0x%jX\n", __FUNCTION__, i, 3663 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3664 } 3665 3666 /* Check the required size before mapping to conserve resources. */ 3667 if (bce_tso_enable) { 3668 max_size = BCE_TSO_MAX_SIZE; 3669 max_segments = BCE_MAX_SEGMENTS; 3670 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3671 } else { 3672 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3673 max_segments = BCE_MAX_SEGMENTS; 3674 max_seg_size = MCLBYTES; 3675 } 3676 3677 /* Create a DMA tag for TX mbufs. */ 3678 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3679 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3680 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3681 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3682 __FILE__, __LINE__); 3683 rc = ENOMEM; 3684 goto bce_dma_alloc_exit; 3685 } 3686 3687 /* Create DMA maps for the TX mbufs clusters. */ 3688 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3689 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3690 &sc->tx_mbuf_map[i])) { 3691 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3692 "map!\n", __FILE__, __LINE__); 3693 rc = ENOMEM; 3694 goto bce_dma_alloc_exit; 3695 } 3696 } 3697 3698 /* 3699 * Create a DMA tag for the RX buffer descriptor chain, 3700 * allocate and clear the memory, and fetch the physical 3701 * address of the blocks. 3702 */ 3703 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3704 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3705 sc->max_bus_addr, NULL, NULL, 3706 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3707 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3708 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3709 "DMA tag!\n", __FILE__, __LINE__); 3710 rc = ENOMEM; 3711 goto bce_dma_alloc_exit; 3712 } 3713 3714 for (i = 0; i < sc->rx_pages; i++) { 3715 3716 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3717 (void **)&sc->rx_bd_chain[i], 3718 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3719 &sc->rx_bd_chain_map[i])) { 3720 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3721 "chain DMA memory!\n", __FILE__, __LINE__); 3722 rc = ENOMEM; 3723 goto bce_dma_alloc_exit; 3724 } 3725 3726 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3727 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3728 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3729 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3730 3731 if (error) { 3732 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3733 "chain DMA memory!\n", __FILE__, __LINE__); 3734 rc = ENOMEM; 3735 goto bce_dma_alloc_exit; 3736 } 3737 3738 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3739 "0x%jX\n", __FUNCTION__, i, 3740 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3741 } 3742 3743 /* 3744 * Create a DMA tag for RX mbufs. 3745 */ 3746 if (bce_hdr_split == TRUE) 3747 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3748 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3749 else 3750 max_size = max_seg_size = MJUM9BYTES; 3751 max_segments = 1; 3752 3753 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3754 "(max size = 0x%jX max segments = %d, max segment " 3755 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, 3756 max_segments, (uintmax_t) max_seg_size); 3757 3758 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3759 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3760 max_size, max_segments, max_seg_size, 0, NULL, NULL, 3761 &sc->rx_mbuf_tag)) { 3762 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3763 __FILE__, __LINE__); 3764 rc = ENOMEM; 3765 goto bce_dma_alloc_exit; 3766 } 3767 3768 /* Create DMA maps for the RX mbuf clusters. */ 3769 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3770 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3771 &sc->rx_mbuf_map[i])) { 3772 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3773 "DMA map!\n", __FILE__, __LINE__); 3774 rc = ENOMEM; 3775 goto bce_dma_alloc_exit; 3776 } 3777 } 3778 3779 if (bce_hdr_split == TRUE) { 3780 /* 3781 * Create a DMA tag for the page buffer descriptor chain, 3782 * allocate and clear the memory, and fetch the physical 3783 * address of the blocks. 3784 */ 3785 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3786 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3787 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3788 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3789 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3790 "chain DMA tag!\n", __FILE__, __LINE__); 3791 rc = ENOMEM; 3792 goto bce_dma_alloc_exit; 3793 } 3794 3795 for (i = 0; i < sc->pg_pages; i++) { 3796 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3797 (void **)&sc->pg_bd_chain[i], 3798 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3799 &sc->pg_bd_chain_map[i])) { 3800 BCE_PRINTF("%s(%d): Could not allocate page " 3801 "descriptor chain DMA memory!\n", 3802 __FILE__, __LINE__); 3803 rc = ENOMEM; 3804 goto bce_dma_alloc_exit; 3805 } 3806 3807 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3808 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3809 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3810 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3811 3812 if (error) { 3813 BCE_PRINTF("%s(%d): Could not map page descriptor " 3814 "chain DMA memory!\n", __FILE__, __LINE__); 3815 rc = ENOMEM; 3816 goto bce_dma_alloc_exit; 3817 } 3818 3819 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3820 "0x%jX\n", __FUNCTION__, i, 3821 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3822 } 3823 3824 /* 3825 * Create a DMA tag for page mbufs. 3826 */ 3827 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3828 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3829 3830 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3831 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3832 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3833 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3834 "DMA tag!\n", __FILE__, __LINE__); 3835 rc = ENOMEM; 3836 goto bce_dma_alloc_exit; 3837 } 3838 3839 /* Create DMA maps for the page mbuf clusters. */ 3840 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3841 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3842 &sc->pg_mbuf_map[i])) { 3843 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3844 "DMA map!\n", __FILE__, __LINE__); 3845 rc = ENOMEM; 3846 goto bce_dma_alloc_exit; 3847 } 3848 } 3849 } 3850 3851 bce_dma_alloc_exit: 3852 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3853 return(rc); 3854 } 3855 3856 3857 /****************************************************************************/ 3858 /* Release all resources used by the driver. */ 3859 /* */ 3860 /* Releases all resources acquired by the driver including interrupts, */ 3861 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3862 /* */ 3863 /* Returns: */ 3864 /* Nothing. */ 3865 /****************************************************************************/ 3866 static void 3867 bce_release_resources(struct bce_softc *sc) 3868 { 3869 device_t dev; 3870 3871 DBENTER(BCE_VERBOSE_RESET); 3872 3873 dev = sc->bce_dev; 3874 3875 bce_dma_free(sc); 3876 3877 if (sc->bce_intrhand != NULL) { 3878 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3879 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3880 } 3881 3882 if (sc->bce_res_irq != NULL) { 3883 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3884 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3885 sc->bce_res_irq); 3886 } 3887 3888 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3889 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3890 pci_release_msi(dev); 3891 } 3892 3893 if (sc->bce_res_mem != NULL) { 3894 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3895 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3896 sc->bce_res_mem); 3897 } 3898 3899 if (sc->bce_ifp != NULL) { 3900 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3901 if_free(sc->bce_ifp); 3902 } 3903 3904 if (mtx_initialized(&sc->bce_mtx)) 3905 BCE_LOCK_DESTROY(sc); 3906 3907 DBEXIT(BCE_VERBOSE_RESET); 3908 } 3909 3910 3911 /****************************************************************************/ 3912 /* Firmware synchronization. */ 3913 /* */ 3914 /* Before performing certain events such as a chip reset, synchronize with */ 3915 /* the firmware first. */ 3916 /* */ 3917 /* Returns: */ 3918 /* 0 for success, positive value for failure. */ 3919 /****************************************************************************/ 3920 static int 3921 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3922 { 3923 int i, rc = 0; 3924 u32 val; 3925 3926 DBENTER(BCE_VERBOSE_RESET); 3927 3928 /* Don't waste any time if we've timed out before. */ 3929 if (sc->bce_fw_timed_out == TRUE) { 3930 rc = EBUSY; 3931 goto bce_fw_sync_exit; 3932 } 3933 3934 /* Increment the message sequence number. */ 3935 sc->bce_fw_wr_seq++; 3936 msg_data |= sc->bce_fw_wr_seq; 3937 3938 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3939 "0x%08X\n", msg_data); 3940 3941 /* Send the message to the bootcode driver mailbox. */ 3942 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3943 3944 /* Wait for the bootcode to acknowledge the message. */ 3945 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3946 /* Check for a response in the bootcode firmware mailbox. */ 3947 val = bce_shmem_rd(sc, BCE_FW_MB); 3948 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3949 break; 3950 DELAY(1000); 3951 } 3952 3953 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3954 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3955 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3956 3957 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3958 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3959 3960 msg_data &= ~BCE_DRV_MSG_CODE; 3961 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3962 3963 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3964 3965 sc->bce_fw_timed_out = TRUE; 3966 rc = EBUSY; 3967 } 3968 3969 bce_fw_sync_exit: 3970 DBEXIT(BCE_VERBOSE_RESET); 3971 return (rc); 3972 } 3973 3974 3975 /****************************************************************************/ 3976 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3977 /* */ 3978 /* Returns: */ 3979 /* Nothing. */ 3980 /****************************************************************************/ 3981 static void 3982 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3983 u32 rv2p_code_len, u32 rv2p_proc) 3984 { 3985 int i; 3986 u32 val; 3987 3988 DBENTER(BCE_VERBOSE_RESET); 3989 3990 /* Set the page size used by RV2P. */ 3991 if (rv2p_proc == RV2P_PROC2) { 3992 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3993 } 3994 3995 for (i = 0; i < rv2p_code_len; i += 8) { 3996 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3997 rv2p_code++; 3998 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3999 rv2p_code++; 4000 4001 if (rv2p_proc == RV2P_PROC1) { 4002 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4003 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4004 } 4005 else { 4006 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4007 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4008 } 4009 } 4010 4011 /* Reset the processor, un-stall is done later. */ 4012 if (rv2p_proc == RV2P_PROC1) { 4013 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4014 } 4015 else { 4016 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4017 } 4018 4019 DBEXIT(BCE_VERBOSE_RESET); 4020 } 4021 4022 4023 /****************************************************************************/ 4024 /* Load RISC processor firmware. */ 4025 /* */ 4026 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4027 /* associated with a particular processor. */ 4028 /* */ 4029 /* Returns: */ 4030 /* Nothing. */ 4031 /****************************************************************************/ 4032 static void 4033 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4034 struct fw_info *fw) 4035 { 4036 u32 offset; 4037 4038 DBENTER(BCE_VERBOSE_RESET); 4039 4040 bce_halt_cpu(sc, cpu_reg); 4041 4042 /* Load the Text area. */ 4043 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4044 if (fw->text) { 4045 int j; 4046 4047 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4048 REG_WR_IND(sc, offset, fw->text[j]); 4049 } 4050 } 4051 4052 /* Load the Data area. */ 4053 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4054 if (fw->data) { 4055 int j; 4056 4057 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4058 REG_WR_IND(sc, offset, fw->data[j]); 4059 } 4060 } 4061 4062 /* Load the SBSS area. */ 4063 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4064 if (fw->sbss) { 4065 int j; 4066 4067 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4068 REG_WR_IND(sc, offset, fw->sbss[j]); 4069 } 4070 } 4071 4072 /* Load the BSS area. */ 4073 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4074 if (fw->bss) { 4075 int j; 4076 4077 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4078 REG_WR_IND(sc, offset, fw->bss[j]); 4079 } 4080 } 4081 4082 /* Load the Read-Only area. */ 4083 offset = cpu_reg->spad_base + 4084 (fw->rodata_addr - cpu_reg->mips_view_base); 4085 if (fw->rodata) { 4086 int j; 4087 4088 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4089 REG_WR_IND(sc, offset, fw->rodata[j]); 4090 } 4091 } 4092 4093 /* Clear the pre-fetch instruction and set the FW start address. */ 4094 REG_WR_IND(sc, cpu_reg->inst, 0); 4095 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4096 4097 DBEXIT(BCE_VERBOSE_RESET); 4098 } 4099 4100 4101 /****************************************************************************/ 4102 /* Starts the RISC processor. */ 4103 /* */ 4104 /* Assumes the CPU starting address has already been set. */ 4105 /* */ 4106 /* Returns: */ 4107 /* Nothing. */ 4108 /****************************************************************************/ 4109 static void 4110 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4111 { 4112 u32 val; 4113 4114 DBENTER(BCE_VERBOSE_RESET); 4115 4116 /* Start the CPU. */ 4117 val = REG_RD_IND(sc, cpu_reg->mode); 4118 val &= ~cpu_reg->mode_value_halt; 4119 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4120 REG_WR_IND(sc, cpu_reg->mode, val); 4121 4122 DBEXIT(BCE_VERBOSE_RESET); 4123 } 4124 4125 4126 /****************************************************************************/ 4127 /* Halts the RISC processor. */ 4128 /* */ 4129 /* Returns: */ 4130 /* Nothing. */ 4131 /****************************************************************************/ 4132 static void 4133 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4134 { 4135 u32 val; 4136 4137 DBENTER(BCE_VERBOSE_RESET); 4138 4139 /* Halt the CPU. */ 4140 val = REG_RD_IND(sc, cpu_reg->mode); 4141 val |= cpu_reg->mode_value_halt; 4142 REG_WR_IND(sc, cpu_reg->mode, val); 4143 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4144 4145 DBEXIT(BCE_VERBOSE_RESET); 4146 } 4147 4148 4149 /****************************************************************************/ 4150 /* Initialize the RX CPU. */ 4151 /* */ 4152 /* Returns: */ 4153 /* Nothing. */ 4154 /****************************************************************************/ 4155 static void 4156 bce_start_rxp_cpu(struct bce_softc *sc) 4157 { 4158 struct cpu_reg cpu_reg; 4159 4160 DBENTER(BCE_VERBOSE_RESET); 4161 4162 cpu_reg.mode = BCE_RXP_CPU_MODE; 4163 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4164 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4165 cpu_reg.state = BCE_RXP_CPU_STATE; 4166 cpu_reg.state_value_clear = 0xffffff; 4167 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4168 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4169 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4170 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4171 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4172 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4173 cpu_reg.mips_view_base = 0x8000000; 4174 4175 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4176 bce_start_cpu(sc, &cpu_reg); 4177 4178 DBEXIT(BCE_VERBOSE_RESET); 4179 } 4180 4181 4182 /****************************************************************************/ 4183 /* Initialize the RX CPU. */ 4184 /* */ 4185 /* Returns: */ 4186 /* Nothing. */ 4187 /****************************************************************************/ 4188 static void 4189 bce_init_rxp_cpu(struct bce_softc *sc) 4190 { 4191 struct cpu_reg cpu_reg; 4192 struct fw_info fw; 4193 4194 DBENTER(BCE_VERBOSE_RESET); 4195 4196 cpu_reg.mode = BCE_RXP_CPU_MODE; 4197 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4198 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4199 cpu_reg.state = BCE_RXP_CPU_STATE; 4200 cpu_reg.state_value_clear = 0xffffff; 4201 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4202 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4203 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4204 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4205 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4206 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4207 cpu_reg.mips_view_base = 0x8000000; 4208 4209 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4210 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4211 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4212 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4213 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4214 fw.start_addr = bce_RXP_b09FwStartAddr; 4215 4216 fw.text_addr = bce_RXP_b09FwTextAddr; 4217 fw.text_len = bce_RXP_b09FwTextLen; 4218 fw.text_index = 0; 4219 fw.text = bce_RXP_b09FwText; 4220 4221 fw.data_addr = bce_RXP_b09FwDataAddr; 4222 fw.data_len = bce_RXP_b09FwDataLen; 4223 fw.data_index = 0; 4224 fw.data = bce_RXP_b09FwData; 4225 4226 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4227 fw.sbss_len = bce_RXP_b09FwSbssLen; 4228 fw.sbss_index = 0; 4229 fw.sbss = bce_RXP_b09FwSbss; 4230 4231 fw.bss_addr = bce_RXP_b09FwBssAddr; 4232 fw.bss_len = bce_RXP_b09FwBssLen; 4233 fw.bss_index = 0; 4234 fw.bss = bce_RXP_b09FwBss; 4235 4236 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4237 fw.rodata_len = bce_RXP_b09FwRodataLen; 4238 fw.rodata_index = 0; 4239 fw.rodata = bce_RXP_b09FwRodata; 4240 } else { 4241 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4242 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4243 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4244 fw.start_addr = bce_RXP_b06FwStartAddr; 4245 4246 fw.text_addr = bce_RXP_b06FwTextAddr; 4247 fw.text_len = bce_RXP_b06FwTextLen; 4248 fw.text_index = 0; 4249 fw.text = bce_RXP_b06FwText; 4250 4251 fw.data_addr = bce_RXP_b06FwDataAddr; 4252 fw.data_len = bce_RXP_b06FwDataLen; 4253 fw.data_index = 0; 4254 fw.data = bce_RXP_b06FwData; 4255 4256 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4257 fw.sbss_len = bce_RXP_b06FwSbssLen; 4258 fw.sbss_index = 0; 4259 fw.sbss = bce_RXP_b06FwSbss; 4260 4261 fw.bss_addr = bce_RXP_b06FwBssAddr; 4262 fw.bss_len = bce_RXP_b06FwBssLen; 4263 fw.bss_index = 0; 4264 fw.bss = bce_RXP_b06FwBss; 4265 4266 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4267 fw.rodata_len = bce_RXP_b06FwRodataLen; 4268 fw.rodata_index = 0; 4269 fw.rodata = bce_RXP_b06FwRodata; 4270 } 4271 4272 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4273 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4274 4275 /* Delay RXP start until initialization is complete. */ 4276 4277 DBEXIT(BCE_VERBOSE_RESET); 4278 } 4279 4280 4281 /****************************************************************************/ 4282 /* Initialize the TX CPU. */ 4283 /* */ 4284 /* Returns: */ 4285 /* Nothing. */ 4286 /****************************************************************************/ 4287 static void 4288 bce_init_txp_cpu(struct bce_softc *sc) 4289 { 4290 struct cpu_reg cpu_reg; 4291 struct fw_info fw; 4292 4293 DBENTER(BCE_VERBOSE_RESET); 4294 4295 cpu_reg.mode = BCE_TXP_CPU_MODE; 4296 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4297 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4298 cpu_reg.state = BCE_TXP_CPU_STATE; 4299 cpu_reg.state_value_clear = 0xffffff; 4300 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4301 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4302 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4303 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4304 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4305 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4306 cpu_reg.mips_view_base = 0x8000000; 4307 4308 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4309 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4310 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4311 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4312 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4313 fw.start_addr = bce_TXP_b09FwStartAddr; 4314 4315 fw.text_addr = bce_TXP_b09FwTextAddr; 4316 fw.text_len = bce_TXP_b09FwTextLen; 4317 fw.text_index = 0; 4318 fw.text = bce_TXP_b09FwText; 4319 4320 fw.data_addr = bce_TXP_b09FwDataAddr; 4321 fw.data_len = bce_TXP_b09FwDataLen; 4322 fw.data_index = 0; 4323 fw.data = bce_TXP_b09FwData; 4324 4325 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4326 fw.sbss_len = bce_TXP_b09FwSbssLen; 4327 fw.sbss_index = 0; 4328 fw.sbss = bce_TXP_b09FwSbss; 4329 4330 fw.bss_addr = bce_TXP_b09FwBssAddr; 4331 fw.bss_len = bce_TXP_b09FwBssLen; 4332 fw.bss_index = 0; 4333 fw.bss = bce_TXP_b09FwBss; 4334 4335 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4336 fw.rodata_len = bce_TXP_b09FwRodataLen; 4337 fw.rodata_index = 0; 4338 fw.rodata = bce_TXP_b09FwRodata; 4339 } else { 4340 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4341 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4342 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4343 fw.start_addr = bce_TXP_b06FwStartAddr; 4344 4345 fw.text_addr = bce_TXP_b06FwTextAddr; 4346 fw.text_len = bce_TXP_b06FwTextLen; 4347 fw.text_index = 0; 4348 fw.text = bce_TXP_b06FwText; 4349 4350 fw.data_addr = bce_TXP_b06FwDataAddr; 4351 fw.data_len = bce_TXP_b06FwDataLen; 4352 fw.data_index = 0; 4353 fw.data = bce_TXP_b06FwData; 4354 4355 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4356 fw.sbss_len = bce_TXP_b06FwSbssLen; 4357 fw.sbss_index = 0; 4358 fw.sbss = bce_TXP_b06FwSbss; 4359 4360 fw.bss_addr = bce_TXP_b06FwBssAddr; 4361 fw.bss_len = bce_TXP_b06FwBssLen; 4362 fw.bss_index = 0; 4363 fw.bss = bce_TXP_b06FwBss; 4364 4365 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4366 fw.rodata_len = bce_TXP_b06FwRodataLen; 4367 fw.rodata_index = 0; 4368 fw.rodata = bce_TXP_b06FwRodata; 4369 } 4370 4371 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4372 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4373 bce_start_cpu(sc, &cpu_reg); 4374 4375 DBEXIT(BCE_VERBOSE_RESET); 4376 } 4377 4378 4379 /****************************************************************************/ 4380 /* Initialize the TPAT CPU. */ 4381 /* */ 4382 /* Returns: */ 4383 /* Nothing. */ 4384 /****************************************************************************/ 4385 static void 4386 bce_init_tpat_cpu(struct bce_softc *sc) 4387 { 4388 struct cpu_reg cpu_reg; 4389 struct fw_info fw; 4390 4391 DBENTER(BCE_VERBOSE_RESET); 4392 4393 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4394 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4395 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4396 cpu_reg.state = BCE_TPAT_CPU_STATE; 4397 cpu_reg.state_value_clear = 0xffffff; 4398 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4399 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4400 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4401 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4402 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4403 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4404 cpu_reg.mips_view_base = 0x8000000; 4405 4406 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4407 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4408 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4409 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4410 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4411 fw.start_addr = bce_TPAT_b09FwStartAddr; 4412 4413 fw.text_addr = bce_TPAT_b09FwTextAddr; 4414 fw.text_len = bce_TPAT_b09FwTextLen; 4415 fw.text_index = 0; 4416 fw.text = bce_TPAT_b09FwText; 4417 4418 fw.data_addr = bce_TPAT_b09FwDataAddr; 4419 fw.data_len = bce_TPAT_b09FwDataLen; 4420 fw.data_index = 0; 4421 fw.data = bce_TPAT_b09FwData; 4422 4423 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4424 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4425 fw.sbss_index = 0; 4426 fw.sbss = bce_TPAT_b09FwSbss; 4427 4428 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4429 fw.bss_len = bce_TPAT_b09FwBssLen; 4430 fw.bss_index = 0; 4431 fw.bss = bce_TPAT_b09FwBss; 4432 4433 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4434 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4435 fw.rodata_index = 0; 4436 fw.rodata = bce_TPAT_b09FwRodata; 4437 } else { 4438 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4439 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4440 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4441 fw.start_addr = bce_TPAT_b06FwStartAddr; 4442 4443 fw.text_addr = bce_TPAT_b06FwTextAddr; 4444 fw.text_len = bce_TPAT_b06FwTextLen; 4445 fw.text_index = 0; 4446 fw.text = bce_TPAT_b06FwText; 4447 4448 fw.data_addr = bce_TPAT_b06FwDataAddr; 4449 fw.data_len = bce_TPAT_b06FwDataLen; 4450 fw.data_index = 0; 4451 fw.data = bce_TPAT_b06FwData; 4452 4453 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4454 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4455 fw.sbss_index = 0; 4456 fw.sbss = bce_TPAT_b06FwSbss; 4457 4458 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4459 fw.bss_len = bce_TPAT_b06FwBssLen; 4460 fw.bss_index = 0; 4461 fw.bss = bce_TPAT_b06FwBss; 4462 4463 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4464 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4465 fw.rodata_index = 0; 4466 fw.rodata = bce_TPAT_b06FwRodata; 4467 } 4468 4469 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4470 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4471 bce_start_cpu(sc, &cpu_reg); 4472 4473 DBEXIT(BCE_VERBOSE_RESET); 4474 } 4475 4476 4477 /****************************************************************************/ 4478 /* Initialize the CP CPU. */ 4479 /* */ 4480 /* Returns: */ 4481 /* Nothing. */ 4482 /****************************************************************************/ 4483 static void 4484 bce_init_cp_cpu(struct bce_softc *sc) 4485 { 4486 struct cpu_reg cpu_reg; 4487 struct fw_info fw; 4488 4489 DBENTER(BCE_VERBOSE_RESET); 4490 4491 cpu_reg.mode = BCE_CP_CPU_MODE; 4492 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4493 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4494 cpu_reg.state = BCE_CP_CPU_STATE; 4495 cpu_reg.state_value_clear = 0xffffff; 4496 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4497 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4498 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4499 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4500 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4501 cpu_reg.spad_base = BCE_CP_SCRATCH; 4502 cpu_reg.mips_view_base = 0x8000000; 4503 4504 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4505 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4506 fw.ver_major = bce_CP_b09FwReleaseMajor; 4507 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4508 fw.ver_fix = bce_CP_b09FwReleaseFix; 4509 fw.start_addr = bce_CP_b09FwStartAddr; 4510 4511 fw.text_addr = bce_CP_b09FwTextAddr; 4512 fw.text_len = bce_CP_b09FwTextLen; 4513 fw.text_index = 0; 4514 fw.text = bce_CP_b09FwText; 4515 4516 fw.data_addr = bce_CP_b09FwDataAddr; 4517 fw.data_len = bce_CP_b09FwDataLen; 4518 fw.data_index = 0; 4519 fw.data = bce_CP_b09FwData; 4520 4521 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4522 fw.sbss_len = bce_CP_b09FwSbssLen; 4523 fw.sbss_index = 0; 4524 fw.sbss = bce_CP_b09FwSbss; 4525 4526 fw.bss_addr = bce_CP_b09FwBssAddr; 4527 fw.bss_len = bce_CP_b09FwBssLen; 4528 fw.bss_index = 0; 4529 fw.bss = bce_CP_b09FwBss; 4530 4531 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4532 fw.rodata_len = bce_CP_b09FwRodataLen; 4533 fw.rodata_index = 0; 4534 fw.rodata = bce_CP_b09FwRodata; 4535 } else { 4536 fw.ver_major = bce_CP_b06FwReleaseMajor; 4537 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4538 fw.ver_fix = bce_CP_b06FwReleaseFix; 4539 fw.start_addr = bce_CP_b06FwStartAddr; 4540 4541 fw.text_addr = bce_CP_b06FwTextAddr; 4542 fw.text_len = bce_CP_b06FwTextLen; 4543 fw.text_index = 0; 4544 fw.text = bce_CP_b06FwText; 4545 4546 fw.data_addr = bce_CP_b06FwDataAddr; 4547 fw.data_len = bce_CP_b06FwDataLen; 4548 fw.data_index = 0; 4549 fw.data = bce_CP_b06FwData; 4550 4551 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4552 fw.sbss_len = bce_CP_b06FwSbssLen; 4553 fw.sbss_index = 0; 4554 fw.sbss = bce_CP_b06FwSbss; 4555 4556 fw.bss_addr = bce_CP_b06FwBssAddr; 4557 fw.bss_len = bce_CP_b06FwBssLen; 4558 fw.bss_index = 0; 4559 fw.bss = bce_CP_b06FwBss; 4560 4561 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4562 fw.rodata_len = bce_CP_b06FwRodataLen; 4563 fw.rodata_index = 0; 4564 fw.rodata = bce_CP_b06FwRodata; 4565 } 4566 4567 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4568 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4569 bce_start_cpu(sc, &cpu_reg); 4570 4571 DBEXIT(BCE_VERBOSE_RESET); 4572 } 4573 4574 4575 /****************************************************************************/ 4576 /* Initialize the COM CPU. */ 4577 /* */ 4578 /* Returns: */ 4579 /* Nothing. */ 4580 /****************************************************************************/ 4581 static void 4582 bce_init_com_cpu(struct bce_softc *sc) 4583 { 4584 struct cpu_reg cpu_reg; 4585 struct fw_info fw; 4586 4587 DBENTER(BCE_VERBOSE_RESET); 4588 4589 cpu_reg.mode = BCE_COM_CPU_MODE; 4590 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4591 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4592 cpu_reg.state = BCE_COM_CPU_STATE; 4593 cpu_reg.state_value_clear = 0xffffff; 4594 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4595 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4596 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4597 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4598 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4599 cpu_reg.spad_base = BCE_COM_SCRATCH; 4600 cpu_reg.mips_view_base = 0x8000000; 4601 4602 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4603 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4604 fw.ver_major = bce_COM_b09FwReleaseMajor; 4605 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4606 fw.ver_fix = bce_COM_b09FwReleaseFix; 4607 fw.start_addr = bce_COM_b09FwStartAddr; 4608 4609 fw.text_addr = bce_COM_b09FwTextAddr; 4610 fw.text_len = bce_COM_b09FwTextLen; 4611 fw.text_index = 0; 4612 fw.text = bce_COM_b09FwText; 4613 4614 fw.data_addr = bce_COM_b09FwDataAddr; 4615 fw.data_len = bce_COM_b09FwDataLen; 4616 fw.data_index = 0; 4617 fw.data = bce_COM_b09FwData; 4618 4619 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4620 fw.sbss_len = bce_COM_b09FwSbssLen; 4621 fw.sbss_index = 0; 4622 fw.sbss = bce_COM_b09FwSbss; 4623 4624 fw.bss_addr = bce_COM_b09FwBssAddr; 4625 fw.bss_len = bce_COM_b09FwBssLen; 4626 fw.bss_index = 0; 4627 fw.bss = bce_COM_b09FwBss; 4628 4629 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4630 fw.rodata_len = bce_COM_b09FwRodataLen; 4631 fw.rodata_index = 0; 4632 fw.rodata = bce_COM_b09FwRodata; 4633 } else { 4634 fw.ver_major = bce_COM_b06FwReleaseMajor; 4635 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4636 fw.ver_fix = bce_COM_b06FwReleaseFix; 4637 fw.start_addr = bce_COM_b06FwStartAddr; 4638 4639 fw.text_addr = bce_COM_b06FwTextAddr; 4640 fw.text_len = bce_COM_b06FwTextLen; 4641 fw.text_index = 0; 4642 fw.text = bce_COM_b06FwText; 4643 4644 fw.data_addr = bce_COM_b06FwDataAddr; 4645 fw.data_len = bce_COM_b06FwDataLen; 4646 fw.data_index = 0; 4647 fw.data = bce_COM_b06FwData; 4648 4649 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4650 fw.sbss_len = bce_COM_b06FwSbssLen; 4651 fw.sbss_index = 0; 4652 fw.sbss = bce_COM_b06FwSbss; 4653 4654 fw.bss_addr = bce_COM_b06FwBssAddr; 4655 fw.bss_len = bce_COM_b06FwBssLen; 4656 fw.bss_index = 0; 4657 fw.bss = bce_COM_b06FwBss; 4658 4659 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4660 fw.rodata_len = bce_COM_b06FwRodataLen; 4661 fw.rodata_index = 0; 4662 fw.rodata = bce_COM_b06FwRodata; 4663 } 4664 4665 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4666 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4667 bce_start_cpu(sc, &cpu_reg); 4668 4669 DBEXIT(BCE_VERBOSE_RESET); 4670 } 4671 4672 4673 /****************************************************************************/ 4674 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4675 /* */ 4676 /* Loads the firmware for each CPU and starts the CPU. */ 4677 /* */ 4678 /* Returns: */ 4679 /* Nothing. */ 4680 /****************************************************************************/ 4681 static void 4682 bce_init_cpus(struct bce_softc *sc) 4683 { 4684 DBENTER(BCE_VERBOSE_RESET); 4685 4686 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4687 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4688 4689 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4690 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4691 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4692 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4693 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4694 } else { 4695 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4696 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4697 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4698 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4699 } 4700 4701 } else { 4702 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4703 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4704 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4705 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4706 } 4707 4708 bce_init_rxp_cpu(sc); 4709 bce_init_txp_cpu(sc); 4710 bce_init_tpat_cpu(sc); 4711 bce_init_com_cpu(sc); 4712 bce_init_cp_cpu(sc); 4713 4714 DBEXIT(BCE_VERBOSE_RESET); 4715 } 4716 4717 4718 /****************************************************************************/ 4719 /* Initialize context memory. */ 4720 /* */ 4721 /* Clears the memory associated with each Context ID (CID). */ 4722 /* */ 4723 /* Returns: */ 4724 /* Nothing. */ 4725 /****************************************************************************/ 4726 static int 4727 bce_init_ctx(struct bce_softc *sc) 4728 { 4729 u32 offset, val, vcid_addr; 4730 int i, j, rc, retry_cnt; 4731 4732 rc = 0; 4733 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4734 4735 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4736 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4737 retry_cnt = CTX_INIT_RETRY_COUNT; 4738 4739 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4740 4741 /* 4742 * BCM5709 context memory may be cached 4743 * in host memory so prepare the host memory 4744 * for access. 4745 */ 4746 val = BCE_CTX_COMMAND_ENABLED | 4747 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4748 val |= (BCM_PAGE_BITS - 8) << 16; 4749 REG_WR(sc, BCE_CTX_COMMAND, val); 4750 4751 /* Wait for mem init command to complete. */ 4752 for (i = 0; i < retry_cnt; i++) { 4753 val = REG_RD(sc, BCE_CTX_COMMAND); 4754 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4755 break; 4756 DELAY(2); 4757 } 4758 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4759 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4760 __FUNCTION__); 4761 rc = EBUSY; 4762 goto init_ctx_fail; 4763 } 4764 4765 for (i = 0; i < sc->ctx_pages; i++) { 4766 /* Set the physical address of the context memory. */ 4767 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4768 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4769 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4770 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4771 BCE_ADDR_HI(sc->ctx_paddr[i])); 4772 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4773 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4774 4775 /* Verify the context memory write was successful. */ 4776 for (j = 0; j < retry_cnt; j++) { 4777 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4778 if ((val & 4779 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4780 break; 4781 DELAY(5); 4782 } 4783 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4784 BCE_PRINTF("%s(): Failed to initialize " 4785 "context page %d!\n", __FUNCTION__, i); 4786 rc = EBUSY; 4787 goto init_ctx_fail; 4788 } 4789 } 4790 } else { 4791 4792 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4793 4794 /* 4795 * For the 5706/5708, context memory is local to 4796 * the controller, so initialize the controller 4797 * context memory. 4798 */ 4799 4800 vcid_addr = GET_CID_ADDR(96); 4801 while (vcid_addr) { 4802 4803 vcid_addr -= PHY_CTX_SIZE; 4804 4805 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4806 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4807 4808 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4809 CTX_WR(sc, 0x00, offset, 0); 4810 } 4811 4812 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4813 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4814 } 4815 4816 } 4817 init_ctx_fail: 4818 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4819 return (rc); 4820 } 4821 4822 4823 /****************************************************************************/ 4824 /* Fetch the permanent MAC address of the controller. */ 4825 /* */ 4826 /* Returns: */ 4827 /* Nothing. */ 4828 /****************************************************************************/ 4829 static void 4830 bce_get_mac_addr(struct bce_softc *sc) 4831 { 4832 u32 mac_lo = 0, mac_hi = 0; 4833 4834 DBENTER(BCE_VERBOSE_RESET); 4835 4836 /* 4837 * The NetXtreme II bootcode populates various NIC 4838 * power-on and runtime configuration items in a 4839 * shared memory area. The factory configured MAC 4840 * address is available from both NVRAM and the 4841 * shared memory area so we'll read the value from 4842 * shared memory for speed. 4843 */ 4844 4845 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4846 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4847 4848 if ((mac_lo == 0) && (mac_hi == 0)) { 4849 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4850 __FILE__, __LINE__); 4851 } else { 4852 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4853 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4854 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4855 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4856 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4857 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4858 } 4859 4860 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4861 "address = %6D\n", sc->eaddr, ":"); 4862 DBEXIT(BCE_VERBOSE_RESET); 4863 } 4864 4865 4866 /****************************************************************************/ 4867 /* Program the MAC address. */ 4868 /* */ 4869 /* Returns: */ 4870 /* Nothing. */ 4871 /****************************************************************************/ 4872 static void 4873 bce_set_mac_addr(struct bce_softc *sc) 4874 { 4875 u32 val; 4876 u8 *mac_addr = sc->eaddr; 4877 4878 /* ToDo: Add support for setting multiple MAC addresses. */ 4879 4880 DBENTER(BCE_VERBOSE_RESET); 4881 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4882 "%6D\n", sc->eaddr, ":"); 4883 4884 val = (mac_addr[0] << 8) | mac_addr[1]; 4885 4886 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4887 4888 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4889 (mac_addr[4] << 8) | mac_addr[5]; 4890 4891 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4892 4893 DBEXIT(BCE_VERBOSE_RESET); 4894 } 4895 4896 4897 /****************************************************************************/ 4898 /* Stop the controller. */ 4899 /* */ 4900 /* Returns: */ 4901 /* Nothing. */ 4902 /****************************************************************************/ 4903 static void 4904 bce_stop(struct bce_softc *sc) 4905 { 4906 struct ifnet *ifp; 4907 4908 DBENTER(BCE_VERBOSE_RESET); 4909 4910 BCE_LOCK_ASSERT(sc); 4911 4912 ifp = sc->bce_ifp; 4913 4914 callout_stop(&sc->bce_tick_callout); 4915 4916 /* Disable the transmit/receive blocks. */ 4917 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4918 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4919 DELAY(20); 4920 4921 bce_disable_intr(sc); 4922 4923 /* Free RX buffers. */ 4924 if (bce_hdr_split == TRUE) { 4925 bce_free_pg_chain(sc); 4926 } 4927 bce_free_rx_chain(sc); 4928 4929 /* Free TX buffers. */ 4930 bce_free_tx_chain(sc); 4931 4932 sc->watchdog_timer = 0; 4933 4934 sc->bce_link_up = FALSE; 4935 4936 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4937 4938 DBEXIT(BCE_VERBOSE_RESET); 4939 } 4940 4941 4942 static int 4943 bce_reset(struct bce_softc *sc, u32 reset_code) 4944 { 4945 u32 val; 4946 int i, rc = 0; 4947 4948 DBENTER(BCE_VERBOSE_RESET); 4949 4950 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4951 __FUNCTION__, reset_code); 4952 4953 /* Wait for pending PCI transactions to complete. */ 4954 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4955 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4956 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4957 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4958 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4959 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4960 DELAY(5); 4961 4962 /* Disable DMA */ 4963 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4964 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4965 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4966 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4967 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4968 } 4969 4970 /* Assume bootcode is running. */ 4971 sc->bce_fw_timed_out = FALSE; 4972 sc->bce_drv_cardiac_arrest = FALSE; 4973 4974 /* Give the firmware a chance to prepare for the reset. */ 4975 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4976 if (rc) 4977 goto bce_reset_exit; 4978 4979 /* Set a firmware reminder that this is a soft reset. */ 4980 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4981 4982 /* Dummy read to force the chip to complete all current transactions. */ 4983 val = REG_RD(sc, BCE_MISC_ID); 4984 4985 /* Chip reset. */ 4986 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4987 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4988 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4989 REG_RD(sc, BCE_MISC_COMMAND); 4990 DELAY(5); 4991 4992 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4993 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4994 4995 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4996 } else { 4997 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4998 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4999 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5000 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 5001 5002 /* Allow up to 30us for reset to complete. */ 5003 for (i = 0; i < 10; i++) { 5004 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5005 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5006 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5007 break; 5008 } 5009 DELAY(10); 5010 } 5011 5012 /* Check that reset completed successfully. */ 5013 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5014 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5015 BCE_PRINTF("%s(%d): Reset failed!\n", 5016 __FILE__, __LINE__); 5017 rc = EBUSY; 5018 goto bce_reset_exit; 5019 } 5020 } 5021 5022 /* Make sure byte swapping is properly configured. */ 5023 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5024 if (val != 0x01020304) { 5025 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5026 __FILE__, __LINE__); 5027 rc = ENODEV; 5028 goto bce_reset_exit; 5029 } 5030 5031 /* Just completed a reset, assume that firmware is running again. */ 5032 sc->bce_fw_timed_out = FALSE; 5033 sc->bce_drv_cardiac_arrest = FALSE; 5034 5035 /* Wait for the firmware to finish its initialization. */ 5036 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5037 if (rc) 5038 BCE_PRINTF("%s(%d): Firmware did not complete " 5039 "initialization!\n", __FILE__, __LINE__); 5040 5041 bce_reset_exit: 5042 DBEXIT(BCE_VERBOSE_RESET); 5043 return (rc); 5044 } 5045 5046 5047 static int 5048 bce_chipinit(struct bce_softc *sc) 5049 { 5050 u32 val; 5051 int rc = 0; 5052 5053 DBENTER(BCE_VERBOSE_RESET); 5054 5055 bce_disable_intr(sc); 5056 5057 /* 5058 * Initialize DMA byte/word swapping, configure the number of DMA 5059 * channels and PCI clock compensation delay. 5060 */ 5061 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5062 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5063 #if BYTE_ORDER == BIG_ENDIAN 5064 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5065 #endif 5066 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5067 DMA_READ_CHANS << 12 | 5068 DMA_WRITE_CHANS << 16; 5069 5070 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5071 5072 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5073 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5074 5075 /* 5076 * This setting resolves a problem observed on certain Intel PCI 5077 * chipsets that cannot handle multiple outstanding DMA operations. 5078 * See errata E9_5706A1_65. 5079 */ 5080 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5081 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5082 !(sc->bce_flags & BCE_PCIX_FLAG)) 5083 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5084 5085 REG_WR(sc, BCE_DMA_CONFIG, val); 5086 5087 /* Enable the RX_V2P and Context state machines before access. */ 5088 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5089 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5090 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5091 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5092 5093 /* Initialize context mapping and zero out the quick contexts. */ 5094 if ((rc = bce_init_ctx(sc)) != 0) 5095 goto bce_chipinit_exit; 5096 5097 /* Initialize the on-boards CPUs */ 5098 bce_init_cpus(sc); 5099 5100 /* Enable management frames (NC-SI) to flow to the MCP. */ 5101 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5102 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5103 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5104 } 5105 5106 /* Prepare NVRAM for access. */ 5107 if ((rc = bce_init_nvram(sc)) != 0) 5108 goto bce_chipinit_exit; 5109 5110 /* Set the kernel bypass block size */ 5111 val = REG_RD(sc, BCE_MQ_CONFIG); 5112 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5113 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5114 5115 /* Enable bins used on the 5709. */ 5116 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5117 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5118 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5119 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5120 val |= BCE_MQ_CONFIG_HALT_DIS; 5121 } 5122 5123 REG_WR(sc, BCE_MQ_CONFIG, val); 5124 5125 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5126 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5127 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5128 5129 /* Set the page size and clear the RV2P processor stall bits. */ 5130 val = (BCM_PAGE_BITS - 8) << 24; 5131 REG_WR(sc, BCE_RV2P_CONFIG, val); 5132 5133 /* Configure page size. */ 5134 val = REG_RD(sc, BCE_TBDR_CONFIG); 5135 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5136 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5137 REG_WR(sc, BCE_TBDR_CONFIG, val); 5138 5139 /* Set the perfect match control register to default. */ 5140 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5141 5142 bce_chipinit_exit: 5143 DBEXIT(BCE_VERBOSE_RESET); 5144 5145 return(rc); 5146 } 5147 5148 5149 /****************************************************************************/ 5150 /* Initialize the controller in preparation to send/receive traffic. */ 5151 /* */ 5152 /* Returns: */ 5153 /* 0 for success, positive value for failure. */ 5154 /****************************************************************************/ 5155 static int 5156 bce_blockinit(struct bce_softc *sc) 5157 { 5158 u32 reg, val; 5159 int rc = 0; 5160 5161 DBENTER(BCE_VERBOSE_RESET); 5162 5163 /* Load the hardware default MAC address. */ 5164 bce_set_mac_addr(sc); 5165 5166 /* Set the Ethernet backoff seed value */ 5167 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5168 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5169 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5170 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5171 5172 sc->last_status_idx = 0; 5173 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5174 5175 /* Set up link change interrupt generation. */ 5176 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5177 5178 /* Program the physical address of the status block. */ 5179 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5180 BCE_ADDR_LO(sc->status_block_paddr)); 5181 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5182 BCE_ADDR_HI(sc->status_block_paddr)); 5183 5184 /* Program the physical address of the statistics block. */ 5185 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5186 BCE_ADDR_LO(sc->stats_block_paddr)); 5187 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5188 BCE_ADDR_HI(sc->stats_block_paddr)); 5189 5190 /* Program various host coalescing parameters. */ 5191 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5192 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 5193 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5194 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 5195 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 5196 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 5197 REG_WR(sc, BCE_HC_TX_TICKS, 5198 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5199 REG_WR(sc, BCE_HC_RX_TICKS, 5200 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5201 REG_WR(sc, BCE_HC_COM_TICKS, 5202 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 5203 REG_WR(sc, BCE_HC_CMD_TICKS, 5204 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 5205 REG_WR(sc, BCE_HC_STATS_TICKS, 5206 (sc->bce_stats_ticks & 0xffff00)); 5207 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5208 5209 /* Configure the Host Coalescing block. */ 5210 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5211 BCE_HC_CONFIG_COLLECT_STATS; 5212 5213 #if 0 5214 /* ToDo: Add MSI-X support. */ 5215 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5216 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5217 BCE_HC_SB_CONFIG_1; 5218 5219 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5220 5221 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5222 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5223 5224 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5225 (sc->tx_quick_cons_trip_int << 16) | 5226 sc->tx_quick_cons_trip); 5227 5228 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5229 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5230 5231 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5232 } 5233 5234 /* 5235 * Tell the HC block to automatically set the 5236 * INT_MASK bit after an MSI/MSI-X interrupt 5237 * is generated so the driver doesn't have to. 5238 */ 5239 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5240 val |= BCE_HC_CONFIG_ONE_SHOT; 5241 5242 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5243 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5244 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5245 #endif 5246 5247 REG_WR(sc, BCE_HC_CONFIG, val); 5248 5249 /* Clear the internal statistics counters. */ 5250 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5251 5252 /* Verify that bootcode is running. */ 5253 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5254 5255 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5256 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5257 __FILE__, __LINE__); 5258 reg = 0); 5259 5260 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5261 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5262 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5263 "Expected: 08%08X\n", __FILE__, __LINE__, 5264 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5265 BCE_DEV_INFO_SIGNATURE_MAGIC); 5266 rc = ENODEV; 5267 goto bce_blockinit_exit; 5268 } 5269 5270 /* Enable DMA */ 5271 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5272 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5273 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5274 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5275 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5276 } 5277 5278 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5279 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5280 BCE_DRV_MSG_CODE_RESET); 5281 5282 /* Enable link state change interrupt generation. */ 5283 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5284 5285 /* Enable the RXP. */ 5286 bce_start_rxp_cpu(sc); 5287 5288 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5289 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5290 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5291 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5292 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5293 } 5294 5295 /* Enable all remaining blocks in the MAC. */ 5296 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5297 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 5298 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5299 BCE_MISC_ENABLE_DEFAULT_XI); 5300 else 5301 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5302 BCE_MISC_ENABLE_DEFAULT); 5303 5304 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5305 DELAY(20); 5306 5307 /* Save the current host coalescing block settings. */ 5308 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5309 5310 bce_blockinit_exit: 5311 DBEXIT(BCE_VERBOSE_RESET); 5312 5313 return (rc); 5314 } 5315 5316 5317 /****************************************************************************/ 5318 /* Encapsulate an mbuf into the rx_bd chain. */ 5319 /* */ 5320 /* Returns: */ 5321 /* 0 for success, positive value for failure. */ 5322 /****************************************************************************/ 5323 static int 5324 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5325 u16 *chain_prod, u32 *prod_bseq) 5326 { 5327 bus_dmamap_t map; 5328 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 5329 struct mbuf *m_new = NULL; 5330 struct rx_bd *rxbd; 5331 int nsegs, error, rc = 0; 5332 #ifdef BCE_DEBUG 5333 u16 debug_chain_prod = *chain_prod; 5334 #endif 5335 5336 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5337 5338 /* Make sure the inputs are valid. */ 5339 DBRUNIF((*chain_prod > MAX_RX_BD_ALLOC), 5340 BCE_PRINTF("%s(%d): RX producer out of range: " 5341 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5342 *chain_prod, (u16) MAX_RX_BD_ALLOC)); 5343 5344 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5345 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5346 *prod, *chain_prod, *prod_bseq); 5347 5348 /* Update some debug statistic counters */ 5349 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5350 sc->rx_low_watermark = sc->free_rx_bd); 5351 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5352 sc->rx_empty_count++); 5353 5354 /* Check whether this is a new mbuf allocation. */ 5355 if (m == NULL) { 5356 5357 /* Simulate an mbuf allocation failure. */ 5358 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5359 sc->mbuf_alloc_failed_count++; 5360 sc->mbuf_alloc_failed_sim_count++; 5361 rc = ENOBUFS; 5362 goto bce_get_rx_buf_exit); 5363 5364 /* This is a new mbuf allocation. */ 5365 if (bce_hdr_split == TRUE) 5366 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5367 else 5368 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 5369 sc->rx_bd_mbuf_alloc_size); 5370 5371 if (m_new == NULL) { 5372 sc->mbuf_alloc_failed_count++; 5373 rc = ENOBUFS; 5374 goto bce_get_rx_buf_exit; 5375 } 5376 5377 DBRUN(sc->debug_rx_mbuf_alloc++); 5378 } else { 5379 /* Reuse an existing mbuf. */ 5380 m_new = m; 5381 } 5382 5383 /* Make sure we have a valid packet header. */ 5384 M_ASSERTPKTHDR(m_new); 5385 5386 /* Initialize the mbuf size and pad if necessary for alignment. */ 5387 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5388 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5389 5390 /* ToDo: Consider calling m_fragment() to test error handling. */ 5391 5392 /* Map the mbuf cluster into device memory. */ 5393 map = sc->rx_mbuf_map[*chain_prod]; 5394 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5395 segs, &nsegs, BUS_DMA_NOWAIT); 5396 5397 /* Handle any mapping errors. */ 5398 if (error) { 5399 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5400 "chain (%d)!\n", __FILE__, __LINE__, error); 5401 5402 sc->dma_map_addr_rx_failed_count++; 5403 m_freem(m_new); 5404 5405 DBRUN(sc->debug_rx_mbuf_alloc--); 5406 5407 rc = ENOBUFS; 5408 goto bce_get_rx_buf_exit; 5409 } 5410 5411 /* All mbufs must map to a single segment. */ 5412 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5413 __FUNCTION__, nsegs)); 5414 5415 /* Setup the rx_bd for the segment. */ 5416 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5417 5418 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5419 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5420 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5421 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5422 *prod_bseq += segs[0].ds_len; 5423 5424 /* Save the mbuf and update our counter. */ 5425 sc->rx_mbuf_ptr[*chain_prod] = m_new; 5426 sc->free_rx_bd -= nsegs; 5427 5428 DBRUNMSG(BCE_INSANE_RECV, 5429 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5430 5431 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5432 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", 5433 __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5434 5435 bce_get_rx_buf_exit: 5436 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5437 5438 return(rc); 5439 } 5440 5441 5442 /****************************************************************************/ 5443 /* Encapsulate an mbuf cluster into the page chain. */ 5444 /* */ 5445 /* Returns: */ 5446 /* 0 for success, positive value for failure. */ 5447 /****************************************************************************/ 5448 static int 5449 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5450 u16 *prod_idx) 5451 { 5452 bus_dmamap_t map; 5453 bus_addr_t busaddr; 5454 struct mbuf *m_new = NULL; 5455 struct rx_bd *pgbd; 5456 int error, rc = 0; 5457 #ifdef BCE_DEBUG 5458 u16 debug_prod_idx = *prod_idx; 5459 #endif 5460 5461 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5462 5463 /* Make sure the inputs are valid. */ 5464 DBRUNIF((*prod_idx > MAX_PG_BD_ALLOC), 5465 BCE_PRINTF("%s(%d): page producer out of range: " 5466 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5467 *prod_idx, (u16) MAX_PG_BD_ALLOC)); 5468 5469 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5470 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5471 5472 /* Update counters if we've hit a new low or run out of pages. */ 5473 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5474 sc->pg_low_watermark = sc->free_pg_bd); 5475 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5476 5477 /* Check whether this is a new mbuf allocation. */ 5478 if (m == NULL) { 5479 5480 /* Simulate an mbuf allocation failure. */ 5481 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5482 sc->mbuf_alloc_failed_count++; 5483 sc->mbuf_alloc_failed_sim_count++; 5484 rc = ENOBUFS; 5485 goto bce_get_pg_buf_exit); 5486 5487 /* This is a new mbuf allocation. */ 5488 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5489 if (m_new == NULL) { 5490 sc->mbuf_alloc_failed_count++; 5491 rc = ENOBUFS; 5492 goto bce_get_pg_buf_exit; 5493 } 5494 5495 DBRUN(sc->debug_pg_mbuf_alloc++); 5496 } else { 5497 /* Reuse an existing mbuf. */ 5498 m_new = m; 5499 m_new->m_data = m_new->m_ext.ext_buf; 5500 } 5501 5502 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5503 5504 /* ToDo: Consider calling m_fragment() to test error handling. */ 5505 5506 /* Map the mbuf cluster into device memory. */ 5507 map = sc->pg_mbuf_map[*prod_idx]; 5508 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5509 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, 5510 &busaddr, BUS_DMA_NOWAIT); 5511 5512 /* Handle any mapping errors. */ 5513 if (error) { 5514 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5515 __FILE__, __LINE__); 5516 5517 m_freem(m_new); 5518 DBRUN(sc->debug_pg_mbuf_alloc--); 5519 5520 rc = ENOBUFS; 5521 goto bce_get_pg_buf_exit; 5522 } 5523 5524 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5525 5526 /* 5527 * The page chain uses the same rx_bd data structure 5528 * as the receive chain but doesn't require a byte sequence (bseq). 5529 */ 5530 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5531 5532 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5533 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5534 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5535 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5536 5537 /* Save the mbuf and update our counter. */ 5538 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5539 sc->free_pg_bd--; 5540 5541 DBRUNMSG(BCE_INSANE_RECV, 5542 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5543 5544 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5545 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5546 5547 bce_get_pg_buf_exit: 5548 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5549 5550 return(rc); 5551 } 5552 5553 5554 /****************************************************************************/ 5555 /* Initialize the TX context memory. */ 5556 /* */ 5557 /* Returns: */ 5558 /* Nothing */ 5559 /****************************************************************************/ 5560 static void 5561 bce_init_tx_context(struct bce_softc *sc) 5562 { 5563 u32 val; 5564 5565 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5566 5567 /* Initialize the context ID for an L2 TX chain. */ 5568 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5569 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5570 /* Set the CID type to support an L2 connection. */ 5571 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5572 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5573 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5574 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5575 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5576 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5577 5578 /* Point the hardware to the first page in the chain. */ 5579 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5580 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5581 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5582 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5583 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5584 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5585 } else { 5586 /* Set the CID type to support an L2 connection. */ 5587 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5588 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5589 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5590 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5591 5592 /* Point the hardware to the first page in the chain. */ 5593 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5594 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5595 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5596 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5597 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5598 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5599 } 5600 5601 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5602 } 5603 5604 5605 /****************************************************************************/ 5606 /* Allocate memory and initialize the TX data structures. */ 5607 /* */ 5608 /* Returns: */ 5609 /* 0 for success, positive value for failure. */ 5610 /****************************************************************************/ 5611 static int 5612 bce_init_tx_chain(struct bce_softc *sc) 5613 { 5614 struct tx_bd *txbd; 5615 int i, rc = 0; 5616 5617 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5618 5619 /* Set the initial TX producer/consumer indices. */ 5620 sc->tx_prod = 0; 5621 sc->tx_cons = 0; 5622 sc->tx_prod_bseq = 0; 5623 sc->used_tx_bd = 0; 5624 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5625 DBRUN(sc->tx_hi_watermark = 0); 5626 DBRUN(sc->tx_full_count = 0); 5627 5628 /* 5629 * The NetXtreme II supports a linked-list structre called 5630 * a Buffer Descriptor Chain (or BD chain). A BD chain 5631 * consists of a series of 1 or more chain pages, each of which 5632 * consists of a fixed number of BD entries. 5633 * The last BD entry on each page is a pointer to the next page 5634 * in the chain, and the last pointer in the BD chain 5635 * points back to the beginning of the chain. 5636 */ 5637 5638 /* Set the TX next pointer chain entries. */ 5639 for (i = 0; i < sc->tx_pages; i++) { 5640 int j; 5641 5642 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5643 5644 /* Check if we've reached the last page. */ 5645 if (i == (sc->tx_pages - 1)) 5646 j = 0; 5647 else 5648 j = i + 1; 5649 5650 txbd->tx_bd_haddr_hi = 5651 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5652 txbd->tx_bd_haddr_lo = 5653 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5654 } 5655 5656 bce_init_tx_context(sc); 5657 5658 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5659 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5660 5661 return(rc); 5662 } 5663 5664 5665 /****************************************************************************/ 5666 /* Free memory and clear the TX data structures. */ 5667 /* */ 5668 /* Returns: */ 5669 /* Nothing. */ 5670 /****************************************************************************/ 5671 static void 5672 bce_free_tx_chain(struct bce_softc *sc) 5673 { 5674 int i; 5675 5676 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5677 5678 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5679 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5680 if (sc->tx_mbuf_ptr[i] != NULL) { 5681 if (sc->tx_mbuf_map[i] != NULL) 5682 bus_dmamap_sync(sc->tx_mbuf_tag, 5683 sc->tx_mbuf_map[i], 5684 BUS_DMASYNC_POSTWRITE); 5685 m_freem(sc->tx_mbuf_ptr[i]); 5686 sc->tx_mbuf_ptr[i] = NULL; 5687 DBRUN(sc->debug_tx_mbuf_alloc--); 5688 } 5689 } 5690 5691 /* Clear each TX chain page. */ 5692 for (i = 0; i < sc->tx_pages; i++) 5693 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5694 5695 sc->used_tx_bd = 0; 5696 5697 /* Check if we lost any mbufs in the process. */ 5698 DBRUNIF((sc->debug_tx_mbuf_alloc), 5699 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5700 "from tx chain!\n", __FILE__, __LINE__, 5701 sc->debug_tx_mbuf_alloc)); 5702 5703 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5704 } 5705 5706 5707 /****************************************************************************/ 5708 /* Initialize the RX context memory. */ 5709 /* */ 5710 /* Returns: */ 5711 /* Nothing */ 5712 /****************************************************************************/ 5713 static void 5714 bce_init_rx_context(struct bce_softc *sc) 5715 { 5716 u32 val; 5717 5718 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5719 5720 /* Init the type, size, and BD cache levels for the RX context. */ 5721 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5722 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5723 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5724 5725 /* 5726 * Set the level for generating pause frames 5727 * when the number of available rx_bd's gets 5728 * too low (the low watermark) and the level 5729 * when pause frames can be stopped (the high 5730 * watermark). 5731 */ 5732 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5733 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5734 u32 lo_water, hi_water; 5735 5736 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5737 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5738 } else { 5739 lo_water = 0; 5740 } 5741 5742 if (lo_water >= USABLE_RX_BD_ALLOC) { 5743 lo_water = 0; 5744 } 5745 5746 hi_water = USABLE_RX_BD_ALLOC / 4; 5747 5748 if (hi_water <= lo_water) { 5749 lo_water = 0; 5750 } 5751 5752 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5753 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5754 5755 if (hi_water > 0xf) 5756 hi_water = 0xf; 5757 else if (hi_water == 0) 5758 lo_water = 0; 5759 5760 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5761 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5762 } 5763 5764 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5765 5766 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5767 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5768 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5769 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5770 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5771 } 5772 5773 /* Point the hardware to the first page in the chain. */ 5774 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5775 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5776 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5777 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5778 5779 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5780 } 5781 5782 5783 /****************************************************************************/ 5784 /* Allocate memory and initialize the RX data structures. */ 5785 /* */ 5786 /* Returns: */ 5787 /* 0 for success, positive value for failure. */ 5788 /****************************************************************************/ 5789 static int 5790 bce_init_rx_chain(struct bce_softc *sc) 5791 { 5792 struct rx_bd *rxbd; 5793 int i, rc = 0; 5794 5795 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5796 BCE_VERBOSE_CTX); 5797 5798 /* Initialize the RX producer and consumer indices. */ 5799 sc->rx_prod = 0; 5800 sc->rx_cons = 0; 5801 sc->rx_prod_bseq = 0; 5802 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5803 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5804 5805 /* Initialize the RX next pointer chain entries. */ 5806 for (i = 0; i < sc->rx_pages; i++) { 5807 int j; 5808 5809 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5810 5811 /* Check if we've reached the last page. */ 5812 if (i == (sc->rx_pages - 1)) 5813 j = 0; 5814 else 5815 j = i + 1; 5816 5817 /* Setup the chain page pointers. */ 5818 rxbd->rx_bd_haddr_hi = 5819 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5820 rxbd->rx_bd_haddr_lo = 5821 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5822 } 5823 5824 /* Fill up the RX chain. */ 5825 bce_fill_rx_chain(sc); 5826 5827 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5828 DBRUN(sc->rx_empty_count = 0); 5829 for (i = 0; i < sc->rx_pages; i++) { 5830 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5831 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5832 } 5833 5834 bce_init_rx_context(sc); 5835 5836 DBRUNMSG(BCE_EXTREME_RECV, 5837 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5838 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5839 BCE_VERBOSE_CTX); 5840 5841 /* ToDo: Are there possible failure modes here? */ 5842 5843 return(rc); 5844 } 5845 5846 5847 /****************************************************************************/ 5848 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5849 /* occurs. */ 5850 /* */ 5851 /* Returns: */ 5852 /* Nothing */ 5853 /****************************************************************************/ 5854 static void 5855 bce_fill_rx_chain(struct bce_softc *sc) 5856 { 5857 u16 prod, prod_idx; 5858 u32 prod_bseq; 5859 5860 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5861 BCE_VERBOSE_CTX); 5862 5863 /* Get the RX chain producer indices. */ 5864 prod = sc->rx_prod; 5865 prod_bseq = sc->rx_prod_bseq; 5866 5867 /* Keep filling the RX chain until it's full. */ 5868 while (sc->free_rx_bd > 0) { 5869 prod_idx = RX_CHAIN_IDX(prod); 5870 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5871 /* Bail out if we can't add an mbuf to the chain. */ 5872 break; 5873 } 5874 prod = NEXT_RX_BD(prod); 5875 } 5876 5877 /* Save the RX chain producer indices. */ 5878 sc->rx_prod = prod; 5879 sc->rx_prod_bseq = prod_bseq; 5880 5881 /* We should never end up pointing to a next page pointer. */ 5882 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5883 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5884 __FUNCTION__, sc->rx_prod)); 5885 5886 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5887 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5888 BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); 5889 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + 5890 BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); 5891 5892 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5893 BCE_VERBOSE_CTX); 5894 } 5895 5896 5897 /****************************************************************************/ 5898 /* Free memory and clear the RX data structures. */ 5899 /* */ 5900 /* Returns: */ 5901 /* Nothing. */ 5902 /****************************************************************************/ 5903 static void 5904 bce_free_rx_chain(struct bce_softc *sc) 5905 { 5906 int i; 5907 5908 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5909 5910 /* Free any mbufs still in the RX mbuf chain. */ 5911 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5912 if (sc->rx_mbuf_ptr[i] != NULL) { 5913 if (sc->rx_mbuf_map[i] != NULL) 5914 bus_dmamap_sync(sc->rx_mbuf_tag, 5915 sc->rx_mbuf_map[i], 5916 BUS_DMASYNC_POSTREAD); 5917 m_freem(sc->rx_mbuf_ptr[i]); 5918 sc->rx_mbuf_ptr[i] = NULL; 5919 DBRUN(sc->debug_rx_mbuf_alloc--); 5920 } 5921 } 5922 5923 /* Clear each RX chain page. */ 5924 for (i = 0; i < sc->rx_pages; i++) 5925 if (sc->rx_bd_chain[i] != NULL) { 5926 bzero((char *)sc->rx_bd_chain[i], 5927 BCE_RX_CHAIN_PAGE_SZ); 5928 } 5929 5930 sc->free_rx_bd = sc->max_rx_bd; 5931 5932 /* Check if we lost any mbufs in the process. */ 5933 DBRUNIF((sc->debug_rx_mbuf_alloc), 5934 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5935 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5936 5937 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5938 } 5939 5940 5941 /****************************************************************************/ 5942 /* Allocate memory and initialize the page data structures. */ 5943 /* Assumes that bce_init_rx_chain() has not already been called. */ 5944 /* */ 5945 /* Returns: */ 5946 /* 0 for success, positive value for failure. */ 5947 /****************************************************************************/ 5948 static int 5949 bce_init_pg_chain(struct bce_softc *sc) 5950 { 5951 struct rx_bd *pgbd; 5952 int i, rc = 0; 5953 u32 val; 5954 5955 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5956 BCE_VERBOSE_CTX); 5957 5958 /* Initialize the page producer and consumer indices. */ 5959 sc->pg_prod = 0; 5960 sc->pg_cons = 0; 5961 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5962 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5963 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5964 DBRUN(sc->pg_empty_count = 0); 5965 5966 /* Initialize the page next pointer chain entries. */ 5967 for (i = 0; i < sc->pg_pages; i++) { 5968 int j; 5969 5970 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5971 5972 /* Check if we've reached the last page. */ 5973 if (i == (sc->pg_pages - 1)) 5974 j = 0; 5975 else 5976 j = i + 1; 5977 5978 /* Setup the chain page pointers. */ 5979 pgbd->rx_bd_haddr_hi = 5980 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5981 pgbd->rx_bd_haddr_lo = 5982 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5983 } 5984 5985 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5986 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5987 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 5988 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5989 5990 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5991 5992 /* Configure the rx_bd and page chain mbuf cluster size. */ 5993 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5994 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5995 5996 /* Configure the context reserved for jumbo support. */ 5997 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5998 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5999 6000 /* Point the hardware to the first page in the page chain. */ 6001 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 6002 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 6003 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 6004 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 6005 6006 /* Fill up the page chain. */ 6007 bce_fill_pg_chain(sc); 6008 6009 for (i = 0; i < sc->pg_pages; i++) { 6010 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6011 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6012 } 6013 6014 DBRUNMSG(BCE_EXTREME_RECV, 6015 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6016 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6017 BCE_VERBOSE_CTX); 6018 return(rc); 6019 } 6020 6021 6022 /****************************************************************************/ 6023 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 6024 /* occurs. */ 6025 /* */ 6026 /* Returns: */ 6027 /* Nothing */ 6028 /****************************************************************************/ 6029 static void 6030 bce_fill_pg_chain(struct bce_softc *sc) 6031 { 6032 u16 prod, prod_idx; 6033 6034 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6035 BCE_VERBOSE_CTX); 6036 6037 /* Get the page chain prodcuer index. */ 6038 prod = sc->pg_prod; 6039 6040 /* Keep filling the page chain until it's full. */ 6041 while (sc->free_pg_bd > 0) { 6042 prod_idx = PG_CHAIN_IDX(prod); 6043 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 6044 /* Bail out if we can't add an mbuf to the chain. */ 6045 break; 6046 } 6047 prod = NEXT_PG_BD(prod); 6048 } 6049 6050 /* Save the page chain producer index. */ 6051 sc->pg_prod = prod; 6052 6053 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6054 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6055 __FUNCTION__, sc->pg_prod)); 6056 6057 /* 6058 * Write the mailbox and tell the chip about 6059 * the new rx_bd's in the page chain. 6060 */ 6061 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 6062 BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); 6063 6064 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6065 BCE_VERBOSE_CTX); 6066 } 6067 6068 6069 /****************************************************************************/ 6070 /* Free memory and clear the RX data structures. */ 6071 /* */ 6072 /* Returns: */ 6073 /* Nothing. */ 6074 /****************************************************************************/ 6075 static void 6076 bce_free_pg_chain(struct bce_softc *sc) 6077 { 6078 int i; 6079 6080 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6081 6082 /* Free any mbufs still in the mbuf page chain. */ 6083 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6084 if (sc->pg_mbuf_ptr[i] != NULL) { 6085 if (sc->pg_mbuf_map[i] != NULL) 6086 bus_dmamap_sync(sc->pg_mbuf_tag, 6087 sc->pg_mbuf_map[i], 6088 BUS_DMASYNC_POSTREAD); 6089 m_freem(sc->pg_mbuf_ptr[i]); 6090 sc->pg_mbuf_ptr[i] = NULL; 6091 DBRUN(sc->debug_pg_mbuf_alloc--); 6092 } 6093 } 6094 6095 /* Clear each page chain pages. */ 6096 for (i = 0; i < sc->pg_pages; i++) 6097 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6098 6099 sc->free_pg_bd = sc->max_pg_bd; 6100 6101 /* Check if we lost any mbufs in the process. */ 6102 DBRUNIF((sc->debug_pg_mbuf_alloc), 6103 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6104 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6105 6106 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6107 } 6108 6109 6110 /****************************************************************************/ 6111 /* Set media options. */ 6112 /* */ 6113 /* Returns: */ 6114 /* 0 for success, positive value for failure. */ 6115 /****************************************************************************/ 6116 static int 6117 bce_ifmedia_upd(struct ifnet *ifp) 6118 { 6119 struct bce_softc *sc = ifp->if_softc; 6120 int error; 6121 6122 DBENTER(BCE_VERBOSE); 6123 6124 BCE_LOCK(sc); 6125 error = bce_ifmedia_upd_locked(ifp); 6126 BCE_UNLOCK(sc); 6127 6128 DBEXIT(BCE_VERBOSE); 6129 return (error); 6130 } 6131 6132 6133 /****************************************************************************/ 6134 /* Set media options. */ 6135 /* */ 6136 /* Returns: */ 6137 /* Nothing. */ 6138 /****************************************************************************/ 6139 static int 6140 bce_ifmedia_upd_locked(struct ifnet *ifp) 6141 { 6142 struct bce_softc *sc = ifp->if_softc; 6143 struct mii_data *mii; 6144 int error; 6145 6146 DBENTER(BCE_VERBOSE_PHY); 6147 6148 error = 0; 6149 BCE_LOCK_ASSERT(sc); 6150 6151 mii = device_get_softc(sc->bce_miibus); 6152 6153 /* Make sure the MII bus has been enumerated. */ 6154 if (mii) { 6155 sc->bce_link_up = FALSE; 6156 if (mii->mii_instance) { 6157 struct mii_softc *miisc; 6158 6159 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6160 mii_phy_reset(miisc); 6161 } 6162 error = mii_mediachg(mii); 6163 } 6164 6165 DBEXIT(BCE_VERBOSE_PHY); 6166 return (error); 6167 } 6168 6169 6170 /****************************************************************************/ 6171 /* Reports current media status. */ 6172 /* */ 6173 /* Returns: */ 6174 /* Nothing. */ 6175 /****************************************************************************/ 6176 static void 6177 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6178 { 6179 struct bce_softc *sc = ifp->if_softc; 6180 struct mii_data *mii; 6181 6182 DBENTER(BCE_VERBOSE_PHY); 6183 6184 BCE_LOCK(sc); 6185 6186 if ((ifp->if_flags & IFF_UP) == 0) { 6187 BCE_UNLOCK(sc); 6188 return; 6189 } 6190 mii = device_get_softc(sc->bce_miibus); 6191 6192 mii_pollstat(mii); 6193 ifmr->ifm_active = mii->mii_media_active; 6194 ifmr->ifm_status = mii->mii_media_status; 6195 6196 BCE_UNLOCK(sc); 6197 6198 DBEXIT(BCE_VERBOSE_PHY); 6199 } 6200 6201 6202 /****************************************************************************/ 6203 /* Handles PHY generated interrupt events. */ 6204 /* */ 6205 /* Returns: */ 6206 /* Nothing. */ 6207 /****************************************************************************/ 6208 static void 6209 bce_phy_intr(struct bce_softc *sc) 6210 { 6211 u32 new_link_state, old_link_state; 6212 6213 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6214 6215 DBRUN(sc->phy_interrupts++); 6216 6217 new_link_state = sc->status_block->status_attn_bits & 6218 STATUS_ATTN_BITS_LINK_STATE; 6219 old_link_state = sc->status_block->status_attn_bits_ack & 6220 STATUS_ATTN_BITS_LINK_STATE; 6221 6222 /* Handle any changes if the link state has changed. */ 6223 if (new_link_state != old_link_state) { 6224 6225 /* Update the status_attn_bits_ack field. */ 6226 if (new_link_state) { 6227 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6228 STATUS_ATTN_BITS_LINK_STATE); 6229 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6230 __FUNCTION__); 6231 } 6232 else { 6233 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6234 STATUS_ATTN_BITS_LINK_STATE); 6235 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6236 __FUNCTION__); 6237 } 6238 6239 /* 6240 * Assume link is down and allow 6241 * tick routine to update the state 6242 * based on the actual media state. 6243 */ 6244 sc->bce_link_up = FALSE; 6245 callout_stop(&sc->bce_tick_callout); 6246 bce_tick(sc); 6247 } 6248 6249 /* Acknowledge the link change interrupt. */ 6250 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6251 6252 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6253 } 6254 6255 6256 /****************************************************************************/ 6257 /* Reads the receive consumer value from the status block (skipping over */ 6258 /* chain page pointer if necessary). */ 6259 /* */ 6260 /* Returns: */ 6261 /* hw_cons */ 6262 /****************************************************************************/ 6263 static inline u16 6264 bce_get_hw_rx_cons(struct bce_softc *sc) 6265 { 6266 u16 hw_cons; 6267 6268 rmb(); 6269 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6270 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6271 hw_cons++; 6272 6273 return hw_cons; 6274 } 6275 6276 /****************************************************************************/ 6277 /* Handles received frame interrupt events. */ 6278 /* */ 6279 /* Returns: */ 6280 /* Nothing. */ 6281 /****************************************************************************/ 6282 static void 6283 bce_rx_intr(struct bce_softc *sc) 6284 { 6285 struct ifnet *ifp = sc->bce_ifp; 6286 struct l2_fhdr *l2fhdr; 6287 struct ether_vlan_header *vh; 6288 unsigned int pkt_len; 6289 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6290 u32 status; 6291 unsigned int rem_len; 6292 u16 sw_pg_cons, sw_pg_cons_idx; 6293 6294 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6295 DBRUN(sc->interrupts_rx++); 6296 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6297 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6298 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6299 6300 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6301 for (int i = 0; i < sc->rx_pages; i++) 6302 bus_dmamap_sync(sc->rx_bd_chain_tag, 6303 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6304 6305 /* Prepare the page chain pages to be accessed by the host CPU. */ 6306 if (bce_hdr_split == TRUE) { 6307 for (int i = 0; i < sc->pg_pages; i++) 6308 bus_dmamap_sync(sc->pg_bd_chain_tag, 6309 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6310 } 6311 6312 /* Get the hardware's view of the RX consumer index. */ 6313 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6314 6315 /* Get working copies of the driver's view of the consumer indices. */ 6316 sw_rx_cons = sc->rx_cons; 6317 sw_pg_cons = sc->pg_cons; 6318 6319 /* Update some debug statistics counters */ 6320 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6321 sc->rx_low_watermark = sc->free_rx_bd); 6322 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6323 sc->rx_empty_count++); 6324 6325 /* Scan through the receive chain as long as there is work to do */ 6326 /* ToDo: Consider setting a limit on the number of packets processed. */ 6327 rmb(); 6328 while (sw_rx_cons != hw_rx_cons) { 6329 struct mbuf *m0; 6330 6331 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6332 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6333 6334 /* Unmap the mbuf from DMA space. */ 6335 bus_dmamap_sync(sc->rx_mbuf_tag, 6336 sc->rx_mbuf_map[sw_rx_cons_idx], 6337 BUS_DMASYNC_POSTREAD); 6338 bus_dmamap_unload(sc->rx_mbuf_tag, 6339 sc->rx_mbuf_map[sw_rx_cons_idx]); 6340 6341 /* Remove the mbuf from the RX chain. */ 6342 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6343 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6344 DBRUN(sc->debug_rx_mbuf_alloc--); 6345 sc->free_rx_bd++; 6346 6347 if(m0 == NULL) { 6348 DBPRINT(sc, BCE_EXTREME_RECV, 6349 "%s(): Oops! Empty mbuf pointer " 6350 "found in sc->rx_mbuf_ptr[0x%04X]!\n", 6351 __FUNCTION__, sw_rx_cons_idx); 6352 goto bce_rx_int_next_rx; 6353 } 6354 6355 /* 6356 * Frames received on the NetXteme II are prepended 6357 * with an l2_fhdr structure which provides status 6358 * information about the received frame (including 6359 * VLAN tags and checksum info). The frames are 6360 * also automatically adjusted to word align the IP 6361 * header (i.e. two null bytes are inserted before 6362 * the Ethernet header). As a result the data 6363 * DMA'd by the controller into the mbuf looks 6364 * like this: 6365 * 6366 * +---------+-----+---------------------+-----+ 6367 * | l2_fhdr | pad | packet data | FCS | 6368 * +---------+-----+---------------------+-----+ 6369 * 6370 * The l2_fhdr needs to be checked and skipped and 6371 * the FCS needs to be stripped before sending the 6372 * packet up the stack. 6373 */ 6374 l2fhdr = mtod(m0, struct l2_fhdr *); 6375 6376 /* Get the packet data + FCS length and the status. */ 6377 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6378 status = l2fhdr->l2_fhdr_status; 6379 6380 /* 6381 * Skip over the l2_fhdr and pad, resulting in the 6382 * following data in the mbuf: 6383 * +---------------------+-----+ 6384 * | packet data | FCS | 6385 * +---------------------+-----+ 6386 */ 6387 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6388 6389 /* 6390 * When split header mode is used, an ethernet frame 6391 * may be split across the receive chain and the 6392 * page chain. If that occurs an mbuf cluster must be 6393 * reassembled from the individual mbuf pieces. 6394 */ 6395 if (bce_hdr_split == TRUE) { 6396 /* 6397 * Check whether the received frame fits in a single 6398 * mbuf or not (i.e. packet data + FCS <= 6399 * sc->rx_bd_mbuf_data_len bytes). 6400 */ 6401 if (pkt_len > m0->m_len) { 6402 /* 6403 * The received frame is larger than a single mbuf. 6404 * If the frame was a TCP frame then only the TCP 6405 * header is placed in the mbuf, the remaining 6406 * payload (including FCS) is placed in the page 6407 * chain, the SPLIT flag is set, and the header 6408 * length is placed in the IP checksum field. 6409 * If the frame is not a TCP frame then the mbuf 6410 * is filled and the remaining bytes are placed 6411 * in the page chain. 6412 */ 6413 6414 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6415 "packet.\n", __FUNCTION__); 6416 DBRUN(sc->split_header_frames_rcvd++); 6417 6418 /* 6419 * When the page chain is enabled and the TCP 6420 * header has been split from the TCP payload, 6421 * the ip_xsum structure will reflect the length 6422 * of the TCP header, not the IP checksum. Set 6423 * the packet length of the mbuf accordingly. 6424 */ 6425 if (status & L2_FHDR_STATUS_SPLIT) { 6426 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6427 DBRUN(sc->split_header_tcp_frames_rcvd++); 6428 } 6429 6430 rem_len = pkt_len - m0->m_len; 6431 6432 /* Pull mbufs off the page chain for any remaining data. */ 6433 while (rem_len > 0) { 6434 struct mbuf *m_pg; 6435 6436 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6437 6438 /* Remove the mbuf from the page chain. */ 6439 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6440 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6441 DBRUN(sc->debug_pg_mbuf_alloc--); 6442 sc->free_pg_bd++; 6443 6444 /* Unmap the page chain mbuf from DMA space. */ 6445 bus_dmamap_sync(sc->pg_mbuf_tag, 6446 sc->pg_mbuf_map[sw_pg_cons_idx], 6447 BUS_DMASYNC_POSTREAD); 6448 bus_dmamap_unload(sc->pg_mbuf_tag, 6449 sc->pg_mbuf_map[sw_pg_cons_idx]); 6450 6451 /* Adjust the mbuf length. */ 6452 if (rem_len < m_pg->m_len) { 6453 /* The mbuf chain is complete. */ 6454 m_pg->m_len = rem_len; 6455 rem_len = 0; 6456 } else { 6457 /* More packet data is waiting. */ 6458 rem_len -= m_pg->m_len; 6459 } 6460 6461 /* Concatenate the mbuf cluster to the mbuf. */ 6462 m_cat(m0, m_pg); 6463 6464 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6465 } 6466 6467 /* Set the total packet length. */ 6468 m0->m_pkthdr.len = pkt_len; 6469 6470 } else { 6471 /* 6472 * The received packet is small and fits in a 6473 * single mbuf (i.e. the l2_fhdr + pad + packet + 6474 * FCS <= MHLEN). In other words, the packet is 6475 * 154 bytes or less in size. 6476 */ 6477 6478 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6479 "packet.\n", __FUNCTION__); 6480 6481 /* Set the total packet length. */ 6482 m0->m_pkthdr.len = m0->m_len = pkt_len; 6483 } 6484 } else 6485 /* Set the total packet length. */ 6486 m0->m_pkthdr.len = m0->m_len = pkt_len; 6487 6488 /* Remove the trailing Ethernet FCS. */ 6489 m_adj(m0, -ETHER_CRC_LEN); 6490 6491 /* Check that the resulting mbuf chain is valid. */ 6492 DBRUN(m_sanity(m0, FALSE)); 6493 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6494 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6495 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6496 m_print(m0, 128)); 6497 6498 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6499 sc->l2fhdr_error_sim_count++; 6500 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6501 6502 /* Check the received frame for errors. */ 6503 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6504 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6505 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6506 6507 /* Log the error and release the mbuf. */ 6508 ifp->if_ierrors++; 6509 sc->l2fhdr_error_count++; 6510 6511 m_freem(m0); 6512 m0 = NULL; 6513 goto bce_rx_int_next_rx; 6514 } 6515 6516 /* Send the packet to the appropriate interface. */ 6517 m0->m_pkthdr.rcvif = ifp; 6518 6519 /* Assume no hardware checksum. */ 6520 m0->m_pkthdr.csum_flags = 0; 6521 6522 /* Validate the checksum if offload enabled. */ 6523 if (ifp->if_capenable & IFCAP_RXCSUM) { 6524 6525 /* Check for an IP datagram. */ 6526 if (!(status & L2_FHDR_STATUS_SPLIT) && 6527 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6528 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6529 DBRUN(sc->csum_offload_ip++); 6530 /* Check if the IP checksum is valid. */ 6531 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6532 m0->m_pkthdr.csum_flags |= 6533 CSUM_IP_VALID; 6534 } 6535 6536 /* Check for a valid TCP/UDP frame. */ 6537 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6538 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6539 6540 /* Check for a good TCP/UDP checksum. */ 6541 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6542 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6543 DBRUN(sc->csum_offload_tcp_udp++); 6544 m0->m_pkthdr.csum_data = 6545 l2fhdr->l2_fhdr_tcp_udp_xsum; 6546 m0->m_pkthdr.csum_flags |= 6547 (CSUM_DATA_VALID 6548 | CSUM_PSEUDO_HDR); 6549 } 6550 } 6551 } 6552 6553 /* Attach the VLAN tag. */ 6554 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6555 DBRUN(sc->vlan_tagged_frames_rcvd++); 6556 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6557 DBRUN(sc->vlan_tagged_frames_stripped++); 6558 #if __FreeBSD_version < 700000 6559 VLAN_INPUT_TAG(ifp, m0, 6560 l2fhdr->l2_fhdr_vlan_tag, continue); 6561 #else 6562 m0->m_pkthdr.ether_vtag = 6563 l2fhdr->l2_fhdr_vlan_tag; 6564 m0->m_flags |= M_VLANTAG; 6565 #endif 6566 } else { 6567 /* 6568 * bce(4) controllers can't disable VLAN 6569 * tag stripping if management firmware 6570 * (ASF/IPMI/UMP) is running. So we always 6571 * strip VLAN tag and manually reconstruct 6572 * the VLAN frame by appending stripped 6573 * VLAN tag in driver if VLAN tag stripping 6574 * was disabled. 6575 * 6576 * TODO: LLC SNAP handling. 6577 */ 6578 bcopy(mtod(m0, uint8_t *), 6579 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6580 ETHER_ADDR_LEN * 2); 6581 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6582 vh = mtod(m0, struct ether_vlan_header *); 6583 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6584 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6585 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6586 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6587 } 6588 } 6589 6590 /* Increment received packet statistics. */ 6591 ifp->if_ipackets++; 6592 6593 bce_rx_int_next_rx: 6594 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6595 6596 /* If we have a packet, pass it up the stack */ 6597 if (m0) { 6598 /* Make sure we don't lose our place when we release the lock. */ 6599 sc->rx_cons = sw_rx_cons; 6600 sc->pg_cons = sw_pg_cons; 6601 6602 BCE_UNLOCK(sc); 6603 (*ifp->if_input)(ifp, m0); 6604 BCE_LOCK(sc); 6605 6606 /* Recover our place. */ 6607 sw_rx_cons = sc->rx_cons; 6608 sw_pg_cons = sc->pg_cons; 6609 } 6610 6611 /* Refresh hw_cons to see if there's new work */ 6612 if (sw_rx_cons == hw_rx_cons) 6613 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6614 } 6615 6616 /* No new packets. Refill the page chain. */ 6617 if (bce_hdr_split == TRUE) { 6618 sc->pg_cons = sw_pg_cons; 6619 bce_fill_pg_chain(sc); 6620 } 6621 6622 /* No new packets. Refill the RX chain. */ 6623 sc->rx_cons = sw_rx_cons; 6624 bce_fill_rx_chain(sc); 6625 6626 /* Prepare the page chain pages to be accessed by the NIC. */ 6627 for (int i = 0; i < sc->rx_pages; i++) 6628 bus_dmamap_sync(sc->rx_bd_chain_tag, 6629 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6630 6631 if (bce_hdr_split == TRUE) { 6632 for (int i = 0; i < sc->pg_pages; i++) 6633 bus_dmamap_sync(sc->pg_bd_chain_tag, 6634 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6635 } 6636 6637 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6638 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6639 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6640 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6641 } 6642 6643 6644 /****************************************************************************/ 6645 /* Reads the transmit consumer value from the status block (skipping over */ 6646 /* chain page pointer if necessary). */ 6647 /* */ 6648 /* Returns: */ 6649 /* hw_cons */ 6650 /****************************************************************************/ 6651 static inline u16 6652 bce_get_hw_tx_cons(struct bce_softc *sc) 6653 { 6654 u16 hw_cons; 6655 6656 mb(); 6657 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6658 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6659 hw_cons++; 6660 6661 return hw_cons; 6662 } 6663 6664 6665 /****************************************************************************/ 6666 /* Handles transmit completion interrupt events. */ 6667 /* */ 6668 /* Returns: */ 6669 /* Nothing. */ 6670 /****************************************************************************/ 6671 static void 6672 bce_tx_intr(struct bce_softc *sc) 6673 { 6674 struct ifnet *ifp = sc->bce_ifp; 6675 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6676 6677 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6678 DBRUN(sc->interrupts_tx++); 6679 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6680 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6681 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6682 6683 BCE_LOCK_ASSERT(sc); 6684 6685 /* Get the hardware's view of the TX consumer index. */ 6686 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6687 sw_tx_cons = sc->tx_cons; 6688 6689 /* Prevent speculative reads of the status block. */ 6690 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6691 BUS_SPACE_BARRIER_READ); 6692 6693 /* Cycle through any completed TX chain page entries. */ 6694 while (sw_tx_cons != hw_tx_cons) { 6695 #ifdef BCE_DEBUG 6696 struct tx_bd *txbd = NULL; 6697 #endif 6698 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6699 6700 DBPRINT(sc, BCE_INFO_SEND, 6701 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6702 "sw_tx_chain_cons = 0x%04X\n", 6703 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6704 6705 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6706 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6707 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6708 (int) MAX_TX_BD_ALLOC); 6709 bce_breakpoint(sc)); 6710 6711 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6712 [TX_IDX(sw_tx_chain_cons)]); 6713 6714 DBRUNIF((txbd == NULL), 6715 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6716 __FILE__, __LINE__, sw_tx_chain_cons); 6717 bce_breakpoint(sc)); 6718 6719 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6720 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6721 6722 /* 6723 * Free the associated mbuf. Remember 6724 * that only the last tx_bd of a packet 6725 * has an mbuf pointer and DMA map. 6726 */ 6727 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6728 6729 /* Validate that this is the last tx_bd. */ 6730 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6731 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6732 "txmbuf == NULL!\n", __FILE__, __LINE__); 6733 bce_breakpoint(sc)); 6734 6735 DBRUNMSG(BCE_INFO_SEND, 6736 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6737 "from tx_bd[0x%04X]\n", __FUNCTION__, 6738 sw_tx_chain_cons)); 6739 6740 /* Unmap the mbuf. */ 6741 bus_dmamap_unload(sc->tx_mbuf_tag, 6742 sc->tx_mbuf_map[sw_tx_chain_cons]); 6743 6744 /* Free the mbuf. */ 6745 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6746 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6747 DBRUN(sc->debug_tx_mbuf_alloc--); 6748 6749 ifp->if_opackets++; 6750 } 6751 6752 sc->used_tx_bd--; 6753 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6754 6755 /* Refresh hw_cons to see if there's new work. */ 6756 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6757 6758 /* Prevent speculative reads of the status block. */ 6759 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6760 BUS_SPACE_BARRIER_READ); 6761 } 6762 6763 /* Clear the TX timeout timer. */ 6764 sc->watchdog_timer = 0; 6765 6766 /* Clear the tx hardware queue full flag. */ 6767 if (sc->used_tx_bd < sc->max_tx_bd) { 6768 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6769 DBPRINT(sc, BCE_INFO_SEND, 6770 "%s(): Open TX chain! %d/%d (used/total)\n", 6771 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6772 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6773 } 6774 6775 sc->tx_cons = sw_tx_cons; 6776 6777 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6778 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6779 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6780 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6781 } 6782 6783 6784 /****************************************************************************/ 6785 /* Disables interrupt generation. */ 6786 /* */ 6787 /* Returns: */ 6788 /* Nothing. */ 6789 /****************************************************************************/ 6790 static void 6791 bce_disable_intr(struct bce_softc *sc) 6792 { 6793 DBENTER(BCE_VERBOSE_INTR); 6794 6795 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6796 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6797 6798 DBEXIT(BCE_VERBOSE_INTR); 6799 } 6800 6801 6802 /****************************************************************************/ 6803 /* Enables interrupt generation. */ 6804 /* */ 6805 /* Returns: */ 6806 /* Nothing. */ 6807 /****************************************************************************/ 6808 static void 6809 bce_enable_intr(struct bce_softc *sc, int coal_now) 6810 { 6811 DBENTER(BCE_VERBOSE_INTR); 6812 6813 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6814 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6815 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6816 6817 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6818 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6819 6820 /* Force an immediate interrupt (whether there is new data or not). */ 6821 if (coal_now) 6822 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6823 6824 DBEXIT(BCE_VERBOSE_INTR); 6825 } 6826 6827 6828 /****************************************************************************/ 6829 /* Handles controller initialization. */ 6830 /* */ 6831 /* Returns: */ 6832 /* Nothing. */ 6833 /****************************************************************************/ 6834 static void 6835 bce_init_locked(struct bce_softc *sc) 6836 { 6837 struct ifnet *ifp; 6838 u32 ether_mtu = 0; 6839 6840 DBENTER(BCE_VERBOSE_RESET); 6841 6842 BCE_LOCK_ASSERT(sc); 6843 6844 ifp = sc->bce_ifp; 6845 6846 /* Check if the driver is still running and bail out if it is. */ 6847 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6848 goto bce_init_locked_exit; 6849 6850 bce_stop(sc); 6851 6852 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6853 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6854 __FILE__, __LINE__); 6855 goto bce_init_locked_exit; 6856 } 6857 6858 if (bce_chipinit(sc)) { 6859 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6860 __FILE__, __LINE__); 6861 goto bce_init_locked_exit; 6862 } 6863 6864 if (bce_blockinit(sc)) { 6865 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6866 __FILE__, __LINE__); 6867 goto bce_init_locked_exit; 6868 } 6869 6870 /* Load our MAC address. */ 6871 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6872 bce_set_mac_addr(sc); 6873 6874 /* 6875 * Calculate and program the hardware Ethernet MTU 6876 * size. Be generous on the receive if we have room 6877 * and allowed by the user. 6878 */ 6879 if (bce_strict_rx_mtu == TRUE) 6880 ether_mtu = ifp->if_mtu; 6881 else { 6882 if (bce_hdr_split == TRUE) { 6883 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + 6884 sc->pg_bd_mbuf_alloc_size)) 6885 ether_mtu = sc->rx_bd_mbuf_data_len + 6886 sc->pg_bd_mbuf_alloc_size; 6887 else 6888 ether_mtu = ifp->if_mtu; 6889 } else { 6890 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6891 ether_mtu = sc->rx_bd_mbuf_data_len; 6892 else 6893 ether_mtu = ifp->if_mtu; 6894 } 6895 } 6896 6897 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6898 6899 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 6900 __FUNCTION__, ether_mtu); 6901 6902 /* Program the mtu, enabling jumbo frame support if necessary. */ 6903 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6904 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6905 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6906 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6907 else 6908 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6909 6910 /* Program appropriate promiscuous/multicast filtering. */ 6911 bce_set_rx_mode(sc); 6912 6913 if (bce_hdr_split == TRUE) { 6914 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6915 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6916 6917 /* Init page buffer descriptor chain. */ 6918 bce_init_pg_chain(sc); 6919 } 6920 6921 /* Init RX buffer descriptor chain. */ 6922 bce_init_rx_chain(sc); 6923 6924 /* Init TX buffer descriptor chain. */ 6925 bce_init_tx_chain(sc); 6926 6927 /* Enable host interrupts. */ 6928 bce_enable_intr(sc, 1); 6929 6930 bce_ifmedia_upd_locked(ifp); 6931 6932 /* Let the OS know the driver is up and running. */ 6933 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6934 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6935 6936 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6937 6938 bce_init_locked_exit: 6939 DBEXIT(BCE_VERBOSE_RESET); 6940 } 6941 6942 6943 /****************************************************************************/ 6944 /* Initialize the controller just enough so that any management firmware */ 6945 /* running on the device will continue to operate correctly. */ 6946 /* */ 6947 /* Returns: */ 6948 /* Nothing. */ 6949 /****************************************************************************/ 6950 static void 6951 bce_mgmt_init_locked(struct bce_softc *sc) 6952 { 6953 struct ifnet *ifp; 6954 6955 DBENTER(BCE_VERBOSE_RESET); 6956 6957 BCE_LOCK_ASSERT(sc); 6958 6959 /* Bail out if management firmware is not running. */ 6960 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6961 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6962 "No management firmware running...\n"); 6963 goto bce_mgmt_init_locked_exit; 6964 } 6965 6966 ifp = sc->bce_ifp; 6967 6968 /* Enable all critical blocks in the MAC. */ 6969 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6970 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6971 DELAY(20); 6972 6973 bce_ifmedia_upd_locked(ifp); 6974 6975 bce_mgmt_init_locked_exit: 6976 DBEXIT(BCE_VERBOSE_RESET); 6977 } 6978 6979 6980 /****************************************************************************/ 6981 /* Handles controller initialization when called from an unlocked routine. */ 6982 /* */ 6983 /* Returns: */ 6984 /* Nothing. */ 6985 /****************************************************************************/ 6986 static void 6987 bce_init(void *xsc) 6988 { 6989 struct bce_softc *sc = xsc; 6990 6991 DBENTER(BCE_VERBOSE_RESET); 6992 6993 BCE_LOCK(sc); 6994 bce_init_locked(sc); 6995 BCE_UNLOCK(sc); 6996 6997 DBEXIT(BCE_VERBOSE_RESET); 6998 } 6999 7000 7001 /****************************************************************************/ 7002 /* Modifies an mbuf for TSO on the hardware. */ 7003 /* */ 7004 /* Returns: */ 7005 /* Pointer to a modified mbuf. */ 7006 /****************************************************************************/ 7007 static struct mbuf * 7008 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7009 { 7010 struct mbuf *m; 7011 struct ether_header *eh; 7012 struct ip *ip; 7013 struct tcphdr *th; 7014 u16 etype; 7015 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7016 7017 DBRUN(sc->tso_frames_requested++); 7018 7019 /* Controller may modify mbuf chains. */ 7020 if (M_WRITABLE(*m_head) == 0) { 7021 m = m_dup(*m_head, M_DONTWAIT); 7022 m_freem(*m_head); 7023 if (m == NULL) { 7024 sc->mbuf_alloc_failed_count++; 7025 *m_head = NULL; 7026 return (NULL); 7027 } 7028 *m_head = m; 7029 } 7030 7031 /* 7032 * For TSO the controller needs two pieces of info, 7033 * the MSS and the IP+TCP options length. 7034 */ 7035 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7036 if (m == NULL) { 7037 *m_head = NULL; 7038 return (NULL); 7039 } 7040 eh = mtod(m, struct ether_header *); 7041 etype = ntohs(eh->ether_type); 7042 7043 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7044 switch (etype) { 7045 case ETHERTYPE_IP: 7046 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7047 /* TSO only supported for TCP protocol. */ 7048 if (ip->ip_p != IPPROTO_TCP) { 7049 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7050 __FILE__, __LINE__); 7051 m_freem(*m_head); 7052 *m_head = NULL; 7053 return (NULL); 7054 } 7055 7056 /* Get IP header length in bytes (min 20) */ 7057 ip_hlen = ip->ip_hl << 2; 7058 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7059 sizeof(struct tcphdr)); 7060 if (m == NULL) { 7061 *m_head = NULL; 7062 return (NULL); 7063 } 7064 7065 /* Get the TCP header length in bytes (min 20) */ 7066 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7067 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7068 tcp_hlen = (th->th_off << 2); 7069 7070 /* Make sure all IP/TCP options live in the same buffer. */ 7071 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7072 tcp_hlen); 7073 if (m == NULL) { 7074 *m_head = NULL; 7075 return (NULL); 7076 } 7077 7078 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7079 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7080 ip_len = ip->ip_len; 7081 ip->ip_len = 0; 7082 ip->ip_sum = 0; 7083 break; 7084 case ETHERTYPE_IPV6: 7085 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7086 __FILE__, __LINE__); 7087 m_freem(*m_head); 7088 *m_head = NULL; 7089 return (NULL); 7090 /* NOT REACHED */ 7091 default: 7092 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7093 __FILE__, __LINE__); 7094 m_freem(*m_head); 7095 *m_head = NULL; 7096 return (NULL); 7097 } 7098 7099 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7100 7101 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7102 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7103 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7104 tcp_hlen, ip_len); 7105 7106 /* Set the LSO flag in the TX BD */ 7107 *flags |= TX_BD_FLAGS_SW_LSO; 7108 7109 /* Set the length of IP + TCP options (in 32 bit words) */ 7110 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7111 sizeof(struct tcphdr)) >> 2) << 8); 7112 7113 DBRUN(sc->tso_frames_completed++); 7114 return (*m_head); 7115 } 7116 7117 7118 /****************************************************************************/ 7119 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7120 /* memory visible to the controller. */ 7121 /* */ 7122 /* Returns: */ 7123 /* 0 for success, positive value for failure. */ 7124 /* Modified: */ 7125 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7126 /****************************************************************************/ 7127 static int 7128 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7129 { 7130 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7131 bus_dmamap_t map; 7132 struct tx_bd *txbd = NULL; 7133 struct mbuf *m0; 7134 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7135 u32 prod_bseq; 7136 7137 #ifdef BCE_DEBUG 7138 u16 debug_prod; 7139 #endif 7140 7141 int i, error, nsegs, rc = 0; 7142 7143 DBENTER(BCE_VERBOSE_SEND); 7144 7145 /* Make sure we have room in the TX chain. */ 7146 if (sc->used_tx_bd >= sc->max_tx_bd) 7147 goto bce_tx_encap_exit; 7148 7149 /* Transfer any checksum offload flags to the bd. */ 7150 m0 = *m_head; 7151 if (m0->m_pkthdr.csum_flags) { 7152 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7153 m0 = bce_tso_setup(sc, m_head, &flags); 7154 if (m0 == NULL) { 7155 DBRUN(sc->tso_frames_failed++); 7156 goto bce_tx_encap_exit; 7157 } 7158 mss = htole16(m0->m_pkthdr.tso_segsz); 7159 } else { 7160 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7161 flags |= TX_BD_FLAGS_IP_CKSUM; 7162 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7163 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7164 } 7165 } 7166 7167 /* Transfer any VLAN tags to the bd. */ 7168 if (m0->m_flags & M_VLANTAG) { 7169 flags |= TX_BD_FLAGS_VLAN_TAG; 7170 vlan_tag = m0->m_pkthdr.ether_vtag; 7171 } 7172 7173 /* Map the mbuf into DMAable memory. */ 7174 prod = sc->tx_prod; 7175 chain_prod = TX_CHAIN_IDX(prod); 7176 map = sc->tx_mbuf_map[chain_prod]; 7177 7178 /* Map the mbuf into our DMA address space. */ 7179 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7180 segs, &nsegs, BUS_DMA_NOWAIT); 7181 7182 /* Check if the DMA mapping was successful */ 7183 if (error == EFBIG) { 7184 sc->mbuf_frag_count++; 7185 7186 /* Try to defrag the mbuf. */ 7187 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 7188 if (m0 == NULL) { 7189 /* Defrag was unsuccessful */ 7190 m_freem(*m_head); 7191 *m_head = NULL; 7192 sc->mbuf_alloc_failed_count++; 7193 rc = ENOBUFS; 7194 goto bce_tx_encap_exit; 7195 } 7196 7197 /* Defrag was successful, try mapping again */ 7198 *m_head = m0; 7199 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7200 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7201 7202 /* Still getting an error after a defrag. */ 7203 if (error == ENOMEM) { 7204 /* Insufficient DMA buffers available. */ 7205 sc->dma_map_addr_tx_failed_count++; 7206 rc = error; 7207 goto bce_tx_encap_exit; 7208 } else if (error != 0) { 7209 /* Release it and return an error. */ 7210 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7211 "TX chain!\n", __FILE__, __LINE__); 7212 m_freem(m0); 7213 *m_head = NULL; 7214 sc->dma_map_addr_tx_failed_count++; 7215 rc = ENOBUFS; 7216 goto bce_tx_encap_exit; 7217 } 7218 } else if (error == ENOMEM) { 7219 /* Insufficient DMA buffers available. */ 7220 sc->dma_map_addr_tx_failed_count++; 7221 rc = error; 7222 goto bce_tx_encap_exit; 7223 } else if (error != 0) { 7224 m_freem(m0); 7225 *m_head = NULL; 7226 sc->dma_map_addr_tx_failed_count++; 7227 rc = error; 7228 goto bce_tx_encap_exit; 7229 } 7230 7231 /* Make sure there's room in the chain */ 7232 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7233 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7234 rc = ENOBUFS; 7235 goto bce_tx_encap_exit; 7236 } 7237 7238 /* prod points to an empty tx_bd at this point. */ 7239 prod_bseq = sc->tx_prod_bseq; 7240 7241 #ifdef BCE_DEBUG 7242 debug_prod = chain_prod; 7243 #endif 7244 7245 DBPRINT(sc, BCE_INFO_SEND, 7246 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7247 "prod_bseq = 0x%08X\n", 7248 __FUNCTION__, prod, chain_prod, prod_bseq); 7249 7250 /* 7251 * Cycle through each mbuf segment that makes up 7252 * the outgoing frame, gathering the mapping info 7253 * for that segment and creating a tx_bd for 7254 * the mbuf. 7255 */ 7256 for (i = 0; i < nsegs ; i++) { 7257 7258 chain_prod = TX_CHAIN_IDX(prod); 7259 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7260 [TX_IDX(chain_prod)]; 7261 7262 txbd->tx_bd_haddr_lo = 7263 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7264 txbd->tx_bd_haddr_hi = 7265 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7266 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7267 htole16(segs[i].ds_len); 7268 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7269 txbd->tx_bd_flags = htole16(flags); 7270 prod_bseq += segs[i].ds_len; 7271 if (i == 0) 7272 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7273 prod = NEXT_TX_BD(prod); 7274 } 7275 7276 /* Set the END flag on the last TX buffer descriptor. */ 7277 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7278 7279 DBRUNMSG(BCE_EXTREME_SEND, 7280 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7281 7282 /* 7283 * Ensure that the mbuf pointer for this transmission 7284 * is placed at the array index of the last 7285 * descriptor in this chain. This is done 7286 * because a single map is used for all 7287 * segments of the mbuf and we don't want to 7288 * unload the map before all of the segments 7289 * have been freed. 7290 */ 7291 sc->tx_mbuf_ptr[chain_prod] = m0; 7292 sc->used_tx_bd += nsegs; 7293 7294 /* Update some debug statistic counters */ 7295 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7296 sc->tx_hi_watermark = sc->used_tx_bd); 7297 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7298 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7299 7300 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7301 7302 /* prod points to the next free tx_bd at this point. */ 7303 sc->tx_prod = prod; 7304 sc->tx_prod_bseq = prod_bseq; 7305 7306 /* Tell the chip about the waiting TX frames. */ 7307 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7308 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7309 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7310 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7311 7312 bce_tx_encap_exit: 7313 DBEXIT(BCE_VERBOSE_SEND); 7314 return(rc); 7315 } 7316 7317 7318 /****************************************************************************/ 7319 /* Main transmit routine when called from another routine with a lock. */ 7320 /* */ 7321 /* Returns: */ 7322 /* Nothing. */ 7323 /****************************************************************************/ 7324 static void 7325 bce_start_locked(struct ifnet *ifp) 7326 { 7327 struct bce_softc *sc = ifp->if_softc; 7328 struct mbuf *m_head = NULL; 7329 int count = 0; 7330 u16 tx_prod, tx_chain_prod; 7331 7332 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7333 7334 BCE_LOCK_ASSERT(sc); 7335 7336 /* prod points to the next free tx_bd. */ 7337 tx_prod = sc->tx_prod; 7338 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7339 7340 DBPRINT(sc, BCE_INFO_SEND, 7341 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7342 "tx_prod_bseq = 0x%08X\n", 7343 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7344 7345 /* If there's no link or the transmit queue is empty then just exit. */ 7346 if (sc->bce_link_up == FALSE) { 7347 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7348 __FUNCTION__); 7349 goto bce_start_locked_exit; 7350 } 7351 7352 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7353 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7354 __FUNCTION__); 7355 goto bce_start_locked_exit; 7356 } 7357 7358 /* 7359 * Keep adding entries while there is space in the ring. 7360 */ 7361 while (sc->used_tx_bd < sc->max_tx_bd) { 7362 7363 /* Check for any frames to send. */ 7364 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7365 7366 /* Stop when the transmit queue is empty. */ 7367 if (m_head == NULL) 7368 break; 7369 7370 /* 7371 * Pack the data into the transmit ring. If we 7372 * don't have room, place the mbuf back at the 7373 * head of the queue and set the OACTIVE flag 7374 * to wait for the NIC to drain the chain. 7375 */ 7376 if (bce_tx_encap(sc, &m_head)) { 7377 if (m_head != NULL) 7378 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7379 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7380 DBPRINT(sc, BCE_INFO_SEND, 7381 "TX chain is closed for business! Total " 7382 "tx_bd used = %d\n", sc->used_tx_bd); 7383 break; 7384 } 7385 7386 count++; 7387 7388 /* Send a copy of the frame to any BPF listeners. */ 7389 ETHER_BPF_MTAP(ifp, m_head); 7390 } 7391 7392 /* Exit if no packets were dequeued. */ 7393 if (count == 0) { 7394 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7395 "dequeued\n", __FUNCTION__); 7396 goto bce_start_locked_exit; 7397 } 7398 7399 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7400 "send queue.\n", __FUNCTION__, count); 7401 7402 /* Set the tx timeout. */ 7403 sc->watchdog_timer = BCE_TX_TIMEOUT; 7404 7405 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7406 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7407 7408 bce_start_locked_exit: 7409 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7410 return; 7411 } 7412 7413 7414 /****************************************************************************/ 7415 /* Main transmit routine when called from another routine without a lock. */ 7416 /* */ 7417 /* Returns: */ 7418 /* Nothing. */ 7419 /****************************************************************************/ 7420 static void 7421 bce_start(struct ifnet *ifp) 7422 { 7423 struct bce_softc *sc = ifp->if_softc; 7424 7425 DBENTER(BCE_VERBOSE_SEND); 7426 7427 BCE_LOCK(sc); 7428 bce_start_locked(ifp); 7429 BCE_UNLOCK(sc); 7430 7431 DBEXIT(BCE_VERBOSE_SEND); 7432 } 7433 7434 7435 /****************************************************************************/ 7436 /* Handles any IOCTL calls from the operating system. */ 7437 /* */ 7438 /* Returns: */ 7439 /* 0 for success, positive value for failure. */ 7440 /****************************************************************************/ 7441 static int 7442 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7443 { 7444 struct bce_softc *sc = ifp->if_softc; 7445 struct ifreq *ifr = (struct ifreq *) data; 7446 struct mii_data *mii; 7447 int mask, error = 0; 7448 7449 DBENTER(BCE_VERBOSE_MISC); 7450 7451 switch(command) { 7452 7453 /* Set the interface MTU. */ 7454 case SIOCSIFMTU: 7455 /* Check that the MTU setting is supported. */ 7456 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7457 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7458 error = EINVAL; 7459 break; 7460 } 7461 7462 DBPRINT(sc, BCE_INFO_MISC, 7463 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7464 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7465 7466 BCE_LOCK(sc); 7467 ifp->if_mtu = ifr->ifr_mtu; 7468 7469 if (bce_hdr_split == FALSE) { 7470 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7471 /* 7472 * Because allocation size is used in RX 7473 * buffer allocation, stop controller if 7474 * it is already running. 7475 */ 7476 bce_stop(sc); 7477 } 7478 7479 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7480 7481 bce_init_locked(sc); 7482 } 7483 7484 BCE_UNLOCK(sc); 7485 break; 7486 7487 /* Set interface flags. */ 7488 case SIOCSIFFLAGS: 7489 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7490 7491 BCE_LOCK(sc); 7492 7493 /* Check if the interface is up. */ 7494 if (ifp->if_flags & IFF_UP) { 7495 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7496 /* Change promiscuous/multicast flags as necessary. */ 7497 bce_set_rx_mode(sc); 7498 } else { 7499 /* Start the HW */ 7500 bce_init_locked(sc); 7501 } 7502 } else { 7503 /* The interface is down, check if driver is running. */ 7504 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7505 bce_stop(sc); 7506 7507 /* If MFW is running, restart the controller a bit. */ 7508 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7509 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7510 bce_chipinit(sc); 7511 bce_mgmt_init_locked(sc); 7512 } 7513 } 7514 } 7515 7516 BCE_UNLOCK(sc); 7517 break; 7518 7519 /* Add/Delete multicast address */ 7520 case SIOCADDMULTI: 7521 case SIOCDELMULTI: 7522 DBPRINT(sc, BCE_VERBOSE_MISC, 7523 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7524 7525 BCE_LOCK(sc); 7526 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7527 bce_set_rx_mode(sc); 7528 BCE_UNLOCK(sc); 7529 7530 break; 7531 7532 /* Set/Get Interface media */ 7533 case SIOCSIFMEDIA: 7534 case SIOCGIFMEDIA: 7535 DBPRINT(sc, BCE_VERBOSE_MISC, 7536 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7537 7538 mii = device_get_softc(sc->bce_miibus); 7539 error = ifmedia_ioctl(ifp, ifr, 7540 &mii->mii_media, command); 7541 break; 7542 7543 /* Set interface capability */ 7544 case SIOCSIFCAP: 7545 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7546 DBPRINT(sc, BCE_INFO_MISC, 7547 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7548 7549 /* Toggle the TX checksum capabilities enable flag. */ 7550 if (mask & IFCAP_TXCSUM && 7551 ifp->if_capabilities & IFCAP_TXCSUM) { 7552 ifp->if_capenable ^= IFCAP_TXCSUM; 7553 if (IFCAP_TXCSUM & ifp->if_capenable) 7554 ifp->if_hwassist |= BCE_IF_HWASSIST; 7555 else 7556 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7557 } 7558 7559 /* Toggle the RX checksum capabilities enable flag. */ 7560 if (mask & IFCAP_RXCSUM && 7561 ifp->if_capabilities & IFCAP_RXCSUM) 7562 ifp->if_capenable ^= IFCAP_RXCSUM; 7563 7564 /* Toggle the TSO capabilities enable flag. */ 7565 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7566 ifp->if_capabilities & IFCAP_TSO4) { 7567 ifp->if_capenable ^= IFCAP_TSO4; 7568 if (IFCAP_TSO4 & ifp->if_capenable) 7569 ifp->if_hwassist |= CSUM_TSO; 7570 else 7571 ifp->if_hwassist &= ~CSUM_TSO; 7572 } 7573 7574 if (mask & IFCAP_VLAN_HWCSUM && 7575 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7576 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7577 7578 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7579 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7580 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7581 /* 7582 * Don't actually disable VLAN tag stripping as 7583 * management firmware (ASF/IPMI/UMP) requires the 7584 * feature. If VLAN tag stripping is disabled driver 7585 * will manually reconstruct the VLAN frame by 7586 * appending stripped VLAN tag. 7587 */ 7588 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7589 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7590 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7591 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7592 == 0) 7593 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7594 } 7595 VLAN_CAPABILITIES(ifp); 7596 break; 7597 default: 7598 /* We don't know how to handle the IOCTL, pass it on. */ 7599 error = ether_ioctl(ifp, command, data); 7600 break; 7601 } 7602 7603 DBEXIT(BCE_VERBOSE_MISC); 7604 return(error); 7605 } 7606 7607 7608 /****************************************************************************/ 7609 /* Transmit timeout handler. */ 7610 /* */ 7611 /* Returns: */ 7612 /* Nothing. */ 7613 /****************************************************************************/ 7614 static void 7615 bce_watchdog(struct bce_softc *sc) 7616 { 7617 DBENTER(BCE_EXTREME_SEND); 7618 7619 BCE_LOCK_ASSERT(sc); 7620 7621 /* If the watchdog timer hasn't expired then just exit. */ 7622 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7623 goto bce_watchdog_exit; 7624 7625 /* If pause frames are active then don't reset the hardware. */ 7626 /* ToDo: Should we reset the timer here? */ 7627 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7628 goto bce_watchdog_exit; 7629 7630 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7631 __FILE__, __LINE__); 7632 7633 DBRUNMSG(BCE_INFO, 7634 bce_dump_driver_state(sc); 7635 bce_dump_status_block(sc); 7636 bce_dump_stats_block(sc); 7637 bce_dump_ftqs(sc); 7638 bce_dump_txp_state(sc, 0); 7639 bce_dump_rxp_state(sc, 0); 7640 bce_dump_tpat_state(sc, 0); 7641 bce_dump_cp_state(sc, 0); 7642 bce_dump_com_state(sc, 0)); 7643 7644 DBRUN(bce_breakpoint(sc)); 7645 7646 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7647 7648 bce_init_locked(sc); 7649 sc->bce_ifp->if_oerrors++; 7650 7651 bce_watchdog_exit: 7652 DBEXIT(BCE_EXTREME_SEND); 7653 } 7654 7655 7656 /* 7657 * Interrupt handler. 7658 */ 7659 /****************************************************************************/ 7660 /* Main interrupt entry point. Verifies that the controller generated the */ 7661 /* interrupt and then calls a separate routine for handle the various */ 7662 /* interrupt causes (PHY, TX, RX). */ 7663 /* */ 7664 /* Returns: */ 7665 /* 0 for success, positive value for failure. */ 7666 /****************************************************************************/ 7667 static void 7668 bce_intr(void *xsc) 7669 { 7670 struct bce_softc *sc; 7671 struct ifnet *ifp; 7672 u32 status_attn_bits; 7673 u16 hw_rx_cons, hw_tx_cons; 7674 7675 sc = xsc; 7676 ifp = sc->bce_ifp; 7677 7678 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7679 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7680 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7681 7682 BCE_LOCK(sc); 7683 7684 DBRUN(sc->interrupts_generated++); 7685 7686 /* Synchnorize before we read from interface's status block */ 7687 bus_dmamap_sync(sc->status_tag, sc->status_map, 7688 BUS_DMASYNC_POSTREAD); 7689 7690 /* 7691 * If the hardware status block index 7692 * matches the last value read by the 7693 * driver and we haven't asserted our 7694 * interrupt then there's nothing to do. 7695 */ 7696 if ((sc->status_block->status_idx == sc->last_status_idx) && 7697 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7698 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7699 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7700 __FUNCTION__); 7701 goto bce_intr_exit; 7702 } 7703 7704 /* Ack the interrupt and stop others from occuring. */ 7705 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7706 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7707 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7708 7709 /* Check if the hardware has finished any work. */ 7710 hw_rx_cons = bce_get_hw_rx_cons(sc); 7711 hw_tx_cons = bce_get_hw_tx_cons(sc); 7712 7713 /* Keep processing data as long as there is work to do. */ 7714 for (;;) { 7715 7716 status_attn_bits = sc->status_block->status_attn_bits; 7717 7718 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7719 BCE_PRINTF("Simulating unexpected status attention " 7720 "bit set."); 7721 sc->unexpected_attention_sim_count++; 7722 status_attn_bits = status_attn_bits | 7723 STATUS_ATTN_BITS_PARITY_ERROR); 7724 7725 /* Was it a link change interrupt? */ 7726 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7727 (sc->status_block->status_attn_bits_ack & 7728 STATUS_ATTN_BITS_LINK_STATE)) { 7729 bce_phy_intr(sc); 7730 7731 /* Clear transient updates during link state change. */ 7732 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7733 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7734 REG_RD(sc, BCE_HC_COMMAND); 7735 } 7736 7737 /* If any other attention is asserted, the chip is toast. */ 7738 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7739 (sc->status_block->status_attn_bits_ack & 7740 ~STATUS_ATTN_BITS_LINK_STATE))) { 7741 7742 sc->unexpected_attention_count++; 7743 7744 BCE_PRINTF("%s(%d): Fatal attention detected: " 7745 "0x%08X\n", __FILE__, __LINE__, 7746 sc->status_block->status_attn_bits); 7747 7748 DBRUNMSG(BCE_FATAL, 7749 if (unexpected_attention_sim_control == 0) 7750 bce_breakpoint(sc)); 7751 7752 bce_init_locked(sc); 7753 goto bce_intr_exit; 7754 } 7755 7756 /* Check for any completed RX frames. */ 7757 if (hw_rx_cons != sc->hw_rx_cons) 7758 bce_rx_intr(sc); 7759 7760 /* Check for any completed TX frames. */ 7761 if (hw_tx_cons != sc->hw_tx_cons) 7762 bce_tx_intr(sc); 7763 7764 /* Save status block index value for the next interrupt. */ 7765 sc->last_status_idx = sc->status_block->status_idx; 7766 7767 /* 7768 * Prevent speculative reads from getting 7769 * ahead of the status block. 7770 */ 7771 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7772 BUS_SPACE_BARRIER_READ); 7773 7774 /* 7775 * If there's no work left then exit the 7776 * interrupt service routine. 7777 */ 7778 hw_rx_cons = bce_get_hw_rx_cons(sc); 7779 hw_tx_cons = bce_get_hw_tx_cons(sc); 7780 7781 if ((hw_rx_cons == sc->hw_rx_cons) && 7782 (hw_tx_cons == sc->hw_tx_cons)) 7783 break; 7784 7785 } 7786 7787 bus_dmamap_sync(sc->status_tag, sc->status_map, 7788 BUS_DMASYNC_PREREAD); 7789 7790 /* Re-enable interrupts. */ 7791 bce_enable_intr(sc, 0); 7792 7793 /* Handle any frames that arrived while handling the interrupt. */ 7794 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7795 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7796 bce_start_locked(ifp); 7797 7798 bce_intr_exit: 7799 BCE_UNLOCK(sc); 7800 7801 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7802 } 7803 7804 7805 /****************************************************************************/ 7806 /* Programs the various packet receive modes (broadcast and multicast). */ 7807 /* */ 7808 /* Returns: */ 7809 /* Nothing. */ 7810 /****************************************************************************/ 7811 static void 7812 bce_set_rx_mode(struct bce_softc *sc) 7813 { 7814 struct ifnet *ifp; 7815 struct ifmultiaddr *ifma; 7816 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7817 u32 rx_mode, sort_mode; 7818 int h, i; 7819 7820 DBENTER(BCE_VERBOSE_MISC); 7821 7822 BCE_LOCK_ASSERT(sc); 7823 7824 ifp = sc->bce_ifp; 7825 7826 /* Initialize receive mode default settings. */ 7827 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7828 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7829 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7830 7831 /* 7832 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7833 * be enbled. 7834 */ 7835 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7836 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7837 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7838 7839 /* 7840 * Check for promiscuous, all multicast, or selected 7841 * multicast address filtering. 7842 */ 7843 if (ifp->if_flags & IFF_PROMISC) { 7844 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7845 7846 /* Enable promiscuous mode. */ 7847 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7848 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7849 } else if (ifp->if_flags & IFF_ALLMULTI) { 7850 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7851 7852 /* Enable all multicast addresses. */ 7853 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7854 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7855 } 7856 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7857 } else { 7858 /* Accept one or more multicast(s). */ 7859 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7860 7861 if_maddr_rlock(ifp); 7862 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7863 if (ifma->ifma_addr->sa_family != AF_LINK) 7864 continue; 7865 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7866 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7867 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7868 } 7869 if_maddr_runlock(ifp); 7870 7871 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7872 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7873 7874 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7875 } 7876 7877 /* Only make changes if the recive mode has actually changed. */ 7878 if (rx_mode != sc->rx_mode) { 7879 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7880 "0x%08X\n", rx_mode); 7881 7882 sc->rx_mode = rx_mode; 7883 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7884 } 7885 7886 /* Disable and clear the exisitng sort before enabling a new sort. */ 7887 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7888 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7889 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7890 7891 DBEXIT(BCE_VERBOSE_MISC); 7892 } 7893 7894 7895 /****************************************************************************/ 7896 /* Called periodically to updates statistics from the controllers */ 7897 /* statistics block. */ 7898 /* */ 7899 /* Returns: */ 7900 /* Nothing. */ 7901 /****************************************************************************/ 7902 static void 7903 bce_stats_update(struct bce_softc *sc) 7904 { 7905 struct ifnet *ifp; 7906 struct statistics_block *stats; 7907 7908 DBENTER(BCE_EXTREME_MISC); 7909 7910 ifp = sc->bce_ifp; 7911 7912 stats = (struct statistics_block *) sc->stats_block; 7913 7914 /* 7915 * Certain controllers don't report 7916 * carrier sense errors correctly. 7917 * See errata E11_5708CA0_1165. 7918 */ 7919 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7920 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7921 ifp->if_oerrors += 7922 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7923 7924 /* 7925 * Update the sysctl statistics from the 7926 * hardware statistics. 7927 */ 7928 sc->stat_IfHCInOctets = 7929 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7930 (u64) stats->stat_IfHCInOctets_lo; 7931 7932 sc->stat_IfHCInBadOctets = 7933 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7934 (u64) stats->stat_IfHCInBadOctets_lo; 7935 7936 sc->stat_IfHCOutOctets = 7937 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7938 (u64) stats->stat_IfHCOutOctets_lo; 7939 7940 sc->stat_IfHCOutBadOctets = 7941 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7942 (u64) stats->stat_IfHCOutBadOctets_lo; 7943 7944 sc->stat_IfHCInUcastPkts = 7945 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7946 (u64) stats->stat_IfHCInUcastPkts_lo; 7947 7948 sc->stat_IfHCInMulticastPkts = 7949 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7950 (u64) stats->stat_IfHCInMulticastPkts_lo; 7951 7952 sc->stat_IfHCInBroadcastPkts = 7953 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7954 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7955 7956 sc->stat_IfHCOutUcastPkts = 7957 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7958 (u64) stats->stat_IfHCOutUcastPkts_lo; 7959 7960 sc->stat_IfHCOutMulticastPkts = 7961 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7962 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7963 7964 sc->stat_IfHCOutBroadcastPkts = 7965 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7966 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7967 7968 /* ToDo: Preserve counters beyond 32 bits? */ 7969 /* ToDo: Read the statistics from auto-clear regs? */ 7970 7971 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7972 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7973 7974 sc->stat_Dot3StatsCarrierSenseErrors = 7975 stats->stat_Dot3StatsCarrierSenseErrors; 7976 7977 sc->stat_Dot3StatsFCSErrors = 7978 stats->stat_Dot3StatsFCSErrors; 7979 7980 sc->stat_Dot3StatsAlignmentErrors = 7981 stats->stat_Dot3StatsAlignmentErrors; 7982 7983 sc->stat_Dot3StatsSingleCollisionFrames = 7984 stats->stat_Dot3StatsSingleCollisionFrames; 7985 7986 sc->stat_Dot3StatsMultipleCollisionFrames = 7987 stats->stat_Dot3StatsMultipleCollisionFrames; 7988 7989 sc->stat_Dot3StatsDeferredTransmissions = 7990 stats->stat_Dot3StatsDeferredTransmissions; 7991 7992 sc->stat_Dot3StatsExcessiveCollisions = 7993 stats->stat_Dot3StatsExcessiveCollisions; 7994 7995 sc->stat_Dot3StatsLateCollisions = 7996 stats->stat_Dot3StatsLateCollisions; 7997 7998 sc->stat_EtherStatsCollisions = 7999 stats->stat_EtherStatsCollisions; 8000 8001 sc->stat_EtherStatsFragments = 8002 stats->stat_EtherStatsFragments; 8003 8004 sc->stat_EtherStatsJabbers = 8005 stats->stat_EtherStatsJabbers; 8006 8007 sc->stat_EtherStatsUndersizePkts = 8008 stats->stat_EtherStatsUndersizePkts; 8009 8010 sc->stat_EtherStatsOversizePkts = 8011 stats->stat_EtherStatsOversizePkts; 8012 8013 sc->stat_EtherStatsPktsRx64Octets = 8014 stats->stat_EtherStatsPktsRx64Octets; 8015 8016 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8017 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8018 8019 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8020 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8021 8022 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8023 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8024 8025 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8026 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8027 8028 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8029 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8030 8031 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8032 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8033 8034 sc->stat_EtherStatsPktsTx64Octets = 8035 stats->stat_EtherStatsPktsTx64Octets; 8036 8037 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8038 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8039 8040 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8041 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8042 8043 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8044 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8045 8046 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8047 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8048 8049 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8050 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8051 8052 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8053 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8054 8055 sc->stat_XonPauseFramesReceived = 8056 stats->stat_XonPauseFramesReceived; 8057 8058 sc->stat_XoffPauseFramesReceived = 8059 stats->stat_XoffPauseFramesReceived; 8060 8061 sc->stat_OutXonSent = 8062 stats->stat_OutXonSent; 8063 8064 sc->stat_OutXoffSent = 8065 stats->stat_OutXoffSent; 8066 8067 sc->stat_FlowControlDone = 8068 stats->stat_FlowControlDone; 8069 8070 sc->stat_MacControlFramesReceived = 8071 stats->stat_MacControlFramesReceived; 8072 8073 sc->stat_XoffStateEntered = 8074 stats->stat_XoffStateEntered; 8075 8076 sc->stat_IfInFramesL2FilterDiscards = 8077 stats->stat_IfInFramesL2FilterDiscards; 8078 8079 sc->stat_IfInRuleCheckerDiscards = 8080 stats->stat_IfInRuleCheckerDiscards; 8081 8082 sc->stat_IfInFTQDiscards = 8083 stats->stat_IfInFTQDiscards; 8084 8085 sc->stat_IfInMBUFDiscards = 8086 stats->stat_IfInMBUFDiscards; 8087 8088 sc->stat_IfInRuleCheckerP4Hit = 8089 stats->stat_IfInRuleCheckerP4Hit; 8090 8091 sc->stat_CatchupInRuleCheckerDiscards = 8092 stats->stat_CatchupInRuleCheckerDiscards; 8093 8094 sc->stat_CatchupInFTQDiscards = 8095 stats->stat_CatchupInFTQDiscards; 8096 8097 sc->stat_CatchupInMBUFDiscards = 8098 stats->stat_CatchupInMBUFDiscards; 8099 8100 sc->stat_CatchupInRuleCheckerP4Hit = 8101 stats->stat_CatchupInRuleCheckerP4Hit; 8102 8103 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8104 8105 /* 8106 * Update the interface statistics from the 8107 * hardware statistics. 8108 */ 8109 ifp->if_collisions = 8110 (u_long) sc->stat_EtherStatsCollisions; 8111 8112 /* ToDo: This method loses soft errors. */ 8113 ifp->if_ierrors = 8114 (u_long) sc->stat_EtherStatsUndersizePkts + 8115 (u_long) sc->stat_EtherStatsOversizePkts + 8116 (u_long) sc->stat_IfInMBUFDiscards + 8117 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8118 (u_long) sc->stat_Dot3StatsFCSErrors + 8119 (u_long) sc->stat_IfInRuleCheckerDiscards + 8120 (u_long) sc->stat_IfInFTQDiscards + 8121 (u_long) sc->com_no_buffers; 8122 8123 /* ToDo: This method loses soft errors. */ 8124 ifp->if_oerrors = 8125 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8126 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8127 (u_long) sc->stat_Dot3StatsLateCollisions; 8128 8129 /* ToDo: Add additional statistics? */ 8130 8131 DBEXIT(BCE_EXTREME_MISC); 8132 } 8133 8134 8135 /****************************************************************************/ 8136 /* Periodic function to notify the bootcode that the driver is still */ 8137 /* present. */ 8138 /* */ 8139 /* Returns: */ 8140 /* Nothing. */ 8141 /****************************************************************************/ 8142 static void 8143 bce_pulse(void *xsc) 8144 { 8145 struct bce_softc *sc = xsc; 8146 u32 msg; 8147 8148 DBENTER(BCE_EXTREME_MISC); 8149 8150 BCE_LOCK_ASSERT(sc); 8151 8152 /* Tell the firmware that the driver is still running. */ 8153 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8154 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8155 8156 /* Update the bootcode condition. */ 8157 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8158 8159 /* Report whether the bootcode still knows the driver is running. */ 8160 if (bce_verbose || bootverbose) { 8161 if (sc->bce_drv_cardiac_arrest == FALSE) { 8162 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8163 sc->bce_drv_cardiac_arrest = TRUE; 8164 BCE_PRINTF("%s(): Warning: bootcode " 8165 "thinks driver is absent! " 8166 "(bc_state = 0x%08X)\n", 8167 __FUNCTION__, sc->bc_state); 8168 } 8169 } else { 8170 /* 8171 * Not supported by all bootcode versions. 8172 * (v5.0.11+ and v5.2.1+) Older bootcode 8173 * will require the driver to reset the 8174 * controller to clear this condition. 8175 */ 8176 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8177 sc->bce_drv_cardiac_arrest = FALSE; 8178 BCE_PRINTF("%s(): Bootcode found the " 8179 "driver pulse! (bc_state = 0x%08X)\n", 8180 __FUNCTION__, sc->bc_state); 8181 } 8182 } 8183 } 8184 8185 8186 /* Schedule the next pulse. */ 8187 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8188 8189 DBEXIT(BCE_EXTREME_MISC); 8190 } 8191 8192 8193 /****************************************************************************/ 8194 /* Periodic function to perform maintenance tasks. */ 8195 /* */ 8196 /* Returns: */ 8197 /* Nothing. */ 8198 /****************************************************************************/ 8199 static void 8200 bce_tick(void *xsc) 8201 { 8202 struct bce_softc *sc = xsc; 8203 struct mii_data *mii; 8204 struct ifnet *ifp; 8205 8206 ifp = sc->bce_ifp; 8207 8208 DBENTER(BCE_EXTREME_MISC); 8209 8210 BCE_LOCK_ASSERT(sc); 8211 8212 /* Schedule the next tick. */ 8213 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8214 8215 /* Update the statistics from the hardware statistics block. */ 8216 bce_stats_update(sc); 8217 8218 /* 8219 * ToDo: This is a safety measure. Need to re-evaluate 8220 * high level processing logic and eliminate this code. 8221 */ 8222 /* Top off the receive and page chains. */ 8223 if (bce_hdr_split == TRUE) 8224 bce_fill_pg_chain(sc); 8225 bce_fill_rx_chain(sc); 8226 8227 /* Check that chip hasn't hung. */ 8228 bce_watchdog(sc); 8229 8230 /* If link is up already up then we're done. */ 8231 if (sc->bce_link_up == TRUE) 8232 goto bce_tick_exit; 8233 8234 /* Link is down. Check what the PHY's doing. */ 8235 mii = device_get_softc(sc->bce_miibus); 8236 mii_tick(mii); 8237 8238 /* Check if the link has come up. */ 8239 if ((mii->mii_media_status & IFM_ACTIVE) && 8240 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8241 DBPRINT(sc, BCE_VERBOSE_MISC, 8242 "%s(): Link up!\n", __FUNCTION__); 8243 sc->bce_link_up = TRUE; 8244 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8245 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8246 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8247 (bce_verbose || bootverbose)) 8248 BCE_PRINTF("Gigabit link up!\n"); 8249 8250 /* Now that link is up, handle any outstanding TX traffic. */ 8251 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8252 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8253 "pending TX traffic.\n", __FUNCTION__); 8254 bce_start_locked(ifp); 8255 } 8256 } 8257 8258 bce_tick_exit: 8259 DBEXIT(BCE_EXTREME_MISC); 8260 return; 8261 } 8262 8263 #ifdef BCE_DEBUG 8264 /****************************************************************************/ 8265 /* Allows the driver state to be dumped through the sysctl interface. */ 8266 /* */ 8267 /* Returns: */ 8268 /* 0 for success, positive value for failure. */ 8269 /****************************************************************************/ 8270 static int 8271 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8272 { 8273 int error; 8274 int result; 8275 struct bce_softc *sc; 8276 8277 result = -1; 8278 error = sysctl_handle_int(oidp, &result, 0, req); 8279 8280 if (error || !req->newptr) 8281 return (error); 8282 8283 if (result == 1) { 8284 sc = (struct bce_softc *)arg1; 8285 bce_dump_driver_state(sc); 8286 } 8287 8288 return error; 8289 } 8290 8291 8292 /****************************************************************************/ 8293 /* Allows the hardware state to be dumped through the sysctl interface. */ 8294 /* */ 8295 /* Returns: */ 8296 /* 0 for success, positive value for failure. */ 8297 /****************************************************************************/ 8298 static int 8299 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8300 { 8301 int error; 8302 int result; 8303 struct bce_softc *sc; 8304 8305 result = -1; 8306 error = sysctl_handle_int(oidp, &result, 0, req); 8307 8308 if (error || !req->newptr) 8309 return (error); 8310 8311 if (result == 1) { 8312 sc = (struct bce_softc *)arg1; 8313 bce_dump_hw_state(sc); 8314 } 8315 8316 return error; 8317 } 8318 8319 8320 /****************************************************************************/ 8321 /* Allows the status block to be dumped through the sysctl interface. */ 8322 /* */ 8323 /* Returns: */ 8324 /* 0 for success, positive value for failure. */ 8325 /****************************************************************************/ 8326 static int 8327 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8328 { 8329 int error; 8330 int result; 8331 struct bce_softc *sc; 8332 8333 result = -1; 8334 error = sysctl_handle_int(oidp, &result, 0, req); 8335 8336 if (error || !req->newptr) 8337 return (error); 8338 8339 if (result == 1) { 8340 sc = (struct bce_softc *)arg1; 8341 bce_dump_status_block(sc); 8342 } 8343 8344 return error; 8345 } 8346 8347 8348 /****************************************************************************/ 8349 /* Allows the stats block to be dumped through the sysctl interface. */ 8350 /* */ 8351 /* Returns: */ 8352 /* 0 for success, positive value for failure. */ 8353 /****************************************************************************/ 8354 static int 8355 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8356 { 8357 int error; 8358 int result; 8359 struct bce_softc *sc; 8360 8361 result = -1; 8362 error = sysctl_handle_int(oidp, &result, 0, req); 8363 8364 if (error || !req->newptr) 8365 return (error); 8366 8367 if (result == 1) { 8368 sc = (struct bce_softc *)arg1; 8369 bce_dump_stats_block(sc); 8370 } 8371 8372 return error; 8373 } 8374 8375 8376 /****************************************************************************/ 8377 /* Allows the stat counters to be cleared without unloading/reloading the */ 8378 /* driver. */ 8379 /* */ 8380 /* Returns: */ 8381 /* 0 for success, positive value for failure. */ 8382 /****************************************************************************/ 8383 static int 8384 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8385 { 8386 int error; 8387 int result; 8388 struct bce_softc *sc; 8389 8390 result = -1; 8391 error = sysctl_handle_int(oidp, &result, 0, req); 8392 8393 if (error || !req->newptr) 8394 return (error); 8395 8396 if (result == 1) { 8397 sc = (struct bce_softc *)arg1; 8398 struct statistics_block *stats; 8399 8400 stats = (struct statistics_block *) sc->stats_block; 8401 bzero(stats, sizeof(struct statistics_block)); 8402 8403 /* Clear the internal H/W statistics counters. */ 8404 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8405 8406 /* Reset the driver maintained statistics. */ 8407 sc->interrupts_rx = 8408 sc->interrupts_tx = 0; 8409 sc->tso_frames_requested = 8410 sc->tso_frames_completed = 8411 sc->tso_frames_failed = 0; 8412 sc->rx_empty_count = 8413 sc->tx_full_count = 0; 8414 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8415 sc->tx_hi_watermark = 0; 8416 sc->l2fhdr_error_count = 8417 sc->l2fhdr_error_sim_count = 0; 8418 sc->mbuf_alloc_failed_count = 8419 sc->mbuf_alloc_failed_sim_count = 0; 8420 sc->dma_map_addr_rx_failed_count = 8421 sc->dma_map_addr_tx_failed_count = 0; 8422 sc->mbuf_frag_count = 0; 8423 sc->csum_offload_tcp_udp = 8424 sc->csum_offload_ip = 0; 8425 sc->vlan_tagged_frames_rcvd = 8426 sc->vlan_tagged_frames_stripped = 0; 8427 sc->split_header_frames_rcvd = 8428 sc->split_header_tcp_frames_rcvd = 0; 8429 8430 /* Clear firmware maintained statistics. */ 8431 REG_WR_IND(sc, 0x120084, 0); 8432 } 8433 8434 return error; 8435 } 8436 8437 8438 /****************************************************************************/ 8439 /* Allows the shared memory contents to be dumped through the sysctl . */ 8440 /* interface. */ 8441 /* */ 8442 /* Returns: */ 8443 /* 0 for success, positive value for failure. */ 8444 /****************************************************************************/ 8445 static int 8446 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8447 { 8448 int error; 8449 int result; 8450 struct bce_softc *sc; 8451 8452 result = -1; 8453 error = sysctl_handle_int(oidp, &result, 0, req); 8454 8455 if (error || !req->newptr) 8456 return (error); 8457 8458 if (result == 1) { 8459 sc = (struct bce_softc *)arg1; 8460 bce_dump_shmem_state(sc); 8461 } 8462 8463 return error; 8464 } 8465 8466 8467 /****************************************************************************/ 8468 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8469 /* */ 8470 /* Returns: */ 8471 /* 0 for success, positive value for failure. */ 8472 /****************************************************************************/ 8473 static int 8474 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8475 { 8476 int error; 8477 int result; 8478 struct bce_softc *sc; 8479 8480 result = -1; 8481 error = sysctl_handle_int(oidp, &result, 0, req); 8482 8483 if (error || !req->newptr) 8484 return (error); 8485 8486 if (result == 1) { 8487 sc = (struct bce_softc *)arg1; 8488 bce_dump_bc_state(sc); 8489 } 8490 8491 return error; 8492 } 8493 8494 8495 /****************************************************************************/ 8496 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8497 /* */ 8498 /* Returns: */ 8499 /* 0 for success, positive value for failure. */ 8500 /****************************************************************************/ 8501 static int 8502 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8503 { 8504 int error; 8505 int result; 8506 struct bce_softc *sc; 8507 8508 result = -1; 8509 error = sysctl_handle_int(oidp, &result, 0, req); 8510 8511 if (error || !req->newptr) 8512 return (error); 8513 8514 if (result == 1) { 8515 sc = (struct bce_softc *)arg1; 8516 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8517 } 8518 8519 return error; 8520 } 8521 8522 8523 /****************************************************************************/ 8524 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8525 /* */ 8526 /* Returns: */ 8527 /* 0 for success, positive value for failure. */ 8528 /****************************************************************************/ 8529 static int 8530 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8531 { 8532 int error; 8533 int result; 8534 struct bce_softc *sc; 8535 8536 result = -1; 8537 error = sysctl_handle_int(oidp, &result, 0, req); 8538 8539 if (error || !req->newptr) 8540 return (error); 8541 8542 if (result == 1) { 8543 sc = (struct bce_softc *)arg1; 8544 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8545 } 8546 8547 return error; 8548 } 8549 8550 8551 /****************************************************************************/ 8552 /* Provides a sysctl interface to allow dumping the TX chain. */ 8553 /* */ 8554 /* Returns: */ 8555 /* 0 for success, positive value for failure. */ 8556 /****************************************************************************/ 8557 static int 8558 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8559 { 8560 int error; 8561 int result; 8562 struct bce_softc *sc; 8563 8564 result = -1; 8565 error = sysctl_handle_int(oidp, &result, 0, req); 8566 8567 if (error || !req->newptr) 8568 return (error); 8569 8570 if (result == 1) { 8571 sc = (struct bce_softc *)arg1; 8572 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8573 } 8574 8575 return error; 8576 } 8577 8578 8579 /****************************************************************************/ 8580 /* Provides a sysctl interface to allow dumping the page chain. */ 8581 /* */ 8582 /* Returns: */ 8583 /* 0 for success, positive value for failure. */ 8584 /****************************************************************************/ 8585 static int 8586 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8587 { 8588 int error; 8589 int result; 8590 struct bce_softc *sc; 8591 8592 result = -1; 8593 error = sysctl_handle_int(oidp, &result, 0, req); 8594 8595 if (error || !req->newptr) 8596 return (error); 8597 8598 if (result == 1) { 8599 sc = (struct bce_softc *)arg1; 8600 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8601 } 8602 8603 return error; 8604 } 8605 8606 /****************************************************************************/ 8607 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8608 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8609 /* */ 8610 /* Returns: */ 8611 /* 0 for success, positive value for failure. */ 8612 /****************************************************************************/ 8613 static int 8614 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8615 { 8616 struct bce_softc *sc = (struct bce_softc *)arg1; 8617 int error; 8618 u32 result; 8619 u32 val[1]; 8620 u8 *data = (u8 *) val; 8621 8622 result = -1; 8623 error = sysctl_handle_int(oidp, &result, 0, req); 8624 if (error || (req->newptr == NULL)) 8625 return (error); 8626 8627 error = bce_nvram_read(sc, result, data, 4); 8628 8629 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8630 8631 return (error); 8632 } 8633 8634 8635 /****************************************************************************/ 8636 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8637 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8638 /* */ 8639 /* Returns: */ 8640 /* 0 for success, positive value for failure. */ 8641 /****************************************************************************/ 8642 static int 8643 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8644 { 8645 struct bce_softc *sc = (struct bce_softc *)arg1; 8646 int error; 8647 u32 val, result; 8648 8649 result = -1; 8650 error = sysctl_handle_int(oidp, &result, 0, req); 8651 if (error || (req->newptr == NULL)) 8652 return (error); 8653 8654 /* Make sure the register is accessible. */ 8655 if (result < 0x8000) { 8656 val = REG_RD(sc, result); 8657 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8658 } else if (result < 0x0280000) { 8659 val = REG_RD_IND(sc, result); 8660 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8661 } 8662 8663 return (error); 8664 } 8665 8666 8667 /****************************************************************************/ 8668 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8669 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8670 /* */ 8671 /* Returns: */ 8672 /* 0 for success, positive value for failure. */ 8673 /****************************************************************************/ 8674 static int 8675 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8676 { 8677 struct bce_softc *sc; 8678 device_t dev; 8679 int error, result; 8680 u16 val; 8681 8682 result = -1; 8683 error = sysctl_handle_int(oidp, &result, 0, req); 8684 if (error || (req->newptr == NULL)) 8685 return (error); 8686 8687 /* Make sure the register is accessible. */ 8688 if (result < 0x20) { 8689 sc = (struct bce_softc *)arg1; 8690 dev = sc->bce_dev; 8691 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8692 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8693 } 8694 return (error); 8695 } 8696 8697 8698 /****************************************************************************/ 8699 /* Provides a sysctl interface for dumping the nvram contents. */ 8700 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8701 /* */ 8702 /* Returns: */ 8703 /* 0 for success, positive errno for failure. */ 8704 /****************************************************************************/ 8705 static int 8706 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8707 { 8708 struct bce_softc *sc = (struct bce_softc *)arg1; 8709 int error, i; 8710 8711 if (sc->nvram_buf == NULL) 8712 sc->nvram_buf = malloc(sc->bce_flash_size, 8713 M_TEMP, M_ZERO | M_WAITOK); 8714 8715 error = 0; 8716 if (req->oldlen == sc->bce_flash_size) { 8717 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8718 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8719 } 8720 8721 if (error == 0) 8722 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8723 8724 return error; 8725 } 8726 8727 #ifdef BCE_NVRAM_WRITE_SUPPORT 8728 /****************************************************************************/ 8729 /* Provides a sysctl interface for writing to nvram. */ 8730 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8731 /* */ 8732 /* Returns: */ 8733 /* 0 for success, positive errno for failure. */ 8734 /****************************************************************************/ 8735 static int 8736 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8737 { 8738 struct bce_softc *sc = (struct bce_softc *)arg1; 8739 int error; 8740 8741 if (sc->nvram_buf == NULL) 8742 sc->nvram_buf = malloc(sc->bce_flash_size, 8743 M_TEMP, M_ZERO | M_WAITOK); 8744 else 8745 bzero(sc->nvram_buf, sc->bce_flash_size); 8746 8747 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 8748 if (error == 0) 8749 return (error); 8750 8751 if (req->newlen == sc->bce_flash_size) 8752 error = bce_nvram_write(sc, 0, sc->nvram_buf, 8753 sc->bce_flash_size); 8754 8755 8756 return error; 8757 } 8758 #endif 8759 8760 8761 /****************************************************************************/ 8762 /* Provides a sysctl interface to allow reading a CID. */ 8763 /* */ 8764 /* Returns: */ 8765 /* 0 for success, positive value for failure. */ 8766 /****************************************************************************/ 8767 static int 8768 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8769 { 8770 struct bce_softc *sc; 8771 int error, result; 8772 8773 result = -1; 8774 error = sysctl_handle_int(oidp, &result, 0, req); 8775 if (error || (req->newptr == NULL)) 8776 return (error); 8777 8778 /* Make sure the register is accessible. */ 8779 if (result <= TX_CID) { 8780 sc = (struct bce_softc *)arg1; 8781 bce_dump_ctx(sc, result); 8782 } 8783 8784 return (error); 8785 } 8786 8787 8788 /****************************************************************************/ 8789 /* Provides a sysctl interface to forcing the driver to dump state and */ 8790 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8791 /* */ 8792 /* Returns: */ 8793 /* 0 for success, positive value for failure. */ 8794 /****************************************************************************/ 8795 static int 8796 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8797 { 8798 int error; 8799 int result; 8800 struct bce_softc *sc; 8801 8802 result = -1; 8803 error = sysctl_handle_int(oidp, &result, 0, req); 8804 8805 if (error || !req->newptr) 8806 return (error); 8807 8808 if (result == 1) { 8809 sc = (struct bce_softc *)arg1; 8810 bce_breakpoint(sc); 8811 } 8812 8813 return error; 8814 } 8815 #endif 8816 8817 /****************************************************************************/ 8818 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8819 /* */ 8820 /* Returns: */ 8821 /* 0 for success, positive value for failure. */ 8822 /****************************************************************************/ 8823 static void 8824 bce_add_sysctls(struct bce_softc *sc) 8825 { 8826 struct sysctl_ctx_list *ctx; 8827 struct sysctl_oid_list *children; 8828 8829 DBENTER(BCE_VERBOSE_MISC); 8830 8831 ctx = device_get_sysctl_ctx(sc->bce_dev); 8832 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8833 8834 #ifdef BCE_DEBUG 8835 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8836 "l2fhdr_error_sim_control", 8837 CTLFLAG_RW, &l2fhdr_error_sim_control, 8838 0, "Debug control to force l2fhdr errors"); 8839 8840 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8841 "l2fhdr_error_sim_count", 8842 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8843 0, "Number of simulated l2_fhdr errors"); 8844 #endif 8845 8846 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8847 "l2fhdr_error_count", 8848 CTLFLAG_RD, &sc->l2fhdr_error_count, 8849 0, "Number of l2_fhdr errors"); 8850 8851 #ifdef BCE_DEBUG 8852 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8853 "mbuf_alloc_failed_sim_control", 8854 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8855 0, "Debug control to force mbuf allocation failures"); 8856 8857 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8858 "mbuf_alloc_failed_sim_count", 8859 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8860 0, "Number of simulated mbuf cluster allocation failures"); 8861 #endif 8862 8863 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8864 "mbuf_alloc_failed_count", 8865 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8866 0, "Number of mbuf allocation failures"); 8867 8868 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8869 "mbuf_frag_count", 8870 CTLFLAG_RD, &sc->mbuf_frag_count, 8871 0, "Number of fragmented mbufs"); 8872 8873 #ifdef BCE_DEBUG 8874 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8875 "dma_map_addr_failed_sim_control", 8876 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8877 0, "Debug control to force DMA mapping failures"); 8878 8879 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 8880 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8881 "dma_map_addr_failed_sim_count", 8882 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 8883 0, "Number of simulated DMA mapping failures"); 8884 8885 #endif 8886 8887 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8888 "dma_map_addr_rx_failed_count", 8889 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 8890 0, "Number of RX DMA mapping failures"); 8891 8892 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8893 "dma_map_addr_tx_failed_count", 8894 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 8895 0, "Number of TX DMA mapping failures"); 8896 8897 #ifdef BCE_DEBUG 8898 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8899 "unexpected_attention_sim_control", 8900 CTLFLAG_RW, &unexpected_attention_sim_control, 8901 0, "Debug control to simulate unexpected attentions"); 8902 8903 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8904 "unexpected_attention_sim_count", 8905 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 8906 0, "Number of simulated unexpected attentions"); 8907 #endif 8908 8909 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8910 "unexpected_attention_count", 8911 CTLFLAG_RW, &sc->unexpected_attention_count, 8912 0, "Number of unexpected attentions"); 8913 8914 #ifdef BCE_DEBUG 8915 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8916 "debug_bootcode_running_failure", 8917 CTLFLAG_RW, &bootcode_running_failure_sim_control, 8918 0, "Debug control to force bootcode running failures"); 8919 8920 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8921 "rx_low_watermark", 8922 CTLFLAG_RD, &sc->rx_low_watermark, 8923 0, "Lowest level of free rx_bd's"); 8924 8925 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8926 "rx_empty_count", 8927 CTLFLAG_RD, &sc->rx_empty_count, 8928 "Number of times the RX chain was empty"); 8929 8930 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8931 "tx_hi_watermark", 8932 CTLFLAG_RD, &sc->tx_hi_watermark, 8933 0, "Highest level of used tx_bd's"); 8934 8935 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8936 "tx_full_count", 8937 CTLFLAG_RD, &sc->tx_full_count, 8938 "Number of times the TX chain was full"); 8939 8940 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8941 "tso_frames_requested", 8942 CTLFLAG_RD, &sc->tso_frames_requested, 8943 "Number of TSO frames requested"); 8944 8945 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8946 "tso_frames_completed", 8947 CTLFLAG_RD, &sc->tso_frames_completed, 8948 "Number of TSO frames completed"); 8949 8950 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8951 "tso_frames_failed", 8952 CTLFLAG_RD, &sc->tso_frames_failed, 8953 "Number of TSO frames failed"); 8954 8955 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8956 "csum_offload_ip", 8957 CTLFLAG_RD, &sc->csum_offload_ip, 8958 "Number of IP checksum offload frames"); 8959 8960 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8961 "csum_offload_tcp_udp", 8962 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 8963 "Number of TCP/UDP checksum offload frames"); 8964 8965 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8966 "vlan_tagged_frames_rcvd", 8967 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 8968 "Number of VLAN tagged frames received"); 8969 8970 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8971 "vlan_tagged_frames_stripped", 8972 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 8973 "Number of VLAN tagged frames stripped"); 8974 8975 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8976 "interrupts_rx", 8977 CTLFLAG_RD, &sc->interrupts_rx, 8978 "Number of RX interrupts"); 8979 8980 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8981 "interrupts_tx", 8982 CTLFLAG_RD, &sc->interrupts_tx, 8983 "Number of TX interrupts"); 8984 8985 if (bce_hdr_split == TRUE) { 8986 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8987 "split_header_frames_rcvd", 8988 CTLFLAG_RD, &sc->split_header_frames_rcvd, 8989 "Number of split header frames received"); 8990 8991 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8992 "split_header_tcp_frames_rcvd", 8993 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 8994 "Number of split header TCP frames received"); 8995 } 8996 8997 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8998 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 8999 (void *)sc, 0, 9000 bce_sysctl_nvram_dump, "S", ""); 9001 9002 #ifdef BCE_NVRAM_WRITE_SUPPORT 9003 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9004 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 9005 (void *)sc, 0, 9006 bce_sysctl_nvram_write, "S", ""); 9007 #endif 9008 #endif /* BCE_DEBUG */ 9009 9010 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9011 "stat_IfHcInOctets", 9012 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9013 "Bytes received"); 9014 9015 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9016 "stat_IfHCInBadOctets", 9017 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9018 "Bad bytes received"); 9019 9020 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9021 "stat_IfHCOutOctets", 9022 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9023 "Bytes sent"); 9024 9025 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9026 "stat_IfHCOutBadOctets", 9027 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9028 "Bad bytes sent"); 9029 9030 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9031 "stat_IfHCInUcastPkts", 9032 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9033 "Unicast packets received"); 9034 9035 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9036 "stat_IfHCInMulticastPkts", 9037 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9038 "Multicast packets received"); 9039 9040 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9041 "stat_IfHCInBroadcastPkts", 9042 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9043 "Broadcast packets received"); 9044 9045 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9046 "stat_IfHCOutUcastPkts", 9047 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9048 "Unicast packets sent"); 9049 9050 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9051 "stat_IfHCOutMulticastPkts", 9052 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9053 "Multicast packets sent"); 9054 9055 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9056 "stat_IfHCOutBroadcastPkts", 9057 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9058 "Broadcast packets sent"); 9059 9060 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9061 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9062 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9063 0, "Internal MAC transmit errors"); 9064 9065 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9066 "stat_Dot3StatsCarrierSenseErrors", 9067 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9068 0, "Carrier sense errors"); 9069 9070 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9071 "stat_Dot3StatsFCSErrors", 9072 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9073 0, "Frame check sequence errors"); 9074 9075 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9076 "stat_Dot3StatsAlignmentErrors", 9077 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9078 0, "Alignment errors"); 9079 9080 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9081 "stat_Dot3StatsSingleCollisionFrames", 9082 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9083 0, "Single Collision Frames"); 9084 9085 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9086 "stat_Dot3StatsMultipleCollisionFrames", 9087 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9088 0, "Multiple Collision Frames"); 9089 9090 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9091 "stat_Dot3StatsDeferredTransmissions", 9092 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9093 0, "Deferred Transmissions"); 9094 9095 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9096 "stat_Dot3StatsExcessiveCollisions", 9097 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9098 0, "Excessive Collisions"); 9099 9100 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9101 "stat_Dot3StatsLateCollisions", 9102 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9103 0, "Late Collisions"); 9104 9105 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9106 "stat_EtherStatsCollisions", 9107 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9108 0, "Collisions"); 9109 9110 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9111 "stat_EtherStatsFragments", 9112 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9113 0, "Fragments"); 9114 9115 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9116 "stat_EtherStatsJabbers", 9117 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9118 0, "Jabbers"); 9119 9120 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9121 "stat_EtherStatsUndersizePkts", 9122 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9123 0, "Undersize packets"); 9124 9125 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9126 "stat_EtherStatsOversizePkts", 9127 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9128 0, "stat_EtherStatsOversizePkts"); 9129 9130 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9131 "stat_EtherStatsPktsRx64Octets", 9132 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9133 0, "Bytes received in 64 byte packets"); 9134 9135 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9136 "stat_EtherStatsPktsRx65Octetsto127Octets", 9137 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9138 0, "Bytes received in 65 to 127 byte packets"); 9139 9140 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9141 "stat_EtherStatsPktsRx128Octetsto255Octets", 9142 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9143 0, "Bytes received in 128 to 255 byte packets"); 9144 9145 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9146 "stat_EtherStatsPktsRx256Octetsto511Octets", 9147 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9148 0, "Bytes received in 256 to 511 byte packets"); 9149 9150 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9151 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9152 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9153 0, "Bytes received in 512 to 1023 byte packets"); 9154 9155 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9156 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9157 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9158 0, "Bytes received in 1024 t0 1522 byte packets"); 9159 9160 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9161 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9162 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9163 0, "Bytes received in 1523 to 9022 byte packets"); 9164 9165 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9166 "stat_EtherStatsPktsTx64Octets", 9167 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9168 0, "Bytes sent in 64 byte packets"); 9169 9170 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9171 "stat_EtherStatsPktsTx65Octetsto127Octets", 9172 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9173 0, "Bytes sent in 65 to 127 byte packets"); 9174 9175 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9176 "stat_EtherStatsPktsTx128Octetsto255Octets", 9177 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9178 0, "Bytes sent in 128 to 255 byte packets"); 9179 9180 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9181 "stat_EtherStatsPktsTx256Octetsto511Octets", 9182 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9183 0, "Bytes sent in 256 to 511 byte packets"); 9184 9185 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9186 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9187 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9188 0, "Bytes sent in 512 to 1023 byte packets"); 9189 9190 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9191 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9192 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9193 0, "Bytes sent in 1024 to 1522 byte packets"); 9194 9195 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9196 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9197 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9198 0, "Bytes sent in 1523 to 9022 byte packets"); 9199 9200 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9201 "stat_XonPauseFramesReceived", 9202 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9203 0, "XON pause frames receved"); 9204 9205 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9206 "stat_XoffPauseFramesReceived", 9207 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9208 0, "XOFF pause frames received"); 9209 9210 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9211 "stat_OutXonSent", 9212 CTLFLAG_RD, &sc->stat_OutXonSent, 9213 0, "XON pause frames sent"); 9214 9215 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9216 "stat_OutXoffSent", 9217 CTLFLAG_RD, &sc->stat_OutXoffSent, 9218 0, "XOFF pause frames sent"); 9219 9220 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9221 "stat_FlowControlDone", 9222 CTLFLAG_RD, &sc->stat_FlowControlDone, 9223 0, "Flow control done"); 9224 9225 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9226 "stat_MacControlFramesReceived", 9227 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9228 0, "MAC control frames received"); 9229 9230 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9231 "stat_XoffStateEntered", 9232 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9233 0, "XOFF state entered"); 9234 9235 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9236 "stat_IfInFramesL2FilterDiscards", 9237 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9238 0, "Received L2 packets discarded"); 9239 9240 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9241 "stat_IfInRuleCheckerDiscards", 9242 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9243 0, "Received packets discarded by rule"); 9244 9245 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9246 "stat_IfInFTQDiscards", 9247 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9248 0, "Received packet FTQ discards"); 9249 9250 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9251 "stat_IfInMBUFDiscards", 9252 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9253 0, "Received packets discarded due to lack " 9254 "of controller buffer memory"); 9255 9256 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9257 "stat_IfInRuleCheckerP4Hit", 9258 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9259 0, "Received packets rule checker hits"); 9260 9261 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9262 "stat_CatchupInRuleCheckerDiscards", 9263 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9264 0, "Received packets discarded in Catchup path"); 9265 9266 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9267 "stat_CatchupInFTQDiscards", 9268 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9269 0, "Received packets discarded in FTQ in Catchup path"); 9270 9271 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9272 "stat_CatchupInMBUFDiscards", 9273 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9274 0, "Received packets discarded in controller " 9275 "buffer memory in Catchup path"); 9276 9277 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9278 "stat_CatchupInRuleCheckerP4Hit", 9279 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9280 0, "Received packets rule checker hits in Catchup path"); 9281 9282 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9283 "com_no_buffers", 9284 CTLFLAG_RD, &sc->com_no_buffers, 9285 0, "Valid packets received but no RX buffers available"); 9286 9287 #ifdef BCE_DEBUG 9288 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9289 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9290 (void *)sc, 0, 9291 bce_sysctl_driver_state, "I", "Drive state information"); 9292 9293 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9294 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9295 (void *)sc, 0, 9296 bce_sysctl_hw_state, "I", "Hardware state information"); 9297 9298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9299 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9300 (void *)sc, 0, 9301 bce_sysctl_status_block, "I", "Dump status block"); 9302 9303 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9304 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9305 (void *)sc, 0, 9306 bce_sysctl_stats_block, "I", "Dump statistics block"); 9307 9308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9309 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9310 (void *)sc, 0, 9311 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9312 9313 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9314 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9315 (void *)sc, 0, 9316 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9317 9318 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9319 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9320 (void *)sc, 0, 9321 bce_sysctl_bc_state, "I", "Bootcode state information"); 9322 9323 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9324 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9325 (void *)sc, 0, 9326 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9327 9328 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9329 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9330 (void *)sc, 0, 9331 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9332 9333 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9334 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9335 (void *)sc, 0, 9336 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9337 9338 if (bce_hdr_split == TRUE) { 9339 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9340 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9341 (void *)sc, 0, 9342 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9343 } 9344 9345 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9346 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9347 (void *)sc, 0, 9348 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9349 9350 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9351 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9352 (void *)sc, 0, 9353 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9354 9355 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9356 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9357 (void *)sc, 0, 9358 bce_sysctl_reg_read, "I", "Register read"); 9359 9360 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9361 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9362 (void *)sc, 0, 9363 bce_sysctl_nvram_read, "I", "NVRAM read"); 9364 9365 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9366 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9367 (void *)sc, 0, 9368 bce_sysctl_phy_read, "I", "PHY register read"); 9369 9370 #endif 9371 9372 DBEXIT(BCE_VERBOSE_MISC); 9373 } 9374 9375 9376 /****************************************************************************/ 9377 /* BCE Debug Routines */ 9378 /****************************************************************************/ 9379 #ifdef BCE_DEBUG 9380 9381 /****************************************************************************/ 9382 /* Freezes the controller to allow for a cohesive state dump. */ 9383 /* */ 9384 /* Returns: */ 9385 /* Nothing. */ 9386 /****************************************************************************/ 9387 static __attribute__ ((noinline)) void 9388 bce_freeze_controller(struct bce_softc *sc) 9389 { 9390 u32 val; 9391 val = REG_RD(sc, BCE_MISC_COMMAND); 9392 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9393 REG_WR(sc, BCE_MISC_COMMAND, val); 9394 } 9395 9396 9397 /****************************************************************************/ 9398 /* Unfreezes the controller after a freeze operation. This may not always */ 9399 /* work and the controller will require a reset! */ 9400 /* */ 9401 /* Returns: */ 9402 /* Nothing. */ 9403 /****************************************************************************/ 9404 static __attribute__ ((noinline)) void 9405 bce_unfreeze_controller(struct bce_softc *sc) 9406 { 9407 u32 val; 9408 val = REG_RD(sc, BCE_MISC_COMMAND); 9409 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9410 REG_WR(sc, BCE_MISC_COMMAND, val); 9411 } 9412 9413 9414 /****************************************************************************/ 9415 /* Prints out Ethernet frame information from an mbuf. */ 9416 /* */ 9417 /* Partially decode an Ethernet frame to look at some important headers. */ 9418 /* */ 9419 /* Returns: */ 9420 /* Nothing. */ 9421 /****************************************************************************/ 9422 static __attribute__ ((noinline)) void 9423 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9424 { 9425 struct ether_vlan_header *eh; 9426 u16 etype; 9427 int ehlen; 9428 struct ip *ip; 9429 struct tcphdr *th; 9430 struct udphdr *uh; 9431 struct arphdr *ah; 9432 9433 BCE_PRINTF( 9434 "-----------------------------" 9435 " Frame Decode " 9436 "-----------------------------\n"); 9437 9438 eh = mtod(m, struct ether_vlan_header *); 9439 9440 /* Handle VLAN encapsulation if present. */ 9441 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9442 etype = ntohs(eh->evl_proto); 9443 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9444 } else { 9445 etype = ntohs(eh->evl_encap_proto); 9446 ehlen = ETHER_HDR_LEN; 9447 } 9448 9449 /* ToDo: Add VLAN output. */ 9450 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9451 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9452 9453 switch (etype) { 9454 case ETHERTYPE_IP: 9455 ip = (struct ip *)(m->m_data + ehlen); 9456 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9457 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9458 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9459 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9460 9461 switch (ip->ip_p) { 9462 case IPPROTO_TCP: 9463 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9464 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9465 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9466 ntohs(th->th_dport), ntohs(th->th_sport), 9467 (th->th_off << 2), th->th_flags, 9468 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9469 "\02SYN\01FIN", ntohs(th->th_sum)); 9470 break; 9471 case IPPROTO_UDP: 9472 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9473 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9474 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9475 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9476 ntohs(uh->uh_sum)); 9477 break; 9478 case IPPROTO_ICMP: 9479 BCE_PRINTF("icmp:\n"); 9480 break; 9481 default: 9482 BCE_PRINTF("----: Other IP protocol.\n"); 9483 } 9484 break; 9485 case ETHERTYPE_IPV6: 9486 BCE_PRINTF("ipv6: No decode supported.\n"); 9487 break; 9488 case ETHERTYPE_ARP: 9489 BCE_PRINTF("-arp: "); 9490 ah = (struct arphdr *) (m->m_data + ehlen); 9491 switch (ntohs(ah->ar_op)) { 9492 case ARPOP_REVREQUEST: 9493 printf("reverse ARP request\n"); 9494 break; 9495 case ARPOP_REVREPLY: 9496 printf("reverse ARP reply\n"); 9497 break; 9498 case ARPOP_REQUEST: 9499 printf("ARP request\n"); 9500 break; 9501 case ARPOP_REPLY: 9502 printf("ARP reply\n"); 9503 break; 9504 default: 9505 printf("other ARP operation\n"); 9506 } 9507 break; 9508 default: 9509 BCE_PRINTF("----: Other protocol.\n"); 9510 } 9511 9512 BCE_PRINTF( 9513 "-----------------------------" 9514 "--------------" 9515 "-----------------------------\n"); 9516 } 9517 9518 9519 /****************************************************************************/ 9520 /* Prints out information about an mbuf. */ 9521 /* */ 9522 /* Returns: */ 9523 /* Nothing. */ 9524 /****************************************************************************/ 9525 static __attribute__ ((noinline)) void 9526 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9527 { 9528 struct mbuf *mp = m; 9529 9530 if (m == NULL) { 9531 BCE_PRINTF("mbuf: null pointer\n"); 9532 return; 9533 } 9534 9535 while (mp) { 9536 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9537 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9538 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9539 9540 if (mp->m_flags & M_PKTHDR) { 9541 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9542 "csum_flags = %b\n", mp->m_pkthdr.len, 9543 mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" 9544 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9545 "\22M_PROMISC\23M_NOFREE", 9546 mp->m_pkthdr.csum_flags, 9547 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 9548 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9549 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9550 "\14CSUM_PSEUDO_HDR"); 9551 } 9552 9553 if (mp->m_flags & M_EXT) { 9554 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9555 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9556 switch (mp->m_ext.ext_type) { 9557 case EXT_CLUSTER: 9558 printf("EXT_CLUSTER\n"); break; 9559 case EXT_SFBUF: 9560 printf("EXT_SFBUF\n"); break; 9561 case EXT_JUMBO9: 9562 printf("EXT_JUMBO9\n"); break; 9563 case EXT_JUMBO16: 9564 printf("EXT_JUMBO16\n"); break; 9565 case EXT_PACKET: 9566 printf("EXT_PACKET\n"); break; 9567 case EXT_MBUF: 9568 printf("EXT_MBUF\n"); break; 9569 case EXT_NET_DRV: 9570 printf("EXT_NET_DRV\n"); break; 9571 case EXT_MOD_TYPE: 9572 printf("EXT_MDD_TYPE\n"); break; 9573 case EXT_DISPOSABLE: 9574 printf("EXT_DISPOSABLE\n"); break; 9575 case EXT_EXTREF: 9576 printf("EXT_EXTREF\n"); break; 9577 default: 9578 printf("UNKNOWN\n"); 9579 } 9580 } 9581 9582 mp = mp->m_next; 9583 } 9584 } 9585 9586 9587 /****************************************************************************/ 9588 /* Prints out the mbufs in the TX mbuf chain. */ 9589 /* */ 9590 /* Returns: */ 9591 /* Nothing. */ 9592 /****************************************************************************/ 9593 static __attribute__ ((noinline)) void 9594 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9595 { 9596 struct mbuf *m; 9597 9598 BCE_PRINTF( 9599 "----------------------------" 9600 " tx mbuf data " 9601 "----------------------------\n"); 9602 9603 for (int i = 0; i < count; i++) { 9604 m = sc->tx_mbuf_ptr[chain_prod]; 9605 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9606 bce_dump_mbuf(sc, m); 9607 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9608 } 9609 9610 BCE_PRINTF( 9611 "----------------------------" 9612 "----------------" 9613 "----------------------------\n"); 9614 } 9615 9616 9617 /****************************************************************************/ 9618 /* Prints out the mbufs in the RX mbuf chain. */ 9619 /* */ 9620 /* Returns: */ 9621 /* Nothing. */ 9622 /****************************************************************************/ 9623 static __attribute__ ((noinline)) void 9624 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9625 { 9626 struct mbuf *m; 9627 9628 BCE_PRINTF( 9629 "----------------------------" 9630 " rx mbuf data " 9631 "----------------------------\n"); 9632 9633 for (int i = 0; i < count; i++) { 9634 m = sc->rx_mbuf_ptr[chain_prod]; 9635 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9636 bce_dump_mbuf(sc, m); 9637 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9638 } 9639 9640 9641 BCE_PRINTF( 9642 "----------------------------" 9643 "----------------" 9644 "----------------------------\n"); 9645 } 9646 9647 9648 /****************************************************************************/ 9649 /* Prints out the mbufs in the mbuf page chain. */ 9650 /* */ 9651 /* Returns: */ 9652 /* Nothing. */ 9653 /****************************************************************************/ 9654 static __attribute__ ((noinline)) void 9655 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9656 { 9657 struct mbuf *m; 9658 9659 BCE_PRINTF( 9660 "----------------------------" 9661 " pg mbuf data " 9662 "----------------------------\n"); 9663 9664 for (int i = 0; i < count; i++) { 9665 m = sc->pg_mbuf_ptr[chain_prod]; 9666 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9667 bce_dump_mbuf(sc, m); 9668 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9669 } 9670 9671 9672 BCE_PRINTF( 9673 "----------------------------" 9674 "----------------" 9675 "----------------------------\n"); 9676 } 9677 9678 9679 /****************************************************************************/ 9680 /* Prints out a tx_bd structure. */ 9681 /* */ 9682 /* Returns: */ 9683 /* Nothing. */ 9684 /****************************************************************************/ 9685 static __attribute__ ((noinline)) void 9686 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9687 { 9688 int i = 0; 9689 9690 if (idx > MAX_TX_BD_ALLOC) 9691 /* Index out of range. */ 9692 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9693 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9694 /* TX Chain page pointer. */ 9695 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9696 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9697 txbd->tx_bd_haddr_lo); 9698 else { 9699 /* Normal tx_bd entry. */ 9700 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9701 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9702 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9703 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9704 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9705 9706 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9707 if (i>0) 9708 printf("|"); 9709 printf("CONN_FAULT"); 9710 i++; 9711 } 9712 9713 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9714 if (i>0) 9715 printf("|"); 9716 printf("TCP_UDP_CKSUM"); 9717 i++; 9718 } 9719 9720 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9721 if (i>0) 9722 printf("|"); 9723 printf("IP_CKSUM"); 9724 i++; 9725 } 9726 9727 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9728 if (i>0) 9729 printf("|"); 9730 printf("VLAN"); 9731 i++; 9732 } 9733 9734 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9735 if (i>0) 9736 printf("|"); 9737 printf("COAL_NOW"); 9738 i++; 9739 } 9740 9741 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9742 if (i>0) 9743 printf("|"); 9744 printf("DONT_GEN_CRC"); 9745 i++; 9746 } 9747 9748 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9749 if (i>0) 9750 printf("|"); 9751 printf("START"); 9752 i++; 9753 } 9754 9755 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9756 if (i>0) 9757 printf("|"); 9758 printf("END"); 9759 i++; 9760 } 9761 9762 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9763 if (i>0) 9764 printf("|"); 9765 printf("LSO"); 9766 i++; 9767 } 9768 9769 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9770 if (i>0) 9771 printf("|"); 9772 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9773 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9774 } 9775 9776 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9777 if (i>0) 9778 printf("|"); 9779 printf("SW_FLAGS"); 9780 i++; 9781 } 9782 9783 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9784 if (i>0) 9785 printf("|"); 9786 printf("SNAP)"); 9787 } else { 9788 printf(")\n"); 9789 } 9790 } 9791 } 9792 9793 9794 /****************************************************************************/ 9795 /* Prints out a rx_bd structure. */ 9796 /* */ 9797 /* Returns: */ 9798 /* Nothing. */ 9799 /****************************************************************************/ 9800 static __attribute__ ((noinline)) void 9801 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9802 { 9803 if (idx > MAX_RX_BD_ALLOC) 9804 /* Index out of range. */ 9805 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9806 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9807 /* RX Chain page pointer. */ 9808 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9809 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9810 rxbd->rx_bd_haddr_lo); 9811 else 9812 /* Normal rx_bd entry. */ 9813 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9814 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9815 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9816 rxbd->rx_bd_flags); 9817 } 9818 9819 9820 /****************************************************************************/ 9821 /* Prints out a rx_bd structure in the page chain. */ 9822 /* */ 9823 /* Returns: */ 9824 /* Nothing. */ 9825 /****************************************************************************/ 9826 static __attribute__ ((noinline)) void 9827 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9828 { 9829 if (idx > MAX_PG_BD_ALLOC) 9830 /* Index out of range. */ 9831 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9832 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9833 /* Page Chain page pointer. */ 9834 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9835 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9836 else 9837 /* Normal rx_bd entry. */ 9838 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9839 "flags = 0x%08X\n", idx, 9840 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9841 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9842 } 9843 9844 9845 /****************************************************************************/ 9846 /* Prints out a l2_fhdr structure. */ 9847 /* */ 9848 /* Returns: */ 9849 /* Nothing. */ 9850 /****************************************************************************/ 9851 static __attribute__ ((noinline)) void 9852 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9853 { 9854 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9855 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9856 "tcp_udp_xsum = 0x%04X\n", idx, 9857 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9858 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9859 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9860 } 9861 9862 9863 /****************************************************************************/ 9864 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9865 /* */ 9866 /* Returns: */ 9867 /* Nothing. */ 9868 /****************************************************************************/ 9869 static __attribute__ ((noinline)) void 9870 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9871 { 9872 if (cid > TX_CID) { 9873 BCE_PRINTF(" Unknown CID\n"); 9874 return; 9875 } 9876 9877 BCE_PRINTF( 9878 "----------------------------" 9879 " CTX Data " 9880 "----------------------------\n"); 9881 9882 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9883 9884 if (cid == RX_CID) { 9885 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9886 "producer index\n", 9887 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9888 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 9889 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9890 BCE_L2CTX_RX_HOST_BSEQ)); 9891 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9892 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9893 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9894 "descriptor address\n", 9895 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9896 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9897 "descriptor address\n", 9898 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 9899 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 9900 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9901 BCE_L2CTX_RX_NX_BDIDX)); 9902 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 9903 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9904 BCE_L2CTX_RX_HOST_PG_BDIDX)); 9905 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 9906 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 9907 BCE_L2CTX_RX_PG_BUF_SIZE)); 9908 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 9909 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9910 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 9911 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 9912 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9913 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 9914 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 9915 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9916 BCE_L2CTX_RX_NX_PG_BDIDX)); 9917 } else if (cid == TX_CID) { 9918 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9919 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9920 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 9921 CTX_RD(sc, GET_CID_ADDR(cid), 9922 BCE_L2CTX_TX_TYPE_XI)); 9923 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 9924 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 9925 BCE_L2CTX_TX_CMD_TYPE_XI)); 9926 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 9927 "h/w buffer descriptor address\n", 9928 CTX_RD(sc, GET_CID_ADDR(cid), 9929 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 9930 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 9931 "h/w buffer descriptor address\n", 9932 CTX_RD(sc, GET_CID_ADDR(cid), 9933 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 9934 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 9935 "host producer index\n", 9936 CTX_RD(sc, GET_CID_ADDR(cid), 9937 BCE_L2CTX_TX_HOST_BIDX_XI)); 9938 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 9939 "host byte sequence\n", 9940 CTX_RD(sc, GET_CID_ADDR(cid), 9941 BCE_L2CTX_TX_HOST_BSEQ_XI)); 9942 } else { 9943 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 9944 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 9945 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 9946 CTX_RD(sc, GET_CID_ADDR(cid), 9947 BCE_L2CTX_TX_CMD_TYPE)); 9948 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 9949 "h/w buffer descriptor address\n", 9950 CTX_RD(sc, GET_CID_ADDR(cid), 9951 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 9952 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 9953 "h/w buffer descriptor address\n", 9954 CTX_RD(sc, GET_CID_ADDR(cid), 9955 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 9956 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 9957 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9958 BCE_L2CTX_TX_HOST_BIDX)); 9959 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 9960 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9961 BCE_L2CTX_TX_HOST_BSEQ)); 9962 } 9963 } 9964 9965 BCE_PRINTF( 9966 "----------------------------" 9967 " Raw CTX " 9968 "----------------------------\n"); 9969 9970 for (int i = 0x0; i < 0x300; i += 0x10) { 9971 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 9972 CTX_RD(sc, GET_CID_ADDR(cid), i), 9973 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 9974 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 9975 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 9976 } 9977 9978 9979 BCE_PRINTF( 9980 "----------------------------" 9981 "----------------" 9982 "----------------------------\n"); 9983 } 9984 9985 9986 /****************************************************************************/ 9987 /* Prints out the FTQ data. */ 9988 /* */ 9989 /* Returns: */ 9990 /* Nothing. */ 9991 /****************************************************************************/ 9992 static __attribute__ ((noinline)) void 9993 bce_dump_ftqs(struct bce_softc *sc) 9994 { 9995 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 9996 9997 BCE_PRINTF( 9998 "----------------------------" 9999 " FTQ Data " 10000 "----------------------------\n"); 10001 10002 BCE_PRINTF(" FTQ Command Control Depth_Now " 10003 "Max_Depth Valid_Cnt \n"); 10004 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10005 "---------- ----------\n"); 10006 10007 /* Setup the generic statistic counters for the FTQ valid count. */ 10008 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10009 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10010 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10011 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10012 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10013 10014 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10015 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10016 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10017 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10018 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10019 10020 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10021 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10022 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10023 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10024 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10025 10026 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10027 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10028 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10029 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10030 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10031 10032 /* Input queue to the Receive Lookup state machine */ 10033 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10034 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10035 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10036 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10037 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10038 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10039 cmd, ctl, cur_depth, max_depth, valid_cnt); 10040 10041 /* Input queue to the Receive Processor */ 10042 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10043 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10044 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10045 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10046 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10047 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10048 cmd, ctl, cur_depth, max_depth, valid_cnt); 10049 10050 /* Input queue to the Recevie Processor */ 10051 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10052 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10053 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10054 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10055 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10056 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10057 cmd, ctl, cur_depth, max_depth, valid_cnt); 10058 10059 /* Input queue to the Receive Virtual to Physical state machine */ 10060 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10061 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10062 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10063 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10064 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10065 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10066 cmd, ctl, cur_depth, max_depth, valid_cnt); 10067 10068 /* Input queue to the Recevie Virtual to Physical state machine */ 10069 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10070 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10071 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10072 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10073 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10074 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10075 cmd, ctl, cur_depth, max_depth, valid_cnt); 10076 10077 /* Input queue to the Receive Virtual to Physical state machine */ 10078 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10079 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10080 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10081 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10082 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10083 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10084 cmd, ctl, cur_depth, max_depth, valid_cnt); 10085 10086 /* Input queue to the Receive DMA state machine */ 10087 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10088 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10089 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10090 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10091 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10092 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10093 cmd, ctl, cur_depth, max_depth, valid_cnt); 10094 10095 /* Input queue to the Transmit Scheduler state machine */ 10096 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10097 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10098 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10099 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10100 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10101 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10102 cmd, ctl, cur_depth, max_depth, valid_cnt); 10103 10104 /* Input queue to the Transmit Buffer Descriptor state machine */ 10105 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10106 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10107 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10108 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10109 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10110 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10111 cmd, ctl, cur_depth, max_depth, valid_cnt); 10112 10113 /* Input queue to the Transmit Processor */ 10114 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10115 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10116 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10117 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10118 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10119 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10120 cmd, ctl, cur_depth, max_depth, valid_cnt); 10121 10122 /* Input queue to the Transmit DMA state machine */ 10123 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10124 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10125 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10126 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10127 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10128 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10129 cmd, ctl, cur_depth, max_depth, valid_cnt); 10130 10131 /* Input queue to the Transmit Patch-Up Processor */ 10132 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10133 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10134 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10135 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10136 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10137 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10138 cmd, ctl, cur_depth, max_depth, valid_cnt); 10139 10140 /* Input queue to the Transmit Assembler state machine */ 10141 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10142 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10143 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10144 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10145 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10146 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10147 cmd, ctl, cur_depth, max_depth, valid_cnt); 10148 10149 /* Input queue to the Completion Processor */ 10150 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10151 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10152 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10153 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10154 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10155 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10156 cmd, ctl, cur_depth, max_depth, valid_cnt); 10157 10158 /* Input queue to the Completion Processor */ 10159 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10160 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10161 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10162 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10163 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10164 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10165 cmd, ctl, cur_depth, max_depth, valid_cnt); 10166 10167 /* Input queue to the Completion Processor */ 10168 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10169 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10170 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10171 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10172 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10173 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10174 cmd, ctl, cur_depth, max_depth, valid_cnt); 10175 10176 /* Setup the generic statistic counters for the FTQ valid count. */ 10177 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10178 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10179 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10180 10181 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 10182 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 10183 val = val | 10184 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10185 24); 10186 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10187 10188 /* Input queue to the Management Control Processor */ 10189 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10190 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10191 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10192 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10193 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10194 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10195 cmd, ctl, cur_depth, max_depth, valid_cnt); 10196 10197 /* Input queue to the Command Processor */ 10198 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10199 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10200 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10201 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10202 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10203 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10204 cmd, ctl, cur_depth, max_depth, valid_cnt); 10205 10206 /* Input queue to the Completion Scheduler state machine */ 10207 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10208 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10209 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10210 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10211 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10212 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10213 cmd, ctl, cur_depth, max_depth, valid_cnt); 10214 10215 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 10216 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 10217 /* Input queue to the RV2P Command Scheduler */ 10218 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10219 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10220 cur_depth = (ctl & 0xFFC00000) >> 22; 10221 max_depth = (ctl & 0x003FF000) >> 12; 10222 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10223 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10224 cmd, ctl, cur_depth, max_depth, valid_cnt); 10225 } 10226 10227 BCE_PRINTF( 10228 "----------------------------" 10229 "----------------" 10230 "----------------------------\n"); 10231 } 10232 10233 10234 /****************************************************************************/ 10235 /* Prints out the TX chain. */ 10236 /* */ 10237 /* Returns: */ 10238 /* Nothing. */ 10239 /****************************************************************************/ 10240 static __attribute__ ((noinline)) void 10241 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10242 { 10243 struct tx_bd *txbd; 10244 10245 /* First some info about the tx_bd chain structure. */ 10246 BCE_PRINTF( 10247 "----------------------------" 10248 " tx_bd chain " 10249 "----------------------------\n"); 10250 10251 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10252 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10253 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10254 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10255 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10256 10257 BCE_PRINTF( 10258 "----------------------------" 10259 " tx_bd data " 10260 "----------------------------\n"); 10261 10262 /* Now print out a decoded list of TX buffer descriptors. */ 10263 for (int i = 0; i < count; i++) { 10264 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10265 bce_dump_txbd(sc, tx_prod, txbd); 10266 tx_prod++; 10267 } 10268 10269 BCE_PRINTF( 10270 "----------------------------" 10271 "----------------" 10272 "----------------------------\n"); 10273 } 10274 10275 10276 /****************************************************************************/ 10277 /* Prints out the RX chain. */ 10278 /* */ 10279 /* Returns: */ 10280 /* Nothing. */ 10281 /****************************************************************************/ 10282 static __attribute__ ((noinline)) void 10283 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10284 { 10285 struct rx_bd *rxbd; 10286 10287 /* First some info about the rx_bd chain structure. */ 10288 BCE_PRINTF( 10289 "----------------------------" 10290 " rx_bd chain " 10291 "----------------------------\n"); 10292 10293 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10294 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10295 10296 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10297 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10298 10299 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10300 10301 BCE_PRINTF( 10302 "----------------------------" 10303 " rx_bd data " 10304 "----------------------------\n"); 10305 10306 /* Now print out the rx_bd's themselves. */ 10307 for (int i = 0; i < count; i++) { 10308 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10309 bce_dump_rxbd(sc, rx_prod, rxbd); 10310 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10311 } 10312 10313 BCE_PRINTF( 10314 "----------------------------" 10315 "----------------" 10316 "----------------------------\n"); 10317 } 10318 10319 10320 /****************************************************************************/ 10321 /* Prints out the page chain. */ 10322 /* */ 10323 /* Returns: */ 10324 /* Nothing. */ 10325 /****************************************************************************/ 10326 static __attribute__ ((noinline)) void 10327 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10328 { 10329 struct rx_bd *pgbd; 10330 10331 /* First some info about the page chain structure. */ 10332 BCE_PRINTF( 10333 "----------------------------" 10334 " page chain " 10335 "----------------------------\n"); 10336 10337 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10338 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10339 10340 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10341 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10342 10343 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10344 10345 BCE_PRINTF( 10346 "----------------------------" 10347 " page data " 10348 "----------------------------\n"); 10349 10350 /* Now print out the rx_bd's themselves. */ 10351 for (int i = 0; i < count; i++) { 10352 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10353 bce_dump_pgbd(sc, pg_prod, pgbd); 10354 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10355 } 10356 10357 BCE_PRINTF( 10358 "----------------------------" 10359 "----------------" 10360 "----------------------------\n"); 10361 } 10362 10363 10364 #define BCE_PRINT_RX_CONS(arg) \ 10365 if (sblk->status_rx_quick_consumer_index##arg) \ 10366 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10367 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10368 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10369 arg); 10370 10371 10372 #define BCE_PRINT_TX_CONS(arg) \ 10373 if (sblk->status_tx_quick_consumer_index##arg) \ 10374 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10375 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10376 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10377 arg); 10378 10379 /****************************************************************************/ 10380 /* Prints out the status block from host memory. */ 10381 /* */ 10382 /* Returns: */ 10383 /* Nothing. */ 10384 /****************************************************************************/ 10385 static __attribute__ ((noinline)) void 10386 bce_dump_status_block(struct bce_softc *sc) 10387 { 10388 struct status_block *sblk; 10389 10390 sblk = sc->status_block; 10391 10392 BCE_PRINTF( 10393 "----------------------------" 10394 " Status Block " 10395 "----------------------------\n"); 10396 10397 /* Theses indices are used for normal L2 drivers. */ 10398 BCE_PRINTF(" 0x%08X - attn_bits\n", 10399 sblk->status_attn_bits); 10400 10401 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10402 sblk->status_attn_bits_ack); 10403 10404 BCE_PRINT_RX_CONS(0); 10405 BCE_PRINT_TX_CONS(0) 10406 10407 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10408 10409 /* Theses indices are not used for normal L2 drivers. */ 10410 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10411 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10412 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10413 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10414 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10415 10416 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10417 10418 if (sblk->status_completion_producer_index || 10419 sblk->status_cmd_consumer_index) 10420 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10421 sblk->status_completion_producer_index, 10422 sblk->status_cmd_consumer_index); 10423 10424 BCE_PRINTF( 10425 "----------------------------" 10426 "----------------" 10427 "----------------------------\n"); 10428 } 10429 10430 10431 #define BCE_PRINT_64BIT_STAT(arg) \ 10432 if (sblk->arg##_lo || sblk->arg##_hi) \ 10433 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10434 sblk->arg##_lo, #arg); 10435 10436 #define BCE_PRINT_32BIT_STAT(arg) \ 10437 if (sblk->arg) \ 10438 BCE_PRINTF(" 0x%08X : %s\n", \ 10439 sblk->arg, #arg); 10440 10441 /****************************************************************************/ 10442 /* Prints out the statistics block from host memory. */ 10443 /* */ 10444 /* Returns: */ 10445 /* Nothing. */ 10446 /****************************************************************************/ 10447 static __attribute__ ((noinline)) void 10448 bce_dump_stats_block(struct bce_softc *sc) 10449 { 10450 struct statistics_block *sblk; 10451 10452 sblk = sc->stats_block; 10453 10454 BCE_PRINTF( 10455 "---------------" 10456 " Stats Block (All Stats Not Shown Are 0) " 10457 "---------------\n"); 10458 10459 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10460 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10461 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10462 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10463 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10464 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10465 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10466 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10467 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10468 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10469 BCE_PRINT_32BIT_STAT( 10470 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10471 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10472 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10473 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10474 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10475 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10476 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10477 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10478 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10479 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10480 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10481 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10482 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10483 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10484 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10485 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10486 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10487 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10488 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10489 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10490 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10491 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10492 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10493 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10494 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10495 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10496 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10497 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10498 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10499 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10500 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10501 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10502 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10503 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10504 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10505 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10506 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10507 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10508 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10509 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10510 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10511 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10512 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10513 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10514 10515 BCE_PRINTF( 10516 "----------------------------" 10517 "----------------" 10518 "----------------------------\n"); 10519 } 10520 10521 10522 /****************************************************************************/ 10523 /* Prints out a summary of the driver state. */ 10524 /* */ 10525 /* Returns: */ 10526 /* Nothing. */ 10527 /****************************************************************************/ 10528 static __attribute__ ((noinline)) void 10529 bce_dump_driver_state(struct bce_softc *sc) 10530 { 10531 u32 val_hi, val_lo; 10532 10533 BCE_PRINTF( 10534 "-----------------------------" 10535 " Driver State " 10536 "-----------------------------\n"); 10537 10538 val_hi = BCE_ADDR_HI(sc); 10539 val_lo = BCE_ADDR_LO(sc); 10540 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10541 "address\n", val_hi, val_lo); 10542 10543 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10544 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10545 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10546 "address\n", val_hi, val_lo); 10547 10548 val_hi = BCE_ADDR_HI(sc->status_block); 10549 val_lo = BCE_ADDR_LO(sc->status_block); 10550 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10551 "virtual address\n", val_hi, val_lo); 10552 10553 val_hi = BCE_ADDR_HI(sc->stats_block); 10554 val_lo = BCE_ADDR_LO(sc->stats_block); 10555 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10556 "virtual address\n", val_hi, val_lo); 10557 10558 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10559 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10560 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10561 "virtual adddress\n", val_hi, val_lo); 10562 10563 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10564 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10565 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10566 "virtual address\n", val_hi, val_lo); 10567 10568 if (bce_hdr_split == TRUE) { 10569 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10570 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10571 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10572 "virtual address\n", val_hi, val_lo); 10573 } 10574 10575 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10576 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10577 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10578 "virtual address\n", val_hi, val_lo); 10579 10580 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10581 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10582 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10583 "virtual address\n", val_hi, val_lo); 10584 10585 if (bce_hdr_split == TRUE) { 10586 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10587 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10588 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10589 "virtual address\n", val_hi, val_lo); 10590 } 10591 10592 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10593 "h/w intrs\n", 10594 (long long unsigned int) sc->interrupts_generated); 10595 10596 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10597 "rx interrupts handled\n", 10598 (long long unsigned int) sc->interrupts_rx); 10599 10600 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10601 "tx interrupts handled\n", 10602 (long long unsigned int) sc->interrupts_tx); 10603 10604 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10605 "phy interrupts handled\n", 10606 (long long unsigned int) sc->phy_interrupts); 10607 10608 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10609 "status block index\n", sc->last_status_idx); 10610 10611 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10612 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10613 10614 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10615 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10616 10617 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10618 "byte seq index\n", sc->tx_prod_bseq); 10619 10620 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10621 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10622 10623 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10624 "tx_bd's\n", sc->used_tx_bd); 10625 10626 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10627 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10628 10629 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10630 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10631 10632 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10633 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10634 10635 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10636 "byte seq index\n", sc->rx_prod_bseq); 10637 10638 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10639 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10640 10641 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10642 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10643 10644 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10645 "rx_bd's\n", sc->free_rx_bd); 10646 10647 if (bce_hdr_split == TRUE) { 10648 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10649 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10650 10651 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10652 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10653 10654 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10655 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10656 } 10657 10658 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10659 "rx_bd's\n", sc->free_pg_bd); 10660 10661 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10662 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10663 10664 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10665 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10666 10667 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10668 "bce mac flags\n", sc->bce_flags); 10669 10670 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10671 "bce phy flags\n", sc->bce_phy_flags); 10672 10673 BCE_PRINTF( 10674 "----------------------------" 10675 "----------------" 10676 "----------------------------\n"); 10677 } 10678 10679 10680 /****************************************************************************/ 10681 /* Prints out the hardware state through a summary of important register, */ 10682 /* followed by a complete register dump. */ 10683 /* */ 10684 /* Returns: */ 10685 /* Nothing. */ 10686 /****************************************************************************/ 10687 static __attribute__ ((noinline)) void 10688 bce_dump_hw_state(struct bce_softc *sc) 10689 { 10690 u32 val; 10691 10692 BCE_PRINTF( 10693 "----------------------------" 10694 " Hardware State " 10695 "----------------------------\n"); 10696 10697 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10698 10699 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10700 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10701 val, BCE_MISC_ENABLE_STATUS_BITS); 10702 10703 val = REG_RD(sc, BCE_DMA_STATUS); 10704 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10705 val, BCE_DMA_STATUS); 10706 10707 val = REG_RD(sc, BCE_CTX_STATUS); 10708 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10709 val, BCE_CTX_STATUS); 10710 10711 val = REG_RD(sc, BCE_EMAC_STATUS); 10712 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10713 val, BCE_EMAC_STATUS); 10714 10715 val = REG_RD(sc, BCE_RPM_STATUS); 10716 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10717 val, BCE_RPM_STATUS); 10718 10719 /* ToDo: Create a #define for this constant. */ 10720 val = REG_RD(sc, 0x2004); 10721 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10722 val, 0x2004); 10723 10724 val = REG_RD(sc, BCE_RV2P_STATUS); 10725 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10726 val, BCE_RV2P_STATUS); 10727 10728 /* ToDo: Create a #define for this constant. */ 10729 val = REG_RD(sc, 0x2c04); 10730 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10731 val, 0x2c04); 10732 10733 val = REG_RD(sc, BCE_TBDR_STATUS); 10734 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10735 val, BCE_TBDR_STATUS); 10736 10737 val = REG_RD(sc, BCE_TDMA_STATUS); 10738 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10739 val, BCE_TDMA_STATUS); 10740 10741 val = REG_RD(sc, BCE_HC_STATUS); 10742 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10743 val, BCE_HC_STATUS); 10744 10745 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10746 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10747 val, BCE_TXP_CPU_STATE); 10748 10749 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10750 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10751 val, BCE_TPAT_CPU_STATE); 10752 10753 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10754 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10755 val, BCE_RXP_CPU_STATE); 10756 10757 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10758 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10759 val, BCE_COM_CPU_STATE); 10760 10761 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10762 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10763 val, BCE_MCP_CPU_STATE); 10764 10765 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10766 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10767 val, BCE_CP_CPU_STATE); 10768 10769 BCE_PRINTF( 10770 "----------------------------" 10771 "----------------" 10772 "----------------------------\n"); 10773 10774 BCE_PRINTF( 10775 "----------------------------" 10776 " Register Dump " 10777 "----------------------------\n"); 10778 10779 for (int i = 0x400; i < 0x8000; i += 0x10) { 10780 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10781 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10782 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10783 } 10784 10785 BCE_PRINTF( 10786 "----------------------------" 10787 "----------------" 10788 "----------------------------\n"); 10789 } 10790 10791 10792 /****************************************************************************/ 10793 /* Prints out the contentst of shared memory which is used for host driver */ 10794 /* to bootcode firmware communication. */ 10795 /* */ 10796 /* Returns: */ 10797 /* Nothing. */ 10798 /****************************************************************************/ 10799 static __attribute__ ((noinline)) void 10800 bce_dump_shmem_state(struct bce_softc *sc) 10801 { 10802 BCE_PRINTF( 10803 "----------------------------" 10804 " Hardware State " 10805 "----------------------------\n"); 10806 10807 BCE_PRINTF("0x%08X - Shared memory base address\n", 10808 sc->bce_shmem_base); 10809 BCE_PRINTF("%s - bootcode version\n", 10810 sc->bce_bc_ver); 10811 10812 BCE_PRINTF( 10813 "----------------------------" 10814 " Shared Mem " 10815 "----------------------------\n"); 10816 10817 for (int i = 0x0; i < 0x200; i += 0x10) { 10818 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10819 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 10820 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 10821 } 10822 10823 BCE_PRINTF( 10824 "----------------------------" 10825 "----------------" 10826 "----------------------------\n"); 10827 } 10828 10829 10830 /****************************************************************************/ 10831 /* Prints out the mailbox queue registers. */ 10832 /* */ 10833 /* Returns: */ 10834 /* Nothing. */ 10835 /****************************************************************************/ 10836 static __attribute__ ((noinline)) void 10837 bce_dump_mq_regs(struct bce_softc *sc) 10838 { 10839 BCE_PRINTF( 10840 "----------------------------" 10841 " MQ Regs " 10842 "----------------------------\n"); 10843 10844 BCE_PRINTF( 10845 "----------------------------" 10846 "----------------" 10847 "----------------------------\n"); 10848 10849 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10850 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10851 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10852 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10853 } 10854 10855 BCE_PRINTF( 10856 "----------------------------" 10857 "----------------" 10858 "----------------------------\n"); 10859 } 10860 10861 10862 /****************************************************************************/ 10863 /* Prints out the bootcode state. */ 10864 /* */ 10865 /* Returns: */ 10866 /* Nothing. */ 10867 /****************************************************************************/ 10868 static __attribute__ ((noinline)) void 10869 bce_dump_bc_state(struct bce_softc *sc) 10870 { 10871 u32 val; 10872 10873 BCE_PRINTF( 10874 "----------------------------" 10875 " Bootcode State " 10876 "----------------------------\n"); 10877 10878 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10879 10880 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10881 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10882 val, BCE_BC_RESET_TYPE); 10883 10884 val = bce_shmem_rd(sc, BCE_BC_STATE); 10885 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10886 val, BCE_BC_STATE); 10887 10888 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10889 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10890 val, BCE_BC_STATE_CONDITION); 10891 10892 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10893 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10894 val, BCE_BC_STATE_DEBUG_CMD); 10895 10896 BCE_PRINTF( 10897 "----------------------------" 10898 "----------------" 10899 "----------------------------\n"); 10900 } 10901 10902 10903 /****************************************************************************/ 10904 /* Prints out the TXP processor state. */ 10905 /* */ 10906 /* Returns: */ 10907 /* Nothing. */ 10908 /****************************************************************************/ 10909 static __attribute__ ((noinline)) void 10910 bce_dump_txp_state(struct bce_softc *sc, int regs) 10911 { 10912 u32 val; 10913 u32 fw_version[3]; 10914 10915 BCE_PRINTF( 10916 "----------------------------" 10917 " TXP State " 10918 "----------------------------\n"); 10919 10920 for (int i = 0; i < 3; i++) 10921 fw_version[i] = htonl(REG_RD_IND(sc, 10922 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10923 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10924 10925 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10926 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 10927 val, BCE_TXP_CPU_MODE); 10928 10929 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10930 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10931 val, BCE_TXP_CPU_STATE); 10932 10933 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10934 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 10935 val, BCE_TXP_CPU_EVENT_MASK); 10936 10937 if (regs) { 10938 BCE_PRINTF( 10939 "----------------------------" 10940 " Register Dump " 10941 "----------------------------\n"); 10942 10943 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10944 /* Skip the big blank spaces */ 10945 if (i < 0x454000 && i > 0x5ffff) 10946 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10947 "0x%08X 0x%08X\n", i, 10948 REG_RD_IND(sc, i), 10949 REG_RD_IND(sc, i + 0x4), 10950 REG_RD_IND(sc, i + 0x8), 10951 REG_RD_IND(sc, i + 0xC)); 10952 } 10953 } 10954 10955 BCE_PRINTF( 10956 "----------------------------" 10957 "----------------" 10958 "----------------------------\n"); 10959 } 10960 10961 10962 /****************************************************************************/ 10963 /* Prints out the RXP processor state. */ 10964 /* */ 10965 /* Returns: */ 10966 /* Nothing. */ 10967 /****************************************************************************/ 10968 static __attribute__ ((noinline)) void 10969 bce_dump_rxp_state(struct bce_softc *sc, int regs) 10970 { 10971 u32 val; 10972 u32 fw_version[3]; 10973 10974 BCE_PRINTF( 10975 "----------------------------" 10976 " RXP State " 10977 "----------------------------\n"); 10978 10979 for (int i = 0; i < 3; i++) 10980 fw_version[i] = htonl(REG_RD_IND(sc, 10981 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10982 10983 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10984 10985 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10986 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 10987 val, BCE_RXP_CPU_MODE); 10988 10989 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10990 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10991 val, BCE_RXP_CPU_STATE); 10992 10993 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10994 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 10995 val, BCE_RXP_CPU_EVENT_MASK); 10996 10997 if (regs) { 10998 BCE_PRINTF( 10999 "----------------------------" 11000 " Register Dump " 11001 "----------------------------\n"); 11002 11003 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11004 /* Skip the big blank sapces */ 11005 if (i < 0xc5400 && i > 0xdffff) 11006 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11007 "0x%08X 0x%08X\n", i, 11008 REG_RD_IND(sc, i), 11009 REG_RD_IND(sc, i + 0x4), 11010 REG_RD_IND(sc, i + 0x8), 11011 REG_RD_IND(sc, i + 0xC)); 11012 } 11013 } 11014 11015 BCE_PRINTF( 11016 "----------------------------" 11017 "----------------" 11018 "----------------------------\n"); 11019 } 11020 11021 11022 /****************************************************************************/ 11023 /* Prints out the TPAT processor state. */ 11024 /* */ 11025 /* Returns: */ 11026 /* Nothing. */ 11027 /****************************************************************************/ 11028 static __attribute__ ((noinline)) void 11029 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11030 { 11031 u32 val; 11032 u32 fw_version[3]; 11033 11034 BCE_PRINTF( 11035 "----------------------------" 11036 " TPAT State " 11037 "----------------------------\n"); 11038 11039 for (int i = 0; i < 3; i++) 11040 fw_version[i] = htonl(REG_RD_IND(sc, 11041 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11042 11043 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11044 11045 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11046 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11047 val, BCE_TPAT_CPU_MODE); 11048 11049 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11050 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11051 val, BCE_TPAT_CPU_STATE); 11052 11053 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11054 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11055 val, BCE_TPAT_CPU_EVENT_MASK); 11056 11057 if (regs) { 11058 BCE_PRINTF( 11059 "----------------------------" 11060 " Register Dump " 11061 "----------------------------\n"); 11062 11063 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11064 /* Skip the big blank spaces */ 11065 if (i < 0x854000 && i > 0x9ffff) 11066 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11067 "0x%08X 0x%08X\n", i, 11068 REG_RD_IND(sc, i), 11069 REG_RD_IND(sc, i + 0x4), 11070 REG_RD_IND(sc, i + 0x8), 11071 REG_RD_IND(sc, i + 0xC)); 11072 } 11073 } 11074 11075 BCE_PRINTF( 11076 "----------------------------" 11077 "----------------" 11078 "----------------------------\n"); 11079 } 11080 11081 11082 /****************************************************************************/ 11083 /* Prints out the Command Procesor (CP) state. */ 11084 /* */ 11085 /* Returns: */ 11086 /* Nothing. */ 11087 /****************************************************************************/ 11088 static __attribute__ ((noinline)) void 11089 bce_dump_cp_state(struct bce_softc *sc, int regs) 11090 { 11091 u32 val; 11092 u32 fw_version[3]; 11093 11094 BCE_PRINTF( 11095 "----------------------------" 11096 " CP State " 11097 "----------------------------\n"); 11098 11099 for (int i = 0; i < 3; i++) 11100 fw_version[i] = htonl(REG_RD_IND(sc, 11101 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11102 11103 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11104 11105 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11106 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11107 val, BCE_CP_CPU_MODE); 11108 11109 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11110 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11111 val, BCE_CP_CPU_STATE); 11112 11113 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11114 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11115 BCE_CP_CPU_EVENT_MASK); 11116 11117 if (regs) { 11118 BCE_PRINTF( 11119 "----------------------------" 11120 " Register Dump " 11121 "----------------------------\n"); 11122 11123 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11124 /* Skip the big blank spaces */ 11125 if (i < 0x185400 && i > 0x19ffff) 11126 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11127 "0x%08X 0x%08X\n", i, 11128 REG_RD_IND(sc, i), 11129 REG_RD_IND(sc, i + 0x4), 11130 REG_RD_IND(sc, i + 0x8), 11131 REG_RD_IND(sc, i + 0xC)); 11132 } 11133 } 11134 11135 BCE_PRINTF( 11136 "----------------------------" 11137 "----------------" 11138 "----------------------------\n"); 11139 } 11140 11141 11142 /****************************************************************************/ 11143 /* Prints out the Completion Procesor (COM) state. */ 11144 /* */ 11145 /* Returns: */ 11146 /* Nothing. */ 11147 /****************************************************************************/ 11148 static __attribute__ ((noinline)) void 11149 bce_dump_com_state(struct bce_softc *sc, int regs) 11150 { 11151 u32 val; 11152 u32 fw_version[4]; 11153 11154 BCE_PRINTF( 11155 "----------------------------" 11156 " COM State " 11157 "----------------------------\n"); 11158 11159 for (int i = 0; i < 3; i++) 11160 fw_version[i] = htonl(REG_RD_IND(sc, 11161 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11162 11163 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11164 11165 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11166 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11167 val, BCE_COM_CPU_MODE); 11168 11169 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11170 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11171 val, BCE_COM_CPU_STATE); 11172 11173 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11174 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11175 BCE_COM_CPU_EVENT_MASK); 11176 11177 if (regs) { 11178 BCE_PRINTF( 11179 "----------------------------" 11180 " Register Dump " 11181 "----------------------------\n"); 11182 11183 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11184 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11185 "0x%08X 0x%08X\n", i, 11186 REG_RD_IND(sc, i), 11187 REG_RD_IND(sc, i + 0x4), 11188 REG_RD_IND(sc, i + 0x8), 11189 REG_RD_IND(sc, i + 0xC)); 11190 } 11191 } 11192 11193 BCE_PRINTF( 11194 "----------------------------" 11195 "----------------" 11196 "----------------------------\n"); 11197 } 11198 11199 11200 /****************************************************************************/ 11201 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11202 /* */ 11203 /* Returns: */ 11204 /* Nothing. */ 11205 /****************************************************************************/ 11206 static __attribute__ ((noinline)) void 11207 bce_dump_rv2p_state(struct bce_softc *sc) 11208 { 11209 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11210 11211 BCE_PRINTF( 11212 "----------------------------" 11213 " RV2P State " 11214 "----------------------------\n"); 11215 11216 /* Stall the RV2P processors. */ 11217 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11218 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11219 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11220 11221 /* Read the firmware version. */ 11222 val = 0x00000001; 11223 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11224 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11225 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11226 BCE_RV2P_INSTR_HIGH_HIGH; 11227 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11228 fw_ver_high, fw_ver_low); 11229 11230 val = 0x00000001; 11231 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11232 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11233 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11234 BCE_RV2P_INSTR_HIGH_HIGH; 11235 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11236 fw_ver_high, fw_ver_low); 11237 11238 /* Resume the RV2P processors. */ 11239 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11240 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11241 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11242 11243 /* Fetch the program counter value. */ 11244 val = 0x68007800; 11245 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11246 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11247 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11248 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11249 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11250 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11251 11252 /* Fetch the program counter value again to see if it is advancing. */ 11253 val = 0x68007800; 11254 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11255 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11256 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11257 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11258 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11259 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11260 11261 BCE_PRINTF( 11262 "----------------------------" 11263 "----------------" 11264 "----------------------------\n"); 11265 } 11266 11267 11268 /****************************************************************************/ 11269 /* Prints out the driver state and then enters the debugger. */ 11270 /* */ 11271 /* Returns: */ 11272 /* Nothing. */ 11273 /****************************************************************************/ 11274 static __attribute__ ((noinline)) void 11275 bce_breakpoint(struct bce_softc *sc) 11276 { 11277 11278 /* 11279 * Unreachable code to silence compiler warnings 11280 * about unused functions. 11281 */ 11282 if (0) { 11283 bce_freeze_controller(sc); 11284 bce_unfreeze_controller(sc); 11285 bce_dump_enet(sc, NULL); 11286 bce_dump_txbd(sc, 0, NULL); 11287 bce_dump_rxbd(sc, 0, NULL); 11288 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11289 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11290 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11291 bce_dump_l2fhdr(sc, 0, NULL); 11292 bce_dump_ctx(sc, RX_CID); 11293 bce_dump_ftqs(sc); 11294 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11295 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11296 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11297 bce_dump_status_block(sc); 11298 bce_dump_stats_block(sc); 11299 bce_dump_driver_state(sc); 11300 bce_dump_hw_state(sc); 11301 bce_dump_bc_state(sc); 11302 bce_dump_txp_state(sc, 0); 11303 bce_dump_rxp_state(sc, 0); 11304 bce_dump_tpat_state(sc, 0); 11305 bce_dump_cp_state(sc, 0); 11306 bce_dump_com_state(sc, 0); 11307 bce_dump_rv2p_state(sc); 11308 bce_dump_pgbd(sc, 0, NULL); 11309 } 11310 11311 bce_dump_status_block(sc); 11312 bce_dump_driver_state(sc); 11313 11314 /* Call the debugger. */ 11315 breakpoint(); 11316 11317 return; 11318 } 11319 #endif 11320 11321