1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2014 QLogic Corporation 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 /* 31 * The following controllers are supported by this driver: 32 * BCM5706C A2, A3 33 * BCM5706S A2, A3 34 * BCM5708C B1, B2 35 * BCM5708S B1, B2 36 * BCM5709C A1, C0 37 * BCM5709S A1, C0 38 * BCM5716C C0 39 * BCM5716S C0 40 * 41 * The following controllers are not supported by this driver: 42 * BCM5706C A0, A1 (pre-production) 43 * BCM5706S A0, A1 (pre-production) 44 * BCM5708C A0, B0 (pre-production) 45 * BCM5708S A0, B0 (pre-production) 46 * BCM5709C A0 B0, B1, B2 (pre-production) 47 * BCM5709S A0, B0, B1, B2 (pre-production) 48 */ 49 50 #include "opt_bce.h" 51 52 #include <sys/param.h> 53 #include <sys/endian.h> 54 #include <sys/systm.h> 55 #include <sys/sockio.h> 56 #include <sys/lock.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/mutex.h> 60 #include <sys/kernel.h> 61 #include <sys/module.h> 62 #include <sys/socket.h> 63 #include <sys/sysctl.h> 64 #include <sys/queue.h> 65 66 #include <net/bpf.h> 67 #include <net/ethernet.h> 68 #include <net/if.h> 69 #include <net/if_var.h> 70 #include <net/if_arp.h> 71 #include <net/if_dl.h> 72 #include <net/if_media.h> 73 74 #include <net/if_types.h> 75 #include <net/if_vlan_var.h> 76 77 #include <netinet/in_systm.h> 78 #include <netinet/in.h> 79 #include <netinet/if_ether.h> 80 #include <netinet/ip.h> 81 #include <netinet/ip6.h> 82 #include <netinet/tcp.h> 83 #include <netinet/udp.h> 84 85 #include <machine/bus.h> 86 #include <machine/resource.h> 87 #include <sys/bus.h> 88 #include <sys/rman.h> 89 90 #include <dev/mii/mii.h> 91 #include <dev/mii/miivar.h> 92 #include "miidevs.h" 93 #include <dev/mii/brgphyreg.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 98 #include "miibus_if.h" 99 100 #include <dev/bce/if_bcereg.h> 101 #include <dev/bce/if_bcefw.h> 102 103 /****************************************************************************/ 104 /* BCE Debug Options */ 105 /****************************************************************************/ 106 #ifdef BCE_DEBUG 107 u32 bce_debug = BCE_WARN; 108 109 /* 0 = Never */ 110 /* 1 = 1 in 2,147,483,648 */ 111 /* 256 = 1 in 8,388,608 */ 112 /* 2048 = 1 in 1,048,576 */ 113 /* 65536 = 1 in 32,768 */ 114 /* 1048576 = 1 in 2,048 */ 115 /* 268435456 = 1 in 8 */ 116 /* 536870912 = 1 in 4 */ 117 /* 1073741824 = 1 in 2 */ 118 119 /* Controls how often the l2_fhdr frame error check will fail. */ 120 int l2fhdr_error_sim_control = 0; 121 122 /* Controls how often the unexpected attention check will fail. */ 123 int unexpected_attention_sim_control = 0; 124 125 /* Controls how often to simulate an mbuf allocation failure. */ 126 int mbuf_alloc_failed_sim_control = 0; 127 128 /* Controls how often to simulate a DMA mapping failure. */ 129 int dma_map_addr_failed_sim_control = 0; 130 131 /* Controls how often to simulate a bootcode failure. */ 132 int bootcode_running_failure_sim_control = 0; 133 #endif 134 135 /****************************************************************************/ 136 /* PCI Device ID Table */ 137 /* */ 138 /* Used by bce_probe() to identify the devices supported by this driver. */ 139 /****************************************************************************/ 140 #define BCE_DEVDESC_MAX 64 141 142 static const struct bce_type bce_devs[] = { 143 /* BCM5706C Controllers and OEM boards. */ 144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 145 "HP NC370T Multifunction Gigabit Server Adapter" }, 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 147 "HP NC370i Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 151 "HP NC371i Multifunction Gigabit Server Adapter" }, 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 153 "QLogic NetXtreme II BCM5706 1000Base-T" }, 154 155 /* BCM5706S controllers and OEM boards. */ 156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 157 "HP NC370F Multifunction Gigabit Server Adapter" }, 158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 159 "QLogic NetXtreme II BCM5706 1000Base-SX" }, 160 161 /* BCM5708C controllers and OEM boards. */ 162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 163 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 165 "HP NC373i Multifunction Gigabit Server Adapter" }, 166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 167 "HP NC374m PCIe Multifunction Adapter" }, 168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 169 "QLogic NetXtreme II BCM5708 1000Base-T" }, 170 171 /* BCM5708S controllers and OEM boards. */ 172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 173 "HP NC373m Multifunction Gigabit Server Adapter" }, 174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 175 "HP NC373i Multifunction Gigabit Server Adapter" }, 176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 177 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 179 "QLogic NetXtreme II BCM5708 1000Base-SX" }, 180 181 /* BCM5709C controllers and OEM boards. */ 182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 183 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 187 "QLogic NetXtreme II BCM5709 1000Base-T" }, 188 189 /* BCM5709S controllers and OEM boards. */ 190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 193 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 195 "QLogic NetXtreme II BCM5709 1000Base-SX" }, 196 197 /* BCM5716 controllers and OEM boards. */ 198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 199 "QLogic NetXtreme II BCM5716 1000Base-T" }, 200 { 0, 0, 0, 0, NULL } 201 }; 202 203 /****************************************************************************/ 204 /* Supported Flash NVRAM device data. */ 205 /****************************************************************************/ 206 static const struct flash_spec flash_table[] = 207 { 208 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 209 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 210 211 /* Slow EEPROM */ 212 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 213 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 214 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 215 "EEPROM - slow"}, 216 /* Expansion entry 0001 */ 217 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 220 "Entry 0001"}, 221 /* Saifun SA25F010 (non-buffered flash) */ 222 /* strap, cfg1, & write1 need updates */ 223 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 226 "Non-buffered flash (128kB)"}, 227 /* Saifun SA25F020 (non-buffered flash) */ 228 /* strap, cfg1, & write1 need updates */ 229 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 230 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 231 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 232 "Non-buffered flash (256kB)"}, 233 /* Expansion entry 0100 */ 234 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 235 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 236 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 237 "Entry 0100"}, 238 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 239 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 240 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 241 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 242 "Entry 0101: ST M45PE10 (128kB non-buffered)"}, 243 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 244 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 245 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 246 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 247 "Entry 0110: ST M45PE20 (256kB non-buffered)"}, 248 /* Saifun SA25F005 (non-buffered flash) */ 249 /* strap, cfg1, & write1 need updates */ 250 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 251 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 252 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 253 "Non-buffered flash (64kB)"}, 254 /* Fast EEPROM */ 255 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 256 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 257 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 258 "EEPROM - fast"}, 259 /* Expansion entry 1001 */ 260 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 261 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 262 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 263 "Entry 1001"}, 264 /* Expansion entry 1010 */ 265 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 266 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 267 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 268 "Entry 1010"}, 269 /* ATMEL AT45DB011B (buffered flash) */ 270 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 271 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 272 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 273 "Buffered flash (128kB)"}, 274 /* Expansion entry 1100 */ 275 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 276 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 277 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 278 "Entry 1100"}, 279 /* Expansion entry 1101 */ 280 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 281 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 282 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 283 "Entry 1101"}, 284 /* Ateml Expansion entry 1110 */ 285 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 286 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 287 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 288 "Entry 1110 (Atmel)"}, 289 /* ATMEL AT45DB021B (buffered flash) */ 290 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 291 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 292 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 293 "Buffered flash (256kB)"}, 294 }; 295 296 /* 297 * The BCM5709 controllers transparently handle the 298 * differences between Atmel 264 byte pages and all 299 * flash devices which use 256 byte pages, so no 300 * logical-to-physical mapping is required in the 301 * driver. 302 */ 303 static const struct flash_spec flash_5709 = { 304 .flags = BCE_NV_BUFFERED, 305 .page_bits = BCM5709_FLASH_PAGE_BITS, 306 .page_size = BCM5709_FLASH_PAGE_SIZE, 307 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 308 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 309 .name = "5709/5716 buffered flash (256kB)", 310 }; 311 312 /****************************************************************************/ 313 /* FreeBSD device entry points. */ 314 /****************************************************************************/ 315 static int bce_probe (device_t); 316 static int bce_attach (device_t); 317 static int bce_detach (device_t); 318 static int bce_shutdown (device_t); 319 320 /****************************************************************************/ 321 /* BCE Debug Data Structure Dump Routines */ 322 /****************************************************************************/ 323 #ifdef BCE_DEBUG 324 static u32 bce_reg_rd (struct bce_softc *, u32); 325 static void bce_reg_wr (struct bce_softc *, u32, u32); 326 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 327 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 328 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 329 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 330 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 331 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 332 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 333 static void bce_dump_txbd (struct bce_softc *, 334 int, struct tx_bd *); 335 static void bce_dump_rxbd (struct bce_softc *, 336 int, struct rx_bd *); 337 static void bce_dump_pgbd (struct bce_softc *, 338 int, struct rx_bd *); 339 static void bce_dump_l2fhdr (struct bce_softc *, 340 int, struct l2_fhdr *); 341 static void bce_dump_ctx (struct bce_softc *, u16); 342 static void bce_dump_ftqs (struct bce_softc *); 343 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 344 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 345 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 346 static void bce_dump_status_block (struct bce_softc *); 347 static void bce_dump_stats_block (struct bce_softc *); 348 static void bce_dump_driver_state (struct bce_softc *); 349 static void bce_dump_hw_state (struct bce_softc *); 350 static void bce_dump_shmem_state (struct bce_softc *); 351 static void bce_dump_mq_regs (struct bce_softc *); 352 static void bce_dump_bc_state (struct bce_softc *); 353 static void bce_dump_txp_state (struct bce_softc *, int); 354 static void bce_dump_rxp_state (struct bce_softc *, int); 355 static void bce_dump_tpat_state (struct bce_softc *, int); 356 static void bce_dump_cp_state (struct bce_softc *, int); 357 static void bce_dump_com_state (struct bce_softc *, int); 358 static void bce_dump_rv2p_state (struct bce_softc *); 359 static void bce_breakpoint (struct bce_softc *); 360 #endif /*BCE_DEBUG */ 361 362 /****************************************************************************/ 363 /* BCE Register/Memory Access Routines */ 364 /****************************************************************************/ 365 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 366 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 367 static void bce_shmem_wr (struct bce_softc *, u32, u32); 368 static u32 bce_shmem_rd (struct bce_softc *, u32); 369 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 370 static int bce_miibus_read_reg (device_t, int, int); 371 static int bce_miibus_write_reg (device_t, int, int, int); 372 static void bce_miibus_statchg (device_t); 373 374 #ifdef BCE_DEBUG 375 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 376 #ifdef BCE_NVRAM_WRITE_SUPPORT 377 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 378 #endif 379 #endif 380 381 /****************************************************************************/ 382 /* BCE NVRAM Access Routines */ 383 /****************************************************************************/ 384 static int bce_acquire_nvram_lock (struct bce_softc *); 385 static int bce_release_nvram_lock (struct bce_softc *); 386 static void bce_enable_nvram_access(struct bce_softc *); 387 static void bce_disable_nvram_access(struct bce_softc *); 388 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 389 static int bce_init_nvram (struct bce_softc *); 390 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 391 static int bce_nvram_test (struct bce_softc *); 392 #ifdef BCE_NVRAM_WRITE_SUPPORT 393 static int bce_enable_nvram_write (struct bce_softc *); 394 static void bce_disable_nvram_write(struct bce_softc *); 395 static int bce_nvram_erase_page (struct bce_softc *, u32); 396 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 397 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 398 #endif 399 400 /****************************************************************************/ 401 /* */ 402 /****************************************************************************/ 403 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 404 static void bce_get_media (struct bce_softc *); 405 static void bce_init_media (struct bce_softc *); 406 static u32 bce_get_rphy_link (struct bce_softc *); 407 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 408 static int bce_dma_alloc (device_t); 409 static void bce_dma_free (struct bce_softc *); 410 static void bce_release_resources (struct bce_softc *); 411 412 /****************************************************************************/ 413 /* BCE Firmware Synchronization and Load */ 414 /****************************************************************************/ 415 static void bce_fw_cap_init (struct bce_softc *); 416 static int bce_fw_sync (struct bce_softc *, u32); 417 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 418 u32); 419 static void bce_load_cpu_fw (struct bce_softc *, 420 struct cpu_reg *, struct fw_info *); 421 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 422 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 423 static void bce_start_rxp_cpu (struct bce_softc *); 424 static void bce_init_rxp_cpu (struct bce_softc *); 425 static void bce_init_txp_cpu (struct bce_softc *); 426 static void bce_init_tpat_cpu (struct bce_softc *); 427 static void bce_init_cp_cpu (struct bce_softc *); 428 static void bce_init_com_cpu (struct bce_softc *); 429 static void bce_init_cpus (struct bce_softc *); 430 431 static void bce_print_adapter_info (struct bce_softc *); 432 static void bce_probe_pci_caps (device_t, struct bce_softc *); 433 static void bce_stop (struct bce_softc *); 434 static int bce_reset (struct bce_softc *, u32); 435 static int bce_chipinit (struct bce_softc *); 436 static int bce_blockinit (struct bce_softc *); 437 438 static int bce_init_tx_chain (struct bce_softc *); 439 static void bce_free_tx_chain (struct bce_softc *); 440 441 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 442 static int bce_init_rx_chain (struct bce_softc *); 443 static void bce_fill_rx_chain (struct bce_softc *); 444 static void bce_free_rx_chain (struct bce_softc *); 445 446 static int bce_get_pg_buf (struct bce_softc *, u16, u16); 447 static int bce_init_pg_chain (struct bce_softc *); 448 static void bce_fill_pg_chain (struct bce_softc *); 449 static void bce_free_pg_chain (struct bce_softc *); 450 451 static struct mbuf *bce_tso_setup (struct bce_softc *, 452 struct mbuf **, u16 *); 453 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 454 static void bce_start_locked (if_t); 455 static void bce_start (if_t); 456 static int bce_ioctl (if_t, u_long, caddr_t); 457 static uint64_t bce_get_counter (if_t, ift_counter); 458 static void bce_watchdog (struct bce_softc *); 459 static int bce_ifmedia_upd (if_t); 460 static int bce_ifmedia_upd_locked (if_t); 461 static void bce_ifmedia_sts (if_t, struct ifmediareq *); 462 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 463 static void bce_init_locked (struct bce_softc *); 464 static void bce_init (void *); 465 static void bce_mgmt_init_locked (struct bce_softc *sc); 466 467 static int bce_init_ctx (struct bce_softc *); 468 static void bce_get_mac_addr (struct bce_softc *); 469 static void bce_set_mac_addr (struct bce_softc *); 470 static void bce_phy_intr (struct bce_softc *); 471 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 472 static void bce_rx_intr (struct bce_softc *); 473 static void bce_tx_intr (struct bce_softc *); 474 static void bce_disable_intr (struct bce_softc *); 475 static void bce_enable_intr (struct bce_softc *, int); 476 477 static void bce_intr (void *); 478 static void bce_set_rx_mode (struct bce_softc *); 479 static void bce_stats_update (struct bce_softc *); 480 static void bce_tick (void *); 481 static void bce_pulse (void *); 482 static void bce_add_sysctls (struct bce_softc *); 483 484 /****************************************************************************/ 485 /* FreeBSD device dispatch table. */ 486 /****************************************************************************/ 487 static device_method_t bce_methods[] = { 488 /* Device interface (device_if.h) */ 489 DEVMETHOD(device_probe, bce_probe), 490 DEVMETHOD(device_attach, bce_attach), 491 DEVMETHOD(device_detach, bce_detach), 492 DEVMETHOD(device_shutdown, bce_shutdown), 493 /* Supported by device interface but not used here. */ 494 /* DEVMETHOD(device_identify, bce_identify), */ 495 /* DEVMETHOD(device_suspend, bce_suspend), */ 496 /* DEVMETHOD(device_resume, bce_resume), */ 497 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 498 499 /* MII interface (miibus_if.h) */ 500 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 501 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 502 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 503 /* Supported by MII interface but not used here. */ 504 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 505 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 506 507 DEVMETHOD_END 508 }; 509 510 static driver_t bce_driver = { 511 "bce", 512 bce_methods, 513 sizeof(struct bce_softc) 514 }; 515 516 MODULE_DEPEND(bce, pci, 1, 1, 1); 517 MODULE_DEPEND(bce, ether, 1, 1, 1); 518 MODULE_DEPEND(bce, miibus, 1, 1, 1); 519 520 DRIVER_MODULE(bce, pci, bce_driver, NULL, NULL); 521 DRIVER_MODULE(miibus, bce, miibus_driver, NULL, NULL); 522 MODULE_PNP_INFO("U16:vendor;U16:device;U16:#;U16:#;D:#", pci, bce, 523 bce_devs, nitems(bce_devs) - 1); 524 525 /****************************************************************************/ 526 /* Tunable device values */ 527 /****************************************************************************/ 528 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 529 "bce driver parameters"); 530 531 /* Allowable values are TRUE or FALSE */ 532 static int bce_verbose = TRUE; 533 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 534 "Verbose output enable/disable"); 535 536 /* Allowable values are TRUE or FALSE */ 537 static int bce_tso_enable = TRUE; 538 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 539 "TSO Enable/Disable"); 540 541 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 542 /* ToDo: Add MSI-X support. */ 543 static int bce_msi_enable = 1; 544 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 545 "MSI-X|MSI|INTx selector"); 546 547 /* Allowable values are 1, 2, 4, 8. */ 548 static int bce_rx_pages = DEFAULT_RX_PAGES; 549 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 550 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 551 552 /* Allowable values are 1, 2, 4, 8. */ 553 static int bce_tx_pages = DEFAULT_TX_PAGES; 554 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 555 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 556 557 /* Allowable values are TRUE or FALSE. */ 558 static int bce_hdr_split = TRUE; 559 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 560 "Frame header/payload splitting Enable/Disable"); 561 562 /* Allowable values are TRUE or FALSE. */ 563 static int bce_strict_rx_mtu = FALSE; 564 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 565 &bce_strict_rx_mtu, 0, 566 "Enable/Disable strict RX frame size checking"); 567 568 /* Allowable values are 0 ... 100 */ 569 #ifdef BCE_DEBUG 570 /* Generate 1 interrupt for every transmit completion. */ 571 static int bce_tx_quick_cons_trip_int = 1; 572 #else 573 /* Generate 1 interrupt for every 20 transmit completions. */ 574 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 575 #endif 576 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 577 &bce_tx_quick_cons_trip_int, 0, 578 "Transmit BD trip point during interrupts"); 579 580 /* Allowable values are 0 ... 100 */ 581 /* Generate 1 interrupt for every transmit completion. */ 582 #ifdef BCE_DEBUG 583 static int bce_tx_quick_cons_trip = 1; 584 #else 585 /* Generate 1 interrupt for every 20 transmit completions. */ 586 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 587 #endif 588 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 589 &bce_tx_quick_cons_trip, 0, 590 "Transmit BD trip point"); 591 592 /* Allowable values are 0 ... 100 */ 593 #ifdef BCE_DEBUG 594 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 595 static int bce_tx_ticks_int = 0; 596 #else 597 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 598 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 599 #endif 600 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 601 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 602 603 /* Allowable values are 0 ... 100 */ 604 #ifdef BCE_DEBUG 605 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 606 static int bce_tx_ticks = 0; 607 #else 608 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 609 static int bce_tx_ticks = DEFAULT_TX_TICKS; 610 #endif 611 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 612 &bce_tx_ticks, 0, "Transmit ticks count"); 613 614 /* Allowable values are 1 ... 100 */ 615 #ifdef BCE_DEBUG 616 /* Generate 1 interrupt for every received frame. */ 617 static int bce_rx_quick_cons_trip_int = 1; 618 #else 619 /* Generate 1 interrupt for every 6 received frames. */ 620 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 621 #endif 622 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 623 &bce_rx_quick_cons_trip_int, 0, 624 "Receive BD trip point during interrupts"); 625 626 /* Allowable values are 1 ... 100 */ 627 #ifdef BCE_DEBUG 628 /* Generate 1 interrupt for every received frame. */ 629 static int bce_rx_quick_cons_trip = 1; 630 #else 631 /* Generate 1 interrupt for every 6 received frames. */ 632 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 633 #endif 634 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 635 &bce_rx_quick_cons_trip, 0, 636 "Receive BD trip point"); 637 638 /* Allowable values are 0 ... 100 */ 639 #ifdef BCE_DEBUG 640 /* Generate an int. if 0us have elapsed since the last received frame. */ 641 static int bce_rx_ticks_int = 0; 642 #else 643 /* Generate an int. if 18us have elapsed since the last received frame. */ 644 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 645 #endif 646 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 647 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 648 649 /* Allowable values are 0 ... 100 */ 650 #ifdef BCE_DEBUG 651 /* Generate an int. if 0us have elapsed since the last received frame. */ 652 static int bce_rx_ticks = 0; 653 #else 654 /* Generate an int. if 18us have elapsed since the last received frame. */ 655 static int bce_rx_ticks = DEFAULT_RX_TICKS; 656 #endif 657 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 658 &bce_rx_ticks, 0, "Receive ticks count"); 659 660 /****************************************************************************/ 661 /* Device probe function. */ 662 /* */ 663 /* Compares the device to the driver's list of supported devices and */ 664 /* reports back to the OS whether this is the right driver for the device. */ 665 /* */ 666 /* Returns: */ 667 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 668 /****************************************************************************/ 669 static int 670 bce_probe(device_t dev) 671 { 672 const struct bce_type *t; 673 struct bce_softc *sc; 674 u16 vid = 0, did = 0, svid = 0, sdid = 0; 675 676 t = bce_devs; 677 678 sc = device_get_softc(dev); 679 sc->bce_unit = device_get_unit(dev); 680 sc->bce_dev = dev; 681 682 /* Get the data for the device to be probed. */ 683 vid = pci_get_vendor(dev); 684 did = pci_get_device(dev); 685 svid = pci_get_subvendor(dev); 686 sdid = pci_get_subdevice(dev); 687 688 DBPRINT(sc, BCE_EXTREME_LOAD, 689 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 690 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 691 692 /* Look through the list of known devices for a match. */ 693 while(t->bce_name != NULL) { 694 if ((vid == t->bce_vid) && (did == t->bce_did) && 695 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 696 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 697 device_set_descf(dev, "%s (%c%d)", 698 t->bce_name, (((pci_read_config(dev, 699 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 700 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 701 return(BUS_PROBE_DEFAULT); 702 } 703 t++; 704 } 705 706 return(ENXIO); 707 } 708 709 /****************************************************************************/ 710 /* PCI Capabilities Probe Function. */ 711 /* */ 712 /* Walks the PCI capabiites list for the device to find what features are */ 713 /* supported. */ 714 /* */ 715 /* Returns: */ 716 /* None. */ 717 /****************************************************************************/ 718 static void 719 bce_print_adapter_info(struct bce_softc *sc) 720 { 721 int i = 0; 722 723 DBENTER(BCE_VERBOSE_LOAD); 724 725 if (bce_verbose || bootverbose) { 726 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 727 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 728 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 729 730 /* Bus info. */ 731 if (sc->bce_flags & BCE_PCIE_FLAG) { 732 printf("Bus (PCIe x%d, ", sc->link_width); 733 switch (sc->link_speed) { 734 case 1: printf("2.5Gbps); "); break; 735 case 2: printf("5Gbps); "); break; 736 default: printf("Unknown link speed); "); 737 } 738 } else { 739 printf("Bus (PCI%s, %s, %dMHz); ", 740 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 741 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 742 "32-bit" : "64-bit"), sc->bus_speed_mhz); 743 } 744 745 /* Firmware version and device features. */ 746 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 747 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 748 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 749 750 if (bce_hdr_split == TRUE) { 751 printf("SPLT"); 752 i++; 753 } 754 755 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 756 if (i > 0) printf("|"); 757 printf("MSI"); i++; 758 } 759 760 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 761 if (i > 0) printf("|"); 762 printf("MSI-X"); i++; 763 } 764 765 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 766 if (i > 0) printf("|"); 767 printf("2.5G"); i++; 768 } 769 770 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 771 if (i > 0) printf("|"); 772 printf("Remote PHY(%s)", 773 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 774 "FIBER" : "TP"); i++; 775 } 776 777 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 778 if (i > 0) printf("|"); 779 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 780 } else { 781 printf(")\n"); 782 } 783 784 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 785 sc->bce_rx_quick_cons_trip_int, 786 sc->bce_rx_quick_cons_trip, 787 sc->bce_rx_ticks_int, 788 sc->bce_rx_ticks, 789 sc->bce_tx_quick_cons_trip_int, 790 sc->bce_tx_quick_cons_trip, 791 sc->bce_tx_ticks_int, 792 sc->bce_tx_ticks); 793 } 794 795 DBEXIT(BCE_VERBOSE_LOAD); 796 } 797 798 /****************************************************************************/ 799 /* PCI Capabilities Probe Function. */ 800 /* */ 801 /* Walks the PCI capabiites list for the device to find what features are */ 802 /* supported. */ 803 /* */ 804 /* Returns: */ 805 /* None. */ 806 /****************************************************************************/ 807 static void 808 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 809 { 810 u32 reg; 811 812 DBENTER(BCE_VERBOSE_LOAD); 813 814 /* Check if PCI-X capability is enabled. */ 815 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 816 if (reg != 0) 817 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 818 } 819 820 /* Check if PCIe capability is enabled. */ 821 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 822 if (reg != 0) { 823 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 824 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 825 "0x%08X\n", link_status); 826 sc->link_speed = link_status & 0xf; 827 sc->link_width = (link_status >> 4) & 0x3f; 828 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 829 sc->bce_flags |= BCE_PCIE_FLAG; 830 } 831 } 832 833 /* Check if MSI capability is enabled. */ 834 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 835 if (reg != 0) 836 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 837 } 838 839 /* Check if MSI-X capability is enabled. */ 840 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 841 if (reg != 0) 842 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 843 } 844 845 DBEXIT(BCE_VERBOSE_LOAD); 846 } 847 848 /****************************************************************************/ 849 /* Load and validate user tunable settings. */ 850 /* */ 851 /* Returns: */ 852 /* Nothing. */ 853 /****************************************************************************/ 854 static void 855 bce_set_tunables(struct bce_softc *sc) 856 { 857 /* Set sysctl values for RX page count. */ 858 switch (bce_rx_pages) { 859 case 1: 860 /* fall-through */ 861 case 2: 862 /* fall-through */ 863 case 4: 864 /* fall-through */ 865 case 8: 866 sc->rx_pages = bce_rx_pages; 867 break; 868 default: 869 sc->rx_pages = DEFAULT_RX_PAGES; 870 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 871 "hw.bce.rx_pages! Setting default of %d.\n", 872 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 873 } 874 875 /* ToDo: Consider allowing user setting for pg_pages. */ 876 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 877 878 /* Set sysctl values for TX page count. */ 879 switch (bce_tx_pages) { 880 case 1: 881 /* fall-through */ 882 case 2: 883 /* fall-through */ 884 case 4: 885 /* fall-through */ 886 case 8: 887 sc->tx_pages = bce_tx_pages; 888 break; 889 default: 890 sc->tx_pages = DEFAULT_TX_PAGES; 891 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 892 "hw.bce.tx_pages! Setting default of %d.\n", 893 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 894 } 895 896 /* 897 * Validate the TX trip point (i.e. the number of 898 * TX completions before a status block update is 899 * generated and an interrupt is asserted. 900 */ 901 if (bce_tx_quick_cons_trip_int <= 100) { 902 sc->bce_tx_quick_cons_trip_int = 903 bce_tx_quick_cons_trip_int; 904 } else { 905 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 906 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 907 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 908 DEFAULT_TX_QUICK_CONS_TRIP_INT); 909 sc->bce_tx_quick_cons_trip_int = 910 DEFAULT_TX_QUICK_CONS_TRIP_INT; 911 } 912 913 if (bce_tx_quick_cons_trip <= 100) { 914 sc->bce_tx_quick_cons_trip = 915 bce_tx_quick_cons_trip; 916 } else { 917 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 918 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 919 __FILE__, __LINE__, bce_tx_quick_cons_trip, 920 DEFAULT_TX_QUICK_CONS_TRIP); 921 sc->bce_tx_quick_cons_trip = 922 DEFAULT_TX_QUICK_CONS_TRIP; 923 } 924 925 /* 926 * Validate the TX ticks count (i.e. the maximum amount 927 * of time to wait after the last TX completion has 928 * occurred before a status block update is generated 929 * and an interrupt is asserted. 930 */ 931 if (bce_tx_ticks_int <= 100) { 932 sc->bce_tx_ticks_int = 933 bce_tx_ticks_int; 934 } else { 935 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 936 "hw.bce.tx_ticks_int! Setting default of %d.\n", 937 __FILE__, __LINE__, bce_tx_ticks_int, 938 DEFAULT_TX_TICKS_INT); 939 sc->bce_tx_ticks_int = 940 DEFAULT_TX_TICKS_INT; 941 } 942 943 if (bce_tx_ticks <= 100) { 944 sc->bce_tx_ticks = 945 bce_tx_ticks; 946 } else { 947 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 948 "hw.bce.tx_ticks! Setting default of %d.\n", 949 __FILE__, __LINE__, bce_tx_ticks, 950 DEFAULT_TX_TICKS); 951 sc->bce_tx_ticks = 952 DEFAULT_TX_TICKS; 953 } 954 955 /* 956 * Validate the RX trip point (i.e. the number of 957 * RX frames received before a status block update is 958 * generated and an interrupt is asserted. 959 */ 960 if (bce_rx_quick_cons_trip_int <= 100) { 961 sc->bce_rx_quick_cons_trip_int = 962 bce_rx_quick_cons_trip_int; 963 } else { 964 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 965 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 966 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 967 DEFAULT_RX_QUICK_CONS_TRIP_INT); 968 sc->bce_rx_quick_cons_trip_int = 969 DEFAULT_RX_QUICK_CONS_TRIP_INT; 970 } 971 972 if (bce_rx_quick_cons_trip <= 100) { 973 sc->bce_rx_quick_cons_trip = 974 bce_rx_quick_cons_trip; 975 } else { 976 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 977 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 978 __FILE__, __LINE__, bce_rx_quick_cons_trip, 979 DEFAULT_RX_QUICK_CONS_TRIP); 980 sc->bce_rx_quick_cons_trip = 981 DEFAULT_RX_QUICK_CONS_TRIP; 982 } 983 984 /* 985 * Validate the RX ticks count (i.e. the maximum amount 986 * of time to wait after the last RX frame has been 987 * received before a status block update is generated 988 * and an interrupt is asserted. 989 */ 990 if (bce_rx_ticks_int <= 100) { 991 sc->bce_rx_ticks_int = bce_rx_ticks_int; 992 } else { 993 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 994 "hw.bce.rx_ticks_int! Setting default of %d.\n", 995 __FILE__, __LINE__, bce_rx_ticks_int, 996 DEFAULT_RX_TICKS_INT); 997 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 998 } 999 1000 if (bce_rx_ticks <= 100) { 1001 sc->bce_rx_ticks = bce_rx_ticks; 1002 } else { 1003 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1004 "hw.bce.rx_ticks! Setting default of %d.\n", 1005 __FILE__, __LINE__, bce_rx_ticks, 1006 DEFAULT_RX_TICKS); 1007 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1008 } 1009 1010 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1011 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1012 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1013 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1014 __FILE__, __LINE__); 1015 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1016 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1017 } 1018 1019 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1020 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1021 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1022 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1023 __FILE__, __LINE__); 1024 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1025 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1026 } 1027 } 1028 1029 /****************************************************************************/ 1030 /* Device attach function. */ 1031 /* */ 1032 /* Allocates device resources, performs secondary chip identification, */ 1033 /* resets and initializes the hardware, and initializes driver instance */ 1034 /* variables. */ 1035 /* */ 1036 /* Returns: */ 1037 /* 0 on success, positive value on failure. */ 1038 /****************************************************************************/ 1039 static int 1040 bce_attach(device_t dev) 1041 { 1042 struct bce_softc *sc; 1043 if_t ifp; 1044 u32 val; 1045 int count, error, rc = 0, rid; 1046 1047 sc = device_get_softc(dev); 1048 sc->bce_dev = dev; 1049 1050 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1051 1052 sc->bce_unit = device_get_unit(dev); 1053 1054 /* Set initial device and PHY flags */ 1055 sc->bce_flags = 0; 1056 sc->bce_phy_flags = 0; 1057 1058 bce_set_tunables(sc); 1059 1060 pci_enable_busmaster(dev); 1061 1062 /* Allocate PCI memory resources. */ 1063 rid = PCIR_BAR(0); 1064 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1065 &rid, RF_ACTIVE); 1066 1067 if (sc->bce_res_mem == NULL) { 1068 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1069 __FILE__, __LINE__); 1070 rc = ENXIO; 1071 goto bce_attach_fail; 1072 } 1073 1074 /* Get various resource handles. */ 1075 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1076 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1077 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1078 1079 bce_probe_pci_caps(dev, sc); 1080 1081 rid = 1; 1082 count = 0; 1083 #if 0 1084 /* Try allocating MSI-X interrupts. */ 1085 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1086 (bce_msi_enable >= 2) && 1087 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1088 &rid, RF_ACTIVE)) != NULL)) { 1089 msi_needed = count = 1; 1090 1091 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1092 (count != msi_needed)) { 1093 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1094 "Received = %d, error = %d\n", __FILE__, __LINE__, 1095 msi_needed, count, error); 1096 count = 0; 1097 pci_release_msi(dev); 1098 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1099 sc->bce_res_irq); 1100 sc->bce_res_irq = NULL; 1101 } else { 1102 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1103 __FUNCTION__); 1104 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1105 } 1106 } 1107 #endif 1108 1109 /* Try allocating a MSI interrupt. */ 1110 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1111 (bce_msi_enable >= 1) && (count == 0)) { 1112 count = 1; 1113 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1114 BCE_PRINTF("%s(%d): MSI allocation failed! " 1115 "error = %d\n", __FILE__, __LINE__, error); 1116 count = 0; 1117 pci_release_msi(dev); 1118 } else { 1119 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1120 "interrupt.\n", __FUNCTION__); 1121 sc->bce_flags |= BCE_USING_MSI_FLAG; 1122 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1123 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1124 rid = 1; 1125 } 1126 } 1127 1128 /* Try allocating a legacy interrupt. */ 1129 if (count == 0) { 1130 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1131 __FUNCTION__); 1132 rid = 0; 1133 } 1134 1135 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1136 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1137 1138 /* Report any IRQ allocation errors. */ 1139 if (sc->bce_res_irq == NULL) { 1140 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1141 __FILE__, __LINE__); 1142 rc = ENXIO; 1143 goto bce_attach_fail; 1144 } 1145 1146 /* Initialize mutex for the current device instance. */ 1147 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1148 1149 /* 1150 * Configure byte swap and enable indirect register access. 1151 * Rely on CPU to do target byte swapping on big endian systems. 1152 * Access to registers outside of PCI configurtion space are not 1153 * valid until this is done. 1154 */ 1155 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1156 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1157 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1158 1159 /* Save ASIC revsion info. */ 1160 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1161 1162 /* Weed out any non-production controller revisions. */ 1163 switch(BCE_CHIP_ID(sc)) { 1164 case BCE_CHIP_ID_5706_A0: 1165 case BCE_CHIP_ID_5706_A1: 1166 case BCE_CHIP_ID_5708_A0: 1167 case BCE_CHIP_ID_5708_B0: 1168 case BCE_CHIP_ID_5709_A0: 1169 case BCE_CHIP_ID_5709_B0: 1170 case BCE_CHIP_ID_5709_B1: 1171 case BCE_CHIP_ID_5709_B2: 1172 BCE_PRINTF("%s(%d): Unsupported controller " 1173 "revision (%c%d)!\n", __FILE__, __LINE__, 1174 (((pci_read_config(dev, PCIR_REVID, 4) & 1175 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1176 PCIR_REVID, 4) & 0xf)); 1177 rc = ENODEV; 1178 goto bce_attach_fail; 1179 } 1180 1181 /* 1182 * The embedded PCIe to PCI-X bridge (EPB) 1183 * in the 5708 cannot address memory above 1184 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1185 */ 1186 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1187 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1188 else 1189 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1190 1191 /* 1192 * Find the base address for shared memory access. 1193 * Newer versions of bootcode use a signature and offset 1194 * while older versions use a fixed address. 1195 */ 1196 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1197 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1198 /* Multi-port devices use different offsets in shared memory. */ 1199 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1200 (pci_get_function(sc->bce_dev) << 2)); 1201 else 1202 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1203 1204 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1205 __FUNCTION__, sc->bce_shmem_base); 1206 1207 /* Fetch the bootcode revision. */ 1208 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1209 for (int i = 0, j = 0; i < 3; i++) { 1210 u8 num; 1211 1212 num = (u8) (val >> (24 - (i * 8))); 1213 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1214 if (num >= k || !skip0 || k == 1) { 1215 sc->bce_bc_ver[j++] = (num / k) + '0'; 1216 skip0 = 0; 1217 } 1218 } 1219 1220 if (i != 2) 1221 sc->bce_bc_ver[j++] = '.'; 1222 } 1223 1224 /* Check if any management firwmare is enabled. */ 1225 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1226 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1227 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1228 1229 /* Allow time for firmware to enter the running state. */ 1230 for (int i = 0; i < 30; i++) { 1231 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1232 if (val & BCE_CONDITION_MFW_RUN_MASK) 1233 break; 1234 DELAY(10000); 1235 } 1236 1237 /* Check if management firmware is running. */ 1238 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1239 val &= BCE_CONDITION_MFW_RUN_MASK; 1240 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1241 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1242 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1243 int i = 0; 1244 1245 /* Read the management firmware version string. */ 1246 for (int j = 0; j < 3; j++) { 1247 val = bce_reg_rd_ind(sc, addr + j * 4); 1248 val = bswap32(val); 1249 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1250 i += 4; 1251 } 1252 } else { 1253 /* May cause firmware synchronization timeouts. */ 1254 BCE_PRINTF("%s(%d): Management firmware enabled " 1255 "but not running!\n", __FILE__, __LINE__); 1256 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1257 1258 /* ToDo: Any action the driver should take? */ 1259 } 1260 } 1261 1262 /* Get PCI bus information (speed and type). */ 1263 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1264 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1265 u32 clkreg; 1266 1267 sc->bce_flags |= BCE_PCIX_FLAG; 1268 1269 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1270 1271 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1272 switch (clkreg) { 1273 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1274 sc->bus_speed_mhz = 133; 1275 break; 1276 1277 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1278 sc->bus_speed_mhz = 100; 1279 break; 1280 1281 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1282 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1283 sc->bus_speed_mhz = 66; 1284 break; 1285 1286 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1287 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1288 sc->bus_speed_mhz = 50; 1289 break; 1290 1291 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1292 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1293 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1294 sc->bus_speed_mhz = 33; 1295 break; 1296 } 1297 } else { 1298 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1299 sc->bus_speed_mhz = 66; 1300 else 1301 sc->bus_speed_mhz = 33; 1302 } 1303 1304 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1305 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1306 1307 /* Find the media type for the adapter. */ 1308 bce_get_media(sc); 1309 1310 /* Reset controller and announce to bootcode that driver is present. */ 1311 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1312 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1313 __FILE__, __LINE__); 1314 rc = ENXIO; 1315 goto bce_attach_fail; 1316 } 1317 1318 /* Initialize the controller. */ 1319 if (bce_chipinit(sc)) { 1320 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1321 __FILE__, __LINE__); 1322 rc = ENXIO; 1323 goto bce_attach_fail; 1324 } 1325 1326 /* Perform NVRAM test. */ 1327 if (bce_nvram_test(sc)) { 1328 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1329 __FILE__, __LINE__); 1330 rc = ENXIO; 1331 goto bce_attach_fail; 1332 } 1333 1334 /* Fetch the permanent Ethernet MAC address. */ 1335 bce_get_mac_addr(sc); 1336 1337 /* Update statistics once every second. */ 1338 sc->bce_stats_ticks = 1000000 & 0xffff00; 1339 1340 /* Store data needed by PHY driver for backplane applications */ 1341 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1342 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1343 1344 /* Allocate DMA memory resources. */ 1345 if (bce_dma_alloc(dev)) { 1346 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1347 __FILE__, __LINE__); 1348 rc = ENXIO; 1349 goto bce_attach_fail; 1350 } 1351 1352 /* Allocate an ifnet structure. */ 1353 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1354 if (ifp == NULL) { 1355 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1356 __FILE__, __LINE__); 1357 rc = ENXIO; 1358 goto bce_attach_fail; 1359 } 1360 1361 /* Initialize the ifnet interface. */ 1362 if_setsoftc(ifp, sc); 1363 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1364 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1365 if_setioctlfn(ifp, bce_ioctl); 1366 if_setstartfn(ifp, bce_start); 1367 if_setgetcounterfn(ifp, bce_get_counter); 1368 if_setinitfn(ifp, bce_init); 1369 if_setmtu(ifp, ETHERMTU); 1370 1371 if (bce_tso_enable) { 1372 if_sethwassist(ifp, BCE_IF_HWASSIST | CSUM_TSO); 1373 if_setcapabilities(ifp, BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1374 IFCAP_VLAN_HWTSO); 1375 } else { 1376 if_sethwassist(ifp, BCE_IF_HWASSIST); 1377 if_setcapabilities(ifp, BCE_IF_CAPABILITIES); 1378 } 1379 1380 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1381 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE, 0); 1382 1383 if_setcapenable(ifp, if_getcapabilities(ifp)); 1384 1385 /* 1386 * Assume standard mbuf sizes for buffer allocation. 1387 * This may change later if the MTU size is set to 1388 * something other than 1500. 1389 */ 1390 bce_get_rx_buffer_sizes(sc, 1391 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1392 1393 /* Recalculate our buffer allocation sizes. */ 1394 if_setsendqlen(ifp, USABLE_TX_BD_ALLOC); 1395 if_setsendqready(ifp); 1396 1397 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1398 if_setbaudrate(ifp, IF_Mbps(2500ULL)); 1399 else 1400 if_setbaudrate(ifp, IF_Mbps(1000)); 1401 1402 /* Handle any special PHY initialization for SerDes PHYs. */ 1403 bce_init_media(sc); 1404 1405 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1406 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1407 bce_ifmedia_sts); 1408 /* 1409 * We can't manually override remote PHY's link and assume 1410 * PHY port configuration(Fiber or TP) is not changed after 1411 * device attach. This may not be correct though. 1412 */ 1413 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1414 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1415 ifmedia_add(&sc->bce_ifmedia, 1416 IFM_ETHER | IFM_2500_SX, 0, NULL); 1417 ifmedia_add(&sc->bce_ifmedia, 1418 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1419 } 1420 ifmedia_add(&sc->bce_ifmedia, 1421 IFM_ETHER | IFM_1000_SX, 0, NULL); 1422 ifmedia_add(&sc->bce_ifmedia, 1423 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1424 } else { 1425 ifmedia_add(&sc->bce_ifmedia, 1426 IFM_ETHER | IFM_10_T, 0, NULL); 1427 ifmedia_add(&sc->bce_ifmedia, 1428 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1429 ifmedia_add(&sc->bce_ifmedia, 1430 IFM_ETHER | IFM_100_TX, 0, NULL); 1431 ifmedia_add(&sc->bce_ifmedia, 1432 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1433 ifmedia_add(&sc->bce_ifmedia, 1434 IFM_ETHER | IFM_1000_T, 0, NULL); 1435 ifmedia_add(&sc->bce_ifmedia, 1436 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1437 } 1438 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1439 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1440 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1441 } else { 1442 /* MII child bus by attaching the PHY. */ 1443 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1444 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1445 MII_OFFSET_ANY, MIIF_DOPAUSE); 1446 if (rc != 0) { 1447 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1448 __LINE__); 1449 goto bce_attach_fail; 1450 } 1451 } 1452 1453 /* Attach to the Ethernet interface list. */ 1454 ether_ifattach(ifp, sc->eaddr); 1455 1456 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1457 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1458 1459 /* Hookup IRQ last. */ 1460 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1461 NULL, bce_intr, sc, &sc->bce_intrhand); 1462 1463 if (rc) { 1464 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1465 __FILE__, __LINE__); 1466 bce_detach(dev); 1467 goto bce_attach_exit; 1468 } 1469 1470 /* 1471 * At this point we've acquired all the resources 1472 * we need to run so there's no turning back, we're 1473 * cleared for launch. 1474 */ 1475 1476 /* Print some important debugging info. */ 1477 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1478 1479 /* Add the supported sysctls to the kernel. */ 1480 bce_add_sysctls(sc); 1481 1482 BCE_LOCK(sc); 1483 1484 /* 1485 * The chip reset earlier notified the bootcode that 1486 * a driver is present. We now need to start our pulse 1487 * routine so that the bootcode is reminded that we're 1488 * still running. 1489 */ 1490 bce_pulse(sc); 1491 1492 bce_mgmt_init_locked(sc); 1493 BCE_UNLOCK(sc); 1494 1495 /* Finally, print some useful adapter info */ 1496 bce_print_adapter_info(sc); 1497 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1498 __FUNCTION__, sc); 1499 1500 goto bce_attach_exit; 1501 1502 bce_attach_fail: 1503 bce_release_resources(sc); 1504 1505 bce_attach_exit: 1506 1507 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1508 1509 return(rc); 1510 } 1511 1512 /****************************************************************************/ 1513 /* Device detach function. */ 1514 /* */ 1515 /* Stops the controller, resets the controller, and releases resources. */ 1516 /* */ 1517 /* Returns: */ 1518 /* 0 on success, positive value on failure. */ 1519 /****************************************************************************/ 1520 static int 1521 bce_detach(device_t dev) 1522 { 1523 struct bce_softc *sc = device_get_softc(dev); 1524 if_t ifp; 1525 u32 msg; 1526 1527 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1528 1529 ifp = sc->bce_ifp; 1530 1531 /* Stop and reset the controller. */ 1532 BCE_LOCK(sc); 1533 1534 /* Stop the pulse so the bootcode can go to driver absent state. */ 1535 callout_stop(&sc->bce_pulse_callout); 1536 1537 bce_stop(sc); 1538 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1539 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1540 else 1541 msg = BCE_DRV_MSG_CODE_UNLOAD; 1542 bce_reset(sc, msg); 1543 1544 BCE_UNLOCK(sc); 1545 1546 ether_ifdetach(ifp); 1547 1548 /* If we have a child device on the MII bus remove it too. */ 1549 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1550 ifmedia_removeall(&sc->bce_ifmedia); 1551 else { 1552 bus_generic_detach(dev); 1553 device_delete_child(dev, sc->bce_miibus); 1554 } 1555 1556 /* Release all remaining resources. */ 1557 bce_release_resources(sc); 1558 1559 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1560 1561 return(0); 1562 } 1563 1564 /****************************************************************************/ 1565 /* Device shutdown function. */ 1566 /* */ 1567 /* Stops and resets the controller. */ 1568 /* */ 1569 /* Returns: */ 1570 /* 0 on success, positive value on failure. */ 1571 /****************************************************************************/ 1572 static int 1573 bce_shutdown(device_t dev) 1574 { 1575 struct bce_softc *sc = device_get_softc(dev); 1576 u32 msg; 1577 1578 DBENTER(BCE_VERBOSE); 1579 1580 BCE_LOCK(sc); 1581 bce_stop(sc); 1582 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1583 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1584 else 1585 msg = BCE_DRV_MSG_CODE_UNLOAD; 1586 bce_reset(sc, msg); 1587 BCE_UNLOCK(sc); 1588 1589 DBEXIT(BCE_VERBOSE); 1590 1591 return (0); 1592 } 1593 1594 #ifdef BCE_DEBUG 1595 /****************************************************************************/ 1596 /* Register read. */ 1597 /* */ 1598 /* Returns: */ 1599 /* The value of the register. */ 1600 /****************************************************************************/ 1601 static u32 1602 bce_reg_rd(struct bce_softc *sc, u32 offset) 1603 { 1604 u32 val = REG_RD(sc, offset); 1605 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1606 __FUNCTION__, offset, val); 1607 return val; 1608 } 1609 1610 /****************************************************************************/ 1611 /* Register write (16 bit). */ 1612 /* */ 1613 /* Returns: */ 1614 /* Nothing. */ 1615 /****************************************************************************/ 1616 static void 1617 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1618 { 1619 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1620 __FUNCTION__, offset, val); 1621 REG_WR16(sc, offset, val); 1622 } 1623 1624 /****************************************************************************/ 1625 /* Register write. */ 1626 /* */ 1627 /* Returns: */ 1628 /* Nothing. */ 1629 /****************************************************************************/ 1630 static void 1631 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1632 { 1633 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1634 __FUNCTION__, offset, val); 1635 REG_WR(sc, offset, val); 1636 } 1637 #endif 1638 1639 /****************************************************************************/ 1640 /* Indirect register read. */ 1641 /* */ 1642 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1643 /* configuration space. Using this mechanism avoids issues with posted */ 1644 /* reads but is much slower than memory-mapped I/O. */ 1645 /* */ 1646 /* Returns: */ 1647 /* The value of the register. */ 1648 /****************************************************************************/ 1649 static u32 1650 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1651 { 1652 device_t dev; 1653 dev = sc->bce_dev; 1654 1655 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1656 #ifdef BCE_DEBUG 1657 { 1658 u32 val; 1659 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1660 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1661 __FUNCTION__, offset, val); 1662 return val; 1663 } 1664 #else 1665 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1666 #endif 1667 } 1668 1669 /****************************************************************************/ 1670 /* Indirect register write. */ 1671 /* */ 1672 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1673 /* configuration space. Using this mechanism avoids issues with posted */ 1674 /* writes but is muchh slower than memory-mapped I/O. */ 1675 /* */ 1676 /* Returns: */ 1677 /* Nothing. */ 1678 /****************************************************************************/ 1679 static void 1680 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1681 { 1682 device_t dev; 1683 dev = sc->bce_dev; 1684 1685 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1686 __FUNCTION__, offset, val); 1687 1688 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1689 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1690 } 1691 1692 /****************************************************************************/ 1693 /* Shared memory write. */ 1694 /* */ 1695 /* Writes NetXtreme II shared memory region. */ 1696 /* */ 1697 /* Returns: */ 1698 /* Nothing. */ 1699 /****************************************************************************/ 1700 static void 1701 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1702 { 1703 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1704 "0x%08X\n", __FUNCTION__, val, offset); 1705 1706 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1707 } 1708 1709 /****************************************************************************/ 1710 /* Shared memory read. */ 1711 /* */ 1712 /* Reads NetXtreme II shared memory region. */ 1713 /* */ 1714 /* Returns: */ 1715 /* The 32 bit value read. */ 1716 /****************************************************************************/ 1717 static u32 1718 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1719 { 1720 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1721 1722 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1723 "0x%08X\n", __FUNCTION__, val, offset); 1724 1725 return val; 1726 } 1727 1728 #ifdef BCE_DEBUG 1729 /****************************************************************************/ 1730 /* Context memory read. */ 1731 /* */ 1732 /* The NetXtreme II controller uses context memory to track connection */ 1733 /* information for L2 and higher network protocols. */ 1734 /* */ 1735 /* Returns: */ 1736 /* The requested 32 bit value of context memory. */ 1737 /****************************************************************************/ 1738 static u32 1739 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1740 { 1741 u32 idx, offset, retry_cnt = 5, val; 1742 1743 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1744 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1745 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1746 1747 offset = ctx_offset + cid_addr; 1748 1749 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1750 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1751 1752 for (idx = 0; idx < retry_cnt; idx++) { 1753 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1754 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1755 break; 1756 DELAY(5); 1757 } 1758 1759 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1760 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1761 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1762 __FILE__, __LINE__, cid_addr, ctx_offset); 1763 1764 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1765 } else { 1766 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1767 val = REG_RD(sc, BCE_CTX_DATA); 1768 } 1769 1770 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1771 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1772 1773 return(val); 1774 } 1775 #endif 1776 1777 /****************************************************************************/ 1778 /* Context memory write. */ 1779 /* */ 1780 /* The NetXtreme II controller uses context memory to track connection */ 1781 /* information for L2 and higher network protocols. */ 1782 /* */ 1783 /* Returns: */ 1784 /* Nothing. */ 1785 /****************************************************************************/ 1786 static void 1787 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1788 { 1789 u32 idx, offset = ctx_offset + cid_addr; 1790 u32 val, retry_cnt = 5; 1791 1792 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1793 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1794 1795 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1796 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1797 __FUNCTION__, cid_addr)); 1798 1799 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1800 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1801 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1802 1803 for (idx = 0; idx < retry_cnt; idx++) { 1804 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1805 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1806 break; 1807 DELAY(5); 1808 } 1809 1810 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1811 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1812 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1813 __FILE__, __LINE__, cid_addr, ctx_offset); 1814 1815 } else { 1816 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1817 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1818 } 1819 } 1820 1821 /****************************************************************************/ 1822 /* PHY register read. */ 1823 /* */ 1824 /* Implements register reads on the MII bus. */ 1825 /* */ 1826 /* Returns: */ 1827 /* The value of the register. */ 1828 /****************************************************************************/ 1829 static int 1830 bce_miibus_read_reg(device_t dev, int phy, int reg) 1831 { 1832 struct bce_softc *sc; 1833 u32 val; 1834 int i; 1835 1836 sc = device_get_softc(dev); 1837 1838 /* 1839 * The 5709S PHY is an IEEE Clause 45 PHY 1840 * with special mappings to work with IEEE 1841 * Clause 22 register accesses. 1842 */ 1843 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1844 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1845 reg += 0x10; 1846 } 1847 1848 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1849 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1850 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1851 1852 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1853 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1854 1855 DELAY(40); 1856 } 1857 1858 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1859 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1860 BCE_EMAC_MDIO_COMM_START_BUSY; 1861 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1862 1863 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1864 DELAY(10); 1865 1866 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1867 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1868 DELAY(5); 1869 1870 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1871 val &= BCE_EMAC_MDIO_COMM_DATA; 1872 1873 break; 1874 } 1875 } 1876 1877 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1878 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1879 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1880 val = 0x0; 1881 } else { 1882 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1883 } 1884 1885 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1886 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1887 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1888 1889 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1890 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1891 1892 DELAY(40); 1893 } 1894 1895 DB_PRINT_PHY_REG(reg, val); 1896 return (val & 0xffff); 1897 } 1898 1899 /****************************************************************************/ 1900 /* PHY register write. */ 1901 /* */ 1902 /* Implements register writes on the MII bus. */ 1903 /* */ 1904 /* Returns: */ 1905 /* The value of the register. */ 1906 /****************************************************************************/ 1907 static int 1908 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1909 { 1910 struct bce_softc *sc; 1911 u32 val1; 1912 int i; 1913 1914 sc = device_get_softc(dev); 1915 1916 DB_PRINT_PHY_REG(reg, val); 1917 1918 /* 1919 * The 5709S PHY is an IEEE Clause 45 PHY 1920 * with special mappings to work with IEEE 1921 * Clause 22 register accesses. 1922 */ 1923 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1924 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1925 reg += 0x10; 1926 } 1927 1928 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1929 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1930 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1931 1932 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1933 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1934 1935 DELAY(40); 1936 } 1937 1938 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1939 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1940 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1941 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1942 1943 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1944 DELAY(10); 1945 1946 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1947 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1948 DELAY(5); 1949 break; 1950 } 1951 } 1952 1953 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1954 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1955 __FILE__, __LINE__); 1956 1957 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1958 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1959 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1960 1961 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1962 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1963 1964 DELAY(40); 1965 } 1966 1967 return 0; 1968 } 1969 1970 /****************************************************************************/ 1971 /* MII bus status change. */ 1972 /* */ 1973 /* Called by the MII bus driver when the PHY establishes link to set the */ 1974 /* MAC interface registers. */ 1975 /* */ 1976 /* Returns: */ 1977 /* Nothing. */ 1978 /****************************************************************************/ 1979 static void 1980 bce_miibus_statchg(device_t dev) 1981 { 1982 struct bce_softc *sc; 1983 struct mii_data *mii; 1984 struct ifmediareq ifmr; 1985 int media_active, media_status, val; 1986 1987 sc = device_get_softc(dev); 1988 1989 DBENTER(BCE_VERBOSE_PHY); 1990 1991 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1992 bzero(&ifmr, sizeof(ifmr)); 1993 bce_ifmedia_sts_rphy(sc, &ifmr); 1994 media_active = ifmr.ifm_active; 1995 media_status = ifmr.ifm_status; 1996 } else { 1997 mii = device_get_softc(sc->bce_miibus); 1998 media_active = mii->mii_media_active; 1999 media_status = mii->mii_media_status; 2000 } 2001 2002 /* Ignore invalid media status. */ 2003 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2004 (IFM_ACTIVE | IFM_AVALID)) 2005 goto bce_miibus_statchg_exit; 2006 2007 val = REG_RD(sc, BCE_EMAC_MODE); 2008 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2009 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2010 BCE_EMAC_MODE_25G); 2011 2012 /* Set MII or GMII interface based on the PHY speed. */ 2013 switch (IFM_SUBTYPE(media_active)) { 2014 case IFM_10_T: 2015 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2016 DBPRINT(sc, BCE_INFO_PHY, 2017 "Enabling 10Mb interface.\n"); 2018 val |= BCE_EMAC_MODE_PORT_MII_10; 2019 break; 2020 } 2021 /* fall-through */ 2022 case IFM_100_TX: 2023 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2024 val |= BCE_EMAC_MODE_PORT_MII; 2025 break; 2026 case IFM_2500_SX: 2027 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2028 val |= BCE_EMAC_MODE_25G; 2029 /* fall-through */ 2030 case IFM_1000_T: 2031 case IFM_1000_SX: 2032 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2033 val |= BCE_EMAC_MODE_PORT_GMII; 2034 break; 2035 default: 2036 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2037 "default GMII interface.\n"); 2038 val |= BCE_EMAC_MODE_PORT_GMII; 2039 } 2040 2041 /* Set half or full duplex based on PHY settings. */ 2042 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2043 DBPRINT(sc, BCE_INFO_PHY, 2044 "Setting Half-Duplex interface.\n"); 2045 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2046 } else 2047 DBPRINT(sc, BCE_INFO_PHY, 2048 "Setting Full-Duplex interface.\n"); 2049 2050 REG_WR(sc, BCE_EMAC_MODE, val); 2051 2052 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2053 DBPRINT(sc, BCE_INFO_PHY, 2054 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2055 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2056 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL; 2057 } else { 2058 DBPRINT(sc, BCE_INFO_PHY, 2059 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2060 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2061 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL; 2062 } 2063 2064 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2065 DBPRINT(sc, BCE_INFO_PHY, 2066 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2067 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2068 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2069 } else { 2070 DBPRINT(sc, BCE_INFO_PHY, 2071 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2072 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2073 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2074 } 2075 2076 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2077 2078 bce_miibus_statchg_exit: 2079 DBEXIT(BCE_VERBOSE_PHY); 2080 } 2081 2082 /****************************************************************************/ 2083 /* Acquire NVRAM lock. */ 2084 /* */ 2085 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2086 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2087 /* for use by the driver. */ 2088 /* */ 2089 /* Returns: */ 2090 /* 0 on success, positive value on failure. */ 2091 /****************************************************************************/ 2092 static int 2093 bce_acquire_nvram_lock(struct bce_softc *sc) 2094 { 2095 u32 val; 2096 int j, rc = 0; 2097 2098 DBENTER(BCE_VERBOSE_NVRAM); 2099 2100 /* Request access to the flash interface. */ 2101 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2102 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2103 val = REG_RD(sc, BCE_NVM_SW_ARB); 2104 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2105 break; 2106 2107 DELAY(5); 2108 } 2109 2110 if (j >= NVRAM_TIMEOUT_COUNT) { 2111 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2112 rc = EBUSY; 2113 } 2114 2115 DBEXIT(BCE_VERBOSE_NVRAM); 2116 return (rc); 2117 } 2118 2119 /****************************************************************************/ 2120 /* Release NVRAM lock. */ 2121 /* */ 2122 /* When the caller is finished accessing NVRAM the lock must be released. */ 2123 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2124 /* for use by the driver. */ 2125 /* */ 2126 /* Returns: */ 2127 /* 0 on success, positive value on failure. */ 2128 /****************************************************************************/ 2129 static int 2130 bce_release_nvram_lock(struct bce_softc *sc) 2131 { 2132 u32 val; 2133 int j, rc = 0; 2134 2135 DBENTER(BCE_VERBOSE_NVRAM); 2136 2137 /* 2138 * Relinquish nvram interface. 2139 */ 2140 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2141 2142 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2143 val = REG_RD(sc, BCE_NVM_SW_ARB); 2144 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2145 break; 2146 2147 DELAY(5); 2148 } 2149 2150 if (j >= NVRAM_TIMEOUT_COUNT) { 2151 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2152 rc = EBUSY; 2153 } 2154 2155 DBEXIT(BCE_VERBOSE_NVRAM); 2156 return (rc); 2157 } 2158 2159 #ifdef BCE_NVRAM_WRITE_SUPPORT 2160 /****************************************************************************/ 2161 /* Enable NVRAM write access. */ 2162 /* */ 2163 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2164 /* */ 2165 /* Returns: */ 2166 /* 0 on success, positive value on failure. */ 2167 /****************************************************************************/ 2168 static int 2169 bce_enable_nvram_write(struct bce_softc *sc) 2170 { 2171 u32 val; 2172 int rc = 0; 2173 2174 DBENTER(BCE_VERBOSE_NVRAM); 2175 2176 val = REG_RD(sc, BCE_MISC_CFG); 2177 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2178 2179 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2180 int j; 2181 2182 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2183 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2184 2185 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2186 DELAY(5); 2187 2188 val = REG_RD(sc, BCE_NVM_COMMAND); 2189 if (val & BCE_NVM_COMMAND_DONE) 2190 break; 2191 } 2192 2193 if (j >= NVRAM_TIMEOUT_COUNT) { 2194 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2195 rc = EBUSY; 2196 } 2197 } 2198 2199 DBENTER(BCE_VERBOSE_NVRAM); 2200 return (rc); 2201 } 2202 2203 /****************************************************************************/ 2204 /* Disable NVRAM write access. */ 2205 /* */ 2206 /* When the caller is finished writing to NVRAM write access must be */ 2207 /* disabled. */ 2208 /* */ 2209 /* Returns: */ 2210 /* Nothing. */ 2211 /****************************************************************************/ 2212 static void 2213 bce_disable_nvram_write(struct bce_softc *sc) 2214 { 2215 u32 val; 2216 2217 DBENTER(BCE_VERBOSE_NVRAM); 2218 2219 val = REG_RD(sc, BCE_MISC_CFG); 2220 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2221 2222 DBEXIT(BCE_VERBOSE_NVRAM); 2223 2224 } 2225 #endif 2226 2227 /****************************************************************************/ 2228 /* Enable NVRAM access. */ 2229 /* */ 2230 /* Before accessing NVRAM for read or write operations the caller must */ 2231 /* enabled NVRAM access. */ 2232 /* */ 2233 /* Returns: */ 2234 /* Nothing. */ 2235 /****************************************************************************/ 2236 static void 2237 bce_enable_nvram_access(struct bce_softc *sc) 2238 { 2239 u32 val; 2240 2241 DBENTER(BCE_VERBOSE_NVRAM); 2242 2243 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2244 /* Enable both bits, even on read. */ 2245 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2246 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2247 2248 DBEXIT(BCE_VERBOSE_NVRAM); 2249 } 2250 2251 /****************************************************************************/ 2252 /* Disable NVRAM access. */ 2253 /* */ 2254 /* When the caller is finished accessing NVRAM access must be disabled. */ 2255 /* */ 2256 /* Returns: */ 2257 /* Nothing. */ 2258 /****************************************************************************/ 2259 static void 2260 bce_disable_nvram_access(struct bce_softc *sc) 2261 { 2262 u32 val; 2263 2264 DBENTER(BCE_VERBOSE_NVRAM); 2265 2266 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2267 2268 /* Disable both bits, even after read. */ 2269 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2270 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2271 2272 DBEXIT(BCE_VERBOSE_NVRAM); 2273 } 2274 2275 #ifdef BCE_NVRAM_WRITE_SUPPORT 2276 /****************************************************************************/ 2277 /* Erase NVRAM page before writing. */ 2278 /* */ 2279 /* Non-buffered flash parts require that a page be erased before it is */ 2280 /* written. */ 2281 /* */ 2282 /* Returns: */ 2283 /* 0 on success, positive value on failure. */ 2284 /****************************************************************************/ 2285 static int 2286 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2287 { 2288 u32 cmd; 2289 int j, rc = 0; 2290 2291 DBENTER(BCE_VERBOSE_NVRAM); 2292 2293 /* Buffered flash doesn't require an erase. */ 2294 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2295 goto bce_nvram_erase_page_exit; 2296 2297 /* Build an erase command. */ 2298 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2299 BCE_NVM_COMMAND_DOIT; 2300 2301 /* 2302 * Clear the DONE bit separately, set the NVRAM address to erase, 2303 * and issue the erase command. 2304 */ 2305 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2306 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2307 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2308 2309 /* Wait for completion. */ 2310 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2311 u32 val; 2312 2313 DELAY(5); 2314 2315 val = REG_RD(sc, BCE_NVM_COMMAND); 2316 if (val & BCE_NVM_COMMAND_DONE) 2317 break; 2318 } 2319 2320 if (j >= NVRAM_TIMEOUT_COUNT) { 2321 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2322 rc = EBUSY; 2323 } 2324 2325 bce_nvram_erase_page_exit: 2326 DBEXIT(BCE_VERBOSE_NVRAM); 2327 return (rc); 2328 } 2329 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2330 2331 /****************************************************************************/ 2332 /* Read a dword (32 bits) from NVRAM. */ 2333 /* */ 2334 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2335 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2336 /* */ 2337 /* Returns: */ 2338 /* 0 on success and the 32 bit value read, positive value on failure. */ 2339 /****************************************************************************/ 2340 static int 2341 bce_nvram_read_dword(struct bce_softc *sc, 2342 u32 offset, u8 *ret_val, u32 cmd_flags) 2343 { 2344 u32 cmd; 2345 int i, rc = 0; 2346 2347 DBENTER(BCE_EXTREME_NVRAM); 2348 2349 /* Build the command word. */ 2350 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2351 2352 /* Calculate the offset for buffered flash if translation is used. */ 2353 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2354 offset = ((offset / sc->bce_flash_info->page_size) << 2355 sc->bce_flash_info->page_bits) + 2356 (offset % sc->bce_flash_info->page_size); 2357 } 2358 2359 /* 2360 * Clear the DONE bit separately, set the address to read, 2361 * and issue the read. 2362 */ 2363 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2364 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2365 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2366 2367 /* Wait for completion. */ 2368 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2369 u32 val; 2370 2371 DELAY(5); 2372 2373 val = REG_RD(sc, BCE_NVM_COMMAND); 2374 if (val & BCE_NVM_COMMAND_DONE) { 2375 val = REG_RD(sc, BCE_NVM_READ); 2376 2377 val = bce_be32toh(val); 2378 memcpy(ret_val, &val, 4); 2379 break; 2380 } 2381 } 2382 2383 /* Check for errors. */ 2384 if (i >= NVRAM_TIMEOUT_COUNT) { 2385 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2386 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2387 rc = EBUSY; 2388 } 2389 2390 DBEXIT(BCE_EXTREME_NVRAM); 2391 return(rc); 2392 } 2393 2394 #ifdef BCE_NVRAM_WRITE_SUPPORT 2395 /****************************************************************************/ 2396 /* Write a dword (32 bits) to NVRAM. */ 2397 /* */ 2398 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2399 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2400 /* enabled NVRAM write access. */ 2401 /* */ 2402 /* Returns: */ 2403 /* 0 on success, positive value on failure. */ 2404 /****************************************************************************/ 2405 static int 2406 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2407 u32 cmd_flags) 2408 { 2409 u32 cmd, val32; 2410 int j, rc = 0; 2411 2412 DBENTER(BCE_VERBOSE_NVRAM); 2413 2414 /* Build the command word. */ 2415 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2416 2417 /* Calculate the offset for buffered flash if translation is used. */ 2418 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2419 offset = ((offset / sc->bce_flash_info->page_size) << 2420 sc->bce_flash_info->page_bits) + 2421 (offset % sc->bce_flash_info->page_size); 2422 } 2423 2424 /* 2425 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2426 * set the NVRAM address to write, and issue the write command 2427 */ 2428 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2429 memcpy(&val32, val, 4); 2430 val32 = htobe32(val32); 2431 REG_WR(sc, BCE_NVM_WRITE, val32); 2432 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2433 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2434 2435 /* Wait for completion. */ 2436 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2437 DELAY(5); 2438 2439 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2440 break; 2441 } 2442 if (j >= NVRAM_TIMEOUT_COUNT) { 2443 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2444 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2445 rc = EBUSY; 2446 } 2447 2448 DBEXIT(BCE_VERBOSE_NVRAM); 2449 return (rc); 2450 } 2451 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2452 2453 /****************************************************************************/ 2454 /* Initialize NVRAM access. */ 2455 /* */ 2456 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2457 /* access that device. */ 2458 /* */ 2459 /* Returns: */ 2460 /* 0 on success, positive value on failure. */ 2461 /****************************************************************************/ 2462 static int 2463 bce_init_nvram(struct bce_softc *sc) 2464 { 2465 u32 val; 2466 int j, entry_count, rc = 0; 2467 const struct flash_spec *flash; 2468 2469 DBENTER(BCE_VERBOSE_NVRAM); 2470 2471 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2472 sc->bce_flash_info = &flash_5709; 2473 goto bce_init_nvram_get_flash_size; 2474 } 2475 2476 /* Determine the selected interface. */ 2477 val = REG_RD(sc, BCE_NVM_CFG1); 2478 2479 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2480 2481 /* 2482 * Flash reconfiguration is required to support additional 2483 * NVRAM devices not directly supported in hardware. 2484 * Check if the flash interface was reconfigured 2485 * by the bootcode. 2486 */ 2487 2488 if (val & 0x40000000) { 2489 /* Flash interface reconfigured by bootcode. */ 2490 2491 DBPRINT(sc,BCE_INFO_LOAD, 2492 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2493 2494 for (j = 0, flash = &flash_table[0]; j < entry_count; 2495 j++, flash++) { 2496 if ((val & FLASH_BACKUP_STRAP_MASK) == 2497 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2498 sc->bce_flash_info = flash; 2499 break; 2500 } 2501 } 2502 } else { 2503 /* Flash interface not yet reconfigured. */ 2504 u32 mask; 2505 2506 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2507 __FUNCTION__); 2508 2509 if (val & (1 << 23)) 2510 mask = FLASH_BACKUP_STRAP_MASK; 2511 else 2512 mask = FLASH_STRAP_MASK; 2513 2514 /* Look for the matching NVRAM device configuration data. */ 2515 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2516 /* Check if the device matches any of the known devices. */ 2517 if ((val & mask) == (flash->strapping & mask)) { 2518 /* Found a device match. */ 2519 sc->bce_flash_info = flash; 2520 2521 /* Request access to the flash interface. */ 2522 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2523 return rc; 2524 2525 /* Reconfigure the flash interface. */ 2526 bce_enable_nvram_access(sc); 2527 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2528 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2529 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2530 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2531 bce_disable_nvram_access(sc); 2532 bce_release_nvram_lock(sc); 2533 2534 break; 2535 } 2536 } 2537 } 2538 2539 /* Check if a matching device was found. */ 2540 if (j == entry_count) { 2541 sc->bce_flash_info = NULL; 2542 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2543 __FILE__, __LINE__); 2544 DBEXIT(BCE_VERBOSE_NVRAM); 2545 return (ENODEV); 2546 } 2547 2548 bce_init_nvram_get_flash_size: 2549 /* Write the flash config data to the shared memory interface. */ 2550 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2551 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2552 if (val) 2553 sc->bce_flash_size = val; 2554 else 2555 sc->bce_flash_size = sc->bce_flash_info->total_size; 2556 2557 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2558 __FUNCTION__, sc->bce_flash_info->name, 2559 sc->bce_flash_info->total_size); 2560 2561 DBEXIT(BCE_VERBOSE_NVRAM); 2562 return rc; 2563 } 2564 2565 /****************************************************************************/ 2566 /* Read an arbitrary range of data from NVRAM. */ 2567 /* */ 2568 /* Prepares the NVRAM interface for access and reads the requested data */ 2569 /* into the supplied buffer. */ 2570 /* */ 2571 /* Returns: */ 2572 /* 0 on success and the data read, positive value on failure. */ 2573 /****************************************************************************/ 2574 static int 2575 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2576 int buf_size) 2577 { 2578 int rc = 0; 2579 u32 cmd_flags, offset32, len32, extra; 2580 2581 DBENTER(BCE_VERBOSE_NVRAM); 2582 2583 if (buf_size == 0) 2584 goto bce_nvram_read_exit; 2585 2586 /* Request access to the flash interface. */ 2587 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2588 goto bce_nvram_read_exit; 2589 2590 /* Enable access to flash interface */ 2591 bce_enable_nvram_access(sc); 2592 2593 len32 = buf_size; 2594 offset32 = offset; 2595 extra = 0; 2596 2597 cmd_flags = 0; 2598 2599 if (offset32 & 3) { 2600 u8 buf[4]; 2601 u32 pre_len; 2602 2603 offset32 &= ~3; 2604 pre_len = 4 - (offset & 3); 2605 2606 if (pre_len >= len32) { 2607 pre_len = len32; 2608 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2609 } 2610 else { 2611 cmd_flags = BCE_NVM_COMMAND_FIRST; 2612 } 2613 2614 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2615 2616 if (rc) 2617 return rc; 2618 2619 memcpy(ret_buf, buf + (offset & 3), pre_len); 2620 2621 offset32 += 4; 2622 ret_buf += pre_len; 2623 len32 -= pre_len; 2624 } 2625 2626 if (len32 & 3) { 2627 extra = 4 - (len32 & 3); 2628 len32 = (len32 + 4) & ~3; 2629 } 2630 2631 if (len32 == 4) { 2632 u8 buf[4]; 2633 2634 if (cmd_flags) 2635 cmd_flags = BCE_NVM_COMMAND_LAST; 2636 else 2637 cmd_flags = BCE_NVM_COMMAND_FIRST | 2638 BCE_NVM_COMMAND_LAST; 2639 2640 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2641 2642 memcpy(ret_buf, buf, 4 - extra); 2643 } 2644 else if (len32 > 0) { 2645 u8 buf[4]; 2646 2647 /* Read the first word. */ 2648 if (cmd_flags) 2649 cmd_flags = 0; 2650 else 2651 cmd_flags = BCE_NVM_COMMAND_FIRST; 2652 2653 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2654 2655 /* Advance to the next dword. */ 2656 offset32 += 4; 2657 ret_buf += 4; 2658 len32 -= 4; 2659 2660 while (len32 > 4 && rc == 0) { 2661 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2662 2663 /* Advance to the next dword. */ 2664 offset32 += 4; 2665 ret_buf += 4; 2666 len32 -= 4; 2667 } 2668 2669 if (rc) 2670 goto bce_nvram_read_locked_exit; 2671 2672 cmd_flags = BCE_NVM_COMMAND_LAST; 2673 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2674 2675 memcpy(ret_buf, buf, 4 - extra); 2676 } 2677 2678 bce_nvram_read_locked_exit: 2679 /* Disable access to flash interface and release the lock. */ 2680 bce_disable_nvram_access(sc); 2681 bce_release_nvram_lock(sc); 2682 2683 bce_nvram_read_exit: 2684 DBEXIT(BCE_VERBOSE_NVRAM); 2685 return rc; 2686 } 2687 2688 #ifdef BCE_NVRAM_WRITE_SUPPORT 2689 /****************************************************************************/ 2690 /* Write an arbitrary range of data from NVRAM. */ 2691 /* */ 2692 /* Prepares the NVRAM interface for write access and writes the requested */ 2693 /* data from the supplied buffer. The caller is responsible for */ 2694 /* calculating any appropriate CRCs. */ 2695 /* */ 2696 /* Returns: */ 2697 /* 0 on success, positive value on failure. */ 2698 /****************************************************************************/ 2699 static int 2700 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2701 int buf_size) 2702 { 2703 u32 written, offset32, len32; 2704 u8 *buf, start[4], end[4]; 2705 int rc = 0; 2706 int align_start, align_end; 2707 2708 DBENTER(BCE_VERBOSE_NVRAM); 2709 2710 buf = data_buf; 2711 offset32 = offset; 2712 len32 = buf_size; 2713 align_start = align_end = 0; 2714 2715 if ((align_start = (offset32 & 3))) { 2716 offset32 &= ~3; 2717 len32 += align_start; 2718 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2719 goto bce_nvram_write_exit; 2720 } 2721 2722 if (len32 & 3) { 2723 if ((len32 > 4) || !align_start) { 2724 align_end = 4 - (len32 & 3); 2725 len32 += align_end; 2726 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2727 end, 4))) { 2728 goto bce_nvram_write_exit; 2729 } 2730 } 2731 } 2732 2733 if (align_start || align_end) { 2734 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2735 if (buf == NULL) { 2736 rc = ENOMEM; 2737 goto bce_nvram_write_exit; 2738 } 2739 2740 if (align_start) { 2741 memcpy(buf, start, 4); 2742 } 2743 2744 if (align_end) { 2745 memcpy(buf + len32 - 4, end, 4); 2746 } 2747 memcpy(buf + align_start, data_buf, buf_size); 2748 } 2749 2750 written = 0; 2751 while ((written < len32) && (rc == 0)) { 2752 u32 page_start, page_end, data_start, data_end; 2753 u32 addr, cmd_flags; 2754 int i; 2755 u8 flash_buffer[264]; 2756 2757 /* Find the page_start addr */ 2758 page_start = offset32 + written; 2759 page_start -= (page_start % sc->bce_flash_info->page_size); 2760 /* Find the page_end addr */ 2761 page_end = page_start + sc->bce_flash_info->page_size; 2762 /* Find the data_start addr */ 2763 data_start = (written == 0) ? offset32 : page_start; 2764 /* Find the data_end addr */ 2765 data_end = (page_end > offset32 + len32) ? 2766 (offset32 + len32) : page_end; 2767 2768 /* Request access to the flash interface. */ 2769 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2770 goto bce_nvram_write_exit; 2771 2772 /* Enable access to flash interface */ 2773 bce_enable_nvram_access(sc); 2774 2775 cmd_flags = BCE_NVM_COMMAND_FIRST; 2776 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2777 int j; 2778 2779 /* Read the whole page into the buffer 2780 * (non-buffer flash only) */ 2781 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2782 if (j == (sc->bce_flash_info->page_size - 4)) { 2783 cmd_flags |= BCE_NVM_COMMAND_LAST; 2784 } 2785 rc = bce_nvram_read_dword(sc, 2786 page_start + j, 2787 &flash_buffer[j], 2788 cmd_flags); 2789 2790 if (rc) 2791 goto bce_nvram_write_locked_exit; 2792 2793 cmd_flags = 0; 2794 } 2795 } 2796 2797 /* Enable writes to flash interface (unlock write-protect) */ 2798 if ((rc = bce_enable_nvram_write(sc)) != 0) 2799 goto bce_nvram_write_locked_exit; 2800 2801 /* Erase the page */ 2802 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2803 goto bce_nvram_write_locked_exit; 2804 2805 /* Re-enable the write again for the actual write */ 2806 bce_enable_nvram_write(sc); 2807 2808 /* Loop to write back the buffer data from page_start to 2809 * data_start */ 2810 i = 0; 2811 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2812 for (addr = page_start; addr < data_start; 2813 addr += 4, i += 4) { 2814 rc = bce_nvram_write_dword(sc, addr, 2815 &flash_buffer[i], cmd_flags); 2816 2817 if (rc != 0) 2818 goto bce_nvram_write_locked_exit; 2819 2820 cmd_flags = 0; 2821 } 2822 } 2823 2824 /* Loop to write the new data from data_start to data_end */ 2825 for (addr = data_start; addr < data_end; addr += 4, i++) { 2826 if ((addr == page_end - 4) || 2827 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2828 (addr == data_end - 4))) { 2829 cmd_flags |= BCE_NVM_COMMAND_LAST; 2830 } 2831 rc = bce_nvram_write_dword(sc, addr, buf, 2832 cmd_flags); 2833 2834 if (rc != 0) 2835 goto bce_nvram_write_locked_exit; 2836 2837 cmd_flags = 0; 2838 buf += 4; 2839 } 2840 2841 /* Loop to write back the buffer data from data_end 2842 * to page_end */ 2843 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2844 for (addr = data_end; addr < page_end; 2845 addr += 4, i += 4) { 2846 if (addr == page_end-4) { 2847 cmd_flags = BCE_NVM_COMMAND_LAST; 2848 } 2849 rc = bce_nvram_write_dword(sc, addr, 2850 &flash_buffer[i], cmd_flags); 2851 2852 if (rc != 0) 2853 goto bce_nvram_write_locked_exit; 2854 2855 cmd_flags = 0; 2856 } 2857 } 2858 2859 /* Disable writes to flash interface (lock write-protect) */ 2860 bce_disable_nvram_write(sc); 2861 2862 /* Disable access to flash interface */ 2863 bce_disable_nvram_access(sc); 2864 bce_release_nvram_lock(sc); 2865 2866 /* Increment written */ 2867 written += data_end - data_start; 2868 } 2869 2870 goto bce_nvram_write_exit; 2871 2872 bce_nvram_write_locked_exit: 2873 bce_disable_nvram_write(sc); 2874 bce_disable_nvram_access(sc); 2875 bce_release_nvram_lock(sc); 2876 2877 bce_nvram_write_exit: 2878 if (align_start || align_end) 2879 free(buf, M_DEVBUF); 2880 2881 DBEXIT(BCE_VERBOSE_NVRAM); 2882 return (rc); 2883 } 2884 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2885 2886 /****************************************************************************/ 2887 /* Verifies that NVRAM is accessible and contains valid data. */ 2888 /* */ 2889 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2890 /* correct. */ 2891 /* */ 2892 /* Returns: */ 2893 /* 0 on success, positive value on failure. */ 2894 /****************************************************************************/ 2895 static int 2896 bce_nvram_test(struct bce_softc *sc) 2897 { 2898 u32 buf[BCE_NVRAM_SIZE / 4]; 2899 u8 *data = (u8 *) buf; 2900 int rc = 0; 2901 u32 magic, csum; 2902 2903 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2904 2905 /* 2906 * Check that the device NVRAM is valid by reading 2907 * the magic value at offset 0. 2908 */ 2909 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2910 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2911 __FILE__, __LINE__); 2912 goto bce_nvram_test_exit; 2913 } 2914 2915 /* 2916 * Verify that offset 0 of the NVRAM contains 2917 * a valid magic number. 2918 */ 2919 magic = bce_be32toh(buf[0]); 2920 if (magic != BCE_NVRAM_MAGIC) { 2921 rc = ENODEV; 2922 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2923 "Expected: 0x%08X, Found: 0x%08X\n", 2924 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2925 goto bce_nvram_test_exit; 2926 } 2927 2928 /* 2929 * Verify that the device NVRAM includes valid 2930 * configuration data. 2931 */ 2932 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2933 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2934 "Information from NVRAM!\n", __FILE__, __LINE__); 2935 goto bce_nvram_test_exit; 2936 } 2937 2938 csum = ether_crc32_le(data, 0x100); 2939 if (csum != BCE_CRC32_RESIDUAL) { 2940 rc = ENODEV; 2941 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2942 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2943 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2944 goto bce_nvram_test_exit; 2945 } 2946 2947 csum = ether_crc32_le(data + 0x100, 0x100); 2948 if (csum != BCE_CRC32_RESIDUAL) { 2949 rc = ENODEV; 2950 BCE_PRINTF("%s(%d): Invalid feature configuration " 2951 "information NVRAM CRC! Expected: 0x%08X, " 2952 "Found: 08%08X\n", __FILE__, __LINE__, 2953 BCE_CRC32_RESIDUAL, csum); 2954 } 2955 2956 bce_nvram_test_exit: 2957 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2958 return rc; 2959 } 2960 2961 /****************************************************************************/ 2962 /* Calculates the size of the buffers to allocate based on the MTU. */ 2963 /* */ 2964 /* Returns: */ 2965 /* Nothing. */ 2966 /****************************************************************************/ 2967 static void 2968 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 2969 { 2970 DBENTER(BCE_VERBOSE_LOAD); 2971 2972 /* Use a single allocation type when header splitting enabled. */ 2973 if (bce_hdr_split == TRUE) { 2974 sc->rx_bd_mbuf_alloc_size = MHLEN; 2975 /* Make sure offset is 16 byte aligned for hardware. */ 2976 sc->rx_bd_mbuf_align_pad = 2977 roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN); 2978 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 2979 sc->rx_bd_mbuf_align_pad; 2980 } else { 2981 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2982 ETHER_CRC_LEN) > MCLBYTES) { 2983 /* Setup for jumbo RX buffer allocations. */ 2984 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 2985 sc->rx_bd_mbuf_align_pad = 2986 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 2987 sc->rx_bd_mbuf_data_len = 2988 sc->rx_bd_mbuf_alloc_size - 2989 sc->rx_bd_mbuf_align_pad; 2990 } else { 2991 /* Setup for standard RX buffer allocations. */ 2992 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 2993 sc->rx_bd_mbuf_align_pad = 2994 roundup2(MCLBYTES, 16) - MCLBYTES; 2995 sc->rx_bd_mbuf_data_len = 2996 sc->rx_bd_mbuf_alloc_size - 2997 sc->rx_bd_mbuf_align_pad; 2998 } 2999 } 3000 3001 // DBPRINT(sc, BCE_INFO_LOAD, 3002 DBPRINT(sc, BCE_WARN, 3003 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3004 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3005 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3006 sc->rx_bd_mbuf_align_pad); 3007 3008 DBEXIT(BCE_VERBOSE_LOAD); 3009 } 3010 3011 /****************************************************************************/ 3012 /* Identifies the current media type of the controller and sets the PHY */ 3013 /* address. */ 3014 /* */ 3015 /* Returns: */ 3016 /* Nothing. */ 3017 /****************************************************************************/ 3018 static void 3019 bce_get_media(struct bce_softc *sc) 3020 { 3021 u32 val; 3022 3023 DBENTER(BCE_VERBOSE_PHY); 3024 3025 /* Assume PHY address for copper controllers. */ 3026 sc->bce_phy_addr = 1; 3027 3028 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3029 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3030 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3031 u32 strap; 3032 3033 /* 3034 * The BCM5709S is software configurable 3035 * for Copper or SerDes operation. 3036 */ 3037 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3038 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3039 "for copper.\n"); 3040 goto bce_get_media_exit; 3041 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3042 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3043 "for dual media.\n"); 3044 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3045 goto bce_get_media_exit; 3046 } 3047 3048 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3049 strap = (val & 3050 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3051 else 3052 strap = (val & 3053 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3054 3055 if (pci_get_function(sc->bce_dev) == 0) { 3056 switch (strap) { 3057 case 0x4: 3058 case 0x5: 3059 case 0x6: 3060 DBPRINT(sc, BCE_INFO_LOAD, 3061 "BCM5709 s/w configured for SerDes.\n"); 3062 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3063 break; 3064 default: 3065 DBPRINT(sc, BCE_INFO_LOAD, 3066 "BCM5709 s/w configured for Copper.\n"); 3067 break; 3068 } 3069 } else { 3070 switch (strap) { 3071 case 0x1: 3072 case 0x2: 3073 case 0x4: 3074 DBPRINT(sc, BCE_INFO_LOAD, 3075 "BCM5709 s/w configured for SerDes.\n"); 3076 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3077 break; 3078 default: 3079 DBPRINT(sc, BCE_INFO_LOAD, 3080 "BCM5709 s/w configured for Copper.\n"); 3081 break; 3082 } 3083 } 3084 3085 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3086 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3087 3088 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3089 sc->bce_flags |= BCE_NO_WOL_FLAG; 3090 3091 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3092 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3093 3094 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3095 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3096 sc->bce_phy_addr = 2; 3097 3098 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3099 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3100 sc->bce_phy_flags |= 3101 BCE_PHY_2_5G_CAPABLE_FLAG; 3102 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3103 "capable adapter\n"); 3104 } 3105 } 3106 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3107 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3108 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3109 3110 bce_get_media_exit: 3111 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3112 "Using PHY address %d.\n", sc->bce_phy_addr); 3113 3114 DBEXIT(BCE_VERBOSE_PHY); 3115 } 3116 3117 /****************************************************************************/ 3118 /* Performs PHY initialization required before MII drivers access the */ 3119 /* device. */ 3120 /* */ 3121 /* Returns: */ 3122 /* Nothing. */ 3123 /****************************************************************************/ 3124 static void 3125 bce_init_media(struct bce_softc *sc) 3126 { 3127 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3128 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3129 /* 3130 * Configure 5709S/5716S PHYs to use traditional IEEE 3131 * Clause 22 method. Otherwise we have no way to attach 3132 * the PHY in mii(4) layer. PHY specific configuration 3133 * is done in mii layer. 3134 */ 3135 3136 /* Select auto-negotiation MMD of the PHY. */ 3137 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3138 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3139 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3140 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3141 3142 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3143 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3144 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3145 } 3146 } 3147 3148 /****************************************************************************/ 3149 /* Free any DMA memory owned by the driver. */ 3150 /* */ 3151 /* Scans through each data structure that requires DMA memory and frees */ 3152 /* the memory if allocated. */ 3153 /* */ 3154 /* Returns: */ 3155 /* Nothing. */ 3156 /****************************************************************************/ 3157 static void 3158 bce_dma_free(struct bce_softc *sc) 3159 { 3160 int i; 3161 3162 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3163 3164 /* Free, unmap, and destroy the status block. */ 3165 if (sc->status_block_paddr != 0) { 3166 bus_dmamap_unload( 3167 sc->status_tag, 3168 sc->status_map); 3169 sc->status_block_paddr = 0; 3170 } 3171 3172 if (sc->status_block != NULL) { 3173 bus_dmamem_free( 3174 sc->status_tag, 3175 sc->status_block, 3176 sc->status_map); 3177 sc->status_block = NULL; 3178 } 3179 3180 if (sc->status_tag != NULL) { 3181 bus_dma_tag_destroy(sc->status_tag); 3182 sc->status_tag = NULL; 3183 } 3184 3185 /* Free, unmap, and destroy the statistics block. */ 3186 if (sc->stats_block_paddr != 0) { 3187 bus_dmamap_unload( 3188 sc->stats_tag, 3189 sc->stats_map); 3190 sc->stats_block_paddr = 0; 3191 } 3192 3193 if (sc->stats_block != NULL) { 3194 bus_dmamem_free( 3195 sc->stats_tag, 3196 sc->stats_block, 3197 sc->stats_map); 3198 sc->stats_block = NULL; 3199 } 3200 3201 if (sc->stats_tag != NULL) { 3202 bus_dma_tag_destroy(sc->stats_tag); 3203 sc->stats_tag = NULL; 3204 } 3205 3206 /* Free, unmap and destroy all context memory pages. */ 3207 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3208 for (i = 0; i < sc->ctx_pages; i++ ) { 3209 if (sc->ctx_paddr[i] != 0) { 3210 bus_dmamap_unload( 3211 sc->ctx_tag, 3212 sc->ctx_map[i]); 3213 sc->ctx_paddr[i] = 0; 3214 } 3215 3216 if (sc->ctx_block[i] != NULL) { 3217 bus_dmamem_free( 3218 sc->ctx_tag, 3219 sc->ctx_block[i], 3220 sc->ctx_map[i]); 3221 sc->ctx_block[i] = NULL; 3222 } 3223 } 3224 3225 /* Destroy the context memory tag. */ 3226 if (sc->ctx_tag != NULL) { 3227 bus_dma_tag_destroy(sc->ctx_tag); 3228 sc->ctx_tag = NULL; 3229 } 3230 } 3231 3232 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3233 for (i = 0; i < sc->tx_pages; i++ ) { 3234 if (sc->tx_bd_chain_paddr[i] != 0) { 3235 bus_dmamap_unload( 3236 sc->tx_bd_chain_tag, 3237 sc->tx_bd_chain_map[i]); 3238 sc->tx_bd_chain_paddr[i] = 0; 3239 } 3240 3241 if (sc->tx_bd_chain[i] != NULL) { 3242 bus_dmamem_free( 3243 sc->tx_bd_chain_tag, 3244 sc->tx_bd_chain[i], 3245 sc->tx_bd_chain_map[i]); 3246 sc->tx_bd_chain[i] = NULL; 3247 } 3248 } 3249 3250 /* Destroy the TX buffer descriptor tag. */ 3251 if (sc->tx_bd_chain_tag != NULL) { 3252 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3253 sc->tx_bd_chain_tag = NULL; 3254 } 3255 3256 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3257 for (i = 0; i < sc->rx_pages; i++ ) { 3258 if (sc->rx_bd_chain_paddr[i] != 0) { 3259 bus_dmamap_unload( 3260 sc->rx_bd_chain_tag, 3261 sc->rx_bd_chain_map[i]); 3262 sc->rx_bd_chain_paddr[i] = 0; 3263 } 3264 3265 if (sc->rx_bd_chain[i] != NULL) { 3266 bus_dmamem_free( 3267 sc->rx_bd_chain_tag, 3268 sc->rx_bd_chain[i], 3269 sc->rx_bd_chain_map[i]); 3270 sc->rx_bd_chain[i] = NULL; 3271 } 3272 } 3273 3274 /* Destroy the RX buffer descriptor tag. */ 3275 if (sc->rx_bd_chain_tag != NULL) { 3276 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3277 sc->rx_bd_chain_tag = NULL; 3278 } 3279 3280 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3281 if (bce_hdr_split == TRUE) { 3282 for (i = 0; i < sc->pg_pages; i++ ) { 3283 if (sc->pg_bd_chain_paddr[i] != 0) { 3284 bus_dmamap_unload( 3285 sc->pg_bd_chain_tag, 3286 sc->pg_bd_chain_map[i]); 3287 sc->pg_bd_chain_paddr[i] = 0; 3288 } 3289 3290 if (sc->pg_bd_chain[i] != NULL) { 3291 bus_dmamem_free( 3292 sc->pg_bd_chain_tag, 3293 sc->pg_bd_chain[i], 3294 sc->pg_bd_chain_map[i]); 3295 sc->pg_bd_chain[i] = NULL; 3296 } 3297 } 3298 3299 /* Destroy the page buffer descriptor tag. */ 3300 if (sc->pg_bd_chain_tag != NULL) { 3301 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3302 sc->pg_bd_chain_tag = NULL; 3303 } 3304 } 3305 3306 /* Unload and destroy the TX mbuf maps. */ 3307 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3308 if (sc->tx_mbuf_map[i] != NULL) { 3309 bus_dmamap_unload(sc->tx_mbuf_tag, 3310 sc->tx_mbuf_map[i]); 3311 bus_dmamap_destroy(sc->tx_mbuf_tag, 3312 sc->tx_mbuf_map[i]); 3313 sc->tx_mbuf_map[i] = NULL; 3314 } 3315 } 3316 3317 /* Destroy the TX mbuf tag. */ 3318 if (sc->tx_mbuf_tag != NULL) { 3319 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3320 sc->tx_mbuf_tag = NULL; 3321 } 3322 3323 /* Unload and destroy the RX mbuf maps. */ 3324 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3325 if (sc->rx_mbuf_map[i] != NULL) { 3326 bus_dmamap_unload(sc->rx_mbuf_tag, 3327 sc->rx_mbuf_map[i]); 3328 bus_dmamap_destroy(sc->rx_mbuf_tag, 3329 sc->rx_mbuf_map[i]); 3330 sc->rx_mbuf_map[i] = NULL; 3331 } 3332 } 3333 3334 /* Destroy the RX mbuf tag. */ 3335 if (sc->rx_mbuf_tag != NULL) { 3336 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3337 sc->rx_mbuf_tag = NULL; 3338 } 3339 3340 /* Unload and destroy the page mbuf maps. */ 3341 if (bce_hdr_split == TRUE) { 3342 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3343 if (sc->pg_mbuf_map[i] != NULL) { 3344 bus_dmamap_unload(sc->pg_mbuf_tag, 3345 sc->pg_mbuf_map[i]); 3346 bus_dmamap_destroy(sc->pg_mbuf_tag, 3347 sc->pg_mbuf_map[i]); 3348 sc->pg_mbuf_map[i] = NULL; 3349 } 3350 } 3351 3352 /* Destroy the page mbuf tag. */ 3353 if (sc->pg_mbuf_tag != NULL) { 3354 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3355 sc->pg_mbuf_tag = NULL; 3356 } 3357 } 3358 3359 /* Destroy the parent tag */ 3360 if (sc->parent_tag != NULL) { 3361 bus_dma_tag_destroy(sc->parent_tag); 3362 sc->parent_tag = NULL; 3363 } 3364 3365 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3366 } 3367 3368 /****************************************************************************/ 3369 /* Get DMA memory from the OS. */ 3370 /* */ 3371 /* Validates that the OS has provided DMA buffers in response to a */ 3372 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3373 /* When the callback is used the OS will return 0 for the mapping function */ 3374 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3375 /* failures back to the caller. */ 3376 /* */ 3377 /* Returns: */ 3378 /* Nothing. */ 3379 /****************************************************************************/ 3380 static void 3381 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3382 { 3383 bus_addr_t *busaddr = arg; 3384 3385 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3386 __FUNCTION__, nseg)); 3387 /* Simulate a mapping failure. */ 3388 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3389 error = ENOMEM); 3390 3391 /* ToDo: How to increment debug sim_count variable here? */ 3392 3393 /* Check for an error and signal the caller that an error occurred. */ 3394 if (error) { 3395 *busaddr = 0; 3396 } else { 3397 *busaddr = segs->ds_addr; 3398 } 3399 } 3400 3401 /****************************************************************************/ 3402 /* Allocate any DMA memory needed by the driver. */ 3403 /* */ 3404 /* Allocates DMA memory needed for the various global structures needed by */ 3405 /* hardware. */ 3406 /* */ 3407 /* Memory alignment requirements: */ 3408 /* +-----------------+----------+----------+----------+----------+ */ 3409 /* | | 5706 | 5708 | 5709 | 5716 | */ 3410 /* +-----------------+----------+----------+----------+----------+ */ 3411 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3412 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3413 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3414 /* |PG Buffers | none | none | none | none | */ 3415 /* |TX Buffers | none | none | none | none | */ 3416 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3417 /* |Context Memory | | | | | */ 3418 /* +-----------------+----------+----------+----------+----------+ */ 3419 /* */ 3420 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3421 /* */ 3422 /* Returns: */ 3423 /* 0 for success, positive value for failure. */ 3424 /****************************************************************************/ 3425 static int 3426 bce_dma_alloc(device_t dev) 3427 { 3428 struct bce_softc *sc; 3429 int i, error, rc = 0; 3430 bus_size_t max_size, max_seg_size; 3431 int max_segments; 3432 3433 sc = device_get_softc(dev); 3434 3435 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3436 3437 /* 3438 * Allocate the parent bus DMA tag appropriate for PCI. 3439 */ 3440 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3441 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3442 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3443 &sc->parent_tag)) { 3444 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3445 __FILE__, __LINE__); 3446 rc = ENOMEM; 3447 goto bce_dma_alloc_exit; 3448 } 3449 3450 /* 3451 * Create a DMA tag for the status block, allocate and clear the 3452 * memory, map the memory into DMA space, and fetch the physical 3453 * address of the block. 3454 */ 3455 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3456 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3457 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3458 0, NULL, NULL, &sc->status_tag)) { 3459 BCE_PRINTF("%s(%d): Could not allocate status block " 3460 "DMA tag!\n", __FILE__, __LINE__); 3461 rc = ENOMEM; 3462 goto bce_dma_alloc_exit; 3463 } 3464 3465 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3466 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3467 &sc->status_map)) { 3468 BCE_PRINTF("%s(%d): Could not allocate status block " 3469 "DMA memory!\n", __FILE__, __LINE__); 3470 rc = ENOMEM; 3471 goto bce_dma_alloc_exit; 3472 } 3473 3474 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3475 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3476 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3477 3478 if (error || sc->status_block_paddr == 0) { 3479 BCE_PRINTF("%s(%d): Could not map status block " 3480 "DMA memory!\n", __FILE__, __LINE__); 3481 rc = ENOMEM; 3482 goto bce_dma_alloc_exit; 3483 } 3484 3485 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3486 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3487 3488 /* 3489 * Create a DMA tag for the statistics block, allocate and clear the 3490 * memory, map the memory into DMA space, and fetch the physical 3491 * address of the block. 3492 */ 3493 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3494 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3495 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3496 0, NULL, NULL, &sc->stats_tag)) { 3497 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3498 "DMA tag!\n", __FILE__, __LINE__); 3499 rc = ENOMEM; 3500 goto bce_dma_alloc_exit; 3501 } 3502 3503 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3504 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3505 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3506 "DMA memory!\n", __FILE__, __LINE__); 3507 rc = ENOMEM; 3508 goto bce_dma_alloc_exit; 3509 } 3510 3511 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3512 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3513 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3514 3515 if (error || sc->stats_block_paddr == 0) { 3516 BCE_PRINTF("%s(%d): Could not map statistics block " 3517 "DMA memory!\n", __FILE__, __LINE__); 3518 rc = ENOMEM; 3519 goto bce_dma_alloc_exit; 3520 } 3521 3522 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3523 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3524 3525 /* BCM5709 uses host memory as cache for context memory. */ 3526 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3527 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3528 if (sc->ctx_pages == 0) 3529 sc->ctx_pages = 1; 3530 3531 DBRUNIF((sc->ctx_pages > 512), 3532 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3533 __FILE__, __LINE__, sc->ctx_pages)); 3534 3535 /* 3536 * Create a DMA tag for the context pages, 3537 * allocate and clear the memory, map the 3538 * memory into DMA space, and fetch the 3539 * physical address of the block. 3540 */ 3541 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3542 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3543 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3544 0, NULL, NULL, &sc->ctx_tag)) { 3545 BCE_PRINTF("%s(%d): Could not allocate CTX " 3546 "DMA tag!\n", __FILE__, __LINE__); 3547 rc = ENOMEM; 3548 goto bce_dma_alloc_exit; 3549 } 3550 3551 for (i = 0; i < sc->ctx_pages; i++) { 3552 if(bus_dmamem_alloc(sc->ctx_tag, 3553 (void **)&sc->ctx_block[i], 3554 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3555 &sc->ctx_map[i])) { 3556 BCE_PRINTF("%s(%d): Could not allocate CTX " 3557 "DMA memory!\n", __FILE__, __LINE__); 3558 rc = ENOMEM; 3559 goto bce_dma_alloc_exit; 3560 } 3561 3562 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3563 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3564 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3565 3566 if (error || sc->ctx_paddr[i] == 0) { 3567 BCE_PRINTF("%s(%d): Could not map CTX " 3568 "DMA memory!\n", __FILE__, __LINE__); 3569 rc = ENOMEM; 3570 goto bce_dma_alloc_exit; 3571 } 3572 3573 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3574 "= 0x%jX\n", __FUNCTION__, i, 3575 (uintmax_t) sc->ctx_paddr[i]); 3576 } 3577 } 3578 3579 /* 3580 * Create a DMA tag for the TX buffer descriptor chain, 3581 * allocate and clear the memory, and fetch the 3582 * physical address of the block. 3583 */ 3584 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3585 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3586 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3587 NULL, NULL, &sc->tx_bd_chain_tag)) { 3588 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3589 "chain DMA tag!\n", __FILE__, __LINE__); 3590 rc = ENOMEM; 3591 goto bce_dma_alloc_exit; 3592 } 3593 3594 for (i = 0; i < sc->tx_pages; i++) { 3595 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3596 (void **)&sc->tx_bd_chain[i], 3597 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3598 &sc->tx_bd_chain_map[i])) { 3599 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3600 "chain DMA memory!\n", __FILE__, __LINE__); 3601 rc = ENOMEM; 3602 goto bce_dma_alloc_exit; 3603 } 3604 3605 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3606 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3607 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3608 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3609 3610 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3611 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3612 "chain DMA memory!\n", __FILE__, __LINE__); 3613 rc = ENOMEM; 3614 goto bce_dma_alloc_exit; 3615 } 3616 3617 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3618 "0x%jX\n", __FUNCTION__, i, 3619 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3620 } 3621 3622 /* Check the required size before mapping to conserve resources. */ 3623 if (bce_tso_enable) { 3624 max_size = BCE_TSO_MAX_SIZE; 3625 max_segments = BCE_MAX_SEGMENTS; 3626 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3627 } else { 3628 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3629 max_segments = BCE_MAX_SEGMENTS; 3630 max_seg_size = MCLBYTES; 3631 } 3632 3633 /* Create a DMA tag for TX mbufs. */ 3634 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3635 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3636 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3637 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3638 __FILE__, __LINE__); 3639 rc = ENOMEM; 3640 goto bce_dma_alloc_exit; 3641 } 3642 3643 /* Create DMA maps for the TX mbufs clusters. */ 3644 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3645 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3646 &sc->tx_mbuf_map[i])) { 3647 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3648 "map!\n", __FILE__, __LINE__); 3649 rc = ENOMEM; 3650 goto bce_dma_alloc_exit; 3651 } 3652 } 3653 3654 /* 3655 * Create a DMA tag for the RX buffer descriptor chain, 3656 * allocate and clear the memory, and fetch the physical 3657 * address of the blocks. 3658 */ 3659 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3660 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3661 sc->max_bus_addr, NULL, NULL, 3662 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3663 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3664 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3665 "DMA tag!\n", __FILE__, __LINE__); 3666 rc = ENOMEM; 3667 goto bce_dma_alloc_exit; 3668 } 3669 3670 for (i = 0; i < sc->rx_pages; i++) { 3671 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3672 (void **)&sc->rx_bd_chain[i], 3673 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3674 &sc->rx_bd_chain_map[i])) { 3675 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3676 "chain DMA memory!\n", __FILE__, __LINE__); 3677 rc = ENOMEM; 3678 goto bce_dma_alloc_exit; 3679 } 3680 3681 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3682 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3683 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3684 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3685 3686 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3687 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3688 "chain DMA memory!\n", __FILE__, __LINE__); 3689 rc = ENOMEM; 3690 goto bce_dma_alloc_exit; 3691 } 3692 3693 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3694 "0x%jX\n", __FUNCTION__, i, 3695 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3696 } 3697 3698 /* 3699 * Create a DMA tag for RX mbufs. 3700 */ 3701 if (bce_hdr_split == TRUE) 3702 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3703 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3704 else 3705 max_size = MJUM9BYTES; 3706 3707 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3708 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3709 3710 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3711 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3712 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3713 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3714 __FILE__, __LINE__); 3715 rc = ENOMEM; 3716 goto bce_dma_alloc_exit; 3717 } 3718 3719 /* Create DMA maps for the RX mbuf clusters. */ 3720 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3721 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3722 &sc->rx_mbuf_map[i])) { 3723 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3724 "DMA map!\n", __FILE__, __LINE__); 3725 rc = ENOMEM; 3726 goto bce_dma_alloc_exit; 3727 } 3728 } 3729 3730 if (bce_hdr_split == TRUE) { 3731 /* 3732 * Create a DMA tag for the page buffer descriptor chain, 3733 * allocate and clear the memory, and fetch the physical 3734 * address of the blocks. 3735 */ 3736 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3737 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3738 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3739 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3740 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3741 "chain DMA tag!\n", __FILE__, __LINE__); 3742 rc = ENOMEM; 3743 goto bce_dma_alloc_exit; 3744 } 3745 3746 for (i = 0; i < sc->pg_pages; i++) { 3747 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3748 (void **)&sc->pg_bd_chain[i], 3749 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3750 &sc->pg_bd_chain_map[i])) { 3751 BCE_PRINTF("%s(%d): Could not allocate page " 3752 "descriptor chain DMA memory!\n", 3753 __FILE__, __LINE__); 3754 rc = ENOMEM; 3755 goto bce_dma_alloc_exit; 3756 } 3757 3758 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3759 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3760 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3761 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3762 3763 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3764 BCE_PRINTF("%s(%d): Could not map page descriptor " 3765 "chain DMA memory!\n", __FILE__, __LINE__); 3766 rc = ENOMEM; 3767 goto bce_dma_alloc_exit; 3768 } 3769 3770 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3771 "0x%jX\n", __FUNCTION__, i, 3772 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3773 } 3774 3775 /* 3776 * Create a DMA tag for page mbufs. 3777 */ 3778 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3779 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3780 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3781 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3782 "DMA tag!\n", __FILE__, __LINE__); 3783 rc = ENOMEM; 3784 goto bce_dma_alloc_exit; 3785 } 3786 3787 /* Create DMA maps for the page mbuf clusters. */ 3788 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3789 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3790 &sc->pg_mbuf_map[i])) { 3791 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3792 "DMA map!\n", __FILE__, __LINE__); 3793 rc = ENOMEM; 3794 goto bce_dma_alloc_exit; 3795 } 3796 } 3797 } 3798 3799 bce_dma_alloc_exit: 3800 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3801 return(rc); 3802 } 3803 3804 /****************************************************************************/ 3805 /* Release all resources used by the driver. */ 3806 /* */ 3807 /* Releases all resources acquired by the driver including interrupts, */ 3808 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3809 /* */ 3810 /* Returns: */ 3811 /* Nothing. */ 3812 /****************************************************************************/ 3813 static void 3814 bce_release_resources(struct bce_softc *sc) 3815 { 3816 device_t dev; 3817 3818 DBENTER(BCE_VERBOSE_RESET); 3819 3820 dev = sc->bce_dev; 3821 3822 bce_dma_free(sc); 3823 3824 if (sc->bce_intrhand != NULL) { 3825 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3826 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3827 } 3828 3829 if (sc->bce_res_irq != NULL) { 3830 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3831 bus_release_resource(dev, SYS_RES_IRQ, 3832 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3833 } 3834 3835 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3836 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3837 pci_release_msi(dev); 3838 } 3839 3840 if (sc->bce_res_mem != NULL) { 3841 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3842 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3843 sc->bce_res_mem); 3844 } 3845 3846 if (sc->bce_ifp != NULL) { 3847 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3848 if_free(sc->bce_ifp); 3849 } 3850 3851 if (mtx_initialized(&sc->bce_mtx)) 3852 BCE_LOCK_DESTROY(sc); 3853 3854 DBEXIT(BCE_VERBOSE_RESET); 3855 } 3856 3857 /****************************************************************************/ 3858 /* Firmware synchronization. */ 3859 /* */ 3860 /* Before performing certain events such as a chip reset, synchronize with */ 3861 /* the firmware first. */ 3862 /* */ 3863 /* Returns: */ 3864 /* 0 for success, positive value for failure. */ 3865 /****************************************************************************/ 3866 static int 3867 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3868 { 3869 int i, rc = 0; 3870 u32 val; 3871 3872 DBENTER(BCE_VERBOSE_RESET); 3873 3874 /* Don't waste any time if we've timed out before. */ 3875 if (sc->bce_fw_timed_out == TRUE) { 3876 rc = EBUSY; 3877 goto bce_fw_sync_exit; 3878 } 3879 3880 /* Increment the message sequence number. */ 3881 sc->bce_fw_wr_seq++; 3882 msg_data |= sc->bce_fw_wr_seq; 3883 3884 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3885 "0x%08X\n", msg_data); 3886 3887 /* Send the message to the bootcode driver mailbox. */ 3888 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3889 3890 /* Wait for the bootcode to acknowledge the message. */ 3891 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3892 /* Check for a response in the bootcode firmware mailbox. */ 3893 val = bce_shmem_rd(sc, BCE_FW_MB); 3894 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3895 break; 3896 DELAY(1000); 3897 } 3898 3899 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3900 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3901 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3902 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3903 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3904 3905 msg_data &= ~BCE_DRV_MSG_CODE; 3906 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3907 3908 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3909 3910 sc->bce_fw_timed_out = TRUE; 3911 rc = EBUSY; 3912 } 3913 3914 bce_fw_sync_exit: 3915 DBEXIT(BCE_VERBOSE_RESET); 3916 return (rc); 3917 } 3918 3919 /****************************************************************************/ 3920 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3921 /* */ 3922 /* Returns: */ 3923 /* Nothing. */ 3924 /****************************************************************************/ 3925 static void 3926 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 3927 u32 rv2p_code_len, u32 rv2p_proc) 3928 { 3929 int i; 3930 u32 val; 3931 3932 DBENTER(BCE_VERBOSE_RESET); 3933 3934 /* Set the page size used by RV2P. */ 3935 if (rv2p_proc == RV2P_PROC2) { 3936 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3937 } 3938 3939 for (i = 0; i < rv2p_code_len; i += 8) { 3940 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3941 rv2p_code++; 3942 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3943 rv2p_code++; 3944 3945 if (rv2p_proc == RV2P_PROC1) { 3946 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3947 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3948 } 3949 else { 3950 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3951 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3952 } 3953 } 3954 3955 /* Reset the processor, un-stall is done later. */ 3956 if (rv2p_proc == RV2P_PROC1) { 3957 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3958 } 3959 else { 3960 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3961 } 3962 3963 DBEXIT(BCE_VERBOSE_RESET); 3964 } 3965 3966 /****************************************************************************/ 3967 /* Load RISC processor firmware. */ 3968 /* */ 3969 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3970 /* associated with a particular processor. */ 3971 /* */ 3972 /* Returns: */ 3973 /* Nothing. */ 3974 /****************************************************************************/ 3975 static void 3976 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3977 struct fw_info *fw) 3978 { 3979 u32 offset; 3980 3981 DBENTER(BCE_VERBOSE_RESET); 3982 3983 bce_halt_cpu(sc, cpu_reg); 3984 3985 /* Load the Text area. */ 3986 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 3987 if (fw->text) { 3988 int j; 3989 3990 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 3991 REG_WR_IND(sc, offset, fw->text[j]); 3992 } 3993 } 3994 3995 /* Load the Data area. */ 3996 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 3997 if (fw->data) { 3998 int j; 3999 4000 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4001 REG_WR_IND(sc, offset, fw->data[j]); 4002 } 4003 } 4004 4005 /* Load the SBSS area. */ 4006 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4007 if (fw->sbss) { 4008 int j; 4009 4010 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4011 REG_WR_IND(sc, offset, fw->sbss[j]); 4012 } 4013 } 4014 4015 /* Load the BSS area. */ 4016 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4017 if (fw->bss) { 4018 int j; 4019 4020 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4021 REG_WR_IND(sc, offset, fw->bss[j]); 4022 } 4023 } 4024 4025 /* Load the Read-Only area. */ 4026 offset = cpu_reg->spad_base + 4027 (fw->rodata_addr - cpu_reg->mips_view_base); 4028 if (fw->rodata) { 4029 int j; 4030 4031 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4032 REG_WR_IND(sc, offset, fw->rodata[j]); 4033 } 4034 } 4035 4036 /* Clear the pre-fetch instruction and set the FW start address. */ 4037 REG_WR_IND(sc, cpu_reg->inst, 0); 4038 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4039 4040 DBEXIT(BCE_VERBOSE_RESET); 4041 } 4042 4043 /****************************************************************************/ 4044 /* Starts the RISC processor. */ 4045 /* */ 4046 /* Assumes the CPU starting address has already been set. */ 4047 /* */ 4048 /* Returns: */ 4049 /* Nothing. */ 4050 /****************************************************************************/ 4051 static void 4052 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4053 { 4054 u32 val; 4055 4056 DBENTER(BCE_VERBOSE_RESET); 4057 4058 /* Start the CPU. */ 4059 val = REG_RD_IND(sc, cpu_reg->mode); 4060 val &= ~cpu_reg->mode_value_halt; 4061 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4062 REG_WR_IND(sc, cpu_reg->mode, val); 4063 4064 DBEXIT(BCE_VERBOSE_RESET); 4065 } 4066 4067 /****************************************************************************/ 4068 /* Halts the RISC processor. */ 4069 /* */ 4070 /* Returns: */ 4071 /* Nothing. */ 4072 /****************************************************************************/ 4073 static void 4074 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4075 { 4076 u32 val; 4077 4078 DBENTER(BCE_VERBOSE_RESET); 4079 4080 /* Halt the CPU. */ 4081 val = REG_RD_IND(sc, cpu_reg->mode); 4082 val |= cpu_reg->mode_value_halt; 4083 REG_WR_IND(sc, cpu_reg->mode, val); 4084 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4085 4086 DBEXIT(BCE_VERBOSE_RESET); 4087 } 4088 4089 /****************************************************************************/ 4090 /* Initialize the RX CPU. */ 4091 /* */ 4092 /* Returns: */ 4093 /* Nothing. */ 4094 /****************************************************************************/ 4095 static void 4096 bce_start_rxp_cpu(struct bce_softc *sc) 4097 { 4098 struct cpu_reg cpu_reg; 4099 4100 DBENTER(BCE_VERBOSE_RESET); 4101 4102 cpu_reg.mode = BCE_RXP_CPU_MODE; 4103 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4104 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4105 cpu_reg.state = BCE_RXP_CPU_STATE; 4106 cpu_reg.state_value_clear = 0xffffff; 4107 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4108 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4109 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4110 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4111 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4112 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4113 cpu_reg.mips_view_base = 0x8000000; 4114 4115 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4116 bce_start_cpu(sc, &cpu_reg); 4117 4118 DBEXIT(BCE_VERBOSE_RESET); 4119 } 4120 4121 /****************************************************************************/ 4122 /* Initialize the RX CPU. */ 4123 /* */ 4124 /* Returns: */ 4125 /* Nothing. */ 4126 /****************************************************************************/ 4127 static void 4128 bce_init_rxp_cpu(struct bce_softc *sc) 4129 { 4130 struct cpu_reg cpu_reg; 4131 struct fw_info fw; 4132 4133 DBENTER(BCE_VERBOSE_RESET); 4134 4135 cpu_reg.mode = BCE_RXP_CPU_MODE; 4136 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4137 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4138 cpu_reg.state = BCE_RXP_CPU_STATE; 4139 cpu_reg.state_value_clear = 0xffffff; 4140 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4141 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4142 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4143 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4144 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4145 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4146 cpu_reg.mips_view_base = 0x8000000; 4147 4148 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4149 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4150 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4151 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4152 fw.start_addr = bce_RXP_b09FwStartAddr; 4153 4154 fw.text_addr = bce_RXP_b09FwTextAddr; 4155 fw.text_len = bce_RXP_b09FwTextLen; 4156 fw.text_index = 0; 4157 fw.text = bce_RXP_b09FwText; 4158 4159 fw.data_addr = bce_RXP_b09FwDataAddr; 4160 fw.data_len = bce_RXP_b09FwDataLen; 4161 fw.data_index = 0; 4162 fw.data = bce_RXP_b09FwData; 4163 4164 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4165 fw.sbss_len = bce_RXP_b09FwSbssLen; 4166 fw.sbss_index = 0; 4167 fw.sbss = bce_RXP_b09FwSbss; 4168 4169 fw.bss_addr = bce_RXP_b09FwBssAddr; 4170 fw.bss_len = bce_RXP_b09FwBssLen; 4171 fw.bss_index = 0; 4172 fw.bss = bce_RXP_b09FwBss; 4173 4174 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4175 fw.rodata_len = bce_RXP_b09FwRodataLen; 4176 fw.rodata_index = 0; 4177 fw.rodata = bce_RXP_b09FwRodata; 4178 } else { 4179 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4180 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4181 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4182 fw.start_addr = bce_RXP_b06FwStartAddr; 4183 4184 fw.text_addr = bce_RXP_b06FwTextAddr; 4185 fw.text_len = bce_RXP_b06FwTextLen; 4186 fw.text_index = 0; 4187 fw.text = bce_RXP_b06FwText; 4188 4189 fw.data_addr = bce_RXP_b06FwDataAddr; 4190 fw.data_len = bce_RXP_b06FwDataLen; 4191 fw.data_index = 0; 4192 fw.data = bce_RXP_b06FwData; 4193 4194 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4195 fw.sbss_len = bce_RXP_b06FwSbssLen; 4196 fw.sbss_index = 0; 4197 fw.sbss = bce_RXP_b06FwSbss; 4198 4199 fw.bss_addr = bce_RXP_b06FwBssAddr; 4200 fw.bss_len = bce_RXP_b06FwBssLen; 4201 fw.bss_index = 0; 4202 fw.bss = bce_RXP_b06FwBss; 4203 4204 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4205 fw.rodata_len = bce_RXP_b06FwRodataLen; 4206 fw.rodata_index = 0; 4207 fw.rodata = bce_RXP_b06FwRodata; 4208 } 4209 4210 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4211 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4212 4213 /* Delay RXP start until initialization is complete. */ 4214 4215 DBEXIT(BCE_VERBOSE_RESET); 4216 } 4217 4218 /****************************************************************************/ 4219 /* Initialize the TX CPU. */ 4220 /* */ 4221 /* Returns: */ 4222 /* Nothing. */ 4223 /****************************************************************************/ 4224 static void 4225 bce_init_txp_cpu(struct bce_softc *sc) 4226 { 4227 struct cpu_reg cpu_reg; 4228 struct fw_info fw; 4229 4230 DBENTER(BCE_VERBOSE_RESET); 4231 4232 cpu_reg.mode = BCE_TXP_CPU_MODE; 4233 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4234 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4235 cpu_reg.state = BCE_TXP_CPU_STATE; 4236 cpu_reg.state_value_clear = 0xffffff; 4237 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4238 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4239 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4240 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4241 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4242 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4243 cpu_reg.mips_view_base = 0x8000000; 4244 4245 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4246 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4247 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4248 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4249 fw.start_addr = bce_TXP_b09FwStartAddr; 4250 4251 fw.text_addr = bce_TXP_b09FwTextAddr; 4252 fw.text_len = bce_TXP_b09FwTextLen; 4253 fw.text_index = 0; 4254 fw.text = bce_TXP_b09FwText; 4255 4256 fw.data_addr = bce_TXP_b09FwDataAddr; 4257 fw.data_len = bce_TXP_b09FwDataLen; 4258 fw.data_index = 0; 4259 fw.data = bce_TXP_b09FwData; 4260 4261 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4262 fw.sbss_len = bce_TXP_b09FwSbssLen; 4263 fw.sbss_index = 0; 4264 fw.sbss = bce_TXP_b09FwSbss; 4265 4266 fw.bss_addr = bce_TXP_b09FwBssAddr; 4267 fw.bss_len = bce_TXP_b09FwBssLen; 4268 fw.bss_index = 0; 4269 fw.bss = bce_TXP_b09FwBss; 4270 4271 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4272 fw.rodata_len = bce_TXP_b09FwRodataLen; 4273 fw.rodata_index = 0; 4274 fw.rodata = bce_TXP_b09FwRodata; 4275 } else { 4276 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4277 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4278 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4279 fw.start_addr = bce_TXP_b06FwStartAddr; 4280 4281 fw.text_addr = bce_TXP_b06FwTextAddr; 4282 fw.text_len = bce_TXP_b06FwTextLen; 4283 fw.text_index = 0; 4284 fw.text = bce_TXP_b06FwText; 4285 4286 fw.data_addr = bce_TXP_b06FwDataAddr; 4287 fw.data_len = bce_TXP_b06FwDataLen; 4288 fw.data_index = 0; 4289 fw.data = bce_TXP_b06FwData; 4290 4291 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4292 fw.sbss_len = bce_TXP_b06FwSbssLen; 4293 fw.sbss_index = 0; 4294 fw.sbss = bce_TXP_b06FwSbss; 4295 4296 fw.bss_addr = bce_TXP_b06FwBssAddr; 4297 fw.bss_len = bce_TXP_b06FwBssLen; 4298 fw.bss_index = 0; 4299 fw.bss = bce_TXP_b06FwBss; 4300 4301 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4302 fw.rodata_len = bce_TXP_b06FwRodataLen; 4303 fw.rodata_index = 0; 4304 fw.rodata = bce_TXP_b06FwRodata; 4305 } 4306 4307 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4308 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4309 bce_start_cpu(sc, &cpu_reg); 4310 4311 DBEXIT(BCE_VERBOSE_RESET); 4312 } 4313 4314 /****************************************************************************/ 4315 /* Initialize the TPAT CPU. */ 4316 /* */ 4317 /* Returns: */ 4318 /* Nothing. */ 4319 /****************************************************************************/ 4320 static void 4321 bce_init_tpat_cpu(struct bce_softc *sc) 4322 { 4323 struct cpu_reg cpu_reg; 4324 struct fw_info fw; 4325 4326 DBENTER(BCE_VERBOSE_RESET); 4327 4328 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4329 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4330 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4331 cpu_reg.state = BCE_TPAT_CPU_STATE; 4332 cpu_reg.state_value_clear = 0xffffff; 4333 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4334 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4335 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4336 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4337 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4338 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4339 cpu_reg.mips_view_base = 0x8000000; 4340 4341 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4342 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4343 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4344 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4345 fw.start_addr = bce_TPAT_b09FwStartAddr; 4346 4347 fw.text_addr = bce_TPAT_b09FwTextAddr; 4348 fw.text_len = bce_TPAT_b09FwTextLen; 4349 fw.text_index = 0; 4350 fw.text = bce_TPAT_b09FwText; 4351 4352 fw.data_addr = bce_TPAT_b09FwDataAddr; 4353 fw.data_len = bce_TPAT_b09FwDataLen; 4354 fw.data_index = 0; 4355 fw.data = bce_TPAT_b09FwData; 4356 4357 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4358 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4359 fw.sbss_index = 0; 4360 fw.sbss = bce_TPAT_b09FwSbss; 4361 4362 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4363 fw.bss_len = bce_TPAT_b09FwBssLen; 4364 fw.bss_index = 0; 4365 fw.bss = bce_TPAT_b09FwBss; 4366 4367 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4368 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4369 fw.rodata_index = 0; 4370 fw.rodata = bce_TPAT_b09FwRodata; 4371 } else { 4372 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4373 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4374 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4375 fw.start_addr = bce_TPAT_b06FwStartAddr; 4376 4377 fw.text_addr = bce_TPAT_b06FwTextAddr; 4378 fw.text_len = bce_TPAT_b06FwTextLen; 4379 fw.text_index = 0; 4380 fw.text = bce_TPAT_b06FwText; 4381 4382 fw.data_addr = bce_TPAT_b06FwDataAddr; 4383 fw.data_len = bce_TPAT_b06FwDataLen; 4384 fw.data_index = 0; 4385 fw.data = bce_TPAT_b06FwData; 4386 4387 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4388 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4389 fw.sbss_index = 0; 4390 fw.sbss = bce_TPAT_b06FwSbss; 4391 4392 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4393 fw.bss_len = bce_TPAT_b06FwBssLen; 4394 fw.bss_index = 0; 4395 fw.bss = bce_TPAT_b06FwBss; 4396 4397 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4398 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4399 fw.rodata_index = 0; 4400 fw.rodata = bce_TPAT_b06FwRodata; 4401 } 4402 4403 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4404 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4405 bce_start_cpu(sc, &cpu_reg); 4406 4407 DBEXIT(BCE_VERBOSE_RESET); 4408 } 4409 4410 /****************************************************************************/ 4411 /* Initialize the CP CPU. */ 4412 /* */ 4413 /* Returns: */ 4414 /* Nothing. */ 4415 /****************************************************************************/ 4416 static void 4417 bce_init_cp_cpu(struct bce_softc *sc) 4418 { 4419 struct cpu_reg cpu_reg; 4420 struct fw_info fw; 4421 4422 DBENTER(BCE_VERBOSE_RESET); 4423 4424 cpu_reg.mode = BCE_CP_CPU_MODE; 4425 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4426 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4427 cpu_reg.state = BCE_CP_CPU_STATE; 4428 cpu_reg.state_value_clear = 0xffffff; 4429 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4430 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4431 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4432 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4433 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4434 cpu_reg.spad_base = BCE_CP_SCRATCH; 4435 cpu_reg.mips_view_base = 0x8000000; 4436 4437 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4438 fw.ver_major = bce_CP_b09FwReleaseMajor; 4439 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4440 fw.ver_fix = bce_CP_b09FwReleaseFix; 4441 fw.start_addr = bce_CP_b09FwStartAddr; 4442 4443 fw.text_addr = bce_CP_b09FwTextAddr; 4444 fw.text_len = bce_CP_b09FwTextLen; 4445 fw.text_index = 0; 4446 fw.text = bce_CP_b09FwText; 4447 4448 fw.data_addr = bce_CP_b09FwDataAddr; 4449 fw.data_len = bce_CP_b09FwDataLen; 4450 fw.data_index = 0; 4451 fw.data = bce_CP_b09FwData; 4452 4453 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4454 fw.sbss_len = bce_CP_b09FwSbssLen; 4455 fw.sbss_index = 0; 4456 fw.sbss = bce_CP_b09FwSbss; 4457 4458 fw.bss_addr = bce_CP_b09FwBssAddr; 4459 fw.bss_len = bce_CP_b09FwBssLen; 4460 fw.bss_index = 0; 4461 fw.bss = bce_CP_b09FwBss; 4462 4463 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4464 fw.rodata_len = bce_CP_b09FwRodataLen; 4465 fw.rodata_index = 0; 4466 fw.rodata = bce_CP_b09FwRodata; 4467 } else { 4468 fw.ver_major = bce_CP_b06FwReleaseMajor; 4469 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4470 fw.ver_fix = bce_CP_b06FwReleaseFix; 4471 fw.start_addr = bce_CP_b06FwStartAddr; 4472 4473 fw.text_addr = bce_CP_b06FwTextAddr; 4474 fw.text_len = bce_CP_b06FwTextLen; 4475 fw.text_index = 0; 4476 fw.text = bce_CP_b06FwText; 4477 4478 fw.data_addr = bce_CP_b06FwDataAddr; 4479 fw.data_len = bce_CP_b06FwDataLen; 4480 fw.data_index = 0; 4481 fw.data = bce_CP_b06FwData; 4482 4483 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4484 fw.sbss_len = bce_CP_b06FwSbssLen; 4485 fw.sbss_index = 0; 4486 fw.sbss = bce_CP_b06FwSbss; 4487 4488 fw.bss_addr = bce_CP_b06FwBssAddr; 4489 fw.bss_len = bce_CP_b06FwBssLen; 4490 fw.bss_index = 0; 4491 fw.bss = bce_CP_b06FwBss; 4492 4493 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4494 fw.rodata_len = bce_CP_b06FwRodataLen; 4495 fw.rodata_index = 0; 4496 fw.rodata = bce_CP_b06FwRodata; 4497 } 4498 4499 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4500 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4501 bce_start_cpu(sc, &cpu_reg); 4502 4503 DBEXIT(BCE_VERBOSE_RESET); 4504 } 4505 4506 /****************************************************************************/ 4507 /* Initialize the COM CPU. */ 4508 /* */ 4509 /* Returns: */ 4510 /* Nothing. */ 4511 /****************************************************************************/ 4512 static void 4513 bce_init_com_cpu(struct bce_softc *sc) 4514 { 4515 struct cpu_reg cpu_reg; 4516 struct fw_info fw; 4517 4518 DBENTER(BCE_VERBOSE_RESET); 4519 4520 cpu_reg.mode = BCE_COM_CPU_MODE; 4521 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4522 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4523 cpu_reg.state = BCE_COM_CPU_STATE; 4524 cpu_reg.state_value_clear = 0xffffff; 4525 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4526 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4527 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4528 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4529 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4530 cpu_reg.spad_base = BCE_COM_SCRATCH; 4531 cpu_reg.mips_view_base = 0x8000000; 4532 4533 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4534 fw.ver_major = bce_COM_b09FwReleaseMajor; 4535 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4536 fw.ver_fix = bce_COM_b09FwReleaseFix; 4537 fw.start_addr = bce_COM_b09FwStartAddr; 4538 4539 fw.text_addr = bce_COM_b09FwTextAddr; 4540 fw.text_len = bce_COM_b09FwTextLen; 4541 fw.text_index = 0; 4542 fw.text = bce_COM_b09FwText; 4543 4544 fw.data_addr = bce_COM_b09FwDataAddr; 4545 fw.data_len = bce_COM_b09FwDataLen; 4546 fw.data_index = 0; 4547 fw.data = bce_COM_b09FwData; 4548 4549 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4550 fw.sbss_len = bce_COM_b09FwSbssLen; 4551 fw.sbss_index = 0; 4552 fw.sbss = bce_COM_b09FwSbss; 4553 4554 fw.bss_addr = bce_COM_b09FwBssAddr; 4555 fw.bss_len = bce_COM_b09FwBssLen; 4556 fw.bss_index = 0; 4557 fw.bss = bce_COM_b09FwBss; 4558 4559 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4560 fw.rodata_len = bce_COM_b09FwRodataLen; 4561 fw.rodata_index = 0; 4562 fw.rodata = bce_COM_b09FwRodata; 4563 } else { 4564 fw.ver_major = bce_COM_b06FwReleaseMajor; 4565 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4566 fw.ver_fix = bce_COM_b06FwReleaseFix; 4567 fw.start_addr = bce_COM_b06FwStartAddr; 4568 4569 fw.text_addr = bce_COM_b06FwTextAddr; 4570 fw.text_len = bce_COM_b06FwTextLen; 4571 fw.text_index = 0; 4572 fw.text = bce_COM_b06FwText; 4573 4574 fw.data_addr = bce_COM_b06FwDataAddr; 4575 fw.data_len = bce_COM_b06FwDataLen; 4576 fw.data_index = 0; 4577 fw.data = bce_COM_b06FwData; 4578 4579 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4580 fw.sbss_len = bce_COM_b06FwSbssLen; 4581 fw.sbss_index = 0; 4582 fw.sbss = bce_COM_b06FwSbss; 4583 4584 fw.bss_addr = bce_COM_b06FwBssAddr; 4585 fw.bss_len = bce_COM_b06FwBssLen; 4586 fw.bss_index = 0; 4587 fw.bss = bce_COM_b06FwBss; 4588 4589 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4590 fw.rodata_len = bce_COM_b06FwRodataLen; 4591 fw.rodata_index = 0; 4592 fw.rodata = bce_COM_b06FwRodata; 4593 } 4594 4595 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4596 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4597 bce_start_cpu(sc, &cpu_reg); 4598 4599 DBEXIT(BCE_VERBOSE_RESET); 4600 } 4601 4602 /****************************************************************************/ 4603 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4604 /* */ 4605 /* Loads the firmware for each CPU and starts the CPU. */ 4606 /* */ 4607 /* Returns: */ 4608 /* Nothing. */ 4609 /****************************************************************************/ 4610 static void 4611 bce_init_cpus(struct bce_softc *sc) 4612 { 4613 DBENTER(BCE_VERBOSE_RESET); 4614 4615 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4616 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4617 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4618 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4619 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4620 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4621 } else { 4622 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4623 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4624 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4625 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4626 } 4627 4628 } else { 4629 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4630 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4631 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4632 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4633 } 4634 4635 bce_init_rxp_cpu(sc); 4636 bce_init_txp_cpu(sc); 4637 bce_init_tpat_cpu(sc); 4638 bce_init_com_cpu(sc); 4639 bce_init_cp_cpu(sc); 4640 4641 DBEXIT(BCE_VERBOSE_RESET); 4642 } 4643 4644 /****************************************************************************/ 4645 /* Initialize context memory. */ 4646 /* */ 4647 /* Clears the memory associated with each Context ID (CID). */ 4648 /* */ 4649 /* Returns: */ 4650 /* Nothing. */ 4651 /****************************************************************************/ 4652 static int 4653 bce_init_ctx(struct bce_softc *sc) 4654 { 4655 u32 offset, val, vcid_addr; 4656 int i, j, rc, retry_cnt; 4657 4658 rc = 0; 4659 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4660 4661 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4662 retry_cnt = CTX_INIT_RETRY_COUNT; 4663 4664 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4665 4666 /* 4667 * BCM5709 context memory may be cached 4668 * in host memory so prepare the host memory 4669 * for access. 4670 */ 4671 val = BCE_CTX_COMMAND_ENABLED | 4672 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4673 val |= (BCM_PAGE_BITS - 8) << 16; 4674 REG_WR(sc, BCE_CTX_COMMAND, val); 4675 4676 /* Wait for mem init command to complete. */ 4677 for (i = 0; i < retry_cnt; i++) { 4678 val = REG_RD(sc, BCE_CTX_COMMAND); 4679 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4680 break; 4681 DELAY(2); 4682 } 4683 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4684 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4685 __FUNCTION__); 4686 rc = EBUSY; 4687 goto init_ctx_fail; 4688 } 4689 4690 for (i = 0; i < sc->ctx_pages; i++) { 4691 /* Set the physical address of the context memory. */ 4692 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4693 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4694 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4695 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4696 BCE_ADDR_HI(sc->ctx_paddr[i])); 4697 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4698 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4699 4700 /* Verify the context memory write was successful. */ 4701 for (j = 0; j < retry_cnt; j++) { 4702 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4703 if ((val & 4704 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4705 break; 4706 DELAY(5); 4707 } 4708 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4709 BCE_PRINTF("%s(): Failed to initialize " 4710 "context page %d!\n", __FUNCTION__, i); 4711 rc = EBUSY; 4712 goto init_ctx_fail; 4713 } 4714 } 4715 } else { 4716 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4717 4718 /* 4719 * For the 5706/5708, context memory is local to 4720 * the controller, so initialize the controller 4721 * context memory. 4722 */ 4723 4724 vcid_addr = GET_CID_ADDR(96); 4725 while (vcid_addr) { 4726 vcid_addr -= PHY_CTX_SIZE; 4727 4728 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4729 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4730 4731 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4732 CTX_WR(sc, 0x00, offset, 0); 4733 } 4734 4735 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4736 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4737 } 4738 } 4739 init_ctx_fail: 4740 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4741 return (rc); 4742 } 4743 4744 /****************************************************************************/ 4745 /* Fetch the permanent MAC address of the controller. */ 4746 /* */ 4747 /* Returns: */ 4748 /* Nothing. */ 4749 /****************************************************************************/ 4750 static void 4751 bce_get_mac_addr(struct bce_softc *sc) 4752 { 4753 u32 mac_lo = 0, mac_hi = 0; 4754 4755 DBENTER(BCE_VERBOSE_RESET); 4756 4757 /* 4758 * The NetXtreme II bootcode populates various NIC 4759 * power-on and runtime configuration items in a 4760 * shared memory area. The factory configured MAC 4761 * address is available from both NVRAM and the 4762 * shared memory area so we'll read the value from 4763 * shared memory for speed. 4764 */ 4765 4766 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4767 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4768 4769 if ((mac_lo == 0) && (mac_hi == 0)) { 4770 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4771 __FILE__, __LINE__); 4772 } else { 4773 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4774 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4775 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4776 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4777 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4778 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4779 } 4780 4781 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4782 "address = %6D\n", sc->eaddr, ":"); 4783 DBEXIT(BCE_VERBOSE_RESET); 4784 } 4785 4786 /****************************************************************************/ 4787 /* Program the MAC address. */ 4788 /* */ 4789 /* Returns: */ 4790 /* Nothing. */ 4791 /****************************************************************************/ 4792 static void 4793 bce_set_mac_addr(struct bce_softc *sc) 4794 { 4795 u32 val; 4796 u8 *mac_addr = sc->eaddr; 4797 4798 /* ToDo: Add support for setting multiple MAC addresses. */ 4799 4800 DBENTER(BCE_VERBOSE_RESET); 4801 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4802 "%6D\n", sc->eaddr, ":"); 4803 4804 val = (mac_addr[0] << 8) | mac_addr[1]; 4805 4806 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4807 4808 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4809 (mac_addr[4] << 8) | mac_addr[5]; 4810 4811 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4812 4813 DBEXIT(BCE_VERBOSE_RESET); 4814 } 4815 4816 /****************************************************************************/ 4817 /* Stop the controller. */ 4818 /* */ 4819 /* Returns: */ 4820 /* Nothing. */ 4821 /****************************************************************************/ 4822 static void 4823 bce_stop(struct bce_softc *sc) 4824 { 4825 if_t ifp; 4826 4827 DBENTER(BCE_VERBOSE_RESET); 4828 4829 BCE_LOCK_ASSERT(sc); 4830 4831 ifp = sc->bce_ifp; 4832 4833 callout_stop(&sc->bce_tick_callout); 4834 4835 /* Disable the transmit/receive blocks. */ 4836 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4837 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4838 DELAY(20); 4839 4840 bce_disable_intr(sc); 4841 4842 /* Free RX buffers. */ 4843 if (bce_hdr_split == TRUE) { 4844 bce_free_pg_chain(sc); 4845 } 4846 bce_free_rx_chain(sc); 4847 4848 /* Free TX buffers. */ 4849 bce_free_tx_chain(sc); 4850 4851 sc->watchdog_timer = 0; 4852 4853 sc->bce_link_up = FALSE; 4854 4855 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4856 4857 DBEXIT(BCE_VERBOSE_RESET); 4858 } 4859 4860 static int 4861 bce_reset(struct bce_softc *sc, u32 reset_code) 4862 { 4863 u32 emac_mode_save, val; 4864 int i, rc = 0; 4865 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 4866 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 4867 4868 DBENTER(BCE_VERBOSE_RESET); 4869 4870 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4871 __FUNCTION__, reset_code); 4872 4873 /* 4874 * If ASF/IPMI is operational, then the EMAC Mode register already 4875 * contains appropriate values for the link settings that have 4876 * been auto-negotiated. Resetting the chip will clobber those 4877 * values. Save the important bits so we can restore them after 4878 * the reset. 4879 */ 4880 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 4881 4882 /* Wait for pending PCI transactions to complete. */ 4883 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4884 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4885 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4886 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4887 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4888 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4889 DELAY(5); 4890 4891 /* Disable DMA */ 4892 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4893 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4894 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4895 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4896 } 4897 4898 /* Assume bootcode is running. */ 4899 sc->bce_fw_timed_out = FALSE; 4900 sc->bce_drv_cardiac_arrest = FALSE; 4901 4902 /* Give the firmware a chance to prepare for the reset. */ 4903 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4904 if (rc) 4905 goto bce_reset_exit; 4906 4907 /* Set a firmware reminder that this is a soft reset. */ 4908 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4909 4910 /* Dummy read to force the chip to complete all current transactions. */ 4911 val = REG_RD(sc, BCE_MISC_ID); 4912 4913 /* Chip reset. */ 4914 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4915 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4916 REG_RD(sc, BCE_MISC_COMMAND); 4917 DELAY(5); 4918 4919 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4920 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4921 4922 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4923 } else { 4924 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4925 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4926 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4927 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4928 4929 /* Allow up to 30us for reset to complete. */ 4930 for (i = 0; i < 10; i++) { 4931 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4932 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4933 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4934 break; 4935 } 4936 DELAY(10); 4937 } 4938 4939 /* Check that reset completed successfully. */ 4940 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4941 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4942 BCE_PRINTF("%s(%d): Reset failed!\n", 4943 __FILE__, __LINE__); 4944 rc = EBUSY; 4945 goto bce_reset_exit; 4946 } 4947 } 4948 4949 /* Make sure byte swapping is properly configured. */ 4950 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4951 if (val != 0x01020304) { 4952 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4953 __FILE__, __LINE__); 4954 rc = ENODEV; 4955 goto bce_reset_exit; 4956 } 4957 4958 /* Just completed a reset, assume that firmware is running again. */ 4959 sc->bce_fw_timed_out = FALSE; 4960 sc->bce_drv_cardiac_arrest = FALSE; 4961 4962 /* Wait for the firmware to finish its initialization. */ 4963 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4964 if (rc) 4965 BCE_PRINTF("%s(%d): Firmware did not complete " 4966 "initialization!\n", __FILE__, __LINE__); 4967 /* Get firmware capabilities. */ 4968 bce_fw_cap_init(sc); 4969 4970 bce_reset_exit: 4971 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 4972 if (reset_code == BCE_DRV_MSG_CODE_RESET) { 4973 val = REG_RD(sc, BCE_EMAC_MODE); 4974 val = (val & ~emac_mode_mask) | emac_mode_save; 4975 REG_WR(sc, BCE_EMAC_MODE, val); 4976 } 4977 4978 DBEXIT(BCE_VERBOSE_RESET); 4979 return (rc); 4980 } 4981 4982 static int 4983 bce_chipinit(struct bce_softc *sc) 4984 { 4985 u32 val; 4986 int rc = 0; 4987 4988 DBENTER(BCE_VERBOSE_RESET); 4989 4990 bce_disable_intr(sc); 4991 4992 /* 4993 * Initialize DMA byte/word swapping, configure the number of DMA 4994 * channels and PCI clock compensation delay. 4995 */ 4996 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 4997 BCE_DMA_CONFIG_DATA_WORD_SWAP | 4998 #if BYTE_ORDER == BIG_ENDIAN 4999 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5000 #endif 5001 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5002 DMA_READ_CHANS << 12 | 5003 DMA_WRITE_CHANS << 16; 5004 5005 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5006 5007 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5008 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5009 5010 /* 5011 * This setting resolves a problem observed on certain Intel PCI 5012 * chipsets that cannot handle multiple outstanding DMA operations. 5013 * See errata E9_5706A1_65. 5014 */ 5015 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5016 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5017 !(sc->bce_flags & BCE_PCIX_FLAG)) 5018 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5019 5020 REG_WR(sc, BCE_DMA_CONFIG, val); 5021 5022 /* Enable the RX_V2P and Context state machines before access. */ 5023 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5024 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5025 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5026 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5027 5028 /* Initialize context mapping and zero out the quick contexts. */ 5029 if ((rc = bce_init_ctx(sc)) != 0) 5030 goto bce_chipinit_exit; 5031 5032 /* Initialize the on-boards CPUs */ 5033 bce_init_cpus(sc); 5034 5035 /* Enable management frames (NC-SI) to flow to the MCP. */ 5036 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5037 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5038 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5039 } 5040 5041 /* Prepare NVRAM for access. */ 5042 if ((rc = bce_init_nvram(sc)) != 0) 5043 goto bce_chipinit_exit; 5044 5045 /* Set the kernel bypass block size */ 5046 val = REG_RD(sc, BCE_MQ_CONFIG); 5047 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5048 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5049 5050 /* Enable bins used on the 5709. */ 5051 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5052 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5053 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5054 val |= BCE_MQ_CONFIG_HALT_DIS; 5055 } 5056 5057 REG_WR(sc, BCE_MQ_CONFIG, val); 5058 5059 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5060 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5061 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5062 5063 /* Set the page size and clear the RV2P processor stall bits. */ 5064 val = (BCM_PAGE_BITS - 8) << 24; 5065 REG_WR(sc, BCE_RV2P_CONFIG, val); 5066 5067 /* Configure page size. */ 5068 val = REG_RD(sc, BCE_TBDR_CONFIG); 5069 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5070 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5071 REG_WR(sc, BCE_TBDR_CONFIG, val); 5072 5073 /* Set the perfect match control register to default. */ 5074 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5075 5076 bce_chipinit_exit: 5077 DBEXIT(BCE_VERBOSE_RESET); 5078 5079 return(rc); 5080 } 5081 5082 /****************************************************************************/ 5083 /* Initialize the controller in preparation to send/receive traffic. */ 5084 /* */ 5085 /* Returns: */ 5086 /* 0 for success, positive value for failure. */ 5087 /****************************************************************************/ 5088 static int 5089 bce_blockinit(struct bce_softc *sc) 5090 { 5091 u32 reg, val; 5092 int rc = 0; 5093 5094 DBENTER(BCE_VERBOSE_RESET); 5095 5096 /* Load the hardware default MAC address. */ 5097 bce_set_mac_addr(sc); 5098 5099 /* Set the Ethernet backoff seed value */ 5100 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5101 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5102 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5103 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5104 5105 sc->last_status_idx = 0; 5106 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5107 5108 /* Set up link change interrupt generation. */ 5109 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5110 5111 /* Program the physical address of the status block. */ 5112 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5113 BCE_ADDR_LO(sc->status_block_paddr)); 5114 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5115 BCE_ADDR_HI(sc->status_block_paddr)); 5116 5117 /* Program the physical address of the statistics block. */ 5118 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5119 BCE_ADDR_LO(sc->stats_block_paddr)); 5120 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5121 BCE_ADDR_HI(sc->stats_block_paddr)); 5122 5123 /* 5124 * Program various host coalescing parameters. 5125 * Trip points control how many BDs should be ready before generating 5126 * an interrupt while ticks control how long a BD can sit in the chain 5127 * before generating an interrupt. 5128 */ 5129 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5130 (sc->bce_tx_quick_cons_trip_int << 16) | 5131 sc->bce_tx_quick_cons_trip); 5132 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5133 (sc->bce_rx_quick_cons_trip_int << 16) | 5134 sc->bce_rx_quick_cons_trip); 5135 REG_WR(sc, BCE_HC_TX_TICKS, 5136 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5137 REG_WR(sc, BCE_HC_RX_TICKS, 5138 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5139 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5140 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5141 /* Not used for L2. */ 5142 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5143 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5144 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5145 5146 /* Configure the Host Coalescing block. */ 5147 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5148 BCE_HC_CONFIG_COLLECT_STATS; 5149 5150 #if 0 5151 /* ToDo: Add MSI-X support. */ 5152 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5153 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5154 BCE_HC_SB_CONFIG_1; 5155 5156 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5157 5158 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5159 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5160 5161 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5162 (sc->tx_quick_cons_trip_int << 16) | 5163 sc->tx_quick_cons_trip); 5164 5165 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5166 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5167 5168 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5169 } 5170 5171 /* 5172 * Tell the HC block to automatically set the 5173 * INT_MASK bit after an MSI/MSI-X interrupt 5174 * is generated so the driver doesn't have to. 5175 */ 5176 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5177 val |= BCE_HC_CONFIG_ONE_SHOT; 5178 5179 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5180 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5181 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5182 #endif 5183 5184 REG_WR(sc, BCE_HC_CONFIG, val); 5185 5186 /* Clear the internal statistics counters. */ 5187 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5188 5189 /* Verify that bootcode is running. */ 5190 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5191 5192 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5193 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5194 __FILE__, __LINE__); 5195 reg = 0); 5196 5197 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5198 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5199 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5200 "Expected: 08%08X\n", __FILE__, __LINE__, 5201 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5202 BCE_DEV_INFO_SIGNATURE_MAGIC); 5203 rc = ENODEV; 5204 goto bce_blockinit_exit; 5205 } 5206 5207 /* Enable DMA */ 5208 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5209 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5210 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5211 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5212 } 5213 5214 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5215 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5216 BCE_DRV_MSG_CODE_RESET); 5217 5218 /* Enable link state change interrupt generation. */ 5219 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5220 5221 /* Enable the RXP. */ 5222 bce_start_rxp_cpu(sc); 5223 5224 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5225 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5226 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5227 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5228 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5229 } 5230 5231 /* Enable all remaining blocks in the MAC. */ 5232 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5233 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5234 BCE_MISC_ENABLE_DEFAULT_XI); 5235 else 5236 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5237 BCE_MISC_ENABLE_DEFAULT); 5238 5239 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5240 DELAY(20); 5241 5242 /* Save the current host coalescing block settings. */ 5243 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5244 5245 bce_blockinit_exit: 5246 DBEXIT(BCE_VERBOSE_RESET); 5247 5248 return (rc); 5249 } 5250 5251 /****************************************************************************/ 5252 /* Encapsulate an mbuf into the rx_bd chain. */ 5253 /* */ 5254 /* Returns: */ 5255 /* 0 for success, positive value for failure. */ 5256 /****************************************************************************/ 5257 static int 5258 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5259 { 5260 bus_dma_segment_t segs[1]; 5261 struct mbuf *m_new = NULL; 5262 struct rx_bd *rxbd; 5263 int nsegs, error, rc = 0; 5264 #ifdef BCE_DEBUG 5265 u16 debug_chain_prod = chain_prod; 5266 #endif 5267 5268 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5269 5270 /* Make sure the inputs are valid. */ 5271 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5272 BCE_PRINTF("%s(%d): RX producer out of range: " 5273 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5274 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5275 5276 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5277 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5278 prod, chain_prod, *prod_bseq); 5279 5280 /* Update some debug statistic counters */ 5281 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5282 sc->rx_low_watermark = sc->free_rx_bd); 5283 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5284 sc->rx_empty_count++); 5285 5286 /* Simulate an mbuf allocation failure. */ 5287 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5288 sc->mbuf_alloc_failed_count++; 5289 sc->mbuf_alloc_failed_sim_count++; 5290 rc = ENOBUFS; 5291 goto bce_get_rx_buf_exit); 5292 5293 /* This is a new mbuf allocation. */ 5294 if (bce_hdr_split == TRUE) 5295 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5296 else 5297 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5298 sc->rx_bd_mbuf_alloc_size); 5299 5300 if (m_new == NULL) { 5301 sc->mbuf_alloc_failed_count++; 5302 rc = ENOBUFS; 5303 goto bce_get_rx_buf_exit; 5304 } 5305 5306 DBRUN(sc->debug_rx_mbuf_alloc++); 5307 5308 /* Make sure we have a valid packet header. */ 5309 M_ASSERTPKTHDR(m_new); 5310 5311 /* Initialize the mbuf size and pad if necessary for alignment. */ 5312 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5313 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5314 5315 /* ToDo: Consider calling m_fragment() to test error handling. */ 5316 5317 /* Map the mbuf cluster into device memory. */ 5318 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5319 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5320 5321 /* Handle any mapping errors. */ 5322 if (error) { 5323 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5324 "chain (%d)!\n", __FILE__, __LINE__, error); 5325 5326 sc->dma_map_addr_rx_failed_count++; 5327 m_freem(m_new); 5328 5329 DBRUN(sc->debug_rx_mbuf_alloc--); 5330 5331 rc = ENOBUFS; 5332 goto bce_get_rx_buf_exit; 5333 } 5334 5335 /* All mbufs must map to a single segment. */ 5336 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5337 __FUNCTION__, nsegs)); 5338 5339 /* Setup the rx_bd for the segment. */ 5340 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5341 5342 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5343 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5344 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5345 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5346 *prod_bseq += segs[0].ds_len; 5347 5348 /* Save the mbuf and update our counter. */ 5349 sc->rx_mbuf_ptr[chain_prod] = m_new; 5350 sc->free_rx_bd -= nsegs; 5351 5352 DBRUNMSG(BCE_INSANE_RECV, 5353 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5354 5355 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5356 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5357 chain_prod, *prod_bseq); 5358 5359 bce_get_rx_buf_exit: 5360 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5361 5362 return(rc); 5363 } 5364 5365 /****************************************************************************/ 5366 /* Encapsulate an mbuf cluster into the page chain. */ 5367 /* */ 5368 /* Returns: */ 5369 /* 0 for success, positive value for failure. */ 5370 /****************************************************************************/ 5371 static int 5372 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5373 { 5374 bus_dma_segment_t segs[1]; 5375 struct mbuf *m_new = NULL; 5376 struct rx_bd *pgbd; 5377 int error, nsegs, rc = 0; 5378 #ifdef BCE_DEBUG 5379 u16 debug_prod_idx = prod_idx; 5380 #endif 5381 5382 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5383 5384 /* Make sure the inputs are valid. */ 5385 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5386 BCE_PRINTF("%s(%d): page producer out of range: " 5387 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5388 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5389 5390 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5391 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5392 5393 /* Update counters if we've hit a new low or run out of pages. */ 5394 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5395 sc->pg_low_watermark = sc->free_pg_bd); 5396 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5397 5398 /* Simulate an mbuf allocation failure. */ 5399 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5400 sc->mbuf_alloc_failed_count++; 5401 sc->mbuf_alloc_failed_sim_count++; 5402 rc = ENOBUFS; 5403 goto bce_get_pg_buf_exit); 5404 5405 /* This is a new mbuf allocation. */ 5406 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5407 if (m_new == NULL) { 5408 sc->mbuf_alloc_failed_count++; 5409 rc = ENOBUFS; 5410 goto bce_get_pg_buf_exit; 5411 } 5412 5413 DBRUN(sc->debug_pg_mbuf_alloc++); 5414 5415 m_new->m_len = MCLBYTES; 5416 5417 /* ToDo: Consider calling m_fragment() to test error handling. */ 5418 5419 /* Map the mbuf cluster into device memory. */ 5420 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5421 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5422 5423 /* Handle any mapping errors. */ 5424 if (error) { 5425 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5426 __FILE__, __LINE__); 5427 5428 m_freem(m_new); 5429 DBRUN(sc->debug_pg_mbuf_alloc--); 5430 5431 rc = ENOBUFS; 5432 goto bce_get_pg_buf_exit; 5433 } 5434 5435 /* All mbufs must map to a single segment. */ 5436 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5437 __FUNCTION__, nsegs)); 5438 5439 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5440 5441 /* 5442 * The page chain uses the same rx_bd data structure 5443 * as the receive chain but doesn't require a byte sequence (bseq). 5444 */ 5445 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5446 5447 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5448 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5449 pgbd->rx_bd_len = htole32(MCLBYTES); 5450 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5451 5452 /* Save the mbuf and update our counter. */ 5453 sc->pg_mbuf_ptr[prod_idx] = m_new; 5454 sc->free_pg_bd--; 5455 5456 DBRUNMSG(BCE_INSANE_RECV, 5457 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5458 5459 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5460 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5461 5462 bce_get_pg_buf_exit: 5463 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5464 5465 return(rc); 5466 } 5467 5468 /****************************************************************************/ 5469 /* Initialize the TX context memory. */ 5470 /* */ 5471 /* Returns: */ 5472 /* Nothing */ 5473 /****************************************************************************/ 5474 static void 5475 bce_init_tx_context(struct bce_softc *sc) 5476 { 5477 u32 val; 5478 5479 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5480 5481 /* Initialize the context ID for an L2 TX chain. */ 5482 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5483 /* Set the CID type to support an L2 connection. */ 5484 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5485 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5486 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5487 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5488 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5489 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5490 5491 /* Point the hardware to the first page in the chain. */ 5492 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5493 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5494 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5495 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5496 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5497 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5498 } else { 5499 /* Set the CID type to support an L2 connection. */ 5500 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5501 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5502 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5503 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5504 5505 /* Point the hardware to the first page in the chain. */ 5506 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5507 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5508 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5509 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5510 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5511 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5512 } 5513 5514 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5515 } 5516 5517 /****************************************************************************/ 5518 /* Allocate memory and initialize the TX data structures. */ 5519 /* */ 5520 /* Returns: */ 5521 /* 0 for success, positive value for failure. */ 5522 /****************************************************************************/ 5523 static int 5524 bce_init_tx_chain(struct bce_softc *sc) 5525 { 5526 struct tx_bd *txbd; 5527 int i, rc = 0; 5528 5529 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5530 5531 /* Set the initial TX producer/consumer indices. */ 5532 sc->tx_prod = 0; 5533 sc->tx_cons = 0; 5534 sc->tx_prod_bseq = 0; 5535 sc->used_tx_bd = 0; 5536 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5537 DBRUN(sc->tx_hi_watermark = 0); 5538 DBRUN(sc->tx_full_count = 0); 5539 5540 /* 5541 * The NetXtreme II supports a linked-list structure called 5542 * a Buffer Descriptor Chain (or BD chain). A BD chain 5543 * consists of a series of 1 or more chain pages, each of which 5544 * consists of a fixed number of BD entries. 5545 * The last BD entry on each page is a pointer to the next page 5546 * in the chain, and the last pointer in the BD chain 5547 * points back to the beginning of the chain. 5548 */ 5549 5550 /* Set the TX next pointer chain entries. */ 5551 for (i = 0; i < sc->tx_pages; i++) { 5552 int j; 5553 5554 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5555 5556 /* Check if we've reached the last page. */ 5557 if (i == (sc->tx_pages - 1)) 5558 j = 0; 5559 else 5560 j = i + 1; 5561 5562 txbd->tx_bd_haddr_hi = 5563 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5564 txbd->tx_bd_haddr_lo = 5565 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5566 } 5567 5568 bce_init_tx_context(sc); 5569 5570 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5571 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5572 5573 return(rc); 5574 } 5575 5576 /****************************************************************************/ 5577 /* Free memory and clear the TX data structures. */ 5578 /* */ 5579 /* Returns: */ 5580 /* Nothing. */ 5581 /****************************************************************************/ 5582 static void 5583 bce_free_tx_chain(struct bce_softc *sc) 5584 { 5585 int i; 5586 5587 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5588 5589 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5590 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5591 if (sc->tx_mbuf_ptr[i] != NULL) { 5592 if (sc->tx_mbuf_map[i] != NULL) 5593 bus_dmamap_sync(sc->tx_mbuf_tag, 5594 sc->tx_mbuf_map[i], 5595 BUS_DMASYNC_POSTWRITE); 5596 m_freem(sc->tx_mbuf_ptr[i]); 5597 sc->tx_mbuf_ptr[i] = NULL; 5598 DBRUN(sc->debug_tx_mbuf_alloc--); 5599 } 5600 } 5601 5602 /* Clear each TX chain page. */ 5603 for (i = 0; i < sc->tx_pages; i++) 5604 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5605 5606 sc->used_tx_bd = 0; 5607 5608 /* Check if we lost any mbufs in the process. */ 5609 DBRUNIF((sc->debug_tx_mbuf_alloc), 5610 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5611 "from tx chain!\n", __FILE__, __LINE__, 5612 sc->debug_tx_mbuf_alloc)); 5613 5614 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5615 } 5616 5617 /****************************************************************************/ 5618 /* Initialize the RX context memory. */ 5619 /* */ 5620 /* Returns: */ 5621 /* Nothing */ 5622 /****************************************************************************/ 5623 static void 5624 bce_init_rx_context(struct bce_softc *sc) 5625 { 5626 u32 val; 5627 5628 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5629 5630 /* Init the type, size, and BD cache levels for the RX context. */ 5631 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5632 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5633 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5634 5635 /* 5636 * Set the level for generating pause frames 5637 * when the number of available rx_bd's gets 5638 * too low (the low watermark) and the level 5639 * when pause frames can be stopped (the high 5640 * watermark). 5641 */ 5642 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5643 u32 lo_water, hi_water; 5644 5645 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5646 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5647 } else { 5648 lo_water = 0; 5649 } 5650 5651 if (lo_water >= USABLE_RX_BD_ALLOC) { 5652 lo_water = 0; 5653 } 5654 5655 hi_water = USABLE_RX_BD_ALLOC / 4; 5656 5657 if (hi_water <= lo_water) { 5658 lo_water = 0; 5659 } 5660 5661 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5662 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5663 5664 if (hi_water > 0xf) 5665 hi_water = 0xf; 5666 else if (hi_water == 0) 5667 lo_water = 0; 5668 5669 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5670 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5671 } 5672 5673 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5674 5675 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5676 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5677 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5678 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5679 } 5680 5681 /* Point the hardware to the first page in the chain. */ 5682 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5683 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5684 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5685 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5686 5687 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5688 } 5689 5690 /****************************************************************************/ 5691 /* Allocate memory and initialize the RX data structures. */ 5692 /* */ 5693 /* Returns: */ 5694 /* 0 for success, positive value for failure. */ 5695 /****************************************************************************/ 5696 static int 5697 bce_init_rx_chain(struct bce_softc *sc) 5698 { 5699 struct rx_bd *rxbd; 5700 int i, rc = 0; 5701 5702 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5703 BCE_VERBOSE_CTX); 5704 5705 /* Initialize the RX producer and consumer indices. */ 5706 sc->rx_prod = 0; 5707 sc->rx_cons = 0; 5708 sc->rx_prod_bseq = 0; 5709 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5710 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5711 5712 /* Initialize the RX next pointer chain entries. */ 5713 for (i = 0; i < sc->rx_pages; i++) { 5714 int j; 5715 5716 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5717 5718 /* Check if we've reached the last page. */ 5719 if (i == (sc->rx_pages - 1)) 5720 j = 0; 5721 else 5722 j = i + 1; 5723 5724 /* Setup the chain page pointers. */ 5725 rxbd->rx_bd_haddr_hi = 5726 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5727 rxbd->rx_bd_haddr_lo = 5728 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5729 } 5730 5731 /* Fill up the RX chain. */ 5732 bce_fill_rx_chain(sc); 5733 5734 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5735 DBRUN(sc->rx_empty_count = 0); 5736 for (i = 0; i < sc->rx_pages; i++) { 5737 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5738 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5739 } 5740 5741 bce_init_rx_context(sc); 5742 5743 DBRUNMSG(BCE_EXTREME_RECV, 5744 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5745 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5746 BCE_VERBOSE_CTX); 5747 5748 /* ToDo: Are there possible failure modes here? */ 5749 5750 return(rc); 5751 } 5752 5753 /****************************************************************************/ 5754 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5755 /* occurs. */ 5756 /* */ 5757 /* Returns: */ 5758 /* Nothing */ 5759 /****************************************************************************/ 5760 static void 5761 bce_fill_rx_chain(struct bce_softc *sc) 5762 { 5763 u16 prod, prod_idx; 5764 u32 prod_bseq; 5765 5766 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5767 BCE_VERBOSE_CTX); 5768 5769 /* Get the RX chain producer indices. */ 5770 prod = sc->rx_prod; 5771 prod_bseq = sc->rx_prod_bseq; 5772 5773 /* Keep filling the RX chain until it's full. */ 5774 while (sc->free_rx_bd > 0) { 5775 prod_idx = RX_CHAIN_IDX(prod); 5776 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5777 /* Bail out if we can't add an mbuf to the chain. */ 5778 break; 5779 } 5780 prod = NEXT_RX_BD(prod); 5781 } 5782 5783 /* Save the RX chain producer indices. */ 5784 sc->rx_prod = prod; 5785 sc->rx_prod_bseq = prod_bseq; 5786 5787 /* We should never end up pointing to a next page pointer. */ 5788 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5789 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5790 __FUNCTION__, rx_prod)); 5791 5792 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5793 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5794 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5795 5796 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5797 BCE_VERBOSE_CTX); 5798 } 5799 5800 /****************************************************************************/ 5801 /* Free memory and clear the RX data structures. */ 5802 /* */ 5803 /* Returns: */ 5804 /* Nothing. */ 5805 /****************************************************************************/ 5806 static void 5807 bce_free_rx_chain(struct bce_softc *sc) 5808 { 5809 int i; 5810 5811 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5812 5813 /* Free any mbufs still in the RX mbuf chain. */ 5814 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5815 if (sc->rx_mbuf_ptr[i] != NULL) { 5816 if (sc->rx_mbuf_map[i] != NULL) 5817 bus_dmamap_sync(sc->rx_mbuf_tag, 5818 sc->rx_mbuf_map[i], 5819 BUS_DMASYNC_POSTREAD); 5820 m_freem(sc->rx_mbuf_ptr[i]); 5821 sc->rx_mbuf_ptr[i] = NULL; 5822 DBRUN(sc->debug_rx_mbuf_alloc--); 5823 } 5824 } 5825 5826 /* Clear each RX chain page. */ 5827 for (i = 0; i < sc->rx_pages; i++) 5828 if (sc->rx_bd_chain[i] != NULL) 5829 bzero((char *)sc->rx_bd_chain[i], 5830 BCE_RX_CHAIN_PAGE_SZ); 5831 5832 sc->free_rx_bd = sc->max_rx_bd; 5833 5834 /* Check if we lost any mbufs in the process. */ 5835 DBRUNIF((sc->debug_rx_mbuf_alloc), 5836 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5837 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5838 5839 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5840 } 5841 5842 /****************************************************************************/ 5843 /* Allocate memory and initialize the page data structures. */ 5844 /* Assumes that bce_init_rx_chain() has not already been called. */ 5845 /* */ 5846 /* Returns: */ 5847 /* 0 for success, positive value for failure. */ 5848 /****************************************************************************/ 5849 static int 5850 bce_init_pg_chain(struct bce_softc *sc) 5851 { 5852 struct rx_bd *pgbd; 5853 int i, rc = 0; 5854 u32 val; 5855 5856 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5857 BCE_VERBOSE_CTX); 5858 5859 /* Initialize the page producer and consumer indices. */ 5860 sc->pg_prod = 0; 5861 sc->pg_cons = 0; 5862 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5863 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5864 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5865 DBRUN(sc->pg_empty_count = 0); 5866 5867 /* Initialize the page next pointer chain entries. */ 5868 for (i = 0; i < sc->pg_pages; i++) { 5869 int j; 5870 5871 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5872 5873 /* Check if we've reached the last page. */ 5874 if (i == (sc->pg_pages - 1)) 5875 j = 0; 5876 else 5877 j = i + 1; 5878 5879 /* Setup the chain page pointers. */ 5880 pgbd->rx_bd_haddr_hi = 5881 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5882 pgbd->rx_bd_haddr_lo = 5883 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5884 } 5885 5886 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5887 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5888 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5889 5890 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5891 5892 /* Configure the rx_bd and page chain mbuf cluster size. */ 5893 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 5894 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5895 5896 /* Configure the context reserved for jumbo support. */ 5897 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5898 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5899 5900 /* Point the hardware to the first page in the page chain. */ 5901 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5902 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5903 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5904 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5905 5906 /* Fill up the page chain. */ 5907 bce_fill_pg_chain(sc); 5908 5909 for (i = 0; i < sc->pg_pages; i++) { 5910 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5911 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5912 } 5913 5914 DBRUNMSG(BCE_EXTREME_RECV, 5915 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 5916 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5917 BCE_VERBOSE_CTX); 5918 return(rc); 5919 } 5920 5921 /****************************************************************************/ 5922 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 5923 /* occurs. */ 5924 /* */ 5925 /* Returns: */ 5926 /* Nothing */ 5927 /****************************************************************************/ 5928 static void 5929 bce_fill_pg_chain(struct bce_softc *sc) 5930 { 5931 u16 prod, prod_idx; 5932 5933 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5934 BCE_VERBOSE_CTX); 5935 5936 /* Get the page chain prodcuer index. */ 5937 prod = sc->pg_prod; 5938 5939 /* Keep filling the page chain until it's full. */ 5940 while (sc->free_pg_bd > 0) { 5941 prod_idx = PG_CHAIN_IDX(prod); 5942 if (bce_get_pg_buf(sc, prod, prod_idx)) { 5943 /* Bail out if we can't add an mbuf to the chain. */ 5944 break; 5945 } 5946 prod = NEXT_PG_BD(prod); 5947 } 5948 5949 /* Save the page chain producer index. */ 5950 sc->pg_prod = prod; 5951 5952 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5953 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5954 __FUNCTION__, pg_prod)); 5955 5956 /* 5957 * Write the mailbox and tell the chip about 5958 * the new rx_bd's in the page chain. 5959 */ 5960 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 5961 prod); 5962 5963 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5964 BCE_VERBOSE_CTX); 5965 } 5966 5967 /****************************************************************************/ 5968 /* Free memory and clear the RX data structures. */ 5969 /* */ 5970 /* Returns: */ 5971 /* Nothing. */ 5972 /****************************************************************************/ 5973 static void 5974 bce_free_pg_chain(struct bce_softc *sc) 5975 { 5976 int i; 5977 5978 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5979 5980 /* Free any mbufs still in the mbuf page chain. */ 5981 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 5982 if (sc->pg_mbuf_ptr[i] != NULL) { 5983 if (sc->pg_mbuf_map[i] != NULL) 5984 bus_dmamap_sync(sc->pg_mbuf_tag, 5985 sc->pg_mbuf_map[i], 5986 BUS_DMASYNC_POSTREAD); 5987 m_freem(sc->pg_mbuf_ptr[i]); 5988 sc->pg_mbuf_ptr[i] = NULL; 5989 DBRUN(sc->debug_pg_mbuf_alloc--); 5990 } 5991 } 5992 5993 /* Clear each page chain pages. */ 5994 for (i = 0; i < sc->pg_pages; i++) 5995 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 5996 5997 sc->free_pg_bd = sc->max_pg_bd; 5998 5999 /* Check if we lost any mbufs in the process. */ 6000 DBRUNIF((sc->debug_pg_mbuf_alloc), 6001 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6002 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6003 6004 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6005 } 6006 6007 static u32 6008 bce_get_rphy_link(struct bce_softc *sc) 6009 { 6010 u32 advertise, link; 6011 int fdpx; 6012 6013 advertise = 0; 6014 fdpx = 0; 6015 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6016 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6017 else 6018 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6019 if (link & BCE_NETLINK_ANEG_ENB) 6020 advertise |= BCE_NETLINK_ANEG_ENB; 6021 if (link & BCE_NETLINK_SPEED_10HALF) 6022 advertise |= BCE_NETLINK_SPEED_10HALF; 6023 if (link & BCE_NETLINK_SPEED_10FULL) { 6024 advertise |= BCE_NETLINK_SPEED_10FULL; 6025 fdpx++; 6026 } 6027 if (link & BCE_NETLINK_SPEED_100HALF) 6028 advertise |= BCE_NETLINK_SPEED_100HALF; 6029 if (link & BCE_NETLINK_SPEED_100FULL) { 6030 advertise |= BCE_NETLINK_SPEED_100FULL; 6031 fdpx++; 6032 } 6033 if (link & BCE_NETLINK_SPEED_1000HALF) 6034 advertise |= BCE_NETLINK_SPEED_1000HALF; 6035 if (link & BCE_NETLINK_SPEED_1000FULL) { 6036 advertise |= BCE_NETLINK_SPEED_1000FULL; 6037 fdpx++; 6038 } 6039 if (link & BCE_NETLINK_SPEED_2500HALF) 6040 advertise |= BCE_NETLINK_SPEED_2500HALF; 6041 if (link & BCE_NETLINK_SPEED_2500FULL) { 6042 advertise |= BCE_NETLINK_SPEED_2500FULL; 6043 fdpx++; 6044 } 6045 if (fdpx) 6046 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6047 BCE_NETLINK_FC_PAUSE_ASYM; 6048 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6049 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6050 BCE_NETLINK_ETH_AT_WIRESPEED; 6051 6052 return (advertise); 6053 } 6054 6055 /****************************************************************************/ 6056 /* Set media options. */ 6057 /* */ 6058 /* Returns: */ 6059 /* 0 for success, positive value for failure. */ 6060 /****************************************************************************/ 6061 static int 6062 bce_ifmedia_upd(if_t ifp) 6063 { 6064 struct bce_softc *sc = if_getsoftc(ifp); 6065 int error; 6066 6067 DBENTER(BCE_VERBOSE); 6068 6069 BCE_LOCK(sc); 6070 error = bce_ifmedia_upd_locked(ifp); 6071 BCE_UNLOCK(sc); 6072 6073 DBEXIT(BCE_VERBOSE); 6074 return (error); 6075 } 6076 6077 /****************************************************************************/ 6078 /* Set media options. */ 6079 /* */ 6080 /* Returns: */ 6081 /* Nothing. */ 6082 /****************************************************************************/ 6083 static int 6084 bce_ifmedia_upd_locked(if_t ifp) 6085 { 6086 struct bce_softc *sc = if_getsoftc(ifp); 6087 struct mii_data *mii; 6088 struct mii_softc *miisc; 6089 struct ifmedia *ifm; 6090 u32 link; 6091 int error, fdx; 6092 6093 DBENTER(BCE_VERBOSE_PHY); 6094 6095 error = 0; 6096 BCE_LOCK_ASSERT(sc); 6097 6098 sc->bce_link_up = FALSE; 6099 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6100 ifm = &sc->bce_ifmedia; 6101 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6102 return (EINVAL); 6103 link = 0; 6104 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6105 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6106 case IFM_AUTO: 6107 /* 6108 * Check advertised link of remote PHY by reading 6109 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6110 * Always use the same link type of remote PHY. 6111 */ 6112 link = bce_get_rphy_link(sc); 6113 break; 6114 case IFM_2500_SX: 6115 if ((sc->bce_phy_flags & 6116 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6117 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6118 return (EINVAL); 6119 /* 6120 * XXX 6121 * Have to enable forced 2.5Gbps configuration. 6122 */ 6123 if (fdx != 0) 6124 link |= BCE_NETLINK_SPEED_2500FULL; 6125 else 6126 link |= BCE_NETLINK_SPEED_2500HALF; 6127 break; 6128 case IFM_1000_SX: 6129 if ((sc->bce_phy_flags & 6130 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6131 return (EINVAL); 6132 /* 6133 * XXX 6134 * Have to disable 2.5Gbps configuration. 6135 */ 6136 if (fdx != 0) 6137 link = BCE_NETLINK_SPEED_1000FULL; 6138 else 6139 link = BCE_NETLINK_SPEED_1000HALF; 6140 break; 6141 case IFM_1000_T: 6142 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6143 return (EINVAL); 6144 if (fdx != 0) 6145 link = BCE_NETLINK_SPEED_1000FULL; 6146 else 6147 link = BCE_NETLINK_SPEED_1000HALF; 6148 break; 6149 case IFM_100_TX: 6150 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6151 return (EINVAL); 6152 if (fdx != 0) 6153 link = BCE_NETLINK_SPEED_100FULL; 6154 else 6155 link = BCE_NETLINK_SPEED_100HALF; 6156 break; 6157 case IFM_10_T: 6158 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6159 return (EINVAL); 6160 if (fdx != 0) 6161 link = BCE_NETLINK_SPEED_10FULL; 6162 else 6163 link = BCE_NETLINK_SPEED_10HALF; 6164 break; 6165 default: 6166 return (EINVAL); 6167 } 6168 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6169 /* 6170 * XXX 6171 * Advertise pause capability for full-duplex media. 6172 */ 6173 if (fdx != 0) 6174 link |= BCE_NETLINK_FC_PAUSE_SYM | 6175 BCE_NETLINK_FC_PAUSE_ASYM; 6176 if ((sc->bce_phy_flags & 6177 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6178 link |= BCE_NETLINK_PHY_APP_REMOTE | 6179 BCE_NETLINK_ETH_AT_WIRESPEED; 6180 } 6181 6182 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6183 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6184 } else { 6185 mii = device_get_softc(sc->bce_miibus); 6186 6187 /* Make sure the MII bus has been enumerated. */ 6188 if (mii) { 6189 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6190 PHY_RESET(miisc); 6191 error = mii_mediachg(mii); 6192 } 6193 } 6194 6195 DBEXIT(BCE_VERBOSE_PHY); 6196 return (error); 6197 } 6198 6199 static void 6200 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6201 { 6202 if_t ifp; 6203 u32 link; 6204 6205 ifp = sc->bce_ifp; 6206 BCE_LOCK_ASSERT(sc); 6207 6208 ifmr->ifm_status = IFM_AVALID; 6209 ifmr->ifm_active = IFM_ETHER; 6210 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6211 /* XXX Handle heart beat status? */ 6212 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6213 ifmr->ifm_status |= IFM_ACTIVE; 6214 else { 6215 ifmr->ifm_active |= IFM_NONE; 6216 if_setbaudrate(ifp, 0); 6217 return; 6218 } 6219 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6220 case BCE_LINK_STATUS_10HALF: 6221 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6222 if_setbaudrate(ifp, IF_Mbps(10UL)); 6223 break; 6224 case BCE_LINK_STATUS_10FULL: 6225 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6226 if_setbaudrate(ifp, IF_Mbps(10UL)); 6227 break; 6228 case BCE_LINK_STATUS_100HALF: 6229 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6230 if_setbaudrate(ifp, IF_Mbps(100UL)); 6231 break; 6232 case BCE_LINK_STATUS_100FULL: 6233 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6234 if_setbaudrate(ifp, IF_Mbps(100UL)); 6235 break; 6236 case BCE_LINK_STATUS_1000HALF: 6237 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6238 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6239 else 6240 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6241 if_setbaudrate(ifp, IF_Mbps(1000UL)); 6242 break; 6243 case BCE_LINK_STATUS_1000FULL: 6244 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6245 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6246 else 6247 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6248 if_setbaudrate(ifp, IF_Mbps(1000UL)); 6249 break; 6250 case BCE_LINK_STATUS_2500HALF: 6251 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6252 ifmr->ifm_active |= IFM_NONE; 6253 return; 6254 } else 6255 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6256 if_setbaudrate(ifp, IF_Mbps(2500UL)); 6257 break; 6258 case BCE_LINK_STATUS_2500FULL: 6259 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6260 ifmr->ifm_active |= IFM_NONE; 6261 return; 6262 } else 6263 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6264 if_setbaudrate(ifp, IF_Mbps(2500UL)); 6265 break; 6266 default: 6267 ifmr->ifm_active |= IFM_NONE; 6268 return; 6269 } 6270 6271 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6272 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6273 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6274 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6275 } 6276 6277 /****************************************************************************/ 6278 /* Reports current media status. */ 6279 /* */ 6280 /* Returns: */ 6281 /* Nothing. */ 6282 /****************************************************************************/ 6283 static void 6284 bce_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 6285 { 6286 struct bce_softc *sc = if_getsoftc(ifp); 6287 struct mii_data *mii; 6288 6289 DBENTER(BCE_VERBOSE_PHY); 6290 6291 BCE_LOCK(sc); 6292 6293 if ((if_getflags(ifp) & IFF_UP) == 0) { 6294 BCE_UNLOCK(sc); 6295 return; 6296 } 6297 6298 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6299 bce_ifmedia_sts_rphy(sc, ifmr); 6300 else { 6301 mii = device_get_softc(sc->bce_miibus); 6302 mii_pollstat(mii); 6303 ifmr->ifm_active = mii->mii_media_active; 6304 ifmr->ifm_status = mii->mii_media_status; 6305 } 6306 6307 BCE_UNLOCK(sc); 6308 6309 DBEXIT(BCE_VERBOSE_PHY); 6310 } 6311 6312 /****************************************************************************/ 6313 /* Handles PHY generated interrupt events. */ 6314 /* */ 6315 /* Returns: */ 6316 /* Nothing. */ 6317 /****************************************************************************/ 6318 static void 6319 bce_phy_intr(struct bce_softc *sc) 6320 { 6321 u32 new_link_state, old_link_state; 6322 6323 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6324 6325 DBRUN(sc->phy_interrupts++); 6326 6327 new_link_state = sc->status_block->status_attn_bits & 6328 STATUS_ATTN_BITS_LINK_STATE; 6329 old_link_state = sc->status_block->status_attn_bits_ack & 6330 STATUS_ATTN_BITS_LINK_STATE; 6331 6332 /* Handle any changes if the link state has changed. */ 6333 if (new_link_state != old_link_state) { 6334 /* Update the status_attn_bits_ack field. */ 6335 if (new_link_state) { 6336 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6337 STATUS_ATTN_BITS_LINK_STATE); 6338 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6339 __FUNCTION__); 6340 } else { 6341 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6342 STATUS_ATTN_BITS_LINK_STATE); 6343 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6344 __FUNCTION__); 6345 } 6346 6347 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6348 if (new_link_state) { 6349 if (bootverbose) 6350 if_printf(sc->bce_ifp, "link UP\n"); 6351 if_link_state_change(sc->bce_ifp, 6352 LINK_STATE_UP); 6353 } else { 6354 if (bootverbose) 6355 if_printf(sc->bce_ifp, "link DOWN\n"); 6356 if_link_state_change(sc->bce_ifp, 6357 LINK_STATE_DOWN); 6358 } 6359 } 6360 /* 6361 * Assume link is down and allow 6362 * tick routine to update the state 6363 * based on the actual media state. 6364 */ 6365 sc->bce_link_up = FALSE; 6366 callout_stop(&sc->bce_tick_callout); 6367 bce_tick(sc); 6368 } 6369 6370 /* Acknowledge the link change interrupt. */ 6371 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6372 6373 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6374 } 6375 6376 /****************************************************************************/ 6377 /* Reads the receive consumer value from the status block (skipping over */ 6378 /* chain page pointer if necessary). */ 6379 /* */ 6380 /* Returns: */ 6381 /* hw_cons */ 6382 /****************************************************************************/ 6383 static inline u16 6384 bce_get_hw_rx_cons(struct bce_softc *sc) 6385 { 6386 u16 hw_cons; 6387 6388 rmb(); 6389 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6390 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6391 hw_cons++; 6392 6393 return hw_cons; 6394 } 6395 6396 /****************************************************************************/ 6397 /* Handles received frame interrupt events. */ 6398 /* */ 6399 /* Returns: */ 6400 /* Nothing. */ 6401 /****************************************************************************/ 6402 static void 6403 bce_rx_intr(struct bce_softc *sc) 6404 { 6405 if_t ifp = sc->bce_ifp; 6406 struct l2_fhdr *l2fhdr; 6407 struct ether_vlan_header *vh; 6408 unsigned int pkt_len; 6409 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6410 u32 status; 6411 unsigned int rem_len; 6412 u16 sw_pg_cons, sw_pg_cons_idx; 6413 6414 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6415 DBRUN(sc->interrupts_rx++); 6416 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6417 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6418 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6419 6420 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6421 for (int i = 0; i < sc->rx_pages; i++) 6422 bus_dmamap_sync(sc->rx_bd_chain_tag, 6423 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6424 6425 /* Prepare the page chain pages to be accessed by the host CPU. */ 6426 if (bce_hdr_split == TRUE) { 6427 for (int i = 0; i < sc->pg_pages; i++) 6428 bus_dmamap_sync(sc->pg_bd_chain_tag, 6429 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6430 } 6431 6432 /* Get the hardware's view of the RX consumer index. */ 6433 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6434 6435 /* Get working copies of the driver's view of the consumer indices. */ 6436 sw_rx_cons = sc->rx_cons; 6437 sw_pg_cons = sc->pg_cons; 6438 6439 /* Update some debug statistics counters */ 6440 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6441 sc->rx_low_watermark = sc->free_rx_bd); 6442 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6443 sc->rx_empty_count++); 6444 6445 /* Scan through the receive chain as long as there is work to do */ 6446 /* ToDo: Consider setting a limit on the number of packets processed. */ 6447 rmb(); 6448 while (sw_rx_cons != hw_rx_cons) { 6449 struct mbuf *m0; 6450 6451 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6452 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6453 6454 /* Unmap the mbuf from DMA space. */ 6455 bus_dmamap_sync(sc->rx_mbuf_tag, 6456 sc->rx_mbuf_map[sw_rx_cons_idx], 6457 BUS_DMASYNC_POSTREAD); 6458 bus_dmamap_unload(sc->rx_mbuf_tag, 6459 sc->rx_mbuf_map[sw_rx_cons_idx]); 6460 6461 /* Remove the mbuf from the RX chain. */ 6462 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6463 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6464 DBRUN(sc->debug_rx_mbuf_alloc--); 6465 sc->free_rx_bd++; 6466 6467 /* 6468 * Frames received on the NetXteme II are prepended 6469 * with an l2_fhdr structure which provides status 6470 * information about the received frame (including 6471 * VLAN tags and checksum info). The frames are 6472 * also automatically adjusted to word align the IP 6473 * header (i.e. two null bytes are inserted before 6474 * the Ethernet header). As a result the data 6475 * DMA'd by the controller into the mbuf looks 6476 * like this: 6477 * 6478 * +---------+-----+---------------------+-----+ 6479 * | l2_fhdr | pad | packet data | FCS | 6480 * +---------+-----+---------------------+-----+ 6481 * 6482 * The l2_fhdr needs to be checked and skipped and 6483 * the FCS needs to be stripped before sending the 6484 * packet up the stack. 6485 */ 6486 l2fhdr = mtod(m0, struct l2_fhdr *); 6487 6488 /* Get the packet data + FCS length and the status. */ 6489 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6490 status = l2fhdr->l2_fhdr_status; 6491 6492 /* 6493 * Skip over the l2_fhdr and pad, resulting in the 6494 * following data in the mbuf: 6495 * +---------------------+-----+ 6496 * | packet data | FCS | 6497 * +---------------------+-----+ 6498 */ 6499 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6500 6501 /* 6502 * When split header mode is used, an ethernet frame 6503 * may be split across the receive chain and the 6504 * page chain. If that occurs an mbuf cluster must be 6505 * reassembled from the individual mbuf pieces. 6506 */ 6507 if (bce_hdr_split == TRUE) { 6508 /* 6509 * Check whether the received frame fits in a single 6510 * mbuf or not (i.e. packet data + FCS <= 6511 * sc->rx_bd_mbuf_data_len bytes). 6512 */ 6513 if (pkt_len > m0->m_len) { 6514 /* 6515 * The received frame is larger than a single mbuf. 6516 * If the frame was a TCP frame then only the TCP 6517 * header is placed in the mbuf, the remaining 6518 * payload (including FCS) is placed in the page 6519 * chain, the SPLIT flag is set, and the header 6520 * length is placed in the IP checksum field. 6521 * If the frame is not a TCP frame then the mbuf 6522 * is filled and the remaining bytes are placed 6523 * in the page chain. 6524 */ 6525 6526 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6527 "packet.\n", __FUNCTION__); 6528 DBRUN(sc->split_header_frames_rcvd++); 6529 6530 /* 6531 * When the page chain is enabled and the TCP 6532 * header has been split from the TCP payload, 6533 * the ip_xsum structure will reflect the length 6534 * of the TCP header, not the IP checksum. Set 6535 * the packet length of the mbuf accordingly. 6536 */ 6537 if (status & L2_FHDR_STATUS_SPLIT) { 6538 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6539 DBRUN(sc->split_header_tcp_frames_rcvd++); 6540 } 6541 6542 rem_len = pkt_len - m0->m_len; 6543 6544 /* Pull mbufs off the page chain for any remaining data. */ 6545 while (rem_len > 0) { 6546 struct mbuf *m_pg; 6547 6548 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6549 6550 /* Remove the mbuf from the page chain. */ 6551 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6552 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6553 DBRUN(sc->debug_pg_mbuf_alloc--); 6554 sc->free_pg_bd++; 6555 6556 /* Unmap the page chain mbuf from DMA space. */ 6557 bus_dmamap_sync(sc->pg_mbuf_tag, 6558 sc->pg_mbuf_map[sw_pg_cons_idx], 6559 BUS_DMASYNC_POSTREAD); 6560 bus_dmamap_unload(sc->pg_mbuf_tag, 6561 sc->pg_mbuf_map[sw_pg_cons_idx]); 6562 6563 /* Adjust the mbuf length. */ 6564 if (rem_len < m_pg->m_len) { 6565 /* The mbuf chain is complete. */ 6566 m_pg->m_len = rem_len; 6567 rem_len = 0; 6568 } else { 6569 /* More packet data is waiting. */ 6570 rem_len -= m_pg->m_len; 6571 } 6572 6573 /* Concatenate the mbuf cluster to the mbuf. */ 6574 m_cat(m0, m_pg); 6575 6576 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6577 } 6578 6579 /* Set the total packet length. */ 6580 m0->m_pkthdr.len = pkt_len; 6581 6582 } else { 6583 /* 6584 * The received packet is small and fits in a 6585 * single mbuf (i.e. the l2_fhdr + pad + packet + 6586 * FCS <= MHLEN). In other words, the packet is 6587 * 154 bytes or less in size. 6588 */ 6589 6590 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6591 "packet.\n", __FUNCTION__); 6592 6593 /* Set the total packet length. */ 6594 m0->m_pkthdr.len = m0->m_len = pkt_len; 6595 } 6596 } else 6597 /* Set the total packet length. */ 6598 m0->m_pkthdr.len = m0->m_len = pkt_len; 6599 6600 /* Remove the trailing Ethernet FCS. */ 6601 m_adj(m0, -ETHER_CRC_LEN); 6602 6603 /* Check that the resulting mbuf chain is valid. */ 6604 DBRUN(m_sanity(m0, FALSE)); 6605 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6606 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6607 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6608 m_print(m0, 128)); 6609 6610 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6611 sc->l2fhdr_error_sim_count++; 6612 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6613 6614 /* Check the received frame for errors. */ 6615 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6616 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6617 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6618 /* Log the error and release the mbuf. */ 6619 sc->l2fhdr_error_count++; 6620 m_freem(m0); 6621 m0 = NULL; 6622 goto bce_rx_intr_next_rx; 6623 } 6624 6625 /* Send the packet to the appropriate interface. */ 6626 m0->m_pkthdr.rcvif = ifp; 6627 6628 /* Assume no hardware checksum. */ 6629 m0->m_pkthdr.csum_flags = 0; 6630 6631 /* Validate the checksum if offload enabled. */ 6632 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 6633 /* Check for an IP datagram. */ 6634 if (!(status & L2_FHDR_STATUS_SPLIT) && 6635 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6636 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6637 DBRUN(sc->csum_offload_ip++); 6638 /* Check if the IP checksum is valid. */ 6639 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6640 m0->m_pkthdr.csum_flags |= 6641 CSUM_IP_VALID; 6642 } 6643 6644 /* Check for a valid TCP/UDP frame. */ 6645 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6646 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6647 /* Check for a good TCP/UDP checksum. */ 6648 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6649 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6650 DBRUN(sc->csum_offload_tcp_udp++); 6651 m0->m_pkthdr.csum_data = 6652 l2fhdr->l2_fhdr_tcp_udp_xsum; 6653 m0->m_pkthdr.csum_flags |= 6654 (CSUM_DATA_VALID 6655 | CSUM_PSEUDO_HDR); 6656 } 6657 } 6658 } 6659 6660 /* Attach the VLAN tag. */ 6661 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6662 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6663 DBRUN(sc->vlan_tagged_frames_rcvd++); 6664 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 6665 DBRUN(sc->vlan_tagged_frames_stripped++); 6666 m0->m_pkthdr.ether_vtag = 6667 l2fhdr->l2_fhdr_vlan_tag; 6668 m0->m_flags |= M_VLANTAG; 6669 } else { 6670 /* 6671 * bce(4) controllers can't disable VLAN 6672 * tag stripping if management firmware 6673 * (ASF/IPMI/UMP) is running. So we always 6674 * strip VLAN tag and manually reconstruct 6675 * the VLAN frame by appending stripped 6676 * VLAN tag in driver if VLAN tag stripping 6677 * was disabled. 6678 * 6679 * TODO: LLC SNAP handling. 6680 */ 6681 bcopy(mtod(m0, uint8_t *), 6682 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6683 ETHER_ADDR_LEN * 2); 6684 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6685 vh = mtod(m0, struct ether_vlan_header *); 6686 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6687 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6688 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6689 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6690 } 6691 } 6692 6693 /* Increment received packet statistics. */ 6694 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 6695 6696 bce_rx_intr_next_rx: 6697 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6698 6699 /* If we have a packet, pass it up the stack */ 6700 if (m0) { 6701 /* Make sure we don't lose our place when we release the lock. */ 6702 sc->rx_cons = sw_rx_cons; 6703 sc->pg_cons = sw_pg_cons; 6704 6705 BCE_UNLOCK(sc); 6706 if_input(ifp, m0); 6707 BCE_LOCK(sc); 6708 6709 /* Recover our place. */ 6710 sw_rx_cons = sc->rx_cons; 6711 sw_pg_cons = sc->pg_cons; 6712 } 6713 6714 /* Refresh hw_cons to see if there's new work */ 6715 if (sw_rx_cons == hw_rx_cons) 6716 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6717 } 6718 6719 /* No new packets. Refill the page chain. */ 6720 if (bce_hdr_split == TRUE) { 6721 sc->pg_cons = sw_pg_cons; 6722 bce_fill_pg_chain(sc); 6723 } 6724 6725 /* No new packets. Refill the RX chain. */ 6726 sc->rx_cons = sw_rx_cons; 6727 bce_fill_rx_chain(sc); 6728 6729 /* Prepare the page chain pages to be accessed by the NIC. */ 6730 for (int i = 0; i < sc->rx_pages; i++) 6731 bus_dmamap_sync(sc->rx_bd_chain_tag, 6732 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6733 6734 if (bce_hdr_split == TRUE) { 6735 for (int i = 0; i < sc->pg_pages; i++) 6736 bus_dmamap_sync(sc->pg_bd_chain_tag, 6737 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6738 } 6739 6740 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6741 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6742 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6743 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6744 } 6745 6746 /****************************************************************************/ 6747 /* Reads the transmit consumer value from the status block (skipping over */ 6748 /* chain page pointer if necessary). */ 6749 /* */ 6750 /* Returns: */ 6751 /* hw_cons */ 6752 /****************************************************************************/ 6753 static inline u16 6754 bce_get_hw_tx_cons(struct bce_softc *sc) 6755 { 6756 u16 hw_cons; 6757 6758 mb(); 6759 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6760 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6761 hw_cons++; 6762 6763 return hw_cons; 6764 } 6765 6766 /****************************************************************************/ 6767 /* Handles transmit completion interrupt events. */ 6768 /* */ 6769 /* Returns: */ 6770 /* Nothing. */ 6771 /****************************************************************************/ 6772 static void 6773 bce_tx_intr(struct bce_softc *sc) 6774 { 6775 if_t ifp = sc->bce_ifp; 6776 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6777 6778 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6779 DBRUN(sc->interrupts_tx++); 6780 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6781 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6782 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6783 6784 BCE_LOCK_ASSERT(sc); 6785 6786 /* Get the hardware's view of the TX consumer index. */ 6787 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6788 sw_tx_cons = sc->tx_cons; 6789 6790 /* Prevent speculative reads of the status block. */ 6791 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6792 BUS_SPACE_BARRIER_READ); 6793 6794 /* Cycle through any completed TX chain page entries. */ 6795 while (sw_tx_cons != hw_tx_cons) { 6796 #ifdef BCE_DEBUG 6797 struct tx_bd *txbd = NULL; 6798 #endif 6799 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6800 6801 DBPRINT(sc, BCE_INFO_SEND, 6802 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6803 "sw_tx_chain_cons = 0x%04X\n", 6804 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6805 6806 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6807 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6808 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6809 (int) MAX_TX_BD_ALLOC); 6810 bce_breakpoint(sc)); 6811 6812 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6813 [TX_IDX(sw_tx_chain_cons)]); 6814 6815 DBRUNIF((txbd == NULL), 6816 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6817 __FILE__, __LINE__, sw_tx_chain_cons); 6818 bce_breakpoint(sc)); 6819 6820 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6821 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6822 6823 /* 6824 * Free the associated mbuf. Remember 6825 * that only the last tx_bd of a packet 6826 * has an mbuf pointer and DMA map. 6827 */ 6828 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6829 /* Validate that this is the last tx_bd. */ 6830 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6831 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6832 "txmbuf == NULL!\n", __FILE__, __LINE__); 6833 bce_breakpoint(sc)); 6834 6835 DBRUNMSG(BCE_INFO_SEND, 6836 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6837 "from tx_bd[0x%04X]\n", __FUNCTION__, 6838 sw_tx_chain_cons)); 6839 6840 /* Unmap the mbuf. */ 6841 bus_dmamap_unload(sc->tx_mbuf_tag, 6842 sc->tx_mbuf_map[sw_tx_chain_cons]); 6843 6844 /* Free the mbuf. */ 6845 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6846 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6847 DBRUN(sc->debug_tx_mbuf_alloc--); 6848 6849 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 6850 } 6851 6852 sc->used_tx_bd--; 6853 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6854 6855 /* Refresh hw_cons to see if there's new work. */ 6856 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6857 6858 /* Prevent speculative reads of the status block. */ 6859 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6860 BUS_SPACE_BARRIER_READ); 6861 } 6862 6863 /* Clear the TX timeout timer. */ 6864 sc->watchdog_timer = 0; 6865 6866 /* Clear the tx hardware queue full flag. */ 6867 if (sc->used_tx_bd < sc->max_tx_bd) { 6868 DBRUNIF((if_getdrvflags(ifp) & IFF_DRV_OACTIVE), 6869 DBPRINT(sc, BCE_INFO_SEND, 6870 "%s(): Open TX chain! %d/%d (used/total)\n", 6871 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6872 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 6873 } 6874 6875 sc->tx_cons = sw_tx_cons; 6876 6877 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6878 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6879 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6880 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6881 } 6882 6883 /****************************************************************************/ 6884 /* Disables interrupt generation. */ 6885 /* */ 6886 /* Returns: */ 6887 /* Nothing. */ 6888 /****************************************************************************/ 6889 static void 6890 bce_disable_intr(struct bce_softc *sc) 6891 { 6892 DBENTER(BCE_VERBOSE_INTR); 6893 6894 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6895 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6896 6897 DBEXIT(BCE_VERBOSE_INTR); 6898 } 6899 6900 /****************************************************************************/ 6901 /* Enables interrupt generation. */ 6902 /* */ 6903 /* Returns: */ 6904 /* Nothing. */ 6905 /****************************************************************************/ 6906 static void 6907 bce_enable_intr(struct bce_softc *sc, int coal_now) 6908 { 6909 DBENTER(BCE_VERBOSE_INTR); 6910 6911 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6912 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6913 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6914 6915 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6916 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6917 6918 /* Force an immediate interrupt (whether there is new data or not). */ 6919 if (coal_now) 6920 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6921 6922 DBEXIT(BCE_VERBOSE_INTR); 6923 } 6924 6925 /****************************************************************************/ 6926 /* Handles controller initialization. */ 6927 /* */ 6928 /* Returns: */ 6929 /* Nothing. */ 6930 /****************************************************************************/ 6931 static void 6932 bce_init_locked(struct bce_softc *sc) 6933 { 6934 if_t ifp; 6935 u32 ether_mtu = 0; 6936 6937 DBENTER(BCE_VERBOSE_RESET); 6938 6939 BCE_LOCK_ASSERT(sc); 6940 6941 ifp = sc->bce_ifp; 6942 6943 /* Check if the driver is still running and bail out if it is. */ 6944 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 6945 goto bce_init_locked_exit; 6946 6947 bce_stop(sc); 6948 6949 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6950 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6951 __FILE__, __LINE__); 6952 goto bce_init_locked_exit; 6953 } 6954 6955 if (bce_chipinit(sc)) { 6956 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6957 __FILE__, __LINE__); 6958 goto bce_init_locked_exit; 6959 } 6960 6961 if (bce_blockinit(sc)) { 6962 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6963 __FILE__, __LINE__); 6964 goto bce_init_locked_exit; 6965 } 6966 6967 /* Load our MAC address. */ 6968 bcopy(if_getlladdr(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6969 bce_set_mac_addr(sc); 6970 6971 if (bce_hdr_split == FALSE) 6972 bce_get_rx_buffer_sizes(sc, if_getmtu(ifp)); 6973 /* 6974 * Calculate and program the hardware Ethernet MTU 6975 * size. Be generous on the receive if we have room 6976 * and allowed by the user. 6977 */ 6978 if (bce_strict_rx_mtu == TRUE) 6979 ether_mtu = if_getmtu(ifp); 6980 else { 6981 if (bce_hdr_split == TRUE) { 6982 if (if_getmtu(ifp) <= sc->rx_bd_mbuf_data_len + MCLBYTES) 6983 ether_mtu = sc->rx_bd_mbuf_data_len + 6984 MCLBYTES; 6985 else 6986 ether_mtu = if_getmtu(ifp); 6987 } else { 6988 if (if_getmtu(ifp) <= sc->rx_bd_mbuf_data_len) 6989 ether_mtu = sc->rx_bd_mbuf_data_len; 6990 else 6991 ether_mtu = if_getmtu(ifp); 6992 } 6993 } 6994 6995 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6996 6997 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 6998 __FUNCTION__, ether_mtu); 6999 7000 /* Program the mtu, enabling jumbo frame support if necessary. */ 7001 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7002 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7003 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7004 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7005 else 7006 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7007 7008 /* Program appropriate promiscuous/multicast filtering. */ 7009 bce_set_rx_mode(sc); 7010 7011 if (bce_hdr_split == TRUE) { 7012 /* Init page buffer descriptor chain. */ 7013 bce_init_pg_chain(sc); 7014 } 7015 7016 /* Init RX buffer descriptor chain. */ 7017 bce_init_rx_chain(sc); 7018 7019 /* Init TX buffer descriptor chain. */ 7020 bce_init_tx_chain(sc); 7021 7022 /* Enable host interrupts. */ 7023 bce_enable_intr(sc, 1); 7024 7025 bce_ifmedia_upd_locked(ifp); 7026 7027 /* Let the OS know the driver is up and running. */ 7028 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 7029 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 7030 7031 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7032 7033 bce_init_locked_exit: 7034 DBEXIT(BCE_VERBOSE_RESET); 7035 } 7036 7037 /****************************************************************************/ 7038 /* Initialize the controller just enough so that any management firmware */ 7039 /* running on the device will continue to operate correctly. */ 7040 /* */ 7041 /* Returns: */ 7042 /* Nothing. */ 7043 /****************************************************************************/ 7044 static void 7045 bce_mgmt_init_locked(struct bce_softc *sc) 7046 { 7047 if_t ifp; 7048 7049 DBENTER(BCE_VERBOSE_RESET); 7050 7051 BCE_LOCK_ASSERT(sc); 7052 7053 /* Bail out if management firmware is not running. */ 7054 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7055 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7056 "No management firmware running...\n"); 7057 goto bce_mgmt_init_locked_exit; 7058 } 7059 7060 ifp = sc->bce_ifp; 7061 7062 /* Enable all critical blocks in the MAC. */ 7063 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7064 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7065 DELAY(20); 7066 7067 bce_ifmedia_upd_locked(ifp); 7068 7069 bce_mgmt_init_locked_exit: 7070 DBEXIT(BCE_VERBOSE_RESET); 7071 } 7072 7073 /****************************************************************************/ 7074 /* Handles controller initialization when called from an unlocked routine. */ 7075 /* */ 7076 /* Returns: */ 7077 /* Nothing. */ 7078 /****************************************************************************/ 7079 static void 7080 bce_init(void *xsc) 7081 { 7082 struct bce_softc *sc = xsc; 7083 7084 DBENTER(BCE_VERBOSE_RESET); 7085 7086 BCE_LOCK(sc); 7087 bce_init_locked(sc); 7088 BCE_UNLOCK(sc); 7089 7090 DBEXIT(BCE_VERBOSE_RESET); 7091 } 7092 7093 /****************************************************************************/ 7094 /* Modifies an mbuf for TSO on the hardware. */ 7095 /* */ 7096 /* Returns: */ 7097 /* Pointer to a modified mbuf. */ 7098 /****************************************************************************/ 7099 static struct mbuf * 7100 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7101 { 7102 struct mbuf *m; 7103 struct ether_header *eh; 7104 struct ip *ip; 7105 struct tcphdr *th; 7106 u16 etype; 7107 int hdr_len __unused, ip_len __unused, ip_hlen = 0, tcp_hlen = 0; 7108 7109 DBRUN(sc->tso_frames_requested++); 7110 7111 ip_len = 0; 7112 /* Controller may modify mbuf chains. */ 7113 if (M_WRITABLE(*m_head) == 0) { 7114 m = m_dup(*m_head, M_NOWAIT); 7115 m_freem(*m_head); 7116 if (m == NULL) { 7117 sc->mbuf_alloc_failed_count++; 7118 *m_head = NULL; 7119 return (NULL); 7120 } 7121 *m_head = m; 7122 } 7123 7124 /* 7125 * For TSO the controller needs two pieces of info, 7126 * the MSS and the IP+TCP options length. 7127 */ 7128 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7129 if (m == NULL) { 7130 *m_head = NULL; 7131 return (NULL); 7132 } 7133 eh = mtod(m, struct ether_header *); 7134 etype = ntohs(eh->ether_type); 7135 7136 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7137 switch (etype) { 7138 case ETHERTYPE_IP: 7139 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7140 /* TSO only supported for TCP protocol. */ 7141 if (ip->ip_p != IPPROTO_TCP) { 7142 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7143 __FILE__, __LINE__); 7144 m_freem(*m_head); 7145 *m_head = NULL; 7146 return (NULL); 7147 } 7148 7149 /* Get IP header length in bytes (min 20) */ 7150 ip_hlen = ip->ip_hl << 2; 7151 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7152 sizeof(struct tcphdr)); 7153 if (m == NULL) { 7154 *m_head = NULL; 7155 return (NULL); 7156 } 7157 7158 /* Get the TCP header length in bytes (min 20) */ 7159 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7160 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7161 tcp_hlen = (th->th_off << 2); 7162 7163 /* Make sure all IP/TCP options live in the same buffer. */ 7164 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7165 tcp_hlen); 7166 if (m == NULL) { 7167 *m_head = NULL; 7168 return (NULL); 7169 } 7170 7171 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7172 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7173 ip_len = ip->ip_len; 7174 ip->ip_len = 0; 7175 ip->ip_sum = 0; 7176 break; 7177 case ETHERTYPE_IPV6: 7178 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7179 __FILE__, __LINE__); 7180 m_freem(*m_head); 7181 *m_head = NULL; 7182 return (NULL); 7183 /* NOT REACHED */ 7184 default: 7185 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7186 __FILE__, __LINE__); 7187 m_freem(*m_head); 7188 *m_head = NULL; 7189 return (NULL); 7190 } 7191 7192 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7193 7194 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7195 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7196 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7197 tcp_hlen, ip_len); 7198 7199 /* Set the LSO flag in the TX BD */ 7200 *flags |= TX_BD_FLAGS_SW_LSO; 7201 7202 /* Set the length of IP + TCP options (in 32 bit words) */ 7203 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7204 sizeof(struct tcphdr)) >> 2) << 8); 7205 7206 DBRUN(sc->tso_frames_completed++); 7207 return (*m_head); 7208 } 7209 7210 /****************************************************************************/ 7211 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7212 /* memory visible to the controller. */ 7213 /* */ 7214 /* Returns: */ 7215 /* 0 for success, positive value for failure. */ 7216 /* Modified: */ 7217 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7218 /****************************************************************************/ 7219 static int 7220 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7221 { 7222 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7223 bus_dmamap_t map; 7224 struct tx_bd *txbd = NULL; 7225 struct mbuf *m0; 7226 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7227 u32 prod_bseq; 7228 7229 #ifdef BCE_DEBUG 7230 u16 debug_prod; 7231 #endif 7232 7233 int i, error, nsegs, rc = 0; 7234 7235 DBENTER(BCE_VERBOSE_SEND); 7236 7237 /* Make sure we have room in the TX chain. */ 7238 if (sc->used_tx_bd >= sc->max_tx_bd) 7239 goto bce_tx_encap_exit; 7240 7241 /* Transfer any checksum offload flags to the bd. */ 7242 m0 = *m_head; 7243 if (m0->m_pkthdr.csum_flags) { 7244 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7245 m0 = bce_tso_setup(sc, m_head, &flags); 7246 if (m0 == NULL) { 7247 DBRUN(sc->tso_frames_failed++); 7248 goto bce_tx_encap_exit; 7249 } 7250 mss = htole16(m0->m_pkthdr.tso_segsz); 7251 } else { 7252 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7253 flags |= TX_BD_FLAGS_IP_CKSUM; 7254 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7255 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7256 } 7257 } 7258 7259 /* Transfer any VLAN tags to the bd. */ 7260 if (m0->m_flags & M_VLANTAG) { 7261 flags |= TX_BD_FLAGS_VLAN_TAG; 7262 vlan_tag = m0->m_pkthdr.ether_vtag; 7263 } 7264 7265 /* Map the mbuf into DMAable memory. */ 7266 prod = sc->tx_prod; 7267 chain_prod = TX_CHAIN_IDX(prod); 7268 map = sc->tx_mbuf_map[chain_prod]; 7269 7270 /* Map the mbuf into our DMA address space. */ 7271 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7272 segs, &nsegs, BUS_DMA_NOWAIT); 7273 7274 /* Check if the DMA mapping was successful */ 7275 if (error == EFBIG) { 7276 sc->mbuf_frag_count++; 7277 7278 /* Try to defrag the mbuf. */ 7279 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7280 if (m0 == NULL) { 7281 /* Defrag was unsuccessful */ 7282 m_freem(*m_head); 7283 *m_head = NULL; 7284 sc->mbuf_alloc_failed_count++; 7285 rc = ENOBUFS; 7286 goto bce_tx_encap_exit; 7287 } 7288 7289 /* Defrag was successful, try mapping again */ 7290 *m_head = m0; 7291 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7292 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7293 7294 /* Still getting an error after a defrag. */ 7295 if (error == ENOMEM) { 7296 /* Insufficient DMA buffers available. */ 7297 sc->dma_map_addr_tx_failed_count++; 7298 rc = error; 7299 goto bce_tx_encap_exit; 7300 } else if (error != 0) { 7301 /* Release it and return an error. */ 7302 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7303 "TX chain!\n", __FILE__, __LINE__); 7304 m_freem(m0); 7305 *m_head = NULL; 7306 sc->dma_map_addr_tx_failed_count++; 7307 rc = ENOBUFS; 7308 goto bce_tx_encap_exit; 7309 } 7310 } else if (error == ENOMEM) { 7311 /* Insufficient DMA buffers available. */ 7312 sc->dma_map_addr_tx_failed_count++; 7313 rc = error; 7314 goto bce_tx_encap_exit; 7315 } else if (error != 0) { 7316 m_freem(m0); 7317 *m_head = NULL; 7318 sc->dma_map_addr_tx_failed_count++; 7319 rc = error; 7320 goto bce_tx_encap_exit; 7321 } 7322 7323 /* Make sure there's room in the chain */ 7324 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7325 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7326 rc = ENOBUFS; 7327 goto bce_tx_encap_exit; 7328 } 7329 7330 /* prod points to an empty tx_bd at this point. */ 7331 prod_bseq = sc->tx_prod_bseq; 7332 7333 #ifdef BCE_DEBUG 7334 debug_prod = chain_prod; 7335 #endif 7336 7337 DBPRINT(sc, BCE_INFO_SEND, 7338 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7339 "prod_bseq = 0x%08X\n", 7340 __FUNCTION__, prod, chain_prod, prod_bseq); 7341 7342 /* 7343 * Cycle through each mbuf segment that makes up 7344 * the outgoing frame, gathering the mapping info 7345 * for that segment and creating a tx_bd for 7346 * the mbuf. 7347 */ 7348 for (i = 0; i < nsegs ; i++) { 7349 chain_prod = TX_CHAIN_IDX(prod); 7350 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7351 [TX_IDX(chain_prod)]; 7352 7353 txbd->tx_bd_haddr_lo = 7354 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7355 txbd->tx_bd_haddr_hi = 7356 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7357 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7358 htole16(segs[i].ds_len); 7359 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7360 txbd->tx_bd_flags = htole16(flags); 7361 prod_bseq += segs[i].ds_len; 7362 if (i == 0) 7363 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7364 prod = NEXT_TX_BD(prod); 7365 } 7366 7367 /* Set the END flag on the last TX buffer descriptor. */ 7368 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7369 7370 DBRUNMSG(BCE_EXTREME_SEND, 7371 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7372 7373 /* 7374 * Ensure that the mbuf pointer for this transmission 7375 * is placed at the array index of the last 7376 * descriptor in this chain. This is done 7377 * because a single map is used for all 7378 * segments of the mbuf and we don't want to 7379 * unload the map before all of the segments 7380 * have been freed. 7381 */ 7382 sc->tx_mbuf_ptr[chain_prod] = m0; 7383 sc->used_tx_bd += nsegs; 7384 7385 /* Update some debug statistic counters */ 7386 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7387 sc->tx_hi_watermark = sc->used_tx_bd); 7388 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7389 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7390 7391 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7392 7393 /* prod points to the next free tx_bd at this point. */ 7394 sc->tx_prod = prod; 7395 sc->tx_prod_bseq = prod_bseq; 7396 7397 /* Tell the chip about the waiting TX frames. */ 7398 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7399 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7400 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7401 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7402 7403 bce_tx_encap_exit: 7404 DBEXIT(BCE_VERBOSE_SEND); 7405 return(rc); 7406 } 7407 7408 /****************************************************************************/ 7409 /* Main transmit routine when called from another routine with a lock. */ 7410 /* */ 7411 /* Returns: */ 7412 /* Nothing. */ 7413 /****************************************************************************/ 7414 static void 7415 bce_start_locked(if_t ifp) 7416 { 7417 struct bce_softc *sc = if_getsoftc(ifp); 7418 struct mbuf *m_head = NULL; 7419 int count = 0; 7420 u16 tx_prod, tx_chain_prod __unused; 7421 7422 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7423 7424 BCE_LOCK_ASSERT(sc); 7425 7426 /* prod points to the next free tx_bd. */ 7427 tx_prod = sc->tx_prod; 7428 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7429 7430 DBPRINT(sc, BCE_INFO_SEND, 7431 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7432 "tx_prod_bseq = 0x%08X\n", 7433 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7434 7435 /* If there's no link or the transmit queue is empty then just exit. */ 7436 if (sc->bce_link_up == FALSE) { 7437 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7438 __FUNCTION__); 7439 goto bce_start_locked_exit; 7440 } 7441 7442 if (if_sendq_empty(ifp)) { 7443 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7444 __FUNCTION__); 7445 goto bce_start_locked_exit; 7446 } 7447 7448 /* 7449 * Keep adding entries while there is space in the ring. 7450 */ 7451 while (sc->used_tx_bd < sc->max_tx_bd) { 7452 /* Check for any frames to send. */ 7453 m_head = if_dequeue(ifp); 7454 7455 /* Stop when the transmit queue is empty. */ 7456 if (m_head == NULL) 7457 break; 7458 7459 /* 7460 * Pack the data into the transmit ring. If we 7461 * don't have room, place the mbuf back at the 7462 * head of the queue and set the OACTIVE flag 7463 * to wait for the NIC to drain the chain. 7464 */ 7465 if (bce_tx_encap(sc, &m_head)) { 7466 if (m_head != NULL) 7467 if_sendq_prepend(ifp, m_head); 7468 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 7469 DBPRINT(sc, BCE_INFO_SEND, 7470 "TX chain is closed for business! Total " 7471 "tx_bd used = %d\n", sc->used_tx_bd); 7472 break; 7473 } 7474 7475 count++; 7476 7477 /* Send a copy of the frame to any BPF listeners. */ 7478 ETHER_BPF_MTAP(ifp, m_head); 7479 } 7480 7481 /* Exit if no packets were dequeued. */ 7482 if (count == 0) { 7483 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7484 "dequeued\n", __FUNCTION__); 7485 goto bce_start_locked_exit; 7486 } 7487 7488 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7489 "send queue.\n", __FUNCTION__, count); 7490 7491 /* Set the tx timeout. */ 7492 sc->watchdog_timer = BCE_TX_TIMEOUT; 7493 7494 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7495 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7496 7497 bce_start_locked_exit: 7498 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7499 } 7500 7501 /****************************************************************************/ 7502 /* Main transmit routine when called from another routine without a lock. */ 7503 /* */ 7504 /* Returns: */ 7505 /* Nothing. */ 7506 /****************************************************************************/ 7507 static void 7508 bce_start(if_t ifp) 7509 { 7510 struct bce_softc *sc = if_getsoftc(ifp); 7511 7512 DBENTER(BCE_VERBOSE_SEND); 7513 7514 BCE_LOCK(sc); 7515 bce_start_locked(ifp); 7516 BCE_UNLOCK(sc); 7517 7518 DBEXIT(BCE_VERBOSE_SEND); 7519 } 7520 7521 /****************************************************************************/ 7522 /* Handles any IOCTL calls from the operating system. */ 7523 /* */ 7524 /* Returns: */ 7525 /* 0 for success, positive value for failure. */ 7526 /****************************************************************************/ 7527 static int 7528 bce_ioctl(if_t ifp, u_long command, caddr_t data) 7529 { 7530 struct bce_softc *sc = if_getsoftc(ifp); 7531 struct ifreq *ifr = (struct ifreq *) data; 7532 struct mii_data *mii; 7533 int mask, error = 0; 7534 7535 DBENTER(BCE_VERBOSE_MISC); 7536 7537 switch(command) { 7538 /* Set the interface MTU. */ 7539 case SIOCSIFMTU: 7540 /* Check that the MTU setting is supported. */ 7541 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7542 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7543 error = EINVAL; 7544 break; 7545 } 7546 7547 DBPRINT(sc, BCE_INFO_MISC, 7548 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7549 (int) if_getmtu(ifp), (int) ifr->ifr_mtu); 7550 7551 BCE_LOCK(sc); 7552 if_setmtu(ifp, ifr->ifr_mtu); 7553 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 7554 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 7555 bce_init_locked(sc); 7556 } 7557 BCE_UNLOCK(sc); 7558 break; 7559 7560 /* Set interface flags. */ 7561 case SIOCSIFFLAGS: 7562 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7563 7564 BCE_LOCK(sc); 7565 7566 /* Check if the interface is up. */ 7567 if (if_getflags(ifp) & IFF_UP) { 7568 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 7569 /* Change promiscuous/multicast flags as necessary. */ 7570 bce_set_rx_mode(sc); 7571 } else { 7572 /* Start the HW */ 7573 bce_init_locked(sc); 7574 } 7575 } else { 7576 /* The interface is down, check if driver is running. */ 7577 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 7578 bce_stop(sc); 7579 7580 /* If MFW is running, restart the controller a bit. */ 7581 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7582 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7583 bce_chipinit(sc); 7584 bce_mgmt_init_locked(sc); 7585 } 7586 } 7587 } 7588 7589 BCE_UNLOCK(sc); 7590 break; 7591 7592 /* Add/Delete multicast address */ 7593 case SIOCADDMULTI: 7594 case SIOCDELMULTI: 7595 DBPRINT(sc, BCE_VERBOSE_MISC, 7596 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7597 7598 BCE_LOCK(sc); 7599 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 7600 bce_set_rx_mode(sc); 7601 BCE_UNLOCK(sc); 7602 7603 break; 7604 7605 /* Set/Get Interface media */ 7606 case SIOCSIFMEDIA: 7607 case SIOCGIFMEDIA: 7608 DBPRINT(sc, BCE_VERBOSE_MISC, 7609 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7610 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7611 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7612 command); 7613 else { 7614 mii = device_get_softc(sc->bce_miibus); 7615 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7616 command); 7617 } 7618 break; 7619 7620 /* Set interface capability */ 7621 case SIOCSIFCAP: 7622 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 7623 DBPRINT(sc, BCE_INFO_MISC, 7624 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7625 7626 /* Toggle the TX checksum capabilities enable flag. */ 7627 if (mask & IFCAP_TXCSUM && 7628 if_getcapabilities(ifp) & IFCAP_TXCSUM) { 7629 if_togglecapenable(ifp, IFCAP_TXCSUM); 7630 if (IFCAP_TXCSUM & if_getcapenable(ifp)) 7631 if_sethwassistbits(ifp, BCE_IF_HWASSIST, 0); 7632 else 7633 if_sethwassistbits(ifp, 0, BCE_IF_HWASSIST); 7634 } 7635 7636 /* Toggle the RX checksum capabilities enable flag. */ 7637 if (mask & IFCAP_RXCSUM && 7638 if_getcapabilities(ifp) & IFCAP_RXCSUM) 7639 if_togglecapenable(ifp, IFCAP_RXCSUM); 7640 7641 /* Toggle the TSO capabilities enable flag. */ 7642 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7643 if_getcapabilities(ifp) & IFCAP_TSO4) { 7644 if_togglecapenable(ifp, IFCAP_TSO4); 7645 if (IFCAP_TSO4 & if_getcapenable(ifp)) 7646 if_sethwassistbits(ifp, CSUM_TSO, 0); 7647 else 7648 if_sethwassistbits(ifp, 0, CSUM_TSO); 7649 } 7650 7651 if (mask & IFCAP_VLAN_HWCSUM && 7652 if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) 7653 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 7654 7655 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7656 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 7657 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 7658 /* 7659 * Don't actually disable VLAN tag stripping as 7660 * management firmware (ASF/IPMI/UMP) requires the 7661 * feature. If VLAN tag stripping is disabled driver 7662 * will manually reconstruct the VLAN frame by 7663 * appending stripped VLAN tag. 7664 */ 7665 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7666 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING)) { 7667 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 7668 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) 7669 == 0) 7670 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 7671 } 7672 VLAN_CAPABILITIES(ifp); 7673 break; 7674 default: 7675 /* We don't know how to handle the IOCTL, pass it on. */ 7676 error = ether_ioctl(ifp, command, data); 7677 break; 7678 } 7679 7680 DBEXIT(BCE_VERBOSE_MISC); 7681 return(error); 7682 } 7683 7684 /****************************************************************************/ 7685 /* Transmit timeout handler. */ 7686 /* */ 7687 /* Returns: */ 7688 /* Nothing. */ 7689 /****************************************************************************/ 7690 static void 7691 bce_watchdog(struct bce_softc *sc) 7692 { 7693 uint32_t status; 7694 7695 DBENTER(BCE_EXTREME_SEND); 7696 7697 BCE_LOCK_ASSERT(sc); 7698 7699 status = 0; 7700 /* If the watchdog timer hasn't expired then just exit. */ 7701 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7702 goto bce_watchdog_exit; 7703 7704 status = REG_RD(sc, BCE_EMAC_RX_STATUS); 7705 /* If pause frames are active then don't reset the hardware. */ 7706 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) { 7707 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) { 7708 /* 7709 * If link partner has us in XOFF state then wait for 7710 * the condition to clear. 7711 */ 7712 sc->watchdog_timer = BCE_TX_TIMEOUT; 7713 goto bce_watchdog_exit; 7714 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 && 7715 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) { 7716 /* 7717 * If we're not currently XOFF'ed but have recently 7718 * been XOFF'd/XON'd then assume that's delaying TX 7719 * this time around. 7720 */ 7721 sc->watchdog_timer = BCE_TX_TIMEOUT; 7722 goto bce_watchdog_exit; 7723 } 7724 /* 7725 * Any other condition is unexpected and the controller 7726 * should be reset. 7727 */ 7728 } 7729 7730 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7731 __FILE__, __LINE__); 7732 7733 DBRUNMSG(BCE_INFO, 7734 bce_dump_driver_state(sc); 7735 bce_dump_status_block(sc); 7736 bce_dump_stats_block(sc); 7737 bce_dump_ftqs(sc); 7738 bce_dump_txp_state(sc, 0); 7739 bce_dump_rxp_state(sc, 0); 7740 bce_dump_tpat_state(sc, 0); 7741 bce_dump_cp_state(sc, 0); 7742 bce_dump_com_state(sc, 0)); 7743 7744 DBRUN(bce_breakpoint(sc)); 7745 7746 if_setdrvflagbits(sc->bce_ifp, 0, IFF_DRV_RUNNING); 7747 7748 bce_init_locked(sc); 7749 sc->watchdog_timeouts++; 7750 7751 bce_watchdog_exit: 7752 REG_WR(sc, BCE_EMAC_RX_STATUS, status); 7753 DBEXIT(BCE_EXTREME_SEND); 7754 } 7755 7756 /* 7757 * Interrupt handler. 7758 */ 7759 /****************************************************************************/ 7760 /* Main interrupt entry point. Verifies that the controller generated the */ 7761 /* interrupt and then calls a separate routine for handle the various */ 7762 /* interrupt causes (PHY, TX, RX). */ 7763 /* */ 7764 /* Returns: */ 7765 /* Nothing. */ 7766 /****************************************************************************/ 7767 static void 7768 bce_intr(void *xsc) 7769 { 7770 struct bce_softc *sc; 7771 if_t ifp; 7772 u32 status_attn_bits; 7773 u16 hw_rx_cons, hw_tx_cons; 7774 7775 sc = xsc; 7776 ifp = sc->bce_ifp; 7777 7778 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7779 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7780 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7781 7782 BCE_LOCK(sc); 7783 7784 DBRUN(sc->interrupts_generated++); 7785 7786 /* Synchnorize before we read from interface's status block */ 7787 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7788 7789 /* 7790 * If the hardware status block index matches the last value read 7791 * by the driver and we haven't asserted our interrupt then there's 7792 * nothing to do. This may only happen in case of INTx due to the 7793 * interrupt arriving at the CPU before the status block is updated. 7794 */ 7795 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7796 sc->status_block->status_idx == sc->last_status_idx && 7797 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7798 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7799 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7800 __FUNCTION__); 7801 goto bce_intr_exit; 7802 } 7803 7804 /* Ack the interrupt and stop others from occurring. */ 7805 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7806 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7807 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7808 7809 /* Check if the hardware has finished any work. */ 7810 hw_rx_cons = bce_get_hw_rx_cons(sc); 7811 hw_tx_cons = bce_get_hw_tx_cons(sc); 7812 7813 /* Keep processing data as long as there is work to do. */ 7814 for (;;) { 7815 status_attn_bits = sc->status_block->status_attn_bits; 7816 7817 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7818 BCE_PRINTF("Simulating unexpected status attention " 7819 "bit set."); 7820 sc->unexpected_attention_sim_count++; 7821 status_attn_bits = status_attn_bits | 7822 STATUS_ATTN_BITS_PARITY_ERROR); 7823 7824 /* Was it a link change interrupt? */ 7825 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7826 (sc->status_block->status_attn_bits_ack & 7827 STATUS_ATTN_BITS_LINK_STATE)) { 7828 bce_phy_intr(sc); 7829 7830 /* Clear transient updates during link state change. */ 7831 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7832 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7833 REG_RD(sc, BCE_HC_COMMAND); 7834 } 7835 7836 /* If any other attention is asserted, the chip is toast. */ 7837 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7838 (sc->status_block->status_attn_bits_ack & 7839 ~STATUS_ATTN_BITS_LINK_STATE))) { 7840 sc->unexpected_attention_count++; 7841 7842 BCE_PRINTF("%s(%d): Fatal attention detected: " 7843 "0x%08X\n", __FILE__, __LINE__, 7844 sc->status_block->status_attn_bits); 7845 7846 DBRUNMSG(BCE_FATAL, 7847 if (unexpected_attention_sim_control == 0) 7848 bce_breakpoint(sc)); 7849 7850 bce_init_locked(sc); 7851 goto bce_intr_exit; 7852 } 7853 7854 /* Check for any completed RX frames. */ 7855 if (hw_rx_cons != sc->hw_rx_cons) 7856 bce_rx_intr(sc); 7857 7858 /* Check for any completed TX frames. */ 7859 if (hw_tx_cons != sc->hw_tx_cons) 7860 bce_tx_intr(sc); 7861 7862 /* Save status block index value for the next interrupt. */ 7863 sc->last_status_idx = sc->status_block->status_idx; 7864 7865 /* 7866 * Prevent speculative reads from getting 7867 * ahead of the status block. 7868 */ 7869 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7870 BUS_SPACE_BARRIER_READ); 7871 7872 /* 7873 * If there's no work left then exit the 7874 * interrupt service routine. 7875 */ 7876 hw_rx_cons = bce_get_hw_rx_cons(sc); 7877 hw_tx_cons = bce_get_hw_tx_cons(sc); 7878 7879 if ((hw_rx_cons == sc->hw_rx_cons) && 7880 (hw_tx_cons == sc->hw_tx_cons)) 7881 break; 7882 } 7883 7884 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 7885 7886 /* Re-enable interrupts. */ 7887 bce_enable_intr(sc, 0); 7888 7889 /* Handle any frames that arrived while handling the interrupt. */ 7890 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 7891 !if_sendq_empty(ifp)) 7892 bce_start_locked(ifp); 7893 7894 bce_intr_exit: 7895 BCE_UNLOCK(sc); 7896 7897 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7898 } 7899 7900 /****************************************************************************/ 7901 /* Programs the various packet receive modes (broadcast and multicast). */ 7902 /* */ 7903 /* Returns: */ 7904 /* Nothing. */ 7905 /****************************************************************************/ 7906 static u_int 7907 bce_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 7908 { 7909 u32 *hashes = arg; 7910 int h; 7911 7912 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF; 7913 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7914 7915 return (1); 7916 } 7917 7918 static void 7919 bce_set_rx_mode(struct bce_softc *sc) 7920 { 7921 if_t ifp; 7922 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7923 u32 rx_mode, sort_mode; 7924 int i; 7925 7926 DBENTER(BCE_VERBOSE_MISC); 7927 7928 BCE_LOCK_ASSERT(sc); 7929 7930 ifp = sc->bce_ifp; 7931 7932 /* Initialize receive mode default settings. */ 7933 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7934 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7935 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7936 7937 /* 7938 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7939 * be enbled. 7940 */ 7941 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7942 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7943 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7944 7945 /* 7946 * Check for promiscuous, all multicast, or selected 7947 * multicast address filtering. 7948 */ 7949 if (if_getflags(ifp) & IFF_PROMISC) { 7950 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7951 7952 /* Enable promiscuous mode. */ 7953 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7954 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7955 } else if (if_getflags(ifp) & IFF_ALLMULTI) { 7956 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7957 7958 /* Enable all multicast addresses. */ 7959 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7960 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 7961 0xffffffff); 7962 } 7963 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7964 } else { 7965 /* Accept one or more multicast(s). */ 7966 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7967 if_foreach_llmaddr(ifp, bce_hash_maddr, hashes); 7968 7969 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7970 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7971 7972 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7973 } 7974 7975 /* Only make changes if the recive mode has actually changed. */ 7976 if (rx_mode != sc->rx_mode) { 7977 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7978 "0x%08X\n", rx_mode); 7979 7980 sc->rx_mode = rx_mode; 7981 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7982 } 7983 7984 /* Disable and clear the existing sort before enabling a new sort. */ 7985 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7986 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7987 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7988 7989 DBEXIT(BCE_VERBOSE_MISC); 7990 } 7991 7992 /****************************************************************************/ 7993 /* Called periodically to updates statistics from the controllers */ 7994 /* statistics block. */ 7995 /* */ 7996 /* Returns: */ 7997 /* Nothing. */ 7998 /****************************************************************************/ 7999 static void 8000 bce_stats_update(struct bce_softc *sc) 8001 { 8002 struct statistics_block *stats; 8003 8004 DBENTER(BCE_EXTREME_MISC); 8005 8006 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8007 8008 stats = (struct statistics_block *) sc->stats_block; 8009 8010 /* 8011 * Update the sysctl statistics from the 8012 * hardware statistics. 8013 */ 8014 sc->stat_IfHCInOctets = 8015 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8016 (u64) stats->stat_IfHCInOctets_lo; 8017 8018 sc->stat_IfHCInBadOctets = 8019 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8020 (u64) stats->stat_IfHCInBadOctets_lo; 8021 8022 sc->stat_IfHCOutOctets = 8023 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8024 (u64) stats->stat_IfHCOutOctets_lo; 8025 8026 sc->stat_IfHCOutBadOctets = 8027 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8028 (u64) stats->stat_IfHCOutBadOctets_lo; 8029 8030 sc->stat_IfHCInUcastPkts = 8031 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8032 (u64) stats->stat_IfHCInUcastPkts_lo; 8033 8034 sc->stat_IfHCInMulticastPkts = 8035 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8036 (u64) stats->stat_IfHCInMulticastPkts_lo; 8037 8038 sc->stat_IfHCInBroadcastPkts = 8039 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8040 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8041 8042 sc->stat_IfHCOutUcastPkts = 8043 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8044 (u64) stats->stat_IfHCOutUcastPkts_lo; 8045 8046 sc->stat_IfHCOutMulticastPkts = 8047 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8048 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8049 8050 sc->stat_IfHCOutBroadcastPkts = 8051 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8052 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8053 8054 /* ToDo: Preserve counters beyond 32 bits? */ 8055 /* ToDo: Read the statistics from auto-clear regs? */ 8056 8057 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8058 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8059 8060 sc->stat_Dot3StatsCarrierSenseErrors = 8061 stats->stat_Dot3StatsCarrierSenseErrors; 8062 8063 sc->stat_Dot3StatsFCSErrors = 8064 stats->stat_Dot3StatsFCSErrors; 8065 8066 sc->stat_Dot3StatsAlignmentErrors = 8067 stats->stat_Dot3StatsAlignmentErrors; 8068 8069 sc->stat_Dot3StatsSingleCollisionFrames = 8070 stats->stat_Dot3StatsSingleCollisionFrames; 8071 8072 sc->stat_Dot3StatsMultipleCollisionFrames = 8073 stats->stat_Dot3StatsMultipleCollisionFrames; 8074 8075 sc->stat_Dot3StatsDeferredTransmissions = 8076 stats->stat_Dot3StatsDeferredTransmissions; 8077 8078 sc->stat_Dot3StatsExcessiveCollisions = 8079 stats->stat_Dot3StatsExcessiveCollisions; 8080 8081 sc->stat_Dot3StatsLateCollisions = 8082 stats->stat_Dot3StatsLateCollisions; 8083 8084 sc->stat_EtherStatsCollisions = 8085 stats->stat_EtherStatsCollisions; 8086 8087 sc->stat_EtherStatsFragments = 8088 stats->stat_EtherStatsFragments; 8089 8090 sc->stat_EtherStatsJabbers = 8091 stats->stat_EtherStatsJabbers; 8092 8093 sc->stat_EtherStatsUndersizePkts = 8094 stats->stat_EtherStatsUndersizePkts; 8095 8096 sc->stat_EtherStatsOversizePkts = 8097 stats->stat_EtherStatsOversizePkts; 8098 8099 sc->stat_EtherStatsPktsRx64Octets = 8100 stats->stat_EtherStatsPktsRx64Octets; 8101 8102 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8103 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8104 8105 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8106 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8107 8108 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8109 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8110 8111 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8112 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8113 8114 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8115 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8116 8117 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8118 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8119 8120 sc->stat_EtherStatsPktsTx64Octets = 8121 stats->stat_EtherStatsPktsTx64Octets; 8122 8123 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8124 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8125 8126 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8127 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8128 8129 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8130 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8131 8132 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8133 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8134 8135 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8136 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8137 8138 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8139 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8140 8141 sc->stat_XonPauseFramesReceived = 8142 stats->stat_XonPauseFramesReceived; 8143 8144 sc->stat_XoffPauseFramesReceived = 8145 stats->stat_XoffPauseFramesReceived; 8146 8147 sc->stat_OutXonSent = 8148 stats->stat_OutXonSent; 8149 8150 sc->stat_OutXoffSent = 8151 stats->stat_OutXoffSent; 8152 8153 sc->stat_FlowControlDone = 8154 stats->stat_FlowControlDone; 8155 8156 sc->stat_MacControlFramesReceived = 8157 stats->stat_MacControlFramesReceived; 8158 8159 sc->stat_XoffStateEntered = 8160 stats->stat_XoffStateEntered; 8161 8162 sc->stat_IfInFramesL2FilterDiscards = 8163 stats->stat_IfInFramesL2FilterDiscards; 8164 8165 sc->stat_IfInRuleCheckerDiscards = 8166 stats->stat_IfInRuleCheckerDiscards; 8167 8168 sc->stat_IfInFTQDiscards = 8169 stats->stat_IfInFTQDiscards; 8170 8171 sc->stat_IfInMBUFDiscards = 8172 stats->stat_IfInMBUFDiscards; 8173 8174 sc->stat_IfInRuleCheckerP4Hit = 8175 stats->stat_IfInRuleCheckerP4Hit; 8176 8177 sc->stat_CatchupInRuleCheckerDiscards = 8178 stats->stat_CatchupInRuleCheckerDiscards; 8179 8180 sc->stat_CatchupInFTQDiscards = 8181 stats->stat_CatchupInFTQDiscards; 8182 8183 sc->stat_CatchupInMBUFDiscards = 8184 stats->stat_CatchupInMBUFDiscards; 8185 8186 sc->stat_CatchupInRuleCheckerP4Hit = 8187 stats->stat_CatchupInRuleCheckerP4Hit; 8188 8189 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8190 8191 /* ToDo: Add additional statistics? */ 8192 8193 DBEXIT(BCE_EXTREME_MISC); 8194 } 8195 8196 static uint64_t 8197 bce_get_counter(if_t ifp, ift_counter cnt) 8198 { 8199 struct bce_softc *sc; 8200 uint64_t rv; 8201 8202 sc = if_getsoftc(ifp); 8203 8204 switch (cnt) { 8205 case IFCOUNTER_COLLISIONS: 8206 return (sc->stat_EtherStatsCollisions); 8207 case IFCOUNTER_IERRORS: 8208 return (sc->stat_EtherStatsUndersizePkts + 8209 sc->stat_EtherStatsOversizePkts + 8210 sc->stat_IfInMBUFDiscards + 8211 sc->stat_Dot3StatsAlignmentErrors + 8212 sc->stat_Dot3StatsFCSErrors + 8213 sc->stat_IfInRuleCheckerDiscards + 8214 sc->stat_IfInFTQDiscards + 8215 sc->l2fhdr_error_count + 8216 sc->com_no_buffers); 8217 case IFCOUNTER_OERRORS: 8218 rv = sc->stat_Dot3StatsExcessiveCollisions + 8219 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8220 sc->stat_Dot3StatsLateCollisions + 8221 sc->watchdog_timeouts; 8222 /* 8223 * Certain controllers don't report 8224 * carrier sense errors correctly. 8225 * See errata E11_5708CA0_1165. 8226 */ 8227 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8228 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8229 rv += sc->stat_Dot3StatsCarrierSenseErrors; 8230 return (rv); 8231 default: 8232 return (if_get_counter_default(ifp, cnt)); 8233 } 8234 } 8235 8236 /****************************************************************************/ 8237 /* Periodic function to notify the bootcode that the driver is still */ 8238 /* present. */ 8239 /* */ 8240 /* Returns: */ 8241 /* Nothing. */ 8242 /****************************************************************************/ 8243 static void 8244 bce_pulse(void *xsc) 8245 { 8246 struct bce_softc *sc = xsc; 8247 u32 msg; 8248 8249 DBENTER(BCE_EXTREME_MISC); 8250 8251 BCE_LOCK_ASSERT(sc); 8252 8253 /* Tell the firmware that the driver is still running. */ 8254 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8255 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8256 8257 /* Update the bootcode condition. */ 8258 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8259 8260 /* Report whether the bootcode still knows the driver is running. */ 8261 if (bce_verbose || bootverbose) { 8262 if (sc->bce_drv_cardiac_arrest == FALSE) { 8263 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8264 sc->bce_drv_cardiac_arrest = TRUE; 8265 BCE_PRINTF("%s(): Warning: bootcode " 8266 "thinks driver is absent! " 8267 "(bc_state = 0x%08X)\n", 8268 __FUNCTION__, sc->bc_state); 8269 } 8270 } else { 8271 /* 8272 * Not supported by all bootcode versions. 8273 * (v5.0.11+ and v5.2.1+) Older bootcode 8274 * will require the driver to reset the 8275 * controller to clear this condition. 8276 */ 8277 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8278 sc->bce_drv_cardiac_arrest = FALSE; 8279 BCE_PRINTF("%s(): Bootcode found the " 8280 "driver pulse! (bc_state = 0x%08X)\n", 8281 __FUNCTION__, sc->bc_state); 8282 } 8283 } 8284 } 8285 8286 /* Schedule the next pulse. */ 8287 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8288 8289 DBEXIT(BCE_EXTREME_MISC); 8290 } 8291 8292 /****************************************************************************/ 8293 /* Periodic function to perform maintenance tasks. */ 8294 /* */ 8295 /* Returns: */ 8296 /* Nothing. */ 8297 /****************************************************************************/ 8298 static void 8299 bce_tick(void *xsc) 8300 { 8301 struct bce_softc *sc = xsc; 8302 struct mii_data *mii; 8303 if_t ifp; 8304 struct ifmediareq ifmr; 8305 8306 ifp = sc->bce_ifp; 8307 8308 DBENTER(BCE_EXTREME_MISC); 8309 8310 BCE_LOCK_ASSERT(sc); 8311 8312 /* Schedule the next tick. */ 8313 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8314 8315 /* Update the statistics from the hardware statistics block. */ 8316 bce_stats_update(sc); 8317 8318 /* Ensure page and RX chains get refilled in low-memory situations. */ 8319 if (bce_hdr_split == TRUE) 8320 bce_fill_pg_chain(sc); 8321 bce_fill_rx_chain(sc); 8322 8323 /* Check that chip hasn't hung. */ 8324 bce_watchdog(sc); 8325 8326 /* If link is up already up then we're done. */ 8327 if (sc->bce_link_up == TRUE) 8328 goto bce_tick_exit; 8329 8330 /* Link is down. Check what the PHY's doing. */ 8331 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8332 bzero(&ifmr, sizeof(ifmr)); 8333 bce_ifmedia_sts_rphy(sc, &ifmr); 8334 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8335 (IFM_ACTIVE | IFM_AVALID)) { 8336 sc->bce_link_up = TRUE; 8337 bce_miibus_statchg(sc->bce_dev); 8338 } 8339 } else { 8340 mii = device_get_softc(sc->bce_miibus); 8341 mii_tick(mii); 8342 /* Check if the link has come up. */ 8343 if ((mii->mii_media_status & IFM_ACTIVE) && 8344 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8345 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8346 __FUNCTION__); 8347 sc->bce_link_up = TRUE; 8348 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8349 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8350 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8351 (bce_verbose || bootverbose)) 8352 BCE_PRINTF("Gigabit link up!\n"); 8353 } 8354 } 8355 if (sc->bce_link_up == TRUE) { 8356 /* Now that link is up, handle any outstanding TX traffic. */ 8357 if (!if_sendq_empty(ifp)) { 8358 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8359 "pending TX traffic.\n", __FUNCTION__); 8360 bce_start_locked(ifp); 8361 } 8362 } 8363 8364 bce_tick_exit: 8365 DBEXIT(BCE_EXTREME_MISC); 8366 } 8367 8368 static void 8369 bce_fw_cap_init(struct bce_softc *sc) 8370 { 8371 u32 ack, cap, link; 8372 8373 ack = 0; 8374 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8375 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8376 BCE_FW_CAP_SIGNATURE_MAGIC) 8377 return; 8378 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8379 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8380 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8381 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8382 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8383 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8384 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8385 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8386 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8387 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8388 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8389 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8390 BCE_FW_CAP_REMOTE_PHY_CAP; 8391 } 8392 8393 if (ack != 0) 8394 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8395 } 8396 8397 #ifdef BCE_DEBUG 8398 /****************************************************************************/ 8399 /* Allows the driver state to be dumped through the sysctl interface. */ 8400 /* */ 8401 /* Returns: */ 8402 /* 0 for success, positive value for failure. */ 8403 /****************************************************************************/ 8404 static int 8405 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8406 { 8407 int error; 8408 int result; 8409 struct bce_softc *sc; 8410 8411 result = -1; 8412 error = sysctl_handle_int(oidp, &result, 0, req); 8413 8414 if (error || !req->newptr) 8415 return (error); 8416 8417 if (result == 1) { 8418 sc = (struct bce_softc *)arg1; 8419 bce_dump_driver_state(sc); 8420 } 8421 8422 return error; 8423 } 8424 8425 /****************************************************************************/ 8426 /* Allows the hardware state to be dumped through the sysctl interface. */ 8427 /* */ 8428 /* Returns: */ 8429 /* 0 for success, positive value for failure. */ 8430 /****************************************************************************/ 8431 static int 8432 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8433 { 8434 int error; 8435 int result; 8436 struct bce_softc *sc; 8437 8438 result = -1; 8439 error = sysctl_handle_int(oidp, &result, 0, req); 8440 8441 if (error || !req->newptr) 8442 return (error); 8443 8444 if (result == 1) { 8445 sc = (struct bce_softc *)arg1; 8446 bce_dump_hw_state(sc); 8447 } 8448 8449 return error; 8450 } 8451 8452 /****************************************************************************/ 8453 /* Allows the status block to be dumped through the sysctl interface. */ 8454 /* */ 8455 /* Returns: */ 8456 /* 0 for success, positive value for failure. */ 8457 /****************************************************************************/ 8458 static int 8459 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8460 { 8461 int error; 8462 int result; 8463 struct bce_softc *sc; 8464 8465 result = -1; 8466 error = sysctl_handle_int(oidp, &result, 0, req); 8467 8468 if (error || !req->newptr) 8469 return (error); 8470 8471 if (result == 1) { 8472 sc = (struct bce_softc *)arg1; 8473 bce_dump_status_block(sc); 8474 } 8475 8476 return error; 8477 } 8478 8479 /****************************************************************************/ 8480 /* Allows the stats block to be dumped through the sysctl interface. */ 8481 /* */ 8482 /* Returns: */ 8483 /* 0 for success, positive value for failure. */ 8484 /****************************************************************************/ 8485 static int 8486 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8487 { 8488 int error; 8489 int result; 8490 struct bce_softc *sc; 8491 8492 result = -1; 8493 error = sysctl_handle_int(oidp, &result, 0, req); 8494 8495 if (error || !req->newptr) 8496 return (error); 8497 8498 if (result == 1) { 8499 sc = (struct bce_softc *)arg1; 8500 bce_dump_stats_block(sc); 8501 } 8502 8503 return error; 8504 } 8505 8506 /****************************************************************************/ 8507 /* Allows the stat counters to be cleared without unloading/reloading the */ 8508 /* driver. */ 8509 /* */ 8510 /* Returns: */ 8511 /* 0 for success, positive value for failure. */ 8512 /****************************************************************************/ 8513 static int 8514 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8515 { 8516 int error; 8517 int result; 8518 struct bce_softc *sc; 8519 8520 result = -1; 8521 error = sysctl_handle_int(oidp, &result, 0, req); 8522 8523 if (error || !req->newptr) 8524 return (error); 8525 8526 if (result == 1) { 8527 sc = (struct bce_softc *)arg1; 8528 struct statistics_block *stats; 8529 8530 stats = (struct statistics_block *) sc->stats_block; 8531 bzero(stats, sizeof(struct statistics_block)); 8532 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8533 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8534 8535 /* Clear the internal H/W statistics counters. */ 8536 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8537 8538 /* Reset the driver maintained statistics. */ 8539 sc->interrupts_rx = 8540 sc->interrupts_tx = 0; 8541 sc->tso_frames_requested = 8542 sc->tso_frames_completed = 8543 sc->tso_frames_failed = 0; 8544 sc->rx_empty_count = 8545 sc->tx_full_count = 0; 8546 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8547 sc->tx_hi_watermark = 0; 8548 sc->l2fhdr_error_count = 8549 sc->l2fhdr_error_sim_count = 0; 8550 sc->mbuf_alloc_failed_count = 8551 sc->mbuf_alloc_failed_sim_count = 0; 8552 sc->dma_map_addr_rx_failed_count = 8553 sc->dma_map_addr_tx_failed_count = 0; 8554 sc->mbuf_frag_count = 0; 8555 sc->csum_offload_tcp_udp = 8556 sc->csum_offload_ip = 0; 8557 sc->vlan_tagged_frames_rcvd = 8558 sc->vlan_tagged_frames_stripped = 0; 8559 sc->split_header_frames_rcvd = 8560 sc->split_header_tcp_frames_rcvd = 0; 8561 8562 /* Clear firmware maintained statistics. */ 8563 REG_WR_IND(sc, 0x120084, 0); 8564 } 8565 8566 return error; 8567 } 8568 8569 /****************************************************************************/ 8570 /* Allows the shared memory contents to be dumped through the sysctl . */ 8571 /* interface. */ 8572 /* */ 8573 /* Returns: */ 8574 /* 0 for success, positive value for failure. */ 8575 /****************************************************************************/ 8576 static int 8577 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8578 { 8579 int error; 8580 int result; 8581 struct bce_softc *sc; 8582 8583 result = -1; 8584 error = sysctl_handle_int(oidp, &result, 0, req); 8585 8586 if (error || !req->newptr) 8587 return (error); 8588 8589 if (result == 1) { 8590 sc = (struct bce_softc *)arg1; 8591 bce_dump_shmem_state(sc); 8592 } 8593 8594 return error; 8595 } 8596 8597 /****************************************************************************/ 8598 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8599 /* */ 8600 /* Returns: */ 8601 /* 0 for success, positive value for failure. */ 8602 /****************************************************************************/ 8603 static int 8604 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8605 { 8606 int error; 8607 int result; 8608 struct bce_softc *sc; 8609 8610 result = -1; 8611 error = sysctl_handle_int(oidp, &result, 0, req); 8612 8613 if (error || !req->newptr) 8614 return (error); 8615 8616 if (result == 1) { 8617 sc = (struct bce_softc *)arg1; 8618 bce_dump_bc_state(sc); 8619 } 8620 8621 return error; 8622 } 8623 8624 /****************************************************************************/ 8625 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8626 /* */ 8627 /* Returns: */ 8628 /* 0 for success, positive value for failure. */ 8629 /****************************************************************************/ 8630 static int 8631 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8632 { 8633 int error; 8634 int result; 8635 struct bce_softc *sc; 8636 8637 result = -1; 8638 error = sysctl_handle_int(oidp, &result, 0, req); 8639 8640 if (error || !req->newptr) 8641 return (error); 8642 8643 if (result == 1) { 8644 sc = (struct bce_softc *)arg1; 8645 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8646 } 8647 8648 return error; 8649 } 8650 8651 /****************************************************************************/ 8652 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8653 /* */ 8654 /* Returns: */ 8655 /* 0 for success, positive value for failure. */ 8656 /****************************************************************************/ 8657 static int 8658 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8659 { 8660 int error; 8661 int result; 8662 struct bce_softc *sc; 8663 8664 result = -1; 8665 error = sysctl_handle_int(oidp, &result, 0, req); 8666 8667 if (error || !req->newptr) 8668 return (error); 8669 8670 if (result == 1) { 8671 sc = (struct bce_softc *)arg1; 8672 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8673 } 8674 8675 return error; 8676 } 8677 8678 /****************************************************************************/ 8679 /* Provides a sysctl interface to allow dumping the TX chain. */ 8680 /* */ 8681 /* Returns: */ 8682 /* 0 for success, positive value for failure. */ 8683 /****************************************************************************/ 8684 static int 8685 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8686 { 8687 int error; 8688 int result; 8689 struct bce_softc *sc; 8690 8691 result = -1; 8692 error = sysctl_handle_int(oidp, &result, 0, req); 8693 8694 if (error || !req->newptr) 8695 return (error); 8696 8697 if (result == 1) { 8698 sc = (struct bce_softc *)arg1; 8699 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8700 } 8701 8702 return error; 8703 } 8704 8705 /****************************************************************************/ 8706 /* Provides a sysctl interface to allow dumping the page chain. */ 8707 /* */ 8708 /* Returns: */ 8709 /* 0 for success, positive value for failure. */ 8710 /****************************************************************************/ 8711 static int 8712 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8713 { 8714 int error; 8715 int result; 8716 struct bce_softc *sc; 8717 8718 result = -1; 8719 error = sysctl_handle_int(oidp, &result, 0, req); 8720 8721 if (error || !req->newptr) 8722 return (error); 8723 8724 if (result == 1) { 8725 sc = (struct bce_softc *)arg1; 8726 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8727 } 8728 8729 return error; 8730 } 8731 8732 /****************************************************************************/ 8733 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8734 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8735 /* */ 8736 /* Returns: */ 8737 /* 0 for success, positive value for failure. */ 8738 /****************************************************************************/ 8739 static int 8740 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8741 { 8742 struct bce_softc *sc = (struct bce_softc *)arg1; 8743 int error; 8744 u32 result; 8745 u32 val[1]; 8746 u8 *data = (u8 *) val; 8747 8748 result = -1; 8749 error = sysctl_handle_int(oidp, &result, 0, req); 8750 if (error || (req->newptr == NULL)) 8751 return (error); 8752 8753 error = bce_nvram_read(sc, result, data, 4); 8754 8755 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8756 8757 return (error); 8758 } 8759 8760 /****************************************************************************/ 8761 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8762 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8763 /* */ 8764 /* Returns: */ 8765 /* 0 for success, positive value for failure. */ 8766 /****************************************************************************/ 8767 static int 8768 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8769 { 8770 struct bce_softc *sc = (struct bce_softc *)arg1; 8771 int error; 8772 u32 val, result; 8773 8774 result = -1; 8775 error = sysctl_handle_int(oidp, &result, 0, req); 8776 if (error || (req->newptr == NULL)) 8777 return (error); 8778 8779 /* Make sure the register is accessible. */ 8780 if (result < 0x8000) { 8781 val = REG_RD(sc, result); 8782 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8783 } else if (result < 0x0280000) { 8784 val = REG_RD_IND(sc, result); 8785 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8786 } 8787 8788 return (error); 8789 } 8790 8791 /****************************************************************************/ 8792 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8793 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8794 /* */ 8795 /* Returns: */ 8796 /* 0 for success, positive value for failure. */ 8797 /****************************************************************************/ 8798 static int 8799 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8800 { 8801 struct bce_softc *sc; 8802 device_t dev; 8803 int error, result; 8804 u16 val; 8805 8806 result = -1; 8807 error = sysctl_handle_int(oidp, &result, 0, req); 8808 if (error || (req->newptr == NULL)) 8809 return (error); 8810 8811 /* Make sure the register is accessible. */ 8812 if (result < 0x20) { 8813 sc = (struct bce_softc *)arg1; 8814 dev = sc->bce_dev; 8815 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8816 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8817 } 8818 return (error); 8819 } 8820 8821 /****************************************************************************/ 8822 /* Provides a sysctl interface for dumping the nvram contents. */ 8823 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8824 /* */ 8825 /* Returns: */ 8826 /* 0 for success, positive errno for failure. */ 8827 /****************************************************************************/ 8828 static int 8829 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8830 { 8831 struct bce_softc *sc = (struct bce_softc *)arg1; 8832 int error, i; 8833 8834 if (sc->nvram_buf == NULL) 8835 sc->nvram_buf = malloc(sc->bce_flash_size, 8836 M_TEMP, M_ZERO | M_WAITOK); 8837 8838 error = 0; 8839 if (req->oldlen == sc->bce_flash_size) { 8840 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8841 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8842 } 8843 8844 if (error == 0) 8845 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8846 8847 return error; 8848 } 8849 8850 #ifdef BCE_NVRAM_WRITE_SUPPORT 8851 /****************************************************************************/ 8852 /* Provides a sysctl interface for writing to nvram. */ 8853 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8854 /* */ 8855 /* Returns: */ 8856 /* 0 for success, positive errno for failure. */ 8857 /****************************************************************************/ 8858 static int 8859 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8860 { 8861 struct bce_softc *sc = (struct bce_softc *)arg1; 8862 int error; 8863 8864 if (sc->nvram_buf == NULL) 8865 sc->nvram_buf = malloc(sc->bce_flash_size, 8866 M_TEMP, M_ZERO | M_WAITOK); 8867 else 8868 bzero(sc->nvram_buf, sc->bce_flash_size); 8869 8870 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 8871 if (error == 0) 8872 return (error); 8873 8874 if (req->newlen == sc->bce_flash_size) 8875 error = bce_nvram_write(sc, 0, sc->nvram_buf, 8876 sc->bce_flash_size); 8877 8878 return error; 8879 } 8880 #endif 8881 8882 /****************************************************************************/ 8883 /* Provides a sysctl interface to allow reading a CID. */ 8884 /* */ 8885 /* Returns: */ 8886 /* 0 for success, positive value for failure. */ 8887 /****************************************************************************/ 8888 static int 8889 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8890 { 8891 struct bce_softc *sc; 8892 int error, result; 8893 8894 result = -1; 8895 error = sysctl_handle_int(oidp, &result, 0, req); 8896 if (error || (req->newptr == NULL)) 8897 return (error); 8898 8899 /* Make sure the register is accessible. */ 8900 if (result <= TX_CID) { 8901 sc = (struct bce_softc *)arg1; 8902 bce_dump_ctx(sc, result); 8903 } 8904 8905 return (error); 8906 } 8907 8908 /****************************************************************************/ 8909 /* Provides a sysctl interface to forcing the driver to dump state and */ 8910 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8911 /* */ 8912 /* Returns: */ 8913 /* 0 for success, positive value for failure. */ 8914 /****************************************************************************/ 8915 static int 8916 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8917 { 8918 int error; 8919 int result; 8920 struct bce_softc *sc; 8921 8922 result = -1; 8923 error = sysctl_handle_int(oidp, &result, 0, req); 8924 8925 if (error || !req->newptr) 8926 return (error); 8927 8928 if (result == 1) { 8929 sc = (struct bce_softc *)arg1; 8930 bce_breakpoint(sc); 8931 } 8932 8933 return error; 8934 } 8935 #endif 8936 8937 /****************************************************************************/ 8938 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8939 /* */ 8940 /* Returns: */ 8941 /* 0 for success, positive value for failure. */ 8942 /****************************************************************************/ 8943 static void 8944 bce_add_sysctls(struct bce_softc *sc) 8945 { 8946 struct sysctl_ctx_list *ctx; 8947 struct sysctl_oid_list *children; 8948 8949 DBENTER(BCE_VERBOSE_MISC); 8950 8951 ctx = device_get_sysctl_ctx(sc->bce_dev); 8952 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8953 8954 #ifdef BCE_DEBUG 8955 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8956 "l2fhdr_error_sim_control", 8957 CTLFLAG_RW, &l2fhdr_error_sim_control, 8958 0, "Debug control to force l2fhdr errors"); 8959 8960 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8961 "l2fhdr_error_sim_count", 8962 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8963 0, "Number of simulated l2_fhdr errors"); 8964 #endif 8965 8966 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8967 "l2fhdr_error_count", 8968 CTLFLAG_RD, &sc->l2fhdr_error_count, 8969 0, "Number of l2_fhdr errors"); 8970 8971 #ifdef BCE_DEBUG 8972 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8973 "mbuf_alloc_failed_sim_control", 8974 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8975 0, "Debug control to force mbuf allocation failures"); 8976 8977 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8978 "mbuf_alloc_failed_sim_count", 8979 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8980 0, "Number of simulated mbuf cluster allocation failures"); 8981 #endif 8982 8983 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8984 "mbuf_alloc_failed_count", 8985 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8986 0, "Number of mbuf allocation failures"); 8987 8988 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8989 "mbuf_frag_count", 8990 CTLFLAG_RD, &sc->mbuf_frag_count, 8991 0, "Number of fragmented mbufs"); 8992 8993 #ifdef BCE_DEBUG 8994 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8995 "dma_map_addr_failed_sim_control", 8996 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8997 0, "Debug control to force DMA mapping failures"); 8998 8999 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9000 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9001 "dma_map_addr_failed_sim_count", 9002 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9003 0, "Number of simulated DMA mapping failures"); 9004 9005 #endif 9006 9007 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9008 "dma_map_addr_rx_failed_count", 9009 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9010 0, "Number of RX DMA mapping failures"); 9011 9012 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9013 "dma_map_addr_tx_failed_count", 9014 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9015 0, "Number of TX DMA mapping failures"); 9016 9017 #ifdef BCE_DEBUG 9018 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9019 "unexpected_attention_sim_control", 9020 CTLFLAG_RW, &unexpected_attention_sim_control, 9021 0, "Debug control to simulate unexpected attentions"); 9022 9023 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9024 "unexpected_attention_sim_count", 9025 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9026 0, "Number of simulated unexpected attentions"); 9027 #endif 9028 9029 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9030 "unexpected_attention_count", 9031 CTLFLAG_RW, &sc->unexpected_attention_count, 9032 0, "Number of unexpected attentions"); 9033 9034 #ifdef BCE_DEBUG 9035 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9036 "debug_bootcode_running_failure", 9037 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9038 0, "Debug control to force bootcode running failures"); 9039 9040 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9041 "rx_low_watermark", 9042 CTLFLAG_RD, &sc->rx_low_watermark, 9043 0, "Lowest level of free rx_bd's"); 9044 9045 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9046 "rx_empty_count", 9047 CTLFLAG_RD, &sc->rx_empty_count, 9048 "Number of times the RX chain was empty"); 9049 9050 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9051 "tx_hi_watermark", 9052 CTLFLAG_RD, &sc->tx_hi_watermark, 9053 0, "Highest level of used tx_bd's"); 9054 9055 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9056 "tx_full_count", 9057 CTLFLAG_RD, &sc->tx_full_count, 9058 "Number of times the TX chain was full"); 9059 9060 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9061 "tso_frames_requested", 9062 CTLFLAG_RD, &sc->tso_frames_requested, 9063 "Number of TSO frames requested"); 9064 9065 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9066 "tso_frames_completed", 9067 CTLFLAG_RD, &sc->tso_frames_completed, 9068 "Number of TSO frames completed"); 9069 9070 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9071 "tso_frames_failed", 9072 CTLFLAG_RD, &sc->tso_frames_failed, 9073 "Number of TSO frames failed"); 9074 9075 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9076 "csum_offload_ip", 9077 CTLFLAG_RD, &sc->csum_offload_ip, 9078 "Number of IP checksum offload frames"); 9079 9080 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9081 "csum_offload_tcp_udp", 9082 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9083 "Number of TCP/UDP checksum offload frames"); 9084 9085 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9086 "vlan_tagged_frames_rcvd", 9087 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9088 "Number of VLAN tagged frames received"); 9089 9090 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9091 "vlan_tagged_frames_stripped", 9092 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9093 "Number of VLAN tagged frames stripped"); 9094 9095 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9096 "interrupts_rx", 9097 CTLFLAG_RD, &sc->interrupts_rx, 9098 "Number of RX interrupts"); 9099 9100 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9101 "interrupts_tx", 9102 CTLFLAG_RD, &sc->interrupts_tx, 9103 "Number of TX interrupts"); 9104 9105 if (bce_hdr_split == TRUE) { 9106 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9107 "split_header_frames_rcvd", 9108 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9109 "Number of split header frames received"); 9110 9111 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9112 "split_header_tcp_frames_rcvd", 9113 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9114 "Number of split header TCP frames received"); 9115 } 9116 9117 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9118 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 9119 (void *)sc, 0, 9120 bce_sysctl_nvram_dump, "S", ""); 9121 9122 #ifdef BCE_NVRAM_WRITE_SUPPORT 9123 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9124 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR | CTLFLAG_NEEDGIANT, 9125 (void *)sc, 0, 9126 bce_sysctl_nvram_write, "S", ""); 9127 #endif 9128 #endif /* BCE_DEBUG */ 9129 9130 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9131 "stat_IfHcInOctets", 9132 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9133 "Bytes received"); 9134 9135 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9136 "stat_IfHCInBadOctets", 9137 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9138 "Bad bytes received"); 9139 9140 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9141 "stat_IfHCOutOctets", 9142 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9143 "Bytes sent"); 9144 9145 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9146 "stat_IfHCOutBadOctets", 9147 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9148 "Bad bytes sent"); 9149 9150 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9151 "stat_IfHCInUcastPkts", 9152 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9153 "Unicast packets received"); 9154 9155 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9156 "stat_IfHCInMulticastPkts", 9157 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9158 "Multicast packets received"); 9159 9160 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9161 "stat_IfHCInBroadcastPkts", 9162 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9163 "Broadcast packets received"); 9164 9165 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9166 "stat_IfHCOutUcastPkts", 9167 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9168 "Unicast packets sent"); 9169 9170 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9171 "stat_IfHCOutMulticastPkts", 9172 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9173 "Multicast packets sent"); 9174 9175 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9176 "stat_IfHCOutBroadcastPkts", 9177 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9178 "Broadcast packets sent"); 9179 9180 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9181 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9182 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9183 0, "Internal MAC transmit errors"); 9184 9185 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9186 "stat_Dot3StatsCarrierSenseErrors", 9187 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9188 0, "Carrier sense errors"); 9189 9190 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9191 "stat_Dot3StatsFCSErrors", 9192 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9193 0, "Frame check sequence errors"); 9194 9195 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9196 "stat_Dot3StatsAlignmentErrors", 9197 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9198 0, "Alignment errors"); 9199 9200 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9201 "stat_Dot3StatsSingleCollisionFrames", 9202 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9203 0, "Single Collision Frames"); 9204 9205 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9206 "stat_Dot3StatsMultipleCollisionFrames", 9207 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9208 0, "Multiple Collision Frames"); 9209 9210 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9211 "stat_Dot3StatsDeferredTransmissions", 9212 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9213 0, "Deferred Transmissions"); 9214 9215 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9216 "stat_Dot3StatsExcessiveCollisions", 9217 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9218 0, "Excessive Collisions"); 9219 9220 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9221 "stat_Dot3StatsLateCollisions", 9222 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9223 0, "Late Collisions"); 9224 9225 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9226 "stat_EtherStatsCollisions", 9227 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9228 0, "Collisions"); 9229 9230 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9231 "stat_EtherStatsFragments", 9232 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9233 0, "Fragments"); 9234 9235 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9236 "stat_EtherStatsJabbers", 9237 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9238 0, "Jabbers"); 9239 9240 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9241 "stat_EtherStatsUndersizePkts", 9242 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9243 0, "Undersize packets"); 9244 9245 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9246 "stat_EtherStatsOversizePkts", 9247 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9248 0, "stat_EtherStatsOversizePkts"); 9249 9250 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9251 "stat_EtherStatsPktsRx64Octets", 9252 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9253 0, "Bytes received in 64 byte packets"); 9254 9255 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9256 "stat_EtherStatsPktsRx65Octetsto127Octets", 9257 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9258 0, "Bytes received in 65 to 127 byte packets"); 9259 9260 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9261 "stat_EtherStatsPktsRx128Octetsto255Octets", 9262 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9263 0, "Bytes received in 128 to 255 byte packets"); 9264 9265 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9266 "stat_EtherStatsPktsRx256Octetsto511Octets", 9267 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9268 0, "Bytes received in 256 to 511 byte packets"); 9269 9270 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9271 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9272 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9273 0, "Bytes received in 512 to 1023 byte packets"); 9274 9275 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9276 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9277 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9278 0, "Bytes received in 1024 t0 1522 byte packets"); 9279 9280 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9281 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9282 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9283 0, "Bytes received in 1523 to 9022 byte packets"); 9284 9285 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9286 "stat_EtherStatsPktsTx64Octets", 9287 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9288 0, "Bytes sent in 64 byte packets"); 9289 9290 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9291 "stat_EtherStatsPktsTx65Octetsto127Octets", 9292 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9293 0, "Bytes sent in 65 to 127 byte packets"); 9294 9295 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9296 "stat_EtherStatsPktsTx128Octetsto255Octets", 9297 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9298 0, "Bytes sent in 128 to 255 byte packets"); 9299 9300 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9301 "stat_EtherStatsPktsTx256Octetsto511Octets", 9302 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9303 0, "Bytes sent in 256 to 511 byte packets"); 9304 9305 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9306 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9307 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9308 0, "Bytes sent in 512 to 1023 byte packets"); 9309 9310 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9311 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9312 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9313 0, "Bytes sent in 1024 to 1522 byte packets"); 9314 9315 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9316 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9317 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9318 0, "Bytes sent in 1523 to 9022 byte packets"); 9319 9320 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9321 "stat_XonPauseFramesReceived", 9322 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9323 0, "XON pause frames receved"); 9324 9325 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9326 "stat_XoffPauseFramesReceived", 9327 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9328 0, "XOFF pause frames received"); 9329 9330 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9331 "stat_OutXonSent", 9332 CTLFLAG_RD, &sc->stat_OutXonSent, 9333 0, "XON pause frames sent"); 9334 9335 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9336 "stat_OutXoffSent", 9337 CTLFLAG_RD, &sc->stat_OutXoffSent, 9338 0, "XOFF pause frames sent"); 9339 9340 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9341 "stat_FlowControlDone", 9342 CTLFLAG_RD, &sc->stat_FlowControlDone, 9343 0, "Flow control done"); 9344 9345 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9346 "stat_MacControlFramesReceived", 9347 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9348 0, "MAC control frames received"); 9349 9350 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9351 "stat_XoffStateEntered", 9352 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9353 0, "XOFF state entered"); 9354 9355 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9356 "stat_IfInFramesL2FilterDiscards", 9357 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9358 0, "Received L2 packets discarded"); 9359 9360 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9361 "stat_IfInRuleCheckerDiscards", 9362 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9363 0, "Received packets discarded by rule"); 9364 9365 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9366 "stat_IfInFTQDiscards", 9367 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9368 0, "Received packet FTQ discards"); 9369 9370 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9371 "stat_IfInMBUFDiscards", 9372 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9373 0, "Received packets discarded due to lack " 9374 "of controller buffer memory"); 9375 9376 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9377 "stat_IfInRuleCheckerP4Hit", 9378 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9379 0, "Received packets rule checker hits"); 9380 9381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9382 "stat_CatchupInRuleCheckerDiscards", 9383 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9384 0, "Received packets discarded in Catchup path"); 9385 9386 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9387 "stat_CatchupInFTQDiscards", 9388 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9389 0, "Received packets discarded in FTQ in Catchup path"); 9390 9391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9392 "stat_CatchupInMBUFDiscards", 9393 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9394 0, "Received packets discarded in controller " 9395 "buffer memory in Catchup path"); 9396 9397 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9398 "stat_CatchupInRuleCheckerP4Hit", 9399 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9400 0, "Received packets rule checker hits in Catchup path"); 9401 9402 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9403 "com_no_buffers", 9404 CTLFLAG_RD, &sc->com_no_buffers, 9405 0, "Valid packets received but no RX buffers available"); 9406 9407 #ifdef BCE_DEBUG 9408 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9409 "driver_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9410 (void *)sc, 0, 9411 bce_sysctl_driver_state, "I", "Drive state information"); 9412 9413 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9414 "hw_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9415 (void *)sc, 0, 9416 bce_sysctl_hw_state, "I", "Hardware state information"); 9417 9418 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9419 "status_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9420 (void *)sc, 0, 9421 bce_sysctl_status_block, "I", "Dump status block"); 9422 9423 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9424 "stats_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9425 (void *)sc, 0, 9426 bce_sysctl_stats_block, "I", "Dump statistics block"); 9427 9428 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9429 "stats_clear", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9430 (void *)sc, 0, 9431 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9432 9433 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9434 "shmem_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9435 (void *)sc, 0, 9436 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9437 9438 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9439 "bc_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9440 (void *)sc, 0, 9441 bce_sysctl_bc_state, "I", "Bootcode state information"); 9442 9443 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9444 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9445 (void *)sc, 0, 9446 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9447 9448 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9449 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9450 (void *)sc, 0, 9451 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9452 9453 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9454 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9455 (void *)sc, 0, 9456 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9457 9458 if (bce_hdr_split == TRUE) { 9459 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9460 "dump_pg_chain", 9461 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9462 (void *)sc, 0, 9463 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9464 } 9465 9466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9467 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9468 (void *)sc, 0, 9469 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9470 9471 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9472 "breakpoint", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9473 (void *)sc, 0, 9474 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9475 9476 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9477 "reg_read", CTLTYPE_INT | CTLFLAG_RW| CTLFLAG_NEEDGIANT, 9478 (void *)sc, 0, 9479 bce_sysctl_reg_read, "I", "Register read"); 9480 9481 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9482 "nvram_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9483 (void *)sc, 0, 9484 bce_sysctl_nvram_read, "I", "NVRAM read"); 9485 9486 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9487 "phy_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9488 (void *)sc, 0, 9489 bce_sysctl_phy_read, "I", "PHY register read"); 9490 9491 #endif 9492 9493 DBEXIT(BCE_VERBOSE_MISC); 9494 } 9495 9496 /****************************************************************************/ 9497 /* BCE Debug Routines */ 9498 /****************************************************************************/ 9499 #ifdef BCE_DEBUG 9500 9501 /****************************************************************************/ 9502 /* Freezes the controller to allow for a cohesive state dump. */ 9503 /* */ 9504 /* Returns: */ 9505 /* Nothing. */ 9506 /****************************************************************************/ 9507 static __attribute__ ((noinline)) void 9508 bce_freeze_controller(struct bce_softc *sc) 9509 { 9510 u32 val; 9511 val = REG_RD(sc, BCE_MISC_COMMAND); 9512 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9513 REG_WR(sc, BCE_MISC_COMMAND, val); 9514 } 9515 9516 /****************************************************************************/ 9517 /* Unfreezes the controller after a freeze operation. This may not always */ 9518 /* work and the controller will require a reset! */ 9519 /* */ 9520 /* Returns: */ 9521 /* Nothing. */ 9522 /****************************************************************************/ 9523 static __attribute__ ((noinline)) void 9524 bce_unfreeze_controller(struct bce_softc *sc) 9525 { 9526 u32 val; 9527 val = REG_RD(sc, BCE_MISC_COMMAND); 9528 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9529 REG_WR(sc, BCE_MISC_COMMAND, val); 9530 } 9531 9532 /****************************************************************************/ 9533 /* Prints out Ethernet frame information from an mbuf. */ 9534 /* */ 9535 /* Partially decode an Ethernet frame to look at some important headers. */ 9536 /* */ 9537 /* Returns: */ 9538 /* Nothing. */ 9539 /****************************************************************************/ 9540 static __attribute__ ((noinline)) void 9541 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9542 { 9543 struct ether_vlan_header *eh; 9544 u16 etype; 9545 int ehlen; 9546 struct ip *ip; 9547 struct tcphdr *th; 9548 struct udphdr *uh; 9549 struct arphdr *ah; 9550 9551 BCE_PRINTF( 9552 "-----------------------------" 9553 " Frame Decode " 9554 "-----------------------------\n"); 9555 9556 eh = mtod(m, struct ether_vlan_header *); 9557 9558 /* Handle VLAN encapsulation if present. */ 9559 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9560 etype = ntohs(eh->evl_proto); 9561 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9562 } else { 9563 etype = ntohs(eh->evl_encap_proto); 9564 ehlen = ETHER_HDR_LEN; 9565 } 9566 9567 /* ToDo: Add VLAN output. */ 9568 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9569 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9570 9571 switch (etype) { 9572 case ETHERTYPE_IP: 9573 ip = (struct ip *)(m->m_data + ehlen); 9574 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9575 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9576 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9577 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9578 9579 switch (ip->ip_p) { 9580 case IPPROTO_TCP: 9581 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9582 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9583 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9584 ntohs(th->th_dport), ntohs(th->th_sport), 9585 (th->th_off << 2), th->th_flags, 9586 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9587 "\02SYN\01FIN", ntohs(th->th_sum)); 9588 break; 9589 case IPPROTO_UDP: 9590 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9591 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9592 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9593 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9594 ntohs(uh->uh_sum)); 9595 break; 9596 case IPPROTO_ICMP: 9597 BCE_PRINTF("icmp:\n"); 9598 break; 9599 default: 9600 BCE_PRINTF("----: Other IP protocol.\n"); 9601 } 9602 break; 9603 case ETHERTYPE_IPV6: 9604 BCE_PRINTF("ipv6: No decode supported.\n"); 9605 break; 9606 case ETHERTYPE_ARP: 9607 BCE_PRINTF("-arp: "); 9608 ah = (struct arphdr *) (m->m_data + ehlen); 9609 switch (ntohs(ah->ar_op)) { 9610 case ARPOP_REVREQUEST: 9611 printf("reverse ARP request\n"); 9612 break; 9613 case ARPOP_REVREPLY: 9614 printf("reverse ARP reply\n"); 9615 break; 9616 case ARPOP_REQUEST: 9617 printf("ARP request\n"); 9618 break; 9619 case ARPOP_REPLY: 9620 printf("ARP reply\n"); 9621 break; 9622 default: 9623 printf("other ARP operation\n"); 9624 } 9625 break; 9626 default: 9627 BCE_PRINTF("----: Other protocol.\n"); 9628 } 9629 9630 BCE_PRINTF( 9631 "-----------------------------" 9632 "--------------" 9633 "-----------------------------\n"); 9634 } 9635 9636 /****************************************************************************/ 9637 /* Prints out information about an mbuf. */ 9638 /* */ 9639 /* Returns: */ 9640 /* Nothing. */ 9641 /****************************************************************************/ 9642 static __attribute__ ((noinline)) void 9643 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9644 { 9645 struct mbuf *mp = m; 9646 9647 if (m == NULL) { 9648 BCE_PRINTF("mbuf: null pointer\n"); 9649 return; 9650 } 9651 9652 while (mp) { 9653 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9654 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9655 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9656 9657 if (mp->m_flags & M_PKTHDR) { 9658 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9659 "csum_flags = %b\n", mp->m_pkthdr.len, 9660 mp->m_flags, M_FLAG_PRINTF, 9661 mp->m_pkthdr.csum_flags, CSUM_BITS); 9662 } 9663 9664 if (mp->m_flags & M_EXT) { 9665 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9666 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9667 switch (mp->m_ext.ext_type) { 9668 case EXT_CLUSTER: 9669 printf("EXT_CLUSTER\n"); break; 9670 case EXT_SFBUF: 9671 printf("EXT_SFBUF\n"); break; 9672 case EXT_JUMBO9: 9673 printf("EXT_JUMBO9\n"); break; 9674 case EXT_JUMBO16: 9675 printf("EXT_JUMBO16\n"); break; 9676 case EXT_PACKET: 9677 printf("EXT_PACKET\n"); break; 9678 case EXT_MBUF: 9679 printf("EXT_MBUF\n"); break; 9680 case EXT_NET_DRV: 9681 printf("EXT_NET_DRV\n"); break; 9682 case EXT_MOD_TYPE: 9683 printf("EXT_MDD_TYPE\n"); break; 9684 case EXT_DISPOSABLE: 9685 printf("EXT_DISPOSABLE\n"); break; 9686 case EXT_EXTREF: 9687 printf("EXT_EXTREF\n"); break; 9688 default: 9689 printf("UNKNOWN\n"); 9690 } 9691 } 9692 9693 mp = mp->m_next; 9694 } 9695 } 9696 9697 /****************************************************************************/ 9698 /* Prints out the mbufs in the TX mbuf chain. */ 9699 /* */ 9700 /* Returns: */ 9701 /* Nothing. */ 9702 /****************************************************************************/ 9703 static __attribute__ ((noinline)) void 9704 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9705 { 9706 struct mbuf *m; 9707 9708 BCE_PRINTF( 9709 "----------------------------" 9710 " tx mbuf data " 9711 "----------------------------\n"); 9712 9713 for (int i = 0; i < count; i++) { 9714 m = sc->tx_mbuf_ptr[chain_prod]; 9715 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9716 bce_dump_mbuf(sc, m); 9717 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9718 } 9719 9720 BCE_PRINTF( 9721 "----------------------------" 9722 "----------------" 9723 "----------------------------\n"); 9724 } 9725 9726 /****************************************************************************/ 9727 /* Prints out the mbufs in the RX mbuf chain. */ 9728 /* */ 9729 /* Returns: */ 9730 /* Nothing. */ 9731 /****************************************************************************/ 9732 static __attribute__ ((noinline)) void 9733 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9734 { 9735 struct mbuf *m; 9736 9737 BCE_PRINTF( 9738 "----------------------------" 9739 " rx mbuf data " 9740 "----------------------------\n"); 9741 9742 for (int i = 0; i < count; i++) { 9743 m = sc->rx_mbuf_ptr[chain_prod]; 9744 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9745 bce_dump_mbuf(sc, m); 9746 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9747 } 9748 9749 BCE_PRINTF( 9750 "----------------------------" 9751 "----------------" 9752 "----------------------------\n"); 9753 } 9754 9755 /****************************************************************************/ 9756 /* Prints out the mbufs in the mbuf page chain. */ 9757 /* */ 9758 /* Returns: */ 9759 /* Nothing. */ 9760 /****************************************************************************/ 9761 static __attribute__ ((noinline)) void 9762 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9763 { 9764 struct mbuf *m; 9765 9766 BCE_PRINTF( 9767 "----------------------------" 9768 " pg mbuf data " 9769 "----------------------------\n"); 9770 9771 for (int i = 0; i < count; i++) { 9772 m = sc->pg_mbuf_ptr[chain_prod]; 9773 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9774 bce_dump_mbuf(sc, m); 9775 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9776 } 9777 9778 BCE_PRINTF( 9779 "----------------------------" 9780 "----------------" 9781 "----------------------------\n"); 9782 } 9783 9784 /****************************************************************************/ 9785 /* Prints out a tx_bd structure. */ 9786 /* */ 9787 /* Returns: */ 9788 /* Nothing. */ 9789 /****************************************************************************/ 9790 static __attribute__ ((noinline)) void 9791 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9792 { 9793 int i = 0; 9794 9795 if (idx > MAX_TX_BD_ALLOC) 9796 /* Index out of range. */ 9797 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9798 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9799 /* TX Chain page pointer. */ 9800 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9801 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9802 txbd->tx_bd_haddr_lo); 9803 else { 9804 /* Normal tx_bd entry. */ 9805 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9806 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9807 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9808 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9809 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9810 9811 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9812 if (i>0) 9813 printf("|"); 9814 printf("CONN_FAULT"); 9815 i++; 9816 } 9817 9818 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9819 if (i>0) 9820 printf("|"); 9821 printf("TCP_UDP_CKSUM"); 9822 i++; 9823 } 9824 9825 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9826 if (i>0) 9827 printf("|"); 9828 printf("IP_CKSUM"); 9829 i++; 9830 } 9831 9832 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9833 if (i>0) 9834 printf("|"); 9835 printf("VLAN"); 9836 i++; 9837 } 9838 9839 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9840 if (i>0) 9841 printf("|"); 9842 printf("COAL_NOW"); 9843 i++; 9844 } 9845 9846 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9847 if (i>0) 9848 printf("|"); 9849 printf("DONT_GEN_CRC"); 9850 i++; 9851 } 9852 9853 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9854 if (i>0) 9855 printf("|"); 9856 printf("START"); 9857 i++; 9858 } 9859 9860 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9861 if (i>0) 9862 printf("|"); 9863 printf("END"); 9864 i++; 9865 } 9866 9867 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9868 if (i>0) 9869 printf("|"); 9870 printf("LSO"); 9871 i++; 9872 } 9873 9874 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9875 if (i>0) 9876 printf("|"); 9877 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9878 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9879 } 9880 9881 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9882 if (i>0) 9883 printf("|"); 9884 printf("SW_FLAGS"); 9885 i++; 9886 } 9887 9888 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9889 if (i>0) 9890 printf("|"); 9891 printf("SNAP)"); 9892 } else { 9893 printf(")\n"); 9894 } 9895 } 9896 } 9897 9898 /****************************************************************************/ 9899 /* Prints out a rx_bd structure. */ 9900 /* */ 9901 /* Returns: */ 9902 /* Nothing. */ 9903 /****************************************************************************/ 9904 static __attribute__ ((noinline)) void 9905 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9906 { 9907 if (idx > MAX_RX_BD_ALLOC) 9908 /* Index out of range. */ 9909 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9910 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9911 /* RX Chain page pointer. */ 9912 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9913 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9914 rxbd->rx_bd_haddr_lo); 9915 else 9916 /* Normal rx_bd entry. */ 9917 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9918 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9919 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9920 rxbd->rx_bd_flags); 9921 } 9922 9923 /****************************************************************************/ 9924 /* Prints out a rx_bd structure in the page chain. */ 9925 /* */ 9926 /* Returns: */ 9927 /* Nothing. */ 9928 /****************************************************************************/ 9929 static __attribute__ ((noinline)) void 9930 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9931 { 9932 if (idx > MAX_PG_BD_ALLOC) 9933 /* Index out of range. */ 9934 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9935 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9936 /* Page Chain page pointer. */ 9937 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9938 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9939 else 9940 /* Normal rx_bd entry. */ 9941 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9942 "flags = 0x%08X\n", idx, 9943 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9944 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9945 } 9946 9947 /****************************************************************************/ 9948 /* Prints out a l2_fhdr structure. */ 9949 /* */ 9950 /* Returns: */ 9951 /* Nothing. */ 9952 /****************************************************************************/ 9953 static __attribute__ ((noinline)) void 9954 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9955 { 9956 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9957 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9958 "tcp_udp_xsum = 0x%04X\n", idx, 9959 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9960 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9961 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9962 } 9963 9964 /****************************************************************************/ 9965 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9966 /* */ 9967 /* Returns: */ 9968 /* Nothing. */ 9969 /****************************************************************************/ 9970 static __attribute__ ((noinline)) void 9971 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9972 { 9973 if (cid > TX_CID) { 9974 BCE_PRINTF(" Unknown CID\n"); 9975 return; 9976 } 9977 9978 BCE_PRINTF( 9979 "----------------------------" 9980 " CTX Data " 9981 "----------------------------\n"); 9982 9983 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9984 9985 if (cid == RX_CID) { 9986 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9987 "producer index\n", 9988 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9989 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 9990 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9991 BCE_L2CTX_RX_HOST_BSEQ)); 9992 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9993 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9994 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9995 "descriptor address\n", 9996 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9997 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9998 "descriptor address\n", 9999 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10000 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10001 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10002 BCE_L2CTX_RX_NX_BDIDX)); 10003 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10004 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10005 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10006 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10007 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10008 BCE_L2CTX_RX_PG_BUF_SIZE)); 10009 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10010 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10011 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10012 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10013 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10014 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10015 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10016 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10017 BCE_L2CTX_RX_NX_PG_BDIDX)); 10018 } else if (cid == TX_CID) { 10019 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10020 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10021 CTX_RD(sc, GET_CID_ADDR(cid), 10022 BCE_L2CTX_TX_TYPE_XI)); 10023 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10024 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10025 BCE_L2CTX_TX_CMD_TYPE_XI)); 10026 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10027 "h/w buffer descriptor address\n", 10028 CTX_RD(sc, GET_CID_ADDR(cid), 10029 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10030 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10031 "h/w buffer descriptor address\n", 10032 CTX_RD(sc, GET_CID_ADDR(cid), 10033 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10034 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10035 "host producer index\n", 10036 CTX_RD(sc, GET_CID_ADDR(cid), 10037 BCE_L2CTX_TX_HOST_BIDX_XI)); 10038 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10039 "host byte sequence\n", 10040 CTX_RD(sc, GET_CID_ADDR(cid), 10041 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10042 } else { 10043 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10044 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10045 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10046 CTX_RD(sc, GET_CID_ADDR(cid), 10047 BCE_L2CTX_TX_CMD_TYPE)); 10048 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10049 "h/w buffer descriptor address\n", 10050 CTX_RD(sc, GET_CID_ADDR(cid), 10051 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10052 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10053 "h/w buffer descriptor address\n", 10054 CTX_RD(sc, GET_CID_ADDR(cid), 10055 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10056 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10057 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10058 BCE_L2CTX_TX_HOST_BIDX)); 10059 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10060 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10061 BCE_L2CTX_TX_HOST_BSEQ)); 10062 } 10063 } 10064 10065 BCE_PRINTF( 10066 "----------------------------" 10067 " Raw CTX " 10068 "----------------------------\n"); 10069 10070 for (int i = 0x0; i < 0x300; i += 0x10) { 10071 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10072 CTX_RD(sc, GET_CID_ADDR(cid), i), 10073 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10074 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10075 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10076 } 10077 10078 BCE_PRINTF( 10079 "----------------------------" 10080 "----------------" 10081 "----------------------------\n"); 10082 } 10083 10084 /****************************************************************************/ 10085 /* Prints out the FTQ data. */ 10086 /* */ 10087 /* Returns: */ 10088 /* Nothing. */ 10089 /****************************************************************************/ 10090 static __attribute__ ((noinline)) void 10091 bce_dump_ftqs(struct bce_softc *sc) 10092 { 10093 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10094 10095 BCE_PRINTF( 10096 "----------------------------" 10097 " FTQ Data " 10098 "----------------------------\n"); 10099 10100 BCE_PRINTF(" FTQ Command Control Depth_Now " 10101 "Max_Depth Valid_Cnt \n"); 10102 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10103 "---------- ----------\n"); 10104 10105 /* Setup the generic statistic counters for the FTQ valid count. */ 10106 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10107 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10108 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10109 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10110 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10111 10112 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10113 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10114 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10115 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10116 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10117 10118 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10119 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10120 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10121 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10122 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10123 10124 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10125 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10126 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10127 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10128 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10129 10130 /* Input queue to the Receive Lookup state machine */ 10131 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10132 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10133 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10134 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10135 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10136 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10137 cmd, ctl, cur_depth, max_depth, valid_cnt); 10138 10139 /* Input queue to the Receive Processor */ 10140 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10141 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10142 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10143 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10144 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10145 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10146 cmd, ctl, cur_depth, max_depth, valid_cnt); 10147 10148 /* Input queue to the Recevie Processor */ 10149 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10150 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10151 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10152 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10153 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10154 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10155 cmd, ctl, cur_depth, max_depth, valid_cnt); 10156 10157 /* Input queue to the Receive Virtual to Physical state machine */ 10158 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10159 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10160 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10161 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10162 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10163 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10164 cmd, ctl, cur_depth, max_depth, valid_cnt); 10165 10166 /* Input queue to the Recevie Virtual to Physical state machine */ 10167 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10168 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10169 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10170 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10171 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10172 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10173 cmd, ctl, cur_depth, max_depth, valid_cnt); 10174 10175 /* Input queue to the Receive Virtual to Physical state machine */ 10176 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10177 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10178 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10179 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10180 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10181 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10182 cmd, ctl, cur_depth, max_depth, valid_cnt); 10183 10184 /* Input queue to the Receive DMA state machine */ 10185 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10186 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10187 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10188 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10189 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10190 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10191 cmd, ctl, cur_depth, max_depth, valid_cnt); 10192 10193 /* Input queue to the Transmit Scheduler state machine */ 10194 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10195 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10196 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10197 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10198 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10199 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10200 cmd, ctl, cur_depth, max_depth, valid_cnt); 10201 10202 /* Input queue to the Transmit Buffer Descriptor state machine */ 10203 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10204 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10205 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10206 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10207 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10208 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10209 cmd, ctl, cur_depth, max_depth, valid_cnt); 10210 10211 /* Input queue to the Transmit Processor */ 10212 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10213 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10214 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10215 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10216 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10217 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10218 cmd, ctl, cur_depth, max_depth, valid_cnt); 10219 10220 /* Input queue to the Transmit DMA state machine */ 10221 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10222 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10223 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10224 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10225 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10226 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10227 cmd, ctl, cur_depth, max_depth, valid_cnt); 10228 10229 /* Input queue to the Transmit Patch-Up Processor */ 10230 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10231 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10232 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10233 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10234 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10235 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10236 cmd, ctl, cur_depth, max_depth, valid_cnt); 10237 10238 /* Input queue to the Transmit Assembler state machine */ 10239 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10240 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10241 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10242 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10243 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10244 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10245 cmd, ctl, cur_depth, max_depth, valid_cnt); 10246 10247 /* Input queue to the Completion Processor */ 10248 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10249 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10250 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10251 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10252 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10253 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10254 cmd, ctl, cur_depth, max_depth, valid_cnt); 10255 10256 /* Input queue to the Completion Processor */ 10257 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10258 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10259 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10260 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10261 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10262 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10263 cmd, ctl, cur_depth, max_depth, valid_cnt); 10264 10265 /* Input queue to the Completion Processor */ 10266 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10267 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10268 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10269 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10270 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10271 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10272 cmd, ctl, cur_depth, max_depth, valid_cnt); 10273 10274 /* Setup the generic statistic counters for the FTQ valid count. */ 10275 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10276 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10277 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10278 10279 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10280 val = val | 10281 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10282 24); 10283 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10284 10285 /* Input queue to the Management Control Processor */ 10286 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10287 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10288 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10289 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10290 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10291 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10292 cmd, ctl, cur_depth, max_depth, valid_cnt); 10293 10294 /* Input queue to the Command Processor */ 10295 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10296 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10297 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10298 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10299 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10300 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10301 cmd, ctl, cur_depth, max_depth, valid_cnt); 10302 10303 /* Input queue to the Completion Scheduler state machine */ 10304 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10305 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10306 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10307 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10308 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10309 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10310 cmd, ctl, cur_depth, max_depth, valid_cnt); 10311 10312 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10313 /* Input queue to the RV2P Command Scheduler */ 10314 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10315 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10316 cur_depth = (ctl & 0xFFC00000) >> 22; 10317 max_depth = (ctl & 0x003FF000) >> 12; 10318 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10319 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10320 cmd, ctl, cur_depth, max_depth, valid_cnt); 10321 } 10322 10323 BCE_PRINTF( 10324 "----------------------------" 10325 "----------------" 10326 "----------------------------\n"); 10327 } 10328 10329 /****************************************************************************/ 10330 /* Prints out the TX chain. */ 10331 /* */ 10332 /* Returns: */ 10333 /* Nothing. */ 10334 /****************************************************************************/ 10335 static __attribute__ ((noinline)) void 10336 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10337 { 10338 struct tx_bd *txbd; 10339 10340 /* First some info about the tx_bd chain structure. */ 10341 BCE_PRINTF( 10342 "----------------------------" 10343 " tx_bd chain " 10344 "----------------------------\n"); 10345 10346 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10347 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10348 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10349 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10350 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10351 10352 BCE_PRINTF( 10353 "----------------------------" 10354 " tx_bd data " 10355 "----------------------------\n"); 10356 10357 /* Now print out a decoded list of TX buffer descriptors. */ 10358 for (int i = 0; i < count; i++) { 10359 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10360 bce_dump_txbd(sc, tx_prod, txbd); 10361 tx_prod++; 10362 } 10363 10364 BCE_PRINTF( 10365 "----------------------------" 10366 "----------------" 10367 "----------------------------\n"); 10368 } 10369 10370 /****************************************************************************/ 10371 /* Prints out the RX chain. */ 10372 /* */ 10373 /* Returns: */ 10374 /* Nothing. */ 10375 /****************************************************************************/ 10376 static __attribute__ ((noinline)) void 10377 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10378 { 10379 struct rx_bd *rxbd; 10380 10381 /* First some info about the rx_bd chain structure. */ 10382 BCE_PRINTF( 10383 "----------------------------" 10384 " rx_bd chain " 10385 "----------------------------\n"); 10386 10387 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10388 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10389 10390 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10391 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10392 10393 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10394 10395 BCE_PRINTF( 10396 "----------------------------" 10397 " rx_bd data " 10398 "----------------------------\n"); 10399 10400 /* Now print out the rx_bd's themselves. */ 10401 for (int i = 0; i < count; i++) { 10402 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10403 bce_dump_rxbd(sc, rx_prod, rxbd); 10404 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10405 } 10406 10407 BCE_PRINTF( 10408 "----------------------------" 10409 "----------------" 10410 "----------------------------\n"); 10411 } 10412 10413 /****************************************************************************/ 10414 /* Prints out the page chain. */ 10415 /* */ 10416 /* Returns: */ 10417 /* Nothing. */ 10418 /****************************************************************************/ 10419 static __attribute__ ((noinline)) void 10420 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10421 { 10422 struct rx_bd *pgbd; 10423 10424 /* First some info about the page chain structure. */ 10425 BCE_PRINTF( 10426 "----------------------------" 10427 " page chain " 10428 "----------------------------\n"); 10429 10430 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10431 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10432 10433 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10434 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10435 10436 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10437 10438 BCE_PRINTF( 10439 "----------------------------" 10440 " page data " 10441 "----------------------------\n"); 10442 10443 /* Now print out the rx_bd's themselves. */ 10444 for (int i = 0; i < count; i++) { 10445 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10446 bce_dump_pgbd(sc, pg_prod, pgbd); 10447 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10448 } 10449 10450 BCE_PRINTF( 10451 "----------------------------" 10452 "----------------" 10453 "----------------------------\n"); 10454 } 10455 10456 #define BCE_PRINT_RX_CONS(arg) \ 10457 if (sblk->status_rx_quick_consumer_index##arg) \ 10458 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10459 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10460 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10461 arg); 10462 10463 #define BCE_PRINT_TX_CONS(arg) \ 10464 if (sblk->status_tx_quick_consumer_index##arg) \ 10465 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10466 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10467 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10468 arg); 10469 10470 /****************************************************************************/ 10471 /* Prints out the status block from host memory. */ 10472 /* */ 10473 /* Returns: */ 10474 /* Nothing. */ 10475 /****************************************************************************/ 10476 static __attribute__ ((noinline)) void 10477 bce_dump_status_block(struct bce_softc *sc) 10478 { 10479 struct status_block *sblk; 10480 10481 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10482 10483 sblk = sc->status_block; 10484 10485 BCE_PRINTF( 10486 "----------------------------" 10487 " Status Block " 10488 "----------------------------\n"); 10489 10490 /* Theses indices are used for normal L2 drivers. */ 10491 BCE_PRINTF(" 0x%08X - attn_bits\n", 10492 sblk->status_attn_bits); 10493 10494 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10495 sblk->status_attn_bits_ack); 10496 10497 BCE_PRINT_RX_CONS(0); 10498 BCE_PRINT_TX_CONS(0) 10499 10500 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10501 10502 /* Theses indices are not used for normal L2 drivers. */ 10503 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10504 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10505 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10506 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10507 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10508 10509 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10510 10511 if (sblk->status_completion_producer_index || 10512 sblk->status_cmd_consumer_index) 10513 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10514 sblk->status_completion_producer_index, 10515 sblk->status_cmd_consumer_index); 10516 10517 BCE_PRINTF( 10518 "----------------------------" 10519 "----------------" 10520 "----------------------------\n"); 10521 } 10522 10523 #define BCE_PRINT_64BIT_STAT(arg) \ 10524 if (sblk->arg##_lo || sblk->arg##_hi) \ 10525 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10526 sblk->arg##_lo, #arg); 10527 10528 #define BCE_PRINT_32BIT_STAT(arg) \ 10529 if (sblk->arg) \ 10530 BCE_PRINTF(" 0x%08X : %s\n", \ 10531 sblk->arg, #arg); 10532 10533 /****************************************************************************/ 10534 /* Prints out the statistics block from host memory. */ 10535 /* */ 10536 /* Returns: */ 10537 /* Nothing. */ 10538 /****************************************************************************/ 10539 static __attribute__ ((noinline)) void 10540 bce_dump_stats_block(struct bce_softc *sc) 10541 { 10542 struct statistics_block *sblk; 10543 10544 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10545 10546 sblk = sc->stats_block; 10547 10548 BCE_PRINTF( 10549 "---------------" 10550 " Stats Block (All Stats Not Shown Are 0) " 10551 "---------------\n"); 10552 10553 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10554 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10555 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10556 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10557 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10558 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10559 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10560 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10561 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10562 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10563 BCE_PRINT_32BIT_STAT( 10564 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10565 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10566 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10567 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10568 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10569 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10570 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10571 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10572 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10573 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10574 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10575 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10576 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10577 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10578 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10579 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10580 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10581 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10582 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10583 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10584 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10585 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10586 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10587 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10588 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10589 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10590 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10591 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10592 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10593 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10594 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10595 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10596 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10597 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10598 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10599 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10600 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10601 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10602 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10603 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10604 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10605 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10606 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10607 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10608 10609 BCE_PRINTF( 10610 "----------------------------" 10611 "----------------" 10612 "----------------------------\n"); 10613 } 10614 10615 /****************************************************************************/ 10616 /* Prints out a summary of the driver state. */ 10617 /* */ 10618 /* Returns: */ 10619 /* Nothing. */ 10620 /****************************************************************************/ 10621 static __attribute__ ((noinline)) void 10622 bce_dump_driver_state(struct bce_softc *sc) 10623 { 10624 u32 val_hi, val_lo; 10625 10626 BCE_PRINTF( 10627 "-----------------------------" 10628 " Driver State " 10629 "-----------------------------\n"); 10630 10631 val_hi = BCE_ADDR_HI(sc); 10632 val_lo = BCE_ADDR_LO(sc); 10633 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10634 "address\n", val_hi, val_lo); 10635 10636 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10637 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10638 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10639 "address\n", val_hi, val_lo); 10640 10641 val_hi = BCE_ADDR_HI(sc->status_block); 10642 val_lo = BCE_ADDR_LO(sc->status_block); 10643 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10644 "virtual address\n", val_hi, val_lo); 10645 10646 val_hi = BCE_ADDR_HI(sc->stats_block); 10647 val_lo = BCE_ADDR_LO(sc->stats_block); 10648 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10649 "virtual address\n", val_hi, val_lo); 10650 10651 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10652 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10653 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10654 "virtual address\n", val_hi, val_lo); 10655 10656 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10657 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10658 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10659 "virtual address\n", val_hi, val_lo); 10660 10661 if (bce_hdr_split == TRUE) { 10662 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10663 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10664 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10665 "virtual address\n", val_hi, val_lo); 10666 } 10667 10668 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10669 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10670 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10671 "virtual address\n", val_hi, val_lo); 10672 10673 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10674 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10675 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10676 "virtual address\n", val_hi, val_lo); 10677 10678 if (bce_hdr_split == TRUE) { 10679 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10680 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10681 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10682 "virtual address\n", val_hi, val_lo); 10683 } 10684 10685 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10686 "h/w intrs\n", 10687 (long long unsigned int) sc->interrupts_generated); 10688 10689 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10690 "rx interrupts handled\n", 10691 (long long unsigned int) sc->interrupts_rx); 10692 10693 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10694 "tx interrupts handled\n", 10695 (long long unsigned int) sc->interrupts_tx); 10696 10697 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10698 "phy interrupts handled\n", 10699 (long long unsigned int) sc->phy_interrupts); 10700 10701 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10702 "status block index\n", sc->last_status_idx); 10703 10704 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10705 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10706 10707 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10708 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10709 10710 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10711 "byte seq index\n", sc->tx_prod_bseq); 10712 10713 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10714 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10715 10716 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10717 "tx_bd's\n", sc->used_tx_bd); 10718 10719 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10720 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10721 10722 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10723 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10724 10725 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10726 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10727 10728 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10729 "byte seq index\n", sc->rx_prod_bseq); 10730 10731 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10732 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10733 10734 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10735 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10736 10737 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10738 "rx_bd's\n", sc->free_rx_bd); 10739 10740 if (bce_hdr_split == TRUE) { 10741 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10742 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10743 10744 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10745 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10746 10747 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10748 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10749 } 10750 10751 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10752 "rx_bd's\n", sc->free_pg_bd); 10753 10754 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10755 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10756 10757 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10758 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10759 10760 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10761 "bce mac flags\n", sc->bce_flags); 10762 10763 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10764 "bce phy flags\n", sc->bce_phy_flags); 10765 10766 BCE_PRINTF( 10767 "----------------------------" 10768 "----------------" 10769 "----------------------------\n"); 10770 } 10771 10772 /****************************************************************************/ 10773 /* Prints out the hardware state through a summary of important register, */ 10774 /* followed by a complete register dump. */ 10775 /* */ 10776 /* Returns: */ 10777 /* Nothing. */ 10778 /****************************************************************************/ 10779 static __attribute__ ((noinline)) void 10780 bce_dump_hw_state(struct bce_softc *sc) 10781 { 10782 u32 val; 10783 10784 BCE_PRINTF( 10785 "----------------------------" 10786 " Hardware State " 10787 "----------------------------\n"); 10788 10789 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10790 10791 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10792 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10793 val, BCE_MISC_ENABLE_STATUS_BITS); 10794 10795 val = REG_RD(sc, BCE_DMA_STATUS); 10796 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10797 val, BCE_DMA_STATUS); 10798 10799 val = REG_RD(sc, BCE_CTX_STATUS); 10800 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10801 val, BCE_CTX_STATUS); 10802 10803 val = REG_RD(sc, BCE_EMAC_STATUS); 10804 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10805 val, BCE_EMAC_STATUS); 10806 10807 val = REG_RD(sc, BCE_RPM_STATUS); 10808 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10809 val, BCE_RPM_STATUS); 10810 10811 /* ToDo: Create a #define for this constant. */ 10812 val = REG_RD(sc, 0x2004); 10813 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10814 val, 0x2004); 10815 10816 val = REG_RD(sc, BCE_RV2P_STATUS); 10817 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10818 val, BCE_RV2P_STATUS); 10819 10820 /* ToDo: Create a #define for this constant. */ 10821 val = REG_RD(sc, 0x2c04); 10822 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10823 val, 0x2c04); 10824 10825 val = REG_RD(sc, BCE_TBDR_STATUS); 10826 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10827 val, BCE_TBDR_STATUS); 10828 10829 val = REG_RD(sc, BCE_TDMA_STATUS); 10830 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10831 val, BCE_TDMA_STATUS); 10832 10833 val = REG_RD(sc, BCE_HC_STATUS); 10834 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10835 val, BCE_HC_STATUS); 10836 10837 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10838 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10839 val, BCE_TXP_CPU_STATE); 10840 10841 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10842 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10843 val, BCE_TPAT_CPU_STATE); 10844 10845 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10846 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10847 val, BCE_RXP_CPU_STATE); 10848 10849 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10850 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10851 val, BCE_COM_CPU_STATE); 10852 10853 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10854 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10855 val, BCE_MCP_CPU_STATE); 10856 10857 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10858 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10859 val, BCE_CP_CPU_STATE); 10860 10861 BCE_PRINTF( 10862 "----------------------------" 10863 "----------------" 10864 "----------------------------\n"); 10865 10866 BCE_PRINTF( 10867 "----------------------------" 10868 " Register Dump " 10869 "----------------------------\n"); 10870 10871 for (int i = 0x400; i < 0x8000; i += 0x10) { 10872 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10873 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10874 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10875 } 10876 10877 BCE_PRINTF( 10878 "----------------------------" 10879 "----------------" 10880 "----------------------------\n"); 10881 } 10882 10883 /****************************************************************************/ 10884 /* Prints out the contentst of shared memory which is used for host driver */ 10885 /* to bootcode firmware communication. */ 10886 /* */ 10887 /* Returns: */ 10888 /* Nothing. */ 10889 /****************************************************************************/ 10890 static __attribute__ ((noinline)) void 10891 bce_dump_shmem_state(struct bce_softc *sc) 10892 { 10893 BCE_PRINTF( 10894 "----------------------------" 10895 " Hardware State " 10896 "----------------------------\n"); 10897 10898 BCE_PRINTF("0x%08X - Shared memory base address\n", 10899 sc->bce_shmem_base); 10900 BCE_PRINTF("%s - bootcode version\n", 10901 sc->bce_bc_ver); 10902 10903 BCE_PRINTF( 10904 "----------------------------" 10905 " Shared Mem " 10906 "----------------------------\n"); 10907 10908 for (int i = 0x0; i < 0x200; i += 0x10) { 10909 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10910 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 10911 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 10912 } 10913 10914 BCE_PRINTF( 10915 "----------------------------" 10916 "----------------" 10917 "----------------------------\n"); 10918 } 10919 10920 /****************************************************************************/ 10921 /* Prints out the mailbox queue registers. */ 10922 /* */ 10923 /* Returns: */ 10924 /* Nothing. */ 10925 /****************************************************************************/ 10926 static __attribute__ ((noinline)) void 10927 bce_dump_mq_regs(struct bce_softc *sc) 10928 { 10929 BCE_PRINTF( 10930 "----------------------------" 10931 " MQ Regs " 10932 "----------------------------\n"); 10933 10934 BCE_PRINTF( 10935 "----------------------------" 10936 "----------------" 10937 "----------------------------\n"); 10938 10939 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10940 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10941 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10942 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10943 } 10944 10945 BCE_PRINTF( 10946 "----------------------------" 10947 "----------------" 10948 "----------------------------\n"); 10949 } 10950 10951 /****************************************************************************/ 10952 /* Prints out the bootcode state. */ 10953 /* */ 10954 /* Returns: */ 10955 /* Nothing. */ 10956 /****************************************************************************/ 10957 static __attribute__ ((noinline)) void 10958 bce_dump_bc_state(struct bce_softc *sc) 10959 { 10960 u32 val; 10961 10962 BCE_PRINTF( 10963 "----------------------------" 10964 " Bootcode State " 10965 "----------------------------\n"); 10966 10967 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10968 10969 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10970 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10971 val, BCE_BC_RESET_TYPE); 10972 10973 val = bce_shmem_rd(sc, BCE_BC_STATE); 10974 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10975 val, BCE_BC_STATE); 10976 10977 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10978 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10979 val, BCE_BC_STATE_CONDITION); 10980 10981 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10982 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10983 val, BCE_BC_STATE_DEBUG_CMD); 10984 10985 BCE_PRINTF( 10986 "----------------------------" 10987 "----------------" 10988 "----------------------------\n"); 10989 } 10990 10991 /****************************************************************************/ 10992 /* Prints out the TXP processor state. */ 10993 /* */ 10994 /* Returns: */ 10995 /* Nothing. */ 10996 /****************************************************************************/ 10997 static __attribute__ ((noinline)) void 10998 bce_dump_txp_state(struct bce_softc *sc, int regs) 10999 { 11000 u32 val; 11001 u32 fw_version[3]; 11002 11003 BCE_PRINTF( 11004 "----------------------------" 11005 " TXP State " 11006 "----------------------------\n"); 11007 11008 for (int i = 0; i < 3; i++) 11009 fw_version[i] = htonl(REG_RD_IND(sc, 11010 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11011 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11012 11013 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11014 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11015 val, BCE_TXP_CPU_MODE); 11016 11017 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11018 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11019 val, BCE_TXP_CPU_STATE); 11020 11021 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11022 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11023 val, BCE_TXP_CPU_EVENT_MASK); 11024 11025 if (regs) { 11026 BCE_PRINTF( 11027 "----------------------------" 11028 " Register Dump " 11029 "----------------------------\n"); 11030 11031 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11032 /* Skip the big blank spaces */ 11033 if (i < 0x454000 && i > 0x5ffff) 11034 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11035 "0x%08X 0x%08X\n", i, 11036 REG_RD_IND(sc, i), 11037 REG_RD_IND(sc, i + 0x4), 11038 REG_RD_IND(sc, i + 0x8), 11039 REG_RD_IND(sc, i + 0xC)); 11040 } 11041 } 11042 11043 BCE_PRINTF( 11044 "----------------------------" 11045 "----------------" 11046 "----------------------------\n"); 11047 } 11048 11049 /****************************************************************************/ 11050 /* Prints out the RXP processor state. */ 11051 /* */ 11052 /* Returns: */ 11053 /* Nothing. */ 11054 /****************************************************************************/ 11055 static __attribute__ ((noinline)) void 11056 bce_dump_rxp_state(struct bce_softc *sc, int regs) 11057 { 11058 u32 val; 11059 u32 fw_version[3]; 11060 11061 BCE_PRINTF( 11062 "----------------------------" 11063 " RXP State " 11064 "----------------------------\n"); 11065 11066 for (int i = 0; i < 3; i++) 11067 fw_version[i] = htonl(REG_RD_IND(sc, 11068 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11069 11070 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11071 11072 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11073 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11074 val, BCE_RXP_CPU_MODE); 11075 11076 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11077 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11078 val, BCE_RXP_CPU_STATE); 11079 11080 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11081 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11082 val, BCE_RXP_CPU_EVENT_MASK); 11083 11084 if (regs) { 11085 BCE_PRINTF( 11086 "----------------------------" 11087 " Register Dump " 11088 "----------------------------\n"); 11089 11090 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11091 /* Skip the big blank sapces */ 11092 if (i < 0xc5400 && i > 0xdffff) 11093 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11094 "0x%08X 0x%08X\n", i, 11095 REG_RD_IND(sc, i), 11096 REG_RD_IND(sc, i + 0x4), 11097 REG_RD_IND(sc, i + 0x8), 11098 REG_RD_IND(sc, i + 0xC)); 11099 } 11100 } 11101 11102 BCE_PRINTF( 11103 "----------------------------" 11104 "----------------" 11105 "----------------------------\n"); 11106 } 11107 11108 /****************************************************************************/ 11109 /* Prints out the TPAT processor state. */ 11110 /* */ 11111 /* Returns: */ 11112 /* Nothing. */ 11113 /****************************************************************************/ 11114 static __attribute__ ((noinline)) void 11115 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11116 { 11117 u32 val; 11118 u32 fw_version[3]; 11119 11120 BCE_PRINTF( 11121 "----------------------------" 11122 " TPAT State " 11123 "----------------------------\n"); 11124 11125 for (int i = 0; i < 3; i++) 11126 fw_version[i] = htonl(REG_RD_IND(sc, 11127 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11128 11129 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11130 11131 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11132 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11133 val, BCE_TPAT_CPU_MODE); 11134 11135 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11136 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11137 val, BCE_TPAT_CPU_STATE); 11138 11139 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11140 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11141 val, BCE_TPAT_CPU_EVENT_MASK); 11142 11143 if (regs) { 11144 BCE_PRINTF( 11145 "----------------------------" 11146 " Register Dump " 11147 "----------------------------\n"); 11148 11149 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11150 /* Skip the big blank spaces */ 11151 if (i < 0x854000 && i > 0x9ffff) 11152 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11153 "0x%08X 0x%08X\n", i, 11154 REG_RD_IND(sc, i), 11155 REG_RD_IND(sc, i + 0x4), 11156 REG_RD_IND(sc, i + 0x8), 11157 REG_RD_IND(sc, i + 0xC)); 11158 } 11159 } 11160 11161 BCE_PRINTF( 11162 "----------------------------" 11163 "----------------" 11164 "----------------------------\n"); 11165 } 11166 11167 /****************************************************************************/ 11168 /* Prints out the Command Procesor (CP) state. */ 11169 /* */ 11170 /* Returns: */ 11171 /* Nothing. */ 11172 /****************************************************************************/ 11173 static __attribute__ ((noinline)) void 11174 bce_dump_cp_state(struct bce_softc *sc, int regs) 11175 { 11176 u32 val; 11177 u32 fw_version[3]; 11178 11179 BCE_PRINTF( 11180 "----------------------------" 11181 " CP State " 11182 "----------------------------\n"); 11183 11184 for (int i = 0; i < 3; i++) 11185 fw_version[i] = htonl(REG_RD_IND(sc, 11186 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11187 11188 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11189 11190 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11191 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11192 val, BCE_CP_CPU_MODE); 11193 11194 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11195 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11196 val, BCE_CP_CPU_STATE); 11197 11198 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11199 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11200 BCE_CP_CPU_EVENT_MASK); 11201 11202 if (regs) { 11203 BCE_PRINTF( 11204 "----------------------------" 11205 " Register Dump " 11206 "----------------------------\n"); 11207 11208 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11209 /* Skip the big blank spaces */ 11210 if (i < 0x185400 && i > 0x19ffff) 11211 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11212 "0x%08X 0x%08X\n", i, 11213 REG_RD_IND(sc, i), 11214 REG_RD_IND(sc, i + 0x4), 11215 REG_RD_IND(sc, i + 0x8), 11216 REG_RD_IND(sc, i + 0xC)); 11217 } 11218 } 11219 11220 BCE_PRINTF( 11221 "----------------------------" 11222 "----------------" 11223 "----------------------------\n"); 11224 } 11225 11226 /****************************************************************************/ 11227 /* Prints out the Completion Procesor (COM) state. */ 11228 /* */ 11229 /* Returns: */ 11230 /* Nothing. */ 11231 /****************************************************************************/ 11232 static __attribute__ ((noinline)) void 11233 bce_dump_com_state(struct bce_softc *sc, int regs) 11234 { 11235 u32 val; 11236 u32 fw_version[4]; 11237 11238 BCE_PRINTF( 11239 "----------------------------" 11240 " COM State " 11241 "----------------------------\n"); 11242 11243 for (int i = 0; i < 3; i++) 11244 fw_version[i] = htonl(REG_RD_IND(sc, 11245 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11246 11247 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11248 11249 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11250 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11251 val, BCE_COM_CPU_MODE); 11252 11253 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11254 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11255 val, BCE_COM_CPU_STATE); 11256 11257 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11258 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11259 BCE_COM_CPU_EVENT_MASK); 11260 11261 if (regs) { 11262 BCE_PRINTF( 11263 "----------------------------" 11264 " Register Dump " 11265 "----------------------------\n"); 11266 11267 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11268 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11269 "0x%08X 0x%08X\n", i, 11270 REG_RD_IND(sc, i), 11271 REG_RD_IND(sc, i + 0x4), 11272 REG_RD_IND(sc, i + 0x8), 11273 REG_RD_IND(sc, i + 0xC)); 11274 } 11275 } 11276 11277 BCE_PRINTF( 11278 "----------------------------" 11279 "----------------" 11280 "----------------------------\n"); 11281 } 11282 11283 /****************************************************************************/ 11284 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11285 /* */ 11286 /* Returns: */ 11287 /* Nothing. */ 11288 /****************************************************************************/ 11289 static __attribute__ ((noinline)) void 11290 bce_dump_rv2p_state(struct bce_softc *sc) 11291 { 11292 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11293 11294 BCE_PRINTF( 11295 "----------------------------" 11296 " RV2P State " 11297 "----------------------------\n"); 11298 11299 /* Stall the RV2P processors. */ 11300 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11301 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11302 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11303 11304 /* Read the firmware version. */ 11305 val = 0x00000001; 11306 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11307 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11308 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11309 BCE_RV2P_INSTR_HIGH_HIGH; 11310 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11311 fw_ver_high, fw_ver_low); 11312 11313 val = 0x00000001; 11314 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11315 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11316 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11317 BCE_RV2P_INSTR_HIGH_HIGH; 11318 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11319 fw_ver_high, fw_ver_low); 11320 11321 /* Resume the RV2P processors. */ 11322 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11323 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11324 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11325 11326 /* Fetch the program counter value. */ 11327 val = 0x68007800; 11328 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11329 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11330 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11331 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11332 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11333 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11334 11335 /* Fetch the program counter value again to see if it is advancing. */ 11336 val = 0x68007800; 11337 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11338 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11339 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11340 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11341 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11342 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11343 11344 BCE_PRINTF( 11345 "----------------------------" 11346 "----------------" 11347 "----------------------------\n"); 11348 } 11349 11350 /****************************************************************************/ 11351 /* Prints out the driver state and then enters the debugger. */ 11352 /* */ 11353 /* Returns: */ 11354 /* Nothing. */ 11355 /****************************************************************************/ 11356 static __attribute__ ((noinline)) void 11357 bce_breakpoint(struct bce_softc *sc) 11358 { 11359 11360 /* 11361 * Unreachable code to silence compiler warnings 11362 * about unused functions. 11363 */ 11364 if (0) { 11365 bce_freeze_controller(sc); 11366 bce_unfreeze_controller(sc); 11367 bce_dump_enet(sc, NULL); 11368 bce_dump_txbd(sc, 0, NULL); 11369 bce_dump_rxbd(sc, 0, NULL); 11370 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11371 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11372 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11373 bce_dump_l2fhdr(sc, 0, NULL); 11374 bce_dump_ctx(sc, RX_CID); 11375 bce_dump_ftqs(sc); 11376 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11377 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11378 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11379 bce_dump_status_block(sc); 11380 bce_dump_stats_block(sc); 11381 bce_dump_driver_state(sc); 11382 bce_dump_hw_state(sc); 11383 bce_dump_bc_state(sc); 11384 bce_dump_txp_state(sc, 0); 11385 bce_dump_rxp_state(sc, 0); 11386 bce_dump_tpat_state(sc, 0); 11387 bce_dump_cp_state(sc, 0); 11388 bce_dump_com_state(sc, 0); 11389 bce_dump_rv2p_state(sc); 11390 bce_dump_pgbd(sc, 0, NULL); 11391 } 11392 11393 bce_dump_status_block(sc); 11394 bce_dump_driver_state(sc); 11395 11396 /* Call the debugger. */ 11397 breakpoint(); 11398 } 11399 #endif 11400