1 /*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54 #include "opt_bce.h" 55 56 #include <dev/bce/if_bcereg.h> 57 #include <dev/bce/if_bcefw.h> 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89 #endif 90 91 /****************************************************************************/ 92 /* PCI Device ID Table */ 93 /* */ 94 /* Used by bce_probe() to identify the devices supported by this driver. */ 95 /****************************************************************************/ 96 #define BCE_DEVDESC_MAX 64 97 98 static struct bce_type bce_devs[] = { 99 /* BCM5706C Controllers and OEM boards. */ 100 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 101 "HP NC370T Multifunction Gigabit Server Adapter" }, 102 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 103 "HP NC370i Multifunction Gigabit Server Adapter" }, 104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 105 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 107 "HP NC371i Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 109 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 110 111 /* BCM5706S controllers and OEM boards. */ 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 113 "HP NC370F Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 116 117 /* BCM5708C controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 119 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 121 "HP NC373i Multifunction Gigabit Server Adapter" }, 122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 123 "HP NC374m PCIe Multifunction Adapter" }, 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 125 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 126 127 /* BCM5708S controllers and OEM boards. */ 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 129 "HP NC373m Multifunction Gigabit Server Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 131 "HP NC373i Multifunction Gigabit Server Adapter" }, 132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 133 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 135 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 136 137 /* BCM5709C controllers and OEM boards. */ 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 139 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 141 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 143 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 144 145 /* BCM5709S controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 147 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 149 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 151 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 152 153 /* BCM5716 controllers and OEM boards. */ 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 155 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 156 157 { 0, 0, 0, 0, NULL } 158 }; 159 160 161 /****************************************************************************/ 162 /* Supported Flash NVRAM device data. */ 163 /****************************************************************************/ 164 static struct flash_spec flash_table[] = 165 { 166 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 167 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 168 169 /* Slow EEPROM */ 170 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 171 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 172 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 173 "EEPROM - slow"}, 174 /* Expansion entry 0001 */ 175 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 178 "Entry 0001"}, 179 /* Saifun SA25F010 (non-buffered flash) */ 180 /* strap, cfg1, & write1 need updates */ 181 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 184 "Non-buffered flash (128kB)"}, 185 /* Saifun SA25F020 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 190 "Non-buffered flash (256kB)"}, 191 /* Expansion entry 0100 */ 192 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0100"}, 196 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 197 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 198 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 199 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 200 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 201 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 202 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 204 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 205 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 206 /* Saifun SA25F005 (non-buffered flash) */ 207 /* strap, cfg1, & write1 need updates */ 208 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 210 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 211 "Non-buffered flash (64kB)"}, 212 /* Fast EEPROM */ 213 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 214 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 215 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 216 "EEPROM - fast"}, 217 /* Expansion entry 1001 */ 218 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 221 "Entry 1001"}, 222 /* Expansion entry 1010 */ 223 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 226 "Entry 1010"}, 227 /* ATMEL AT45DB011B (buffered flash) */ 228 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 230 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 231 "Buffered flash (128kB)"}, 232 /* Expansion entry 1100 */ 233 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 236 "Entry 1100"}, 237 /* Expansion entry 1101 */ 238 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 1101"}, 242 /* Ateml Expansion entry 1110 */ 243 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 244 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 245 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 246 "Entry 1110 (Atmel)"}, 247 /* ATMEL AT45DB021B (buffered flash) */ 248 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 251 "Buffered flash (256kB)"}, 252 }; 253 254 /* 255 * The BCM5709 controllers transparently handle the 256 * differences between Atmel 264 byte pages and all 257 * flash devices which use 256 byte pages, so no 258 * logical-to-physical mapping is required in the 259 * driver. 260 */ 261 static struct flash_spec flash_5709 = { 262 .flags = BCE_NV_BUFFERED, 263 .page_bits = BCM5709_FLASH_PAGE_BITS, 264 .page_size = BCM5709_FLASH_PAGE_SIZE, 265 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 266 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 267 .name = "5709/5716 buffered flash (256kB)", 268 }; 269 270 271 /****************************************************************************/ 272 /* FreeBSD device entry points. */ 273 /****************************************************************************/ 274 static int bce_probe (device_t); 275 static int bce_attach (device_t); 276 static int bce_detach (device_t); 277 static int bce_shutdown (device_t); 278 279 280 /****************************************************************************/ 281 /* BCE Debug Data Structure Dump Routines */ 282 /****************************************************************************/ 283 #ifdef BCE_DEBUG 284 static u32 bce_reg_rd (struct bce_softc *, u32); 285 static void bce_reg_wr (struct bce_softc *, u32, u32); 286 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 287 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 288 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 289 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 290 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 291 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 292 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 293 static void bce_dump_txbd (struct bce_softc *, 294 int, struct tx_bd *); 295 static void bce_dump_rxbd (struct bce_softc *, 296 int, struct rx_bd *); 297 static void bce_dump_pgbd (struct bce_softc *, 298 int, struct rx_bd *); 299 static void bce_dump_l2fhdr (struct bce_softc *, 300 int, struct l2_fhdr *); 301 static void bce_dump_ctx (struct bce_softc *, u16); 302 static void bce_dump_ftqs (struct bce_softc *); 303 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 304 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 305 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 306 static void bce_dump_status_block (struct bce_softc *); 307 static void bce_dump_stats_block (struct bce_softc *); 308 static void bce_dump_driver_state (struct bce_softc *); 309 static void bce_dump_hw_state (struct bce_softc *); 310 static void bce_dump_shmem_state (struct bce_softc *); 311 static void bce_dump_mq_regs (struct bce_softc *); 312 static void bce_dump_bc_state (struct bce_softc *); 313 static void bce_dump_txp_state (struct bce_softc *, int); 314 static void bce_dump_rxp_state (struct bce_softc *, int); 315 static void bce_dump_tpat_state (struct bce_softc *, int); 316 static void bce_dump_cp_state (struct bce_softc *, int); 317 static void bce_dump_com_state (struct bce_softc *, int); 318 static void bce_dump_rv2p_state (struct bce_softc *); 319 static void bce_breakpoint (struct bce_softc *); 320 #endif /*BCE_DEBUG */ 321 322 323 /****************************************************************************/ 324 /* BCE Register/Memory Access Routines */ 325 /****************************************************************************/ 326 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 327 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 328 static void bce_shmem_wr (struct bce_softc *, u32, u32); 329 static u32 bce_shmem_rd (struct bce_softc *, u32); 330 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 331 static int bce_miibus_read_reg (device_t, int, int); 332 static int bce_miibus_write_reg (device_t, int, int, int); 333 static void bce_miibus_statchg (device_t); 334 335 #ifdef BCE_DEBUG 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 337 #ifdef BCE_NVRAM_WRITE_SUPPORT 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 339 #endif 340 #endif 341 342 /****************************************************************************/ 343 /* BCE NVRAM Access Routines */ 344 /****************************************************************************/ 345 static int bce_acquire_nvram_lock (struct bce_softc *); 346 static int bce_release_nvram_lock (struct bce_softc *); 347 static void bce_enable_nvram_access(struct bce_softc *); 348 static void bce_disable_nvram_access(struct bce_softc *); 349 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 350 static int bce_init_nvram (struct bce_softc *); 351 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 352 static int bce_nvram_test (struct bce_softc *); 353 #ifdef BCE_NVRAM_WRITE_SUPPORT 354 static int bce_enable_nvram_write (struct bce_softc *); 355 static void bce_disable_nvram_write(struct bce_softc *); 356 static int bce_nvram_erase_page (struct bce_softc *, u32); 357 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 358 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 359 #endif 360 361 /****************************************************************************/ 362 /* */ 363 /****************************************************************************/ 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 365 static void bce_get_media (struct bce_softc *); 366 static void bce_init_media (struct bce_softc *); 367 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 368 static int bce_dma_alloc (device_t); 369 static void bce_dma_free (struct bce_softc *); 370 static void bce_release_resources (struct bce_softc *); 371 372 /****************************************************************************/ 373 /* BCE Firmware Synchronization and Load */ 374 /****************************************************************************/ 375 static int bce_fw_sync (struct bce_softc *, u32); 376 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 377 static void bce_load_cpu_fw (struct bce_softc *, 378 struct cpu_reg *, struct fw_info *); 379 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 380 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 381 static void bce_start_rxp_cpu (struct bce_softc *); 382 static void bce_init_rxp_cpu (struct bce_softc *); 383 static void bce_init_txp_cpu (struct bce_softc *); 384 static void bce_init_tpat_cpu (struct bce_softc *); 385 static void bce_init_cp_cpu (struct bce_softc *); 386 static void bce_init_com_cpu (struct bce_softc *); 387 static void bce_init_cpus (struct bce_softc *); 388 389 static void bce_print_adapter_info (struct bce_softc *); 390 static void bce_probe_pci_caps (device_t, struct bce_softc *); 391 static void bce_stop (struct bce_softc *); 392 static int bce_reset (struct bce_softc *, u32); 393 static int bce_chipinit (struct bce_softc *); 394 static int bce_blockinit (struct bce_softc *); 395 396 static int bce_init_tx_chain (struct bce_softc *); 397 static void bce_free_tx_chain (struct bce_softc *); 398 399 static int bce_get_rx_buf (struct bce_softc *, 400 struct mbuf *, u16 *, u16 *, u32 *); 401 static int bce_init_rx_chain (struct bce_softc *); 402 static void bce_fill_rx_chain (struct bce_softc *); 403 static void bce_free_rx_chain (struct bce_softc *); 404 405 static int bce_get_pg_buf (struct bce_softc *, 406 struct mbuf *, u16 *, u16 *); 407 static int bce_init_pg_chain (struct bce_softc *); 408 static void bce_fill_pg_chain (struct bce_softc *); 409 static void bce_free_pg_chain (struct bce_softc *); 410 411 static struct mbuf *bce_tso_setup (struct bce_softc *, 412 struct mbuf **, u16 *); 413 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 414 static void bce_start_locked (struct ifnet *); 415 static void bce_start (struct ifnet *); 416 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 417 static void bce_watchdog (struct bce_softc *); 418 static int bce_ifmedia_upd (struct ifnet *); 419 static int bce_ifmedia_upd_locked (struct ifnet *); 420 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 421 static void bce_init_locked (struct bce_softc *); 422 static void bce_init (void *); 423 static void bce_mgmt_init_locked (struct bce_softc *sc); 424 425 static int bce_init_ctx (struct bce_softc *); 426 static void bce_get_mac_addr (struct bce_softc *); 427 static void bce_set_mac_addr (struct bce_softc *); 428 static void bce_phy_intr (struct bce_softc *); 429 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 430 static void bce_rx_intr (struct bce_softc *); 431 static void bce_tx_intr (struct bce_softc *); 432 static void bce_disable_intr (struct bce_softc *); 433 static void bce_enable_intr (struct bce_softc *, int); 434 435 static void bce_intr (void *); 436 static void bce_set_rx_mode (struct bce_softc *); 437 static void bce_stats_update (struct bce_softc *); 438 static void bce_tick (void *); 439 static void bce_pulse (void *); 440 static void bce_add_sysctls (struct bce_softc *); 441 442 443 /****************************************************************************/ 444 /* FreeBSD device dispatch table. */ 445 /****************************************************************************/ 446 static device_method_t bce_methods[] = { 447 /* Device interface (device_if.h) */ 448 DEVMETHOD(device_probe, bce_probe), 449 DEVMETHOD(device_attach, bce_attach), 450 DEVMETHOD(device_detach, bce_detach), 451 DEVMETHOD(device_shutdown, bce_shutdown), 452 /* Supported by device interface but not used here. */ 453 /* DEVMETHOD(device_identify, bce_identify), */ 454 /* DEVMETHOD(device_suspend, bce_suspend), */ 455 /* DEVMETHOD(device_resume, bce_resume), */ 456 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 457 458 /* Bus interface (bus_if.h) */ 459 DEVMETHOD(bus_print_child, bus_generic_print_child), 460 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 461 462 /* MII interface (miibus_if.h) */ 463 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 464 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 465 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 466 /* Supported by MII interface but not used here. */ 467 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 468 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 469 470 { 0, 0 } 471 }; 472 473 static driver_t bce_driver = { 474 "bce", 475 bce_methods, 476 sizeof(struct bce_softc) 477 }; 478 479 static devclass_t bce_devclass; 480 481 MODULE_DEPEND(bce, pci, 1, 1, 1); 482 MODULE_DEPEND(bce, ether, 1, 1, 1); 483 MODULE_DEPEND(bce, miibus, 1, 1, 1); 484 485 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 486 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 487 488 489 /****************************************************************************/ 490 /* Tunable device values */ 491 /****************************************************************************/ 492 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 493 494 /* Allowable values are TRUE or FALSE */ 495 static int bce_verbose = TRUE; 496 TUNABLE_INT("hw.bce.verbose", &bce_verbose); 497 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 498 "Verbose output enable/disable"); 499 500 /* Allowable values are TRUE or FALSE */ 501 static int bce_tso_enable = TRUE; 502 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 503 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 504 "TSO Enable/Disable"); 505 506 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 507 /* ToDo: Add MSI-X support. */ 508 static int bce_msi_enable = 1; 509 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 510 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 511 "MSI-X|MSI|INTx selector"); 512 513 /* Allowable values are 1, 2, 4, 8. */ 514 static int bce_rx_pages = DEFAULT_RX_PAGES; 515 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 516 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 517 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 518 519 /* Allowable values are 1, 2, 4, 8. */ 520 static int bce_tx_pages = DEFAULT_TX_PAGES; 521 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 522 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 523 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 524 525 /* Allowable values are TRUE or FALSE. */ 526 static int bce_hdr_split = TRUE; 527 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 528 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 529 "Frame header/payload splitting Enable/Disable"); 530 531 /* Allowable values are TRUE or FALSE. */ 532 static int bce_strict_rx_mtu = FALSE; 533 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 534 SYSCTL_UINT(_hw_bce, OID_AUTO, loose_rx_mtu, CTLFLAG_RDTUN, 535 &bce_strict_rx_mtu, 0, 536 "Enable/Disable strict RX frame size checking"); 537 538 /* Allowable values are 0 ... 100 */ 539 #ifdef BCE_DEBUG 540 /* Generate 1 interrupt for every transmit completion. */ 541 static int bce_tx_quick_cons_trip_int = 1; 542 #else 543 /* Generate 1 interrupt for every 20 transmit completions. */ 544 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 545 #endif 546 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 547 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 548 &bce_tx_quick_cons_trip_int, 0, 549 "Transmit BD trip point during interrupts"); 550 551 /* Allowable values are 0 ... 100 */ 552 /* Generate 1 interrupt for every transmit completion. */ 553 #ifdef BCE_DEBUG 554 static int bce_tx_quick_cons_trip = 1; 555 #else 556 /* Generate 1 interrupt for every 20 transmit completions. */ 557 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 558 #endif 559 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 560 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 561 &bce_tx_quick_cons_trip, 0, 562 "Transmit BD trip point"); 563 564 /* Allowable values are 0 ... 100 */ 565 #ifdef BCE_DEBUG 566 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 567 static int bce_tx_ticks_int = 0; 568 #else 569 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 570 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 571 #endif 572 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 573 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 574 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 575 576 /* Allowable values are 0 ... 100 */ 577 #ifdef BCE_DEBUG 578 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 579 static int bce_tx_ticks = 0; 580 #else 581 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 582 static int bce_tx_ticks = DEFAULT_TX_TICKS; 583 #endif 584 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 585 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 586 &bce_tx_ticks, 0, "Transmit ticks count"); 587 588 /* Allowable values are 1 ... 100 */ 589 #ifdef BCE_DEBUG 590 /* Generate 1 interrupt for every received frame. */ 591 static int bce_rx_quick_cons_trip_int = 1; 592 #else 593 /* Generate 1 interrupt for every 6 received frames. */ 594 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 595 #endif 596 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 597 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 598 &bce_rx_quick_cons_trip_int, 0, 599 "Receive BD trip point duirng interrupts"); 600 601 /* Allowable values are 1 ... 100 */ 602 #ifdef BCE_DEBUG 603 /* Generate 1 interrupt for every received frame. */ 604 static int bce_rx_quick_cons_trip = 1; 605 #else 606 /* Generate 1 interrupt for every 6 received frames. */ 607 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 608 #endif 609 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 610 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 611 &bce_rx_quick_cons_trip, 0, 612 "Receive BD trip point"); 613 614 /* Allowable values are 0 ... 100 */ 615 #ifdef BCE_DEBUG 616 /* Generate an int. if 0us have elapsed since the last received frame. */ 617 static int bce_rx_ticks_int = 0; 618 #else 619 /* Generate an int. if 18us have elapsed since the last received frame. */ 620 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 621 #endif 622 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 623 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 624 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 625 626 /* Allowable values are 0 ... 100 */ 627 #ifdef BCE_DEBUG 628 /* Generate an int. if 0us have elapsed since the last received frame. */ 629 static int bce_rx_ticks = 0; 630 #else 631 /* Generate an int. if 18us have elapsed since the last received frame. */ 632 static int bce_rx_ticks = DEFAULT_RX_TICKS; 633 #endif 634 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 635 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 636 &bce_rx_ticks, 0, "Receive ticks count"); 637 638 639 /****************************************************************************/ 640 /* Device probe function. */ 641 /* */ 642 /* Compares the device to the driver's list of supported devices and */ 643 /* reports back to the OS whether this is the right driver for the device. */ 644 /* */ 645 /* Returns: */ 646 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 647 /****************************************************************************/ 648 static int 649 bce_probe(device_t dev) 650 { 651 struct bce_type *t; 652 struct bce_softc *sc; 653 char *descbuf; 654 u16 vid = 0, did = 0, svid = 0, sdid = 0; 655 656 t = bce_devs; 657 658 sc = device_get_softc(dev); 659 bzero(sc, sizeof(struct bce_softc)); 660 sc->bce_unit = device_get_unit(dev); 661 sc->bce_dev = dev; 662 663 /* Get the data for the device to be probed. */ 664 vid = pci_get_vendor(dev); 665 did = pci_get_device(dev); 666 svid = pci_get_subvendor(dev); 667 sdid = pci_get_subdevice(dev); 668 669 DBPRINT(sc, BCE_EXTREME_LOAD, 670 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 671 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 672 673 /* Look through the list of known devices for a match. */ 674 while(t->bce_name != NULL) { 675 676 if ((vid == t->bce_vid) && (did == t->bce_did) && 677 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 678 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 679 680 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 681 682 if (descbuf == NULL) 683 return(ENOMEM); 684 685 /* Print out the device identity. */ 686 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 687 t->bce_name, (((pci_read_config(dev, 688 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 689 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 690 691 device_set_desc_copy(dev, descbuf); 692 free(descbuf, M_TEMP); 693 return(BUS_PROBE_DEFAULT); 694 } 695 t++; 696 } 697 698 return(ENXIO); 699 } 700 701 702 /****************************************************************************/ 703 /* PCI Capabilities Probe Function. */ 704 /* */ 705 /* Walks the PCI capabiites list for the device to find what features are */ 706 /* supported. */ 707 /* */ 708 /* Returns: */ 709 /* None. */ 710 /****************************************************************************/ 711 static void 712 bce_print_adapter_info(struct bce_softc *sc) 713 { 714 int i = 0; 715 716 DBENTER(BCE_VERBOSE_LOAD); 717 718 if (bce_verbose || bootverbose) { 719 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 720 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 721 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 722 723 724 /* Bus info. */ 725 if (sc->bce_flags & BCE_PCIE_FLAG) { 726 printf("Bus (PCIe x%d, ", sc->link_width); 727 switch (sc->link_speed) { 728 case 1: printf("2.5Gbps); "); break; 729 case 2: printf("5Gbps); "); break; 730 default: printf("Unknown link speed); "); 731 } 732 } else { 733 printf("Bus (PCI%s, %s, %dMHz); ", 734 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 735 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 736 "32-bit" : "64-bit"), sc->bus_speed_mhz); 737 } 738 739 /* Firmware version and device features. */ 740 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 741 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 742 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 743 744 if (bce_hdr_split == TRUE) { 745 printf("SPLT"); 746 i++; 747 } 748 749 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 750 if (i > 0) printf("|"); 751 printf("MSI"); i++; 752 } 753 754 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 755 if (i > 0) printf("|"); 756 printf("MSI-X"); i++; 757 } 758 759 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 760 if (i > 0) printf("|"); 761 printf("2.5G"); i++; 762 } 763 764 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 765 if (i > 0) printf("|"); 766 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 767 } else { 768 printf(")\n"); 769 } 770 771 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 772 sc->bce_rx_quick_cons_trip_int, 773 sc->bce_rx_quick_cons_trip, 774 sc->bce_rx_ticks_int, 775 sc->bce_rx_ticks, 776 sc->bce_tx_quick_cons_trip_int, 777 sc->bce_tx_quick_cons_trip, 778 sc->bce_tx_ticks_int, 779 sc->bce_tx_ticks); 780 781 } 782 783 DBEXIT(BCE_VERBOSE_LOAD); 784 } 785 786 787 /****************************************************************************/ 788 /* PCI Capabilities Probe Function. */ 789 /* */ 790 /* Walks the PCI capabiites list for the device to find what features are */ 791 /* supported. */ 792 /* */ 793 /* Returns: */ 794 /* None. */ 795 /****************************************************************************/ 796 static void 797 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 798 { 799 u32 reg; 800 801 DBENTER(BCE_VERBOSE_LOAD); 802 803 /* Check if PCI-X capability is enabled. */ 804 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 805 if (reg != 0) 806 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 807 } 808 809 /* Check if PCIe capability is enabled. */ 810 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 811 if (reg != 0) { 812 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 813 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 814 "0x%08X\n", link_status); 815 sc->link_speed = link_status & 0xf; 816 sc->link_width = (link_status >> 4) & 0x3f; 817 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 818 sc->bce_flags |= BCE_PCIE_FLAG; 819 } 820 } 821 822 /* Check if MSI capability is enabled. */ 823 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 824 if (reg != 0) 825 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 826 } 827 828 /* Check if MSI-X capability is enabled. */ 829 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 830 if (reg != 0) 831 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 832 } 833 834 DBEXIT(BCE_VERBOSE_LOAD); 835 } 836 837 838 /****************************************************************************/ 839 /* Load and validate user tunable settings. */ 840 /* */ 841 /* Returns: */ 842 /* Nothing. */ 843 /****************************************************************************/ 844 static void 845 bce_set_tunables(struct bce_softc *sc) 846 { 847 /* Set sysctl values for RX page count. */ 848 switch (bce_rx_pages) { 849 case 1: 850 /* fall-through */ 851 case 2: 852 /* fall-through */ 853 case 4: 854 /* fall-through */ 855 case 8: 856 sc->rx_pages = bce_rx_pages; 857 break; 858 default: 859 sc->rx_pages = DEFAULT_RX_PAGES; 860 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 861 "hw.bce.rx_pages! Setting default of %d.\n", 862 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 863 } 864 865 /* ToDo: Consider allowing user setting for pg_pages. */ 866 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 867 868 /* Set sysctl values for TX page count. */ 869 switch (bce_tx_pages) { 870 case 1: 871 /* fall-through */ 872 case 2: 873 /* fall-through */ 874 case 4: 875 /* fall-through */ 876 case 8: 877 sc->tx_pages = bce_tx_pages; 878 break; 879 default: 880 sc->tx_pages = DEFAULT_TX_PAGES; 881 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 882 "hw.bce.tx_pages! Setting default of %d.\n", 883 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 884 } 885 886 /* 887 * Validate the TX trip point (i.e. the number of 888 * TX completions before a status block update is 889 * generated and an interrupt is asserted. 890 */ 891 if (bce_tx_quick_cons_trip_int <= 100) { 892 sc->bce_tx_quick_cons_trip_int = 893 bce_tx_quick_cons_trip_int; 894 } else { 895 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 896 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 897 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 898 DEFAULT_TX_QUICK_CONS_TRIP_INT); 899 sc->bce_tx_quick_cons_trip_int = 900 DEFAULT_TX_QUICK_CONS_TRIP_INT; 901 } 902 903 if (bce_tx_quick_cons_trip <= 100) { 904 sc->bce_tx_quick_cons_trip = 905 bce_tx_quick_cons_trip; 906 } else { 907 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 908 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 909 __FILE__, __LINE__, bce_tx_quick_cons_trip, 910 DEFAULT_TX_QUICK_CONS_TRIP); 911 sc->bce_tx_quick_cons_trip = 912 DEFAULT_TX_QUICK_CONS_TRIP; 913 } 914 915 /* 916 * Validate the TX ticks count (i.e. the maximum amount 917 * of time to wait after the last TX completion has 918 * occurred before a status block update is generated 919 * and an interrupt is asserted. 920 */ 921 if (bce_tx_ticks_int <= 100) { 922 sc->bce_tx_ticks_int = 923 bce_tx_ticks_int; 924 } else { 925 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 926 "hw.bce.tx_ticks_int! Setting default of %d.\n", 927 __FILE__, __LINE__, bce_tx_ticks_int, 928 DEFAULT_TX_TICKS_INT); 929 sc->bce_tx_ticks_int = 930 DEFAULT_TX_TICKS_INT; 931 } 932 933 if (bce_tx_ticks <= 100) { 934 sc->bce_tx_ticks = 935 bce_tx_ticks; 936 } else { 937 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 938 "hw.bce.tx_ticks! Setting default of %d.\n", 939 __FILE__, __LINE__, bce_tx_ticks, 940 DEFAULT_TX_TICKS); 941 sc->bce_tx_ticks = 942 DEFAULT_TX_TICKS; 943 } 944 945 /* 946 * Validate the RX trip point (i.e. the number of 947 * RX frames received before a status block update is 948 * generated and an interrupt is asserted. 949 */ 950 if (bce_rx_quick_cons_trip_int <= 100) { 951 sc->bce_rx_quick_cons_trip_int = 952 bce_rx_quick_cons_trip_int; 953 } else { 954 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 955 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 956 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 957 DEFAULT_RX_QUICK_CONS_TRIP_INT); 958 sc->bce_rx_quick_cons_trip_int = 959 DEFAULT_RX_QUICK_CONS_TRIP_INT; 960 } 961 962 if (bce_rx_quick_cons_trip <= 100) { 963 sc->bce_rx_quick_cons_trip = 964 bce_rx_quick_cons_trip; 965 } else { 966 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 967 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 968 __FILE__, __LINE__, bce_rx_quick_cons_trip, 969 DEFAULT_RX_QUICK_CONS_TRIP); 970 sc->bce_rx_quick_cons_trip = 971 DEFAULT_RX_QUICK_CONS_TRIP; 972 } 973 974 /* 975 * Validate the RX ticks count (i.e. the maximum amount 976 * of time to wait after the last RX frame has been 977 * received before a status block update is generated 978 * and an interrupt is asserted. 979 */ 980 if (bce_rx_ticks_int <= 100) { 981 sc->bce_rx_ticks_int = bce_rx_ticks_int; 982 } else { 983 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 984 "hw.bce.rx_ticks_int! Setting default of %d.\n", 985 __FILE__, __LINE__, bce_rx_ticks_int, 986 DEFAULT_RX_TICKS_INT); 987 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 988 } 989 990 if (bce_rx_ticks <= 100) { 991 sc->bce_rx_ticks = bce_rx_ticks; 992 } else { 993 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 994 "hw.bce.rx_ticks! Setting default of %d.\n", 995 __FILE__, __LINE__, bce_rx_ticks, 996 DEFAULT_RX_TICKS); 997 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 998 } 999 1000 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1001 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1002 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1003 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1004 __FILE__, __LINE__); 1005 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1006 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1007 } 1008 1009 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1010 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1011 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1012 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1013 __FILE__, __LINE__); 1014 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1015 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1016 } 1017 1018 } 1019 1020 1021 /****************************************************************************/ 1022 /* Device attach function. */ 1023 /* */ 1024 /* Allocates device resources, performs secondary chip identification, */ 1025 /* resets and initializes the hardware, and initializes driver instance */ 1026 /* variables. */ 1027 /* */ 1028 /* Returns: */ 1029 /* 0 on success, positive value on failure. */ 1030 /****************************************************************************/ 1031 static int 1032 bce_attach(device_t dev) 1033 { 1034 struct bce_softc *sc; 1035 struct ifnet *ifp; 1036 u32 val; 1037 int error, rid, rc = 0; 1038 1039 sc = device_get_softc(dev); 1040 sc->bce_dev = dev; 1041 1042 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1043 1044 sc->bce_unit = device_get_unit(dev); 1045 1046 /* Set initial device and PHY flags */ 1047 sc->bce_flags = 0; 1048 sc->bce_phy_flags = 0; 1049 1050 bce_set_tunables(sc); 1051 1052 pci_enable_busmaster(dev); 1053 1054 /* Allocate PCI memory resources. */ 1055 rid = PCIR_BAR(0); 1056 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1057 &rid, RF_ACTIVE); 1058 1059 if (sc->bce_res_mem == NULL) { 1060 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1061 __FILE__, __LINE__); 1062 rc = ENXIO; 1063 goto bce_attach_fail; 1064 } 1065 1066 /* Get various resource handles. */ 1067 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1068 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1069 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1070 1071 bce_probe_pci_caps(dev, sc); 1072 1073 rid = 1; 1074 #if 0 1075 /* Try allocating MSI-X interrupts. */ 1076 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1077 (bce_msi_enable >= 2) && 1078 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1079 &rid, RF_ACTIVE)) != NULL)) { 1080 1081 msi_needed = sc->bce_msi_count = 1; 1082 1083 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 1084 (sc->bce_msi_count != msi_needed)) { 1085 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1086 "Received = %d, error = %d\n", __FILE__, __LINE__, 1087 msi_needed, sc->bce_msi_count, error); 1088 sc->bce_msi_count = 0; 1089 pci_release_msi(dev); 1090 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1091 sc->bce_res_irq); 1092 sc->bce_res_irq = NULL; 1093 } else { 1094 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1095 __FUNCTION__); 1096 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1097 sc->bce_intr = bce_intr; 1098 } 1099 } 1100 #endif 1101 1102 /* Try allocating a MSI interrupt. */ 1103 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1104 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 1105 sc->bce_msi_count = 1; 1106 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 1107 BCE_PRINTF("%s(%d): MSI allocation failed! " 1108 "error = %d\n", __FILE__, __LINE__, error); 1109 sc->bce_msi_count = 0; 1110 pci_release_msi(dev); 1111 } else { 1112 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1113 "interrupt.\n", __FUNCTION__); 1114 sc->bce_flags |= BCE_USING_MSI_FLAG; 1115 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1116 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 1117 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1118 sc->bce_irq_rid = 1; 1119 sc->bce_intr = bce_intr; 1120 } 1121 } 1122 1123 /* Try allocating a legacy interrupt. */ 1124 if (sc->bce_msi_count == 0) { 1125 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1126 __FUNCTION__); 1127 rid = 0; 1128 sc->bce_intr = bce_intr; 1129 } 1130 1131 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1132 &rid, RF_SHAREABLE | RF_ACTIVE); 1133 1134 sc->bce_irq_rid = rid; 1135 1136 /* Report any IRQ allocation errors. */ 1137 if (sc->bce_res_irq == NULL) { 1138 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1139 __FILE__, __LINE__); 1140 rc = ENXIO; 1141 goto bce_attach_fail; 1142 } 1143 1144 /* Initialize mutex for the current device instance. */ 1145 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1146 1147 /* 1148 * Configure byte swap and enable indirect register access. 1149 * Rely on CPU to do target byte swapping on big endian systems. 1150 * Access to registers outside of PCI configurtion space are not 1151 * valid until this is done. 1152 */ 1153 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1154 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1155 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1156 1157 /* Save ASIC revsion info. */ 1158 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1159 1160 /* Weed out any non-production controller revisions. */ 1161 switch(BCE_CHIP_ID(sc)) { 1162 case BCE_CHIP_ID_5706_A0: 1163 case BCE_CHIP_ID_5706_A1: 1164 case BCE_CHIP_ID_5708_A0: 1165 case BCE_CHIP_ID_5708_B0: 1166 case BCE_CHIP_ID_5709_A0: 1167 case BCE_CHIP_ID_5709_B0: 1168 case BCE_CHIP_ID_5709_B1: 1169 case BCE_CHIP_ID_5709_B2: 1170 BCE_PRINTF("%s(%d): Unsupported controller " 1171 "revision (%c%d)!\n", __FILE__, __LINE__, 1172 (((pci_read_config(dev, PCIR_REVID, 4) & 1173 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1174 PCIR_REVID, 4) & 0xf)); 1175 rc = ENODEV; 1176 goto bce_attach_fail; 1177 } 1178 1179 /* 1180 * The embedded PCIe to PCI-X bridge (EPB) 1181 * in the 5708 cannot address memory above 1182 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1183 */ 1184 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1185 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1186 else 1187 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1188 1189 /* 1190 * Find the base address for shared memory access. 1191 * Newer versions of bootcode use a signature and offset 1192 * while older versions use a fixed address. 1193 */ 1194 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1195 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1196 /* Multi-port devices use different offsets in shared memory. */ 1197 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1198 (pci_get_function(sc->bce_dev) << 2)); 1199 else 1200 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1201 1202 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1203 __FUNCTION__, sc->bce_shmem_base); 1204 1205 /* Fetch the bootcode revision. */ 1206 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1207 for (int i = 0, j = 0; i < 3; i++) { 1208 u8 num; 1209 1210 num = (u8) (val >> (24 - (i * 8))); 1211 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1212 if (num >= k || !skip0 || k == 1) { 1213 sc->bce_bc_ver[j++] = (num / k) + '0'; 1214 skip0 = 0; 1215 } 1216 } 1217 1218 if (i != 2) 1219 sc->bce_bc_ver[j++] = '.'; 1220 } 1221 1222 /* Check if any management firwmare is enabled. */ 1223 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1224 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1225 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1226 1227 /* Allow time for firmware to enter the running state. */ 1228 for (int i = 0; i < 30; i++) { 1229 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1230 if (val & BCE_CONDITION_MFW_RUN_MASK) 1231 break; 1232 DELAY(10000); 1233 } 1234 1235 /* Check if management firmware is running. */ 1236 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1237 val &= BCE_CONDITION_MFW_RUN_MASK; 1238 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1239 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1240 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1241 int i = 0; 1242 1243 /* Read the management firmware version string. */ 1244 for (int j = 0; j < 3; j++) { 1245 val = bce_reg_rd_ind(sc, addr + j * 4); 1246 val = bswap32(val); 1247 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1248 i += 4; 1249 } 1250 } else { 1251 /* May cause firmware synchronization timeouts. */ 1252 BCE_PRINTF("%s(%d): Management firmware enabled " 1253 "but not running!\n", __FILE__, __LINE__); 1254 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1255 1256 /* ToDo: Any action the driver should take? */ 1257 } 1258 } 1259 1260 /* Get PCI bus information (speed and type). */ 1261 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1262 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1263 u32 clkreg; 1264 1265 sc->bce_flags |= BCE_PCIX_FLAG; 1266 1267 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1268 1269 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1270 switch (clkreg) { 1271 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1272 sc->bus_speed_mhz = 133; 1273 break; 1274 1275 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1276 sc->bus_speed_mhz = 100; 1277 break; 1278 1279 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1280 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1281 sc->bus_speed_mhz = 66; 1282 break; 1283 1284 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1285 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1286 sc->bus_speed_mhz = 50; 1287 break; 1288 1289 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1290 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1291 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1292 sc->bus_speed_mhz = 33; 1293 break; 1294 } 1295 } else { 1296 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1297 sc->bus_speed_mhz = 66; 1298 else 1299 sc->bus_speed_mhz = 33; 1300 } 1301 1302 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1303 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1304 1305 /* Reset controller and announce to bootcode that driver is present. */ 1306 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1307 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1308 __FILE__, __LINE__); 1309 rc = ENXIO; 1310 goto bce_attach_fail; 1311 } 1312 1313 /* Initialize the controller. */ 1314 if (bce_chipinit(sc)) { 1315 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1316 __FILE__, __LINE__); 1317 rc = ENXIO; 1318 goto bce_attach_fail; 1319 } 1320 1321 /* Perform NVRAM test. */ 1322 if (bce_nvram_test(sc)) { 1323 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1324 __FILE__, __LINE__); 1325 rc = ENXIO; 1326 goto bce_attach_fail; 1327 } 1328 1329 /* Fetch the permanent Ethernet MAC address. */ 1330 bce_get_mac_addr(sc); 1331 1332 /* 1333 * Trip points control how many BDs 1334 * should be ready before generating an 1335 * interrupt while ticks control how long 1336 * a BD can sit in the chain before 1337 * generating an interrupt. Set the default 1338 * values for the RX and TX chains. 1339 */ 1340 1341 /* Not used for L2. */ 1342 sc->bce_comp_prod_trip_int = 0; 1343 sc->bce_comp_prod_trip = 0; 1344 sc->bce_com_ticks_int = 0; 1345 sc->bce_com_ticks = 0; 1346 sc->bce_cmd_ticks_int = 0; 1347 sc->bce_cmd_ticks = 0; 1348 1349 /* Update statistics once every second. */ 1350 sc->bce_stats_ticks = 1000000 & 0xffff00; 1351 1352 /* Find the media type for the adapter. */ 1353 bce_get_media(sc); 1354 1355 /* Store data needed by PHY driver for backplane applications */ 1356 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1357 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1358 1359 /* Allocate DMA memory resources. */ 1360 if (bce_dma_alloc(dev)) { 1361 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1362 __FILE__, __LINE__); 1363 rc = ENXIO; 1364 goto bce_attach_fail; 1365 } 1366 1367 /* Allocate an ifnet structure. */ 1368 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1369 if (ifp == NULL) { 1370 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1371 __FILE__, __LINE__); 1372 rc = ENXIO; 1373 goto bce_attach_fail; 1374 } 1375 1376 /* Initialize the ifnet interface. */ 1377 ifp->if_softc = sc; 1378 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1379 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1380 ifp->if_ioctl = bce_ioctl; 1381 ifp->if_start = bce_start; 1382 ifp->if_init = bce_init; 1383 ifp->if_mtu = ETHERMTU; 1384 1385 if (bce_tso_enable) { 1386 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1387 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1388 IFCAP_VLAN_HWTSO; 1389 } else { 1390 ifp->if_hwassist = BCE_IF_HWASSIST; 1391 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1392 } 1393 1394 ifp->if_capenable = ifp->if_capabilities; 1395 1396 /* 1397 * Assume standard mbuf sizes for buffer allocation. 1398 * This may change later if the MTU size is set to 1399 * something other than 1500. 1400 */ 1401 bce_get_rx_buffer_sizes(sc, 1402 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1403 1404 /* Recalculate our buffer allocation sizes. */ 1405 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1406 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1407 IFQ_SET_READY(&ifp->if_snd); 1408 1409 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1410 ifp->if_baudrate = IF_Mbps(2500ULL); 1411 else 1412 ifp->if_baudrate = IF_Mbps(1000); 1413 1414 /* Handle any special PHY initialization for SerDes PHYs. */ 1415 bce_init_media(sc); 1416 1417 /* MII child bus by attaching the PHY. */ 1418 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1419 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1420 MII_OFFSET_ANY, MIIF_DOPAUSE); 1421 if (rc != 0) { 1422 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1423 __LINE__); 1424 goto bce_attach_fail; 1425 } 1426 1427 /* Attach to the Ethernet interface list. */ 1428 ether_ifattach(ifp, sc->eaddr); 1429 1430 #if __FreeBSD_version < 500000 1431 callout_init(&sc->bce_tick_callout); 1432 callout_init(&sc->bce_pulse_callout); 1433 #else 1434 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1435 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1436 #endif 1437 1438 /* Hookup IRQ last. */ 1439 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1440 NULL, bce_intr, sc, &sc->bce_intrhand); 1441 1442 if (rc) { 1443 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1444 __FILE__, __LINE__); 1445 bce_detach(dev); 1446 goto bce_attach_exit; 1447 } 1448 1449 /* 1450 * At this point we've acquired all the resources 1451 * we need to run so there's no turning back, we're 1452 * cleared for launch. 1453 */ 1454 1455 /* Print some important debugging info. */ 1456 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1457 1458 /* Add the supported sysctls to the kernel. */ 1459 bce_add_sysctls(sc); 1460 1461 BCE_LOCK(sc); 1462 1463 /* 1464 * The chip reset earlier notified the bootcode that 1465 * a driver is present. We now need to start our pulse 1466 * routine so that the bootcode is reminded that we're 1467 * still running. 1468 */ 1469 bce_pulse(sc); 1470 1471 bce_mgmt_init_locked(sc); 1472 BCE_UNLOCK(sc); 1473 1474 /* Finally, print some useful adapter info */ 1475 bce_print_adapter_info(sc); 1476 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1477 __FUNCTION__, sc); 1478 1479 goto bce_attach_exit; 1480 1481 bce_attach_fail: 1482 bce_release_resources(sc); 1483 1484 bce_attach_exit: 1485 1486 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1487 1488 return(rc); 1489 } 1490 1491 1492 /****************************************************************************/ 1493 /* Device detach function. */ 1494 /* */ 1495 /* Stops the controller, resets the controller, and releases resources. */ 1496 /* */ 1497 /* Returns: */ 1498 /* 0 on success, positive value on failure. */ 1499 /****************************************************************************/ 1500 static int 1501 bce_detach(device_t dev) 1502 { 1503 struct bce_softc *sc = device_get_softc(dev); 1504 struct ifnet *ifp; 1505 u32 msg; 1506 1507 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1508 1509 ifp = sc->bce_ifp; 1510 1511 /* Stop and reset the controller. */ 1512 BCE_LOCK(sc); 1513 1514 /* Stop the pulse so the bootcode can go to driver absent state. */ 1515 callout_stop(&sc->bce_pulse_callout); 1516 1517 bce_stop(sc); 1518 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1519 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1520 else 1521 msg = BCE_DRV_MSG_CODE_UNLOAD; 1522 bce_reset(sc, msg); 1523 1524 BCE_UNLOCK(sc); 1525 1526 ether_ifdetach(ifp); 1527 1528 /* If we have a child device on the MII bus remove it too. */ 1529 bus_generic_detach(dev); 1530 device_delete_child(dev, sc->bce_miibus); 1531 1532 /* Release all remaining resources. */ 1533 bce_release_resources(sc); 1534 1535 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1536 1537 return(0); 1538 } 1539 1540 1541 /****************************************************************************/ 1542 /* Device shutdown function. */ 1543 /* */ 1544 /* Stops and resets the controller. */ 1545 /* */ 1546 /* Returns: */ 1547 /* 0 on success, positive value on failure. */ 1548 /****************************************************************************/ 1549 static int 1550 bce_shutdown(device_t dev) 1551 { 1552 struct bce_softc *sc = device_get_softc(dev); 1553 u32 msg; 1554 1555 DBENTER(BCE_VERBOSE); 1556 1557 BCE_LOCK(sc); 1558 bce_stop(sc); 1559 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1560 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1561 else 1562 msg = BCE_DRV_MSG_CODE_UNLOAD; 1563 bce_reset(sc, msg); 1564 BCE_UNLOCK(sc); 1565 1566 DBEXIT(BCE_VERBOSE); 1567 1568 return (0); 1569 } 1570 1571 1572 #ifdef BCE_DEBUG 1573 /****************************************************************************/ 1574 /* Register read. */ 1575 /* */ 1576 /* Returns: */ 1577 /* The value of the register. */ 1578 /****************************************************************************/ 1579 static u32 1580 bce_reg_rd(struct bce_softc *sc, u32 offset) 1581 { 1582 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1583 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1584 __FUNCTION__, offset, val); 1585 return val; 1586 } 1587 1588 1589 /****************************************************************************/ 1590 /* Register write (16 bit). */ 1591 /* */ 1592 /* Returns: */ 1593 /* Nothing. */ 1594 /****************************************************************************/ 1595 static void 1596 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1597 { 1598 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1599 __FUNCTION__, offset, val); 1600 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1601 } 1602 1603 1604 /****************************************************************************/ 1605 /* Register write. */ 1606 /* */ 1607 /* Returns: */ 1608 /* Nothing. */ 1609 /****************************************************************************/ 1610 static void 1611 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1612 { 1613 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1614 __FUNCTION__, offset, val); 1615 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1616 } 1617 #endif 1618 1619 /****************************************************************************/ 1620 /* Indirect register read. */ 1621 /* */ 1622 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1623 /* configuration space. Using this mechanism avoids issues with posted */ 1624 /* reads but is much slower than memory-mapped I/O. */ 1625 /* */ 1626 /* Returns: */ 1627 /* The value of the register. */ 1628 /****************************************************************************/ 1629 static u32 1630 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1631 { 1632 device_t dev; 1633 dev = sc->bce_dev; 1634 1635 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1636 #ifdef BCE_DEBUG 1637 { 1638 u32 val; 1639 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1640 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1641 __FUNCTION__, offset, val); 1642 return val; 1643 } 1644 #else 1645 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1646 #endif 1647 } 1648 1649 1650 /****************************************************************************/ 1651 /* Indirect register write. */ 1652 /* */ 1653 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1654 /* configuration space. Using this mechanism avoids issues with posted */ 1655 /* writes but is muchh slower than memory-mapped I/O. */ 1656 /* */ 1657 /* Returns: */ 1658 /* Nothing. */ 1659 /****************************************************************************/ 1660 static void 1661 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1662 { 1663 device_t dev; 1664 dev = sc->bce_dev; 1665 1666 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1667 __FUNCTION__, offset, val); 1668 1669 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1670 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1671 } 1672 1673 1674 /****************************************************************************/ 1675 /* Shared memory write. */ 1676 /* */ 1677 /* Writes NetXtreme II shared memory region. */ 1678 /* */ 1679 /* Returns: */ 1680 /* Nothing. */ 1681 /****************************************************************************/ 1682 static void 1683 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1684 { 1685 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1686 "0x%08X\n", __FUNCTION__, val, offset); 1687 1688 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1689 } 1690 1691 1692 /****************************************************************************/ 1693 /* Shared memory read. */ 1694 /* */ 1695 /* Reads NetXtreme II shared memory region. */ 1696 /* */ 1697 /* Returns: */ 1698 /* The 32 bit value read. */ 1699 /****************************************************************************/ 1700 static u32 1701 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1702 { 1703 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1704 1705 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1706 "0x%08X\n", __FUNCTION__, val, offset); 1707 1708 return val; 1709 } 1710 1711 1712 #ifdef BCE_DEBUG 1713 /****************************************************************************/ 1714 /* Context memory read. */ 1715 /* */ 1716 /* The NetXtreme II controller uses context memory to track connection */ 1717 /* information for L2 and higher network protocols. */ 1718 /* */ 1719 /* Returns: */ 1720 /* The requested 32 bit value of context memory. */ 1721 /****************************************************************************/ 1722 static u32 1723 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1724 { 1725 u32 idx, offset, retry_cnt = 5, val; 1726 1727 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1728 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1729 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1730 1731 offset = ctx_offset + cid_addr; 1732 1733 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1734 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1735 1736 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1737 1738 for (idx = 0; idx < retry_cnt; idx++) { 1739 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1740 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1741 break; 1742 DELAY(5); 1743 } 1744 1745 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1746 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1747 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1748 __FILE__, __LINE__, cid_addr, ctx_offset); 1749 1750 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1751 } else { 1752 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1753 val = REG_RD(sc, BCE_CTX_DATA); 1754 } 1755 1756 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1757 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1758 1759 return(val); 1760 } 1761 #endif 1762 1763 1764 /****************************************************************************/ 1765 /* Context memory write. */ 1766 /* */ 1767 /* The NetXtreme II controller uses context memory to track connection */ 1768 /* information for L2 and higher network protocols. */ 1769 /* */ 1770 /* Returns: */ 1771 /* Nothing. */ 1772 /****************************************************************************/ 1773 static void 1774 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1775 { 1776 u32 idx, offset = ctx_offset + cid_addr; 1777 u32 val, retry_cnt = 5; 1778 1779 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1780 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1781 1782 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1783 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1784 __FUNCTION__, cid_addr)); 1785 1786 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1787 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1788 1789 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1790 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1791 1792 for (idx = 0; idx < retry_cnt; idx++) { 1793 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1794 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1795 break; 1796 DELAY(5); 1797 } 1798 1799 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1800 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1801 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1802 __FILE__, __LINE__, cid_addr, ctx_offset); 1803 1804 } else { 1805 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1806 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1807 } 1808 } 1809 1810 1811 /****************************************************************************/ 1812 /* PHY register read. */ 1813 /* */ 1814 /* Implements register reads on the MII bus. */ 1815 /* */ 1816 /* Returns: */ 1817 /* The value of the register. */ 1818 /****************************************************************************/ 1819 static int 1820 bce_miibus_read_reg(device_t dev, int phy, int reg) 1821 { 1822 struct bce_softc *sc; 1823 u32 val; 1824 int i; 1825 1826 sc = device_get_softc(dev); 1827 1828 /* Make sure we are accessing the correct PHY address. */ 1829 if (phy != sc->bce_phy_addr) { 1830 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1831 "for PHY read!\n", phy); 1832 return(0); 1833 } 1834 1835 /* 1836 * The 5709S PHY is an IEEE Clause 45 PHY 1837 * with special mappings to work with IEEE 1838 * Clause 22 register accesses. 1839 */ 1840 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1841 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1842 reg += 0x10; 1843 } 1844 1845 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1846 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1847 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1848 1849 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1850 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1851 1852 DELAY(40); 1853 } 1854 1855 1856 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1857 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1858 BCE_EMAC_MDIO_COMM_START_BUSY; 1859 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1860 1861 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1862 DELAY(10); 1863 1864 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1865 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1866 DELAY(5); 1867 1868 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1869 val &= BCE_EMAC_MDIO_COMM_DATA; 1870 1871 break; 1872 } 1873 } 1874 1875 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1876 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1877 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1878 val = 0x0; 1879 } else { 1880 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1881 } 1882 1883 1884 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1885 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1886 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1887 1888 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1889 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1890 1891 DELAY(40); 1892 } 1893 1894 DB_PRINT_PHY_REG(reg, val); 1895 return (val & 0xffff); 1896 1897 } 1898 1899 1900 /****************************************************************************/ 1901 /* PHY register write. */ 1902 /* */ 1903 /* Implements register writes on the MII bus. */ 1904 /* */ 1905 /* Returns: */ 1906 /* The value of the register. */ 1907 /****************************************************************************/ 1908 static int 1909 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1910 { 1911 struct bce_softc *sc; 1912 u32 val1; 1913 int i; 1914 1915 sc = device_get_softc(dev); 1916 1917 /* Make sure we are accessing the correct PHY address. */ 1918 if (phy != sc->bce_phy_addr) { 1919 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1920 "for PHY write!\n", phy); 1921 return(0); 1922 } 1923 1924 DB_PRINT_PHY_REG(reg, val); 1925 1926 /* 1927 * The 5709S PHY is an IEEE Clause 45 PHY 1928 * with special mappings to work with IEEE 1929 * Clause 22 register accesses. 1930 */ 1931 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1932 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1933 reg += 0x10; 1934 } 1935 1936 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1937 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1938 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1939 1940 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1941 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1942 1943 DELAY(40); 1944 } 1945 1946 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1947 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1948 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1949 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1950 1951 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1952 DELAY(10); 1953 1954 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1955 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1956 DELAY(5); 1957 break; 1958 } 1959 } 1960 1961 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1962 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1963 __FILE__, __LINE__); 1964 1965 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1966 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1967 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1968 1969 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1970 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1971 1972 DELAY(40); 1973 } 1974 1975 return 0; 1976 } 1977 1978 1979 /****************************************************************************/ 1980 /* MII bus status change. */ 1981 /* */ 1982 /* Called by the MII bus driver when the PHY establishes link to set the */ 1983 /* MAC interface registers. */ 1984 /* */ 1985 /* Returns: */ 1986 /* Nothing. */ 1987 /****************************************************************************/ 1988 static void 1989 bce_miibus_statchg(device_t dev) 1990 { 1991 struct bce_softc *sc; 1992 struct mii_data *mii; 1993 int val; 1994 1995 sc = device_get_softc(dev); 1996 1997 DBENTER(BCE_VERBOSE_PHY); 1998 1999 mii = device_get_softc(sc->bce_miibus); 2000 2001 val = REG_RD(sc, BCE_EMAC_MODE); 2002 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2003 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2004 BCE_EMAC_MODE_25G); 2005 2006 /* Set MII or GMII interface based on the PHY speed. */ 2007 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2008 case IFM_10_T: 2009 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2010 DBPRINT(sc, BCE_INFO_PHY, 2011 "Enabling 10Mb interface.\n"); 2012 val |= BCE_EMAC_MODE_PORT_MII_10; 2013 break; 2014 } 2015 /* fall-through */ 2016 case IFM_100_TX: 2017 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2018 val |= BCE_EMAC_MODE_PORT_MII; 2019 break; 2020 case IFM_2500_SX: 2021 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2022 val |= BCE_EMAC_MODE_25G; 2023 /* fall-through */ 2024 case IFM_1000_T: 2025 case IFM_1000_SX: 2026 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2027 val |= BCE_EMAC_MODE_PORT_GMII; 2028 break; 2029 default: 2030 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2031 "default GMII interface.\n"); 2032 val |= BCE_EMAC_MODE_PORT_GMII; 2033 } 2034 2035 /* Set half or full duplex based on PHY settings. */ 2036 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 2037 DBPRINT(sc, BCE_INFO_PHY, 2038 "Setting Half-Duplex interface.\n"); 2039 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2040 } else 2041 DBPRINT(sc, BCE_INFO_PHY, 2042 "Setting Full-Duplex interface.\n"); 2043 2044 REG_WR(sc, BCE_EMAC_MODE, val); 2045 2046 if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) { 2047 DBPRINT(sc, BCE_INFO_PHY, 2048 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2049 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2050 } else { 2051 DBPRINT(sc, BCE_INFO_PHY, 2052 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2053 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2054 } 2055 2056 if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) { 2057 DBPRINT(sc, BCE_INFO_PHY, 2058 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2059 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2060 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2061 } else { 2062 DBPRINT(sc, BCE_INFO_PHY, 2063 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2064 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2065 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2066 } 2067 2068 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2069 2070 DBEXIT(BCE_VERBOSE_PHY); 2071 } 2072 2073 2074 /****************************************************************************/ 2075 /* Acquire NVRAM lock. */ 2076 /* */ 2077 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2078 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2079 /* for use by the driver. */ 2080 /* */ 2081 /* Returns: */ 2082 /* 0 on success, positive value on failure. */ 2083 /****************************************************************************/ 2084 static int 2085 bce_acquire_nvram_lock(struct bce_softc *sc) 2086 { 2087 u32 val; 2088 int j, rc = 0; 2089 2090 DBENTER(BCE_VERBOSE_NVRAM); 2091 2092 /* Request access to the flash interface. */ 2093 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2094 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2095 val = REG_RD(sc, BCE_NVM_SW_ARB); 2096 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2097 break; 2098 2099 DELAY(5); 2100 } 2101 2102 if (j >= NVRAM_TIMEOUT_COUNT) { 2103 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2104 rc = EBUSY; 2105 } 2106 2107 DBEXIT(BCE_VERBOSE_NVRAM); 2108 return (rc); 2109 } 2110 2111 2112 /****************************************************************************/ 2113 /* Release NVRAM lock. */ 2114 /* */ 2115 /* When the caller is finished accessing NVRAM the lock must be released. */ 2116 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2117 /* for use by the driver. */ 2118 /* */ 2119 /* Returns: */ 2120 /* 0 on success, positive value on failure. */ 2121 /****************************************************************************/ 2122 static int 2123 bce_release_nvram_lock(struct bce_softc *sc) 2124 { 2125 u32 val; 2126 int j, rc = 0; 2127 2128 DBENTER(BCE_VERBOSE_NVRAM); 2129 2130 /* 2131 * Relinquish nvram interface. 2132 */ 2133 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2134 2135 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2136 val = REG_RD(sc, BCE_NVM_SW_ARB); 2137 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2138 break; 2139 2140 DELAY(5); 2141 } 2142 2143 if (j >= NVRAM_TIMEOUT_COUNT) { 2144 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2145 rc = EBUSY; 2146 } 2147 2148 DBEXIT(BCE_VERBOSE_NVRAM); 2149 return (rc); 2150 } 2151 2152 2153 #ifdef BCE_NVRAM_WRITE_SUPPORT 2154 /****************************************************************************/ 2155 /* Enable NVRAM write access. */ 2156 /* */ 2157 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2158 /* */ 2159 /* Returns: */ 2160 /* 0 on success, positive value on failure. */ 2161 /****************************************************************************/ 2162 static int 2163 bce_enable_nvram_write(struct bce_softc *sc) 2164 { 2165 u32 val; 2166 int rc = 0; 2167 2168 DBENTER(BCE_VERBOSE_NVRAM); 2169 2170 val = REG_RD(sc, BCE_MISC_CFG); 2171 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2172 2173 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2174 int j; 2175 2176 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2177 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2178 2179 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2180 DELAY(5); 2181 2182 val = REG_RD(sc, BCE_NVM_COMMAND); 2183 if (val & BCE_NVM_COMMAND_DONE) 2184 break; 2185 } 2186 2187 if (j >= NVRAM_TIMEOUT_COUNT) { 2188 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2189 rc = EBUSY; 2190 } 2191 } 2192 2193 DBENTER(BCE_VERBOSE_NVRAM); 2194 return (rc); 2195 } 2196 2197 2198 /****************************************************************************/ 2199 /* Disable NVRAM write access. */ 2200 /* */ 2201 /* When the caller is finished writing to NVRAM write access must be */ 2202 /* disabled. */ 2203 /* */ 2204 /* Returns: */ 2205 /* Nothing. */ 2206 /****************************************************************************/ 2207 static void 2208 bce_disable_nvram_write(struct bce_softc *sc) 2209 { 2210 u32 val; 2211 2212 DBENTER(BCE_VERBOSE_NVRAM); 2213 2214 val = REG_RD(sc, BCE_MISC_CFG); 2215 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2216 2217 DBEXIT(BCE_VERBOSE_NVRAM); 2218 2219 } 2220 #endif 2221 2222 2223 /****************************************************************************/ 2224 /* Enable NVRAM access. */ 2225 /* */ 2226 /* Before accessing NVRAM for read or write operations the caller must */ 2227 /* enabled NVRAM access. */ 2228 /* */ 2229 /* Returns: */ 2230 /* Nothing. */ 2231 /****************************************************************************/ 2232 static void 2233 bce_enable_nvram_access(struct bce_softc *sc) 2234 { 2235 u32 val; 2236 2237 DBENTER(BCE_VERBOSE_NVRAM); 2238 2239 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2240 /* Enable both bits, even on read. */ 2241 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2242 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2243 2244 DBEXIT(BCE_VERBOSE_NVRAM); 2245 } 2246 2247 2248 /****************************************************************************/ 2249 /* Disable NVRAM access. */ 2250 /* */ 2251 /* When the caller is finished accessing NVRAM access must be disabled. */ 2252 /* */ 2253 /* Returns: */ 2254 /* Nothing. */ 2255 /****************************************************************************/ 2256 static void 2257 bce_disable_nvram_access(struct bce_softc *sc) 2258 { 2259 u32 val; 2260 2261 DBENTER(BCE_VERBOSE_NVRAM); 2262 2263 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2264 2265 /* Disable both bits, even after read. */ 2266 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2267 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2268 2269 DBEXIT(BCE_VERBOSE_NVRAM); 2270 } 2271 2272 2273 #ifdef BCE_NVRAM_WRITE_SUPPORT 2274 /****************************************************************************/ 2275 /* Erase NVRAM page before writing. */ 2276 /* */ 2277 /* Non-buffered flash parts require that a page be erased before it is */ 2278 /* written. */ 2279 /* */ 2280 /* Returns: */ 2281 /* 0 on success, positive value on failure. */ 2282 /****************************************************************************/ 2283 static int 2284 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2285 { 2286 u32 cmd; 2287 int j, rc = 0; 2288 2289 DBENTER(BCE_VERBOSE_NVRAM); 2290 2291 /* Buffered flash doesn't require an erase. */ 2292 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2293 goto bce_nvram_erase_page_exit; 2294 2295 /* Build an erase command. */ 2296 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2297 BCE_NVM_COMMAND_DOIT; 2298 2299 /* 2300 * Clear the DONE bit separately, set the NVRAM adress to erase, 2301 * and issue the erase command. 2302 */ 2303 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2304 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2305 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2306 2307 /* Wait for completion. */ 2308 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2309 u32 val; 2310 2311 DELAY(5); 2312 2313 val = REG_RD(sc, BCE_NVM_COMMAND); 2314 if (val & BCE_NVM_COMMAND_DONE) 2315 break; 2316 } 2317 2318 if (j >= NVRAM_TIMEOUT_COUNT) { 2319 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2320 rc = EBUSY; 2321 } 2322 2323 bce_nvram_erase_page_exit: 2324 DBEXIT(BCE_VERBOSE_NVRAM); 2325 return (rc); 2326 } 2327 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2328 2329 2330 /****************************************************************************/ 2331 /* Read a dword (32 bits) from NVRAM. */ 2332 /* */ 2333 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2334 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2335 /* */ 2336 /* Returns: */ 2337 /* 0 on success and the 32 bit value read, positive value on failure. */ 2338 /****************************************************************************/ 2339 static int 2340 bce_nvram_read_dword(struct bce_softc *sc, 2341 u32 offset, u8 *ret_val, u32 cmd_flags) 2342 { 2343 u32 cmd; 2344 int i, rc = 0; 2345 2346 DBENTER(BCE_EXTREME_NVRAM); 2347 2348 /* Build the command word. */ 2349 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2350 2351 /* Calculate the offset for buffered flash if translation is used. */ 2352 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2353 offset = ((offset / sc->bce_flash_info->page_size) << 2354 sc->bce_flash_info->page_bits) + 2355 (offset % sc->bce_flash_info->page_size); 2356 } 2357 2358 /* 2359 * Clear the DONE bit separately, set the address to read, 2360 * and issue the read. 2361 */ 2362 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2363 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2364 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2365 2366 /* Wait for completion. */ 2367 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2368 u32 val; 2369 2370 DELAY(5); 2371 2372 val = REG_RD(sc, BCE_NVM_COMMAND); 2373 if (val & BCE_NVM_COMMAND_DONE) { 2374 val = REG_RD(sc, BCE_NVM_READ); 2375 2376 val = bce_be32toh(val); 2377 memcpy(ret_val, &val, 4); 2378 break; 2379 } 2380 } 2381 2382 /* Check for errors. */ 2383 if (i >= NVRAM_TIMEOUT_COUNT) { 2384 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2385 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2386 rc = EBUSY; 2387 } 2388 2389 DBEXIT(BCE_EXTREME_NVRAM); 2390 return(rc); 2391 } 2392 2393 2394 #ifdef BCE_NVRAM_WRITE_SUPPORT 2395 /****************************************************************************/ 2396 /* Write a dword (32 bits) to NVRAM. */ 2397 /* */ 2398 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2399 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2400 /* enabled NVRAM write access. */ 2401 /* */ 2402 /* Returns: */ 2403 /* 0 on success, positive value on failure. */ 2404 /****************************************************************************/ 2405 static int 2406 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2407 u32 cmd_flags) 2408 { 2409 u32 cmd, val32; 2410 int j, rc = 0; 2411 2412 DBENTER(BCE_VERBOSE_NVRAM); 2413 2414 /* Build the command word. */ 2415 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2416 2417 /* Calculate the offset for buffered flash if translation is used. */ 2418 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2419 offset = ((offset / sc->bce_flash_info->page_size) << 2420 sc->bce_flash_info->page_bits) + 2421 (offset % sc->bce_flash_info->page_size); 2422 } 2423 2424 /* 2425 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2426 * set the NVRAM address to write, and issue the write command 2427 */ 2428 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2429 memcpy(&val32, val, 4); 2430 val32 = htobe32(val32); 2431 REG_WR(sc, BCE_NVM_WRITE, val32); 2432 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2433 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2434 2435 /* Wait for completion. */ 2436 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2437 DELAY(5); 2438 2439 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2440 break; 2441 } 2442 if (j >= NVRAM_TIMEOUT_COUNT) { 2443 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2444 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2445 rc = EBUSY; 2446 } 2447 2448 DBEXIT(BCE_VERBOSE_NVRAM); 2449 return (rc); 2450 } 2451 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2452 2453 2454 /****************************************************************************/ 2455 /* Initialize NVRAM access. */ 2456 /* */ 2457 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2458 /* access that device. */ 2459 /* */ 2460 /* Returns: */ 2461 /* 0 on success, positive value on failure. */ 2462 /****************************************************************************/ 2463 static int 2464 bce_init_nvram(struct bce_softc *sc) 2465 { 2466 u32 val; 2467 int j, entry_count, rc = 0; 2468 struct flash_spec *flash; 2469 2470 DBENTER(BCE_VERBOSE_NVRAM); 2471 2472 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2473 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2474 sc->bce_flash_info = &flash_5709; 2475 goto bce_init_nvram_get_flash_size; 2476 } 2477 2478 /* Determine the selected interface. */ 2479 val = REG_RD(sc, BCE_NVM_CFG1); 2480 2481 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2482 2483 /* 2484 * Flash reconfiguration is required to support additional 2485 * NVRAM devices not directly supported in hardware. 2486 * Check if the flash interface was reconfigured 2487 * by the bootcode. 2488 */ 2489 2490 if (val & 0x40000000) { 2491 /* Flash interface reconfigured by bootcode. */ 2492 2493 DBPRINT(sc,BCE_INFO_LOAD, 2494 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2495 2496 for (j = 0, flash = &flash_table[0]; j < entry_count; 2497 j++, flash++) { 2498 if ((val & FLASH_BACKUP_STRAP_MASK) == 2499 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2500 sc->bce_flash_info = flash; 2501 break; 2502 } 2503 } 2504 } else { 2505 /* Flash interface not yet reconfigured. */ 2506 u32 mask; 2507 2508 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2509 __FUNCTION__); 2510 2511 if (val & (1 << 23)) 2512 mask = FLASH_BACKUP_STRAP_MASK; 2513 else 2514 mask = FLASH_STRAP_MASK; 2515 2516 /* Look for the matching NVRAM device configuration data. */ 2517 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2518 2519 /* Check if the device matches any of the known devices. */ 2520 if ((val & mask) == (flash->strapping & mask)) { 2521 /* Found a device match. */ 2522 sc->bce_flash_info = flash; 2523 2524 /* Request access to the flash interface. */ 2525 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2526 return rc; 2527 2528 /* Reconfigure the flash interface. */ 2529 bce_enable_nvram_access(sc); 2530 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2531 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2532 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2533 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2534 bce_disable_nvram_access(sc); 2535 bce_release_nvram_lock(sc); 2536 2537 break; 2538 } 2539 } 2540 } 2541 2542 /* Check if a matching device was found. */ 2543 if (j == entry_count) { 2544 sc->bce_flash_info = NULL; 2545 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2546 __FILE__, __LINE__); 2547 DBEXIT(BCE_VERBOSE_NVRAM); 2548 return (ENODEV); 2549 } 2550 2551 bce_init_nvram_get_flash_size: 2552 /* Write the flash config data to the shared memory interface. */ 2553 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2554 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2555 if (val) 2556 sc->bce_flash_size = val; 2557 else 2558 sc->bce_flash_size = sc->bce_flash_info->total_size; 2559 2560 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2561 __FUNCTION__, sc->bce_flash_info->name, 2562 sc->bce_flash_info->total_size); 2563 2564 DBEXIT(BCE_VERBOSE_NVRAM); 2565 return rc; 2566 } 2567 2568 2569 /****************************************************************************/ 2570 /* Read an arbitrary range of data from NVRAM. */ 2571 /* */ 2572 /* Prepares the NVRAM interface for access and reads the requested data */ 2573 /* into the supplied buffer. */ 2574 /* */ 2575 /* Returns: */ 2576 /* 0 on success and the data read, positive value on failure. */ 2577 /****************************************************************************/ 2578 static int 2579 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2580 int buf_size) 2581 { 2582 int rc = 0; 2583 u32 cmd_flags, offset32, len32, extra; 2584 2585 DBENTER(BCE_VERBOSE_NVRAM); 2586 2587 if (buf_size == 0) 2588 goto bce_nvram_read_exit; 2589 2590 /* Request access to the flash interface. */ 2591 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2592 goto bce_nvram_read_exit; 2593 2594 /* Enable access to flash interface */ 2595 bce_enable_nvram_access(sc); 2596 2597 len32 = buf_size; 2598 offset32 = offset; 2599 extra = 0; 2600 2601 cmd_flags = 0; 2602 2603 if (offset32 & 3) { 2604 u8 buf[4]; 2605 u32 pre_len; 2606 2607 offset32 &= ~3; 2608 pre_len = 4 - (offset & 3); 2609 2610 if (pre_len >= len32) { 2611 pre_len = len32; 2612 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2613 } 2614 else { 2615 cmd_flags = BCE_NVM_COMMAND_FIRST; 2616 } 2617 2618 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2619 2620 if (rc) 2621 return rc; 2622 2623 memcpy(ret_buf, buf + (offset & 3), pre_len); 2624 2625 offset32 += 4; 2626 ret_buf += pre_len; 2627 len32 -= pre_len; 2628 } 2629 2630 if (len32 & 3) { 2631 extra = 4 - (len32 & 3); 2632 len32 = (len32 + 4) & ~3; 2633 } 2634 2635 if (len32 == 4) { 2636 u8 buf[4]; 2637 2638 if (cmd_flags) 2639 cmd_flags = BCE_NVM_COMMAND_LAST; 2640 else 2641 cmd_flags = BCE_NVM_COMMAND_FIRST | 2642 BCE_NVM_COMMAND_LAST; 2643 2644 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2645 2646 memcpy(ret_buf, buf, 4 - extra); 2647 } 2648 else if (len32 > 0) { 2649 u8 buf[4]; 2650 2651 /* Read the first word. */ 2652 if (cmd_flags) 2653 cmd_flags = 0; 2654 else 2655 cmd_flags = BCE_NVM_COMMAND_FIRST; 2656 2657 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2658 2659 /* Advance to the next dword. */ 2660 offset32 += 4; 2661 ret_buf += 4; 2662 len32 -= 4; 2663 2664 while (len32 > 4 && rc == 0) { 2665 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2666 2667 /* Advance to the next dword. */ 2668 offset32 += 4; 2669 ret_buf += 4; 2670 len32 -= 4; 2671 } 2672 2673 if (rc) 2674 goto bce_nvram_read_locked_exit; 2675 2676 cmd_flags = BCE_NVM_COMMAND_LAST; 2677 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2678 2679 memcpy(ret_buf, buf, 4 - extra); 2680 } 2681 2682 bce_nvram_read_locked_exit: 2683 /* Disable access to flash interface and release the lock. */ 2684 bce_disable_nvram_access(sc); 2685 bce_release_nvram_lock(sc); 2686 2687 bce_nvram_read_exit: 2688 DBEXIT(BCE_VERBOSE_NVRAM); 2689 return rc; 2690 } 2691 2692 2693 #ifdef BCE_NVRAM_WRITE_SUPPORT 2694 /****************************************************************************/ 2695 /* Write an arbitrary range of data from NVRAM. */ 2696 /* */ 2697 /* Prepares the NVRAM interface for write access and writes the requested */ 2698 /* data from the supplied buffer. The caller is responsible for */ 2699 /* calculating any appropriate CRCs. */ 2700 /* */ 2701 /* Returns: */ 2702 /* 0 on success, positive value on failure. */ 2703 /****************************************************************************/ 2704 static int 2705 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2706 int buf_size) 2707 { 2708 u32 written, offset32, len32; 2709 u8 *buf, start[4], end[4]; 2710 int rc = 0; 2711 int align_start, align_end; 2712 2713 DBENTER(BCE_VERBOSE_NVRAM); 2714 2715 buf = data_buf; 2716 offset32 = offset; 2717 len32 = buf_size; 2718 align_start = align_end = 0; 2719 2720 if ((align_start = (offset32 & 3))) { 2721 offset32 &= ~3; 2722 len32 += align_start; 2723 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2724 goto bce_nvram_write_exit; 2725 } 2726 2727 if (len32 & 3) { 2728 if ((len32 > 4) || !align_start) { 2729 align_end = 4 - (len32 & 3); 2730 len32 += align_end; 2731 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2732 end, 4))) { 2733 goto bce_nvram_write_exit; 2734 } 2735 } 2736 } 2737 2738 if (align_start || align_end) { 2739 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2740 if (buf == 0) { 2741 rc = ENOMEM; 2742 goto bce_nvram_write_exit; 2743 } 2744 2745 if (align_start) { 2746 memcpy(buf, start, 4); 2747 } 2748 2749 if (align_end) { 2750 memcpy(buf + len32 - 4, end, 4); 2751 } 2752 memcpy(buf + align_start, data_buf, buf_size); 2753 } 2754 2755 written = 0; 2756 while ((written < len32) && (rc == 0)) { 2757 u32 page_start, page_end, data_start, data_end; 2758 u32 addr, cmd_flags; 2759 int i; 2760 u8 flash_buffer[264]; 2761 2762 /* Find the page_start addr */ 2763 page_start = offset32 + written; 2764 page_start -= (page_start % sc->bce_flash_info->page_size); 2765 /* Find the page_end addr */ 2766 page_end = page_start + sc->bce_flash_info->page_size; 2767 /* Find the data_start addr */ 2768 data_start = (written == 0) ? offset32 : page_start; 2769 /* Find the data_end addr */ 2770 data_end = (page_end > offset32 + len32) ? 2771 (offset32 + len32) : page_end; 2772 2773 /* Request access to the flash interface. */ 2774 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2775 goto bce_nvram_write_exit; 2776 2777 /* Enable access to flash interface */ 2778 bce_enable_nvram_access(sc); 2779 2780 cmd_flags = BCE_NVM_COMMAND_FIRST; 2781 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2782 int j; 2783 2784 /* Read the whole page into the buffer 2785 * (non-buffer flash only) */ 2786 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2787 if (j == (sc->bce_flash_info->page_size - 4)) { 2788 cmd_flags |= BCE_NVM_COMMAND_LAST; 2789 } 2790 rc = bce_nvram_read_dword(sc, 2791 page_start + j, 2792 &flash_buffer[j], 2793 cmd_flags); 2794 2795 if (rc) 2796 goto bce_nvram_write_locked_exit; 2797 2798 cmd_flags = 0; 2799 } 2800 } 2801 2802 /* Enable writes to flash interface (unlock write-protect) */ 2803 if ((rc = bce_enable_nvram_write(sc)) != 0) 2804 goto bce_nvram_write_locked_exit; 2805 2806 /* Erase the page */ 2807 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2808 goto bce_nvram_write_locked_exit; 2809 2810 /* Re-enable the write again for the actual write */ 2811 bce_enable_nvram_write(sc); 2812 2813 /* Loop to write back the buffer data from page_start to 2814 * data_start */ 2815 i = 0; 2816 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2817 for (addr = page_start; addr < data_start; 2818 addr += 4, i += 4) { 2819 2820 rc = bce_nvram_write_dword(sc, addr, 2821 &flash_buffer[i], cmd_flags); 2822 2823 if (rc != 0) 2824 goto bce_nvram_write_locked_exit; 2825 2826 cmd_flags = 0; 2827 } 2828 } 2829 2830 /* Loop to write the new data from data_start to data_end */ 2831 for (addr = data_start; addr < data_end; addr += 4, i++) { 2832 if ((addr == page_end - 4) || 2833 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2834 (addr == data_end - 4))) { 2835 2836 cmd_flags |= BCE_NVM_COMMAND_LAST; 2837 } 2838 rc = bce_nvram_write_dword(sc, addr, buf, 2839 cmd_flags); 2840 2841 if (rc != 0) 2842 goto bce_nvram_write_locked_exit; 2843 2844 cmd_flags = 0; 2845 buf += 4; 2846 } 2847 2848 /* Loop to write back the buffer data from data_end 2849 * to page_end */ 2850 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2851 for (addr = data_end; addr < page_end; 2852 addr += 4, i += 4) { 2853 2854 if (addr == page_end-4) { 2855 cmd_flags = BCE_NVM_COMMAND_LAST; 2856 } 2857 rc = bce_nvram_write_dword(sc, addr, 2858 &flash_buffer[i], cmd_flags); 2859 2860 if (rc != 0) 2861 goto bce_nvram_write_locked_exit; 2862 2863 cmd_flags = 0; 2864 } 2865 } 2866 2867 /* Disable writes to flash interface (lock write-protect) */ 2868 bce_disable_nvram_write(sc); 2869 2870 /* Disable access to flash interface */ 2871 bce_disable_nvram_access(sc); 2872 bce_release_nvram_lock(sc); 2873 2874 /* Increment written */ 2875 written += data_end - data_start; 2876 } 2877 2878 goto bce_nvram_write_exit; 2879 2880 bce_nvram_write_locked_exit: 2881 bce_disable_nvram_write(sc); 2882 bce_disable_nvram_access(sc); 2883 bce_release_nvram_lock(sc); 2884 2885 bce_nvram_write_exit: 2886 if (align_start || align_end) 2887 free(buf, M_DEVBUF); 2888 2889 DBEXIT(BCE_VERBOSE_NVRAM); 2890 return (rc); 2891 } 2892 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2893 2894 2895 /****************************************************************************/ 2896 /* Verifies that NVRAM is accessible and contains valid data. */ 2897 /* */ 2898 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2899 /* correct. */ 2900 /* */ 2901 /* Returns: */ 2902 /* 0 on success, positive value on failure. */ 2903 /****************************************************************************/ 2904 static int 2905 bce_nvram_test(struct bce_softc *sc) 2906 { 2907 u32 buf[BCE_NVRAM_SIZE / 4]; 2908 u8 *data = (u8 *) buf; 2909 int rc = 0; 2910 u32 magic, csum; 2911 2912 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2913 2914 /* 2915 * Check that the device NVRAM is valid by reading 2916 * the magic value at offset 0. 2917 */ 2918 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2919 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2920 __FILE__, __LINE__); 2921 goto bce_nvram_test_exit; 2922 } 2923 2924 /* 2925 * Verify that offset 0 of the NVRAM contains 2926 * a valid magic number. 2927 */ 2928 magic = bce_be32toh(buf[0]); 2929 if (magic != BCE_NVRAM_MAGIC) { 2930 rc = ENODEV; 2931 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2932 "Expected: 0x%08X, Found: 0x%08X\n", 2933 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2934 goto bce_nvram_test_exit; 2935 } 2936 2937 /* 2938 * Verify that the device NVRAM includes valid 2939 * configuration data. 2940 */ 2941 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2942 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2943 "Information from NVRAM!\n", __FILE__, __LINE__); 2944 goto bce_nvram_test_exit; 2945 } 2946 2947 csum = ether_crc32_le(data, 0x100); 2948 if (csum != BCE_CRC32_RESIDUAL) { 2949 rc = ENODEV; 2950 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2951 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2952 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2953 goto bce_nvram_test_exit; 2954 } 2955 2956 csum = ether_crc32_le(data + 0x100, 0x100); 2957 if (csum != BCE_CRC32_RESIDUAL) { 2958 rc = ENODEV; 2959 BCE_PRINTF("%s(%d): Invalid feature configuration " 2960 "information NVRAM CRC! Expected: 0x%08X, " 2961 "Found: 08%08X\n", __FILE__, __LINE__, 2962 BCE_CRC32_RESIDUAL, csum); 2963 } 2964 2965 bce_nvram_test_exit: 2966 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2967 return rc; 2968 } 2969 2970 2971 /****************************************************************************/ 2972 /* Calculates the size of the buffers to allocate based on the MTU. */ 2973 /* */ 2974 /* Returns: */ 2975 /* Nothing. */ 2976 /****************************************************************************/ 2977 static void 2978 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 2979 { 2980 DBENTER(BCE_VERBOSE_LOAD); 2981 2982 /* Use a single allocation type when header splitting enabled. */ 2983 if (bce_hdr_split == TRUE) { 2984 sc->rx_bd_mbuf_alloc_size = MHLEN; 2985 /* Make sure offset is 16 byte aligned for hardware. */ 2986 sc->rx_bd_mbuf_align_pad = 2987 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 2988 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 2989 sc->rx_bd_mbuf_align_pad; 2990 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 2991 } else { 2992 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2993 ETHER_CRC_LEN) > MCLBYTES) { 2994 /* Setup for jumbo RX buffer allocations. */ 2995 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 2996 sc->rx_bd_mbuf_align_pad = 2997 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 2998 sc->rx_bd_mbuf_data_len = 2999 sc->rx_bd_mbuf_alloc_size - 3000 sc->rx_bd_mbuf_align_pad; 3001 } else { 3002 /* Setup for standard RX buffer allocations. */ 3003 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3004 sc->rx_bd_mbuf_align_pad = 3005 roundup2(MCLBYTES, 16) - MCLBYTES; 3006 sc->rx_bd_mbuf_data_len = 3007 sc->rx_bd_mbuf_alloc_size - 3008 sc->rx_bd_mbuf_align_pad; 3009 } 3010 } 3011 3012 // DBPRINT(sc, BCE_INFO_LOAD, 3013 DBPRINT(sc, BCE_WARN, 3014 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3015 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3016 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3017 sc->rx_bd_mbuf_align_pad); 3018 3019 DBEXIT(BCE_VERBOSE_LOAD); 3020 3021 } 3022 3023 /****************************************************************************/ 3024 /* Identifies the current media type of the controller and sets the PHY */ 3025 /* address. */ 3026 /* */ 3027 /* Returns: */ 3028 /* Nothing. */ 3029 /****************************************************************************/ 3030 static void 3031 bce_get_media(struct bce_softc *sc) 3032 { 3033 u32 val; 3034 3035 DBENTER(BCE_VERBOSE_PHY); 3036 3037 /* Assume PHY address for copper controllers. */ 3038 sc->bce_phy_addr = 1; 3039 3040 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3041 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3042 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3043 u32 strap; 3044 3045 /* 3046 * The BCM5709S is software configurable 3047 * for Copper or SerDes operation. 3048 */ 3049 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3050 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3051 "for copper.\n"); 3052 goto bce_get_media_exit; 3053 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3054 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3055 "for dual media.\n"); 3056 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3057 goto bce_get_media_exit; 3058 } 3059 3060 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3061 strap = (val & 3062 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3063 else 3064 strap = (val & 3065 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3066 3067 if (pci_get_function(sc->bce_dev) == 0) { 3068 switch (strap) { 3069 case 0x4: 3070 case 0x5: 3071 case 0x6: 3072 DBPRINT(sc, BCE_INFO_LOAD, 3073 "BCM5709 s/w configured for SerDes.\n"); 3074 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3075 break; 3076 default: 3077 DBPRINT(sc, BCE_INFO_LOAD, 3078 "BCM5709 s/w configured for Copper.\n"); 3079 break; 3080 } 3081 } else { 3082 switch (strap) { 3083 case 0x1: 3084 case 0x2: 3085 case 0x4: 3086 DBPRINT(sc, BCE_INFO_LOAD, 3087 "BCM5709 s/w configured for SerDes.\n"); 3088 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3089 break; 3090 default: 3091 DBPRINT(sc, BCE_INFO_LOAD, 3092 "BCM5709 s/w configured for Copper.\n"); 3093 break; 3094 } 3095 } 3096 3097 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3098 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3099 3100 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3101 3102 sc->bce_flags |= BCE_NO_WOL_FLAG; 3103 3104 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3105 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3106 3107 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3108 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3109 sc->bce_phy_addr = 2; 3110 3111 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3112 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3113 sc->bce_phy_flags |= 3114 BCE_PHY_2_5G_CAPABLE_FLAG; 3115 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3116 "capable adapter\n"); 3117 } 3118 } 3119 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3120 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3121 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3122 3123 bce_get_media_exit: 3124 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3125 "Using PHY address %d.\n", sc->bce_phy_addr); 3126 3127 DBEXIT(BCE_VERBOSE_PHY); 3128 } 3129 3130 3131 /****************************************************************************/ 3132 /* Performs PHY initialization required before MII drivers access the */ 3133 /* device. */ 3134 /* */ 3135 /* Returns: */ 3136 /* Nothing. */ 3137 /****************************************************************************/ 3138 static void 3139 bce_init_media(struct bce_softc *sc) 3140 { 3141 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 3142 /* 3143 * Configure 5709S/5716S PHYs to use traditional IEEE 3144 * Clause 22 method. Otherwise we have no way to attach 3145 * the PHY in mii(4) layer. PHY specific configuration 3146 * is done in mii layer. 3147 */ 3148 3149 /* Select auto-negotiation MMD of the PHY. */ 3150 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3151 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3152 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3153 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3154 3155 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3156 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3157 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3158 } 3159 } 3160 3161 3162 /****************************************************************************/ 3163 /* Free any DMA memory owned by the driver. */ 3164 /* */ 3165 /* Scans through each data structre that requires DMA memory and frees */ 3166 /* the memory if allocated. */ 3167 /* */ 3168 /* Returns: */ 3169 /* Nothing. */ 3170 /****************************************************************************/ 3171 static void 3172 bce_dma_free(struct bce_softc *sc) 3173 { 3174 int i; 3175 3176 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3177 3178 /* Free, unmap, and destroy the status block. */ 3179 if (sc->status_block != NULL) { 3180 bus_dmamem_free( 3181 sc->status_tag, 3182 sc->status_block, 3183 sc->status_map); 3184 sc->status_block = NULL; 3185 } 3186 3187 if (sc->status_map != NULL) { 3188 bus_dmamap_unload( 3189 sc->status_tag, 3190 sc->status_map); 3191 bus_dmamap_destroy(sc->status_tag, 3192 sc->status_map); 3193 sc->status_map = NULL; 3194 } 3195 3196 if (sc->status_tag != NULL) { 3197 bus_dma_tag_destroy(sc->status_tag); 3198 sc->status_tag = NULL; 3199 } 3200 3201 3202 /* Free, unmap, and destroy the statistics block. */ 3203 if (sc->stats_block != NULL) { 3204 bus_dmamem_free( 3205 sc->stats_tag, 3206 sc->stats_block, 3207 sc->stats_map); 3208 sc->stats_block = NULL; 3209 } 3210 3211 if (sc->stats_map != NULL) { 3212 bus_dmamap_unload( 3213 sc->stats_tag, 3214 sc->stats_map); 3215 bus_dmamap_destroy(sc->stats_tag, 3216 sc->stats_map); 3217 sc->stats_map = NULL; 3218 } 3219 3220 if (sc->stats_tag != NULL) { 3221 bus_dma_tag_destroy(sc->stats_tag); 3222 sc->stats_tag = NULL; 3223 } 3224 3225 3226 /* Free, unmap and destroy all context memory pages. */ 3227 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3228 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3229 for (i = 0; i < sc->ctx_pages; i++ ) { 3230 if (sc->ctx_block[i] != NULL) { 3231 bus_dmamem_free( 3232 sc->ctx_tag, 3233 sc->ctx_block[i], 3234 sc->ctx_map[i]); 3235 sc->ctx_block[i] = NULL; 3236 } 3237 3238 if (sc->ctx_map[i] != NULL) { 3239 bus_dmamap_unload( 3240 sc->ctx_tag, 3241 sc->ctx_map[i]); 3242 bus_dmamap_destroy( 3243 sc->ctx_tag, 3244 sc->ctx_map[i]); 3245 sc->ctx_map[i] = NULL; 3246 } 3247 } 3248 3249 /* Destroy the context memory tag. */ 3250 if (sc->ctx_tag != NULL) { 3251 bus_dma_tag_destroy(sc->ctx_tag); 3252 sc->ctx_tag = NULL; 3253 } 3254 } 3255 3256 3257 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3258 for (i = 0; i < sc->tx_pages; i++ ) { 3259 if (sc->tx_bd_chain[i] != NULL) { 3260 bus_dmamem_free( 3261 sc->tx_bd_chain_tag, 3262 sc->tx_bd_chain[i], 3263 sc->tx_bd_chain_map[i]); 3264 sc->tx_bd_chain[i] = NULL; 3265 } 3266 3267 if (sc->tx_bd_chain_map[i] != NULL) { 3268 bus_dmamap_unload( 3269 sc->tx_bd_chain_tag, 3270 sc->tx_bd_chain_map[i]); 3271 bus_dmamap_destroy( 3272 sc->tx_bd_chain_tag, 3273 sc->tx_bd_chain_map[i]); 3274 sc->tx_bd_chain_map[i] = NULL; 3275 } 3276 } 3277 3278 /* Destroy the TX buffer descriptor tag. */ 3279 if (sc->tx_bd_chain_tag != NULL) { 3280 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3281 sc->tx_bd_chain_tag = NULL; 3282 } 3283 3284 3285 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3286 for (i = 0; i < sc->rx_pages; i++ ) { 3287 if (sc->rx_bd_chain[i] != NULL) { 3288 bus_dmamem_free( 3289 sc->rx_bd_chain_tag, 3290 sc->rx_bd_chain[i], 3291 sc->rx_bd_chain_map[i]); 3292 sc->rx_bd_chain[i] = NULL; 3293 } 3294 3295 if (sc->rx_bd_chain_map[i] != NULL) { 3296 bus_dmamap_unload( 3297 sc->rx_bd_chain_tag, 3298 sc->rx_bd_chain_map[i]); 3299 bus_dmamap_destroy( 3300 sc->rx_bd_chain_tag, 3301 sc->rx_bd_chain_map[i]); 3302 sc->rx_bd_chain_map[i] = NULL; 3303 } 3304 } 3305 3306 /* Destroy the RX buffer descriptor tag. */ 3307 if (sc->rx_bd_chain_tag != NULL) { 3308 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3309 sc->rx_bd_chain_tag = NULL; 3310 } 3311 3312 3313 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3314 if (bce_hdr_split == TRUE) { 3315 for (i = 0; i < sc->pg_pages; i++ ) { 3316 if (sc->pg_bd_chain[i] != NULL) { 3317 bus_dmamem_free( 3318 sc->pg_bd_chain_tag, 3319 sc->pg_bd_chain[i], 3320 sc->pg_bd_chain_map[i]); 3321 sc->pg_bd_chain[i] = NULL; 3322 } 3323 3324 if (sc->pg_bd_chain_map[i] != NULL) { 3325 bus_dmamap_unload( 3326 sc->pg_bd_chain_tag, 3327 sc->pg_bd_chain_map[i]); 3328 bus_dmamap_destroy( 3329 sc->pg_bd_chain_tag, 3330 sc->pg_bd_chain_map[i]); 3331 sc->pg_bd_chain_map[i] = NULL; 3332 } 3333 } 3334 3335 /* Destroy the page buffer descriptor tag. */ 3336 if (sc->pg_bd_chain_tag != NULL) { 3337 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3338 sc->pg_bd_chain_tag = NULL; 3339 } 3340 } 3341 3342 3343 /* Unload and destroy the TX mbuf maps. */ 3344 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3345 if (sc->tx_mbuf_map[i] != NULL) { 3346 bus_dmamap_unload(sc->tx_mbuf_tag, 3347 sc->tx_mbuf_map[i]); 3348 bus_dmamap_destroy(sc->tx_mbuf_tag, 3349 sc->tx_mbuf_map[i]); 3350 sc->tx_mbuf_map[i] = NULL; 3351 } 3352 } 3353 3354 /* Destroy the TX mbuf tag. */ 3355 if (sc->tx_mbuf_tag != NULL) { 3356 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3357 sc->tx_mbuf_tag = NULL; 3358 } 3359 3360 /* Unload and destroy the RX mbuf maps. */ 3361 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3362 if (sc->rx_mbuf_map[i] != NULL) { 3363 bus_dmamap_unload(sc->rx_mbuf_tag, 3364 sc->rx_mbuf_map[i]); 3365 bus_dmamap_destroy(sc->rx_mbuf_tag, 3366 sc->rx_mbuf_map[i]); 3367 sc->rx_mbuf_map[i] = NULL; 3368 } 3369 } 3370 3371 /* Destroy the RX mbuf tag. */ 3372 if (sc->rx_mbuf_tag != NULL) { 3373 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3374 sc->rx_mbuf_tag = NULL; 3375 } 3376 3377 /* Unload and destroy the page mbuf maps. */ 3378 if (bce_hdr_split == TRUE) { 3379 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3380 if (sc->pg_mbuf_map[i] != NULL) { 3381 bus_dmamap_unload(sc->pg_mbuf_tag, 3382 sc->pg_mbuf_map[i]); 3383 bus_dmamap_destroy(sc->pg_mbuf_tag, 3384 sc->pg_mbuf_map[i]); 3385 sc->pg_mbuf_map[i] = NULL; 3386 } 3387 } 3388 3389 /* Destroy the page mbuf tag. */ 3390 if (sc->pg_mbuf_tag != NULL) { 3391 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3392 sc->pg_mbuf_tag = NULL; 3393 } 3394 } 3395 3396 /* Destroy the parent tag */ 3397 if (sc->parent_tag != NULL) { 3398 bus_dma_tag_destroy(sc->parent_tag); 3399 sc->parent_tag = NULL; 3400 } 3401 3402 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3403 } 3404 3405 3406 /****************************************************************************/ 3407 /* Get DMA memory from the OS. */ 3408 /* */ 3409 /* Validates that the OS has provided DMA buffers in response to a */ 3410 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3411 /* When the callback is used the OS will return 0 for the mapping function */ 3412 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3413 /* failures back to the caller. */ 3414 /* */ 3415 /* Returns: */ 3416 /* Nothing. */ 3417 /****************************************************************************/ 3418 static void 3419 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3420 { 3421 bus_addr_t *busaddr = arg; 3422 3423 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3424 __FUNCTION__, nseg)); 3425 /* Simulate a mapping failure. */ 3426 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3427 error = ENOMEM); 3428 3429 /* ToDo: How to increment debug sim_count variable here? */ 3430 3431 /* Check for an error and signal the caller that an error occurred. */ 3432 if (error) { 3433 *busaddr = 0; 3434 } else { 3435 *busaddr = segs->ds_addr; 3436 } 3437 3438 return; 3439 } 3440 3441 3442 /****************************************************************************/ 3443 /* Allocate any DMA memory needed by the driver. */ 3444 /* */ 3445 /* Allocates DMA memory needed for the various global structures needed by */ 3446 /* hardware. */ 3447 /* */ 3448 /* Memory alignment requirements: */ 3449 /* +-----------------+----------+----------+----------+----------+ */ 3450 /* | | 5706 | 5708 | 5709 | 5716 | */ 3451 /* +-----------------+----------+----------+----------+----------+ */ 3452 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3453 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3454 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3455 /* |PG Buffers | none | none | none | none | */ 3456 /* |TX Buffers | none | none | none | none | */ 3457 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3458 /* |Context Memory | | | | | */ 3459 /* +-----------------+----------+----------+----------+----------+ */ 3460 /* */ 3461 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3462 /* */ 3463 /* Returns: */ 3464 /* 0 for success, positive value for failure. */ 3465 /****************************************************************************/ 3466 static int 3467 bce_dma_alloc(device_t dev) 3468 { 3469 struct bce_softc *sc; 3470 int i, error, rc = 0; 3471 bus_size_t max_size, max_seg_size; 3472 int max_segments; 3473 3474 sc = device_get_softc(dev); 3475 3476 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3477 3478 /* 3479 * Allocate the parent bus DMA tag appropriate for PCI. 3480 */ 3481 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3482 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3483 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3484 &sc->parent_tag)) { 3485 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3486 __FILE__, __LINE__); 3487 rc = ENOMEM; 3488 goto bce_dma_alloc_exit; 3489 } 3490 3491 /* 3492 * Create a DMA tag for the status block, allocate and clear the 3493 * memory, map the memory into DMA space, and fetch the physical 3494 * address of the block. 3495 */ 3496 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3497 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3498 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3499 0, NULL, NULL, &sc->status_tag)) { 3500 BCE_PRINTF("%s(%d): Could not allocate status block " 3501 "DMA tag!\n", __FILE__, __LINE__); 3502 rc = ENOMEM; 3503 goto bce_dma_alloc_exit; 3504 } 3505 3506 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3507 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3508 &sc->status_map)) { 3509 BCE_PRINTF("%s(%d): Could not allocate status block " 3510 "DMA memory!\n", __FILE__, __LINE__); 3511 rc = ENOMEM; 3512 goto bce_dma_alloc_exit; 3513 } 3514 3515 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3516 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3517 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3518 3519 if (error) { 3520 BCE_PRINTF("%s(%d): Could not map status block " 3521 "DMA memory!\n", __FILE__, __LINE__); 3522 rc = ENOMEM; 3523 goto bce_dma_alloc_exit; 3524 } 3525 3526 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3527 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3528 3529 /* 3530 * Create a DMA tag for the statistics block, allocate and clear the 3531 * memory, map the memory into DMA space, and fetch the physical 3532 * address of the block. 3533 */ 3534 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3535 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3536 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3537 0, NULL, NULL, &sc->stats_tag)) { 3538 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3539 "DMA tag!\n", __FILE__, __LINE__); 3540 rc = ENOMEM; 3541 goto bce_dma_alloc_exit; 3542 } 3543 3544 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3545 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3546 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3547 "DMA memory!\n", __FILE__, __LINE__); 3548 rc = ENOMEM; 3549 goto bce_dma_alloc_exit; 3550 } 3551 3552 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3553 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3554 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3555 3556 if(error) { 3557 BCE_PRINTF("%s(%d): Could not map statistics block " 3558 "DMA memory!\n", __FILE__, __LINE__); 3559 rc = ENOMEM; 3560 goto bce_dma_alloc_exit; 3561 } 3562 3563 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3564 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3565 3566 /* BCM5709 uses host memory as cache for context memory. */ 3567 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3568 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3569 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3570 if (sc->ctx_pages == 0) 3571 sc->ctx_pages = 1; 3572 3573 DBRUNIF((sc->ctx_pages > 512), 3574 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3575 __FILE__, __LINE__, sc->ctx_pages)); 3576 3577 /* 3578 * Create a DMA tag for the context pages, 3579 * allocate and clear the memory, map the 3580 * memory into DMA space, and fetch the 3581 * physical address of the block. 3582 */ 3583 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3584 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3585 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3586 0, NULL, NULL, &sc->ctx_tag)) { 3587 BCE_PRINTF("%s(%d): Could not allocate CTX " 3588 "DMA tag!\n", __FILE__, __LINE__); 3589 rc = ENOMEM; 3590 goto bce_dma_alloc_exit; 3591 } 3592 3593 for (i = 0; i < sc->ctx_pages; i++) { 3594 3595 if(bus_dmamem_alloc(sc->ctx_tag, 3596 (void **)&sc->ctx_block[i], 3597 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3598 &sc->ctx_map[i])) { 3599 BCE_PRINTF("%s(%d): Could not allocate CTX " 3600 "DMA memory!\n", __FILE__, __LINE__); 3601 rc = ENOMEM; 3602 goto bce_dma_alloc_exit; 3603 } 3604 3605 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3606 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3607 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3608 3609 if (error) { 3610 BCE_PRINTF("%s(%d): Could not map CTX " 3611 "DMA memory!\n", __FILE__, __LINE__); 3612 rc = ENOMEM; 3613 goto bce_dma_alloc_exit; 3614 } 3615 3616 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3617 "= 0x%jX\n", __FUNCTION__, i, 3618 (uintmax_t) sc->ctx_paddr[i]); 3619 } 3620 } 3621 3622 /* 3623 * Create a DMA tag for the TX buffer descriptor chain, 3624 * allocate and clear the memory, and fetch the 3625 * physical address of the block. 3626 */ 3627 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3628 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3629 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3630 NULL, NULL, &sc->tx_bd_chain_tag)) { 3631 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3632 "chain DMA tag!\n", __FILE__, __LINE__); 3633 rc = ENOMEM; 3634 goto bce_dma_alloc_exit; 3635 } 3636 3637 for (i = 0; i < sc->tx_pages; i++) { 3638 3639 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3640 (void **)&sc->tx_bd_chain[i], 3641 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3642 &sc->tx_bd_chain_map[i])) { 3643 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3644 "chain DMA memory!\n", __FILE__, __LINE__); 3645 rc = ENOMEM; 3646 goto bce_dma_alloc_exit; 3647 } 3648 3649 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3650 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3651 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3652 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3653 3654 if (error) { 3655 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3656 "chain DMA memory!\n", __FILE__, __LINE__); 3657 rc = ENOMEM; 3658 goto bce_dma_alloc_exit; 3659 } 3660 3661 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3662 "0x%jX\n", __FUNCTION__, i, 3663 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3664 } 3665 3666 /* Check the required size before mapping to conserve resources. */ 3667 if (bce_tso_enable) { 3668 max_size = BCE_TSO_MAX_SIZE; 3669 max_segments = BCE_MAX_SEGMENTS; 3670 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3671 } else { 3672 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3673 max_segments = BCE_MAX_SEGMENTS; 3674 max_seg_size = MCLBYTES; 3675 } 3676 3677 /* Create a DMA tag for TX mbufs. */ 3678 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3679 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3680 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3681 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3682 __FILE__, __LINE__); 3683 rc = ENOMEM; 3684 goto bce_dma_alloc_exit; 3685 } 3686 3687 /* Create DMA maps for the TX mbufs clusters. */ 3688 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3689 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3690 &sc->tx_mbuf_map[i])) { 3691 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3692 "map!\n", __FILE__, __LINE__); 3693 rc = ENOMEM; 3694 goto bce_dma_alloc_exit; 3695 } 3696 } 3697 3698 /* 3699 * Create a DMA tag for the RX buffer descriptor chain, 3700 * allocate and clear the memory, and fetch the physical 3701 * address of the blocks. 3702 */ 3703 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3704 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3705 sc->max_bus_addr, NULL, NULL, 3706 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3707 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3708 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3709 "DMA tag!\n", __FILE__, __LINE__); 3710 rc = ENOMEM; 3711 goto bce_dma_alloc_exit; 3712 } 3713 3714 for (i = 0; i < sc->rx_pages; i++) { 3715 3716 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3717 (void **)&sc->rx_bd_chain[i], 3718 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3719 &sc->rx_bd_chain_map[i])) { 3720 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3721 "chain DMA memory!\n", __FILE__, __LINE__); 3722 rc = ENOMEM; 3723 goto bce_dma_alloc_exit; 3724 } 3725 3726 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3727 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3728 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3729 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3730 3731 if (error) { 3732 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3733 "chain DMA memory!\n", __FILE__, __LINE__); 3734 rc = ENOMEM; 3735 goto bce_dma_alloc_exit; 3736 } 3737 3738 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3739 "0x%jX\n", __FUNCTION__, i, 3740 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3741 } 3742 3743 /* 3744 * Create a DMA tag for RX mbufs. 3745 */ 3746 if (bce_hdr_split == TRUE) 3747 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3748 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3749 else 3750 max_size = max_seg_size = MJUM9BYTES; 3751 max_segments = 1; 3752 3753 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3754 "(max size = 0x%jX max segments = %d, max segment " 3755 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, 3756 max_segments, (uintmax_t) max_seg_size); 3757 3758 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3759 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3760 max_size, max_segments, max_seg_size, 0, NULL, NULL, 3761 &sc->rx_mbuf_tag)) { 3762 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3763 __FILE__, __LINE__); 3764 rc = ENOMEM; 3765 goto bce_dma_alloc_exit; 3766 } 3767 3768 /* Create DMA maps for the RX mbuf clusters. */ 3769 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3770 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3771 &sc->rx_mbuf_map[i])) { 3772 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3773 "DMA map!\n", __FILE__, __LINE__); 3774 rc = ENOMEM; 3775 goto bce_dma_alloc_exit; 3776 } 3777 } 3778 3779 if (bce_hdr_split == TRUE) { 3780 /* 3781 * Create a DMA tag for the page buffer descriptor chain, 3782 * allocate and clear the memory, and fetch the physical 3783 * address of the blocks. 3784 */ 3785 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3786 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3787 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3788 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3789 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3790 "chain DMA tag!\n", __FILE__, __LINE__); 3791 rc = ENOMEM; 3792 goto bce_dma_alloc_exit; 3793 } 3794 3795 for (i = 0; i < sc->pg_pages; i++) { 3796 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3797 (void **)&sc->pg_bd_chain[i], 3798 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3799 &sc->pg_bd_chain_map[i])) { 3800 BCE_PRINTF("%s(%d): Could not allocate page " 3801 "descriptor chain DMA memory!\n", 3802 __FILE__, __LINE__); 3803 rc = ENOMEM; 3804 goto bce_dma_alloc_exit; 3805 } 3806 3807 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3808 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3809 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3810 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3811 3812 if (error) { 3813 BCE_PRINTF("%s(%d): Could not map page descriptor " 3814 "chain DMA memory!\n", __FILE__, __LINE__); 3815 rc = ENOMEM; 3816 goto bce_dma_alloc_exit; 3817 } 3818 3819 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3820 "0x%jX\n", __FUNCTION__, i, 3821 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3822 } 3823 3824 /* 3825 * Create a DMA tag for page mbufs. 3826 */ 3827 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3828 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3829 3830 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3831 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3832 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3833 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3834 "DMA tag!\n", __FILE__, __LINE__); 3835 rc = ENOMEM; 3836 goto bce_dma_alloc_exit; 3837 } 3838 3839 /* Create DMA maps for the page mbuf clusters. */ 3840 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3841 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3842 &sc->pg_mbuf_map[i])) { 3843 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3844 "DMA map!\n", __FILE__, __LINE__); 3845 rc = ENOMEM; 3846 goto bce_dma_alloc_exit; 3847 } 3848 } 3849 } 3850 3851 bce_dma_alloc_exit: 3852 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3853 return(rc); 3854 } 3855 3856 3857 /****************************************************************************/ 3858 /* Release all resources used by the driver. */ 3859 /* */ 3860 /* Releases all resources acquired by the driver including interrupts, */ 3861 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3862 /* */ 3863 /* Returns: */ 3864 /* Nothing. */ 3865 /****************************************************************************/ 3866 static void 3867 bce_release_resources(struct bce_softc *sc) 3868 { 3869 device_t dev; 3870 3871 DBENTER(BCE_VERBOSE_RESET); 3872 3873 dev = sc->bce_dev; 3874 3875 bce_dma_free(sc); 3876 3877 if (sc->bce_intrhand != NULL) { 3878 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3879 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3880 } 3881 3882 if (sc->bce_res_irq != NULL) { 3883 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3884 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3885 sc->bce_res_irq); 3886 } 3887 3888 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3889 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3890 pci_release_msi(dev); 3891 } 3892 3893 if (sc->bce_res_mem != NULL) { 3894 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3895 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3896 sc->bce_res_mem); 3897 } 3898 3899 if (sc->bce_ifp != NULL) { 3900 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3901 if_free(sc->bce_ifp); 3902 } 3903 3904 if (mtx_initialized(&sc->bce_mtx)) 3905 BCE_LOCK_DESTROY(sc); 3906 3907 DBEXIT(BCE_VERBOSE_RESET); 3908 } 3909 3910 3911 /****************************************************************************/ 3912 /* Firmware synchronization. */ 3913 /* */ 3914 /* Before performing certain events such as a chip reset, synchronize with */ 3915 /* the firmware first. */ 3916 /* */ 3917 /* Returns: */ 3918 /* 0 for success, positive value for failure. */ 3919 /****************************************************************************/ 3920 static int 3921 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3922 { 3923 int i, rc = 0; 3924 u32 val; 3925 3926 DBENTER(BCE_VERBOSE_RESET); 3927 3928 /* Don't waste any time if we've timed out before. */ 3929 if (sc->bce_fw_timed_out == TRUE) { 3930 rc = EBUSY; 3931 goto bce_fw_sync_exit; 3932 } 3933 3934 /* Increment the message sequence number. */ 3935 sc->bce_fw_wr_seq++; 3936 msg_data |= sc->bce_fw_wr_seq; 3937 3938 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3939 "0x%08X\n", msg_data); 3940 3941 /* Send the message to the bootcode driver mailbox. */ 3942 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3943 3944 /* Wait for the bootcode to acknowledge the message. */ 3945 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3946 /* Check for a response in the bootcode firmware mailbox. */ 3947 val = bce_shmem_rd(sc, BCE_FW_MB); 3948 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3949 break; 3950 DELAY(1000); 3951 } 3952 3953 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3954 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3955 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3956 3957 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3958 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3959 3960 msg_data &= ~BCE_DRV_MSG_CODE; 3961 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3962 3963 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3964 3965 sc->bce_fw_timed_out = TRUE; 3966 rc = EBUSY; 3967 } 3968 3969 bce_fw_sync_exit: 3970 DBEXIT(BCE_VERBOSE_RESET); 3971 return (rc); 3972 } 3973 3974 3975 /****************************************************************************/ 3976 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3977 /* */ 3978 /* Returns: */ 3979 /* Nothing. */ 3980 /****************************************************************************/ 3981 static void 3982 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3983 u32 rv2p_code_len, u32 rv2p_proc) 3984 { 3985 int i; 3986 u32 val; 3987 3988 DBENTER(BCE_VERBOSE_RESET); 3989 3990 /* Set the page size used by RV2P. */ 3991 if (rv2p_proc == RV2P_PROC2) { 3992 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3993 } 3994 3995 for (i = 0; i < rv2p_code_len; i += 8) { 3996 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3997 rv2p_code++; 3998 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3999 rv2p_code++; 4000 4001 if (rv2p_proc == RV2P_PROC1) { 4002 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4003 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4004 } 4005 else { 4006 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4007 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4008 } 4009 } 4010 4011 /* Reset the processor, un-stall is done later. */ 4012 if (rv2p_proc == RV2P_PROC1) { 4013 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4014 } 4015 else { 4016 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4017 } 4018 4019 DBEXIT(BCE_VERBOSE_RESET); 4020 } 4021 4022 4023 /****************************************************************************/ 4024 /* Load RISC processor firmware. */ 4025 /* */ 4026 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4027 /* associated with a particular processor. */ 4028 /* */ 4029 /* Returns: */ 4030 /* Nothing. */ 4031 /****************************************************************************/ 4032 static void 4033 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4034 struct fw_info *fw) 4035 { 4036 u32 offset; 4037 4038 DBENTER(BCE_VERBOSE_RESET); 4039 4040 bce_halt_cpu(sc, cpu_reg); 4041 4042 /* Load the Text area. */ 4043 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4044 if (fw->text) { 4045 int j; 4046 4047 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4048 REG_WR_IND(sc, offset, fw->text[j]); 4049 } 4050 } 4051 4052 /* Load the Data area. */ 4053 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4054 if (fw->data) { 4055 int j; 4056 4057 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4058 REG_WR_IND(sc, offset, fw->data[j]); 4059 } 4060 } 4061 4062 /* Load the SBSS area. */ 4063 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4064 if (fw->sbss) { 4065 int j; 4066 4067 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4068 REG_WR_IND(sc, offset, fw->sbss[j]); 4069 } 4070 } 4071 4072 /* Load the BSS area. */ 4073 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4074 if (fw->bss) { 4075 int j; 4076 4077 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4078 REG_WR_IND(sc, offset, fw->bss[j]); 4079 } 4080 } 4081 4082 /* Load the Read-Only area. */ 4083 offset = cpu_reg->spad_base + 4084 (fw->rodata_addr - cpu_reg->mips_view_base); 4085 if (fw->rodata) { 4086 int j; 4087 4088 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4089 REG_WR_IND(sc, offset, fw->rodata[j]); 4090 } 4091 } 4092 4093 /* Clear the pre-fetch instruction and set the FW start address. */ 4094 REG_WR_IND(sc, cpu_reg->inst, 0); 4095 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4096 4097 DBEXIT(BCE_VERBOSE_RESET); 4098 } 4099 4100 4101 /****************************************************************************/ 4102 /* Starts the RISC processor. */ 4103 /* */ 4104 /* Assumes the CPU starting address has already been set. */ 4105 /* */ 4106 /* Returns: */ 4107 /* Nothing. */ 4108 /****************************************************************************/ 4109 static void 4110 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4111 { 4112 u32 val; 4113 4114 DBENTER(BCE_VERBOSE_RESET); 4115 4116 /* Start the CPU. */ 4117 val = REG_RD_IND(sc, cpu_reg->mode); 4118 val &= ~cpu_reg->mode_value_halt; 4119 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4120 REG_WR_IND(sc, cpu_reg->mode, val); 4121 4122 DBEXIT(BCE_VERBOSE_RESET); 4123 } 4124 4125 4126 /****************************************************************************/ 4127 /* Halts the RISC processor. */ 4128 /* */ 4129 /* Returns: */ 4130 /* Nothing. */ 4131 /****************************************************************************/ 4132 static void 4133 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4134 { 4135 u32 val; 4136 4137 DBENTER(BCE_VERBOSE_RESET); 4138 4139 /* Halt the CPU. */ 4140 val = REG_RD_IND(sc, cpu_reg->mode); 4141 val |= cpu_reg->mode_value_halt; 4142 REG_WR_IND(sc, cpu_reg->mode, val); 4143 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4144 4145 DBEXIT(BCE_VERBOSE_RESET); 4146 } 4147 4148 4149 /****************************************************************************/ 4150 /* Initialize the RX CPU. */ 4151 /* */ 4152 /* Returns: */ 4153 /* Nothing. */ 4154 /****************************************************************************/ 4155 static void 4156 bce_start_rxp_cpu(struct bce_softc *sc) 4157 { 4158 struct cpu_reg cpu_reg; 4159 4160 DBENTER(BCE_VERBOSE_RESET); 4161 4162 cpu_reg.mode = BCE_RXP_CPU_MODE; 4163 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4164 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4165 cpu_reg.state = BCE_RXP_CPU_STATE; 4166 cpu_reg.state_value_clear = 0xffffff; 4167 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4168 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4169 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4170 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4171 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4172 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4173 cpu_reg.mips_view_base = 0x8000000; 4174 4175 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4176 bce_start_cpu(sc, &cpu_reg); 4177 4178 DBEXIT(BCE_VERBOSE_RESET); 4179 } 4180 4181 4182 /****************************************************************************/ 4183 /* Initialize the RX CPU. */ 4184 /* */ 4185 /* Returns: */ 4186 /* Nothing. */ 4187 /****************************************************************************/ 4188 static void 4189 bce_init_rxp_cpu(struct bce_softc *sc) 4190 { 4191 struct cpu_reg cpu_reg; 4192 struct fw_info fw; 4193 4194 DBENTER(BCE_VERBOSE_RESET); 4195 4196 cpu_reg.mode = BCE_RXP_CPU_MODE; 4197 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4198 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4199 cpu_reg.state = BCE_RXP_CPU_STATE; 4200 cpu_reg.state_value_clear = 0xffffff; 4201 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4202 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4203 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4204 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4205 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4206 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4207 cpu_reg.mips_view_base = 0x8000000; 4208 4209 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4210 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4211 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4212 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4213 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4214 fw.start_addr = bce_RXP_b09FwStartAddr; 4215 4216 fw.text_addr = bce_RXP_b09FwTextAddr; 4217 fw.text_len = bce_RXP_b09FwTextLen; 4218 fw.text_index = 0; 4219 fw.text = bce_RXP_b09FwText; 4220 4221 fw.data_addr = bce_RXP_b09FwDataAddr; 4222 fw.data_len = bce_RXP_b09FwDataLen; 4223 fw.data_index = 0; 4224 fw.data = bce_RXP_b09FwData; 4225 4226 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4227 fw.sbss_len = bce_RXP_b09FwSbssLen; 4228 fw.sbss_index = 0; 4229 fw.sbss = bce_RXP_b09FwSbss; 4230 4231 fw.bss_addr = bce_RXP_b09FwBssAddr; 4232 fw.bss_len = bce_RXP_b09FwBssLen; 4233 fw.bss_index = 0; 4234 fw.bss = bce_RXP_b09FwBss; 4235 4236 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4237 fw.rodata_len = bce_RXP_b09FwRodataLen; 4238 fw.rodata_index = 0; 4239 fw.rodata = bce_RXP_b09FwRodata; 4240 } else { 4241 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4242 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4243 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4244 fw.start_addr = bce_RXP_b06FwStartAddr; 4245 4246 fw.text_addr = bce_RXP_b06FwTextAddr; 4247 fw.text_len = bce_RXP_b06FwTextLen; 4248 fw.text_index = 0; 4249 fw.text = bce_RXP_b06FwText; 4250 4251 fw.data_addr = bce_RXP_b06FwDataAddr; 4252 fw.data_len = bce_RXP_b06FwDataLen; 4253 fw.data_index = 0; 4254 fw.data = bce_RXP_b06FwData; 4255 4256 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4257 fw.sbss_len = bce_RXP_b06FwSbssLen; 4258 fw.sbss_index = 0; 4259 fw.sbss = bce_RXP_b06FwSbss; 4260 4261 fw.bss_addr = bce_RXP_b06FwBssAddr; 4262 fw.bss_len = bce_RXP_b06FwBssLen; 4263 fw.bss_index = 0; 4264 fw.bss = bce_RXP_b06FwBss; 4265 4266 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4267 fw.rodata_len = bce_RXP_b06FwRodataLen; 4268 fw.rodata_index = 0; 4269 fw.rodata = bce_RXP_b06FwRodata; 4270 } 4271 4272 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4273 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4274 4275 /* Delay RXP start until initialization is complete. */ 4276 4277 DBEXIT(BCE_VERBOSE_RESET); 4278 } 4279 4280 4281 /****************************************************************************/ 4282 /* Initialize the TX CPU. */ 4283 /* */ 4284 /* Returns: */ 4285 /* Nothing. */ 4286 /****************************************************************************/ 4287 static void 4288 bce_init_txp_cpu(struct bce_softc *sc) 4289 { 4290 struct cpu_reg cpu_reg; 4291 struct fw_info fw; 4292 4293 DBENTER(BCE_VERBOSE_RESET); 4294 4295 cpu_reg.mode = BCE_TXP_CPU_MODE; 4296 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4297 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4298 cpu_reg.state = BCE_TXP_CPU_STATE; 4299 cpu_reg.state_value_clear = 0xffffff; 4300 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4301 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4302 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4303 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4304 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4305 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4306 cpu_reg.mips_view_base = 0x8000000; 4307 4308 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4309 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4310 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4311 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4312 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4313 fw.start_addr = bce_TXP_b09FwStartAddr; 4314 4315 fw.text_addr = bce_TXP_b09FwTextAddr; 4316 fw.text_len = bce_TXP_b09FwTextLen; 4317 fw.text_index = 0; 4318 fw.text = bce_TXP_b09FwText; 4319 4320 fw.data_addr = bce_TXP_b09FwDataAddr; 4321 fw.data_len = bce_TXP_b09FwDataLen; 4322 fw.data_index = 0; 4323 fw.data = bce_TXP_b09FwData; 4324 4325 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4326 fw.sbss_len = bce_TXP_b09FwSbssLen; 4327 fw.sbss_index = 0; 4328 fw.sbss = bce_TXP_b09FwSbss; 4329 4330 fw.bss_addr = bce_TXP_b09FwBssAddr; 4331 fw.bss_len = bce_TXP_b09FwBssLen; 4332 fw.bss_index = 0; 4333 fw.bss = bce_TXP_b09FwBss; 4334 4335 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4336 fw.rodata_len = bce_TXP_b09FwRodataLen; 4337 fw.rodata_index = 0; 4338 fw.rodata = bce_TXP_b09FwRodata; 4339 } else { 4340 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4341 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4342 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4343 fw.start_addr = bce_TXP_b06FwStartAddr; 4344 4345 fw.text_addr = bce_TXP_b06FwTextAddr; 4346 fw.text_len = bce_TXP_b06FwTextLen; 4347 fw.text_index = 0; 4348 fw.text = bce_TXP_b06FwText; 4349 4350 fw.data_addr = bce_TXP_b06FwDataAddr; 4351 fw.data_len = bce_TXP_b06FwDataLen; 4352 fw.data_index = 0; 4353 fw.data = bce_TXP_b06FwData; 4354 4355 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4356 fw.sbss_len = bce_TXP_b06FwSbssLen; 4357 fw.sbss_index = 0; 4358 fw.sbss = bce_TXP_b06FwSbss; 4359 4360 fw.bss_addr = bce_TXP_b06FwBssAddr; 4361 fw.bss_len = bce_TXP_b06FwBssLen; 4362 fw.bss_index = 0; 4363 fw.bss = bce_TXP_b06FwBss; 4364 4365 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4366 fw.rodata_len = bce_TXP_b06FwRodataLen; 4367 fw.rodata_index = 0; 4368 fw.rodata = bce_TXP_b06FwRodata; 4369 } 4370 4371 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4372 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4373 bce_start_cpu(sc, &cpu_reg); 4374 4375 DBEXIT(BCE_VERBOSE_RESET); 4376 } 4377 4378 4379 /****************************************************************************/ 4380 /* Initialize the TPAT CPU. */ 4381 /* */ 4382 /* Returns: */ 4383 /* Nothing. */ 4384 /****************************************************************************/ 4385 static void 4386 bce_init_tpat_cpu(struct bce_softc *sc) 4387 { 4388 struct cpu_reg cpu_reg; 4389 struct fw_info fw; 4390 4391 DBENTER(BCE_VERBOSE_RESET); 4392 4393 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4394 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4395 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4396 cpu_reg.state = BCE_TPAT_CPU_STATE; 4397 cpu_reg.state_value_clear = 0xffffff; 4398 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4399 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4400 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4401 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4402 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4403 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4404 cpu_reg.mips_view_base = 0x8000000; 4405 4406 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4407 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4408 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4409 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4410 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4411 fw.start_addr = bce_TPAT_b09FwStartAddr; 4412 4413 fw.text_addr = bce_TPAT_b09FwTextAddr; 4414 fw.text_len = bce_TPAT_b09FwTextLen; 4415 fw.text_index = 0; 4416 fw.text = bce_TPAT_b09FwText; 4417 4418 fw.data_addr = bce_TPAT_b09FwDataAddr; 4419 fw.data_len = bce_TPAT_b09FwDataLen; 4420 fw.data_index = 0; 4421 fw.data = bce_TPAT_b09FwData; 4422 4423 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4424 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4425 fw.sbss_index = 0; 4426 fw.sbss = bce_TPAT_b09FwSbss; 4427 4428 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4429 fw.bss_len = bce_TPAT_b09FwBssLen; 4430 fw.bss_index = 0; 4431 fw.bss = bce_TPAT_b09FwBss; 4432 4433 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4434 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4435 fw.rodata_index = 0; 4436 fw.rodata = bce_TPAT_b09FwRodata; 4437 } else { 4438 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4439 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4440 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4441 fw.start_addr = bce_TPAT_b06FwStartAddr; 4442 4443 fw.text_addr = bce_TPAT_b06FwTextAddr; 4444 fw.text_len = bce_TPAT_b06FwTextLen; 4445 fw.text_index = 0; 4446 fw.text = bce_TPAT_b06FwText; 4447 4448 fw.data_addr = bce_TPAT_b06FwDataAddr; 4449 fw.data_len = bce_TPAT_b06FwDataLen; 4450 fw.data_index = 0; 4451 fw.data = bce_TPAT_b06FwData; 4452 4453 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4454 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4455 fw.sbss_index = 0; 4456 fw.sbss = bce_TPAT_b06FwSbss; 4457 4458 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4459 fw.bss_len = bce_TPAT_b06FwBssLen; 4460 fw.bss_index = 0; 4461 fw.bss = bce_TPAT_b06FwBss; 4462 4463 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4464 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4465 fw.rodata_index = 0; 4466 fw.rodata = bce_TPAT_b06FwRodata; 4467 } 4468 4469 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4470 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4471 bce_start_cpu(sc, &cpu_reg); 4472 4473 DBEXIT(BCE_VERBOSE_RESET); 4474 } 4475 4476 4477 /****************************************************************************/ 4478 /* Initialize the CP CPU. */ 4479 /* */ 4480 /* Returns: */ 4481 /* Nothing. */ 4482 /****************************************************************************/ 4483 static void 4484 bce_init_cp_cpu(struct bce_softc *sc) 4485 { 4486 struct cpu_reg cpu_reg; 4487 struct fw_info fw; 4488 4489 DBENTER(BCE_VERBOSE_RESET); 4490 4491 cpu_reg.mode = BCE_CP_CPU_MODE; 4492 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4493 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4494 cpu_reg.state = BCE_CP_CPU_STATE; 4495 cpu_reg.state_value_clear = 0xffffff; 4496 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4497 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4498 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4499 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4500 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4501 cpu_reg.spad_base = BCE_CP_SCRATCH; 4502 cpu_reg.mips_view_base = 0x8000000; 4503 4504 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4505 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4506 fw.ver_major = bce_CP_b09FwReleaseMajor; 4507 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4508 fw.ver_fix = bce_CP_b09FwReleaseFix; 4509 fw.start_addr = bce_CP_b09FwStartAddr; 4510 4511 fw.text_addr = bce_CP_b09FwTextAddr; 4512 fw.text_len = bce_CP_b09FwTextLen; 4513 fw.text_index = 0; 4514 fw.text = bce_CP_b09FwText; 4515 4516 fw.data_addr = bce_CP_b09FwDataAddr; 4517 fw.data_len = bce_CP_b09FwDataLen; 4518 fw.data_index = 0; 4519 fw.data = bce_CP_b09FwData; 4520 4521 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4522 fw.sbss_len = bce_CP_b09FwSbssLen; 4523 fw.sbss_index = 0; 4524 fw.sbss = bce_CP_b09FwSbss; 4525 4526 fw.bss_addr = bce_CP_b09FwBssAddr; 4527 fw.bss_len = bce_CP_b09FwBssLen; 4528 fw.bss_index = 0; 4529 fw.bss = bce_CP_b09FwBss; 4530 4531 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4532 fw.rodata_len = bce_CP_b09FwRodataLen; 4533 fw.rodata_index = 0; 4534 fw.rodata = bce_CP_b09FwRodata; 4535 } else { 4536 fw.ver_major = bce_CP_b06FwReleaseMajor; 4537 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4538 fw.ver_fix = bce_CP_b06FwReleaseFix; 4539 fw.start_addr = bce_CP_b06FwStartAddr; 4540 4541 fw.text_addr = bce_CP_b06FwTextAddr; 4542 fw.text_len = bce_CP_b06FwTextLen; 4543 fw.text_index = 0; 4544 fw.text = bce_CP_b06FwText; 4545 4546 fw.data_addr = bce_CP_b06FwDataAddr; 4547 fw.data_len = bce_CP_b06FwDataLen; 4548 fw.data_index = 0; 4549 fw.data = bce_CP_b06FwData; 4550 4551 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4552 fw.sbss_len = bce_CP_b06FwSbssLen; 4553 fw.sbss_index = 0; 4554 fw.sbss = bce_CP_b06FwSbss; 4555 4556 fw.bss_addr = bce_CP_b06FwBssAddr; 4557 fw.bss_len = bce_CP_b06FwBssLen; 4558 fw.bss_index = 0; 4559 fw.bss = bce_CP_b06FwBss; 4560 4561 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4562 fw.rodata_len = bce_CP_b06FwRodataLen; 4563 fw.rodata_index = 0; 4564 fw.rodata = bce_CP_b06FwRodata; 4565 } 4566 4567 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4568 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4569 bce_start_cpu(sc, &cpu_reg); 4570 4571 DBEXIT(BCE_VERBOSE_RESET); 4572 } 4573 4574 4575 /****************************************************************************/ 4576 /* Initialize the COM CPU. */ 4577 /* */ 4578 /* Returns: */ 4579 /* Nothing. */ 4580 /****************************************************************************/ 4581 static void 4582 bce_init_com_cpu(struct bce_softc *sc) 4583 { 4584 struct cpu_reg cpu_reg; 4585 struct fw_info fw; 4586 4587 DBENTER(BCE_VERBOSE_RESET); 4588 4589 cpu_reg.mode = BCE_COM_CPU_MODE; 4590 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4591 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4592 cpu_reg.state = BCE_COM_CPU_STATE; 4593 cpu_reg.state_value_clear = 0xffffff; 4594 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4595 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4596 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4597 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4598 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4599 cpu_reg.spad_base = BCE_COM_SCRATCH; 4600 cpu_reg.mips_view_base = 0x8000000; 4601 4602 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4603 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4604 fw.ver_major = bce_COM_b09FwReleaseMajor; 4605 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4606 fw.ver_fix = bce_COM_b09FwReleaseFix; 4607 fw.start_addr = bce_COM_b09FwStartAddr; 4608 4609 fw.text_addr = bce_COM_b09FwTextAddr; 4610 fw.text_len = bce_COM_b09FwTextLen; 4611 fw.text_index = 0; 4612 fw.text = bce_COM_b09FwText; 4613 4614 fw.data_addr = bce_COM_b09FwDataAddr; 4615 fw.data_len = bce_COM_b09FwDataLen; 4616 fw.data_index = 0; 4617 fw.data = bce_COM_b09FwData; 4618 4619 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4620 fw.sbss_len = bce_COM_b09FwSbssLen; 4621 fw.sbss_index = 0; 4622 fw.sbss = bce_COM_b09FwSbss; 4623 4624 fw.bss_addr = bce_COM_b09FwBssAddr; 4625 fw.bss_len = bce_COM_b09FwBssLen; 4626 fw.bss_index = 0; 4627 fw.bss = bce_COM_b09FwBss; 4628 4629 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4630 fw.rodata_len = bce_COM_b09FwRodataLen; 4631 fw.rodata_index = 0; 4632 fw.rodata = bce_COM_b09FwRodata; 4633 } else { 4634 fw.ver_major = bce_COM_b06FwReleaseMajor; 4635 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4636 fw.ver_fix = bce_COM_b06FwReleaseFix; 4637 fw.start_addr = bce_COM_b06FwStartAddr; 4638 4639 fw.text_addr = bce_COM_b06FwTextAddr; 4640 fw.text_len = bce_COM_b06FwTextLen; 4641 fw.text_index = 0; 4642 fw.text = bce_COM_b06FwText; 4643 4644 fw.data_addr = bce_COM_b06FwDataAddr; 4645 fw.data_len = bce_COM_b06FwDataLen; 4646 fw.data_index = 0; 4647 fw.data = bce_COM_b06FwData; 4648 4649 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4650 fw.sbss_len = bce_COM_b06FwSbssLen; 4651 fw.sbss_index = 0; 4652 fw.sbss = bce_COM_b06FwSbss; 4653 4654 fw.bss_addr = bce_COM_b06FwBssAddr; 4655 fw.bss_len = bce_COM_b06FwBssLen; 4656 fw.bss_index = 0; 4657 fw.bss = bce_COM_b06FwBss; 4658 4659 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4660 fw.rodata_len = bce_COM_b06FwRodataLen; 4661 fw.rodata_index = 0; 4662 fw.rodata = bce_COM_b06FwRodata; 4663 } 4664 4665 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4666 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4667 bce_start_cpu(sc, &cpu_reg); 4668 4669 DBEXIT(BCE_VERBOSE_RESET); 4670 } 4671 4672 4673 /****************************************************************************/ 4674 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4675 /* */ 4676 /* Loads the firmware for each CPU and starts the CPU. */ 4677 /* */ 4678 /* Returns: */ 4679 /* Nothing. */ 4680 /****************************************************************************/ 4681 static void 4682 bce_init_cpus(struct bce_softc *sc) 4683 { 4684 DBENTER(BCE_VERBOSE_RESET); 4685 4686 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4687 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4688 4689 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4690 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4691 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4692 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4693 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4694 } else { 4695 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4696 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4697 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4698 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4699 } 4700 4701 } else { 4702 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4703 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4704 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4705 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4706 } 4707 4708 bce_init_rxp_cpu(sc); 4709 bce_init_txp_cpu(sc); 4710 bce_init_tpat_cpu(sc); 4711 bce_init_com_cpu(sc); 4712 bce_init_cp_cpu(sc); 4713 4714 DBEXIT(BCE_VERBOSE_RESET); 4715 } 4716 4717 4718 /****************************************************************************/ 4719 /* Initialize context memory. */ 4720 /* */ 4721 /* Clears the memory associated with each Context ID (CID). */ 4722 /* */ 4723 /* Returns: */ 4724 /* Nothing. */ 4725 /****************************************************************************/ 4726 static int 4727 bce_init_ctx(struct bce_softc *sc) 4728 { 4729 u32 offset, val, vcid_addr; 4730 int i, j, rc, retry_cnt; 4731 4732 rc = 0; 4733 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4734 4735 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4736 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4737 retry_cnt = CTX_INIT_RETRY_COUNT; 4738 4739 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4740 4741 /* 4742 * BCM5709 context memory may be cached 4743 * in host memory so prepare the host memory 4744 * for access. 4745 */ 4746 val = BCE_CTX_COMMAND_ENABLED | 4747 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4748 val |= (BCM_PAGE_BITS - 8) << 16; 4749 REG_WR(sc, BCE_CTX_COMMAND, val); 4750 4751 /* Wait for mem init command to complete. */ 4752 for (i = 0; i < retry_cnt; i++) { 4753 val = REG_RD(sc, BCE_CTX_COMMAND); 4754 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4755 break; 4756 DELAY(2); 4757 } 4758 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4759 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4760 __FUNCTION__); 4761 rc = EBUSY; 4762 goto init_ctx_fail; 4763 } 4764 4765 for (i = 0; i < sc->ctx_pages; i++) { 4766 /* Set the physical address of the context memory. */ 4767 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4768 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4769 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4770 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4771 BCE_ADDR_HI(sc->ctx_paddr[i])); 4772 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4773 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4774 4775 /* Verify the context memory write was successful. */ 4776 for (j = 0; j < retry_cnt; j++) { 4777 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4778 if ((val & 4779 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4780 break; 4781 DELAY(5); 4782 } 4783 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4784 BCE_PRINTF("%s(): Failed to initialize " 4785 "context page %d!\n", __FUNCTION__, i); 4786 rc = EBUSY; 4787 goto init_ctx_fail; 4788 } 4789 } 4790 } else { 4791 4792 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4793 4794 /* 4795 * For the 5706/5708, context memory is local to 4796 * the controller, so initialize the controller 4797 * context memory. 4798 */ 4799 4800 vcid_addr = GET_CID_ADDR(96); 4801 while (vcid_addr) { 4802 4803 vcid_addr -= PHY_CTX_SIZE; 4804 4805 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4806 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4807 4808 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4809 CTX_WR(sc, 0x00, offset, 0); 4810 } 4811 4812 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4813 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4814 } 4815 4816 } 4817 init_ctx_fail: 4818 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4819 return (rc); 4820 } 4821 4822 4823 /****************************************************************************/ 4824 /* Fetch the permanent MAC address of the controller. */ 4825 /* */ 4826 /* Returns: */ 4827 /* Nothing. */ 4828 /****************************************************************************/ 4829 static void 4830 bce_get_mac_addr(struct bce_softc *sc) 4831 { 4832 u32 mac_lo = 0, mac_hi = 0; 4833 4834 DBENTER(BCE_VERBOSE_RESET); 4835 4836 /* 4837 * The NetXtreme II bootcode populates various NIC 4838 * power-on and runtime configuration items in a 4839 * shared memory area. The factory configured MAC 4840 * address is available from both NVRAM and the 4841 * shared memory area so we'll read the value from 4842 * shared memory for speed. 4843 */ 4844 4845 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4846 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4847 4848 if ((mac_lo == 0) && (mac_hi == 0)) { 4849 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4850 __FILE__, __LINE__); 4851 } else { 4852 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4853 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4854 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4855 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4856 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4857 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4858 } 4859 4860 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4861 "address = %6D\n", sc->eaddr, ":"); 4862 DBEXIT(BCE_VERBOSE_RESET); 4863 } 4864 4865 4866 /****************************************************************************/ 4867 /* Program the MAC address. */ 4868 /* */ 4869 /* Returns: */ 4870 /* Nothing. */ 4871 /****************************************************************************/ 4872 static void 4873 bce_set_mac_addr(struct bce_softc *sc) 4874 { 4875 u32 val; 4876 u8 *mac_addr = sc->eaddr; 4877 4878 /* ToDo: Add support for setting multiple MAC addresses. */ 4879 4880 DBENTER(BCE_VERBOSE_RESET); 4881 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4882 "%6D\n", sc->eaddr, ":"); 4883 4884 val = (mac_addr[0] << 8) | mac_addr[1]; 4885 4886 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4887 4888 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4889 (mac_addr[4] << 8) | mac_addr[5]; 4890 4891 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4892 4893 DBEXIT(BCE_VERBOSE_RESET); 4894 } 4895 4896 4897 /****************************************************************************/ 4898 /* Stop the controller. */ 4899 /* */ 4900 /* Returns: */ 4901 /* Nothing. */ 4902 /****************************************************************************/ 4903 static void 4904 bce_stop(struct bce_softc *sc) 4905 { 4906 struct ifnet *ifp; 4907 4908 DBENTER(BCE_VERBOSE_RESET); 4909 4910 BCE_LOCK_ASSERT(sc); 4911 4912 ifp = sc->bce_ifp; 4913 4914 callout_stop(&sc->bce_tick_callout); 4915 4916 /* Disable the transmit/receive blocks. */ 4917 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4918 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4919 DELAY(20); 4920 4921 bce_disable_intr(sc); 4922 4923 /* Free RX buffers. */ 4924 if (bce_hdr_split == TRUE) { 4925 bce_free_pg_chain(sc); 4926 } 4927 bce_free_rx_chain(sc); 4928 4929 /* Free TX buffers. */ 4930 bce_free_tx_chain(sc); 4931 4932 sc->watchdog_timer = 0; 4933 4934 sc->bce_link_up = FALSE; 4935 4936 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4937 4938 DBEXIT(BCE_VERBOSE_RESET); 4939 } 4940 4941 4942 static int 4943 bce_reset(struct bce_softc *sc, u32 reset_code) 4944 { 4945 u32 val; 4946 int i, rc = 0; 4947 4948 DBENTER(BCE_VERBOSE_RESET); 4949 4950 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4951 __FUNCTION__, reset_code); 4952 4953 /* Wait for pending PCI transactions to complete. */ 4954 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4955 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4956 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4957 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4958 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4959 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4960 DELAY(5); 4961 4962 /* Disable DMA */ 4963 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4964 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4965 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4966 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4967 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4968 } 4969 4970 /* Assume bootcode is running. */ 4971 sc->bce_fw_timed_out = FALSE; 4972 sc->bce_drv_cardiac_arrest = FALSE; 4973 4974 /* Give the firmware a chance to prepare for the reset. */ 4975 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4976 if (rc) 4977 goto bce_reset_exit; 4978 4979 /* Set a firmware reminder that this is a soft reset. */ 4980 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4981 4982 /* Dummy read to force the chip to complete all current transactions. */ 4983 val = REG_RD(sc, BCE_MISC_ID); 4984 4985 /* Chip reset. */ 4986 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4987 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4988 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4989 REG_RD(sc, BCE_MISC_COMMAND); 4990 DELAY(5); 4991 4992 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4993 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4994 4995 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4996 } else { 4997 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4998 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4999 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5000 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 5001 5002 /* Allow up to 30us for reset to complete. */ 5003 for (i = 0; i < 10; i++) { 5004 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5005 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5006 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5007 break; 5008 } 5009 DELAY(10); 5010 } 5011 5012 /* Check that reset completed successfully. */ 5013 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5014 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5015 BCE_PRINTF("%s(%d): Reset failed!\n", 5016 __FILE__, __LINE__); 5017 rc = EBUSY; 5018 goto bce_reset_exit; 5019 } 5020 } 5021 5022 /* Make sure byte swapping is properly configured. */ 5023 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5024 if (val != 0x01020304) { 5025 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5026 __FILE__, __LINE__); 5027 rc = ENODEV; 5028 goto bce_reset_exit; 5029 } 5030 5031 /* Just completed a reset, assume that firmware is running again. */ 5032 sc->bce_fw_timed_out = FALSE; 5033 sc->bce_drv_cardiac_arrest = FALSE; 5034 5035 /* Wait for the firmware to finish its initialization. */ 5036 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5037 if (rc) 5038 BCE_PRINTF("%s(%d): Firmware did not complete " 5039 "initialization!\n", __FILE__, __LINE__); 5040 5041 bce_reset_exit: 5042 DBEXIT(BCE_VERBOSE_RESET); 5043 return (rc); 5044 } 5045 5046 5047 static int 5048 bce_chipinit(struct bce_softc *sc) 5049 { 5050 u32 val; 5051 int rc = 0; 5052 5053 DBENTER(BCE_VERBOSE_RESET); 5054 5055 bce_disable_intr(sc); 5056 5057 /* 5058 * Initialize DMA byte/word swapping, configure the number of DMA 5059 * channels and PCI clock compensation delay. 5060 */ 5061 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5062 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5063 #if BYTE_ORDER == BIG_ENDIAN 5064 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5065 #endif 5066 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5067 DMA_READ_CHANS << 12 | 5068 DMA_WRITE_CHANS << 16; 5069 5070 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5071 5072 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5073 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5074 5075 /* 5076 * This setting resolves a problem observed on certain Intel PCI 5077 * chipsets that cannot handle multiple outstanding DMA operations. 5078 * See errata E9_5706A1_65. 5079 */ 5080 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5081 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5082 !(sc->bce_flags & BCE_PCIX_FLAG)) 5083 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5084 5085 REG_WR(sc, BCE_DMA_CONFIG, val); 5086 5087 /* Enable the RX_V2P and Context state machines before access. */ 5088 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5089 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5090 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5091 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5092 5093 /* Initialize context mapping and zero out the quick contexts. */ 5094 if ((rc = bce_init_ctx(sc)) != 0) 5095 goto bce_chipinit_exit; 5096 5097 /* Initialize the on-boards CPUs */ 5098 bce_init_cpus(sc); 5099 5100 /* Enable management frames (NC-SI) to flow to the MCP. */ 5101 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5102 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5103 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5104 } 5105 5106 /* Prepare NVRAM for access. */ 5107 if ((rc = bce_init_nvram(sc)) != 0) 5108 goto bce_chipinit_exit; 5109 5110 /* Set the kernel bypass block size */ 5111 val = REG_RD(sc, BCE_MQ_CONFIG); 5112 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5113 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5114 5115 /* Enable bins used on the 5709. */ 5116 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5117 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5118 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5119 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5120 val |= BCE_MQ_CONFIG_HALT_DIS; 5121 } 5122 5123 REG_WR(sc, BCE_MQ_CONFIG, val); 5124 5125 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5126 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5127 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5128 5129 /* Set the page size and clear the RV2P processor stall bits. */ 5130 val = (BCM_PAGE_BITS - 8) << 24; 5131 REG_WR(sc, BCE_RV2P_CONFIG, val); 5132 5133 /* Configure page size. */ 5134 val = REG_RD(sc, BCE_TBDR_CONFIG); 5135 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5136 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5137 REG_WR(sc, BCE_TBDR_CONFIG, val); 5138 5139 /* Set the perfect match control register to default. */ 5140 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5141 5142 bce_chipinit_exit: 5143 DBEXIT(BCE_VERBOSE_RESET); 5144 5145 return(rc); 5146 } 5147 5148 5149 /****************************************************************************/ 5150 /* Initialize the controller in preparation to send/receive traffic. */ 5151 /* */ 5152 /* Returns: */ 5153 /* 0 for success, positive value for failure. */ 5154 /****************************************************************************/ 5155 static int 5156 bce_blockinit(struct bce_softc *sc) 5157 { 5158 u32 reg, val; 5159 int rc = 0; 5160 5161 DBENTER(BCE_VERBOSE_RESET); 5162 5163 /* Load the hardware default MAC address. */ 5164 bce_set_mac_addr(sc); 5165 5166 /* Set the Ethernet backoff seed value */ 5167 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5168 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5169 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5170 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5171 5172 sc->last_status_idx = 0; 5173 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5174 5175 /* Set up link change interrupt generation. */ 5176 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5177 5178 /* Program the physical address of the status block. */ 5179 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5180 BCE_ADDR_LO(sc->status_block_paddr)); 5181 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5182 BCE_ADDR_HI(sc->status_block_paddr)); 5183 5184 /* Program the physical address of the statistics block. */ 5185 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5186 BCE_ADDR_LO(sc->stats_block_paddr)); 5187 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5188 BCE_ADDR_HI(sc->stats_block_paddr)); 5189 5190 /* Program various host coalescing parameters. */ 5191 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5192 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 5193 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5194 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 5195 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 5196 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 5197 REG_WR(sc, BCE_HC_TX_TICKS, 5198 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5199 REG_WR(sc, BCE_HC_RX_TICKS, 5200 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5201 REG_WR(sc, BCE_HC_COM_TICKS, 5202 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 5203 REG_WR(sc, BCE_HC_CMD_TICKS, 5204 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 5205 REG_WR(sc, BCE_HC_STATS_TICKS, 5206 (sc->bce_stats_ticks & 0xffff00)); 5207 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5208 5209 /* Configure the Host Coalescing block. */ 5210 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5211 BCE_HC_CONFIG_COLLECT_STATS; 5212 5213 #if 0 5214 /* ToDo: Add MSI-X support. */ 5215 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5216 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5217 BCE_HC_SB_CONFIG_1; 5218 5219 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5220 5221 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5222 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5223 5224 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5225 (sc->tx_quick_cons_trip_int << 16) | 5226 sc->tx_quick_cons_trip); 5227 5228 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5229 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5230 5231 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5232 } 5233 5234 /* 5235 * Tell the HC block to automatically set the 5236 * INT_MASK bit after an MSI/MSI-X interrupt 5237 * is generated so the driver doesn't have to. 5238 */ 5239 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5240 val |= BCE_HC_CONFIG_ONE_SHOT; 5241 5242 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5243 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5244 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5245 #endif 5246 5247 REG_WR(sc, BCE_HC_CONFIG, val); 5248 5249 /* Clear the internal statistics counters. */ 5250 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5251 5252 /* Verify that bootcode is running. */ 5253 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5254 5255 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5256 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5257 __FILE__, __LINE__); 5258 reg = 0); 5259 5260 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5261 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5262 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5263 "Expected: 08%08X\n", __FILE__, __LINE__, 5264 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5265 BCE_DEV_INFO_SIGNATURE_MAGIC); 5266 rc = ENODEV; 5267 goto bce_blockinit_exit; 5268 } 5269 5270 /* Enable DMA */ 5271 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5272 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5273 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5274 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5275 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5276 } 5277 5278 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5279 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5280 BCE_DRV_MSG_CODE_RESET); 5281 5282 /* Enable link state change interrupt generation. */ 5283 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5284 5285 /* Enable the RXP. */ 5286 bce_start_rxp_cpu(sc); 5287 5288 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5289 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5290 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5291 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5292 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5293 } 5294 5295 /* Enable all remaining blocks in the MAC. */ 5296 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5297 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 5298 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5299 BCE_MISC_ENABLE_DEFAULT_XI); 5300 else 5301 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5302 BCE_MISC_ENABLE_DEFAULT); 5303 5304 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5305 DELAY(20); 5306 5307 /* Save the current host coalescing block settings. */ 5308 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5309 5310 bce_blockinit_exit: 5311 DBEXIT(BCE_VERBOSE_RESET); 5312 5313 return (rc); 5314 } 5315 5316 5317 /****************************************************************************/ 5318 /* Encapsulate an mbuf into the rx_bd chain. */ 5319 /* */ 5320 /* Returns: */ 5321 /* 0 for success, positive value for failure. */ 5322 /****************************************************************************/ 5323 static int 5324 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5325 u16 *chain_prod, u32 *prod_bseq) 5326 { 5327 bus_dmamap_t map; 5328 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 5329 struct mbuf *m_new = NULL; 5330 struct rx_bd *rxbd; 5331 int nsegs, error, rc = 0; 5332 #ifdef BCE_DEBUG 5333 u16 debug_chain_prod = *chain_prod; 5334 #endif 5335 5336 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5337 5338 /* Make sure the inputs are valid. */ 5339 DBRUNIF((*chain_prod > MAX_RX_BD_ALLOC), 5340 BCE_PRINTF("%s(%d): RX producer out of range: " 5341 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5342 *chain_prod, (u16) MAX_RX_BD_ALLOC)); 5343 5344 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5345 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5346 *prod, *chain_prod, *prod_bseq); 5347 5348 /* Update some debug statistic counters */ 5349 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5350 sc->rx_low_watermark = sc->free_rx_bd); 5351 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5352 sc->rx_empty_count++); 5353 5354 /* Check whether this is a new mbuf allocation. */ 5355 if (m == NULL) { 5356 5357 /* Simulate an mbuf allocation failure. */ 5358 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5359 sc->mbuf_alloc_failed_count++; 5360 sc->mbuf_alloc_failed_sim_count++; 5361 rc = ENOBUFS; 5362 goto bce_get_rx_buf_exit); 5363 5364 /* This is a new mbuf allocation. */ 5365 if (bce_hdr_split == TRUE) 5366 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5367 else 5368 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 5369 sc->rx_bd_mbuf_alloc_size); 5370 5371 if (m_new == NULL) { 5372 sc->mbuf_alloc_failed_count++; 5373 rc = ENOBUFS; 5374 goto bce_get_rx_buf_exit; 5375 } 5376 5377 DBRUN(sc->debug_rx_mbuf_alloc++); 5378 } else { 5379 /* Reuse an existing mbuf. */ 5380 m_new = m; 5381 } 5382 5383 /* Make sure we have a valid packet header. */ 5384 M_ASSERTPKTHDR(m_new); 5385 5386 /* Initialize the mbuf size and pad if necessary for alignment. */ 5387 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5388 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5389 5390 /* ToDo: Consider calling m_fragment() to test error handling. */ 5391 5392 /* Map the mbuf cluster into device memory. */ 5393 map = sc->rx_mbuf_map[*chain_prod]; 5394 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5395 segs, &nsegs, BUS_DMA_NOWAIT); 5396 5397 /* Handle any mapping errors. */ 5398 if (error) { 5399 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5400 "chain (%d)!\n", __FILE__, __LINE__, error); 5401 5402 sc->dma_map_addr_rx_failed_count++; 5403 m_freem(m_new); 5404 5405 DBRUN(sc->debug_rx_mbuf_alloc--); 5406 5407 rc = ENOBUFS; 5408 goto bce_get_rx_buf_exit; 5409 } 5410 5411 /* All mbufs must map to a single segment. */ 5412 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5413 __FUNCTION__, nsegs)); 5414 5415 /* Setup the rx_bd for the segment. */ 5416 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5417 5418 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5419 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5420 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5421 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5422 *prod_bseq += segs[0].ds_len; 5423 5424 /* Save the mbuf and update our counter. */ 5425 sc->rx_mbuf_ptr[*chain_prod] = m_new; 5426 sc->free_rx_bd -= nsegs; 5427 5428 DBRUNMSG(BCE_INSANE_RECV, 5429 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5430 5431 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5432 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", 5433 __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5434 5435 bce_get_rx_buf_exit: 5436 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5437 5438 return(rc); 5439 } 5440 5441 5442 /****************************************************************************/ 5443 /* Encapsulate an mbuf cluster into the page chain. */ 5444 /* */ 5445 /* Returns: */ 5446 /* 0 for success, positive value for failure. */ 5447 /****************************************************************************/ 5448 static int 5449 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5450 u16 *prod_idx) 5451 { 5452 bus_dmamap_t map; 5453 bus_addr_t busaddr; 5454 struct mbuf *m_new = NULL; 5455 struct rx_bd *pgbd; 5456 int error, rc = 0; 5457 #ifdef BCE_DEBUG 5458 u16 debug_prod_idx = *prod_idx; 5459 #endif 5460 5461 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5462 5463 /* Make sure the inputs are valid. */ 5464 DBRUNIF((*prod_idx > MAX_PG_BD_ALLOC), 5465 BCE_PRINTF("%s(%d): page producer out of range: " 5466 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5467 *prod_idx, (u16) MAX_PG_BD_ALLOC)); 5468 5469 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5470 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5471 5472 /* Update counters if we've hit a new low or run out of pages. */ 5473 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5474 sc->pg_low_watermark = sc->free_pg_bd); 5475 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5476 5477 /* Check whether this is a new mbuf allocation. */ 5478 if (m == NULL) { 5479 5480 /* Simulate an mbuf allocation failure. */ 5481 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5482 sc->mbuf_alloc_failed_count++; 5483 sc->mbuf_alloc_failed_sim_count++; 5484 rc = ENOBUFS; 5485 goto bce_get_pg_buf_exit); 5486 5487 /* This is a new mbuf allocation. */ 5488 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5489 if (m_new == NULL) { 5490 sc->mbuf_alloc_failed_count++; 5491 rc = ENOBUFS; 5492 goto bce_get_pg_buf_exit; 5493 } 5494 5495 DBRUN(sc->debug_pg_mbuf_alloc++); 5496 } else { 5497 /* Reuse an existing mbuf. */ 5498 m_new = m; 5499 m_new->m_data = m_new->m_ext.ext_buf; 5500 } 5501 5502 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5503 5504 /* ToDo: Consider calling m_fragment() to test error handling. */ 5505 5506 /* Map the mbuf cluster into device memory. */ 5507 map = sc->pg_mbuf_map[*prod_idx]; 5508 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5509 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, 5510 &busaddr, BUS_DMA_NOWAIT); 5511 5512 /* Handle any mapping errors. */ 5513 if (error) { 5514 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5515 __FILE__, __LINE__); 5516 5517 m_freem(m_new); 5518 DBRUN(sc->debug_pg_mbuf_alloc--); 5519 5520 rc = ENOBUFS; 5521 goto bce_get_pg_buf_exit; 5522 } 5523 5524 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5525 5526 /* 5527 * The page chain uses the same rx_bd data structure 5528 * as the receive chain but doesn't require a byte sequence (bseq). 5529 */ 5530 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5531 5532 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5533 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5534 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5535 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5536 5537 /* Save the mbuf and update our counter. */ 5538 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5539 sc->free_pg_bd--; 5540 5541 DBRUNMSG(BCE_INSANE_RECV, 5542 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5543 5544 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5545 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5546 5547 bce_get_pg_buf_exit: 5548 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5549 5550 return(rc); 5551 } 5552 5553 5554 /****************************************************************************/ 5555 /* Initialize the TX context memory. */ 5556 /* */ 5557 /* Returns: */ 5558 /* Nothing */ 5559 /****************************************************************************/ 5560 static void 5561 bce_init_tx_context(struct bce_softc *sc) 5562 { 5563 u32 val; 5564 5565 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5566 5567 /* Initialize the context ID for an L2 TX chain. */ 5568 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5569 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5570 /* Set the CID type to support an L2 connection. */ 5571 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5572 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5573 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5574 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5575 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5576 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5577 5578 /* Point the hardware to the first page in the chain. */ 5579 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5580 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5581 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5582 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5583 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5584 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5585 } else { 5586 /* Set the CID type to support an L2 connection. */ 5587 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5588 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5589 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5590 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5591 5592 /* Point the hardware to the first page in the chain. */ 5593 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5594 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5595 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5596 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5597 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5598 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5599 } 5600 5601 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5602 } 5603 5604 5605 /****************************************************************************/ 5606 /* Allocate memory and initialize the TX data structures. */ 5607 /* */ 5608 /* Returns: */ 5609 /* 0 for success, positive value for failure. */ 5610 /****************************************************************************/ 5611 static int 5612 bce_init_tx_chain(struct bce_softc *sc) 5613 { 5614 struct tx_bd *txbd; 5615 int i, rc = 0; 5616 5617 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5618 5619 /* Set the initial TX producer/consumer indices. */ 5620 sc->tx_prod = 0; 5621 sc->tx_cons = 0; 5622 sc->tx_prod_bseq = 0; 5623 sc->used_tx_bd = 0; 5624 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5625 DBRUN(sc->tx_hi_watermark = 0); 5626 DBRUN(sc->tx_full_count = 0); 5627 5628 /* 5629 * The NetXtreme II supports a linked-list structre called 5630 * a Buffer Descriptor Chain (or BD chain). A BD chain 5631 * consists of a series of 1 or more chain pages, each of which 5632 * consists of a fixed number of BD entries. 5633 * The last BD entry on each page is a pointer to the next page 5634 * in the chain, and the last pointer in the BD chain 5635 * points back to the beginning of the chain. 5636 */ 5637 5638 /* Set the TX next pointer chain entries. */ 5639 for (i = 0; i < sc->tx_pages; i++) { 5640 int j; 5641 5642 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5643 5644 /* Check if we've reached the last page. */ 5645 if (i == (sc->tx_pages - 1)) 5646 j = 0; 5647 else 5648 j = i + 1; 5649 5650 txbd->tx_bd_haddr_hi = 5651 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5652 txbd->tx_bd_haddr_lo = 5653 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5654 } 5655 5656 bce_init_tx_context(sc); 5657 5658 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5659 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5660 5661 return(rc); 5662 } 5663 5664 5665 /****************************************************************************/ 5666 /* Free memory and clear the TX data structures. */ 5667 /* */ 5668 /* Returns: */ 5669 /* Nothing. */ 5670 /****************************************************************************/ 5671 static void 5672 bce_free_tx_chain(struct bce_softc *sc) 5673 { 5674 int i; 5675 5676 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5677 5678 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5679 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5680 if (sc->tx_mbuf_ptr[i] != NULL) { 5681 if (sc->tx_mbuf_map[i] != NULL) 5682 bus_dmamap_sync(sc->tx_mbuf_tag, 5683 sc->tx_mbuf_map[i], 5684 BUS_DMASYNC_POSTWRITE); 5685 m_freem(sc->tx_mbuf_ptr[i]); 5686 sc->tx_mbuf_ptr[i] = NULL; 5687 DBRUN(sc->debug_tx_mbuf_alloc--); 5688 } 5689 } 5690 5691 /* Clear each TX chain page. */ 5692 for (i = 0; i < sc->tx_pages; i++) 5693 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5694 5695 sc->used_tx_bd = 0; 5696 5697 /* Check if we lost any mbufs in the process. */ 5698 DBRUNIF((sc->debug_tx_mbuf_alloc), 5699 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5700 "from tx chain!\n", __FILE__, __LINE__, 5701 sc->debug_tx_mbuf_alloc)); 5702 5703 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5704 } 5705 5706 5707 /****************************************************************************/ 5708 /* Initialize the RX context memory. */ 5709 /* */ 5710 /* Returns: */ 5711 /* Nothing */ 5712 /****************************************************************************/ 5713 static void 5714 bce_init_rx_context(struct bce_softc *sc) 5715 { 5716 u32 val; 5717 5718 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5719 5720 /* Init the type, size, and BD cache levels for the RX context. */ 5721 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5722 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5723 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5724 5725 /* 5726 * Set the level for generating pause frames 5727 * when the number of available rx_bd's gets 5728 * too low (the low watermark) and the level 5729 * when pause frames can be stopped (the high 5730 * watermark). 5731 */ 5732 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5733 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5734 u32 lo_water, hi_water; 5735 5736 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5737 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5738 } else { 5739 lo_water = 0; 5740 } 5741 5742 if (lo_water >= USABLE_RX_BD_ALLOC) { 5743 lo_water = 0; 5744 } 5745 5746 hi_water = USABLE_RX_BD_ALLOC / 4; 5747 5748 if (hi_water <= lo_water) { 5749 lo_water = 0; 5750 } 5751 5752 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5753 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5754 5755 if (hi_water > 0xf) 5756 hi_water = 0xf; 5757 else if (hi_water == 0) 5758 lo_water = 0; 5759 5760 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5761 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5762 } 5763 5764 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5765 5766 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5767 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5768 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5769 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5770 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5771 } 5772 5773 /* Point the hardware to the first page in the chain. */ 5774 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5775 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5776 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5777 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5778 5779 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5780 } 5781 5782 5783 /****************************************************************************/ 5784 /* Allocate memory and initialize the RX data structures. */ 5785 /* */ 5786 /* Returns: */ 5787 /* 0 for success, positive value for failure. */ 5788 /****************************************************************************/ 5789 static int 5790 bce_init_rx_chain(struct bce_softc *sc) 5791 { 5792 struct rx_bd *rxbd; 5793 int i, rc = 0; 5794 5795 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5796 BCE_VERBOSE_CTX); 5797 5798 /* Initialize the RX producer and consumer indices. */ 5799 sc->rx_prod = 0; 5800 sc->rx_cons = 0; 5801 sc->rx_prod_bseq = 0; 5802 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5803 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5804 5805 /* Initialize the RX next pointer chain entries. */ 5806 for (i = 0; i < sc->rx_pages; i++) { 5807 int j; 5808 5809 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5810 5811 /* Check if we've reached the last page. */ 5812 if (i == (sc->rx_pages - 1)) 5813 j = 0; 5814 else 5815 j = i + 1; 5816 5817 /* Setup the chain page pointers. */ 5818 rxbd->rx_bd_haddr_hi = 5819 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5820 rxbd->rx_bd_haddr_lo = 5821 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5822 } 5823 5824 /* Fill up the RX chain. */ 5825 bce_fill_rx_chain(sc); 5826 5827 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5828 DBRUN(sc->rx_empty_count = 0); 5829 for (i = 0; i < sc->rx_pages; i++) { 5830 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5831 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5832 } 5833 5834 bce_init_rx_context(sc); 5835 5836 DBRUNMSG(BCE_EXTREME_RECV, 5837 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5838 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5839 BCE_VERBOSE_CTX); 5840 5841 /* ToDo: Are there possible failure modes here? */ 5842 5843 return(rc); 5844 } 5845 5846 5847 /****************************************************************************/ 5848 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5849 /* occurs. */ 5850 /* */ 5851 /* Returns: */ 5852 /* Nothing */ 5853 /****************************************************************************/ 5854 static void 5855 bce_fill_rx_chain(struct bce_softc *sc) 5856 { 5857 u16 prod, prod_idx; 5858 u32 prod_bseq; 5859 5860 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5861 BCE_VERBOSE_CTX); 5862 5863 /* Get the RX chain producer indices. */ 5864 prod = sc->rx_prod; 5865 prod_bseq = sc->rx_prod_bseq; 5866 5867 /* Keep filling the RX chain until it's full. */ 5868 while (sc->free_rx_bd > 0) { 5869 prod_idx = RX_CHAIN_IDX(prod); 5870 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5871 /* Bail out if we can't add an mbuf to the chain. */ 5872 break; 5873 } 5874 prod = NEXT_RX_BD(prod); 5875 } 5876 5877 /* Save the RX chain producer indices. */ 5878 sc->rx_prod = prod; 5879 sc->rx_prod_bseq = prod_bseq; 5880 5881 /* We should never end up pointing to a next page pointer. */ 5882 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5883 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5884 __FUNCTION__, sc->rx_prod)); 5885 5886 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5887 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5888 BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); 5889 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + 5890 BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); 5891 5892 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5893 BCE_VERBOSE_CTX); 5894 } 5895 5896 5897 /****************************************************************************/ 5898 /* Free memory and clear the RX data structures. */ 5899 /* */ 5900 /* Returns: */ 5901 /* Nothing. */ 5902 /****************************************************************************/ 5903 static void 5904 bce_free_rx_chain(struct bce_softc *sc) 5905 { 5906 int i; 5907 5908 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5909 5910 /* Free any mbufs still in the RX mbuf chain. */ 5911 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5912 if (sc->rx_mbuf_ptr[i] != NULL) { 5913 if (sc->rx_mbuf_map[i] != NULL) 5914 bus_dmamap_sync(sc->rx_mbuf_tag, 5915 sc->rx_mbuf_map[i], 5916 BUS_DMASYNC_POSTREAD); 5917 m_freem(sc->rx_mbuf_ptr[i]); 5918 sc->rx_mbuf_ptr[i] = NULL; 5919 DBRUN(sc->debug_rx_mbuf_alloc--); 5920 } 5921 } 5922 5923 /* Clear each RX chain page. */ 5924 for (i = 0; i < sc->rx_pages; i++) 5925 if (sc->rx_bd_chain[i] != NULL) { 5926 bzero((char *)sc->rx_bd_chain[i], 5927 BCE_RX_CHAIN_PAGE_SZ); 5928 } 5929 5930 sc->free_rx_bd = sc->max_rx_bd; 5931 5932 /* Check if we lost any mbufs in the process. */ 5933 DBRUNIF((sc->debug_rx_mbuf_alloc), 5934 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5935 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5936 5937 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5938 } 5939 5940 5941 /****************************************************************************/ 5942 /* Allocate memory and initialize the page data structures. */ 5943 /* Assumes that bce_init_rx_chain() has not already been called. */ 5944 /* */ 5945 /* Returns: */ 5946 /* 0 for success, positive value for failure. */ 5947 /****************************************************************************/ 5948 static int 5949 bce_init_pg_chain(struct bce_softc *sc) 5950 { 5951 struct rx_bd *pgbd; 5952 int i, rc = 0; 5953 u32 val; 5954 5955 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5956 BCE_VERBOSE_CTX); 5957 5958 /* Initialize the page producer and consumer indices. */ 5959 sc->pg_prod = 0; 5960 sc->pg_cons = 0; 5961 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5962 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5963 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5964 DBRUN(sc->pg_empty_count = 0); 5965 5966 /* Initialize the page next pointer chain entries. */ 5967 for (i = 0; i < sc->pg_pages; i++) { 5968 int j; 5969 5970 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5971 5972 /* Check if we've reached the last page. */ 5973 if (i == (sc->pg_pages - 1)) 5974 j = 0; 5975 else 5976 j = i + 1; 5977 5978 /* Setup the chain page pointers. */ 5979 pgbd->rx_bd_haddr_hi = 5980 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5981 pgbd->rx_bd_haddr_lo = 5982 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5983 } 5984 5985 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5986 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5987 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 5988 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5989 5990 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5991 5992 /* Configure the rx_bd and page chain mbuf cluster size. */ 5993 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5994 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5995 5996 /* Configure the context reserved for jumbo support. */ 5997 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5998 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5999 6000 /* Point the hardware to the first page in the page chain. */ 6001 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 6002 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 6003 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 6004 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 6005 6006 /* Fill up the page chain. */ 6007 bce_fill_pg_chain(sc); 6008 6009 for (i = 0; i < sc->pg_pages; i++) { 6010 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6011 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6012 } 6013 6014 DBRUNMSG(BCE_EXTREME_RECV, 6015 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6016 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6017 BCE_VERBOSE_CTX); 6018 return(rc); 6019 } 6020 6021 6022 /****************************************************************************/ 6023 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 6024 /* occurs. */ 6025 /* */ 6026 /* Returns: */ 6027 /* Nothing */ 6028 /****************************************************************************/ 6029 static void 6030 bce_fill_pg_chain(struct bce_softc *sc) 6031 { 6032 u16 prod, prod_idx; 6033 6034 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6035 BCE_VERBOSE_CTX); 6036 6037 /* Get the page chain prodcuer index. */ 6038 prod = sc->pg_prod; 6039 6040 /* Keep filling the page chain until it's full. */ 6041 while (sc->free_pg_bd > 0) { 6042 prod_idx = PG_CHAIN_IDX(prod); 6043 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 6044 /* Bail out if we can't add an mbuf to the chain. */ 6045 break; 6046 } 6047 prod = NEXT_PG_BD(prod); 6048 } 6049 6050 /* Save the page chain producer index. */ 6051 sc->pg_prod = prod; 6052 6053 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6054 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6055 __FUNCTION__, sc->pg_prod)); 6056 6057 /* 6058 * Write the mailbox and tell the chip about 6059 * the new rx_bd's in the page chain. 6060 */ 6061 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 6062 BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); 6063 6064 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6065 BCE_VERBOSE_CTX); 6066 } 6067 6068 6069 /****************************************************************************/ 6070 /* Free memory and clear the RX data structures. */ 6071 /* */ 6072 /* Returns: */ 6073 /* Nothing. */ 6074 /****************************************************************************/ 6075 static void 6076 bce_free_pg_chain(struct bce_softc *sc) 6077 { 6078 int i; 6079 6080 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6081 6082 /* Free any mbufs still in the mbuf page chain. */ 6083 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6084 if (sc->pg_mbuf_ptr[i] != NULL) { 6085 if (sc->pg_mbuf_map[i] != NULL) 6086 bus_dmamap_sync(sc->pg_mbuf_tag, 6087 sc->pg_mbuf_map[i], 6088 BUS_DMASYNC_POSTREAD); 6089 m_freem(sc->pg_mbuf_ptr[i]); 6090 sc->pg_mbuf_ptr[i] = NULL; 6091 DBRUN(sc->debug_pg_mbuf_alloc--); 6092 } 6093 } 6094 6095 /* Clear each page chain pages. */ 6096 for (i = 0; i < sc->pg_pages; i++) 6097 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6098 6099 sc->free_pg_bd = sc->max_pg_bd; 6100 6101 /* Check if we lost any mbufs in the process. */ 6102 DBRUNIF((sc->debug_pg_mbuf_alloc), 6103 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6104 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6105 6106 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6107 } 6108 6109 6110 /****************************************************************************/ 6111 /* Set media options. */ 6112 /* */ 6113 /* Returns: */ 6114 /* 0 for success, positive value for failure. */ 6115 /****************************************************************************/ 6116 static int 6117 bce_ifmedia_upd(struct ifnet *ifp) 6118 { 6119 struct bce_softc *sc = ifp->if_softc; 6120 int error; 6121 6122 DBENTER(BCE_VERBOSE); 6123 6124 BCE_LOCK(sc); 6125 error = bce_ifmedia_upd_locked(ifp); 6126 BCE_UNLOCK(sc); 6127 6128 DBEXIT(BCE_VERBOSE); 6129 return (error); 6130 } 6131 6132 6133 /****************************************************************************/ 6134 /* Set media options. */ 6135 /* */ 6136 /* Returns: */ 6137 /* Nothing. */ 6138 /****************************************************************************/ 6139 static int 6140 bce_ifmedia_upd_locked(struct ifnet *ifp) 6141 { 6142 struct bce_softc *sc = ifp->if_softc; 6143 struct mii_data *mii; 6144 struct mii_softc *miisc; 6145 int error; 6146 6147 DBENTER(BCE_VERBOSE_PHY); 6148 6149 error = 0; 6150 BCE_LOCK_ASSERT(sc); 6151 6152 mii = device_get_softc(sc->bce_miibus); 6153 6154 /* Make sure the MII bus has been enumerated. */ 6155 if (mii) { 6156 sc->bce_link_up = FALSE; 6157 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6158 PHY_RESET(miisc); 6159 error = mii_mediachg(mii); 6160 } 6161 6162 DBEXIT(BCE_VERBOSE_PHY); 6163 return (error); 6164 } 6165 6166 6167 /****************************************************************************/ 6168 /* Reports current media status. */ 6169 /* */ 6170 /* Returns: */ 6171 /* Nothing. */ 6172 /****************************************************************************/ 6173 static void 6174 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6175 { 6176 struct bce_softc *sc = ifp->if_softc; 6177 struct mii_data *mii; 6178 6179 DBENTER(BCE_VERBOSE_PHY); 6180 6181 BCE_LOCK(sc); 6182 6183 if ((ifp->if_flags & IFF_UP) == 0) { 6184 BCE_UNLOCK(sc); 6185 return; 6186 } 6187 mii = device_get_softc(sc->bce_miibus); 6188 6189 mii_pollstat(mii); 6190 ifmr->ifm_active = mii->mii_media_active; 6191 ifmr->ifm_status = mii->mii_media_status; 6192 6193 BCE_UNLOCK(sc); 6194 6195 DBEXIT(BCE_VERBOSE_PHY); 6196 } 6197 6198 6199 /****************************************************************************/ 6200 /* Handles PHY generated interrupt events. */ 6201 /* */ 6202 /* Returns: */ 6203 /* Nothing. */ 6204 /****************************************************************************/ 6205 static void 6206 bce_phy_intr(struct bce_softc *sc) 6207 { 6208 u32 new_link_state, old_link_state; 6209 6210 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6211 6212 DBRUN(sc->phy_interrupts++); 6213 6214 new_link_state = sc->status_block->status_attn_bits & 6215 STATUS_ATTN_BITS_LINK_STATE; 6216 old_link_state = sc->status_block->status_attn_bits_ack & 6217 STATUS_ATTN_BITS_LINK_STATE; 6218 6219 /* Handle any changes if the link state has changed. */ 6220 if (new_link_state != old_link_state) { 6221 6222 /* Update the status_attn_bits_ack field. */ 6223 if (new_link_state) { 6224 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6225 STATUS_ATTN_BITS_LINK_STATE); 6226 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6227 __FUNCTION__); 6228 } 6229 else { 6230 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6231 STATUS_ATTN_BITS_LINK_STATE); 6232 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6233 __FUNCTION__); 6234 } 6235 6236 /* 6237 * Assume link is down and allow 6238 * tick routine to update the state 6239 * based on the actual media state. 6240 */ 6241 sc->bce_link_up = FALSE; 6242 callout_stop(&sc->bce_tick_callout); 6243 bce_tick(sc); 6244 } 6245 6246 /* Acknowledge the link change interrupt. */ 6247 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6248 6249 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6250 } 6251 6252 6253 /****************************************************************************/ 6254 /* Reads the receive consumer value from the status block (skipping over */ 6255 /* chain page pointer if necessary). */ 6256 /* */ 6257 /* Returns: */ 6258 /* hw_cons */ 6259 /****************************************************************************/ 6260 static inline u16 6261 bce_get_hw_rx_cons(struct bce_softc *sc) 6262 { 6263 u16 hw_cons; 6264 6265 rmb(); 6266 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6267 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6268 hw_cons++; 6269 6270 return hw_cons; 6271 } 6272 6273 /****************************************************************************/ 6274 /* Handles received frame interrupt events. */ 6275 /* */ 6276 /* Returns: */ 6277 /* Nothing. */ 6278 /****************************************************************************/ 6279 static void 6280 bce_rx_intr(struct bce_softc *sc) 6281 { 6282 struct ifnet *ifp = sc->bce_ifp; 6283 struct l2_fhdr *l2fhdr; 6284 struct ether_vlan_header *vh; 6285 unsigned int pkt_len; 6286 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6287 u32 status; 6288 unsigned int rem_len; 6289 u16 sw_pg_cons, sw_pg_cons_idx; 6290 6291 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6292 DBRUN(sc->interrupts_rx++); 6293 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6294 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6295 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6296 6297 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6298 for (int i = 0; i < sc->rx_pages; i++) 6299 bus_dmamap_sync(sc->rx_bd_chain_tag, 6300 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6301 6302 /* Prepare the page chain pages to be accessed by the host CPU. */ 6303 if (bce_hdr_split == TRUE) { 6304 for (int i = 0; i < sc->pg_pages; i++) 6305 bus_dmamap_sync(sc->pg_bd_chain_tag, 6306 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6307 } 6308 6309 /* Get the hardware's view of the RX consumer index. */ 6310 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6311 6312 /* Get working copies of the driver's view of the consumer indices. */ 6313 sw_rx_cons = sc->rx_cons; 6314 sw_pg_cons = sc->pg_cons; 6315 6316 /* Update some debug statistics counters */ 6317 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6318 sc->rx_low_watermark = sc->free_rx_bd); 6319 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6320 sc->rx_empty_count++); 6321 6322 /* Scan through the receive chain as long as there is work to do */ 6323 /* ToDo: Consider setting a limit on the number of packets processed. */ 6324 rmb(); 6325 while (sw_rx_cons != hw_rx_cons) { 6326 struct mbuf *m0; 6327 6328 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6329 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6330 6331 /* Unmap the mbuf from DMA space. */ 6332 bus_dmamap_sync(sc->rx_mbuf_tag, 6333 sc->rx_mbuf_map[sw_rx_cons_idx], 6334 BUS_DMASYNC_POSTREAD); 6335 bus_dmamap_unload(sc->rx_mbuf_tag, 6336 sc->rx_mbuf_map[sw_rx_cons_idx]); 6337 6338 /* Remove the mbuf from the RX chain. */ 6339 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6340 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6341 DBRUN(sc->debug_rx_mbuf_alloc--); 6342 sc->free_rx_bd++; 6343 6344 if(m0 == NULL) { 6345 DBPRINT(sc, BCE_EXTREME_RECV, 6346 "%s(): Oops! Empty mbuf pointer " 6347 "found in sc->rx_mbuf_ptr[0x%04X]!\n", 6348 __FUNCTION__, sw_rx_cons_idx); 6349 goto bce_rx_int_next_rx; 6350 } 6351 6352 /* 6353 * Frames received on the NetXteme II are prepended 6354 * with an l2_fhdr structure which provides status 6355 * information about the received frame (including 6356 * VLAN tags and checksum info). The frames are 6357 * also automatically adjusted to word align the IP 6358 * header (i.e. two null bytes are inserted before 6359 * the Ethernet header). As a result the data 6360 * DMA'd by the controller into the mbuf looks 6361 * like this: 6362 * 6363 * +---------+-----+---------------------+-----+ 6364 * | l2_fhdr | pad | packet data | FCS | 6365 * +---------+-----+---------------------+-----+ 6366 * 6367 * The l2_fhdr needs to be checked and skipped and 6368 * the FCS needs to be stripped before sending the 6369 * packet up the stack. 6370 */ 6371 l2fhdr = mtod(m0, struct l2_fhdr *); 6372 6373 /* Get the packet data + FCS length and the status. */ 6374 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6375 status = l2fhdr->l2_fhdr_status; 6376 6377 /* 6378 * Skip over the l2_fhdr and pad, resulting in the 6379 * following data in the mbuf: 6380 * +---------------------+-----+ 6381 * | packet data | FCS | 6382 * +---------------------+-----+ 6383 */ 6384 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6385 6386 /* 6387 * When split header mode is used, an ethernet frame 6388 * may be split across the receive chain and the 6389 * page chain. If that occurs an mbuf cluster must be 6390 * reassembled from the individual mbuf pieces. 6391 */ 6392 if (bce_hdr_split == TRUE) { 6393 /* 6394 * Check whether the received frame fits in a single 6395 * mbuf or not (i.e. packet data + FCS <= 6396 * sc->rx_bd_mbuf_data_len bytes). 6397 */ 6398 if (pkt_len > m0->m_len) { 6399 /* 6400 * The received frame is larger than a single mbuf. 6401 * If the frame was a TCP frame then only the TCP 6402 * header is placed in the mbuf, the remaining 6403 * payload (including FCS) is placed in the page 6404 * chain, the SPLIT flag is set, and the header 6405 * length is placed in the IP checksum field. 6406 * If the frame is not a TCP frame then the mbuf 6407 * is filled and the remaining bytes are placed 6408 * in the page chain. 6409 */ 6410 6411 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6412 "packet.\n", __FUNCTION__); 6413 DBRUN(sc->split_header_frames_rcvd++); 6414 6415 /* 6416 * When the page chain is enabled and the TCP 6417 * header has been split from the TCP payload, 6418 * the ip_xsum structure will reflect the length 6419 * of the TCP header, not the IP checksum. Set 6420 * the packet length of the mbuf accordingly. 6421 */ 6422 if (status & L2_FHDR_STATUS_SPLIT) { 6423 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6424 DBRUN(sc->split_header_tcp_frames_rcvd++); 6425 } 6426 6427 rem_len = pkt_len - m0->m_len; 6428 6429 /* Pull mbufs off the page chain for any remaining data. */ 6430 while (rem_len > 0) { 6431 struct mbuf *m_pg; 6432 6433 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6434 6435 /* Remove the mbuf from the page chain. */ 6436 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6437 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6438 DBRUN(sc->debug_pg_mbuf_alloc--); 6439 sc->free_pg_bd++; 6440 6441 /* Unmap the page chain mbuf from DMA space. */ 6442 bus_dmamap_sync(sc->pg_mbuf_tag, 6443 sc->pg_mbuf_map[sw_pg_cons_idx], 6444 BUS_DMASYNC_POSTREAD); 6445 bus_dmamap_unload(sc->pg_mbuf_tag, 6446 sc->pg_mbuf_map[sw_pg_cons_idx]); 6447 6448 /* Adjust the mbuf length. */ 6449 if (rem_len < m_pg->m_len) { 6450 /* The mbuf chain is complete. */ 6451 m_pg->m_len = rem_len; 6452 rem_len = 0; 6453 } else { 6454 /* More packet data is waiting. */ 6455 rem_len -= m_pg->m_len; 6456 } 6457 6458 /* Concatenate the mbuf cluster to the mbuf. */ 6459 m_cat(m0, m_pg); 6460 6461 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6462 } 6463 6464 /* Set the total packet length. */ 6465 m0->m_pkthdr.len = pkt_len; 6466 6467 } else { 6468 /* 6469 * The received packet is small and fits in a 6470 * single mbuf (i.e. the l2_fhdr + pad + packet + 6471 * FCS <= MHLEN). In other words, the packet is 6472 * 154 bytes or less in size. 6473 */ 6474 6475 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6476 "packet.\n", __FUNCTION__); 6477 6478 /* Set the total packet length. */ 6479 m0->m_pkthdr.len = m0->m_len = pkt_len; 6480 } 6481 } else 6482 /* Set the total packet length. */ 6483 m0->m_pkthdr.len = m0->m_len = pkt_len; 6484 6485 /* Remove the trailing Ethernet FCS. */ 6486 m_adj(m0, -ETHER_CRC_LEN); 6487 6488 /* Check that the resulting mbuf chain is valid. */ 6489 DBRUN(m_sanity(m0, FALSE)); 6490 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6491 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6492 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6493 m_print(m0, 128)); 6494 6495 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6496 sc->l2fhdr_error_sim_count++; 6497 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6498 6499 /* Check the received frame for errors. */ 6500 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6501 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6502 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6503 6504 /* Log the error and release the mbuf. */ 6505 ifp->if_ierrors++; 6506 sc->l2fhdr_error_count++; 6507 6508 m_freem(m0); 6509 m0 = NULL; 6510 goto bce_rx_int_next_rx; 6511 } 6512 6513 /* Send the packet to the appropriate interface. */ 6514 m0->m_pkthdr.rcvif = ifp; 6515 6516 /* Assume no hardware checksum. */ 6517 m0->m_pkthdr.csum_flags = 0; 6518 6519 /* Validate the checksum if offload enabled. */ 6520 if (ifp->if_capenable & IFCAP_RXCSUM) { 6521 6522 /* Check for an IP datagram. */ 6523 if (!(status & L2_FHDR_STATUS_SPLIT) && 6524 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6525 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6526 DBRUN(sc->csum_offload_ip++); 6527 /* Check if the IP checksum is valid. */ 6528 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6529 m0->m_pkthdr.csum_flags |= 6530 CSUM_IP_VALID; 6531 } 6532 6533 /* Check for a valid TCP/UDP frame. */ 6534 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6535 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6536 6537 /* Check for a good TCP/UDP checksum. */ 6538 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6539 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6540 DBRUN(sc->csum_offload_tcp_udp++); 6541 m0->m_pkthdr.csum_data = 6542 l2fhdr->l2_fhdr_tcp_udp_xsum; 6543 m0->m_pkthdr.csum_flags |= 6544 (CSUM_DATA_VALID 6545 | CSUM_PSEUDO_HDR); 6546 } 6547 } 6548 } 6549 6550 /* Attach the VLAN tag. */ 6551 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6552 DBRUN(sc->vlan_tagged_frames_rcvd++); 6553 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6554 DBRUN(sc->vlan_tagged_frames_stripped++); 6555 #if __FreeBSD_version < 700000 6556 VLAN_INPUT_TAG(ifp, m0, 6557 l2fhdr->l2_fhdr_vlan_tag, continue); 6558 #else 6559 m0->m_pkthdr.ether_vtag = 6560 l2fhdr->l2_fhdr_vlan_tag; 6561 m0->m_flags |= M_VLANTAG; 6562 #endif 6563 } else { 6564 /* 6565 * bce(4) controllers can't disable VLAN 6566 * tag stripping if management firmware 6567 * (ASF/IPMI/UMP) is running. So we always 6568 * strip VLAN tag and manually reconstruct 6569 * the VLAN frame by appending stripped 6570 * VLAN tag in driver if VLAN tag stripping 6571 * was disabled. 6572 * 6573 * TODO: LLC SNAP handling. 6574 */ 6575 bcopy(mtod(m0, uint8_t *), 6576 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6577 ETHER_ADDR_LEN * 2); 6578 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6579 vh = mtod(m0, struct ether_vlan_header *); 6580 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6581 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6582 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6583 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6584 } 6585 } 6586 6587 /* Increment received packet statistics. */ 6588 ifp->if_ipackets++; 6589 6590 bce_rx_int_next_rx: 6591 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6592 6593 /* If we have a packet, pass it up the stack */ 6594 if (m0) { 6595 /* Make sure we don't lose our place when we release the lock. */ 6596 sc->rx_cons = sw_rx_cons; 6597 sc->pg_cons = sw_pg_cons; 6598 6599 BCE_UNLOCK(sc); 6600 (*ifp->if_input)(ifp, m0); 6601 BCE_LOCK(sc); 6602 6603 /* Recover our place. */ 6604 sw_rx_cons = sc->rx_cons; 6605 sw_pg_cons = sc->pg_cons; 6606 } 6607 6608 /* Refresh hw_cons to see if there's new work */ 6609 if (sw_rx_cons == hw_rx_cons) 6610 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6611 } 6612 6613 /* No new packets. Refill the page chain. */ 6614 if (bce_hdr_split == TRUE) { 6615 sc->pg_cons = sw_pg_cons; 6616 bce_fill_pg_chain(sc); 6617 } 6618 6619 /* No new packets. Refill the RX chain. */ 6620 sc->rx_cons = sw_rx_cons; 6621 bce_fill_rx_chain(sc); 6622 6623 /* Prepare the page chain pages to be accessed by the NIC. */ 6624 for (int i = 0; i < sc->rx_pages; i++) 6625 bus_dmamap_sync(sc->rx_bd_chain_tag, 6626 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6627 6628 if (bce_hdr_split == TRUE) { 6629 for (int i = 0; i < sc->pg_pages; i++) 6630 bus_dmamap_sync(sc->pg_bd_chain_tag, 6631 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6632 } 6633 6634 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6635 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6636 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6637 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6638 } 6639 6640 6641 /****************************************************************************/ 6642 /* Reads the transmit consumer value from the status block (skipping over */ 6643 /* chain page pointer if necessary). */ 6644 /* */ 6645 /* Returns: */ 6646 /* hw_cons */ 6647 /****************************************************************************/ 6648 static inline u16 6649 bce_get_hw_tx_cons(struct bce_softc *sc) 6650 { 6651 u16 hw_cons; 6652 6653 mb(); 6654 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6655 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6656 hw_cons++; 6657 6658 return hw_cons; 6659 } 6660 6661 6662 /****************************************************************************/ 6663 /* Handles transmit completion interrupt events. */ 6664 /* */ 6665 /* Returns: */ 6666 /* Nothing. */ 6667 /****************************************************************************/ 6668 static void 6669 bce_tx_intr(struct bce_softc *sc) 6670 { 6671 struct ifnet *ifp = sc->bce_ifp; 6672 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6673 6674 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6675 DBRUN(sc->interrupts_tx++); 6676 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6677 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6678 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6679 6680 BCE_LOCK_ASSERT(sc); 6681 6682 /* Get the hardware's view of the TX consumer index. */ 6683 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6684 sw_tx_cons = sc->tx_cons; 6685 6686 /* Prevent speculative reads of the status block. */ 6687 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6688 BUS_SPACE_BARRIER_READ); 6689 6690 /* Cycle through any completed TX chain page entries. */ 6691 while (sw_tx_cons != hw_tx_cons) { 6692 #ifdef BCE_DEBUG 6693 struct tx_bd *txbd = NULL; 6694 #endif 6695 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6696 6697 DBPRINT(sc, BCE_INFO_SEND, 6698 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6699 "sw_tx_chain_cons = 0x%04X\n", 6700 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6701 6702 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6703 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6704 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6705 (int) MAX_TX_BD_ALLOC); 6706 bce_breakpoint(sc)); 6707 6708 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6709 [TX_IDX(sw_tx_chain_cons)]); 6710 6711 DBRUNIF((txbd == NULL), 6712 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6713 __FILE__, __LINE__, sw_tx_chain_cons); 6714 bce_breakpoint(sc)); 6715 6716 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6717 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6718 6719 /* 6720 * Free the associated mbuf. Remember 6721 * that only the last tx_bd of a packet 6722 * has an mbuf pointer and DMA map. 6723 */ 6724 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6725 6726 /* Validate that this is the last tx_bd. */ 6727 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6728 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6729 "txmbuf == NULL!\n", __FILE__, __LINE__); 6730 bce_breakpoint(sc)); 6731 6732 DBRUNMSG(BCE_INFO_SEND, 6733 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6734 "from tx_bd[0x%04X]\n", __FUNCTION__, 6735 sw_tx_chain_cons)); 6736 6737 /* Unmap the mbuf. */ 6738 bus_dmamap_unload(sc->tx_mbuf_tag, 6739 sc->tx_mbuf_map[sw_tx_chain_cons]); 6740 6741 /* Free the mbuf. */ 6742 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6743 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6744 DBRUN(sc->debug_tx_mbuf_alloc--); 6745 6746 ifp->if_opackets++; 6747 } 6748 6749 sc->used_tx_bd--; 6750 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6751 6752 /* Refresh hw_cons to see if there's new work. */ 6753 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6754 6755 /* Prevent speculative reads of the status block. */ 6756 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6757 BUS_SPACE_BARRIER_READ); 6758 } 6759 6760 /* Clear the TX timeout timer. */ 6761 sc->watchdog_timer = 0; 6762 6763 /* Clear the tx hardware queue full flag. */ 6764 if (sc->used_tx_bd < sc->max_tx_bd) { 6765 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6766 DBPRINT(sc, BCE_INFO_SEND, 6767 "%s(): Open TX chain! %d/%d (used/total)\n", 6768 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6769 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6770 } 6771 6772 sc->tx_cons = sw_tx_cons; 6773 6774 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6775 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6776 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6777 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6778 } 6779 6780 6781 /****************************************************************************/ 6782 /* Disables interrupt generation. */ 6783 /* */ 6784 /* Returns: */ 6785 /* Nothing. */ 6786 /****************************************************************************/ 6787 static void 6788 bce_disable_intr(struct bce_softc *sc) 6789 { 6790 DBENTER(BCE_VERBOSE_INTR); 6791 6792 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6793 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6794 6795 DBEXIT(BCE_VERBOSE_INTR); 6796 } 6797 6798 6799 /****************************************************************************/ 6800 /* Enables interrupt generation. */ 6801 /* */ 6802 /* Returns: */ 6803 /* Nothing. */ 6804 /****************************************************************************/ 6805 static void 6806 bce_enable_intr(struct bce_softc *sc, int coal_now) 6807 { 6808 DBENTER(BCE_VERBOSE_INTR); 6809 6810 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6811 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6812 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6813 6814 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6815 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6816 6817 /* Force an immediate interrupt (whether there is new data or not). */ 6818 if (coal_now) 6819 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6820 6821 DBEXIT(BCE_VERBOSE_INTR); 6822 } 6823 6824 6825 /****************************************************************************/ 6826 /* Handles controller initialization. */ 6827 /* */ 6828 /* Returns: */ 6829 /* Nothing. */ 6830 /****************************************************************************/ 6831 static void 6832 bce_init_locked(struct bce_softc *sc) 6833 { 6834 struct ifnet *ifp; 6835 u32 ether_mtu = 0; 6836 6837 DBENTER(BCE_VERBOSE_RESET); 6838 6839 BCE_LOCK_ASSERT(sc); 6840 6841 ifp = sc->bce_ifp; 6842 6843 /* Check if the driver is still running and bail out if it is. */ 6844 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6845 goto bce_init_locked_exit; 6846 6847 bce_stop(sc); 6848 6849 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6850 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6851 __FILE__, __LINE__); 6852 goto bce_init_locked_exit; 6853 } 6854 6855 if (bce_chipinit(sc)) { 6856 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6857 __FILE__, __LINE__); 6858 goto bce_init_locked_exit; 6859 } 6860 6861 if (bce_blockinit(sc)) { 6862 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6863 __FILE__, __LINE__); 6864 goto bce_init_locked_exit; 6865 } 6866 6867 /* Load our MAC address. */ 6868 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6869 bce_set_mac_addr(sc); 6870 6871 /* 6872 * Calculate and program the hardware Ethernet MTU 6873 * size. Be generous on the receive if we have room 6874 * and allowed by the user. 6875 */ 6876 if (bce_strict_rx_mtu == TRUE) 6877 ether_mtu = ifp->if_mtu; 6878 else { 6879 if (bce_hdr_split == TRUE) { 6880 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + 6881 sc->pg_bd_mbuf_alloc_size)) 6882 ether_mtu = sc->rx_bd_mbuf_data_len + 6883 sc->pg_bd_mbuf_alloc_size; 6884 else 6885 ether_mtu = ifp->if_mtu; 6886 } else { 6887 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6888 ether_mtu = sc->rx_bd_mbuf_data_len; 6889 else 6890 ether_mtu = ifp->if_mtu; 6891 } 6892 } 6893 6894 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6895 6896 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 6897 __FUNCTION__, ether_mtu); 6898 6899 /* Program the mtu, enabling jumbo frame support if necessary. */ 6900 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6901 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6902 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6903 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6904 else 6905 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6906 6907 /* Program appropriate promiscuous/multicast filtering. */ 6908 bce_set_rx_mode(sc); 6909 6910 if (bce_hdr_split == TRUE) { 6911 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6912 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6913 6914 /* Init page buffer descriptor chain. */ 6915 bce_init_pg_chain(sc); 6916 } 6917 6918 /* Init RX buffer descriptor chain. */ 6919 bce_init_rx_chain(sc); 6920 6921 /* Init TX buffer descriptor chain. */ 6922 bce_init_tx_chain(sc); 6923 6924 /* Enable host interrupts. */ 6925 bce_enable_intr(sc, 1); 6926 6927 bce_ifmedia_upd_locked(ifp); 6928 6929 /* Let the OS know the driver is up and running. */ 6930 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6931 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6932 6933 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6934 6935 bce_init_locked_exit: 6936 DBEXIT(BCE_VERBOSE_RESET); 6937 } 6938 6939 6940 /****************************************************************************/ 6941 /* Initialize the controller just enough so that any management firmware */ 6942 /* running on the device will continue to operate correctly. */ 6943 /* */ 6944 /* Returns: */ 6945 /* Nothing. */ 6946 /****************************************************************************/ 6947 static void 6948 bce_mgmt_init_locked(struct bce_softc *sc) 6949 { 6950 struct ifnet *ifp; 6951 6952 DBENTER(BCE_VERBOSE_RESET); 6953 6954 BCE_LOCK_ASSERT(sc); 6955 6956 /* Bail out if management firmware is not running. */ 6957 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6958 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6959 "No management firmware running...\n"); 6960 goto bce_mgmt_init_locked_exit; 6961 } 6962 6963 ifp = sc->bce_ifp; 6964 6965 /* Enable all critical blocks in the MAC. */ 6966 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6967 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6968 DELAY(20); 6969 6970 bce_ifmedia_upd_locked(ifp); 6971 6972 bce_mgmt_init_locked_exit: 6973 DBEXIT(BCE_VERBOSE_RESET); 6974 } 6975 6976 6977 /****************************************************************************/ 6978 /* Handles controller initialization when called from an unlocked routine. */ 6979 /* */ 6980 /* Returns: */ 6981 /* Nothing. */ 6982 /****************************************************************************/ 6983 static void 6984 bce_init(void *xsc) 6985 { 6986 struct bce_softc *sc = xsc; 6987 6988 DBENTER(BCE_VERBOSE_RESET); 6989 6990 BCE_LOCK(sc); 6991 bce_init_locked(sc); 6992 BCE_UNLOCK(sc); 6993 6994 DBEXIT(BCE_VERBOSE_RESET); 6995 } 6996 6997 6998 /****************************************************************************/ 6999 /* Modifies an mbuf for TSO on the hardware. */ 7000 /* */ 7001 /* Returns: */ 7002 /* Pointer to a modified mbuf. */ 7003 /****************************************************************************/ 7004 static struct mbuf * 7005 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7006 { 7007 struct mbuf *m; 7008 struct ether_header *eh; 7009 struct ip *ip; 7010 struct tcphdr *th; 7011 u16 etype; 7012 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7013 7014 DBRUN(sc->tso_frames_requested++); 7015 7016 /* Controller may modify mbuf chains. */ 7017 if (M_WRITABLE(*m_head) == 0) { 7018 m = m_dup(*m_head, M_DONTWAIT); 7019 m_freem(*m_head); 7020 if (m == NULL) { 7021 sc->mbuf_alloc_failed_count++; 7022 *m_head = NULL; 7023 return (NULL); 7024 } 7025 *m_head = m; 7026 } 7027 7028 /* 7029 * For TSO the controller needs two pieces of info, 7030 * the MSS and the IP+TCP options length. 7031 */ 7032 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7033 if (m == NULL) { 7034 *m_head = NULL; 7035 return (NULL); 7036 } 7037 eh = mtod(m, struct ether_header *); 7038 etype = ntohs(eh->ether_type); 7039 7040 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7041 switch (etype) { 7042 case ETHERTYPE_IP: 7043 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7044 /* TSO only supported for TCP protocol. */ 7045 if (ip->ip_p != IPPROTO_TCP) { 7046 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7047 __FILE__, __LINE__); 7048 m_freem(*m_head); 7049 *m_head = NULL; 7050 return (NULL); 7051 } 7052 7053 /* Get IP header length in bytes (min 20) */ 7054 ip_hlen = ip->ip_hl << 2; 7055 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7056 sizeof(struct tcphdr)); 7057 if (m == NULL) { 7058 *m_head = NULL; 7059 return (NULL); 7060 } 7061 7062 /* Get the TCP header length in bytes (min 20) */ 7063 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7064 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7065 tcp_hlen = (th->th_off << 2); 7066 7067 /* Make sure all IP/TCP options live in the same buffer. */ 7068 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7069 tcp_hlen); 7070 if (m == NULL) { 7071 *m_head = NULL; 7072 return (NULL); 7073 } 7074 7075 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7076 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7077 ip_len = ip->ip_len; 7078 ip->ip_len = 0; 7079 ip->ip_sum = 0; 7080 break; 7081 case ETHERTYPE_IPV6: 7082 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7083 __FILE__, __LINE__); 7084 m_freem(*m_head); 7085 *m_head = NULL; 7086 return (NULL); 7087 /* NOT REACHED */ 7088 default: 7089 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7090 __FILE__, __LINE__); 7091 m_freem(*m_head); 7092 *m_head = NULL; 7093 return (NULL); 7094 } 7095 7096 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7097 7098 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7099 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7100 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7101 tcp_hlen, ip_len); 7102 7103 /* Set the LSO flag in the TX BD */ 7104 *flags |= TX_BD_FLAGS_SW_LSO; 7105 7106 /* Set the length of IP + TCP options (in 32 bit words) */ 7107 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7108 sizeof(struct tcphdr)) >> 2) << 8); 7109 7110 DBRUN(sc->tso_frames_completed++); 7111 return (*m_head); 7112 } 7113 7114 7115 /****************************************************************************/ 7116 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7117 /* memory visible to the controller. */ 7118 /* */ 7119 /* Returns: */ 7120 /* 0 for success, positive value for failure. */ 7121 /* Modified: */ 7122 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7123 /****************************************************************************/ 7124 static int 7125 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7126 { 7127 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7128 bus_dmamap_t map; 7129 struct tx_bd *txbd = NULL; 7130 struct mbuf *m0; 7131 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7132 u32 prod_bseq; 7133 7134 #ifdef BCE_DEBUG 7135 u16 debug_prod; 7136 #endif 7137 7138 int i, error, nsegs, rc = 0; 7139 7140 DBENTER(BCE_VERBOSE_SEND); 7141 7142 /* Make sure we have room in the TX chain. */ 7143 if (sc->used_tx_bd >= sc->max_tx_bd) 7144 goto bce_tx_encap_exit; 7145 7146 /* Transfer any checksum offload flags to the bd. */ 7147 m0 = *m_head; 7148 if (m0->m_pkthdr.csum_flags) { 7149 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7150 m0 = bce_tso_setup(sc, m_head, &flags); 7151 if (m0 == NULL) { 7152 DBRUN(sc->tso_frames_failed++); 7153 goto bce_tx_encap_exit; 7154 } 7155 mss = htole16(m0->m_pkthdr.tso_segsz); 7156 } else { 7157 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7158 flags |= TX_BD_FLAGS_IP_CKSUM; 7159 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7160 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7161 } 7162 } 7163 7164 /* Transfer any VLAN tags to the bd. */ 7165 if (m0->m_flags & M_VLANTAG) { 7166 flags |= TX_BD_FLAGS_VLAN_TAG; 7167 vlan_tag = m0->m_pkthdr.ether_vtag; 7168 } 7169 7170 /* Map the mbuf into DMAable memory. */ 7171 prod = sc->tx_prod; 7172 chain_prod = TX_CHAIN_IDX(prod); 7173 map = sc->tx_mbuf_map[chain_prod]; 7174 7175 /* Map the mbuf into our DMA address space. */ 7176 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7177 segs, &nsegs, BUS_DMA_NOWAIT); 7178 7179 /* Check if the DMA mapping was successful */ 7180 if (error == EFBIG) { 7181 sc->mbuf_frag_count++; 7182 7183 /* Try to defrag the mbuf. */ 7184 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 7185 if (m0 == NULL) { 7186 /* Defrag was unsuccessful */ 7187 m_freem(*m_head); 7188 *m_head = NULL; 7189 sc->mbuf_alloc_failed_count++; 7190 rc = ENOBUFS; 7191 goto bce_tx_encap_exit; 7192 } 7193 7194 /* Defrag was successful, try mapping again */ 7195 *m_head = m0; 7196 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7197 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7198 7199 /* Still getting an error after a defrag. */ 7200 if (error == ENOMEM) { 7201 /* Insufficient DMA buffers available. */ 7202 sc->dma_map_addr_tx_failed_count++; 7203 rc = error; 7204 goto bce_tx_encap_exit; 7205 } else if (error != 0) { 7206 /* Release it and return an error. */ 7207 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7208 "TX chain!\n", __FILE__, __LINE__); 7209 m_freem(m0); 7210 *m_head = NULL; 7211 sc->dma_map_addr_tx_failed_count++; 7212 rc = ENOBUFS; 7213 goto bce_tx_encap_exit; 7214 } 7215 } else if (error == ENOMEM) { 7216 /* Insufficient DMA buffers available. */ 7217 sc->dma_map_addr_tx_failed_count++; 7218 rc = error; 7219 goto bce_tx_encap_exit; 7220 } else if (error != 0) { 7221 m_freem(m0); 7222 *m_head = NULL; 7223 sc->dma_map_addr_tx_failed_count++; 7224 rc = error; 7225 goto bce_tx_encap_exit; 7226 } 7227 7228 /* Make sure there's room in the chain */ 7229 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7230 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7231 rc = ENOBUFS; 7232 goto bce_tx_encap_exit; 7233 } 7234 7235 /* prod points to an empty tx_bd at this point. */ 7236 prod_bseq = sc->tx_prod_bseq; 7237 7238 #ifdef BCE_DEBUG 7239 debug_prod = chain_prod; 7240 #endif 7241 7242 DBPRINT(sc, BCE_INFO_SEND, 7243 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7244 "prod_bseq = 0x%08X\n", 7245 __FUNCTION__, prod, chain_prod, prod_bseq); 7246 7247 /* 7248 * Cycle through each mbuf segment that makes up 7249 * the outgoing frame, gathering the mapping info 7250 * for that segment and creating a tx_bd for 7251 * the mbuf. 7252 */ 7253 for (i = 0; i < nsegs ; i++) { 7254 7255 chain_prod = TX_CHAIN_IDX(prod); 7256 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7257 [TX_IDX(chain_prod)]; 7258 7259 txbd->tx_bd_haddr_lo = 7260 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7261 txbd->tx_bd_haddr_hi = 7262 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7263 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7264 htole16(segs[i].ds_len); 7265 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7266 txbd->tx_bd_flags = htole16(flags); 7267 prod_bseq += segs[i].ds_len; 7268 if (i == 0) 7269 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7270 prod = NEXT_TX_BD(prod); 7271 } 7272 7273 /* Set the END flag on the last TX buffer descriptor. */ 7274 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7275 7276 DBRUNMSG(BCE_EXTREME_SEND, 7277 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7278 7279 /* 7280 * Ensure that the mbuf pointer for this transmission 7281 * is placed at the array index of the last 7282 * descriptor in this chain. This is done 7283 * because a single map is used for all 7284 * segments of the mbuf and we don't want to 7285 * unload the map before all of the segments 7286 * have been freed. 7287 */ 7288 sc->tx_mbuf_ptr[chain_prod] = m0; 7289 sc->used_tx_bd += nsegs; 7290 7291 /* Update some debug statistic counters */ 7292 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7293 sc->tx_hi_watermark = sc->used_tx_bd); 7294 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7295 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7296 7297 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7298 7299 /* prod points to the next free tx_bd at this point. */ 7300 sc->tx_prod = prod; 7301 sc->tx_prod_bseq = prod_bseq; 7302 7303 /* Tell the chip about the waiting TX frames. */ 7304 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7305 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7306 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7307 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7308 7309 bce_tx_encap_exit: 7310 DBEXIT(BCE_VERBOSE_SEND); 7311 return(rc); 7312 } 7313 7314 7315 /****************************************************************************/ 7316 /* Main transmit routine when called from another routine with a lock. */ 7317 /* */ 7318 /* Returns: */ 7319 /* Nothing. */ 7320 /****************************************************************************/ 7321 static void 7322 bce_start_locked(struct ifnet *ifp) 7323 { 7324 struct bce_softc *sc = ifp->if_softc; 7325 struct mbuf *m_head = NULL; 7326 int count = 0; 7327 u16 tx_prod, tx_chain_prod; 7328 7329 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7330 7331 BCE_LOCK_ASSERT(sc); 7332 7333 /* prod points to the next free tx_bd. */ 7334 tx_prod = sc->tx_prod; 7335 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7336 7337 DBPRINT(sc, BCE_INFO_SEND, 7338 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7339 "tx_prod_bseq = 0x%08X\n", 7340 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7341 7342 /* If there's no link or the transmit queue is empty then just exit. */ 7343 if (sc->bce_link_up == FALSE) { 7344 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7345 __FUNCTION__); 7346 goto bce_start_locked_exit; 7347 } 7348 7349 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7350 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7351 __FUNCTION__); 7352 goto bce_start_locked_exit; 7353 } 7354 7355 /* 7356 * Keep adding entries while there is space in the ring. 7357 */ 7358 while (sc->used_tx_bd < sc->max_tx_bd) { 7359 7360 /* Check for any frames to send. */ 7361 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7362 7363 /* Stop when the transmit queue is empty. */ 7364 if (m_head == NULL) 7365 break; 7366 7367 /* 7368 * Pack the data into the transmit ring. If we 7369 * don't have room, place the mbuf back at the 7370 * head of the queue and set the OACTIVE flag 7371 * to wait for the NIC to drain the chain. 7372 */ 7373 if (bce_tx_encap(sc, &m_head)) { 7374 if (m_head != NULL) 7375 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7376 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7377 DBPRINT(sc, BCE_INFO_SEND, 7378 "TX chain is closed for business! Total " 7379 "tx_bd used = %d\n", sc->used_tx_bd); 7380 break; 7381 } 7382 7383 count++; 7384 7385 /* Send a copy of the frame to any BPF listeners. */ 7386 ETHER_BPF_MTAP(ifp, m_head); 7387 } 7388 7389 /* Exit if no packets were dequeued. */ 7390 if (count == 0) { 7391 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7392 "dequeued\n", __FUNCTION__); 7393 goto bce_start_locked_exit; 7394 } 7395 7396 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7397 "send queue.\n", __FUNCTION__, count); 7398 7399 /* Set the tx timeout. */ 7400 sc->watchdog_timer = BCE_TX_TIMEOUT; 7401 7402 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7403 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7404 7405 bce_start_locked_exit: 7406 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7407 return; 7408 } 7409 7410 7411 /****************************************************************************/ 7412 /* Main transmit routine when called from another routine without a lock. */ 7413 /* */ 7414 /* Returns: */ 7415 /* Nothing. */ 7416 /****************************************************************************/ 7417 static void 7418 bce_start(struct ifnet *ifp) 7419 { 7420 struct bce_softc *sc = ifp->if_softc; 7421 7422 DBENTER(BCE_VERBOSE_SEND); 7423 7424 BCE_LOCK(sc); 7425 bce_start_locked(ifp); 7426 BCE_UNLOCK(sc); 7427 7428 DBEXIT(BCE_VERBOSE_SEND); 7429 } 7430 7431 7432 /****************************************************************************/ 7433 /* Handles any IOCTL calls from the operating system. */ 7434 /* */ 7435 /* Returns: */ 7436 /* 0 for success, positive value for failure. */ 7437 /****************************************************************************/ 7438 static int 7439 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7440 { 7441 struct bce_softc *sc = ifp->if_softc; 7442 struct ifreq *ifr = (struct ifreq *) data; 7443 struct mii_data *mii; 7444 int mask, error = 0; 7445 7446 DBENTER(BCE_VERBOSE_MISC); 7447 7448 switch(command) { 7449 7450 /* Set the interface MTU. */ 7451 case SIOCSIFMTU: 7452 /* Check that the MTU setting is supported. */ 7453 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7454 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7455 error = EINVAL; 7456 break; 7457 } 7458 7459 DBPRINT(sc, BCE_INFO_MISC, 7460 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7461 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7462 7463 BCE_LOCK(sc); 7464 ifp->if_mtu = ifr->ifr_mtu; 7465 7466 if (bce_hdr_split == FALSE) { 7467 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7468 /* 7469 * Because allocation size is used in RX 7470 * buffer allocation, stop controller if 7471 * it is already running. 7472 */ 7473 bce_stop(sc); 7474 } 7475 7476 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7477 7478 bce_init_locked(sc); 7479 } 7480 7481 BCE_UNLOCK(sc); 7482 break; 7483 7484 /* Set interface flags. */ 7485 case SIOCSIFFLAGS: 7486 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7487 7488 BCE_LOCK(sc); 7489 7490 /* Check if the interface is up. */ 7491 if (ifp->if_flags & IFF_UP) { 7492 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7493 /* Change promiscuous/multicast flags as necessary. */ 7494 bce_set_rx_mode(sc); 7495 } else { 7496 /* Start the HW */ 7497 bce_init_locked(sc); 7498 } 7499 } else { 7500 /* The interface is down, check if driver is running. */ 7501 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7502 bce_stop(sc); 7503 7504 /* If MFW is running, restart the controller a bit. */ 7505 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7506 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7507 bce_chipinit(sc); 7508 bce_mgmt_init_locked(sc); 7509 } 7510 } 7511 } 7512 7513 BCE_UNLOCK(sc); 7514 break; 7515 7516 /* Add/Delete multicast address */ 7517 case SIOCADDMULTI: 7518 case SIOCDELMULTI: 7519 DBPRINT(sc, BCE_VERBOSE_MISC, 7520 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7521 7522 BCE_LOCK(sc); 7523 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7524 bce_set_rx_mode(sc); 7525 BCE_UNLOCK(sc); 7526 7527 break; 7528 7529 /* Set/Get Interface media */ 7530 case SIOCSIFMEDIA: 7531 case SIOCGIFMEDIA: 7532 DBPRINT(sc, BCE_VERBOSE_MISC, 7533 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7534 7535 mii = device_get_softc(sc->bce_miibus); 7536 error = ifmedia_ioctl(ifp, ifr, 7537 &mii->mii_media, command); 7538 break; 7539 7540 /* Set interface capability */ 7541 case SIOCSIFCAP: 7542 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7543 DBPRINT(sc, BCE_INFO_MISC, 7544 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7545 7546 /* Toggle the TX checksum capabilities enable flag. */ 7547 if (mask & IFCAP_TXCSUM && 7548 ifp->if_capabilities & IFCAP_TXCSUM) { 7549 ifp->if_capenable ^= IFCAP_TXCSUM; 7550 if (IFCAP_TXCSUM & ifp->if_capenable) 7551 ifp->if_hwassist |= BCE_IF_HWASSIST; 7552 else 7553 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7554 } 7555 7556 /* Toggle the RX checksum capabilities enable flag. */ 7557 if (mask & IFCAP_RXCSUM && 7558 ifp->if_capabilities & IFCAP_RXCSUM) 7559 ifp->if_capenable ^= IFCAP_RXCSUM; 7560 7561 /* Toggle the TSO capabilities enable flag. */ 7562 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7563 ifp->if_capabilities & IFCAP_TSO4) { 7564 ifp->if_capenable ^= IFCAP_TSO4; 7565 if (IFCAP_TSO4 & ifp->if_capenable) 7566 ifp->if_hwassist |= CSUM_TSO; 7567 else 7568 ifp->if_hwassist &= ~CSUM_TSO; 7569 } 7570 7571 if (mask & IFCAP_VLAN_HWCSUM && 7572 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7573 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7574 7575 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7576 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7577 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7578 /* 7579 * Don't actually disable VLAN tag stripping as 7580 * management firmware (ASF/IPMI/UMP) requires the 7581 * feature. If VLAN tag stripping is disabled driver 7582 * will manually reconstruct the VLAN frame by 7583 * appending stripped VLAN tag. 7584 */ 7585 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7586 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7587 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7588 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7589 == 0) 7590 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7591 } 7592 VLAN_CAPABILITIES(ifp); 7593 break; 7594 default: 7595 /* We don't know how to handle the IOCTL, pass it on. */ 7596 error = ether_ioctl(ifp, command, data); 7597 break; 7598 } 7599 7600 DBEXIT(BCE_VERBOSE_MISC); 7601 return(error); 7602 } 7603 7604 7605 /****************************************************************************/ 7606 /* Transmit timeout handler. */ 7607 /* */ 7608 /* Returns: */ 7609 /* Nothing. */ 7610 /****************************************************************************/ 7611 static void 7612 bce_watchdog(struct bce_softc *sc) 7613 { 7614 DBENTER(BCE_EXTREME_SEND); 7615 7616 BCE_LOCK_ASSERT(sc); 7617 7618 /* If the watchdog timer hasn't expired then just exit. */ 7619 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7620 goto bce_watchdog_exit; 7621 7622 /* If pause frames are active then don't reset the hardware. */ 7623 /* ToDo: Should we reset the timer here? */ 7624 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7625 goto bce_watchdog_exit; 7626 7627 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7628 __FILE__, __LINE__); 7629 7630 DBRUNMSG(BCE_INFO, 7631 bce_dump_driver_state(sc); 7632 bce_dump_status_block(sc); 7633 bce_dump_stats_block(sc); 7634 bce_dump_ftqs(sc); 7635 bce_dump_txp_state(sc, 0); 7636 bce_dump_rxp_state(sc, 0); 7637 bce_dump_tpat_state(sc, 0); 7638 bce_dump_cp_state(sc, 0); 7639 bce_dump_com_state(sc, 0)); 7640 7641 DBRUN(bce_breakpoint(sc)); 7642 7643 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7644 7645 bce_init_locked(sc); 7646 sc->bce_ifp->if_oerrors++; 7647 7648 bce_watchdog_exit: 7649 DBEXIT(BCE_EXTREME_SEND); 7650 } 7651 7652 7653 /* 7654 * Interrupt handler. 7655 */ 7656 /****************************************************************************/ 7657 /* Main interrupt entry point. Verifies that the controller generated the */ 7658 /* interrupt and then calls a separate routine for handle the various */ 7659 /* interrupt causes (PHY, TX, RX). */ 7660 /* */ 7661 /* Returns: */ 7662 /* 0 for success, positive value for failure. */ 7663 /****************************************************************************/ 7664 static void 7665 bce_intr(void *xsc) 7666 { 7667 struct bce_softc *sc; 7668 struct ifnet *ifp; 7669 u32 status_attn_bits; 7670 u16 hw_rx_cons, hw_tx_cons; 7671 7672 sc = xsc; 7673 ifp = sc->bce_ifp; 7674 7675 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7676 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7677 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7678 7679 BCE_LOCK(sc); 7680 7681 DBRUN(sc->interrupts_generated++); 7682 7683 /* Synchnorize before we read from interface's status block */ 7684 bus_dmamap_sync(sc->status_tag, sc->status_map, 7685 BUS_DMASYNC_POSTREAD); 7686 7687 /* 7688 * If the hardware status block index 7689 * matches the last value read by the 7690 * driver and we haven't asserted our 7691 * interrupt then there's nothing to do. 7692 */ 7693 if ((sc->status_block->status_idx == sc->last_status_idx) && 7694 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7695 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7696 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7697 __FUNCTION__); 7698 goto bce_intr_exit; 7699 } 7700 7701 /* Ack the interrupt and stop others from occuring. */ 7702 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7703 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7704 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7705 7706 /* Check if the hardware has finished any work. */ 7707 hw_rx_cons = bce_get_hw_rx_cons(sc); 7708 hw_tx_cons = bce_get_hw_tx_cons(sc); 7709 7710 /* Keep processing data as long as there is work to do. */ 7711 for (;;) { 7712 7713 status_attn_bits = sc->status_block->status_attn_bits; 7714 7715 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7716 BCE_PRINTF("Simulating unexpected status attention " 7717 "bit set."); 7718 sc->unexpected_attention_sim_count++; 7719 status_attn_bits = status_attn_bits | 7720 STATUS_ATTN_BITS_PARITY_ERROR); 7721 7722 /* Was it a link change interrupt? */ 7723 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7724 (sc->status_block->status_attn_bits_ack & 7725 STATUS_ATTN_BITS_LINK_STATE)) { 7726 bce_phy_intr(sc); 7727 7728 /* Clear transient updates during link state change. */ 7729 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7730 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7731 REG_RD(sc, BCE_HC_COMMAND); 7732 } 7733 7734 /* If any other attention is asserted, the chip is toast. */ 7735 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7736 (sc->status_block->status_attn_bits_ack & 7737 ~STATUS_ATTN_BITS_LINK_STATE))) { 7738 7739 sc->unexpected_attention_count++; 7740 7741 BCE_PRINTF("%s(%d): Fatal attention detected: " 7742 "0x%08X\n", __FILE__, __LINE__, 7743 sc->status_block->status_attn_bits); 7744 7745 DBRUNMSG(BCE_FATAL, 7746 if (unexpected_attention_sim_control == 0) 7747 bce_breakpoint(sc)); 7748 7749 bce_init_locked(sc); 7750 goto bce_intr_exit; 7751 } 7752 7753 /* Check for any completed RX frames. */ 7754 if (hw_rx_cons != sc->hw_rx_cons) 7755 bce_rx_intr(sc); 7756 7757 /* Check for any completed TX frames. */ 7758 if (hw_tx_cons != sc->hw_tx_cons) 7759 bce_tx_intr(sc); 7760 7761 /* Save status block index value for the next interrupt. */ 7762 sc->last_status_idx = sc->status_block->status_idx; 7763 7764 /* 7765 * Prevent speculative reads from getting 7766 * ahead of the status block. 7767 */ 7768 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7769 BUS_SPACE_BARRIER_READ); 7770 7771 /* 7772 * If there's no work left then exit the 7773 * interrupt service routine. 7774 */ 7775 hw_rx_cons = bce_get_hw_rx_cons(sc); 7776 hw_tx_cons = bce_get_hw_tx_cons(sc); 7777 7778 if ((hw_rx_cons == sc->hw_rx_cons) && 7779 (hw_tx_cons == sc->hw_tx_cons)) 7780 break; 7781 7782 } 7783 7784 bus_dmamap_sync(sc->status_tag, sc->status_map, 7785 BUS_DMASYNC_PREREAD); 7786 7787 /* Re-enable interrupts. */ 7788 bce_enable_intr(sc, 0); 7789 7790 /* Handle any frames that arrived while handling the interrupt. */ 7791 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7792 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7793 bce_start_locked(ifp); 7794 7795 bce_intr_exit: 7796 BCE_UNLOCK(sc); 7797 7798 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7799 } 7800 7801 7802 /****************************************************************************/ 7803 /* Programs the various packet receive modes (broadcast and multicast). */ 7804 /* */ 7805 /* Returns: */ 7806 /* Nothing. */ 7807 /****************************************************************************/ 7808 static void 7809 bce_set_rx_mode(struct bce_softc *sc) 7810 { 7811 struct ifnet *ifp; 7812 struct ifmultiaddr *ifma; 7813 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7814 u32 rx_mode, sort_mode; 7815 int h, i; 7816 7817 DBENTER(BCE_VERBOSE_MISC); 7818 7819 BCE_LOCK_ASSERT(sc); 7820 7821 ifp = sc->bce_ifp; 7822 7823 /* Initialize receive mode default settings. */ 7824 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7825 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7826 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7827 7828 /* 7829 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7830 * be enbled. 7831 */ 7832 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7833 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7834 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7835 7836 /* 7837 * Check for promiscuous, all multicast, or selected 7838 * multicast address filtering. 7839 */ 7840 if (ifp->if_flags & IFF_PROMISC) { 7841 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7842 7843 /* Enable promiscuous mode. */ 7844 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7845 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7846 } else if (ifp->if_flags & IFF_ALLMULTI) { 7847 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7848 7849 /* Enable all multicast addresses. */ 7850 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7851 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7852 } 7853 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7854 } else { 7855 /* Accept one or more multicast(s). */ 7856 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7857 7858 if_maddr_rlock(ifp); 7859 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7860 if (ifma->ifma_addr->sa_family != AF_LINK) 7861 continue; 7862 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7863 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7864 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7865 } 7866 if_maddr_runlock(ifp); 7867 7868 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7869 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7870 7871 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7872 } 7873 7874 /* Only make changes if the recive mode has actually changed. */ 7875 if (rx_mode != sc->rx_mode) { 7876 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7877 "0x%08X\n", rx_mode); 7878 7879 sc->rx_mode = rx_mode; 7880 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7881 } 7882 7883 /* Disable and clear the exisitng sort before enabling a new sort. */ 7884 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7885 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7886 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7887 7888 DBEXIT(BCE_VERBOSE_MISC); 7889 } 7890 7891 7892 /****************************************************************************/ 7893 /* Called periodically to updates statistics from the controllers */ 7894 /* statistics block. */ 7895 /* */ 7896 /* Returns: */ 7897 /* Nothing. */ 7898 /****************************************************************************/ 7899 static void 7900 bce_stats_update(struct bce_softc *sc) 7901 { 7902 struct ifnet *ifp; 7903 struct statistics_block *stats; 7904 7905 DBENTER(BCE_EXTREME_MISC); 7906 7907 ifp = sc->bce_ifp; 7908 7909 stats = (struct statistics_block *) sc->stats_block; 7910 7911 /* 7912 * Certain controllers don't report 7913 * carrier sense errors correctly. 7914 * See errata E11_5708CA0_1165. 7915 */ 7916 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7917 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7918 ifp->if_oerrors += 7919 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7920 7921 /* 7922 * Update the sysctl statistics from the 7923 * hardware statistics. 7924 */ 7925 sc->stat_IfHCInOctets = 7926 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7927 (u64) stats->stat_IfHCInOctets_lo; 7928 7929 sc->stat_IfHCInBadOctets = 7930 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7931 (u64) stats->stat_IfHCInBadOctets_lo; 7932 7933 sc->stat_IfHCOutOctets = 7934 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7935 (u64) stats->stat_IfHCOutOctets_lo; 7936 7937 sc->stat_IfHCOutBadOctets = 7938 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7939 (u64) stats->stat_IfHCOutBadOctets_lo; 7940 7941 sc->stat_IfHCInUcastPkts = 7942 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7943 (u64) stats->stat_IfHCInUcastPkts_lo; 7944 7945 sc->stat_IfHCInMulticastPkts = 7946 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7947 (u64) stats->stat_IfHCInMulticastPkts_lo; 7948 7949 sc->stat_IfHCInBroadcastPkts = 7950 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7951 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7952 7953 sc->stat_IfHCOutUcastPkts = 7954 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7955 (u64) stats->stat_IfHCOutUcastPkts_lo; 7956 7957 sc->stat_IfHCOutMulticastPkts = 7958 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7959 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7960 7961 sc->stat_IfHCOutBroadcastPkts = 7962 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7963 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7964 7965 /* ToDo: Preserve counters beyond 32 bits? */ 7966 /* ToDo: Read the statistics from auto-clear regs? */ 7967 7968 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7969 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7970 7971 sc->stat_Dot3StatsCarrierSenseErrors = 7972 stats->stat_Dot3StatsCarrierSenseErrors; 7973 7974 sc->stat_Dot3StatsFCSErrors = 7975 stats->stat_Dot3StatsFCSErrors; 7976 7977 sc->stat_Dot3StatsAlignmentErrors = 7978 stats->stat_Dot3StatsAlignmentErrors; 7979 7980 sc->stat_Dot3StatsSingleCollisionFrames = 7981 stats->stat_Dot3StatsSingleCollisionFrames; 7982 7983 sc->stat_Dot3StatsMultipleCollisionFrames = 7984 stats->stat_Dot3StatsMultipleCollisionFrames; 7985 7986 sc->stat_Dot3StatsDeferredTransmissions = 7987 stats->stat_Dot3StatsDeferredTransmissions; 7988 7989 sc->stat_Dot3StatsExcessiveCollisions = 7990 stats->stat_Dot3StatsExcessiveCollisions; 7991 7992 sc->stat_Dot3StatsLateCollisions = 7993 stats->stat_Dot3StatsLateCollisions; 7994 7995 sc->stat_EtherStatsCollisions = 7996 stats->stat_EtherStatsCollisions; 7997 7998 sc->stat_EtherStatsFragments = 7999 stats->stat_EtherStatsFragments; 8000 8001 sc->stat_EtherStatsJabbers = 8002 stats->stat_EtherStatsJabbers; 8003 8004 sc->stat_EtherStatsUndersizePkts = 8005 stats->stat_EtherStatsUndersizePkts; 8006 8007 sc->stat_EtherStatsOversizePkts = 8008 stats->stat_EtherStatsOversizePkts; 8009 8010 sc->stat_EtherStatsPktsRx64Octets = 8011 stats->stat_EtherStatsPktsRx64Octets; 8012 8013 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8014 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8015 8016 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8017 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8018 8019 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8020 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8021 8022 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8023 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8024 8025 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8026 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8027 8028 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8029 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8030 8031 sc->stat_EtherStatsPktsTx64Octets = 8032 stats->stat_EtherStatsPktsTx64Octets; 8033 8034 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8035 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8036 8037 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8038 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8039 8040 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8041 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8042 8043 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8044 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8045 8046 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8047 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8048 8049 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8050 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8051 8052 sc->stat_XonPauseFramesReceived = 8053 stats->stat_XonPauseFramesReceived; 8054 8055 sc->stat_XoffPauseFramesReceived = 8056 stats->stat_XoffPauseFramesReceived; 8057 8058 sc->stat_OutXonSent = 8059 stats->stat_OutXonSent; 8060 8061 sc->stat_OutXoffSent = 8062 stats->stat_OutXoffSent; 8063 8064 sc->stat_FlowControlDone = 8065 stats->stat_FlowControlDone; 8066 8067 sc->stat_MacControlFramesReceived = 8068 stats->stat_MacControlFramesReceived; 8069 8070 sc->stat_XoffStateEntered = 8071 stats->stat_XoffStateEntered; 8072 8073 sc->stat_IfInFramesL2FilterDiscards = 8074 stats->stat_IfInFramesL2FilterDiscards; 8075 8076 sc->stat_IfInRuleCheckerDiscards = 8077 stats->stat_IfInRuleCheckerDiscards; 8078 8079 sc->stat_IfInFTQDiscards = 8080 stats->stat_IfInFTQDiscards; 8081 8082 sc->stat_IfInMBUFDiscards = 8083 stats->stat_IfInMBUFDiscards; 8084 8085 sc->stat_IfInRuleCheckerP4Hit = 8086 stats->stat_IfInRuleCheckerP4Hit; 8087 8088 sc->stat_CatchupInRuleCheckerDiscards = 8089 stats->stat_CatchupInRuleCheckerDiscards; 8090 8091 sc->stat_CatchupInFTQDiscards = 8092 stats->stat_CatchupInFTQDiscards; 8093 8094 sc->stat_CatchupInMBUFDiscards = 8095 stats->stat_CatchupInMBUFDiscards; 8096 8097 sc->stat_CatchupInRuleCheckerP4Hit = 8098 stats->stat_CatchupInRuleCheckerP4Hit; 8099 8100 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8101 8102 /* 8103 * Update the interface statistics from the 8104 * hardware statistics. 8105 */ 8106 ifp->if_collisions = 8107 (u_long) sc->stat_EtherStatsCollisions; 8108 8109 /* ToDo: This method loses soft errors. */ 8110 ifp->if_ierrors = 8111 (u_long) sc->stat_EtherStatsUndersizePkts + 8112 (u_long) sc->stat_EtherStatsOversizePkts + 8113 (u_long) sc->stat_IfInMBUFDiscards + 8114 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8115 (u_long) sc->stat_Dot3StatsFCSErrors + 8116 (u_long) sc->stat_IfInRuleCheckerDiscards + 8117 (u_long) sc->stat_IfInFTQDiscards + 8118 (u_long) sc->com_no_buffers; 8119 8120 /* ToDo: This method loses soft errors. */ 8121 ifp->if_oerrors = 8122 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8123 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8124 (u_long) sc->stat_Dot3StatsLateCollisions; 8125 8126 /* ToDo: Add additional statistics? */ 8127 8128 DBEXIT(BCE_EXTREME_MISC); 8129 } 8130 8131 8132 /****************************************************************************/ 8133 /* Periodic function to notify the bootcode that the driver is still */ 8134 /* present. */ 8135 /* */ 8136 /* Returns: */ 8137 /* Nothing. */ 8138 /****************************************************************************/ 8139 static void 8140 bce_pulse(void *xsc) 8141 { 8142 struct bce_softc *sc = xsc; 8143 u32 msg; 8144 8145 DBENTER(BCE_EXTREME_MISC); 8146 8147 BCE_LOCK_ASSERT(sc); 8148 8149 /* Tell the firmware that the driver is still running. */ 8150 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8151 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8152 8153 /* Update the bootcode condition. */ 8154 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8155 8156 /* Report whether the bootcode still knows the driver is running. */ 8157 if (bce_verbose || bootverbose) { 8158 if (sc->bce_drv_cardiac_arrest == FALSE) { 8159 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8160 sc->bce_drv_cardiac_arrest = TRUE; 8161 BCE_PRINTF("%s(): Warning: bootcode " 8162 "thinks driver is absent! " 8163 "(bc_state = 0x%08X)\n", 8164 __FUNCTION__, sc->bc_state); 8165 } 8166 } else { 8167 /* 8168 * Not supported by all bootcode versions. 8169 * (v5.0.11+ and v5.2.1+) Older bootcode 8170 * will require the driver to reset the 8171 * controller to clear this condition. 8172 */ 8173 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8174 sc->bce_drv_cardiac_arrest = FALSE; 8175 BCE_PRINTF("%s(): Bootcode found the " 8176 "driver pulse! (bc_state = 0x%08X)\n", 8177 __FUNCTION__, sc->bc_state); 8178 } 8179 } 8180 } 8181 8182 8183 /* Schedule the next pulse. */ 8184 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8185 8186 DBEXIT(BCE_EXTREME_MISC); 8187 } 8188 8189 8190 /****************************************************************************/ 8191 /* Periodic function to perform maintenance tasks. */ 8192 /* */ 8193 /* Returns: */ 8194 /* Nothing. */ 8195 /****************************************************************************/ 8196 static void 8197 bce_tick(void *xsc) 8198 { 8199 struct bce_softc *sc = xsc; 8200 struct mii_data *mii; 8201 struct ifnet *ifp; 8202 8203 ifp = sc->bce_ifp; 8204 8205 DBENTER(BCE_EXTREME_MISC); 8206 8207 BCE_LOCK_ASSERT(sc); 8208 8209 /* Schedule the next tick. */ 8210 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8211 8212 /* Update the statistics from the hardware statistics block. */ 8213 bce_stats_update(sc); 8214 8215 /* 8216 * ToDo: This is a safety measure. Need to re-evaluate 8217 * high level processing logic and eliminate this code. 8218 */ 8219 /* Top off the receive and page chains. */ 8220 if (bce_hdr_split == TRUE) 8221 bce_fill_pg_chain(sc); 8222 bce_fill_rx_chain(sc); 8223 8224 /* Check that chip hasn't hung. */ 8225 bce_watchdog(sc); 8226 8227 /* If link is up already up then we're done. */ 8228 if (sc->bce_link_up == TRUE) 8229 goto bce_tick_exit; 8230 8231 /* Link is down. Check what the PHY's doing. */ 8232 mii = device_get_softc(sc->bce_miibus); 8233 mii_tick(mii); 8234 8235 /* Check if the link has come up. */ 8236 if ((mii->mii_media_status & IFM_ACTIVE) && 8237 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8238 DBPRINT(sc, BCE_VERBOSE_MISC, 8239 "%s(): Link up!\n", __FUNCTION__); 8240 sc->bce_link_up = TRUE; 8241 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8242 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8243 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8244 (bce_verbose || bootverbose)) 8245 BCE_PRINTF("Gigabit link up!\n"); 8246 8247 /* Now that link is up, handle any outstanding TX traffic. */ 8248 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8249 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8250 "pending TX traffic.\n", __FUNCTION__); 8251 bce_start_locked(ifp); 8252 } 8253 } 8254 8255 bce_tick_exit: 8256 DBEXIT(BCE_EXTREME_MISC); 8257 return; 8258 } 8259 8260 #ifdef BCE_DEBUG 8261 /****************************************************************************/ 8262 /* Allows the driver state to be dumped through the sysctl interface. */ 8263 /* */ 8264 /* Returns: */ 8265 /* 0 for success, positive value for failure. */ 8266 /****************************************************************************/ 8267 static int 8268 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8269 { 8270 int error; 8271 int result; 8272 struct bce_softc *sc; 8273 8274 result = -1; 8275 error = sysctl_handle_int(oidp, &result, 0, req); 8276 8277 if (error || !req->newptr) 8278 return (error); 8279 8280 if (result == 1) { 8281 sc = (struct bce_softc *)arg1; 8282 bce_dump_driver_state(sc); 8283 } 8284 8285 return error; 8286 } 8287 8288 8289 /****************************************************************************/ 8290 /* Allows the hardware state to be dumped through the sysctl interface. */ 8291 /* */ 8292 /* Returns: */ 8293 /* 0 for success, positive value for failure. */ 8294 /****************************************************************************/ 8295 static int 8296 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8297 { 8298 int error; 8299 int result; 8300 struct bce_softc *sc; 8301 8302 result = -1; 8303 error = sysctl_handle_int(oidp, &result, 0, req); 8304 8305 if (error || !req->newptr) 8306 return (error); 8307 8308 if (result == 1) { 8309 sc = (struct bce_softc *)arg1; 8310 bce_dump_hw_state(sc); 8311 } 8312 8313 return error; 8314 } 8315 8316 8317 /****************************************************************************/ 8318 /* Allows the status block to be dumped through the sysctl interface. */ 8319 /* */ 8320 /* Returns: */ 8321 /* 0 for success, positive value for failure. */ 8322 /****************************************************************************/ 8323 static int 8324 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8325 { 8326 int error; 8327 int result; 8328 struct bce_softc *sc; 8329 8330 result = -1; 8331 error = sysctl_handle_int(oidp, &result, 0, req); 8332 8333 if (error || !req->newptr) 8334 return (error); 8335 8336 if (result == 1) { 8337 sc = (struct bce_softc *)arg1; 8338 bce_dump_status_block(sc); 8339 } 8340 8341 return error; 8342 } 8343 8344 8345 /****************************************************************************/ 8346 /* Allows the stats block to be dumped through the sysctl interface. */ 8347 /* */ 8348 /* Returns: */ 8349 /* 0 for success, positive value for failure. */ 8350 /****************************************************************************/ 8351 static int 8352 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8353 { 8354 int error; 8355 int result; 8356 struct bce_softc *sc; 8357 8358 result = -1; 8359 error = sysctl_handle_int(oidp, &result, 0, req); 8360 8361 if (error || !req->newptr) 8362 return (error); 8363 8364 if (result == 1) { 8365 sc = (struct bce_softc *)arg1; 8366 bce_dump_stats_block(sc); 8367 } 8368 8369 return error; 8370 } 8371 8372 8373 /****************************************************************************/ 8374 /* Allows the stat counters to be cleared without unloading/reloading the */ 8375 /* driver. */ 8376 /* */ 8377 /* Returns: */ 8378 /* 0 for success, positive value for failure. */ 8379 /****************************************************************************/ 8380 static int 8381 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8382 { 8383 int error; 8384 int result; 8385 struct bce_softc *sc; 8386 8387 result = -1; 8388 error = sysctl_handle_int(oidp, &result, 0, req); 8389 8390 if (error || !req->newptr) 8391 return (error); 8392 8393 if (result == 1) { 8394 sc = (struct bce_softc *)arg1; 8395 struct statistics_block *stats; 8396 8397 stats = (struct statistics_block *) sc->stats_block; 8398 bzero(stats, sizeof(struct statistics_block)); 8399 8400 /* Clear the internal H/W statistics counters. */ 8401 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8402 8403 /* Reset the driver maintained statistics. */ 8404 sc->interrupts_rx = 8405 sc->interrupts_tx = 0; 8406 sc->tso_frames_requested = 8407 sc->tso_frames_completed = 8408 sc->tso_frames_failed = 0; 8409 sc->rx_empty_count = 8410 sc->tx_full_count = 0; 8411 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8412 sc->tx_hi_watermark = 0; 8413 sc->l2fhdr_error_count = 8414 sc->l2fhdr_error_sim_count = 0; 8415 sc->mbuf_alloc_failed_count = 8416 sc->mbuf_alloc_failed_sim_count = 0; 8417 sc->dma_map_addr_rx_failed_count = 8418 sc->dma_map_addr_tx_failed_count = 0; 8419 sc->mbuf_frag_count = 0; 8420 sc->csum_offload_tcp_udp = 8421 sc->csum_offload_ip = 0; 8422 sc->vlan_tagged_frames_rcvd = 8423 sc->vlan_tagged_frames_stripped = 0; 8424 sc->split_header_frames_rcvd = 8425 sc->split_header_tcp_frames_rcvd = 0; 8426 8427 /* Clear firmware maintained statistics. */ 8428 REG_WR_IND(sc, 0x120084, 0); 8429 } 8430 8431 return error; 8432 } 8433 8434 8435 /****************************************************************************/ 8436 /* Allows the shared memory contents to be dumped through the sysctl . */ 8437 /* interface. */ 8438 /* */ 8439 /* Returns: */ 8440 /* 0 for success, positive value for failure. */ 8441 /****************************************************************************/ 8442 static int 8443 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8444 { 8445 int error; 8446 int result; 8447 struct bce_softc *sc; 8448 8449 result = -1; 8450 error = sysctl_handle_int(oidp, &result, 0, req); 8451 8452 if (error || !req->newptr) 8453 return (error); 8454 8455 if (result == 1) { 8456 sc = (struct bce_softc *)arg1; 8457 bce_dump_shmem_state(sc); 8458 } 8459 8460 return error; 8461 } 8462 8463 8464 /****************************************************************************/ 8465 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8466 /* */ 8467 /* Returns: */ 8468 /* 0 for success, positive value for failure. */ 8469 /****************************************************************************/ 8470 static int 8471 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8472 { 8473 int error; 8474 int result; 8475 struct bce_softc *sc; 8476 8477 result = -1; 8478 error = sysctl_handle_int(oidp, &result, 0, req); 8479 8480 if (error || !req->newptr) 8481 return (error); 8482 8483 if (result == 1) { 8484 sc = (struct bce_softc *)arg1; 8485 bce_dump_bc_state(sc); 8486 } 8487 8488 return error; 8489 } 8490 8491 8492 /****************************************************************************/ 8493 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8494 /* */ 8495 /* Returns: */ 8496 /* 0 for success, positive value for failure. */ 8497 /****************************************************************************/ 8498 static int 8499 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8500 { 8501 int error; 8502 int result; 8503 struct bce_softc *sc; 8504 8505 result = -1; 8506 error = sysctl_handle_int(oidp, &result, 0, req); 8507 8508 if (error || !req->newptr) 8509 return (error); 8510 8511 if (result == 1) { 8512 sc = (struct bce_softc *)arg1; 8513 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8514 } 8515 8516 return error; 8517 } 8518 8519 8520 /****************************************************************************/ 8521 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8522 /* */ 8523 /* Returns: */ 8524 /* 0 for success, positive value for failure. */ 8525 /****************************************************************************/ 8526 static int 8527 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8528 { 8529 int error; 8530 int result; 8531 struct bce_softc *sc; 8532 8533 result = -1; 8534 error = sysctl_handle_int(oidp, &result, 0, req); 8535 8536 if (error || !req->newptr) 8537 return (error); 8538 8539 if (result == 1) { 8540 sc = (struct bce_softc *)arg1; 8541 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8542 } 8543 8544 return error; 8545 } 8546 8547 8548 /****************************************************************************/ 8549 /* Provides a sysctl interface to allow dumping the TX chain. */ 8550 /* */ 8551 /* Returns: */ 8552 /* 0 for success, positive value for failure. */ 8553 /****************************************************************************/ 8554 static int 8555 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8556 { 8557 int error; 8558 int result; 8559 struct bce_softc *sc; 8560 8561 result = -1; 8562 error = sysctl_handle_int(oidp, &result, 0, req); 8563 8564 if (error || !req->newptr) 8565 return (error); 8566 8567 if (result == 1) { 8568 sc = (struct bce_softc *)arg1; 8569 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8570 } 8571 8572 return error; 8573 } 8574 8575 8576 /****************************************************************************/ 8577 /* Provides a sysctl interface to allow dumping the page chain. */ 8578 /* */ 8579 /* Returns: */ 8580 /* 0 for success, positive value for failure. */ 8581 /****************************************************************************/ 8582 static int 8583 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8584 { 8585 int error; 8586 int result; 8587 struct bce_softc *sc; 8588 8589 result = -1; 8590 error = sysctl_handle_int(oidp, &result, 0, req); 8591 8592 if (error || !req->newptr) 8593 return (error); 8594 8595 if (result == 1) { 8596 sc = (struct bce_softc *)arg1; 8597 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8598 } 8599 8600 return error; 8601 } 8602 8603 /****************************************************************************/ 8604 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8605 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8606 /* */ 8607 /* Returns: */ 8608 /* 0 for success, positive value for failure. */ 8609 /****************************************************************************/ 8610 static int 8611 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8612 { 8613 struct bce_softc *sc = (struct bce_softc *)arg1; 8614 int error; 8615 u32 result; 8616 u32 val[1]; 8617 u8 *data = (u8 *) val; 8618 8619 result = -1; 8620 error = sysctl_handle_int(oidp, &result, 0, req); 8621 if (error || (req->newptr == NULL)) 8622 return (error); 8623 8624 error = bce_nvram_read(sc, result, data, 4); 8625 8626 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8627 8628 return (error); 8629 } 8630 8631 8632 /****************************************************************************/ 8633 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8634 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8635 /* */ 8636 /* Returns: */ 8637 /* 0 for success, positive value for failure. */ 8638 /****************************************************************************/ 8639 static int 8640 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8641 { 8642 struct bce_softc *sc = (struct bce_softc *)arg1; 8643 int error; 8644 u32 val, result; 8645 8646 result = -1; 8647 error = sysctl_handle_int(oidp, &result, 0, req); 8648 if (error || (req->newptr == NULL)) 8649 return (error); 8650 8651 /* Make sure the register is accessible. */ 8652 if (result < 0x8000) { 8653 val = REG_RD(sc, result); 8654 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8655 } else if (result < 0x0280000) { 8656 val = REG_RD_IND(sc, result); 8657 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8658 } 8659 8660 return (error); 8661 } 8662 8663 8664 /****************************************************************************/ 8665 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8666 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8667 /* */ 8668 /* Returns: */ 8669 /* 0 for success, positive value for failure. */ 8670 /****************************************************************************/ 8671 static int 8672 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8673 { 8674 struct bce_softc *sc; 8675 device_t dev; 8676 int error, result; 8677 u16 val; 8678 8679 result = -1; 8680 error = sysctl_handle_int(oidp, &result, 0, req); 8681 if (error || (req->newptr == NULL)) 8682 return (error); 8683 8684 /* Make sure the register is accessible. */ 8685 if (result < 0x20) { 8686 sc = (struct bce_softc *)arg1; 8687 dev = sc->bce_dev; 8688 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8689 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8690 } 8691 return (error); 8692 } 8693 8694 8695 /****************************************************************************/ 8696 /* Provides a sysctl interface for dumping the nvram contents. */ 8697 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8698 /* */ 8699 /* Returns: */ 8700 /* 0 for success, positive errno for failure. */ 8701 /****************************************************************************/ 8702 static int 8703 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8704 { 8705 struct bce_softc *sc = (struct bce_softc *)arg1; 8706 int error, i; 8707 8708 if (sc->nvram_buf == NULL) 8709 sc->nvram_buf = malloc(sc->bce_flash_size, 8710 M_TEMP, M_ZERO | M_WAITOK); 8711 8712 error = 0; 8713 if (req->oldlen == sc->bce_flash_size) { 8714 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8715 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8716 } 8717 8718 if (error == 0) 8719 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8720 8721 return error; 8722 } 8723 8724 #ifdef BCE_NVRAM_WRITE_SUPPORT 8725 /****************************************************************************/ 8726 /* Provides a sysctl interface for writing to nvram. */ 8727 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8728 /* */ 8729 /* Returns: */ 8730 /* 0 for success, positive errno for failure. */ 8731 /****************************************************************************/ 8732 static int 8733 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8734 { 8735 struct bce_softc *sc = (struct bce_softc *)arg1; 8736 int error; 8737 8738 if (sc->nvram_buf == NULL) 8739 sc->nvram_buf = malloc(sc->bce_flash_size, 8740 M_TEMP, M_ZERO | M_WAITOK); 8741 else 8742 bzero(sc->nvram_buf, sc->bce_flash_size); 8743 8744 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 8745 if (error == 0) 8746 return (error); 8747 8748 if (req->newlen == sc->bce_flash_size) 8749 error = bce_nvram_write(sc, 0, sc->nvram_buf, 8750 sc->bce_flash_size); 8751 8752 8753 return error; 8754 } 8755 #endif 8756 8757 8758 /****************************************************************************/ 8759 /* Provides a sysctl interface to allow reading a CID. */ 8760 /* */ 8761 /* Returns: */ 8762 /* 0 for success, positive value for failure. */ 8763 /****************************************************************************/ 8764 static int 8765 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8766 { 8767 struct bce_softc *sc; 8768 int error, result; 8769 8770 result = -1; 8771 error = sysctl_handle_int(oidp, &result, 0, req); 8772 if (error || (req->newptr == NULL)) 8773 return (error); 8774 8775 /* Make sure the register is accessible. */ 8776 if (result <= TX_CID) { 8777 sc = (struct bce_softc *)arg1; 8778 bce_dump_ctx(sc, result); 8779 } 8780 8781 return (error); 8782 } 8783 8784 8785 /****************************************************************************/ 8786 /* Provides a sysctl interface to forcing the driver to dump state and */ 8787 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8788 /* */ 8789 /* Returns: */ 8790 /* 0 for success, positive value for failure. */ 8791 /****************************************************************************/ 8792 static int 8793 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8794 { 8795 int error; 8796 int result; 8797 struct bce_softc *sc; 8798 8799 result = -1; 8800 error = sysctl_handle_int(oidp, &result, 0, req); 8801 8802 if (error || !req->newptr) 8803 return (error); 8804 8805 if (result == 1) { 8806 sc = (struct bce_softc *)arg1; 8807 bce_breakpoint(sc); 8808 } 8809 8810 return error; 8811 } 8812 #endif 8813 8814 /****************************************************************************/ 8815 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8816 /* */ 8817 /* Returns: */ 8818 /* 0 for success, positive value for failure. */ 8819 /****************************************************************************/ 8820 static void 8821 bce_add_sysctls(struct bce_softc *sc) 8822 { 8823 struct sysctl_ctx_list *ctx; 8824 struct sysctl_oid_list *children; 8825 8826 DBENTER(BCE_VERBOSE_MISC); 8827 8828 ctx = device_get_sysctl_ctx(sc->bce_dev); 8829 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8830 8831 #ifdef BCE_DEBUG 8832 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8833 "l2fhdr_error_sim_control", 8834 CTLFLAG_RW, &l2fhdr_error_sim_control, 8835 0, "Debug control to force l2fhdr errors"); 8836 8837 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8838 "l2fhdr_error_sim_count", 8839 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8840 0, "Number of simulated l2_fhdr errors"); 8841 #endif 8842 8843 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8844 "l2fhdr_error_count", 8845 CTLFLAG_RD, &sc->l2fhdr_error_count, 8846 0, "Number of l2_fhdr errors"); 8847 8848 #ifdef BCE_DEBUG 8849 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8850 "mbuf_alloc_failed_sim_control", 8851 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8852 0, "Debug control to force mbuf allocation failures"); 8853 8854 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8855 "mbuf_alloc_failed_sim_count", 8856 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8857 0, "Number of simulated mbuf cluster allocation failures"); 8858 #endif 8859 8860 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8861 "mbuf_alloc_failed_count", 8862 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8863 0, "Number of mbuf allocation failures"); 8864 8865 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8866 "mbuf_frag_count", 8867 CTLFLAG_RD, &sc->mbuf_frag_count, 8868 0, "Number of fragmented mbufs"); 8869 8870 #ifdef BCE_DEBUG 8871 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8872 "dma_map_addr_failed_sim_control", 8873 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8874 0, "Debug control to force DMA mapping failures"); 8875 8876 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 8877 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8878 "dma_map_addr_failed_sim_count", 8879 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 8880 0, "Number of simulated DMA mapping failures"); 8881 8882 #endif 8883 8884 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8885 "dma_map_addr_rx_failed_count", 8886 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 8887 0, "Number of RX DMA mapping failures"); 8888 8889 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8890 "dma_map_addr_tx_failed_count", 8891 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 8892 0, "Number of TX DMA mapping failures"); 8893 8894 #ifdef BCE_DEBUG 8895 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8896 "unexpected_attention_sim_control", 8897 CTLFLAG_RW, &unexpected_attention_sim_control, 8898 0, "Debug control to simulate unexpected attentions"); 8899 8900 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8901 "unexpected_attention_sim_count", 8902 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 8903 0, "Number of simulated unexpected attentions"); 8904 #endif 8905 8906 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8907 "unexpected_attention_count", 8908 CTLFLAG_RW, &sc->unexpected_attention_count, 8909 0, "Number of unexpected attentions"); 8910 8911 #ifdef BCE_DEBUG 8912 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8913 "debug_bootcode_running_failure", 8914 CTLFLAG_RW, &bootcode_running_failure_sim_control, 8915 0, "Debug control to force bootcode running failures"); 8916 8917 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8918 "rx_low_watermark", 8919 CTLFLAG_RD, &sc->rx_low_watermark, 8920 0, "Lowest level of free rx_bd's"); 8921 8922 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8923 "rx_empty_count", 8924 CTLFLAG_RD, &sc->rx_empty_count, 8925 "Number of times the RX chain was empty"); 8926 8927 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8928 "tx_hi_watermark", 8929 CTLFLAG_RD, &sc->tx_hi_watermark, 8930 0, "Highest level of used tx_bd's"); 8931 8932 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8933 "tx_full_count", 8934 CTLFLAG_RD, &sc->tx_full_count, 8935 "Number of times the TX chain was full"); 8936 8937 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8938 "tso_frames_requested", 8939 CTLFLAG_RD, &sc->tso_frames_requested, 8940 "Number of TSO frames requested"); 8941 8942 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8943 "tso_frames_completed", 8944 CTLFLAG_RD, &sc->tso_frames_completed, 8945 "Number of TSO frames completed"); 8946 8947 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8948 "tso_frames_failed", 8949 CTLFLAG_RD, &sc->tso_frames_failed, 8950 "Number of TSO frames failed"); 8951 8952 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8953 "csum_offload_ip", 8954 CTLFLAG_RD, &sc->csum_offload_ip, 8955 "Number of IP checksum offload frames"); 8956 8957 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8958 "csum_offload_tcp_udp", 8959 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 8960 "Number of TCP/UDP checksum offload frames"); 8961 8962 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8963 "vlan_tagged_frames_rcvd", 8964 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 8965 "Number of VLAN tagged frames received"); 8966 8967 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8968 "vlan_tagged_frames_stripped", 8969 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 8970 "Number of VLAN tagged frames stripped"); 8971 8972 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8973 "interrupts_rx", 8974 CTLFLAG_RD, &sc->interrupts_rx, 8975 "Number of RX interrupts"); 8976 8977 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8978 "interrupts_tx", 8979 CTLFLAG_RD, &sc->interrupts_tx, 8980 "Number of TX interrupts"); 8981 8982 if (bce_hdr_split == TRUE) { 8983 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8984 "split_header_frames_rcvd", 8985 CTLFLAG_RD, &sc->split_header_frames_rcvd, 8986 "Number of split header frames received"); 8987 8988 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8989 "split_header_tcp_frames_rcvd", 8990 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 8991 "Number of split header TCP frames received"); 8992 } 8993 8994 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8995 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 8996 (void *)sc, 0, 8997 bce_sysctl_nvram_dump, "S", ""); 8998 8999 #ifdef BCE_NVRAM_WRITE_SUPPORT 9000 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9001 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 9002 (void *)sc, 0, 9003 bce_sysctl_nvram_write, "S", ""); 9004 #endif 9005 #endif /* BCE_DEBUG */ 9006 9007 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9008 "stat_IfHcInOctets", 9009 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9010 "Bytes received"); 9011 9012 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9013 "stat_IfHCInBadOctets", 9014 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9015 "Bad bytes received"); 9016 9017 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9018 "stat_IfHCOutOctets", 9019 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9020 "Bytes sent"); 9021 9022 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9023 "stat_IfHCOutBadOctets", 9024 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9025 "Bad bytes sent"); 9026 9027 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9028 "stat_IfHCInUcastPkts", 9029 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9030 "Unicast packets received"); 9031 9032 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9033 "stat_IfHCInMulticastPkts", 9034 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9035 "Multicast packets received"); 9036 9037 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9038 "stat_IfHCInBroadcastPkts", 9039 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9040 "Broadcast packets received"); 9041 9042 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9043 "stat_IfHCOutUcastPkts", 9044 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9045 "Unicast packets sent"); 9046 9047 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9048 "stat_IfHCOutMulticastPkts", 9049 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9050 "Multicast packets sent"); 9051 9052 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9053 "stat_IfHCOutBroadcastPkts", 9054 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9055 "Broadcast packets sent"); 9056 9057 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9058 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9059 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9060 0, "Internal MAC transmit errors"); 9061 9062 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9063 "stat_Dot3StatsCarrierSenseErrors", 9064 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9065 0, "Carrier sense errors"); 9066 9067 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9068 "stat_Dot3StatsFCSErrors", 9069 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9070 0, "Frame check sequence errors"); 9071 9072 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9073 "stat_Dot3StatsAlignmentErrors", 9074 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9075 0, "Alignment errors"); 9076 9077 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9078 "stat_Dot3StatsSingleCollisionFrames", 9079 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9080 0, "Single Collision Frames"); 9081 9082 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9083 "stat_Dot3StatsMultipleCollisionFrames", 9084 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9085 0, "Multiple Collision Frames"); 9086 9087 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9088 "stat_Dot3StatsDeferredTransmissions", 9089 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9090 0, "Deferred Transmissions"); 9091 9092 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9093 "stat_Dot3StatsExcessiveCollisions", 9094 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9095 0, "Excessive Collisions"); 9096 9097 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9098 "stat_Dot3StatsLateCollisions", 9099 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9100 0, "Late Collisions"); 9101 9102 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9103 "stat_EtherStatsCollisions", 9104 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9105 0, "Collisions"); 9106 9107 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9108 "stat_EtherStatsFragments", 9109 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9110 0, "Fragments"); 9111 9112 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9113 "stat_EtherStatsJabbers", 9114 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9115 0, "Jabbers"); 9116 9117 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9118 "stat_EtherStatsUndersizePkts", 9119 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9120 0, "Undersize packets"); 9121 9122 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9123 "stat_EtherStatsOversizePkts", 9124 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9125 0, "stat_EtherStatsOversizePkts"); 9126 9127 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9128 "stat_EtherStatsPktsRx64Octets", 9129 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9130 0, "Bytes received in 64 byte packets"); 9131 9132 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9133 "stat_EtherStatsPktsRx65Octetsto127Octets", 9134 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9135 0, "Bytes received in 65 to 127 byte packets"); 9136 9137 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9138 "stat_EtherStatsPktsRx128Octetsto255Octets", 9139 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9140 0, "Bytes received in 128 to 255 byte packets"); 9141 9142 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9143 "stat_EtherStatsPktsRx256Octetsto511Octets", 9144 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9145 0, "Bytes received in 256 to 511 byte packets"); 9146 9147 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9148 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9149 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9150 0, "Bytes received in 512 to 1023 byte packets"); 9151 9152 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9153 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9154 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9155 0, "Bytes received in 1024 t0 1522 byte packets"); 9156 9157 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9158 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9159 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9160 0, "Bytes received in 1523 to 9022 byte packets"); 9161 9162 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9163 "stat_EtherStatsPktsTx64Octets", 9164 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9165 0, "Bytes sent in 64 byte packets"); 9166 9167 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9168 "stat_EtherStatsPktsTx65Octetsto127Octets", 9169 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9170 0, "Bytes sent in 65 to 127 byte packets"); 9171 9172 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9173 "stat_EtherStatsPktsTx128Octetsto255Octets", 9174 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9175 0, "Bytes sent in 128 to 255 byte packets"); 9176 9177 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9178 "stat_EtherStatsPktsTx256Octetsto511Octets", 9179 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9180 0, "Bytes sent in 256 to 511 byte packets"); 9181 9182 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9183 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9184 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9185 0, "Bytes sent in 512 to 1023 byte packets"); 9186 9187 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9188 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9189 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9190 0, "Bytes sent in 1024 to 1522 byte packets"); 9191 9192 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9193 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9194 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9195 0, "Bytes sent in 1523 to 9022 byte packets"); 9196 9197 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9198 "stat_XonPauseFramesReceived", 9199 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9200 0, "XON pause frames receved"); 9201 9202 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9203 "stat_XoffPauseFramesReceived", 9204 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9205 0, "XOFF pause frames received"); 9206 9207 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9208 "stat_OutXonSent", 9209 CTLFLAG_RD, &sc->stat_OutXonSent, 9210 0, "XON pause frames sent"); 9211 9212 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9213 "stat_OutXoffSent", 9214 CTLFLAG_RD, &sc->stat_OutXoffSent, 9215 0, "XOFF pause frames sent"); 9216 9217 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9218 "stat_FlowControlDone", 9219 CTLFLAG_RD, &sc->stat_FlowControlDone, 9220 0, "Flow control done"); 9221 9222 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9223 "stat_MacControlFramesReceived", 9224 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9225 0, "MAC control frames received"); 9226 9227 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9228 "stat_XoffStateEntered", 9229 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9230 0, "XOFF state entered"); 9231 9232 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9233 "stat_IfInFramesL2FilterDiscards", 9234 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9235 0, "Received L2 packets discarded"); 9236 9237 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9238 "stat_IfInRuleCheckerDiscards", 9239 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9240 0, "Received packets discarded by rule"); 9241 9242 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9243 "stat_IfInFTQDiscards", 9244 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9245 0, "Received packet FTQ discards"); 9246 9247 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9248 "stat_IfInMBUFDiscards", 9249 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9250 0, "Received packets discarded due to lack " 9251 "of controller buffer memory"); 9252 9253 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9254 "stat_IfInRuleCheckerP4Hit", 9255 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9256 0, "Received packets rule checker hits"); 9257 9258 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9259 "stat_CatchupInRuleCheckerDiscards", 9260 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9261 0, "Received packets discarded in Catchup path"); 9262 9263 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9264 "stat_CatchupInFTQDiscards", 9265 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9266 0, "Received packets discarded in FTQ in Catchup path"); 9267 9268 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9269 "stat_CatchupInMBUFDiscards", 9270 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9271 0, "Received packets discarded in controller " 9272 "buffer memory in Catchup path"); 9273 9274 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9275 "stat_CatchupInRuleCheckerP4Hit", 9276 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9277 0, "Received packets rule checker hits in Catchup path"); 9278 9279 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9280 "com_no_buffers", 9281 CTLFLAG_RD, &sc->com_no_buffers, 9282 0, "Valid packets received but no RX buffers available"); 9283 9284 #ifdef BCE_DEBUG 9285 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9286 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9287 (void *)sc, 0, 9288 bce_sysctl_driver_state, "I", "Drive state information"); 9289 9290 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9291 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9292 (void *)sc, 0, 9293 bce_sysctl_hw_state, "I", "Hardware state information"); 9294 9295 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9296 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9297 (void *)sc, 0, 9298 bce_sysctl_status_block, "I", "Dump status block"); 9299 9300 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9301 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9302 (void *)sc, 0, 9303 bce_sysctl_stats_block, "I", "Dump statistics block"); 9304 9305 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9306 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9307 (void *)sc, 0, 9308 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9309 9310 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9311 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9312 (void *)sc, 0, 9313 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9314 9315 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9316 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9317 (void *)sc, 0, 9318 bce_sysctl_bc_state, "I", "Bootcode state information"); 9319 9320 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9321 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9322 (void *)sc, 0, 9323 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9324 9325 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9326 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9327 (void *)sc, 0, 9328 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9329 9330 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9331 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9332 (void *)sc, 0, 9333 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9334 9335 if (bce_hdr_split == TRUE) { 9336 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9337 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9338 (void *)sc, 0, 9339 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9340 } 9341 9342 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9343 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9344 (void *)sc, 0, 9345 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9346 9347 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9348 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9349 (void *)sc, 0, 9350 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9351 9352 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9353 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9354 (void *)sc, 0, 9355 bce_sysctl_reg_read, "I", "Register read"); 9356 9357 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9358 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9359 (void *)sc, 0, 9360 bce_sysctl_nvram_read, "I", "NVRAM read"); 9361 9362 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9363 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9364 (void *)sc, 0, 9365 bce_sysctl_phy_read, "I", "PHY register read"); 9366 9367 #endif 9368 9369 DBEXIT(BCE_VERBOSE_MISC); 9370 } 9371 9372 9373 /****************************************************************************/ 9374 /* BCE Debug Routines */ 9375 /****************************************************************************/ 9376 #ifdef BCE_DEBUG 9377 9378 /****************************************************************************/ 9379 /* Freezes the controller to allow for a cohesive state dump. */ 9380 /* */ 9381 /* Returns: */ 9382 /* Nothing. */ 9383 /****************************************************************************/ 9384 static __attribute__ ((noinline)) void 9385 bce_freeze_controller(struct bce_softc *sc) 9386 { 9387 u32 val; 9388 val = REG_RD(sc, BCE_MISC_COMMAND); 9389 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9390 REG_WR(sc, BCE_MISC_COMMAND, val); 9391 } 9392 9393 9394 /****************************************************************************/ 9395 /* Unfreezes the controller after a freeze operation. This may not always */ 9396 /* work and the controller will require a reset! */ 9397 /* */ 9398 /* Returns: */ 9399 /* Nothing. */ 9400 /****************************************************************************/ 9401 static __attribute__ ((noinline)) void 9402 bce_unfreeze_controller(struct bce_softc *sc) 9403 { 9404 u32 val; 9405 val = REG_RD(sc, BCE_MISC_COMMAND); 9406 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9407 REG_WR(sc, BCE_MISC_COMMAND, val); 9408 } 9409 9410 9411 /****************************************************************************/ 9412 /* Prints out Ethernet frame information from an mbuf. */ 9413 /* */ 9414 /* Partially decode an Ethernet frame to look at some important headers. */ 9415 /* */ 9416 /* Returns: */ 9417 /* Nothing. */ 9418 /****************************************************************************/ 9419 static __attribute__ ((noinline)) void 9420 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9421 { 9422 struct ether_vlan_header *eh; 9423 u16 etype; 9424 int ehlen; 9425 struct ip *ip; 9426 struct tcphdr *th; 9427 struct udphdr *uh; 9428 struct arphdr *ah; 9429 9430 BCE_PRINTF( 9431 "-----------------------------" 9432 " Frame Decode " 9433 "-----------------------------\n"); 9434 9435 eh = mtod(m, struct ether_vlan_header *); 9436 9437 /* Handle VLAN encapsulation if present. */ 9438 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9439 etype = ntohs(eh->evl_proto); 9440 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9441 } else { 9442 etype = ntohs(eh->evl_encap_proto); 9443 ehlen = ETHER_HDR_LEN; 9444 } 9445 9446 /* ToDo: Add VLAN output. */ 9447 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9448 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9449 9450 switch (etype) { 9451 case ETHERTYPE_IP: 9452 ip = (struct ip *)(m->m_data + ehlen); 9453 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9454 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9455 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9456 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9457 9458 switch (ip->ip_p) { 9459 case IPPROTO_TCP: 9460 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9461 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9462 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9463 ntohs(th->th_dport), ntohs(th->th_sport), 9464 (th->th_off << 2), th->th_flags, 9465 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9466 "\02SYN\01FIN", ntohs(th->th_sum)); 9467 break; 9468 case IPPROTO_UDP: 9469 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9470 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9471 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9472 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9473 ntohs(uh->uh_sum)); 9474 break; 9475 case IPPROTO_ICMP: 9476 BCE_PRINTF("icmp:\n"); 9477 break; 9478 default: 9479 BCE_PRINTF("----: Other IP protocol.\n"); 9480 } 9481 break; 9482 case ETHERTYPE_IPV6: 9483 BCE_PRINTF("ipv6: No decode supported.\n"); 9484 break; 9485 case ETHERTYPE_ARP: 9486 BCE_PRINTF("-arp: "); 9487 ah = (struct arphdr *) (m->m_data + ehlen); 9488 switch (ntohs(ah->ar_op)) { 9489 case ARPOP_REVREQUEST: 9490 printf("reverse ARP request\n"); 9491 break; 9492 case ARPOP_REVREPLY: 9493 printf("reverse ARP reply\n"); 9494 break; 9495 case ARPOP_REQUEST: 9496 printf("ARP request\n"); 9497 break; 9498 case ARPOP_REPLY: 9499 printf("ARP reply\n"); 9500 break; 9501 default: 9502 printf("other ARP operation\n"); 9503 } 9504 break; 9505 default: 9506 BCE_PRINTF("----: Other protocol.\n"); 9507 } 9508 9509 BCE_PRINTF( 9510 "-----------------------------" 9511 "--------------" 9512 "-----------------------------\n"); 9513 } 9514 9515 9516 /****************************************************************************/ 9517 /* Prints out information about an mbuf. */ 9518 /* */ 9519 /* Returns: */ 9520 /* Nothing. */ 9521 /****************************************************************************/ 9522 static __attribute__ ((noinline)) void 9523 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9524 { 9525 struct mbuf *mp = m; 9526 9527 if (m == NULL) { 9528 BCE_PRINTF("mbuf: null pointer\n"); 9529 return; 9530 } 9531 9532 while (mp) { 9533 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9534 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9535 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9536 9537 if (mp->m_flags & M_PKTHDR) { 9538 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9539 "csum_flags = %b\n", mp->m_pkthdr.len, 9540 mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" 9541 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9542 "\22M_PROMISC\23M_NOFREE", 9543 mp->m_pkthdr.csum_flags, 9544 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 9545 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9546 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9547 "\14CSUM_PSEUDO_HDR"); 9548 } 9549 9550 if (mp->m_flags & M_EXT) { 9551 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9552 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9553 switch (mp->m_ext.ext_type) { 9554 case EXT_CLUSTER: 9555 printf("EXT_CLUSTER\n"); break; 9556 case EXT_SFBUF: 9557 printf("EXT_SFBUF\n"); break; 9558 case EXT_JUMBO9: 9559 printf("EXT_JUMBO9\n"); break; 9560 case EXT_JUMBO16: 9561 printf("EXT_JUMBO16\n"); break; 9562 case EXT_PACKET: 9563 printf("EXT_PACKET\n"); break; 9564 case EXT_MBUF: 9565 printf("EXT_MBUF\n"); break; 9566 case EXT_NET_DRV: 9567 printf("EXT_NET_DRV\n"); break; 9568 case EXT_MOD_TYPE: 9569 printf("EXT_MDD_TYPE\n"); break; 9570 case EXT_DISPOSABLE: 9571 printf("EXT_DISPOSABLE\n"); break; 9572 case EXT_EXTREF: 9573 printf("EXT_EXTREF\n"); break; 9574 default: 9575 printf("UNKNOWN\n"); 9576 } 9577 } 9578 9579 mp = mp->m_next; 9580 } 9581 } 9582 9583 9584 /****************************************************************************/ 9585 /* Prints out the mbufs in the TX mbuf chain. */ 9586 /* */ 9587 /* Returns: */ 9588 /* Nothing. */ 9589 /****************************************************************************/ 9590 static __attribute__ ((noinline)) void 9591 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9592 { 9593 struct mbuf *m; 9594 9595 BCE_PRINTF( 9596 "----------------------------" 9597 " tx mbuf data " 9598 "----------------------------\n"); 9599 9600 for (int i = 0; i < count; i++) { 9601 m = sc->tx_mbuf_ptr[chain_prod]; 9602 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9603 bce_dump_mbuf(sc, m); 9604 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9605 } 9606 9607 BCE_PRINTF( 9608 "----------------------------" 9609 "----------------" 9610 "----------------------------\n"); 9611 } 9612 9613 9614 /****************************************************************************/ 9615 /* Prints out the mbufs in the RX mbuf chain. */ 9616 /* */ 9617 /* Returns: */ 9618 /* Nothing. */ 9619 /****************************************************************************/ 9620 static __attribute__ ((noinline)) void 9621 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9622 { 9623 struct mbuf *m; 9624 9625 BCE_PRINTF( 9626 "----------------------------" 9627 " rx mbuf data " 9628 "----------------------------\n"); 9629 9630 for (int i = 0; i < count; i++) { 9631 m = sc->rx_mbuf_ptr[chain_prod]; 9632 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9633 bce_dump_mbuf(sc, m); 9634 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9635 } 9636 9637 9638 BCE_PRINTF( 9639 "----------------------------" 9640 "----------------" 9641 "----------------------------\n"); 9642 } 9643 9644 9645 /****************************************************************************/ 9646 /* Prints out the mbufs in the mbuf page chain. */ 9647 /* */ 9648 /* Returns: */ 9649 /* Nothing. */ 9650 /****************************************************************************/ 9651 static __attribute__ ((noinline)) void 9652 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9653 { 9654 struct mbuf *m; 9655 9656 BCE_PRINTF( 9657 "----------------------------" 9658 " pg mbuf data " 9659 "----------------------------\n"); 9660 9661 for (int i = 0; i < count; i++) { 9662 m = sc->pg_mbuf_ptr[chain_prod]; 9663 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9664 bce_dump_mbuf(sc, m); 9665 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9666 } 9667 9668 9669 BCE_PRINTF( 9670 "----------------------------" 9671 "----------------" 9672 "----------------------------\n"); 9673 } 9674 9675 9676 /****************************************************************************/ 9677 /* Prints out a tx_bd structure. */ 9678 /* */ 9679 /* Returns: */ 9680 /* Nothing. */ 9681 /****************************************************************************/ 9682 static __attribute__ ((noinline)) void 9683 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9684 { 9685 int i = 0; 9686 9687 if (idx > MAX_TX_BD_ALLOC) 9688 /* Index out of range. */ 9689 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9690 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9691 /* TX Chain page pointer. */ 9692 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9693 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9694 txbd->tx_bd_haddr_lo); 9695 else { 9696 /* Normal tx_bd entry. */ 9697 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9698 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9699 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9700 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9701 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9702 9703 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9704 if (i>0) 9705 printf("|"); 9706 printf("CONN_FAULT"); 9707 i++; 9708 } 9709 9710 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9711 if (i>0) 9712 printf("|"); 9713 printf("TCP_UDP_CKSUM"); 9714 i++; 9715 } 9716 9717 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9718 if (i>0) 9719 printf("|"); 9720 printf("IP_CKSUM"); 9721 i++; 9722 } 9723 9724 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9725 if (i>0) 9726 printf("|"); 9727 printf("VLAN"); 9728 i++; 9729 } 9730 9731 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9732 if (i>0) 9733 printf("|"); 9734 printf("COAL_NOW"); 9735 i++; 9736 } 9737 9738 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9739 if (i>0) 9740 printf("|"); 9741 printf("DONT_GEN_CRC"); 9742 i++; 9743 } 9744 9745 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9746 if (i>0) 9747 printf("|"); 9748 printf("START"); 9749 i++; 9750 } 9751 9752 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9753 if (i>0) 9754 printf("|"); 9755 printf("END"); 9756 i++; 9757 } 9758 9759 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9760 if (i>0) 9761 printf("|"); 9762 printf("LSO"); 9763 i++; 9764 } 9765 9766 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9767 if (i>0) 9768 printf("|"); 9769 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9770 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9771 } 9772 9773 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9774 if (i>0) 9775 printf("|"); 9776 printf("SW_FLAGS"); 9777 i++; 9778 } 9779 9780 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9781 if (i>0) 9782 printf("|"); 9783 printf("SNAP)"); 9784 } else { 9785 printf(")\n"); 9786 } 9787 } 9788 } 9789 9790 9791 /****************************************************************************/ 9792 /* Prints out a rx_bd structure. */ 9793 /* */ 9794 /* Returns: */ 9795 /* Nothing. */ 9796 /****************************************************************************/ 9797 static __attribute__ ((noinline)) void 9798 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9799 { 9800 if (idx > MAX_RX_BD_ALLOC) 9801 /* Index out of range. */ 9802 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9803 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9804 /* RX Chain page pointer. */ 9805 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9806 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9807 rxbd->rx_bd_haddr_lo); 9808 else 9809 /* Normal rx_bd entry. */ 9810 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9811 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9812 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9813 rxbd->rx_bd_flags); 9814 } 9815 9816 9817 /****************************************************************************/ 9818 /* Prints out a rx_bd structure in the page chain. */ 9819 /* */ 9820 /* Returns: */ 9821 /* Nothing. */ 9822 /****************************************************************************/ 9823 static __attribute__ ((noinline)) void 9824 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9825 { 9826 if (idx > MAX_PG_BD_ALLOC) 9827 /* Index out of range. */ 9828 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9829 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9830 /* Page Chain page pointer. */ 9831 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9832 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9833 else 9834 /* Normal rx_bd entry. */ 9835 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9836 "flags = 0x%08X\n", idx, 9837 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9838 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9839 } 9840 9841 9842 /****************************************************************************/ 9843 /* Prints out a l2_fhdr structure. */ 9844 /* */ 9845 /* Returns: */ 9846 /* Nothing. */ 9847 /****************************************************************************/ 9848 static __attribute__ ((noinline)) void 9849 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9850 { 9851 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9852 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9853 "tcp_udp_xsum = 0x%04X\n", idx, 9854 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9855 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9856 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9857 } 9858 9859 9860 /****************************************************************************/ 9861 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9862 /* */ 9863 /* Returns: */ 9864 /* Nothing. */ 9865 /****************************************************************************/ 9866 static __attribute__ ((noinline)) void 9867 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9868 { 9869 if (cid > TX_CID) { 9870 BCE_PRINTF(" Unknown CID\n"); 9871 return; 9872 } 9873 9874 BCE_PRINTF( 9875 "----------------------------" 9876 " CTX Data " 9877 "----------------------------\n"); 9878 9879 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9880 9881 if (cid == RX_CID) { 9882 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9883 "producer index\n", 9884 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9885 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 9886 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9887 BCE_L2CTX_RX_HOST_BSEQ)); 9888 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9889 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9890 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9891 "descriptor address\n", 9892 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9893 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9894 "descriptor address\n", 9895 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 9896 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 9897 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9898 BCE_L2CTX_RX_NX_BDIDX)); 9899 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 9900 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9901 BCE_L2CTX_RX_HOST_PG_BDIDX)); 9902 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 9903 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 9904 BCE_L2CTX_RX_PG_BUF_SIZE)); 9905 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 9906 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9907 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 9908 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 9909 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9910 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 9911 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 9912 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9913 BCE_L2CTX_RX_NX_PG_BDIDX)); 9914 } else if (cid == TX_CID) { 9915 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9916 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9917 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 9918 CTX_RD(sc, GET_CID_ADDR(cid), 9919 BCE_L2CTX_TX_TYPE_XI)); 9920 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 9921 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 9922 BCE_L2CTX_TX_CMD_TYPE_XI)); 9923 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 9924 "h/w buffer descriptor address\n", 9925 CTX_RD(sc, GET_CID_ADDR(cid), 9926 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 9927 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 9928 "h/w buffer descriptor address\n", 9929 CTX_RD(sc, GET_CID_ADDR(cid), 9930 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 9931 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 9932 "host producer index\n", 9933 CTX_RD(sc, GET_CID_ADDR(cid), 9934 BCE_L2CTX_TX_HOST_BIDX_XI)); 9935 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 9936 "host byte sequence\n", 9937 CTX_RD(sc, GET_CID_ADDR(cid), 9938 BCE_L2CTX_TX_HOST_BSEQ_XI)); 9939 } else { 9940 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 9941 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 9942 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 9943 CTX_RD(sc, GET_CID_ADDR(cid), 9944 BCE_L2CTX_TX_CMD_TYPE)); 9945 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 9946 "h/w buffer descriptor address\n", 9947 CTX_RD(sc, GET_CID_ADDR(cid), 9948 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 9949 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 9950 "h/w buffer descriptor address\n", 9951 CTX_RD(sc, GET_CID_ADDR(cid), 9952 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 9953 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 9954 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9955 BCE_L2CTX_TX_HOST_BIDX)); 9956 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 9957 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9958 BCE_L2CTX_TX_HOST_BSEQ)); 9959 } 9960 } 9961 9962 BCE_PRINTF( 9963 "----------------------------" 9964 " Raw CTX " 9965 "----------------------------\n"); 9966 9967 for (int i = 0x0; i < 0x300; i += 0x10) { 9968 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 9969 CTX_RD(sc, GET_CID_ADDR(cid), i), 9970 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 9971 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 9972 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 9973 } 9974 9975 9976 BCE_PRINTF( 9977 "----------------------------" 9978 "----------------" 9979 "----------------------------\n"); 9980 } 9981 9982 9983 /****************************************************************************/ 9984 /* Prints out the FTQ data. */ 9985 /* */ 9986 /* Returns: */ 9987 /* Nothing. */ 9988 /****************************************************************************/ 9989 static __attribute__ ((noinline)) void 9990 bce_dump_ftqs(struct bce_softc *sc) 9991 { 9992 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 9993 9994 BCE_PRINTF( 9995 "----------------------------" 9996 " FTQ Data " 9997 "----------------------------\n"); 9998 9999 BCE_PRINTF(" FTQ Command Control Depth_Now " 10000 "Max_Depth Valid_Cnt \n"); 10001 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10002 "---------- ----------\n"); 10003 10004 /* Setup the generic statistic counters for the FTQ valid count. */ 10005 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10006 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10007 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10008 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10009 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10010 10011 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10012 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10013 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10014 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10015 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10016 10017 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10018 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10019 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10020 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10021 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10022 10023 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10024 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10025 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10026 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10027 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10028 10029 /* Input queue to the Receive Lookup state machine */ 10030 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10031 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10032 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10033 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10034 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10035 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10036 cmd, ctl, cur_depth, max_depth, valid_cnt); 10037 10038 /* Input queue to the Receive Processor */ 10039 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10040 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10041 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10042 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10043 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10044 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10045 cmd, ctl, cur_depth, max_depth, valid_cnt); 10046 10047 /* Input queue to the Recevie Processor */ 10048 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10049 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10050 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10051 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10052 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10053 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10054 cmd, ctl, cur_depth, max_depth, valid_cnt); 10055 10056 /* Input queue to the Receive Virtual to Physical state machine */ 10057 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10058 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10059 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10060 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10061 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10062 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10063 cmd, ctl, cur_depth, max_depth, valid_cnt); 10064 10065 /* Input queue to the Recevie Virtual to Physical state machine */ 10066 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10067 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10068 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10069 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10070 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10071 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10072 cmd, ctl, cur_depth, max_depth, valid_cnt); 10073 10074 /* Input queue to the Receive Virtual to Physical state machine */ 10075 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10076 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10077 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10078 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10079 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10080 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10081 cmd, ctl, cur_depth, max_depth, valid_cnt); 10082 10083 /* Input queue to the Receive DMA state machine */ 10084 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10085 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10086 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10087 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10088 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10089 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10090 cmd, ctl, cur_depth, max_depth, valid_cnt); 10091 10092 /* Input queue to the Transmit Scheduler state machine */ 10093 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10094 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10095 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10096 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10097 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10098 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10099 cmd, ctl, cur_depth, max_depth, valid_cnt); 10100 10101 /* Input queue to the Transmit Buffer Descriptor state machine */ 10102 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10103 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10104 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10105 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10106 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10107 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10108 cmd, ctl, cur_depth, max_depth, valid_cnt); 10109 10110 /* Input queue to the Transmit Processor */ 10111 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10112 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10113 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10114 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10115 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10116 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10117 cmd, ctl, cur_depth, max_depth, valid_cnt); 10118 10119 /* Input queue to the Transmit DMA state machine */ 10120 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10121 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10122 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10123 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10124 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10125 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10126 cmd, ctl, cur_depth, max_depth, valid_cnt); 10127 10128 /* Input queue to the Transmit Patch-Up Processor */ 10129 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10130 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10131 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10132 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10133 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10134 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10135 cmd, ctl, cur_depth, max_depth, valid_cnt); 10136 10137 /* Input queue to the Transmit Assembler state machine */ 10138 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10139 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10140 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10141 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10142 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10143 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10144 cmd, ctl, cur_depth, max_depth, valid_cnt); 10145 10146 /* Input queue to the Completion Processor */ 10147 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10148 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10149 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10150 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10151 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10152 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10153 cmd, ctl, cur_depth, max_depth, valid_cnt); 10154 10155 /* Input queue to the Completion Processor */ 10156 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10157 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10158 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10159 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10160 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10161 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10162 cmd, ctl, cur_depth, max_depth, valid_cnt); 10163 10164 /* Input queue to the Completion Processor */ 10165 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10166 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10167 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10168 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10169 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10170 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10171 cmd, ctl, cur_depth, max_depth, valid_cnt); 10172 10173 /* Setup the generic statistic counters for the FTQ valid count. */ 10174 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10175 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10176 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10177 10178 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 10179 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 10180 val = val | 10181 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10182 24); 10183 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10184 10185 /* Input queue to the Management Control Processor */ 10186 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10187 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10188 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10189 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10190 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10191 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10192 cmd, ctl, cur_depth, max_depth, valid_cnt); 10193 10194 /* Input queue to the Command Processor */ 10195 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10196 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10197 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10198 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10199 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10200 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10201 cmd, ctl, cur_depth, max_depth, valid_cnt); 10202 10203 /* Input queue to the Completion Scheduler state machine */ 10204 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10205 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10206 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10207 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10208 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10209 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10210 cmd, ctl, cur_depth, max_depth, valid_cnt); 10211 10212 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 10213 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 10214 /* Input queue to the RV2P Command Scheduler */ 10215 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10216 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10217 cur_depth = (ctl & 0xFFC00000) >> 22; 10218 max_depth = (ctl & 0x003FF000) >> 12; 10219 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10220 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10221 cmd, ctl, cur_depth, max_depth, valid_cnt); 10222 } 10223 10224 BCE_PRINTF( 10225 "----------------------------" 10226 "----------------" 10227 "----------------------------\n"); 10228 } 10229 10230 10231 /****************************************************************************/ 10232 /* Prints out the TX chain. */ 10233 /* */ 10234 /* Returns: */ 10235 /* Nothing. */ 10236 /****************************************************************************/ 10237 static __attribute__ ((noinline)) void 10238 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10239 { 10240 struct tx_bd *txbd; 10241 10242 /* First some info about the tx_bd chain structure. */ 10243 BCE_PRINTF( 10244 "----------------------------" 10245 " tx_bd chain " 10246 "----------------------------\n"); 10247 10248 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10249 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10250 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10251 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10252 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10253 10254 BCE_PRINTF( 10255 "----------------------------" 10256 " tx_bd data " 10257 "----------------------------\n"); 10258 10259 /* Now print out a decoded list of TX buffer descriptors. */ 10260 for (int i = 0; i < count; i++) { 10261 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10262 bce_dump_txbd(sc, tx_prod, txbd); 10263 tx_prod++; 10264 } 10265 10266 BCE_PRINTF( 10267 "----------------------------" 10268 "----------------" 10269 "----------------------------\n"); 10270 } 10271 10272 10273 /****************************************************************************/ 10274 /* Prints out the RX chain. */ 10275 /* */ 10276 /* Returns: */ 10277 /* Nothing. */ 10278 /****************************************************************************/ 10279 static __attribute__ ((noinline)) void 10280 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10281 { 10282 struct rx_bd *rxbd; 10283 10284 /* First some info about the rx_bd chain structure. */ 10285 BCE_PRINTF( 10286 "----------------------------" 10287 " rx_bd chain " 10288 "----------------------------\n"); 10289 10290 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10291 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10292 10293 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10294 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10295 10296 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10297 10298 BCE_PRINTF( 10299 "----------------------------" 10300 " rx_bd data " 10301 "----------------------------\n"); 10302 10303 /* Now print out the rx_bd's themselves. */ 10304 for (int i = 0; i < count; i++) { 10305 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10306 bce_dump_rxbd(sc, rx_prod, rxbd); 10307 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10308 } 10309 10310 BCE_PRINTF( 10311 "----------------------------" 10312 "----------------" 10313 "----------------------------\n"); 10314 } 10315 10316 10317 /****************************************************************************/ 10318 /* Prints out the page chain. */ 10319 /* */ 10320 /* Returns: */ 10321 /* Nothing. */ 10322 /****************************************************************************/ 10323 static __attribute__ ((noinline)) void 10324 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10325 { 10326 struct rx_bd *pgbd; 10327 10328 /* First some info about the page chain structure. */ 10329 BCE_PRINTF( 10330 "----------------------------" 10331 " page chain " 10332 "----------------------------\n"); 10333 10334 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10335 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10336 10337 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10338 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10339 10340 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10341 10342 BCE_PRINTF( 10343 "----------------------------" 10344 " page data " 10345 "----------------------------\n"); 10346 10347 /* Now print out the rx_bd's themselves. */ 10348 for (int i = 0; i < count; i++) { 10349 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10350 bce_dump_pgbd(sc, pg_prod, pgbd); 10351 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10352 } 10353 10354 BCE_PRINTF( 10355 "----------------------------" 10356 "----------------" 10357 "----------------------------\n"); 10358 } 10359 10360 10361 #define BCE_PRINT_RX_CONS(arg) \ 10362 if (sblk->status_rx_quick_consumer_index##arg) \ 10363 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10364 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10365 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10366 arg); 10367 10368 10369 #define BCE_PRINT_TX_CONS(arg) \ 10370 if (sblk->status_tx_quick_consumer_index##arg) \ 10371 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10372 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10373 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10374 arg); 10375 10376 /****************************************************************************/ 10377 /* Prints out the status block from host memory. */ 10378 /* */ 10379 /* Returns: */ 10380 /* Nothing. */ 10381 /****************************************************************************/ 10382 static __attribute__ ((noinline)) void 10383 bce_dump_status_block(struct bce_softc *sc) 10384 { 10385 struct status_block *sblk; 10386 10387 sblk = sc->status_block; 10388 10389 BCE_PRINTF( 10390 "----------------------------" 10391 " Status Block " 10392 "----------------------------\n"); 10393 10394 /* Theses indices are used for normal L2 drivers. */ 10395 BCE_PRINTF(" 0x%08X - attn_bits\n", 10396 sblk->status_attn_bits); 10397 10398 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10399 sblk->status_attn_bits_ack); 10400 10401 BCE_PRINT_RX_CONS(0); 10402 BCE_PRINT_TX_CONS(0) 10403 10404 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10405 10406 /* Theses indices are not used for normal L2 drivers. */ 10407 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10408 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10409 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10410 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10411 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10412 10413 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10414 10415 if (sblk->status_completion_producer_index || 10416 sblk->status_cmd_consumer_index) 10417 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10418 sblk->status_completion_producer_index, 10419 sblk->status_cmd_consumer_index); 10420 10421 BCE_PRINTF( 10422 "----------------------------" 10423 "----------------" 10424 "----------------------------\n"); 10425 } 10426 10427 10428 #define BCE_PRINT_64BIT_STAT(arg) \ 10429 if (sblk->arg##_lo || sblk->arg##_hi) \ 10430 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10431 sblk->arg##_lo, #arg); 10432 10433 #define BCE_PRINT_32BIT_STAT(arg) \ 10434 if (sblk->arg) \ 10435 BCE_PRINTF(" 0x%08X : %s\n", \ 10436 sblk->arg, #arg); 10437 10438 /****************************************************************************/ 10439 /* Prints out the statistics block from host memory. */ 10440 /* */ 10441 /* Returns: */ 10442 /* Nothing. */ 10443 /****************************************************************************/ 10444 static __attribute__ ((noinline)) void 10445 bce_dump_stats_block(struct bce_softc *sc) 10446 { 10447 struct statistics_block *sblk; 10448 10449 sblk = sc->stats_block; 10450 10451 BCE_PRINTF( 10452 "---------------" 10453 " Stats Block (All Stats Not Shown Are 0) " 10454 "---------------\n"); 10455 10456 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10457 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10458 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10459 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10460 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10461 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10462 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10463 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10464 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10465 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10466 BCE_PRINT_32BIT_STAT( 10467 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10468 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10469 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10470 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10471 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10472 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10473 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10474 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10475 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10476 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10477 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10478 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10479 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10480 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10481 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10482 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10483 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10484 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10485 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10486 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10487 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10488 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10489 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10490 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10491 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10492 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10493 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10494 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10495 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10496 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10497 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10498 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10499 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10500 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10501 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10502 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10503 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10504 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10505 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10506 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10507 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10508 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10509 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10510 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10511 10512 BCE_PRINTF( 10513 "----------------------------" 10514 "----------------" 10515 "----------------------------\n"); 10516 } 10517 10518 10519 /****************************************************************************/ 10520 /* Prints out a summary of the driver state. */ 10521 /* */ 10522 /* Returns: */ 10523 /* Nothing. */ 10524 /****************************************************************************/ 10525 static __attribute__ ((noinline)) void 10526 bce_dump_driver_state(struct bce_softc *sc) 10527 { 10528 u32 val_hi, val_lo; 10529 10530 BCE_PRINTF( 10531 "-----------------------------" 10532 " Driver State " 10533 "-----------------------------\n"); 10534 10535 val_hi = BCE_ADDR_HI(sc); 10536 val_lo = BCE_ADDR_LO(sc); 10537 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10538 "address\n", val_hi, val_lo); 10539 10540 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10541 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10542 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10543 "address\n", val_hi, val_lo); 10544 10545 val_hi = BCE_ADDR_HI(sc->status_block); 10546 val_lo = BCE_ADDR_LO(sc->status_block); 10547 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10548 "virtual address\n", val_hi, val_lo); 10549 10550 val_hi = BCE_ADDR_HI(sc->stats_block); 10551 val_lo = BCE_ADDR_LO(sc->stats_block); 10552 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10553 "virtual address\n", val_hi, val_lo); 10554 10555 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10556 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10557 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10558 "virtual adddress\n", val_hi, val_lo); 10559 10560 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10561 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10562 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10563 "virtual address\n", val_hi, val_lo); 10564 10565 if (bce_hdr_split == TRUE) { 10566 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10567 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10568 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10569 "virtual address\n", val_hi, val_lo); 10570 } 10571 10572 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10573 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10574 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10575 "virtual address\n", val_hi, val_lo); 10576 10577 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10578 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10579 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10580 "virtual address\n", val_hi, val_lo); 10581 10582 if (bce_hdr_split == TRUE) { 10583 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10584 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10585 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10586 "virtual address\n", val_hi, val_lo); 10587 } 10588 10589 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10590 "h/w intrs\n", 10591 (long long unsigned int) sc->interrupts_generated); 10592 10593 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10594 "rx interrupts handled\n", 10595 (long long unsigned int) sc->interrupts_rx); 10596 10597 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10598 "tx interrupts handled\n", 10599 (long long unsigned int) sc->interrupts_tx); 10600 10601 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10602 "phy interrupts handled\n", 10603 (long long unsigned int) sc->phy_interrupts); 10604 10605 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10606 "status block index\n", sc->last_status_idx); 10607 10608 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10609 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10610 10611 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10612 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10613 10614 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10615 "byte seq index\n", sc->tx_prod_bseq); 10616 10617 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10618 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10619 10620 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10621 "tx_bd's\n", sc->used_tx_bd); 10622 10623 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10624 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10625 10626 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10627 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10628 10629 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10630 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10631 10632 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10633 "byte seq index\n", sc->rx_prod_bseq); 10634 10635 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10636 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10637 10638 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10639 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10640 10641 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10642 "rx_bd's\n", sc->free_rx_bd); 10643 10644 if (bce_hdr_split == TRUE) { 10645 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10646 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10647 10648 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10649 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10650 10651 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10652 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10653 } 10654 10655 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10656 "rx_bd's\n", sc->free_pg_bd); 10657 10658 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10659 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10660 10661 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10662 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10663 10664 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10665 "bce mac flags\n", sc->bce_flags); 10666 10667 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10668 "bce phy flags\n", sc->bce_phy_flags); 10669 10670 BCE_PRINTF( 10671 "----------------------------" 10672 "----------------" 10673 "----------------------------\n"); 10674 } 10675 10676 10677 /****************************************************************************/ 10678 /* Prints out the hardware state through a summary of important register, */ 10679 /* followed by a complete register dump. */ 10680 /* */ 10681 /* Returns: */ 10682 /* Nothing. */ 10683 /****************************************************************************/ 10684 static __attribute__ ((noinline)) void 10685 bce_dump_hw_state(struct bce_softc *sc) 10686 { 10687 u32 val; 10688 10689 BCE_PRINTF( 10690 "----------------------------" 10691 " Hardware State " 10692 "----------------------------\n"); 10693 10694 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10695 10696 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10697 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10698 val, BCE_MISC_ENABLE_STATUS_BITS); 10699 10700 val = REG_RD(sc, BCE_DMA_STATUS); 10701 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10702 val, BCE_DMA_STATUS); 10703 10704 val = REG_RD(sc, BCE_CTX_STATUS); 10705 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10706 val, BCE_CTX_STATUS); 10707 10708 val = REG_RD(sc, BCE_EMAC_STATUS); 10709 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10710 val, BCE_EMAC_STATUS); 10711 10712 val = REG_RD(sc, BCE_RPM_STATUS); 10713 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10714 val, BCE_RPM_STATUS); 10715 10716 /* ToDo: Create a #define for this constant. */ 10717 val = REG_RD(sc, 0x2004); 10718 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10719 val, 0x2004); 10720 10721 val = REG_RD(sc, BCE_RV2P_STATUS); 10722 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10723 val, BCE_RV2P_STATUS); 10724 10725 /* ToDo: Create a #define for this constant. */ 10726 val = REG_RD(sc, 0x2c04); 10727 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10728 val, 0x2c04); 10729 10730 val = REG_RD(sc, BCE_TBDR_STATUS); 10731 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10732 val, BCE_TBDR_STATUS); 10733 10734 val = REG_RD(sc, BCE_TDMA_STATUS); 10735 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10736 val, BCE_TDMA_STATUS); 10737 10738 val = REG_RD(sc, BCE_HC_STATUS); 10739 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10740 val, BCE_HC_STATUS); 10741 10742 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10743 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10744 val, BCE_TXP_CPU_STATE); 10745 10746 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10747 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10748 val, BCE_TPAT_CPU_STATE); 10749 10750 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10751 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10752 val, BCE_RXP_CPU_STATE); 10753 10754 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10755 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10756 val, BCE_COM_CPU_STATE); 10757 10758 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10759 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10760 val, BCE_MCP_CPU_STATE); 10761 10762 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10763 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10764 val, BCE_CP_CPU_STATE); 10765 10766 BCE_PRINTF( 10767 "----------------------------" 10768 "----------------" 10769 "----------------------------\n"); 10770 10771 BCE_PRINTF( 10772 "----------------------------" 10773 " Register Dump " 10774 "----------------------------\n"); 10775 10776 for (int i = 0x400; i < 0x8000; i += 0x10) { 10777 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10778 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10779 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10780 } 10781 10782 BCE_PRINTF( 10783 "----------------------------" 10784 "----------------" 10785 "----------------------------\n"); 10786 } 10787 10788 10789 /****************************************************************************/ 10790 /* Prints out the contentst of shared memory which is used for host driver */ 10791 /* to bootcode firmware communication. */ 10792 /* */ 10793 /* Returns: */ 10794 /* Nothing. */ 10795 /****************************************************************************/ 10796 static __attribute__ ((noinline)) void 10797 bce_dump_shmem_state(struct bce_softc *sc) 10798 { 10799 BCE_PRINTF( 10800 "----------------------------" 10801 " Hardware State " 10802 "----------------------------\n"); 10803 10804 BCE_PRINTF("0x%08X - Shared memory base address\n", 10805 sc->bce_shmem_base); 10806 BCE_PRINTF("%s - bootcode version\n", 10807 sc->bce_bc_ver); 10808 10809 BCE_PRINTF( 10810 "----------------------------" 10811 " Shared Mem " 10812 "----------------------------\n"); 10813 10814 for (int i = 0x0; i < 0x200; i += 0x10) { 10815 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10816 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 10817 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 10818 } 10819 10820 BCE_PRINTF( 10821 "----------------------------" 10822 "----------------" 10823 "----------------------------\n"); 10824 } 10825 10826 10827 /****************************************************************************/ 10828 /* Prints out the mailbox queue registers. */ 10829 /* */ 10830 /* Returns: */ 10831 /* Nothing. */ 10832 /****************************************************************************/ 10833 static __attribute__ ((noinline)) void 10834 bce_dump_mq_regs(struct bce_softc *sc) 10835 { 10836 BCE_PRINTF( 10837 "----------------------------" 10838 " MQ Regs " 10839 "----------------------------\n"); 10840 10841 BCE_PRINTF( 10842 "----------------------------" 10843 "----------------" 10844 "----------------------------\n"); 10845 10846 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10847 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10848 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10849 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10850 } 10851 10852 BCE_PRINTF( 10853 "----------------------------" 10854 "----------------" 10855 "----------------------------\n"); 10856 } 10857 10858 10859 /****************************************************************************/ 10860 /* Prints out the bootcode state. */ 10861 /* */ 10862 /* Returns: */ 10863 /* Nothing. */ 10864 /****************************************************************************/ 10865 static __attribute__ ((noinline)) void 10866 bce_dump_bc_state(struct bce_softc *sc) 10867 { 10868 u32 val; 10869 10870 BCE_PRINTF( 10871 "----------------------------" 10872 " Bootcode State " 10873 "----------------------------\n"); 10874 10875 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10876 10877 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10878 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10879 val, BCE_BC_RESET_TYPE); 10880 10881 val = bce_shmem_rd(sc, BCE_BC_STATE); 10882 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10883 val, BCE_BC_STATE); 10884 10885 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10886 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10887 val, BCE_BC_STATE_CONDITION); 10888 10889 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10890 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10891 val, BCE_BC_STATE_DEBUG_CMD); 10892 10893 BCE_PRINTF( 10894 "----------------------------" 10895 "----------------" 10896 "----------------------------\n"); 10897 } 10898 10899 10900 /****************************************************************************/ 10901 /* Prints out the TXP processor state. */ 10902 /* */ 10903 /* Returns: */ 10904 /* Nothing. */ 10905 /****************************************************************************/ 10906 static __attribute__ ((noinline)) void 10907 bce_dump_txp_state(struct bce_softc *sc, int regs) 10908 { 10909 u32 val; 10910 u32 fw_version[3]; 10911 10912 BCE_PRINTF( 10913 "----------------------------" 10914 " TXP State " 10915 "----------------------------\n"); 10916 10917 for (int i = 0; i < 3; i++) 10918 fw_version[i] = htonl(REG_RD_IND(sc, 10919 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10920 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10921 10922 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10923 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 10924 val, BCE_TXP_CPU_MODE); 10925 10926 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10927 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10928 val, BCE_TXP_CPU_STATE); 10929 10930 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10931 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 10932 val, BCE_TXP_CPU_EVENT_MASK); 10933 10934 if (regs) { 10935 BCE_PRINTF( 10936 "----------------------------" 10937 " Register Dump " 10938 "----------------------------\n"); 10939 10940 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10941 /* Skip the big blank spaces */ 10942 if (i < 0x454000 && i > 0x5ffff) 10943 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10944 "0x%08X 0x%08X\n", i, 10945 REG_RD_IND(sc, i), 10946 REG_RD_IND(sc, i + 0x4), 10947 REG_RD_IND(sc, i + 0x8), 10948 REG_RD_IND(sc, i + 0xC)); 10949 } 10950 } 10951 10952 BCE_PRINTF( 10953 "----------------------------" 10954 "----------------" 10955 "----------------------------\n"); 10956 } 10957 10958 10959 /****************************************************************************/ 10960 /* Prints out the RXP processor state. */ 10961 /* */ 10962 /* Returns: */ 10963 /* Nothing. */ 10964 /****************************************************************************/ 10965 static __attribute__ ((noinline)) void 10966 bce_dump_rxp_state(struct bce_softc *sc, int regs) 10967 { 10968 u32 val; 10969 u32 fw_version[3]; 10970 10971 BCE_PRINTF( 10972 "----------------------------" 10973 " RXP State " 10974 "----------------------------\n"); 10975 10976 for (int i = 0; i < 3; i++) 10977 fw_version[i] = htonl(REG_RD_IND(sc, 10978 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10979 10980 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10981 10982 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10983 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 10984 val, BCE_RXP_CPU_MODE); 10985 10986 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10987 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10988 val, BCE_RXP_CPU_STATE); 10989 10990 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10991 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 10992 val, BCE_RXP_CPU_EVENT_MASK); 10993 10994 if (regs) { 10995 BCE_PRINTF( 10996 "----------------------------" 10997 " Register Dump " 10998 "----------------------------\n"); 10999 11000 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11001 /* Skip the big blank sapces */ 11002 if (i < 0xc5400 && i > 0xdffff) 11003 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11004 "0x%08X 0x%08X\n", i, 11005 REG_RD_IND(sc, i), 11006 REG_RD_IND(sc, i + 0x4), 11007 REG_RD_IND(sc, i + 0x8), 11008 REG_RD_IND(sc, i + 0xC)); 11009 } 11010 } 11011 11012 BCE_PRINTF( 11013 "----------------------------" 11014 "----------------" 11015 "----------------------------\n"); 11016 } 11017 11018 11019 /****************************************************************************/ 11020 /* Prints out the TPAT processor state. */ 11021 /* */ 11022 /* Returns: */ 11023 /* Nothing. */ 11024 /****************************************************************************/ 11025 static __attribute__ ((noinline)) void 11026 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11027 { 11028 u32 val; 11029 u32 fw_version[3]; 11030 11031 BCE_PRINTF( 11032 "----------------------------" 11033 " TPAT State " 11034 "----------------------------\n"); 11035 11036 for (int i = 0; i < 3; i++) 11037 fw_version[i] = htonl(REG_RD_IND(sc, 11038 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11039 11040 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11041 11042 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11043 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11044 val, BCE_TPAT_CPU_MODE); 11045 11046 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11047 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11048 val, BCE_TPAT_CPU_STATE); 11049 11050 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11051 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11052 val, BCE_TPAT_CPU_EVENT_MASK); 11053 11054 if (regs) { 11055 BCE_PRINTF( 11056 "----------------------------" 11057 " Register Dump " 11058 "----------------------------\n"); 11059 11060 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11061 /* Skip the big blank spaces */ 11062 if (i < 0x854000 && i > 0x9ffff) 11063 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11064 "0x%08X 0x%08X\n", i, 11065 REG_RD_IND(sc, i), 11066 REG_RD_IND(sc, i + 0x4), 11067 REG_RD_IND(sc, i + 0x8), 11068 REG_RD_IND(sc, i + 0xC)); 11069 } 11070 } 11071 11072 BCE_PRINTF( 11073 "----------------------------" 11074 "----------------" 11075 "----------------------------\n"); 11076 } 11077 11078 11079 /****************************************************************************/ 11080 /* Prints out the Command Procesor (CP) state. */ 11081 /* */ 11082 /* Returns: */ 11083 /* Nothing. */ 11084 /****************************************************************************/ 11085 static __attribute__ ((noinline)) void 11086 bce_dump_cp_state(struct bce_softc *sc, int regs) 11087 { 11088 u32 val; 11089 u32 fw_version[3]; 11090 11091 BCE_PRINTF( 11092 "----------------------------" 11093 " CP State " 11094 "----------------------------\n"); 11095 11096 for (int i = 0; i < 3; i++) 11097 fw_version[i] = htonl(REG_RD_IND(sc, 11098 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11099 11100 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11101 11102 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11103 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11104 val, BCE_CP_CPU_MODE); 11105 11106 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11107 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11108 val, BCE_CP_CPU_STATE); 11109 11110 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11111 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11112 BCE_CP_CPU_EVENT_MASK); 11113 11114 if (regs) { 11115 BCE_PRINTF( 11116 "----------------------------" 11117 " Register Dump " 11118 "----------------------------\n"); 11119 11120 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11121 /* Skip the big blank spaces */ 11122 if (i < 0x185400 && i > 0x19ffff) 11123 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11124 "0x%08X 0x%08X\n", i, 11125 REG_RD_IND(sc, i), 11126 REG_RD_IND(sc, i + 0x4), 11127 REG_RD_IND(sc, i + 0x8), 11128 REG_RD_IND(sc, i + 0xC)); 11129 } 11130 } 11131 11132 BCE_PRINTF( 11133 "----------------------------" 11134 "----------------" 11135 "----------------------------\n"); 11136 } 11137 11138 11139 /****************************************************************************/ 11140 /* Prints out the Completion Procesor (COM) state. */ 11141 /* */ 11142 /* Returns: */ 11143 /* Nothing. */ 11144 /****************************************************************************/ 11145 static __attribute__ ((noinline)) void 11146 bce_dump_com_state(struct bce_softc *sc, int regs) 11147 { 11148 u32 val; 11149 u32 fw_version[4]; 11150 11151 BCE_PRINTF( 11152 "----------------------------" 11153 " COM State " 11154 "----------------------------\n"); 11155 11156 for (int i = 0; i < 3; i++) 11157 fw_version[i] = htonl(REG_RD_IND(sc, 11158 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11159 11160 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11161 11162 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11163 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11164 val, BCE_COM_CPU_MODE); 11165 11166 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11167 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11168 val, BCE_COM_CPU_STATE); 11169 11170 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11171 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11172 BCE_COM_CPU_EVENT_MASK); 11173 11174 if (regs) { 11175 BCE_PRINTF( 11176 "----------------------------" 11177 " Register Dump " 11178 "----------------------------\n"); 11179 11180 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11181 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11182 "0x%08X 0x%08X\n", i, 11183 REG_RD_IND(sc, i), 11184 REG_RD_IND(sc, i + 0x4), 11185 REG_RD_IND(sc, i + 0x8), 11186 REG_RD_IND(sc, i + 0xC)); 11187 } 11188 } 11189 11190 BCE_PRINTF( 11191 "----------------------------" 11192 "----------------" 11193 "----------------------------\n"); 11194 } 11195 11196 11197 /****************************************************************************/ 11198 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11199 /* */ 11200 /* Returns: */ 11201 /* Nothing. */ 11202 /****************************************************************************/ 11203 static __attribute__ ((noinline)) void 11204 bce_dump_rv2p_state(struct bce_softc *sc) 11205 { 11206 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11207 11208 BCE_PRINTF( 11209 "----------------------------" 11210 " RV2P State " 11211 "----------------------------\n"); 11212 11213 /* Stall the RV2P processors. */ 11214 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11215 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11216 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11217 11218 /* Read the firmware version. */ 11219 val = 0x00000001; 11220 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11221 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11222 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11223 BCE_RV2P_INSTR_HIGH_HIGH; 11224 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11225 fw_ver_high, fw_ver_low); 11226 11227 val = 0x00000001; 11228 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11229 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11230 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11231 BCE_RV2P_INSTR_HIGH_HIGH; 11232 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11233 fw_ver_high, fw_ver_low); 11234 11235 /* Resume the RV2P processors. */ 11236 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11237 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11238 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11239 11240 /* Fetch the program counter value. */ 11241 val = 0x68007800; 11242 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11243 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11244 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11245 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11246 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11247 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11248 11249 /* Fetch the program counter value again to see if it is advancing. */ 11250 val = 0x68007800; 11251 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11252 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11253 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11254 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11255 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11256 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11257 11258 BCE_PRINTF( 11259 "----------------------------" 11260 "----------------" 11261 "----------------------------\n"); 11262 } 11263 11264 11265 /****************************************************************************/ 11266 /* Prints out the driver state and then enters the debugger. */ 11267 /* */ 11268 /* Returns: */ 11269 /* Nothing. */ 11270 /****************************************************************************/ 11271 static __attribute__ ((noinline)) void 11272 bce_breakpoint(struct bce_softc *sc) 11273 { 11274 11275 /* 11276 * Unreachable code to silence compiler warnings 11277 * about unused functions. 11278 */ 11279 if (0) { 11280 bce_freeze_controller(sc); 11281 bce_unfreeze_controller(sc); 11282 bce_dump_enet(sc, NULL); 11283 bce_dump_txbd(sc, 0, NULL); 11284 bce_dump_rxbd(sc, 0, NULL); 11285 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11286 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11287 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11288 bce_dump_l2fhdr(sc, 0, NULL); 11289 bce_dump_ctx(sc, RX_CID); 11290 bce_dump_ftqs(sc); 11291 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11292 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11293 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11294 bce_dump_status_block(sc); 11295 bce_dump_stats_block(sc); 11296 bce_dump_driver_state(sc); 11297 bce_dump_hw_state(sc); 11298 bce_dump_bc_state(sc); 11299 bce_dump_txp_state(sc, 0); 11300 bce_dump_rxp_state(sc, 0); 11301 bce_dump_tpat_state(sc, 0); 11302 bce_dump_cp_state(sc, 0); 11303 bce_dump_com_state(sc, 0); 11304 bce_dump_rv2p_state(sc); 11305 bce_dump_pgbd(sc, 0, NULL); 11306 } 11307 11308 bce_dump_status_block(sc); 11309 bce_dump_driver_state(sc); 11310 11311 /* Call the debugger. */ 11312 breakpoint(); 11313 11314 return; 11315 } 11316 #endif 11317 11318