1 /*- 2 * Copyright (c) 2006 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5708C B1 38 * 39 * The following controllers are not supported by this driver: 40 * (These are not "Production" versions of the controller.) 41 * 42 * BCM5706C A0, A1 43 * BCM5706S A0, A1, A2, A3 44 * BCM5708C A0, B0 45 * BCM5708S A0, B0, B1 46 */ 47 48 #include "opt_bce.h" 49 50 #include <dev/bce/if_bcereg.h> 51 #include <dev/bce/if_bcefw.h> 52 53 /****************************************************************************/ 54 /* BCE Driver Version */ 55 /****************************************************************************/ 56 char bce_driver_version[] = "v0.9.6"; 57 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int bce_debug_l2fhdr_status_check = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int bce_debug_unexpected_attention = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int bce_debug_mbuf_allocation_failure = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int bce_debug_dma_map_addr_failure = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bce_debug_bootcode_running_failure = 0; 89 #endif 90 91 92 /****************************************************************************/ 93 /* PCI Device ID Table */ 94 /* */ 95 /* Used by bce_probe() to identify the devices supported by this driver. */ 96 /****************************************************************************/ 97 #define BCE_DEVDESC_MAX 64 98 99 static struct bce_type bce_devs[] = { 100 /* BCM5706C Controllers and OEM boards. */ 101 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 102 "HP NC370T Multifunction Gigabit Server Adapter" }, 103 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 104 "HP NC370i Multifunction Gigabit Server Adapter" }, 105 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 106 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 107 108 /* BCM5706S controllers and OEM boards. */ 109 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 110 "HP NC370F Multifunction Gigabit Server Adapter" }, 111 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 112 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 113 114 /* BCM5708C controllers and OEM boards. */ 115 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 116 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 117 118 /* BCM5708S controllers and OEM boards. */ 119 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 120 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 121 { 0, 0, 0, 0, NULL } 122 }; 123 124 125 /****************************************************************************/ 126 /* Supported Flash NVRAM device data. */ 127 /****************************************************************************/ 128 static struct flash_spec flash_table[] = 129 { 130 /* Slow EEPROM */ 131 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 132 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 133 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 134 "EEPROM - slow"}, 135 /* Expansion entry 0001 */ 136 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 137 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 138 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 139 "Entry 0001"}, 140 /* Saifun SA25F010 (non-buffered flash) */ 141 /* strap, cfg1, & write1 need updates */ 142 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 143 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 144 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 145 "Non-buffered flash (128kB)"}, 146 /* Saifun SA25F020 (non-buffered flash) */ 147 /* strap, cfg1, & write1 need updates */ 148 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 149 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 150 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 151 "Non-buffered flash (256kB)"}, 152 /* Expansion entry 0100 */ 153 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 154 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 155 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 156 "Entry 0100"}, 157 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 158 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 159 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 160 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 161 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 162 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 163 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 164 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 165 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 166 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 167 /* Saifun SA25F005 (non-buffered flash) */ 168 /* strap, cfg1, & write1 need updates */ 169 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 170 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 171 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 172 "Non-buffered flash (64kB)"}, 173 /* Fast EEPROM */ 174 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 175 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 176 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 177 "EEPROM - fast"}, 178 /* Expansion entry 1001 */ 179 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 180 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 182 "Entry 1001"}, 183 /* Expansion entry 1010 */ 184 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 185 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 186 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 187 "Entry 1010"}, 188 /* ATMEL AT45DB011B (buffered flash) */ 189 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 190 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 191 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 192 "Buffered flash (128kB)"}, 193 /* Expansion entry 1100 */ 194 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 195 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 196 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 197 "Entry 1100"}, 198 /* Expansion entry 1101 */ 199 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 200 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 201 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 202 "Entry 1101"}, 203 /* Ateml Expansion entry 1110 */ 204 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 205 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 206 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 207 "Entry 1110 (Atmel)"}, 208 /* ATMEL AT45DB021B (buffered flash) */ 209 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 210 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 211 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 212 "Buffered flash (256kB)"}, 213 }; 214 215 216 /****************************************************************************/ 217 /* FreeBSD device entry points. */ 218 /****************************************************************************/ 219 static int bce_probe (device_t); 220 static int bce_attach (device_t); 221 static int bce_detach (device_t); 222 static void bce_shutdown (device_t); 223 224 225 /****************************************************************************/ 226 /* BCE Debug Data Structure Dump Routines */ 227 /****************************************************************************/ 228 #ifdef BCE_DEBUG 229 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 230 static void bce_dump_tx_mbuf_chain (struct bce_softc *, int, int); 231 static void bce_dump_rx_mbuf_chain (struct bce_softc *, int, int); 232 static void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *); 233 static void bce_dump_rxbd (struct bce_softc *, int, struct rx_bd *); 234 static void bce_dump_l2fhdr (struct bce_softc *, int, struct l2_fhdr *); 235 static void bce_dump_tx_chain (struct bce_softc *, int, int); 236 static void bce_dump_rx_chain (struct bce_softc *, int, int); 237 static void bce_dump_status_block (struct bce_softc *); 238 static void bce_dump_stats_block (struct bce_softc *); 239 static void bce_dump_driver_state (struct bce_softc *); 240 static void bce_dump_hw_state (struct bce_softc *); 241 static void bce_breakpoint (struct bce_softc *); 242 #endif 243 244 245 /****************************************************************************/ 246 /* BCE Register/Memory Access Routines */ 247 /****************************************************************************/ 248 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 249 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 250 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 251 static int bce_miibus_read_reg (device_t, int, int); 252 static int bce_miibus_write_reg (device_t, int, int, int); 253 static void bce_miibus_statchg (device_t); 254 255 256 /****************************************************************************/ 257 /* BCE NVRAM Access Routines */ 258 /****************************************************************************/ 259 static int bce_acquire_nvram_lock (struct bce_softc *); 260 static int bce_release_nvram_lock (struct bce_softc *); 261 static void bce_enable_nvram_access (struct bce_softc *); 262 static void bce_disable_nvram_access(struct bce_softc *); 263 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 264 static int bce_init_nvram (struct bce_softc *); 265 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 266 static int bce_nvram_test (struct bce_softc *); 267 #ifdef BCE_NVRAM_WRITE_SUPPORT 268 static int bce_enable_nvram_write (struct bce_softc *); 269 static void bce_disable_nvram_write (struct bce_softc *); 270 static int bce_nvram_erase_page (struct bce_softc *, u32); 271 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 272 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 273 #endif 274 275 /****************************************************************************/ 276 /* */ 277 /****************************************************************************/ 278 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 279 static int bce_dma_alloc (device_t); 280 static void bce_dma_free (struct bce_softc *); 281 static void bce_release_resources (struct bce_softc *); 282 283 /****************************************************************************/ 284 /* BCE Firmware Synchronization and Load */ 285 /****************************************************************************/ 286 static int bce_fw_sync (struct bce_softc *, u32); 287 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 288 static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *); 289 static void bce_init_cpus (struct bce_softc *); 290 291 static void bce_stop (struct bce_softc *); 292 static int bce_reset (struct bce_softc *, u32); 293 static int bce_chipinit (struct bce_softc *); 294 static int bce_blockinit (struct bce_softc *); 295 static int bce_get_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *); 296 297 static int bce_init_tx_chain (struct bce_softc *); 298 static int bce_init_rx_chain (struct bce_softc *); 299 static void bce_free_rx_chain (struct bce_softc *); 300 static void bce_free_tx_chain (struct bce_softc *); 301 302 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 303 static void bce_start_locked (struct ifnet *); 304 static void bce_start (struct ifnet *); 305 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 306 static void bce_watchdog (struct ifnet *); 307 static int bce_ifmedia_upd (struct ifnet *); 308 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 309 static void bce_init_locked (struct bce_softc *); 310 static void bce_init (void *); 311 static void bce_mgmt_init_locked(struct bce_softc *sc); 312 313 static void bce_init_context (struct bce_softc *); 314 static void bce_get_mac_addr (struct bce_softc *); 315 static void bce_set_mac_addr (struct bce_softc *); 316 static void bce_phy_intr (struct bce_softc *); 317 static void bce_rx_intr (struct bce_softc *); 318 static void bce_tx_intr (struct bce_softc *); 319 static void bce_disable_intr (struct bce_softc *); 320 static void bce_enable_intr (struct bce_softc *); 321 322 #ifdef DEVICE_POLLING 323 static void bce_poll_locked (struct ifnet *, enum poll_cmd, int); 324 static void bce_poll (struct ifnet *, enum poll_cmd, int); 325 #endif 326 static void bce_intr (void *); 327 static void bce_set_rx_mode (struct bce_softc *); 328 static void bce_stats_update (struct bce_softc *); 329 static void bce_tick_locked (struct bce_softc *); 330 static void bce_tick (void *); 331 static void bce_add_sysctls (struct bce_softc *); 332 333 334 /****************************************************************************/ 335 /* FreeBSD device dispatch table. */ 336 /****************************************************************************/ 337 static device_method_t bce_methods[] = { 338 /* Device interface */ 339 DEVMETHOD(device_probe, bce_probe), 340 DEVMETHOD(device_attach, bce_attach), 341 DEVMETHOD(device_detach, bce_detach), 342 DEVMETHOD(device_shutdown, bce_shutdown), 343 344 /* bus interface */ 345 DEVMETHOD(bus_print_child, bus_generic_print_child), 346 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 347 348 /* MII interface */ 349 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 350 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 351 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 352 353 { 0, 0 } 354 }; 355 356 static driver_t bce_driver = { 357 "bce", 358 bce_methods, 359 sizeof(struct bce_softc) 360 }; 361 362 static devclass_t bce_devclass; 363 364 MODULE_DEPEND(bce, pci, 1, 1, 1); 365 MODULE_DEPEND(bce, ether, 1, 1, 1); 366 MODULE_DEPEND(bce, miibus, 1, 1, 1); 367 368 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 369 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 370 371 372 /****************************************************************************/ 373 /* Device probe function. */ 374 /* */ 375 /* Compares the device to the driver's list of supported devices and */ 376 /* reports back to the OS whether this is the right driver for the device. */ 377 /* */ 378 /* Returns: */ 379 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 380 /****************************************************************************/ 381 static int 382 bce_probe(device_t dev) 383 { 384 struct bce_type *t; 385 struct bce_softc *sc; 386 char *descbuf; 387 u16 vid = 0, did = 0, svid = 0, sdid = 0; 388 389 t = bce_devs; 390 391 sc = device_get_softc(dev); 392 bzero(sc, sizeof(struct bce_softc)); 393 sc->bce_unit = device_get_unit(dev); 394 sc->bce_dev = dev; 395 396 /* Get the data for the device to be probed. */ 397 vid = pci_get_vendor(dev); 398 did = pci_get_device(dev); 399 svid = pci_get_subvendor(dev); 400 sdid = pci_get_subdevice(dev); 401 402 DBPRINT(sc, BCE_VERBOSE_LOAD, 403 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 404 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 405 406 /* Look through the list of known devices for a match. */ 407 while(t->bce_name != NULL) { 408 409 if ((vid == t->bce_vid) && (did == t->bce_did) && 410 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 411 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 412 413 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 414 415 if (descbuf == NULL) 416 return(ENOMEM); 417 418 /* Print out the device identity. */ 419 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d), %s", 420 t->bce_name, 421 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 422 (pci_read_config(dev, PCIR_REVID, 4) & 0xf), 423 bce_driver_version); 424 425 device_set_desc_copy(dev, descbuf); 426 free(descbuf, M_TEMP); 427 return(BUS_PROBE_DEFAULT); 428 } 429 t++; 430 } 431 432 DBPRINT(sc, BCE_VERBOSE_LOAD, "%s(%d): No IOCTL match found!\n", 433 __FILE__, __LINE__); 434 435 return(ENXIO); 436 } 437 438 439 /****************************************************************************/ 440 /* Device attach function. */ 441 /* */ 442 /* Allocates device resources, performs secondary chip identification, */ 443 /* resets and initializes the hardware, and initializes driver instance */ 444 /* variables. */ 445 /* */ 446 /* Returns: */ 447 /* 0 on success, positive value on failure. */ 448 /****************************************************************************/ 449 static int 450 bce_attach(device_t dev) 451 { 452 struct bce_softc *sc; 453 struct ifnet *ifp; 454 u32 val; 455 int mbuf, rid, rc = 0; 456 457 sc = device_get_softc(dev); 458 sc->bce_dev = dev; 459 460 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 461 462 mbuf = device_get_unit(dev); 463 sc->bce_unit = mbuf; 464 465 pci_enable_busmaster(dev); 466 467 /* Allocate PCI memory resources. */ 468 rid = PCIR_BAR(0); 469 sc->bce_res = bus_alloc_resource_any( 470 dev, /* dev */ 471 SYS_RES_MEMORY, /* type */ 472 &rid, /* rid */ 473 RF_ACTIVE | PCI_RF_DENSE); /* flags */ 474 475 if (sc->bce_res == NULL) { 476 BCE_PRINTF(sc, "%s(%d): PCI memory allocation failed\n", 477 __FILE__, __LINE__); 478 rc = ENXIO; 479 goto bce_attach_fail; 480 } 481 482 /* Get various resource handles. */ 483 sc->bce_btag = rman_get_bustag(sc->bce_res); 484 sc->bce_bhandle = rman_get_bushandle(sc->bce_res); 485 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res); 486 487 /* Allocate PCI IRQ resources. */ 488 rid = 0; 489 sc->bce_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 490 RF_SHAREABLE | RF_ACTIVE); 491 492 if (sc->bce_irq == NULL) { 493 BCE_PRINTF(sc, "%s(%d): PCI map interrupt failed\n", 494 __FILE__, __LINE__); 495 rc = ENXIO; 496 goto bce_attach_fail; 497 } 498 499 /* Initialize mutex for the current device instance. */ 500 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 501 502 /* 503 * Configure byte swap and enable indirect register access. 504 * Rely on CPU to do target byte swapping on big endian systems. 505 * Access to registers outside of PCI configurtion space are not 506 * valid until this is done. 507 */ 508 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 509 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 510 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 511 512 /* Save ASIC revsion info. */ 513 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 514 515 /* Weed out any non-production controller revisions. */ 516 switch(BCE_CHIP_ID(sc)) { 517 case BCE_CHIP_ID_5706_A0: 518 case BCE_CHIP_ID_5706_A1: 519 case BCE_CHIP_ID_5708_A0: 520 case BCE_CHIP_ID_5708_B0: 521 BCE_PRINTF(sc, "%s(%d): Unsupported controller revision (%c%d)!\n", 522 __FILE__, __LINE__, 523 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 524 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 525 rc = ENODEV; 526 goto bce_attach_fail; 527 } 528 529 if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) { 530 BCE_PRINTF(sc, "%s(%d): SerDes controllers are not supported!\n", 531 __FILE__, __LINE__); 532 rc = ENODEV; 533 goto bce_attach_fail; 534 } 535 536 /* 537 * The embedded PCIe to PCI-X bridge (EPB) 538 * in the 5708 cannot address memory above 539 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 540 */ 541 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 542 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 543 else 544 sc->max_bus_addr = BUS_SPACE_MAXADDR; 545 546 /* 547 * Find the base address for shared memory access. 548 * Newer versions of bootcode use a signature and offset 549 * while older versions use a fixed address. 550 */ 551 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 552 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 553 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0); 554 else 555 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 556 557 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base); 558 559 /* Set initial device and PHY flags */ 560 sc->bce_flags = 0; 561 sc->bce_phy_flags = 0; 562 563 /* Get PCI bus information (speed and type). */ 564 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 565 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 566 u32 clkreg; 567 568 sc->bce_flags |= BCE_PCIX_FLAG; 569 570 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 571 572 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 573 switch (clkreg) { 574 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 575 sc->bus_speed_mhz = 133; 576 break; 577 578 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 579 sc->bus_speed_mhz = 100; 580 break; 581 582 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 583 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 584 sc->bus_speed_mhz = 66; 585 break; 586 587 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 588 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 589 sc->bus_speed_mhz = 50; 590 break; 591 592 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 593 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 594 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 595 sc->bus_speed_mhz = 33; 596 break; 597 } 598 } else { 599 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 600 sc->bus_speed_mhz = 66; 601 else 602 sc->bus_speed_mhz = 33; 603 } 604 605 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 606 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 607 608 BCE_PRINTF(sc, "ASIC ID 0x%08X; Revision (%c%d); PCI%s %s %dMHz\n", 609 sc->bce_chipid, 610 ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A', 611 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4), 612 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 613 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), 614 sc->bus_speed_mhz); 615 616 /* Reset the controller. */ 617 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 618 rc = ENXIO; 619 goto bce_attach_fail; 620 } 621 622 /* Initialize the controller. */ 623 if (bce_chipinit(sc)) { 624 BCE_PRINTF(sc, "%s(%d): Controller initialization failed!\n", 625 __FILE__, __LINE__); 626 rc = ENXIO; 627 goto bce_attach_fail; 628 } 629 630 /* Perform NVRAM test. */ 631 if (bce_nvram_test(sc)) { 632 BCE_PRINTF(sc, "%s(%d): NVRAM test failed!\n", 633 __FILE__, __LINE__); 634 rc = ENXIO; 635 goto bce_attach_fail; 636 } 637 638 /* Fetch the permanent Ethernet MAC address. */ 639 bce_get_mac_addr(sc); 640 641 /* 642 * Trip points control how many BDs 643 * should be ready before generating an 644 * interrupt while ticks control how long 645 * a BD can sit in the chain before 646 * generating an interrupt. Set the default 647 * values for the RX and TX rings. 648 */ 649 650 #ifdef BCE_DRBUG 651 /* Force more frequent interrupts. */ 652 sc->bce_tx_quick_cons_trip_int = 1; 653 sc->bce_tx_quick_cons_trip = 1; 654 sc->bce_tx_ticks_int = 0; 655 sc->bce_tx_ticks = 0; 656 657 sc->bce_rx_quick_cons_trip_int = 1; 658 sc->bce_rx_quick_cons_trip = 1; 659 sc->bce_rx_ticks_int = 0; 660 sc->bce_rx_ticks = 0; 661 #else 662 sc->bce_tx_quick_cons_trip_int = 20; 663 sc->bce_tx_quick_cons_trip = 20; 664 sc->bce_tx_ticks_int = 80; 665 sc->bce_tx_ticks = 80; 666 667 sc->bce_rx_quick_cons_trip_int = 6; 668 sc->bce_rx_quick_cons_trip = 6; 669 sc->bce_rx_ticks_int = 18; 670 sc->bce_rx_ticks = 18; 671 #endif 672 673 /* Update statistics once every second. */ 674 sc->bce_stats_ticks = 1000000 & 0xffff00; 675 676 /* 677 * The copper based NetXtreme II controllers 678 * use an integrated PHY at address 1 while 679 * the SerDes controllers use a PHY at 680 * address 2. 681 */ 682 sc->bce_phy_addr = 1; 683 684 if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) { 685 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 686 sc->bce_flags |= BCE_NO_WOL_FLAG; 687 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) { 688 sc->bce_phy_addr = 2; 689 val = REG_RD_IND(sc, sc->bce_shmem_base + 690 BCE_SHARED_HW_CFG_CONFIG); 691 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) 692 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG; 693 } 694 } 695 696 /* Allocate DMA memory resources. */ 697 if (bce_dma_alloc(dev)) { 698 BCE_PRINTF(sc, "%s(%d): DMA resource allocation failed!\n", 699 __FILE__, __LINE__); 700 rc = ENXIO; 701 goto bce_attach_fail; 702 } 703 704 /* Allocate an ifnet structure. */ 705 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 706 if (ifp == NULL) { 707 BCE_PRINTF(sc, "%s(%d): Interface allocation failed!\n", 708 __FILE__, __LINE__); 709 rc = ENXIO; 710 goto bce_attach_fail; 711 } 712 713 /* Initialize the ifnet interface. */ 714 ifp->if_softc = sc; 715 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 716 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 717 ifp->if_ioctl = bce_ioctl; 718 ifp->if_start = bce_start; 719 ifp->if_timer = 0; 720 ifp->if_watchdog = bce_watchdog; 721 ifp->if_init = bce_init; 722 ifp->if_mtu = ETHERMTU; 723 ifp->if_hwassist = BCE_IF_HWASSIST; 724 ifp->if_capabilities = BCE_IF_CAPABILITIES; 725 ifp->if_capenable = ifp->if_capabilities; 726 727 /* Assume a standard 1500 byte MTU size for mbuf allocations. */ 728 sc->mbuf_alloc_size = MCLBYTES; 729 #ifdef DEVICE_POLLING 730 ifp->if_capabilities |= IFCAP_POLLING; 731 #endif 732 733 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 734 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 735 ifp->if_baudrate = IF_Gbps(2.5); 736 else 737 ifp->if_baudrate = IF_Gbps(1); 738 739 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 740 IFQ_SET_READY(&ifp->if_snd); 741 742 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 743 BCE_PRINTF(sc, "%s(%d): SerDes is not supported by this driver!\n", 744 __FILE__, __LINE__); 745 rc = ENODEV; 746 goto bce_attach_fail; 747 } else { 748 /* Look for our PHY. */ 749 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 750 bce_ifmedia_sts)) { 751 BCE_PRINTF(sc, "%s(%d): PHY probe failed!\n", 752 __FILE__, __LINE__); 753 rc = ENXIO; 754 goto bce_attach_fail; 755 } 756 } 757 758 /* Attach to the Ethernet interface list. */ 759 ether_ifattach(ifp, sc->eaddr); 760 761 #if __FreeBSD_version < 500000 762 callout_init(&sc->bce_stat_ch); 763 #else 764 callout_init(&sc->bce_stat_ch, CALLOUT_MPSAFE); 765 #endif 766 767 /* Hookup IRQ last. */ 768 rc = bus_setup_intr(dev, sc->bce_irq, INTR_TYPE_NET | INTR_MPSAFE, 769 bce_intr, sc, &sc->bce_intrhand); 770 771 if (rc) { 772 BCE_PRINTF(sc, "%s(%d): Failed to setup IRQ!\n", 773 __FILE__, __LINE__); 774 bce_detach(dev); 775 goto bce_attach_exit; 776 } 777 778 /* Print some important debugging info. */ 779 DBRUN(BCE_INFO, bce_dump_driver_state(sc)); 780 781 /* Add the supported sysctls to the kernel. */ 782 bce_add_sysctls(sc); 783 784 /* Get the firmware running so IPMI still works */ 785 BCE_LOCK(sc); 786 bce_mgmt_init_locked(sc); 787 BCE_UNLOCK(sc); 788 789 goto bce_attach_exit; 790 791 bce_attach_fail: 792 bce_release_resources(sc); 793 794 bce_attach_exit: 795 796 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 797 798 return(rc); 799 } 800 801 802 /****************************************************************************/ 803 /* Device detach function. */ 804 /* */ 805 /* Stops the controller, resets the controller, and releases resources. */ 806 /* */ 807 /* Returns: */ 808 /* 0 on success, positive value on failure. */ 809 /****************************************************************************/ 810 static int 811 bce_detach(device_t dev) 812 { 813 struct bce_softc *sc; 814 struct ifnet *ifp; 815 816 sc = device_get_softc(dev); 817 818 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 819 820 ifp = sc->bce_ifp; 821 822 #ifdef DEVICE_POLLING 823 if (ifp->if_capenable & IFCAP_POLLING) 824 ether_poll_deregister(ifp); 825 #endif 826 827 /* Stop and reset the controller. */ 828 BCE_LOCK(sc); 829 bce_stop(sc); 830 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 831 BCE_UNLOCK(sc); 832 833 ether_ifdetach(ifp); 834 835 /* If we have a child device on the MII bus remove it too. */ 836 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 837 ifmedia_removeall(&sc->bce_ifmedia); 838 } else { 839 bus_generic_detach(dev); 840 device_delete_child(dev, sc->bce_miibus); 841 } 842 843 /* Release all remaining resources. */ 844 bce_release_resources(sc); 845 846 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 847 848 return(0); 849 } 850 851 852 /****************************************************************************/ 853 /* Device shutdown function. */ 854 /* */ 855 /* Stops and resets the controller. */ 856 /* */ 857 /* Returns: */ 858 /* Nothing */ 859 /****************************************************************************/ 860 static void 861 bce_shutdown(device_t dev) 862 { 863 struct bce_softc *sc = device_get_softc(dev); 864 865 BCE_LOCK(sc); 866 bce_stop(sc); 867 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 868 BCE_UNLOCK(sc); 869 } 870 871 872 /****************************************************************************/ 873 /* Indirect register read. */ 874 /* */ 875 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 876 /* configuration space. Using this mechanism avoids issues with posted */ 877 /* reads but is much slower than memory-mapped I/O. */ 878 /* */ 879 /* Returns: */ 880 /* The value of the register. */ 881 /****************************************************************************/ 882 static u32 883 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 884 { 885 device_t dev; 886 dev = sc->bce_dev; 887 888 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 889 #ifdef BCE_DEBUG 890 { 891 u32 val; 892 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 893 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 894 __FUNCTION__, offset, val); 895 return val; 896 } 897 #else 898 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 899 #endif 900 } 901 902 903 /****************************************************************************/ 904 /* Indirect register write. */ 905 /* */ 906 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 907 /* configuration space. Using this mechanism avoids issues with posted */ 908 /* writes but is muchh slower than memory-mapped I/O. */ 909 /* */ 910 /* Returns: */ 911 /* Nothing. */ 912 /****************************************************************************/ 913 static void 914 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 915 { 916 device_t dev; 917 dev = sc->bce_dev; 918 919 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 920 __FUNCTION__, offset, val); 921 922 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 923 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 924 } 925 926 927 /****************************************************************************/ 928 /* Context memory write. */ 929 /* */ 930 /* The NetXtreme II controller uses context memory to track connection */ 931 /* information for L2 and higher network protocols. */ 932 /* */ 933 /* Returns: */ 934 /* Nothing. */ 935 /****************************************************************************/ 936 static void 937 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 offset, u32 val) 938 { 939 940 DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 941 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val); 942 943 offset += cid_addr; 944 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 945 REG_WR(sc, BCE_CTX_DATA, val); 946 } 947 948 949 /****************************************************************************/ 950 /* PHY register read. */ 951 /* */ 952 /* Implements register reads on the MII bus. */ 953 /* */ 954 /* Returns: */ 955 /* The value of the register. */ 956 /****************************************************************************/ 957 static int 958 bce_miibus_read_reg(device_t dev, int phy, int reg) 959 { 960 struct bce_softc *sc; 961 u32 val; 962 int i; 963 964 sc = device_get_softc(dev); 965 966 /* Make sure we are accessing the correct PHY address. */ 967 if (phy != sc->bce_phy_addr) { 968 DBPRINT(sc, BCE_VERBOSE, "Invalid PHY address %d for PHY read!\n", phy); 969 return(0); 970 } 971 972 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 973 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 974 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 975 976 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 977 REG_RD(sc, BCE_EMAC_MDIO_MODE); 978 979 DELAY(40); 980 } 981 982 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 983 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 984 BCE_EMAC_MDIO_COMM_START_BUSY; 985 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 986 987 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 988 DELAY(10); 989 990 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 991 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 992 DELAY(5); 993 994 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 995 val &= BCE_EMAC_MDIO_COMM_DATA; 996 997 break; 998 } 999 } 1000 1001 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1002 BCE_PRINTF(sc, "%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n", 1003 __FILE__, __LINE__, phy, reg); 1004 val = 0x0; 1005 } else { 1006 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1007 } 1008 1009 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1010 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1011 1012 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1013 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1014 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1015 1016 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1017 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1018 1019 DELAY(40); 1020 } 1021 1022 return (val & 0xffff); 1023 1024 } 1025 1026 1027 /****************************************************************************/ 1028 /* PHY register write. */ 1029 /* */ 1030 /* Implements register writes on the MII bus. */ 1031 /* */ 1032 /* Returns: */ 1033 /* The value of the register. */ 1034 /****************************************************************************/ 1035 static int 1036 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1037 { 1038 struct bce_softc *sc; 1039 u32 val1; 1040 int i; 1041 1042 sc = device_get_softc(dev); 1043 1044 /* Make sure we are accessing the correct PHY address. */ 1045 if (phy != sc->bce_phy_addr) { 1046 DBPRINT(sc, BCE_WARN, "Invalid PHY address %d for PHY write!\n", phy); 1047 return(0); 1048 } 1049 1050 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1051 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1052 1053 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1054 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1055 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1056 1057 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1058 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1059 1060 DELAY(40); 1061 } 1062 1063 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1064 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1065 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1066 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1067 1068 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1069 DELAY(10); 1070 1071 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1072 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1073 DELAY(5); 1074 break; 1075 } 1076 } 1077 1078 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1079 BCE_PRINTF(sc, "%s(%d): PHY write timeout!\n", 1080 __FILE__, __LINE__); 1081 1082 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1083 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1084 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1085 1086 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1087 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1088 1089 DELAY(40); 1090 } 1091 1092 return 0; 1093 } 1094 1095 1096 /****************************************************************************/ 1097 /* MII bus status change. */ 1098 /* */ 1099 /* Called by the MII bus driver when the PHY establishes link to set the */ 1100 /* MAC interface registers. */ 1101 /* */ 1102 /* Returns: */ 1103 /* Nothing. */ 1104 /****************************************************************************/ 1105 static void 1106 bce_miibus_statchg(device_t dev) 1107 { 1108 struct bce_softc *sc; 1109 struct mii_data *mii; 1110 1111 sc = device_get_softc(dev); 1112 1113 mii = device_get_softc(sc->bce_miibus); 1114 1115 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT); 1116 1117 /* Set MII or GMII inerface based on the speed negotiated by the PHY. */ 1118 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 1119 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n"); 1120 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII); 1121 } else { 1122 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n"); 1123 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII); 1124 } 1125 1126 /* Set half or full duplex based on the duplicity negotiated by the PHY. */ 1127 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1128 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n"); 1129 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX); 1130 } else { 1131 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n"); 1132 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX); 1133 } 1134 } 1135 1136 1137 /****************************************************************************/ 1138 /* Acquire NVRAM lock. */ 1139 /* */ 1140 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1141 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1142 /* for use by the driver. */ 1143 /* */ 1144 /* Returns: */ 1145 /* 0 on success, positive value on failure. */ 1146 /****************************************************************************/ 1147 static int 1148 bce_acquire_nvram_lock(struct bce_softc *sc) 1149 { 1150 u32 val; 1151 int j; 1152 1153 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n"); 1154 1155 /* Request access to the flash interface. */ 1156 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1157 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1158 val = REG_RD(sc, BCE_NVM_SW_ARB); 1159 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1160 break; 1161 1162 DELAY(5); 1163 } 1164 1165 if (j >= NVRAM_TIMEOUT_COUNT) { 1166 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1167 return EBUSY; 1168 } 1169 1170 return 0; 1171 } 1172 1173 1174 /****************************************************************************/ 1175 /* Release NVRAM lock. */ 1176 /* */ 1177 /* When the caller is finished accessing NVRAM the lock must be released. */ 1178 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1179 /* for use by the driver. */ 1180 /* */ 1181 /* Returns: */ 1182 /* 0 on success, positive value on failure. */ 1183 /****************************************************************************/ 1184 static int 1185 bce_release_nvram_lock(struct bce_softc *sc) 1186 { 1187 int j; 1188 u32 val; 1189 1190 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n"); 1191 1192 /* 1193 * Relinquish nvram interface. 1194 */ 1195 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1196 1197 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1198 val = REG_RD(sc, BCE_NVM_SW_ARB); 1199 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1200 break; 1201 1202 DELAY(5); 1203 } 1204 1205 if (j >= NVRAM_TIMEOUT_COUNT) { 1206 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n"); 1207 return EBUSY; 1208 } 1209 1210 return 0; 1211 } 1212 1213 1214 #ifdef BCE_NVRAM_WRITE_SUPPORT 1215 /****************************************************************************/ 1216 /* Enable NVRAM write access. */ 1217 /* */ 1218 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1219 /* */ 1220 /* Returns: */ 1221 /* 0 on success, positive value on failure. */ 1222 /****************************************************************************/ 1223 static int 1224 bce_enable_nvram_write(struct bce_softc *sc) 1225 { 1226 u32 val; 1227 1228 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM write.\n"); 1229 1230 val = REG_RD(sc, BCE_MISC_CFG); 1231 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1232 1233 if (!sc->bce_flash_info->buffered) { 1234 int j; 1235 1236 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1237 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1238 1239 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1240 DELAY(5); 1241 1242 val = REG_RD(sc, BCE_NVM_COMMAND); 1243 if (val & BCE_NVM_COMMAND_DONE) 1244 break; 1245 } 1246 1247 if (j >= NVRAM_TIMEOUT_COUNT) { 1248 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1249 return EBUSY; 1250 } 1251 } 1252 return 0; 1253 } 1254 1255 1256 /****************************************************************************/ 1257 /* Disable NVRAM write access. */ 1258 /* */ 1259 /* When the caller is finished writing to NVRAM write access must be */ 1260 /* disabled. */ 1261 /* */ 1262 /* Returns: */ 1263 /* Nothing. */ 1264 /****************************************************************************/ 1265 static void 1266 bce_disable_nvram_write(struct bce_softc *sc) 1267 { 1268 u32 val; 1269 1270 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM write.\n"); 1271 1272 val = REG_RD(sc, BCE_MISC_CFG); 1273 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1274 } 1275 #endif 1276 1277 1278 /****************************************************************************/ 1279 /* Enable NVRAM access. */ 1280 /* */ 1281 /* Before accessing NVRAM for read or write operations the caller must */ 1282 /* enabled NVRAM access. */ 1283 /* */ 1284 /* Returns: */ 1285 /* Nothing. */ 1286 /****************************************************************************/ 1287 static void 1288 bce_enable_nvram_access(struct bce_softc *sc) 1289 { 1290 u32 val; 1291 1292 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n"); 1293 1294 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1295 /* Enable both bits, even on read. */ 1296 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1297 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1298 } 1299 1300 1301 /****************************************************************************/ 1302 /* Disable NVRAM access. */ 1303 /* */ 1304 /* When the caller is finished accessing NVRAM access must be disabled. */ 1305 /* */ 1306 /* Returns: */ 1307 /* Nothing. */ 1308 /****************************************************************************/ 1309 static void 1310 bce_disable_nvram_access(struct bce_softc *sc) 1311 { 1312 u32 val; 1313 1314 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n"); 1315 1316 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1317 1318 /* Disable both bits, even after read. */ 1319 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1320 val & ~(BCE_NVM_ACCESS_ENABLE_EN | 1321 BCE_NVM_ACCESS_ENABLE_WR_EN)); 1322 } 1323 1324 1325 #ifdef BCE_NVRAM_WRITE_SUPPORT 1326 /****************************************************************************/ 1327 /* Erase NVRAM page before writing. */ 1328 /* */ 1329 /* Non-buffered flash parts require that a page be erased before it is */ 1330 /* written. */ 1331 /* */ 1332 /* Returns: */ 1333 /* 0 on success, positive value on failure. */ 1334 /****************************************************************************/ 1335 static int 1336 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 1337 { 1338 u32 cmd; 1339 int j; 1340 1341 /* Buffered flash doesn't require an erase. */ 1342 if (sc->bce_flash_info->buffered) 1343 return 0; 1344 1345 DBPRINT(sc, BCE_VERBOSE, "Erasing NVRAM page.\n"); 1346 1347 /* Build an erase command. */ 1348 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 1349 BCE_NVM_COMMAND_DOIT; 1350 1351 /* 1352 * Clear the DONE bit separately, set the NVRAM adress to erase, 1353 * and issue the erase command. 1354 */ 1355 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1356 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1357 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1358 1359 /* Wait for completion. */ 1360 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1361 u32 val; 1362 1363 DELAY(5); 1364 1365 val = REG_RD(sc, BCE_NVM_COMMAND); 1366 if (val & BCE_NVM_COMMAND_DONE) 1367 break; 1368 } 1369 1370 if (j >= NVRAM_TIMEOUT_COUNT) { 1371 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 1372 return EBUSY; 1373 } 1374 1375 return 0; 1376 } 1377 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1378 1379 1380 /****************************************************************************/ 1381 /* Read a dword (32 bits) from NVRAM. */ 1382 /* */ 1383 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1384 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1385 /* */ 1386 /* Returns: */ 1387 /* 0 on success and the 32 bit value read, positive value on failure. */ 1388 /****************************************************************************/ 1389 static int 1390 bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val, 1391 u32 cmd_flags) 1392 { 1393 u32 cmd; 1394 int i, rc = 0; 1395 1396 /* Build the command word. */ 1397 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 1398 1399 /* Calculate the offset for buffered flash. */ 1400 if (sc->bce_flash_info->buffered) { 1401 offset = ((offset / sc->bce_flash_info->page_size) << 1402 sc->bce_flash_info->page_bits) + 1403 (offset % sc->bce_flash_info->page_size); 1404 } 1405 1406 /* 1407 * Clear the DONE bit separately, set the address to read, 1408 * and issue the read. 1409 */ 1410 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1411 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1412 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1413 1414 /* Wait for completion. */ 1415 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1416 u32 val; 1417 1418 DELAY(5); 1419 1420 val = REG_RD(sc, BCE_NVM_COMMAND); 1421 if (val & BCE_NVM_COMMAND_DONE) { 1422 val = REG_RD(sc, BCE_NVM_READ); 1423 1424 val = bce_be32toh(val); 1425 memcpy(ret_val, &val, 4); 1426 break; 1427 } 1428 } 1429 1430 /* Check for errors. */ 1431 if (i >= NVRAM_TIMEOUT_COUNT) { 1432 BCE_PRINTF(sc, "%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n", 1433 __FILE__, __LINE__, offset); 1434 rc = EBUSY; 1435 } 1436 1437 return(rc); 1438 } 1439 1440 1441 #ifdef BCE_NVRAM_WRITE_SUPPORT 1442 /****************************************************************************/ 1443 /* Write a dword (32 bits) to NVRAM. */ 1444 /* */ 1445 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1446 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1447 /* enabled NVRAM write access. */ 1448 /* */ 1449 /* Returns: */ 1450 /* 0 on success, positive value on failure. */ 1451 /****************************************************************************/ 1452 static int 1453 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 1454 u32 cmd_flags) 1455 { 1456 u32 cmd, val32; 1457 int j; 1458 1459 /* Build the command word. */ 1460 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 1461 1462 /* Calculate the offset for buffered flash. */ 1463 if (sc->bce_flash_info->buffered) { 1464 offset = ((offset / sc->bce_flash_info->page_size) << 1465 sc->bce_flash_info->page_bits) + 1466 (offset % sc->bce_flash_info->page_size); 1467 } 1468 1469 /* 1470 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1471 * set the NVRAM address to write, and issue the write command 1472 */ 1473 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1474 memcpy(&val32, val, 4); 1475 val32 = htobe32(val32); 1476 REG_WR(sc, BCE_NVM_WRITE, val32); 1477 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1478 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1479 1480 /* Wait for completion. */ 1481 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1482 DELAY(5); 1483 1484 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 1485 break; 1486 } 1487 if (j >= NVRAM_TIMEOUT_COUNT) { 1488 BCE_PRINTF(sc, "%s(%d): Timeout error writing NVRAM at offset 0x%08X\n", 1489 __FILE__, __LINE__, offset); 1490 return EBUSY; 1491 } 1492 1493 return 0; 1494 } 1495 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1496 1497 1498 /****************************************************************************/ 1499 /* Initialize NVRAM access. */ 1500 /* */ 1501 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1502 /* access that device. */ 1503 /* */ 1504 /* Returns: */ 1505 /* 0 on success, positive value on failure. */ 1506 /****************************************************************************/ 1507 static int 1508 bce_init_nvram(struct bce_softc *sc) 1509 { 1510 u32 val; 1511 int j, entry_count, rc; 1512 struct flash_spec *flash; 1513 1514 DBPRINT(sc,BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1515 1516 /* Determine the selected interface. */ 1517 val = REG_RD(sc, BCE_NVM_CFG1); 1518 1519 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1520 1521 rc = 0; 1522 1523 /* 1524 * Flash reconfiguration is required to support additional 1525 * NVRAM devices not directly supported in hardware. 1526 * Check if the flash interface was reconfigured 1527 * by the bootcode. 1528 */ 1529 1530 if (val & 0x40000000) { 1531 /* Flash interface reconfigured by bootcode. */ 1532 1533 DBPRINT(sc,BCE_INFO_LOAD, 1534 "bce_init_nvram(): Flash WAS reconfigured.\n"); 1535 1536 for (j = 0, flash = &flash_table[0]; j < entry_count; 1537 j++, flash++) { 1538 if ((val & FLASH_BACKUP_STRAP_MASK) == 1539 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1540 sc->bce_flash_info = flash; 1541 break; 1542 } 1543 } 1544 } else { 1545 /* Flash interface not yet reconfigured. */ 1546 u32 mask; 1547 1548 DBPRINT(sc,BCE_INFO_LOAD, 1549 "bce_init_nvram(): Flash was NOT reconfigured.\n"); 1550 1551 if (val & (1 << 23)) 1552 mask = FLASH_BACKUP_STRAP_MASK; 1553 else 1554 mask = FLASH_STRAP_MASK; 1555 1556 /* Look for the matching NVRAM device configuration data. */ 1557 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 1558 1559 /* Check if the device matches any of the known devices. */ 1560 if ((val & mask) == (flash->strapping & mask)) { 1561 /* Found a device match. */ 1562 sc->bce_flash_info = flash; 1563 1564 /* Request access to the flash interface. */ 1565 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1566 return rc; 1567 1568 /* Reconfigure the flash interface. */ 1569 bce_enable_nvram_access(sc); 1570 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 1571 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 1572 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 1573 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 1574 bce_disable_nvram_access(sc); 1575 bce_release_nvram_lock(sc); 1576 1577 break; 1578 } 1579 } 1580 } 1581 1582 /* Check if a matching device was found. */ 1583 if (j == entry_count) { 1584 sc->bce_flash_info = NULL; 1585 BCE_PRINTF(sc, "%s(%d): Unknown Flash NVRAM found!\n", 1586 __FILE__, __LINE__); 1587 rc = ENODEV; 1588 } 1589 1590 /* Write the flash config data to the shared memory interface. */ 1591 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2); 1592 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 1593 if (val) 1594 sc->bce_flash_size = val; 1595 else 1596 sc->bce_flash_size = sc->bce_flash_info->total_size; 1597 1598 DBPRINT(sc, BCE_INFO_LOAD, "bce_init_nvram() flash->total_size = 0x%08X\n", 1599 sc->bce_flash_info->total_size); 1600 1601 DBPRINT(sc,BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 1602 1603 return rc; 1604 } 1605 1606 1607 /****************************************************************************/ 1608 /* Read an arbitrary range of data from NVRAM. */ 1609 /* */ 1610 /* Prepares the NVRAM interface for access and reads the requested data */ 1611 /* into the supplied buffer. */ 1612 /* */ 1613 /* Returns: */ 1614 /* 0 on success and the data read, positive value on failure. */ 1615 /****************************************************************************/ 1616 static int 1617 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 1618 int buf_size) 1619 { 1620 int rc = 0; 1621 u32 cmd_flags, offset32, len32, extra; 1622 1623 if (buf_size == 0) 1624 return 0; 1625 1626 /* Request access to the flash interface. */ 1627 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1628 return rc; 1629 1630 /* Enable access to flash interface */ 1631 bce_enable_nvram_access(sc); 1632 1633 len32 = buf_size; 1634 offset32 = offset; 1635 extra = 0; 1636 1637 cmd_flags = 0; 1638 1639 if (offset32 & 3) { 1640 u8 buf[4]; 1641 u32 pre_len; 1642 1643 offset32 &= ~3; 1644 pre_len = 4 - (offset & 3); 1645 1646 if (pre_len >= len32) { 1647 pre_len = len32; 1648 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 1649 } 1650 else { 1651 cmd_flags = BCE_NVM_COMMAND_FIRST; 1652 } 1653 1654 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1655 1656 if (rc) 1657 return rc; 1658 1659 memcpy(ret_buf, buf + (offset & 3), pre_len); 1660 1661 offset32 += 4; 1662 ret_buf += pre_len; 1663 len32 -= pre_len; 1664 } 1665 1666 if (len32 & 3) { 1667 extra = 4 - (len32 & 3); 1668 len32 = (len32 + 4) & ~3; 1669 } 1670 1671 if (len32 == 4) { 1672 u8 buf[4]; 1673 1674 if (cmd_flags) 1675 cmd_flags = BCE_NVM_COMMAND_LAST; 1676 else 1677 cmd_flags = BCE_NVM_COMMAND_FIRST | 1678 BCE_NVM_COMMAND_LAST; 1679 1680 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1681 1682 memcpy(ret_buf, buf, 4 - extra); 1683 } 1684 else if (len32 > 0) { 1685 u8 buf[4]; 1686 1687 /* Read the first word. */ 1688 if (cmd_flags) 1689 cmd_flags = 0; 1690 else 1691 cmd_flags = BCE_NVM_COMMAND_FIRST; 1692 1693 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1694 1695 /* Advance to the next dword. */ 1696 offset32 += 4; 1697 ret_buf += 4; 1698 len32 -= 4; 1699 1700 while (len32 > 4 && rc == 0) { 1701 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 1702 1703 /* Advance to the next dword. */ 1704 offset32 += 4; 1705 ret_buf += 4; 1706 len32 -= 4; 1707 } 1708 1709 if (rc) 1710 return rc; 1711 1712 cmd_flags = BCE_NVM_COMMAND_LAST; 1713 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1714 1715 memcpy(ret_buf, buf, 4 - extra); 1716 } 1717 1718 /* Disable access to flash interface and release the lock. */ 1719 bce_disable_nvram_access(sc); 1720 bce_release_nvram_lock(sc); 1721 1722 return rc; 1723 } 1724 1725 1726 #ifdef BCE_NVRAM_WRITE_SUPPORT 1727 /****************************************************************************/ 1728 /* Write an arbitrary range of data from NVRAM. */ 1729 /* */ 1730 /* Prepares the NVRAM interface for write access and writes the requested */ 1731 /* data from the supplied buffer. The caller is responsible for */ 1732 /* calculating any appropriate CRCs. */ 1733 /* */ 1734 /* Returns: */ 1735 /* 0 on success, positive value on failure. */ 1736 /****************************************************************************/ 1737 static int 1738 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 1739 int buf_size) 1740 { 1741 u32 written, offset32, len32; 1742 u8 *buf, start[4], end[4]; 1743 int rc = 0; 1744 int align_start, align_end; 1745 1746 buf = data_buf; 1747 offset32 = offset; 1748 len32 = buf_size; 1749 align_start = align_end = 0; 1750 1751 if ((align_start = (offset32 & 3))) { 1752 offset32 &= ~3; 1753 len32 += align_start; 1754 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 1755 return rc; 1756 } 1757 1758 if (len32 & 3) { 1759 if ((len32 > 4) || !align_start) { 1760 align_end = 4 - (len32 & 3); 1761 len32 += align_end; 1762 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 1763 end, 4))) { 1764 return rc; 1765 } 1766 } 1767 } 1768 1769 if (align_start || align_end) { 1770 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1771 if (buf == 0) 1772 return ENOMEM; 1773 if (align_start) { 1774 memcpy(buf, start, 4); 1775 } 1776 if (align_end) { 1777 memcpy(buf + len32 - 4, end, 4); 1778 } 1779 memcpy(buf + align_start, data_buf, buf_size); 1780 } 1781 1782 written = 0; 1783 while ((written < len32) && (rc == 0)) { 1784 u32 page_start, page_end, data_start, data_end; 1785 u32 addr, cmd_flags; 1786 int i; 1787 u8 flash_buffer[264]; 1788 1789 /* Find the page_start addr */ 1790 page_start = offset32 + written; 1791 page_start -= (page_start % sc->bce_flash_info->page_size); 1792 /* Find the page_end addr */ 1793 page_end = page_start + sc->bce_flash_info->page_size; 1794 /* Find the data_start addr */ 1795 data_start = (written == 0) ? offset32 : page_start; 1796 /* Find the data_end addr */ 1797 data_end = (page_end > offset32 + len32) ? 1798 (offset32 + len32) : page_end; 1799 1800 /* Request access to the flash interface. */ 1801 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1802 goto nvram_write_end; 1803 1804 /* Enable access to flash interface */ 1805 bce_enable_nvram_access(sc); 1806 1807 cmd_flags = BCE_NVM_COMMAND_FIRST; 1808 if (sc->bce_flash_info->buffered == 0) { 1809 int j; 1810 1811 /* Read the whole page into the buffer 1812 * (non-buffer flash only) */ 1813 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 1814 if (j == (sc->bce_flash_info->page_size - 4)) { 1815 cmd_flags |= BCE_NVM_COMMAND_LAST; 1816 } 1817 rc = bce_nvram_read_dword(sc, 1818 page_start + j, 1819 &flash_buffer[j], 1820 cmd_flags); 1821 1822 if (rc) 1823 goto nvram_write_end; 1824 1825 cmd_flags = 0; 1826 } 1827 } 1828 1829 /* Enable writes to flash interface (unlock write-protect) */ 1830 if ((rc = bce_enable_nvram_write(sc)) != 0) 1831 goto nvram_write_end; 1832 1833 /* Erase the page */ 1834 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 1835 goto nvram_write_end; 1836 1837 /* Re-enable the write again for the actual write */ 1838 bce_enable_nvram_write(sc); 1839 1840 /* Loop to write back the buffer data from page_start to 1841 * data_start */ 1842 i = 0; 1843 if (sc->bce_flash_info->buffered == 0) { 1844 for (addr = page_start; addr < data_start; 1845 addr += 4, i += 4) { 1846 1847 rc = bce_nvram_write_dword(sc, addr, 1848 &flash_buffer[i], cmd_flags); 1849 1850 if (rc != 0) 1851 goto nvram_write_end; 1852 1853 cmd_flags = 0; 1854 } 1855 } 1856 1857 /* Loop to write the new data from data_start to data_end */ 1858 for (addr = data_start; addr < data_end; addr += 4, i++) { 1859 if ((addr == page_end - 4) || 1860 ((sc->bce_flash_info->buffered) && 1861 (addr == data_end - 4))) { 1862 1863 cmd_flags |= BCE_NVM_COMMAND_LAST; 1864 } 1865 rc = bce_nvram_write_dword(sc, addr, buf, 1866 cmd_flags); 1867 1868 if (rc != 0) 1869 goto nvram_write_end; 1870 1871 cmd_flags = 0; 1872 buf += 4; 1873 } 1874 1875 /* Loop to write back the buffer data from data_end 1876 * to page_end */ 1877 if (sc->bce_flash_info->buffered == 0) { 1878 for (addr = data_end; addr < page_end; 1879 addr += 4, i += 4) { 1880 1881 if (addr == page_end-4) { 1882 cmd_flags = BCE_NVM_COMMAND_LAST; 1883 } 1884 rc = bce_nvram_write_dword(sc, addr, 1885 &flash_buffer[i], cmd_flags); 1886 1887 if (rc != 0) 1888 goto nvram_write_end; 1889 1890 cmd_flags = 0; 1891 } 1892 } 1893 1894 /* Disable writes to flash interface (lock write-protect) */ 1895 bce_disable_nvram_write(sc); 1896 1897 /* Disable access to flash interface */ 1898 bce_disable_nvram_access(sc); 1899 bce_release_nvram_lock(sc); 1900 1901 /* Increment written */ 1902 written += data_end - data_start; 1903 } 1904 1905 nvram_write_end: 1906 if (align_start || align_end) 1907 free(buf, M_DEVBUF); 1908 1909 return rc; 1910 } 1911 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1912 1913 1914 /****************************************************************************/ 1915 /* Verifies that NVRAM is accessible and contains valid data. */ 1916 /* */ 1917 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 1918 /* correct. */ 1919 /* */ 1920 /* Returns: */ 1921 /* 0 on success, positive value on failure. */ 1922 /****************************************************************************/ 1923 static int 1924 bce_nvram_test(struct bce_softc *sc) 1925 { 1926 u32 buf[BCE_NVRAM_SIZE / 4]; 1927 u8 *data = (u8 *) buf; 1928 int rc = 0; 1929 u32 magic, csum; 1930 1931 1932 /* 1933 * Check that the device NVRAM is valid by reading 1934 * the magic value at offset 0. 1935 */ 1936 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) 1937 goto bce_nvram_test_done; 1938 1939 1940 magic = bce_be32toh(buf[0]); 1941 if (magic != BCE_NVRAM_MAGIC) { 1942 rc = ENODEV; 1943 BCE_PRINTF(sc, "%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, " 1944 "Found: 0x%08X\n", 1945 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 1946 goto bce_nvram_test_done; 1947 } 1948 1949 /* 1950 * Verify that the device NVRAM includes valid 1951 * configuration data. 1952 */ 1953 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) 1954 goto bce_nvram_test_done; 1955 1956 csum = ether_crc32_le(data, 0x100); 1957 if (csum != BCE_CRC32_RESIDUAL) { 1958 rc = ENODEV; 1959 BCE_PRINTF(sc, "%s(%d): Invalid Manufacturing Information NVRAM CRC! " 1960 "Expected: 0x%08X, Found: 0x%08X\n", 1961 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 1962 goto bce_nvram_test_done; 1963 } 1964 1965 csum = ether_crc32_le(data + 0x100, 0x100); 1966 if (csum != BCE_CRC32_RESIDUAL) { 1967 BCE_PRINTF(sc, "%s(%d): Invalid Feature Configuration Information " 1968 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 1969 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 1970 rc = ENODEV; 1971 } 1972 1973 bce_nvram_test_done: 1974 return rc; 1975 } 1976 1977 1978 /****************************************************************************/ 1979 /* Free any DMA memory owned by the driver. */ 1980 /* */ 1981 /* Scans through each data structre that requires DMA memory and frees */ 1982 /* the memory if allocated. */ 1983 /* */ 1984 /* Returns: */ 1985 /* Nothing. */ 1986 /****************************************************************************/ 1987 static void 1988 bce_dma_free(struct bce_softc *sc) 1989 { 1990 int i; 1991 1992 DBPRINT(sc,BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 1993 1994 /* Destroy the status block. */ 1995 if (sc->status_block != NULL) 1996 bus_dmamem_free( 1997 sc->status_tag, 1998 sc->status_block, 1999 sc->status_map); 2000 2001 if (sc->status_map != NULL) { 2002 bus_dmamap_unload( 2003 sc->status_tag, 2004 sc->status_map); 2005 bus_dmamap_destroy(sc->status_tag, 2006 sc->status_map); 2007 } 2008 2009 if (sc->status_tag != NULL) 2010 bus_dma_tag_destroy(sc->status_tag); 2011 2012 2013 /* Destroy the statistics block. */ 2014 if (sc->stats_block != NULL) 2015 bus_dmamem_free( 2016 sc->stats_tag, 2017 sc->stats_block, 2018 sc->stats_map); 2019 2020 if (sc->stats_map != NULL) { 2021 bus_dmamap_unload( 2022 sc->stats_tag, 2023 sc->stats_map); 2024 bus_dmamap_destroy(sc->stats_tag, 2025 sc->stats_map); 2026 } 2027 2028 if (sc->stats_tag != NULL) 2029 bus_dma_tag_destroy(sc->stats_tag); 2030 2031 2032 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2033 for (i = 0; i < TX_PAGES; i++ ) { 2034 if (sc->tx_bd_chain[i] != NULL) 2035 bus_dmamem_free( 2036 sc->tx_bd_chain_tag, 2037 sc->tx_bd_chain[i], 2038 sc->tx_bd_chain_map[i]); 2039 2040 if (sc->tx_bd_chain_map[i] != NULL) { 2041 bus_dmamap_unload( 2042 sc->tx_bd_chain_tag, 2043 sc->tx_bd_chain_map[i]); 2044 bus_dmamap_destroy( 2045 sc->tx_bd_chain_tag, 2046 sc->tx_bd_chain_map[i]); 2047 } 2048 2049 } 2050 2051 /* Destroy the TX buffer descriptor tag. */ 2052 if (sc->tx_bd_chain_tag != NULL) 2053 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2054 2055 2056 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2057 for (i = 0; i < RX_PAGES; i++ ) { 2058 if (sc->rx_bd_chain[i] != NULL) 2059 bus_dmamem_free( 2060 sc->rx_bd_chain_tag, 2061 sc->rx_bd_chain[i], 2062 sc->rx_bd_chain_map[i]); 2063 2064 if (sc->rx_bd_chain_map[i] != NULL) { 2065 bus_dmamap_unload( 2066 sc->rx_bd_chain_tag, 2067 sc->rx_bd_chain_map[i]); 2068 bus_dmamap_destroy( 2069 sc->rx_bd_chain_tag, 2070 sc->rx_bd_chain_map[i]); 2071 } 2072 } 2073 2074 /* Destroy the RX buffer descriptor tag. */ 2075 if (sc->rx_bd_chain_tag != NULL) 2076 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2077 2078 2079 /* Unload and destroy the TX mbuf maps. */ 2080 for (i = 0; i < TOTAL_TX_BD; i++) { 2081 if (sc->tx_mbuf_map[i] != NULL) { 2082 bus_dmamap_unload(sc->tx_mbuf_tag, 2083 sc->tx_mbuf_map[i]); 2084 bus_dmamap_destroy(sc->tx_mbuf_tag, 2085 sc->tx_mbuf_map[i]); 2086 } 2087 } 2088 2089 /* Destroy the TX mbuf tag. */ 2090 if (sc->tx_mbuf_tag != NULL) 2091 bus_dma_tag_destroy(sc->tx_mbuf_tag); 2092 2093 2094 /* Unload and destroy the RX mbuf maps. */ 2095 for (i = 0; i < TOTAL_RX_BD; i++) { 2096 if (sc->rx_mbuf_map[i] != NULL) { 2097 bus_dmamap_unload(sc->rx_mbuf_tag, 2098 sc->rx_mbuf_map[i]); 2099 bus_dmamap_destroy(sc->rx_mbuf_tag, 2100 sc->rx_mbuf_map[i]); 2101 } 2102 } 2103 2104 /* Destroy the RX mbuf tag. */ 2105 if (sc->rx_mbuf_tag != NULL) 2106 bus_dma_tag_destroy(sc->rx_mbuf_tag); 2107 2108 2109 /* Destroy the parent tag */ 2110 if (sc->parent_tag != NULL) 2111 bus_dma_tag_destroy(sc->parent_tag); 2112 2113 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2114 2115 } 2116 2117 2118 /****************************************************************************/ 2119 /* Get DMA memory from the OS. */ 2120 /* */ 2121 /* Validates that the OS has provided DMA buffers in response to a */ 2122 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 2123 /* When the callback is used the OS will return 0 for the mapping function */ 2124 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 2125 /* failures back to the caller. */ 2126 /* */ 2127 /* Returns: */ 2128 /* Nothing. */ 2129 /****************************************************************************/ 2130 static void 2131 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2132 { 2133 bus_addr_t *busaddr = arg; 2134 2135 /* Simulate a mapping failure. */ 2136 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure), 2137 printf("bce: %s(%d): Simulating DMA mapping error.\n", 2138 __FILE__, __LINE__); 2139 error = ENOMEM); 2140 2141 /* Check for an error and signal the caller that an error occurred. */ 2142 if (error) { 2143 printf("bce %s(%d): DMA mapping error! error = %d, " 2144 "nseg = %d\n", __FILE__, __LINE__, error, nseg); 2145 *busaddr = 0; 2146 return; 2147 } 2148 2149 *busaddr = segs->ds_addr; 2150 return; 2151 } 2152 2153 2154 /****************************************************************************/ 2155 /* Allocate any DMA memory needed by the driver. */ 2156 /* */ 2157 /* Allocates DMA memory needed for the various global structures needed by */ 2158 /* hardware. */ 2159 /* */ 2160 /* Returns: */ 2161 /* 0 for success, positive value for failure. */ 2162 /****************************************************************************/ 2163 static int 2164 bce_dma_alloc(device_t dev) 2165 { 2166 struct bce_softc *sc; 2167 int i, error, rc = 0; 2168 bus_addr_t busaddr; 2169 2170 sc = device_get_softc(dev); 2171 2172 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2173 2174 /* 2175 * Allocate the parent bus DMA tag appropriate for PCI. 2176 */ 2177 if (bus_dma_tag_create(NULL, /* parent */ 2178 1, /* alignment */ 2179 BCE_DMA_BOUNDARY, /* boundary */ 2180 sc->max_bus_addr, /* lowaddr */ 2181 BUS_SPACE_MAXADDR, /* highaddr */ 2182 NULL, /* filterfunc */ 2183 NULL, /* filterarg */ 2184 MAXBSIZE, /* maxsize */ 2185 BUS_SPACE_UNRESTRICTED, /* nsegments */ 2186 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 2187 0, /* flags */ 2188 NULL, /* locfunc */ 2189 NULL, /* lockarg */ 2190 &sc->parent_tag)) { 2191 BCE_PRINTF(sc, "%s(%d): Could not allocate parent DMA tag!\n", 2192 __FILE__, __LINE__); 2193 rc = ENOMEM; 2194 goto bce_dma_alloc_exit; 2195 } 2196 2197 /* 2198 * Create a DMA tag for the status block, allocate and clear the 2199 * memory, map the memory into DMA space, and fetch the physical 2200 * address of the block. 2201 */ 2202 if (bus_dma_tag_create( 2203 sc->parent_tag, /* parent */ 2204 BCE_DMA_ALIGN, /* alignment */ 2205 BCE_DMA_BOUNDARY, /* boundary */ 2206 sc->max_bus_addr, /* lowaddr */ 2207 BUS_SPACE_MAXADDR, /* highaddr */ 2208 NULL, /* filterfunc */ 2209 NULL, /* filterarg */ 2210 BCE_STATUS_BLK_SZ, /* maxsize */ 2211 1, /* nsegments */ 2212 BCE_STATUS_BLK_SZ, /* maxsegsize */ 2213 0, /* flags */ 2214 NULL, /* lockfunc */ 2215 NULL, /* lockarg */ 2216 &sc->status_tag)) { 2217 BCE_PRINTF(sc, "%s(%d): Could not allocate status block DMA tag!\n", 2218 __FILE__, __LINE__); 2219 rc = ENOMEM; 2220 goto bce_dma_alloc_exit; 2221 } 2222 2223 if(bus_dmamem_alloc( 2224 sc->status_tag, /* dmat */ 2225 (void **)&sc->status_block, /* vaddr */ 2226 BUS_DMA_NOWAIT, /* flags */ 2227 &sc->status_map)) { 2228 BCE_PRINTF(sc, "%s(%d): Could not allocate status block DMA memory!\n", 2229 __FILE__, __LINE__); 2230 rc = ENOMEM; 2231 goto bce_dma_alloc_exit; 2232 } 2233 2234 bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 2235 2236 error = bus_dmamap_load( 2237 sc->status_tag, /* dmat */ 2238 sc->status_map, /* map */ 2239 sc->status_block, /* buf */ 2240 BCE_STATUS_BLK_SZ, /* buflen */ 2241 bce_dma_map_addr, /* callback */ 2242 &busaddr, /* callbackarg */ 2243 BUS_DMA_NOWAIT); /* flags */ 2244 2245 if (error) { 2246 BCE_PRINTF(sc, "%s(%d): Could not map status block DMA memory!\n", 2247 __FILE__, __LINE__); 2248 rc = ENOMEM; 2249 goto bce_dma_alloc_exit; 2250 } 2251 2252 sc->status_block_paddr = busaddr; 2253 /* DRC - Fix for 64 bit addresses. */ 2254 DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n", 2255 (u32) sc->status_block_paddr); 2256 2257 /* 2258 * Create a DMA tag for the statistics block, allocate and clear the 2259 * memory, map the memory into DMA space, and fetch the physical 2260 * address of the block. 2261 */ 2262 if (bus_dma_tag_create( 2263 sc->parent_tag, /* parent */ 2264 BCE_DMA_ALIGN, /* alignment */ 2265 BCE_DMA_BOUNDARY, /* boundary */ 2266 sc->max_bus_addr, /* lowaddr */ 2267 BUS_SPACE_MAXADDR, /* highaddr */ 2268 NULL, /* filterfunc */ 2269 NULL, /* filterarg */ 2270 BCE_STATS_BLK_SZ, /* maxsize */ 2271 1, /* nsegments */ 2272 BCE_STATS_BLK_SZ, /* maxsegsize */ 2273 0, /* flags */ 2274 NULL, /* lockfunc */ 2275 NULL, /* lockarg */ 2276 &sc->stats_tag)) { 2277 BCE_PRINTF(sc, "%s(%d): Could not allocate statistics block DMA tag!\n", 2278 __FILE__, __LINE__); 2279 rc = ENOMEM; 2280 goto bce_dma_alloc_exit; 2281 } 2282 2283 if (bus_dmamem_alloc( 2284 sc->stats_tag, /* dmat */ 2285 (void **)&sc->stats_block, /* vaddr */ 2286 BUS_DMA_NOWAIT, /* flags */ 2287 &sc->stats_map)) { 2288 BCE_PRINTF(sc, "%s(%d): Could not allocate statistics block DMA memory!\n", 2289 __FILE__, __LINE__); 2290 rc = ENOMEM; 2291 goto bce_dma_alloc_exit; 2292 } 2293 2294 bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 2295 2296 error = bus_dmamap_load( 2297 sc->stats_tag, /* dmat */ 2298 sc->stats_map, /* map */ 2299 sc->stats_block, /* buf */ 2300 BCE_STATS_BLK_SZ, /* buflen */ 2301 bce_dma_map_addr, /* callback */ 2302 &busaddr, /* callbackarg */ 2303 BUS_DMA_NOWAIT); /* flags */ 2304 2305 if(error) { 2306 BCE_PRINTF(sc, "%s(%d): Could not map statistics block DMA memory!\n", 2307 __FILE__, __LINE__); 2308 rc = ENOMEM; 2309 goto bce_dma_alloc_exit; 2310 } 2311 2312 sc->stats_block_paddr = busaddr; 2313 /* DRC - Fix for 64 bit address. */ 2314 DBPRINT(sc,BCE_INFO, "stats_block_paddr = 0x%08X\n", 2315 (u32) sc->stats_block_paddr); 2316 2317 /* 2318 * Create a DMA tag for the TX buffer descriptor chain, 2319 * allocate and clear the memory, and fetch the 2320 * physical address of the block. 2321 */ 2322 if(bus_dma_tag_create( 2323 sc->parent_tag, /* parent */ 2324 BCM_PAGE_SIZE, /* alignment */ 2325 BCE_DMA_BOUNDARY, /* boundary */ 2326 sc->max_bus_addr, /* lowaddr */ 2327 BUS_SPACE_MAXADDR, /* highaddr */ 2328 NULL, /* filterfunc */ 2329 NULL, /* filterarg */ 2330 BCE_TX_CHAIN_PAGE_SZ, /* maxsize */ 2331 1, /* nsegments */ 2332 BCE_TX_CHAIN_PAGE_SZ, /* maxsegsize */ 2333 0, /* flags */ 2334 NULL, /* lockfunc */ 2335 NULL, /* lockarg */ 2336 &sc->tx_bd_chain_tag)) { 2337 BCE_PRINTF(sc, "%s(%d): Could not allocate TX descriptor chain DMA tag!\n", 2338 __FILE__, __LINE__); 2339 rc = ENOMEM; 2340 goto bce_dma_alloc_exit; 2341 } 2342 2343 for (i = 0; i < TX_PAGES; i++) { 2344 2345 if(bus_dmamem_alloc( 2346 sc->tx_bd_chain_tag, /* tag */ 2347 (void **)&sc->tx_bd_chain[i], /* vaddr */ 2348 BUS_DMA_NOWAIT, /* flags */ 2349 &sc->tx_bd_chain_map[i])) { 2350 BCE_PRINTF(sc, "%s(%d): Could not allocate TX descriptor " 2351 "chain DMA memory!\n", __FILE__, __LINE__); 2352 rc = ENOMEM; 2353 goto bce_dma_alloc_exit; 2354 } 2355 2356 error = bus_dmamap_load( 2357 sc->tx_bd_chain_tag, /* dmat */ 2358 sc->tx_bd_chain_map[i], /* map */ 2359 sc->tx_bd_chain[i], /* buf */ 2360 BCE_TX_CHAIN_PAGE_SZ, /* buflen */ 2361 bce_dma_map_addr, /* callback */ 2362 &busaddr, /* callbackarg */ 2363 BUS_DMA_NOWAIT); /* flags */ 2364 2365 if (error) { 2366 BCE_PRINTF(sc, "%s(%d): Could not map TX descriptor chain DMA memory!\n", 2367 __FILE__, __LINE__); 2368 rc = ENOMEM; 2369 goto bce_dma_alloc_exit; 2370 } 2371 2372 sc->tx_bd_chain_paddr[i] = busaddr; 2373 /* DRC - Fix for 64 bit systems. */ 2374 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2375 i, (u32) sc->tx_bd_chain_paddr[i]); 2376 } 2377 2378 /* Create a DMA tag for TX mbufs. */ 2379 if (bus_dma_tag_create( 2380 sc->parent_tag, /* parent */ 2381 1, /* alignment */ 2382 BCE_DMA_BOUNDARY, /* boundary */ 2383 sc->max_bus_addr, /* lowaddr */ 2384 BUS_SPACE_MAXADDR, /* highaddr */ 2385 NULL, /* filterfunc */ 2386 NULL, /* filterarg */ 2387 MCLBYTES * BCE_MAX_SEGMENTS, /* maxsize */ 2388 BCE_MAX_SEGMENTS, /* nsegments */ 2389 MCLBYTES, /* maxsegsize */ 2390 0, /* flags */ 2391 NULL, /* lockfunc */ 2392 NULL, /* lockarg */ 2393 &sc->tx_mbuf_tag)) { 2394 BCE_PRINTF(sc, "%s(%d): Could not allocate TX mbuf DMA tag!\n", 2395 __FILE__, __LINE__); 2396 rc = ENOMEM; 2397 goto bce_dma_alloc_exit; 2398 } 2399 2400 /* Create DMA maps for the TX mbufs clusters. */ 2401 for (i = 0; i < TOTAL_TX_BD; i++) { 2402 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 2403 &sc->tx_mbuf_map[i])) { 2404 BCE_PRINTF(sc, "%s(%d): Unable to create TX mbuf DMA map!\n", 2405 __FILE__, __LINE__); 2406 rc = ENOMEM; 2407 goto bce_dma_alloc_exit; 2408 } 2409 } 2410 2411 /* 2412 * Create a DMA tag for the RX buffer descriptor chain, 2413 * allocate and clear the memory, and fetch the physical 2414 * address of the blocks. 2415 */ 2416 if (bus_dma_tag_create( 2417 sc->parent_tag, /* parent */ 2418 BCM_PAGE_SIZE, /* alignment */ 2419 BCE_DMA_BOUNDARY, /* boundary */ 2420 BUS_SPACE_MAXADDR, /* lowaddr */ 2421 sc->max_bus_addr, /* lowaddr */ 2422 NULL, /* filter */ 2423 NULL, /* filterarg */ 2424 BCE_RX_CHAIN_PAGE_SZ, /* maxsize */ 2425 1, /* nsegments */ 2426 BCE_RX_CHAIN_PAGE_SZ, /* maxsegsize */ 2427 0, /* flags */ 2428 NULL, /* lockfunc */ 2429 NULL, /* lockarg */ 2430 &sc->rx_bd_chain_tag)) { 2431 BCE_PRINTF(sc, "%s(%d): Could not allocate RX descriptor chain DMA tag!\n", 2432 __FILE__, __LINE__); 2433 rc = ENOMEM; 2434 goto bce_dma_alloc_exit; 2435 } 2436 2437 for (i = 0; i < RX_PAGES; i++) { 2438 2439 if (bus_dmamem_alloc( 2440 sc->rx_bd_chain_tag, /* tag */ 2441 (void **)&sc->rx_bd_chain[i], /* vaddr */ 2442 BUS_DMA_NOWAIT, /* flags */ 2443 &sc->rx_bd_chain_map[i])) { 2444 BCE_PRINTF(sc, "%s(%d): Could not allocate RX descriptor chain " 2445 "DMA memory!\n", __FILE__, __LINE__); 2446 rc = ENOMEM; 2447 goto bce_dma_alloc_exit; 2448 } 2449 2450 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 2451 2452 error = bus_dmamap_load( 2453 sc->rx_bd_chain_tag, /* dmat */ 2454 sc->rx_bd_chain_map[i], /* map */ 2455 sc->rx_bd_chain[i], /* buf */ 2456 BCE_RX_CHAIN_PAGE_SZ, /* buflen */ 2457 bce_dma_map_addr, /* callback */ 2458 &busaddr, /* callbackarg */ 2459 BUS_DMA_NOWAIT); /* flags */ 2460 2461 if (error) { 2462 BCE_PRINTF(sc, "%s(%d): Could not map RX descriptor chain DMA memory!\n", 2463 __FILE__, __LINE__); 2464 rc = ENOMEM; 2465 goto bce_dma_alloc_exit; 2466 } 2467 2468 sc->rx_bd_chain_paddr[i] = busaddr; 2469 /* DRC - Fix for 64 bit systems. */ 2470 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2471 i, (u32) sc->rx_bd_chain_paddr[i]); 2472 } 2473 2474 /* 2475 * Create a DMA tag for RX mbufs. 2476 */ 2477 if (bus_dma_tag_create( 2478 sc->parent_tag, /* parent */ 2479 1, /* alignment */ 2480 BCE_DMA_BOUNDARY, /* boundary */ 2481 sc->max_bus_addr, /* lowaddr */ 2482 BUS_SPACE_MAXADDR, /* highaddr */ 2483 NULL, /* filterfunc */ 2484 NULL, /* filterarg */ 2485 MJUM9BYTES, /* maxsize */ 2486 BCE_MAX_SEGMENTS, /* nsegments */ 2487 MJUM9BYTES, /* maxsegsize */ 2488 0, /* flags */ 2489 NULL, /* lockfunc */ 2490 NULL, /* lockarg */ 2491 &sc->rx_mbuf_tag)) { 2492 BCE_PRINTF(sc, "%s(%d): Could not allocate RX mbuf DMA tag!\n", 2493 __FILE__, __LINE__); 2494 rc = ENOMEM; 2495 goto bce_dma_alloc_exit; 2496 } 2497 2498 /* Create DMA maps for the RX mbuf clusters. */ 2499 for (i = 0; i < TOTAL_RX_BD; i++) { 2500 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 2501 &sc->rx_mbuf_map[i])) { 2502 BCE_PRINTF(sc, "%s(%d): Unable to create RX mbuf DMA map!\n", 2503 __FILE__, __LINE__); 2504 rc = ENOMEM; 2505 goto bce_dma_alloc_exit; 2506 } 2507 } 2508 2509 bce_dma_alloc_exit: 2510 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2511 2512 return(rc); 2513 } 2514 2515 2516 /****************************************************************************/ 2517 /* Release all resources used by the driver. */ 2518 /* */ 2519 /* Releases all resources acquired by the driver including interrupts, */ 2520 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2521 /* */ 2522 /* Returns: */ 2523 /* Nothing. */ 2524 /****************************************************************************/ 2525 static void 2526 bce_release_resources(struct bce_softc *sc) 2527 { 2528 device_t dev; 2529 2530 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2531 2532 dev = sc->bce_dev; 2533 2534 bce_dma_free(sc); 2535 2536 if (sc->bce_intrhand != NULL) 2537 bus_teardown_intr(dev, sc->bce_irq, sc->bce_intrhand); 2538 2539 if (sc->bce_irq != NULL) 2540 bus_release_resource(dev, 2541 SYS_RES_IRQ, 2542 0, 2543 sc->bce_irq); 2544 2545 if (sc->bce_res != NULL) 2546 bus_release_resource(dev, 2547 SYS_RES_MEMORY, 2548 PCIR_BAR(0), 2549 sc->bce_res); 2550 2551 if (sc->bce_ifp != NULL) 2552 if_free(sc->bce_ifp); 2553 2554 2555 if (mtx_initialized(&sc->bce_mtx)) 2556 BCE_LOCK_DESTROY(sc); 2557 2558 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2559 2560 } 2561 2562 2563 /****************************************************************************/ 2564 /* Firmware synchronization. */ 2565 /* */ 2566 /* Before performing certain events such as a chip reset, synchronize with */ 2567 /* the firmware first. */ 2568 /* */ 2569 /* Returns: */ 2570 /* 0 for success, positive value for failure. */ 2571 /****************************************************************************/ 2572 static int 2573 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 2574 { 2575 int i, rc = 0; 2576 u32 val; 2577 2578 /* Don't waste any time if we've timed out before. */ 2579 if (sc->bce_fw_timed_out) { 2580 rc = EBUSY; 2581 goto bce_fw_sync_exit; 2582 } 2583 2584 /* Increment the message sequence number. */ 2585 sc->bce_fw_wr_seq++; 2586 msg_data |= sc->bce_fw_wr_seq; 2587 2588 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data); 2589 2590 /* Send the message to the bootcode driver mailbox. */ 2591 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2592 2593 /* Wait for the bootcode to acknowledge the message. */ 2594 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2595 /* Check for a response in the bootcode firmware mailbox. */ 2596 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB); 2597 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 2598 break; 2599 DELAY(1000); 2600 } 2601 2602 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2603 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 2604 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 2605 2606 BCE_PRINTF(sc, "%s(%d): Firmware synchronization timeout! " 2607 "msg_data = 0x%08X\n", 2608 __FILE__, __LINE__, msg_data); 2609 2610 msg_data &= ~BCE_DRV_MSG_CODE; 2611 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 2612 2613 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2614 2615 sc->bce_fw_timed_out = 1; 2616 rc = EBUSY; 2617 } 2618 2619 bce_fw_sync_exit: 2620 return (rc); 2621 } 2622 2623 2624 /****************************************************************************/ 2625 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2626 /* */ 2627 /* Returns: */ 2628 /* Nothing. */ 2629 /****************************************************************************/ 2630 static void 2631 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 2632 u32 rv2p_code_len, u32 rv2p_proc) 2633 { 2634 int i; 2635 u32 val; 2636 2637 for (i = 0; i < rv2p_code_len; i += 8) { 2638 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 2639 rv2p_code++; 2640 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 2641 rv2p_code++; 2642 2643 if (rv2p_proc == RV2P_PROC1) { 2644 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 2645 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 2646 } 2647 else { 2648 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 2649 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 2650 } 2651 } 2652 2653 /* Reset the processor, un-stall is done later. */ 2654 if (rv2p_proc == RV2P_PROC1) { 2655 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 2656 } 2657 else { 2658 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 2659 } 2660 } 2661 2662 2663 /****************************************************************************/ 2664 /* Load RISC processor firmware. */ 2665 /* */ 2666 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 2667 /* associated with a particular processor. */ 2668 /* */ 2669 /* Returns: */ 2670 /* Nothing. */ 2671 /****************************************************************************/ 2672 static void 2673 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 2674 struct fw_info *fw) 2675 { 2676 u32 offset; 2677 u32 val; 2678 2679 /* Halt the CPU. */ 2680 val = REG_RD_IND(sc, cpu_reg->mode); 2681 val |= cpu_reg->mode_value_halt; 2682 REG_WR_IND(sc, cpu_reg->mode, val); 2683 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2684 2685 /* Load the Text area. */ 2686 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2687 if (fw->text) { 2688 int j; 2689 2690 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 2691 REG_WR_IND(sc, offset, fw->text[j]); 2692 } 2693 } 2694 2695 /* Load the Data area. */ 2696 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2697 if (fw->data) { 2698 int j; 2699 2700 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 2701 REG_WR_IND(sc, offset, fw->data[j]); 2702 } 2703 } 2704 2705 /* Load the SBSS area. */ 2706 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2707 if (fw->sbss) { 2708 int j; 2709 2710 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 2711 REG_WR_IND(sc, offset, fw->sbss[j]); 2712 } 2713 } 2714 2715 /* Load the BSS area. */ 2716 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2717 if (fw->bss) { 2718 int j; 2719 2720 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 2721 REG_WR_IND(sc, offset, fw->bss[j]); 2722 } 2723 } 2724 2725 /* Load the Read-Only area. */ 2726 offset = cpu_reg->spad_base + 2727 (fw->rodata_addr - cpu_reg->mips_view_base); 2728 if (fw->rodata) { 2729 int j; 2730 2731 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 2732 REG_WR_IND(sc, offset, fw->rodata[j]); 2733 } 2734 } 2735 2736 /* Clear the pre-fetch instruction. */ 2737 REG_WR_IND(sc, cpu_reg->inst, 0); 2738 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2739 2740 /* Start the CPU. */ 2741 val = REG_RD_IND(sc, cpu_reg->mode); 2742 val &= ~cpu_reg->mode_value_halt; 2743 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2744 REG_WR_IND(sc, cpu_reg->mode, val); 2745 } 2746 2747 2748 /****************************************************************************/ 2749 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2750 /* */ 2751 /* Loads the firmware for each CPU and starts the CPU. */ 2752 /* */ 2753 /* Returns: */ 2754 /* Nothing. */ 2755 /****************************************************************************/ 2756 static void 2757 bce_init_cpus(struct bce_softc *sc) 2758 { 2759 struct cpu_reg cpu_reg; 2760 struct fw_info fw; 2761 2762 /* Initialize the RV2P processor. */ 2763 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1); 2764 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2); 2765 2766 /* Initialize the RX Processor. */ 2767 cpu_reg.mode = BCE_RXP_CPU_MODE; 2768 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 2769 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 2770 cpu_reg.state = BCE_RXP_CPU_STATE; 2771 cpu_reg.state_value_clear = 0xffffff; 2772 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 2773 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 2774 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 2775 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 2776 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 2777 cpu_reg.spad_base = BCE_RXP_SCRATCH; 2778 cpu_reg.mips_view_base = 0x8000000; 2779 2780 fw.ver_major = bce_RXP_b06FwReleaseMajor; 2781 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 2782 fw.ver_fix = bce_RXP_b06FwReleaseFix; 2783 fw.start_addr = bce_RXP_b06FwStartAddr; 2784 2785 fw.text_addr = bce_RXP_b06FwTextAddr; 2786 fw.text_len = bce_RXP_b06FwTextLen; 2787 fw.text_index = 0; 2788 fw.text = bce_RXP_b06FwText; 2789 2790 fw.data_addr = bce_RXP_b06FwDataAddr; 2791 fw.data_len = bce_RXP_b06FwDataLen; 2792 fw.data_index = 0; 2793 fw.data = bce_RXP_b06FwData; 2794 2795 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 2796 fw.sbss_len = bce_RXP_b06FwSbssLen; 2797 fw.sbss_index = 0; 2798 fw.sbss = bce_RXP_b06FwSbss; 2799 2800 fw.bss_addr = bce_RXP_b06FwBssAddr; 2801 fw.bss_len = bce_RXP_b06FwBssLen; 2802 fw.bss_index = 0; 2803 fw.bss = bce_RXP_b06FwBss; 2804 2805 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 2806 fw.rodata_len = bce_RXP_b06FwRodataLen; 2807 fw.rodata_index = 0; 2808 fw.rodata = bce_RXP_b06FwRodata; 2809 2810 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 2811 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2812 2813 /* Initialize the TX Processor. */ 2814 cpu_reg.mode = BCE_TXP_CPU_MODE; 2815 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 2816 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 2817 cpu_reg.state = BCE_TXP_CPU_STATE; 2818 cpu_reg.state_value_clear = 0xffffff; 2819 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 2820 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 2821 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 2822 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 2823 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 2824 cpu_reg.spad_base = BCE_TXP_SCRATCH; 2825 cpu_reg.mips_view_base = 0x8000000; 2826 2827 fw.ver_major = bce_TXP_b06FwReleaseMajor; 2828 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 2829 fw.ver_fix = bce_TXP_b06FwReleaseFix; 2830 fw.start_addr = bce_TXP_b06FwStartAddr; 2831 2832 fw.text_addr = bce_TXP_b06FwTextAddr; 2833 fw.text_len = bce_TXP_b06FwTextLen; 2834 fw.text_index = 0; 2835 fw.text = bce_TXP_b06FwText; 2836 2837 fw.data_addr = bce_TXP_b06FwDataAddr; 2838 fw.data_len = bce_TXP_b06FwDataLen; 2839 fw.data_index = 0; 2840 fw.data = bce_TXP_b06FwData; 2841 2842 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 2843 fw.sbss_len = bce_TXP_b06FwSbssLen; 2844 fw.sbss_index = 0; 2845 fw.sbss = bce_TXP_b06FwSbss; 2846 2847 fw.bss_addr = bce_TXP_b06FwBssAddr; 2848 fw.bss_len = bce_TXP_b06FwBssLen; 2849 fw.bss_index = 0; 2850 fw.bss = bce_TXP_b06FwBss; 2851 2852 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 2853 fw.rodata_len = bce_TXP_b06FwRodataLen; 2854 fw.rodata_index = 0; 2855 fw.rodata = bce_TXP_b06FwRodata; 2856 2857 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 2858 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2859 2860 /* Initialize the TX Patch-up Processor. */ 2861 cpu_reg.mode = BCE_TPAT_CPU_MODE; 2862 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 2863 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 2864 cpu_reg.state = BCE_TPAT_CPU_STATE; 2865 cpu_reg.state_value_clear = 0xffffff; 2866 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 2867 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 2868 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 2869 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 2870 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 2871 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 2872 cpu_reg.mips_view_base = 0x8000000; 2873 2874 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 2875 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 2876 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 2877 fw.start_addr = bce_TPAT_b06FwStartAddr; 2878 2879 fw.text_addr = bce_TPAT_b06FwTextAddr; 2880 fw.text_len = bce_TPAT_b06FwTextLen; 2881 fw.text_index = 0; 2882 fw.text = bce_TPAT_b06FwText; 2883 2884 fw.data_addr = bce_TPAT_b06FwDataAddr; 2885 fw.data_len = bce_TPAT_b06FwDataLen; 2886 fw.data_index = 0; 2887 fw.data = bce_TPAT_b06FwData; 2888 2889 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 2890 fw.sbss_len = bce_TPAT_b06FwSbssLen; 2891 fw.sbss_index = 0; 2892 fw.sbss = bce_TPAT_b06FwSbss; 2893 2894 fw.bss_addr = bce_TPAT_b06FwBssAddr; 2895 fw.bss_len = bce_TPAT_b06FwBssLen; 2896 fw.bss_index = 0; 2897 fw.bss = bce_TPAT_b06FwBss; 2898 2899 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 2900 fw.rodata_len = bce_TPAT_b06FwRodataLen; 2901 fw.rodata_index = 0; 2902 fw.rodata = bce_TPAT_b06FwRodata; 2903 2904 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 2905 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2906 2907 /* Initialize the Completion Processor. */ 2908 cpu_reg.mode = BCE_COM_CPU_MODE; 2909 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 2910 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 2911 cpu_reg.state = BCE_COM_CPU_STATE; 2912 cpu_reg.state_value_clear = 0xffffff; 2913 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 2914 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 2915 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 2916 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 2917 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 2918 cpu_reg.spad_base = BCE_COM_SCRATCH; 2919 cpu_reg.mips_view_base = 0x8000000; 2920 2921 fw.ver_major = bce_COM_b06FwReleaseMajor; 2922 fw.ver_minor = bce_COM_b06FwReleaseMinor; 2923 fw.ver_fix = bce_COM_b06FwReleaseFix; 2924 fw.start_addr = bce_COM_b06FwStartAddr; 2925 2926 fw.text_addr = bce_COM_b06FwTextAddr; 2927 fw.text_len = bce_COM_b06FwTextLen; 2928 fw.text_index = 0; 2929 fw.text = bce_COM_b06FwText; 2930 2931 fw.data_addr = bce_COM_b06FwDataAddr; 2932 fw.data_len = bce_COM_b06FwDataLen; 2933 fw.data_index = 0; 2934 fw.data = bce_COM_b06FwData; 2935 2936 fw.sbss_addr = bce_COM_b06FwSbssAddr; 2937 fw.sbss_len = bce_COM_b06FwSbssLen; 2938 fw.sbss_index = 0; 2939 fw.sbss = bce_COM_b06FwSbss; 2940 2941 fw.bss_addr = bce_COM_b06FwBssAddr; 2942 fw.bss_len = bce_COM_b06FwBssLen; 2943 fw.bss_index = 0; 2944 fw.bss = bce_COM_b06FwBss; 2945 2946 fw.rodata_addr = bce_COM_b06FwRodataAddr; 2947 fw.rodata_len = bce_COM_b06FwRodataLen; 2948 fw.rodata_index = 0; 2949 fw.rodata = bce_COM_b06FwRodata; 2950 2951 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 2952 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2953 } 2954 2955 2956 /****************************************************************************/ 2957 /* Initialize context memory. */ 2958 /* */ 2959 /* Clears the memory associated with each Context ID (CID). */ 2960 /* */ 2961 /* Returns: */ 2962 /* Nothing. */ 2963 /****************************************************************************/ 2964 static void 2965 bce_init_context(struct bce_softc *sc) 2966 { 2967 u32 vcid; 2968 2969 vcid = 96; 2970 while (vcid) { 2971 u32 vcid_addr, pcid_addr, offset; 2972 2973 vcid--; 2974 2975 vcid_addr = GET_CID_ADDR(vcid); 2976 pcid_addr = vcid_addr; 2977 2978 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0x00); 2979 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 2980 2981 /* Zero out the context. */ 2982 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 2983 CTX_WR(sc, 0x00, offset, 0); 2984 } 2985 2986 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 2987 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 2988 } 2989 } 2990 2991 2992 /****************************************************************************/ 2993 /* Fetch the permanent MAC address of the controller. */ 2994 /* */ 2995 /* Returns: */ 2996 /* Nothing. */ 2997 /****************************************************************************/ 2998 static void 2999 bce_get_mac_addr(struct bce_softc *sc) 3000 { 3001 u32 mac_lo = 0, mac_hi = 0; 3002 3003 /* 3004 * The NetXtreme II bootcode populates various NIC 3005 * power-on and runtime configuration items in a 3006 * shared memory area. The factory configured MAC 3007 * address is available from both NVRAM and the 3008 * shared memory area so we'll read the value from 3009 * shared memory for speed. 3010 */ 3011 3012 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + 3013 BCE_PORT_HW_CFG_MAC_UPPER); 3014 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + 3015 BCE_PORT_HW_CFG_MAC_LOWER); 3016 3017 if ((mac_lo == 0) && (mac_hi == 0)) { 3018 BCE_PRINTF(sc, "%s(%d): Invalid Ethernet address!\n", 3019 __FILE__, __LINE__); 3020 } else { 3021 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3022 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3023 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3024 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3025 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3026 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3027 } 3028 3029 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":"); 3030 } 3031 3032 3033 /****************************************************************************/ 3034 /* Program the MAC address. */ 3035 /* */ 3036 /* Returns: */ 3037 /* Nothing. */ 3038 /****************************************************************************/ 3039 static void 3040 bce_set_mac_addr(struct bce_softc *sc) 3041 { 3042 u32 val; 3043 u8 *mac_addr = sc->eaddr; 3044 3045 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n", sc->eaddr, ":"); 3046 3047 val = (mac_addr[0] << 8) | mac_addr[1]; 3048 3049 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 3050 3051 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3052 (mac_addr[4] << 8) | mac_addr[5]; 3053 3054 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 3055 } 3056 3057 3058 /****************************************************************************/ 3059 /* Stop the controller. */ 3060 /* */ 3061 /* Returns: */ 3062 /* Nothing. */ 3063 /****************************************************************************/ 3064 static void 3065 bce_stop(struct bce_softc *sc) 3066 { 3067 struct ifnet *ifp; 3068 struct ifmedia_entry *ifm; 3069 struct mii_data *mii = NULL; 3070 int mtmp, itmp; 3071 3072 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3073 3074 BCE_LOCK_ASSERT(sc); 3075 3076 ifp = sc->bce_ifp; 3077 3078 mii = device_get_softc(sc->bce_miibus); 3079 3080 callout_stop(&sc->bce_stat_ch); 3081 3082 /* Disable the transmit/receive blocks. */ 3083 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3084 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3085 DELAY(20); 3086 3087 bce_disable_intr(sc); 3088 3089 /* Tell firmware that the driver is going away. */ 3090 bce_reset(sc, BCE_DRV_MSG_CODE_SUSPEND_NO_WOL); 3091 3092 /* Free the RX lists. */ 3093 bce_free_rx_chain(sc); 3094 3095 /* Free TX buffers. */ 3096 bce_free_tx_chain(sc); 3097 3098 /* 3099 * Isolate/power down the PHY, but leave the media selection 3100 * unchanged so that things will be put back to normal when 3101 * we bring the interface back up. 3102 */ 3103 3104 itmp = ifp->if_flags; 3105 ifp->if_flags |= IFF_UP; 3106 /* 3107 * If we are called from bce_detach(), mii is already NULL. 3108 */ 3109 if (mii != NULL) { 3110 ifm = mii->mii_media.ifm_cur; 3111 mtmp = ifm->ifm_media; 3112 ifm->ifm_media = IFM_ETHER | IFM_NONE; 3113 mii_mediachg(mii); 3114 ifm->ifm_media = mtmp; 3115 } 3116 3117 ifp->if_flags = itmp; 3118 ifp->if_timer = 0; 3119 3120 sc->bce_link = 0; 3121 3122 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3123 3124 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3125 3126 bce_mgmt_init_locked(sc); 3127 } 3128 3129 3130 static int 3131 bce_reset(struct bce_softc *sc, u32 reset_code) 3132 { 3133 u32 val; 3134 int i, rc = 0; 3135 3136 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3137 3138 /* Wait for pending PCI transactions to complete. */ 3139 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 3140 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3141 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3142 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3143 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3144 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3145 DELAY(5); 3146 3147 /* Assume bootcode is running. */ 3148 sc->bce_fw_timed_out = 0; 3149 3150 /* Give the firmware a chance to prepare for the reset. */ 3151 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 3152 if (rc) 3153 goto bce_reset_exit; 3154 3155 /* Set a firmware reminder that this is a soft reset. */ 3156 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE, 3157 BCE_DRV_RESET_SIGNATURE_MAGIC); 3158 3159 /* Dummy read to force the chip to complete all current transactions. */ 3160 val = REG_RD(sc, BCE_MISC_ID); 3161 3162 /* Chip reset. */ 3163 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3164 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3165 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3166 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 3167 3168 /* Allow up to 30us for reset to complete. */ 3169 for (i = 0; i < 10; i++) { 3170 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 3171 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3172 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3173 break; 3174 } 3175 DELAY(10); 3176 } 3177 3178 /* Check that reset completed successfully. */ 3179 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3180 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3181 BCE_PRINTF(sc, "%s(%d): Reset failed!\n", 3182 __FILE__, __LINE__); 3183 rc = EBUSY; 3184 goto bce_reset_exit; 3185 } 3186 3187 /* Make sure byte swapping is properly configured. */ 3188 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 3189 if (val != 0x01020304) { 3190 BCE_PRINTF(sc, "%s(%d): Byte swap is incorrect!\n", 3191 __FILE__, __LINE__); 3192 rc = ENODEV; 3193 goto bce_reset_exit; 3194 } 3195 3196 /* Just completed a reset, assume that firmware is running again. */ 3197 sc->bce_fw_timed_out = 0; 3198 3199 /* Wait for the firmware to finish its initialization. */ 3200 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 3201 if (rc) 3202 BCE_PRINTF(sc, "%s(%d): Firmware did not complete initialization!\n", 3203 __FILE__, __LINE__); 3204 3205 bce_reset_exit: 3206 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3207 3208 return (rc); 3209 } 3210 3211 3212 static int 3213 bce_chipinit(struct bce_softc *sc) 3214 { 3215 u32 val; 3216 int rc = 0; 3217 3218 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3219 3220 /* Make sure the interrupt is not active. */ 3221 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 3222 3223 /* Initialize DMA byte/word swapping, configure the number of DMA */ 3224 /* channels and PCI clock compensation delay. */ 3225 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 3226 BCE_DMA_CONFIG_DATA_WORD_SWAP | 3227 #if BYTE_ORDER == BIG_ENDIAN 3228 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 3229 #endif 3230 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 3231 DMA_READ_CHANS << 12 | 3232 DMA_WRITE_CHANS << 16; 3233 3234 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3235 3236 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3237 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 3238 3239 /* 3240 * This setting resolves a problem observed on certain Intel PCI 3241 * chipsets that cannot handle multiple outstanding DMA operations. 3242 * See errata E9_5706A1_65. 3243 */ 3244 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 3245 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 3246 !(sc->bce_flags & BCE_PCIX_FLAG)) 3247 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 3248 3249 REG_WR(sc, BCE_DMA_CONFIG, val); 3250 3251 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3252 if (sc->bce_flags & BCE_PCIX_FLAG) { 3253 u16 val; 3254 3255 val = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2); 3256 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, val & ~0x2, 2); 3257 } 3258 3259 /* Enable the RX_V2P and Context state machines before access. */ 3260 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 3261 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3262 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3263 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3264 3265 /* Initialize context mapping and zero out the quick contexts. */ 3266 bce_init_context(sc); 3267 3268 /* Initialize the on-boards CPUs */ 3269 bce_init_cpus(sc); 3270 3271 /* Prepare NVRAM for access. */ 3272 if (bce_init_nvram(sc)) { 3273 rc = ENODEV; 3274 goto bce_chipinit_exit; 3275 } 3276 3277 /* Set the kernel bypass block size */ 3278 val = REG_RD(sc, BCE_MQ_CONFIG); 3279 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3280 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3281 REG_WR(sc, BCE_MQ_CONFIG, val); 3282 3283 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 3284 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 3285 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 3286 3287 val = (BCM_PAGE_BITS - 8) << 24; 3288 REG_WR(sc, BCE_RV2P_CONFIG, val); 3289 3290 /* Configure page size. */ 3291 val = REG_RD(sc, BCE_TBDR_CONFIG); 3292 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 3293 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3294 REG_WR(sc, BCE_TBDR_CONFIG, val); 3295 3296 bce_chipinit_exit: 3297 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3298 3299 return(rc); 3300 } 3301 3302 3303 /****************************************************************************/ 3304 /* Initialize the controller in preparation to send/receive traffic. */ 3305 /* */ 3306 /* Returns: */ 3307 /* 0 for success, positive value for failure. */ 3308 /****************************************************************************/ 3309 static int 3310 bce_blockinit(struct bce_softc *sc) 3311 { 3312 u32 reg, val; 3313 int rc = 0; 3314 3315 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3316 3317 /* Load the hardware default MAC address. */ 3318 bce_set_mac_addr(sc); 3319 3320 /* Set the Ethernet backoff seed value */ 3321 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 3322 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 3323 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3324 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 3325 3326 sc->last_status_idx = 0; 3327 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 3328 3329 /* Set up link change interrupt generation. */ 3330 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 3331 3332 /* Program the physical address of the status block. */ 3333 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 3334 BCE_ADDR_LO(sc->status_block_paddr)); 3335 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 3336 BCE_ADDR_HI(sc->status_block_paddr)); 3337 3338 /* Program the physical address of the statistics block. */ 3339 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 3340 BCE_ADDR_LO(sc->stats_block_paddr)); 3341 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 3342 BCE_ADDR_HI(sc->stats_block_paddr)); 3343 3344 /* Program various host coalescing parameters. */ 3345 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 3346 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 3347 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 3348 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 3349 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 3350 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 3351 REG_WR(sc, BCE_HC_TX_TICKS, 3352 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 3353 REG_WR(sc, BCE_HC_RX_TICKS, 3354 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 3355 REG_WR(sc, BCE_HC_COM_TICKS, 3356 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 3357 REG_WR(sc, BCE_HC_CMD_TICKS, 3358 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 3359 REG_WR(sc, BCE_HC_STATS_TICKS, 3360 (sc->bce_stats_ticks & 0xffff00)); 3361 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 3362 0xbb8); /* 3ms */ 3363 REG_WR(sc, BCE_HC_CONFIG, 3364 (BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 3365 BCE_HC_CONFIG_COLLECT_STATS)); 3366 3367 /* Clear the internal statistics counters. */ 3368 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 3369 3370 /* Verify that bootcode is running. */ 3371 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE); 3372 3373 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure), 3374 BCE_PRINTF(sc, "%s(%d): Simulating bootcode failure.\n", 3375 __FILE__, __LINE__); 3376 reg = 0); 3377 3378 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3379 BCE_DEV_INFO_SIGNATURE_MAGIC) { 3380 BCE_PRINTF(sc, "%s(%d): Bootcode not running! Found: 0x%08X, " 3381 "Expected: 08%08X\n", __FILE__, __LINE__, 3382 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 3383 BCE_DEV_INFO_SIGNATURE_MAGIC); 3384 rc = ENODEV; 3385 goto bce_blockinit_exit; 3386 } 3387 3388 /* Check if any management firmware is running. */ 3389 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE); 3390 if (reg & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED)) { 3391 DBPRINT(sc, BCE_INFO, "Management F/W Enabled.\n"); 3392 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 3393 } 3394 3395 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_BC_REV); 3396 DBPRINT(sc, BCE_INFO, "bootcode rev = 0x%08X\n", sc->bce_fw_ver); 3397 3398 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3399 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET); 3400 3401 /* Enable link state change interrupt generation. */ 3402 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3403 3404 /* Enable all remaining blocks in the MAC. */ 3405 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff); 3406 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 3407 DELAY(20); 3408 3409 bce_blockinit_exit: 3410 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3411 3412 return (rc); 3413 } 3414 3415 3416 /****************************************************************************/ 3417 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3418 /* */ 3419 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3420 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3421 /* necessary. */ 3422 /* */ 3423 /* Returns: */ 3424 /* 0 for success, positive value for failure. */ 3425 /****************************************************************************/ 3426 static int 3427 bce_get_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, u16 *chain_prod, 3428 u32 *prod_bseq) 3429 { 3430 bus_dmamap_t map; 3431 bus_dma_segment_t segs[4]; 3432 struct mbuf *m_new = NULL; 3433 struct rx_bd *rxbd; 3434 int i, nsegs, error, rc = 0; 3435 #ifdef BCE_DEBUG 3436 u16 debug_chain_prod = *chain_prod; 3437 #endif 3438 3439 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Entering %s()\n", 3440 __FUNCTION__); 3441 3442 /* Make sure the inputs are valid. */ 3443 DBRUNIF((*chain_prod > MAX_RX_BD), 3444 BCE_PRINTF(sc, "%s(%d): RX producer out of range: 0x%04X > 0x%04X\n", 3445 __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD)); 3446 3447 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, " 3448 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3449 3450 if (m == NULL) { 3451 3452 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure), 3453 BCE_PRINTF(sc, "%s(%d): Simulating mbuf allocation failure.\n", 3454 __FILE__, __LINE__); 3455 sc->mbuf_alloc_failed++; 3456 rc = ENOBUFS; 3457 goto bce_get_buf_exit); 3458 3459 /* This is a new mbuf allocation. */ 3460 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3461 if (m_new == NULL) { 3462 3463 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf header allocation failed!\n", 3464 __FILE__, __LINE__); 3465 3466 DBRUNIF(1, sc->mbuf_alloc_failed++); 3467 3468 rc = ENOBUFS; 3469 goto bce_get_buf_exit; 3470 } 3471 3472 DBRUNIF(1, sc->rx_mbuf_alloc++); 3473 m_cljget(m_new, M_DONTWAIT, sc->mbuf_alloc_size); 3474 if (!(m_new->m_flags & M_EXT)) { 3475 3476 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf chain allocation failed!\n", 3477 __FILE__, __LINE__); 3478 3479 m_freem(m_new); 3480 3481 DBRUNIF(1, sc->rx_mbuf_alloc--); 3482 DBRUNIF(1, sc->mbuf_alloc_failed++); 3483 3484 rc = ENOBUFS; 3485 goto bce_get_buf_exit; 3486 } 3487 3488 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3489 } else { 3490 m_new = m; 3491 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3492 m_new->m_data = m_new->m_ext.ext_buf; 3493 } 3494 3495 /* Map the mbuf cluster into device memory. */ 3496 map = sc->rx_mbuf_map[*chain_prod]; 3497 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 3498 segs, &nsegs, BUS_DMA_NOWAIT); 3499 3500 if (error) { 3501 BCE_PRINTF(sc, "%s(%d): Error mapping mbuf into RX chain!\n", 3502 __FILE__, __LINE__); 3503 3504 m_freem(m_new); 3505 3506 DBRUNIF(1, sc->rx_mbuf_alloc--); 3507 3508 rc = ENOBUFS; 3509 goto bce_get_buf_exit; 3510 } 3511 3512 /* Watch for overflow. */ 3513 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3514 BCE_PRINTF(sc, "%s(%d): Too many free rx_bd (0x%04X > 0x%04X)!\n", 3515 __FILE__, __LINE__, sc->free_rx_bd, (u16) USABLE_RX_BD)); 3516 3517 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3518 sc->rx_low_watermark = sc->free_rx_bd); 3519 3520 /* Setup the rx_bd for the first segment. */ 3521 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3522 3523 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 3524 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 3525 rxbd->rx_bd_len = htole32(segs[0].ds_len); 3526 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3527 *prod_bseq += segs[0].ds_len; 3528 3529 for (i = 1; i < nsegs; i++) { 3530 3531 *prod = NEXT_RX_BD(*prod); 3532 *chain_prod = RX_CHAIN_IDX(*prod); 3533 3534 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3535 3536 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 3537 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 3538 rxbd->rx_bd_len = htole32(segs[i].ds_len); 3539 rxbd->rx_bd_flags = 0; 3540 *prod_bseq += segs[i].ds_len; 3541 } 3542 3543 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3544 3545 /* Save the mbuf and update our counter. */ 3546 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3547 sc->free_rx_bd -= nsegs; 3548 3549 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 3550 nsegs)); 3551 3552 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, " 3553 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3554 3555 bce_get_buf_exit: 3556 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Exiting %s()\n", 3557 __FUNCTION__); 3558 3559 return(rc); 3560 } 3561 3562 3563 /****************************************************************************/ 3564 /* Allocate memory and initialize the TX data structures. */ 3565 /* */ 3566 /* Returns: */ 3567 /* 0 for success, positive value for failure. */ 3568 /****************************************************************************/ 3569 static int 3570 bce_init_tx_chain(struct bce_softc *sc) 3571 { 3572 struct tx_bd *txbd; 3573 u32 val; 3574 int i, rc = 0; 3575 3576 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3577 3578 /* Set the initial TX producer/consumer indices. */ 3579 sc->tx_prod = 0; 3580 sc->tx_cons = 0; 3581 sc->tx_prod_bseq = 0; 3582 sc->used_tx_bd = 0; 3583 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3584 3585 /* 3586 * The NetXtreme II supports a linked-list structre called 3587 * a Buffer Descriptor Chain (or BD chain). A BD chain 3588 * consists of a series of 1 or more chain pages, each of which 3589 * consists of a fixed number of BD entries. 3590 * The last BD entry on each page is a pointer to the next page 3591 * in the chain, and the last pointer in the BD chain 3592 * points back to the beginning of the chain. 3593 */ 3594 3595 /* Set the TX next pointer chain entries. */ 3596 for (i = 0; i < TX_PAGES; i++) { 3597 int j; 3598 3599 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3600 3601 /* Check if we've reached the last page. */ 3602 if (i == (TX_PAGES - 1)) 3603 j = 0; 3604 else 3605 j = i + 1; 3606 3607 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 3608 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 3609 } 3610 3611 /* 3612 * Initialize the context ID for an L2 TX chain. 3613 */ 3614 val = BCE_L2CTX_TYPE_TYPE_L2; 3615 val |= BCE_L2CTX_TYPE_SIZE_L2; 3616 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val); 3617 3618 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3619 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val); 3620 3621 /* Point the hardware to the first page in the chain. */ 3622 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 3623 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val); 3624 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 3625 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val); 3626 3627 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3628 3629 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3630 3631 return(rc); 3632 } 3633 3634 3635 /****************************************************************************/ 3636 /* Free memory and clear the TX data structures. */ 3637 /* */ 3638 /* Returns: */ 3639 /* Nothing. */ 3640 /****************************************************************************/ 3641 static void 3642 bce_free_tx_chain(struct bce_softc *sc) 3643 { 3644 int i; 3645 3646 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3647 3648 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3649 for (i = 0; i < TOTAL_TX_BD; i++) { 3650 if (sc->tx_mbuf_ptr[i] != NULL) { 3651 if (sc->tx_mbuf_map != NULL) 3652 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i], 3653 BUS_DMASYNC_POSTWRITE); 3654 m_freem(sc->tx_mbuf_ptr[i]); 3655 sc->tx_mbuf_ptr[i] = NULL; 3656 DBRUNIF(1, sc->tx_mbuf_alloc--); 3657 } 3658 } 3659 3660 /* Clear each TX chain page. */ 3661 for (i = 0; i < TX_PAGES; i++) 3662 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 3663 3664 /* Check if we lost any mbufs in the process. */ 3665 DBRUNIF((sc->tx_mbuf_alloc), 3666 BCE_PRINTF(sc, "%s(%d): Memory leak! Lost %d mbufs " 3667 "from tx chain!\n", 3668 __FILE__, __LINE__, sc->tx_mbuf_alloc)); 3669 3670 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3671 } 3672 3673 3674 /****************************************************************************/ 3675 /* Allocate memory and initialize the RX data structures. */ 3676 /* */ 3677 /* Returns: */ 3678 /* 0 for success, positive value for failure. */ 3679 /****************************************************************************/ 3680 static int 3681 bce_init_rx_chain(struct bce_softc *sc) 3682 { 3683 struct rx_bd *rxbd; 3684 int i, rc = 0; 3685 u16 prod, chain_prod; 3686 u32 prod_bseq, val; 3687 3688 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3689 3690 /* Initialize the RX producer and consumer indices. */ 3691 sc->rx_prod = 0; 3692 sc->rx_cons = 0; 3693 sc->rx_prod_bseq = 0; 3694 sc->free_rx_bd = BCE_RX_SLACK_SPACE; 3695 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3696 3697 /* Initialize the RX next pointer chain entries. */ 3698 for (i = 0; i < RX_PAGES; i++) { 3699 int j; 3700 3701 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3702 3703 /* Check if we've reached the last page. */ 3704 if (i == (RX_PAGES - 1)) 3705 j = 0; 3706 else 3707 j = i + 1; 3708 3709 /* Setup the chain page pointers. */ 3710 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 3711 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 3712 } 3713 3714 /* Initialize the context ID for an L2 RX chain. */ 3715 val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3716 val |= BCE_L2CTX_CTX_TYPE_SIZE_L2; 3717 val |= 0x02 << 8; 3718 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val); 3719 3720 /* Point the hardware to the first page in the chain. */ 3721 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 3722 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val); 3723 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 3724 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val); 3725 3726 /* Allocate mbuf clusters for the rx_bd chain. */ 3727 prod = prod_bseq = 0; 3728 while (prod < BCE_RX_SLACK_SPACE) { 3729 chain_prod = RX_CHAIN_IDX(prod); 3730 if (bce_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3731 BCE_PRINTF(sc, "%s(%d): Error filling RX chain: rx_bd[0x%04X]!\n", 3732 __FILE__, __LINE__, chain_prod); 3733 rc = ENOBUFS; 3734 break; 3735 } 3736 prod = NEXT_RX_BD(prod); 3737 } 3738 3739 /* Save the RX chain producer index. */ 3740 sc->rx_prod = prod; 3741 sc->rx_prod_bseq = prod_bseq; 3742 3743 for (i = 0; i < RX_PAGES; i++) { 3744 bus_dmamap_sync( 3745 sc->rx_bd_chain_tag, 3746 sc->rx_bd_chain_map[i], 3747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3748 } 3749 3750 /* Tell the chip about the waiting rx_bd's. */ 3751 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); 3752 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3753 3754 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3755 3756 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3757 3758 return(rc); 3759 } 3760 3761 3762 /****************************************************************************/ 3763 /* Free memory and clear the RX data structures. */ 3764 /* */ 3765 /* Returns: */ 3766 /* Nothing. */ 3767 /****************************************************************************/ 3768 static void 3769 bce_free_rx_chain(struct bce_softc *sc) 3770 { 3771 int i; 3772 3773 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3774 3775 /* Free any mbufs still in the RX mbuf chain. */ 3776 for (i = 0; i < TOTAL_RX_BD; i++) { 3777 if (sc->rx_mbuf_ptr[i] != NULL) { 3778 if (sc->rx_mbuf_map[i] != NULL) 3779 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i], 3780 BUS_DMASYNC_POSTREAD); 3781 m_freem(sc->rx_mbuf_ptr[i]); 3782 sc->rx_mbuf_ptr[i] = NULL; 3783 DBRUNIF(1, sc->rx_mbuf_alloc--); 3784 } 3785 } 3786 3787 /* Clear each RX chain page. */ 3788 for (i = 0; i < RX_PAGES; i++) 3789 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3790 3791 /* Check if we lost any mbufs in the process. */ 3792 DBRUNIF((sc->rx_mbuf_alloc), 3793 BCE_PRINTF(sc, "%s(%d): Memory leak! Lost %d mbufs from rx chain!\n", 3794 __FILE__, __LINE__, sc->rx_mbuf_alloc)); 3795 3796 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3797 } 3798 3799 3800 /****************************************************************************/ 3801 /* Set media options. */ 3802 /* */ 3803 /* Returns: */ 3804 /* 0 for success, positive value for failure. */ 3805 /****************************************************************************/ 3806 static int 3807 bce_ifmedia_upd(struct ifnet *ifp) 3808 { 3809 struct bce_softc *sc; 3810 struct mii_data *mii; 3811 struct ifmedia *ifm; 3812 int rc = 0; 3813 3814 sc = ifp->if_softc; 3815 ifm = &sc->bce_ifmedia; 3816 3817 /* DRC - ToDo: Add SerDes support. */ 3818 3819 mii = device_get_softc(sc->bce_miibus); 3820 sc->bce_link = 0; 3821 if (mii->mii_instance) { 3822 struct mii_softc *miisc; 3823 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3824 miisc = LIST_NEXT(miisc, mii_list)) 3825 mii_phy_reset(miisc); 3826 } 3827 mii_mediachg(mii); 3828 3829 return(rc); 3830 } 3831 3832 3833 /****************************************************************************/ 3834 /* Reports current media status. */ 3835 /* */ 3836 /* Returns: */ 3837 /* Nothing. */ 3838 /****************************************************************************/ 3839 static void 3840 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3841 { 3842 struct bce_softc *sc; 3843 struct mii_data *mii; 3844 3845 sc = ifp->if_softc; 3846 3847 BCE_LOCK(sc); 3848 3849 mii = device_get_softc(sc->bce_miibus); 3850 3851 /* DRC - ToDo: Add SerDes support. */ 3852 3853 mii_pollstat(mii); 3854 ifmr->ifm_active = mii->mii_media_active; 3855 ifmr->ifm_status = mii->mii_media_status; 3856 3857 BCE_UNLOCK(sc); 3858 } 3859 3860 3861 /****************************************************************************/ 3862 /* Handles PHY generated interrupt events. */ 3863 /* */ 3864 /* Returns: */ 3865 /* Nothing. */ 3866 /****************************************************************************/ 3867 static void 3868 bce_phy_intr(struct bce_softc *sc) 3869 { 3870 u32 new_link_state, old_link_state; 3871 3872 new_link_state = sc->status_block->status_attn_bits & 3873 STATUS_ATTN_BITS_LINK_STATE; 3874 old_link_state = sc->status_block->status_attn_bits_ack & 3875 STATUS_ATTN_BITS_LINK_STATE; 3876 3877 /* Handle any changes if the link state has changed. */ 3878 if (new_link_state != old_link_state) { 3879 3880 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 3881 3882 sc->bce_link = 0; 3883 callout_stop(&sc->bce_stat_ch); 3884 bce_tick_locked(sc); 3885 3886 /* Update the status_attn_bits_ack field in the status block. */ 3887 if (new_link_state) { 3888 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 3889 STATUS_ATTN_BITS_LINK_STATE); 3890 DBPRINT(sc, BCE_INFO, "Link is now UP.\n"); 3891 } 3892 else { 3893 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 3894 STATUS_ATTN_BITS_LINK_STATE); 3895 DBPRINT(sc, BCE_INFO, "Link is now DOWN.\n"); 3896 } 3897 3898 } 3899 3900 /* Acknowledge the link change interrupt. */ 3901 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 3902 } 3903 3904 3905 /****************************************************************************/ 3906 /* Handles received frame interrupt events. */ 3907 /* */ 3908 /* Returns: */ 3909 /* Nothing. */ 3910 /****************************************************************************/ 3911 static void 3912 bce_rx_intr(struct bce_softc *sc) 3913 { 3914 struct status_block *sblk = sc->status_block; 3915 struct ifnet *ifp = sc->bce_ifp; 3916 u16 hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod; 3917 u32 sw_prod_bseq; 3918 struct l2_fhdr *l2fhdr; 3919 3920 DBRUNIF(1, sc->rx_interrupts++); 3921 3922 /* Prepare the RX chain pages to be accessed by the host CPU. */ 3923 for (int i = 0; i < RX_PAGES; i++) 3924 bus_dmamap_sync(sc->rx_bd_chain_tag, 3925 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE); 3926 3927 /* Get the hardware's view of the RX consumer index. */ 3928 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 3929 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 3930 hw_cons++; 3931 3932 /* Get working copies of the driver's view of the RX indices. */ 3933 sw_cons = sc->rx_cons; 3934 sw_prod = sc->rx_prod; 3935 sw_prod_bseq = sc->rx_prod_bseq; 3936 3937 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 3938 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 3939 __FUNCTION__, sw_prod, sw_cons, 3940 sw_prod_bseq); 3941 3942 /* Prevent speculative reads from getting ahead of the status block. */ 3943 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 3944 BUS_SPACE_BARRIER_READ); 3945 3946 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3947 sc->rx_low_watermark = sc->free_rx_bd); 3948 3949 /* 3950 * Scan through the receive chain as long 3951 * as there is work to do. 3952 */ 3953 while (sw_cons != hw_cons) { 3954 struct mbuf *m; 3955 struct rx_bd *rxbd; 3956 unsigned int len; 3957 u32 status; 3958 3959 /* Convert the producer/consumer indices to an actual rx_bd index. */ 3960 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 3961 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 3962 3963 /* Get the used rx_bd. */ 3964 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 3965 sc->free_rx_bd++; 3966 3967 DBRUN(BCE_VERBOSE_RECV, 3968 BCE_PRINTF(sc, "%s(): ", __FUNCTION__); 3969 bce_dump_rxbd(sc, sw_chain_cons, rxbd)); 3970 3971 #ifdef DEVICE_POLLING 3972 if (ifp->if_capenable & IFCAP_POLLING) { 3973 if (sc->bce_rxcycles <= 0) 3974 break; 3975 sc->bce_rxcycles--; 3976 } 3977 #endif 3978 3979 /* The mbuf is stored with the last rx_bd entry of a packet. */ 3980 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 3981 3982 /* Validate that this is the last rx_bd. */ 3983 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)), 3984 BCE_PRINTF(sc, "%s(%d): Unexpected mbuf found in rx_bd[0x%04X]!\n", 3985 __FILE__, __LINE__, sw_chain_cons); 3986 bce_breakpoint(sc)); 3987 3988 /* DRC - ToDo: If the received packet is small, say less */ 3989 /* than 128 bytes, allocate a new mbuf here, */ 3990 /* copy the data to that mbuf, and recycle */ 3991 /* the mapped jumbo frame. */ 3992 3993 /* Unmap the mbuf from DMA space. */ 3994 bus_dmamap_sync(sc->rx_mbuf_tag, 3995 sc->rx_mbuf_map[sw_chain_cons], 3996 BUS_DMASYNC_POSTREAD); 3997 bus_dmamap_unload(sc->rx_mbuf_tag, 3998 sc->rx_mbuf_map[sw_chain_cons]); 3999 4000 /* Remove the mbuf from the driver's chain. */ 4001 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4002 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4003 4004 /* 4005 * Frames received on the NetXteme II are prepended 4006 * with the l2_fhdr structure which provides status 4007 * information about the received frame (including 4008 * VLAN tags and checksum info) and are also 4009 * automatically adjusted to align the IP header 4010 * (i.e. two null bytes are inserted before the 4011 * Ethernet header). 4012 */ 4013 l2fhdr = mtod(m, struct l2_fhdr *); 4014 4015 len = l2fhdr->l2_fhdr_pkt_len; 4016 status = l2fhdr->l2_fhdr_status; 4017 4018 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check), 4019 BCE_PRINTF(sc, "Simulating l2_fhdr status error.\n"); 4020 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4021 4022 /* Watch for unusual sized frames. */ 4023 DBRUNIF(((len < BCE_MIN_MTU) || (len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 4024 BCE_PRINTF(sc, "%s(%d): Unusual frame size found. " 4025 "Min(%d), Actual(%d), Max(%d)\n", 4026 __FILE__, __LINE__, (int) BCE_MIN_MTU, 4027 len, (int) BCE_MAX_JUMBO_ETHER_MTU_VLAN); 4028 bce_dump_mbuf(sc, m); 4029 bce_breakpoint(sc)); 4030 4031 len -= ETHER_CRC_LEN; 4032 4033 /* Check the received frame for errors. */ 4034 if (status & (L2_FHDR_ERRORS_BAD_CRC | 4035 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 4036 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 4037 4038 ifp->if_ierrors++; 4039 DBRUNIF(1, sc->l2fhdr_status_errors++); 4040 4041 /* Reuse the mbuf for a new frame. */ 4042 if (bce_get_buf(sc, m, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4043 4044 DBRUNIF(1, bce_breakpoint(sc)); 4045 panic("bce%d: Can't reuse RX mbuf!\n", sc->bce_unit); 4046 4047 } 4048 goto bce_rx_int_next_rx; 4049 } 4050 4051 /* 4052 * Get a new mbuf for the rx_bd. If no new 4053 * mbufs are available then reuse the current mbuf, 4054 * log an ierror on the interface, and generate 4055 * an error in the system log. 4056 */ 4057 if (bce_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4058 4059 DBRUN(BCE_WARN, 4060 BCE_PRINTF(sc, "%s(%d): Failed to allocate " 4061 "new mbuf, incoming frame dropped!\n", 4062 __FILE__, __LINE__)); 4063 4064 ifp->if_ierrors++; 4065 4066 /* Try and reuse the exisitng mbuf. */ 4067 if (bce_get_buf(sc, m, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4068 4069 DBRUNIF(1, bce_breakpoint(sc)); 4070 panic("bce%d: Double mbuf allocation failure!", sc->bce_unit); 4071 4072 } 4073 goto bce_rx_int_next_rx; 4074 } 4075 4076 /* Skip over the l2_fhdr when passing the data up the stack. */ 4077 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4078 4079 /* Adjust the packet length to match the received data. */ 4080 m->m_pkthdr.len = m->m_len = len; 4081 4082 /* Send the packet to the appropriate interface. */ 4083 m->m_pkthdr.rcvif = ifp; 4084 4085 DBRUN(BCE_VERBOSE_RECV, 4086 struct ether_header *eh; 4087 eh = mtod(m, struct ether_header *); 4088 BCE_PRINTF(sc, "%s(): to: %6D, from: %6D, type: 0x%04X\n", 4089 __FUNCTION__, eh->ether_dhost, ":", 4090 eh->ether_shost, ":", htons(eh->ether_type))); 4091 4092 /* Validate the checksum if offload enabled. */ 4093 if (ifp->if_capenable & IFCAP_RXCSUM) { 4094 4095 /* Check for an IP datagram. */ 4096 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4097 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4098 4099 /* Check if the IP checksum is valid. */ 4100 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4101 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4102 else 4103 DBPRINT(sc, BCE_WARN_SEND, 4104 "%s(): Invalid IP checksum = 0x%04X!\n", 4105 __FUNCTION__, l2fhdr->l2_fhdr_ip_xsum); 4106 } 4107 4108 /* Check for a valid TCP/UDP frame. */ 4109 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4110 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4111 4112 /* Check for a good TCP/UDP checksum. */ 4113 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 4114 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4115 m->m_pkthdr.csum_data = 4116 l2fhdr->l2_fhdr_tcp_udp_xsum; 4117 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID 4118 | CSUM_PSEUDO_HDR); 4119 } else 4120 DBPRINT(sc, BCE_WARN_SEND, 4121 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n", 4122 __FUNCTION__, l2fhdr->l2_fhdr_tcp_udp_xsum); 4123 } 4124 } 4125 4126 4127 /* 4128 * If we received a packet with a vlan tag, 4129 * attach that information to the packet. 4130 */ 4131 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 4132 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): VLAN tag = 0x%04X\n", 4133 __FUNCTION__, l2fhdr->l2_fhdr_vlan_tag); 4134 #if __FreeBSD_version < 700000 4135 VLAN_INPUT_TAG(ifp, m, l2fhdr->l2_fhdr_vlan_tag, continue); 4136 #else 4137 m->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag; 4138 m->m_flags |= M_VLANTAG; 4139 #endif 4140 } 4141 4142 /* Pass the mbuf off to the upper layers. */ 4143 ifp->if_ipackets++; 4144 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(): Passing received frame up.\n", 4145 __FUNCTION__); 4146 BCE_UNLOCK(sc); 4147 (*ifp->if_input)(ifp, m); 4148 DBRUNIF(1, sc->rx_mbuf_alloc--); 4149 BCE_LOCK(sc); 4150 4151 bce_rx_int_next_rx: 4152 sw_prod = NEXT_RX_BD(sw_prod); 4153 } 4154 4155 sw_cons = NEXT_RX_BD(sw_cons); 4156 4157 /* Refresh hw_cons to see if there's new work */ 4158 if (sw_cons == hw_cons) { 4159 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4160 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4161 hw_cons++; 4162 } 4163 4164 /* Prevent speculative reads from getting ahead of the status block. */ 4165 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4166 BUS_SPACE_BARRIER_READ); 4167 } 4168 4169 for (int i = 0; i < RX_PAGES; i++) 4170 bus_dmamap_sync(sc->rx_bd_chain_tag, 4171 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 4172 4173 sc->rx_cons = sw_cons; 4174 sc->rx_prod = sw_prod; 4175 sc->rx_prod_bseq = sw_prod_bseq; 4176 4177 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); 4178 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4179 4180 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4181 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4182 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4183 } 4184 4185 4186 /****************************************************************************/ 4187 /* Handles transmit completion interrupt events. */ 4188 /* */ 4189 /* Returns: */ 4190 /* Nothing. */ 4191 /****************************************************************************/ 4192 static void 4193 bce_tx_intr(struct bce_softc *sc) 4194 { 4195 struct status_block *sblk = sc->status_block; 4196 struct ifnet *ifp = sc->bce_ifp; 4197 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4198 4199 BCE_LOCK_ASSERT(sc); 4200 4201 DBRUNIF(1, sc->tx_interrupts++); 4202 4203 /* Get the hardware's view of the TX consumer index. */ 4204 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4205 4206 /* Skip to the next entry if this is a chain page pointer. */ 4207 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4208 hw_tx_cons++; 4209 4210 sw_tx_cons = sc->tx_cons; 4211 4212 /* Prevent speculative reads from getting ahead of the status block. */ 4213 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4214 BUS_SPACE_BARRIER_READ); 4215 4216 /* Cycle through any completed TX chain page entries. */ 4217 while (sw_tx_cons != hw_tx_cons) { 4218 #ifdef BCE_DEBUG 4219 struct tx_bd *txbd = NULL; 4220 #endif 4221 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4222 4223 DBPRINT(sc, BCE_INFO_SEND, 4224 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 4225 "sw_tx_chain_cons = 0x%04X\n", 4226 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4227 4228 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4229 BCE_PRINTF(sc, "%s(%d): TX chain consumer out of range! " 4230 " 0x%04X > 0x%04X\n", 4231 __FILE__, __LINE__, sw_tx_chain_cons, 4232 (int) MAX_TX_BD); 4233 bce_breakpoint(sc)); 4234 4235 DBRUNIF(1, 4236 txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 4237 [TX_IDX(sw_tx_chain_cons)]); 4238 4239 DBRUNIF((txbd == NULL), 4240 BCE_PRINTF(sc, "%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 4241 __FILE__, __LINE__, sw_tx_chain_cons); 4242 bce_breakpoint(sc)); 4243 4244 DBRUN(BCE_INFO_SEND, 4245 BCE_PRINTF(sc, "%s(): ", __FUNCTION__); 4246 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4247 4248 /* 4249 * Free the associated mbuf. Remember 4250 * that only the last tx_bd of a packet 4251 * has an mbuf pointer and DMA map. 4252 */ 4253 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 4254 4255 /* Validate that this is the last tx_bd. */ 4256 DBRUNIF((!(txbd->tx_bd_vlan_tag_flags & TX_BD_FLAGS_END)), 4257 BCE_PRINTF(sc, "%s(%d): tx_bd END flag not set but " 4258 "txmbuf == NULL!\n", __FILE__, __LINE__); 4259 bce_breakpoint(sc)); 4260 4261 DBRUN(BCE_INFO_SEND, 4262 BCE_PRINTF(sc, "%s(): Unloading map/freeing mbuf " 4263 "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons)); 4264 4265 /* Unmap the mbuf. */ 4266 bus_dmamap_unload(sc->tx_mbuf_tag, 4267 sc->tx_mbuf_map[sw_tx_chain_cons]); 4268 4269 /* Free the mbuf. */ 4270 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 4271 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 4272 DBRUNIF(1, sc->tx_mbuf_alloc--); 4273 4274 ifp->if_opackets++; 4275 } 4276 4277 sc->used_tx_bd--; 4278 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4279 4280 /* Refresh hw_cons to see if there's new work. */ 4281 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4282 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4283 hw_tx_cons++; 4284 4285 /* Prevent speculative reads from getting ahead of the status block. */ 4286 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4287 BUS_SPACE_BARRIER_READ); 4288 } 4289 4290 /* Clear the TX timeout timer. */ 4291 ifp->if_timer = 0; 4292 4293 /* Clear the tx hardware queue full flag. */ 4294 if ((sc->used_tx_bd + BCE_TX_SLACK_SPACE) < USABLE_TX_BD) { 4295 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 4296 BCE_PRINTF(sc, "%s(): TX chain is open for business! Used tx_bd = %d\n", 4297 __FUNCTION__, sc->used_tx_bd)); 4298 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4299 } 4300 4301 sc->tx_cons = sw_tx_cons; 4302 } 4303 4304 4305 /****************************************************************************/ 4306 /* Disables interrupt generation. */ 4307 /* */ 4308 /* Returns: */ 4309 /* Nothing. */ 4310 /****************************************************************************/ 4311 static void 4312 bce_disable_intr(struct bce_softc *sc) 4313 { 4314 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4315 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 4316 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 4317 } 4318 4319 4320 /****************************************************************************/ 4321 /* Enables interrupt generation. */ 4322 /* */ 4323 /* Returns: */ 4324 /* Nothing. */ 4325 /****************************************************************************/ 4326 static void 4327 bce_enable_intr(struct bce_softc *sc) 4328 { 4329 u32 val; 4330 4331 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4332 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 4333 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4334 4335 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4336 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4337 4338 val = REG_RD(sc, BCE_HC_COMMAND); 4339 REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW); 4340 } 4341 4342 4343 /****************************************************************************/ 4344 /* Handles controller initialization. */ 4345 /* */ 4346 /* Must be called from a locked routine. */ 4347 /* */ 4348 /* Returns: */ 4349 /* Nothing. */ 4350 /****************************************************************************/ 4351 static void 4352 bce_init_locked(struct bce_softc *sc) 4353 { 4354 struct ifnet *ifp; 4355 u32 ether_mtu; 4356 4357 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4358 4359 BCE_LOCK_ASSERT(sc); 4360 4361 ifp = sc->bce_ifp; 4362 4363 /* Check if the driver is still running and bail out if it is. */ 4364 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4365 goto bce_init_locked_exit; 4366 4367 bce_stop(sc); 4368 4369 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 4370 BCE_PRINTF(sc, "%s(%d): Controller reset failed!\n", 4371 __FILE__, __LINE__); 4372 goto bce_init_locked_exit; 4373 } 4374 4375 if (bce_chipinit(sc)) { 4376 BCE_PRINTF(sc, "%s(%d): Controller initialization failed!\n", 4377 __FILE__, __LINE__); 4378 goto bce_init_locked_exit; 4379 } 4380 4381 if (bce_blockinit(sc)) { 4382 BCE_PRINTF(sc, "%s(%d): Block initialization failed!\n", 4383 __FILE__, __LINE__); 4384 goto bce_init_locked_exit; 4385 } 4386 4387 /* Load our MAC address. */ 4388 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 4389 bce_set_mac_addr(sc); 4390 4391 /* Calculate and program the Ethernet MTU size. */ 4392 ether_mtu = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ifp->if_mtu + 4393 ETHER_CRC_LEN; 4394 4395 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n",__FUNCTION__, ether_mtu); 4396 4397 /* 4398 * Program the mtu, enabling jumbo frame 4399 * support if necessary. Also set the mbuf 4400 * allocation count for RX frames. 4401 */ 4402 if (ether_mtu > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 4403 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu | 4404 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4405 sc->mbuf_alloc_size = MJUM9BYTES; 4406 } else { 4407 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 4408 sc->mbuf_alloc_size = MCLBYTES; 4409 } 4410 4411 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4412 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4413 4414 DBPRINT(sc, BCE_INFO, 4415 "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4416 "max_frame_size = %d\n", 4417 __FUNCTION__, (int) MCLBYTES, sc->mbuf_alloc_size, sc->max_frame_size); 4418 4419 /* Program appropriate promiscuous/multicast filtering. */ 4420 bce_set_rx_mode(sc); 4421 4422 /* Init RX buffer descriptor chain. */ 4423 bce_init_rx_chain(sc); 4424 4425 /* Init TX buffer descriptor chain. */ 4426 bce_init_tx_chain(sc); 4427 4428 #ifdef DEVICE_POLLING 4429 /* Disable interrupts if we are polling. */ 4430 if (ifp->if_capenable & IFCAP_POLLING) { 4431 bce_disable_intr(sc); 4432 4433 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4434 (1 << 16) | sc->bce_rx_quick_cons_trip); 4435 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4436 (1 << 16) | sc->bce_tx_quick_cons_trip); 4437 } else 4438 #endif 4439 /* Enable host interrupts. */ 4440 bce_enable_intr(sc); 4441 4442 bce_ifmedia_upd(ifp); 4443 4444 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4445 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4446 4447 callout_reset(&sc->bce_stat_ch, hz, bce_tick, sc); 4448 4449 bce_init_locked_exit: 4450 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4451 4452 return; 4453 } 4454 4455 static void 4456 bce_mgmt_init_locked(struct bce_softc *sc) 4457 { 4458 u32 val; 4459 struct ifnet *ifp; 4460 4461 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4462 4463 BCE_LOCK_ASSERT(sc); 4464 4465 ifp = sc->bce_ifp; 4466 4467 /* Check if the driver is still running and bail out if it is. */ 4468 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4469 goto bce_mgmt_init_locked_exit; 4470 4471 /* Initialize the on-boards CPUs */ 4472 bce_init_cpus(sc); 4473 4474 val = (BCM_PAGE_BITS - 8) << 24; 4475 REG_WR(sc, BCE_RV2P_CONFIG, val); 4476 4477 /* Enable all critical blocks in the MAC. */ 4478 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4479 BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE | 4480 BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE | 4481 BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE); 4482 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4483 DELAY(20); 4484 4485 bce_ifmedia_upd(ifp); 4486 bce_mgmt_init_locked_exit: 4487 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4488 4489 return; 4490 } 4491 4492 4493 /****************************************************************************/ 4494 /* Handles controller initialization when called from an unlocked routine. */ 4495 /* */ 4496 /* Returns: */ 4497 /* Nothing. */ 4498 /****************************************************************************/ 4499 static void 4500 bce_init(void *xsc) 4501 { 4502 struct bce_softc *sc = xsc; 4503 4504 BCE_LOCK(sc); 4505 bce_init_locked(sc); 4506 BCE_UNLOCK(sc); 4507 } 4508 4509 4510 /****************************************************************************/ 4511 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4512 /* memory visible to the controller. */ 4513 /* */ 4514 /* Returns: */ 4515 /* 0 for success, positive value for failure. */ 4516 /****************************************************************************/ 4517 static int 4518 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 4519 { 4520 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 4521 bus_dmamap_t map; 4522 struct tx_bd *txbd = NULL; 4523 struct mbuf *m0; 4524 u32 vlan_tag_flags = 0; 4525 u32 prod_bseq; 4526 u16 chain_prod, prod; 4527 4528 #ifdef BCE_DEBUG 4529 u16 debug_prod; 4530 #endif 4531 int i, error, nsegs, rc = 0; 4532 4533 /* Transfer any checksum offload flags to the bd. */ 4534 m0 = *m_head; 4535 if (m0->m_pkthdr.csum_flags) { 4536 if (m0->m_pkthdr.csum_flags & CSUM_IP) 4537 vlan_tag_flags |= TX_BD_FLAGS_IP_CKSUM; 4538 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 4539 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4540 } 4541 4542 /* Transfer any VLAN tags to the bd. */ 4543 if (m0->m_flags & M_VLANTAG) 4544 vlan_tag_flags |= (TX_BD_FLAGS_VLAN_TAG | 4545 (m0->m_pkthdr.ether_vtag << 16)); 4546 4547 /* Map the mbuf into DMAable memory. */ 4548 prod = sc->tx_prod; 4549 chain_prod = TX_CHAIN_IDX(prod); 4550 map = sc->tx_mbuf_map[chain_prod]; 4551 4552 /* 4553 * XXX This should be handled higher up. 4554 */ 4555 if ((USABLE_TX_BD - sc->used_tx_bd - BCE_TX_SLACK_SPACE) <= 0) { 4556 return (ENOBUFS); 4557 } 4558 4559 /* Map the mbuf into our DMA address space. */ 4560 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4561 segs, &nsegs, BUS_DMA_NOWAIT); 4562 4563 if (error == EFBIG) { 4564 4565 /* Try to defrag the mbuf if there are too many segments. */ 4566 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n", 4567 __FUNCTION__, map_arg.maxsegs); 4568 4569 m0 = m_defrag(*m_head, M_DONTWAIT); 4570 if (m0 == NULL) { 4571 m_freem(*m_head); 4572 *m_head = NULL; 4573 return (ENOBUFS); 4574 } 4575 4576 *m_head = m0; 4577 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4578 segs, &nsegs, BUS_DMA_NOWAIT); 4579 4580 /* Still getting an error after a defrag. */ 4581 if (error == ENOMEM) { 4582 return (error); 4583 } else if (error != 0) { 4584 BCE_PRINTF(sc, 4585 "%s(%d): Error mapping mbuf into TX chain!\n", 4586 __FILE__, __LINE__); 4587 m_freem(m0); 4588 *m_head = NULL; 4589 return (ENOBUFS); 4590 } 4591 } else if (error == ENOMEM) { 4592 return (error); 4593 } else if (error != 0) { 4594 m_freem(m0); 4595 *m_head = NULL; 4596 return (error); 4597 } 4598 4599 4600 /* prod points to an empty tx_bd at this point. */ 4601 prod_bseq = sc->tx_prod_bseq; 4602 4603 #ifdef BCE_DEBUG 4604 debug_prod = chain_prod; 4605 #endif 4606 4607 DBPRINT(sc, BCE_INFO_SEND, 4608 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4609 "prod_bseq = 0x%08X\n", 4610 __FUNCTION__, *prod, chain_prod, prod_bseq); 4611 4612 /* 4613 * Cycle through each mbuf segment that makes up 4614 * the outgoing frame, gathering the mapping info 4615 * for that segment and creating a tx_bd to for 4616 * the mbuf. 4617 */ 4618 for (i = 0; i < nsegs ; i++) { 4619 4620 chain_prod = TX_CHAIN_IDX(prod); 4621 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4622 4623 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 4624 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 4625 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len); 4626 txbd->tx_bd_vlan_tag_flags = htole16(vlan_tag_flags); 4627 prod_bseq += segs[i].ds_len; 4628 if (i == 0) 4629 txbd->tx_bd_vlan_tag_flags |=htole16(TX_BD_FLAGS_START); 4630 prod = NEXT_TX_BD(prod); 4631 } 4632 4633 /* Set the END flag on the last TX buffer descriptor. */ 4634 txbd->tx_bd_vlan_tag_flags |= htole16(TX_BD_FLAGS_END); 4635 4636 DBRUN(BCE_INFO_SEND, bce_dump_tx_chain(sc, debug_prod, nseg)); 4637 4638 DBPRINT(sc, BCE_INFO_SEND, 4639 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4640 "prod_bseq = 0x%08X\n", 4641 __FUNCTION__, prod, chain_prod, prod_bseq); 4642 4643 /* 4644 * Ensure that the map for this transmission 4645 * is placed at the array index of the last 4646 * descriptor in this chain. This is done 4647 * because a single map is used for all 4648 * segments of the mbuf and we don't want to 4649 * delete the map before all of the segments 4650 * have been freed. 4651 */ 4652 sc->tx_mbuf_map[TX_CHAIN_IDX(sc->tx_prod)] = 4653 sc->tx_mbuf_map[chain_prod]; 4654 sc->tx_mbuf_map[chain_prod] = map; 4655 sc->tx_mbuf_ptr[chain_prod] = m0; 4656 sc->used_tx_bd += nsegs; 4657 4658 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4659 sc->tx_hi_watermark = sc->used_tx_bd); 4660 4661 DBRUNIF(1, sc->tx_mbuf_alloc++); 4662 4663 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs)); 4664 4665 /* prod still points the last used tx_bd at this point. */ 4666 sc->tx_prod = prod; 4667 sc->tx_prod_bseq = prod_bseq; 4668 4669 return(rc); 4670 } 4671 4672 4673 /****************************************************************************/ 4674 /* Main transmit routine when called from another routine with a lock. */ 4675 /* */ 4676 /* Returns: */ 4677 /* Nothing. */ 4678 /****************************************************************************/ 4679 static void 4680 bce_start_locked(struct ifnet *ifp) 4681 { 4682 struct bce_softc *sc = ifp->if_softc; 4683 struct mbuf *m_head = NULL; 4684 int count = 0; 4685 u16 tx_prod, tx_chain_prod; 4686 4687 /* If there's no link or the transmit queue is empty then just exit. */ 4688 if (!sc->bce_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 4689 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link or transmit queue empty.\n", 4690 __FUNCTION__); 4691 goto bce_start_locked_exit; 4692 } 4693 4694 /* prod points to the next free tx_bd. */ 4695 tx_prod = sc->tx_prod; 4696 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4697 4698 DBPRINT(sc, BCE_INFO_SEND, 4699 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, " 4700 "tx_prod_bseq = 0x%08X\n", 4701 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4702 4703 /* Keep adding entries while there is space in the ring. */ 4704 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 4705 4706 /* Check for any frames to send. */ 4707 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4708 if (m_head == NULL) 4709 break; 4710 4711 /* 4712 * Pack the data into the transmit ring. If we 4713 * don't have room, place the mbuf back at the 4714 * head of the queue and set the OACTIVE flag 4715 * to wait for the NIC to drain the chain. 4716 */ 4717 if (bce_tx_encap(sc, &m_head)) { 4718 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4719 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4720 DBPRINT(sc, BCE_INFO_SEND, 4721 "TX chain is closed for business! Total tx_bd used = %d\n", 4722 sc->used_tx_bd); 4723 break; 4724 } 4725 4726 count++; 4727 4728 /* Send a copy of the frame to any BPF listeners. */ 4729 BPF_MTAP(ifp, m_head); 4730 } 4731 4732 if (count == 0) { 4733 /* no packets were dequeued */ 4734 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n", 4735 __FUNCTION__); 4736 goto bce_start_locked_exit; 4737 } 4738 4739 /* Update the driver's counters. */ 4740 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4741 4742 DBPRINT(sc, BCE_INFO_SEND, 4743 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 4744 "tx_prod_bseq = 0x%08X\n", 4745 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4746 4747 /* Start the transmit. */ 4748 REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4749 REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4750 4751 /* Set the tx timeout. */ 4752 ifp->if_timer = BCE_TX_TIMEOUT; 4753 4754 bce_start_locked_exit: 4755 return; 4756 } 4757 4758 4759 /****************************************************************************/ 4760 /* Main transmit routine when called from another routine without a lock. */ 4761 /* */ 4762 /* Returns: */ 4763 /* Nothing. */ 4764 /****************************************************************************/ 4765 static void 4766 bce_start(struct ifnet *ifp) 4767 { 4768 struct bce_softc *sc = ifp->if_softc; 4769 4770 BCE_LOCK(sc); 4771 bce_start_locked(ifp); 4772 BCE_UNLOCK(sc); 4773 } 4774 4775 4776 /****************************************************************************/ 4777 /* Handles any IOCTL calls from the operating system. */ 4778 /* */ 4779 /* Returns: */ 4780 /* 0 for success, positive value for failure. */ 4781 /****************************************************************************/ 4782 static int 4783 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4784 { 4785 struct bce_softc *sc = ifp->if_softc; 4786 struct ifreq *ifr = (struct ifreq *) data; 4787 struct mii_data *mii; 4788 int mask, error = 0; 4789 4790 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4791 4792 switch(command) { 4793 4794 /* Set the MTU. */ 4795 case SIOCSIFMTU: 4796 /* Check that the MTU setting is supported. */ 4797 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 4798 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 4799 error = EINVAL; 4800 break; 4801 } 4802 4803 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu); 4804 4805 BCE_LOCK(sc); 4806 ifp->if_mtu = ifr->ifr_mtu; 4807 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4808 bce_init_locked(sc); 4809 BCE_UNLOCK(sc); 4810 break; 4811 4812 /* Set interface. */ 4813 case SIOCSIFFLAGS: 4814 DBPRINT(sc, BCE_VERBOSE, "Received SIOCSIFFLAGS\n"); 4815 4816 BCE_LOCK(sc); 4817 4818 /* Check if the interface is up. */ 4819 if (ifp->if_flags & IFF_UP) { 4820 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4821 /* Change the promiscuous/multicast flags as necessary. */ 4822 bce_set_rx_mode(sc); 4823 } else { 4824 /* Start the HW */ 4825 bce_init_locked(sc); 4826 } 4827 } else { 4828 /* The interface is down. Check if the driver is running. */ 4829 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4830 bce_stop(sc); 4831 } 4832 } 4833 4834 BCE_UNLOCK(sc); 4835 error = 0; 4836 4837 break; 4838 4839 /* Add/Delete multicast address */ 4840 case SIOCADDMULTI: 4841 case SIOCDELMULTI: 4842 DBPRINT(sc, BCE_VERBOSE, "Received SIOCADDMULTI/SIOCDELMULTI\n"); 4843 4844 BCE_LOCK(sc); 4845 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4846 bce_set_rx_mode(sc); 4847 error = 0; 4848 } 4849 BCE_UNLOCK(sc); 4850 4851 break; 4852 4853 /* Set/Get Interface media */ 4854 case SIOCSIFMEDIA: 4855 case SIOCGIFMEDIA: 4856 DBPRINT(sc, BCE_VERBOSE, "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 4857 4858 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n", 4859 sc->bce_phy_flags); 4860 4861 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 4862 DBPRINT(sc, BCE_VERBOSE, "SerDes media set/get\n"); 4863 4864 error = ifmedia_ioctl(ifp, ifr, 4865 &sc->bce_ifmedia, command); 4866 } else { 4867 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n"); 4868 mii = device_get_softc(sc->bce_miibus); 4869 error = ifmedia_ioctl(ifp, ifr, 4870 &mii->mii_media, command); 4871 } 4872 break; 4873 4874 /* Set interface capability */ 4875 case SIOCSIFCAP: 4876 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4877 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 4878 4879 #ifdef DEVICE_POLLING 4880 if (mask & IFCAP_POLLING) { 4881 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4882 4883 /* Setup the poll routine to call. */ 4884 error = ether_poll_register(bce_poll, ifp); 4885 if (error) { 4886 BCE_PRINTF(sc, "%s(%d): Error registering poll function!\n", 4887 __FILE__, __LINE__); 4888 goto bce_ioctl_exit; 4889 } 4890 4891 /* Clear the interrupt. */ 4892 BCE_LOCK(sc); 4893 bce_disable_intr(sc); 4894 4895 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4896 (1 << 16) | sc->bce_rx_quick_cons_trip); 4897 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4898 (1 << 16) | sc->bce_tx_quick_cons_trip); 4899 4900 ifp->if_capenable |= IFCAP_POLLING; 4901 BCE_UNLOCK(sc); 4902 } else { 4903 /* Clear the poll routine. */ 4904 error = ether_poll_deregister(ifp); 4905 4906 /* Enable interrupt even in error case */ 4907 BCE_LOCK(sc); 4908 bce_enable_intr(sc); 4909 4910 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4911 (sc->bce_tx_quick_cons_trip_int << 16) | 4912 sc->bce_tx_quick_cons_trip); 4913 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4914 (sc->bce_rx_quick_cons_trip_int << 16) | 4915 sc->bce_rx_quick_cons_trip); 4916 4917 ifp->if_capenable &= ~IFCAP_POLLING; 4918 BCE_UNLOCK(sc); 4919 } 4920 } 4921 #endif /*DEVICE_POLLING */ 4922 4923 /* Toggle the TX checksum capabilites enable flag. */ 4924 if (mask & IFCAP_TXCSUM) { 4925 ifp->if_capenable ^= IFCAP_TXCSUM; 4926 if (IFCAP_TXCSUM & ifp->if_capenable) 4927 ifp->if_hwassist = BCE_IF_HWASSIST; 4928 else 4929 ifp->if_hwassist = 0; 4930 } 4931 4932 /* Toggle the RX checksum capabilities enable flag. */ 4933 if (mask & IFCAP_RXCSUM) { 4934 ifp->if_capenable ^= IFCAP_RXCSUM; 4935 if (IFCAP_RXCSUM & ifp->if_capenable) 4936 ifp->if_hwassist = BCE_IF_HWASSIST; 4937 else 4938 ifp->if_hwassist = 0; 4939 } 4940 4941 /* Toggle VLAN_MTU capabilities enable flag. */ 4942 if (mask & IFCAP_VLAN_MTU) { 4943 BCE_PRINTF(sc, "%s(%d): Changing VLAN_MTU not supported.\n", 4944 __FILE__, __LINE__); 4945 } 4946 4947 /* Toggle VLANHWTAG capabilities enabled flag. */ 4948 if (mask & IFCAP_VLAN_HWTAGGING) { 4949 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 4950 BCE_PRINTF(sc, "%s(%d): Cannot change VLAN_HWTAGGING while " 4951 "management firmware (ASF/IPMI/UMP) is running!\n", 4952 __FILE__, __LINE__); 4953 else 4954 BCE_PRINTF(sc, "%s(%d): Changing VLAN_HWTAGGING not supported!\n", 4955 __FILE__, __LINE__); 4956 } 4957 4958 break; 4959 default: 4960 DBPRINT(sc, BCE_INFO, "Received unsupported IOCTL: 0x%08X\n", 4961 (u32) command); 4962 4963 /* We don't know how to handle the IOCTL, pass it on. */ 4964 error = ether_ioctl(ifp, command, data); 4965 break; 4966 } 4967 4968 #ifdef DEVICE_POLLING 4969 bce_ioctl_exit: 4970 #endif 4971 4972 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4973 4974 return(error); 4975 } 4976 4977 4978 /****************************************************************************/ 4979 /* Transmit timeout handler. */ 4980 /* */ 4981 /* Returns: */ 4982 /* Nothing. */ 4983 /****************************************************************************/ 4984 static void 4985 bce_watchdog(struct ifnet *ifp) 4986 { 4987 struct bce_softc *sc = ifp->if_softc; 4988 4989 DBRUN(BCE_WARN_SEND, 4990 bce_dump_driver_state(sc); 4991 bce_dump_status_block(sc)); 4992 4993 BCE_PRINTF(sc, "%s(%d): Watchdog timeout occurred, resetting!\n", 4994 __FILE__, __LINE__); 4995 4996 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */ 4997 4998 BCE_LOCK(sc); 4999 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5000 5001 bce_init_locked(sc); 5002 ifp->if_oerrors++; 5003 BCE_UNLOCK(sc); 5004 5005 } 5006 5007 5008 #ifdef DEVICE_POLLING 5009 static void 5010 bce_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 5011 { 5012 struct bce_softc *sc = ifp->if_softc; 5013 5014 BCE_LOCK_ASSERT(sc); 5015 5016 sc->bce_rxcycles = count; 5017 5018 bus_dmamap_sync(sc->status_tag, sc->status_map, 5019 BUS_DMASYNC_POSTWRITE); 5020 5021 /* Check for any completed RX frames. */ 5022 if (sc->status_block->status_rx_quick_consumer_index0 != 5023 sc->hw_rx_cons) 5024 bce_rx_intr(sc); 5025 5026 /* Check for any completed TX frames. */ 5027 if (sc->status_block->status_tx_quick_consumer_index0 != 5028 sc->hw_tx_cons) 5029 bce_tx_intr(sc); 5030 5031 /* Check for new frames to transmit. */ 5032 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5033 bce_start_locked(ifp); 5034 5035 } 5036 5037 5038 static void 5039 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 5040 { 5041 struct bce_softc *sc = ifp->if_softc; 5042 5043 BCE_LOCK(sc); 5044 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5045 bce_poll_locked(ifp, cmd, count); 5046 BCE_UNLOCK(sc); 5047 } 5048 #endif /* DEVICE_POLLING */ 5049 5050 5051 #if 0 5052 static inline int 5053 bce_has_work(struct bce_softc *sc) 5054 { 5055 struct status_block *stat = sc->status_block; 5056 5057 if ((stat->status_rx_quick_consumer_index0 != sc->hw_rx_cons) || 5058 (stat->status_tx_quick_consumer_index0 != sc->hw_tx_cons)) 5059 return 1; 5060 5061 if (((stat->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) != 5062 bp->link_up) 5063 return 1; 5064 5065 return 0; 5066 } 5067 #endif 5068 5069 5070 /* 5071 * Interrupt handler. 5072 */ 5073 /****************************************************************************/ 5074 /* Main interrupt entry point. Verifies that the controller generated the */ 5075 /* interrupt and then calls a separate routine for handle the various */ 5076 /* interrupt causes (PHY, TX, RX). */ 5077 /* */ 5078 /* Returns: */ 5079 /* 0 for success, positive value for failure. */ 5080 /****************************************************************************/ 5081 static void 5082 bce_intr(void *xsc) 5083 { 5084 struct bce_softc *sc; 5085 struct ifnet *ifp; 5086 u32 status_attn_bits; 5087 5088 sc = xsc; 5089 ifp = sc->bce_ifp; 5090 5091 BCE_LOCK(sc); 5092 5093 DBRUNIF(1, sc->interrupts_generated++); 5094 5095 #ifdef DEVICE_POLLING 5096 if (ifp->if_capenable & IFCAP_POLLING) { 5097 DBPRINT(sc, BCE_INFO, "Polling enabled!\n"); 5098 goto bce_intr_exit; 5099 } 5100 #endif 5101 5102 bus_dmamap_sync(sc->status_tag, sc->status_map, 5103 BUS_DMASYNC_POSTWRITE); 5104 5105 /* 5106 * If the hardware status block index 5107 * matches the last value read by the 5108 * driver and we haven't asserted our 5109 * interrupt then there's nothing to do. 5110 */ 5111 if ((sc->status_block->status_idx == sc->last_status_idx) && 5112 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) 5113 goto bce_intr_exit; 5114 5115 /* Ack the interrupt and stop others from occuring. */ 5116 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5117 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5118 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5119 5120 /* Keep processing data as long as there is work to do. */ 5121 for (;;) { 5122 5123 status_attn_bits = sc->status_block->status_attn_bits; 5124 5125 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention), 5126 BCE_PRINTF(sc, "Simulating unexpected status attention bit set."); 5127 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR); 5128 5129 /* Was it a link change interrupt? */ 5130 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5131 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) 5132 bce_phy_intr(sc); 5133 5134 /* If any other attention is asserted then the chip is toast. */ 5135 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5136 (sc->status_block->status_attn_bits_ack & 5137 ~STATUS_ATTN_BITS_LINK_STATE))) { 5138 5139 DBRUN(1, sc->unexpected_attentions++); 5140 5141 BCE_PRINTF(sc, "%s(%d): Fatal attention detected: 0x%08X\n", 5142 __FILE__, __LINE__, sc->status_block->status_attn_bits); 5143 5144 DBRUN(BCE_FATAL, 5145 if (bce_debug_unexpected_attention == 0) 5146 bce_breakpoint(sc)); 5147 5148 bce_init_locked(sc); 5149 goto bce_intr_exit; 5150 } 5151 5152 /* Check for any completed RX frames. */ 5153 if (sc->status_block->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5154 bce_rx_intr(sc); 5155 5156 /* Check for any completed TX frames. */ 5157 if (sc->status_block->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5158 bce_tx_intr(sc); 5159 5160 /* Save the status block index value for use during the next interrupt. */ 5161 sc->last_status_idx = sc->status_block->status_idx; 5162 5163 /* Prevent speculative reads from getting ahead of the status block. */ 5164 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 5165 BUS_SPACE_BARRIER_READ); 5166 5167 /* If there's no work left then exit the interrupt service routine. */ 5168 if ((sc->status_block->status_rx_quick_consumer_index0 == sc->hw_rx_cons) && 5169 (sc->status_block->status_tx_quick_consumer_index0 == sc->hw_tx_cons)) 5170 break; 5171 5172 } 5173 5174 bus_dmamap_sync(sc->status_tag, sc->status_map, 5175 BUS_DMASYNC_PREWRITE); 5176 5177 /* Re-enable interrupts. */ 5178 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5179 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5180 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5181 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5182 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5183 5184 /* Handle any frames that arrived while handling the interrupt. */ 5185 if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5186 bce_start_locked(ifp); 5187 5188 bce_intr_exit: 5189 BCE_UNLOCK(sc); 5190 } 5191 5192 5193 /****************************************************************************/ 5194 /* Programs the various packet receive modes (broadcast and multicast). */ 5195 /* */ 5196 /* Returns: */ 5197 /* Nothing. */ 5198 /****************************************************************************/ 5199 static void 5200 bce_set_rx_mode(struct bce_softc *sc) 5201 { 5202 struct ifnet *ifp; 5203 struct ifmultiaddr *ifma; 5204 u32 hashes[4] = { 0, 0, 0, 0 }; 5205 u32 rx_mode, sort_mode; 5206 int h, i; 5207 5208 BCE_LOCK_ASSERT(sc); 5209 5210 ifp = sc->bce_ifp; 5211 5212 /* Initialize receive mode default settings. */ 5213 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 5214 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 5215 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 5216 5217 /* 5218 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5219 * be enbled. 5220 */ 5221 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 5222 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 5223 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 5224 5225 /* 5226 * Check for promiscuous, all multicast, or selected 5227 * multicast address filtering. 5228 */ 5229 if (ifp->if_flags & IFF_PROMISC) { 5230 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n"); 5231 5232 /* Enable promiscuous mode. */ 5233 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 5234 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 5235 } else if (ifp->if_flags & IFF_ALLMULTI) { 5236 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n"); 5237 5238 /* Enable all multicast addresses. */ 5239 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 5240 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 5241 } 5242 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 5243 } else { 5244 /* Accept one or more multicast(s). */ 5245 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n"); 5246 5247 IF_ADDR_LOCK(ifp); 5248 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 5249 if (ifma->ifma_addr->sa_family != AF_LINK) 5250 continue; 5251 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 5252 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 5253 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 5254 } 5255 IF_ADDR_UNLOCK(ifp); 5256 5257 for (i = 0; i < 4; i++) 5258 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 5259 5260 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 5261 } 5262 5263 /* Only make changes if the recive mode has actually changed. */ 5264 if (rx_mode != sc->rx_mode) { 5265 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n", 5266 rx_mode); 5267 5268 sc->rx_mode = rx_mode; 5269 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 5270 } 5271 5272 /* Disable and clear the exisitng sort before enabling a new sort. */ 5273 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 5274 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 5275 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 5276 } 5277 5278 5279 /****************************************************************************/ 5280 /* Called periodically to updates statistics from the controllers */ 5281 /* statistics block. */ 5282 /* */ 5283 /* Returns: */ 5284 /* Nothing. */ 5285 /****************************************************************************/ 5286 static void 5287 bce_stats_update(struct bce_softc *sc) 5288 { 5289 struct ifnet *ifp; 5290 struct statistics_block *stats; 5291 5292 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 5293 5294 ifp = sc->bce_ifp; 5295 5296 stats = (struct statistics_block *) sc->stats_block; 5297 5298 /* 5299 * Update the interface statistics from the 5300 * hardware statistics. 5301 */ 5302 ifp->if_collisions = (u_long) stats->stat_EtherStatsCollisions; 5303 5304 ifp->if_ierrors = (u_long) stats->stat_EtherStatsUndersizePkts + 5305 (u_long) stats->stat_EtherStatsOverrsizePkts + 5306 (u_long) stats->stat_IfInMBUFDiscards + 5307 (u_long) stats->stat_Dot3StatsAlignmentErrors + 5308 (u_long) stats->stat_Dot3StatsFCSErrors; 5309 5310 ifp->if_oerrors = (u_long) stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5311 (u_long) stats->stat_Dot3StatsExcessiveCollisions + 5312 (u_long) stats->stat_Dot3StatsLateCollisions; 5313 5314 /* 5315 * Certain controllers don't report 5316 * carrier sense errors correctly. 5317 * See errata E11_5708CA0_1165. 5318 */ 5319 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5320 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 5321 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5322 5323 /* 5324 * Update the sysctl statistics from the 5325 * hardware statistics. 5326 */ 5327 sc->stat_IfHCInOctets = 5328 ((u64) stats->stat_IfHCInOctets_hi << 32) + 5329 (u64) stats->stat_IfHCInOctets_lo; 5330 5331 sc->stat_IfHCInBadOctets = 5332 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 5333 (u64) stats->stat_IfHCInBadOctets_lo; 5334 5335 sc->stat_IfHCOutOctets = 5336 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 5337 (u64) stats->stat_IfHCOutOctets_lo; 5338 5339 sc->stat_IfHCOutBadOctets = 5340 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 5341 (u64) stats->stat_IfHCOutBadOctets_lo; 5342 5343 sc->stat_IfHCInUcastPkts = 5344 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 5345 (u64) stats->stat_IfHCInUcastPkts_lo; 5346 5347 sc->stat_IfHCInMulticastPkts = 5348 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 5349 (u64) stats->stat_IfHCInMulticastPkts_lo; 5350 5351 sc->stat_IfHCInBroadcastPkts = 5352 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5353 (u64) stats->stat_IfHCInBroadcastPkts_lo; 5354 5355 sc->stat_IfHCOutUcastPkts = 5356 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 5357 (u64) stats->stat_IfHCOutUcastPkts_lo; 5358 5359 sc->stat_IfHCOutMulticastPkts = 5360 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5361 (u64) stats->stat_IfHCOutMulticastPkts_lo; 5362 5363 sc->stat_IfHCOutBroadcastPkts = 5364 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5365 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 5366 5367 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5368 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5369 5370 sc->stat_Dot3StatsCarrierSenseErrors = 5371 stats->stat_Dot3StatsCarrierSenseErrors; 5372 5373 sc->stat_Dot3StatsFCSErrors = 5374 stats->stat_Dot3StatsFCSErrors; 5375 5376 sc->stat_Dot3StatsAlignmentErrors = 5377 stats->stat_Dot3StatsAlignmentErrors; 5378 5379 sc->stat_Dot3StatsSingleCollisionFrames = 5380 stats->stat_Dot3StatsSingleCollisionFrames; 5381 5382 sc->stat_Dot3StatsMultipleCollisionFrames = 5383 stats->stat_Dot3StatsMultipleCollisionFrames; 5384 5385 sc->stat_Dot3StatsDeferredTransmissions = 5386 stats->stat_Dot3StatsDeferredTransmissions; 5387 5388 sc->stat_Dot3StatsExcessiveCollisions = 5389 stats->stat_Dot3StatsExcessiveCollisions; 5390 5391 sc->stat_Dot3StatsLateCollisions = 5392 stats->stat_Dot3StatsLateCollisions; 5393 5394 sc->stat_EtherStatsCollisions = 5395 stats->stat_EtherStatsCollisions; 5396 5397 sc->stat_EtherStatsFragments = 5398 stats->stat_EtherStatsFragments; 5399 5400 sc->stat_EtherStatsJabbers = 5401 stats->stat_EtherStatsJabbers; 5402 5403 sc->stat_EtherStatsUndersizePkts = 5404 stats->stat_EtherStatsUndersizePkts; 5405 5406 sc->stat_EtherStatsOverrsizePkts = 5407 stats->stat_EtherStatsOverrsizePkts; 5408 5409 sc->stat_EtherStatsPktsRx64Octets = 5410 stats->stat_EtherStatsPktsRx64Octets; 5411 5412 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5413 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5414 5415 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5416 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5417 5418 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5419 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5420 5421 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5422 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5423 5424 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5425 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5426 5427 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5428 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5429 5430 sc->stat_EtherStatsPktsTx64Octets = 5431 stats->stat_EtherStatsPktsTx64Octets; 5432 5433 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5434 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5435 5436 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5437 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5438 5439 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5440 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5441 5442 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5443 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5444 5445 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5446 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5447 5448 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5449 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5450 5451 sc->stat_XonPauseFramesReceived = 5452 stats->stat_XonPauseFramesReceived; 5453 5454 sc->stat_XoffPauseFramesReceived = 5455 stats->stat_XoffPauseFramesReceived; 5456 5457 sc->stat_OutXonSent = 5458 stats->stat_OutXonSent; 5459 5460 sc->stat_OutXoffSent = 5461 stats->stat_OutXoffSent; 5462 5463 sc->stat_FlowControlDone = 5464 stats->stat_FlowControlDone; 5465 5466 sc->stat_MacControlFramesReceived = 5467 stats->stat_MacControlFramesReceived; 5468 5469 sc->stat_XoffStateEntered = 5470 stats->stat_XoffStateEntered; 5471 5472 sc->stat_IfInFramesL2FilterDiscards = 5473 stats->stat_IfInFramesL2FilterDiscards; 5474 5475 sc->stat_IfInRuleCheckerDiscards = 5476 stats->stat_IfInRuleCheckerDiscards; 5477 5478 sc->stat_IfInFTQDiscards = 5479 stats->stat_IfInFTQDiscards; 5480 5481 sc->stat_IfInMBUFDiscards = 5482 stats->stat_IfInMBUFDiscards; 5483 5484 sc->stat_IfInRuleCheckerP4Hit = 5485 stats->stat_IfInRuleCheckerP4Hit; 5486 5487 sc->stat_CatchupInRuleCheckerDiscards = 5488 stats->stat_CatchupInRuleCheckerDiscards; 5489 5490 sc->stat_CatchupInFTQDiscards = 5491 stats->stat_CatchupInFTQDiscards; 5492 5493 sc->stat_CatchupInMBUFDiscards = 5494 stats->stat_CatchupInMBUFDiscards; 5495 5496 sc->stat_CatchupInRuleCheckerP4Hit = 5497 stats->stat_CatchupInRuleCheckerP4Hit; 5498 5499 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __FUNCTION__); 5500 } 5501 5502 5503 static void 5504 bce_tick_locked(struct bce_softc *sc) 5505 { 5506 struct mii_data *mii = NULL; 5507 struct ifnet *ifp; 5508 u32 msg; 5509 5510 ifp = sc->bce_ifp; 5511 5512 BCE_LOCK_ASSERT(sc); 5513 5514 /* Tell the firmware that the driver is still running. */ 5515 #ifdef BCE_DEBUG 5516 msg = (u32) BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE; 5517 #else 5518 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 5519 #endif 5520 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg); 5521 5522 /* Update the statistics from the hardware statistics block. */ 5523 bce_stats_update(sc); 5524 5525 /* Schedule the next tick. */ 5526 callout_reset( 5527 &sc->bce_stat_ch, /* callout */ 5528 hz, /* ticks */ 5529 bce_tick, /* function */ 5530 sc); /* function argument */ 5531 5532 /* If link is up already up then we're done. */ 5533 if (sc->bce_link) 5534 goto bce_tick_locked_exit; 5535 5536 /* DRC - ToDo: Add SerDes support and check SerDes link here. */ 5537 5538 mii = device_get_softc(sc->bce_miibus); 5539 mii_tick(mii); 5540 5541 /* Check if the link has come up. */ 5542 if (!sc->bce_link && mii->mii_media_status & IFM_ACTIVE && 5543 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5544 sc->bce_link++; 5545 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 5546 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) && 5547 bootverbose) 5548 BCE_PRINTF(sc, "Gigabit link up\n"); 5549 /* Now that link is up, handle any outstanding TX traffic. */ 5550 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5551 bce_start_locked(ifp); 5552 } 5553 5554 bce_tick_locked_exit: 5555 return; 5556 } 5557 5558 5559 static void 5560 bce_tick(void *xsc) 5561 { 5562 struct bce_softc *sc; 5563 5564 sc = xsc; 5565 5566 BCE_LOCK(sc); 5567 bce_tick_locked(sc); 5568 BCE_UNLOCK(sc); 5569 } 5570 5571 5572 #ifdef BCE_DEBUG 5573 /****************************************************************************/ 5574 /* Allows the driver state to be dumped through the sysctl interface. */ 5575 /* */ 5576 /* Returns: */ 5577 /* 0 for success, positive value for failure. */ 5578 /****************************************************************************/ 5579 static int 5580 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 5581 { 5582 int error; 5583 int result; 5584 struct bce_softc *sc; 5585 5586 result = -1; 5587 error = sysctl_handle_int(oidp, &result, 0, req); 5588 5589 if (error || !req->newptr) 5590 return (error); 5591 5592 if (result == 1) { 5593 sc = (struct bce_softc *)arg1; 5594 bce_dump_driver_state(sc); 5595 } 5596 5597 return error; 5598 } 5599 5600 5601 /****************************************************************************/ 5602 /* Allows the hardware state to be dumped through the sysctl interface. */ 5603 /* */ 5604 /* Returns: */ 5605 /* 0 for success, positive value for failure. */ 5606 /****************************************************************************/ 5607 static int 5608 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 5609 { 5610 int error; 5611 int result; 5612 struct bce_softc *sc; 5613 5614 result = -1; 5615 error = sysctl_handle_int(oidp, &result, 0, req); 5616 5617 if (error || !req->newptr) 5618 return (error); 5619 5620 if (result == 1) { 5621 sc = (struct bce_softc *)arg1; 5622 bce_dump_hw_state(sc); 5623 } 5624 5625 return error; 5626 } 5627 5628 5629 /****************************************************************************/ 5630 /* */ 5631 /* */ 5632 /* Returns: */ 5633 /* 0 for success, positive value for failure. */ 5634 /****************************************************************************/ 5635 static int 5636 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS) 5637 { 5638 int error; 5639 int result; 5640 struct bce_softc *sc; 5641 5642 result = -1; 5643 error = sysctl_handle_int(oidp, &result, 0, req); 5644 5645 if (error || !req->newptr) 5646 return (error); 5647 5648 if (result == 1) { 5649 sc = (struct bce_softc *)arg1; 5650 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 5651 } 5652 5653 return error; 5654 } 5655 5656 5657 /****************************************************************************/ 5658 /* */ 5659 /* */ 5660 /* Returns: */ 5661 /* 0 for success, positive value for failure. */ 5662 /****************************************************************************/ 5663 static int 5664 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 5665 { 5666 int error; 5667 int result; 5668 struct bce_softc *sc; 5669 5670 result = -1; 5671 error = sysctl_handle_int(oidp, &result, 0, req); 5672 5673 if (error || !req->newptr) 5674 return (error); 5675 5676 if (result == 1) { 5677 sc = (struct bce_softc *)arg1; 5678 bce_breakpoint(sc); 5679 } 5680 5681 return error; 5682 } 5683 #endif 5684 5685 5686 /****************************************************************************/ 5687 /* Adds any sysctl parameters for tuning or debugging purposes. */ 5688 /* */ 5689 /* Returns: */ 5690 /* 0 for success, positive value for failure. */ 5691 /****************************************************************************/ 5692 static void 5693 bce_add_sysctls(struct bce_softc *sc) 5694 { 5695 struct sysctl_ctx_list *ctx; 5696 struct sysctl_oid_list *children; 5697 5698 ctx = device_get_sysctl_ctx(sc->bce_dev); 5699 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 5700 5701 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, 5702 "driver_version", 5703 CTLFLAG_RD, &bce_driver_version, 5704 0, "bce driver version"); 5705 5706 #ifdef BCE_DEBUG 5707 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5708 "rx_low_watermark", 5709 CTLFLAG_RD, &sc->rx_low_watermark, 5710 0, "Lowest level of free rx_bd's"); 5711 5712 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5713 "tx_hi_watermark", 5714 CTLFLAG_RD, &sc->tx_hi_watermark, 5715 0, "Highest level of used tx_bd's"); 5716 5717 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5718 "l2fhdr_status_errors", 5719 CTLFLAG_RD, &sc->l2fhdr_status_errors, 5720 0, "l2_fhdr status errors"); 5721 5722 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5723 "unexpected_attentions", 5724 CTLFLAG_RD, &sc->unexpected_attentions, 5725 0, "unexpected attentions"); 5726 5727 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5728 "lost_status_block_updates", 5729 CTLFLAG_RD, &sc->lost_status_block_updates, 5730 0, "lost status block updates"); 5731 5732 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 5733 "mbuf_alloc_failed", 5734 CTLFLAG_RD, &sc->mbuf_alloc_failed, 5735 0, "mbuf cluster allocation failures"); 5736 #endif 5737 5738 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5739 "stat_IfHcInOctets", 5740 CTLFLAG_RD, &sc->stat_IfHCInOctets, 5741 "Bytes received"); 5742 5743 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5744 "stat_IfHCInBadOctets", 5745 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 5746 "Bad bytes received"); 5747 5748 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5749 "stat_IfHCOutOctets", 5750 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 5751 "Bytes sent"); 5752 5753 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5754 "stat_IfHCOutBadOctets", 5755 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 5756 "Bad bytes sent"); 5757 5758 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5759 "stat_IfHCInUcastPkts", 5760 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 5761 "Unicast packets received"); 5762 5763 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5764 "stat_IfHCInMulticastPkts", 5765 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 5766 "Multicast packets received"); 5767 5768 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5769 "stat_IfHCInBroadcastPkts", 5770 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 5771 "Broadcast packets received"); 5772 5773 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5774 "stat_IfHCOutUcastPkts", 5775 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 5776 "Unicast packets sent"); 5777 5778 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5779 "stat_IfHCOutMulticastPkts", 5780 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 5781 "Multicast packets sent"); 5782 5783 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 5784 "stat_IfHCOutBroadcastPkts", 5785 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 5786 "Broadcast packets sent"); 5787 5788 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5789 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 5790 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 5791 0, "Internal MAC transmit errors"); 5792 5793 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5794 "stat_Dot3StatsCarrierSenseErrors", 5795 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 5796 0, "Carrier sense errors"); 5797 5798 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5799 "stat_Dot3StatsFCSErrors", 5800 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 5801 0, "Frame check sequence errors"); 5802 5803 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5804 "stat_Dot3StatsAlignmentErrors", 5805 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 5806 0, "Alignment errors"); 5807 5808 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5809 "stat_Dot3StatsSingleCollisionFrames", 5810 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 5811 0, "Single Collision Frames"); 5812 5813 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5814 "stat_Dot3StatsMultipleCollisionFrames", 5815 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 5816 0, "Multiple Collision Frames"); 5817 5818 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5819 "stat_Dot3StatsDeferredTransmissions", 5820 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 5821 0, "Deferred Transmissions"); 5822 5823 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5824 "stat_Dot3StatsExcessiveCollisions", 5825 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 5826 0, "Excessive Collisions"); 5827 5828 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5829 "stat_Dot3StatsLateCollisions", 5830 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 5831 0, "Late Collisions"); 5832 5833 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5834 "stat_EtherStatsCollisions", 5835 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 5836 0, "Collisions"); 5837 5838 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5839 "stat_EtherStatsFragments", 5840 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 5841 0, "Fragments"); 5842 5843 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5844 "stat_EtherStatsJabbers", 5845 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 5846 0, "Jabbers"); 5847 5848 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5849 "stat_EtherStatsUndersizePkts", 5850 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 5851 0, "Undersize packets"); 5852 5853 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5854 "stat_EtherStatsOverrsizePkts", 5855 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts, 5856 0, "stat_EtherStatsOverrsizePkts"); 5857 5858 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5859 "stat_EtherStatsPktsRx64Octets", 5860 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 5861 0, "Bytes received in 64 byte packets"); 5862 5863 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5864 "stat_EtherStatsPktsRx65Octetsto127Octets", 5865 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 5866 0, "Bytes received in 65 to 127 byte packets"); 5867 5868 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5869 "stat_EtherStatsPktsRx128Octetsto255Octets", 5870 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 5871 0, "Bytes received in 128 to 255 byte packets"); 5872 5873 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5874 "stat_EtherStatsPktsRx256Octetsto511Octets", 5875 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 5876 0, "Bytes received in 256 to 511 byte packets"); 5877 5878 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5879 "stat_EtherStatsPktsRx512Octetsto1023Octets", 5880 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 5881 0, "Bytes received in 512 to 1023 byte packets"); 5882 5883 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5884 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 5885 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 5886 0, "Bytes received in 1024 t0 1522 byte packets"); 5887 5888 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5889 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 5890 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 5891 0, "Bytes received in 1523 to 9022 byte packets"); 5892 5893 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5894 "stat_EtherStatsPktsTx64Octets", 5895 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 5896 0, "Bytes sent in 64 byte packets"); 5897 5898 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5899 "stat_EtherStatsPktsTx65Octetsto127Octets", 5900 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 5901 0, "Bytes sent in 65 to 127 byte packets"); 5902 5903 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5904 "stat_EtherStatsPktsTx128Octetsto255Octets", 5905 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 5906 0, "Bytes sent in 128 to 255 byte packets"); 5907 5908 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5909 "stat_EtherStatsPktsTx256Octetsto511Octets", 5910 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 5911 0, "Bytes sent in 256 to 511 byte packets"); 5912 5913 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5914 "stat_EtherStatsPktsTx512Octetsto1023Octets", 5915 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 5916 0, "Bytes sent in 512 to 1023 byte packets"); 5917 5918 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5919 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 5920 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 5921 0, "Bytes sent in 1024 to 1522 byte packets"); 5922 5923 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5924 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 5925 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 5926 0, "Bytes sent in 1523 to 9022 byte packets"); 5927 5928 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5929 "stat_XonPauseFramesReceived", 5930 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 5931 0, "XON pause frames receved"); 5932 5933 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5934 "stat_XoffPauseFramesReceived", 5935 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 5936 0, "XOFF pause frames received"); 5937 5938 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5939 "stat_OutXonSent", 5940 CTLFLAG_RD, &sc->stat_OutXonSent, 5941 0, "XON pause frames sent"); 5942 5943 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5944 "stat_OutXoffSent", 5945 CTLFLAG_RD, &sc->stat_OutXoffSent, 5946 0, "XOFF pause frames sent"); 5947 5948 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5949 "stat_FlowControlDone", 5950 CTLFLAG_RD, &sc->stat_FlowControlDone, 5951 0, "Flow control done"); 5952 5953 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5954 "stat_MacControlFramesReceived", 5955 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 5956 0, "MAC control frames received"); 5957 5958 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5959 "stat_XoffStateEntered", 5960 CTLFLAG_RD, &sc->stat_XoffStateEntered, 5961 0, "XOFF state entered"); 5962 5963 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5964 "stat_IfInFramesL2FilterDiscards", 5965 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 5966 0, "Received L2 packets discarded"); 5967 5968 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5969 "stat_IfInRuleCheckerDiscards", 5970 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 5971 0, "Received packets discarded by rule"); 5972 5973 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5974 "stat_IfInFTQDiscards", 5975 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 5976 0, "Received packet FTQ discards"); 5977 5978 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5979 "stat_IfInMBUFDiscards", 5980 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 5981 0, "Received packets discarded due to lack of controller buffer memory"); 5982 5983 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5984 "stat_IfInRuleCheckerP4Hit", 5985 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 5986 0, "Received packets rule checker hits"); 5987 5988 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5989 "stat_CatchupInRuleCheckerDiscards", 5990 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 5991 0, "Received packets discarded in Catchup path"); 5992 5993 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5994 "stat_CatchupInFTQDiscards", 5995 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 5996 0, "Received packets discarded in FTQ in Catchup path"); 5997 5998 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 5999 "stat_CatchupInMBUFDiscards", 6000 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 6001 0, "Received packets discarded in controller buffer memory in Catchup path"); 6002 6003 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6004 "stat_CatchupInRuleCheckerP4Hit", 6005 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 6006 0, "Received packets rule checker hits in Catchup path"); 6007 6008 #ifdef BCE_DEBUG 6009 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6010 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 6011 (void *)sc, 0, 6012 bce_sysctl_driver_state, "I", "Drive state information"); 6013 6014 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6015 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 6016 (void *)sc, 0, 6017 bce_sysctl_hw_state, "I", "Hardware state information"); 6018 6019 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6020 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW, 6021 (void *)sc, 0, 6022 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain"); 6023 6024 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6025 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 6026 (void *)sc, 0, 6027 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 6028 #endif 6029 6030 } 6031 6032 6033 /****************************************************************************/ 6034 /* BCE Debug Routines */ 6035 /****************************************************************************/ 6036 #ifdef BCE_DEBUG 6037 6038 /****************************************************************************/ 6039 /* Prints out information about an mbuf. */ 6040 /* */ 6041 /* Returns: */ 6042 /* Nothing. */ 6043 /****************************************************************************/ 6044 static void 6045 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 6046 { 6047 u32 val_hi, val_lo; 6048 struct mbuf *mp = m; 6049 6050 if (m == NULL) { 6051 /* Index out of range. */ 6052 printf("mbuf ptr is null!\n"); 6053 return; 6054 } 6055 6056 while (mp) { 6057 val_hi = BCE_ADDR_HI(mp); 6058 val_lo = BCE_ADDR_LO(mp); 6059 BCE_PRINTF(sc, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, m_flags = ", 6060 val_hi, val_lo, mp->m_len); 6061 6062 if (mp->m_flags & M_EXT) 6063 printf("M_EXT "); 6064 if (mp->m_flags & M_PKTHDR) 6065 printf("M_PKTHDR "); 6066 printf("\n"); 6067 6068 if (mp->m_flags & M_EXT) { 6069 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf); 6070 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf); 6071 BCE_PRINTF(sc, "- m_ext: vaddr = 0x%08X:%08X, ext_size = 0x%04X\n", 6072 val_hi, val_lo, mp->m_ext.ext_size); 6073 } 6074 6075 mp = mp->m_next; 6076 } 6077 6078 6079 } 6080 6081 6082 /****************************************************************************/ 6083 /* Prints out the mbufs in the TX mbuf chain. */ 6084 /* */ 6085 /* Returns: */ 6086 /* Nothing. */ 6087 /****************************************************************************/ 6088 static void 6089 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6090 { 6091 struct mbuf *m; 6092 6093 BCE_PRINTF(sc, 6094 "----------------------------" 6095 " tx mbuf data " 6096 "----------------------------\n"); 6097 6098 for (int i = 0; i < count; i++) { 6099 m = sc->tx_mbuf_ptr[chain_prod]; 6100 BCE_PRINTF(sc, "txmbuf[%d]\n", chain_prod); 6101 bce_dump_mbuf(sc, m); 6102 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 6103 } 6104 6105 BCE_PRINTF(sc, 6106 "----------------------------" 6107 "----------------" 6108 "----------------------------\n"); 6109 } 6110 6111 6112 /* 6113 * This routine prints the RX mbuf chain. 6114 */ 6115 static void 6116 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6117 { 6118 struct mbuf *m; 6119 6120 BCE_PRINTF(sc, 6121 "----------------------------" 6122 " rx mbuf data " 6123 "----------------------------\n"); 6124 6125 for (int i = 0; i < count; i++) { 6126 m = sc->rx_mbuf_ptr[chain_prod]; 6127 BCE_PRINTF(sc, "rxmbuf[0x%04X]\n", chain_prod); 6128 bce_dump_mbuf(sc, m); 6129 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6130 } 6131 6132 6133 BCE_PRINTF(sc, 6134 "----------------------------" 6135 "----------------" 6136 "----------------------------\n"); 6137 } 6138 6139 6140 static void 6141 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 6142 { 6143 if (idx > MAX_TX_BD) 6144 /* Index out of range. */ 6145 BCE_PRINTF(sc, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6146 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6147 /* TX Chain page pointer. */ 6148 BCE_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6149 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo); 6150 else 6151 /* Normal tx_bd entry. */ 6152 BCE_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6153 "flags = 0x%08X\n", idx, 6154 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6155 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag_flags); 6156 } 6157 6158 6159 static void 6160 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 6161 { 6162 if (idx > MAX_RX_BD) 6163 /* Index out of range. */ 6164 BCE_PRINTF(sc, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6165 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6166 /* TX Chain page pointer. */ 6167 BCE_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6168 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo); 6169 else 6170 /* Normal tx_bd entry. */ 6171 BCE_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6172 "flags = 0x%08X\n", idx, 6173 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6174 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6175 } 6176 6177 6178 static void 6179 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6180 { 6181 BCE_PRINTF(sc, "l2_fhdr[0x%04X]: status = 0x%08X, " 6182 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6183 "tcp_udp_xsum = 0x%04X\n", idx, 6184 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6185 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6186 l2fhdr->l2_fhdr_tcp_udp_xsum); 6187 } 6188 6189 6190 /* 6191 * This routine prints the TX chain. 6192 */ 6193 static void 6194 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count) 6195 { 6196 struct tx_bd *txbd; 6197 6198 /* First some info about the tx_bd chain structure. */ 6199 BCE_PRINTF(sc, 6200 "----------------------------" 6201 " tx_bd chain " 6202 "----------------------------\n"); 6203 6204 BCE_PRINTF(sc, "page size = 0x%08X, tx chain pages = 0x%08X\n", 6205 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 6206 6207 BCE_PRINTF(sc, "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6208 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 6209 6210 BCE_PRINTF(sc, "total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 6211 6212 BCE_PRINTF(sc, "" 6213 "-----------------------------" 6214 " tx_bd data " 6215 "-----------------------------\n"); 6216 6217 /* Now print out the tx_bd's themselves. */ 6218 for (int i = 0; i < count; i++) { 6219 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6220 bce_dump_txbd(sc, tx_prod, txbd); 6221 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6222 } 6223 6224 BCE_PRINTF(sc, 6225 "-----------------------------" 6226 "--------------" 6227 "-----------------------------\n"); 6228 } 6229 6230 6231 /* 6232 * This routine prints the RX chain. 6233 */ 6234 static void 6235 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count) 6236 { 6237 struct rx_bd *rxbd; 6238 6239 /* First some info about the tx_bd chain structure. */ 6240 BCE_PRINTF(sc, 6241 "----------------------------" 6242 " rx_bd chain " 6243 "----------------------------\n"); 6244 6245 BCE_PRINTF(sc, "----- RX_BD Chain -----\n"); 6246 6247 BCE_PRINTF(sc, "page size = 0x%08X, rx chain pages = 0x%08X\n", 6248 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 6249 6250 BCE_PRINTF(sc, "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6251 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 6252 6253 BCE_PRINTF(sc, "total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 6254 6255 BCE_PRINTF(sc, 6256 "----------------------------" 6257 " rx_bd data " 6258 "----------------------------\n"); 6259 6260 /* Now print out the rx_bd's themselves. */ 6261 for (int i = 0; i < count; i++) { 6262 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6263 bce_dump_rxbd(sc, rx_prod, rxbd); 6264 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6265 } 6266 6267 BCE_PRINTF(sc, 6268 "----------------------------" 6269 "--------------" 6270 "----------------------------\n"); 6271 } 6272 6273 6274 /* 6275 * This routine prints the status block. 6276 */ 6277 static void 6278 bce_dump_status_block(struct bce_softc *sc) 6279 { 6280 struct status_block *sblk; 6281 6282 sblk = sc->status_block; 6283 6284 BCE_PRINTF(sc, "----------------------------- Status Block " 6285 "-----------------------------\n"); 6286 6287 BCE_PRINTF(sc, "attn_bits = 0x%08X, attn_bits_ack = 0x%08X, index = 0x%04X\n", 6288 sblk->status_attn_bits, sblk->status_attn_bits_ack, 6289 sblk->status_idx); 6290 6291 BCE_PRINTF(sc, "rx_cons0 = 0x%08X, tx_cons0 = 0x%08X\n", 6292 sblk->status_rx_quick_consumer_index0, 6293 sblk->status_tx_quick_consumer_index0); 6294 6295 BCE_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); 6296 6297 /* Theses indices are not used for normal L2 drivers. */ 6298 if (sblk->status_rx_quick_consumer_index1 || 6299 sblk->status_tx_quick_consumer_index1) 6300 BCE_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", 6301 sblk->status_rx_quick_consumer_index1, 6302 sblk->status_tx_quick_consumer_index1); 6303 6304 if (sblk->status_rx_quick_consumer_index2 || 6305 sblk->status_tx_quick_consumer_index2) 6306 BCE_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", 6307 sblk->status_rx_quick_consumer_index2, 6308 sblk->status_tx_quick_consumer_index2); 6309 6310 if (sblk->status_rx_quick_consumer_index3 || 6311 sblk->status_tx_quick_consumer_index3) 6312 BCE_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", 6313 sblk->status_rx_quick_consumer_index3, 6314 sblk->status_tx_quick_consumer_index3); 6315 6316 if (sblk->status_rx_quick_consumer_index4 || 6317 sblk->status_rx_quick_consumer_index5) 6318 BCE_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6319 sblk->status_rx_quick_consumer_index4, 6320 sblk->status_rx_quick_consumer_index5); 6321 6322 if (sblk->status_rx_quick_consumer_index6 || 6323 sblk->status_rx_quick_consumer_index7) 6324 BCE_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6325 sblk->status_rx_quick_consumer_index6, 6326 sblk->status_rx_quick_consumer_index7); 6327 6328 if (sblk->status_rx_quick_consumer_index8 || 6329 sblk->status_rx_quick_consumer_index9) 6330 BCE_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6331 sblk->status_rx_quick_consumer_index8, 6332 sblk->status_rx_quick_consumer_index9); 6333 6334 if (sblk->status_rx_quick_consumer_index10 || 6335 sblk->status_rx_quick_consumer_index11) 6336 BCE_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6337 sblk->status_rx_quick_consumer_index10, 6338 sblk->status_rx_quick_consumer_index11); 6339 6340 if (sblk->status_rx_quick_consumer_index12 || 6341 sblk->status_rx_quick_consumer_index13) 6342 BCE_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6343 sblk->status_rx_quick_consumer_index12, 6344 sblk->status_rx_quick_consumer_index13); 6345 6346 if (sblk->status_rx_quick_consumer_index14 || 6347 sblk->status_rx_quick_consumer_index15) 6348 BCE_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6349 sblk->status_rx_quick_consumer_index14, 6350 sblk->status_rx_quick_consumer_index15); 6351 6352 if (sblk->status_completion_producer_index || 6353 sblk->status_cmd_consumer_index) 6354 BCE_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6355 sblk->status_completion_producer_index, 6356 sblk->status_cmd_consumer_index); 6357 6358 BCE_PRINTF(sc, "-------------------------------------------" 6359 "-----------------------------\n"); 6360 } 6361 6362 6363 /* 6364 * This routine prints the statistics block. 6365 */ 6366 static void 6367 bce_dump_stats_block(struct bce_softc *sc) 6368 { 6369 struct statistics_block *sblk; 6370 6371 sblk = sc->stats_block; 6372 6373 BCE_PRINTF(sc, "" 6374 "-----------------------------" 6375 " Stats Block " 6376 "-----------------------------\n"); 6377 6378 BCE_PRINTF(sc, "IfHcInOctets = 0x%08X:%08X, " 6379 "IfHcInBadOctets = 0x%08X:%08X\n", 6380 sblk->stat_IfHCInOctets_hi, sblk->stat_IfHCInOctets_lo, 6381 sblk->stat_IfHCInBadOctets_hi, sblk->stat_IfHCInBadOctets_lo); 6382 6383 BCE_PRINTF(sc, "IfHcOutOctets = 0x%08X:%08X, " 6384 "IfHcOutBadOctets = 0x%08X:%08X\n", 6385 sblk->stat_IfHCOutOctets_hi, sblk->stat_IfHCOutOctets_lo, 6386 sblk->stat_IfHCOutBadOctets_hi, sblk->stat_IfHCOutBadOctets_lo); 6387 6388 BCE_PRINTF(sc, "IfHcInUcastPkts = 0x%08X:%08X, " 6389 "IfHcInMulticastPkts = 0x%08X:%08X\n", 6390 sblk->stat_IfHCInUcastPkts_hi, sblk->stat_IfHCInUcastPkts_lo, 6391 sblk->stat_IfHCInMulticastPkts_hi, sblk->stat_IfHCInMulticastPkts_lo); 6392 6393 BCE_PRINTF(sc, "IfHcInBroadcastPkts = 0x%08X:%08X, " 6394 "IfHcOutUcastPkts = 0x%08X:%08X\n", 6395 sblk->stat_IfHCInBroadcastPkts_hi, sblk->stat_IfHCInBroadcastPkts_lo, 6396 sblk->stat_IfHCOutUcastPkts_hi, sblk->stat_IfHCOutUcastPkts_lo); 6397 6398 BCE_PRINTF(sc, "IfHcOutMulticastPkts = 0x%08X:%08X, IfHcOutBroadcastPkts = 0x%08X:%08X\n", 6399 sblk->stat_IfHCOutMulticastPkts_hi, sblk->stat_IfHCOutMulticastPkts_lo, 6400 sblk->stat_IfHCOutBroadcastPkts_hi, sblk->stat_IfHCOutBroadcastPkts_lo); 6401 6402 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 6403 BCE_PRINTF(sc, "0x%08X : " 6404 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 6405 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 6406 6407 if (sblk->stat_Dot3StatsCarrierSenseErrors) 6408 BCE_PRINTF(sc, "0x%08X : Dot3StatsCarrierSenseErrors\n", 6409 sblk->stat_Dot3StatsCarrierSenseErrors); 6410 6411 if (sblk->stat_Dot3StatsFCSErrors) 6412 BCE_PRINTF(sc, "0x%08X : Dot3StatsFCSErrors\n", 6413 sblk->stat_Dot3StatsFCSErrors); 6414 6415 if (sblk->stat_Dot3StatsAlignmentErrors) 6416 BCE_PRINTF(sc, "0x%08X : Dot3StatsAlignmentErrors\n", 6417 sblk->stat_Dot3StatsAlignmentErrors); 6418 6419 if (sblk->stat_Dot3StatsSingleCollisionFrames) 6420 BCE_PRINTF(sc, "0x%08X : Dot3StatsSingleCollisionFrames\n", 6421 sblk->stat_Dot3StatsSingleCollisionFrames); 6422 6423 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 6424 BCE_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", 6425 sblk->stat_Dot3StatsMultipleCollisionFrames); 6426 6427 if (sblk->stat_Dot3StatsDeferredTransmissions) 6428 BCE_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", 6429 sblk->stat_Dot3StatsDeferredTransmissions); 6430 6431 if (sblk->stat_Dot3StatsExcessiveCollisions) 6432 BCE_PRINTF(sc, "0x%08X : Dot3StatsExcessiveCollisions\n", 6433 sblk->stat_Dot3StatsExcessiveCollisions); 6434 6435 if (sblk->stat_Dot3StatsLateCollisions) 6436 BCE_PRINTF(sc, "0x%08X : Dot3StatsLateCollisions\n", 6437 sblk->stat_Dot3StatsLateCollisions); 6438 6439 if (sblk->stat_EtherStatsCollisions) 6440 BCE_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", 6441 sblk->stat_EtherStatsCollisions); 6442 6443 if (sblk->stat_EtherStatsFragments) 6444 BCE_PRINTF(sc, "0x%08X : EtherStatsFragments\n", 6445 sblk->stat_EtherStatsFragments); 6446 6447 if (sblk->stat_EtherStatsJabbers) 6448 BCE_PRINTF(sc, "0x%08X : EtherStatsJabbers\n", 6449 sblk->stat_EtherStatsJabbers); 6450 6451 if (sblk->stat_EtherStatsUndersizePkts) 6452 BCE_PRINTF(sc, "0x%08X : EtherStatsUndersizePkts\n", 6453 sblk->stat_EtherStatsUndersizePkts); 6454 6455 if (sblk->stat_EtherStatsOverrsizePkts) 6456 BCE_PRINTF(sc, "0x%08X : EtherStatsOverrsizePkts\n", 6457 sblk->stat_EtherStatsOverrsizePkts); 6458 6459 if (sblk->stat_EtherStatsPktsRx64Octets) 6460 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx64Octets\n", 6461 sblk->stat_EtherStatsPktsRx64Octets); 6462 6463 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 6464 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 6465 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 6466 6467 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 6468 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx128Octetsto255Octets\n", 6469 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 6470 6471 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 6472 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx256Octetsto511Octets\n", 6473 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 6474 6475 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 6476 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx512Octetsto1023Octets\n", 6477 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 6478 6479 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 6480 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx1024Octetsto1522Octets\n", 6481 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 6482 6483 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 6484 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsRx1523Octetsto9022Octets\n", 6485 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 6486 6487 if (sblk->stat_EtherStatsPktsTx64Octets) 6488 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx64Octets\n", 6489 sblk->stat_EtherStatsPktsTx64Octets); 6490 6491 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 6492 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 6493 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 6494 6495 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 6496 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx128Octetsto255Octets\n", 6497 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 6498 6499 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 6500 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx256Octetsto511Octets\n", 6501 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 6502 6503 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 6504 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx512Octetsto1023Octets\n", 6505 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 6506 6507 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 6508 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx1024Octetsto1522Octets\n", 6509 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 6510 6511 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 6512 BCE_PRINTF(sc, "0x%08X : EtherStatsPktsTx1523Octetsto9022Octets\n", 6513 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 6514 6515 if (sblk->stat_XonPauseFramesReceived) 6516 BCE_PRINTF(sc, "0x%08X : XonPauseFramesReceived\n", 6517 sblk->stat_XonPauseFramesReceived); 6518 6519 if (sblk->stat_XoffPauseFramesReceived) 6520 BCE_PRINTF(sc, "0x%08X : XoffPauseFramesReceived\n", 6521 sblk->stat_XoffPauseFramesReceived); 6522 6523 if (sblk->stat_OutXonSent) 6524 BCE_PRINTF(sc, "0x%08X : OutXonSent\n", 6525 sblk->stat_OutXonSent); 6526 6527 if (sblk->stat_OutXoffSent) 6528 BCE_PRINTF(sc, "0x%08X : OutXoffSent\n", 6529 sblk->stat_OutXoffSent); 6530 6531 if (sblk->stat_FlowControlDone) 6532 BCE_PRINTF(sc, "0x%08X : FlowControlDone\n", 6533 sblk->stat_FlowControlDone); 6534 6535 if (sblk->stat_MacControlFramesReceived) 6536 BCE_PRINTF(sc, "0x%08X : MacControlFramesReceived\n", 6537 sblk->stat_MacControlFramesReceived); 6538 6539 if (sblk->stat_XoffStateEntered) 6540 BCE_PRINTF(sc, "0x%08X : XoffStateEntered\n", 6541 sblk->stat_XoffStateEntered); 6542 6543 if (sblk->stat_IfInFramesL2FilterDiscards) 6544 BCE_PRINTF(sc, "0x%08X : IfInFramesL2FilterDiscards\n", 6545 sblk->stat_IfInFramesL2FilterDiscards); 6546 6547 if (sblk->stat_IfInRuleCheckerDiscards) 6548 BCE_PRINTF(sc, "0x%08X : IfInRuleCheckerDiscards\n", 6549 sblk->stat_IfInRuleCheckerDiscards); 6550 6551 if (sblk->stat_IfInFTQDiscards) 6552 BCE_PRINTF(sc, "0x%08X : IfInFTQDiscards\n", 6553 sblk->stat_IfInFTQDiscards); 6554 6555 if (sblk->stat_IfInMBUFDiscards) 6556 BCE_PRINTF(sc, "0x%08X : IfInMBUFDiscards\n", 6557 sblk->stat_IfInMBUFDiscards); 6558 6559 if (sblk->stat_IfInRuleCheckerP4Hit) 6560 BCE_PRINTF(sc, "0x%08X : IfInRuleCheckerP4Hit\n", 6561 sblk->stat_IfInRuleCheckerP4Hit); 6562 6563 if (sblk->stat_CatchupInRuleCheckerDiscards) 6564 BCE_PRINTF(sc, "0x%08X : CatchupInRuleCheckerDiscards\n", 6565 sblk->stat_CatchupInRuleCheckerDiscards); 6566 6567 if (sblk->stat_CatchupInFTQDiscards) 6568 BCE_PRINTF(sc, "0x%08X : CatchupInFTQDiscards\n", 6569 sblk->stat_CatchupInFTQDiscards); 6570 6571 if (sblk->stat_CatchupInMBUFDiscards) 6572 BCE_PRINTF(sc, "0x%08X : CatchupInMBUFDiscards\n", 6573 sblk->stat_CatchupInMBUFDiscards); 6574 6575 if (sblk->stat_CatchupInRuleCheckerP4Hit) 6576 BCE_PRINTF(sc, "0x%08X : CatchupInRuleCheckerP4Hit\n", 6577 sblk->stat_CatchupInRuleCheckerP4Hit); 6578 6579 BCE_PRINTF(sc, 6580 "-----------------------------" 6581 "--------------" 6582 "-----------------------------\n"); 6583 } 6584 6585 6586 static void 6587 bce_dump_driver_state(struct bce_softc *sc) 6588 { 6589 u32 val_hi, val_lo; 6590 6591 BCE_PRINTF(sc, 6592 "-----------------------------" 6593 " Driver State " 6594 "-----------------------------\n"); 6595 6596 val_hi = BCE_ADDR_HI(sc); 6597 val_lo = BCE_ADDR_LO(sc); 6598 BCE_PRINTF(sc, "0x%08X:%08X - (sc) driver softc structure virtual address\n", 6599 val_hi, val_lo); 6600 6601 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 6602 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 6603 BCE_PRINTF(sc, "0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual address\n", 6604 val_hi, val_lo); 6605 6606 val_hi = BCE_ADDR_HI(sc->status_block); 6607 val_lo = BCE_ADDR_LO(sc->status_block); 6608 BCE_PRINTF(sc, "0x%08X:%08X - (sc->status_block) status block virtual address\n", 6609 val_hi, val_lo); 6610 6611 val_hi = BCE_ADDR_HI(sc->stats_block); 6612 val_lo = BCE_ADDR_LO(sc->stats_block); 6613 BCE_PRINTF(sc, "0x%08X:%08X - (sc->stats_block) statistics block virtual address\n", 6614 val_hi, val_lo); 6615 6616 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 6617 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 6618 BCE_PRINTF(sc, 6619 "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain virtual adddress\n", 6620 val_hi, val_lo); 6621 6622 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 6623 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 6624 BCE_PRINTF(sc, 6625 "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain virtual address\n", 6626 val_hi, val_lo); 6627 6628 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 6629 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 6630 BCE_PRINTF(sc, 6631 "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 6632 val_hi, val_lo); 6633 6634 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 6635 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 6636 BCE_PRINTF(sc, 6637 "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 6638 val_hi, val_lo); 6639 6640 BCE_PRINTF(sc, " 0x%08X - (sc->interrupts_generated) h/w intrs\n", 6641 sc->interrupts_generated); 6642 6643 BCE_PRINTF(sc, " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 6644 sc->rx_interrupts); 6645 6646 BCE_PRINTF(sc, " 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 6647 sc->tx_interrupts); 6648 6649 BCE_PRINTF(sc, " 0x%08X - (sc->last_status_idx) status block index\n", 6650 sc->last_status_idx); 6651 6652 BCE_PRINTF(sc, " 0x%08X - (sc->tx_prod) tx producer index\n", 6653 sc->tx_prod); 6654 6655 BCE_PRINTF(sc, " 0x%08X - (sc->tx_cons) tx consumer index\n", 6656 sc->tx_cons); 6657 6658 BCE_PRINTF(sc, " 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 6659 sc->tx_prod_bseq); 6660 6661 BCE_PRINTF(sc, " 0x%08X - (sc->rx_prod) rx producer index\n", 6662 sc->rx_prod); 6663 6664 BCE_PRINTF(sc, " 0x%08X - (sc->rx_cons) rx consumer index\n", 6665 sc->rx_cons); 6666 6667 BCE_PRINTF(sc, " 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 6668 sc->rx_prod_bseq); 6669 6670 BCE_PRINTF(sc, " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6671 sc->rx_mbuf_alloc); 6672 6673 BCE_PRINTF(sc, " 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 6674 sc->free_rx_bd); 6675 6676 BCE_PRINTF(sc, "0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 6677 sc->rx_low_watermark, (u32) USABLE_RX_BD); 6678 6679 BCE_PRINTF(sc, " 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 6680 sc->tx_mbuf_alloc); 6681 6682 BCE_PRINTF(sc, " 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 6683 sc->rx_mbuf_alloc); 6684 6685 BCE_PRINTF(sc, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 6686 sc->used_tx_bd); 6687 6688 BCE_PRINTF(sc, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 6689 sc->tx_hi_watermark, (u32) USABLE_TX_BD); 6690 6691 BCE_PRINTF(sc, " 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 6692 sc->mbuf_alloc_failed); 6693 6694 BCE_PRINTF(sc, 6695 "-----------------------------" 6696 "--------------" 6697 "-----------------------------\n"); 6698 } 6699 6700 6701 static void 6702 bce_dump_hw_state(struct bce_softc *sc) 6703 { 6704 u32 val1; 6705 6706 BCE_PRINTF(sc, 6707 "----------------------------" 6708 " Hardware State " 6709 "----------------------------\n"); 6710 6711 BCE_PRINTF(sc, "0x%08X : bootcode version\n", sc->bce_fw_ver); 6712 6713 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 6714 BCE_PRINTF(sc, "0x%08X : (0x%04X) misc_enable_status_bits\n", 6715 val1, BCE_MISC_ENABLE_STATUS_BITS); 6716 6717 val1 = REG_RD(sc, BCE_DMA_STATUS); 6718 BCE_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BCE_DMA_STATUS); 6719 6720 val1 = REG_RD(sc, BCE_CTX_STATUS); 6721 BCE_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS); 6722 6723 val1 = REG_RD(sc, BCE_EMAC_STATUS); 6724 BCE_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1, BCE_EMAC_STATUS); 6725 6726 val1 = REG_RD(sc, BCE_RPM_STATUS); 6727 BCE_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS); 6728 6729 val1 = REG_RD(sc, BCE_TBDR_STATUS); 6730 BCE_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1, BCE_TBDR_STATUS); 6731 6732 val1 = REG_RD(sc, BCE_TDMA_STATUS); 6733 BCE_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1, BCE_TDMA_STATUS); 6734 6735 val1 = REG_RD(sc, BCE_HC_STATUS); 6736 BCE_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BCE_HC_STATUS); 6737 6738 BCE_PRINTF(sc, 6739 "----------------------------" 6740 "----------------" 6741 "----------------------------\n"); 6742 6743 BCE_PRINTF(sc, 6744 "----------------------------" 6745 " Register Dump " 6746 "----------------------------\n"); 6747 6748 for (int i = 0x400; i < 0x8000; i += 0x10) 6749 BCE_PRINTF(sc, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 6750 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 6751 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 6752 6753 BCE_PRINTF(sc, 6754 "----------------------------" 6755 "----------------" 6756 "----------------------------\n"); 6757 } 6758 6759 6760 static void 6761 bce_breakpoint(struct bce_softc *sc) 6762 { 6763 6764 /* Unreachable code to shut the compiler up about unused functions. */ 6765 if (0) { 6766 bce_dump_txbd(sc, 0, NULL); 6767 bce_dump_rxbd(sc, 0, NULL); 6768 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 6769 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 6770 bce_dump_l2fhdr(sc, 0, NULL); 6771 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 6772 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 6773 bce_dump_status_block(sc); 6774 bce_dump_stats_block(sc); 6775 bce_dump_driver_state(sc); 6776 bce_dump_hw_state(sc); 6777 } 6778 6779 bce_dump_driver_state(sc); 6780 /* Print the important status block fields. */ 6781 bce_dump_status_block(sc); 6782 6783 /* Call the debugger. */ 6784 breakpoint(); 6785 6786 return; 6787 } 6788 #endif 6789