1 /*- 2 * Copyright (c) 2006-2009 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5716C C0 42 * 43 * The following controllers are not supported by this driver: 44 * BCM5706C A0, A1 (pre-production) 45 * BCM5706S A0, A1 (pre-production) 46 * BCM5708C A0, B0 (pre-production) 47 * BCM5708S A0, B0 (pre-production) 48 * BCM5709C A0 B0, B1, B2 (pre-production) 49 * BCM5709S A0, A1, B0, B1, B2, C0 (pre-production) 50 */ 51 52 #include "opt_bce.h" 53 54 #include <dev/bce/if_bcereg.h> 55 #include <dev/bce/if_bcefw.h> 56 57 /****************************************************************************/ 58 /* BCE Debug Options */ 59 /****************************************************************************/ 60 #ifdef BCE_DEBUG 61 u32 bce_debug = BCE_WARN; 62 63 /* 0 = Never */ 64 /* 1 = 1 in 2,147,483,648 */ 65 /* 256 = 1 in 8,388,608 */ 66 /* 2048 = 1 in 1,048,576 */ 67 /* 65536 = 1 in 32,768 */ 68 /* 1048576 = 1 in 2,048 */ 69 /* 268435456 = 1 in 8 */ 70 /* 536870912 = 1 in 4 */ 71 /* 1073741824 = 1 in 2 */ 72 73 /* Controls how often the l2_fhdr frame error check will fail. */ 74 int l2fhdr_error_sim_control = 0; 75 76 /* Controls how often the unexpected attention check will fail. */ 77 int unexpected_attention_sim_control = 0; 78 79 /* Controls how often to simulate an mbuf allocation failure. */ 80 int mbuf_alloc_failed_sim_control = 0; 81 82 /* Controls how often to simulate a DMA mapping failure. */ 83 int dma_map_addr_failed_sim_control = 0; 84 85 /* Controls how often to simulate a bootcode failure. */ 86 int bootcode_running_failure_sim_control = 0; 87 #endif 88 89 /****************************************************************************/ 90 /* BCE Build Time Options */ 91 /****************************************************************************/ 92 /* #define BCE_NVRAM_WRITE_SUPPORT 1 */ 93 94 95 /****************************************************************************/ 96 /* PCI Device ID Table */ 97 /* */ 98 /* Used by bce_probe() to identify the devices supported by this driver. */ 99 /****************************************************************************/ 100 #define BCE_DEVDESC_MAX 64 101 102 static struct bce_type bce_devs[] = { 103 /* BCM5706C Controllers and OEM boards. */ 104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 105 "HP NC370T Multifunction Gigabit Server Adapter" }, 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 107 "HP NC370i Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 109 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 110 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 111 "HP NC371i Multifunction Gigabit Server Adapter" }, 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 113 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 114 115 /* BCM5706S controllers and OEM boards. */ 116 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 117 "HP NC370F Multifunction Gigabit Server Adapter" }, 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 119 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 120 121 /* BCM5708C controllers and OEM boards. */ 122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 123 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 125 "HP NC373i Multifunction Gigabit Server Adapter" }, 126 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 127 "HP NC374m PCIe Multifunction Adapter" }, 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 129 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 130 131 /* BCM5708S controllers and OEM boards. */ 132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 133 "HP NC373m Multifunction Gigabit Server Adapter" }, 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 135 "HP NC373i Multifunction Gigabit Server Adapter" }, 136 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 137 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 139 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 140 141 /* BCM5709C controllers and OEM boards. */ 142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 143 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 145 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 147 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 148 149 /* BCM5709S controllers and OEM boards. */ 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 151 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 153 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 155 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 156 157 /* BCM5716 controllers and OEM boards. */ 158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 159 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 160 161 { 0, 0, 0, 0, NULL } 162 }; 163 164 165 /****************************************************************************/ 166 /* Supported Flash NVRAM device data. */ 167 /****************************************************************************/ 168 static struct flash_spec flash_table[] = 169 { 170 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 171 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 172 173 /* Slow EEPROM */ 174 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 175 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 176 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 177 "EEPROM - slow"}, 178 /* Expansion entry 0001 */ 179 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 180 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 181 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 182 "Entry 0001"}, 183 /* Saifun SA25F010 (non-buffered flash) */ 184 /* strap, cfg1, & write1 need updates */ 185 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 186 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 187 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 188 "Non-buffered flash (128kB)"}, 189 /* Saifun SA25F020 (non-buffered flash) */ 190 /* strap, cfg1, & write1 need updates */ 191 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 192 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 193 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 194 "Non-buffered flash (256kB)"}, 195 /* Expansion entry 0100 */ 196 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 197 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 198 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 199 "Entry 0100"}, 200 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 201 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 202 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 203 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 204 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 205 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 206 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 207 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 208 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 209 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 210 /* Saifun SA25F005 (non-buffered flash) */ 211 /* strap, cfg1, & write1 need updates */ 212 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 213 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 214 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 215 "Non-buffered flash (64kB)"}, 216 /* Fast EEPROM */ 217 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 218 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 219 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 220 "EEPROM - fast"}, 221 /* Expansion entry 1001 */ 222 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 225 "Entry 1001"}, 226 /* Expansion entry 1010 */ 227 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 230 "Entry 1010"}, 231 /* ATMEL AT45DB011B (buffered flash) */ 232 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 235 "Buffered flash (128kB)"}, 236 /* Expansion entry 1100 */ 237 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 240 "Entry 1100"}, 241 /* Expansion entry 1101 */ 242 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 243 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 244 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 245 "Entry 1101"}, 246 /* Ateml Expansion entry 1110 */ 247 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 248 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 249 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 250 "Entry 1110 (Atmel)"}, 251 /* ATMEL AT45DB021B (buffered flash) */ 252 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 253 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 254 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 255 "Buffered flash (256kB)"}, 256 }; 257 258 /* 259 * The BCM5709 controllers transparently handle the 260 * differences between Atmel 264 byte pages and all 261 * flash devices which use 256 byte pages, so no 262 * logical-to-physical mapping is required in the 263 * driver. 264 */ 265 static struct flash_spec flash_5709 = { 266 .flags = BCE_NV_BUFFERED, 267 .page_bits = BCM5709_FLASH_PAGE_BITS, 268 .page_size = BCM5709_FLASH_PAGE_SIZE, 269 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 270 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 271 .name = "5709/5716 buffered flash (256kB)", 272 }; 273 274 275 /****************************************************************************/ 276 /* FreeBSD device entry points. */ 277 /****************************************************************************/ 278 static int bce_probe (device_t); 279 static int bce_attach (device_t); 280 static int bce_detach (device_t); 281 static int bce_shutdown (device_t); 282 283 284 /****************************************************************************/ 285 /* BCE Debug Data Structure Dump Routines */ 286 /****************************************************************************/ 287 #ifdef BCE_DEBUG 288 static u32 bce_reg_rd (struct bce_softc *, u32); 289 static void bce_reg_wr (struct bce_softc *, u32, u32); 290 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 291 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 292 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 293 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 294 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 295 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 296 #ifdef ZERO_COPY_SOCKETS 297 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 298 #endif 299 static void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *); 300 static void bce_dump_rxbd (struct bce_softc *, int, struct rx_bd *); 301 #ifdef ZERO_COPY_SOCKETS 302 static void bce_dump_pgbd (struct bce_softc *, int, struct rx_bd *); 303 #endif 304 static void bce_dump_l2fhdr (struct bce_softc *, int, struct l2_fhdr *); 305 static void bce_dump_ctx (struct bce_softc *, u16); 306 static void bce_dump_ftqs (struct bce_softc *); 307 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 308 static void bce_dump_rx_chain (struct bce_softc *, u16, int); 309 #ifdef ZERO_COPY_SOCKETS 310 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 311 #endif 312 static void bce_dump_status_block (struct bce_softc *); 313 static void bce_dump_stats_block (struct bce_softc *); 314 static void bce_dump_driver_state (struct bce_softc *); 315 static void bce_dump_hw_state (struct bce_softc *); 316 static void bce_dump_mq_regs (struct bce_softc *); 317 static void bce_dump_bc_state (struct bce_softc *); 318 static void bce_dump_txp_state (struct bce_softc *, int); 319 static void bce_dump_rxp_state (struct bce_softc *, int); 320 static void bce_dump_tpat_state (struct bce_softc *, int); 321 static void bce_dump_cp_state (struct bce_softc *, int); 322 static void bce_dump_com_state (struct bce_softc *, int); 323 static void bce_breakpoint (struct bce_softc *); 324 #endif 325 326 327 /****************************************************************************/ 328 /* BCE Register/Memory Access Routines */ 329 /****************************************************************************/ 330 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 331 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 332 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 333 static int bce_miibus_read_reg (device_t, int, int); 334 static int bce_miibus_write_reg (device_t, int, int, int); 335 static void bce_miibus_statchg (device_t); 336 337 338 /****************************************************************************/ 339 /* BCE NVRAM Access Routines */ 340 /****************************************************************************/ 341 static int bce_acquire_nvram_lock (struct bce_softc *); 342 static int bce_release_nvram_lock (struct bce_softc *); 343 static void bce_enable_nvram_access (struct bce_softc *); 344 static void bce_disable_nvram_access(struct bce_softc *); 345 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 346 static int bce_init_nvram (struct bce_softc *); 347 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 348 static int bce_nvram_test (struct bce_softc *); 349 #ifdef BCE_NVRAM_WRITE_SUPPORT 350 static int bce_enable_nvram_write (struct bce_softc *); 351 static void bce_disable_nvram_write (struct bce_softc *); 352 static int bce_nvram_erase_page (struct bce_softc *, u32); 353 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 354 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 355 #endif 356 357 /****************************************************************************/ 358 /* */ 359 /****************************************************************************/ 360 static void bce_get_media (struct bce_softc *); 361 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 362 static int bce_dma_alloc (device_t); 363 static void bce_dma_free (struct bce_softc *); 364 static void bce_release_resources (struct bce_softc *); 365 366 /****************************************************************************/ 367 /* BCE Firmware Synchronization and Load */ 368 /****************************************************************************/ 369 static int bce_fw_sync (struct bce_softc *, u32); 370 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 371 static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *); 372 static void bce_init_rxp_cpu (struct bce_softc *); 373 static void bce_init_txp_cpu (struct bce_softc *); 374 static void bce_init_tpat_cpu (struct bce_softc *); 375 static void bce_init_cp_cpu (struct bce_softc *); 376 static void bce_init_com_cpu (struct bce_softc *); 377 static void bce_init_cpus (struct bce_softc *); 378 379 static void bce_print_adapter_info (struct bce_softc *); 380 static void bce_probe_pci_caps (device_t, struct bce_softc *); 381 static void bce_stop (struct bce_softc *); 382 static int bce_reset (struct bce_softc *, u32); 383 static int bce_chipinit (struct bce_softc *); 384 static int bce_blockinit (struct bce_softc *); 385 386 static int bce_init_tx_chain (struct bce_softc *); 387 static void bce_free_tx_chain (struct bce_softc *); 388 389 static int bce_get_rx_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *); 390 static int bce_init_rx_chain (struct bce_softc *); 391 static void bce_fill_rx_chain (struct bce_softc *); 392 static void bce_free_rx_chain (struct bce_softc *); 393 394 #ifdef ZERO_COPY_SOCKETS 395 static int bce_get_pg_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *); 396 static int bce_init_pg_chain (struct bce_softc *); 397 static void bce_fill_pg_chain (struct bce_softc *); 398 static void bce_free_pg_chain (struct bce_softc *); 399 #endif 400 401 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 402 static void bce_start_locked (struct ifnet *); 403 static void bce_start (struct ifnet *); 404 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 405 static void bce_watchdog (struct bce_softc *); 406 static int bce_ifmedia_upd (struct ifnet *); 407 static void bce_ifmedia_upd_locked (struct ifnet *); 408 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 409 static void bce_init_locked (struct bce_softc *); 410 static void bce_init (void *); 411 static void bce_mgmt_init_locked (struct bce_softc *sc); 412 413 static void bce_init_ctx (struct bce_softc *); 414 static void bce_get_mac_addr (struct bce_softc *); 415 static void bce_set_mac_addr (struct bce_softc *); 416 static void bce_phy_intr (struct bce_softc *); 417 static inline u16 bce_get_hw_rx_cons(struct bce_softc *); 418 static void bce_rx_intr (struct bce_softc *); 419 static void bce_tx_intr (struct bce_softc *); 420 static void bce_disable_intr (struct bce_softc *); 421 static void bce_enable_intr (struct bce_softc *, int); 422 423 static void bce_intr (void *); 424 static void bce_set_rx_mode (struct bce_softc *); 425 static void bce_stats_update (struct bce_softc *); 426 static void bce_tick (void *); 427 static void bce_pulse (void *); 428 static void bce_add_sysctls (struct bce_softc *); 429 430 431 /****************************************************************************/ 432 /* FreeBSD device dispatch table. */ 433 /****************************************************************************/ 434 static device_method_t bce_methods[] = { 435 /* Device interface (device_if.h) */ 436 DEVMETHOD(device_probe, bce_probe), 437 DEVMETHOD(device_attach, bce_attach), 438 DEVMETHOD(device_detach, bce_detach), 439 DEVMETHOD(device_shutdown, bce_shutdown), 440 /* Supported by device interface but not used here. */ 441 /* DEVMETHOD(device_identify, bce_identify), */ 442 /* DEVMETHOD(device_suspend, bce_suspend), */ 443 /* DEVMETHOD(device_resume, bce_resume), */ 444 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 445 446 /* Bus interface (bus_if.h) */ 447 DEVMETHOD(bus_print_child, bus_generic_print_child), 448 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 449 450 /* MII interface (miibus_if.h) */ 451 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 452 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 453 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 454 /* Supported by MII interface but not used here. */ 455 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 456 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 457 458 { 0, 0 } 459 }; 460 461 static driver_t bce_driver = { 462 "bce", 463 bce_methods, 464 sizeof(struct bce_softc) 465 }; 466 467 static devclass_t bce_devclass; 468 469 MODULE_DEPEND(bce, pci, 1, 1, 1); 470 MODULE_DEPEND(bce, ether, 1, 1, 1); 471 MODULE_DEPEND(bce, miibus, 1, 1, 1); 472 473 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 474 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 475 476 477 /****************************************************************************/ 478 /* Tunable device values */ 479 /****************************************************************************/ 480 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 481 482 /* Allowable values are TRUE or FALSE */ 483 static int bce_tso_enable = TRUE; 484 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 485 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 486 "TSO Enable/Disable"); 487 488 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 489 /* ToDo: Add MSI-X support. */ 490 static int bce_msi_enable = 1; 491 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 492 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 493 "MSI-X|MSI|INTx selector"); 494 495 /* ToDo: Add tunable to enable/disable strict MTU handling. */ 496 /* Currently allows "loose" RX MTU checking (i.e. sets the */ 497 /* H/W RX MTU to the size of the largest receive buffer, or */ 498 /* 2048 bytes). This will cause a UNH failure but is more */ 499 /* desireable from a functional perspective. */ 500 501 502 /****************************************************************************/ 503 /* Device probe function. */ 504 /* */ 505 /* Compares the device to the driver's list of supported devices and */ 506 /* reports back to the OS whether this is the right driver for the device. */ 507 /* */ 508 /* Returns: */ 509 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 510 /****************************************************************************/ 511 static int 512 bce_probe(device_t dev) 513 { 514 struct bce_type *t; 515 struct bce_softc *sc; 516 char *descbuf; 517 u16 vid = 0, did = 0, svid = 0, sdid = 0; 518 519 t = bce_devs; 520 521 sc = device_get_softc(dev); 522 bzero(sc, sizeof(struct bce_softc)); 523 sc->bce_unit = device_get_unit(dev); 524 sc->bce_dev = dev; 525 526 /* Get the data for the device to be probed. */ 527 vid = pci_get_vendor(dev); 528 did = pci_get_device(dev); 529 svid = pci_get_subvendor(dev); 530 sdid = pci_get_subdevice(dev); 531 532 DBPRINT(sc, BCE_EXTREME_LOAD, 533 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 534 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 535 536 /* Look through the list of known devices for a match. */ 537 while(t->bce_name != NULL) { 538 539 if ((vid == t->bce_vid) && (did == t->bce_did) && 540 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 541 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 542 543 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 544 545 if (descbuf == NULL) 546 return(ENOMEM); 547 548 /* Print out the device identity. */ 549 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 550 t->bce_name, 551 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 552 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 553 554 device_set_desc_copy(dev, descbuf); 555 free(descbuf, M_TEMP); 556 return(BUS_PROBE_DEFAULT); 557 } 558 t++; 559 } 560 561 return(ENXIO); 562 } 563 564 565 /****************************************************************************/ 566 /* PCI Capabilities Probe Function. */ 567 /* */ 568 /* Walks the PCI capabiites list for the device to find what features are */ 569 /* supported. */ 570 /* */ 571 /* Returns: */ 572 /* None. */ 573 /****************************************************************************/ 574 static void 575 bce_print_adapter_info(struct bce_softc *sc) 576 { 577 DBENTER(BCE_VERBOSE_LOAD); 578 579 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 580 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A', 581 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 582 583 /* Bus info. */ 584 if (sc->bce_flags & BCE_PCIE_FLAG) { 585 printf("Bus (PCIe x%d, ", sc->link_width); 586 switch (sc->link_speed) { 587 case 1: printf("2.5Gbps); "); break; 588 case 2: printf("5Gbps); "); break; 589 default: printf("Unknown link speed); "); 590 } 591 } else { 592 printf("Bus (PCI%s, %s, %dMHz); ", 593 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 594 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), 595 sc->bus_speed_mhz); 596 } 597 598 /* Firmware version and device features. */ 599 printf("B/C (0x%08X); Flags( ", sc->bce_bc_ver); 600 #ifdef ZERO_COPY_SOCKETS 601 printf("SPLT "); 602 #endif 603 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 604 printf("MFW "); 605 if (sc->bce_flags & BCE_USING_MSI_FLAG) 606 printf("MSI "); 607 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 608 printf("MSI-X "); 609 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 610 printf("2.5G "); 611 printf(")\n"); 612 613 DBEXIT(BCE_VERBOSE_LOAD); 614 } 615 616 617 /****************************************************************************/ 618 /* PCI Capabilities Probe Function. */ 619 /* */ 620 /* Walks the PCI capabiites list for the device to find what features are */ 621 /* supported. */ 622 /* */ 623 /* Returns: */ 624 /* None. */ 625 /****************************************************************************/ 626 static void 627 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 628 { 629 u32 reg; 630 631 DBENTER(BCE_VERBOSE_LOAD); 632 633 /* Check if PCI-X capability is enabled. */ 634 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 635 if (reg != 0) 636 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 637 } 638 639 /* Check if PCIe capability is enabled. */ 640 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 641 if (reg != 0) { 642 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 643 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = 0x%08X\n", 644 link_status); 645 sc->link_speed = link_status & 0xf; 646 sc->link_width = (link_status >> 4) & 0x3f; 647 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 648 sc->bce_flags |= BCE_PCIE_FLAG; 649 } 650 } 651 652 /* Check if MSI capability is enabled. */ 653 if (pci_find_extcap(dev, PCIY_MSI, ®) == 0) { 654 if (reg != 0) 655 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 656 } 657 658 /* Check if MSI-X capability is enabled. */ 659 if (pci_find_extcap(dev, PCIY_MSIX, ®) == 0) { 660 if (reg != 0) 661 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 662 } 663 664 DBEXIT(BCE_VERBOSE_LOAD); 665 } 666 667 668 /****************************************************************************/ 669 /* Device attach function. */ 670 /* */ 671 /* Allocates device resources, performs secondary chip identification, */ 672 /* resets and initializes the hardware, and initializes driver instance */ 673 /* variables. */ 674 /* */ 675 /* Returns: */ 676 /* 0 on success, positive value on failure. */ 677 /****************************************************************************/ 678 static int 679 bce_attach(device_t dev) 680 { 681 struct bce_softc *sc; 682 struct ifnet *ifp; 683 u32 val; 684 int error, rid, rc = 0; 685 686 sc = device_get_softc(dev); 687 sc->bce_dev = dev; 688 689 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 690 691 sc->bce_unit = device_get_unit(dev); 692 693 /* Set initial device and PHY flags */ 694 sc->bce_flags = 0; 695 sc->bce_phy_flags = 0; 696 697 pci_enable_busmaster(dev); 698 699 /* Allocate PCI memory resources. */ 700 rid = PCIR_BAR(0); 701 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 702 &rid, RF_ACTIVE); 703 704 if (sc->bce_res_mem == NULL) { 705 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 706 __FILE__, __LINE__); 707 rc = ENXIO; 708 goto bce_attach_fail; 709 } 710 711 /* Get various resource handles. */ 712 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 713 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 714 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 715 716 bce_probe_pci_caps(dev, sc); 717 718 rid = 1; 719 #if 0 720 /* Try allocating MSI-X interrupts. */ 721 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 722 (bce_msi_enable >= 2) && 723 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 724 &rid, RF_ACTIVE)) != NULL)) { 725 726 msi_needed = sc->bce_msi_count = 1; 727 728 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 729 (sc->bce_msi_count != msi_needed)) { 730 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 731 "Received = %d, error = %d\n", __FILE__, __LINE__, 732 msi_needed, sc->bce_msi_count, error); 733 sc->bce_msi_count = 0; 734 pci_release_msi(dev); 735 bus_release_resource(dev, SYS_RES_MEMORY, rid, 736 sc->bce_res_irq); 737 sc->bce_res_irq = NULL; 738 } else { 739 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 740 __FUNCTION__); 741 sc->bce_flags |= BCE_USING_MSIX_FLAG; 742 sc->bce_intr = bce_intr; 743 } 744 } 745 #endif 746 747 /* Try allocating a MSI interrupt. */ 748 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 749 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 750 sc->bce_msi_count = 1; 751 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 752 BCE_PRINTF("%s(%d): MSI allocation failed! error = %d\n", 753 __FILE__, __LINE__, error); 754 sc->bce_msi_count = 0; 755 pci_release_msi(dev); 756 } else { 757 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI interrupt.\n", 758 __FUNCTION__); 759 sc->bce_flags |= BCE_USING_MSI_FLAG; 760 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 761 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 762 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 763 sc->bce_irq_rid = 1; 764 sc->bce_intr = bce_intr; 765 } 766 } 767 768 /* Try allocating a legacy interrupt. */ 769 if (sc->bce_msi_count == 0) { 770 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 771 __FUNCTION__); 772 rid = 0; 773 sc->bce_intr = bce_intr; 774 } 775 776 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 777 &rid, RF_SHAREABLE | RF_ACTIVE); 778 779 sc->bce_irq_rid = rid; 780 781 /* Report any IRQ allocation errors. */ 782 if (sc->bce_res_irq == NULL) { 783 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 784 __FILE__, __LINE__); 785 rc = ENXIO; 786 goto bce_attach_fail; 787 } 788 789 /* Initialize mutex for the current device instance. */ 790 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 791 792 /* 793 * Configure byte swap and enable indirect register access. 794 * Rely on CPU to do target byte swapping on big endian systems. 795 * Access to registers outside of PCI configurtion space are not 796 * valid until this is done. 797 */ 798 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 799 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 800 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 801 802 /* Save ASIC revsion info. */ 803 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 804 805 /* Weed out any non-production controller revisions. */ 806 switch(BCE_CHIP_ID(sc)) { 807 case BCE_CHIP_ID_5706_A0: 808 case BCE_CHIP_ID_5706_A1: 809 case BCE_CHIP_ID_5708_A0: 810 case BCE_CHIP_ID_5708_B0: 811 case BCE_CHIP_ID_5709_A0: 812 case BCE_CHIP_ID_5709_B0: 813 case BCE_CHIP_ID_5709_B1: 814 case BCE_CHIP_ID_5709_B2: 815 BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n", 816 __FILE__, __LINE__, 817 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 818 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 819 rc = ENODEV; 820 goto bce_attach_fail; 821 } 822 823 /* 824 * The embedded PCIe to PCI-X bridge (EPB) 825 * in the 5708 cannot address memory above 826 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 827 */ 828 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 829 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 830 else 831 sc->max_bus_addr = BUS_SPACE_MAXADDR; 832 833 /* 834 * Find the base address for shared memory access. 835 * Newer versions of bootcode use a signature and offset 836 * while older versions use a fixed address. 837 */ 838 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 839 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 840 /* Multi-port devices use different offsets in shared memory. */ 841 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 842 (pci_get_function(sc->bce_dev) << 2)); 843 else 844 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 845 846 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 847 __FUNCTION__, sc->bce_shmem_base); 848 849 /* Fetch the bootcode revision. */ 850 sc->bce_bc_ver = REG_RD_IND(sc, sc->bce_shmem_base + 851 BCE_DEV_INFO_BC_REV); 852 853 /* Check if any management firmware is running. */ 854 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE); 855 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED)) 856 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 857 858 /* Get PCI bus information (speed and type). */ 859 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 860 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 861 u32 clkreg; 862 863 sc->bce_flags |= BCE_PCIX_FLAG; 864 865 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 866 867 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 868 switch (clkreg) { 869 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 870 sc->bus_speed_mhz = 133; 871 break; 872 873 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 874 sc->bus_speed_mhz = 100; 875 break; 876 877 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 878 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 879 sc->bus_speed_mhz = 66; 880 break; 881 882 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 883 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 884 sc->bus_speed_mhz = 50; 885 break; 886 887 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 888 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 889 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 890 sc->bus_speed_mhz = 33; 891 break; 892 } 893 } else { 894 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 895 sc->bus_speed_mhz = 66; 896 else 897 sc->bus_speed_mhz = 33; 898 } 899 900 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 901 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 902 903 /* Reset the controller and announce to bootcode that driver is present. */ 904 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 905 BCE_PRINTF("%s(%d): Controller reset failed!\n", 906 __FILE__, __LINE__); 907 rc = ENXIO; 908 goto bce_attach_fail; 909 } 910 911 /* Initialize the controller. */ 912 if (bce_chipinit(sc)) { 913 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 914 __FILE__, __LINE__); 915 rc = ENXIO; 916 goto bce_attach_fail; 917 } 918 919 /* Perform NVRAM test. */ 920 if (bce_nvram_test(sc)) { 921 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 922 __FILE__, __LINE__); 923 rc = ENXIO; 924 goto bce_attach_fail; 925 } 926 927 /* Fetch the permanent Ethernet MAC address. */ 928 bce_get_mac_addr(sc); 929 930 /* 931 * Trip points control how many BDs 932 * should be ready before generating an 933 * interrupt while ticks control how long 934 * a BD can sit in the chain before 935 * generating an interrupt. Set the default 936 * values for the RX and TX chains. 937 */ 938 939 #ifdef BCE_DEBUG 940 /* Force more frequent interrupts. */ 941 sc->bce_tx_quick_cons_trip_int = 1; 942 sc->bce_tx_quick_cons_trip = 1; 943 sc->bce_tx_ticks_int = 0; 944 sc->bce_tx_ticks = 0; 945 946 sc->bce_rx_quick_cons_trip_int = 1; 947 sc->bce_rx_quick_cons_trip = 1; 948 sc->bce_rx_ticks_int = 0; 949 sc->bce_rx_ticks = 0; 950 #else 951 /* Improve throughput at the expense of increased latency. */ 952 sc->bce_tx_quick_cons_trip_int = 20; 953 sc->bce_tx_quick_cons_trip = 20; 954 sc->bce_tx_ticks_int = 80; 955 sc->bce_tx_ticks = 80; 956 957 sc->bce_rx_quick_cons_trip_int = 6; 958 sc->bce_rx_quick_cons_trip = 6; 959 sc->bce_rx_ticks_int = 18; 960 sc->bce_rx_ticks = 18; 961 #endif 962 963 /* Update statistics once every second. */ 964 sc->bce_stats_ticks = 1000000 & 0xffff00; 965 966 /* Find the media type for the adapter. */ 967 bce_get_media(sc); 968 969 /* Store data needed by PHY driver for backplane applications */ 970 sc->bce_shared_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 971 BCE_SHARED_HW_CFG_CONFIG); 972 sc->bce_port_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 973 BCE_PORT_HW_CFG_CONFIG); 974 975 /* Allocate DMA memory resources. */ 976 if (bce_dma_alloc(dev)) { 977 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 978 __FILE__, __LINE__); 979 rc = ENXIO; 980 goto bce_attach_fail; 981 } 982 983 /* Allocate an ifnet structure. */ 984 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 985 if (ifp == NULL) { 986 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 987 __FILE__, __LINE__); 988 rc = ENXIO; 989 goto bce_attach_fail; 990 } 991 992 /* Initialize the ifnet interface. */ 993 ifp->if_softc = sc; 994 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 995 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 996 ifp->if_ioctl = bce_ioctl; 997 ifp->if_start = bce_start; 998 ifp->if_init = bce_init; 999 ifp->if_mtu = ETHERMTU; 1000 1001 if (bce_tso_enable) { 1002 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1003 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4; 1004 } else { 1005 ifp->if_hwassist = BCE_IF_HWASSIST; 1006 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1007 } 1008 1009 ifp->if_capenable = ifp->if_capabilities; 1010 1011 /* 1012 * Assume standard mbuf sizes for buffer allocation. 1013 * This may change later if the MTU size is set to 1014 * something other than 1500. 1015 */ 1016 #ifdef ZERO_COPY_SOCKETS 1017 sc->rx_bd_mbuf_alloc_size = MHLEN; 1018 /* Make sure offset is 16 byte aligned for hardware. */ 1019 sc->rx_bd_mbuf_align_pad = roundup2((MSIZE - MHLEN), 16) - 1020 (MSIZE - MHLEN); 1021 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1022 sc->rx_bd_mbuf_align_pad; 1023 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 1024 #else 1025 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 1026 sc->rx_bd_mbuf_align_pad = roundup2(MCLBYTES, 16) - MCLBYTES; 1027 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 1028 sc->rx_bd_mbuf_align_pad; 1029 #endif 1030 1031 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 1032 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1033 IFQ_SET_READY(&ifp->if_snd); 1034 1035 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1036 ifp->if_baudrate = IF_Mbps(2500ULL); 1037 else 1038 ifp->if_baudrate = IF_Mbps(1000); 1039 1040 /* Check for an MII child bus by probing the PHY. */ 1041 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 1042 bce_ifmedia_sts)) { 1043 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n", 1044 __FILE__, __LINE__); 1045 rc = ENXIO; 1046 goto bce_attach_fail; 1047 } 1048 1049 /* Attach to the Ethernet interface list. */ 1050 ether_ifattach(ifp, sc->eaddr); 1051 1052 #if __FreeBSD_version < 500000 1053 callout_init(&sc->bce_tick_callout); 1054 callout_init(&sc->bce_pulse_callout); 1055 #else 1056 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1057 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1058 #endif 1059 1060 /* Hookup IRQ last. */ 1061 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1062 NULL, bce_intr, sc, &sc->bce_intrhand); 1063 1064 if (rc) { 1065 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1066 __FILE__, __LINE__); 1067 bce_detach(dev); 1068 goto bce_attach_exit; 1069 } 1070 1071 /* 1072 * At this point we've acquired all the resources 1073 * we need to run so there's no turning back, we're 1074 * cleared for launch. 1075 */ 1076 1077 /* Print some important debugging info. */ 1078 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1079 1080 /* Add the supported sysctls to the kernel. */ 1081 bce_add_sysctls(sc); 1082 1083 BCE_LOCK(sc); 1084 1085 /* 1086 * The chip reset earlier notified the bootcode that 1087 * a driver is present. We now need to start our pulse 1088 * routine so that the bootcode is reminded that we're 1089 * still running. 1090 */ 1091 bce_pulse(sc); 1092 1093 bce_mgmt_init_locked(sc); 1094 BCE_UNLOCK(sc); 1095 1096 /* Finally, print some useful adapter info */ 1097 bce_print_adapter_info(sc); 1098 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1099 __FUNCTION__, sc); 1100 1101 goto bce_attach_exit; 1102 1103 bce_attach_fail: 1104 bce_release_resources(sc); 1105 1106 bce_attach_exit: 1107 1108 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1109 1110 return(rc); 1111 } 1112 1113 1114 /****************************************************************************/ 1115 /* Device detach function. */ 1116 /* */ 1117 /* Stops the controller, resets the controller, and releases resources. */ 1118 /* */ 1119 /* Returns: */ 1120 /* 0 on success, positive value on failure. */ 1121 /****************************************************************************/ 1122 static int 1123 bce_detach(device_t dev) 1124 { 1125 struct bce_softc *sc = device_get_softc(dev); 1126 struct ifnet *ifp; 1127 u32 msg; 1128 1129 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1130 1131 ifp = sc->bce_ifp; 1132 1133 /* Stop and reset the controller. */ 1134 BCE_LOCK(sc); 1135 1136 /* Stop the pulse so the bootcode can go to driver absent state. */ 1137 callout_stop(&sc->bce_pulse_callout); 1138 1139 bce_stop(sc); 1140 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1141 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1142 else 1143 msg = BCE_DRV_MSG_CODE_UNLOAD; 1144 bce_reset(sc, msg); 1145 1146 BCE_UNLOCK(sc); 1147 1148 ether_ifdetach(ifp); 1149 1150 /* If we have a child device on the MII bus remove it too. */ 1151 bus_generic_detach(dev); 1152 device_delete_child(dev, sc->bce_miibus); 1153 1154 /* Release all remaining resources. */ 1155 bce_release_resources(sc); 1156 1157 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1158 1159 return(0); 1160 } 1161 1162 1163 /****************************************************************************/ 1164 /* Device shutdown function. */ 1165 /* */ 1166 /* Stops and resets the controller. */ 1167 /* */ 1168 /* Returns: */ 1169 /* 0 on success, positive value on failure. */ 1170 /****************************************************************************/ 1171 static int 1172 bce_shutdown(device_t dev) 1173 { 1174 struct bce_softc *sc = device_get_softc(dev); 1175 u32 msg; 1176 1177 DBENTER(BCE_VERBOSE); 1178 1179 BCE_LOCK(sc); 1180 bce_stop(sc); 1181 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1182 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1183 else 1184 msg = BCE_DRV_MSG_CODE_UNLOAD; 1185 bce_reset(sc, msg); 1186 BCE_UNLOCK(sc); 1187 1188 DBEXIT(BCE_VERBOSE); 1189 1190 return (0); 1191 } 1192 1193 1194 #ifdef BCE_DEBUG 1195 /****************************************************************************/ 1196 /* Register read. */ 1197 /* */ 1198 /* Returns: */ 1199 /* The value of the register. */ 1200 /****************************************************************************/ 1201 static u32 1202 bce_reg_rd(struct bce_softc *sc, u32 offset) 1203 { 1204 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1205 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1206 __FUNCTION__, offset, val); 1207 return val; 1208 } 1209 1210 1211 /****************************************************************************/ 1212 /* Register write (16 bit). */ 1213 /* */ 1214 /* Returns: */ 1215 /* Nothing. */ 1216 /****************************************************************************/ 1217 static void 1218 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1219 { 1220 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1221 __FUNCTION__, offset, val); 1222 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1223 } 1224 1225 1226 /****************************************************************************/ 1227 /* Register write. */ 1228 /* */ 1229 /* Returns: */ 1230 /* Nothing. */ 1231 /****************************************************************************/ 1232 static void 1233 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1234 { 1235 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1236 __FUNCTION__, offset, val); 1237 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1238 } 1239 #endif 1240 1241 /****************************************************************************/ 1242 /* Indirect register read. */ 1243 /* */ 1244 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1245 /* configuration space. Using this mechanism avoids issues with posted */ 1246 /* reads but is much slower than memory-mapped I/O. */ 1247 /* */ 1248 /* Returns: */ 1249 /* The value of the register. */ 1250 /****************************************************************************/ 1251 static u32 1252 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1253 { 1254 device_t dev; 1255 dev = sc->bce_dev; 1256 1257 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1258 #ifdef BCE_DEBUG 1259 { 1260 u32 val; 1261 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1262 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1263 __FUNCTION__, offset, val); 1264 return val; 1265 } 1266 #else 1267 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1268 #endif 1269 } 1270 1271 1272 /****************************************************************************/ 1273 /* Indirect register write. */ 1274 /* */ 1275 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1276 /* configuration space. Using this mechanism avoids issues with posted */ 1277 /* writes but is muchh slower than memory-mapped I/O. */ 1278 /* */ 1279 /* Returns: */ 1280 /* Nothing. */ 1281 /****************************************************************************/ 1282 static void 1283 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1284 { 1285 device_t dev; 1286 dev = sc->bce_dev; 1287 1288 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1289 __FUNCTION__, offset, val); 1290 1291 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1292 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1293 } 1294 1295 1296 #ifdef BCE_DEBUG 1297 /****************************************************************************/ 1298 /* Context memory read. */ 1299 /* */ 1300 /* The NetXtreme II controller uses context memory to track connection */ 1301 /* information for L2 and higher network protocols. */ 1302 /* */ 1303 /* Returns: */ 1304 /* The requested 32 bit value of context memory. */ 1305 /****************************************************************************/ 1306 static u32 1307 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1308 { 1309 u32 idx, offset, retry_cnt = 5, val; 1310 1311 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1312 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1313 __FUNCTION__, cid_addr)); 1314 1315 offset = ctx_offset + cid_addr; 1316 1317 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1318 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1319 1320 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1321 1322 for (idx = 0; idx < retry_cnt; idx++) { 1323 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1324 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1325 break; 1326 DELAY(5); 1327 } 1328 1329 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1330 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1331 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1332 __FILE__, __LINE__, cid_addr, ctx_offset); 1333 1334 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1335 } else { 1336 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1337 val = REG_RD(sc, BCE_CTX_DATA); 1338 } 1339 1340 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1341 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1342 1343 return(val); 1344 } 1345 #endif 1346 1347 1348 /****************************************************************************/ 1349 /* Context memory write. */ 1350 /* */ 1351 /* The NetXtreme II controller uses context memory to track connection */ 1352 /* information for L2 and higher network protocols. */ 1353 /* */ 1354 /* Returns: */ 1355 /* Nothing. */ 1356 /****************************************************************************/ 1357 static void 1358 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1359 { 1360 u32 idx, offset = ctx_offset + cid_addr; 1361 u32 val, retry_cnt = 5; 1362 1363 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1364 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1365 1366 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1367 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1368 __FUNCTION__, cid_addr)); 1369 1370 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 1371 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 1372 1373 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1374 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1375 1376 for (idx = 0; idx < retry_cnt; idx++) { 1377 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1378 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1379 break; 1380 DELAY(5); 1381 } 1382 1383 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1384 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1385 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1386 __FILE__, __LINE__, cid_addr, ctx_offset); 1387 1388 } else { 1389 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1390 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1391 } 1392 } 1393 1394 1395 /****************************************************************************/ 1396 /* PHY register read. */ 1397 /* */ 1398 /* Implements register reads on the MII bus. */ 1399 /* */ 1400 /* Returns: */ 1401 /* The value of the register. */ 1402 /****************************************************************************/ 1403 static int 1404 bce_miibus_read_reg(device_t dev, int phy, int reg) 1405 { 1406 struct bce_softc *sc; 1407 u32 val; 1408 int i; 1409 1410 sc = device_get_softc(dev); 1411 1412 /* Make sure we are accessing the correct PHY address. */ 1413 if (phy != sc->bce_phy_addr) { 1414 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY read!\n", phy); 1415 return(0); 1416 } 1417 1418 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1419 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1420 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1421 1422 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1423 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1424 1425 DELAY(40); 1426 } 1427 1428 1429 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1430 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1431 BCE_EMAC_MDIO_COMM_START_BUSY; 1432 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1433 1434 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1435 DELAY(10); 1436 1437 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1438 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1439 DELAY(5); 1440 1441 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1442 val &= BCE_EMAC_MDIO_COMM_DATA; 1443 1444 break; 1445 } 1446 } 1447 1448 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1449 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n", 1450 __FILE__, __LINE__, phy, reg); 1451 val = 0x0; 1452 } else { 1453 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1454 } 1455 1456 1457 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1458 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1459 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1460 1461 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1462 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1463 1464 DELAY(40); 1465 } 1466 1467 DB_PRINT_PHY_REG(reg, val); 1468 return (val & 0xffff); 1469 1470 } 1471 1472 1473 /****************************************************************************/ 1474 /* PHY register write. */ 1475 /* */ 1476 /* Implements register writes on the MII bus. */ 1477 /* */ 1478 /* Returns: */ 1479 /* The value of the register. */ 1480 /****************************************************************************/ 1481 static int 1482 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1483 { 1484 struct bce_softc *sc; 1485 u32 val1; 1486 int i; 1487 1488 sc = device_get_softc(dev); 1489 1490 /* Make sure we are accessing the correct PHY address. */ 1491 if (phy != sc->bce_phy_addr) { 1492 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY write!\n", phy); 1493 return(0); 1494 } 1495 1496 DB_PRINT_PHY_REG(reg, val); 1497 1498 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1499 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1500 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1501 1502 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1503 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1504 1505 DELAY(40); 1506 } 1507 1508 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1509 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1510 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1511 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1512 1513 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1514 DELAY(10); 1515 1516 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1517 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1518 DELAY(5); 1519 break; 1520 } 1521 } 1522 1523 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1524 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1525 __FILE__, __LINE__); 1526 1527 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1528 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1529 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1530 1531 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1532 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1533 1534 DELAY(40); 1535 } 1536 1537 return 0; 1538 } 1539 1540 1541 /****************************************************************************/ 1542 /* MII bus status change. */ 1543 /* */ 1544 /* Called by the MII bus driver when the PHY establishes link to set the */ 1545 /* MAC interface registers. */ 1546 /* */ 1547 /* Returns: */ 1548 /* Nothing. */ 1549 /****************************************************************************/ 1550 static void 1551 bce_miibus_statchg(device_t dev) 1552 { 1553 struct bce_softc *sc; 1554 struct mii_data *mii; 1555 int val; 1556 1557 sc = device_get_softc(dev); 1558 1559 DBENTER(BCE_VERBOSE_PHY); 1560 1561 mii = device_get_softc(sc->bce_miibus); 1562 1563 val = REG_RD(sc, BCE_EMAC_MODE); 1564 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1565 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1566 BCE_EMAC_MODE_25G); 1567 1568 /* Set MII or GMII interface based on the speed negotiated by the PHY. */ 1569 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1570 case IFM_10_T: 1571 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 1572 DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n"); 1573 val |= BCE_EMAC_MODE_PORT_MII_10; 1574 break; 1575 } 1576 /* fall-through */ 1577 case IFM_100_TX: 1578 DBPRINT(sc, BCE_INFO, "Enabling MII interface.\n"); 1579 val |= BCE_EMAC_MODE_PORT_MII; 1580 break; 1581 case IFM_2500_SX: 1582 DBPRINT(sc, BCE_INFO, "Enabling 2.5G MAC mode.\n"); 1583 val |= BCE_EMAC_MODE_25G; 1584 /* fall-through */ 1585 case IFM_1000_T: 1586 case IFM_1000_SX: 1587 DBPRINT(sc, BCE_INFO, "Enabling GMII interface.\n"); 1588 val |= BCE_EMAC_MODE_PORT_GMII; 1589 break; 1590 default: 1591 DBPRINT(sc, BCE_INFO, "Unknown speed, enabling default GMII " 1592 "interface.\n"); 1593 val |= BCE_EMAC_MODE_PORT_GMII; 1594 } 1595 1596 /* Set half or full duplex based on the duplicity negotiated by the PHY. */ 1597 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1598 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n"); 1599 val |= BCE_EMAC_MODE_HALF_DUPLEX; 1600 } else 1601 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n"); 1602 1603 REG_WR(sc, BCE_EMAC_MODE, val); 1604 1605 #if 0 1606 /* ToDo: Enable flow control support in brgphy and bge. */ 1607 /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */ 1608 if (mii->mii_media_active & IFM_FLAG0) 1609 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1610 if (mii->mii_media_active & IFM_FLAG1) 1611 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1612 #endif 1613 1614 DBEXIT(BCE_VERBOSE_PHY); 1615 } 1616 1617 1618 /****************************************************************************/ 1619 /* Acquire NVRAM lock. */ 1620 /* */ 1621 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1622 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1623 /* for use by the driver. */ 1624 /* */ 1625 /* Returns: */ 1626 /* 0 on success, positive value on failure. */ 1627 /****************************************************************************/ 1628 static int 1629 bce_acquire_nvram_lock(struct bce_softc *sc) 1630 { 1631 u32 val; 1632 int j, rc = 0; 1633 1634 DBENTER(BCE_VERBOSE_NVRAM); 1635 1636 /* Request access to the flash interface. */ 1637 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1638 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1639 val = REG_RD(sc, BCE_NVM_SW_ARB); 1640 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1641 break; 1642 1643 DELAY(5); 1644 } 1645 1646 if (j >= NVRAM_TIMEOUT_COUNT) { 1647 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1648 rc = EBUSY; 1649 } 1650 1651 DBEXIT(BCE_VERBOSE_NVRAM); 1652 return (rc); 1653 } 1654 1655 1656 /****************************************************************************/ 1657 /* Release NVRAM lock. */ 1658 /* */ 1659 /* When the caller is finished accessing NVRAM the lock must be released. */ 1660 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1661 /* for use by the driver. */ 1662 /* */ 1663 /* Returns: */ 1664 /* 0 on success, positive value on failure. */ 1665 /****************************************************************************/ 1666 static int 1667 bce_release_nvram_lock(struct bce_softc *sc) 1668 { 1669 u32 val; 1670 int j, rc = 0; 1671 1672 DBENTER(BCE_VERBOSE_NVRAM); 1673 1674 /* 1675 * Relinquish nvram interface. 1676 */ 1677 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1678 1679 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1680 val = REG_RD(sc, BCE_NVM_SW_ARB); 1681 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1682 break; 1683 1684 DELAY(5); 1685 } 1686 1687 if (j >= NVRAM_TIMEOUT_COUNT) { 1688 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 1689 rc = EBUSY; 1690 } 1691 1692 DBEXIT(BCE_VERBOSE_NVRAM); 1693 return (rc); 1694 } 1695 1696 1697 #ifdef BCE_NVRAM_WRITE_SUPPORT 1698 /****************************************************************************/ 1699 /* Enable NVRAM write access. */ 1700 /* */ 1701 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1702 /* */ 1703 /* Returns: */ 1704 /* 0 on success, positive value on failure. */ 1705 /****************************************************************************/ 1706 static int 1707 bce_enable_nvram_write(struct bce_softc *sc) 1708 { 1709 u32 val; 1710 int rc = 0; 1711 1712 DBENTER(BCE_VERBOSE_NVRAM); 1713 1714 val = REG_RD(sc, BCE_MISC_CFG); 1715 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1716 1717 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 1718 int j; 1719 1720 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1721 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1722 1723 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1724 DELAY(5); 1725 1726 val = REG_RD(sc, BCE_NVM_COMMAND); 1727 if (val & BCE_NVM_COMMAND_DONE) 1728 break; 1729 } 1730 1731 if (j >= NVRAM_TIMEOUT_COUNT) { 1732 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1733 rc = EBUSY; 1734 } 1735 } 1736 1737 DBENTER(BCE_VERBOSE_NVRAM); 1738 return (rc); 1739 } 1740 1741 1742 /****************************************************************************/ 1743 /* Disable NVRAM write access. */ 1744 /* */ 1745 /* When the caller is finished writing to NVRAM write access must be */ 1746 /* disabled. */ 1747 /* */ 1748 /* Returns: */ 1749 /* Nothing. */ 1750 /****************************************************************************/ 1751 static void 1752 bce_disable_nvram_write(struct bce_softc *sc) 1753 { 1754 u32 val; 1755 1756 DBENTER(BCE_VERBOSE_NVRAM); 1757 1758 val = REG_RD(sc, BCE_MISC_CFG); 1759 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1760 1761 DBEXIT(BCE_VERBOSE_NVRAM); 1762 1763 } 1764 #endif 1765 1766 1767 /****************************************************************************/ 1768 /* Enable NVRAM access. */ 1769 /* */ 1770 /* Before accessing NVRAM for read or write operations the caller must */ 1771 /* enabled NVRAM access. */ 1772 /* */ 1773 /* Returns: */ 1774 /* Nothing. */ 1775 /****************************************************************************/ 1776 static void 1777 bce_enable_nvram_access(struct bce_softc *sc) 1778 { 1779 u32 val; 1780 1781 DBENTER(BCE_VERBOSE_NVRAM); 1782 1783 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1784 /* Enable both bits, even on read. */ 1785 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1786 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1787 1788 DBEXIT(BCE_VERBOSE_NVRAM); 1789 } 1790 1791 1792 /****************************************************************************/ 1793 /* Disable NVRAM access. */ 1794 /* */ 1795 /* When the caller is finished accessing NVRAM access must be disabled. */ 1796 /* */ 1797 /* Returns: */ 1798 /* Nothing. */ 1799 /****************************************************************************/ 1800 static void 1801 bce_disable_nvram_access(struct bce_softc *sc) 1802 { 1803 u32 val; 1804 1805 DBENTER(BCE_VERBOSE_NVRAM); 1806 1807 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1808 1809 /* Disable both bits, even after read. */ 1810 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1811 val & ~(BCE_NVM_ACCESS_ENABLE_EN | 1812 BCE_NVM_ACCESS_ENABLE_WR_EN)); 1813 1814 DBEXIT(BCE_VERBOSE_NVRAM); 1815 } 1816 1817 1818 #ifdef BCE_NVRAM_WRITE_SUPPORT 1819 /****************************************************************************/ 1820 /* Erase NVRAM page before writing. */ 1821 /* */ 1822 /* Non-buffered flash parts require that a page be erased before it is */ 1823 /* written. */ 1824 /* */ 1825 /* Returns: */ 1826 /* 0 on success, positive value on failure. */ 1827 /****************************************************************************/ 1828 static int 1829 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 1830 { 1831 u32 cmd; 1832 int j, rc = 0; 1833 1834 DBENTER(BCE_VERBOSE_NVRAM); 1835 1836 /* Buffered flash doesn't require an erase. */ 1837 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 1838 goto bce_nvram_erase_page_exit; 1839 1840 /* Build an erase command. */ 1841 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 1842 BCE_NVM_COMMAND_DOIT; 1843 1844 /* 1845 * Clear the DONE bit separately, set the NVRAM adress to erase, 1846 * and issue the erase command. 1847 */ 1848 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1849 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1850 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1851 1852 /* Wait for completion. */ 1853 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1854 u32 val; 1855 1856 DELAY(5); 1857 1858 val = REG_RD(sc, BCE_NVM_COMMAND); 1859 if (val & BCE_NVM_COMMAND_DONE) 1860 break; 1861 } 1862 1863 if (j >= NVRAM_TIMEOUT_COUNT) { 1864 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 1865 rc = EBUSY; 1866 } 1867 1868 bce_nvram_erase_page_exit: 1869 DBEXIT(BCE_VERBOSE_NVRAM); 1870 return (rc); 1871 } 1872 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1873 1874 1875 /****************************************************************************/ 1876 /* Read a dword (32 bits) from NVRAM. */ 1877 /* */ 1878 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1879 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1880 /* */ 1881 /* Returns: */ 1882 /* 0 on success and the 32 bit value read, positive value on failure. */ 1883 /****************************************************************************/ 1884 static int 1885 bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val, 1886 u32 cmd_flags) 1887 { 1888 u32 cmd; 1889 int i, rc = 0; 1890 1891 DBENTER(BCE_EXTREME_NVRAM); 1892 1893 /* Build the command word. */ 1894 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 1895 1896 /* Calculate the offset for buffered flash if translation is used. */ 1897 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 1898 offset = ((offset / sc->bce_flash_info->page_size) << 1899 sc->bce_flash_info->page_bits) + 1900 (offset % sc->bce_flash_info->page_size); 1901 } 1902 1903 /* 1904 * Clear the DONE bit separately, set the address to read, 1905 * and issue the read. 1906 */ 1907 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1908 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1909 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1910 1911 /* Wait for completion. */ 1912 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1913 u32 val; 1914 1915 DELAY(5); 1916 1917 val = REG_RD(sc, BCE_NVM_COMMAND); 1918 if (val & BCE_NVM_COMMAND_DONE) { 1919 val = REG_RD(sc, BCE_NVM_READ); 1920 1921 val = bce_be32toh(val); 1922 memcpy(ret_val, &val, 4); 1923 break; 1924 } 1925 } 1926 1927 /* Check for errors. */ 1928 if (i >= NVRAM_TIMEOUT_COUNT) { 1929 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n", 1930 __FILE__, __LINE__, offset); 1931 rc = EBUSY; 1932 } 1933 1934 DBEXIT(BCE_EXTREME_NVRAM); 1935 return(rc); 1936 } 1937 1938 1939 #ifdef BCE_NVRAM_WRITE_SUPPORT 1940 /****************************************************************************/ 1941 /* Write a dword (32 bits) to NVRAM. */ 1942 /* */ 1943 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1944 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1945 /* enabled NVRAM write access. */ 1946 /* */ 1947 /* Returns: */ 1948 /* 0 on success, positive value on failure. */ 1949 /****************************************************************************/ 1950 static int 1951 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 1952 u32 cmd_flags) 1953 { 1954 u32 cmd, val32; 1955 int j, rc = 0; 1956 1957 DBENTER(BCE_VERBOSE_NVRAM); 1958 1959 /* Build the command word. */ 1960 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 1961 1962 /* Calculate the offset for buffered flash if translation is used. */ 1963 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 1964 offset = ((offset / sc->bce_flash_info->page_size) << 1965 sc->bce_flash_info->page_bits) + 1966 (offset % sc->bce_flash_info->page_size); 1967 } 1968 1969 /* 1970 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1971 * set the NVRAM address to write, and issue the write command 1972 */ 1973 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1974 memcpy(&val32, val, 4); 1975 val32 = htobe32(val32); 1976 REG_WR(sc, BCE_NVM_WRITE, val32); 1977 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1978 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1979 1980 /* Wait for completion. */ 1981 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1982 DELAY(5); 1983 1984 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 1985 break; 1986 } 1987 if (j >= NVRAM_TIMEOUT_COUNT) { 1988 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n", 1989 __FILE__, __LINE__, offset); 1990 rc = EBUSY; 1991 } 1992 1993 DBEXIT(BCE_VERBOSE_NVRAM); 1994 return (rc); 1995 } 1996 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1997 1998 1999 /****************************************************************************/ 2000 /* Initialize NVRAM access. */ 2001 /* */ 2002 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2003 /* access that device. */ 2004 /* */ 2005 /* Returns: */ 2006 /* 0 on success, positive value on failure. */ 2007 /****************************************************************************/ 2008 static int 2009 bce_init_nvram(struct bce_softc *sc) 2010 { 2011 u32 val; 2012 int j, entry_count, rc = 0; 2013 struct flash_spec *flash; 2014 2015 DBENTER(BCE_VERBOSE_NVRAM); 2016 2017 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2018 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2019 sc->bce_flash_info = &flash_5709; 2020 goto bce_init_nvram_get_flash_size; 2021 } 2022 2023 /* Determine the selected interface. */ 2024 val = REG_RD(sc, BCE_NVM_CFG1); 2025 2026 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2027 2028 /* 2029 * Flash reconfiguration is required to support additional 2030 * NVRAM devices not directly supported in hardware. 2031 * Check if the flash interface was reconfigured 2032 * by the bootcode. 2033 */ 2034 2035 if (val & 0x40000000) { 2036 /* Flash interface reconfigured by bootcode. */ 2037 2038 DBPRINT(sc,BCE_INFO_LOAD, 2039 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2040 2041 for (j = 0, flash = &flash_table[0]; j < entry_count; 2042 j++, flash++) { 2043 if ((val & FLASH_BACKUP_STRAP_MASK) == 2044 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2045 sc->bce_flash_info = flash; 2046 break; 2047 } 2048 } 2049 } else { 2050 /* Flash interface not yet reconfigured. */ 2051 u32 mask; 2052 2053 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2054 __FUNCTION__); 2055 2056 if (val & (1 << 23)) 2057 mask = FLASH_BACKUP_STRAP_MASK; 2058 else 2059 mask = FLASH_STRAP_MASK; 2060 2061 /* Look for the matching NVRAM device configuration data. */ 2062 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2063 2064 /* Check if the device matches any of the known devices. */ 2065 if ((val & mask) == (flash->strapping & mask)) { 2066 /* Found a device match. */ 2067 sc->bce_flash_info = flash; 2068 2069 /* Request access to the flash interface. */ 2070 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2071 return rc; 2072 2073 /* Reconfigure the flash interface. */ 2074 bce_enable_nvram_access(sc); 2075 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2076 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2077 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2078 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2079 bce_disable_nvram_access(sc); 2080 bce_release_nvram_lock(sc); 2081 2082 break; 2083 } 2084 } 2085 } 2086 2087 /* Check if a matching device was found. */ 2088 if (j == entry_count) { 2089 sc->bce_flash_info = NULL; 2090 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2091 __FILE__, __LINE__); 2092 rc = ENODEV; 2093 } 2094 2095 bce_init_nvram_get_flash_size: 2096 /* Write the flash config data to the shared memory interface. */ 2097 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2); 2098 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2099 if (val) 2100 sc->bce_flash_size = val; 2101 else 2102 sc->bce_flash_size = sc->bce_flash_info->total_size; 2103 2104 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2105 __FUNCTION__, sc->bce_flash_info->name, 2106 sc->bce_flash_info->total_size); 2107 2108 DBEXIT(BCE_VERBOSE_NVRAM); 2109 return rc; 2110 } 2111 2112 2113 /****************************************************************************/ 2114 /* Read an arbitrary range of data from NVRAM. */ 2115 /* */ 2116 /* Prepares the NVRAM interface for access and reads the requested data */ 2117 /* into the supplied buffer. */ 2118 /* */ 2119 /* Returns: */ 2120 /* 0 on success and the data read, positive value on failure. */ 2121 /****************************************************************************/ 2122 static int 2123 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2124 int buf_size) 2125 { 2126 int rc = 0; 2127 u32 cmd_flags, offset32, len32, extra; 2128 2129 DBENTER(BCE_VERBOSE_NVRAM); 2130 2131 if (buf_size == 0) 2132 goto bce_nvram_read_exit; 2133 2134 /* Request access to the flash interface. */ 2135 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2136 goto bce_nvram_read_exit; 2137 2138 /* Enable access to flash interface */ 2139 bce_enable_nvram_access(sc); 2140 2141 len32 = buf_size; 2142 offset32 = offset; 2143 extra = 0; 2144 2145 cmd_flags = 0; 2146 2147 if (offset32 & 3) { 2148 u8 buf[4]; 2149 u32 pre_len; 2150 2151 offset32 &= ~3; 2152 pre_len = 4 - (offset & 3); 2153 2154 if (pre_len >= len32) { 2155 pre_len = len32; 2156 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2157 } 2158 else { 2159 cmd_flags = BCE_NVM_COMMAND_FIRST; 2160 } 2161 2162 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2163 2164 if (rc) 2165 return rc; 2166 2167 memcpy(ret_buf, buf + (offset & 3), pre_len); 2168 2169 offset32 += 4; 2170 ret_buf += pre_len; 2171 len32 -= pre_len; 2172 } 2173 2174 if (len32 & 3) { 2175 extra = 4 - (len32 & 3); 2176 len32 = (len32 + 4) & ~3; 2177 } 2178 2179 if (len32 == 4) { 2180 u8 buf[4]; 2181 2182 if (cmd_flags) 2183 cmd_flags = BCE_NVM_COMMAND_LAST; 2184 else 2185 cmd_flags = BCE_NVM_COMMAND_FIRST | 2186 BCE_NVM_COMMAND_LAST; 2187 2188 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2189 2190 memcpy(ret_buf, buf, 4 - extra); 2191 } 2192 else if (len32 > 0) { 2193 u8 buf[4]; 2194 2195 /* Read the first word. */ 2196 if (cmd_flags) 2197 cmd_flags = 0; 2198 else 2199 cmd_flags = BCE_NVM_COMMAND_FIRST; 2200 2201 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2202 2203 /* Advance to the next dword. */ 2204 offset32 += 4; 2205 ret_buf += 4; 2206 len32 -= 4; 2207 2208 while (len32 > 4 && rc == 0) { 2209 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2210 2211 /* Advance to the next dword. */ 2212 offset32 += 4; 2213 ret_buf += 4; 2214 len32 -= 4; 2215 } 2216 2217 if (rc) 2218 goto bce_nvram_read_locked_exit; 2219 2220 cmd_flags = BCE_NVM_COMMAND_LAST; 2221 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2222 2223 memcpy(ret_buf, buf, 4 - extra); 2224 } 2225 2226 bce_nvram_read_locked_exit: 2227 /* Disable access to flash interface and release the lock. */ 2228 bce_disable_nvram_access(sc); 2229 bce_release_nvram_lock(sc); 2230 2231 bce_nvram_read_exit: 2232 DBEXIT(BCE_VERBOSE_NVRAM); 2233 return rc; 2234 } 2235 2236 2237 #ifdef BCE_NVRAM_WRITE_SUPPORT 2238 /****************************************************************************/ 2239 /* Write an arbitrary range of data from NVRAM. */ 2240 /* */ 2241 /* Prepares the NVRAM interface for write access and writes the requested */ 2242 /* data from the supplied buffer. The caller is responsible for */ 2243 /* calculating any appropriate CRCs. */ 2244 /* */ 2245 /* Returns: */ 2246 /* 0 on success, positive value on failure. */ 2247 /****************************************************************************/ 2248 static int 2249 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2250 int buf_size) 2251 { 2252 u32 written, offset32, len32; 2253 u8 *buf, start[4], end[4]; 2254 int rc = 0; 2255 int align_start, align_end; 2256 2257 DBENTER(BCE_VERBOSE_NVRAM); 2258 2259 buf = data_buf; 2260 offset32 = offset; 2261 len32 = buf_size; 2262 align_start = align_end = 0; 2263 2264 if ((align_start = (offset32 & 3))) { 2265 offset32 &= ~3; 2266 len32 += align_start; 2267 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2268 goto bce_nvram_write_exit; 2269 } 2270 2271 if (len32 & 3) { 2272 if ((len32 > 4) || !align_start) { 2273 align_end = 4 - (len32 & 3); 2274 len32 += align_end; 2275 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2276 end, 4))) { 2277 goto bce_nvram_write_exit; 2278 } 2279 } 2280 } 2281 2282 if (align_start || align_end) { 2283 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2284 if (buf == 0) { 2285 rc = ENOMEM; 2286 goto bce_nvram_write_exit; 2287 } 2288 2289 if (align_start) { 2290 memcpy(buf, start, 4); 2291 } 2292 2293 if (align_end) { 2294 memcpy(buf + len32 - 4, end, 4); 2295 } 2296 memcpy(buf + align_start, data_buf, buf_size); 2297 } 2298 2299 written = 0; 2300 while ((written < len32) && (rc == 0)) { 2301 u32 page_start, page_end, data_start, data_end; 2302 u32 addr, cmd_flags; 2303 int i; 2304 u8 flash_buffer[264]; 2305 2306 /* Find the page_start addr */ 2307 page_start = offset32 + written; 2308 page_start -= (page_start % sc->bce_flash_info->page_size); 2309 /* Find the page_end addr */ 2310 page_end = page_start + sc->bce_flash_info->page_size; 2311 /* Find the data_start addr */ 2312 data_start = (written == 0) ? offset32 : page_start; 2313 /* Find the data_end addr */ 2314 data_end = (page_end > offset32 + len32) ? 2315 (offset32 + len32) : page_end; 2316 2317 /* Request access to the flash interface. */ 2318 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2319 goto bce_nvram_write_exit; 2320 2321 /* Enable access to flash interface */ 2322 bce_enable_nvram_access(sc); 2323 2324 cmd_flags = BCE_NVM_COMMAND_FIRST; 2325 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2326 int j; 2327 2328 /* Read the whole page into the buffer 2329 * (non-buffer flash only) */ 2330 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2331 if (j == (sc->bce_flash_info->page_size - 4)) { 2332 cmd_flags |= BCE_NVM_COMMAND_LAST; 2333 } 2334 rc = bce_nvram_read_dword(sc, 2335 page_start + j, 2336 &flash_buffer[j], 2337 cmd_flags); 2338 2339 if (rc) 2340 goto bce_nvram_write_locked_exit; 2341 2342 cmd_flags = 0; 2343 } 2344 } 2345 2346 /* Enable writes to flash interface (unlock write-protect) */ 2347 if ((rc = bce_enable_nvram_write(sc)) != 0) 2348 goto bce_nvram_write_locked_exit; 2349 2350 /* Erase the page */ 2351 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2352 goto bce_nvram_write_locked_exit; 2353 2354 /* Re-enable the write again for the actual write */ 2355 bce_enable_nvram_write(sc); 2356 2357 /* Loop to write back the buffer data from page_start to 2358 * data_start */ 2359 i = 0; 2360 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2361 for (addr = page_start; addr < data_start; 2362 addr += 4, i += 4) { 2363 2364 rc = bce_nvram_write_dword(sc, addr, 2365 &flash_buffer[i], cmd_flags); 2366 2367 if (rc != 0) 2368 goto bce_nvram_write_locked_exit; 2369 2370 cmd_flags = 0; 2371 } 2372 } 2373 2374 /* Loop to write the new data from data_start to data_end */ 2375 for (addr = data_start; addr < data_end; addr += 4, i++) { 2376 if ((addr == page_end - 4) || 2377 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2378 (addr == data_end - 4))) { 2379 2380 cmd_flags |= BCE_NVM_COMMAND_LAST; 2381 } 2382 rc = bce_nvram_write_dword(sc, addr, buf, 2383 cmd_flags); 2384 2385 if (rc != 0) 2386 goto bce_nvram_write_locked_exit; 2387 2388 cmd_flags = 0; 2389 buf += 4; 2390 } 2391 2392 /* Loop to write back the buffer data from data_end 2393 * to page_end */ 2394 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2395 for (addr = data_end; addr < page_end; 2396 addr += 4, i += 4) { 2397 2398 if (addr == page_end-4) { 2399 cmd_flags = BCE_NVM_COMMAND_LAST; 2400 } 2401 rc = bce_nvram_write_dword(sc, addr, 2402 &flash_buffer[i], cmd_flags); 2403 2404 if (rc != 0) 2405 goto bce_nvram_write_locked_exit; 2406 2407 cmd_flags = 0; 2408 } 2409 } 2410 2411 /* Disable writes to flash interface (lock write-protect) */ 2412 bce_disable_nvram_write(sc); 2413 2414 /* Disable access to flash interface */ 2415 bce_disable_nvram_access(sc); 2416 bce_release_nvram_lock(sc); 2417 2418 /* Increment written */ 2419 written += data_end - data_start; 2420 } 2421 2422 goto bce_nvram_write_exit; 2423 2424 bce_nvram_write_locked_exit: 2425 bce_disable_nvram_write(sc); 2426 bce_disable_nvram_access(sc); 2427 bce_release_nvram_lock(sc); 2428 2429 bce_nvram_write_exit: 2430 if (align_start || align_end) 2431 free(buf, M_DEVBUF); 2432 2433 DBEXIT(BCE_VERBOSE_NVRAM); 2434 return (rc); 2435 } 2436 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2437 2438 2439 /****************************************************************************/ 2440 /* Verifies that NVRAM is accessible and contains valid data. */ 2441 /* */ 2442 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2443 /* correct. */ 2444 /* */ 2445 /* Returns: */ 2446 /* 0 on success, positive value on failure. */ 2447 /****************************************************************************/ 2448 static int 2449 bce_nvram_test(struct bce_softc *sc) 2450 { 2451 u32 buf[BCE_NVRAM_SIZE / 4]; 2452 u8 *data = (u8 *) buf; 2453 int rc = 0; 2454 u32 magic, csum; 2455 2456 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2457 2458 /* 2459 * Check that the device NVRAM is valid by reading 2460 * the magic value at offset 0. 2461 */ 2462 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2463 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", __FILE__, __LINE__); 2464 goto bce_nvram_test_exit; 2465 } 2466 2467 /* 2468 * Verify that offset 0 of the NVRAM contains 2469 * a valid magic number. 2470 */ 2471 magic = bce_be32toh(buf[0]); 2472 if (magic != BCE_NVRAM_MAGIC) { 2473 rc = ENODEV; 2474 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, " 2475 "Found: 0x%08X\n", 2476 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2477 goto bce_nvram_test_exit; 2478 } 2479 2480 /* 2481 * Verify that the device NVRAM includes valid 2482 * configuration data. 2483 */ 2484 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2485 BCE_PRINTF("%s(%d): Unable to read Manufacturing Information from " 2486 "NVRAM!\n", __FILE__, __LINE__); 2487 goto bce_nvram_test_exit; 2488 } 2489 2490 csum = ether_crc32_le(data, 0x100); 2491 if (csum != BCE_CRC32_RESIDUAL) { 2492 rc = ENODEV; 2493 BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! " 2494 "Expected: 0x%08X, Found: 0x%08X\n", 2495 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2496 goto bce_nvram_test_exit; 2497 } 2498 2499 csum = ether_crc32_le(data + 0x100, 0x100); 2500 if (csum != BCE_CRC32_RESIDUAL) { 2501 rc = ENODEV; 2502 BCE_PRINTF("%s(%d): Invalid Feature Configuration Information " 2503 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2504 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2505 } 2506 2507 bce_nvram_test_exit: 2508 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2509 return rc; 2510 } 2511 2512 2513 /****************************************************************************/ 2514 /* Identifies the current media type of the controller and sets the PHY */ 2515 /* address. */ 2516 /* */ 2517 /* Returns: */ 2518 /* Nothing. */ 2519 /****************************************************************************/ 2520 static void 2521 bce_get_media(struct bce_softc *sc) 2522 { 2523 u32 val; 2524 2525 DBENTER(BCE_VERBOSE); 2526 2527 /* Assume PHY address for copper controllers. */ 2528 sc->bce_phy_addr = 1; 2529 2530 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2531 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 2532 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 2533 u32 strap; 2534 2535 /* 2536 * The BCM5709S is software configurable 2537 * for Copper or SerDes operation. 2538 */ 2539 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 2540 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for copper.\n"); 2541 goto bce_get_media_exit; 2542 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 2543 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for dual media.\n"); 2544 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2545 goto bce_get_media_exit; 2546 } 2547 2548 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 2549 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 2550 else 2551 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 2552 2553 if (pci_get_function(sc->bce_dev) == 0) { 2554 switch (strap) { 2555 case 0x4: 2556 case 0x5: 2557 case 0x6: 2558 DBPRINT(sc, BCE_INFO_LOAD, 2559 "BCM5709 s/w configured for SerDes.\n"); 2560 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2561 default: 2562 DBPRINT(sc, BCE_INFO_LOAD, 2563 "BCM5709 s/w configured for Copper.\n"); 2564 } 2565 } else { 2566 switch (strap) { 2567 case 0x1: 2568 case 0x2: 2569 case 0x4: 2570 DBPRINT(sc, BCE_INFO_LOAD, 2571 "BCM5709 s/w configured for SerDes.\n"); 2572 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2573 default: 2574 DBPRINT(sc, BCE_INFO_LOAD, 2575 "BCM5709 s/w configured for Copper.\n"); 2576 } 2577 } 2578 2579 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 2580 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 2581 2582 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 2583 sc->bce_flags |= BCE_NO_WOL_FLAG; 2584 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2585 sc->bce_phy_addr = 2; 2586 val = REG_RD_IND(sc, sc->bce_shmem_base + 2587 BCE_SHARED_HW_CFG_CONFIG); 2588 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 2589 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG; 2590 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb capable adapter\n"); 2591 } 2592 } 2593 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 2594 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 2595 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 2596 2597 bce_get_media_exit: 2598 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 2599 "Using PHY address %d.\n", sc->bce_phy_addr); 2600 2601 DBEXIT(BCE_VERBOSE); 2602 } 2603 2604 2605 /****************************************************************************/ 2606 /* Free any DMA memory owned by the driver. */ 2607 /* */ 2608 /* Scans through each data structre that requires DMA memory and frees */ 2609 /* the memory if allocated. */ 2610 /* */ 2611 /* Returns: */ 2612 /* Nothing. */ 2613 /****************************************************************************/ 2614 static void 2615 bce_dma_free(struct bce_softc *sc) 2616 { 2617 int i; 2618 2619 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 2620 2621 /* Free, unmap, and destroy the status block. */ 2622 if (sc->status_block != NULL) { 2623 bus_dmamem_free( 2624 sc->status_tag, 2625 sc->status_block, 2626 sc->status_map); 2627 sc->status_block = NULL; 2628 } 2629 2630 if (sc->status_map != NULL) { 2631 bus_dmamap_unload( 2632 sc->status_tag, 2633 sc->status_map); 2634 bus_dmamap_destroy(sc->status_tag, 2635 sc->status_map); 2636 sc->status_map = NULL; 2637 } 2638 2639 if (sc->status_tag != NULL) { 2640 bus_dma_tag_destroy(sc->status_tag); 2641 sc->status_tag = NULL; 2642 } 2643 2644 2645 /* Free, unmap, and destroy the statistics block. */ 2646 if (sc->stats_block != NULL) { 2647 bus_dmamem_free( 2648 sc->stats_tag, 2649 sc->stats_block, 2650 sc->stats_map); 2651 sc->stats_block = NULL; 2652 } 2653 2654 if (sc->stats_map != NULL) { 2655 bus_dmamap_unload( 2656 sc->stats_tag, 2657 sc->stats_map); 2658 bus_dmamap_destroy(sc->stats_tag, 2659 sc->stats_map); 2660 sc->stats_map = NULL; 2661 } 2662 2663 if (sc->stats_tag != NULL) { 2664 bus_dma_tag_destroy(sc->stats_tag); 2665 sc->stats_tag = NULL; 2666 } 2667 2668 2669 /* Free, unmap and destroy all context memory pages. */ 2670 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 2671 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 2672 for (i = 0; i < sc->ctx_pages; i++ ) { 2673 if (sc->ctx_block[i] != NULL) { 2674 bus_dmamem_free( 2675 sc->ctx_tag, 2676 sc->ctx_block[i], 2677 sc->ctx_map[i]); 2678 sc->ctx_block[i] = NULL; 2679 } 2680 2681 if (sc->ctx_map[i] != NULL) { 2682 bus_dmamap_unload( 2683 sc->ctx_tag, 2684 sc->ctx_map[i]); 2685 bus_dmamap_destroy( 2686 sc->ctx_tag, 2687 sc->ctx_map[i]); 2688 sc->ctx_map[i] = NULL; 2689 } 2690 } 2691 2692 /* Destroy the context memory tag. */ 2693 if (sc->ctx_tag != NULL) { 2694 bus_dma_tag_destroy(sc->ctx_tag); 2695 sc->ctx_tag = NULL; 2696 } 2697 } 2698 2699 2700 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2701 for (i = 0; i < TX_PAGES; i++ ) { 2702 if (sc->tx_bd_chain[i] != NULL) { 2703 bus_dmamem_free( 2704 sc->tx_bd_chain_tag, 2705 sc->tx_bd_chain[i], 2706 sc->tx_bd_chain_map[i]); 2707 sc->tx_bd_chain[i] = NULL; 2708 } 2709 2710 if (sc->tx_bd_chain_map[i] != NULL) { 2711 bus_dmamap_unload( 2712 sc->tx_bd_chain_tag, 2713 sc->tx_bd_chain_map[i]); 2714 bus_dmamap_destroy( 2715 sc->tx_bd_chain_tag, 2716 sc->tx_bd_chain_map[i]); 2717 sc->tx_bd_chain_map[i] = NULL; 2718 } 2719 } 2720 2721 /* Destroy the TX buffer descriptor tag. */ 2722 if (sc->tx_bd_chain_tag != NULL) { 2723 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2724 sc->tx_bd_chain_tag = NULL; 2725 } 2726 2727 2728 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2729 for (i = 0; i < RX_PAGES; i++ ) { 2730 if (sc->rx_bd_chain[i] != NULL) { 2731 bus_dmamem_free( 2732 sc->rx_bd_chain_tag, 2733 sc->rx_bd_chain[i], 2734 sc->rx_bd_chain_map[i]); 2735 sc->rx_bd_chain[i] = NULL; 2736 } 2737 2738 if (sc->rx_bd_chain_map[i] != NULL) { 2739 bus_dmamap_unload( 2740 sc->rx_bd_chain_tag, 2741 sc->rx_bd_chain_map[i]); 2742 bus_dmamap_destroy( 2743 sc->rx_bd_chain_tag, 2744 sc->rx_bd_chain_map[i]); 2745 sc->rx_bd_chain_map[i] = NULL; 2746 } 2747 } 2748 2749 /* Destroy the RX buffer descriptor tag. */ 2750 if (sc->rx_bd_chain_tag != NULL) { 2751 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2752 sc->rx_bd_chain_tag = NULL; 2753 } 2754 2755 2756 #ifdef ZERO_COPY_SOCKETS 2757 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 2758 for (i = 0; i < PG_PAGES; i++ ) { 2759 if (sc->pg_bd_chain[i] != NULL) { 2760 bus_dmamem_free( 2761 sc->pg_bd_chain_tag, 2762 sc->pg_bd_chain[i], 2763 sc->pg_bd_chain_map[i]); 2764 sc->pg_bd_chain[i] = NULL; 2765 } 2766 2767 if (sc->pg_bd_chain_map[i] != NULL) { 2768 bus_dmamap_unload( 2769 sc->pg_bd_chain_tag, 2770 sc->pg_bd_chain_map[i]); 2771 bus_dmamap_destroy( 2772 sc->pg_bd_chain_tag, 2773 sc->pg_bd_chain_map[i]); 2774 sc->pg_bd_chain_map[i] = NULL; 2775 } 2776 } 2777 2778 /* Destroy the page buffer descriptor tag. */ 2779 if (sc->pg_bd_chain_tag != NULL) { 2780 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 2781 sc->pg_bd_chain_tag = NULL; 2782 } 2783 #endif 2784 2785 2786 /* Unload and destroy the TX mbuf maps. */ 2787 for (i = 0; i < TOTAL_TX_BD; i++) { 2788 if (sc->tx_mbuf_map[i] != NULL) { 2789 bus_dmamap_unload(sc->tx_mbuf_tag, 2790 sc->tx_mbuf_map[i]); 2791 bus_dmamap_destroy(sc->tx_mbuf_tag, 2792 sc->tx_mbuf_map[i]); 2793 sc->tx_mbuf_map[i] = NULL; 2794 } 2795 } 2796 2797 /* Destroy the TX mbuf tag. */ 2798 if (sc->tx_mbuf_tag != NULL) { 2799 bus_dma_tag_destroy(sc->tx_mbuf_tag); 2800 sc->tx_mbuf_tag = NULL; 2801 } 2802 2803 /* Unload and destroy the RX mbuf maps. */ 2804 for (i = 0; i < TOTAL_RX_BD; i++) { 2805 if (sc->rx_mbuf_map[i] != NULL) { 2806 bus_dmamap_unload(sc->rx_mbuf_tag, 2807 sc->rx_mbuf_map[i]); 2808 bus_dmamap_destroy(sc->rx_mbuf_tag, 2809 sc->rx_mbuf_map[i]); 2810 sc->rx_mbuf_map[i] = NULL; 2811 } 2812 } 2813 2814 /* Destroy the RX mbuf tag. */ 2815 if (sc->rx_mbuf_tag != NULL) { 2816 bus_dma_tag_destroy(sc->rx_mbuf_tag); 2817 sc->rx_mbuf_tag = NULL; 2818 } 2819 2820 #ifdef ZERO_COPY_SOCKETS 2821 /* Unload and destroy the page mbuf maps. */ 2822 for (i = 0; i < TOTAL_PG_BD; i++) { 2823 if (sc->pg_mbuf_map[i] != NULL) { 2824 bus_dmamap_unload(sc->pg_mbuf_tag, 2825 sc->pg_mbuf_map[i]); 2826 bus_dmamap_destroy(sc->pg_mbuf_tag, 2827 sc->pg_mbuf_map[i]); 2828 sc->pg_mbuf_map[i] = NULL; 2829 } 2830 } 2831 2832 /* Destroy the page mbuf tag. */ 2833 if (sc->pg_mbuf_tag != NULL) { 2834 bus_dma_tag_destroy(sc->pg_mbuf_tag); 2835 sc->pg_mbuf_tag = NULL; 2836 } 2837 #endif 2838 2839 /* Destroy the parent tag */ 2840 if (sc->parent_tag != NULL) { 2841 bus_dma_tag_destroy(sc->parent_tag); 2842 sc->parent_tag = NULL; 2843 } 2844 2845 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 2846 } 2847 2848 2849 /****************************************************************************/ 2850 /* Get DMA memory from the OS. */ 2851 /* */ 2852 /* Validates that the OS has provided DMA buffers in response to a */ 2853 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 2854 /* When the callback is used the OS will return 0 for the mapping function */ 2855 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 2856 /* failures back to the caller. */ 2857 /* */ 2858 /* Returns: */ 2859 /* Nothing. */ 2860 /****************************************************************************/ 2861 static void 2862 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2863 { 2864 bus_addr_t *busaddr = arg; 2865 2866 /* Simulate a mapping failure. */ 2867 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 2868 error = ENOMEM); 2869 2870 /* Check for an error and signal the caller that an error occurred. */ 2871 if (error) { 2872 *busaddr = 0; 2873 } else { 2874 *busaddr = segs->ds_addr; 2875 } 2876 2877 return; 2878 } 2879 2880 2881 /****************************************************************************/ 2882 /* Allocate any DMA memory needed by the driver. */ 2883 /* */ 2884 /* Allocates DMA memory needed for the various global structures needed by */ 2885 /* hardware. */ 2886 /* */ 2887 /* Memory alignment requirements: */ 2888 /* +-----------------+----------+----------+----------+----------+ */ 2889 /* | | 5706 | 5708 | 5709 | 5716 | */ 2890 /* +-----------------+----------+----------+----------+----------+ */ 2891 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 2892 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 2893 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 2894 /* |PG Buffers | none | none | none | none | */ 2895 /* |TX Buffers | none | none | none | none | */ 2896 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 2897 /* +-----------------+----------+----------+----------+----------+ */ 2898 /* */ 2899 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 2900 /* */ 2901 /* Returns: */ 2902 /* 0 for success, positive value for failure. */ 2903 /****************************************************************************/ 2904 static int 2905 bce_dma_alloc(device_t dev) 2906 { 2907 struct bce_softc *sc; 2908 int i, error, rc = 0; 2909 bus_size_t max_size, max_seg_size; 2910 int max_segments; 2911 2912 sc = device_get_softc(dev); 2913 2914 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 2915 2916 /* 2917 * Allocate the parent bus DMA tag appropriate for PCI. 2918 */ 2919 if (bus_dma_tag_create(NULL, 2920 1, 2921 BCE_DMA_BOUNDARY, 2922 sc->max_bus_addr, 2923 BUS_SPACE_MAXADDR, 2924 NULL, NULL, 2925 MAXBSIZE, 2926 BUS_SPACE_UNRESTRICTED, 2927 BUS_SPACE_MAXSIZE_32BIT, 2928 0, 2929 NULL, NULL, 2930 &sc->parent_tag)) { 2931 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 2932 __FILE__, __LINE__); 2933 rc = ENOMEM; 2934 goto bce_dma_alloc_exit; 2935 } 2936 2937 /* 2938 * Create a DMA tag for the status block, allocate and clear the 2939 * memory, map the memory into DMA space, and fetch the physical 2940 * address of the block. 2941 */ 2942 if (bus_dma_tag_create(sc->parent_tag, 2943 BCE_DMA_ALIGN, 2944 BCE_DMA_BOUNDARY, 2945 sc->max_bus_addr, 2946 BUS_SPACE_MAXADDR, 2947 NULL, NULL, 2948 BCE_STATUS_BLK_SZ, 2949 1, 2950 BCE_STATUS_BLK_SZ, 2951 0, 2952 NULL, NULL, 2953 &sc->status_tag)) { 2954 BCE_PRINTF("%s(%d): Could not allocate status block DMA tag!\n", 2955 __FILE__, __LINE__); 2956 rc = ENOMEM; 2957 goto bce_dma_alloc_exit; 2958 } 2959 2960 if(bus_dmamem_alloc(sc->status_tag, 2961 (void **)&sc->status_block, 2962 BUS_DMA_NOWAIT, 2963 &sc->status_map)) { 2964 BCE_PRINTF("%s(%d): Could not allocate status block DMA memory!\n", 2965 __FILE__, __LINE__); 2966 rc = ENOMEM; 2967 goto bce_dma_alloc_exit; 2968 } 2969 2970 bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 2971 2972 error = bus_dmamap_load(sc->status_tag, 2973 sc->status_map, 2974 sc->status_block, 2975 BCE_STATUS_BLK_SZ, 2976 bce_dma_map_addr, 2977 &sc->status_block_paddr, 2978 BUS_DMA_NOWAIT); 2979 2980 if (error) { 2981 BCE_PRINTF("%s(%d): Could not map status block DMA memory!\n", 2982 __FILE__, __LINE__); 2983 rc = ENOMEM; 2984 goto bce_dma_alloc_exit; 2985 } 2986 2987 DBPRINT(sc, BCE_INFO, "%s(): status_block_paddr = 0x%jX\n", 2988 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 2989 2990 /* 2991 * Create a DMA tag for the statistics block, allocate and clear the 2992 * memory, map the memory into DMA space, and fetch the physical 2993 * address of the block. 2994 */ 2995 if (bus_dma_tag_create(sc->parent_tag, 2996 BCE_DMA_ALIGN, 2997 BCE_DMA_BOUNDARY, 2998 sc->max_bus_addr, 2999 BUS_SPACE_MAXADDR, 3000 NULL, NULL, 3001 BCE_STATS_BLK_SZ, 3002 1, 3003 BCE_STATS_BLK_SZ, 3004 0, 3005 NULL, NULL, 3006 &sc->stats_tag)) { 3007 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA tag!\n", 3008 __FILE__, __LINE__); 3009 rc = ENOMEM; 3010 goto bce_dma_alloc_exit; 3011 } 3012 3013 if (bus_dmamem_alloc(sc->stats_tag, 3014 (void **)&sc->stats_block, 3015 BUS_DMA_NOWAIT, 3016 &sc->stats_map)) { 3017 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA memory!\n", 3018 __FILE__, __LINE__); 3019 rc = ENOMEM; 3020 goto bce_dma_alloc_exit; 3021 } 3022 3023 bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 3024 3025 error = bus_dmamap_load(sc->stats_tag, 3026 sc->stats_map, 3027 sc->stats_block, 3028 BCE_STATS_BLK_SZ, 3029 bce_dma_map_addr, 3030 &sc->stats_block_paddr, 3031 BUS_DMA_NOWAIT); 3032 3033 if(error) { 3034 BCE_PRINTF("%s(%d): Could not map statistics block DMA memory!\n", 3035 __FILE__, __LINE__); 3036 rc = ENOMEM; 3037 goto bce_dma_alloc_exit; 3038 } 3039 3040 DBPRINT(sc, BCE_INFO, "%s(): stats_block_paddr = 0x%jX\n", 3041 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3042 3043 /* BCM5709 uses host memory as cache for context memory. */ 3044 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3045 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3046 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3047 if (sc->ctx_pages == 0) 3048 sc->ctx_pages = 1; 3049 3050 DBRUNIF((sc->ctx_pages > 512), 3051 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3052 __FILE__, __LINE__, sc->ctx_pages)); 3053 3054 /* 3055 * Create a DMA tag for the context pages, 3056 * allocate and clear the memory, map the 3057 * memory into DMA space, and fetch the 3058 * physical address of the block. 3059 */ 3060 if(bus_dma_tag_create(sc->parent_tag, 3061 BCM_PAGE_SIZE, 3062 BCE_DMA_BOUNDARY, 3063 sc->max_bus_addr, 3064 BUS_SPACE_MAXADDR, 3065 NULL, NULL, 3066 BCM_PAGE_SIZE, 3067 1, 3068 BCM_PAGE_SIZE, 3069 0, 3070 NULL, NULL, 3071 &sc->ctx_tag)) { 3072 BCE_PRINTF("%s(%d): Could not allocate CTX DMA tag!\n", 3073 __FILE__, __LINE__); 3074 rc = ENOMEM; 3075 goto bce_dma_alloc_exit; 3076 } 3077 3078 for (i = 0; i < sc->ctx_pages; i++) { 3079 3080 if(bus_dmamem_alloc(sc->ctx_tag, 3081 (void **)&sc->ctx_block[i], 3082 BUS_DMA_NOWAIT, 3083 &sc->ctx_map[i])) { 3084 BCE_PRINTF("%s(%d): Could not allocate CTX " 3085 "DMA memory!\n", __FILE__, __LINE__); 3086 rc = ENOMEM; 3087 goto bce_dma_alloc_exit; 3088 } 3089 3090 bzero((char *)sc->ctx_block[i], BCM_PAGE_SIZE); 3091 3092 error = bus_dmamap_load(sc->ctx_tag, 3093 sc->ctx_map[i], 3094 sc->ctx_block[i], 3095 BCM_PAGE_SIZE, 3096 bce_dma_map_addr, 3097 &sc->ctx_paddr[i], 3098 BUS_DMA_NOWAIT); 3099 3100 if (error) { 3101 BCE_PRINTF("%s(%d): Could not map CTX DMA memory!\n", 3102 __FILE__, __LINE__); 3103 rc = ENOMEM; 3104 goto bce_dma_alloc_exit; 3105 } 3106 3107 DBPRINT(sc, BCE_INFO, "%s(): ctx_paddr[%d] = 0x%jX\n", 3108 __FUNCTION__, i, (uintmax_t) sc->ctx_paddr[i]); 3109 } 3110 } 3111 3112 /* 3113 * Create a DMA tag for the TX buffer descriptor chain, 3114 * allocate and clear the memory, and fetch the 3115 * physical address of the block. 3116 */ 3117 if(bus_dma_tag_create(sc->parent_tag, 3118 BCM_PAGE_SIZE, 3119 BCE_DMA_BOUNDARY, 3120 sc->max_bus_addr, 3121 BUS_SPACE_MAXADDR, 3122 NULL, NULL, 3123 BCE_TX_CHAIN_PAGE_SZ, 3124 1, 3125 BCE_TX_CHAIN_PAGE_SZ, 3126 0, 3127 NULL, NULL, 3128 &sc->tx_bd_chain_tag)) { 3129 BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain DMA tag!\n", 3130 __FILE__, __LINE__); 3131 rc = ENOMEM; 3132 goto bce_dma_alloc_exit; 3133 } 3134 3135 for (i = 0; i < TX_PAGES; i++) { 3136 3137 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3138 (void **)&sc->tx_bd_chain[i], 3139 BUS_DMA_NOWAIT, 3140 &sc->tx_bd_chain_map[i])) { 3141 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3142 "chain DMA memory!\n", __FILE__, __LINE__); 3143 rc = ENOMEM; 3144 goto bce_dma_alloc_exit; 3145 } 3146 3147 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3148 sc->tx_bd_chain_map[i], 3149 sc->tx_bd_chain[i], 3150 BCE_TX_CHAIN_PAGE_SZ, 3151 bce_dma_map_addr, 3152 &sc->tx_bd_chain_paddr[i], 3153 BUS_DMA_NOWAIT); 3154 3155 if (error) { 3156 BCE_PRINTF("%s(%d): Could not map TX descriptor chain DMA memory!\n", 3157 __FILE__, __LINE__); 3158 rc = ENOMEM; 3159 goto bce_dma_alloc_exit; 3160 } 3161 3162 DBPRINT(sc, BCE_INFO, "%s(): tx_bd_chain_paddr[%d] = 0x%jX\n", 3163 __FUNCTION__, i, (uintmax_t) sc->tx_bd_chain_paddr[i]); 3164 } 3165 3166 /* Check the required size before mapping to conserve resources. */ 3167 if (bce_tso_enable) { 3168 max_size = BCE_TSO_MAX_SIZE; 3169 max_segments = BCE_MAX_SEGMENTS; 3170 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3171 } else { 3172 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3173 max_segments = BCE_MAX_SEGMENTS; 3174 max_seg_size = MCLBYTES; 3175 } 3176 3177 /* Create a DMA tag for TX mbufs. */ 3178 if (bus_dma_tag_create(sc->parent_tag, 3179 1, 3180 BCE_DMA_BOUNDARY, 3181 sc->max_bus_addr, 3182 BUS_SPACE_MAXADDR, 3183 NULL, NULL, 3184 max_size, 3185 max_segments, 3186 max_seg_size, 3187 0, 3188 NULL, NULL, 3189 &sc->tx_mbuf_tag)) { 3190 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3191 __FILE__, __LINE__); 3192 rc = ENOMEM; 3193 goto bce_dma_alloc_exit; 3194 } 3195 3196 /* Create DMA maps for the TX mbufs clusters. */ 3197 for (i = 0; i < TOTAL_TX_BD; i++) { 3198 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3199 &sc->tx_mbuf_map[i])) { 3200 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA map!\n", 3201 __FILE__, __LINE__); 3202 rc = ENOMEM; 3203 goto bce_dma_alloc_exit; 3204 } 3205 } 3206 3207 /* 3208 * Create a DMA tag for the RX buffer descriptor chain, 3209 * allocate and clear the memory, and fetch the physical 3210 * address of the blocks. 3211 */ 3212 if (bus_dma_tag_create(sc->parent_tag, 3213 BCM_PAGE_SIZE, 3214 BCE_DMA_BOUNDARY, 3215 BUS_SPACE_MAXADDR, 3216 sc->max_bus_addr, 3217 NULL, NULL, 3218 BCE_RX_CHAIN_PAGE_SZ, 3219 1, 3220 BCE_RX_CHAIN_PAGE_SZ, 3221 0, 3222 NULL, NULL, 3223 &sc->rx_bd_chain_tag)) { 3224 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain DMA tag!\n", 3225 __FILE__, __LINE__); 3226 rc = ENOMEM; 3227 goto bce_dma_alloc_exit; 3228 } 3229 3230 for (i = 0; i < RX_PAGES; i++) { 3231 3232 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3233 (void **)&sc->rx_bd_chain[i], 3234 BUS_DMA_NOWAIT, 3235 &sc->rx_bd_chain_map[i])) { 3236 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3237 "DMA memory!\n", __FILE__, __LINE__); 3238 rc = ENOMEM; 3239 goto bce_dma_alloc_exit; 3240 } 3241 3242 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3243 3244 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3245 sc->rx_bd_chain_map[i], 3246 sc->rx_bd_chain[i], 3247 BCE_RX_CHAIN_PAGE_SZ, 3248 bce_dma_map_addr, 3249 &sc->rx_bd_chain_paddr[i], 3250 BUS_DMA_NOWAIT); 3251 3252 if (error) { 3253 BCE_PRINTF("%s(%d): Could not map RX descriptor chain DMA memory!\n", 3254 __FILE__, __LINE__); 3255 rc = ENOMEM; 3256 goto bce_dma_alloc_exit; 3257 } 3258 3259 DBPRINT(sc, BCE_INFO, "%s(): rx_bd_chain_paddr[%d] = 0x%jX\n", 3260 __FUNCTION__, i, (uintmax_t) sc->rx_bd_chain_paddr[i]); 3261 } 3262 3263 /* 3264 * Create a DMA tag for RX mbufs. 3265 */ 3266 #ifdef ZERO_COPY_SOCKETS 3267 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3268 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3269 #else 3270 max_size = max_seg_size = MJUM9BYTES; 3271 #endif 3272 max_segments = 1; 3273 3274 DBPRINT(sc, BCE_INFO, "%s(): Creating rx_mbuf_tag (max size = 0x%jX " 3275 "max segments = %d, max segment size = 0x%jX)\n", __FUNCTION__, 3276 (uintmax_t) max_size, max_segments, (uintmax_t) max_seg_size); 3277 3278 if (bus_dma_tag_create(sc->parent_tag, 3279 1, 3280 BCE_DMA_BOUNDARY, 3281 sc->max_bus_addr, 3282 BUS_SPACE_MAXADDR, 3283 NULL, NULL, 3284 max_size, 3285 max_segments, 3286 max_seg_size, 3287 0, 3288 NULL, NULL, 3289 &sc->rx_mbuf_tag)) { 3290 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3291 __FILE__, __LINE__); 3292 rc = ENOMEM; 3293 goto bce_dma_alloc_exit; 3294 } 3295 3296 /* Create DMA maps for the RX mbuf clusters. */ 3297 for (i = 0; i < TOTAL_RX_BD; i++) { 3298 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3299 &sc->rx_mbuf_map[i])) { 3300 BCE_PRINTF("%s(%d): Unable to create RX mbuf DMA map!\n", 3301 __FILE__, __LINE__); 3302 rc = ENOMEM; 3303 goto bce_dma_alloc_exit; 3304 } 3305 } 3306 3307 #ifdef ZERO_COPY_SOCKETS 3308 /* 3309 * Create a DMA tag for the page buffer descriptor chain, 3310 * allocate and clear the memory, and fetch the physical 3311 * address of the blocks. 3312 */ 3313 if (bus_dma_tag_create(sc->parent_tag, 3314 BCM_PAGE_SIZE, 3315 BCE_DMA_BOUNDARY, 3316 BUS_SPACE_MAXADDR, 3317 sc->max_bus_addr, 3318 NULL, NULL, 3319 BCE_PG_CHAIN_PAGE_SZ, 3320 1, 3321 BCE_PG_CHAIN_PAGE_SZ, 3322 0, 3323 NULL, NULL, 3324 &sc->pg_bd_chain_tag)) { 3325 BCE_PRINTF("%s(%d): Could not allocate page descriptor chain DMA tag!\n", 3326 __FILE__, __LINE__); 3327 rc = ENOMEM; 3328 goto bce_dma_alloc_exit; 3329 } 3330 3331 for (i = 0; i < PG_PAGES; i++) { 3332 3333 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3334 (void **)&sc->pg_bd_chain[i], 3335 BUS_DMA_NOWAIT, 3336 &sc->pg_bd_chain_map[i])) { 3337 BCE_PRINTF("%s(%d): Could not allocate page descriptor chain " 3338 "DMA memory!\n", __FILE__, __LINE__); 3339 rc = ENOMEM; 3340 goto bce_dma_alloc_exit; 3341 } 3342 3343 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 3344 3345 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3346 sc->pg_bd_chain_map[i], 3347 sc->pg_bd_chain[i], 3348 BCE_PG_CHAIN_PAGE_SZ, 3349 bce_dma_map_addr, 3350 &sc->pg_bd_chain_paddr[i], 3351 BUS_DMA_NOWAIT); 3352 3353 if (error) { 3354 BCE_PRINTF("%s(%d): Could not map page descriptor chain DMA memory!\n", 3355 __FILE__, __LINE__); 3356 rc = ENOMEM; 3357 goto bce_dma_alloc_exit; 3358 } 3359 3360 DBPRINT(sc, BCE_INFO, "%s(): pg_bd_chain_paddr[%d] = 0x%jX\n", 3361 __FUNCTION__, i, (uintmax_t) sc->pg_bd_chain_paddr[i]); 3362 } 3363 3364 /* 3365 * Create a DMA tag for page mbufs. 3366 */ 3367 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3368 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3369 3370 if (bus_dma_tag_create(sc->parent_tag, 3371 1, 3372 BCE_DMA_BOUNDARY, 3373 sc->max_bus_addr, 3374 BUS_SPACE_MAXADDR, 3375 NULL, NULL, 3376 max_size, 3377 1, 3378 max_seg_size, 3379 0, 3380 NULL, NULL, 3381 &sc->pg_mbuf_tag)) { 3382 BCE_PRINTF("%s(%d): Could not allocate page mbuf DMA tag!\n", 3383 __FILE__, __LINE__); 3384 rc = ENOMEM; 3385 goto bce_dma_alloc_exit; 3386 } 3387 3388 /* Create DMA maps for the page mbuf clusters. */ 3389 for (i = 0; i < TOTAL_PG_BD; i++) { 3390 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3391 &sc->pg_mbuf_map[i])) { 3392 BCE_PRINTF("%s(%d): Unable to create page mbuf DMA map!\n", 3393 __FILE__, __LINE__); 3394 rc = ENOMEM; 3395 goto bce_dma_alloc_exit; 3396 } 3397 } 3398 #endif 3399 3400 bce_dma_alloc_exit: 3401 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3402 return(rc); 3403 } 3404 3405 3406 /****************************************************************************/ 3407 /* Release all resources used by the driver. */ 3408 /* */ 3409 /* Releases all resources acquired by the driver including interrupts, */ 3410 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3411 /* */ 3412 /* Returns: */ 3413 /* Nothing. */ 3414 /****************************************************************************/ 3415 static void 3416 bce_release_resources(struct bce_softc *sc) 3417 { 3418 device_t dev; 3419 3420 DBENTER(BCE_VERBOSE_RESET); 3421 3422 dev = sc->bce_dev; 3423 3424 bce_dma_free(sc); 3425 3426 if (sc->bce_intrhand != NULL) { 3427 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3428 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3429 } 3430 3431 if (sc->bce_res_irq != NULL) { 3432 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3433 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3434 sc->bce_res_irq); 3435 } 3436 3437 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3438 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3439 pci_release_msi(dev); 3440 } 3441 3442 if (sc->bce_res_mem != NULL) { 3443 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3444 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bce_res_mem); 3445 } 3446 3447 if (sc->bce_ifp != NULL) { 3448 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3449 if_free(sc->bce_ifp); 3450 } 3451 3452 if (mtx_initialized(&sc->bce_mtx)) 3453 BCE_LOCK_DESTROY(sc); 3454 3455 DBEXIT(BCE_VERBOSE_RESET); 3456 } 3457 3458 3459 /****************************************************************************/ 3460 /* Firmware synchronization. */ 3461 /* */ 3462 /* Before performing certain events such as a chip reset, synchronize with */ 3463 /* the firmware first. */ 3464 /* */ 3465 /* Returns: */ 3466 /* 0 for success, positive value for failure. */ 3467 /****************************************************************************/ 3468 static int 3469 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3470 { 3471 int i, rc = 0; 3472 u32 val; 3473 3474 DBENTER(BCE_VERBOSE_RESET); 3475 3476 /* Don't waste any time if we've timed out before. */ 3477 if (sc->bce_fw_timed_out) { 3478 rc = EBUSY; 3479 goto bce_fw_sync_exit; 3480 } 3481 3482 /* Increment the message sequence number. */ 3483 sc->bce_fw_wr_seq++; 3484 msg_data |= sc->bce_fw_wr_seq; 3485 3486 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = 0x%08X\n", 3487 msg_data); 3488 3489 /* Send the message to the bootcode driver mailbox. */ 3490 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 3491 3492 /* Wait for the bootcode to acknowledge the message. */ 3493 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3494 /* Check for a response in the bootcode firmware mailbox. */ 3495 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB); 3496 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3497 break; 3498 DELAY(1000); 3499 } 3500 3501 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 3502 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3503 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3504 3505 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3506 "msg_data = 0x%08X\n", 3507 __FILE__, __LINE__, msg_data); 3508 3509 msg_data &= ~BCE_DRV_MSG_CODE; 3510 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3511 3512 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 3513 3514 sc->bce_fw_timed_out = 1; 3515 rc = EBUSY; 3516 } 3517 3518 bce_fw_sync_exit: 3519 DBEXIT(BCE_VERBOSE_RESET); 3520 return (rc); 3521 } 3522 3523 3524 /****************************************************************************/ 3525 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3526 /* */ 3527 /* Returns: */ 3528 /* Nothing. */ 3529 /****************************************************************************/ 3530 static void 3531 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3532 u32 rv2p_code_len, u32 rv2p_proc) 3533 { 3534 int i; 3535 u32 val; 3536 3537 DBENTER(BCE_VERBOSE_RESET); 3538 3539 /* Set the page size used by RV2P. */ 3540 if (rv2p_proc == RV2P_PROC2) { 3541 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3542 } 3543 3544 for (i = 0; i < rv2p_code_len; i += 8) { 3545 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3546 rv2p_code++; 3547 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3548 rv2p_code++; 3549 3550 if (rv2p_proc == RV2P_PROC1) { 3551 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3552 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3553 } 3554 else { 3555 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3556 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3557 } 3558 } 3559 3560 /* Reset the processor, un-stall is done later. */ 3561 if (rv2p_proc == RV2P_PROC1) { 3562 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 3563 } 3564 else { 3565 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 3566 } 3567 3568 DBEXIT(BCE_VERBOSE_RESET); 3569 } 3570 3571 3572 /****************************************************************************/ 3573 /* Load RISC processor firmware. */ 3574 /* */ 3575 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 3576 /* associated with a particular processor. */ 3577 /* */ 3578 /* Returns: */ 3579 /* Nothing. */ 3580 /****************************************************************************/ 3581 static void 3582 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 3583 struct fw_info *fw) 3584 { 3585 u32 offset; 3586 u32 val; 3587 3588 DBENTER(BCE_VERBOSE_RESET); 3589 3590 /* Halt the CPU. */ 3591 val = REG_RD_IND(sc, cpu_reg->mode); 3592 val |= cpu_reg->mode_value_halt; 3593 REG_WR_IND(sc, cpu_reg->mode, val); 3594 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3595 3596 /* Load the Text area. */ 3597 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 3598 if (fw->text) { 3599 int j; 3600 3601 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 3602 REG_WR_IND(sc, offset, fw->text[j]); 3603 } 3604 } 3605 3606 /* Load the Data area. */ 3607 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 3608 if (fw->data) { 3609 int j; 3610 3611 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 3612 REG_WR_IND(sc, offset, fw->data[j]); 3613 } 3614 } 3615 3616 /* Load the SBSS area. */ 3617 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 3618 if (fw->sbss) { 3619 int j; 3620 3621 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 3622 REG_WR_IND(sc, offset, fw->sbss[j]); 3623 } 3624 } 3625 3626 /* Load the BSS area. */ 3627 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 3628 if (fw->bss) { 3629 int j; 3630 3631 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 3632 REG_WR_IND(sc, offset, fw->bss[j]); 3633 } 3634 } 3635 3636 /* Load the Read-Only area. */ 3637 offset = cpu_reg->spad_base + 3638 (fw->rodata_addr - cpu_reg->mips_view_base); 3639 if (fw->rodata) { 3640 int j; 3641 3642 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 3643 REG_WR_IND(sc, offset, fw->rodata[j]); 3644 } 3645 } 3646 3647 /* Clear the pre-fetch instruction. */ 3648 REG_WR_IND(sc, cpu_reg->inst, 0); 3649 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 3650 3651 /* Start the CPU. */ 3652 val = REG_RD_IND(sc, cpu_reg->mode); 3653 val &= ~cpu_reg->mode_value_halt; 3654 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 3655 REG_WR_IND(sc, cpu_reg->mode, val); 3656 3657 DBEXIT(BCE_VERBOSE_RESET); 3658 } 3659 3660 3661 /****************************************************************************/ 3662 /* Initialize the RX CPU. */ 3663 /* */ 3664 /* Returns: */ 3665 /* Nothing. */ 3666 /****************************************************************************/ 3667 static void 3668 bce_init_rxp_cpu(struct bce_softc *sc) 3669 { 3670 struct cpu_reg cpu_reg; 3671 struct fw_info fw; 3672 3673 DBENTER(BCE_VERBOSE_RESET); 3674 3675 cpu_reg.mode = BCE_RXP_CPU_MODE; 3676 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 3677 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 3678 cpu_reg.state = BCE_RXP_CPU_STATE; 3679 cpu_reg.state_value_clear = 0xffffff; 3680 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 3681 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 3682 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 3683 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 3684 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 3685 cpu_reg.spad_base = BCE_RXP_SCRATCH; 3686 cpu_reg.mips_view_base = 0x8000000; 3687 3688 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3689 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3690 fw.ver_major = bce_RXP_b09FwReleaseMajor; 3691 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 3692 fw.ver_fix = bce_RXP_b09FwReleaseFix; 3693 fw.start_addr = bce_RXP_b09FwStartAddr; 3694 3695 fw.text_addr = bce_RXP_b09FwTextAddr; 3696 fw.text_len = bce_RXP_b09FwTextLen; 3697 fw.text_index = 0; 3698 fw.text = bce_RXP_b09FwText; 3699 3700 fw.data_addr = bce_RXP_b09FwDataAddr; 3701 fw.data_len = bce_RXP_b09FwDataLen; 3702 fw.data_index = 0; 3703 fw.data = bce_RXP_b09FwData; 3704 3705 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 3706 fw.sbss_len = bce_RXP_b09FwSbssLen; 3707 fw.sbss_index = 0; 3708 fw.sbss = bce_RXP_b09FwSbss; 3709 3710 fw.bss_addr = bce_RXP_b09FwBssAddr; 3711 fw.bss_len = bce_RXP_b09FwBssLen; 3712 fw.bss_index = 0; 3713 fw.bss = bce_RXP_b09FwBss; 3714 3715 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 3716 fw.rodata_len = bce_RXP_b09FwRodataLen; 3717 fw.rodata_index = 0; 3718 fw.rodata = bce_RXP_b09FwRodata; 3719 } else { 3720 fw.ver_major = bce_RXP_b06FwReleaseMajor; 3721 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 3722 fw.ver_fix = bce_RXP_b06FwReleaseFix; 3723 fw.start_addr = bce_RXP_b06FwStartAddr; 3724 3725 fw.text_addr = bce_RXP_b06FwTextAddr; 3726 fw.text_len = bce_RXP_b06FwTextLen; 3727 fw.text_index = 0; 3728 fw.text = bce_RXP_b06FwText; 3729 3730 fw.data_addr = bce_RXP_b06FwDataAddr; 3731 fw.data_len = bce_RXP_b06FwDataLen; 3732 fw.data_index = 0; 3733 fw.data = bce_RXP_b06FwData; 3734 3735 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 3736 fw.sbss_len = bce_RXP_b06FwSbssLen; 3737 fw.sbss_index = 0; 3738 fw.sbss = bce_RXP_b06FwSbss; 3739 3740 fw.bss_addr = bce_RXP_b06FwBssAddr; 3741 fw.bss_len = bce_RXP_b06FwBssLen; 3742 fw.bss_index = 0; 3743 fw.bss = bce_RXP_b06FwBss; 3744 3745 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 3746 fw.rodata_len = bce_RXP_b06FwRodataLen; 3747 fw.rodata_index = 0; 3748 fw.rodata = bce_RXP_b06FwRodata; 3749 } 3750 3751 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 3752 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3753 3754 DBEXIT(BCE_VERBOSE_RESET); 3755 } 3756 3757 3758 /****************************************************************************/ 3759 /* Initialize the TX CPU. */ 3760 /* */ 3761 /* Returns: */ 3762 /* Nothing. */ 3763 /****************************************************************************/ 3764 static void 3765 bce_init_txp_cpu(struct bce_softc *sc) 3766 { 3767 struct cpu_reg cpu_reg; 3768 struct fw_info fw; 3769 3770 DBENTER(BCE_VERBOSE_RESET); 3771 3772 cpu_reg.mode = BCE_TXP_CPU_MODE; 3773 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 3774 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 3775 cpu_reg.state = BCE_TXP_CPU_STATE; 3776 cpu_reg.state_value_clear = 0xffffff; 3777 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 3778 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 3779 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 3780 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 3781 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 3782 cpu_reg.spad_base = BCE_TXP_SCRATCH; 3783 cpu_reg.mips_view_base = 0x8000000; 3784 3785 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3786 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3787 fw.ver_major = bce_TXP_b09FwReleaseMajor; 3788 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 3789 fw.ver_fix = bce_TXP_b09FwReleaseFix; 3790 fw.start_addr = bce_TXP_b09FwStartAddr; 3791 3792 fw.text_addr = bce_TXP_b09FwTextAddr; 3793 fw.text_len = bce_TXP_b09FwTextLen; 3794 fw.text_index = 0; 3795 fw.text = bce_TXP_b09FwText; 3796 3797 fw.data_addr = bce_TXP_b09FwDataAddr; 3798 fw.data_len = bce_TXP_b09FwDataLen; 3799 fw.data_index = 0; 3800 fw.data = bce_TXP_b09FwData; 3801 3802 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 3803 fw.sbss_len = bce_TXP_b09FwSbssLen; 3804 fw.sbss_index = 0; 3805 fw.sbss = bce_TXP_b09FwSbss; 3806 3807 fw.bss_addr = bce_TXP_b09FwBssAddr; 3808 fw.bss_len = bce_TXP_b09FwBssLen; 3809 fw.bss_index = 0; 3810 fw.bss = bce_TXP_b09FwBss; 3811 3812 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 3813 fw.rodata_len = bce_TXP_b09FwRodataLen; 3814 fw.rodata_index = 0; 3815 fw.rodata = bce_TXP_b09FwRodata; 3816 } else { 3817 fw.ver_major = bce_TXP_b06FwReleaseMajor; 3818 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 3819 fw.ver_fix = bce_TXP_b06FwReleaseFix; 3820 fw.start_addr = bce_TXP_b06FwStartAddr; 3821 3822 fw.text_addr = bce_TXP_b06FwTextAddr; 3823 fw.text_len = bce_TXP_b06FwTextLen; 3824 fw.text_index = 0; 3825 fw.text = bce_TXP_b06FwText; 3826 3827 fw.data_addr = bce_TXP_b06FwDataAddr; 3828 fw.data_len = bce_TXP_b06FwDataLen; 3829 fw.data_index = 0; 3830 fw.data = bce_TXP_b06FwData; 3831 3832 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 3833 fw.sbss_len = bce_TXP_b06FwSbssLen; 3834 fw.sbss_index = 0; 3835 fw.sbss = bce_TXP_b06FwSbss; 3836 3837 fw.bss_addr = bce_TXP_b06FwBssAddr; 3838 fw.bss_len = bce_TXP_b06FwBssLen; 3839 fw.bss_index = 0; 3840 fw.bss = bce_TXP_b06FwBss; 3841 3842 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 3843 fw.rodata_len = bce_TXP_b06FwRodataLen; 3844 fw.rodata_index = 0; 3845 fw.rodata = bce_TXP_b06FwRodata; 3846 } 3847 3848 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 3849 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3850 3851 DBEXIT(BCE_VERBOSE_RESET); 3852 } 3853 3854 3855 /****************************************************************************/ 3856 /* Initialize the TPAT CPU. */ 3857 /* */ 3858 /* Returns: */ 3859 /* Nothing. */ 3860 /****************************************************************************/ 3861 static void 3862 bce_init_tpat_cpu(struct bce_softc *sc) 3863 { 3864 struct cpu_reg cpu_reg; 3865 struct fw_info fw; 3866 3867 DBENTER(BCE_VERBOSE_RESET); 3868 3869 cpu_reg.mode = BCE_TPAT_CPU_MODE; 3870 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 3871 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 3872 cpu_reg.state = BCE_TPAT_CPU_STATE; 3873 cpu_reg.state_value_clear = 0xffffff; 3874 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 3875 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 3876 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 3877 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 3878 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 3879 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 3880 cpu_reg.mips_view_base = 0x8000000; 3881 3882 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3883 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3884 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 3885 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 3886 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 3887 fw.start_addr = bce_TPAT_b09FwStartAddr; 3888 3889 fw.text_addr = bce_TPAT_b09FwTextAddr; 3890 fw.text_len = bce_TPAT_b09FwTextLen; 3891 fw.text_index = 0; 3892 fw.text = bce_TPAT_b09FwText; 3893 3894 fw.data_addr = bce_TPAT_b09FwDataAddr; 3895 fw.data_len = bce_TPAT_b09FwDataLen; 3896 fw.data_index = 0; 3897 fw.data = bce_TPAT_b09FwData; 3898 3899 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 3900 fw.sbss_len = bce_TPAT_b09FwSbssLen; 3901 fw.sbss_index = 0; 3902 fw.sbss = bce_TPAT_b09FwSbss; 3903 3904 fw.bss_addr = bce_TPAT_b09FwBssAddr; 3905 fw.bss_len = bce_TPAT_b09FwBssLen; 3906 fw.bss_index = 0; 3907 fw.bss = bce_TPAT_b09FwBss; 3908 3909 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 3910 fw.rodata_len = bce_TPAT_b09FwRodataLen; 3911 fw.rodata_index = 0; 3912 fw.rodata = bce_TPAT_b09FwRodata; 3913 } else { 3914 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 3915 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 3916 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 3917 fw.start_addr = bce_TPAT_b06FwStartAddr; 3918 3919 fw.text_addr = bce_TPAT_b06FwTextAddr; 3920 fw.text_len = bce_TPAT_b06FwTextLen; 3921 fw.text_index = 0; 3922 fw.text = bce_TPAT_b06FwText; 3923 3924 fw.data_addr = bce_TPAT_b06FwDataAddr; 3925 fw.data_len = bce_TPAT_b06FwDataLen; 3926 fw.data_index = 0; 3927 fw.data = bce_TPAT_b06FwData; 3928 3929 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 3930 fw.sbss_len = bce_TPAT_b06FwSbssLen; 3931 fw.sbss_index = 0; 3932 fw.sbss = bce_TPAT_b06FwSbss; 3933 3934 fw.bss_addr = bce_TPAT_b06FwBssAddr; 3935 fw.bss_len = bce_TPAT_b06FwBssLen; 3936 fw.bss_index = 0; 3937 fw.bss = bce_TPAT_b06FwBss; 3938 3939 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 3940 fw.rodata_len = bce_TPAT_b06FwRodataLen; 3941 fw.rodata_index = 0; 3942 fw.rodata = bce_TPAT_b06FwRodata; 3943 } 3944 3945 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 3946 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3947 3948 DBEXIT(BCE_VERBOSE_RESET); 3949 } 3950 3951 3952 /****************************************************************************/ 3953 /* Initialize the CP CPU. */ 3954 /* */ 3955 /* Returns: */ 3956 /* Nothing. */ 3957 /****************************************************************************/ 3958 static void 3959 bce_init_cp_cpu(struct bce_softc *sc) 3960 { 3961 struct cpu_reg cpu_reg; 3962 struct fw_info fw; 3963 3964 DBENTER(BCE_VERBOSE_RESET); 3965 3966 cpu_reg.mode = BCE_CP_CPU_MODE; 3967 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 3968 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 3969 cpu_reg.state = BCE_CP_CPU_STATE; 3970 cpu_reg.state_value_clear = 0xffffff; 3971 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 3972 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 3973 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 3974 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 3975 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 3976 cpu_reg.spad_base = BCE_CP_SCRATCH; 3977 cpu_reg.mips_view_base = 0x8000000; 3978 3979 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 3980 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 3981 fw.ver_major = bce_CP_b09FwReleaseMajor; 3982 fw.ver_minor = bce_CP_b09FwReleaseMinor; 3983 fw.ver_fix = bce_CP_b09FwReleaseFix; 3984 fw.start_addr = bce_CP_b09FwStartAddr; 3985 3986 fw.text_addr = bce_CP_b09FwTextAddr; 3987 fw.text_len = bce_CP_b09FwTextLen; 3988 fw.text_index = 0; 3989 fw.text = bce_CP_b09FwText; 3990 3991 fw.data_addr = bce_CP_b09FwDataAddr; 3992 fw.data_len = bce_CP_b09FwDataLen; 3993 fw.data_index = 0; 3994 fw.data = bce_CP_b09FwData; 3995 3996 fw.sbss_addr = bce_CP_b09FwSbssAddr; 3997 fw.sbss_len = bce_CP_b09FwSbssLen; 3998 fw.sbss_index = 0; 3999 fw.sbss = bce_CP_b09FwSbss; 4000 4001 fw.bss_addr = bce_CP_b09FwBssAddr; 4002 fw.bss_len = bce_CP_b09FwBssLen; 4003 fw.bss_index = 0; 4004 fw.bss = bce_CP_b09FwBss; 4005 4006 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4007 fw.rodata_len = bce_CP_b09FwRodataLen; 4008 fw.rodata_index = 0; 4009 fw.rodata = bce_CP_b09FwRodata; 4010 } else { 4011 fw.ver_major = bce_CP_b06FwReleaseMajor; 4012 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4013 fw.ver_fix = bce_CP_b06FwReleaseFix; 4014 fw.start_addr = bce_CP_b06FwStartAddr; 4015 4016 fw.text_addr = bce_CP_b06FwTextAddr; 4017 fw.text_len = bce_CP_b06FwTextLen; 4018 fw.text_index = 0; 4019 fw.text = bce_CP_b06FwText; 4020 4021 fw.data_addr = bce_CP_b06FwDataAddr; 4022 fw.data_len = bce_CP_b06FwDataLen; 4023 fw.data_index = 0; 4024 fw.data = bce_CP_b06FwData; 4025 4026 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4027 fw.sbss_len = bce_CP_b06FwSbssLen; 4028 fw.sbss_index = 0; 4029 fw.sbss = bce_CP_b06FwSbss; 4030 4031 fw.bss_addr = bce_CP_b06FwBssAddr; 4032 fw.bss_len = bce_CP_b06FwBssLen; 4033 fw.bss_index = 0; 4034 fw.bss = bce_CP_b06FwBss; 4035 4036 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4037 fw.rodata_len = bce_CP_b06FwRodataLen; 4038 fw.rodata_index = 0; 4039 fw.rodata = bce_CP_b06FwRodata; 4040 } 4041 4042 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4043 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4044 4045 DBEXIT(BCE_VERBOSE_RESET); 4046 } 4047 4048 4049 /****************************************************************************/ 4050 /* Initialize the COM CPU. */ 4051 /* */ 4052 /* Returns: */ 4053 /* Nothing. */ 4054 /****************************************************************************/ 4055 static void 4056 bce_init_com_cpu(struct bce_softc *sc) 4057 { 4058 struct cpu_reg cpu_reg; 4059 struct fw_info fw; 4060 4061 DBENTER(BCE_VERBOSE_RESET); 4062 4063 cpu_reg.mode = BCE_COM_CPU_MODE; 4064 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4065 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4066 cpu_reg.state = BCE_COM_CPU_STATE; 4067 cpu_reg.state_value_clear = 0xffffff; 4068 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4069 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4070 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4071 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4072 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4073 cpu_reg.spad_base = BCE_COM_SCRATCH; 4074 cpu_reg.mips_view_base = 0x8000000; 4075 4076 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4077 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4078 fw.ver_major = bce_COM_b09FwReleaseMajor; 4079 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4080 fw.ver_fix = bce_COM_b09FwReleaseFix; 4081 fw.start_addr = bce_COM_b09FwStartAddr; 4082 4083 fw.text_addr = bce_COM_b09FwTextAddr; 4084 fw.text_len = bce_COM_b09FwTextLen; 4085 fw.text_index = 0; 4086 fw.text = bce_COM_b09FwText; 4087 4088 fw.data_addr = bce_COM_b09FwDataAddr; 4089 fw.data_len = bce_COM_b09FwDataLen; 4090 fw.data_index = 0; 4091 fw.data = bce_COM_b09FwData; 4092 4093 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4094 fw.sbss_len = bce_COM_b09FwSbssLen; 4095 fw.sbss_index = 0; 4096 fw.sbss = bce_COM_b09FwSbss; 4097 4098 fw.bss_addr = bce_COM_b09FwBssAddr; 4099 fw.bss_len = bce_COM_b09FwBssLen; 4100 fw.bss_index = 0; 4101 fw.bss = bce_COM_b09FwBss; 4102 4103 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4104 fw.rodata_len = bce_COM_b09FwRodataLen; 4105 fw.rodata_index = 0; 4106 fw.rodata = bce_COM_b09FwRodata; 4107 } else { 4108 fw.ver_major = bce_COM_b06FwReleaseMajor; 4109 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4110 fw.ver_fix = bce_COM_b06FwReleaseFix; 4111 fw.start_addr = bce_COM_b06FwStartAddr; 4112 4113 fw.text_addr = bce_COM_b06FwTextAddr; 4114 fw.text_len = bce_COM_b06FwTextLen; 4115 fw.text_index = 0; 4116 fw.text = bce_COM_b06FwText; 4117 4118 fw.data_addr = bce_COM_b06FwDataAddr; 4119 fw.data_len = bce_COM_b06FwDataLen; 4120 fw.data_index = 0; 4121 fw.data = bce_COM_b06FwData; 4122 4123 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4124 fw.sbss_len = bce_COM_b06FwSbssLen; 4125 fw.sbss_index = 0; 4126 fw.sbss = bce_COM_b06FwSbss; 4127 4128 fw.bss_addr = bce_COM_b06FwBssAddr; 4129 fw.bss_len = bce_COM_b06FwBssLen; 4130 fw.bss_index = 0; 4131 fw.bss = bce_COM_b06FwBss; 4132 4133 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4134 fw.rodata_len = bce_COM_b06FwRodataLen; 4135 fw.rodata_index = 0; 4136 fw.rodata = bce_COM_b06FwRodata; 4137 } 4138 4139 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4140 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4141 4142 DBEXIT(BCE_VERBOSE_RESET); 4143 } 4144 4145 4146 /****************************************************************************/ 4147 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4148 /* */ 4149 /* Loads the firmware for each CPU and starts the CPU. */ 4150 /* */ 4151 /* Returns: */ 4152 /* Nothing. */ 4153 /****************************************************************************/ 4154 static void 4155 bce_init_cpus(struct bce_softc *sc) 4156 { 4157 DBENTER(BCE_VERBOSE_RESET); 4158 4159 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4160 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4161 4162 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4163 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4164 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4165 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4166 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4167 } else { 4168 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4169 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4170 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4171 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4172 } 4173 4174 } else { 4175 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4176 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4177 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4178 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4179 } 4180 4181 bce_init_rxp_cpu(sc); 4182 bce_init_txp_cpu(sc); 4183 bce_init_tpat_cpu(sc); 4184 bce_init_com_cpu(sc); 4185 bce_init_cp_cpu(sc); 4186 4187 DBEXIT(BCE_VERBOSE_RESET); 4188 } 4189 4190 4191 /****************************************************************************/ 4192 /* Initialize context memory. */ 4193 /* */ 4194 /* Clears the memory associated with each Context ID (CID). */ 4195 /* */ 4196 /* Returns: */ 4197 /* Nothing. */ 4198 /****************************************************************************/ 4199 static void 4200 bce_init_ctx(struct bce_softc *sc) 4201 { 4202 4203 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4204 4205 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4206 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4207 int i, retry_cnt = CTX_INIT_RETRY_COUNT; 4208 u32 val; 4209 4210 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4211 4212 /* 4213 * BCM5709 context memory may be cached 4214 * in host memory so prepare the host memory 4215 * for access. 4216 */ 4217 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4218 val |= (BCM_PAGE_BITS - 8) << 16; 4219 REG_WR(sc, BCE_CTX_COMMAND, val); 4220 4221 /* Wait for mem init command to complete. */ 4222 for (i = 0; i < retry_cnt; i++) { 4223 val = REG_RD(sc, BCE_CTX_COMMAND); 4224 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4225 break; 4226 DELAY(2); 4227 } 4228 4229 /* ToDo: Consider returning an error here. */ 4230 DBRUNIF((val & BCE_CTX_COMMAND_MEM_INIT), 4231 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4232 __FUNCTION__)); 4233 4234 for (i = 0; i < sc->ctx_pages; i++) { 4235 int j; 4236 4237 /* Set the physical address of the context memory cache. */ 4238 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4239 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4240 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4241 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4242 BCE_ADDR_HI(sc->ctx_paddr[i])); 4243 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4244 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4245 4246 /* Verify that the context memory write was successful. */ 4247 for (j = 0; j < retry_cnt; j++) { 4248 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4249 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4250 break; 4251 DELAY(5); 4252 } 4253 4254 /* ToDo: Consider returning an error here. */ 4255 DBRUNIF((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ), 4256 BCE_PRINTF("%s(): Failed to initialize context page %d!\n", 4257 __FUNCTION__, i)); 4258 } 4259 } else { 4260 u32 vcid_addr, offset; 4261 4262 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4263 4264 /* 4265 * For the 5706/5708, context memory is local to 4266 * the controller, so initialize the controller 4267 * context memory. 4268 */ 4269 4270 vcid_addr = GET_CID_ADDR(96); 4271 while (vcid_addr) { 4272 4273 vcid_addr -= PHY_CTX_SIZE; 4274 4275 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4276 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4277 4278 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4279 CTX_WR(sc, 0x00, offset, 0); 4280 } 4281 4282 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4283 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4284 } 4285 4286 } 4287 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4288 } 4289 4290 4291 /****************************************************************************/ 4292 /* Fetch the permanent MAC address of the controller. */ 4293 /* */ 4294 /* Returns: */ 4295 /* Nothing. */ 4296 /****************************************************************************/ 4297 static void 4298 bce_get_mac_addr(struct bce_softc *sc) 4299 { 4300 u32 mac_lo = 0, mac_hi = 0; 4301 4302 DBENTER(BCE_VERBOSE_RESET); 4303 /* 4304 * The NetXtreme II bootcode populates various NIC 4305 * power-on and runtime configuration items in a 4306 * shared memory area. The factory configured MAC 4307 * address is available from both NVRAM and the 4308 * shared memory area so we'll read the value from 4309 * shared memory for speed. 4310 */ 4311 4312 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + 4313 BCE_PORT_HW_CFG_MAC_UPPER); 4314 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + 4315 BCE_PORT_HW_CFG_MAC_LOWER); 4316 4317 if ((mac_lo == 0) && (mac_hi == 0)) { 4318 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4319 __FILE__, __LINE__); 4320 } else { 4321 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4322 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4323 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4324 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4325 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4326 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4327 } 4328 4329 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet address = %6D\n", sc->eaddr, ":"); 4330 DBEXIT(BCE_VERBOSE_RESET); 4331 } 4332 4333 4334 /****************************************************************************/ 4335 /* Program the MAC address. */ 4336 /* */ 4337 /* Returns: */ 4338 /* Nothing. */ 4339 /****************************************************************************/ 4340 static void 4341 bce_set_mac_addr(struct bce_softc *sc) 4342 { 4343 u32 val; 4344 u8 *mac_addr = sc->eaddr; 4345 4346 /* ToDo: Add support for setting multiple MAC addresses. */ 4347 4348 DBENTER(BCE_VERBOSE_RESET); 4349 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = %6D\n", sc->eaddr, ":"); 4350 4351 val = (mac_addr[0] << 8) | mac_addr[1]; 4352 4353 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4354 4355 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4356 (mac_addr[4] << 8) | mac_addr[5]; 4357 4358 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4359 4360 DBEXIT(BCE_VERBOSE_RESET); 4361 } 4362 4363 4364 /****************************************************************************/ 4365 /* Stop the controller. */ 4366 /* */ 4367 /* Returns: */ 4368 /* Nothing. */ 4369 /****************************************************************************/ 4370 static void 4371 bce_stop(struct bce_softc *sc) 4372 { 4373 struct ifnet *ifp; 4374 struct ifmedia_entry *ifm; 4375 struct mii_data *mii = NULL; 4376 int mtmp, itmp; 4377 4378 DBENTER(BCE_VERBOSE_RESET); 4379 4380 BCE_LOCK_ASSERT(sc); 4381 4382 ifp = sc->bce_ifp; 4383 4384 mii = device_get_softc(sc->bce_miibus); 4385 4386 callout_stop(&sc->bce_tick_callout); 4387 4388 /* Disable the transmit/receive blocks. */ 4389 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4390 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4391 DELAY(20); 4392 4393 bce_disable_intr(sc); 4394 4395 /* Free RX buffers. */ 4396 #ifdef ZERO_COPY_SOCKETS 4397 bce_free_pg_chain(sc); 4398 #endif 4399 bce_free_rx_chain(sc); 4400 4401 /* Free TX buffers. */ 4402 bce_free_tx_chain(sc); 4403 4404 /* 4405 * Isolate/power down the PHY, but leave the media selection 4406 * unchanged so that things will be put back to normal when 4407 * we bring the interface back up. 4408 */ 4409 4410 itmp = ifp->if_flags; 4411 ifp->if_flags |= IFF_UP; 4412 4413 /* If we are called from bce_detach(), mii is already NULL. */ 4414 if (mii != NULL) { 4415 ifm = mii->mii_media.ifm_cur; 4416 mtmp = ifm->ifm_media; 4417 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4418 mii_mediachg(mii); 4419 ifm->ifm_media = mtmp; 4420 } 4421 4422 ifp->if_flags = itmp; 4423 sc->watchdog_timer = 0; 4424 4425 sc->bce_link = 0; 4426 4427 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4428 4429 DBEXIT(BCE_VERBOSE_RESET); 4430 } 4431 4432 4433 static int 4434 bce_reset(struct bce_softc *sc, u32 reset_code) 4435 { 4436 u32 val; 4437 int i, rc = 0; 4438 4439 DBENTER(BCE_VERBOSE_RESET); 4440 4441 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4442 __FUNCTION__, reset_code); 4443 4444 /* Wait for pending PCI transactions to complete. */ 4445 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4446 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4447 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4448 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4449 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4450 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4451 DELAY(5); 4452 4453 /* Disable DMA */ 4454 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4455 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4456 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4457 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4458 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4459 } 4460 4461 /* Assume bootcode is running. */ 4462 sc->bce_fw_timed_out = 0; 4463 4464 /* Give the firmware a chance to prepare for the reset. */ 4465 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4466 if (rc) 4467 goto bce_reset_exit; 4468 4469 /* Set a firmware reminder that this is a soft reset. */ 4470 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE, 4471 BCE_DRV_RESET_SIGNATURE_MAGIC); 4472 4473 /* Dummy read to force the chip to complete all current transactions. */ 4474 val = REG_RD(sc, BCE_MISC_ID); 4475 4476 /* Chip reset. */ 4477 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4478 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4479 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4480 REG_RD(sc, BCE_MISC_COMMAND); 4481 DELAY(5); 4482 4483 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4484 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4485 4486 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4487 } else { 4488 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4489 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4490 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4491 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4492 4493 /* Allow up to 30us for reset to complete. */ 4494 for (i = 0; i < 10; i++) { 4495 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4496 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4497 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4498 break; 4499 } 4500 DELAY(10); 4501 } 4502 4503 /* Check that reset completed successfully. */ 4504 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4505 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4506 BCE_PRINTF("%s(%d): Reset failed!\n", 4507 __FILE__, __LINE__); 4508 rc = EBUSY; 4509 goto bce_reset_exit; 4510 } 4511 } 4512 4513 /* Make sure byte swapping is properly configured. */ 4514 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 4515 if (val != 0x01020304) { 4516 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 4517 __FILE__, __LINE__); 4518 rc = ENODEV; 4519 goto bce_reset_exit; 4520 } 4521 4522 /* Just completed a reset, assume that firmware is running again. */ 4523 sc->bce_fw_timed_out = 0; 4524 4525 /* Wait for the firmware to finish its initialization. */ 4526 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 4527 if (rc) 4528 BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n", 4529 __FILE__, __LINE__); 4530 4531 bce_reset_exit: 4532 DBEXIT(BCE_VERBOSE_RESET); 4533 return (rc); 4534 } 4535 4536 4537 static int 4538 bce_chipinit(struct bce_softc *sc) 4539 { 4540 u32 val; 4541 int rc = 0; 4542 4543 DBENTER(BCE_VERBOSE_RESET); 4544 4545 bce_disable_intr(sc); 4546 4547 /* 4548 * Initialize DMA byte/word swapping, configure the number of DMA 4549 * channels and PCI clock compensation delay. 4550 */ 4551 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 4552 BCE_DMA_CONFIG_DATA_WORD_SWAP | 4553 #if BYTE_ORDER == BIG_ENDIAN 4554 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 4555 #endif 4556 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 4557 DMA_READ_CHANS << 12 | 4558 DMA_WRITE_CHANS << 16; 4559 4560 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 4561 4562 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 4563 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 4564 4565 /* 4566 * This setting resolves a problem observed on certain Intel PCI 4567 * chipsets that cannot handle multiple outstanding DMA operations. 4568 * See errata E9_5706A1_65. 4569 */ 4570 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 4571 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 4572 !(sc->bce_flags & BCE_PCIX_FLAG)) 4573 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 4574 4575 REG_WR(sc, BCE_DMA_CONFIG, val); 4576 4577 /* Enable the RX_V2P and Context state machines before access. */ 4578 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 4579 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 4580 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 4581 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 4582 4583 /* Initialize context mapping and zero out the quick contexts. */ 4584 bce_init_ctx(sc); 4585 4586 /* Initialize the on-boards CPUs */ 4587 bce_init_cpus(sc); 4588 4589 /* Prepare NVRAM for access. */ 4590 if (bce_init_nvram(sc)) { 4591 rc = ENODEV; 4592 goto bce_chipinit_exit; 4593 } 4594 4595 /* Set the kernel bypass block size */ 4596 val = REG_RD(sc, BCE_MQ_CONFIG); 4597 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 4598 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 4599 4600 /* Enable bins used on the 5709. */ 4601 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4602 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4603 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 4604 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 4605 val |= BCE_MQ_CONFIG_HALT_DIS; 4606 } 4607 4608 REG_WR(sc, BCE_MQ_CONFIG, val); 4609 4610 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 4611 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 4612 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 4613 4614 /* Set the page size and clear the RV2P processor stall bits. */ 4615 val = (BCM_PAGE_BITS - 8) << 24; 4616 REG_WR(sc, BCE_RV2P_CONFIG, val); 4617 4618 /* Configure page size. */ 4619 val = REG_RD(sc, BCE_TBDR_CONFIG); 4620 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 4621 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 4622 REG_WR(sc, BCE_TBDR_CONFIG, val); 4623 4624 /* Set the perfect match control register to default. */ 4625 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 4626 4627 bce_chipinit_exit: 4628 DBEXIT(BCE_VERBOSE_RESET); 4629 4630 return(rc); 4631 } 4632 4633 4634 /****************************************************************************/ 4635 /* Initialize the controller in preparation to send/receive traffic. */ 4636 /* */ 4637 /* Returns: */ 4638 /* 0 for success, positive value for failure. */ 4639 /****************************************************************************/ 4640 static int 4641 bce_blockinit(struct bce_softc *sc) 4642 { 4643 u32 reg, val; 4644 int rc = 0; 4645 4646 DBENTER(BCE_VERBOSE_RESET); 4647 4648 /* Load the hardware default MAC address. */ 4649 bce_set_mac_addr(sc); 4650 4651 /* Set the Ethernet backoff seed value */ 4652 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 4653 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 4654 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 4655 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 4656 4657 sc->last_status_idx = 0; 4658 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 4659 4660 /* Set up link change interrupt generation. */ 4661 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 4662 4663 /* Program the physical address of the status block. */ 4664 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 4665 BCE_ADDR_LO(sc->status_block_paddr)); 4666 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 4667 BCE_ADDR_HI(sc->status_block_paddr)); 4668 4669 /* Program the physical address of the statistics block. */ 4670 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 4671 BCE_ADDR_LO(sc->stats_block_paddr)); 4672 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 4673 BCE_ADDR_HI(sc->stats_block_paddr)); 4674 4675 /* Program various host coalescing parameters. */ 4676 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4677 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 4678 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4679 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 4680 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 4681 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 4682 REG_WR(sc, BCE_HC_TX_TICKS, 4683 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 4684 REG_WR(sc, BCE_HC_RX_TICKS, 4685 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 4686 REG_WR(sc, BCE_HC_COM_TICKS, 4687 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 4688 REG_WR(sc, BCE_HC_CMD_TICKS, 4689 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 4690 REG_WR(sc, BCE_HC_STATS_TICKS, 4691 (sc->bce_stats_ticks & 0xffff00)); 4692 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 4693 4694 /* Configure the Host Coalescing block. */ 4695 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 4696 BCE_HC_CONFIG_COLLECT_STATS; 4697 4698 #if 0 4699 /* ToDo: Add MSI-X support. */ 4700 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 4701 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 4702 BCE_HC_SB_CONFIG_1; 4703 4704 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 4705 4706 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 4707 BCE_HC_SB_CONFIG_1_ONE_SHOT); 4708 4709 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 4710 (sc->tx_quick_cons_trip_int << 16) | 4711 sc->tx_quick_cons_trip); 4712 4713 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 4714 (sc->tx_ticks_int << 16) | sc->tx_ticks); 4715 4716 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4717 } 4718 4719 /* 4720 * Tell the HC block to automatically set the 4721 * INT_MASK bit after an MSI/MSI-X interrupt 4722 * is generated so the driver doesn't have to. 4723 */ 4724 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 4725 val |= BCE_HC_CONFIG_ONE_SHOT; 4726 4727 /* Set the MSI-X status blocks to 128 byte boundaries. */ 4728 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 4729 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 4730 #endif 4731 4732 REG_WR(sc, BCE_HC_CONFIG, val); 4733 4734 /* Clear the internal statistics counters. */ 4735 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 4736 4737 /* Verify that bootcode is running. */ 4738 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE); 4739 4740 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 4741 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 4742 __FILE__, __LINE__); 4743 reg = 0); 4744 4745 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 4746 BCE_DEV_INFO_SIGNATURE_MAGIC) { 4747 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 4748 "Expected: 08%08X\n", __FILE__, __LINE__, 4749 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 4750 BCE_DEV_INFO_SIGNATURE_MAGIC); 4751 rc = ENODEV; 4752 goto bce_blockinit_exit; 4753 } 4754 4755 /* Enable DMA */ 4756 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4757 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 4758 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4759 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4760 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4761 } 4762 4763 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 4764 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET); 4765 4766 /* Enable link state change interrupt generation. */ 4767 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 4768 4769 /* Enable all remaining blocks in the MAC. */ 4770 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 4771 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 4772 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT_XI); 4773 else 4774 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 4775 4776 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4777 DELAY(20); 4778 4779 /* Save the current host coalescing block settings. */ 4780 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 4781 4782 bce_blockinit_exit: 4783 DBEXIT(BCE_VERBOSE_RESET); 4784 4785 return (rc); 4786 } 4787 4788 4789 /****************************************************************************/ 4790 /* Encapsulate an mbuf into the rx_bd chain. */ 4791 /* */ 4792 /* Returns: */ 4793 /* 0 for success, positive value for failure. */ 4794 /****************************************************************************/ 4795 static int 4796 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 4797 u16 *chain_prod, u32 *prod_bseq) 4798 { 4799 bus_dmamap_t map; 4800 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 4801 struct mbuf *m_new = NULL; 4802 struct rx_bd *rxbd; 4803 int nsegs, error, rc = 0; 4804 #ifdef BCE_DEBUG 4805 u16 debug_chain_prod = *chain_prod; 4806 #endif 4807 4808 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 4809 4810 /* Make sure the inputs are valid. */ 4811 DBRUNIF((*chain_prod > MAX_RX_BD), 4812 BCE_PRINTF("%s(%d): RX producer out of range: 0x%04X > 0x%04X\n", 4813 __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD)); 4814 4815 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, " 4816 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 4817 4818 /* Update some debug statistic counters */ 4819 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4820 sc->rx_low_watermark = sc->free_rx_bd); 4821 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 4822 4823 /* Check whether this is a new mbuf allocation. */ 4824 if (m == NULL) { 4825 4826 /* Simulate an mbuf allocation failure. */ 4827 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 4828 sc->mbuf_alloc_failed_count++; 4829 sc->mbuf_alloc_failed_sim_count++; 4830 rc = ENOBUFS; 4831 goto bce_get_rx_buf_exit); 4832 4833 /* This is a new mbuf allocation. */ 4834 #ifdef ZERO_COPY_SOCKETS 4835 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 4836 #else 4837 if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES) 4838 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 4839 else 4840 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, sc->rx_bd_mbuf_alloc_size); 4841 #endif 4842 4843 if (m_new == NULL) { 4844 sc->mbuf_alloc_failed_count++; 4845 rc = ENOBUFS; 4846 goto bce_get_rx_buf_exit; 4847 } 4848 4849 DBRUN(sc->debug_rx_mbuf_alloc++); 4850 } else { 4851 /* Reuse an existing mbuf. */ 4852 m_new = m; 4853 } 4854 4855 /* Make sure we have a valid packet header. */ 4856 M_ASSERTPKTHDR(m_new); 4857 4858 /* Initialize the mbuf size and pad if necessary for alignment. */ 4859 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 4860 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 4861 4862 /* ToDo: Consider calling m_fragment() to test error handling. */ 4863 4864 /* Map the mbuf cluster into device memory. */ 4865 map = sc->rx_mbuf_map[*chain_prod]; 4866 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 4867 segs, &nsegs, BUS_DMA_NOWAIT); 4868 4869 /* Handle any mapping errors. */ 4870 if (error) { 4871 BCE_PRINTF("%s(%d): Error mapping mbuf into RX chain (%d)!\n", 4872 __FILE__, __LINE__, error); 4873 4874 sc->dma_map_addr_rx_failed_count++; 4875 m_freem(m_new); 4876 4877 DBRUN(sc->debug_rx_mbuf_alloc--); 4878 4879 rc = ENOBUFS; 4880 goto bce_get_rx_buf_exit; 4881 } 4882 4883 /* All mbufs must map to a single segment. */ 4884 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 4885 __FUNCTION__, nsegs)); 4886 4887 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */ 4888 4889 /* Setup the rx_bd for the segment. */ 4890 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 4891 4892 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 4893 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 4894 rxbd->rx_bd_len = htole32(segs[0].ds_len); 4895 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 4896 *prod_bseq += segs[0].ds_len; 4897 4898 /* Save the mbuf and update our counter. */ 4899 sc->rx_mbuf_ptr[*chain_prod] = m_new; 4900 sc->free_rx_bd -= nsegs; 4901 4902 DBRUNMSG(BCE_INSANE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 4903 nsegs)); 4904 4905 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, " 4906 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 4907 4908 bce_get_rx_buf_exit: 4909 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 4910 4911 return(rc); 4912 } 4913 4914 4915 #ifdef ZERO_COPY_SOCKETS 4916 /****************************************************************************/ 4917 /* Encapsulate an mbuf cluster into the page chain. */ 4918 /* */ 4919 /* Returns: */ 4920 /* 0 for success, positive value for failure. */ 4921 /****************************************************************************/ 4922 static int 4923 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 4924 u16 *prod_idx) 4925 { 4926 bus_dmamap_t map; 4927 bus_addr_t busaddr; 4928 struct mbuf *m_new = NULL; 4929 struct rx_bd *pgbd; 4930 int error, rc = 0; 4931 #ifdef BCE_DEBUG 4932 u16 debug_prod_idx = *prod_idx; 4933 #endif 4934 4935 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 4936 4937 /* Make sure the inputs are valid. */ 4938 DBRUNIF((*prod_idx > MAX_PG_BD), 4939 BCE_PRINTF("%s(%d): page producer out of range: 0x%04X > 0x%04X\n", 4940 __FILE__, __LINE__, *prod_idx, (u16) MAX_PG_BD)); 4941 4942 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 4943 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 4944 4945 /* Update counters if we've hit a new low or run out of pages. */ 4946 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 4947 sc->pg_low_watermark = sc->free_pg_bd); 4948 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 4949 4950 /* Check whether this is a new mbuf allocation. */ 4951 if (m == NULL) { 4952 4953 /* Simulate an mbuf allocation failure. */ 4954 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 4955 sc->mbuf_alloc_failed_count++; 4956 sc->mbuf_alloc_failed_sim_count++; 4957 rc = ENOBUFS; 4958 goto bce_get_pg_buf_exit); 4959 4960 /* This is a new mbuf allocation. */ 4961 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 4962 if (m_new == NULL) { 4963 sc->mbuf_alloc_failed_count++; 4964 rc = ENOBUFS; 4965 goto bce_get_pg_buf_exit; 4966 } 4967 4968 DBRUN(sc->debug_pg_mbuf_alloc++); 4969 } else { 4970 /* Reuse an existing mbuf. */ 4971 m_new = m; 4972 m_new->m_data = m_new->m_ext.ext_buf; 4973 } 4974 4975 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 4976 4977 /* ToDo: Consider calling m_fragment() to test error handling. */ 4978 4979 /* Map the mbuf cluster into device memory. */ 4980 map = sc->pg_mbuf_map[*prod_idx]; 4981 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 4982 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, &busaddr, BUS_DMA_NOWAIT); 4983 4984 /* Handle any mapping errors. */ 4985 if (error) { 4986 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 4987 __FILE__, __LINE__); 4988 4989 m_freem(m_new); 4990 DBRUN(sc->debug_pg_mbuf_alloc--); 4991 4992 rc = ENOBUFS; 4993 goto bce_get_pg_buf_exit; 4994 } 4995 4996 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */ 4997 4998 /* 4999 * The page chain uses the same rx_bd data structure 5000 * as the receive chain but doesn't require a byte sequence (bseq). 5001 */ 5002 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5003 5004 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5005 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5006 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5007 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5008 5009 /* Save the mbuf and update our counter. */ 5010 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5011 sc->free_pg_bd--; 5012 5013 DBRUNMSG(BCE_INSANE_RECV, bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 5014 1)); 5015 5016 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5017 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5018 5019 bce_get_pg_buf_exit: 5020 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5021 5022 return(rc); 5023 } 5024 #endif /* ZERO_COPY_SOCKETS */ 5025 5026 /****************************************************************************/ 5027 /* Initialize the TX context memory. */ 5028 /* */ 5029 /* Returns: */ 5030 /* Nothing */ 5031 /****************************************************************************/ 5032 static void 5033 bce_init_tx_context(struct bce_softc *sc) 5034 { 5035 u32 val; 5036 5037 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5038 5039 /* Initialize the context ID for an L2 TX chain. */ 5040 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5041 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5042 /* Set the CID type to support an L2 connection. */ 5043 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5044 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5045 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5046 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val); 5047 5048 /* Point the hardware to the first page in the chain. */ 5049 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5050 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5051 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5052 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5053 } else { 5054 /* Set the CID type to support an L2 connection. */ 5055 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5056 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5057 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5058 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5059 5060 /* Point the hardware to the first page in the chain. */ 5061 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5062 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5063 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5064 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5065 } 5066 5067 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5068 } 5069 5070 5071 /****************************************************************************/ 5072 /* Allocate memory and initialize the TX data structures. */ 5073 /* */ 5074 /* Returns: */ 5075 /* 0 for success, positive value for failure. */ 5076 /****************************************************************************/ 5077 static int 5078 bce_init_tx_chain(struct bce_softc *sc) 5079 { 5080 struct tx_bd *txbd; 5081 int i, rc = 0; 5082 5083 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5084 5085 /* Set the initial TX producer/consumer indices. */ 5086 sc->tx_prod = 0; 5087 sc->tx_cons = 0; 5088 sc->tx_prod_bseq = 0; 5089 sc->used_tx_bd = 0; 5090 sc->max_tx_bd = USABLE_TX_BD; 5091 DBRUN(sc->tx_hi_watermark = USABLE_TX_BD); 5092 DBRUN(sc->tx_full_count = 0); 5093 5094 /* 5095 * The NetXtreme II supports a linked-list structre called 5096 * a Buffer Descriptor Chain (or BD chain). A BD chain 5097 * consists of a series of 1 or more chain pages, each of which 5098 * consists of a fixed number of BD entries. 5099 * The last BD entry on each page is a pointer to the next page 5100 * in the chain, and the last pointer in the BD chain 5101 * points back to the beginning of the chain. 5102 */ 5103 5104 /* Set the TX next pointer chain entries. */ 5105 for (i = 0; i < TX_PAGES; i++) { 5106 int j; 5107 5108 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5109 5110 /* Check if we've reached the last page. */ 5111 if (i == (TX_PAGES - 1)) 5112 j = 0; 5113 else 5114 j = i + 1; 5115 5116 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5117 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5118 } 5119 5120 bce_init_tx_context(sc); 5121 5122 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 5123 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5124 5125 return(rc); 5126 } 5127 5128 5129 /****************************************************************************/ 5130 /* Free memory and clear the TX data structures. */ 5131 /* */ 5132 /* Returns: */ 5133 /* Nothing. */ 5134 /****************************************************************************/ 5135 static void 5136 bce_free_tx_chain(struct bce_softc *sc) 5137 { 5138 int i; 5139 5140 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5141 5142 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5143 for (i = 0; i < TOTAL_TX_BD; i++) { 5144 if (sc->tx_mbuf_ptr[i] != NULL) { 5145 if (sc->tx_mbuf_map[i] != NULL) 5146 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i], 5147 BUS_DMASYNC_POSTWRITE); 5148 m_freem(sc->tx_mbuf_ptr[i]); 5149 sc->tx_mbuf_ptr[i] = NULL; 5150 DBRUN(sc->debug_tx_mbuf_alloc--); 5151 } 5152 } 5153 5154 /* Clear each TX chain page. */ 5155 for (i = 0; i < TX_PAGES; i++) 5156 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5157 5158 sc->used_tx_bd = 0; 5159 5160 /* Check if we lost any mbufs in the process. */ 5161 DBRUNIF((sc->debug_tx_mbuf_alloc), 5162 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5163 "from tx chain!\n", 5164 __FILE__, __LINE__, sc->debug_tx_mbuf_alloc)); 5165 5166 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5167 } 5168 5169 5170 /****************************************************************************/ 5171 /* Initialize the RX context memory. */ 5172 /* */ 5173 /* Returns: */ 5174 /* Nothing */ 5175 /****************************************************************************/ 5176 static void 5177 bce_init_rx_context(struct bce_softc *sc) 5178 { 5179 u32 val; 5180 5181 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5182 5183 /* Initialize the type, size, and BD cache levels for the RX context. */ 5184 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5185 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5186 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5187 5188 /* 5189 * Set the level for generating pause frames 5190 * when the number of available rx_bd's gets 5191 * too low (the low watermark) and the level 5192 * when pause frames can be stopped (the high 5193 * watermark). 5194 */ 5195 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5196 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5197 u32 lo_water, hi_water; 5198 5199 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5200 hi_water = USABLE_RX_BD / 4; 5201 5202 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5203 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5204 5205 if (hi_water > 0xf) 5206 hi_water = 0xf; 5207 else if (hi_water == 0) 5208 lo_water = 0; 5209 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5210 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5211 } 5212 5213 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5214 5215 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5216 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5217 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 5218 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5219 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5220 } 5221 5222 /* Point the hardware to the first page in the chain. */ 5223 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5224 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5225 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5226 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5227 5228 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5229 } 5230 5231 5232 /****************************************************************************/ 5233 /* Allocate memory and initialize the RX data structures. */ 5234 /* */ 5235 /* Returns: */ 5236 /* 0 for success, positive value for failure. */ 5237 /****************************************************************************/ 5238 static int 5239 bce_init_rx_chain(struct bce_softc *sc) 5240 { 5241 struct rx_bd *rxbd; 5242 int i, rc = 0; 5243 5244 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5245 BCE_VERBOSE_CTX); 5246 5247 /* Initialize the RX producer and consumer indices. */ 5248 sc->rx_prod = 0; 5249 sc->rx_cons = 0; 5250 sc->rx_prod_bseq = 0; 5251 sc->free_rx_bd = USABLE_RX_BD; 5252 sc->max_rx_bd = USABLE_RX_BD; 5253 DBRUN(sc->rx_low_watermark = sc->max_rx_bd); 5254 DBRUN(sc->rx_empty_count = 0); 5255 5256 /* Initialize the RX next pointer chain entries. */ 5257 for (i = 0; i < RX_PAGES; i++) { 5258 int j; 5259 5260 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5261 5262 /* Check if we've reached the last page. */ 5263 if (i == (RX_PAGES - 1)) 5264 j = 0; 5265 else 5266 j = i + 1; 5267 5268 /* Setup the chain page pointers. */ 5269 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5270 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5271 } 5272 5273 /* Fill up the RX chain. */ 5274 bce_fill_rx_chain(sc); 5275 5276 for (i = 0; i < RX_PAGES; i++) { 5277 bus_dmamap_sync( 5278 sc->rx_bd_chain_tag, 5279 sc->rx_bd_chain_map[i], 5280 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5281 } 5282 5283 bce_init_rx_context(sc); 5284 5285 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 5286 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5287 BCE_VERBOSE_CTX); 5288 /* ToDo: Are there possible failure modes here? */ 5289 return(rc); 5290 } 5291 5292 5293 /****************************************************************************/ 5294 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5295 /* occurs. */ 5296 /* */ 5297 /* Returns: */ 5298 /* Nothing */ 5299 /****************************************************************************/ 5300 static void 5301 bce_fill_rx_chain(struct bce_softc *sc) 5302 { 5303 u16 prod, prod_idx; 5304 u32 prod_bseq; 5305 5306 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5307 BCE_VERBOSE_CTX); 5308 5309 /* Get the RX chain producer indices. */ 5310 prod = sc->rx_prod; 5311 prod_bseq = sc->rx_prod_bseq; 5312 5313 /* Keep filling the RX chain until it's full. */ 5314 while (sc->free_rx_bd > 0) { 5315 prod_idx = RX_CHAIN_IDX(prod); 5316 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5317 /* Bail out if we can't add an mbuf to the chain. */ 5318 break; 5319 } 5320 prod = NEXT_RX_BD(prod); 5321 } 5322 5323 /* Save the RX chain producer indices. */ 5324 sc->rx_prod = prod; 5325 sc->rx_prod_bseq = prod_bseq; 5326 5327 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5328 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5329 __FUNCTION__, sc->rx_prod)); 5330 5331 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5332 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, 5333 sc->rx_prod); 5334 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, 5335 sc->rx_prod_bseq); 5336 5337 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5338 BCE_VERBOSE_CTX); 5339 } 5340 5341 5342 /****************************************************************************/ 5343 /* Free memory and clear the RX data structures. */ 5344 /* */ 5345 /* Returns: */ 5346 /* Nothing. */ 5347 /****************************************************************************/ 5348 static void 5349 bce_free_rx_chain(struct bce_softc *sc) 5350 { 5351 int i; 5352 5353 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5354 5355 /* Free any mbufs still in the RX mbuf chain. */ 5356 for (i = 0; i < TOTAL_RX_BD; i++) { 5357 if (sc->rx_mbuf_ptr[i] != NULL) { 5358 if (sc->rx_mbuf_map[i] != NULL) 5359 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i], 5360 BUS_DMASYNC_POSTREAD); 5361 m_freem(sc->rx_mbuf_ptr[i]); 5362 sc->rx_mbuf_ptr[i] = NULL; 5363 DBRUN(sc->debug_rx_mbuf_alloc--); 5364 } 5365 } 5366 5367 /* Clear each RX chain page. */ 5368 for (i = 0; i < RX_PAGES; i++) 5369 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 5370 5371 sc->free_rx_bd = sc->max_rx_bd; 5372 5373 /* Check if we lost any mbufs in the process. */ 5374 DBRUNIF((sc->debug_rx_mbuf_alloc), 5375 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5376 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5377 5378 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5379 } 5380 5381 5382 #ifdef ZERO_COPY_SOCKETS 5383 /****************************************************************************/ 5384 /* Allocate memory and initialize the page data structures. */ 5385 /* Assumes that bce_init_rx_chain() has not already been called. */ 5386 /* */ 5387 /* Returns: */ 5388 /* 0 for success, positive value for failure. */ 5389 /****************************************************************************/ 5390 static int 5391 bce_init_pg_chain(struct bce_softc *sc) 5392 { 5393 struct rx_bd *pgbd; 5394 int i, rc = 0; 5395 u32 val; 5396 5397 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5398 BCE_VERBOSE_CTX); 5399 5400 /* Initialize the page producer and consumer indices. */ 5401 sc->pg_prod = 0; 5402 sc->pg_cons = 0; 5403 sc->free_pg_bd = USABLE_PG_BD; 5404 sc->max_pg_bd = USABLE_PG_BD; 5405 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5406 DBRUN(sc->pg_empty_count = 0); 5407 5408 /* Initialize the page next pointer chain entries. */ 5409 for (i = 0; i < PG_PAGES; i++) { 5410 int j; 5411 5412 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5413 5414 /* Check if we've reached the last page. */ 5415 if (i == (PG_PAGES - 1)) 5416 j = 0; 5417 else 5418 j = i + 1; 5419 5420 /* Setup the chain page pointers. */ 5421 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5422 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5423 } 5424 5425 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5426 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 5427 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 5428 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5429 5430 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5431 5432 /* Configure the rx_bd and page chain mbuf cluster size. */ 5433 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5434 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5435 5436 /* Configure the context reserved for jumbo support. */ 5437 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5438 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5439 5440 /* Point the hardware to the first page in the page chain. */ 5441 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5442 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5443 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5444 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5445 5446 /* Fill up the page chain. */ 5447 bce_fill_pg_chain(sc); 5448 5449 for (i = 0; i < PG_PAGES; i++) { 5450 bus_dmamap_sync( 5451 sc->pg_bd_chain_tag, 5452 sc->pg_bd_chain_map[i], 5453 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5454 } 5455 5456 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD)); 5457 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5458 BCE_VERBOSE_CTX); 5459 return(rc); 5460 } 5461 5462 5463 /****************************************************************************/ 5464 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 5465 /* occurs. */ 5466 /* */ 5467 /* Returns: */ 5468 /* Nothing */ 5469 /****************************************************************************/ 5470 static void 5471 bce_fill_pg_chain(struct bce_softc *sc) 5472 { 5473 u16 prod, prod_idx; 5474 5475 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5476 BCE_VERBOSE_CTX); 5477 5478 /* Get the page chain prodcuer index. */ 5479 prod = sc->pg_prod; 5480 5481 /* Keep filling the page chain until it's full. */ 5482 while (sc->free_pg_bd > 0) { 5483 prod_idx = PG_CHAIN_IDX(prod); 5484 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 5485 /* Bail out if we can't add an mbuf to the chain. */ 5486 break; 5487 } 5488 prod = NEXT_PG_BD(prod); 5489 } 5490 5491 /* Save the page chain producer index. */ 5492 sc->pg_prod = prod; 5493 5494 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5495 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 5496 __FUNCTION__, sc->pg_prod)); 5497 5498 /* 5499 * Write the mailbox and tell the chip about 5500 * the new rx_bd's in the page chain. 5501 */ 5502 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 5503 sc->pg_prod); 5504 5505 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5506 BCE_VERBOSE_CTX); 5507 } 5508 5509 5510 /****************************************************************************/ 5511 /* Free memory and clear the RX data structures. */ 5512 /* */ 5513 /* Returns: */ 5514 /* Nothing. */ 5515 /****************************************************************************/ 5516 static void 5517 bce_free_pg_chain(struct bce_softc *sc) 5518 { 5519 int i; 5520 5521 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5522 5523 /* Free any mbufs still in the mbuf page chain. */ 5524 for (i = 0; i < TOTAL_PG_BD; i++) { 5525 if (sc->pg_mbuf_ptr[i] != NULL) { 5526 if (sc->pg_mbuf_map[i] != NULL) 5527 bus_dmamap_sync(sc->pg_mbuf_tag, sc->pg_mbuf_map[i], 5528 BUS_DMASYNC_POSTREAD); 5529 m_freem(sc->pg_mbuf_ptr[i]); 5530 sc->pg_mbuf_ptr[i] = NULL; 5531 DBRUN(sc->debug_pg_mbuf_alloc--); 5532 } 5533 } 5534 5535 /* Clear each page chain pages. */ 5536 for (i = 0; i < PG_PAGES; i++) 5537 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 5538 5539 sc->free_pg_bd = sc->max_pg_bd; 5540 5541 /* Check if we lost any mbufs in the process. */ 5542 DBRUNIF((sc->debug_pg_mbuf_alloc), 5543 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 5544 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 5545 5546 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5547 } 5548 #endif /* ZERO_COPY_SOCKETS */ 5549 5550 5551 /****************************************************************************/ 5552 /* Set media options. */ 5553 /* */ 5554 /* Returns: */ 5555 /* 0 for success, positive value for failure. */ 5556 /****************************************************************************/ 5557 static int 5558 bce_ifmedia_upd(struct ifnet *ifp) 5559 { 5560 struct bce_softc *sc = ifp->if_softc; 5561 5562 DBENTER(BCE_VERBOSE); 5563 5564 BCE_LOCK(sc); 5565 bce_ifmedia_upd_locked(ifp); 5566 BCE_UNLOCK(sc); 5567 5568 DBEXIT(BCE_VERBOSE); 5569 return (0); 5570 } 5571 5572 5573 /****************************************************************************/ 5574 /* Set media options. */ 5575 /* */ 5576 /* Returns: */ 5577 /* Nothing. */ 5578 /****************************************************************************/ 5579 static void 5580 bce_ifmedia_upd_locked(struct ifnet *ifp) 5581 { 5582 struct bce_softc *sc = ifp->if_softc; 5583 struct mii_data *mii; 5584 5585 DBENTER(BCE_VERBOSE); 5586 5587 BCE_LOCK_ASSERT(sc); 5588 5589 mii = device_get_softc(sc->bce_miibus); 5590 5591 /* Make sure the MII bus has been enumerated. */ 5592 if (mii) { 5593 sc->bce_link = 0; 5594 if (mii->mii_instance) { 5595 struct mii_softc *miisc; 5596 5597 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5598 mii_phy_reset(miisc); 5599 } 5600 mii_mediachg(mii); 5601 } 5602 5603 DBEXIT(BCE_VERBOSE); 5604 } 5605 5606 5607 /****************************************************************************/ 5608 /* Reports current media status. */ 5609 /* */ 5610 /* Returns: */ 5611 /* Nothing. */ 5612 /****************************************************************************/ 5613 static void 5614 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5615 { 5616 struct bce_softc *sc = ifp->if_softc; 5617 struct mii_data *mii; 5618 5619 DBENTER(BCE_VERBOSE); 5620 5621 BCE_LOCK(sc); 5622 5623 mii = device_get_softc(sc->bce_miibus); 5624 5625 mii_pollstat(mii); 5626 ifmr->ifm_active = mii->mii_media_active; 5627 ifmr->ifm_status = mii->mii_media_status; 5628 5629 BCE_UNLOCK(sc); 5630 5631 DBEXIT(BCE_VERBOSE); 5632 } 5633 5634 5635 /****************************************************************************/ 5636 /* Handles PHY generated interrupt events. */ 5637 /* */ 5638 /* Returns: */ 5639 /* Nothing. */ 5640 /****************************************************************************/ 5641 static void 5642 bce_phy_intr(struct bce_softc *sc) 5643 { 5644 u32 new_link_state, old_link_state; 5645 5646 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5647 5648 new_link_state = sc->status_block->status_attn_bits & 5649 STATUS_ATTN_BITS_LINK_STATE; 5650 old_link_state = sc->status_block->status_attn_bits_ack & 5651 STATUS_ATTN_BITS_LINK_STATE; 5652 5653 /* Handle any changes if the link state has changed. */ 5654 if (new_link_state != old_link_state) { 5655 5656 /* Update the status_attn_bits_ack field in the status block. */ 5657 if (new_link_state) { 5658 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 5659 STATUS_ATTN_BITS_LINK_STATE); 5660 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 5661 __FUNCTION__); 5662 } 5663 else { 5664 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 5665 STATUS_ATTN_BITS_LINK_STATE); 5666 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 5667 __FUNCTION__); 5668 } 5669 5670 /* 5671 * Assume link is down and allow 5672 * tick routine to update the state 5673 * based on the actual media state. 5674 */ 5675 sc->bce_link = 0; 5676 callout_stop(&sc->bce_tick_callout); 5677 bce_tick(sc); 5678 } 5679 5680 /* Acknowledge the link change interrupt. */ 5681 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 5682 5683 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 5684 } 5685 5686 5687 /****************************************************************************/ 5688 /* Reads the receive consumer value from the status block (skipping over */ 5689 /* chain page pointer if necessary). */ 5690 /* */ 5691 /* Returns: */ 5692 /* hw_cons */ 5693 /****************************************************************************/ 5694 static inline u16 5695 bce_get_hw_rx_cons(struct bce_softc *sc) 5696 { 5697 u16 hw_cons; 5698 5699 rmb(); 5700 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 5701 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 5702 hw_cons++; 5703 5704 return hw_cons; 5705 } 5706 5707 /****************************************************************************/ 5708 /* Handles received frame interrupt events. */ 5709 /* */ 5710 /* Returns: */ 5711 /* Nothing. */ 5712 /****************************************************************************/ 5713 static void 5714 bce_rx_intr(struct bce_softc *sc) 5715 { 5716 struct ifnet *ifp = sc->bce_ifp; 5717 struct l2_fhdr *l2fhdr; 5718 unsigned int pkt_len; 5719 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 5720 u32 status; 5721 #ifdef ZERO_COPY_SOCKETS 5722 unsigned int rem_len; 5723 u16 sw_pg_cons, sw_pg_cons_idx; 5724 #endif 5725 5726 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 5727 DBRUN(sc->rx_interrupts++); 5728 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 5729 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 5730 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 5731 5732 /* Prepare the RX chain pages to be accessed by the host CPU. */ 5733 for (int i = 0; i < RX_PAGES; i++) 5734 bus_dmamap_sync(sc->rx_bd_chain_tag, 5735 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE); 5736 5737 #ifdef ZERO_COPY_SOCKETS 5738 /* Prepare the page chain pages to be accessed by the host CPU. */ 5739 for (int i = 0; i < PG_PAGES; i++) 5740 bus_dmamap_sync(sc->pg_bd_chain_tag, 5741 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTWRITE); 5742 #endif 5743 5744 /* Get the hardware's view of the RX consumer index. */ 5745 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 5746 5747 /* Get working copies of the driver's view of the consumer indices. */ 5748 sw_rx_cons = sc->rx_cons; 5749 #ifdef ZERO_COPY_SOCKETS 5750 sw_pg_cons = sc->pg_cons; 5751 #endif 5752 5753 /* Update some debug statistics counters */ 5754 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5755 sc->rx_low_watermark = sc->free_rx_bd); 5756 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++); 5757 5758 /* Scan through the receive chain as long as there is work to do */ 5759 /* ToDo: Consider setting a limit on the number of packets processed. */ 5760 rmb(); 5761 while (sw_rx_cons != hw_rx_cons) { 5762 struct mbuf *m0; 5763 5764 /* Convert the producer/consumer indices to an actual rx_bd index. */ 5765 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 5766 5767 /* Unmap the mbuf from DMA space. */ 5768 bus_dmamap_sync(sc->rx_mbuf_tag, 5769 sc->rx_mbuf_map[sw_rx_cons_idx], 5770 BUS_DMASYNC_POSTREAD); 5771 bus_dmamap_unload(sc->rx_mbuf_tag, 5772 sc->rx_mbuf_map[sw_rx_cons_idx]); 5773 5774 /* Remove the mbuf from the RX chain. */ 5775 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 5776 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 5777 DBRUN(sc->debug_rx_mbuf_alloc--); 5778 sc->free_rx_bd++; 5779 5780 /* 5781 * Frames received on the NetXteme II are prepended with an 5782 * l2_fhdr structure which provides status information about 5783 * the received frame (including VLAN tags and checksum info). 5784 * The frames are also automatically adjusted to align the IP 5785 * header (i.e. two null bytes are inserted before the Ethernet 5786 * header). As a result the data DMA'd by the controller into 5787 * the mbuf is as follows: 5788 * 5789 * +---------+-----+---------------------+-----+ 5790 * | l2_fhdr | pad | packet data | FCS | 5791 * +---------+-----+---------------------+-----+ 5792 * 5793 * The l2_fhdr needs to be checked and skipped and the FCS needs 5794 * to be stripped before sending the packet up the stack. 5795 */ 5796 l2fhdr = mtod(m0, struct l2_fhdr *); 5797 5798 /* Get the packet data + FCS length and the status. */ 5799 pkt_len = l2fhdr->l2_fhdr_pkt_len; 5800 status = l2fhdr->l2_fhdr_status; 5801 5802 /* 5803 * Skip over the l2_fhdr and pad, resulting in the 5804 * following data in the mbuf: 5805 * +---------------------+-----+ 5806 * | packet data | FCS | 5807 * +---------------------+-----+ 5808 */ 5809 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 5810 5811 #ifdef ZERO_COPY_SOCKETS 5812 /* 5813 * Check whether the received frame fits in a single 5814 * mbuf or not (i.e. packet data + FCS <= 5815 * sc->rx_bd_mbuf_data_len bytes). 5816 */ 5817 if (pkt_len > m0->m_len) { 5818 /* 5819 * The received frame is larger than a single mbuf. 5820 * If the frame was a TCP frame then only the TCP 5821 * header is placed in the mbuf, the remaining 5822 * payload (including FCS) is placed in the page 5823 * chain, the SPLIT flag is set, and the header 5824 * length is placed in the IP checksum field. 5825 * If the frame is not a TCP frame then the mbuf 5826 * is filled and the remaining bytes are placed 5827 * in the page chain. 5828 */ 5829 5830 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large packet.\n", 5831 __FUNCTION__); 5832 5833 /* 5834 * When the page chain is enabled and the TCP 5835 * header has been split from the TCP payload, 5836 * the ip_xsum structure will reflect the length 5837 * of the TCP header, not the IP checksum. Set 5838 * the packet length of the mbuf accordingly. 5839 */ 5840 if (status & L2_FHDR_STATUS_SPLIT) 5841 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 5842 5843 rem_len = pkt_len - m0->m_len; 5844 5845 /* Pull mbufs off the page chain for the remaining data. */ 5846 while (rem_len > 0) { 5847 struct mbuf *m_pg; 5848 5849 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 5850 5851 /* Remove the mbuf from the page chain. */ 5852 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 5853 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 5854 DBRUN(sc->debug_pg_mbuf_alloc--); 5855 sc->free_pg_bd++; 5856 5857 /* Unmap the page chain mbuf from DMA space. */ 5858 bus_dmamap_sync(sc->pg_mbuf_tag, 5859 sc->pg_mbuf_map[sw_pg_cons_idx], 5860 BUS_DMASYNC_POSTREAD); 5861 bus_dmamap_unload(sc->pg_mbuf_tag, 5862 sc->pg_mbuf_map[sw_pg_cons_idx]); 5863 5864 /* Adjust the mbuf length. */ 5865 if (rem_len < m_pg->m_len) { 5866 /* The mbuf chain is complete. */ 5867 m_pg->m_len = rem_len; 5868 rem_len = 0; 5869 } else { 5870 /* More packet data is waiting. */ 5871 rem_len -= m_pg->m_len; 5872 } 5873 5874 /* Concatenate the mbuf cluster to the mbuf. */ 5875 m_cat(m0, m_pg); 5876 5877 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 5878 } 5879 5880 /* Set the total packet length. */ 5881 m0->m_pkthdr.len = pkt_len; 5882 5883 } else { 5884 /* 5885 * The received packet is small and fits in a 5886 * single mbuf (i.e. the l2_fhdr + pad + packet + 5887 * FCS <= MHLEN). In other words, the packet is 5888 * 154 bytes or less in size. 5889 */ 5890 5891 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small packet.\n", 5892 __FUNCTION__); 5893 5894 /* Set the total packet length. */ 5895 m0->m_pkthdr.len = m0->m_len = pkt_len; 5896 } 5897 #else 5898 /* Set the total packet length. */ 5899 m0->m_pkthdr.len = m0->m_len = pkt_len; 5900 #endif 5901 5902 /* Remove the trailing Ethernet FCS. */ 5903 m_adj(m0, -ETHER_CRC_LEN); 5904 5905 /* Check that the resulting mbuf chain is valid. */ 5906 DBRUN(m_sanity(m0, FALSE)); 5907 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 5908 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 5909 BCE_PRINTF("Invalid Ethernet frame size!\n"); 5910 m_print(m0, 128)); 5911 5912 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 5913 BCE_PRINTF("Simulating l2_fhdr status error.\n"); 5914 sc->l2fhdr_error_sim_count++; 5915 status = status | L2_FHDR_ERRORS_PHY_DECODE); 5916 5917 /* Check the received frame for errors. */ 5918 if (status & (L2_FHDR_ERRORS_BAD_CRC | 5919 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 5920 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 5921 5922 /* Log the error and release the mbuf. */ 5923 ifp->if_ierrors++; 5924 sc->l2fhdr_error_count++; 5925 5926 m_freem(m0); 5927 m0 = NULL; 5928 goto bce_rx_int_next_rx; 5929 } 5930 5931 /* Send the packet to the appropriate interface. */ 5932 m0->m_pkthdr.rcvif = ifp; 5933 5934 /* Assume no hardware checksum. */ 5935 m0->m_pkthdr.csum_flags = 0; 5936 5937 /* Validate the checksum if offload enabled. */ 5938 if (ifp->if_capenable & IFCAP_RXCSUM) { 5939 5940 /* Check for an IP datagram. */ 5941 if (!(status & L2_FHDR_STATUS_SPLIT) && 5942 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 5943 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 5944 5945 /* Check if the IP checksum is valid. */ 5946 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 5947 m0->m_pkthdr.csum_flags |= CSUM_IP_VALID; 5948 } 5949 5950 /* Check for a valid TCP/UDP frame. */ 5951 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 5952 L2_FHDR_STATUS_UDP_DATAGRAM)) { 5953 5954 /* Check for a good TCP/UDP checksum. */ 5955 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 5956 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 5957 m0->m_pkthdr.csum_data = 5958 l2fhdr->l2_fhdr_tcp_udp_xsum; 5959 m0->m_pkthdr.csum_flags |= (CSUM_DATA_VALID 5960 | CSUM_PSEUDO_HDR); 5961 } 5962 } 5963 } 5964 5965 /* Attach the VLAN tag. */ 5966 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 5967 #if __FreeBSD_version < 700000 5968 VLAN_INPUT_TAG(ifp, m0, l2fhdr->l2_fhdr_vlan_tag, continue); 5969 #else 5970 m0->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag; 5971 m0->m_flags |= M_VLANTAG; 5972 #endif 5973 } 5974 5975 /* Increment received packet statistics. */ 5976 ifp->if_ipackets++; 5977 5978 bce_rx_int_next_rx: 5979 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 5980 5981 /* If we have a packet, pass it up the stack */ 5982 if (m0) { 5983 /* Make sure we don't lose our place when we release the lock. */ 5984 sc->rx_cons = sw_rx_cons; 5985 #ifdef ZERO_COPY_SOCKETS 5986 sc->pg_cons = sw_pg_cons; 5987 #endif 5988 5989 BCE_UNLOCK(sc); 5990 (*ifp->if_input)(ifp, m0); 5991 BCE_LOCK(sc); 5992 5993 /* Recover our place. */ 5994 sw_rx_cons = sc->rx_cons; 5995 #ifdef ZERO_COPY_SOCKETS 5996 sw_pg_cons = sc->pg_cons; 5997 #endif 5998 } 5999 6000 /* Refresh hw_cons to see if there's new work */ 6001 if (sw_rx_cons == hw_rx_cons) 6002 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6003 } 6004 6005 /* No new packets to process. Refill the RX and page chains and exit. */ 6006 #ifdef ZERO_COPY_SOCKETS 6007 sc->pg_cons = sw_pg_cons; 6008 bce_fill_pg_chain(sc); 6009 #endif 6010 6011 sc->rx_cons = sw_rx_cons; 6012 bce_fill_rx_chain(sc); 6013 6014 for (int i = 0; i < RX_PAGES; i++) 6015 bus_dmamap_sync(sc->rx_bd_chain_tag, 6016 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6017 6018 #ifdef ZERO_COPY_SOCKETS 6019 for (int i = 0; i < PG_PAGES; i++) 6020 bus_dmamap_sync(sc->pg_bd_chain_tag, 6021 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6022 #endif 6023 6024 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6025 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6026 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6027 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6028 } 6029 6030 6031 /****************************************************************************/ 6032 /* Reads the transmit consumer value from the status block (skipping over */ 6033 /* chain page pointer if necessary). */ 6034 /* */ 6035 /* Returns: */ 6036 /* hw_cons */ 6037 /****************************************************************************/ 6038 static inline u16 6039 bce_get_hw_tx_cons(struct bce_softc *sc) 6040 { 6041 u16 hw_cons; 6042 6043 mb(); 6044 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6045 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6046 hw_cons++; 6047 6048 return hw_cons; 6049 } 6050 6051 6052 /****************************************************************************/ 6053 /* Handles transmit completion interrupt events. */ 6054 /* */ 6055 /* Returns: */ 6056 /* Nothing. */ 6057 /****************************************************************************/ 6058 static void 6059 bce_tx_intr(struct bce_softc *sc) 6060 { 6061 struct ifnet *ifp = sc->bce_ifp; 6062 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6063 6064 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6065 DBRUN(sc->tx_interrupts++); 6066 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6067 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6068 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6069 6070 BCE_LOCK_ASSERT(sc); 6071 6072 /* Get the hardware's view of the TX consumer index. */ 6073 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6074 sw_tx_cons = sc->tx_cons; 6075 6076 /* Prevent speculative reads from getting ahead of the status block. */ 6077 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6078 BUS_SPACE_BARRIER_READ); 6079 6080 /* Cycle through any completed TX chain page entries. */ 6081 while (sw_tx_cons != hw_tx_cons) { 6082 #ifdef BCE_DEBUG 6083 struct tx_bd *txbd = NULL; 6084 #endif 6085 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6086 6087 DBPRINT(sc, BCE_INFO_SEND, 6088 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6089 "sw_tx_chain_cons = 0x%04X\n", 6090 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6091 6092 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 6093 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6094 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6095 (int) MAX_TX_BD); 6096 bce_breakpoint(sc)); 6097 6098 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6099 [TX_IDX(sw_tx_chain_cons)]); 6100 6101 DBRUNIF((txbd == NULL), 6102 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6103 __FILE__, __LINE__, sw_tx_chain_cons); 6104 bce_breakpoint(sc)); 6105 6106 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6107 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6108 6109 /* 6110 * Free the associated mbuf. Remember 6111 * that only the last tx_bd of a packet 6112 * has an mbuf pointer and DMA map. 6113 */ 6114 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6115 6116 /* Validate that this is the last tx_bd. */ 6117 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6118 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6119 "txmbuf == NULL!\n", __FILE__, __LINE__); 6120 bce_breakpoint(sc)); 6121 6122 DBRUNMSG(BCE_INFO_SEND, 6123 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6124 "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons)); 6125 6126 /* Unmap the mbuf. */ 6127 bus_dmamap_unload(sc->tx_mbuf_tag, 6128 sc->tx_mbuf_map[sw_tx_chain_cons]); 6129 6130 /* Free the mbuf. */ 6131 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6132 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6133 DBRUN(sc->debug_tx_mbuf_alloc--); 6134 6135 ifp->if_opackets++; 6136 } 6137 6138 sc->used_tx_bd--; 6139 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6140 6141 /* Refresh hw_cons to see if there's new work. */ 6142 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6143 6144 /* Prevent speculative reads from getting ahead of the status block. */ 6145 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6146 BUS_SPACE_BARRIER_READ); 6147 } 6148 6149 /* Clear the TX timeout timer. */ 6150 sc->watchdog_timer = 0; 6151 6152 /* Clear the tx hardware queue full flag. */ 6153 if (sc->used_tx_bd < sc->max_tx_bd) { 6154 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6155 DBPRINT(sc, BCE_INFO_SEND, 6156 "%s(): Open TX chain! %d/%d (used/total)\n", 6157 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6158 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6159 } 6160 6161 sc->tx_cons = sw_tx_cons; 6162 6163 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6164 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6165 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6166 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6167 } 6168 6169 6170 /****************************************************************************/ 6171 /* Disables interrupt generation. */ 6172 /* */ 6173 /* Returns: */ 6174 /* Nothing. */ 6175 /****************************************************************************/ 6176 static void 6177 bce_disable_intr(struct bce_softc *sc) 6178 { 6179 DBENTER(BCE_VERBOSE_INTR); 6180 6181 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6182 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6183 6184 DBEXIT(BCE_VERBOSE_INTR); 6185 } 6186 6187 6188 /****************************************************************************/ 6189 /* Enables interrupt generation. */ 6190 /* */ 6191 /* Returns: */ 6192 /* Nothing. */ 6193 /****************************************************************************/ 6194 static void 6195 bce_enable_intr(struct bce_softc *sc, int coal_now) 6196 { 6197 DBENTER(BCE_VERBOSE_INTR); 6198 6199 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6200 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6201 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6202 6203 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6204 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6205 6206 /* Force an immediate interrupt (whether there is new data or not). */ 6207 if (coal_now) 6208 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6209 6210 DBEXIT(BCE_VERBOSE_INTR); 6211 } 6212 6213 6214 /****************************************************************************/ 6215 /* Handles controller initialization. */ 6216 /* */ 6217 /* Returns: */ 6218 /* Nothing. */ 6219 /****************************************************************************/ 6220 static void 6221 bce_init_locked(struct bce_softc *sc) 6222 { 6223 struct ifnet *ifp; 6224 u32 ether_mtu = 0; 6225 6226 DBENTER(BCE_VERBOSE_RESET); 6227 6228 BCE_LOCK_ASSERT(sc); 6229 6230 ifp = sc->bce_ifp; 6231 6232 /* Check if the driver is still running and bail out if it is. */ 6233 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6234 goto bce_init_locked_exit; 6235 6236 bce_stop(sc); 6237 6238 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6239 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6240 __FILE__, __LINE__); 6241 goto bce_init_locked_exit; 6242 } 6243 6244 if (bce_chipinit(sc)) { 6245 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6246 __FILE__, __LINE__); 6247 goto bce_init_locked_exit; 6248 } 6249 6250 if (bce_blockinit(sc)) { 6251 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6252 __FILE__, __LINE__); 6253 goto bce_init_locked_exit; 6254 } 6255 6256 /* Load our MAC address. */ 6257 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6258 bce_set_mac_addr(sc); 6259 6260 /* 6261 * Calculate and program the hardware Ethernet MTU 6262 * size. Be generous on the receive if we have room. 6263 */ 6264 #ifdef ZERO_COPY_SOCKETS 6265 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + sc->pg_bd_mbuf_alloc_size)) 6266 ether_mtu = sc->rx_bd_mbuf_data_len + sc->pg_bd_mbuf_alloc_size; 6267 #else 6268 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6269 ether_mtu = sc->rx_bd_mbuf_data_len; 6270 #endif 6271 else 6272 ether_mtu = ifp->if_mtu; 6273 6274 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6275 6276 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", __FUNCTION__, 6277 ether_mtu); 6278 6279 /* Program the mtu, enabling jumbo frame support if necessary. */ 6280 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6281 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6282 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6283 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6284 else 6285 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6286 6287 DBPRINT(sc, BCE_INFO_LOAD, 6288 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, " 6289 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 6290 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 6291 sc->rx_bd_mbuf_align_pad); 6292 6293 /* Program appropriate promiscuous/multicast filtering. */ 6294 bce_set_rx_mode(sc); 6295 6296 #ifdef ZERO_COPY_SOCKETS 6297 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6298 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6299 6300 /* Init page buffer descriptor chain. */ 6301 bce_init_pg_chain(sc); 6302 #endif 6303 6304 /* Init RX buffer descriptor chain. */ 6305 bce_init_rx_chain(sc); 6306 6307 /* Init TX buffer descriptor chain. */ 6308 bce_init_tx_chain(sc); 6309 6310 /* Enable host interrupts. */ 6311 bce_enable_intr(sc, 1); 6312 6313 bce_ifmedia_upd_locked(ifp); 6314 6315 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6316 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6317 6318 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6319 6320 bce_init_locked_exit: 6321 DBEXIT(BCE_VERBOSE_RESET); 6322 } 6323 6324 6325 /****************************************************************************/ 6326 /* Initialize the controller just enough so that any management firmware */ 6327 /* running on the device will continue to operate correctly. */ 6328 /* */ 6329 /* Returns: */ 6330 /* Nothing. */ 6331 /****************************************************************************/ 6332 static void 6333 bce_mgmt_init_locked(struct bce_softc *sc) 6334 { 6335 struct ifnet *ifp; 6336 6337 DBENTER(BCE_VERBOSE_RESET); 6338 6339 BCE_LOCK_ASSERT(sc); 6340 6341 /* Bail out if management firmware is not running. */ 6342 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6343 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6344 "No management firmware running...\n"); 6345 goto bce_mgmt_init_locked_exit; 6346 } 6347 6348 ifp = sc->bce_ifp; 6349 6350 /* Enable all critical blocks in the MAC. */ 6351 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6352 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6353 DELAY(20); 6354 6355 bce_ifmedia_upd_locked(ifp); 6356 6357 bce_mgmt_init_locked_exit: 6358 DBEXIT(BCE_VERBOSE_RESET); 6359 } 6360 6361 6362 /****************************************************************************/ 6363 /* Handles controller initialization when called from an unlocked routine. */ 6364 /* */ 6365 /* Returns: */ 6366 /* Nothing. */ 6367 /****************************************************************************/ 6368 static void 6369 bce_init(void *xsc) 6370 { 6371 struct bce_softc *sc = xsc; 6372 6373 DBENTER(BCE_VERBOSE_RESET); 6374 6375 BCE_LOCK(sc); 6376 bce_init_locked(sc); 6377 BCE_UNLOCK(sc); 6378 6379 DBEXIT(BCE_VERBOSE_RESET); 6380 } 6381 6382 6383 /****************************************************************************/ 6384 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 6385 /* memory visible to the controller. */ 6386 /* */ 6387 /* Returns: */ 6388 /* 0 for success, positive value for failure. */ 6389 /* Modified: */ 6390 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 6391 /****************************************************************************/ 6392 static int 6393 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 6394 { 6395 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 6396 bus_dmamap_t map; 6397 struct tx_bd *txbd = NULL; 6398 struct mbuf *m0; 6399 struct ether_vlan_header *eh; 6400 struct ip *ip; 6401 struct tcphdr *th; 6402 u16 prod, chain_prod, etype, mss = 0, vlan_tag = 0, flags = 0; 6403 u32 prod_bseq; 6404 int hdr_len = 0, e_hlen = 0, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 6405 6406 #ifdef BCE_DEBUG 6407 u16 debug_prod; 6408 #endif 6409 int i, error, nsegs, rc = 0; 6410 6411 DBENTER(BCE_VERBOSE_SEND); 6412 DBPRINT(sc, BCE_INFO_SEND, 6413 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = %04X, " 6414 "tx_prod_bseq = 0x%08X\n", 6415 __FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod), 6416 sc->tx_prod_bseq); 6417 6418 /* Transfer any checksum offload flags to the bd. */ 6419 m0 = *m_head; 6420 if (m0->m_pkthdr.csum_flags) { 6421 if (m0->m_pkthdr.csum_flags & CSUM_IP) 6422 flags |= TX_BD_FLAGS_IP_CKSUM; 6423 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 6424 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 6425 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 6426 /* For TSO the controller needs two pieces of info, */ 6427 /* the MSS and the IP+TCP options length. */ 6428 mss = htole16(m0->m_pkthdr.tso_segsz); 6429 6430 /* Map the header and find the Ethernet type & header length */ 6431 eh = mtod(m0, struct ether_vlan_header *); 6432 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 6433 etype = ntohs(eh->evl_proto); 6434 e_hlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 6435 } else { 6436 etype = ntohs(eh->evl_encap_proto); 6437 e_hlen = ETHER_HDR_LEN; 6438 } 6439 6440 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 6441 switch (etype) { 6442 case ETHERTYPE_IP: 6443 ip = (struct ip *)(m0->m_data + e_hlen); 6444 6445 /* TSO only supported for TCP protocol */ 6446 if (ip->ip_p != IPPROTO_TCP) { 6447 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 6448 __FILE__, __LINE__); 6449 goto bce_tx_encap_skip_tso; 6450 } 6451 6452 /* Get IP header length in bytes (min 20) */ 6453 ip_hlen = ip->ip_hl << 2; 6454 6455 /* Get the TCP header length in bytes (min 20) */ 6456 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 6457 tcp_hlen = (th->th_off << 2); 6458 6459 /* IP header length and checksum will be calc'd by hardware */ 6460 ip_len = ip->ip_len; 6461 ip->ip_len = 0; 6462 ip->ip_sum = 0; 6463 break; 6464 case ETHERTYPE_IPV6: 6465 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 6466 __FILE__, __LINE__); 6467 goto bce_tx_encap_skip_tso; 6468 default: 6469 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 6470 __FILE__, __LINE__); 6471 goto bce_tx_encap_skip_tso; 6472 } 6473 6474 hdr_len = e_hlen + ip_hlen + tcp_hlen; 6475 6476 DBPRINT(sc, BCE_EXTREME_SEND, 6477 "%s(): hdr_len = %d, e_hlen = %d, ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 6478 __FUNCTION__, hdr_len, e_hlen, ip_hlen, tcp_hlen, ip_len); 6479 6480 /* Set the LSO flag in the TX BD */ 6481 flags |= TX_BD_FLAGS_SW_LSO; 6482 /* Set the length of IP + TCP options (in 32 bit words) */ 6483 flags |= (((ip_hlen + tcp_hlen - 40) >> 2) << 8); 6484 6485 bce_tx_encap_skip_tso: 6486 DBRUN(sc->requested_tso_frames++); 6487 } 6488 } 6489 6490 /* Transfer any VLAN tags to the bd. */ 6491 if (m0->m_flags & M_VLANTAG) { 6492 flags |= TX_BD_FLAGS_VLAN_TAG; 6493 vlan_tag = m0->m_pkthdr.ether_vtag; 6494 } 6495 6496 /* Map the mbuf into DMAable memory. */ 6497 prod = sc->tx_prod; 6498 chain_prod = TX_CHAIN_IDX(prod); 6499 map = sc->tx_mbuf_map[chain_prod]; 6500 6501 /* Map the mbuf into our DMA address space. */ 6502 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 6503 segs, &nsegs, BUS_DMA_NOWAIT); 6504 6505 /* Check if the DMA mapping was successful */ 6506 if (error == EFBIG) { 6507 6508 sc->fragmented_mbuf_count++; 6509 6510 /* Try to defrag the mbuf. */ 6511 m0 = m_defrag(*m_head, M_DONTWAIT); 6512 if (m0 == NULL) { 6513 /* Defrag was unsuccessful */ 6514 m_freem(*m_head); 6515 *m_head = NULL; 6516 sc->mbuf_alloc_failed_count++; 6517 rc = ENOBUFS; 6518 goto bce_tx_encap_exit; 6519 } 6520 6521 /* Defrag was successful, try mapping again */ 6522 *m_head = m0; 6523 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 6524 segs, &nsegs, BUS_DMA_NOWAIT); 6525 6526 /* Still getting an error after a defrag. */ 6527 if (error == ENOMEM) { 6528 /* Insufficient DMA buffers available. */ 6529 sc->dma_map_addr_tx_failed_count++; 6530 rc = error; 6531 goto bce_tx_encap_exit; 6532 } else if (error != 0) { 6533 /* Still can't map the mbuf, release it and return an error. */ 6534 BCE_PRINTF( 6535 "%s(%d): Unknown error mapping mbuf into TX chain!\n", 6536 __FILE__, __LINE__); 6537 m_freem(m0); 6538 *m_head = NULL; 6539 sc->dma_map_addr_tx_failed_count++; 6540 rc = ENOBUFS; 6541 goto bce_tx_encap_exit; 6542 } 6543 } else if (error == ENOMEM) { 6544 /* Insufficient DMA buffers available. */ 6545 sc->dma_map_addr_tx_failed_count++; 6546 rc = error; 6547 goto bce_tx_encap_exit; 6548 } else if (error != 0) { 6549 m_freem(m0); 6550 *m_head = NULL; 6551 sc->dma_map_addr_tx_failed_count++; 6552 rc = error; 6553 goto bce_tx_encap_exit; 6554 } 6555 6556 /* Make sure there's room in the chain */ 6557 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 6558 bus_dmamap_unload(sc->tx_mbuf_tag, map); 6559 rc = ENOBUFS; 6560 goto bce_tx_encap_exit; 6561 } 6562 6563 /* prod points to an empty tx_bd at this point. */ 6564 prod_bseq = sc->tx_prod_bseq; 6565 6566 #ifdef BCE_DEBUG 6567 debug_prod = chain_prod; 6568 #endif 6569 6570 DBPRINT(sc, BCE_INFO_SEND, 6571 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 6572 "prod_bseq = 0x%08X\n", 6573 __FUNCTION__, prod, chain_prod, prod_bseq); 6574 6575 /* 6576 * Cycle through each mbuf segment that makes up 6577 * the outgoing frame, gathering the mapping info 6578 * for that segment and creating a tx_bd for 6579 * the mbuf. 6580 */ 6581 for (i = 0; i < nsegs ; i++) { 6582 6583 chain_prod = TX_CHAIN_IDX(prod); 6584 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 6585 6586 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 6587 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 6588 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | htole16(segs[i].ds_len); 6589 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 6590 txbd->tx_bd_flags = htole16(flags); 6591 prod_bseq += segs[i].ds_len; 6592 if (i == 0) 6593 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 6594 prod = NEXT_TX_BD(prod); 6595 } 6596 6597 /* Set the END flag on the last TX buffer descriptor. */ 6598 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 6599 6600 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs)); 6601 6602 DBPRINT(sc, BCE_INFO_SEND, 6603 "%s( end ): prod = 0x%04X, chain_prod = 0x%04X, " 6604 "prod_bseq = 0x%08X\n", 6605 __FUNCTION__, prod, chain_prod, prod_bseq); 6606 6607 /* 6608 * Ensure that the mbuf pointer for this transmission 6609 * is placed at the array index of the last 6610 * descriptor in this chain. This is done 6611 * because a single map is used for all 6612 * segments of the mbuf and we don't want to 6613 * unload the map before all of the segments 6614 * have been freed. 6615 */ 6616 sc->tx_mbuf_ptr[chain_prod] = m0; 6617 sc->used_tx_bd += nsegs; 6618 6619 /* Update some debug statistic counters */ 6620 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 6621 sc->tx_hi_watermark = sc->used_tx_bd); 6622 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 6623 DBRUNIF(sc->debug_tx_mbuf_alloc++); 6624 6625 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 6626 6627 /* prod points to the next free tx_bd at this point. */ 6628 sc->tx_prod = prod; 6629 sc->tx_prod_bseq = prod_bseq; 6630 6631 DBPRINT(sc, BCE_INFO_SEND, 6632 "%s(exit): prod = 0x%04X, chain_prod = %04X, " 6633 "prod_bseq = 0x%08X\n", 6634 __FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod), 6635 sc->tx_prod_bseq); 6636 6637 bce_tx_encap_exit: 6638 DBEXIT(BCE_VERBOSE_SEND); 6639 return(rc); 6640 } 6641 6642 6643 /****************************************************************************/ 6644 /* Main transmit routine when called from another routine with a lock. */ 6645 /* */ 6646 /* Returns: */ 6647 /* Nothing. */ 6648 /****************************************************************************/ 6649 static void 6650 bce_start_locked(struct ifnet *ifp) 6651 { 6652 struct bce_softc *sc = ifp->if_softc; 6653 struct mbuf *m_head = NULL; 6654 int count = 0; 6655 u16 tx_prod, tx_chain_prod; 6656 6657 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 6658 6659 BCE_LOCK_ASSERT(sc); 6660 6661 /* prod points to the next free tx_bd. */ 6662 tx_prod = sc->tx_prod; 6663 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 6664 6665 DBPRINT(sc, BCE_INFO_SEND, 6666 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 6667 "tx_prod_bseq = 0x%08X\n", 6668 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 6669 6670 /* If there's no link or the transmit queue is empty then just exit. */ 6671 if (!sc->bce_link) { 6672 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 6673 __FUNCTION__); 6674 goto bce_start_locked_exit; 6675 } 6676 6677 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 6678 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 6679 __FUNCTION__); 6680 goto bce_start_locked_exit; 6681 } 6682 6683 /* 6684 * Keep adding entries while there is space in the ring. 6685 */ 6686 while (sc->used_tx_bd < sc->max_tx_bd) { 6687 6688 /* Check for any frames to send. */ 6689 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 6690 6691 /* Stop when the transmit queue is empty. */ 6692 if (m_head == NULL) 6693 break; 6694 6695 /* 6696 * Pack the data into the transmit ring. If we 6697 * don't have room, place the mbuf back at the 6698 * head of the queue and set the OACTIVE flag 6699 * to wait for the NIC to drain the chain. 6700 */ 6701 if (bce_tx_encap(sc, &m_head)) { 6702 /* No room, put the frame back on the transmit queue. */ 6703 if (m_head != NULL) 6704 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 6705 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 6706 DBPRINT(sc, BCE_INFO_SEND, 6707 "TX chain is closed for business! Total tx_bd used = %d\n", 6708 sc->used_tx_bd); 6709 break; 6710 } 6711 6712 count++; 6713 6714 /* Send a copy of the frame to any BPF listeners. */ 6715 ETHER_BPF_MTAP(ifp, m_head); 6716 } 6717 6718 /* Exit if no packets were dequeued. */ 6719 if (count == 0) { 6720 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n", 6721 __FUNCTION__); 6722 goto bce_start_locked_exit; 6723 } 6724 6725 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into send queue.\n", 6726 __FUNCTION__, count); 6727 6728 REG_WR(sc, BCE_MQ_COMMAND, REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR); 6729 6730 /* Write the mailbox and tell the chip about the waiting tx_bd's. */ 6731 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; " 6732 "BCE_L2MQ_TX_HOST_BIDX = 0x%08X, sc->tx_prod = 0x%04X\n", 6733 __FUNCTION__, 6734 MB_GET_CID_ADDR(TX_CID), BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 6735 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 6736 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; " 6737 "BCE_L2MQ_TX_HOST_BSEQ = 0x%08X, sc->tx_prod_bseq = 0x%04X\n", 6738 __FUNCTION__, 6739 MB_GET_CID_ADDR(TX_CID), BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 6740 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 6741 6742 /* Set the tx timeout. */ 6743 sc->watchdog_timer = BCE_TX_TIMEOUT; 6744 6745 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 6746 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 6747 6748 bce_start_locked_exit: 6749 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 6750 return; 6751 } 6752 6753 6754 /****************************************************************************/ 6755 /* Main transmit routine when called from another routine without a lock. */ 6756 /* */ 6757 /* Returns: */ 6758 /* Nothing. */ 6759 /****************************************************************************/ 6760 static void 6761 bce_start(struct ifnet *ifp) 6762 { 6763 struct bce_softc *sc = ifp->if_softc; 6764 6765 DBENTER(BCE_VERBOSE_SEND); 6766 6767 BCE_LOCK(sc); 6768 bce_start_locked(ifp); 6769 BCE_UNLOCK(sc); 6770 6771 DBEXIT(BCE_VERBOSE_SEND); 6772 } 6773 6774 6775 /****************************************************************************/ 6776 /* Handles any IOCTL calls from the operating system. */ 6777 /* */ 6778 /* Returns: */ 6779 /* 0 for success, positive value for failure. */ 6780 /****************************************************************************/ 6781 static int 6782 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 6783 { 6784 struct bce_softc *sc = ifp->if_softc; 6785 struct ifreq *ifr = (struct ifreq *) data; 6786 struct mii_data *mii; 6787 int mask, error = 0; 6788 6789 DBENTER(BCE_VERBOSE_MISC); 6790 6791 switch(command) { 6792 6793 /* Set the interface MTU. */ 6794 case SIOCSIFMTU: 6795 /* Check that the MTU setting is supported. */ 6796 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 6797 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 6798 error = EINVAL; 6799 break; 6800 } 6801 6802 DBPRINT(sc, BCE_INFO_MISC, 6803 "SIOCSIFMTU: Changing MTU from %d to %d\n", 6804 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 6805 6806 BCE_LOCK(sc); 6807 ifp->if_mtu = ifr->ifr_mtu; 6808 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 6809 #ifdef ZERO_COPY_SOCKETS 6810 /* No buffer allocation size changes are necessary. */ 6811 #else 6812 /* Recalculate our buffer allocation sizes. */ 6813 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN) > MCLBYTES) { 6814 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 6815 sc->rx_bd_mbuf_align_pad = roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 6816 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 6817 sc->rx_bd_mbuf_align_pad; 6818 } else { 6819 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 6820 sc->rx_bd_mbuf_align_pad = roundup2(MCLBYTES, 16) - MCLBYTES; 6821 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 6822 sc->rx_bd_mbuf_align_pad; 6823 } 6824 #endif 6825 6826 bce_init_locked(sc); 6827 BCE_UNLOCK(sc); 6828 break; 6829 6830 /* Set interface flags. */ 6831 case SIOCSIFFLAGS: 6832 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 6833 6834 BCE_LOCK(sc); 6835 6836 /* Check if the interface is up. */ 6837 if (ifp->if_flags & IFF_UP) { 6838 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 6839 /* Change promiscuous/multicast flags as necessary. */ 6840 bce_set_rx_mode(sc); 6841 } else { 6842 /* Start the HW */ 6843 bce_init_locked(sc); 6844 } 6845 } else { 6846 /* The interface is down, check if driver is running. */ 6847 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 6848 bce_stop(sc); 6849 6850 /* If MFW is running, restart the controller a bit. */ 6851 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 6852 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 6853 bce_chipinit(sc); 6854 bce_mgmt_init_locked(sc); 6855 } 6856 } 6857 } 6858 6859 BCE_UNLOCK(sc); 6860 error = 0; 6861 6862 break; 6863 6864 /* Add/Delete multicast address */ 6865 case SIOCADDMULTI: 6866 case SIOCDELMULTI: 6867 DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCADDMULTI/SIOCDELMULTI\n"); 6868 6869 BCE_LOCK(sc); 6870 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 6871 bce_set_rx_mode(sc); 6872 error = 0; 6873 } 6874 BCE_UNLOCK(sc); 6875 6876 break; 6877 6878 /* Set/Get Interface media */ 6879 case SIOCSIFMEDIA: 6880 case SIOCGIFMEDIA: 6881 DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 6882 6883 mii = device_get_softc(sc->bce_miibus); 6884 error = ifmedia_ioctl(ifp, ifr, 6885 &mii->mii_media, command); 6886 break; 6887 6888 /* Set interface capability */ 6889 case SIOCSIFCAP: 6890 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 6891 DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 6892 6893 /* Toggle the TX checksum capabilites enable flag. */ 6894 if (mask & IFCAP_TXCSUM) { 6895 ifp->if_capenable ^= IFCAP_TXCSUM; 6896 if (IFCAP_TXCSUM & ifp->if_capenable) 6897 ifp->if_hwassist = BCE_IF_HWASSIST; 6898 else 6899 ifp->if_hwassist = 0; 6900 } 6901 6902 /* Toggle the RX checksum capabilities enable flag. */ 6903 if (mask & IFCAP_RXCSUM) { 6904 ifp->if_capenable ^= IFCAP_RXCSUM; 6905 if (IFCAP_RXCSUM & ifp->if_capenable) 6906 ifp->if_hwassist = BCE_IF_HWASSIST; 6907 else 6908 ifp->if_hwassist = 0; 6909 } 6910 6911 /* Toggle the TSO capabilities enable flag. */ 6912 if (bce_tso_enable && (mask & IFCAP_TSO4)) { 6913 ifp->if_capenable ^= IFCAP_TSO4; 6914 if (IFCAP_RXCSUM & ifp->if_capenable) 6915 ifp->if_hwassist = BCE_IF_HWASSIST; 6916 else 6917 ifp->if_hwassist = 0; 6918 } 6919 6920 /* Toggle VLAN_MTU capabilities enable flag. */ 6921 if (mask & IFCAP_VLAN_MTU) { 6922 BCE_PRINTF("%s(%d): Changing VLAN_MTU not supported.\n", 6923 __FILE__, __LINE__); 6924 } 6925 6926 /* Toggle VLANHWTAG capabilities enabled flag. */ 6927 if (mask & IFCAP_VLAN_HWTAGGING) { 6928 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 6929 BCE_PRINTF("%s(%d): Cannot change VLAN_HWTAGGING while " 6930 "management firmware (ASF/IPMI/UMP) is running!\n", 6931 __FILE__, __LINE__); 6932 else 6933 BCE_PRINTF("%s(%d): Changing VLAN_HWTAGGING not supported!\n", 6934 __FILE__, __LINE__); 6935 } 6936 6937 break; 6938 default: 6939 /* We don't know how to handle the IOCTL, pass it on. */ 6940 error = ether_ioctl(ifp, command, data); 6941 break; 6942 } 6943 6944 DBEXIT(BCE_VERBOSE_MISC); 6945 return(error); 6946 } 6947 6948 6949 /****************************************************************************/ 6950 /* Transmit timeout handler. */ 6951 /* */ 6952 /* Returns: */ 6953 /* Nothing. */ 6954 /****************************************************************************/ 6955 static void 6956 bce_watchdog(struct bce_softc *sc) 6957 { 6958 DBENTER(BCE_EXTREME_SEND); 6959 6960 BCE_LOCK_ASSERT(sc); 6961 6962 /* If the watchdog timer hasn't expired then just exit. */ 6963 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 6964 goto bce_watchdog_exit; 6965 6966 /* If pause frames are active then don't reset the hardware. */ 6967 /* ToDo: Should we reset the timer here? */ 6968 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 6969 goto bce_watchdog_exit; 6970 6971 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 6972 __FILE__, __LINE__); 6973 6974 DBRUNMSG(BCE_INFO, 6975 bce_dump_driver_state(sc); 6976 bce_dump_status_block(sc); 6977 bce_dump_stats_block(sc); 6978 bce_dump_ftqs(sc); 6979 bce_dump_txp_state(sc, 0); 6980 bce_dump_rxp_state(sc, 0); 6981 bce_dump_tpat_state(sc, 0); 6982 bce_dump_cp_state(sc, 0); 6983 bce_dump_com_state(sc, 0)); 6984 6985 DBRUN(bce_breakpoint(sc)); 6986 6987 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 6988 6989 bce_init_locked(sc); 6990 sc->bce_ifp->if_oerrors++; 6991 6992 bce_watchdog_exit: 6993 DBEXIT(BCE_EXTREME_SEND); 6994 } 6995 6996 6997 /* 6998 * Interrupt handler. 6999 */ 7000 /****************************************************************************/ 7001 /* Main interrupt entry point. Verifies that the controller generated the */ 7002 /* interrupt and then calls a separate routine for handle the various */ 7003 /* interrupt causes (PHY, TX, RX). */ 7004 /* */ 7005 /* Returns: */ 7006 /* 0 for success, positive value for failure. */ 7007 /****************************************************************************/ 7008 static void 7009 bce_intr(void *xsc) 7010 { 7011 struct bce_softc *sc; 7012 struct ifnet *ifp; 7013 u32 status_attn_bits; 7014 u16 hw_rx_cons, hw_tx_cons; 7015 7016 sc = xsc; 7017 ifp = sc->bce_ifp; 7018 7019 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7020 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7021 7022 BCE_LOCK(sc); 7023 7024 DBRUN(sc->interrupts_generated++); 7025 7026 bus_dmamap_sync(sc->status_tag, sc->status_map, 7027 BUS_DMASYNC_POSTWRITE); 7028 7029 /* 7030 * If the hardware status block index 7031 * matches the last value read by the 7032 * driver and we haven't asserted our 7033 * interrupt then there's nothing to do. 7034 */ 7035 if ((sc->status_block->status_idx == sc->last_status_idx) && 7036 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7037 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7038 __FUNCTION__); 7039 goto bce_intr_exit; 7040 } 7041 7042 /* Ack the interrupt and stop others from occuring. */ 7043 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7044 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7045 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7046 7047 /* Check if the hardware has finished any work. */ 7048 hw_rx_cons = bce_get_hw_rx_cons(sc); 7049 hw_tx_cons = bce_get_hw_tx_cons(sc); 7050 7051 /* Keep processing data as long as there is work to do. */ 7052 for (;;) { 7053 7054 status_attn_bits = sc->status_block->status_attn_bits; 7055 7056 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7057 BCE_PRINTF("Simulating unexpected status attention bit set."); 7058 sc->unexpected_attention_sim_count++; 7059 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR); 7060 7061 /* Was it a link change interrupt? */ 7062 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7063 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) { 7064 bce_phy_intr(sc); 7065 7066 /* Clear any transient status updates during link state change. */ 7067 REG_WR(sc, BCE_HC_COMMAND, 7068 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT); 7069 REG_RD(sc, BCE_HC_COMMAND); 7070 } 7071 7072 /* If any other attention is asserted then the chip is toast. */ 7073 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7074 (sc->status_block->status_attn_bits_ack & 7075 ~STATUS_ATTN_BITS_LINK_STATE))) { 7076 7077 sc->unexpected_attention_count++; 7078 7079 BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n", 7080 __FILE__, __LINE__, sc->status_block->status_attn_bits); 7081 7082 DBRUNMSG(BCE_FATAL, 7083 if (unexpected_attention_sim_control == 0) 7084 bce_breakpoint(sc)); 7085 7086 bce_init_locked(sc); 7087 goto bce_intr_exit; 7088 } 7089 7090 /* Check for any completed RX frames. */ 7091 if (hw_rx_cons != sc->hw_rx_cons) 7092 bce_rx_intr(sc); 7093 7094 /* Check for any completed TX frames. */ 7095 if (hw_tx_cons != sc->hw_tx_cons) 7096 bce_tx_intr(sc); 7097 7098 /* Save the status block index value for use during the next interrupt. */ 7099 sc->last_status_idx = sc->status_block->status_idx; 7100 7101 /* Prevent speculative reads from getting ahead of the status block. */ 7102 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7103 BUS_SPACE_BARRIER_READ); 7104 7105 /* If there's no work left then exit the interrupt service routine. */ 7106 hw_rx_cons = bce_get_hw_rx_cons(sc); 7107 hw_tx_cons = bce_get_hw_tx_cons(sc); 7108 7109 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons)) 7110 break; 7111 7112 } 7113 7114 bus_dmamap_sync(sc->status_tag, sc->status_map, 7115 BUS_DMASYNC_PREWRITE); 7116 7117 /* Re-enable interrupts. */ 7118 bce_enable_intr(sc, 0); 7119 7120 /* Handle any frames that arrived while handling the interrupt. */ 7121 if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7122 bce_start_locked(ifp); 7123 7124 bce_intr_exit: 7125 BCE_UNLOCK(sc); 7126 7127 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7128 } 7129 7130 7131 /****************************************************************************/ 7132 /* Programs the various packet receive modes (broadcast and multicast). */ 7133 /* */ 7134 /* Returns: */ 7135 /* Nothing. */ 7136 /****************************************************************************/ 7137 static void 7138 bce_set_rx_mode(struct bce_softc *sc) 7139 { 7140 struct ifnet *ifp; 7141 struct ifmultiaddr *ifma; 7142 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7143 u32 rx_mode, sort_mode; 7144 int h, i; 7145 7146 DBENTER(BCE_VERBOSE_MISC); 7147 7148 BCE_LOCK_ASSERT(sc); 7149 7150 ifp = sc->bce_ifp; 7151 7152 /* Initialize receive mode default settings. */ 7153 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7154 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7155 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7156 7157 /* 7158 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7159 * be enbled. 7160 */ 7161 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7162 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7163 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7164 7165 /* 7166 * Check for promiscuous, all multicast, or selected 7167 * multicast address filtering. 7168 */ 7169 if (ifp->if_flags & IFF_PROMISC) { 7170 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7171 7172 /* Enable promiscuous mode. */ 7173 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7174 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7175 } else if (ifp->if_flags & IFF_ALLMULTI) { 7176 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7177 7178 /* Enable all multicast addresses. */ 7179 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7180 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7181 } 7182 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7183 } else { 7184 /* Accept one or more multicast(s). */ 7185 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7186 7187 IF_ADDR_LOCK(ifp); 7188 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7189 if (ifma->ifma_addr->sa_family != AF_LINK) 7190 continue; 7191 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7192 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7193 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7194 } 7195 IF_ADDR_UNLOCK(ifp); 7196 7197 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7198 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7199 7200 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7201 } 7202 7203 /* Only make changes if the recive mode has actually changed. */ 7204 if (rx_mode != sc->rx_mode) { 7205 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: 0x%08X\n", 7206 rx_mode); 7207 7208 sc->rx_mode = rx_mode; 7209 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7210 } 7211 7212 /* Disable and clear the exisitng sort before enabling a new sort. */ 7213 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7214 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7215 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7216 7217 DBEXIT(BCE_VERBOSE_MISC); 7218 } 7219 7220 7221 /****************************************************************************/ 7222 /* Called periodically to updates statistics from the controllers */ 7223 /* statistics block. */ 7224 /* */ 7225 /* Returns: */ 7226 /* Nothing. */ 7227 /****************************************************************************/ 7228 static void 7229 bce_stats_update(struct bce_softc *sc) 7230 { 7231 struct ifnet *ifp; 7232 struct statistics_block *stats; 7233 7234 DBENTER(BCE_EXTREME_MISC); 7235 7236 ifp = sc->bce_ifp; 7237 7238 stats = (struct statistics_block *) sc->stats_block; 7239 7240 /* 7241 * Certain controllers don't report 7242 * carrier sense errors correctly. 7243 * See errata E11_5708CA0_1165. 7244 */ 7245 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7246 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7247 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7248 7249 /* 7250 * Update the sysctl statistics from the 7251 * hardware statistics. 7252 */ 7253 sc->stat_IfHCInOctets = 7254 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7255 (u64) stats->stat_IfHCInOctets_lo; 7256 7257 sc->stat_IfHCInBadOctets = 7258 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7259 (u64) stats->stat_IfHCInBadOctets_lo; 7260 7261 sc->stat_IfHCOutOctets = 7262 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7263 (u64) stats->stat_IfHCOutOctets_lo; 7264 7265 sc->stat_IfHCOutBadOctets = 7266 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7267 (u64) stats->stat_IfHCOutBadOctets_lo; 7268 7269 sc->stat_IfHCInUcastPkts = 7270 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7271 (u64) stats->stat_IfHCInUcastPkts_lo; 7272 7273 sc->stat_IfHCInMulticastPkts = 7274 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7275 (u64) stats->stat_IfHCInMulticastPkts_lo; 7276 7277 sc->stat_IfHCInBroadcastPkts = 7278 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7279 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7280 7281 sc->stat_IfHCOutUcastPkts = 7282 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7283 (u64) stats->stat_IfHCOutUcastPkts_lo; 7284 7285 sc->stat_IfHCOutMulticastPkts = 7286 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7287 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7288 7289 sc->stat_IfHCOutBroadcastPkts = 7290 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7291 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7292 7293 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7294 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7295 7296 sc->stat_Dot3StatsCarrierSenseErrors = 7297 stats->stat_Dot3StatsCarrierSenseErrors; 7298 7299 sc->stat_Dot3StatsFCSErrors = 7300 stats->stat_Dot3StatsFCSErrors; 7301 7302 sc->stat_Dot3StatsAlignmentErrors = 7303 stats->stat_Dot3StatsAlignmentErrors; 7304 7305 sc->stat_Dot3StatsSingleCollisionFrames = 7306 stats->stat_Dot3StatsSingleCollisionFrames; 7307 7308 sc->stat_Dot3StatsMultipleCollisionFrames = 7309 stats->stat_Dot3StatsMultipleCollisionFrames; 7310 7311 sc->stat_Dot3StatsDeferredTransmissions = 7312 stats->stat_Dot3StatsDeferredTransmissions; 7313 7314 sc->stat_Dot3StatsExcessiveCollisions = 7315 stats->stat_Dot3StatsExcessiveCollisions; 7316 7317 sc->stat_Dot3StatsLateCollisions = 7318 stats->stat_Dot3StatsLateCollisions; 7319 7320 sc->stat_EtherStatsCollisions = 7321 stats->stat_EtherStatsCollisions; 7322 7323 sc->stat_EtherStatsFragments = 7324 stats->stat_EtherStatsFragments; 7325 7326 sc->stat_EtherStatsJabbers = 7327 stats->stat_EtherStatsJabbers; 7328 7329 sc->stat_EtherStatsUndersizePkts = 7330 stats->stat_EtherStatsUndersizePkts; 7331 7332 sc->stat_EtherStatsOversizePkts = 7333 stats->stat_EtherStatsOversizePkts; 7334 7335 sc->stat_EtherStatsPktsRx64Octets = 7336 stats->stat_EtherStatsPktsRx64Octets; 7337 7338 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 7339 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 7340 7341 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 7342 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 7343 7344 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 7345 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 7346 7347 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 7348 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 7349 7350 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 7351 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 7352 7353 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 7354 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 7355 7356 sc->stat_EtherStatsPktsTx64Octets = 7357 stats->stat_EtherStatsPktsTx64Octets; 7358 7359 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 7360 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 7361 7362 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 7363 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 7364 7365 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 7366 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 7367 7368 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 7369 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 7370 7371 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 7372 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 7373 7374 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 7375 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 7376 7377 sc->stat_XonPauseFramesReceived = 7378 stats->stat_XonPauseFramesReceived; 7379 7380 sc->stat_XoffPauseFramesReceived = 7381 stats->stat_XoffPauseFramesReceived; 7382 7383 sc->stat_OutXonSent = 7384 stats->stat_OutXonSent; 7385 7386 sc->stat_OutXoffSent = 7387 stats->stat_OutXoffSent; 7388 7389 sc->stat_FlowControlDone = 7390 stats->stat_FlowControlDone; 7391 7392 sc->stat_MacControlFramesReceived = 7393 stats->stat_MacControlFramesReceived; 7394 7395 sc->stat_XoffStateEntered = 7396 stats->stat_XoffStateEntered; 7397 7398 sc->stat_IfInFramesL2FilterDiscards = 7399 stats->stat_IfInFramesL2FilterDiscards; 7400 7401 sc->stat_IfInRuleCheckerDiscards = 7402 stats->stat_IfInRuleCheckerDiscards; 7403 7404 sc->stat_IfInFTQDiscards = 7405 stats->stat_IfInFTQDiscards; 7406 7407 sc->stat_IfInMBUFDiscards = 7408 stats->stat_IfInMBUFDiscards; 7409 7410 sc->stat_IfInRuleCheckerP4Hit = 7411 stats->stat_IfInRuleCheckerP4Hit; 7412 7413 sc->stat_CatchupInRuleCheckerDiscards = 7414 stats->stat_CatchupInRuleCheckerDiscards; 7415 7416 sc->stat_CatchupInFTQDiscards = 7417 stats->stat_CatchupInFTQDiscards; 7418 7419 sc->stat_CatchupInMBUFDiscards = 7420 stats->stat_CatchupInMBUFDiscards; 7421 7422 sc->stat_CatchupInRuleCheckerP4Hit = 7423 stats->stat_CatchupInRuleCheckerP4Hit; 7424 7425 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 7426 7427 /* 7428 * Update the interface statistics from the 7429 * hardware statistics. 7430 */ 7431 ifp->if_collisions = 7432 (u_long) sc->stat_EtherStatsCollisions; 7433 7434 /* ToDo: This method loses soft errors. */ 7435 ifp->if_ierrors = 7436 (u_long) sc->stat_EtherStatsUndersizePkts + 7437 (u_long) sc->stat_EtherStatsOversizePkts + 7438 (u_long) sc->stat_IfInMBUFDiscards + 7439 (u_long) sc->stat_Dot3StatsAlignmentErrors + 7440 (u_long) sc->stat_Dot3StatsFCSErrors + 7441 (u_long) sc->stat_IfInRuleCheckerDiscards + 7442 (u_long) sc->stat_IfInFTQDiscards + 7443 (u_long) sc->com_no_buffers; 7444 7445 /* ToDo: This method loses soft errors. */ 7446 ifp->if_oerrors = 7447 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 7448 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 7449 (u_long) sc->stat_Dot3StatsLateCollisions; 7450 7451 /* ToDo: Add additional statistics. */ 7452 7453 DBEXIT(BCE_EXTREME_MISC); 7454 } 7455 7456 7457 /****************************************************************************/ 7458 /* Periodic function to notify the bootcode that the driver is still */ 7459 /* present. */ 7460 /* */ 7461 /* Returns: */ 7462 /* Nothing. */ 7463 /****************************************************************************/ 7464 static void 7465 bce_pulse(void *xsc) 7466 { 7467 struct bce_softc *sc = xsc; 7468 u32 msg; 7469 7470 DBENTER(BCE_EXTREME_MISC); 7471 7472 BCE_LOCK_ASSERT(sc); 7473 7474 /* Tell the firmware that the driver is still running. */ 7475 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 7476 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg); 7477 7478 /* Schedule the next pulse. */ 7479 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 7480 7481 DBEXIT(BCE_EXTREME_MISC); 7482 } 7483 7484 7485 /****************************************************************************/ 7486 /* Periodic function to perform maintenance tasks. */ 7487 /* */ 7488 /* Returns: */ 7489 /* Nothing. */ 7490 /****************************************************************************/ 7491 static void 7492 bce_tick(void *xsc) 7493 { 7494 struct bce_softc *sc = xsc; 7495 struct mii_data *mii; 7496 struct ifnet *ifp; 7497 7498 ifp = sc->bce_ifp; 7499 7500 DBENTER(BCE_EXTREME_MISC); 7501 7502 BCE_LOCK_ASSERT(sc); 7503 7504 /* Schedule the next tick. */ 7505 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7506 7507 /* Update the statistics from the hardware statistics block. */ 7508 bce_stats_update(sc); 7509 7510 /* Top off the receive and page chains. */ 7511 #ifdef ZERO_COPY_SOCKETS 7512 bce_fill_pg_chain(sc); 7513 #endif 7514 bce_fill_rx_chain(sc); 7515 7516 /* Check that chip hasn't hung. */ 7517 bce_watchdog(sc); 7518 7519 /* If link is up already up then we're done. */ 7520 if (sc->bce_link) 7521 goto bce_tick_exit; 7522 7523 /* Link is down. Check what the PHY's doing. */ 7524 mii = device_get_softc(sc->bce_miibus); 7525 mii_tick(mii); 7526 7527 /* Check if the link has come up. */ 7528 if ((mii->mii_media_status & IFM_ACTIVE) && 7529 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 7530 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", __FUNCTION__); 7531 sc->bce_link++; 7532 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 7533 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) && 7534 bootverbose) 7535 BCE_PRINTF("Gigabit link up!\n"); 7536 /* Now that link is up, handle any outstanding TX traffic. */ 7537 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7538 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found pending TX traffic.\n", 7539 __FUNCTION__); 7540 bce_start_locked(ifp); 7541 } 7542 } 7543 7544 bce_tick_exit: 7545 DBEXIT(BCE_EXTREME_MISC); 7546 return; 7547 } 7548 7549 7550 #ifdef BCE_DEBUG 7551 /****************************************************************************/ 7552 /* Allows the driver state to be dumped through the sysctl interface. */ 7553 /* */ 7554 /* Returns: */ 7555 /* 0 for success, positive value for failure. */ 7556 /****************************************************************************/ 7557 static int 7558 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 7559 { 7560 int error; 7561 int result; 7562 struct bce_softc *sc; 7563 7564 result = -1; 7565 error = sysctl_handle_int(oidp, &result, 0, req); 7566 7567 if (error || !req->newptr) 7568 return (error); 7569 7570 if (result == 1) { 7571 sc = (struct bce_softc *)arg1; 7572 bce_dump_driver_state(sc); 7573 } 7574 7575 return error; 7576 } 7577 7578 7579 /****************************************************************************/ 7580 /* Allows the hardware state to be dumped through the sysctl interface. */ 7581 /* */ 7582 /* Returns: */ 7583 /* 0 for success, positive value for failure. */ 7584 /****************************************************************************/ 7585 static int 7586 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 7587 { 7588 int error; 7589 int result; 7590 struct bce_softc *sc; 7591 7592 result = -1; 7593 error = sysctl_handle_int(oidp, &result, 0, req); 7594 7595 if (error || !req->newptr) 7596 return (error); 7597 7598 if (result == 1) { 7599 sc = (struct bce_softc *)arg1; 7600 bce_dump_hw_state(sc); 7601 } 7602 7603 return error; 7604 } 7605 7606 7607 /****************************************************************************/ 7608 /* Allows the bootcode state to be dumped through the sysctl interface. */ 7609 /* */ 7610 /* Returns: */ 7611 /* 0 for success, positive value for failure. */ 7612 /****************************************************************************/ 7613 static int 7614 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 7615 { 7616 int error; 7617 int result; 7618 struct bce_softc *sc; 7619 7620 result = -1; 7621 error = sysctl_handle_int(oidp, &result, 0, req); 7622 7623 if (error || !req->newptr) 7624 return (error); 7625 7626 if (result == 1) { 7627 sc = (struct bce_softc *)arg1; 7628 bce_dump_bc_state(sc); 7629 } 7630 7631 return error; 7632 } 7633 7634 7635 /****************************************************************************/ 7636 /* Provides a sysctl interface to allow dumping the RX chain. */ 7637 /* */ 7638 /* Returns: */ 7639 /* 0 for success, positive value for failure. */ 7640 /****************************************************************************/ 7641 static int 7642 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS) 7643 { 7644 int error; 7645 int result; 7646 struct bce_softc *sc; 7647 7648 result = -1; 7649 error = sysctl_handle_int(oidp, &result, 0, req); 7650 7651 if (error || !req->newptr) 7652 return (error); 7653 7654 if (result == 1) { 7655 sc = (struct bce_softc *)arg1; 7656 bce_dump_rx_chain(sc, 0, TOTAL_RX_BD); 7657 } 7658 7659 return error; 7660 } 7661 7662 7663 /****************************************************************************/ 7664 /* Provides a sysctl interface to allow dumping the TX chain. */ 7665 /* */ 7666 /* Returns: */ 7667 /* 0 for success, positive value for failure. */ 7668 /****************************************************************************/ 7669 static int 7670 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 7671 { 7672 int error; 7673 int result; 7674 struct bce_softc *sc; 7675 7676 result = -1; 7677 error = sysctl_handle_int(oidp, &result, 0, req); 7678 7679 if (error || !req->newptr) 7680 return (error); 7681 7682 if (result == 1) { 7683 sc = (struct bce_softc *)arg1; 7684 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 7685 } 7686 7687 return error; 7688 } 7689 7690 7691 #ifdef ZERO_COPY_SOCKETS 7692 /****************************************************************************/ 7693 /* Provides a sysctl interface to allow dumping the page chain. */ 7694 /* */ 7695 /* Returns: */ 7696 /* 0 for success, positive value for failure. */ 7697 /****************************************************************************/ 7698 static int 7699 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 7700 { 7701 int error; 7702 int result; 7703 struct bce_softc *sc; 7704 7705 result = -1; 7706 error = sysctl_handle_int(oidp, &result, 0, req); 7707 7708 if (error || !req->newptr) 7709 return (error); 7710 7711 if (result == 1) { 7712 sc = (struct bce_softc *)arg1; 7713 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD); 7714 } 7715 7716 return error; 7717 } 7718 #endif 7719 7720 /****************************************************************************/ 7721 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 7722 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 7723 /* */ 7724 /* Returns: */ 7725 /* 0 for success, positive value for failure. */ 7726 /****************************************************************************/ 7727 static int 7728 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 7729 { 7730 struct bce_softc *sc = (struct bce_softc *)arg1; 7731 int error; 7732 u32 result; 7733 u32 val[1]; 7734 u8 *data = (u8 *) val; 7735 7736 result = -1; 7737 error = sysctl_handle_int(oidp, &result, 0, req); 7738 if (error || (req->newptr == NULL)) 7739 return (error); 7740 7741 bce_nvram_read(sc, result, data, 4); 7742 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 7743 7744 return (error); 7745 } 7746 7747 7748 /****************************************************************************/ 7749 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 7750 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 7751 /* */ 7752 /* Returns: */ 7753 /* 0 for success, positive value for failure. */ 7754 /****************************************************************************/ 7755 static int 7756 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 7757 { 7758 struct bce_softc *sc = (struct bce_softc *)arg1; 7759 int error; 7760 u32 val, result; 7761 7762 result = -1; 7763 error = sysctl_handle_int(oidp, &result, 0, req); 7764 if (error || (req->newptr == NULL)) 7765 return (error); 7766 7767 /* Make sure the register is accessible. */ 7768 if (result < 0x8000) { 7769 val = REG_RD(sc, result); 7770 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 7771 } else if (result < 0x0280000) { 7772 val = REG_RD_IND(sc, result); 7773 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 7774 } 7775 7776 return (error); 7777 } 7778 7779 7780 /****************************************************************************/ 7781 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 7782 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 7783 /* */ 7784 /* Returns: */ 7785 /* 0 for success, positive value for failure. */ 7786 /****************************************************************************/ 7787 static int 7788 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 7789 { 7790 struct bce_softc *sc; 7791 device_t dev; 7792 int error, result; 7793 u16 val; 7794 7795 result = -1; 7796 error = sysctl_handle_int(oidp, &result, 0, req); 7797 if (error || (req->newptr == NULL)) 7798 return (error); 7799 7800 /* Make sure the register is accessible. */ 7801 if (result < 0x20) { 7802 sc = (struct bce_softc *)arg1; 7803 dev = sc->bce_dev; 7804 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 7805 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 7806 } 7807 return (error); 7808 } 7809 7810 7811 /****************************************************************************/ 7812 /* Provides a sysctl interface to allow reading a CID. */ 7813 /* */ 7814 /* Returns: */ 7815 /* 0 for success, positive value for failure. */ 7816 /****************************************************************************/ 7817 static int 7818 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 7819 { 7820 struct bce_softc *sc; 7821 int error; 7822 u16 result; 7823 7824 result = -1; 7825 error = sysctl_handle_int(oidp, &result, 0, req); 7826 if (error || (req->newptr == NULL)) 7827 return (error); 7828 7829 /* Make sure the register is accessible. */ 7830 if (result <= TX_CID) { 7831 sc = (struct bce_softc *)arg1; 7832 bce_dump_ctx(sc, result); 7833 } 7834 7835 return (error); 7836 } 7837 7838 7839 /****************************************************************************/ 7840 /* Provides a sysctl interface to forcing the driver to dump state and */ 7841 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 7842 /* */ 7843 /* Returns: */ 7844 /* 0 for success, positive value for failure. */ 7845 /****************************************************************************/ 7846 static int 7847 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 7848 { 7849 int error; 7850 int result; 7851 struct bce_softc *sc; 7852 7853 result = -1; 7854 error = sysctl_handle_int(oidp, &result, 0, req); 7855 7856 if (error || !req->newptr) 7857 return (error); 7858 7859 if (result == 1) { 7860 sc = (struct bce_softc *)arg1; 7861 bce_breakpoint(sc); 7862 } 7863 7864 return error; 7865 } 7866 #endif 7867 7868 7869 /****************************************************************************/ 7870 /* Adds any sysctl parameters for tuning or debugging purposes. */ 7871 /* */ 7872 /* Returns: */ 7873 /* 0 for success, positive value for failure. */ 7874 /****************************************************************************/ 7875 static void 7876 bce_add_sysctls(struct bce_softc *sc) 7877 { 7878 struct sysctl_ctx_list *ctx; 7879 struct sysctl_oid_list *children; 7880 7881 DBENTER(BCE_VERBOSE_MISC); 7882 7883 ctx = device_get_sysctl_ctx(sc->bce_dev); 7884 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 7885 7886 #ifdef BCE_DEBUG 7887 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7888 "l2fhdr_error_sim_control", 7889 CTLFLAG_RW, &l2fhdr_error_sim_control, 7890 0, "Debug control to force l2fhdr errors"); 7891 7892 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7893 "l2fhdr_error_sim_count", 7894 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 7895 0, "Number of simulated l2_fhdr errors"); 7896 #endif 7897 7898 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7899 "l2fhdr_error_count", 7900 CTLFLAG_RD, &sc->l2fhdr_error_count, 7901 0, "Number of l2_fhdr errors"); 7902 7903 #ifdef BCE_DEBUG 7904 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7905 "mbuf_alloc_failed_sim_control", 7906 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 7907 0, "Debug control to force mbuf allocation failures"); 7908 7909 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7910 "mbuf_alloc_failed_sim_count", 7911 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 7912 0, "Number of simulated mbuf cluster allocation failures"); 7913 #endif 7914 7915 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7916 "mbuf_alloc_failed_count", 7917 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 7918 0, "Number of mbuf allocation failures"); 7919 7920 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7921 "fragmented_mbuf_count", 7922 CTLFLAG_RD, &sc->fragmented_mbuf_count, 7923 0, "Number of fragmented mbufs"); 7924 7925 #ifdef BCE_DEBUG 7926 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7927 "dma_map_addr_failed_sim_control", 7928 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 7929 0, "Debug control to force DMA mapping failures"); 7930 7931 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 7932 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7933 "dma_map_addr_failed_sim_count", 7934 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 7935 0, "Number of simulated DMA mapping failures"); 7936 7937 #endif 7938 7939 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7940 "dma_map_addr_rx_failed_count", 7941 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 7942 0, "Number of RX DMA mapping failures"); 7943 7944 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7945 "dma_map_addr_tx_failed_count", 7946 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 7947 0, "Number of TX DMA mapping failures"); 7948 7949 #ifdef BCE_DEBUG 7950 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7951 "unexpected_attention_sim_control", 7952 CTLFLAG_RW, &unexpected_attention_sim_control, 7953 0, "Debug control to simulate unexpected attentions"); 7954 7955 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7956 "unexpected_attention_sim_count", 7957 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 7958 0, "Number of simulated unexpected attentions"); 7959 #endif 7960 7961 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7962 "unexpected_attention_count", 7963 CTLFLAG_RW, &sc->unexpected_attention_count, 7964 0, "Number of unexpected attentions"); 7965 7966 #ifdef BCE_DEBUG 7967 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7968 "debug_bootcode_running_failure", 7969 CTLFLAG_RW, &bootcode_running_failure_sim_control, 7970 0, "Debug control to force bootcode running failures"); 7971 7972 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7973 "rx_low_watermark", 7974 CTLFLAG_RD, &sc->rx_low_watermark, 7975 0, "Lowest level of free rx_bd's"); 7976 7977 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7978 "rx_empty_count", 7979 CTLFLAG_RD, &sc->rx_empty_count, 7980 0, "Number of times the RX chain was empty"); 7981 7982 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7983 "tx_hi_watermark", 7984 CTLFLAG_RD, &sc->tx_hi_watermark, 7985 0, "Highest level of used tx_bd's"); 7986 7987 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7988 "tx_full_count", 7989 CTLFLAG_RD, &sc->tx_full_count, 7990 0, "Number of times the TX chain was full"); 7991 7992 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 7993 "requested_tso_frames", 7994 CTLFLAG_RD, &sc->requested_tso_frames, 7995 0, "Number of TSO frames received"); 7996 7997 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 7998 "rx_interrupts", 7999 CTLFLAG_RD, &sc->rx_interrupts, 8000 0, "Number of RX interrupts"); 8001 8002 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8003 "tx_interrupts", 8004 CTLFLAG_RD, &sc->tx_interrupts, 8005 0, "Number of TX interrupts"); 8006 8007 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8008 "rx_intr_time", 8009 CTLFLAG_RD, &sc->rx_intr_time, 8010 "RX interrupt time"); 8011 8012 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8013 "tx_intr_time", 8014 CTLFLAG_RD, &sc->tx_intr_time, 8015 "TX interrupt time"); 8016 #endif 8017 8018 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8019 "stat_IfHcInOctets", 8020 CTLFLAG_RD, &sc->stat_IfHCInOctets, 8021 "Bytes received"); 8022 8023 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8024 "stat_IfHCInBadOctets", 8025 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 8026 "Bad bytes received"); 8027 8028 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8029 "stat_IfHCOutOctets", 8030 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 8031 "Bytes sent"); 8032 8033 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8034 "stat_IfHCOutBadOctets", 8035 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 8036 "Bad bytes sent"); 8037 8038 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8039 "stat_IfHCInUcastPkts", 8040 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 8041 "Unicast packets received"); 8042 8043 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8044 "stat_IfHCInMulticastPkts", 8045 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 8046 "Multicast packets received"); 8047 8048 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8049 "stat_IfHCInBroadcastPkts", 8050 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 8051 "Broadcast packets received"); 8052 8053 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8054 "stat_IfHCOutUcastPkts", 8055 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 8056 "Unicast packets sent"); 8057 8058 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8059 "stat_IfHCOutMulticastPkts", 8060 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 8061 "Multicast packets sent"); 8062 8063 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 8064 "stat_IfHCOutBroadcastPkts", 8065 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 8066 "Broadcast packets sent"); 8067 8068 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8069 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 8070 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 8071 0, "Internal MAC transmit errors"); 8072 8073 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8074 "stat_Dot3StatsCarrierSenseErrors", 8075 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 8076 0, "Carrier sense errors"); 8077 8078 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8079 "stat_Dot3StatsFCSErrors", 8080 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 8081 0, "Frame check sequence errors"); 8082 8083 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8084 "stat_Dot3StatsAlignmentErrors", 8085 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 8086 0, "Alignment errors"); 8087 8088 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8089 "stat_Dot3StatsSingleCollisionFrames", 8090 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 8091 0, "Single Collision Frames"); 8092 8093 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8094 "stat_Dot3StatsMultipleCollisionFrames", 8095 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 8096 0, "Multiple Collision Frames"); 8097 8098 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8099 "stat_Dot3StatsDeferredTransmissions", 8100 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 8101 0, "Deferred Transmissions"); 8102 8103 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8104 "stat_Dot3StatsExcessiveCollisions", 8105 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 8106 0, "Excessive Collisions"); 8107 8108 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8109 "stat_Dot3StatsLateCollisions", 8110 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 8111 0, "Late Collisions"); 8112 8113 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8114 "stat_EtherStatsCollisions", 8115 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 8116 0, "Collisions"); 8117 8118 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8119 "stat_EtherStatsFragments", 8120 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 8121 0, "Fragments"); 8122 8123 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8124 "stat_EtherStatsJabbers", 8125 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 8126 0, "Jabbers"); 8127 8128 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8129 "stat_EtherStatsUndersizePkts", 8130 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 8131 0, "Undersize packets"); 8132 8133 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8134 "stat_EtherStatsOversizePkts", 8135 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 8136 0, "stat_EtherStatsOversizePkts"); 8137 8138 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8139 "stat_EtherStatsPktsRx64Octets", 8140 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 8141 0, "Bytes received in 64 byte packets"); 8142 8143 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8144 "stat_EtherStatsPktsRx65Octetsto127Octets", 8145 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 8146 0, "Bytes received in 65 to 127 byte packets"); 8147 8148 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8149 "stat_EtherStatsPktsRx128Octetsto255Octets", 8150 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 8151 0, "Bytes received in 128 to 255 byte packets"); 8152 8153 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8154 "stat_EtherStatsPktsRx256Octetsto511Octets", 8155 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 8156 0, "Bytes received in 256 to 511 byte packets"); 8157 8158 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8159 "stat_EtherStatsPktsRx512Octetsto1023Octets", 8160 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 8161 0, "Bytes received in 512 to 1023 byte packets"); 8162 8163 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8164 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 8165 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 8166 0, "Bytes received in 1024 t0 1522 byte packets"); 8167 8168 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8169 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 8170 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 8171 0, "Bytes received in 1523 to 9022 byte packets"); 8172 8173 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8174 "stat_EtherStatsPktsTx64Octets", 8175 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 8176 0, "Bytes sent in 64 byte packets"); 8177 8178 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8179 "stat_EtherStatsPktsTx65Octetsto127Octets", 8180 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 8181 0, "Bytes sent in 65 to 127 byte packets"); 8182 8183 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8184 "stat_EtherStatsPktsTx128Octetsto255Octets", 8185 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 8186 0, "Bytes sent in 128 to 255 byte packets"); 8187 8188 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8189 "stat_EtherStatsPktsTx256Octetsto511Octets", 8190 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 8191 0, "Bytes sent in 256 to 511 byte packets"); 8192 8193 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8194 "stat_EtherStatsPktsTx512Octetsto1023Octets", 8195 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 8196 0, "Bytes sent in 512 to 1023 byte packets"); 8197 8198 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8199 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 8200 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 8201 0, "Bytes sent in 1024 to 1522 byte packets"); 8202 8203 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8204 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 8205 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 8206 0, "Bytes sent in 1523 to 9022 byte packets"); 8207 8208 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8209 "stat_XonPauseFramesReceived", 8210 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 8211 0, "XON pause frames receved"); 8212 8213 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8214 "stat_XoffPauseFramesReceived", 8215 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 8216 0, "XOFF pause frames received"); 8217 8218 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8219 "stat_OutXonSent", 8220 CTLFLAG_RD, &sc->stat_OutXonSent, 8221 0, "XON pause frames sent"); 8222 8223 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8224 "stat_OutXoffSent", 8225 CTLFLAG_RD, &sc->stat_OutXoffSent, 8226 0, "XOFF pause frames sent"); 8227 8228 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8229 "stat_FlowControlDone", 8230 CTLFLAG_RD, &sc->stat_FlowControlDone, 8231 0, "Flow control done"); 8232 8233 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8234 "stat_MacControlFramesReceived", 8235 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 8236 0, "MAC control frames received"); 8237 8238 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8239 "stat_XoffStateEntered", 8240 CTLFLAG_RD, &sc->stat_XoffStateEntered, 8241 0, "XOFF state entered"); 8242 8243 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8244 "stat_IfInFramesL2FilterDiscards", 8245 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 8246 0, "Received L2 packets discarded"); 8247 8248 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8249 "stat_IfInRuleCheckerDiscards", 8250 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 8251 0, "Received packets discarded by rule"); 8252 8253 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8254 "stat_IfInFTQDiscards", 8255 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 8256 0, "Received packet FTQ discards"); 8257 8258 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8259 "stat_IfInMBUFDiscards", 8260 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 8261 0, "Received packets discarded due to lack of controller buffer memory"); 8262 8263 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8264 "stat_IfInRuleCheckerP4Hit", 8265 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 8266 0, "Received packets rule checker hits"); 8267 8268 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8269 "stat_CatchupInRuleCheckerDiscards", 8270 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 8271 0, "Received packets discarded in Catchup path"); 8272 8273 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8274 "stat_CatchupInFTQDiscards", 8275 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 8276 0, "Received packets discarded in FTQ in Catchup path"); 8277 8278 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8279 "stat_CatchupInMBUFDiscards", 8280 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 8281 0, "Received packets discarded in controller buffer memory in Catchup path"); 8282 8283 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8284 "stat_CatchupInRuleCheckerP4Hit", 8285 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 8286 0, "Received packets rule checker hits in Catchup path"); 8287 8288 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8289 "com_no_buffers", 8290 CTLFLAG_RD, &sc->com_no_buffers, 8291 0, "Valid packets received but no RX buffers available"); 8292 8293 #ifdef BCE_DEBUG 8294 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8295 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 8296 (void *)sc, 0, 8297 bce_sysctl_driver_state, "I", "Drive state information"); 8298 8299 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8300 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 8301 (void *)sc, 0, 8302 bce_sysctl_hw_state, "I", "Hardware state information"); 8303 8304 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8305 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 8306 (void *)sc, 0, 8307 bce_sysctl_bc_state, "I", "Bootcode state information"); 8308 8309 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8310 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW, 8311 (void *)sc, 0, 8312 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain"); 8313 8314 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8315 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 8316 (void *)sc, 0, 8317 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 8318 8319 #ifdef ZERO_COPY_SOCKETS 8320 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8321 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 8322 (void *)sc, 0, 8323 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 8324 #endif 8325 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8326 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 8327 (void *)sc, 0, 8328 bce_sysctl_dump_ctx, "I", "Dump context memory"); 8329 8330 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8331 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 8332 (void *)sc, 0, 8333 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 8334 8335 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8336 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 8337 (void *)sc, 0, 8338 bce_sysctl_reg_read, "I", "Register read"); 8339 8340 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8341 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 8342 (void *)sc, 0, 8343 bce_sysctl_nvram_read, "I", "NVRAM read"); 8344 8345 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8346 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 8347 (void *)sc, 0, 8348 bce_sysctl_phy_read, "I", "PHY register read"); 8349 8350 #endif 8351 8352 DBEXIT(BCE_VERBOSE_MISC); 8353 } 8354 8355 8356 /****************************************************************************/ 8357 /* BCE Debug Routines */ 8358 /****************************************************************************/ 8359 #ifdef BCE_DEBUG 8360 8361 /****************************************************************************/ 8362 /* Freezes the controller to allow for a cohesive state dump. */ 8363 /* */ 8364 /* Returns: */ 8365 /* Nothing. */ 8366 /****************************************************************************/ 8367 static void 8368 bce_freeze_controller(struct bce_softc *sc) 8369 { 8370 u32 val; 8371 val = REG_RD(sc, BCE_MISC_COMMAND); 8372 val |= BCE_MISC_COMMAND_DISABLE_ALL; 8373 REG_WR(sc, BCE_MISC_COMMAND, val); 8374 } 8375 8376 8377 /****************************************************************************/ 8378 /* Unfreezes the controller after a freeze operation. This may not always */ 8379 /* work and the controller will require a reset! */ 8380 /* */ 8381 /* Returns: */ 8382 /* Nothing. */ 8383 /****************************************************************************/ 8384 static void 8385 bce_unfreeze_controller(struct bce_softc *sc) 8386 { 8387 u32 val; 8388 val = REG_RD(sc, BCE_MISC_COMMAND); 8389 val |= BCE_MISC_COMMAND_ENABLE_ALL; 8390 REG_WR(sc, BCE_MISC_COMMAND, val); 8391 } 8392 8393 8394 /****************************************************************************/ 8395 /* Prints out Ethernet frame information from an mbuf. */ 8396 /* */ 8397 /* Partially decode an Ethernet frame to look at some important headers. */ 8398 /* */ 8399 /* Returns: */ 8400 /* Nothing. */ 8401 /****************************************************************************/ 8402 static void 8403 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 8404 { 8405 struct ether_vlan_header *eh; 8406 u16 etype; 8407 int ehlen; 8408 struct ip *ip; 8409 struct tcphdr *th; 8410 struct udphdr *uh; 8411 struct arphdr *ah; 8412 8413 BCE_PRINTF( 8414 "-----------------------------" 8415 " Frame Decode " 8416 "-----------------------------\n"); 8417 8418 eh = mtod(m, struct ether_vlan_header *); 8419 8420 /* Handle VLAN encapsulation if present. */ 8421 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 8422 etype = ntohs(eh->evl_proto); 8423 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 8424 } else { 8425 etype = ntohs(eh->evl_encap_proto); 8426 ehlen = ETHER_HDR_LEN; 8427 } 8428 8429 /* ToDo: Add VLAN output. */ 8430 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 8431 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 8432 8433 switch (etype) { 8434 case ETHERTYPE_IP: 8435 ip = (struct ip *)(m->m_data + ehlen); 8436 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, len = %d bytes, " 8437 "protocol = 0x%02X, xsum = 0x%04X\n", 8438 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 8439 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 8440 8441 switch (ip->ip_p) { 8442 case IPPROTO_TCP: 8443 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 8444 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = %d bytes, " 8445 "flags = 0x%b, csum = 0x%04X\n", 8446 ntohs(th->th_dport), ntohs(th->th_sport), (th->th_off << 2), 8447 th->th_flags, "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST\02SYN\01FIN", 8448 ntohs(th->th_sum)); 8449 break; 8450 case IPPROTO_UDP: 8451 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 8452 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d bytes, " 8453 "csum = 0x%04X\n", ntohs(uh->uh_dport), ntohs(uh->uh_sport), 8454 ntohs(uh->uh_ulen), ntohs(uh->uh_sum)); 8455 break; 8456 case IPPROTO_ICMP: 8457 BCE_PRINTF("icmp:\n"); 8458 break; 8459 default: 8460 BCE_PRINTF("----: Other IP protocol.\n"); 8461 } 8462 break; 8463 case ETHERTYPE_IPV6: 8464 BCE_PRINTF("ipv6: No decode supported.\n"); 8465 break; 8466 case ETHERTYPE_ARP: 8467 BCE_PRINTF("-arp: "); 8468 ah = (struct arphdr *) (m->m_data + ehlen); 8469 switch (ntohs(ah->ar_op)) { 8470 case ARPOP_REVREQUEST: 8471 printf("reverse ARP request\n"); 8472 break; 8473 case ARPOP_REVREPLY: 8474 printf("reverse ARP reply\n"); 8475 break; 8476 case ARPOP_REQUEST: 8477 printf("ARP request\n"); 8478 break; 8479 case ARPOP_REPLY: 8480 printf("ARP reply\n"); 8481 break; 8482 default: 8483 printf("other ARP operation\n"); 8484 } 8485 break; 8486 default: 8487 BCE_PRINTF("----: Other protocol.\n"); 8488 } 8489 8490 BCE_PRINTF( 8491 "-----------------------------" 8492 "--------------" 8493 "-----------------------------\n"); 8494 } 8495 8496 8497 /****************************************************************************/ 8498 /* Prints out information about an mbuf. */ 8499 /* */ 8500 /* Returns: */ 8501 /* Nothing. */ 8502 /****************************************************************************/ 8503 static __attribute__ ((noinline)) void 8504 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 8505 { 8506 struct mbuf *mp = m; 8507 8508 if (m == NULL) { 8509 BCE_PRINTF("mbuf: null pointer\n"); 8510 return; 8511 } 8512 8513 while (mp) { 8514 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, m_data = %p\n", 8515 mp, mp->m_len, mp->m_flags, 8516 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", 8517 mp->m_data); 8518 8519 if (mp->m_flags & M_PKTHDR) { 8520 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, csum_flags = %b\n", 8521 mp->m_pkthdr.len, mp->m_flags, 8522 "\20\12M_BCAST\13M_MCAST\14M_FRAG\15M_FIRSTFRAG" 8523 "\16M_LASTFRAG\21M_VLANTAG\22M_PROMISC\23M_NOFREE", 8524 mp->m_pkthdr.csum_flags, 8525 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 8526 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 8527 "\12CSUM_IP_VALID\13CSUM_DATA_VALID\14CSUM_PSEUDO_HDR"); 8528 } 8529 8530 if (mp->m_flags & M_EXT) { 8531 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 8532 mp->m_ext.ext_buf, mp->m_ext.ext_size); 8533 switch (mp->m_ext.ext_type) { 8534 case EXT_CLUSTER: printf("EXT_CLUSTER\n"); break; 8535 case EXT_SFBUF: printf("EXT_SFBUF\n"); break; 8536 case EXT_JUMBO9: printf("EXT_JUMBO9\n"); break; 8537 case EXT_JUMBO16: printf("EXT_JUMBO16\n"); break; 8538 case EXT_PACKET: printf("EXT_PACKET\n"); break; 8539 case EXT_MBUF: printf("EXT_MBUF\n"); break; 8540 case EXT_NET_DRV: printf("EXT_NET_DRV\n"); break; 8541 case EXT_MOD_TYPE: printf("EXT_MDD_TYPE\n"); break; 8542 case EXT_DISPOSABLE: printf("EXT_DISPOSABLE\n"); break; 8543 case EXT_EXTREF: printf("EXT_EXTREF\n"); break; 8544 default: printf("UNKNOWN\n"); 8545 } 8546 } 8547 8548 mp = mp->m_next; 8549 } 8550 } 8551 8552 8553 /****************************************************************************/ 8554 /* Prints out the mbufs in the TX mbuf chain. */ 8555 /* */ 8556 /* Returns: */ 8557 /* Nothing. */ 8558 /****************************************************************************/ 8559 static __attribute__ ((noinline)) void 8560 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 8561 { 8562 struct mbuf *m; 8563 8564 BCE_PRINTF( 8565 "----------------------------" 8566 " tx mbuf data " 8567 "----------------------------\n"); 8568 8569 for (int i = 0; i < count; i++) { 8570 m = sc->tx_mbuf_ptr[chain_prod]; 8571 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 8572 bce_dump_mbuf(sc, m); 8573 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 8574 } 8575 8576 BCE_PRINTF( 8577 "----------------------------" 8578 "----------------" 8579 "----------------------------\n"); 8580 } 8581 8582 8583 /****************************************************************************/ 8584 /* Prints out the mbufs in the RX mbuf chain. */ 8585 /* */ 8586 /* Returns: */ 8587 /* Nothing. */ 8588 /****************************************************************************/ 8589 static __attribute__ ((noinline)) void 8590 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 8591 { 8592 struct mbuf *m; 8593 8594 BCE_PRINTF( 8595 "----------------------------" 8596 " rx mbuf data " 8597 "----------------------------\n"); 8598 8599 for (int i = 0; i < count; i++) { 8600 m = sc->rx_mbuf_ptr[chain_prod]; 8601 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 8602 bce_dump_mbuf(sc, m); 8603 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 8604 } 8605 8606 8607 BCE_PRINTF( 8608 "----------------------------" 8609 "----------------" 8610 "----------------------------\n"); 8611 } 8612 8613 8614 #ifdef ZERO_COPY_SOCKETS 8615 /****************************************************************************/ 8616 /* Prints out the mbufs in the mbuf page chain. */ 8617 /* */ 8618 /* Returns: */ 8619 /* Nothing. */ 8620 /****************************************************************************/ 8621 static __attribute__ ((noinline)) void 8622 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 8623 { 8624 struct mbuf *m; 8625 8626 BCE_PRINTF( 8627 "----------------------------" 8628 " pg mbuf data " 8629 "----------------------------\n"); 8630 8631 for (int i = 0; i < count; i++) { 8632 m = sc->pg_mbuf_ptr[chain_prod]; 8633 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 8634 bce_dump_mbuf(sc, m); 8635 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 8636 } 8637 8638 8639 BCE_PRINTF( 8640 "----------------------------" 8641 "----------------" 8642 "----------------------------\n"); 8643 } 8644 #endif 8645 8646 8647 /****************************************************************************/ 8648 /* Prints out a tx_bd structure. */ 8649 /* */ 8650 /* Returns: */ 8651 /* Nothing. */ 8652 /****************************************************************************/ 8653 static __attribute__ ((noinline)) void 8654 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 8655 { 8656 if (idx > MAX_TX_BD) 8657 /* Index out of range. */ 8658 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 8659 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 8660 /* TX Chain page pointer. */ 8661 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 8662 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo); 8663 else { 8664 /* Normal tx_bd entry. */ 8665 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 8666 "vlan tag= 0x%04X, flags = 0x%04X (", idx, 8667 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 8668 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 8669 txbd->tx_bd_flags); 8670 8671 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) 8672 printf(" CONN_FAULT"); 8673 8674 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) 8675 printf(" TCP_UDP_CKSUM"); 8676 8677 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) 8678 printf(" IP_CKSUM"); 8679 8680 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) 8681 printf(" VLAN"); 8682 8683 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) 8684 printf(" COAL_NOW"); 8685 8686 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) 8687 printf(" DONT_GEN_CRC"); 8688 8689 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) 8690 printf(" START"); 8691 8692 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) 8693 printf(" END"); 8694 8695 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) 8696 printf(" LSO"); 8697 8698 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) 8699 printf(" OPTION_WORD"); 8700 8701 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) 8702 printf(" FLAGS"); 8703 8704 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) 8705 printf(" SNAP"); 8706 8707 printf(" )\n"); 8708 } 8709 8710 } 8711 8712 8713 /****************************************************************************/ 8714 /* Prints out a rx_bd structure. */ 8715 /* */ 8716 /* Returns: */ 8717 /* Nothing. */ 8718 /****************************************************************************/ 8719 static __attribute__ ((noinline)) void 8720 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 8721 { 8722 if (idx > MAX_RX_BD) 8723 /* Index out of range. */ 8724 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 8725 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 8726 /* RX Chain page pointer. */ 8727 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 8728 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo); 8729 else 8730 /* Normal rx_bd entry. */ 8731 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 8732 "flags = 0x%08X\n", idx, 8733 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 8734 rxbd->rx_bd_len, rxbd->rx_bd_flags); 8735 } 8736 8737 8738 #ifdef ZERO_COPY_SOCKETS 8739 /****************************************************************************/ 8740 /* Prints out a rx_bd structure in the page chain. */ 8741 /* */ 8742 /* Returns: */ 8743 /* Nothing. */ 8744 /****************************************************************************/ 8745 static __attribute__ ((noinline)) void 8746 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 8747 { 8748 if (idx > MAX_PG_BD) 8749 /* Index out of range. */ 8750 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 8751 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 8752 /* Page Chain page pointer. */ 8753 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 8754 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 8755 else 8756 /* Normal rx_bd entry. */ 8757 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 8758 "flags = 0x%08X\n", idx, 8759 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 8760 pgbd->rx_bd_len, pgbd->rx_bd_flags); 8761 } 8762 #endif 8763 8764 8765 /****************************************************************************/ 8766 /* Prints out a l2_fhdr structure. */ 8767 /* */ 8768 /* Returns: */ 8769 /* Nothing. */ 8770 /****************************************************************************/ 8771 static __attribute__ ((noinline)) void 8772 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 8773 { 8774 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 8775 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 8776 "tcp_udp_xsum = 0x%04X\n", idx, 8777 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 8778 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 8779 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 8780 } 8781 8782 8783 /****************************************************************************/ 8784 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 8785 /* */ 8786 /* Returns: */ 8787 /* Nothing. */ 8788 /****************************************************************************/ 8789 static __attribute__ ((noinline)) void 8790 bce_dump_ctx(struct bce_softc *sc, u16 cid) 8791 { 8792 if (cid <= TX_CID) { 8793 BCE_PRINTF( 8794 "----------------------------" 8795 " CTX Data " 8796 "----------------------------\n"); 8797 8798 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 8799 8800 if (cid == RX_CID) { 8801 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 8802 "producer index\n", 8803 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 8804 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host byte sequence\n", 8805 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BSEQ)); 8806 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 8807 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 8808 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 8809 "descriptor address\n", 8810 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 8811 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 8812 "descriptor address\n", 8813 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 8814 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer index\n", 8815 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDIDX)); 8816 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 8817 "producer index\n", 8818 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_PG_BDIDX)); 8819 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 8820 "buffer size\n", 8821 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_PG_BUF_SIZE)); 8822 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 8823 "chain address\n", 8824 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 8825 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 8826 "chain address\n", 8827 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 8828 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 8829 "consumer index\n", 8830 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_PG_BDIDX)); 8831 } else if (cid == TX_CID) { 8832 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 8833 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 8834 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 8835 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE_XI)); 8836 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx cmd\n", 8837 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_CMD_TYPE_XI)); 8838 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) h/w buffer " 8839 "descriptor address\n", CTX_RD(sc, 8840 GET_CID_ADDR(cid), BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 8841 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) h/w buffer " 8842 "descriptor address\n", CTX_RD(sc, 8843 GET_CID_ADDR(cid), BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 8844 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) host producer " 8845 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 8846 BCE_L2CTX_TX_HOST_BIDX_XI)); 8847 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) host byte " 8848 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 8849 BCE_L2CTX_TX_HOST_BSEQ_XI)); 8850 } else { 8851 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 8852 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 8853 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 8854 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_CMD_TYPE)); 8855 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) h/w buffer " 8856 "descriptor address\n", CTX_RD(sc, GET_CID_ADDR(cid), 8857 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 8858 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) h/w buffer " 8859 "descriptor address\n", CTX_RD(sc, GET_CID_ADDR(cid), 8860 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 8861 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host producer " 8862 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 8863 BCE_L2CTX_TX_HOST_BIDX)); 8864 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 8865 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 8866 BCE_L2CTX_TX_HOST_BSEQ)); 8867 } 8868 } else 8869 BCE_PRINTF(" Unknown CID\n"); 8870 8871 BCE_PRINTF( 8872 "----------------------------" 8873 " Raw CTX " 8874 "----------------------------\n"); 8875 8876 for (int i = 0x0; i < 0x300; i += 0x10) { 8877 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 8878 CTX_RD(sc, GET_CID_ADDR(cid), i), 8879 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 8880 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 8881 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 8882 } 8883 8884 8885 BCE_PRINTF( 8886 "----------------------------" 8887 "----------------" 8888 "----------------------------\n"); 8889 } 8890 } 8891 8892 8893 /****************************************************************************/ 8894 /* Prints out the FTQ data. */ 8895 /* */ 8896 /* Returns: */ 8897 /* Nothing. */ 8898 /****************************************************************************/ 8899 static __attribute__ ((noinline)) void 8900 bce_dump_ftqs(struct bce_softc *sc) 8901 { 8902 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 8903 8904 BCE_PRINTF( 8905 "----------------------------" 8906 " FTQ Data " 8907 "----------------------------\n"); 8908 8909 BCE_PRINTF(" FTQ Command Control Depth_Now Max_Depth Valid_Cnt \n"); 8910 BCE_PRINTF(" ------- ---------- ---------- ---------- ---------- ----------\n"); 8911 8912 /* Setup the generic statistic counters for the FTQ valid count. */ 8913 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 8914 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 8915 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 8916 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 8917 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 8918 8919 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 8920 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 8921 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 8922 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 8923 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 8924 8925 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 8926 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 8927 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 8928 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 8929 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 8930 8931 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 8932 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 8933 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 8934 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 8935 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 8936 8937 /* Input queue to the Receive Lookup state machine */ 8938 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 8939 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 8940 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 8941 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 8942 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 8943 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8944 cmd, ctl, cur_depth, max_depth, valid_cnt); 8945 8946 /* Input queue to the Receive Processor */ 8947 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 8948 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 8949 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 8950 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 8951 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 8952 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8953 cmd, ctl, cur_depth, max_depth, valid_cnt); 8954 8955 /* Input queue to the Recevie Processor */ 8956 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 8957 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 8958 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 8959 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 8960 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 8961 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8962 cmd, ctl, cur_depth, max_depth, valid_cnt); 8963 8964 /* Input queue to the Receive Virtual to Physical state machine */ 8965 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 8966 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 8967 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 8968 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 8969 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 8970 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8971 cmd, ctl, cur_depth, max_depth, valid_cnt); 8972 8973 /* Input queue to the Recevie Virtual to Physical state machine */ 8974 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 8975 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 8976 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 8977 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 8978 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 8979 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8980 cmd, ctl, cur_depth, max_depth, valid_cnt); 8981 8982 /* Input queue to the Receive Virtual to Physical state machine */ 8983 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 8984 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 8985 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 8986 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 8987 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 8988 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8989 cmd, ctl, cur_depth, max_depth, valid_cnt); 8990 8991 /* Input queue to the Receive DMA state machine */ 8992 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 8993 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 8994 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 8995 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 8996 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 8997 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 8998 cmd, ctl, cur_depth, max_depth, valid_cnt); 8999 9000 /* Input queue to the Transmit Scheduler state machine */ 9001 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 9002 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 9003 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 9004 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 9005 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 9006 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9007 cmd, ctl, cur_depth, max_depth, valid_cnt); 9008 9009 /* Input queue to the Transmit Buffer Descriptor state machine */ 9010 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 9011 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 9012 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 9013 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 9014 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 9015 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9016 cmd, ctl, cur_depth, max_depth, valid_cnt); 9017 9018 /* Input queue to the Transmit Processor */ 9019 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 9020 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 9021 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 9022 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 9023 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 9024 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9025 cmd, ctl, cur_depth, max_depth, valid_cnt); 9026 9027 /* Input queue to the Transmit DMA state machine */ 9028 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 9029 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 9030 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 9031 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 9032 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 9033 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9034 cmd, ctl, cur_depth, max_depth, valid_cnt); 9035 9036 /* Input queue to the Transmit Patch-Up Processor */ 9037 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 9038 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 9039 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 9040 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 9041 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 9042 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9043 cmd, ctl, cur_depth, max_depth, valid_cnt); 9044 9045 /* Input queue to the Transmit Assembler state machine */ 9046 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 9047 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 9048 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 9049 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 9050 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 9051 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9052 cmd, ctl, cur_depth, max_depth, valid_cnt); 9053 9054 /* Input queue to the Completion Processor */ 9055 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 9056 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 9057 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 9058 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 9059 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 9060 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9061 cmd, ctl, cur_depth, max_depth, valid_cnt); 9062 9063 /* Input queue to the Completion Processor */ 9064 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 9065 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 9066 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 9067 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 9068 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 9069 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9070 cmd, ctl, cur_depth, max_depth, valid_cnt); 9071 9072 /* Input queue to the Completion Processor */ 9073 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 9074 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 9075 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 9076 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 9077 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 9078 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9079 cmd, ctl, cur_depth, max_depth, valid_cnt); 9080 9081 /* Setup the generic statistic counters for the FTQ valid count. */ 9082 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 9083 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 9084 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 9085 9086 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9087 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) 9088 val = val | (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 24); 9089 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9090 9091 /* Input queue to the Management Control Processor */ 9092 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 9093 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 9094 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9095 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9096 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 9097 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9098 cmd, ctl, cur_depth, max_depth, valid_cnt); 9099 9100 /* Input queue to the Command Processor */ 9101 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 9102 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 9103 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 9104 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 9105 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 9106 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9107 cmd, ctl, cur_depth, max_depth, valid_cnt); 9108 9109 /* Input queue to the Completion Scheduler state machine */ 9110 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 9111 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 9112 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 9113 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 9114 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 9115 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9116 cmd, ctl, cur_depth, max_depth, valid_cnt); 9117 9118 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) || 9119 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) { 9120 /* Input queue to the Receive Virtual to Physical Command Scheduler */ 9121 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 9122 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 9123 cur_depth = (ctl & 0xFFC00000) >> 22; 9124 max_depth = (ctl & 0x003FF000) >> 12; 9125 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 9126 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 9127 cmd, ctl, cur_depth, max_depth, valid_cnt); 9128 } 9129 9130 BCE_PRINTF( 9131 "----------------------------" 9132 "----------------" 9133 "----------------------------\n"); 9134 } 9135 9136 9137 /****************************************************************************/ 9138 /* Prints out the TX chain. */ 9139 /* */ 9140 /* Returns: */ 9141 /* Nothing. */ 9142 /****************************************************************************/ 9143 static __attribute__ ((noinline)) void 9144 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 9145 { 9146 struct tx_bd *txbd; 9147 9148 /* First some info about the tx_bd chain structure. */ 9149 BCE_PRINTF( 9150 "----------------------------" 9151 " tx_bd chain " 9152 "----------------------------\n"); 9153 9154 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 9155 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 9156 9157 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 9158 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 9159 9160 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 9161 9162 BCE_PRINTF( 9163 "----------------------------" 9164 " tx_bd data " 9165 "----------------------------\n"); 9166 9167 /* Now print out the tx_bd's themselves. */ 9168 for (int i = 0; i < count; i++) { 9169 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 9170 bce_dump_txbd(sc, tx_prod, txbd); 9171 tx_prod = NEXT_TX_BD(tx_prod); 9172 } 9173 9174 BCE_PRINTF( 9175 "----------------------------" 9176 "----------------" 9177 "----------------------------\n"); 9178 } 9179 9180 9181 /****************************************************************************/ 9182 /* Prints out the RX chain. */ 9183 /* */ 9184 /* Returns: */ 9185 /* Nothing. */ 9186 /****************************************************************************/ 9187 static __attribute__ ((noinline)) void 9188 bce_dump_rx_chain(struct bce_softc *sc, u16 rx_prod, int count) 9189 { 9190 struct rx_bd *rxbd; 9191 9192 /* First some info about the rx_bd chain structure. */ 9193 BCE_PRINTF( 9194 "----------------------------" 9195 " rx_bd chain " 9196 "----------------------------\n"); 9197 9198 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 9199 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 9200 9201 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9202 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 9203 9204 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 9205 9206 BCE_PRINTF( 9207 "----------------------------" 9208 " rx_bd data " 9209 "----------------------------\n"); 9210 9211 /* Now print out the rx_bd's themselves. */ 9212 for (int i = 0; i < count; i++) { 9213 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 9214 bce_dump_rxbd(sc, rx_prod, rxbd); 9215 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 9216 } 9217 9218 BCE_PRINTF( 9219 "----------------------------" 9220 "----------------" 9221 "----------------------------\n"); 9222 } 9223 9224 9225 #ifdef ZERO_COPY_SOCKETS 9226 /****************************************************************************/ 9227 /* Prints out the page chain. */ 9228 /* */ 9229 /* Returns: */ 9230 /* Nothing. */ 9231 /****************************************************************************/ 9232 static __attribute__ ((noinline)) void 9233 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 9234 { 9235 struct rx_bd *pgbd; 9236 9237 /* First some info about the page chain structure. */ 9238 BCE_PRINTF( 9239 "----------------------------" 9240 " page chain " 9241 "----------------------------\n"); 9242 9243 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 9244 (u32) BCM_PAGE_SIZE, (u32) PG_PAGES); 9245 9246 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 9247 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 9248 9249 BCE_PRINTF("total rx_bd = 0x%08X, max_pg_bd = 0x%08X\n", 9250 (u32) TOTAL_PG_BD, (u32) MAX_PG_BD); 9251 9252 BCE_PRINTF( 9253 "----------------------------" 9254 " page data " 9255 "----------------------------\n"); 9256 9257 /* Now print out the rx_bd's themselves. */ 9258 for (int i = 0; i < count; i++) { 9259 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 9260 bce_dump_pgbd(sc, pg_prod, pgbd); 9261 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 9262 } 9263 9264 BCE_PRINTF( 9265 "----------------------------" 9266 "----------------" 9267 "----------------------------\n"); 9268 } 9269 #endif 9270 9271 9272 /****************************************************************************/ 9273 /* Prints out the status block from host memory. */ 9274 /* */ 9275 /* Returns: */ 9276 /* Nothing. */ 9277 /****************************************************************************/ 9278 static __attribute__ ((noinline)) void 9279 bce_dump_status_block(struct bce_softc *sc) 9280 { 9281 struct status_block *sblk; 9282 9283 sblk = sc->status_block; 9284 9285 BCE_PRINTF( 9286 "----------------------------" 9287 " Status Block " 9288 "----------------------------\n"); 9289 9290 BCE_PRINTF(" 0x%08X - attn_bits\n", 9291 sblk->status_attn_bits); 9292 9293 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 9294 sblk->status_attn_bits_ack); 9295 9296 BCE_PRINTF("0x%04X(0x%04X) - rx_cons0\n", 9297 sblk->status_rx_quick_consumer_index0, 9298 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0)); 9299 9300 BCE_PRINTF("0x%04X(0x%04X) - tx_cons0\n", 9301 sblk->status_tx_quick_consumer_index0, 9302 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0)); 9303 9304 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 9305 9306 /* Theses indices are not used for normal L2 drivers. */ 9307 if (sblk->status_rx_quick_consumer_index1) 9308 BCE_PRINTF("0x%04X(0x%04X) - rx_cons1\n", 9309 sblk->status_rx_quick_consumer_index1, 9310 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1)); 9311 9312 if (sblk->status_tx_quick_consumer_index1) 9313 BCE_PRINTF("0x%04X(0x%04X) - tx_cons1\n", 9314 sblk->status_tx_quick_consumer_index1, 9315 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1)); 9316 9317 if (sblk->status_rx_quick_consumer_index2) 9318 BCE_PRINTF("0x%04X(0x%04X)- rx_cons2\n", 9319 sblk->status_rx_quick_consumer_index2, 9320 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2)); 9321 9322 if (sblk->status_tx_quick_consumer_index2) 9323 BCE_PRINTF("0x%04X(0x%04X) - tx_cons2\n", 9324 sblk->status_tx_quick_consumer_index2, 9325 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2)); 9326 9327 if (sblk->status_rx_quick_consumer_index3) 9328 BCE_PRINTF("0x%04X(0x%04X) - rx_cons3\n", 9329 sblk->status_rx_quick_consumer_index3, 9330 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3)); 9331 9332 if (sblk->status_tx_quick_consumer_index3) 9333 BCE_PRINTF("0x%04X(0x%04X) - tx_cons3\n", 9334 sblk->status_tx_quick_consumer_index3, 9335 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3)); 9336 9337 if (sblk->status_rx_quick_consumer_index4 || 9338 sblk->status_rx_quick_consumer_index5) 9339 BCE_PRINTF("rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 9340 sblk->status_rx_quick_consumer_index4, 9341 sblk->status_rx_quick_consumer_index5); 9342 9343 if (sblk->status_rx_quick_consumer_index6 || 9344 sblk->status_rx_quick_consumer_index7) 9345 BCE_PRINTF("rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 9346 sblk->status_rx_quick_consumer_index6, 9347 sblk->status_rx_quick_consumer_index7); 9348 9349 if (sblk->status_rx_quick_consumer_index8 || 9350 sblk->status_rx_quick_consumer_index9) 9351 BCE_PRINTF("rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 9352 sblk->status_rx_quick_consumer_index8, 9353 sblk->status_rx_quick_consumer_index9); 9354 9355 if (sblk->status_rx_quick_consumer_index10 || 9356 sblk->status_rx_quick_consumer_index11) 9357 BCE_PRINTF("rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 9358 sblk->status_rx_quick_consumer_index10, 9359 sblk->status_rx_quick_consumer_index11); 9360 9361 if (sblk->status_rx_quick_consumer_index12 || 9362 sblk->status_rx_quick_consumer_index13) 9363 BCE_PRINTF("rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 9364 sblk->status_rx_quick_consumer_index12, 9365 sblk->status_rx_quick_consumer_index13); 9366 9367 if (sblk->status_rx_quick_consumer_index14 || 9368 sblk->status_rx_quick_consumer_index15) 9369 BCE_PRINTF("rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 9370 sblk->status_rx_quick_consumer_index14, 9371 sblk->status_rx_quick_consumer_index15); 9372 9373 if (sblk->status_completion_producer_index || 9374 sblk->status_cmd_consumer_index) 9375 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 9376 sblk->status_completion_producer_index, 9377 sblk->status_cmd_consumer_index); 9378 9379 BCE_PRINTF( 9380 "----------------------------" 9381 "----------------" 9382 "----------------------------\n"); 9383 } 9384 9385 9386 /****************************************************************************/ 9387 /* Prints out the statistics block from host memory. */ 9388 /* */ 9389 /* Returns: */ 9390 /* Nothing. */ 9391 /****************************************************************************/ 9392 static __attribute__ ((noinline)) void 9393 bce_dump_stats_block(struct bce_softc *sc) 9394 { 9395 struct statistics_block *sblk; 9396 9397 sblk = sc->stats_block; 9398 9399 BCE_PRINTF( 9400 "---------------" 9401 " Stats Block (All Stats Not Shown Are 0) " 9402 "---------------\n"); 9403 9404 if (sblk->stat_IfHCInOctets_hi 9405 || sblk->stat_IfHCInOctets_lo) 9406 BCE_PRINTF("0x%08X:%08X : " 9407 "IfHcInOctets\n", 9408 sblk->stat_IfHCInOctets_hi, 9409 sblk->stat_IfHCInOctets_lo); 9410 9411 if (sblk->stat_IfHCInBadOctets_hi 9412 || sblk->stat_IfHCInBadOctets_lo) 9413 BCE_PRINTF("0x%08X:%08X : " 9414 "IfHcInBadOctets\n", 9415 sblk->stat_IfHCInBadOctets_hi, 9416 sblk->stat_IfHCInBadOctets_lo); 9417 9418 if (sblk->stat_IfHCOutOctets_hi 9419 || sblk->stat_IfHCOutOctets_lo) 9420 BCE_PRINTF("0x%08X:%08X : " 9421 "IfHcOutOctets\n", 9422 sblk->stat_IfHCOutOctets_hi, 9423 sblk->stat_IfHCOutOctets_lo); 9424 9425 if (sblk->stat_IfHCOutBadOctets_hi 9426 || sblk->stat_IfHCOutBadOctets_lo) 9427 BCE_PRINTF("0x%08X:%08X : " 9428 "IfHcOutBadOctets\n", 9429 sblk->stat_IfHCOutBadOctets_hi, 9430 sblk->stat_IfHCOutBadOctets_lo); 9431 9432 if (sblk->stat_IfHCInUcastPkts_hi 9433 || sblk->stat_IfHCInUcastPkts_lo) 9434 BCE_PRINTF("0x%08X:%08X : " 9435 "IfHcInUcastPkts\n", 9436 sblk->stat_IfHCInUcastPkts_hi, 9437 sblk->stat_IfHCInUcastPkts_lo); 9438 9439 if (sblk->stat_IfHCInBroadcastPkts_hi 9440 || sblk->stat_IfHCInBroadcastPkts_lo) 9441 BCE_PRINTF("0x%08X:%08X : " 9442 "IfHcInBroadcastPkts\n", 9443 sblk->stat_IfHCInBroadcastPkts_hi, 9444 sblk->stat_IfHCInBroadcastPkts_lo); 9445 9446 if (sblk->stat_IfHCInMulticastPkts_hi 9447 || sblk->stat_IfHCInMulticastPkts_lo) 9448 BCE_PRINTF("0x%08X:%08X : " 9449 "IfHcInMulticastPkts\n", 9450 sblk->stat_IfHCInMulticastPkts_hi, 9451 sblk->stat_IfHCInMulticastPkts_lo); 9452 9453 if (sblk->stat_IfHCOutUcastPkts_hi 9454 || sblk->stat_IfHCOutUcastPkts_lo) 9455 BCE_PRINTF("0x%08X:%08X : " 9456 "IfHcOutUcastPkts\n", 9457 sblk->stat_IfHCOutUcastPkts_hi, 9458 sblk->stat_IfHCOutUcastPkts_lo); 9459 9460 if (sblk->stat_IfHCOutBroadcastPkts_hi 9461 || sblk->stat_IfHCOutBroadcastPkts_lo) 9462 BCE_PRINTF("0x%08X:%08X : " 9463 "IfHcOutBroadcastPkts\n", 9464 sblk->stat_IfHCOutBroadcastPkts_hi, 9465 sblk->stat_IfHCOutBroadcastPkts_lo); 9466 9467 if (sblk->stat_IfHCOutMulticastPkts_hi 9468 || sblk->stat_IfHCOutMulticastPkts_lo) 9469 BCE_PRINTF("0x%08X:%08X : " 9470 "IfHcOutMulticastPkts\n", 9471 sblk->stat_IfHCOutMulticastPkts_hi, 9472 sblk->stat_IfHCOutMulticastPkts_lo); 9473 9474 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 9475 BCE_PRINTF(" 0x%08X : " 9476 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 9477 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 9478 9479 if (sblk->stat_Dot3StatsCarrierSenseErrors) 9480 BCE_PRINTF(" 0x%08X : Dot3StatsCarrierSenseErrors\n", 9481 sblk->stat_Dot3StatsCarrierSenseErrors); 9482 9483 if (sblk->stat_Dot3StatsFCSErrors) 9484 BCE_PRINTF(" 0x%08X : Dot3StatsFCSErrors\n", 9485 sblk->stat_Dot3StatsFCSErrors); 9486 9487 if (sblk->stat_Dot3StatsAlignmentErrors) 9488 BCE_PRINTF(" 0x%08X : Dot3StatsAlignmentErrors\n", 9489 sblk->stat_Dot3StatsAlignmentErrors); 9490 9491 if (sblk->stat_Dot3StatsSingleCollisionFrames) 9492 BCE_PRINTF(" 0x%08X : Dot3StatsSingleCollisionFrames\n", 9493 sblk->stat_Dot3StatsSingleCollisionFrames); 9494 9495 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 9496 BCE_PRINTF(" 0x%08X : Dot3StatsMultipleCollisionFrames\n", 9497 sblk->stat_Dot3StatsMultipleCollisionFrames); 9498 9499 if (sblk->stat_Dot3StatsDeferredTransmissions) 9500 BCE_PRINTF(" 0x%08X : Dot3StatsDeferredTransmissions\n", 9501 sblk->stat_Dot3StatsDeferredTransmissions); 9502 9503 if (sblk->stat_Dot3StatsExcessiveCollisions) 9504 BCE_PRINTF(" 0x%08X : Dot3StatsExcessiveCollisions\n", 9505 sblk->stat_Dot3StatsExcessiveCollisions); 9506 9507 if (sblk->stat_Dot3StatsLateCollisions) 9508 BCE_PRINTF(" 0x%08X : Dot3StatsLateCollisions\n", 9509 sblk->stat_Dot3StatsLateCollisions); 9510 9511 if (sblk->stat_EtherStatsCollisions) 9512 BCE_PRINTF(" 0x%08X : EtherStatsCollisions\n", 9513 sblk->stat_EtherStatsCollisions); 9514 9515 if (sblk->stat_EtherStatsFragments) 9516 BCE_PRINTF(" 0x%08X : EtherStatsFragments\n", 9517 sblk->stat_EtherStatsFragments); 9518 9519 if (sblk->stat_EtherStatsJabbers) 9520 BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n", 9521 sblk->stat_EtherStatsJabbers); 9522 9523 if (sblk->stat_EtherStatsUndersizePkts) 9524 BCE_PRINTF(" 0x%08X : EtherStatsUndersizePkts\n", 9525 sblk->stat_EtherStatsUndersizePkts); 9526 9527 if (sblk->stat_EtherStatsOversizePkts) 9528 BCE_PRINTF(" 0x%08X : EtherStatsOverrsizePkts\n", 9529 sblk->stat_EtherStatsOversizePkts); 9530 9531 if (sblk->stat_EtherStatsPktsRx64Octets) 9532 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx64Octets\n", 9533 sblk->stat_EtherStatsPktsRx64Octets); 9534 9535 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 9536 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 9537 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 9538 9539 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 9540 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx128Octetsto255Octets\n", 9541 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 9542 9543 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 9544 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx256Octetsto511Octets\n", 9545 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 9546 9547 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 9548 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx512Octetsto1023Octets\n", 9549 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 9550 9551 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 9552 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1024Octetsto1522Octets\n", 9553 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 9554 9555 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 9556 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1523Octetsto9022Octets\n", 9557 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 9558 9559 if (sblk->stat_EtherStatsPktsTx64Octets) 9560 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx64Octets\n", 9561 sblk->stat_EtherStatsPktsTx64Octets); 9562 9563 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 9564 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 9565 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 9566 9567 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 9568 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx128Octetsto255Octets\n", 9569 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 9570 9571 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 9572 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx256Octetsto511Octets\n", 9573 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 9574 9575 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 9576 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx512Octetsto1023Octets\n", 9577 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 9578 9579 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 9580 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1024Octetsto1522Octets\n", 9581 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 9582 9583 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 9584 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1523Octetsto9022Octets\n", 9585 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 9586 9587 if (sblk->stat_XonPauseFramesReceived) 9588 BCE_PRINTF(" 0x%08X : XonPauseFramesReceived\n", 9589 sblk->stat_XonPauseFramesReceived); 9590 9591 if (sblk->stat_XoffPauseFramesReceived) 9592 BCE_PRINTF(" 0x%08X : XoffPauseFramesReceived\n", 9593 sblk->stat_XoffPauseFramesReceived); 9594 9595 if (sblk->stat_OutXonSent) 9596 BCE_PRINTF(" 0x%08X : OutXonSent\n", 9597 sblk->stat_OutXonSent); 9598 9599 if (sblk->stat_OutXoffSent) 9600 BCE_PRINTF(" 0x%08X : OutXoffSent\n", 9601 sblk->stat_OutXoffSent); 9602 9603 if (sblk->stat_FlowControlDone) 9604 BCE_PRINTF(" 0x%08X : FlowControlDone\n", 9605 sblk->stat_FlowControlDone); 9606 9607 if (sblk->stat_MacControlFramesReceived) 9608 BCE_PRINTF(" 0x%08X : MacControlFramesReceived\n", 9609 sblk->stat_MacControlFramesReceived); 9610 9611 if (sblk->stat_XoffStateEntered) 9612 BCE_PRINTF(" 0x%08X : XoffStateEntered\n", 9613 sblk->stat_XoffStateEntered); 9614 9615 if (sblk->stat_IfInFramesL2FilterDiscards) 9616 BCE_PRINTF(" 0x%08X : IfInFramesL2FilterDiscards\n", 9617 sblk->stat_IfInFramesL2FilterDiscards); 9618 9619 if (sblk->stat_IfInRuleCheckerDiscards) 9620 BCE_PRINTF(" 0x%08X : IfInRuleCheckerDiscards\n", 9621 sblk->stat_IfInRuleCheckerDiscards); 9622 9623 if (sblk->stat_IfInFTQDiscards) 9624 BCE_PRINTF(" 0x%08X : IfInFTQDiscards\n", 9625 sblk->stat_IfInFTQDiscards); 9626 9627 if (sblk->stat_IfInMBUFDiscards) 9628 BCE_PRINTF(" 0x%08X : IfInMBUFDiscards\n", 9629 sblk->stat_IfInMBUFDiscards); 9630 9631 if (sblk->stat_IfInRuleCheckerP4Hit) 9632 BCE_PRINTF(" 0x%08X : IfInRuleCheckerP4Hit\n", 9633 sblk->stat_IfInRuleCheckerP4Hit); 9634 9635 if (sblk->stat_CatchupInRuleCheckerDiscards) 9636 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerDiscards\n", 9637 sblk->stat_CatchupInRuleCheckerDiscards); 9638 9639 if (sblk->stat_CatchupInFTQDiscards) 9640 BCE_PRINTF(" 0x%08X : CatchupInFTQDiscards\n", 9641 sblk->stat_CatchupInFTQDiscards); 9642 9643 if (sblk->stat_CatchupInMBUFDiscards) 9644 BCE_PRINTF(" 0x%08X : CatchupInMBUFDiscards\n", 9645 sblk->stat_CatchupInMBUFDiscards); 9646 9647 if (sblk->stat_CatchupInRuleCheckerP4Hit) 9648 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerP4Hit\n", 9649 sblk->stat_CatchupInRuleCheckerP4Hit); 9650 9651 BCE_PRINTF( 9652 "----------------------------" 9653 "----------------" 9654 "----------------------------\n"); 9655 } 9656 9657 9658 /****************************************************************************/ 9659 /* Prints out a summary of the driver state. */ 9660 /* */ 9661 /* Returns: */ 9662 /* Nothing. */ 9663 /****************************************************************************/ 9664 static __attribute__ ((noinline)) void 9665 bce_dump_driver_state(struct bce_softc *sc) 9666 { 9667 u32 val_hi, val_lo; 9668 9669 BCE_PRINTF( 9670 "-----------------------------" 9671 " Driver State " 9672 "-----------------------------\n"); 9673 9674 val_hi = BCE_ADDR_HI(sc); 9675 val_lo = BCE_ADDR_LO(sc); 9676 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual address\n", 9677 val_hi, val_lo); 9678 9679 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 9680 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 9681 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual address\n", 9682 val_hi, val_lo); 9683 9684 val_hi = BCE_ADDR_HI(sc->status_block); 9685 val_lo = BCE_ADDR_LO(sc->status_block); 9686 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block virtual address\n", 9687 val_hi, val_lo); 9688 9689 val_hi = BCE_ADDR_HI(sc->stats_block); 9690 val_lo = BCE_ADDR_LO(sc->stats_block); 9691 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block virtual address\n", 9692 val_hi, val_lo); 9693 9694 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 9695 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 9696 BCE_PRINTF( 9697 "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain virtual adddress\n", 9698 val_hi, val_lo); 9699 9700 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 9701 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 9702 BCE_PRINTF( 9703 "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain virtual address\n", 9704 val_hi, val_lo); 9705 9706 #ifdef ZERO_COPY_SOCKETS 9707 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 9708 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 9709 BCE_PRINTF( 9710 "0x%08X:%08X - (sc->pg_bd_chain) page chain virtual address\n", 9711 val_hi, val_lo); 9712 #endif 9713 9714 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 9715 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 9716 BCE_PRINTF( 9717 "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 9718 val_hi, val_lo); 9719 9720 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 9721 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 9722 BCE_PRINTF( 9723 "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 9724 val_hi, val_lo); 9725 9726 #ifdef ZERO_COPY_SOCKETS 9727 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 9728 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 9729 BCE_PRINTF( 9730 "0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain virtual address\n", 9731 val_hi, val_lo); 9732 #endif 9733 9734 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) h/w intrs\n", 9735 sc->interrupts_generated); 9736 9737 BCE_PRINTF(" 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 9738 sc->rx_interrupts); 9739 9740 BCE_PRINTF(" 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 9741 sc->tx_interrupts); 9742 9743 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) status block index\n", 9744 sc->last_status_idx); 9745 9746 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer index\n", 9747 sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 9748 9749 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer index\n", 9750 sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 9751 9752 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 9753 sc->tx_prod_bseq); 9754 9755 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx mbufs allocated\n", 9756 sc->debug_tx_mbuf_alloc); 9757 9758 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 9759 sc->used_tx_bd); 9760 9761 BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 9762 sc->tx_hi_watermark, sc->max_tx_bd); 9763 9764 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer index\n", 9765 sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 9766 9767 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer index\n", 9768 sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 9769 9770 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 9771 sc->rx_prod_bseq); 9772 9773 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx mbufs allocated\n", 9774 sc->debug_rx_mbuf_alloc); 9775 9776 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 9777 sc->free_rx_bd); 9778 9779 #ifdef ZERO_COPY_SOCKETS 9780 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer index\n", 9781 sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 9782 9783 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer index\n", 9784 sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 9785 9786 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page mbufs allocated\n", 9787 sc->debug_pg_mbuf_alloc); 9788 9789 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page rx_bd's\n", 9790 sc->free_pg_bd); 9791 9792 BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low watermark\n", 9793 sc->pg_low_watermark, sc->max_pg_bd); 9794 #endif 9795 9796 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 9797 "mbuf alloc failures\n", 9798 sc->mbuf_alloc_failed_count); 9799 9800 BCE_PRINTF(" 0x%08X - (sc->bce_flags) bce mac flags\n", 9801 sc->bce_flags); 9802 9803 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) bce phy flags\n", 9804 sc->bce_phy_flags); 9805 9806 BCE_PRINTF( 9807 "----------------------------" 9808 "----------------" 9809 "----------------------------\n"); 9810 } 9811 9812 9813 /****************************************************************************/ 9814 /* Prints out the hardware state through a summary of important register, */ 9815 /* followed by a complete register dump. */ 9816 /* */ 9817 /* Returns: */ 9818 /* Nothing. */ 9819 /****************************************************************************/ 9820 static __attribute__ ((noinline)) void 9821 bce_dump_hw_state(struct bce_softc *sc) 9822 { 9823 u32 val; 9824 9825 BCE_PRINTF( 9826 "----------------------------" 9827 " Hardware State " 9828 "----------------------------\n"); 9829 9830 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_bc_ver); 9831 9832 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 9833 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 9834 val, BCE_MISC_ENABLE_STATUS_BITS); 9835 9836 val = REG_RD(sc, BCE_DMA_STATUS); 9837 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", val, BCE_DMA_STATUS); 9838 9839 val = REG_RD(sc, BCE_CTX_STATUS); 9840 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", val, BCE_CTX_STATUS); 9841 9842 val = REG_RD(sc, BCE_EMAC_STATUS); 9843 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", val, BCE_EMAC_STATUS); 9844 9845 val = REG_RD(sc, BCE_RPM_STATUS); 9846 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", val, BCE_RPM_STATUS); 9847 9848 val = REG_RD(sc, 0x2004); 9849 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", val, 0x2004); 9850 9851 val = REG_RD(sc, BCE_RV2P_STATUS); 9852 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", val, BCE_RV2P_STATUS); 9853 9854 val = REG_RD(sc, 0x2c04); 9855 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", val, 0x2c04); 9856 9857 val = REG_RD(sc, BCE_TBDR_STATUS); 9858 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", val, BCE_TBDR_STATUS); 9859 9860 val = REG_RD(sc, BCE_TDMA_STATUS); 9861 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", val, BCE_TDMA_STATUS); 9862 9863 val = REG_RD(sc, BCE_HC_STATUS); 9864 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", val, BCE_HC_STATUS); 9865 9866 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 9867 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val, BCE_TXP_CPU_STATE); 9868 9869 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 9870 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val, BCE_TPAT_CPU_STATE); 9871 9872 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 9873 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val, BCE_RXP_CPU_STATE); 9874 9875 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 9876 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE); 9877 9878 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 9879 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", val, BCE_MCP_CPU_STATE); 9880 9881 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 9882 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE); 9883 9884 BCE_PRINTF( 9885 "----------------------------" 9886 "----------------" 9887 "----------------------------\n"); 9888 9889 BCE_PRINTF( 9890 "----------------------------" 9891 " Register Dump " 9892 "----------------------------\n"); 9893 9894 for (int i = 0x400; i < 0x8000; i += 0x10) { 9895 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 9896 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 9897 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 9898 } 9899 9900 BCE_PRINTF( 9901 "----------------------------" 9902 "----------------" 9903 "----------------------------\n"); 9904 } 9905 9906 9907 /****************************************************************************/ 9908 /* Prints out the mailbox queue registers. */ 9909 /* */ 9910 /* Returns: */ 9911 /* Nothing. */ 9912 /****************************************************************************/ 9913 static __attribute__ ((noinline)) void 9914 bce_dump_mq_regs(struct bce_softc *sc) 9915 { 9916 BCE_PRINTF( 9917 "----------------------------" 9918 " MQ Regs " 9919 "----------------------------\n"); 9920 9921 BCE_PRINTF( 9922 "----------------------------" 9923 "----------------" 9924 "----------------------------\n"); 9925 9926 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 9927 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 9928 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 9929 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 9930 } 9931 9932 BCE_PRINTF( 9933 "----------------------------" 9934 "----------------" 9935 "----------------------------\n"); 9936 } 9937 9938 9939 /****************************************************************************/ 9940 /* Prints out the bootcode state. */ 9941 /* */ 9942 /* Returns: */ 9943 /* Nothing. */ 9944 /****************************************************************************/ 9945 static __attribute__ ((noinline)) void 9946 bce_dump_bc_state(struct bce_softc *sc) 9947 { 9948 u32 val; 9949 9950 BCE_PRINTF( 9951 "----------------------------" 9952 " Bootcode State " 9953 "----------------------------\n"); 9954 9955 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_bc_ver); 9956 9957 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_RESET_TYPE); 9958 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 9959 val, BCE_BC_RESET_TYPE); 9960 9961 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE); 9962 BCE_PRINTF("0x%08X - (0x%06X) state\n", 9963 val, BCE_BC_STATE); 9964 9965 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_CONDITION); 9966 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 9967 val, BCE_BC_CONDITION); 9968 9969 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE_DEBUG_CMD); 9970 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 9971 val, BCE_BC_STATE_DEBUG_CMD); 9972 9973 BCE_PRINTF( 9974 "----------------------------" 9975 "----------------" 9976 "----------------------------\n"); 9977 } 9978 9979 9980 /****************************************************************************/ 9981 /* Prints out the TXP processor state. */ 9982 /* */ 9983 /* Returns: */ 9984 /* Nothing. */ 9985 /****************************************************************************/ 9986 static __attribute__ ((noinline)) void 9987 bce_dump_txp_state(struct bce_softc *sc, int regs) 9988 { 9989 u32 val; 9990 u32 fw_version[3]; 9991 9992 BCE_PRINTF( 9993 "----------------------------" 9994 " TXP State " 9995 "----------------------------\n"); 9996 9997 for (int i = 0; i < 3; i++) 9998 fw_version[i] = htonl(REG_RD_IND(sc, 9999 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10000 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10001 10002 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10003 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", val, BCE_TXP_CPU_MODE); 10004 10005 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10006 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val, BCE_TXP_CPU_STATE); 10007 10008 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10009 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", val, 10010 BCE_TXP_CPU_EVENT_MASK); 10011 10012 if (regs) { 10013 BCE_PRINTF( 10014 "----------------------------" 10015 " Register Dump " 10016 "----------------------------\n"); 10017 10018 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10019 /* Skip the big blank spaces */ 10020 if (i < 0x454000 && i > 0x5ffff) 10021 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10022 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10023 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10024 } 10025 } 10026 10027 BCE_PRINTF( 10028 "----------------------------" 10029 "----------------" 10030 "----------------------------\n"); 10031 } 10032 10033 10034 /****************************************************************************/ 10035 /* Prints out the RXP processor state. */ 10036 /* */ 10037 /* Returns: */ 10038 /* Nothing. */ 10039 /****************************************************************************/ 10040 static __attribute__ ((noinline)) void 10041 bce_dump_rxp_state(struct bce_softc *sc, int regs) 10042 { 10043 u32 val; 10044 u32 fw_version[3]; 10045 10046 BCE_PRINTF( 10047 "----------------------------" 10048 " RXP State " 10049 "----------------------------\n"); 10050 10051 for (int i = 0; i < 3; i++) 10052 fw_version[i] = htonl(REG_RD_IND(sc, 10053 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10054 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10055 10056 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10057 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", val, BCE_RXP_CPU_MODE); 10058 10059 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10060 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val, BCE_RXP_CPU_STATE); 10061 10062 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10063 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", val, 10064 BCE_RXP_CPU_EVENT_MASK); 10065 10066 if (regs) { 10067 BCE_PRINTF( 10068 "----------------------------" 10069 " Register Dump " 10070 "----------------------------\n"); 10071 10072 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 10073 /* Skip the big blank sapces */ 10074 if (i < 0xc5400 && i > 0xdffff) 10075 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10076 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10077 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10078 } 10079 } 10080 10081 BCE_PRINTF( 10082 "----------------------------" 10083 "----------------" 10084 "----------------------------\n"); 10085 } 10086 10087 10088 /****************************************************************************/ 10089 /* Prints out the TPAT processor state. */ 10090 /* */ 10091 /* Returns: */ 10092 /* Nothing. */ 10093 /****************************************************************************/ 10094 static __attribute__ ((noinline)) void 10095 bce_dump_tpat_state(struct bce_softc *sc, int regs) 10096 { 10097 u32 val; 10098 u32 fw_version[3]; 10099 10100 BCE_PRINTF( 10101 "----------------------------" 10102 " TPAT State " 10103 "----------------------------\n"); 10104 10105 for (int i = 0; i < 3; i++) 10106 fw_version[i] = htonl(REG_RD_IND(sc, 10107 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 10108 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10109 10110 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 10111 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", val, BCE_TPAT_CPU_MODE); 10112 10113 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10114 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val, BCE_TPAT_CPU_STATE); 10115 10116 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 10117 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", val, 10118 BCE_TPAT_CPU_EVENT_MASK); 10119 10120 if (regs) { 10121 BCE_PRINTF( 10122 "----------------------------" 10123 " Register Dump " 10124 "----------------------------\n"); 10125 10126 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 10127 /* Skip the big blank spaces */ 10128 if (i < 0x854000 && i > 0x9ffff) 10129 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10130 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10131 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10132 } 10133 } 10134 10135 BCE_PRINTF( 10136 "----------------------------" 10137 "----------------" 10138 "----------------------------\n"); 10139 } 10140 10141 10142 /****************************************************************************/ 10143 /* Prints out the Command Procesor (CP) state. */ 10144 /* */ 10145 /* Returns: */ 10146 /* Nothing. */ 10147 /****************************************************************************/ 10148 static __attribute__ ((noinline)) void 10149 bce_dump_cp_state(struct bce_softc *sc, int regs) 10150 { 10151 u32 val; 10152 u32 fw_version[3]; 10153 10154 BCE_PRINTF( 10155 "----------------------------" 10156 " CP State " 10157 "----------------------------\n"); 10158 10159 for (int i = 0; i < 3; i++) 10160 fw_version[i] = htonl(REG_RD_IND(sc, 10161 (BCE_CP_SCRATCH + 0x10 + i * 4))); 10162 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10163 10164 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 10165 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", val, BCE_CP_CPU_MODE); 10166 10167 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10168 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE); 10169 10170 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 10171 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 10172 BCE_CP_CPU_EVENT_MASK); 10173 10174 if (regs) { 10175 BCE_PRINTF( 10176 "----------------------------" 10177 " Register Dump " 10178 "----------------------------\n"); 10179 10180 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 10181 /* Skip the big blank spaces */ 10182 if (i < 0x185400 && i > 0x19ffff) 10183 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10184 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10185 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10186 } 10187 } 10188 10189 BCE_PRINTF( 10190 "----------------------------" 10191 "----------------" 10192 "----------------------------\n"); 10193 } 10194 10195 10196 /****************************************************************************/ 10197 /* Prints out the Completion Procesor (COM) state. */ 10198 /* */ 10199 /* Returns: */ 10200 /* Nothing. */ 10201 /****************************************************************************/ 10202 static __attribute__ ((noinline)) void 10203 bce_dump_com_state(struct bce_softc *sc, int regs) 10204 { 10205 u32 val; 10206 u32 fw_version[3]; 10207 10208 BCE_PRINTF( 10209 "----------------------------" 10210 " COM State " 10211 "----------------------------\n"); 10212 10213 for (int i = 0; i < 3; i++) 10214 fw_version[i] = htonl(REG_RD_IND(sc, 10215 (BCE_COM_SCRATCH + 0x10 + i * 4))); 10216 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10217 10218 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 10219 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", val, BCE_COM_CPU_MODE); 10220 10221 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10222 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE); 10223 10224 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 10225 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 10226 BCE_COM_CPU_EVENT_MASK); 10227 10228 if (regs) { 10229 BCE_PRINTF( 10230 "----------------------------" 10231 " Register Dump " 10232 "----------------------------\n"); 10233 10234 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 10235 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10236 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 10237 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 10238 } 10239 } 10240 10241 BCE_PRINTF( 10242 "----------------------------" 10243 "----------------" 10244 "----------------------------\n"); 10245 } 10246 10247 10248 /****************************************************************************/ 10249 /* Prints out the driver state and then enters the debugger. */ 10250 /* */ 10251 /* Returns: */ 10252 /* Nothing. */ 10253 /****************************************************************************/ 10254 static void 10255 bce_breakpoint(struct bce_softc *sc) 10256 { 10257 10258 /* 10259 * Unreachable code to silence compiler warnings 10260 * about unused functions. 10261 */ 10262 if (0) { 10263 bce_freeze_controller(sc); 10264 bce_unfreeze_controller(sc); 10265 bce_dump_enet(sc, NULL); 10266 bce_dump_txbd(sc, 0, NULL); 10267 bce_dump_rxbd(sc, 0, NULL); 10268 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 10269 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 10270 bce_dump_l2fhdr(sc, 0, NULL); 10271 bce_dump_ctx(sc, RX_CID); 10272 bce_dump_ftqs(sc); 10273 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 10274 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 10275 bce_dump_status_block(sc); 10276 bce_dump_stats_block(sc); 10277 bce_dump_driver_state(sc); 10278 bce_dump_hw_state(sc); 10279 bce_dump_bc_state(sc); 10280 bce_dump_txp_state(sc, 0); 10281 bce_dump_rxp_state(sc, 0); 10282 bce_dump_tpat_state(sc, 0); 10283 bce_dump_cp_state(sc, 0); 10284 bce_dump_com_state(sc, 0); 10285 #ifdef ZERO_COPY_SOCKETS 10286 bce_dump_pgbd(sc, 0, NULL); 10287 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD); 10288 bce_dump_pg_chain(sc, 0, USABLE_PG_BD); 10289 #endif 10290 } 10291 10292 bce_dump_status_block(sc); 10293 bce_dump_driver_state(sc); 10294 10295 /* Call the debugger. */ 10296 breakpoint(); 10297 10298 return; 10299 } 10300 #endif 10301 10302