1 /*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54 #include "opt_bce.h" 55 56 #include <dev/bce/if_bcereg.h> 57 #include <dev/bce/if_bcefw.h> 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89 #endif 90 91 /****************************************************************************/ 92 /* PCI Device ID Table */ 93 /* */ 94 /* Used by bce_probe() to identify the devices supported by this driver. */ 95 /****************************************************************************/ 96 #define BCE_DEVDESC_MAX 64 97 98 static struct bce_type bce_devs[] = { 99 /* BCM5706C Controllers and OEM boards. */ 100 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 101 "HP NC370T Multifunction Gigabit Server Adapter" }, 102 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 103 "HP NC370i Multifunction Gigabit Server Adapter" }, 104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 105 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 107 "HP NC371i Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 109 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 110 111 /* BCM5706S controllers and OEM boards. */ 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 113 "HP NC370F Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 116 117 /* BCM5708C controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 119 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 121 "HP NC373i Multifunction Gigabit Server Adapter" }, 122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 123 "HP NC374m PCIe Multifunction Adapter" }, 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 125 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 126 127 /* BCM5708S controllers and OEM boards. */ 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 129 "HP NC373m Multifunction Gigabit Server Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 131 "HP NC373i Multifunction Gigabit Server Adapter" }, 132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 133 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 135 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 136 137 /* BCM5709C controllers and OEM boards. */ 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 139 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 141 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 143 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 144 145 /* BCM5709S controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 147 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 149 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 151 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 152 153 /* BCM5716 controllers and OEM boards. */ 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 155 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 156 157 { 0, 0, 0, 0, NULL } 158 }; 159 160 161 /****************************************************************************/ 162 /* Supported Flash NVRAM device data. */ 163 /****************************************************************************/ 164 static struct flash_spec flash_table[] = 165 { 166 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 167 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 168 169 /* Slow EEPROM */ 170 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 171 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 172 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 173 "EEPROM - slow"}, 174 /* Expansion entry 0001 */ 175 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 178 "Entry 0001"}, 179 /* Saifun SA25F010 (non-buffered flash) */ 180 /* strap, cfg1, & write1 need updates */ 181 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 184 "Non-buffered flash (128kB)"}, 185 /* Saifun SA25F020 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 190 "Non-buffered flash (256kB)"}, 191 /* Expansion entry 0100 */ 192 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0100"}, 196 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 197 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 198 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 199 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 200 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 201 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 202 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 204 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 205 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 206 /* Saifun SA25F005 (non-buffered flash) */ 207 /* strap, cfg1, & write1 need updates */ 208 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 210 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 211 "Non-buffered flash (64kB)"}, 212 /* Fast EEPROM */ 213 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 214 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 215 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 216 "EEPROM - fast"}, 217 /* Expansion entry 1001 */ 218 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 221 "Entry 1001"}, 222 /* Expansion entry 1010 */ 223 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 226 "Entry 1010"}, 227 /* ATMEL AT45DB011B (buffered flash) */ 228 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 230 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 231 "Buffered flash (128kB)"}, 232 /* Expansion entry 1100 */ 233 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 236 "Entry 1100"}, 237 /* Expansion entry 1101 */ 238 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 1101"}, 242 /* Ateml Expansion entry 1110 */ 243 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 244 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 245 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 246 "Entry 1110 (Atmel)"}, 247 /* ATMEL AT45DB021B (buffered flash) */ 248 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 251 "Buffered flash (256kB)"}, 252 }; 253 254 /* 255 * The BCM5709 controllers transparently handle the 256 * differences between Atmel 264 byte pages and all 257 * flash devices which use 256 byte pages, so no 258 * logical-to-physical mapping is required in the 259 * driver. 260 */ 261 static struct flash_spec flash_5709 = { 262 .flags = BCE_NV_BUFFERED, 263 .page_bits = BCM5709_FLASH_PAGE_BITS, 264 .page_size = BCM5709_FLASH_PAGE_SIZE, 265 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 266 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 267 .name = "5709/5716 buffered flash (256kB)", 268 }; 269 270 271 /****************************************************************************/ 272 /* FreeBSD device entry points. */ 273 /****************************************************************************/ 274 static int bce_probe (device_t); 275 static int bce_attach (device_t); 276 static int bce_detach (device_t); 277 static int bce_shutdown (device_t); 278 279 280 /****************************************************************************/ 281 /* BCE Debug Data Structure Dump Routines */ 282 /****************************************************************************/ 283 #ifdef BCE_DEBUG 284 static u32 bce_reg_rd (struct bce_softc *, u32); 285 static void bce_reg_wr (struct bce_softc *, u32, u32); 286 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 287 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 288 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 289 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 290 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 291 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 292 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 293 static void bce_dump_txbd (struct bce_softc *, 294 int, struct tx_bd *); 295 static void bce_dump_rxbd (struct bce_softc *, 296 int, struct rx_bd *); 297 static void bce_dump_pgbd (struct bce_softc *, 298 int, struct rx_bd *); 299 static void bce_dump_l2fhdr (struct bce_softc *, 300 int, struct l2_fhdr *); 301 static void bce_dump_ctx (struct bce_softc *, u16); 302 static void bce_dump_ftqs (struct bce_softc *); 303 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 304 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 305 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 306 static void bce_dump_status_block (struct bce_softc *); 307 static void bce_dump_stats_block (struct bce_softc *); 308 static void bce_dump_driver_state (struct bce_softc *); 309 static void bce_dump_hw_state (struct bce_softc *); 310 static void bce_dump_shmem_state (struct bce_softc *); 311 static void bce_dump_mq_regs (struct bce_softc *); 312 static void bce_dump_bc_state (struct bce_softc *); 313 static void bce_dump_txp_state (struct bce_softc *, int); 314 static void bce_dump_rxp_state (struct bce_softc *, int); 315 static void bce_dump_tpat_state (struct bce_softc *, int); 316 static void bce_dump_cp_state (struct bce_softc *, int); 317 static void bce_dump_com_state (struct bce_softc *, int); 318 static void bce_dump_rv2p_state (struct bce_softc *); 319 static void bce_breakpoint (struct bce_softc *); 320 #endif /*BCE_DEBUG */ 321 322 323 /****************************************************************************/ 324 /* BCE Register/Memory Access Routines */ 325 /****************************************************************************/ 326 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 327 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 328 static void bce_shmem_wr (struct bce_softc *, u32, u32); 329 static u32 bce_shmem_rd (struct bce_softc *, u32); 330 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 331 static int bce_miibus_read_reg (device_t, int, int); 332 static int bce_miibus_write_reg (device_t, int, int, int); 333 static void bce_miibus_statchg (device_t); 334 335 #ifdef BCE_DEBUG 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 337 #ifdef BCE_NVRAM_WRITE_SUPPORT 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 339 #endif 340 #endif 341 342 /****************************************************************************/ 343 /* BCE NVRAM Access Routines */ 344 /****************************************************************************/ 345 static int bce_acquire_nvram_lock (struct bce_softc *); 346 static int bce_release_nvram_lock (struct bce_softc *); 347 static void bce_enable_nvram_access(struct bce_softc *); 348 static void bce_disable_nvram_access(struct bce_softc *); 349 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 350 static int bce_init_nvram (struct bce_softc *); 351 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 352 static int bce_nvram_test (struct bce_softc *); 353 #ifdef BCE_NVRAM_WRITE_SUPPORT 354 static int bce_enable_nvram_write (struct bce_softc *); 355 static void bce_disable_nvram_write(struct bce_softc *); 356 static int bce_nvram_erase_page (struct bce_softc *, u32); 357 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 358 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 359 #endif 360 361 /****************************************************************************/ 362 /* */ 363 /****************************************************************************/ 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 365 static void bce_get_media (struct bce_softc *); 366 static void bce_init_media (struct bce_softc *); 367 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 368 static int bce_dma_alloc (device_t); 369 static void bce_dma_free (struct bce_softc *); 370 static void bce_release_resources (struct bce_softc *); 371 372 /****************************************************************************/ 373 /* BCE Firmware Synchronization and Load */ 374 /****************************************************************************/ 375 static int bce_fw_sync (struct bce_softc *, u32); 376 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 377 static void bce_load_cpu_fw (struct bce_softc *, 378 struct cpu_reg *, struct fw_info *); 379 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 380 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 381 static void bce_start_rxp_cpu (struct bce_softc *); 382 static void bce_init_rxp_cpu (struct bce_softc *); 383 static void bce_init_txp_cpu (struct bce_softc *); 384 static void bce_init_tpat_cpu (struct bce_softc *); 385 static void bce_init_cp_cpu (struct bce_softc *); 386 static void bce_init_com_cpu (struct bce_softc *); 387 static void bce_init_cpus (struct bce_softc *); 388 389 static void bce_print_adapter_info (struct bce_softc *); 390 static void bce_probe_pci_caps (device_t, struct bce_softc *); 391 static void bce_stop (struct bce_softc *); 392 static int bce_reset (struct bce_softc *, u32); 393 static int bce_chipinit (struct bce_softc *); 394 static int bce_blockinit (struct bce_softc *); 395 396 static int bce_init_tx_chain (struct bce_softc *); 397 static void bce_free_tx_chain (struct bce_softc *); 398 399 static int bce_get_rx_buf (struct bce_softc *, 400 struct mbuf *, u16 *, u16 *, u32 *); 401 static int bce_init_rx_chain (struct bce_softc *); 402 static void bce_fill_rx_chain (struct bce_softc *); 403 static void bce_free_rx_chain (struct bce_softc *); 404 405 static int bce_get_pg_buf (struct bce_softc *, 406 struct mbuf *, u16 *, u16 *); 407 static int bce_init_pg_chain (struct bce_softc *); 408 static void bce_fill_pg_chain (struct bce_softc *); 409 static void bce_free_pg_chain (struct bce_softc *); 410 411 static struct mbuf *bce_tso_setup (struct bce_softc *, 412 struct mbuf **, u16 *); 413 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 414 static void bce_start_locked (struct ifnet *); 415 static void bce_start (struct ifnet *); 416 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 417 static void bce_watchdog (struct bce_softc *); 418 static int bce_ifmedia_upd (struct ifnet *); 419 static int bce_ifmedia_upd_locked (struct ifnet *); 420 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 421 static void bce_init_locked (struct bce_softc *); 422 static void bce_init (void *); 423 static void bce_mgmt_init_locked (struct bce_softc *sc); 424 425 static int bce_init_ctx (struct bce_softc *); 426 static void bce_get_mac_addr (struct bce_softc *); 427 static void bce_set_mac_addr (struct bce_softc *); 428 static void bce_phy_intr (struct bce_softc *); 429 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 430 static void bce_rx_intr (struct bce_softc *); 431 static void bce_tx_intr (struct bce_softc *); 432 static void bce_disable_intr (struct bce_softc *); 433 static void bce_enable_intr (struct bce_softc *, int); 434 435 static void bce_intr (void *); 436 static void bce_set_rx_mode (struct bce_softc *); 437 static void bce_stats_update (struct bce_softc *); 438 static void bce_tick (void *); 439 static void bce_pulse (void *); 440 static void bce_add_sysctls (struct bce_softc *); 441 442 443 /****************************************************************************/ 444 /* FreeBSD device dispatch table. */ 445 /****************************************************************************/ 446 static device_method_t bce_methods[] = { 447 /* Device interface (device_if.h) */ 448 DEVMETHOD(device_probe, bce_probe), 449 DEVMETHOD(device_attach, bce_attach), 450 DEVMETHOD(device_detach, bce_detach), 451 DEVMETHOD(device_shutdown, bce_shutdown), 452 /* Supported by device interface but not used here. */ 453 /* DEVMETHOD(device_identify, bce_identify), */ 454 /* DEVMETHOD(device_suspend, bce_suspend), */ 455 /* DEVMETHOD(device_resume, bce_resume), */ 456 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 457 458 /* MII interface (miibus_if.h) */ 459 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 460 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 461 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 462 /* Supported by MII interface but not used here. */ 463 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 464 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 465 466 DEVMETHOD_END 467 }; 468 469 static driver_t bce_driver = { 470 "bce", 471 bce_methods, 472 sizeof(struct bce_softc) 473 }; 474 475 static devclass_t bce_devclass; 476 477 MODULE_DEPEND(bce, pci, 1, 1, 1); 478 MODULE_DEPEND(bce, ether, 1, 1, 1); 479 MODULE_DEPEND(bce, miibus, 1, 1, 1); 480 481 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 482 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 483 484 485 /****************************************************************************/ 486 /* Tunable device values */ 487 /****************************************************************************/ 488 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 489 490 /* Allowable values are TRUE or FALSE */ 491 static int bce_verbose = TRUE; 492 TUNABLE_INT("hw.bce.verbose", &bce_verbose); 493 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 494 "Verbose output enable/disable"); 495 496 /* Allowable values are TRUE or FALSE */ 497 static int bce_tso_enable = TRUE; 498 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 499 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 500 "TSO Enable/Disable"); 501 502 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 503 /* ToDo: Add MSI-X support. */ 504 static int bce_msi_enable = 1; 505 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 506 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 507 "MSI-X|MSI|INTx selector"); 508 509 /* Allowable values are 1, 2, 4, 8. */ 510 static int bce_rx_pages = DEFAULT_RX_PAGES; 511 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 512 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 513 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 514 515 /* Allowable values are 1, 2, 4, 8. */ 516 static int bce_tx_pages = DEFAULT_TX_PAGES; 517 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 518 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 519 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 520 521 /* Allowable values are TRUE or FALSE. */ 522 static int bce_hdr_split = TRUE; 523 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 524 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 525 "Frame header/payload splitting Enable/Disable"); 526 527 /* Allowable values are TRUE or FALSE. */ 528 static int bce_strict_rx_mtu = FALSE; 529 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 530 SYSCTL_UINT(_hw_bce, OID_AUTO, loose_rx_mtu, CTLFLAG_RDTUN, 531 &bce_strict_rx_mtu, 0, 532 "Enable/Disable strict RX frame size checking"); 533 534 /* Allowable values are 0 ... 100 */ 535 #ifdef BCE_DEBUG 536 /* Generate 1 interrupt for every transmit completion. */ 537 static int bce_tx_quick_cons_trip_int = 1; 538 #else 539 /* Generate 1 interrupt for every 20 transmit completions. */ 540 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 541 #endif 542 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 543 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 544 &bce_tx_quick_cons_trip_int, 0, 545 "Transmit BD trip point during interrupts"); 546 547 /* Allowable values are 0 ... 100 */ 548 /* Generate 1 interrupt for every transmit completion. */ 549 #ifdef BCE_DEBUG 550 static int bce_tx_quick_cons_trip = 1; 551 #else 552 /* Generate 1 interrupt for every 20 transmit completions. */ 553 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 554 #endif 555 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 556 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 557 &bce_tx_quick_cons_trip, 0, 558 "Transmit BD trip point"); 559 560 /* Allowable values are 0 ... 100 */ 561 #ifdef BCE_DEBUG 562 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 563 static int bce_tx_ticks_int = 0; 564 #else 565 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 566 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 567 #endif 568 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 569 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 570 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 571 572 /* Allowable values are 0 ... 100 */ 573 #ifdef BCE_DEBUG 574 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 575 static int bce_tx_ticks = 0; 576 #else 577 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 578 static int bce_tx_ticks = DEFAULT_TX_TICKS; 579 #endif 580 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 581 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 582 &bce_tx_ticks, 0, "Transmit ticks count"); 583 584 /* Allowable values are 1 ... 100 */ 585 #ifdef BCE_DEBUG 586 /* Generate 1 interrupt for every received frame. */ 587 static int bce_rx_quick_cons_trip_int = 1; 588 #else 589 /* Generate 1 interrupt for every 6 received frames. */ 590 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 591 #endif 592 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 593 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 594 &bce_rx_quick_cons_trip_int, 0, 595 "Receive BD trip point duirng interrupts"); 596 597 /* Allowable values are 1 ... 100 */ 598 #ifdef BCE_DEBUG 599 /* Generate 1 interrupt for every received frame. */ 600 static int bce_rx_quick_cons_trip = 1; 601 #else 602 /* Generate 1 interrupt for every 6 received frames. */ 603 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 604 #endif 605 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 606 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 607 &bce_rx_quick_cons_trip, 0, 608 "Receive BD trip point"); 609 610 /* Allowable values are 0 ... 100 */ 611 #ifdef BCE_DEBUG 612 /* Generate an int. if 0us have elapsed since the last received frame. */ 613 static int bce_rx_ticks_int = 0; 614 #else 615 /* Generate an int. if 18us have elapsed since the last received frame. */ 616 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 617 #endif 618 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 619 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 620 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 621 622 /* Allowable values are 0 ... 100 */ 623 #ifdef BCE_DEBUG 624 /* Generate an int. if 0us have elapsed since the last received frame. */ 625 static int bce_rx_ticks = 0; 626 #else 627 /* Generate an int. if 18us have elapsed since the last received frame. */ 628 static int bce_rx_ticks = DEFAULT_RX_TICKS; 629 #endif 630 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 631 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 632 &bce_rx_ticks, 0, "Receive ticks count"); 633 634 635 /****************************************************************************/ 636 /* Device probe function. */ 637 /* */ 638 /* Compares the device to the driver's list of supported devices and */ 639 /* reports back to the OS whether this is the right driver for the device. */ 640 /* */ 641 /* Returns: */ 642 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 643 /****************************************************************************/ 644 static int 645 bce_probe(device_t dev) 646 { 647 struct bce_type *t; 648 struct bce_softc *sc; 649 char *descbuf; 650 u16 vid = 0, did = 0, svid = 0, sdid = 0; 651 652 t = bce_devs; 653 654 sc = device_get_softc(dev); 655 bzero(sc, sizeof(struct bce_softc)); 656 sc->bce_unit = device_get_unit(dev); 657 sc->bce_dev = dev; 658 659 /* Get the data for the device to be probed. */ 660 vid = pci_get_vendor(dev); 661 did = pci_get_device(dev); 662 svid = pci_get_subvendor(dev); 663 sdid = pci_get_subdevice(dev); 664 665 DBPRINT(sc, BCE_EXTREME_LOAD, 666 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 667 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 668 669 /* Look through the list of known devices for a match. */ 670 while(t->bce_name != NULL) { 671 672 if ((vid == t->bce_vid) && (did == t->bce_did) && 673 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 674 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 675 676 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 677 678 if (descbuf == NULL) 679 return(ENOMEM); 680 681 /* Print out the device identity. */ 682 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 683 t->bce_name, (((pci_read_config(dev, 684 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 685 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 686 687 device_set_desc_copy(dev, descbuf); 688 free(descbuf, M_TEMP); 689 return(BUS_PROBE_DEFAULT); 690 } 691 t++; 692 } 693 694 return(ENXIO); 695 } 696 697 698 /****************************************************************************/ 699 /* PCI Capabilities Probe Function. */ 700 /* */ 701 /* Walks the PCI capabiites list for the device to find what features are */ 702 /* supported. */ 703 /* */ 704 /* Returns: */ 705 /* None. */ 706 /****************************************************************************/ 707 static void 708 bce_print_adapter_info(struct bce_softc *sc) 709 { 710 int i = 0; 711 712 DBENTER(BCE_VERBOSE_LOAD); 713 714 if (bce_verbose || bootverbose) { 715 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 716 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 717 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 718 719 720 /* Bus info. */ 721 if (sc->bce_flags & BCE_PCIE_FLAG) { 722 printf("Bus (PCIe x%d, ", sc->link_width); 723 switch (sc->link_speed) { 724 case 1: printf("2.5Gbps); "); break; 725 case 2: printf("5Gbps); "); break; 726 default: printf("Unknown link speed); "); 727 } 728 } else { 729 printf("Bus (PCI%s, %s, %dMHz); ", 730 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 731 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 732 "32-bit" : "64-bit"), sc->bus_speed_mhz); 733 } 734 735 /* Firmware version and device features. */ 736 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 737 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 738 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 739 740 if (bce_hdr_split == TRUE) { 741 printf("SPLT"); 742 i++; 743 } 744 745 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 746 if (i > 0) printf("|"); 747 printf("MSI"); i++; 748 } 749 750 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 751 if (i > 0) printf("|"); 752 printf("MSI-X"); i++; 753 } 754 755 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 756 if (i > 0) printf("|"); 757 printf("2.5G"); i++; 758 } 759 760 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 761 if (i > 0) printf("|"); 762 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 763 } else { 764 printf(")\n"); 765 } 766 767 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 768 sc->bce_rx_quick_cons_trip_int, 769 sc->bce_rx_quick_cons_trip, 770 sc->bce_rx_ticks_int, 771 sc->bce_rx_ticks, 772 sc->bce_tx_quick_cons_trip_int, 773 sc->bce_tx_quick_cons_trip, 774 sc->bce_tx_ticks_int, 775 sc->bce_tx_ticks); 776 777 } 778 779 DBEXIT(BCE_VERBOSE_LOAD); 780 } 781 782 783 /****************************************************************************/ 784 /* PCI Capabilities Probe Function. */ 785 /* */ 786 /* Walks the PCI capabiites list for the device to find what features are */ 787 /* supported. */ 788 /* */ 789 /* Returns: */ 790 /* None. */ 791 /****************************************************************************/ 792 static void 793 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 794 { 795 u32 reg; 796 797 DBENTER(BCE_VERBOSE_LOAD); 798 799 /* Check if PCI-X capability is enabled. */ 800 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 801 if (reg != 0) 802 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 803 } 804 805 /* Check if PCIe capability is enabled. */ 806 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 807 if (reg != 0) { 808 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 809 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 810 "0x%08X\n", link_status); 811 sc->link_speed = link_status & 0xf; 812 sc->link_width = (link_status >> 4) & 0x3f; 813 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 814 sc->bce_flags |= BCE_PCIE_FLAG; 815 } 816 } 817 818 /* Check if MSI capability is enabled. */ 819 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 820 if (reg != 0) 821 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 822 } 823 824 /* Check if MSI-X capability is enabled. */ 825 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 826 if (reg != 0) 827 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 828 } 829 830 DBEXIT(BCE_VERBOSE_LOAD); 831 } 832 833 834 /****************************************************************************/ 835 /* Load and validate user tunable settings. */ 836 /* */ 837 /* Returns: */ 838 /* Nothing. */ 839 /****************************************************************************/ 840 static void 841 bce_set_tunables(struct bce_softc *sc) 842 { 843 /* Set sysctl values for RX page count. */ 844 switch (bce_rx_pages) { 845 case 1: 846 /* fall-through */ 847 case 2: 848 /* fall-through */ 849 case 4: 850 /* fall-through */ 851 case 8: 852 sc->rx_pages = bce_rx_pages; 853 break; 854 default: 855 sc->rx_pages = DEFAULT_RX_PAGES; 856 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 857 "hw.bce.rx_pages! Setting default of %d.\n", 858 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 859 } 860 861 /* ToDo: Consider allowing user setting for pg_pages. */ 862 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 863 864 /* Set sysctl values for TX page count. */ 865 switch (bce_tx_pages) { 866 case 1: 867 /* fall-through */ 868 case 2: 869 /* fall-through */ 870 case 4: 871 /* fall-through */ 872 case 8: 873 sc->tx_pages = bce_tx_pages; 874 break; 875 default: 876 sc->tx_pages = DEFAULT_TX_PAGES; 877 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 878 "hw.bce.tx_pages! Setting default of %d.\n", 879 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 880 } 881 882 /* 883 * Validate the TX trip point (i.e. the number of 884 * TX completions before a status block update is 885 * generated and an interrupt is asserted. 886 */ 887 if (bce_tx_quick_cons_trip_int <= 100) { 888 sc->bce_tx_quick_cons_trip_int = 889 bce_tx_quick_cons_trip_int; 890 } else { 891 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 892 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 893 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 894 DEFAULT_TX_QUICK_CONS_TRIP_INT); 895 sc->bce_tx_quick_cons_trip_int = 896 DEFAULT_TX_QUICK_CONS_TRIP_INT; 897 } 898 899 if (bce_tx_quick_cons_trip <= 100) { 900 sc->bce_tx_quick_cons_trip = 901 bce_tx_quick_cons_trip; 902 } else { 903 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 904 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 905 __FILE__, __LINE__, bce_tx_quick_cons_trip, 906 DEFAULT_TX_QUICK_CONS_TRIP); 907 sc->bce_tx_quick_cons_trip = 908 DEFAULT_TX_QUICK_CONS_TRIP; 909 } 910 911 /* 912 * Validate the TX ticks count (i.e. the maximum amount 913 * of time to wait after the last TX completion has 914 * occurred before a status block update is generated 915 * and an interrupt is asserted. 916 */ 917 if (bce_tx_ticks_int <= 100) { 918 sc->bce_tx_ticks_int = 919 bce_tx_ticks_int; 920 } else { 921 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 922 "hw.bce.tx_ticks_int! Setting default of %d.\n", 923 __FILE__, __LINE__, bce_tx_ticks_int, 924 DEFAULT_TX_TICKS_INT); 925 sc->bce_tx_ticks_int = 926 DEFAULT_TX_TICKS_INT; 927 } 928 929 if (bce_tx_ticks <= 100) { 930 sc->bce_tx_ticks = 931 bce_tx_ticks; 932 } else { 933 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 934 "hw.bce.tx_ticks! Setting default of %d.\n", 935 __FILE__, __LINE__, bce_tx_ticks, 936 DEFAULT_TX_TICKS); 937 sc->bce_tx_ticks = 938 DEFAULT_TX_TICKS; 939 } 940 941 /* 942 * Validate the RX trip point (i.e. the number of 943 * RX frames received before a status block update is 944 * generated and an interrupt is asserted. 945 */ 946 if (bce_rx_quick_cons_trip_int <= 100) { 947 sc->bce_rx_quick_cons_trip_int = 948 bce_rx_quick_cons_trip_int; 949 } else { 950 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 951 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 952 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 953 DEFAULT_RX_QUICK_CONS_TRIP_INT); 954 sc->bce_rx_quick_cons_trip_int = 955 DEFAULT_RX_QUICK_CONS_TRIP_INT; 956 } 957 958 if (bce_rx_quick_cons_trip <= 100) { 959 sc->bce_rx_quick_cons_trip = 960 bce_rx_quick_cons_trip; 961 } else { 962 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 963 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 964 __FILE__, __LINE__, bce_rx_quick_cons_trip, 965 DEFAULT_RX_QUICK_CONS_TRIP); 966 sc->bce_rx_quick_cons_trip = 967 DEFAULT_RX_QUICK_CONS_TRIP; 968 } 969 970 /* 971 * Validate the RX ticks count (i.e. the maximum amount 972 * of time to wait after the last RX frame has been 973 * received before a status block update is generated 974 * and an interrupt is asserted. 975 */ 976 if (bce_rx_ticks_int <= 100) { 977 sc->bce_rx_ticks_int = bce_rx_ticks_int; 978 } else { 979 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 980 "hw.bce.rx_ticks_int! Setting default of %d.\n", 981 __FILE__, __LINE__, bce_rx_ticks_int, 982 DEFAULT_RX_TICKS_INT); 983 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 984 } 985 986 if (bce_rx_ticks <= 100) { 987 sc->bce_rx_ticks = bce_rx_ticks; 988 } else { 989 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 990 "hw.bce.rx_ticks! Setting default of %d.\n", 991 __FILE__, __LINE__, bce_rx_ticks, 992 DEFAULT_RX_TICKS); 993 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 994 } 995 996 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 997 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 998 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 999 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1000 __FILE__, __LINE__); 1001 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1002 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1003 } 1004 1005 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1006 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1007 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1008 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1009 __FILE__, __LINE__); 1010 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1011 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1012 } 1013 1014 } 1015 1016 1017 /****************************************************************************/ 1018 /* Device attach function. */ 1019 /* */ 1020 /* Allocates device resources, performs secondary chip identification, */ 1021 /* resets and initializes the hardware, and initializes driver instance */ 1022 /* variables. */ 1023 /* */ 1024 /* Returns: */ 1025 /* 0 on success, positive value on failure. */ 1026 /****************************************************************************/ 1027 static int 1028 bce_attach(device_t dev) 1029 { 1030 struct bce_softc *sc; 1031 struct ifnet *ifp; 1032 u32 val; 1033 int error, rid, rc = 0; 1034 1035 sc = device_get_softc(dev); 1036 sc->bce_dev = dev; 1037 1038 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1039 1040 sc->bce_unit = device_get_unit(dev); 1041 1042 /* Set initial device and PHY flags */ 1043 sc->bce_flags = 0; 1044 sc->bce_phy_flags = 0; 1045 1046 bce_set_tunables(sc); 1047 1048 pci_enable_busmaster(dev); 1049 1050 /* Allocate PCI memory resources. */ 1051 rid = PCIR_BAR(0); 1052 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1053 &rid, RF_ACTIVE); 1054 1055 if (sc->bce_res_mem == NULL) { 1056 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1057 __FILE__, __LINE__); 1058 rc = ENXIO; 1059 goto bce_attach_fail; 1060 } 1061 1062 /* Get various resource handles. */ 1063 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1064 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1065 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1066 1067 bce_probe_pci_caps(dev, sc); 1068 1069 rid = 1; 1070 #if 0 1071 /* Try allocating MSI-X interrupts. */ 1072 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1073 (bce_msi_enable >= 2) && 1074 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1075 &rid, RF_ACTIVE)) != NULL)) { 1076 1077 msi_needed = sc->bce_msi_count = 1; 1078 1079 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 1080 (sc->bce_msi_count != msi_needed)) { 1081 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1082 "Received = %d, error = %d\n", __FILE__, __LINE__, 1083 msi_needed, sc->bce_msi_count, error); 1084 sc->bce_msi_count = 0; 1085 pci_release_msi(dev); 1086 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1087 sc->bce_res_irq); 1088 sc->bce_res_irq = NULL; 1089 } else { 1090 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1091 __FUNCTION__); 1092 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1093 sc->bce_intr = bce_intr; 1094 } 1095 } 1096 #endif 1097 1098 /* Try allocating a MSI interrupt. */ 1099 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1100 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 1101 sc->bce_msi_count = 1; 1102 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 1103 BCE_PRINTF("%s(%d): MSI allocation failed! " 1104 "error = %d\n", __FILE__, __LINE__, error); 1105 sc->bce_msi_count = 0; 1106 pci_release_msi(dev); 1107 } else { 1108 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1109 "interrupt.\n", __FUNCTION__); 1110 sc->bce_flags |= BCE_USING_MSI_FLAG; 1111 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1112 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1113 sc->bce_irq_rid = 1; 1114 sc->bce_intr = bce_intr; 1115 } 1116 } 1117 1118 /* Try allocating a legacy interrupt. */ 1119 if (sc->bce_msi_count == 0) { 1120 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1121 __FUNCTION__); 1122 rid = 0; 1123 sc->bce_intr = bce_intr; 1124 } 1125 1126 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1127 &rid, RF_SHAREABLE | RF_ACTIVE); 1128 1129 sc->bce_irq_rid = rid; 1130 1131 /* Report any IRQ allocation errors. */ 1132 if (sc->bce_res_irq == NULL) { 1133 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1134 __FILE__, __LINE__); 1135 rc = ENXIO; 1136 goto bce_attach_fail; 1137 } 1138 1139 /* Initialize mutex for the current device instance. */ 1140 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1141 1142 /* 1143 * Configure byte swap and enable indirect register access. 1144 * Rely on CPU to do target byte swapping on big endian systems. 1145 * Access to registers outside of PCI configurtion space are not 1146 * valid until this is done. 1147 */ 1148 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1149 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1150 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1151 1152 /* Save ASIC revsion info. */ 1153 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1154 1155 /* Weed out any non-production controller revisions. */ 1156 switch(BCE_CHIP_ID(sc)) { 1157 case BCE_CHIP_ID_5706_A0: 1158 case BCE_CHIP_ID_5706_A1: 1159 case BCE_CHIP_ID_5708_A0: 1160 case BCE_CHIP_ID_5708_B0: 1161 case BCE_CHIP_ID_5709_A0: 1162 case BCE_CHIP_ID_5709_B0: 1163 case BCE_CHIP_ID_5709_B1: 1164 case BCE_CHIP_ID_5709_B2: 1165 BCE_PRINTF("%s(%d): Unsupported controller " 1166 "revision (%c%d)!\n", __FILE__, __LINE__, 1167 (((pci_read_config(dev, PCIR_REVID, 4) & 1168 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1169 PCIR_REVID, 4) & 0xf)); 1170 rc = ENODEV; 1171 goto bce_attach_fail; 1172 } 1173 1174 /* 1175 * The embedded PCIe to PCI-X bridge (EPB) 1176 * in the 5708 cannot address memory above 1177 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1178 */ 1179 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1180 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1181 else 1182 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1183 1184 /* 1185 * Find the base address for shared memory access. 1186 * Newer versions of bootcode use a signature and offset 1187 * while older versions use a fixed address. 1188 */ 1189 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1190 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1191 /* Multi-port devices use different offsets in shared memory. */ 1192 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1193 (pci_get_function(sc->bce_dev) << 2)); 1194 else 1195 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1196 1197 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1198 __FUNCTION__, sc->bce_shmem_base); 1199 1200 /* Fetch the bootcode revision. */ 1201 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1202 for (int i = 0, j = 0; i < 3; i++) { 1203 u8 num; 1204 1205 num = (u8) (val >> (24 - (i * 8))); 1206 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1207 if (num >= k || !skip0 || k == 1) { 1208 sc->bce_bc_ver[j++] = (num / k) + '0'; 1209 skip0 = 0; 1210 } 1211 } 1212 1213 if (i != 2) 1214 sc->bce_bc_ver[j++] = '.'; 1215 } 1216 1217 /* Check if any management firwmare is enabled. */ 1218 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1219 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1220 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1221 1222 /* Allow time for firmware to enter the running state. */ 1223 for (int i = 0; i < 30; i++) { 1224 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1225 if (val & BCE_CONDITION_MFW_RUN_MASK) 1226 break; 1227 DELAY(10000); 1228 } 1229 1230 /* Check if management firmware is running. */ 1231 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1232 val &= BCE_CONDITION_MFW_RUN_MASK; 1233 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1234 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1235 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1236 int i = 0; 1237 1238 /* Read the management firmware version string. */ 1239 for (int j = 0; j < 3; j++) { 1240 val = bce_reg_rd_ind(sc, addr + j * 4); 1241 val = bswap32(val); 1242 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1243 i += 4; 1244 } 1245 } else { 1246 /* May cause firmware synchronization timeouts. */ 1247 BCE_PRINTF("%s(%d): Management firmware enabled " 1248 "but not running!\n", __FILE__, __LINE__); 1249 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1250 1251 /* ToDo: Any action the driver should take? */ 1252 } 1253 } 1254 1255 /* Get PCI bus information (speed and type). */ 1256 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1257 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1258 u32 clkreg; 1259 1260 sc->bce_flags |= BCE_PCIX_FLAG; 1261 1262 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1263 1264 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1265 switch (clkreg) { 1266 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1267 sc->bus_speed_mhz = 133; 1268 break; 1269 1270 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1271 sc->bus_speed_mhz = 100; 1272 break; 1273 1274 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1275 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1276 sc->bus_speed_mhz = 66; 1277 break; 1278 1279 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1280 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1281 sc->bus_speed_mhz = 50; 1282 break; 1283 1284 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1285 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1286 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1287 sc->bus_speed_mhz = 33; 1288 break; 1289 } 1290 } else { 1291 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1292 sc->bus_speed_mhz = 66; 1293 else 1294 sc->bus_speed_mhz = 33; 1295 } 1296 1297 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1298 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1299 1300 /* Reset controller and announce to bootcode that driver is present. */ 1301 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1302 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1303 __FILE__, __LINE__); 1304 rc = ENXIO; 1305 goto bce_attach_fail; 1306 } 1307 1308 /* Initialize the controller. */ 1309 if (bce_chipinit(sc)) { 1310 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1311 __FILE__, __LINE__); 1312 rc = ENXIO; 1313 goto bce_attach_fail; 1314 } 1315 1316 /* Perform NVRAM test. */ 1317 if (bce_nvram_test(sc)) { 1318 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1319 __FILE__, __LINE__); 1320 rc = ENXIO; 1321 goto bce_attach_fail; 1322 } 1323 1324 /* Fetch the permanent Ethernet MAC address. */ 1325 bce_get_mac_addr(sc); 1326 1327 /* 1328 * Trip points control how many BDs 1329 * should be ready before generating an 1330 * interrupt while ticks control how long 1331 * a BD can sit in the chain before 1332 * generating an interrupt. Set the default 1333 * values for the RX and TX chains. 1334 */ 1335 1336 /* Not used for L2. */ 1337 sc->bce_comp_prod_trip_int = 0; 1338 sc->bce_comp_prod_trip = 0; 1339 sc->bce_com_ticks_int = 0; 1340 sc->bce_com_ticks = 0; 1341 sc->bce_cmd_ticks_int = 0; 1342 sc->bce_cmd_ticks = 0; 1343 1344 /* Update statistics once every second. */ 1345 sc->bce_stats_ticks = 1000000 & 0xffff00; 1346 1347 /* Find the media type for the adapter. */ 1348 bce_get_media(sc); 1349 1350 /* Store data needed by PHY driver for backplane applications */ 1351 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1352 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1353 1354 /* Allocate DMA memory resources. */ 1355 if (bce_dma_alloc(dev)) { 1356 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1357 __FILE__, __LINE__); 1358 rc = ENXIO; 1359 goto bce_attach_fail; 1360 } 1361 1362 /* Allocate an ifnet structure. */ 1363 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1364 if (ifp == NULL) { 1365 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1366 __FILE__, __LINE__); 1367 rc = ENXIO; 1368 goto bce_attach_fail; 1369 } 1370 1371 /* Initialize the ifnet interface. */ 1372 ifp->if_softc = sc; 1373 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1374 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1375 ifp->if_ioctl = bce_ioctl; 1376 ifp->if_start = bce_start; 1377 ifp->if_init = bce_init; 1378 ifp->if_mtu = ETHERMTU; 1379 1380 if (bce_tso_enable) { 1381 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1382 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1383 IFCAP_VLAN_HWTSO; 1384 } else { 1385 ifp->if_hwassist = BCE_IF_HWASSIST; 1386 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1387 } 1388 1389 ifp->if_capenable = ifp->if_capabilities; 1390 1391 /* 1392 * Assume standard mbuf sizes for buffer allocation. 1393 * This may change later if the MTU size is set to 1394 * something other than 1500. 1395 */ 1396 bce_get_rx_buffer_sizes(sc, 1397 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1398 1399 /* Recalculate our buffer allocation sizes. */ 1400 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1401 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1402 IFQ_SET_READY(&ifp->if_snd); 1403 1404 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1405 ifp->if_baudrate = IF_Mbps(2500ULL); 1406 else 1407 ifp->if_baudrate = IF_Mbps(1000); 1408 1409 /* Handle any special PHY initialization for SerDes PHYs. */ 1410 bce_init_media(sc); 1411 1412 /* MII child bus by attaching the PHY. */ 1413 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1414 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1415 MII_OFFSET_ANY, MIIF_DOPAUSE); 1416 if (rc != 0) { 1417 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1418 __LINE__); 1419 goto bce_attach_fail; 1420 } 1421 1422 /* Attach to the Ethernet interface list. */ 1423 ether_ifattach(ifp, sc->eaddr); 1424 1425 #if __FreeBSD_version < 500000 1426 callout_init(&sc->bce_tick_callout); 1427 callout_init(&sc->bce_pulse_callout); 1428 #else 1429 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1430 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1431 #endif 1432 1433 /* Hookup IRQ last. */ 1434 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1435 NULL, bce_intr, sc, &sc->bce_intrhand); 1436 1437 if (rc) { 1438 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1439 __FILE__, __LINE__); 1440 bce_detach(dev); 1441 goto bce_attach_exit; 1442 } 1443 1444 /* 1445 * At this point we've acquired all the resources 1446 * we need to run so there's no turning back, we're 1447 * cleared for launch. 1448 */ 1449 1450 /* Print some important debugging info. */ 1451 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1452 1453 /* Add the supported sysctls to the kernel. */ 1454 bce_add_sysctls(sc); 1455 1456 BCE_LOCK(sc); 1457 1458 /* 1459 * The chip reset earlier notified the bootcode that 1460 * a driver is present. We now need to start our pulse 1461 * routine so that the bootcode is reminded that we're 1462 * still running. 1463 */ 1464 bce_pulse(sc); 1465 1466 bce_mgmt_init_locked(sc); 1467 BCE_UNLOCK(sc); 1468 1469 /* Finally, print some useful adapter info */ 1470 bce_print_adapter_info(sc); 1471 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1472 __FUNCTION__, sc); 1473 1474 goto bce_attach_exit; 1475 1476 bce_attach_fail: 1477 bce_release_resources(sc); 1478 1479 bce_attach_exit: 1480 1481 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1482 1483 return(rc); 1484 } 1485 1486 1487 /****************************************************************************/ 1488 /* Device detach function. */ 1489 /* */ 1490 /* Stops the controller, resets the controller, and releases resources. */ 1491 /* */ 1492 /* Returns: */ 1493 /* 0 on success, positive value on failure. */ 1494 /****************************************************************************/ 1495 static int 1496 bce_detach(device_t dev) 1497 { 1498 struct bce_softc *sc = device_get_softc(dev); 1499 struct ifnet *ifp; 1500 u32 msg; 1501 1502 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1503 1504 ifp = sc->bce_ifp; 1505 1506 /* Stop and reset the controller. */ 1507 BCE_LOCK(sc); 1508 1509 /* Stop the pulse so the bootcode can go to driver absent state. */ 1510 callout_stop(&sc->bce_pulse_callout); 1511 1512 bce_stop(sc); 1513 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1514 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1515 else 1516 msg = BCE_DRV_MSG_CODE_UNLOAD; 1517 bce_reset(sc, msg); 1518 1519 BCE_UNLOCK(sc); 1520 1521 ether_ifdetach(ifp); 1522 1523 /* If we have a child device on the MII bus remove it too. */ 1524 bus_generic_detach(dev); 1525 device_delete_child(dev, sc->bce_miibus); 1526 1527 /* Release all remaining resources. */ 1528 bce_release_resources(sc); 1529 1530 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1531 1532 return(0); 1533 } 1534 1535 1536 /****************************************************************************/ 1537 /* Device shutdown function. */ 1538 /* */ 1539 /* Stops and resets the controller. */ 1540 /* */ 1541 /* Returns: */ 1542 /* 0 on success, positive value on failure. */ 1543 /****************************************************************************/ 1544 static int 1545 bce_shutdown(device_t dev) 1546 { 1547 struct bce_softc *sc = device_get_softc(dev); 1548 u32 msg; 1549 1550 DBENTER(BCE_VERBOSE); 1551 1552 BCE_LOCK(sc); 1553 bce_stop(sc); 1554 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1555 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1556 else 1557 msg = BCE_DRV_MSG_CODE_UNLOAD; 1558 bce_reset(sc, msg); 1559 BCE_UNLOCK(sc); 1560 1561 DBEXIT(BCE_VERBOSE); 1562 1563 return (0); 1564 } 1565 1566 1567 #ifdef BCE_DEBUG 1568 /****************************************************************************/ 1569 /* Register read. */ 1570 /* */ 1571 /* Returns: */ 1572 /* The value of the register. */ 1573 /****************************************************************************/ 1574 static u32 1575 bce_reg_rd(struct bce_softc *sc, u32 offset) 1576 { 1577 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1578 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1579 __FUNCTION__, offset, val); 1580 return val; 1581 } 1582 1583 1584 /****************************************************************************/ 1585 /* Register write (16 bit). */ 1586 /* */ 1587 /* Returns: */ 1588 /* Nothing. */ 1589 /****************************************************************************/ 1590 static void 1591 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1592 { 1593 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1594 __FUNCTION__, offset, val); 1595 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1596 } 1597 1598 1599 /****************************************************************************/ 1600 /* Register write. */ 1601 /* */ 1602 /* Returns: */ 1603 /* Nothing. */ 1604 /****************************************************************************/ 1605 static void 1606 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1607 { 1608 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1609 __FUNCTION__, offset, val); 1610 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1611 } 1612 #endif 1613 1614 /****************************************************************************/ 1615 /* Indirect register read. */ 1616 /* */ 1617 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1618 /* configuration space. Using this mechanism avoids issues with posted */ 1619 /* reads but is much slower than memory-mapped I/O. */ 1620 /* */ 1621 /* Returns: */ 1622 /* The value of the register. */ 1623 /****************************************************************************/ 1624 static u32 1625 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1626 { 1627 device_t dev; 1628 dev = sc->bce_dev; 1629 1630 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1631 #ifdef BCE_DEBUG 1632 { 1633 u32 val; 1634 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1635 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1636 __FUNCTION__, offset, val); 1637 return val; 1638 } 1639 #else 1640 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1641 #endif 1642 } 1643 1644 1645 /****************************************************************************/ 1646 /* Indirect register write. */ 1647 /* */ 1648 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1649 /* configuration space. Using this mechanism avoids issues with posted */ 1650 /* writes but is muchh slower than memory-mapped I/O. */ 1651 /* */ 1652 /* Returns: */ 1653 /* Nothing. */ 1654 /****************************************************************************/ 1655 static void 1656 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1657 { 1658 device_t dev; 1659 dev = sc->bce_dev; 1660 1661 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1662 __FUNCTION__, offset, val); 1663 1664 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1665 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1666 } 1667 1668 1669 /****************************************************************************/ 1670 /* Shared memory write. */ 1671 /* */ 1672 /* Writes NetXtreme II shared memory region. */ 1673 /* */ 1674 /* Returns: */ 1675 /* Nothing. */ 1676 /****************************************************************************/ 1677 static void 1678 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1679 { 1680 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1681 "0x%08X\n", __FUNCTION__, val, offset); 1682 1683 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1684 } 1685 1686 1687 /****************************************************************************/ 1688 /* Shared memory read. */ 1689 /* */ 1690 /* Reads NetXtreme II shared memory region. */ 1691 /* */ 1692 /* Returns: */ 1693 /* The 32 bit value read. */ 1694 /****************************************************************************/ 1695 static u32 1696 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1697 { 1698 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1699 1700 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1701 "0x%08X\n", __FUNCTION__, val, offset); 1702 1703 return val; 1704 } 1705 1706 1707 #ifdef BCE_DEBUG 1708 /****************************************************************************/ 1709 /* Context memory read. */ 1710 /* */ 1711 /* The NetXtreme II controller uses context memory to track connection */ 1712 /* information for L2 and higher network protocols. */ 1713 /* */ 1714 /* Returns: */ 1715 /* The requested 32 bit value of context memory. */ 1716 /****************************************************************************/ 1717 static u32 1718 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1719 { 1720 u32 idx, offset, retry_cnt = 5, val; 1721 1722 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1723 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1724 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1725 1726 offset = ctx_offset + cid_addr; 1727 1728 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1729 1730 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1731 1732 for (idx = 0; idx < retry_cnt; idx++) { 1733 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1734 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1735 break; 1736 DELAY(5); 1737 } 1738 1739 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1740 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1741 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1742 __FILE__, __LINE__, cid_addr, ctx_offset); 1743 1744 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1745 } else { 1746 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1747 val = REG_RD(sc, BCE_CTX_DATA); 1748 } 1749 1750 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1751 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1752 1753 return(val); 1754 } 1755 #endif 1756 1757 1758 /****************************************************************************/ 1759 /* Context memory write. */ 1760 /* */ 1761 /* The NetXtreme II controller uses context memory to track connection */ 1762 /* information for L2 and higher network protocols. */ 1763 /* */ 1764 /* Returns: */ 1765 /* Nothing. */ 1766 /****************************************************************************/ 1767 static void 1768 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1769 { 1770 u32 idx, offset = ctx_offset + cid_addr; 1771 u32 val, retry_cnt = 5; 1772 1773 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1774 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1775 1776 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1777 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1778 __FUNCTION__, cid_addr)); 1779 1780 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1781 1782 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1783 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1784 1785 for (idx = 0; idx < retry_cnt; idx++) { 1786 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1787 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1788 break; 1789 DELAY(5); 1790 } 1791 1792 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1793 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1794 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1795 __FILE__, __LINE__, cid_addr, ctx_offset); 1796 1797 } else { 1798 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1799 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1800 } 1801 } 1802 1803 1804 /****************************************************************************/ 1805 /* PHY register read. */ 1806 /* */ 1807 /* Implements register reads on the MII bus. */ 1808 /* */ 1809 /* Returns: */ 1810 /* The value of the register. */ 1811 /****************************************************************************/ 1812 static int 1813 bce_miibus_read_reg(device_t dev, int phy, int reg) 1814 { 1815 struct bce_softc *sc; 1816 u32 val; 1817 int i; 1818 1819 sc = device_get_softc(dev); 1820 1821 /* Make sure we are accessing the correct PHY address. */ 1822 if (phy != sc->bce_phy_addr) { 1823 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1824 "for PHY read!\n", phy); 1825 return(0); 1826 } 1827 1828 /* 1829 * The 5709S PHY is an IEEE Clause 45 PHY 1830 * with special mappings to work with IEEE 1831 * Clause 22 register accesses. 1832 */ 1833 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1834 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1835 reg += 0x10; 1836 } 1837 1838 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1839 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1840 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1841 1842 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1843 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1844 1845 DELAY(40); 1846 } 1847 1848 1849 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1850 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1851 BCE_EMAC_MDIO_COMM_START_BUSY; 1852 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1853 1854 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1855 DELAY(10); 1856 1857 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1858 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1859 DELAY(5); 1860 1861 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1862 val &= BCE_EMAC_MDIO_COMM_DATA; 1863 1864 break; 1865 } 1866 } 1867 1868 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1869 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1870 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1871 val = 0x0; 1872 } else { 1873 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1874 } 1875 1876 1877 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1878 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1879 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1880 1881 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1882 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1883 1884 DELAY(40); 1885 } 1886 1887 DB_PRINT_PHY_REG(reg, val); 1888 return (val & 0xffff); 1889 1890 } 1891 1892 1893 /****************************************************************************/ 1894 /* PHY register write. */ 1895 /* */ 1896 /* Implements register writes on the MII bus. */ 1897 /* */ 1898 /* Returns: */ 1899 /* The value of the register. */ 1900 /****************************************************************************/ 1901 static int 1902 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1903 { 1904 struct bce_softc *sc; 1905 u32 val1; 1906 int i; 1907 1908 sc = device_get_softc(dev); 1909 1910 /* Make sure we are accessing the correct PHY address. */ 1911 if (phy != sc->bce_phy_addr) { 1912 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1913 "for PHY write!\n", phy); 1914 return(0); 1915 } 1916 1917 DB_PRINT_PHY_REG(reg, val); 1918 1919 /* 1920 * The 5709S PHY is an IEEE Clause 45 PHY 1921 * with special mappings to work with IEEE 1922 * Clause 22 register accesses. 1923 */ 1924 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1925 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1926 reg += 0x10; 1927 } 1928 1929 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1930 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1931 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1932 1933 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1934 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1935 1936 DELAY(40); 1937 } 1938 1939 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1940 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1941 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1942 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1943 1944 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1945 DELAY(10); 1946 1947 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1948 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1949 DELAY(5); 1950 break; 1951 } 1952 } 1953 1954 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1955 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1956 __FILE__, __LINE__); 1957 1958 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1959 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1960 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1961 1962 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1963 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1964 1965 DELAY(40); 1966 } 1967 1968 return 0; 1969 } 1970 1971 1972 /****************************************************************************/ 1973 /* MII bus status change. */ 1974 /* */ 1975 /* Called by the MII bus driver when the PHY establishes link to set the */ 1976 /* MAC interface registers. */ 1977 /* */ 1978 /* Returns: */ 1979 /* Nothing. */ 1980 /****************************************************************************/ 1981 static void 1982 bce_miibus_statchg(device_t dev) 1983 { 1984 struct bce_softc *sc; 1985 struct mii_data *mii; 1986 int val; 1987 1988 sc = device_get_softc(dev); 1989 1990 DBENTER(BCE_VERBOSE_PHY); 1991 1992 mii = device_get_softc(sc->bce_miibus); 1993 1994 val = REG_RD(sc, BCE_EMAC_MODE); 1995 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1996 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1997 BCE_EMAC_MODE_25G); 1998 1999 /* Set MII or GMII interface based on the PHY speed. */ 2000 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2001 case IFM_10_T: 2002 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2003 DBPRINT(sc, BCE_INFO_PHY, 2004 "Enabling 10Mb interface.\n"); 2005 val |= BCE_EMAC_MODE_PORT_MII_10; 2006 break; 2007 } 2008 /* fall-through */ 2009 case IFM_100_TX: 2010 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2011 val |= BCE_EMAC_MODE_PORT_MII; 2012 break; 2013 case IFM_2500_SX: 2014 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2015 val |= BCE_EMAC_MODE_25G; 2016 /* fall-through */ 2017 case IFM_1000_T: 2018 case IFM_1000_SX: 2019 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2020 val |= BCE_EMAC_MODE_PORT_GMII; 2021 break; 2022 default: 2023 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2024 "default GMII interface.\n"); 2025 val |= BCE_EMAC_MODE_PORT_GMII; 2026 } 2027 2028 /* Set half or full duplex based on PHY settings. */ 2029 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 2030 DBPRINT(sc, BCE_INFO_PHY, 2031 "Setting Half-Duplex interface.\n"); 2032 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2033 } else 2034 DBPRINT(sc, BCE_INFO_PHY, 2035 "Setting Full-Duplex interface.\n"); 2036 2037 REG_WR(sc, BCE_EMAC_MODE, val); 2038 2039 if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) { 2040 DBPRINT(sc, BCE_INFO_PHY, 2041 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2042 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2043 } else { 2044 DBPRINT(sc, BCE_INFO_PHY, 2045 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2046 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2047 } 2048 2049 if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) { 2050 DBPRINT(sc, BCE_INFO_PHY, 2051 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2052 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2053 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2054 } else { 2055 DBPRINT(sc, BCE_INFO_PHY, 2056 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2057 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2058 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2059 } 2060 2061 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2062 2063 DBEXIT(BCE_VERBOSE_PHY); 2064 } 2065 2066 2067 /****************************************************************************/ 2068 /* Acquire NVRAM lock. */ 2069 /* */ 2070 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2071 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2072 /* for use by the driver. */ 2073 /* */ 2074 /* Returns: */ 2075 /* 0 on success, positive value on failure. */ 2076 /****************************************************************************/ 2077 static int 2078 bce_acquire_nvram_lock(struct bce_softc *sc) 2079 { 2080 u32 val; 2081 int j, rc = 0; 2082 2083 DBENTER(BCE_VERBOSE_NVRAM); 2084 2085 /* Request access to the flash interface. */ 2086 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2087 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2088 val = REG_RD(sc, BCE_NVM_SW_ARB); 2089 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2090 break; 2091 2092 DELAY(5); 2093 } 2094 2095 if (j >= NVRAM_TIMEOUT_COUNT) { 2096 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2097 rc = EBUSY; 2098 } 2099 2100 DBEXIT(BCE_VERBOSE_NVRAM); 2101 return (rc); 2102 } 2103 2104 2105 /****************************************************************************/ 2106 /* Release NVRAM lock. */ 2107 /* */ 2108 /* When the caller is finished accessing NVRAM the lock must be released. */ 2109 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2110 /* for use by the driver. */ 2111 /* */ 2112 /* Returns: */ 2113 /* 0 on success, positive value on failure. */ 2114 /****************************************************************************/ 2115 static int 2116 bce_release_nvram_lock(struct bce_softc *sc) 2117 { 2118 u32 val; 2119 int j, rc = 0; 2120 2121 DBENTER(BCE_VERBOSE_NVRAM); 2122 2123 /* 2124 * Relinquish nvram interface. 2125 */ 2126 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2127 2128 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2129 val = REG_RD(sc, BCE_NVM_SW_ARB); 2130 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2131 break; 2132 2133 DELAY(5); 2134 } 2135 2136 if (j >= NVRAM_TIMEOUT_COUNT) { 2137 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2138 rc = EBUSY; 2139 } 2140 2141 DBEXIT(BCE_VERBOSE_NVRAM); 2142 return (rc); 2143 } 2144 2145 2146 #ifdef BCE_NVRAM_WRITE_SUPPORT 2147 /****************************************************************************/ 2148 /* Enable NVRAM write access. */ 2149 /* */ 2150 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2151 /* */ 2152 /* Returns: */ 2153 /* 0 on success, positive value on failure. */ 2154 /****************************************************************************/ 2155 static int 2156 bce_enable_nvram_write(struct bce_softc *sc) 2157 { 2158 u32 val; 2159 int rc = 0; 2160 2161 DBENTER(BCE_VERBOSE_NVRAM); 2162 2163 val = REG_RD(sc, BCE_MISC_CFG); 2164 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2165 2166 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2167 int j; 2168 2169 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2170 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2171 2172 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2173 DELAY(5); 2174 2175 val = REG_RD(sc, BCE_NVM_COMMAND); 2176 if (val & BCE_NVM_COMMAND_DONE) 2177 break; 2178 } 2179 2180 if (j >= NVRAM_TIMEOUT_COUNT) { 2181 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2182 rc = EBUSY; 2183 } 2184 } 2185 2186 DBENTER(BCE_VERBOSE_NVRAM); 2187 return (rc); 2188 } 2189 2190 2191 /****************************************************************************/ 2192 /* Disable NVRAM write access. */ 2193 /* */ 2194 /* When the caller is finished writing to NVRAM write access must be */ 2195 /* disabled. */ 2196 /* */ 2197 /* Returns: */ 2198 /* Nothing. */ 2199 /****************************************************************************/ 2200 static void 2201 bce_disable_nvram_write(struct bce_softc *sc) 2202 { 2203 u32 val; 2204 2205 DBENTER(BCE_VERBOSE_NVRAM); 2206 2207 val = REG_RD(sc, BCE_MISC_CFG); 2208 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2209 2210 DBEXIT(BCE_VERBOSE_NVRAM); 2211 2212 } 2213 #endif 2214 2215 2216 /****************************************************************************/ 2217 /* Enable NVRAM access. */ 2218 /* */ 2219 /* Before accessing NVRAM for read or write operations the caller must */ 2220 /* enabled NVRAM access. */ 2221 /* */ 2222 /* Returns: */ 2223 /* Nothing. */ 2224 /****************************************************************************/ 2225 static void 2226 bce_enable_nvram_access(struct bce_softc *sc) 2227 { 2228 u32 val; 2229 2230 DBENTER(BCE_VERBOSE_NVRAM); 2231 2232 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2233 /* Enable both bits, even on read. */ 2234 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2235 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2236 2237 DBEXIT(BCE_VERBOSE_NVRAM); 2238 } 2239 2240 2241 /****************************************************************************/ 2242 /* Disable NVRAM access. */ 2243 /* */ 2244 /* When the caller is finished accessing NVRAM access must be disabled. */ 2245 /* */ 2246 /* Returns: */ 2247 /* Nothing. */ 2248 /****************************************************************************/ 2249 static void 2250 bce_disable_nvram_access(struct bce_softc *sc) 2251 { 2252 u32 val; 2253 2254 DBENTER(BCE_VERBOSE_NVRAM); 2255 2256 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2257 2258 /* Disable both bits, even after read. */ 2259 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2260 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2261 2262 DBEXIT(BCE_VERBOSE_NVRAM); 2263 } 2264 2265 2266 #ifdef BCE_NVRAM_WRITE_SUPPORT 2267 /****************************************************************************/ 2268 /* Erase NVRAM page before writing. */ 2269 /* */ 2270 /* Non-buffered flash parts require that a page be erased before it is */ 2271 /* written. */ 2272 /* */ 2273 /* Returns: */ 2274 /* 0 on success, positive value on failure. */ 2275 /****************************************************************************/ 2276 static int 2277 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2278 { 2279 u32 cmd; 2280 int j, rc = 0; 2281 2282 DBENTER(BCE_VERBOSE_NVRAM); 2283 2284 /* Buffered flash doesn't require an erase. */ 2285 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2286 goto bce_nvram_erase_page_exit; 2287 2288 /* Build an erase command. */ 2289 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2290 BCE_NVM_COMMAND_DOIT; 2291 2292 /* 2293 * Clear the DONE bit separately, set the NVRAM adress to erase, 2294 * and issue the erase command. 2295 */ 2296 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2297 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2298 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2299 2300 /* Wait for completion. */ 2301 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2302 u32 val; 2303 2304 DELAY(5); 2305 2306 val = REG_RD(sc, BCE_NVM_COMMAND); 2307 if (val & BCE_NVM_COMMAND_DONE) 2308 break; 2309 } 2310 2311 if (j >= NVRAM_TIMEOUT_COUNT) { 2312 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2313 rc = EBUSY; 2314 } 2315 2316 bce_nvram_erase_page_exit: 2317 DBEXIT(BCE_VERBOSE_NVRAM); 2318 return (rc); 2319 } 2320 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2321 2322 2323 /****************************************************************************/ 2324 /* Read a dword (32 bits) from NVRAM. */ 2325 /* */ 2326 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2327 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2328 /* */ 2329 /* Returns: */ 2330 /* 0 on success and the 32 bit value read, positive value on failure. */ 2331 /****************************************************************************/ 2332 static int 2333 bce_nvram_read_dword(struct bce_softc *sc, 2334 u32 offset, u8 *ret_val, u32 cmd_flags) 2335 { 2336 u32 cmd; 2337 int i, rc = 0; 2338 2339 DBENTER(BCE_EXTREME_NVRAM); 2340 2341 /* Build the command word. */ 2342 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2343 2344 /* Calculate the offset for buffered flash if translation is used. */ 2345 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2346 offset = ((offset / sc->bce_flash_info->page_size) << 2347 sc->bce_flash_info->page_bits) + 2348 (offset % sc->bce_flash_info->page_size); 2349 } 2350 2351 /* 2352 * Clear the DONE bit separately, set the address to read, 2353 * and issue the read. 2354 */ 2355 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2356 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2357 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2358 2359 /* Wait for completion. */ 2360 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2361 u32 val; 2362 2363 DELAY(5); 2364 2365 val = REG_RD(sc, BCE_NVM_COMMAND); 2366 if (val & BCE_NVM_COMMAND_DONE) { 2367 val = REG_RD(sc, BCE_NVM_READ); 2368 2369 val = bce_be32toh(val); 2370 memcpy(ret_val, &val, 4); 2371 break; 2372 } 2373 } 2374 2375 /* Check for errors. */ 2376 if (i >= NVRAM_TIMEOUT_COUNT) { 2377 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2378 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2379 rc = EBUSY; 2380 } 2381 2382 DBEXIT(BCE_EXTREME_NVRAM); 2383 return(rc); 2384 } 2385 2386 2387 #ifdef BCE_NVRAM_WRITE_SUPPORT 2388 /****************************************************************************/ 2389 /* Write a dword (32 bits) to NVRAM. */ 2390 /* */ 2391 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2392 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2393 /* enabled NVRAM write access. */ 2394 /* */ 2395 /* Returns: */ 2396 /* 0 on success, positive value on failure. */ 2397 /****************************************************************************/ 2398 static int 2399 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2400 u32 cmd_flags) 2401 { 2402 u32 cmd, val32; 2403 int j, rc = 0; 2404 2405 DBENTER(BCE_VERBOSE_NVRAM); 2406 2407 /* Build the command word. */ 2408 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2409 2410 /* Calculate the offset for buffered flash if translation is used. */ 2411 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2412 offset = ((offset / sc->bce_flash_info->page_size) << 2413 sc->bce_flash_info->page_bits) + 2414 (offset % sc->bce_flash_info->page_size); 2415 } 2416 2417 /* 2418 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2419 * set the NVRAM address to write, and issue the write command 2420 */ 2421 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2422 memcpy(&val32, val, 4); 2423 val32 = htobe32(val32); 2424 REG_WR(sc, BCE_NVM_WRITE, val32); 2425 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2426 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2427 2428 /* Wait for completion. */ 2429 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2430 DELAY(5); 2431 2432 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2433 break; 2434 } 2435 if (j >= NVRAM_TIMEOUT_COUNT) { 2436 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2437 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2438 rc = EBUSY; 2439 } 2440 2441 DBEXIT(BCE_VERBOSE_NVRAM); 2442 return (rc); 2443 } 2444 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2445 2446 2447 /****************************************************************************/ 2448 /* Initialize NVRAM access. */ 2449 /* */ 2450 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2451 /* access that device. */ 2452 /* */ 2453 /* Returns: */ 2454 /* 0 on success, positive value on failure. */ 2455 /****************************************************************************/ 2456 static int 2457 bce_init_nvram(struct bce_softc *sc) 2458 { 2459 u32 val; 2460 int j, entry_count, rc = 0; 2461 struct flash_spec *flash; 2462 2463 DBENTER(BCE_VERBOSE_NVRAM); 2464 2465 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2466 sc->bce_flash_info = &flash_5709; 2467 goto bce_init_nvram_get_flash_size; 2468 } 2469 2470 /* Determine the selected interface. */ 2471 val = REG_RD(sc, BCE_NVM_CFG1); 2472 2473 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2474 2475 /* 2476 * Flash reconfiguration is required to support additional 2477 * NVRAM devices not directly supported in hardware. 2478 * Check if the flash interface was reconfigured 2479 * by the bootcode. 2480 */ 2481 2482 if (val & 0x40000000) { 2483 /* Flash interface reconfigured by bootcode. */ 2484 2485 DBPRINT(sc,BCE_INFO_LOAD, 2486 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2487 2488 for (j = 0, flash = &flash_table[0]; j < entry_count; 2489 j++, flash++) { 2490 if ((val & FLASH_BACKUP_STRAP_MASK) == 2491 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2492 sc->bce_flash_info = flash; 2493 break; 2494 } 2495 } 2496 } else { 2497 /* Flash interface not yet reconfigured. */ 2498 u32 mask; 2499 2500 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2501 __FUNCTION__); 2502 2503 if (val & (1 << 23)) 2504 mask = FLASH_BACKUP_STRAP_MASK; 2505 else 2506 mask = FLASH_STRAP_MASK; 2507 2508 /* Look for the matching NVRAM device configuration data. */ 2509 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2510 2511 /* Check if the device matches any of the known devices. */ 2512 if ((val & mask) == (flash->strapping & mask)) { 2513 /* Found a device match. */ 2514 sc->bce_flash_info = flash; 2515 2516 /* Request access to the flash interface. */ 2517 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2518 return rc; 2519 2520 /* Reconfigure the flash interface. */ 2521 bce_enable_nvram_access(sc); 2522 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2523 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2524 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2525 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2526 bce_disable_nvram_access(sc); 2527 bce_release_nvram_lock(sc); 2528 2529 break; 2530 } 2531 } 2532 } 2533 2534 /* Check if a matching device was found. */ 2535 if (j == entry_count) { 2536 sc->bce_flash_info = NULL; 2537 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2538 __FILE__, __LINE__); 2539 DBEXIT(BCE_VERBOSE_NVRAM); 2540 return (ENODEV); 2541 } 2542 2543 bce_init_nvram_get_flash_size: 2544 /* Write the flash config data to the shared memory interface. */ 2545 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2546 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2547 if (val) 2548 sc->bce_flash_size = val; 2549 else 2550 sc->bce_flash_size = sc->bce_flash_info->total_size; 2551 2552 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2553 __FUNCTION__, sc->bce_flash_info->name, 2554 sc->bce_flash_info->total_size); 2555 2556 DBEXIT(BCE_VERBOSE_NVRAM); 2557 return rc; 2558 } 2559 2560 2561 /****************************************************************************/ 2562 /* Read an arbitrary range of data from NVRAM. */ 2563 /* */ 2564 /* Prepares the NVRAM interface for access and reads the requested data */ 2565 /* into the supplied buffer. */ 2566 /* */ 2567 /* Returns: */ 2568 /* 0 on success and the data read, positive value on failure. */ 2569 /****************************************************************************/ 2570 static int 2571 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2572 int buf_size) 2573 { 2574 int rc = 0; 2575 u32 cmd_flags, offset32, len32, extra; 2576 2577 DBENTER(BCE_VERBOSE_NVRAM); 2578 2579 if (buf_size == 0) 2580 goto bce_nvram_read_exit; 2581 2582 /* Request access to the flash interface. */ 2583 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2584 goto bce_nvram_read_exit; 2585 2586 /* Enable access to flash interface */ 2587 bce_enable_nvram_access(sc); 2588 2589 len32 = buf_size; 2590 offset32 = offset; 2591 extra = 0; 2592 2593 cmd_flags = 0; 2594 2595 if (offset32 & 3) { 2596 u8 buf[4]; 2597 u32 pre_len; 2598 2599 offset32 &= ~3; 2600 pre_len = 4 - (offset & 3); 2601 2602 if (pre_len >= len32) { 2603 pre_len = len32; 2604 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2605 } 2606 else { 2607 cmd_flags = BCE_NVM_COMMAND_FIRST; 2608 } 2609 2610 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2611 2612 if (rc) 2613 return rc; 2614 2615 memcpy(ret_buf, buf + (offset & 3), pre_len); 2616 2617 offset32 += 4; 2618 ret_buf += pre_len; 2619 len32 -= pre_len; 2620 } 2621 2622 if (len32 & 3) { 2623 extra = 4 - (len32 & 3); 2624 len32 = (len32 + 4) & ~3; 2625 } 2626 2627 if (len32 == 4) { 2628 u8 buf[4]; 2629 2630 if (cmd_flags) 2631 cmd_flags = BCE_NVM_COMMAND_LAST; 2632 else 2633 cmd_flags = BCE_NVM_COMMAND_FIRST | 2634 BCE_NVM_COMMAND_LAST; 2635 2636 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2637 2638 memcpy(ret_buf, buf, 4 - extra); 2639 } 2640 else if (len32 > 0) { 2641 u8 buf[4]; 2642 2643 /* Read the first word. */ 2644 if (cmd_flags) 2645 cmd_flags = 0; 2646 else 2647 cmd_flags = BCE_NVM_COMMAND_FIRST; 2648 2649 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2650 2651 /* Advance to the next dword. */ 2652 offset32 += 4; 2653 ret_buf += 4; 2654 len32 -= 4; 2655 2656 while (len32 > 4 && rc == 0) { 2657 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2658 2659 /* Advance to the next dword. */ 2660 offset32 += 4; 2661 ret_buf += 4; 2662 len32 -= 4; 2663 } 2664 2665 if (rc) 2666 goto bce_nvram_read_locked_exit; 2667 2668 cmd_flags = BCE_NVM_COMMAND_LAST; 2669 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2670 2671 memcpy(ret_buf, buf, 4 - extra); 2672 } 2673 2674 bce_nvram_read_locked_exit: 2675 /* Disable access to flash interface and release the lock. */ 2676 bce_disable_nvram_access(sc); 2677 bce_release_nvram_lock(sc); 2678 2679 bce_nvram_read_exit: 2680 DBEXIT(BCE_VERBOSE_NVRAM); 2681 return rc; 2682 } 2683 2684 2685 #ifdef BCE_NVRAM_WRITE_SUPPORT 2686 /****************************************************************************/ 2687 /* Write an arbitrary range of data from NVRAM. */ 2688 /* */ 2689 /* Prepares the NVRAM interface for write access and writes the requested */ 2690 /* data from the supplied buffer. The caller is responsible for */ 2691 /* calculating any appropriate CRCs. */ 2692 /* */ 2693 /* Returns: */ 2694 /* 0 on success, positive value on failure. */ 2695 /****************************************************************************/ 2696 static int 2697 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2698 int buf_size) 2699 { 2700 u32 written, offset32, len32; 2701 u8 *buf, start[4], end[4]; 2702 int rc = 0; 2703 int align_start, align_end; 2704 2705 DBENTER(BCE_VERBOSE_NVRAM); 2706 2707 buf = data_buf; 2708 offset32 = offset; 2709 len32 = buf_size; 2710 align_start = align_end = 0; 2711 2712 if ((align_start = (offset32 & 3))) { 2713 offset32 &= ~3; 2714 len32 += align_start; 2715 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2716 goto bce_nvram_write_exit; 2717 } 2718 2719 if (len32 & 3) { 2720 if ((len32 > 4) || !align_start) { 2721 align_end = 4 - (len32 & 3); 2722 len32 += align_end; 2723 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2724 end, 4))) { 2725 goto bce_nvram_write_exit; 2726 } 2727 } 2728 } 2729 2730 if (align_start || align_end) { 2731 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2732 if (buf == 0) { 2733 rc = ENOMEM; 2734 goto bce_nvram_write_exit; 2735 } 2736 2737 if (align_start) { 2738 memcpy(buf, start, 4); 2739 } 2740 2741 if (align_end) { 2742 memcpy(buf + len32 - 4, end, 4); 2743 } 2744 memcpy(buf + align_start, data_buf, buf_size); 2745 } 2746 2747 written = 0; 2748 while ((written < len32) && (rc == 0)) { 2749 u32 page_start, page_end, data_start, data_end; 2750 u32 addr, cmd_flags; 2751 int i; 2752 u8 flash_buffer[264]; 2753 2754 /* Find the page_start addr */ 2755 page_start = offset32 + written; 2756 page_start -= (page_start % sc->bce_flash_info->page_size); 2757 /* Find the page_end addr */ 2758 page_end = page_start + sc->bce_flash_info->page_size; 2759 /* Find the data_start addr */ 2760 data_start = (written == 0) ? offset32 : page_start; 2761 /* Find the data_end addr */ 2762 data_end = (page_end > offset32 + len32) ? 2763 (offset32 + len32) : page_end; 2764 2765 /* Request access to the flash interface. */ 2766 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2767 goto bce_nvram_write_exit; 2768 2769 /* Enable access to flash interface */ 2770 bce_enable_nvram_access(sc); 2771 2772 cmd_flags = BCE_NVM_COMMAND_FIRST; 2773 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2774 int j; 2775 2776 /* Read the whole page into the buffer 2777 * (non-buffer flash only) */ 2778 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2779 if (j == (sc->bce_flash_info->page_size - 4)) { 2780 cmd_flags |= BCE_NVM_COMMAND_LAST; 2781 } 2782 rc = bce_nvram_read_dword(sc, 2783 page_start + j, 2784 &flash_buffer[j], 2785 cmd_flags); 2786 2787 if (rc) 2788 goto bce_nvram_write_locked_exit; 2789 2790 cmd_flags = 0; 2791 } 2792 } 2793 2794 /* Enable writes to flash interface (unlock write-protect) */ 2795 if ((rc = bce_enable_nvram_write(sc)) != 0) 2796 goto bce_nvram_write_locked_exit; 2797 2798 /* Erase the page */ 2799 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2800 goto bce_nvram_write_locked_exit; 2801 2802 /* Re-enable the write again for the actual write */ 2803 bce_enable_nvram_write(sc); 2804 2805 /* Loop to write back the buffer data from page_start to 2806 * data_start */ 2807 i = 0; 2808 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2809 for (addr = page_start; addr < data_start; 2810 addr += 4, i += 4) { 2811 2812 rc = bce_nvram_write_dword(sc, addr, 2813 &flash_buffer[i], cmd_flags); 2814 2815 if (rc != 0) 2816 goto bce_nvram_write_locked_exit; 2817 2818 cmd_flags = 0; 2819 } 2820 } 2821 2822 /* Loop to write the new data from data_start to data_end */ 2823 for (addr = data_start; addr < data_end; addr += 4, i++) { 2824 if ((addr == page_end - 4) || 2825 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2826 (addr == data_end - 4))) { 2827 2828 cmd_flags |= BCE_NVM_COMMAND_LAST; 2829 } 2830 rc = bce_nvram_write_dword(sc, addr, buf, 2831 cmd_flags); 2832 2833 if (rc != 0) 2834 goto bce_nvram_write_locked_exit; 2835 2836 cmd_flags = 0; 2837 buf += 4; 2838 } 2839 2840 /* Loop to write back the buffer data from data_end 2841 * to page_end */ 2842 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2843 for (addr = data_end; addr < page_end; 2844 addr += 4, i += 4) { 2845 2846 if (addr == page_end-4) { 2847 cmd_flags = BCE_NVM_COMMAND_LAST; 2848 } 2849 rc = bce_nvram_write_dword(sc, addr, 2850 &flash_buffer[i], cmd_flags); 2851 2852 if (rc != 0) 2853 goto bce_nvram_write_locked_exit; 2854 2855 cmd_flags = 0; 2856 } 2857 } 2858 2859 /* Disable writes to flash interface (lock write-protect) */ 2860 bce_disable_nvram_write(sc); 2861 2862 /* Disable access to flash interface */ 2863 bce_disable_nvram_access(sc); 2864 bce_release_nvram_lock(sc); 2865 2866 /* Increment written */ 2867 written += data_end - data_start; 2868 } 2869 2870 goto bce_nvram_write_exit; 2871 2872 bce_nvram_write_locked_exit: 2873 bce_disable_nvram_write(sc); 2874 bce_disable_nvram_access(sc); 2875 bce_release_nvram_lock(sc); 2876 2877 bce_nvram_write_exit: 2878 if (align_start || align_end) 2879 free(buf, M_DEVBUF); 2880 2881 DBEXIT(BCE_VERBOSE_NVRAM); 2882 return (rc); 2883 } 2884 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2885 2886 2887 /****************************************************************************/ 2888 /* Verifies that NVRAM is accessible and contains valid data. */ 2889 /* */ 2890 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2891 /* correct. */ 2892 /* */ 2893 /* Returns: */ 2894 /* 0 on success, positive value on failure. */ 2895 /****************************************************************************/ 2896 static int 2897 bce_nvram_test(struct bce_softc *sc) 2898 { 2899 u32 buf[BCE_NVRAM_SIZE / 4]; 2900 u8 *data = (u8 *) buf; 2901 int rc = 0; 2902 u32 magic, csum; 2903 2904 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2905 2906 /* 2907 * Check that the device NVRAM is valid by reading 2908 * the magic value at offset 0. 2909 */ 2910 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2911 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2912 __FILE__, __LINE__); 2913 goto bce_nvram_test_exit; 2914 } 2915 2916 /* 2917 * Verify that offset 0 of the NVRAM contains 2918 * a valid magic number. 2919 */ 2920 magic = bce_be32toh(buf[0]); 2921 if (magic != BCE_NVRAM_MAGIC) { 2922 rc = ENODEV; 2923 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2924 "Expected: 0x%08X, Found: 0x%08X\n", 2925 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2926 goto bce_nvram_test_exit; 2927 } 2928 2929 /* 2930 * Verify that the device NVRAM includes valid 2931 * configuration data. 2932 */ 2933 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2934 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2935 "Information from NVRAM!\n", __FILE__, __LINE__); 2936 goto bce_nvram_test_exit; 2937 } 2938 2939 csum = ether_crc32_le(data, 0x100); 2940 if (csum != BCE_CRC32_RESIDUAL) { 2941 rc = ENODEV; 2942 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2943 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2944 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2945 goto bce_nvram_test_exit; 2946 } 2947 2948 csum = ether_crc32_le(data + 0x100, 0x100); 2949 if (csum != BCE_CRC32_RESIDUAL) { 2950 rc = ENODEV; 2951 BCE_PRINTF("%s(%d): Invalid feature configuration " 2952 "information NVRAM CRC! Expected: 0x%08X, " 2953 "Found: 08%08X\n", __FILE__, __LINE__, 2954 BCE_CRC32_RESIDUAL, csum); 2955 } 2956 2957 bce_nvram_test_exit: 2958 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2959 return rc; 2960 } 2961 2962 2963 /****************************************************************************/ 2964 /* Calculates the size of the buffers to allocate based on the MTU. */ 2965 /* */ 2966 /* Returns: */ 2967 /* Nothing. */ 2968 /****************************************************************************/ 2969 static void 2970 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 2971 { 2972 DBENTER(BCE_VERBOSE_LOAD); 2973 2974 /* Use a single allocation type when header splitting enabled. */ 2975 if (bce_hdr_split == TRUE) { 2976 sc->rx_bd_mbuf_alloc_size = MHLEN; 2977 /* Make sure offset is 16 byte aligned for hardware. */ 2978 sc->rx_bd_mbuf_align_pad = 2979 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 2980 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 2981 sc->rx_bd_mbuf_align_pad; 2982 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 2983 } else { 2984 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2985 ETHER_CRC_LEN) > MCLBYTES) { 2986 /* Setup for jumbo RX buffer allocations. */ 2987 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 2988 sc->rx_bd_mbuf_align_pad = 2989 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 2990 sc->rx_bd_mbuf_data_len = 2991 sc->rx_bd_mbuf_alloc_size - 2992 sc->rx_bd_mbuf_align_pad; 2993 } else { 2994 /* Setup for standard RX buffer allocations. */ 2995 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 2996 sc->rx_bd_mbuf_align_pad = 2997 roundup2(MCLBYTES, 16) - MCLBYTES; 2998 sc->rx_bd_mbuf_data_len = 2999 sc->rx_bd_mbuf_alloc_size - 3000 sc->rx_bd_mbuf_align_pad; 3001 } 3002 } 3003 3004 // DBPRINT(sc, BCE_INFO_LOAD, 3005 DBPRINT(sc, BCE_WARN, 3006 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3007 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3008 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3009 sc->rx_bd_mbuf_align_pad); 3010 3011 DBEXIT(BCE_VERBOSE_LOAD); 3012 3013 } 3014 3015 /****************************************************************************/ 3016 /* Identifies the current media type of the controller and sets the PHY */ 3017 /* address. */ 3018 /* */ 3019 /* Returns: */ 3020 /* Nothing. */ 3021 /****************************************************************************/ 3022 static void 3023 bce_get_media(struct bce_softc *sc) 3024 { 3025 u32 val; 3026 3027 DBENTER(BCE_VERBOSE_PHY); 3028 3029 /* Assume PHY address for copper controllers. */ 3030 sc->bce_phy_addr = 1; 3031 3032 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3033 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3034 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3035 u32 strap; 3036 3037 /* 3038 * The BCM5709S is software configurable 3039 * for Copper or SerDes operation. 3040 */ 3041 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3042 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3043 "for copper.\n"); 3044 goto bce_get_media_exit; 3045 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3046 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3047 "for dual media.\n"); 3048 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3049 goto bce_get_media_exit; 3050 } 3051 3052 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3053 strap = (val & 3054 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3055 else 3056 strap = (val & 3057 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3058 3059 if (pci_get_function(sc->bce_dev) == 0) { 3060 switch (strap) { 3061 case 0x4: 3062 case 0x5: 3063 case 0x6: 3064 DBPRINT(sc, BCE_INFO_LOAD, 3065 "BCM5709 s/w configured for SerDes.\n"); 3066 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3067 break; 3068 default: 3069 DBPRINT(sc, BCE_INFO_LOAD, 3070 "BCM5709 s/w configured for Copper.\n"); 3071 break; 3072 } 3073 } else { 3074 switch (strap) { 3075 case 0x1: 3076 case 0x2: 3077 case 0x4: 3078 DBPRINT(sc, BCE_INFO_LOAD, 3079 "BCM5709 s/w configured for SerDes.\n"); 3080 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3081 break; 3082 default: 3083 DBPRINT(sc, BCE_INFO_LOAD, 3084 "BCM5709 s/w configured for Copper.\n"); 3085 break; 3086 } 3087 } 3088 3089 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3090 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3091 3092 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3093 3094 sc->bce_flags |= BCE_NO_WOL_FLAG; 3095 3096 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3097 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3098 3099 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3100 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3101 sc->bce_phy_addr = 2; 3102 3103 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3104 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3105 sc->bce_phy_flags |= 3106 BCE_PHY_2_5G_CAPABLE_FLAG; 3107 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3108 "capable adapter\n"); 3109 } 3110 } 3111 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3112 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3113 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3114 3115 bce_get_media_exit: 3116 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3117 "Using PHY address %d.\n", sc->bce_phy_addr); 3118 3119 DBEXIT(BCE_VERBOSE_PHY); 3120 } 3121 3122 3123 /****************************************************************************/ 3124 /* Performs PHY initialization required before MII drivers access the */ 3125 /* device. */ 3126 /* */ 3127 /* Returns: */ 3128 /* Nothing. */ 3129 /****************************************************************************/ 3130 static void 3131 bce_init_media(struct bce_softc *sc) 3132 { 3133 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 3134 /* 3135 * Configure 5709S/5716S PHYs to use traditional IEEE 3136 * Clause 22 method. Otherwise we have no way to attach 3137 * the PHY in mii(4) layer. PHY specific configuration 3138 * is done in mii layer. 3139 */ 3140 3141 /* Select auto-negotiation MMD of the PHY. */ 3142 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3143 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3144 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3145 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3146 3147 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3148 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3149 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3150 } 3151 } 3152 3153 3154 /****************************************************************************/ 3155 /* Free any DMA memory owned by the driver. */ 3156 /* */ 3157 /* Scans through each data structre that requires DMA memory and frees */ 3158 /* the memory if allocated. */ 3159 /* */ 3160 /* Returns: */ 3161 /* Nothing. */ 3162 /****************************************************************************/ 3163 static void 3164 bce_dma_free(struct bce_softc *sc) 3165 { 3166 int i; 3167 3168 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3169 3170 /* Free, unmap, and destroy the status block. */ 3171 if (sc->status_block != NULL) { 3172 bus_dmamem_free( 3173 sc->status_tag, 3174 sc->status_block, 3175 sc->status_map); 3176 sc->status_block = NULL; 3177 } 3178 3179 if (sc->status_map != NULL) { 3180 bus_dmamap_unload( 3181 sc->status_tag, 3182 sc->status_map); 3183 bus_dmamap_destroy(sc->status_tag, 3184 sc->status_map); 3185 sc->status_map = NULL; 3186 } 3187 3188 if (sc->status_tag != NULL) { 3189 bus_dma_tag_destroy(sc->status_tag); 3190 sc->status_tag = NULL; 3191 } 3192 3193 3194 /* Free, unmap, and destroy the statistics block. */ 3195 if (sc->stats_block != NULL) { 3196 bus_dmamem_free( 3197 sc->stats_tag, 3198 sc->stats_block, 3199 sc->stats_map); 3200 sc->stats_block = NULL; 3201 } 3202 3203 if (sc->stats_map != NULL) { 3204 bus_dmamap_unload( 3205 sc->stats_tag, 3206 sc->stats_map); 3207 bus_dmamap_destroy(sc->stats_tag, 3208 sc->stats_map); 3209 sc->stats_map = NULL; 3210 } 3211 3212 if (sc->stats_tag != NULL) { 3213 bus_dma_tag_destroy(sc->stats_tag); 3214 sc->stats_tag = NULL; 3215 } 3216 3217 3218 /* Free, unmap and destroy all context memory pages. */ 3219 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3220 for (i = 0; i < sc->ctx_pages; i++ ) { 3221 if (sc->ctx_block[i] != NULL) { 3222 bus_dmamem_free( 3223 sc->ctx_tag, 3224 sc->ctx_block[i], 3225 sc->ctx_map[i]); 3226 sc->ctx_block[i] = NULL; 3227 } 3228 3229 if (sc->ctx_map[i] != NULL) { 3230 bus_dmamap_unload( 3231 sc->ctx_tag, 3232 sc->ctx_map[i]); 3233 bus_dmamap_destroy( 3234 sc->ctx_tag, 3235 sc->ctx_map[i]); 3236 sc->ctx_map[i] = NULL; 3237 } 3238 } 3239 3240 /* Destroy the context memory tag. */ 3241 if (sc->ctx_tag != NULL) { 3242 bus_dma_tag_destroy(sc->ctx_tag); 3243 sc->ctx_tag = NULL; 3244 } 3245 } 3246 3247 3248 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3249 for (i = 0; i < sc->tx_pages; i++ ) { 3250 if (sc->tx_bd_chain[i] != NULL) { 3251 bus_dmamem_free( 3252 sc->tx_bd_chain_tag, 3253 sc->tx_bd_chain[i], 3254 sc->tx_bd_chain_map[i]); 3255 sc->tx_bd_chain[i] = NULL; 3256 } 3257 3258 if (sc->tx_bd_chain_map[i] != NULL) { 3259 bus_dmamap_unload( 3260 sc->tx_bd_chain_tag, 3261 sc->tx_bd_chain_map[i]); 3262 bus_dmamap_destroy( 3263 sc->tx_bd_chain_tag, 3264 sc->tx_bd_chain_map[i]); 3265 sc->tx_bd_chain_map[i] = NULL; 3266 } 3267 } 3268 3269 /* Destroy the TX buffer descriptor tag. */ 3270 if (sc->tx_bd_chain_tag != NULL) { 3271 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3272 sc->tx_bd_chain_tag = NULL; 3273 } 3274 3275 3276 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3277 for (i = 0; i < sc->rx_pages; i++ ) { 3278 if (sc->rx_bd_chain[i] != NULL) { 3279 bus_dmamem_free( 3280 sc->rx_bd_chain_tag, 3281 sc->rx_bd_chain[i], 3282 sc->rx_bd_chain_map[i]); 3283 sc->rx_bd_chain[i] = NULL; 3284 } 3285 3286 if (sc->rx_bd_chain_map[i] != NULL) { 3287 bus_dmamap_unload( 3288 sc->rx_bd_chain_tag, 3289 sc->rx_bd_chain_map[i]); 3290 bus_dmamap_destroy( 3291 sc->rx_bd_chain_tag, 3292 sc->rx_bd_chain_map[i]); 3293 sc->rx_bd_chain_map[i] = NULL; 3294 } 3295 } 3296 3297 /* Destroy the RX buffer descriptor tag. */ 3298 if (sc->rx_bd_chain_tag != NULL) { 3299 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3300 sc->rx_bd_chain_tag = NULL; 3301 } 3302 3303 3304 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3305 if (bce_hdr_split == TRUE) { 3306 for (i = 0; i < sc->pg_pages; i++ ) { 3307 if (sc->pg_bd_chain[i] != NULL) { 3308 bus_dmamem_free( 3309 sc->pg_bd_chain_tag, 3310 sc->pg_bd_chain[i], 3311 sc->pg_bd_chain_map[i]); 3312 sc->pg_bd_chain[i] = NULL; 3313 } 3314 3315 if (sc->pg_bd_chain_map[i] != NULL) { 3316 bus_dmamap_unload( 3317 sc->pg_bd_chain_tag, 3318 sc->pg_bd_chain_map[i]); 3319 bus_dmamap_destroy( 3320 sc->pg_bd_chain_tag, 3321 sc->pg_bd_chain_map[i]); 3322 sc->pg_bd_chain_map[i] = NULL; 3323 } 3324 } 3325 3326 /* Destroy the page buffer descriptor tag. */ 3327 if (sc->pg_bd_chain_tag != NULL) { 3328 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3329 sc->pg_bd_chain_tag = NULL; 3330 } 3331 } 3332 3333 3334 /* Unload and destroy the TX mbuf maps. */ 3335 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3336 if (sc->tx_mbuf_map[i] != NULL) { 3337 bus_dmamap_unload(sc->tx_mbuf_tag, 3338 sc->tx_mbuf_map[i]); 3339 bus_dmamap_destroy(sc->tx_mbuf_tag, 3340 sc->tx_mbuf_map[i]); 3341 sc->tx_mbuf_map[i] = NULL; 3342 } 3343 } 3344 3345 /* Destroy the TX mbuf tag. */ 3346 if (sc->tx_mbuf_tag != NULL) { 3347 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3348 sc->tx_mbuf_tag = NULL; 3349 } 3350 3351 /* Unload and destroy the RX mbuf maps. */ 3352 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3353 if (sc->rx_mbuf_map[i] != NULL) { 3354 bus_dmamap_unload(sc->rx_mbuf_tag, 3355 sc->rx_mbuf_map[i]); 3356 bus_dmamap_destroy(sc->rx_mbuf_tag, 3357 sc->rx_mbuf_map[i]); 3358 sc->rx_mbuf_map[i] = NULL; 3359 } 3360 } 3361 3362 /* Destroy the RX mbuf tag. */ 3363 if (sc->rx_mbuf_tag != NULL) { 3364 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3365 sc->rx_mbuf_tag = NULL; 3366 } 3367 3368 /* Unload and destroy the page mbuf maps. */ 3369 if (bce_hdr_split == TRUE) { 3370 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3371 if (sc->pg_mbuf_map[i] != NULL) { 3372 bus_dmamap_unload(sc->pg_mbuf_tag, 3373 sc->pg_mbuf_map[i]); 3374 bus_dmamap_destroy(sc->pg_mbuf_tag, 3375 sc->pg_mbuf_map[i]); 3376 sc->pg_mbuf_map[i] = NULL; 3377 } 3378 } 3379 3380 /* Destroy the page mbuf tag. */ 3381 if (sc->pg_mbuf_tag != NULL) { 3382 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3383 sc->pg_mbuf_tag = NULL; 3384 } 3385 } 3386 3387 /* Destroy the parent tag */ 3388 if (sc->parent_tag != NULL) { 3389 bus_dma_tag_destroy(sc->parent_tag); 3390 sc->parent_tag = NULL; 3391 } 3392 3393 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3394 } 3395 3396 3397 /****************************************************************************/ 3398 /* Get DMA memory from the OS. */ 3399 /* */ 3400 /* Validates that the OS has provided DMA buffers in response to a */ 3401 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3402 /* When the callback is used the OS will return 0 for the mapping function */ 3403 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3404 /* failures back to the caller. */ 3405 /* */ 3406 /* Returns: */ 3407 /* Nothing. */ 3408 /****************************************************************************/ 3409 static void 3410 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3411 { 3412 bus_addr_t *busaddr = arg; 3413 3414 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3415 __FUNCTION__, nseg)); 3416 /* Simulate a mapping failure. */ 3417 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3418 error = ENOMEM); 3419 3420 /* ToDo: How to increment debug sim_count variable here? */ 3421 3422 /* Check for an error and signal the caller that an error occurred. */ 3423 if (error) { 3424 *busaddr = 0; 3425 } else { 3426 *busaddr = segs->ds_addr; 3427 } 3428 3429 return; 3430 } 3431 3432 3433 /****************************************************************************/ 3434 /* Allocate any DMA memory needed by the driver. */ 3435 /* */ 3436 /* Allocates DMA memory needed for the various global structures needed by */ 3437 /* hardware. */ 3438 /* */ 3439 /* Memory alignment requirements: */ 3440 /* +-----------------+----------+----------+----------+----------+ */ 3441 /* | | 5706 | 5708 | 5709 | 5716 | */ 3442 /* +-----------------+----------+----------+----------+----------+ */ 3443 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3444 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3445 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3446 /* |PG Buffers | none | none | none | none | */ 3447 /* |TX Buffers | none | none | none | none | */ 3448 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3449 /* |Context Memory | | | | | */ 3450 /* +-----------------+----------+----------+----------+----------+ */ 3451 /* */ 3452 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3453 /* */ 3454 /* Returns: */ 3455 /* 0 for success, positive value for failure. */ 3456 /****************************************************************************/ 3457 static int 3458 bce_dma_alloc(device_t dev) 3459 { 3460 struct bce_softc *sc; 3461 int i, error, rc = 0; 3462 bus_size_t max_size, max_seg_size; 3463 int max_segments; 3464 3465 sc = device_get_softc(dev); 3466 3467 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3468 3469 /* 3470 * Allocate the parent bus DMA tag appropriate for PCI. 3471 */ 3472 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3473 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3474 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3475 &sc->parent_tag)) { 3476 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3477 __FILE__, __LINE__); 3478 rc = ENOMEM; 3479 goto bce_dma_alloc_exit; 3480 } 3481 3482 /* 3483 * Create a DMA tag for the status block, allocate and clear the 3484 * memory, map the memory into DMA space, and fetch the physical 3485 * address of the block. 3486 */ 3487 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3488 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3489 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3490 0, NULL, NULL, &sc->status_tag)) { 3491 BCE_PRINTF("%s(%d): Could not allocate status block " 3492 "DMA tag!\n", __FILE__, __LINE__); 3493 rc = ENOMEM; 3494 goto bce_dma_alloc_exit; 3495 } 3496 3497 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3498 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3499 &sc->status_map)) { 3500 BCE_PRINTF("%s(%d): Could not allocate status block " 3501 "DMA memory!\n", __FILE__, __LINE__); 3502 rc = ENOMEM; 3503 goto bce_dma_alloc_exit; 3504 } 3505 3506 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3507 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3508 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3509 3510 if (error) { 3511 BCE_PRINTF("%s(%d): Could not map status block " 3512 "DMA memory!\n", __FILE__, __LINE__); 3513 rc = ENOMEM; 3514 goto bce_dma_alloc_exit; 3515 } 3516 3517 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3518 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3519 3520 /* 3521 * Create a DMA tag for the statistics block, allocate and clear the 3522 * memory, map the memory into DMA space, and fetch the physical 3523 * address of the block. 3524 */ 3525 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3526 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3527 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3528 0, NULL, NULL, &sc->stats_tag)) { 3529 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3530 "DMA tag!\n", __FILE__, __LINE__); 3531 rc = ENOMEM; 3532 goto bce_dma_alloc_exit; 3533 } 3534 3535 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3536 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3537 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3538 "DMA memory!\n", __FILE__, __LINE__); 3539 rc = ENOMEM; 3540 goto bce_dma_alloc_exit; 3541 } 3542 3543 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3544 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3545 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3546 3547 if(error) { 3548 BCE_PRINTF("%s(%d): Could not map statistics block " 3549 "DMA memory!\n", __FILE__, __LINE__); 3550 rc = ENOMEM; 3551 goto bce_dma_alloc_exit; 3552 } 3553 3554 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3555 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3556 3557 /* BCM5709 uses host memory as cache for context memory. */ 3558 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3559 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3560 if (sc->ctx_pages == 0) 3561 sc->ctx_pages = 1; 3562 3563 DBRUNIF((sc->ctx_pages > 512), 3564 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3565 __FILE__, __LINE__, sc->ctx_pages)); 3566 3567 /* 3568 * Create a DMA tag for the context pages, 3569 * allocate and clear the memory, map the 3570 * memory into DMA space, and fetch the 3571 * physical address of the block. 3572 */ 3573 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3574 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3575 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3576 0, NULL, NULL, &sc->ctx_tag)) { 3577 BCE_PRINTF("%s(%d): Could not allocate CTX " 3578 "DMA tag!\n", __FILE__, __LINE__); 3579 rc = ENOMEM; 3580 goto bce_dma_alloc_exit; 3581 } 3582 3583 for (i = 0; i < sc->ctx_pages; i++) { 3584 3585 if(bus_dmamem_alloc(sc->ctx_tag, 3586 (void **)&sc->ctx_block[i], 3587 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3588 &sc->ctx_map[i])) { 3589 BCE_PRINTF("%s(%d): Could not allocate CTX " 3590 "DMA memory!\n", __FILE__, __LINE__); 3591 rc = ENOMEM; 3592 goto bce_dma_alloc_exit; 3593 } 3594 3595 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3596 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3597 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3598 3599 if (error) { 3600 BCE_PRINTF("%s(%d): Could not map CTX " 3601 "DMA memory!\n", __FILE__, __LINE__); 3602 rc = ENOMEM; 3603 goto bce_dma_alloc_exit; 3604 } 3605 3606 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3607 "= 0x%jX\n", __FUNCTION__, i, 3608 (uintmax_t) sc->ctx_paddr[i]); 3609 } 3610 } 3611 3612 /* 3613 * Create a DMA tag for the TX buffer descriptor chain, 3614 * allocate and clear the memory, and fetch the 3615 * physical address of the block. 3616 */ 3617 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3618 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3619 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3620 NULL, NULL, &sc->tx_bd_chain_tag)) { 3621 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3622 "chain DMA tag!\n", __FILE__, __LINE__); 3623 rc = ENOMEM; 3624 goto bce_dma_alloc_exit; 3625 } 3626 3627 for (i = 0; i < sc->tx_pages; i++) { 3628 3629 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3630 (void **)&sc->tx_bd_chain[i], 3631 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3632 &sc->tx_bd_chain_map[i])) { 3633 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3634 "chain DMA memory!\n", __FILE__, __LINE__); 3635 rc = ENOMEM; 3636 goto bce_dma_alloc_exit; 3637 } 3638 3639 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3640 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3641 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3642 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3643 3644 if (error) { 3645 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3646 "chain DMA memory!\n", __FILE__, __LINE__); 3647 rc = ENOMEM; 3648 goto bce_dma_alloc_exit; 3649 } 3650 3651 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3652 "0x%jX\n", __FUNCTION__, i, 3653 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3654 } 3655 3656 /* Check the required size before mapping to conserve resources. */ 3657 if (bce_tso_enable) { 3658 max_size = BCE_TSO_MAX_SIZE; 3659 max_segments = BCE_MAX_SEGMENTS; 3660 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3661 } else { 3662 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3663 max_segments = BCE_MAX_SEGMENTS; 3664 max_seg_size = MCLBYTES; 3665 } 3666 3667 /* Create a DMA tag for TX mbufs. */ 3668 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3669 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3670 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3671 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3672 __FILE__, __LINE__); 3673 rc = ENOMEM; 3674 goto bce_dma_alloc_exit; 3675 } 3676 3677 /* Create DMA maps for the TX mbufs clusters. */ 3678 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3679 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3680 &sc->tx_mbuf_map[i])) { 3681 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3682 "map!\n", __FILE__, __LINE__); 3683 rc = ENOMEM; 3684 goto bce_dma_alloc_exit; 3685 } 3686 } 3687 3688 /* 3689 * Create a DMA tag for the RX buffer descriptor chain, 3690 * allocate and clear the memory, and fetch the physical 3691 * address of the blocks. 3692 */ 3693 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3694 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3695 sc->max_bus_addr, NULL, NULL, 3696 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3697 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3698 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3699 "DMA tag!\n", __FILE__, __LINE__); 3700 rc = ENOMEM; 3701 goto bce_dma_alloc_exit; 3702 } 3703 3704 for (i = 0; i < sc->rx_pages; i++) { 3705 3706 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3707 (void **)&sc->rx_bd_chain[i], 3708 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3709 &sc->rx_bd_chain_map[i])) { 3710 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3711 "chain DMA memory!\n", __FILE__, __LINE__); 3712 rc = ENOMEM; 3713 goto bce_dma_alloc_exit; 3714 } 3715 3716 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3717 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3718 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3719 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3720 3721 if (error) { 3722 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3723 "chain DMA memory!\n", __FILE__, __LINE__); 3724 rc = ENOMEM; 3725 goto bce_dma_alloc_exit; 3726 } 3727 3728 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3729 "0x%jX\n", __FUNCTION__, i, 3730 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3731 } 3732 3733 /* 3734 * Create a DMA tag for RX mbufs. 3735 */ 3736 if (bce_hdr_split == TRUE) 3737 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3738 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3739 else 3740 max_size = max_seg_size = MJUM9BYTES; 3741 max_segments = 1; 3742 3743 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3744 "(max size = 0x%jX max segments = %d, max segment " 3745 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, 3746 max_segments, (uintmax_t) max_seg_size); 3747 3748 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3749 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3750 max_size, max_segments, max_seg_size, 0, NULL, NULL, 3751 &sc->rx_mbuf_tag)) { 3752 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3753 __FILE__, __LINE__); 3754 rc = ENOMEM; 3755 goto bce_dma_alloc_exit; 3756 } 3757 3758 /* Create DMA maps for the RX mbuf clusters. */ 3759 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3760 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3761 &sc->rx_mbuf_map[i])) { 3762 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3763 "DMA map!\n", __FILE__, __LINE__); 3764 rc = ENOMEM; 3765 goto bce_dma_alloc_exit; 3766 } 3767 } 3768 3769 if (bce_hdr_split == TRUE) { 3770 /* 3771 * Create a DMA tag for the page buffer descriptor chain, 3772 * allocate and clear the memory, and fetch the physical 3773 * address of the blocks. 3774 */ 3775 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3776 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3777 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3778 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3779 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3780 "chain DMA tag!\n", __FILE__, __LINE__); 3781 rc = ENOMEM; 3782 goto bce_dma_alloc_exit; 3783 } 3784 3785 for (i = 0; i < sc->pg_pages; i++) { 3786 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3787 (void **)&sc->pg_bd_chain[i], 3788 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3789 &sc->pg_bd_chain_map[i])) { 3790 BCE_PRINTF("%s(%d): Could not allocate page " 3791 "descriptor chain DMA memory!\n", 3792 __FILE__, __LINE__); 3793 rc = ENOMEM; 3794 goto bce_dma_alloc_exit; 3795 } 3796 3797 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3798 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3799 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3800 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3801 3802 if (error) { 3803 BCE_PRINTF("%s(%d): Could not map page descriptor " 3804 "chain DMA memory!\n", __FILE__, __LINE__); 3805 rc = ENOMEM; 3806 goto bce_dma_alloc_exit; 3807 } 3808 3809 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3810 "0x%jX\n", __FUNCTION__, i, 3811 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3812 } 3813 3814 /* 3815 * Create a DMA tag for page mbufs. 3816 */ 3817 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3818 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3819 3820 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3821 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3822 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3823 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3824 "DMA tag!\n", __FILE__, __LINE__); 3825 rc = ENOMEM; 3826 goto bce_dma_alloc_exit; 3827 } 3828 3829 /* Create DMA maps for the page mbuf clusters. */ 3830 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3831 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3832 &sc->pg_mbuf_map[i])) { 3833 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3834 "DMA map!\n", __FILE__, __LINE__); 3835 rc = ENOMEM; 3836 goto bce_dma_alloc_exit; 3837 } 3838 } 3839 } 3840 3841 bce_dma_alloc_exit: 3842 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3843 return(rc); 3844 } 3845 3846 3847 /****************************************************************************/ 3848 /* Release all resources used by the driver. */ 3849 /* */ 3850 /* Releases all resources acquired by the driver including interrupts, */ 3851 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3852 /* */ 3853 /* Returns: */ 3854 /* Nothing. */ 3855 /****************************************************************************/ 3856 static void 3857 bce_release_resources(struct bce_softc *sc) 3858 { 3859 device_t dev; 3860 3861 DBENTER(BCE_VERBOSE_RESET); 3862 3863 dev = sc->bce_dev; 3864 3865 bce_dma_free(sc); 3866 3867 if (sc->bce_intrhand != NULL) { 3868 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3869 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3870 } 3871 3872 if (sc->bce_res_irq != NULL) { 3873 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3874 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3875 sc->bce_res_irq); 3876 } 3877 3878 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3879 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3880 pci_release_msi(dev); 3881 } 3882 3883 if (sc->bce_res_mem != NULL) { 3884 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3885 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3886 sc->bce_res_mem); 3887 } 3888 3889 if (sc->bce_ifp != NULL) { 3890 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3891 if_free(sc->bce_ifp); 3892 } 3893 3894 if (mtx_initialized(&sc->bce_mtx)) 3895 BCE_LOCK_DESTROY(sc); 3896 3897 DBEXIT(BCE_VERBOSE_RESET); 3898 } 3899 3900 3901 /****************************************************************************/ 3902 /* Firmware synchronization. */ 3903 /* */ 3904 /* Before performing certain events such as a chip reset, synchronize with */ 3905 /* the firmware first. */ 3906 /* */ 3907 /* Returns: */ 3908 /* 0 for success, positive value for failure. */ 3909 /****************************************************************************/ 3910 static int 3911 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3912 { 3913 int i, rc = 0; 3914 u32 val; 3915 3916 DBENTER(BCE_VERBOSE_RESET); 3917 3918 /* Don't waste any time if we've timed out before. */ 3919 if (sc->bce_fw_timed_out == TRUE) { 3920 rc = EBUSY; 3921 goto bce_fw_sync_exit; 3922 } 3923 3924 /* Increment the message sequence number. */ 3925 sc->bce_fw_wr_seq++; 3926 msg_data |= sc->bce_fw_wr_seq; 3927 3928 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3929 "0x%08X\n", msg_data); 3930 3931 /* Send the message to the bootcode driver mailbox. */ 3932 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3933 3934 /* Wait for the bootcode to acknowledge the message. */ 3935 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3936 /* Check for a response in the bootcode firmware mailbox. */ 3937 val = bce_shmem_rd(sc, BCE_FW_MB); 3938 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3939 break; 3940 DELAY(1000); 3941 } 3942 3943 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3944 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3945 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3946 3947 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3948 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3949 3950 msg_data &= ~BCE_DRV_MSG_CODE; 3951 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3952 3953 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3954 3955 sc->bce_fw_timed_out = TRUE; 3956 rc = EBUSY; 3957 } 3958 3959 bce_fw_sync_exit: 3960 DBEXIT(BCE_VERBOSE_RESET); 3961 return (rc); 3962 } 3963 3964 3965 /****************************************************************************/ 3966 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3967 /* */ 3968 /* Returns: */ 3969 /* Nothing. */ 3970 /****************************************************************************/ 3971 static void 3972 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3973 u32 rv2p_code_len, u32 rv2p_proc) 3974 { 3975 int i; 3976 u32 val; 3977 3978 DBENTER(BCE_VERBOSE_RESET); 3979 3980 /* Set the page size used by RV2P. */ 3981 if (rv2p_proc == RV2P_PROC2) { 3982 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3983 } 3984 3985 for (i = 0; i < rv2p_code_len; i += 8) { 3986 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3987 rv2p_code++; 3988 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3989 rv2p_code++; 3990 3991 if (rv2p_proc == RV2P_PROC1) { 3992 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3993 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3994 } 3995 else { 3996 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 3997 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 3998 } 3999 } 4000 4001 /* Reset the processor, un-stall is done later. */ 4002 if (rv2p_proc == RV2P_PROC1) { 4003 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4004 } 4005 else { 4006 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4007 } 4008 4009 DBEXIT(BCE_VERBOSE_RESET); 4010 } 4011 4012 4013 /****************************************************************************/ 4014 /* Load RISC processor firmware. */ 4015 /* */ 4016 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4017 /* associated with a particular processor. */ 4018 /* */ 4019 /* Returns: */ 4020 /* Nothing. */ 4021 /****************************************************************************/ 4022 static void 4023 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4024 struct fw_info *fw) 4025 { 4026 u32 offset; 4027 4028 DBENTER(BCE_VERBOSE_RESET); 4029 4030 bce_halt_cpu(sc, cpu_reg); 4031 4032 /* Load the Text area. */ 4033 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4034 if (fw->text) { 4035 int j; 4036 4037 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4038 REG_WR_IND(sc, offset, fw->text[j]); 4039 } 4040 } 4041 4042 /* Load the Data area. */ 4043 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4044 if (fw->data) { 4045 int j; 4046 4047 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4048 REG_WR_IND(sc, offset, fw->data[j]); 4049 } 4050 } 4051 4052 /* Load the SBSS area. */ 4053 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4054 if (fw->sbss) { 4055 int j; 4056 4057 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4058 REG_WR_IND(sc, offset, fw->sbss[j]); 4059 } 4060 } 4061 4062 /* Load the BSS area. */ 4063 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4064 if (fw->bss) { 4065 int j; 4066 4067 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4068 REG_WR_IND(sc, offset, fw->bss[j]); 4069 } 4070 } 4071 4072 /* Load the Read-Only area. */ 4073 offset = cpu_reg->spad_base + 4074 (fw->rodata_addr - cpu_reg->mips_view_base); 4075 if (fw->rodata) { 4076 int j; 4077 4078 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4079 REG_WR_IND(sc, offset, fw->rodata[j]); 4080 } 4081 } 4082 4083 /* Clear the pre-fetch instruction and set the FW start address. */ 4084 REG_WR_IND(sc, cpu_reg->inst, 0); 4085 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4086 4087 DBEXIT(BCE_VERBOSE_RESET); 4088 } 4089 4090 4091 /****************************************************************************/ 4092 /* Starts the RISC processor. */ 4093 /* */ 4094 /* Assumes the CPU starting address has already been set. */ 4095 /* */ 4096 /* Returns: */ 4097 /* Nothing. */ 4098 /****************************************************************************/ 4099 static void 4100 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4101 { 4102 u32 val; 4103 4104 DBENTER(BCE_VERBOSE_RESET); 4105 4106 /* Start the CPU. */ 4107 val = REG_RD_IND(sc, cpu_reg->mode); 4108 val &= ~cpu_reg->mode_value_halt; 4109 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4110 REG_WR_IND(sc, cpu_reg->mode, val); 4111 4112 DBEXIT(BCE_VERBOSE_RESET); 4113 } 4114 4115 4116 /****************************************************************************/ 4117 /* Halts the RISC processor. */ 4118 /* */ 4119 /* Returns: */ 4120 /* Nothing. */ 4121 /****************************************************************************/ 4122 static void 4123 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4124 { 4125 u32 val; 4126 4127 DBENTER(BCE_VERBOSE_RESET); 4128 4129 /* Halt the CPU. */ 4130 val = REG_RD_IND(sc, cpu_reg->mode); 4131 val |= cpu_reg->mode_value_halt; 4132 REG_WR_IND(sc, cpu_reg->mode, val); 4133 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4134 4135 DBEXIT(BCE_VERBOSE_RESET); 4136 } 4137 4138 4139 /****************************************************************************/ 4140 /* Initialize the RX CPU. */ 4141 /* */ 4142 /* Returns: */ 4143 /* Nothing. */ 4144 /****************************************************************************/ 4145 static void 4146 bce_start_rxp_cpu(struct bce_softc *sc) 4147 { 4148 struct cpu_reg cpu_reg; 4149 4150 DBENTER(BCE_VERBOSE_RESET); 4151 4152 cpu_reg.mode = BCE_RXP_CPU_MODE; 4153 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4154 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4155 cpu_reg.state = BCE_RXP_CPU_STATE; 4156 cpu_reg.state_value_clear = 0xffffff; 4157 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4158 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4159 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4160 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4161 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4162 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4163 cpu_reg.mips_view_base = 0x8000000; 4164 4165 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4166 bce_start_cpu(sc, &cpu_reg); 4167 4168 DBEXIT(BCE_VERBOSE_RESET); 4169 } 4170 4171 4172 /****************************************************************************/ 4173 /* Initialize the RX CPU. */ 4174 /* */ 4175 /* Returns: */ 4176 /* Nothing. */ 4177 /****************************************************************************/ 4178 static void 4179 bce_init_rxp_cpu(struct bce_softc *sc) 4180 { 4181 struct cpu_reg cpu_reg; 4182 struct fw_info fw; 4183 4184 DBENTER(BCE_VERBOSE_RESET); 4185 4186 cpu_reg.mode = BCE_RXP_CPU_MODE; 4187 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4188 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4189 cpu_reg.state = BCE_RXP_CPU_STATE; 4190 cpu_reg.state_value_clear = 0xffffff; 4191 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4192 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4193 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4194 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4195 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4196 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4197 cpu_reg.mips_view_base = 0x8000000; 4198 4199 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4200 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4201 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4202 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4203 fw.start_addr = bce_RXP_b09FwStartAddr; 4204 4205 fw.text_addr = bce_RXP_b09FwTextAddr; 4206 fw.text_len = bce_RXP_b09FwTextLen; 4207 fw.text_index = 0; 4208 fw.text = bce_RXP_b09FwText; 4209 4210 fw.data_addr = bce_RXP_b09FwDataAddr; 4211 fw.data_len = bce_RXP_b09FwDataLen; 4212 fw.data_index = 0; 4213 fw.data = bce_RXP_b09FwData; 4214 4215 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4216 fw.sbss_len = bce_RXP_b09FwSbssLen; 4217 fw.sbss_index = 0; 4218 fw.sbss = bce_RXP_b09FwSbss; 4219 4220 fw.bss_addr = bce_RXP_b09FwBssAddr; 4221 fw.bss_len = bce_RXP_b09FwBssLen; 4222 fw.bss_index = 0; 4223 fw.bss = bce_RXP_b09FwBss; 4224 4225 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4226 fw.rodata_len = bce_RXP_b09FwRodataLen; 4227 fw.rodata_index = 0; 4228 fw.rodata = bce_RXP_b09FwRodata; 4229 } else { 4230 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4231 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4232 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4233 fw.start_addr = bce_RXP_b06FwStartAddr; 4234 4235 fw.text_addr = bce_RXP_b06FwTextAddr; 4236 fw.text_len = bce_RXP_b06FwTextLen; 4237 fw.text_index = 0; 4238 fw.text = bce_RXP_b06FwText; 4239 4240 fw.data_addr = bce_RXP_b06FwDataAddr; 4241 fw.data_len = bce_RXP_b06FwDataLen; 4242 fw.data_index = 0; 4243 fw.data = bce_RXP_b06FwData; 4244 4245 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4246 fw.sbss_len = bce_RXP_b06FwSbssLen; 4247 fw.sbss_index = 0; 4248 fw.sbss = bce_RXP_b06FwSbss; 4249 4250 fw.bss_addr = bce_RXP_b06FwBssAddr; 4251 fw.bss_len = bce_RXP_b06FwBssLen; 4252 fw.bss_index = 0; 4253 fw.bss = bce_RXP_b06FwBss; 4254 4255 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4256 fw.rodata_len = bce_RXP_b06FwRodataLen; 4257 fw.rodata_index = 0; 4258 fw.rodata = bce_RXP_b06FwRodata; 4259 } 4260 4261 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4262 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4263 4264 /* Delay RXP start until initialization is complete. */ 4265 4266 DBEXIT(BCE_VERBOSE_RESET); 4267 } 4268 4269 4270 /****************************************************************************/ 4271 /* Initialize the TX CPU. */ 4272 /* */ 4273 /* Returns: */ 4274 /* Nothing. */ 4275 /****************************************************************************/ 4276 static void 4277 bce_init_txp_cpu(struct bce_softc *sc) 4278 { 4279 struct cpu_reg cpu_reg; 4280 struct fw_info fw; 4281 4282 DBENTER(BCE_VERBOSE_RESET); 4283 4284 cpu_reg.mode = BCE_TXP_CPU_MODE; 4285 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4286 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4287 cpu_reg.state = BCE_TXP_CPU_STATE; 4288 cpu_reg.state_value_clear = 0xffffff; 4289 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4290 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4291 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4292 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4293 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4294 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4295 cpu_reg.mips_view_base = 0x8000000; 4296 4297 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4298 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4299 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4300 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4301 fw.start_addr = bce_TXP_b09FwStartAddr; 4302 4303 fw.text_addr = bce_TXP_b09FwTextAddr; 4304 fw.text_len = bce_TXP_b09FwTextLen; 4305 fw.text_index = 0; 4306 fw.text = bce_TXP_b09FwText; 4307 4308 fw.data_addr = bce_TXP_b09FwDataAddr; 4309 fw.data_len = bce_TXP_b09FwDataLen; 4310 fw.data_index = 0; 4311 fw.data = bce_TXP_b09FwData; 4312 4313 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4314 fw.sbss_len = bce_TXP_b09FwSbssLen; 4315 fw.sbss_index = 0; 4316 fw.sbss = bce_TXP_b09FwSbss; 4317 4318 fw.bss_addr = bce_TXP_b09FwBssAddr; 4319 fw.bss_len = bce_TXP_b09FwBssLen; 4320 fw.bss_index = 0; 4321 fw.bss = bce_TXP_b09FwBss; 4322 4323 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4324 fw.rodata_len = bce_TXP_b09FwRodataLen; 4325 fw.rodata_index = 0; 4326 fw.rodata = bce_TXP_b09FwRodata; 4327 } else { 4328 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4329 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4330 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4331 fw.start_addr = bce_TXP_b06FwStartAddr; 4332 4333 fw.text_addr = bce_TXP_b06FwTextAddr; 4334 fw.text_len = bce_TXP_b06FwTextLen; 4335 fw.text_index = 0; 4336 fw.text = bce_TXP_b06FwText; 4337 4338 fw.data_addr = bce_TXP_b06FwDataAddr; 4339 fw.data_len = bce_TXP_b06FwDataLen; 4340 fw.data_index = 0; 4341 fw.data = bce_TXP_b06FwData; 4342 4343 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4344 fw.sbss_len = bce_TXP_b06FwSbssLen; 4345 fw.sbss_index = 0; 4346 fw.sbss = bce_TXP_b06FwSbss; 4347 4348 fw.bss_addr = bce_TXP_b06FwBssAddr; 4349 fw.bss_len = bce_TXP_b06FwBssLen; 4350 fw.bss_index = 0; 4351 fw.bss = bce_TXP_b06FwBss; 4352 4353 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4354 fw.rodata_len = bce_TXP_b06FwRodataLen; 4355 fw.rodata_index = 0; 4356 fw.rodata = bce_TXP_b06FwRodata; 4357 } 4358 4359 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4360 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4361 bce_start_cpu(sc, &cpu_reg); 4362 4363 DBEXIT(BCE_VERBOSE_RESET); 4364 } 4365 4366 4367 /****************************************************************************/ 4368 /* Initialize the TPAT CPU. */ 4369 /* */ 4370 /* Returns: */ 4371 /* Nothing. */ 4372 /****************************************************************************/ 4373 static void 4374 bce_init_tpat_cpu(struct bce_softc *sc) 4375 { 4376 struct cpu_reg cpu_reg; 4377 struct fw_info fw; 4378 4379 DBENTER(BCE_VERBOSE_RESET); 4380 4381 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4382 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4383 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4384 cpu_reg.state = BCE_TPAT_CPU_STATE; 4385 cpu_reg.state_value_clear = 0xffffff; 4386 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4387 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4388 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4389 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4390 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4391 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4392 cpu_reg.mips_view_base = 0x8000000; 4393 4394 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4395 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4396 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4397 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4398 fw.start_addr = bce_TPAT_b09FwStartAddr; 4399 4400 fw.text_addr = bce_TPAT_b09FwTextAddr; 4401 fw.text_len = bce_TPAT_b09FwTextLen; 4402 fw.text_index = 0; 4403 fw.text = bce_TPAT_b09FwText; 4404 4405 fw.data_addr = bce_TPAT_b09FwDataAddr; 4406 fw.data_len = bce_TPAT_b09FwDataLen; 4407 fw.data_index = 0; 4408 fw.data = bce_TPAT_b09FwData; 4409 4410 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4411 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4412 fw.sbss_index = 0; 4413 fw.sbss = bce_TPAT_b09FwSbss; 4414 4415 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4416 fw.bss_len = bce_TPAT_b09FwBssLen; 4417 fw.bss_index = 0; 4418 fw.bss = bce_TPAT_b09FwBss; 4419 4420 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4421 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4422 fw.rodata_index = 0; 4423 fw.rodata = bce_TPAT_b09FwRodata; 4424 } else { 4425 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4426 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4427 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4428 fw.start_addr = bce_TPAT_b06FwStartAddr; 4429 4430 fw.text_addr = bce_TPAT_b06FwTextAddr; 4431 fw.text_len = bce_TPAT_b06FwTextLen; 4432 fw.text_index = 0; 4433 fw.text = bce_TPAT_b06FwText; 4434 4435 fw.data_addr = bce_TPAT_b06FwDataAddr; 4436 fw.data_len = bce_TPAT_b06FwDataLen; 4437 fw.data_index = 0; 4438 fw.data = bce_TPAT_b06FwData; 4439 4440 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4441 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4442 fw.sbss_index = 0; 4443 fw.sbss = bce_TPAT_b06FwSbss; 4444 4445 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4446 fw.bss_len = bce_TPAT_b06FwBssLen; 4447 fw.bss_index = 0; 4448 fw.bss = bce_TPAT_b06FwBss; 4449 4450 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4451 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4452 fw.rodata_index = 0; 4453 fw.rodata = bce_TPAT_b06FwRodata; 4454 } 4455 4456 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4457 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4458 bce_start_cpu(sc, &cpu_reg); 4459 4460 DBEXIT(BCE_VERBOSE_RESET); 4461 } 4462 4463 4464 /****************************************************************************/ 4465 /* Initialize the CP CPU. */ 4466 /* */ 4467 /* Returns: */ 4468 /* Nothing. */ 4469 /****************************************************************************/ 4470 static void 4471 bce_init_cp_cpu(struct bce_softc *sc) 4472 { 4473 struct cpu_reg cpu_reg; 4474 struct fw_info fw; 4475 4476 DBENTER(BCE_VERBOSE_RESET); 4477 4478 cpu_reg.mode = BCE_CP_CPU_MODE; 4479 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4480 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4481 cpu_reg.state = BCE_CP_CPU_STATE; 4482 cpu_reg.state_value_clear = 0xffffff; 4483 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4484 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4485 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4486 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4487 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4488 cpu_reg.spad_base = BCE_CP_SCRATCH; 4489 cpu_reg.mips_view_base = 0x8000000; 4490 4491 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4492 fw.ver_major = bce_CP_b09FwReleaseMajor; 4493 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4494 fw.ver_fix = bce_CP_b09FwReleaseFix; 4495 fw.start_addr = bce_CP_b09FwStartAddr; 4496 4497 fw.text_addr = bce_CP_b09FwTextAddr; 4498 fw.text_len = bce_CP_b09FwTextLen; 4499 fw.text_index = 0; 4500 fw.text = bce_CP_b09FwText; 4501 4502 fw.data_addr = bce_CP_b09FwDataAddr; 4503 fw.data_len = bce_CP_b09FwDataLen; 4504 fw.data_index = 0; 4505 fw.data = bce_CP_b09FwData; 4506 4507 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4508 fw.sbss_len = bce_CP_b09FwSbssLen; 4509 fw.sbss_index = 0; 4510 fw.sbss = bce_CP_b09FwSbss; 4511 4512 fw.bss_addr = bce_CP_b09FwBssAddr; 4513 fw.bss_len = bce_CP_b09FwBssLen; 4514 fw.bss_index = 0; 4515 fw.bss = bce_CP_b09FwBss; 4516 4517 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4518 fw.rodata_len = bce_CP_b09FwRodataLen; 4519 fw.rodata_index = 0; 4520 fw.rodata = bce_CP_b09FwRodata; 4521 } else { 4522 fw.ver_major = bce_CP_b06FwReleaseMajor; 4523 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4524 fw.ver_fix = bce_CP_b06FwReleaseFix; 4525 fw.start_addr = bce_CP_b06FwStartAddr; 4526 4527 fw.text_addr = bce_CP_b06FwTextAddr; 4528 fw.text_len = bce_CP_b06FwTextLen; 4529 fw.text_index = 0; 4530 fw.text = bce_CP_b06FwText; 4531 4532 fw.data_addr = bce_CP_b06FwDataAddr; 4533 fw.data_len = bce_CP_b06FwDataLen; 4534 fw.data_index = 0; 4535 fw.data = bce_CP_b06FwData; 4536 4537 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4538 fw.sbss_len = bce_CP_b06FwSbssLen; 4539 fw.sbss_index = 0; 4540 fw.sbss = bce_CP_b06FwSbss; 4541 4542 fw.bss_addr = bce_CP_b06FwBssAddr; 4543 fw.bss_len = bce_CP_b06FwBssLen; 4544 fw.bss_index = 0; 4545 fw.bss = bce_CP_b06FwBss; 4546 4547 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4548 fw.rodata_len = bce_CP_b06FwRodataLen; 4549 fw.rodata_index = 0; 4550 fw.rodata = bce_CP_b06FwRodata; 4551 } 4552 4553 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4554 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4555 bce_start_cpu(sc, &cpu_reg); 4556 4557 DBEXIT(BCE_VERBOSE_RESET); 4558 } 4559 4560 4561 /****************************************************************************/ 4562 /* Initialize the COM CPU. */ 4563 /* */ 4564 /* Returns: */ 4565 /* Nothing. */ 4566 /****************************************************************************/ 4567 static void 4568 bce_init_com_cpu(struct bce_softc *sc) 4569 { 4570 struct cpu_reg cpu_reg; 4571 struct fw_info fw; 4572 4573 DBENTER(BCE_VERBOSE_RESET); 4574 4575 cpu_reg.mode = BCE_COM_CPU_MODE; 4576 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4577 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4578 cpu_reg.state = BCE_COM_CPU_STATE; 4579 cpu_reg.state_value_clear = 0xffffff; 4580 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4581 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4582 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4583 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4584 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4585 cpu_reg.spad_base = BCE_COM_SCRATCH; 4586 cpu_reg.mips_view_base = 0x8000000; 4587 4588 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4589 fw.ver_major = bce_COM_b09FwReleaseMajor; 4590 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4591 fw.ver_fix = bce_COM_b09FwReleaseFix; 4592 fw.start_addr = bce_COM_b09FwStartAddr; 4593 4594 fw.text_addr = bce_COM_b09FwTextAddr; 4595 fw.text_len = bce_COM_b09FwTextLen; 4596 fw.text_index = 0; 4597 fw.text = bce_COM_b09FwText; 4598 4599 fw.data_addr = bce_COM_b09FwDataAddr; 4600 fw.data_len = bce_COM_b09FwDataLen; 4601 fw.data_index = 0; 4602 fw.data = bce_COM_b09FwData; 4603 4604 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4605 fw.sbss_len = bce_COM_b09FwSbssLen; 4606 fw.sbss_index = 0; 4607 fw.sbss = bce_COM_b09FwSbss; 4608 4609 fw.bss_addr = bce_COM_b09FwBssAddr; 4610 fw.bss_len = bce_COM_b09FwBssLen; 4611 fw.bss_index = 0; 4612 fw.bss = bce_COM_b09FwBss; 4613 4614 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4615 fw.rodata_len = bce_COM_b09FwRodataLen; 4616 fw.rodata_index = 0; 4617 fw.rodata = bce_COM_b09FwRodata; 4618 } else { 4619 fw.ver_major = bce_COM_b06FwReleaseMajor; 4620 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4621 fw.ver_fix = bce_COM_b06FwReleaseFix; 4622 fw.start_addr = bce_COM_b06FwStartAddr; 4623 4624 fw.text_addr = bce_COM_b06FwTextAddr; 4625 fw.text_len = bce_COM_b06FwTextLen; 4626 fw.text_index = 0; 4627 fw.text = bce_COM_b06FwText; 4628 4629 fw.data_addr = bce_COM_b06FwDataAddr; 4630 fw.data_len = bce_COM_b06FwDataLen; 4631 fw.data_index = 0; 4632 fw.data = bce_COM_b06FwData; 4633 4634 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4635 fw.sbss_len = bce_COM_b06FwSbssLen; 4636 fw.sbss_index = 0; 4637 fw.sbss = bce_COM_b06FwSbss; 4638 4639 fw.bss_addr = bce_COM_b06FwBssAddr; 4640 fw.bss_len = bce_COM_b06FwBssLen; 4641 fw.bss_index = 0; 4642 fw.bss = bce_COM_b06FwBss; 4643 4644 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4645 fw.rodata_len = bce_COM_b06FwRodataLen; 4646 fw.rodata_index = 0; 4647 fw.rodata = bce_COM_b06FwRodata; 4648 } 4649 4650 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4651 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4652 bce_start_cpu(sc, &cpu_reg); 4653 4654 DBEXIT(BCE_VERBOSE_RESET); 4655 } 4656 4657 4658 /****************************************************************************/ 4659 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4660 /* */ 4661 /* Loads the firmware for each CPU and starts the CPU. */ 4662 /* */ 4663 /* Returns: */ 4664 /* Nothing. */ 4665 /****************************************************************************/ 4666 static void 4667 bce_init_cpus(struct bce_softc *sc) 4668 { 4669 DBENTER(BCE_VERBOSE_RESET); 4670 4671 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4672 4673 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4674 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4675 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4676 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4677 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4678 } else { 4679 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4680 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4681 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4682 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4683 } 4684 4685 } else { 4686 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4687 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4688 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4689 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4690 } 4691 4692 bce_init_rxp_cpu(sc); 4693 bce_init_txp_cpu(sc); 4694 bce_init_tpat_cpu(sc); 4695 bce_init_com_cpu(sc); 4696 bce_init_cp_cpu(sc); 4697 4698 DBEXIT(BCE_VERBOSE_RESET); 4699 } 4700 4701 4702 /****************************************************************************/ 4703 /* Initialize context memory. */ 4704 /* */ 4705 /* Clears the memory associated with each Context ID (CID). */ 4706 /* */ 4707 /* Returns: */ 4708 /* Nothing. */ 4709 /****************************************************************************/ 4710 static int 4711 bce_init_ctx(struct bce_softc *sc) 4712 { 4713 u32 offset, val, vcid_addr; 4714 int i, j, rc, retry_cnt; 4715 4716 rc = 0; 4717 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4718 4719 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4720 retry_cnt = CTX_INIT_RETRY_COUNT; 4721 4722 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4723 4724 /* 4725 * BCM5709 context memory may be cached 4726 * in host memory so prepare the host memory 4727 * for access. 4728 */ 4729 val = BCE_CTX_COMMAND_ENABLED | 4730 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4731 val |= (BCM_PAGE_BITS - 8) << 16; 4732 REG_WR(sc, BCE_CTX_COMMAND, val); 4733 4734 /* Wait for mem init command to complete. */ 4735 for (i = 0; i < retry_cnt; i++) { 4736 val = REG_RD(sc, BCE_CTX_COMMAND); 4737 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4738 break; 4739 DELAY(2); 4740 } 4741 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4742 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4743 __FUNCTION__); 4744 rc = EBUSY; 4745 goto init_ctx_fail; 4746 } 4747 4748 for (i = 0; i < sc->ctx_pages; i++) { 4749 /* Set the physical address of the context memory. */ 4750 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4751 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4752 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4753 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4754 BCE_ADDR_HI(sc->ctx_paddr[i])); 4755 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4756 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4757 4758 /* Verify the context memory write was successful. */ 4759 for (j = 0; j < retry_cnt; j++) { 4760 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4761 if ((val & 4762 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4763 break; 4764 DELAY(5); 4765 } 4766 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4767 BCE_PRINTF("%s(): Failed to initialize " 4768 "context page %d!\n", __FUNCTION__, i); 4769 rc = EBUSY; 4770 goto init_ctx_fail; 4771 } 4772 } 4773 } else { 4774 4775 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4776 4777 /* 4778 * For the 5706/5708, context memory is local to 4779 * the controller, so initialize the controller 4780 * context memory. 4781 */ 4782 4783 vcid_addr = GET_CID_ADDR(96); 4784 while (vcid_addr) { 4785 4786 vcid_addr -= PHY_CTX_SIZE; 4787 4788 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4789 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4790 4791 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4792 CTX_WR(sc, 0x00, offset, 0); 4793 } 4794 4795 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4796 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4797 } 4798 4799 } 4800 init_ctx_fail: 4801 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4802 return (rc); 4803 } 4804 4805 4806 /****************************************************************************/ 4807 /* Fetch the permanent MAC address of the controller. */ 4808 /* */ 4809 /* Returns: */ 4810 /* Nothing. */ 4811 /****************************************************************************/ 4812 static void 4813 bce_get_mac_addr(struct bce_softc *sc) 4814 { 4815 u32 mac_lo = 0, mac_hi = 0; 4816 4817 DBENTER(BCE_VERBOSE_RESET); 4818 4819 /* 4820 * The NetXtreme II bootcode populates various NIC 4821 * power-on and runtime configuration items in a 4822 * shared memory area. The factory configured MAC 4823 * address is available from both NVRAM and the 4824 * shared memory area so we'll read the value from 4825 * shared memory for speed. 4826 */ 4827 4828 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4829 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4830 4831 if ((mac_lo == 0) && (mac_hi == 0)) { 4832 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4833 __FILE__, __LINE__); 4834 } else { 4835 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4836 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4837 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4838 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4839 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4840 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4841 } 4842 4843 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4844 "address = %6D\n", sc->eaddr, ":"); 4845 DBEXIT(BCE_VERBOSE_RESET); 4846 } 4847 4848 4849 /****************************************************************************/ 4850 /* Program the MAC address. */ 4851 /* */ 4852 /* Returns: */ 4853 /* Nothing. */ 4854 /****************************************************************************/ 4855 static void 4856 bce_set_mac_addr(struct bce_softc *sc) 4857 { 4858 u32 val; 4859 u8 *mac_addr = sc->eaddr; 4860 4861 /* ToDo: Add support for setting multiple MAC addresses. */ 4862 4863 DBENTER(BCE_VERBOSE_RESET); 4864 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4865 "%6D\n", sc->eaddr, ":"); 4866 4867 val = (mac_addr[0] << 8) | mac_addr[1]; 4868 4869 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4870 4871 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4872 (mac_addr[4] << 8) | mac_addr[5]; 4873 4874 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4875 4876 DBEXIT(BCE_VERBOSE_RESET); 4877 } 4878 4879 4880 /****************************************************************************/ 4881 /* Stop the controller. */ 4882 /* */ 4883 /* Returns: */ 4884 /* Nothing. */ 4885 /****************************************************************************/ 4886 static void 4887 bce_stop(struct bce_softc *sc) 4888 { 4889 struct ifnet *ifp; 4890 4891 DBENTER(BCE_VERBOSE_RESET); 4892 4893 BCE_LOCK_ASSERT(sc); 4894 4895 ifp = sc->bce_ifp; 4896 4897 callout_stop(&sc->bce_tick_callout); 4898 4899 /* Disable the transmit/receive blocks. */ 4900 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4901 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4902 DELAY(20); 4903 4904 bce_disable_intr(sc); 4905 4906 /* Free RX buffers. */ 4907 if (bce_hdr_split == TRUE) { 4908 bce_free_pg_chain(sc); 4909 } 4910 bce_free_rx_chain(sc); 4911 4912 /* Free TX buffers. */ 4913 bce_free_tx_chain(sc); 4914 4915 sc->watchdog_timer = 0; 4916 4917 sc->bce_link_up = FALSE; 4918 4919 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4920 4921 DBEXIT(BCE_VERBOSE_RESET); 4922 } 4923 4924 4925 static int 4926 bce_reset(struct bce_softc *sc, u32 reset_code) 4927 { 4928 u32 val; 4929 int i, rc = 0; 4930 4931 DBENTER(BCE_VERBOSE_RESET); 4932 4933 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4934 __FUNCTION__, reset_code); 4935 4936 /* Wait for pending PCI transactions to complete. */ 4937 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4938 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4939 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4940 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4941 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4942 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4943 DELAY(5); 4944 4945 /* Disable DMA */ 4946 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4947 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4948 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4949 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4950 } 4951 4952 /* Assume bootcode is running. */ 4953 sc->bce_fw_timed_out = FALSE; 4954 sc->bce_drv_cardiac_arrest = FALSE; 4955 4956 /* Give the firmware a chance to prepare for the reset. */ 4957 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4958 if (rc) 4959 goto bce_reset_exit; 4960 4961 /* Set a firmware reminder that this is a soft reset. */ 4962 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4963 4964 /* Dummy read to force the chip to complete all current transactions. */ 4965 val = REG_RD(sc, BCE_MISC_ID); 4966 4967 /* Chip reset. */ 4968 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4969 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4970 REG_RD(sc, BCE_MISC_COMMAND); 4971 DELAY(5); 4972 4973 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4974 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4975 4976 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4977 } else { 4978 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4979 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4980 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4981 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4982 4983 /* Allow up to 30us for reset to complete. */ 4984 for (i = 0; i < 10; i++) { 4985 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4986 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4987 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4988 break; 4989 } 4990 DELAY(10); 4991 } 4992 4993 /* Check that reset completed successfully. */ 4994 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4995 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 4996 BCE_PRINTF("%s(%d): Reset failed!\n", 4997 __FILE__, __LINE__); 4998 rc = EBUSY; 4999 goto bce_reset_exit; 5000 } 5001 } 5002 5003 /* Make sure byte swapping is properly configured. */ 5004 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5005 if (val != 0x01020304) { 5006 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5007 __FILE__, __LINE__); 5008 rc = ENODEV; 5009 goto bce_reset_exit; 5010 } 5011 5012 /* Just completed a reset, assume that firmware is running again. */ 5013 sc->bce_fw_timed_out = FALSE; 5014 sc->bce_drv_cardiac_arrest = FALSE; 5015 5016 /* Wait for the firmware to finish its initialization. */ 5017 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5018 if (rc) 5019 BCE_PRINTF("%s(%d): Firmware did not complete " 5020 "initialization!\n", __FILE__, __LINE__); 5021 5022 bce_reset_exit: 5023 DBEXIT(BCE_VERBOSE_RESET); 5024 return (rc); 5025 } 5026 5027 5028 static int 5029 bce_chipinit(struct bce_softc *sc) 5030 { 5031 u32 val; 5032 int rc = 0; 5033 5034 DBENTER(BCE_VERBOSE_RESET); 5035 5036 bce_disable_intr(sc); 5037 5038 /* 5039 * Initialize DMA byte/word swapping, configure the number of DMA 5040 * channels and PCI clock compensation delay. 5041 */ 5042 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5043 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5044 #if BYTE_ORDER == BIG_ENDIAN 5045 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5046 #endif 5047 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5048 DMA_READ_CHANS << 12 | 5049 DMA_WRITE_CHANS << 16; 5050 5051 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5052 5053 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5054 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5055 5056 /* 5057 * This setting resolves a problem observed on certain Intel PCI 5058 * chipsets that cannot handle multiple outstanding DMA operations. 5059 * See errata E9_5706A1_65. 5060 */ 5061 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5062 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5063 !(sc->bce_flags & BCE_PCIX_FLAG)) 5064 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5065 5066 REG_WR(sc, BCE_DMA_CONFIG, val); 5067 5068 /* Enable the RX_V2P and Context state machines before access. */ 5069 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5070 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5071 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5072 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5073 5074 /* Initialize context mapping and zero out the quick contexts. */ 5075 if ((rc = bce_init_ctx(sc)) != 0) 5076 goto bce_chipinit_exit; 5077 5078 /* Initialize the on-boards CPUs */ 5079 bce_init_cpus(sc); 5080 5081 /* Enable management frames (NC-SI) to flow to the MCP. */ 5082 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5083 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5084 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5085 } 5086 5087 /* Prepare NVRAM for access. */ 5088 if ((rc = bce_init_nvram(sc)) != 0) 5089 goto bce_chipinit_exit; 5090 5091 /* Set the kernel bypass block size */ 5092 val = REG_RD(sc, BCE_MQ_CONFIG); 5093 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5094 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5095 5096 /* Enable bins used on the 5709. */ 5097 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5098 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5099 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5100 val |= BCE_MQ_CONFIG_HALT_DIS; 5101 } 5102 5103 REG_WR(sc, BCE_MQ_CONFIG, val); 5104 5105 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5106 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5107 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5108 5109 /* Set the page size and clear the RV2P processor stall bits. */ 5110 val = (BCM_PAGE_BITS - 8) << 24; 5111 REG_WR(sc, BCE_RV2P_CONFIG, val); 5112 5113 /* Configure page size. */ 5114 val = REG_RD(sc, BCE_TBDR_CONFIG); 5115 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5116 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5117 REG_WR(sc, BCE_TBDR_CONFIG, val); 5118 5119 /* Set the perfect match control register to default. */ 5120 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5121 5122 bce_chipinit_exit: 5123 DBEXIT(BCE_VERBOSE_RESET); 5124 5125 return(rc); 5126 } 5127 5128 5129 /****************************************************************************/ 5130 /* Initialize the controller in preparation to send/receive traffic. */ 5131 /* */ 5132 /* Returns: */ 5133 /* 0 for success, positive value for failure. */ 5134 /****************************************************************************/ 5135 static int 5136 bce_blockinit(struct bce_softc *sc) 5137 { 5138 u32 reg, val; 5139 int rc = 0; 5140 5141 DBENTER(BCE_VERBOSE_RESET); 5142 5143 /* Load the hardware default MAC address. */ 5144 bce_set_mac_addr(sc); 5145 5146 /* Set the Ethernet backoff seed value */ 5147 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5148 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5149 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5150 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5151 5152 sc->last_status_idx = 0; 5153 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5154 5155 /* Set up link change interrupt generation. */ 5156 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5157 5158 /* Program the physical address of the status block. */ 5159 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5160 BCE_ADDR_LO(sc->status_block_paddr)); 5161 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5162 BCE_ADDR_HI(sc->status_block_paddr)); 5163 5164 /* Program the physical address of the statistics block. */ 5165 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5166 BCE_ADDR_LO(sc->stats_block_paddr)); 5167 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5168 BCE_ADDR_HI(sc->stats_block_paddr)); 5169 5170 /* Program various host coalescing parameters. */ 5171 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5172 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 5173 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5174 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 5175 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 5176 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 5177 REG_WR(sc, BCE_HC_TX_TICKS, 5178 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5179 REG_WR(sc, BCE_HC_RX_TICKS, 5180 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5181 REG_WR(sc, BCE_HC_COM_TICKS, 5182 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 5183 REG_WR(sc, BCE_HC_CMD_TICKS, 5184 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 5185 REG_WR(sc, BCE_HC_STATS_TICKS, 5186 (sc->bce_stats_ticks & 0xffff00)); 5187 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5188 5189 /* Configure the Host Coalescing block. */ 5190 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5191 BCE_HC_CONFIG_COLLECT_STATS; 5192 5193 #if 0 5194 /* ToDo: Add MSI-X support. */ 5195 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5196 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5197 BCE_HC_SB_CONFIG_1; 5198 5199 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5200 5201 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5202 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5203 5204 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5205 (sc->tx_quick_cons_trip_int << 16) | 5206 sc->tx_quick_cons_trip); 5207 5208 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5209 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5210 5211 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5212 } 5213 5214 /* 5215 * Tell the HC block to automatically set the 5216 * INT_MASK bit after an MSI/MSI-X interrupt 5217 * is generated so the driver doesn't have to. 5218 */ 5219 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5220 val |= BCE_HC_CONFIG_ONE_SHOT; 5221 5222 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5223 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5224 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5225 #endif 5226 5227 REG_WR(sc, BCE_HC_CONFIG, val); 5228 5229 /* Clear the internal statistics counters. */ 5230 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5231 5232 /* Verify that bootcode is running. */ 5233 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5234 5235 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5236 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5237 __FILE__, __LINE__); 5238 reg = 0); 5239 5240 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5241 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5242 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5243 "Expected: 08%08X\n", __FILE__, __LINE__, 5244 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5245 BCE_DEV_INFO_SIGNATURE_MAGIC); 5246 rc = ENODEV; 5247 goto bce_blockinit_exit; 5248 } 5249 5250 /* Enable DMA */ 5251 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5252 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5253 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5254 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5255 } 5256 5257 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5258 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5259 BCE_DRV_MSG_CODE_RESET); 5260 5261 /* Enable link state change interrupt generation. */ 5262 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5263 5264 /* Enable the RXP. */ 5265 bce_start_rxp_cpu(sc); 5266 5267 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5268 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5269 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5270 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5271 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5272 } 5273 5274 /* Enable all remaining blocks in the MAC. */ 5275 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5276 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5277 BCE_MISC_ENABLE_DEFAULT_XI); 5278 else 5279 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5280 BCE_MISC_ENABLE_DEFAULT); 5281 5282 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5283 DELAY(20); 5284 5285 /* Save the current host coalescing block settings. */ 5286 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5287 5288 bce_blockinit_exit: 5289 DBEXIT(BCE_VERBOSE_RESET); 5290 5291 return (rc); 5292 } 5293 5294 5295 /****************************************************************************/ 5296 /* Encapsulate an mbuf into the rx_bd chain. */ 5297 /* */ 5298 /* Returns: */ 5299 /* 0 for success, positive value for failure. */ 5300 /****************************************************************************/ 5301 static int 5302 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5303 u16 *chain_prod, u32 *prod_bseq) 5304 { 5305 bus_dmamap_t map; 5306 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 5307 struct mbuf *m_new = NULL; 5308 struct rx_bd *rxbd; 5309 int nsegs, error, rc = 0; 5310 #ifdef BCE_DEBUG 5311 u16 debug_chain_prod = *chain_prod; 5312 #endif 5313 5314 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5315 5316 /* Make sure the inputs are valid. */ 5317 DBRUNIF((*chain_prod > MAX_RX_BD_ALLOC), 5318 BCE_PRINTF("%s(%d): RX producer out of range: " 5319 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5320 *chain_prod, (u16) MAX_RX_BD_ALLOC)); 5321 5322 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5323 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5324 *prod, *chain_prod, *prod_bseq); 5325 5326 /* Update some debug statistic counters */ 5327 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5328 sc->rx_low_watermark = sc->free_rx_bd); 5329 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5330 sc->rx_empty_count++); 5331 5332 /* Check whether this is a new mbuf allocation. */ 5333 if (m == NULL) { 5334 5335 /* Simulate an mbuf allocation failure. */ 5336 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5337 sc->mbuf_alloc_failed_count++; 5338 sc->mbuf_alloc_failed_sim_count++; 5339 rc = ENOBUFS; 5340 goto bce_get_rx_buf_exit); 5341 5342 /* This is a new mbuf allocation. */ 5343 if (bce_hdr_split == TRUE) 5344 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5345 else 5346 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 5347 sc->rx_bd_mbuf_alloc_size); 5348 5349 if (m_new == NULL) { 5350 sc->mbuf_alloc_failed_count++; 5351 rc = ENOBUFS; 5352 goto bce_get_rx_buf_exit; 5353 } 5354 5355 DBRUN(sc->debug_rx_mbuf_alloc++); 5356 } else { 5357 /* Reuse an existing mbuf. */ 5358 m_new = m; 5359 } 5360 5361 /* Make sure we have a valid packet header. */ 5362 M_ASSERTPKTHDR(m_new); 5363 5364 /* Initialize the mbuf size and pad if necessary for alignment. */ 5365 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5366 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5367 5368 /* ToDo: Consider calling m_fragment() to test error handling. */ 5369 5370 /* Map the mbuf cluster into device memory. */ 5371 map = sc->rx_mbuf_map[*chain_prod]; 5372 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5373 segs, &nsegs, BUS_DMA_NOWAIT); 5374 5375 /* Handle any mapping errors. */ 5376 if (error) { 5377 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5378 "chain (%d)!\n", __FILE__, __LINE__, error); 5379 5380 sc->dma_map_addr_rx_failed_count++; 5381 m_freem(m_new); 5382 5383 DBRUN(sc->debug_rx_mbuf_alloc--); 5384 5385 rc = ENOBUFS; 5386 goto bce_get_rx_buf_exit; 5387 } 5388 5389 /* All mbufs must map to a single segment. */ 5390 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5391 __FUNCTION__, nsegs)); 5392 5393 /* Setup the rx_bd for the segment. */ 5394 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5395 5396 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5397 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5398 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5399 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5400 *prod_bseq += segs[0].ds_len; 5401 5402 /* Save the mbuf and update our counter. */ 5403 sc->rx_mbuf_ptr[*chain_prod] = m_new; 5404 sc->free_rx_bd -= nsegs; 5405 5406 DBRUNMSG(BCE_INSANE_RECV, 5407 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5408 5409 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5410 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", 5411 __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5412 5413 bce_get_rx_buf_exit: 5414 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5415 5416 return(rc); 5417 } 5418 5419 5420 /****************************************************************************/ 5421 /* Encapsulate an mbuf cluster into the page chain. */ 5422 /* */ 5423 /* Returns: */ 5424 /* 0 for success, positive value for failure. */ 5425 /****************************************************************************/ 5426 static int 5427 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5428 u16 *prod_idx) 5429 { 5430 bus_dmamap_t map; 5431 bus_addr_t busaddr; 5432 struct mbuf *m_new = NULL; 5433 struct rx_bd *pgbd; 5434 int error, rc = 0; 5435 #ifdef BCE_DEBUG 5436 u16 debug_prod_idx = *prod_idx; 5437 #endif 5438 5439 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5440 5441 /* Make sure the inputs are valid. */ 5442 DBRUNIF((*prod_idx > MAX_PG_BD_ALLOC), 5443 BCE_PRINTF("%s(%d): page producer out of range: " 5444 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5445 *prod_idx, (u16) MAX_PG_BD_ALLOC)); 5446 5447 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5448 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5449 5450 /* Update counters if we've hit a new low or run out of pages. */ 5451 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5452 sc->pg_low_watermark = sc->free_pg_bd); 5453 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5454 5455 /* Check whether this is a new mbuf allocation. */ 5456 if (m == NULL) { 5457 5458 /* Simulate an mbuf allocation failure. */ 5459 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5460 sc->mbuf_alloc_failed_count++; 5461 sc->mbuf_alloc_failed_sim_count++; 5462 rc = ENOBUFS; 5463 goto bce_get_pg_buf_exit); 5464 5465 /* This is a new mbuf allocation. */ 5466 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5467 if (m_new == NULL) { 5468 sc->mbuf_alloc_failed_count++; 5469 rc = ENOBUFS; 5470 goto bce_get_pg_buf_exit; 5471 } 5472 5473 DBRUN(sc->debug_pg_mbuf_alloc++); 5474 } else { 5475 /* Reuse an existing mbuf. */ 5476 m_new = m; 5477 m_new->m_data = m_new->m_ext.ext_buf; 5478 } 5479 5480 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5481 5482 /* ToDo: Consider calling m_fragment() to test error handling. */ 5483 5484 /* Map the mbuf cluster into device memory. */ 5485 map = sc->pg_mbuf_map[*prod_idx]; 5486 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5487 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, 5488 &busaddr, BUS_DMA_NOWAIT); 5489 5490 /* Handle any mapping errors. */ 5491 if (error) { 5492 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5493 __FILE__, __LINE__); 5494 5495 m_freem(m_new); 5496 DBRUN(sc->debug_pg_mbuf_alloc--); 5497 5498 rc = ENOBUFS; 5499 goto bce_get_pg_buf_exit; 5500 } 5501 5502 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5503 5504 /* 5505 * The page chain uses the same rx_bd data structure 5506 * as the receive chain but doesn't require a byte sequence (bseq). 5507 */ 5508 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5509 5510 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5511 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5512 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5513 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5514 5515 /* Save the mbuf and update our counter. */ 5516 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5517 sc->free_pg_bd--; 5518 5519 DBRUNMSG(BCE_INSANE_RECV, 5520 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5521 5522 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5523 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5524 5525 bce_get_pg_buf_exit: 5526 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5527 5528 return(rc); 5529 } 5530 5531 5532 /****************************************************************************/ 5533 /* Initialize the TX context memory. */ 5534 /* */ 5535 /* Returns: */ 5536 /* Nothing */ 5537 /****************************************************************************/ 5538 static void 5539 bce_init_tx_context(struct bce_softc *sc) 5540 { 5541 u32 val; 5542 5543 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5544 5545 /* Initialize the context ID for an L2 TX chain. */ 5546 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5547 /* Set the CID type to support an L2 connection. */ 5548 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5549 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5550 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5551 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5552 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5553 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5554 5555 /* Point the hardware to the first page in the chain. */ 5556 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5557 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5558 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5559 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5560 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5561 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5562 } else { 5563 /* Set the CID type to support an L2 connection. */ 5564 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5565 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5566 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5567 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5568 5569 /* Point the hardware to the first page in the chain. */ 5570 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5571 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5572 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5573 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5574 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5575 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5576 } 5577 5578 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5579 } 5580 5581 5582 /****************************************************************************/ 5583 /* Allocate memory and initialize the TX data structures. */ 5584 /* */ 5585 /* Returns: */ 5586 /* 0 for success, positive value for failure. */ 5587 /****************************************************************************/ 5588 static int 5589 bce_init_tx_chain(struct bce_softc *sc) 5590 { 5591 struct tx_bd *txbd; 5592 int i, rc = 0; 5593 5594 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5595 5596 /* Set the initial TX producer/consumer indices. */ 5597 sc->tx_prod = 0; 5598 sc->tx_cons = 0; 5599 sc->tx_prod_bseq = 0; 5600 sc->used_tx_bd = 0; 5601 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5602 DBRUN(sc->tx_hi_watermark = 0); 5603 DBRUN(sc->tx_full_count = 0); 5604 5605 /* 5606 * The NetXtreme II supports a linked-list structre called 5607 * a Buffer Descriptor Chain (or BD chain). A BD chain 5608 * consists of a series of 1 or more chain pages, each of which 5609 * consists of a fixed number of BD entries. 5610 * The last BD entry on each page is a pointer to the next page 5611 * in the chain, and the last pointer in the BD chain 5612 * points back to the beginning of the chain. 5613 */ 5614 5615 /* Set the TX next pointer chain entries. */ 5616 for (i = 0; i < sc->tx_pages; i++) { 5617 int j; 5618 5619 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5620 5621 /* Check if we've reached the last page. */ 5622 if (i == (sc->tx_pages - 1)) 5623 j = 0; 5624 else 5625 j = i + 1; 5626 5627 txbd->tx_bd_haddr_hi = 5628 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5629 txbd->tx_bd_haddr_lo = 5630 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5631 } 5632 5633 bce_init_tx_context(sc); 5634 5635 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5636 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5637 5638 return(rc); 5639 } 5640 5641 5642 /****************************************************************************/ 5643 /* Free memory and clear the TX data structures. */ 5644 /* */ 5645 /* Returns: */ 5646 /* Nothing. */ 5647 /****************************************************************************/ 5648 static void 5649 bce_free_tx_chain(struct bce_softc *sc) 5650 { 5651 int i; 5652 5653 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5654 5655 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5656 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5657 if (sc->tx_mbuf_ptr[i] != NULL) { 5658 if (sc->tx_mbuf_map[i] != NULL) 5659 bus_dmamap_sync(sc->tx_mbuf_tag, 5660 sc->tx_mbuf_map[i], 5661 BUS_DMASYNC_POSTWRITE); 5662 m_freem(sc->tx_mbuf_ptr[i]); 5663 sc->tx_mbuf_ptr[i] = NULL; 5664 DBRUN(sc->debug_tx_mbuf_alloc--); 5665 } 5666 } 5667 5668 /* Clear each TX chain page. */ 5669 for (i = 0; i < sc->tx_pages; i++) 5670 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5671 5672 sc->used_tx_bd = 0; 5673 5674 /* Check if we lost any mbufs in the process. */ 5675 DBRUNIF((sc->debug_tx_mbuf_alloc), 5676 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5677 "from tx chain!\n", __FILE__, __LINE__, 5678 sc->debug_tx_mbuf_alloc)); 5679 5680 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5681 } 5682 5683 5684 /****************************************************************************/ 5685 /* Initialize the RX context memory. */ 5686 /* */ 5687 /* Returns: */ 5688 /* Nothing */ 5689 /****************************************************************************/ 5690 static void 5691 bce_init_rx_context(struct bce_softc *sc) 5692 { 5693 u32 val; 5694 5695 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5696 5697 /* Init the type, size, and BD cache levels for the RX context. */ 5698 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5699 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5700 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5701 5702 /* 5703 * Set the level for generating pause frames 5704 * when the number of available rx_bd's gets 5705 * too low (the low watermark) and the level 5706 * when pause frames can be stopped (the high 5707 * watermark). 5708 */ 5709 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5710 u32 lo_water, hi_water; 5711 5712 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5713 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5714 } else { 5715 lo_water = 0; 5716 } 5717 5718 if (lo_water >= USABLE_RX_BD_ALLOC) { 5719 lo_water = 0; 5720 } 5721 5722 hi_water = USABLE_RX_BD_ALLOC / 4; 5723 5724 if (hi_water <= lo_water) { 5725 lo_water = 0; 5726 } 5727 5728 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5729 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5730 5731 if (hi_water > 0xf) 5732 hi_water = 0xf; 5733 else if (hi_water == 0) 5734 lo_water = 0; 5735 5736 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5737 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5738 } 5739 5740 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5741 5742 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5743 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5744 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5745 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5746 } 5747 5748 /* Point the hardware to the first page in the chain. */ 5749 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5750 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5751 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5752 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5753 5754 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5755 } 5756 5757 5758 /****************************************************************************/ 5759 /* Allocate memory and initialize the RX data structures. */ 5760 /* */ 5761 /* Returns: */ 5762 /* 0 for success, positive value for failure. */ 5763 /****************************************************************************/ 5764 static int 5765 bce_init_rx_chain(struct bce_softc *sc) 5766 { 5767 struct rx_bd *rxbd; 5768 int i, rc = 0; 5769 5770 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5771 BCE_VERBOSE_CTX); 5772 5773 /* Initialize the RX producer and consumer indices. */ 5774 sc->rx_prod = 0; 5775 sc->rx_cons = 0; 5776 sc->rx_prod_bseq = 0; 5777 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5778 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5779 5780 /* Initialize the RX next pointer chain entries. */ 5781 for (i = 0; i < sc->rx_pages; i++) { 5782 int j; 5783 5784 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5785 5786 /* Check if we've reached the last page. */ 5787 if (i == (sc->rx_pages - 1)) 5788 j = 0; 5789 else 5790 j = i + 1; 5791 5792 /* Setup the chain page pointers. */ 5793 rxbd->rx_bd_haddr_hi = 5794 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5795 rxbd->rx_bd_haddr_lo = 5796 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5797 } 5798 5799 /* Fill up the RX chain. */ 5800 bce_fill_rx_chain(sc); 5801 5802 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5803 DBRUN(sc->rx_empty_count = 0); 5804 for (i = 0; i < sc->rx_pages; i++) { 5805 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5806 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5807 } 5808 5809 bce_init_rx_context(sc); 5810 5811 DBRUNMSG(BCE_EXTREME_RECV, 5812 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5813 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5814 BCE_VERBOSE_CTX); 5815 5816 /* ToDo: Are there possible failure modes here? */ 5817 5818 return(rc); 5819 } 5820 5821 5822 /****************************************************************************/ 5823 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5824 /* occurs. */ 5825 /* */ 5826 /* Returns: */ 5827 /* Nothing */ 5828 /****************************************************************************/ 5829 static void 5830 bce_fill_rx_chain(struct bce_softc *sc) 5831 { 5832 u16 prod, prod_idx; 5833 u32 prod_bseq; 5834 5835 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5836 BCE_VERBOSE_CTX); 5837 5838 /* Get the RX chain producer indices. */ 5839 prod = sc->rx_prod; 5840 prod_bseq = sc->rx_prod_bseq; 5841 5842 /* Keep filling the RX chain until it's full. */ 5843 while (sc->free_rx_bd > 0) { 5844 prod_idx = RX_CHAIN_IDX(prod); 5845 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5846 /* Bail out if we can't add an mbuf to the chain. */ 5847 break; 5848 } 5849 prod = NEXT_RX_BD(prod); 5850 } 5851 5852 /* Save the RX chain producer indices. */ 5853 sc->rx_prod = prod; 5854 sc->rx_prod_bseq = prod_bseq; 5855 5856 /* We should never end up pointing to a next page pointer. */ 5857 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5858 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5859 __FUNCTION__, sc->rx_prod)); 5860 5861 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5862 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5863 BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); 5864 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + 5865 BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); 5866 5867 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5868 BCE_VERBOSE_CTX); 5869 } 5870 5871 5872 /****************************************************************************/ 5873 /* Free memory and clear the RX data structures. */ 5874 /* */ 5875 /* Returns: */ 5876 /* Nothing. */ 5877 /****************************************************************************/ 5878 static void 5879 bce_free_rx_chain(struct bce_softc *sc) 5880 { 5881 int i; 5882 5883 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5884 5885 /* Free any mbufs still in the RX mbuf chain. */ 5886 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5887 if (sc->rx_mbuf_ptr[i] != NULL) { 5888 if (sc->rx_mbuf_map[i] != NULL) 5889 bus_dmamap_sync(sc->rx_mbuf_tag, 5890 sc->rx_mbuf_map[i], 5891 BUS_DMASYNC_POSTREAD); 5892 m_freem(sc->rx_mbuf_ptr[i]); 5893 sc->rx_mbuf_ptr[i] = NULL; 5894 DBRUN(sc->debug_rx_mbuf_alloc--); 5895 } 5896 } 5897 5898 /* Clear each RX chain page. */ 5899 for (i = 0; i < sc->rx_pages; i++) 5900 if (sc->rx_bd_chain[i] != NULL) { 5901 bzero((char *)sc->rx_bd_chain[i], 5902 BCE_RX_CHAIN_PAGE_SZ); 5903 } 5904 5905 sc->free_rx_bd = sc->max_rx_bd; 5906 5907 /* Check if we lost any mbufs in the process. */ 5908 DBRUNIF((sc->debug_rx_mbuf_alloc), 5909 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5910 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5911 5912 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5913 } 5914 5915 5916 /****************************************************************************/ 5917 /* Allocate memory and initialize the page data structures. */ 5918 /* Assumes that bce_init_rx_chain() has not already been called. */ 5919 /* */ 5920 /* Returns: */ 5921 /* 0 for success, positive value for failure. */ 5922 /****************************************************************************/ 5923 static int 5924 bce_init_pg_chain(struct bce_softc *sc) 5925 { 5926 struct rx_bd *pgbd; 5927 int i, rc = 0; 5928 u32 val; 5929 5930 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5931 BCE_VERBOSE_CTX); 5932 5933 /* Initialize the page producer and consumer indices. */ 5934 sc->pg_prod = 0; 5935 sc->pg_cons = 0; 5936 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5937 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5938 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5939 DBRUN(sc->pg_empty_count = 0); 5940 5941 /* Initialize the page next pointer chain entries. */ 5942 for (i = 0; i < sc->pg_pages; i++) { 5943 int j; 5944 5945 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5946 5947 /* Check if we've reached the last page. */ 5948 if (i == (sc->pg_pages - 1)) 5949 j = 0; 5950 else 5951 j = i + 1; 5952 5953 /* Setup the chain page pointers. */ 5954 pgbd->rx_bd_haddr_hi = 5955 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5956 pgbd->rx_bd_haddr_lo = 5957 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5958 } 5959 5960 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5961 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5962 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5963 5964 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5965 5966 /* Configure the rx_bd and page chain mbuf cluster size. */ 5967 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5968 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5969 5970 /* Configure the context reserved for jumbo support. */ 5971 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5972 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5973 5974 /* Point the hardware to the first page in the page chain. */ 5975 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5976 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5977 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5978 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5979 5980 /* Fill up the page chain. */ 5981 bce_fill_pg_chain(sc); 5982 5983 for (i = 0; i < sc->pg_pages; i++) { 5984 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5985 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5986 } 5987 5988 DBRUNMSG(BCE_EXTREME_RECV, 5989 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 5990 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5991 BCE_VERBOSE_CTX); 5992 return(rc); 5993 } 5994 5995 5996 /****************************************************************************/ 5997 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 5998 /* occurs. */ 5999 /* */ 6000 /* Returns: */ 6001 /* Nothing */ 6002 /****************************************************************************/ 6003 static void 6004 bce_fill_pg_chain(struct bce_softc *sc) 6005 { 6006 u16 prod, prod_idx; 6007 6008 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6009 BCE_VERBOSE_CTX); 6010 6011 /* Get the page chain prodcuer index. */ 6012 prod = sc->pg_prod; 6013 6014 /* Keep filling the page chain until it's full. */ 6015 while (sc->free_pg_bd > 0) { 6016 prod_idx = PG_CHAIN_IDX(prod); 6017 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 6018 /* Bail out if we can't add an mbuf to the chain. */ 6019 break; 6020 } 6021 prod = NEXT_PG_BD(prod); 6022 } 6023 6024 /* Save the page chain producer index. */ 6025 sc->pg_prod = prod; 6026 6027 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6028 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6029 __FUNCTION__, sc->pg_prod)); 6030 6031 /* 6032 * Write the mailbox and tell the chip about 6033 * the new rx_bd's in the page chain. 6034 */ 6035 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 6036 BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); 6037 6038 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6039 BCE_VERBOSE_CTX); 6040 } 6041 6042 6043 /****************************************************************************/ 6044 /* Free memory and clear the RX data structures. */ 6045 /* */ 6046 /* Returns: */ 6047 /* Nothing. */ 6048 /****************************************************************************/ 6049 static void 6050 bce_free_pg_chain(struct bce_softc *sc) 6051 { 6052 int i; 6053 6054 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6055 6056 /* Free any mbufs still in the mbuf page chain. */ 6057 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6058 if (sc->pg_mbuf_ptr[i] != NULL) { 6059 if (sc->pg_mbuf_map[i] != NULL) 6060 bus_dmamap_sync(sc->pg_mbuf_tag, 6061 sc->pg_mbuf_map[i], 6062 BUS_DMASYNC_POSTREAD); 6063 m_freem(sc->pg_mbuf_ptr[i]); 6064 sc->pg_mbuf_ptr[i] = NULL; 6065 DBRUN(sc->debug_pg_mbuf_alloc--); 6066 } 6067 } 6068 6069 /* Clear each page chain pages. */ 6070 for (i = 0; i < sc->pg_pages; i++) 6071 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6072 6073 sc->free_pg_bd = sc->max_pg_bd; 6074 6075 /* Check if we lost any mbufs in the process. */ 6076 DBRUNIF((sc->debug_pg_mbuf_alloc), 6077 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6078 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6079 6080 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6081 } 6082 6083 6084 /****************************************************************************/ 6085 /* Set media options. */ 6086 /* */ 6087 /* Returns: */ 6088 /* 0 for success, positive value for failure. */ 6089 /****************************************************************************/ 6090 static int 6091 bce_ifmedia_upd(struct ifnet *ifp) 6092 { 6093 struct bce_softc *sc = ifp->if_softc; 6094 int error; 6095 6096 DBENTER(BCE_VERBOSE); 6097 6098 BCE_LOCK(sc); 6099 error = bce_ifmedia_upd_locked(ifp); 6100 BCE_UNLOCK(sc); 6101 6102 DBEXIT(BCE_VERBOSE); 6103 return (error); 6104 } 6105 6106 6107 /****************************************************************************/ 6108 /* Set media options. */ 6109 /* */ 6110 /* Returns: */ 6111 /* Nothing. */ 6112 /****************************************************************************/ 6113 static int 6114 bce_ifmedia_upd_locked(struct ifnet *ifp) 6115 { 6116 struct bce_softc *sc = ifp->if_softc; 6117 struct mii_data *mii; 6118 struct mii_softc *miisc; 6119 int error; 6120 6121 DBENTER(BCE_VERBOSE_PHY); 6122 6123 error = 0; 6124 BCE_LOCK_ASSERT(sc); 6125 6126 mii = device_get_softc(sc->bce_miibus); 6127 6128 /* Make sure the MII bus has been enumerated. */ 6129 if (mii) { 6130 sc->bce_link_up = FALSE; 6131 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6132 PHY_RESET(miisc); 6133 error = mii_mediachg(mii); 6134 } 6135 6136 DBEXIT(BCE_VERBOSE_PHY); 6137 return (error); 6138 } 6139 6140 6141 /****************************************************************************/ 6142 /* Reports current media status. */ 6143 /* */ 6144 /* Returns: */ 6145 /* Nothing. */ 6146 /****************************************************************************/ 6147 static void 6148 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6149 { 6150 struct bce_softc *sc = ifp->if_softc; 6151 struct mii_data *mii; 6152 6153 DBENTER(BCE_VERBOSE_PHY); 6154 6155 BCE_LOCK(sc); 6156 6157 if ((ifp->if_flags & IFF_UP) == 0) { 6158 BCE_UNLOCK(sc); 6159 return; 6160 } 6161 mii = device_get_softc(sc->bce_miibus); 6162 6163 mii_pollstat(mii); 6164 ifmr->ifm_active = mii->mii_media_active; 6165 ifmr->ifm_status = mii->mii_media_status; 6166 6167 BCE_UNLOCK(sc); 6168 6169 DBEXIT(BCE_VERBOSE_PHY); 6170 } 6171 6172 6173 /****************************************************************************/ 6174 /* Handles PHY generated interrupt events. */ 6175 /* */ 6176 /* Returns: */ 6177 /* Nothing. */ 6178 /****************************************************************************/ 6179 static void 6180 bce_phy_intr(struct bce_softc *sc) 6181 { 6182 u32 new_link_state, old_link_state; 6183 6184 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6185 6186 DBRUN(sc->phy_interrupts++); 6187 6188 new_link_state = sc->status_block->status_attn_bits & 6189 STATUS_ATTN_BITS_LINK_STATE; 6190 old_link_state = sc->status_block->status_attn_bits_ack & 6191 STATUS_ATTN_BITS_LINK_STATE; 6192 6193 /* Handle any changes if the link state has changed. */ 6194 if (new_link_state != old_link_state) { 6195 6196 /* Update the status_attn_bits_ack field. */ 6197 if (new_link_state) { 6198 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6199 STATUS_ATTN_BITS_LINK_STATE); 6200 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6201 __FUNCTION__); 6202 } 6203 else { 6204 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6205 STATUS_ATTN_BITS_LINK_STATE); 6206 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6207 __FUNCTION__); 6208 } 6209 6210 /* 6211 * Assume link is down and allow 6212 * tick routine to update the state 6213 * based on the actual media state. 6214 */ 6215 sc->bce_link_up = FALSE; 6216 callout_stop(&sc->bce_tick_callout); 6217 bce_tick(sc); 6218 } 6219 6220 /* Acknowledge the link change interrupt. */ 6221 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6222 6223 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6224 } 6225 6226 6227 /****************************************************************************/ 6228 /* Reads the receive consumer value from the status block (skipping over */ 6229 /* chain page pointer if necessary). */ 6230 /* */ 6231 /* Returns: */ 6232 /* hw_cons */ 6233 /****************************************************************************/ 6234 static inline u16 6235 bce_get_hw_rx_cons(struct bce_softc *sc) 6236 { 6237 u16 hw_cons; 6238 6239 rmb(); 6240 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6241 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6242 hw_cons++; 6243 6244 return hw_cons; 6245 } 6246 6247 /****************************************************************************/ 6248 /* Handles received frame interrupt events. */ 6249 /* */ 6250 /* Returns: */ 6251 /* Nothing. */ 6252 /****************************************************************************/ 6253 static void 6254 bce_rx_intr(struct bce_softc *sc) 6255 { 6256 struct ifnet *ifp = sc->bce_ifp; 6257 struct l2_fhdr *l2fhdr; 6258 struct ether_vlan_header *vh; 6259 unsigned int pkt_len; 6260 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6261 u32 status; 6262 unsigned int rem_len; 6263 u16 sw_pg_cons, sw_pg_cons_idx; 6264 6265 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6266 DBRUN(sc->interrupts_rx++); 6267 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6268 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6269 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6270 6271 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6272 for (int i = 0; i < sc->rx_pages; i++) 6273 bus_dmamap_sync(sc->rx_bd_chain_tag, 6274 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6275 6276 /* Prepare the page chain pages to be accessed by the host CPU. */ 6277 if (bce_hdr_split == TRUE) { 6278 for (int i = 0; i < sc->pg_pages; i++) 6279 bus_dmamap_sync(sc->pg_bd_chain_tag, 6280 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6281 } 6282 6283 /* Get the hardware's view of the RX consumer index. */ 6284 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6285 6286 /* Get working copies of the driver's view of the consumer indices. */ 6287 sw_rx_cons = sc->rx_cons; 6288 sw_pg_cons = sc->pg_cons; 6289 6290 /* Update some debug statistics counters */ 6291 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6292 sc->rx_low_watermark = sc->free_rx_bd); 6293 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6294 sc->rx_empty_count++); 6295 6296 /* Scan through the receive chain as long as there is work to do */ 6297 /* ToDo: Consider setting a limit on the number of packets processed. */ 6298 rmb(); 6299 while (sw_rx_cons != hw_rx_cons) { 6300 struct mbuf *m0; 6301 6302 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6303 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6304 6305 /* Unmap the mbuf from DMA space. */ 6306 bus_dmamap_sync(sc->rx_mbuf_tag, 6307 sc->rx_mbuf_map[sw_rx_cons_idx], 6308 BUS_DMASYNC_POSTREAD); 6309 bus_dmamap_unload(sc->rx_mbuf_tag, 6310 sc->rx_mbuf_map[sw_rx_cons_idx]); 6311 6312 /* Remove the mbuf from the RX chain. */ 6313 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6314 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6315 DBRUN(sc->debug_rx_mbuf_alloc--); 6316 sc->free_rx_bd++; 6317 6318 if(m0 == NULL) { 6319 DBPRINT(sc, BCE_EXTREME_RECV, 6320 "%s(): Oops! Empty mbuf pointer " 6321 "found in sc->rx_mbuf_ptr[0x%04X]!\n", 6322 __FUNCTION__, sw_rx_cons_idx); 6323 goto bce_rx_int_next_rx; 6324 } 6325 6326 /* 6327 * Frames received on the NetXteme II are prepended 6328 * with an l2_fhdr structure which provides status 6329 * information about the received frame (including 6330 * VLAN tags and checksum info). The frames are 6331 * also automatically adjusted to word align the IP 6332 * header (i.e. two null bytes are inserted before 6333 * the Ethernet header). As a result the data 6334 * DMA'd by the controller into the mbuf looks 6335 * like this: 6336 * 6337 * +---------+-----+---------------------+-----+ 6338 * | l2_fhdr | pad | packet data | FCS | 6339 * +---------+-----+---------------------+-----+ 6340 * 6341 * The l2_fhdr needs to be checked and skipped and 6342 * the FCS needs to be stripped before sending the 6343 * packet up the stack. 6344 */ 6345 l2fhdr = mtod(m0, struct l2_fhdr *); 6346 6347 /* Get the packet data + FCS length and the status. */ 6348 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6349 status = l2fhdr->l2_fhdr_status; 6350 6351 /* 6352 * Skip over the l2_fhdr and pad, resulting in the 6353 * following data in the mbuf: 6354 * +---------------------+-----+ 6355 * | packet data | FCS | 6356 * +---------------------+-----+ 6357 */ 6358 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6359 6360 /* 6361 * When split header mode is used, an ethernet frame 6362 * may be split across the receive chain and the 6363 * page chain. If that occurs an mbuf cluster must be 6364 * reassembled from the individual mbuf pieces. 6365 */ 6366 if (bce_hdr_split == TRUE) { 6367 /* 6368 * Check whether the received frame fits in a single 6369 * mbuf or not (i.e. packet data + FCS <= 6370 * sc->rx_bd_mbuf_data_len bytes). 6371 */ 6372 if (pkt_len > m0->m_len) { 6373 /* 6374 * The received frame is larger than a single mbuf. 6375 * If the frame was a TCP frame then only the TCP 6376 * header is placed in the mbuf, the remaining 6377 * payload (including FCS) is placed in the page 6378 * chain, the SPLIT flag is set, and the header 6379 * length is placed in the IP checksum field. 6380 * If the frame is not a TCP frame then the mbuf 6381 * is filled and the remaining bytes are placed 6382 * in the page chain. 6383 */ 6384 6385 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6386 "packet.\n", __FUNCTION__); 6387 DBRUN(sc->split_header_frames_rcvd++); 6388 6389 /* 6390 * When the page chain is enabled and the TCP 6391 * header has been split from the TCP payload, 6392 * the ip_xsum structure will reflect the length 6393 * of the TCP header, not the IP checksum. Set 6394 * the packet length of the mbuf accordingly. 6395 */ 6396 if (status & L2_FHDR_STATUS_SPLIT) { 6397 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6398 DBRUN(sc->split_header_tcp_frames_rcvd++); 6399 } 6400 6401 rem_len = pkt_len - m0->m_len; 6402 6403 /* Pull mbufs off the page chain for any remaining data. */ 6404 while (rem_len > 0) { 6405 struct mbuf *m_pg; 6406 6407 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6408 6409 /* Remove the mbuf from the page chain. */ 6410 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6411 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6412 DBRUN(sc->debug_pg_mbuf_alloc--); 6413 sc->free_pg_bd++; 6414 6415 /* Unmap the page chain mbuf from DMA space. */ 6416 bus_dmamap_sync(sc->pg_mbuf_tag, 6417 sc->pg_mbuf_map[sw_pg_cons_idx], 6418 BUS_DMASYNC_POSTREAD); 6419 bus_dmamap_unload(sc->pg_mbuf_tag, 6420 sc->pg_mbuf_map[sw_pg_cons_idx]); 6421 6422 /* Adjust the mbuf length. */ 6423 if (rem_len < m_pg->m_len) { 6424 /* The mbuf chain is complete. */ 6425 m_pg->m_len = rem_len; 6426 rem_len = 0; 6427 } else { 6428 /* More packet data is waiting. */ 6429 rem_len -= m_pg->m_len; 6430 } 6431 6432 /* Concatenate the mbuf cluster to the mbuf. */ 6433 m_cat(m0, m_pg); 6434 6435 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6436 } 6437 6438 /* Set the total packet length. */ 6439 m0->m_pkthdr.len = pkt_len; 6440 6441 } else { 6442 /* 6443 * The received packet is small and fits in a 6444 * single mbuf (i.e. the l2_fhdr + pad + packet + 6445 * FCS <= MHLEN). In other words, the packet is 6446 * 154 bytes or less in size. 6447 */ 6448 6449 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6450 "packet.\n", __FUNCTION__); 6451 6452 /* Set the total packet length. */ 6453 m0->m_pkthdr.len = m0->m_len = pkt_len; 6454 } 6455 } else 6456 /* Set the total packet length. */ 6457 m0->m_pkthdr.len = m0->m_len = pkt_len; 6458 6459 /* Remove the trailing Ethernet FCS. */ 6460 m_adj(m0, -ETHER_CRC_LEN); 6461 6462 /* Check that the resulting mbuf chain is valid. */ 6463 DBRUN(m_sanity(m0, FALSE)); 6464 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6465 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6466 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6467 m_print(m0, 128)); 6468 6469 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6470 sc->l2fhdr_error_sim_count++; 6471 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6472 6473 /* Check the received frame for errors. */ 6474 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6475 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6476 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6477 6478 /* Log the error and release the mbuf. */ 6479 ifp->if_ierrors++; 6480 sc->l2fhdr_error_count++; 6481 6482 m_freem(m0); 6483 m0 = NULL; 6484 goto bce_rx_int_next_rx; 6485 } 6486 6487 /* Send the packet to the appropriate interface. */ 6488 m0->m_pkthdr.rcvif = ifp; 6489 6490 /* Assume no hardware checksum. */ 6491 m0->m_pkthdr.csum_flags = 0; 6492 6493 /* Validate the checksum if offload enabled. */ 6494 if (ifp->if_capenable & IFCAP_RXCSUM) { 6495 6496 /* Check for an IP datagram. */ 6497 if (!(status & L2_FHDR_STATUS_SPLIT) && 6498 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6499 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6500 DBRUN(sc->csum_offload_ip++); 6501 /* Check if the IP checksum is valid. */ 6502 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6503 m0->m_pkthdr.csum_flags |= 6504 CSUM_IP_VALID; 6505 } 6506 6507 /* Check for a valid TCP/UDP frame. */ 6508 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6509 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6510 6511 /* Check for a good TCP/UDP checksum. */ 6512 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6513 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6514 DBRUN(sc->csum_offload_tcp_udp++); 6515 m0->m_pkthdr.csum_data = 6516 l2fhdr->l2_fhdr_tcp_udp_xsum; 6517 m0->m_pkthdr.csum_flags |= 6518 (CSUM_DATA_VALID 6519 | CSUM_PSEUDO_HDR); 6520 } 6521 } 6522 } 6523 6524 /* Attach the VLAN tag. */ 6525 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6526 DBRUN(sc->vlan_tagged_frames_rcvd++); 6527 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6528 DBRUN(sc->vlan_tagged_frames_stripped++); 6529 #if __FreeBSD_version < 700000 6530 VLAN_INPUT_TAG(ifp, m0, 6531 l2fhdr->l2_fhdr_vlan_tag, continue); 6532 #else 6533 m0->m_pkthdr.ether_vtag = 6534 l2fhdr->l2_fhdr_vlan_tag; 6535 m0->m_flags |= M_VLANTAG; 6536 #endif 6537 } else { 6538 /* 6539 * bce(4) controllers can't disable VLAN 6540 * tag stripping if management firmware 6541 * (ASF/IPMI/UMP) is running. So we always 6542 * strip VLAN tag and manually reconstruct 6543 * the VLAN frame by appending stripped 6544 * VLAN tag in driver if VLAN tag stripping 6545 * was disabled. 6546 * 6547 * TODO: LLC SNAP handling. 6548 */ 6549 bcopy(mtod(m0, uint8_t *), 6550 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6551 ETHER_ADDR_LEN * 2); 6552 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6553 vh = mtod(m0, struct ether_vlan_header *); 6554 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6555 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6556 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6557 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6558 } 6559 } 6560 6561 /* Increment received packet statistics. */ 6562 ifp->if_ipackets++; 6563 6564 bce_rx_int_next_rx: 6565 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6566 6567 /* If we have a packet, pass it up the stack */ 6568 if (m0) { 6569 /* Make sure we don't lose our place when we release the lock. */ 6570 sc->rx_cons = sw_rx_cons; 6571 sc->pg_cons = sw_pg_cons; 6572 6573 BCE_UNLOCK(sc); 6574 (*ifp->if_input)(ifp, m0); 6575 BCE_LOCK(sc); 6576 6577 /* Recover our place. */ 6578 sw_rx_cons = sc->rx_cons; 6579 sw_pg_cons = sc->pg_cons; 6580 } 6581 6582 /* Refresh hw_cons to see if there's new work */ 6583 if (sw_rx_cons == hw_rx_cons) 6584 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6585 } 6586 6587 /* No new packets. Refill the page chain. */ 6588 if (bce_hdr_split == TRUE) { 6589 sc->pg_cons = sw_pg_cons; 6590 bce_fill_pg_chain(sc); 6591 } 6592 6593 /* No new packets. Refill the RX chain. */ 6594 sc->rx_cons = sw_rx_cons; 6595 bce_fill_rx_chain(sc); 6596 6597 /* Prepare the page chain pages to be accessed by the NIC. */ 6598 for (int i = 0; i < sc->rx_pages; i++) 6599 bus_dmamap_sync(sc->rx_bd_chain_tag, 6600 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6601 6602 if (bce_hdr_split == TRUE) { 6603 for (int i = 0; i < sc->pg_pages; i++) 6604 bus_dmamap_sync(sc->pg_bd_chain_tag, 6605 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6606 } 6607 6608 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6609 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6610 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6611 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6612 } 6613 6614 6615 /****************************************************************************/ 6616 /* Reads the transmit consumer value from the status block (skipping over */ 6617 /* chain page pointer if necessary). */ 6618 /* */ 6619 /* Returns: */ 6620 /* hw_cons */ 6621 /****************************************************************************/ 6622 static inline u16 6623 bce_get_hw_tx_cons(struct bce_softc *sc) 6624 { 6625 u16 hw_cons; 6626 6627 mb(); 6628 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6629 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6630 hw_cons++; 6631 6632 return hw_cons; 6633 } 6634 6635 6636 /****************************************************************************/ 6637 /* Handles transmit completion interrupt events. */ 6638 /* */ 6639 /* Returns: */ 6640 /* Nothing. */ 6641 /****************************************************************************/ 6642 static void 6643 bce_tx_intr(struct bce_softc *sc) 6644 { 6645 struct ifnet *ifp = sc->bce_ifp; 6646 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6647 6648 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6649 DBRUN(sc->interrupts_tx++); 6650 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6651 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6652 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6653 6654 BCE_LOCK_ASSERT(sc); 6655 6656 /* Get the hardware's view of the TX consumer index. */ 6657 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6658 sw_tx_cons = sc->tx_cons; 6659 6660 /* Prevent speculative reads of the status block. */ 6661 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6662 BUS_SPACE_BARRIER_READ); 6663 6664 /* Cycle through any completed TX chain page entries. */ 6665 while (sw_tx_cons != hw_tx_cons) { 6666 #ifdef BCE_DEBUG 6667 struct tx_bd *txbd = NULL; 6668 #endif 6669 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6670 6671 DBPRINT(sc, BCE_INFO_SEND, 6672 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6673 "sw_tx_chain_cons = 0x%04X\n", 6674 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6675 6676 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6677 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6678 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6679 (int) MAX_TX_BD_ALLOC); 6680 bce_breakpoint(sc)); 6681 6682 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6683 [TX_IDX(sw_tx_chain_cons)]); 6684 6685 DBRUNIF((txbd == NULL), 6686 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6687 __FILE__, __LINE__, sw_tx_chain_cons); 6688 bce_breakpoint(sc)); 6689 6690 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6691 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6692 6693 /* 6694 * Free the associated mbuf. Remember 6695 * that only the last tx_bd of a packet 6696 * has an mbuf pointer and DMA map. 6697 */ 6698 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6699 6700 /* Validate that this is the last tx_bd. */ 6701 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6702 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6703 "txmbuf == NULL!\n", __FILE__, __LINE__); 6704 bce_breakpoint(sc)); 6705 6706 DBRUNMSG(BCE_INFO_SEND, 6707 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6708 "from tx_bd[0x%04X]\n", __FUNCTION__, 6709 sw_tx_chain_cons)); 6710 6711 /* Unmap the mbuf. */ 6712 bus_dmamap_unload(sc->tx_mbuf_tag, 6713 sc->tx_mbuf_map[sw_tx_chain_cons]); 6714 6715 /* Free the mbuf. */ 6716 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6717 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6718 DBRUN(sc->debug_tx_mbuf_alloc--); 6719 6720 ifp->if_opackets++; 6721 } 6722 6723 sc->used_tx_bd--; 6724 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6725 6726 /* Refresh hw_cons to see if there's new work. */ 6727 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6728 6729 /* Prevent speculative reads of the status block. */ 6730 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6731 BUS_SPACE_BARRIER_READ); 6732 } 6733 6734 /* Clear the TX timeout timer. */ 6735 sc->watchdog_timer = 0; 6736 6737 /* Clear the tx hardware queue full flag. */ 6738 if (sc->used_tx_bd < sc->max_tx_bd) { 6739 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6740 DBPRINT(sc, BCE_INFO_SEND, 6741 "%s(): Open TX chain! %d/%d (used/total)\n", 6742 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6743 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6744 } 6745 6746 sc->tx_cons = sw_tx_cons; 6747 6748 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6749 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6750 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6751 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6752 } 6753 6754 6755 /****************************************************************************/ 6756 /* Disables interrupt generation. */ 6757 /* */ 6758 /* Returns: */ 6759 /* Nothing. */ 6760 /****************************************************************************/ 6761 static void 6762 bce_disable_intr(struct bce_softc *sc) 6763 { 6764 DBENTER(BCE_VERBOSE_INTR); 6765 6766 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6767 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6768 6769 DBEXIT(BCE_VERBOSE_INTR); 6770 } 6771 6772 6773 /****************************************************************************/ 6774 /* Enables interrupt generation. */ 6775 /* */ 6776 /* Returns: */ 6777 /* Nothing. */ 6778 /****************************************************************************/ 6779 static void 6780 bce_enable_intr(struct bce_softc *sc, int coal_now) 6781 { 6782 DBENTER(BCE_VERBOSE_INTR); 6783 6784 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6785 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6786 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6787 6788 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6789 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6790 6791 /* Force an immediate interrupt (whether there is new data or not). */ 6792 if (coal_now) 6793 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6794 6795 DBEXIT(BCE_VERBOSE_INTR); 6796 } 6797 6798 6799 /****************************************************************************/ 6800 /* Handles controller initialization. */ 6801 /* */ 6802 /* Returns: */ 6803 /* Nothing. */ 6804 /****************************************************************************/ 6805 static void 6806 bce_init_locked(struct bce_softc *sc) 6807 { 6808 struct ifnet *ifp; 6809 u32 ether_mtu = 0; 6810 6811 DBENTER(BCE_VERBOSE_RESET); 6812 6813 BCE_LOCK_ASSERT(sc); 6814 6815 ifp = sc->bce_ifp; 6816 6817 /* Check if the driver is still running and bail out if it is. */ 6818 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6819 goto bce_init_locked_exit; 6820 6821 bce_stop(sc); 6822 6823 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6824 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6825 __FILE__, __LINE__); 6826 goto bce_init_locked_exit; 6827 } 6828 6829 if (bce_chipinit(sc)) { 6830 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6831 __FILE__, __LINE__); 6832 goto bce_init_locked_exit; 6833 } 6834 6835 if (bce_blockinit(sc)) { 6836 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6837 __FILE__, __LINE__); 6838 goto bce_init_locked_exit; 6839 } 6840 6841 /* Load our MAC address. */ 6842 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6843 bce_set_mac_addr(sc); 6844 6845 /* 6846 * Calculate and program the hardware Ethernet MTU 6847 * size. Be generous on the receive if we have room 6848 * and allowed by the user. 6849 */ 6850 if (bce_strict_rx_mtu == TRUE) 6851 ether_mtu = ifp->if_mtu; 6852 else { 6853 if (bce_hdr_split == TRUE) { 6854 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + 6855 sc->pg_bd_mbuf_alloc_size)) 6856 ether_mtu = sc->rx_bd_mbuf_data_len + 6857 sc->pg_bd_mbuf_alloc_size; 6858 else 6859 ether_mtu = ifp->if_mtu; 6860 } else { 6861 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6862 ether_mtu = sc->rx_bd_mbuf_data_len; 6863 else 6864 ether_mtu = ifp->if_mtu; 6865 } 6866 } 6867 6868 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6869 6870 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 6871 __FUNCTION__, ether_mtu); 6872 6873 /* Program the mtu, enabling jumbo frame support if necessary. */ 6874 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6875 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6876 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6877 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6878 else 6879 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6880 6881 /* Program appropriate promiscuous/multicast filtering. */ 6882 bce_set_rx_mode(sc); 6883 6884 if (bce_hdr_split == TRUE) { 6885 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6886 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6887 6888 /* Init page buffer descriptor chain. */ 6889 bce_init_pg_chain(sc); 6890 } 6891 6892 /* Init RX buffer descriptor chain. */ 6893 bce_init_rx_chain(sc); 6894 6895 /* Init TX buffer descriptor chain. */ 6896 bce_init_tx_chain(sc); 6897 6898 /* Enable host interrupts. */ 6899 bce_enable_intr(sc, 1); 6900 6901 bce_ifmedia_upd_locked(ifp); 6902 6903 /* Let the OS know the driver is up and running. */ 6904 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6905 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6906 6907 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6908 6909 bce_init_locked_exit: 6910 DBEXIT(BCE_VERBOSE_RESET); 6911 } 6912 6913 6914 /****************************************************************************/ 6915 /* Initialize the controller just enough so that any management firmware */ 6916 /* running on the device will continue to operate correctly. */ 6917 /* */ 6918 /* Returns: */ 6919 /* Nothing. */ 6920 /****************************************************************************/ 6921 static void 6922 bce_mgmt_init_locked(struct bce_softc *sc) 6923 { 6924 struct ifnet *ifp; 6925 6926 DBENTER(BCE_VERBOSE_RESET); 6927 6928 BCE_LOCK_ASSERT(sc); 6929 6930 /* Bail out if management firmware is not running. */ 6931 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6932 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6933 "No management firmware running...\n"); 6934 goto bce_mgmt_init_locked_exit; 6935 } 6936 6937 ifp = sc->bce_ifp; 6938 6939 /* Enable all critical blocks in the MAC. */ 6940 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6941 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6942 DELAY(20); 6943 6944 bce_ifmedia_upd_locked(ifp); 6945 6946 bce_mgmt_init_locked_exit: 6947 DBEXIT(BCE_VERBOSE_RESET); 6948 } 6949 6950 6951 /****************************************************************************/ 6952 /* Handles controller initialization when called from an unlocked routine. */ 6953 /* */ 6954 /* Returns: */ 6955 /* Nothing. */ 6956 /****************************************************************************/ 6957 static void 6958 bce_init(void *xsc) 6959 { 6960 struct bce_softc *sc = xsc; 6961 6962 DBENTER(BCE_VERBOSE_RESET); 6963 6964 BCE_LOCK(sc); 6965 bce_init_locked(sc); 6966 BCE_UNLOCK(sc); 6967 6968 DBEXIT(BCE_VERBOSE_RESET); 6969 } 6970 6971 6972 /****************************************************************************/ 6973 /* Modifies an mbuf for TSO on the hardware. */ 6974 /* */ 6975 /* Returns: */ 6976 /* Pointer to a modified mbuf. */ 6977 /****************************************************************************/ 6978 static struct mbuf * 6979 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 6980 { 6981 struct mbuf *m; 6982 struct ether_header *eh; 6983 struct ip *ip; 6984 struct tcphdr *th; 6985 u16 etype; 6986 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 6987 6988 DBRUN(sc->tso_frames_requested++); 6989 6990 /* Controller may modify mbuf chains. */ 6991 if (M_WRITABLE(*m_head) == 0) { 6992 m = m_dup(*m_head, M_DONTWAIT); 6993 m_freem(*m_head); 6994 if (m == NULL) { 6995 sc->mbuf_alloc_failed_count++; 6996 *m_head = NULL; 6997 return (NULL); 6998 } 6999 *m_head = m; 7000 } 7001 7002 /* 7003 * For TSO the controller needs two pieces of info, 7004 * the MSS and the IP+TCP options length. 7005 */ 7006 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7007 if (m == NULL) { 7008 *m_head = NULL; 7009 return (NULL); 7010 } 7011 eh = mtod(m, struct ether_header *); 7012 etype = ntohs(eh->ether_type); 7013 7014 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7015 switch (etype) { 7016 case ETHERTYPE_IP: 7017 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7018 /* TSO only supported for TCP protocol. */ 7019 if (ip->ip_p != IPPROTO_TCP) { 7020 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7021 __FILE__, __LINE__); 7022 m_freem(*m_head); 7023 *m_head = NULL; 7024 return (NULL); 7025 } 7026 7027 /* Get IP header length in bytes (min 20) */ 7028 ip_hlen = ip->ip_hl << 2; 7029 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7030 sizeof(struct tcphdr)); 7031 if (m == NULL) { 7032 *m_head = NULL; 7033 return (NULL); 7034 } 7035 7036 /* Get the TCP header length in bytes (min 20) */ 7037 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7038 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7039 tcp_hlen = (th->th_off << 2); 7040 7041 /* Make sure all IP/TCP options live in the same buffer. */ 7042 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7043 tcp_hlen); 7044 if (m == NULL) { 7045 *m_head = NULL; 7046 return (NULL); 7047 } 7048 7049 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7050 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7051 ip_len = ip->ip_len; 7052 ip->ip_len = 0; 7053 ip->ip_sum = 0; 7054 break; 7055 case ETHERTYPE_IPV6: 7056 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7057 __FILE__, __LINE__); 7058 m_freem(*m_head); 7059 *m_head = NULL; 7060 return (NULL); 7061 /* NOT REACHED */ 7062 default: 7063 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7064 __FILE__, __LINE__); 7065 m_freem(*m_head); 7066 *m_head = NULL; 7067 return (NULL); 7068 } 7069 7070 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7071 7072 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7073 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7074 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7075 tcp_hlen, ip_len); 7076 7077 /* Set the LSO flag in the TX BD */ 7078 *flags |= TX_BD_FLAGS_SW_LSO; 7079 7080 /* Set the length of IP + TCP options (in 32 bit words) */ 7081 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7082 sizeof(struct tcphdr)) >> 2) << 8); 7083 7084 DBRUN(sc->tso_frames_completed++); 7085 return (*m_head); 7086 } 7087 7088 7089 /****************************************************************************/ 7090 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7091 /* memory visible to the controller. */ 7092 /* */ 7093 /* Returns: */ 7094 /* 0 for success, positive value for failure. */ 7095 /* Modified: */ 7096 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7097 /****************************************************************************/ 7098 static int 7099 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7100 { 7101 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7102 bus_dmamap_t map; 7103 struct tx_bd *txbd = NULL; 7104 struct mbuf *m0; 7105 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7106 u32 prod_bseq; 7107 7108 #ifdef BCE_DEBUG 7109 u16 debug_prod; 7110 #endif 7111 7112 int i, error, nsegs, rc = 0; 7113 7114 DBENTER(BCE_VERBOSE_SEND); 7115 7116 /* Make sure we have room in the TX chain. */ 7117 if (sc->used_tx_bd >= sc->max_tx_bd) 7118 goto bce_tx_encap_exit; 7119 7120 /* Transfer any checksum offload flags to the bd. */ 7121 m0 = *m_head; 7122 if (m0->m_pkthdr.csum_flags) { 7123 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7124 m0 = bce_tso_setup(sc, m_head, &flags); 7125 if (m0 == NULL) { 7126 DBRUN(sc->tso_frames_failed++); 7127 goto bce_tx_encap_exit; 7128 } 7129 mss = htole16(m0->m_pkthdr.tso_segsz); 7130 } else { 7131 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7132 flags |= TX_BD_FLAGS_IP_CKSUM; 7133 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7134 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7135 } 7136 } 7137 7138 /* Transfer any VLAN tags to the bd. */ 7139 if (m0->m_flags & M_VLANTAG) { 7140 flags |= TX_BD_FLAGS_VLAN_TAG; 7141 vlan_tag = m0->m_pkthdr.ether_vtag; 7142 } 7143 7144 /* Map the mbuf into DMAable memory. */ 7145 prod = sc->tx_prod; 7146 chain_prod = TX_CHAIN_IDX(prod); 7147 map = sc->tx_mbuf_map[chain_prod]; 7148 7149 /* Map the mbuf into our DMA address space. */ 7150 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7151 segs, &nsegs, BUS_DMA_NOWAIT); 7152 7153 /* Check if the DMA mapping was successful */ 7154 if (error == EFBIG) { 7155 sc->mbuf_frag_count++; 7156 7157 /* Try to defrag the mbuf. */ 7158 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 7159 if (m0 == NULL) { 7160 /* Defrag was unsuccessful */ 7161 m_freem(*m_head); 7162 *m_head = NULL; 7163 sc->mbuf_alloc_failed_count++; 7164 rc = ENOBUFS; 7165 goto bce_tx_encap_exit; 7166 } 7167 7168 /* Defrag was successful, try mapping again */ 7169 *m_head = m0; 7170 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7171 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7172 7173 /* Still getting an error after a defrag. */ 7174 if (error == ENOMEM) { 7175 /* Insufficient DMA buffers available. */ 7176 sc->dma_map_addr_tx_failed_count++; 7177 rc = error; 7178 goto bce_tx_encap_exit; 7179 } else if (error != 0) { 7180 /* Release it and return an error. */ 7181 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7182 "TX chain!\n", __FILE__, __LINE__); 7183 m_freem(m0); 7184 *m_head = NULL; 7185 sc->dma_map_addr_tx_failed_count++; 7186 rc = ENOBUFS; 7187 goto bce_tx_encap_exit; 7188 } 7189 } else if (error == ENOMEM) { 7190 /* Insufficient DMA buffers available. */ 7191 sc->dma_map_addr_tx_failed_count++; 7192 rc = error; 7193 goto bce_tx_encap_exit; 7194 } else if (error != 0) { 7195 m_freem(m0); 7196 *m_head = NULL; 7197 sc->dma_map_addr_tx_failed_count++; 7198 rc = error; 7199 goto bce_tx_encap_exit; 7200 } 7201 7202 /* Make sure there's room in the chain */ 7203 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7204 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7205 rc = ENOBUFS; 7206 goto bce_tx_encap_exit; 7207 } 7208 7209 /* prod points to an empty tx_bd at this point. */ 7210 prod_bseq = sc->tx_prod_bseq; 7211 7212 #ifdef BCE_DEBUG 7213 debug_prod = chain_prod; 7214 #endif 7215 7216 DBPRINT(sc, BCE_INFO_SEND, 7217 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7218 "prod_bseq = 0x%08X\n", 7219 __FUNCTION__, prod, chain_prod, prod_bseq); 7220 7221 /* 7222 * Cycle through each mbuf segment that makes up 7223 * the outgoing frame, gathering the mapping info 7224 * for that segment and creating a tx_bd for 7225 * the mbuf. 7226 */ 7227 for (i = 0; i < nsegs ; i++) { 7228 7229 chain_prod = TX_CHAIN_IDX(prod); 7230 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7231 [TX_IDX(chain_prod)]; 7232 7233 txbd->tx_bd_haddr_lo = 7234 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7235 txbd->tx_bd_haddr_hi = 7236 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7237 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7238 htole16(segs[i].ds_len); 7239 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7240 txbd->tx_bd_flags = htole16(flags); 7241 prod_bseq += segs[i].ds_len; 7242 if (i == 0) 7243 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7244 prod = NEXT_TX_BD(prod); 7245 } 7246 7247 /* Set the END flag on the last TX buffer descriptor. */ 7248 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7249 7250 DBRUNMSG(BCE_EXTREME_SEND, 7251 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7252 7253 /* 7254 * Ensure that the mbuf pointer for this transmission 7255 * is placed at the array index of the last 7256 * descriptor in this chain. This is done 7257 * because a single map is used for all 7258 * segments of the mbuf and we don't want to 7259 * unload the map before all of the segments 7260 * have been freed. 7261 */ 7262 sc->tx_mbuf_ptr[chain_prod] = m0; 7263 sc->used_tx_bd += nsegs; 7264 7265 /* Update some debug statistic counters */ 7266 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7267 sc->tx_hi_watermark = sc->used_tx_bd); 7268 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7269 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7270 7271 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7272 7273 /* prod points to the next free tx_bd at this point. */ 7274 sc->tx_prod = prod; 7275 sc->tx_prod_bseq = prod_bseq; 7276 7277 /* Tell the chip about the waiting TX frames. */ 7278 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7279 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7280 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7281 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7282 7283 bce_tx_encap_exit: 7284 DBEXIT(BCE_VERBOSE_SEND); 7285 return(rc); 7286 } 7287 7288 7289 /****************************************************************************/ 7290 /* Main transmit routine when called from another routine with a lock. */ 7291 /* */ 7292 /* Returns: */ 7293 /* Nothing. */ 7294 /****************************************************************************/ 7295 static void 7296 bce_start_locked(struct ifnet *ifp) 7297 { 7298 struct bce_softc *sc = ifp->if_softc; 7299 struct mbuf *m_head = NULL; 7300 int count = 0; 7301 u16 tx_prod, tx_chain_prod; 7302 7303 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7304 7305 BCE_LOCK_ASSERT(sc); 7306 7307 /* prod points to the next free tx_bd. */ 7308 tx_prod = sc->tx_prod; 7309 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7310 7311 DBPRINT(sc, BCE_INFO_SEND, 7312 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7313 "tx_prod_bseq = 0x%08X\n", 7314 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7315 7316 /* If there's no link or the transmit queue is empty then just exit. */ 7317 if (sc->bce_link_up == FALSE) { 7318 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7319 __FUNCTION__); 7320 goto bce_start_locked_exit; 7321 } 7322 7323 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7324 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7325 __FUNCTION__); 7326 goto bce_start_locked_exit; 7327 } 7328 7329 /* 7330 * Keep adding entries while there is space in the ring. 7331 */ 7332 while (sc->used_tx_bd < sc->max_tx_bd) { 7333 7334 /* Check for any frames to send. */ 7335 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7336 7337 /* Stop when the transmit queue is empty. */ 7338 if (m_head == NULL) 7339 break; 7340 7341 /* 7342 * Pack the data into the transmit ring. If we 7343 * don't have room, place the mbuf back at the 7344 * head of the queue and set the OACTIVE flag 7345 * to wait for the NIC to drain the chain. 7346 */ 7347 if (bce_tx_encap(sc, &m_head)) { 7348 if (m_head != NULL) 7349 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7350 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7351 DBPRINT(sc, BCE_INFO_SEND, 7352 "TX chain is closed for business! Total " 7353 "tx_bd used = %d\n", sc->used_tx_bd); 7354 break; 7355 } 7356 7357 count++; 7358 7359 /* Send a copy of the frame to any BPF listeners. */ 7360 ETHER_BPF_MTAP(ifp, m_head); 7361 } 7362 7363 /* Exit if no packets were dequeued. */ 7364 if (count == 0) { 7365 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7366 "dequeued\n", __FUNCTION__); 7367 goto bce_start_locked_exit; 7368 } 7369 7370 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7371 "send queue.\n", __FUNCTION__, count); 7372 7373 /* Set the tx timeout. */ 7374 sc->watchdog_timer = BCE_TX_TIMEOUT; 7375 7376 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7377 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7378 7379 bce_start_locked_exit: 7380 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7381 return; 7382 } 7383 7384 7385 /****************************************************************************/ 7386 /* Main transmit routine when called from another routine without a lock. */ 7387 /* */ 7388 /* Returns: */ 7389 /* Nothing. */ 7390 /****************************************************************************/ 7391 static void 7392 bce_start(struct ifnet *ifp) 7393 { 7394 struct bce_softc *sc = ifp->if_softc; 7395 7396 DBENTER(BCE_VERBOSE_SEND); 7397 7398 BCE_LOCK(sc); 7399 bce_start_locked(ifp); 7400 BCE_UNLOCK(sc); 7401 7402 DBEXIT(BCE_VERBOSE_SEND); 7403 } 7404 7405 7406 /****************************************************************************/ 7407 /* Handles any IOCTL calls from the operating system. */ 7408 /* */ 7409 /* Returns: */ 7410 /* 0 for success, positive value for failure. */ 7411 /****************************************************************************/ 7412 static int 7413 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7414 { 7415 struct bce_softc *sc = ifp->if_softc; 7416 struct ifreq *ifr = (struct ifreq *) data; 7417 struct mii_data *mii; 7418 int mask, error = 0; 7419 7420 DBENTER(BCE_VERBOSE_MISC); 7421 7422 switch(command) { 7423 7424 /* Set the interface MTU. */ 7425 case SIOCSIFMTU: 7426 /* Check that the MTU setting is supported. */ 7427 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7428 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7429 error = EINVAL; 7430 break; 7431 } 7432 7433 DBPRINT(sc, BCE_INFO_MISC, 7434 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7435 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7436 7437 BCE_LOCK(sc); 7438 ifp->if_mtu = ifr->ifr_mtu; 7439 7440 if (bce_hdr_split == FALSE) { 7441 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7442 /* 7443 * Because allocation size is used in RX 7444 * buffer allocation, stop controller if 7445 * it is already running. 7446 */ 7447 bce_stop(sc); 7448 } 7449 7450 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7451 7452 bce_init_locked(sc); 7453 } 7454 7455 BCE_UNLOCK(sc); 7456 break; 7457 7458 /* Set interface flags. */ 7459 case SIOCSIFFLAGS: 7460 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7461 7462 BCE_LOCK(sc); 7463 7464 /* Check if the interface is up. */ 7465 if (ifp->if_flags & IFF_UP) { 7466 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7467 /* Change promiscuous/multicast flags as necessary. */ 7468 bce_set_rx_mode(sc); 7469 } else { 7470 /* Start the HW */ 7471 bce_init_locked(sc); 7472 } 7473 } else { 7474 /* The interface is down, check if driver is running. */ 7475 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7476 bce_stop(sc); 7477 7478 /* If MFW is running, restart the controller a bit. */ 7479 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7480 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7481 bce_chipinit(sc); 7482 bce_mgmt_init_locked(sc); 7483 } 7484 } 7485 } 7486 7487 BCE_UNLOCK(sc); 7488 break; 7489 7490 /* Add/Delete multicast address */ 7491 case SIOCADDMULTI: 7492 case SIOCDELMULTI: 7493 DBPRINT(sc, BCE_VERBOSE_MISC, 7494 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7495 7496 BCE_LOCK(sc); 7497 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7498 bce_set_rx_mode(sc); 7499 BCE_UNLOCK(sc); 7500 7501 break; 7502 7503 /* Set/Get Interface media */ 7504 case SIOCSIFMEDIA: 7505 case SIOCGIFMEDIA: 7506 DBPRINT(sc, BCE_VERBOSE_MISC, 7507 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7508 7509 mii = device_get_softc(sc->bce_miibus); 7510 error = ifmedia_ioctl(ifp, ifr, 7511 &mii->mii_media, command); 7512 break; 7513 7514 /* Set interface capability */ 7515 case SIOCSIFCAP: 7516 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7517 DBPRINT(sc, BCE_INFO_MISC, 7518 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7519 7520 /* Toggle the TX checksum capabilities enable flag. */ 7521 if (mask & IFCAP_TXCSUM && 7522 ifp->if_capabilities & IFCAP_TXCSUM) { 7523 ifp->if_capenable ^= IFCAP_TXCSUM; 7524 if (IFCAP_TXCSUM & ifp->if_capenable) 7525 ifp->if_hwassist |= BCE_IF_HWASSIST; 7526 else 7527 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7528 } 7529 7530 /* Toggle the RX checksum capabilities enable flag. */ 7531 if (mask & IFCAP_RXCSUM && 7532 ifp->if_capabilities & IFCAP_RXCSUM) 7533 ifp->if_capenable ^= IFCAP_RXCSUM; 7534 7535 /* Toggle the TSO capabilities enable flag. */ 7536 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7537 ifp->if_capabilities & IFCAP_TSO4) { 7538 ifp->if_capenable ^= IFCAP_TSO4; 7539 if (IFCAP_TSO4 & ifp->if_capenable) 7540 ifp->if_hwassist |= CSUM_TSO; 7541 else 7542 ifp->if_hwassist &= ~CSUM_TSO; 7543 } 7544 7545 if (mask & IFCAP_VLAN_HWCSUM && 7546 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7547 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7548 7549 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7550 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7551 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7552 /* 7553 * Don't actually disable VLAN tag stripping as 7554 * management firmware (ASF/IPMI/UMP) requires the 7555 * feature. If VLAN tag stripping is disabled driver 7556 * will manually reconstruct the VLAN frame by 7557 * appending stripped VLAN tag. 7558 */ 7559 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7560 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7561 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7562 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7563 == 0) 7564 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7565 } 7566 VLAN_CAPABILITIES(ifp); 7567 break; 7568 default: 7569 /* We don't know how to handle the IOCTL, pass it on. */ 7570 error = ether_ioctl(ifp, command, data); 7571 break; 7572 } 7573 7574 DBEXIT(BCE_VERBOSE_MISC); 7575 return(error); 7576 } 7577 7578 7579 /****************************************************************************/ 7580 /* Transmit timeout handler. */ 7581 /* */ 7582 /* Returns: */ 7583 /* Nothing. */ 7584 /****************************************************************************/ 7585 static void 7586 bce_watchdog(struct bce_softc *sc) 7587 { 7588 DBENTER(BCE_EXTREME_SEND); 7589 7590 BCE_LOCK_ASSERT(sc); 7591 7592 /* If the watchdog timer hasn't expired then just exit. */ 7593 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7594 goto bce_watchdog_exit; 7595 7596 /* If pause frames are active then don't reset the hardware. */ 7597 /* ToDo: Should we reset the timer here? */ 7598 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7599 goto bce_watchdog_exit; 7600 7601 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7602 __FILE__, __LINE__); 7603 7604 DBRUNMSG(BCE_INFO, 7605 bce_dump_driver_state(sc); 7606 bce_dump_status_block(sc); 7607 bce_dump_stats_block(sc); 7608 bce_dump_ftqs(sc); 7609 bce_dump_txp_state(sc, 0); 7610 bce_dump_rxp_state(sc, 0); 7611 bce_dump_tpat_state(sc, 0); 7612 bce_dump_cp_state(sc, 0); 7613 bce_dump_com_state(sc, 0)); 7614 7615 DBRUN(bce_breakpoint(sc)); 7616 7617 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7618 7619 bce_init_locked(sc); 7620 sc->bce_ifp->if_oerrors++; 7621 7622 bce_watchdog_exit: 7623 DBEXIT(BCE_EXTREME_SEND); 7624 } 7625 7626 7627 /* 7628 * Interrupt handler. 7629 */ 7630 /****************************************************************************/ 7631 /* Main interrupt entry point. Verifies that the controller generated the */ 7632 /* interrupt and then calls a separate routine for handle the various */ 7633 /* interrupt causes (PHY, TX, RX). */ 7634 /* */ 7635 /* Returns: */ 7636 /* 0 for success, positive value for failure. */ 7637 /****************************************************************************/ 7638 static void 7639 bce_intr(void *xsc) 7640 { 7641 struct bce_softc *sc; 7642 struct ifnet *ifp; 7643 u32 status_attn_bits; 7644 u16 hw_rx_cons, hw_tx_cons; 7645 7646 sc = xsc; 7647 ifp = sc->bce_ifp; 7648 7649 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7650 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7651 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7652 7653 BCE_LOCK(sc); 7654 7655 DBRUN(sc->interrupts_generated++); 7656 7657 /* Synchnorize before we read from interface's status block */ 7658 bus_dmamap_sync(sc->status_tag, sc->status_map, 7659 BUS_DMASYNC_POSTREAD); 7660 7661 /* 7662 * If the hardware status block index 7663 * matches the last value read by the 7664 * driver and we haven't asserted our 7665 * interrupt then there's nothing to do. 7666 */ 7667 if ((sc->status_block->status_idx == sc->last_status_idx) && 7668 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7669 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7670 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7671 __FUNCTION__); 7672 goto bce_intr_exit; 7673 } 7674 7675 /* Ack the interrupt and stop others from occuring. */ 7676 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7677 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7678 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7679 7680 /* Check if the hardware has finished any work. */ 7681 hw_rx_cons = bce_get_hw_rx_cons(sc); 7682 hw_tx_cons = bce_get_hw_tx_cons(sc); 7683 7684 /* Keep processing data as long as there is work to do. */ 7685 for (;;) { 7686 7687 status_attn_bits = sc->status_block->status_attn_bits; 7688 7689 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7690 BCE_PRINTF("Simulating unexpected status attention " 7691 "bit set."); 7692 sc->unexpected_attention_sim_count++; 7693 status_attn_bits = status_attn_bits | 7694 STATUS_ATTN_BITS_PARITY_ERROR); 7695 7696 /* Was it a link change interrupt? */ 7697 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7698 (sc->status_block->status_attn_bits_ack & 7699 STATUS_ATTN_BITS_LINK_STATE)) { 7700 bce_phy_intr(sc); 7701 7702 /* Clear transient updates during link state change. */ 7703 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7704 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7705 REG_RD(sc, BCE_HC_COMMAND); 7706 } 7707 7708 /* If any other attention is asserted, the chip is toast. */ 7709 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7710 (sc->status_block->status_attn_bits_ack & 7711 ~STATUS_ATTN_BITS_LINK_STATE))) { 7712 7713 sc->unexpected_attention_count++; 7714 7715 BCE_PRINTF("%s(%d): Fatal attention detected: " 7716 "0x%08X\n", __FILE__, __LINE__, 7717 sc->status_block->status_attn_bits); 7718 7719 DBRUNMSG(BCE_FATAL, 7720 if (unexpected_attention_sim_control == 0) 7721 bce_breakpoint(sc)); 7722 7723 bce_init_locked(sc); 7724 goto bce_intr_exit; 7725 } 7726 7727 /* Check for any completed RX frames. */ 7728 if (hw_rx_cons != sc->hw_rx_cons) 7729 bce_rx_intr(sc); 7730 7731 /* Check for any completed TX frames. */ 7732 if (hw_tx_cons != sc->hw_tx_cons) 7733 bce_tx_intr(sc); 7734 7735 /* Save status block index value for the next interrupt. */ 7736 sc->last_status_idx = sc->status_block->status_idx; 7737 7738 /* 7739 * Prevent speculative reads from getting 7740 * ahead of the status block. 7741 */ 7742 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7743 BUS_SPACE_BARRIER_READ); 7744 7745 /* 7746 * If there's no work left then exit the 7747 * interrupt service routine. 7748 */ 7749 hw_rx_cons = bce_get_hw_rx_cons(sc); 7750 hw_tx_cons = bce_get_hw_tx_cons(sc); 7751 7752 if ((hw_rx_cons == sc->hw_rx_cons) && 7753 (hw_tx_cons == sc->hw_tx_cons)) 7754 break; 7755 7756 } 7757 7758 bus_dmamap_sync(sc->status_tag, sc->status_map, 7759 BUS_DMASYNC_PREREAD); 7760 7761 /* Re-enable interrupts. */ 7762 bce_enable_intr(sc, 0); 7763 7764 /* Handle any frames that arrived while handling the interrupt. */ 7765 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7766 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7767 bce_start_locked(ifp); 7768 7769 bce_intr_exit: 7770 BCE_UNLOCK(sc); 7771 7772 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7773 } 7774 7775 7776 /****************************************************************************/ 7777 /* Programs the various packet receive modes (broadcast and multicast). */ 7778 /* */ 7779 /* Returns: */ 7780 /* Nothing. */ 7781 /****************************************************************************/ 7782 static void 7783 bce_set_rx_mode(struct bce_softc *sc) 7784 { 7785 struct ifnet *ifp; 7786 struct ifmultiaddr *ifma; 7787 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7788 u32 rx_mode, sort_mode; 7789 int h, i; 7790 7791 DBENTER(BCE_VERBOSE_MISC); 7792 7793 BCE_LOCK_ASSERT(sc); 7794 7795 ifp = sc->bce_ifp; 7796 7797 /* Initialize receive mode default settings. */ 7798 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7799 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7800 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7801 7802 /* 7803 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7804 * be enbled. 7805 */ 7806 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7807 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7808 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7809 7810 /* 7811 * Check for promiscuous, all multicast, or selected 7812 * multicast address filtering. 7813 */ 7814 if (ifp->if_flags & IFF_PROMISC) { 7815 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7816 7817 /* Enable promiscuous mode. */ 7818 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7819 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7820 } else if (ifp->if_flags & IFF_ALLMULTI) { 7821 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7822 7823 /* Enable all multicast addresses. */ 7824 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7825 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7826 } 7827 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7828 } else { 7829 /* Accept one or more multicast(s). */ 7830 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7831 7832 if_maddr_rlock(ifp); 7833 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7834 if (ifma->ifma_addr->sa_family != AF_LINK) 7835 continue; 7836 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7837 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7838 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7839 } 7840 if_maddr_runlock(ifp); 7841 7842 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7843 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7844 7845 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7846 } 7847 7848 /* Only make changes if the recive mode has actually changed. */ 7849 if (rx_mode != sc->rx_mode) { 7850 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7851 "0x%08X\n", rx_mode); 7852 7853 sc->rx_mode = rx_mode; 7854 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7855 } 7856 7857 /* Disable and clear the exisitng sort before enabling a new sort. */ 7858 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7859 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7860 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7861 7862 DBEXIT(BCE_VERBOSE_MISC); 7863 } 7864 7865 7866 /****************************************************************************/ 7867 /* Called periodically to updates statistics from the controllers */ 7868 /* statistics block. */ 7869 /* */ 7870 /* Returns: */ 7871 /* Nothing. */ 7872 /****************************************************************************/ 7873 static void 7874 bce_stats_update(struct bce_softc *sc) 7875 { 7876 struct ifnet *ifp; 7877 struct statistics_block *stats; 7878 7879 DBENTER(BCE_EXTREME_MISC); 7880 7881 ifp = sc->bce_ifp; 7882 7883 stats = (struct statistics_block *) sc->stats_block; 7884 7885 /* 7886 * Certain controllers don't report 7887 * carrier sense errors correctly. 7888 * See errata E11_5708CA0_1165. 7889 */ 7890 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7891 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7892 ifp->if_oerrors += 7893 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7894 7895 /* 7896 * Update the sysctl statistics from the 7897 * hardware statistics. 7898 */ 7899 sc->stat_IfHCInOctets = 7900 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7901 (u64) stats->stat_IfHCInOctets_lo; 7902 7903 sc->stat_IfHCInBadOctets = 7904 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7905 (u64) stats->stat_IfHCInBadOctets_lo; 7906 7907 sc->stat_IfHCOutOctets = 7908 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7909 (u64) stats->stat_IfHCOutOctets_lo; 7910 7911 sc->stat_IfHCOutBadOctets = 7912 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7913 (u64) stats->stat_IfHCOutBadOctets_lo; 7914 7915 sc->stat_IfHCInUcastPkts = 7916 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7917 (u64) stats->stat_IfHCInUcastPkts_lo; 7918 7919 sc->stat_IfHCInMulticastPkts = 7920 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7921 (u64) stats->stat_IfHCInMulticastPkts_lo; 7922 7923 sc->stat_IfHCInBroadcastPkts = 7924 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7925 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7926 7927 sc->stat_IfHCOutUcastPkts = 7928 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7929 (u64) stats->stat_IfHCOutUcastPkts_lo; 7930 7931 sc->stat_IfHCOutMulticastPkts = 7932 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7933 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7934 7935 sc->stat_IfHCOutBroadcastPkts = 7936 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7937 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7938 7939 /* ToDo: Preserve counters beyond 32 bits? */ 7940 /* ToDo: Read the statistics from auto-clear regs? */ 7941 7942 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7943 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7944 7945 sc->stat_Dot3StatsCarrierSenseErrors = 7946 stats->stat_Dot3StatsCarrierSenseErrors; 7947 7948 sc->stat_Dot3StatsFCSErrors = 7949 stats->stat_Dot3StatsFCSErrors; 7950 7951 sc->stat_Dot3StatsAlignmentErrors = 7952 stats->stat_Dot3StatsAlignmentErrors; 7953 7954 sc->stat_Dot3StatsSingleCollisionFrames = 7955 stats->stat_Dot3StatsSingleCollisionFrames; 7956 7957 sc->stat_Dot3StatsMultipleCollisionFrames = 7958 stats->stat_Dot3StatsMultipleCollisionFrames; 7959 7960 sc->stat_Dot3StatsDeferredTransmissions = 7961 stats->stat_Dot3StatsDeferredTransmissions; 7962 7963 sc->stat_Dot3StatsExcessiveCollisions = 7964 stats->stat_Dot3StatsExcessiveCollisions; 7965 7966 sc->stat_Dot3StatsLateCollisions = 7967 stats->stat_Dot3StatsLateCollisions; 7968 7969 sc->stat_EtherStatsCollisions = 7970 stats->stat_EtherStatsCollisions; 7971 7972 sc->stat_EtherStatsFragments = 7973 stats->stat_EtherStatsFragments; 7974 7975 sc->stat_EtherStatsJabbers = 7976 stats->stat_EtherStatsJabbers; 7977 7978 sc->stat_EtherStatsUndersizePkts = 7979 stats->stat_EtherStatsUndersizePkts; 7980 7981 sc->stat_EtherStatsOversizePkts = 7982 stats->stat_EtherStatsOversizePkts; 7983 7984 sc->stat_EtherStatsPktsRx64Octets = 7985 stats->stat_EtherStatsPktsRx64Octets; 7986 7987 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 7988 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 7989 7990 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 7991 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 7992 7993 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 7994 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 7995 7996 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 7997 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 7998 7999 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8000 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8001 8002 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8003 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8004 8005 sc->stat_EtherStatsPktsTx64Octets = 8006 stats->stat_EtherStatsPktsTx64Octets; 8007 8008 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8009 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8010 8011 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8012 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8013 8014 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8015 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8016 8017 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8018 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8019 8020 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8021 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8022 8023 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8024 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8025 8026 sc->stat_XonPauseFramesReceived = 8027 stats->stat_XonPauseFramesReceived; 8028 8029 sc->stat_XoffPauseFramesReceived = 8030 stats->stat_XoffPauseFramesReceived; 8031 8032 sc->stat_OutXonSent = 8033 stats->stat_OutXonSent; 8034 8035 sc->stat_OutXoffSent = 8036 stats->stat_OutXoffSent; 8037 8038 sc->stat_FlowControlDone = 8039 stats->stat_FlowControlDone; 8040 8041 sc->stat_MacControlFramesReceived = 8042 stats->stat_MacControlFramesReceived; 8043 8044 sc->stat_XoffStateEntered = 8045 stats->stat_XoffStateEntered; 8046 8047 sc->stat_IfInFramesL2FilterDiscards = 8048 stats->stat_IfInFramesL2FilterDiscards; 8049 8050 sc->stat_IfInRuleCheckerDiscards = 8051 stats->stat_IfInRuleCheckerDiscards; 8052 8053 sc->stat_IfInFTQDiscards = 8054 stats->stat_IfInFTQDiscards; 8055 8056 sc->stat_IfInMBUFDiscards = 8057 stats->stat_IfInMBUFDiscards; 8058 8059 sc->stat_IfInRuleCheckerP4Hit = 8060 stats->stat_IfInRuleCheckerP4Hit; 8061 8062 sc->stat_CatchupInRuleCheckerDiscards = 8063 stats->stat_CatchupInRuleCheckerDiscards; 8064 8065 sc->stat_CatchupInFTQDiscards = 8066 stats->stat_CatchupInFTQDiscards; 8067 8068 sc->stat_CatchupInMBUFDiscards = 8069 stats->stat_CatchupInMBUFDiscards; 8070 8071 sc->stat_CatchupInRuleCheckerP4Hit = 8072 stats->stat_CatchupInRuleCheckerP4Hit; 8073 8074 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8075 8076 /* 8077 * Update the interface statistics from the 8078 * hardware statistics. 8079 */ 8080 ifp->if_collisions = 8081 (u_long) sc->stat_EtherStatsCollisions; 8082 8083 /* ToDo: This method loses soft errors. */ 8084 ifp->if_ierrors = 8085 (u_long) sc->stat_EtherStatsUndersizePkts + 8086 (u_long) sc->stat_EtherStatsOversizePkts + 8087 (u_long) sc->stat_IfInMBUFDiscards + 8088 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8089 (u_long) sc->stat_Dot3StatsFCSErrors + 8090 (u_long) sc->stat_IfInRuleCheckerDiscards + 8091 (u_long) sc->stat_IfInFTQDiscards + 8092 (u_long) sc->com_no_buffers; 8093 8094 /* ToDo: This method loses soft errors. */ 8095 ifp->if_oerrors = 8096 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8097 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8098 (u_long) sc->stat_Dot3StatsLateCollisions; 8099 8100 /* ToDo: Add additional statistics? */ 8101 8102 DBEXIT(BCE_EXTREME_MISC); 8103 } 8104 8105 8106 /****************************************************************************/ 8107 /* Periodic function to notify the bootcode that the driver is still */ 8108 /* present. */ 8109 /* */ 8110 /* Returns: */ 8111 /* Nothing. */ 8112 /****************************************************************************/ 8113 static void 8114 bce_pulse(void *xsc) 8115 { 8116 struct bce_softc *sc = xsc; 8117 u32 msg; 8118 8119 DBENTER(BCE_EXTREME_MISC); 8120 8121 BCE_LOCK_ASSERT(sc); 8122 8123 /* Tell the firmware that the driver is still running. */ 8124 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8125 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8126 8127 /* Update the bootcode condition. */ 8128 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8129 8130 /* Report whether the bootcode still knows the driver is running. */ 8131 if (bce_verbose || bootverbose) { 8132 if (sc->bce_drv_cardiac_arrest == FALSE) { 8133 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8134 sc->bce_drv_cardiac_arrest = TRUE; 8135 BCE_PRINTF("%s(): Warning: bootcode " 8136 "thinks driver is absent! " 8137 "(bc_state = 0x%08X)\n", 8138 __FUNCTION__, sc->bc_state); 8139 } 8140 } else { 8141 /* 8142 * Not supported by all bootcode versions. 8143 * (v5.0.11+ and v5.2.1+) Older bootcode 8144 * will require the driver to reset the 8145 * controller to clear this condition. 8146 */ 8147 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8148 sc->bce_drv_cardiac_arrest = FALSE; 8149 BCE_PRINTF("%s(): Bootcode found the " 8150 "driver pulse! (bc_state = 0x%08X)\n", 8151 __FUNCTION__, sc->bc_state); 8152 } 8153 } 8154 } 8155 8156 8157 /* Schedule the next pulse. */ 8158 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8159 8160 DBEXIT(BCE_EXTREME_MISC); 8161 } 8162 8163 8164 /****************************************************************************/ 8165 /* Periodic function to perform maintenance tasks. */ 8166 /* */ 8167 /* Returns: */ 8168 /* Nothing. */ 8169 /****************************************************************************/ 8170 static void 8171 bce_tick(void *xsc) 8172 { 8173 struct bce_softc *sc = xsc; 8174 struct mii_data *mii; 8175 struct ifnet *ifp; 8176 8177 ifp = sc->bce_ifp; 8178 8179 DBENTER(BCE_EXTREME_MISC); 8180 8181 BCE_LOCK_ASSERT(sc); 8182 8183 /* Schedule the next tick. */ 8184 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8185 8186 /* Update the statistics from the hardware statistics block. */ 8187 bce_stats_update(sc); 8188 8189 /* 8190 * ToDo: This is a safety measure. Need to re-evaluate 8191 * high level processing logic and eliminate this code. 8192 */ 8193 /* Top off the receive and page chains. */ 8194 if (bce_hdr_split == TRUE) 8195 bce_fill_pg_chain(sc); 8196 bce_fill_rx_chain(sc); 8197 8198 /* Check that chip hasn't hung. */ 8199 bce_watchdog(sc); 8200 8201 /* If link is up already up then we're done. */ 8202 if (sc->bce_link_up == TRUE) 8203 goto bce_tick_exit; 8204 8205 /* Link is down. Check what the PHY's doing. */ 8206 mii = device_get_softc(sc->bce_miibus); 8207 mii_tick(mii); 8208 8209 /* Check if the link has come up. */ 8210 if ((mii->mii_media_status & IFM_ACTIVE) && 8211 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8212 DBPRINT(sc, BCE_VERBOSE_MISC, 8213 "%s(): Link up!\n", __FUNCTION__); 8214 sc->bce_link_up = TRUE; 8215 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8216 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8217 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8218 (bce_verbose || bootverbose)) 8219 BCE_PRINTF("Gigabit link up!\n"); 8220 8221 /* Now that link is up, handle any outstanding TX traffic. */ 8222 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8223 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8224 "pending TX traffic.\n", __FUNCTION__); 8225 bce_start_locked(ifp); 8226 } 8227 } 8228 8229 bce_tick_exit: 8230 DBEXIT(BCE_EXTREME_MISC); 8231 return; 8232 } 8233 8234 #ifdef BCE_DEBUG 8235 /****************************************************************************/ 8236 /* Allows the driver state to be dumped through the sysctl interface. */ 8237 /* */ 8238 /* Returns: */ 8239 /* 0 for success, positive value for failure. */ 8240 /****************************************************************************/ 8241 static int 8242 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8243 { 8244 int error; 8245 int result; 8246 struct bce_softc *sc; 8247 8248 result = -1; 8249 error = sysctl_handle_int(oidp, &result, 0, req); 8250 8251 if (error || !req->newptr) 8252 return (error); 8253 8254 if (result == 1) { 8255 sc = (struct bce_softc *)arg1; 8256 bce_dump_driver_state(sc); 8257 } 8258 8259 return error; 8260 } 8261 8262 8263 /****************************************************************************/ 8264 /* Allows the hardware state to be dumped through the sysctl interface. */ 8265 /* */ 8266 /* Returns: */ 8267 /* 0 for success, positive value for failure. */ 8268 /****************************************************************************/ 8269 static int 8270 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8271 { 8272 int error; 8273 int result; 8274 struct bce_softc *sc; 8275 8276 result = -1; 8277 error = sysctl_handle_int(oidp, &result, 0, req); 8278 8279 if (error || !req->newptr) 8280 return (error); 8281 8282 if (result == 1) { 8283 sc = (struct bce_softc *)arg1; 8284 bce_dump_hw_state(sc); 8285 } 8286 8287 return error; 8288 } 8289 8290 8291 /****************************************************************************/ 8292 /* Allows the status block to be dumped through the sysctl interface. */ 8293 /* */ 8294 /* Returns: */ 8295 /* 0 for success, positive value for failure. */ 8296 /****************************************************************************/ 8297 static int 8298 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8299 { 8300 int error; 8301 int result; 8302 struct bce_softc *sc; 8303 8304 result = -1; 8305 error = sysctl_handle_int(oidp, &result, 0, req); 8306 8307 if (error || !req->newptr) 8308 return (error); 8309 8310 if (result == 1) { 8311 sc = (struct bce_softc *)arg1; 8312 bce_dump_status_block(sc); 8313 } 8314 8315 return error; 8316 } 8317 8318 8319 /****************************************************************************/ 8320 /* Allows the stats block to be dumped through the sysctl interface. */ 8321 /* */ 8322 /* Returns: */ 8323 /* 0 for success, positive value for failure. */ 8324 /****************************************************************************/ 8325 static int 8326 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8327 { 8328 int error; 8329 int result; 8330 struct bce_softc *sc; 8331 8332 result = -1; 8333 error = sysctl_handle_int(oidp, &result, 0, req); 8334 8335 if (error || !req->newptr) 8336 return (error); 8337 8338 if (result == 1) { 8339 sc = (struct bce_softc *)arg1; 8340 bce_dump_stats_block(sc); 8341 } 8342 8343 return error; 8344 } 8345 8346 8347 /****************************************************************************/ 8348 /* Allows the stat counters to be cleared without unloading/reloading the */ 8349 /* driver. */ 8350 /* */ 8351 /* Returns: */ 8352 /* 0 for success, positive value for failure. */ 8353 /****************************************************************************/ 8354 static int 8355 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8356 { 8357 int error; 8358 int result; 8359 struct bce_softc *sc; 8360 8361 result = -1; 8362 error = sysctl_handle_int(oidp, &result, 0, req); 8363 8364 if (error || !req->newptr) 8365 return (error); 8366 8367 if (result == 1) { 8368 sc = (struct bce_softc *)arg1; 8369 struct statistics_block *stats; 8370 8371 stats = (struct statistics_block *) sc->stats_block; 8372 bzero(stats, sizeof(struct statistics_block)); 8373 8374 /* Clear the internal H/W statistics counters. */ 8375 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8376 8377 /* Reset the driver maintained statistics. */ 8378 sc->interrupts_rx = 8379 sc->interrupts_tx = 0; 8380 sc->tso_frames_requested = 8381 sc->tso_frames_completed = 8382 sc->tso_frames_failed = 0; 8383 sc->rx_empty_count = 8384 sc->tx_full_count = 0; 8385 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8386 sc->tx_hi_watermark = 0; 8387 sc->l2fhdr_error_count = 8388 sc->l2fhdr_error_sim_count = 0; 8389 sc->mbuf_alloc_failed_count = 8390 sc->mbuf_alloc_failed_sim_count = 0; 8391 sc->dma_map_addr_rx_failed_count = 8392 sc->dma_map_addr_tx_failed_count = 0; 8393 sc->mbuf_frag_count = 0; 8394 sc->csum_offload_tcp_udp = 8395 sc->csum_offload_ip = 0; 8396 sc->vlan_tagged_frames_rcvd = 8397 sc->vlan_tagged_frames_stripped = 0; 8398 sc->split_header_frames_rcvd = 8399 sc->split_header_tcp_frames_rcvd = 0; 8400 8401 /* Clear firmware maintained statistics. */ 8402 REG_WR_IND(sc, 0x120084, 0); 8403 } 8404 8405 return error; 8406 } 8407 8408 8409 /****************************************************************************/ 8410 /* Allows the shared memory contents to be dumped through the sysctl . */ 8411 /* interface. */ 8412 /* */ 8413 /* Returns: */ 8414 /* 0 for success, positive value for failure. */ 8415 /****************************************************************************/ 8416 static int 8417 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8418 { 8419 int error; 8420 int result; 8421 struct bce_softc *sc; 8422 8423 result = -1; 8424 error = sysctl_handle_int(oidp, &result, 0, req); 8425 8426 if (error || !req->newptr) 8427 return (error); 8428 8429 if (result == 1) { 8430 sc = (struct bce_softc *)arg1; 8431 bce_dump_shmem_state(sc); 8432 } 8433 8434 return error; 8435 } 8436 8437 8438 /****************************************************************************/ 8439 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8440 /* */ 8441 /* Returns: */ 8442 /* 0 for success, positive value for failure. */ 8443 /****************************************************************************/ 8444 static int 8445 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8446 { 8447 int error; 8448 int result; 8449 struct bce_softc *sc; 8450 8451 result = -1; 8452 error = sysctl_handle_int(oidp, &result, 0, req); 8453 8454 if (error || !req->newptr) 8455 return (error); 8456 8457 if (result == 1) { 8458 sc = (struct bce_softc *)arg1; 8459 bce_dump_bc_state(sc); 8460 } 8461 8462 return error; 8463 } 8464 8465 8466 /****************************************************************************/ 8467 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8468 /* */ 8469 /* Returns: */ 8470 /* 0 for success, positive value for failure. */ 8471 /****************************************************************************/ 8472 static int 8473 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8474 { 8475 int error; 8476 int result; 8477 struct bce_softc *sc; 8478 8479 result = -1; 8480 error = sysctl_handle_int(oidp, &result, 0, req); 8481 8482 if (error || !req->newptr) 8483 return (error); 8484 8485 if (result == 1) { 8486 sc = (struct bce_softc *)arg1; 8487 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8488 } 8489 8490 return error; 8491 } 8492 8493 8494 /****************************************************************************/ 8495 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8496 /* */ 8497 /* Returns: */ 8498 /* 0 for success, positive value for failure. */ 8499 /****************************************************************************/ 8500 static int 8501 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8502 { 8503 int error; 8504 int result; 8505 struct bce_softc *sc; 8506 8507 result = -1; 8508 error = sysctl_handle_int(oidp, &result, 0, req); 8509 8510 if (error || !req->newptr) 8511 return (error); 8512 8513 if (result == 1) { 8514 sc = (struct bce_softc *)arg1; 8515 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8516 } 8517 8518 return error; 8519 } 8520 8521 8522 /****************************************************************************/ 8523 /* Provides a sysctl interface to allow dumping the TX chain. */ 8524 /* */ 8525 /* Returns: */ 8526 /* 0 for success, positive value for failure. */ 8527 /****************************************************************************/ 8528 static int 8529 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8530 { 8531 int error; 8532 int result; 8533 struct bce_softc *sc; 8534 8535 result = -1; 8536 error = sysctl_handle_int(oidp, &result, 0, req); 8537 8538 if (error || !req->newptr) 8539 return (error); 8540 8541 if (result == 1) { 8542 sc = (struct bce_softc *)arg1; 8543 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8544 } 8545 8546 return error; 8547 } 8548 8549 8550 /****************************************************************************/ 8551 /* Provides a sysctl interface to allow dumping the page chain. */ 8552 /* */ 8553 /* Returns: */ 8554 /* 0 for success, positive value for failure. */ 8555 /****************************************************************************/ 8556 static int 8557 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8558 { 8559 int error; 8560 int result; 8561 struct bce_softc *sc; 8562 8563 result = -1; 8564 error = sysctl_handle_int(oidp, &result, 0, req); 8565 8566 if (error || !req->newptr) 8567 return (error); 8568 8569 if (result == 1) { 8570 sc = (struct bce_softc *)arg1; 8571 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8572 } 8573 8574 return error; 8575 } 8576 8577 /****************************************************************************/ 8578 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8579 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8580 /* */ 8581 /* Returns: */ 8582 /* 0 for success, positive value for failure. */ 8583 /****************************************************************************/ 8584 static int 8585 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8586 { 8587 struct bce_softc *sc = (struct bce_softc *)arg1; 8588 int error; 8589 u32 result; 8590 u32 val[1]; 8591 u8 *data = (u8 *) val; 8592 8593 result = -1; 8594 error = sysctl_handle_int(oidp, &result, 0, req); 8595 if (error || (req->newptr == NULL)) 8596 return (error); 8597 8598 error = bce_nvram_read(sc, result, data, 4); 8599 8600 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8601 8602 return (error); 8603 } 8604 8605 8606 /****************************************************************************/ 8607 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8608 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8609 /* */ 8610 /* Returns: */ 8611 /* 0 for success, positive value for failure. */ 8612 /****************************************************************************/ 8613 static int 8614 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8615 { 8616 struct bce_softc *sc = (struct bce_softc *)arg1; 8617 int error; 8618 u32 val, result; 8619 8620 result = -1; 8621 error = sysctl_handle_int(oidp, &result, 0, req); 8622 if (error || (req->newptr == NULL)) 8623 return (error); 8624 8625 /* Make sure the register is accessible. */ 8626 if (result < 0x8000) { 8627 val = REG_RD(sc, result); 8628 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8629 } else if (result < 0x0280000) { 8630 val = REG_RD_IND(sc, result); 8631 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8632 } 8633 8634 return (error); 8635 } 8636 8637 8638 /****************************************************************************/ 8639 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8640 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8641 /* */ 8642 /* Returns: */ 8643 /* 0 for success, positive value for failure. */ 8644 /****************************************************************************/ 8645 static int 8646 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8647 { 8648 struct bce_softc *sc; 8649 device_t dev; 8650 int error, result; 8651 u16 val; 8652 8653 result = -1; 8654 error = sysctl_handle_int(oidp, &result, 0, req); 8655 if (error || (req->newptr == NULL)) 8656 return (error); 8657 8658 /* Make sure the register is accessible. */ 8659 if (result < 0x20) { 8660 sc = (struct bce_softc *)arg1; 8661 dev = sc->bce_dev; 8662 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8663 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8664 } 8665 return (error); 8666 } 8667 8668 8669 /****************************************************************************/ 8670 /* Provides a sysctl interface for dumping the nvram contents. */ 8671 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8672 /* */ 8673 /* Returns: */ 8674 /* 0 for success, positive errno for failure. */ 8675 /****************************************************************************/ 8676 static int 8677 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8678 { 8679 struct bce_softc *sc = (struct bce_softc *)arg1; 8680 int error, i; 8681 8682 if (sc->nvram_buf == NULL) 8683 sc->nvram_buf = malloc(sc->bce_flash_size, 8684 M_TEMP, M_ZERO | M_WAITOK); 8685 8686 error = 0; 8687 if (req->oldlen == sc->bce_flash_size) { 8688 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8689 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8690 } 8691 8692 if (error == 0) 8693 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8694 8695 return error; 8696 } 8697 8698 #ifdef BCE_NVRAM_WRITE_SUPPORT 8699 /****************************************************************************/ 8700 /* Provides a sysctl interface for writing to nvram. */ 8701 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8702 /* */ 8703 /* Returns: */ 8704 /* 0 for success, positive errno for failure. */ 8705 /****************************************************************************/ 8706 static int 8707 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8708 { 8709 struct bce_softc *sc = (struct bce_softc *)arg1; 8710 int error; 8711 8712 if (sc->nvram_buf == NULL) 8713 sc->nvram_buf = malloc(sc->bce_flash_size, 8714 M_TEMP, M_ZERO | M_WAITOK); 8715 else 8716 bzero(sc->nvram_buf, sc->bce_flash_size); 8717 8718 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 8719 if (error == 0) 8720 return (error); 8721 8722 if (req->newlen == sc->bce_flash_size) 8723 error = bce_nvram_write(sc, 0, sc->nvram_buf, 8724 sc->bce_flash_size); 8725 8726 8727 return error; 8728 } 8729 #endif 8730 8731 8732 /****************************************************************************/ 8733 /* Provides a sysctl interface to allow reading a CID. */ 8734 /* */ 8735 /* Returns: */ 8736 /* 0 for success, positive value for failure. */ 8737 /****************************************************************************/ 8738 static int 8739 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8740 { 8741 struct bce_softc *sc; 8742 int error, result; 8743 8744 result = -1; 8745 error = sysctl_handle_int(oidp, &result, 0, req); 8746 if (error || (req->newptr == NULL)) 8747 return (error); 8748 8749 /* Make sure the register is accessible. */ 8750 if (result <= TX_CID) { 8751 sc = (struct bce_softc *)arg1; 8752 bce_dump_ctx(sc, result); 8753 } 8754 8755 return (error); 8756 } 8757 8758 8759 /****************************************************************************/ 8760 /* Provides a sysctl interface to forcing the driver to dump state and */ 8761 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8762 /* */ 8763 /* Returns: */ 8764 /* 0 for success, positive value for failure. */ 8765 /****************************************************************************/ 8766 static int 8767 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8768 { 8769 int error; 8770 int result; 8771 struct bce_softc *sc; 8772 8773 result = -1; 8774 error = sysctl_handle_int(oidp, &result, 0, req); 8775 8776 if (error || !req->newptr) 8777 return (error); 8778 8779 if (result == 1) { 8780 sc = (struct bce_softc *)arg1; 8781 bce_breakpoint(sc); 8782 } 8783 8784 return error; 8785 } 8786 #endif 8787 8788 /****************************************************************************/ 8789 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8790 /* */ 8791 /* Returns: */ 8792 /* 0 for success, positive value for failure. */ 8793 /****************************************************************************/ 8794 static void 8795 bce_add_sysctls(struct bce_softc *sc) 8796 { 8797 struct sysctl_ctx_list *ctx; 8798 struct sysctl_oid_list *children; 8799 8800 DBENTER(BCE_VERBOSE_MISC); 8801 8802 ctx = device_get_sysctl_ctx(sc->bce_dev); 8803 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8804 8805 #ifdef BCE_DEBUG 8806 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8807 "l2fhdr_error_sim_control", 8808 CTLFLAG_RW, &l2fhdr_error_sim_control, 8809 0, "Debug control to force l2fhdr errors"); 8810 8811 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8812 "l2fhdr_error_sim_count", 8813 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8814 0, "Number of simulated l2_fhdr errors"); 8815 #endif 8816 8817 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8818 "l2fhdr_error_count", 8819 CTLFLAG_RD, &sc->l2fhdr_error_count, 8820 0, "Number of l2_fhdr errors"); 8821 8822 #ifdef BCE_DEBUG 8823 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8824 "mbuf_alloc_failed_sim_control", 8825 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8826 0, "Debug control to force mbuf allocation failures"); 8827 8828 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8829 "mbuf_alloc_failed_sim_count", 8830 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8831 0, "Number of simulated mbuf cluster allocation failures"); 8832 #endif 8833 8834 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8835 "mbuf_alloc_failed_count", 8836 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8837 0, "Number of mbuf allocation failures"); 8838 8839 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8840 "mbuf_frag_count", 8841 CTLFLAG_RD, &sc->mbuf_frag_count, 8842 0, "Number of fragmented mbufs"); 8843 8844 #ifdef BCE_DEBUG 8845 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8846 "dma_map_addr_failed_sim_control", 8847 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8848 0, "Debug control to force DMA mapping failures"); 8849 8850 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 8851 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8852 "dma_map_addr_failed_sim_count", 8853 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 8854 0, "Number of simulated DMA mapping failures"); 8855 8856 #endif 8857 8858 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8859 "dma_map_addr_rx_failed_count", 8860 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 8861 0, "Number of RX DMA mapping failures"); 8862 8863 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8864 "dma_map_addr_tx_failed_count", 8865 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 8866 0, "Number of TX DMA mapping failures"); 8867 8868 #ifdef BCE_DEBUG 8869 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8870 "unexpected_attention_sim_control", 8871 CTLFLAG_RW, &unexpected_attention_sim_control, 8872 0, "Debug control to simulate unexpected attentions"); 8873 8874 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8875 "unexpected_attention_sim_count", 8876 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 8877 0, "Number of simulated unexpected attentions"); 8878 #endif 8879 8880 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8881 "unexpected_attention_count", 8882 CTLFLAG_RW, &sc->unexpected_attention_count, 8883 0, "Number of unexpected attentions"); 8884 8885 #ifdef BCE_DEBUG 8886 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8887 "debug_bootcode_running_failure", 8888 CTLFLAG_RW, &bootcode_running_failure_sim_control, 8889 0, "Debug control to force bootcode running failures"); 8890 8891 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8892 "rx_low_watermark", 8893 CTLFLAG_RD, &sc->rx_low_watermark, 8894 0, "Lowest level of free rx_bd's"); 8895 8896 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8897 "rx_empty_count", 8898 CTLFLAG_RD, &sc->rx_empty_count, 8899 "Number of times the RX chain was empty"); 8900 8901 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8902 "tx_hi_watermark", 8903 CTLFLAG_RD, &sc->tx_hi_watermark, 8904 0, "Highest level of used tx_bd's"); 8905 8906 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8907 "tx_full_count", 8908 CTLFLAG_RD, &sc->tx_full_count, 8909 "Number of times the TX chain was full"); 8910 8911 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8912 "tso_frames_requested", 8913 CTLFLAG_RD, &sc->tso_frames_requested, 8914 "Number of TSO frames requested"); 8915 8916 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8917 "tso_frames_completed", 8918 CTLFLAG_RD, &sc->tso_frames_completed, 8919 "Number of TSO frames completed"); 8920 8921 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8922 "tso_frames_failed", 8923 CTLFLAG_RD, &sc->tso_frames_failed, 8924 "Number of TSO frames failed"); 8925 8926 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8927 "csum_offload_ip", 8928 CTLFLAG_RD, &sc->csum_offload_ip, 8929 "Number of IP checksum offload frames"); 8930 8931 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8932 "csum_offload_tcp_udp", 8933 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 8934 "Number of TCP/UDP checksum offload frames"); 8935 8936 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8937 "vlan_tagged_frames_rcvd", 8938 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 8939 "Number of VLAN tagged frames received"); 8940 8941 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8942 "vlan_tagged_frames_stripped", 8943 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 8944 "Number of VLAN tagged frames stripped"); 8945 8946 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8947 "interrupts_rx", 8948 CTLFLAG_RD, &sc->interrupts_rx, 8949 "Number of RX interrupts"); 8950 8951 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8952 "interrupts_tx", 8953 CTLFLAG_RD, &sc->interrupts_tx, 8954 "Number of TX interrupts"); 8955 8956 if (bce_hdr_split == TRUE) { 8957 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8958 "split_header_frames_rcvd", 8959 CTLFLAG_RD, &sc->split_header_frames_rcvd, 8960 "Number of split header frames received"); 8961 8962 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8963 "split_header_tcp_frames_rcvd", 8964 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 8965 "Number of split header TCP frames received"); 8966 } 8967 8968 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8969 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 8970 (void *)sc, 0, 8971 bce_sysctl_nvram_dump, "S", ""); 8972 8973 #ifdef BCE_NVRAM_WRITE_SUPPORT 8974 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8975 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 8976 (void *)sc, 0, 8977 bce_sysctl_nvram_write, "S", ""); 8978 #endif 8979 #endif /* BCE_DEBUG */ 8980 8981 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8982 "stat_IfHcInOctets", 8983 CTLFLAG_RD, &sc->stat_IfHCInOctets, 8984 "Bytes received"); 8985 8986 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8987 "stat_IfHCInBadOctets", 8988 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 8989 "Bad bytes received"); 8990 8991 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8992 "stat_IfHCOutOctets", 8993 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 8994 "Bytes sent"); 8995 8996 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8997 "stat_IfHCOutBadOctets", 8998 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 8999 "Bad bytes sent"); 9000 9001 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9002 "stat_IfHCInUcastPkts", 9003 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9004 "Unicast packets received"); 9005 9006 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9007 "stat_IfHCInMulticastPkts", 9008 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9009 "Multicast packets received"); 9010 9011 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9012 "stat_IfHCInBroadcastPkts", 9013 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9014 "Broadcast packets received"); 9015 9016 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9017 "stat_IfHCOutUcastPkts", 9018 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9019 "Unicast packets sent"); 9020 9021 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9022 "stat_IfHCOutMulticastPkts", 9023 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9024 "Multicast packets sent"); 9025 9026 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9027 "stat_IfHCOutBroadcastPkts", 9028 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9029 "Broadcast packets sent"); 9030 9031 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9032 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9033 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9034 0, "Internal MAC transmit errors"); 9035 9036 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9037 "stat_Dot3StatsCarrierSenseErrors", 9038 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9039 0, "Carrier sense errors"); 9040 9041 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9042 "stat_Dot3StatsFCSErrors", 9043 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9044 0, "Frame check sequence errors"); 9045 9046 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9047 "stat_Dot3StatsAlignmentErrors", 9048 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9049 0, "Alignment errors"); 9050 9051 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9052 "stat_Dot3StatsSingleCollisionFrames", 9053 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9054 0, "Single Collision Frames"); 9055 9056 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9057 "stat_Dot3StatsMultipleCollisionFrames", 9058 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9059 0, "Multiple Collision Frames"); 9060 9061 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9062 "stat_Dot3StatsDeferredTransmissions", 9063 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9064 0, "Deferred Transmissions"); 9065 9066 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9067 "stat_Dot3StatsExcessiveCollisions", 9068 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9069 0, "Excessive Collisions"); 9070 9071 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9072 "stat_Dot3StatsLateCollisions", 9073 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9074 0, "Late Collisions"); 9075 9076 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9077 "stat_EtherStatsCollisions", 9078 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9079 0, "Collisions"); 9080 9081 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9082 "stat_EtherStatsFragments", 9083 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9084 0, "Fragments"); 9085 9086 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9087 "stat_EtherStatsJabbers", 9088 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9089 0, "Jabbers"); 9090 9091 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9092 "stat_EtherStatsUndersizePkts", 9093 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9094 0, "Undersize packets"); 9095 9096 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9097 "stat_EtherStatsOversizePkts", 9098 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9099 0, "stat_EtherStatsOversizePkts"); 9100 9101 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9102 "stat_EtherStatsPktsRx64Octets", 9103 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9104 0, "Bytes received in 64 byte packets"); 9105 9106 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9107 "stat_EtherStatsPktsRx65Octetsto127Octets", 9108 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9109 0, "Bytes received in 65 to 127 byte packets"); 9110 9111 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9112 "stat_EtherStatsPktsRx128Octetsto255Octets", 9113 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9114 0, "Bytes received in 128 to 255 byte packets"); 9115 9116 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9117 "stat_EtherStatsPktsRx256Octetsto511Octets", 9118 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9119 0, "Bytes received in 256 to 511 byte packets"); 9120 9121 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9122 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9123 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9124 0, "Bytes received in 512 to 1023 byte packets"); 9125 9126 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9127 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9128 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9129 0, "Bytes received in 1024 t0 1522 byte packets"); 9130 9131 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9132 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9133 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9134 0, "Bytes received in 1523 to 9022 byte packets"); 9135 9136 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9137 "stat_EtherStatsPktsTx64Octets", 9138 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9139 0, "Bytes sent in 64 byte packets"); 9140 9141 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9142 "stat_EtherStatsPktsTx65Octetsto127Octets", 9143 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9144 0, "Bytes sent in 65 to 127 byte packets"); 9145 9146 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9147 "stat_EtherStatsPktsTx128Octetsto255Octets", 9148 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9149 0, "Bytes sent in 128 to 255 byte packets"); 9150 9151 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9152 "stat_EtherStatsPktsTx256Octetsto511Octets", 9153 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9154 0, "Bytes sent in 256 to 511 byte packets"); 9155 9156 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9157 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9158 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9159 0, "Bytes sent in 512 to 1023 byte packets"); 9160 9161 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9162 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9163 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9164 0, "Bytes sent in 1024 to 1522 byte packets"); 9165 9166 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9167 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9168 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9169 0, "Bytes sent in 1523 to 9022 byte packets"); 9170 9171 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9172 "stat_XonPauseFramesReceived", 9173 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9174 0, "XON pause frames receved"); 9175 9176 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9177 "stat_XoffPauseFramesReceived", 9178 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9179 0, "XOFF pause frames received"); 9180 9181 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9182 "stat_OutXonSent", 9183 CTLFLAG_RD, &sc->stat_OutXonSent, 9184 0, "XON pause frames sent"); 9185 9186 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9187 "stat_OutXoffSent", 9188 CTLFLAG_RD, &sc->stat_OutXoffSent, 9189 0, "XOFF pause frames sent"); 9190 9191 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9192 "stat_FlowControlDone", 9193 CTLFLAG_RD, &sc->stat_FlowControlDone, 9194 0, "Flow control done"); 9195 9196 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9197 "stat_MacControlFramesReceived", 9198 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9199 0, "MAC control frames received"); 9200 9201 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9202 "stat_XoffStateEntered", 9203 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9204 0, "XOFF state entered"); 9205 9206 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9207 "stat_IfInFramesL2FilterDiscards", 9208 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9209 0, "Received L2 packets discarded"); 9210 9211 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9212 "stat_IfInRuleCheckerDiscards", 9213 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9214 0, "Received packets discarded by rule"); 9215 9216 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9217 "stat_IfInFTQDiscards", 9218 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9219 0, "Received packet FTQ discards"); 9220 9221 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9222 "stat_IfInMBUFDiscards", 9223 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9224 0, "Received packets discarded due to lack " 9225 "of controller buffer memory"); 9226 9227 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9228 "stat_IfInRuleCheckerP4Hit", 9229 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9230 0, "Received packets rule checker hits"); 9231 9232 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9233 "stat_CatchupInRuleCheckerDiscards", 9234 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9235 0, "Received packets discarded in Catchup path"); 9236 9237 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9238 "stat_CatchupInFTQDiscards", 9239 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9240 0, "Received packets discarded in FTQ in Catchup path"); 9241 9242 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9243 "stat_CatchupInMBUFDiscards", 9244 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9245 0, "Received packets discarded in controller " 9246 "buffer memory in Catchup path"); 9247 9248 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9249 "stat_CatchupInRuleCheckerP4Hit", 9250 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9251 0, "Received packets rule checker hits in Catchup path"); 9252 9253 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9254 "com_no_buffers", 9255 CTLFLAG_RD, &sc->com_no_buffers, 9256 0, "Valid packets received but no RX buffers available"); 9257 9258 #ifdef BCE_DEBUG 9259 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9260 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9261 (void *)sc, 0, 9262 bce_sysctl_driver_state, "I", "Drive state information"); 9263 9264 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9265 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9266 (void *)sc, 0, 9267 bce_sysctl_hw_state, "I", "Hardware state information"); 9268 9269 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9270 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9271 (void *)sc, 0, 9272 bce_sysctl_status_block, "I", "Dump status block"); 9273 9274 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9275 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9276 (void *)sc, 0, 9277 bce_sysctl_stats_block, "I", "Dump statistics block"); 9278 9279 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9280 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9281 (void *)sc, 0, 9282 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9283 9284 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9285 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9286 (void *)sc, 0, 9287 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9288 9289 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9290 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9291 (void *)sc, 0, 9292 bce_sysctl_bc_state, "I", "Bootcode state information"); 9293 9294 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9295 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9296 (void *)sc, 0, 9297 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9298 9299 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9300 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9301 (void *)sc, 0, 9302 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9303 9304 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9305 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9306 (void *)sc, 0, 9307 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9308 9309 if (bce_hdr_split == TRUE) { 9310 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9311 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9312 (void *)sc, 0, 9313 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9314 } 9315 9316 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9317 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9318 (void *)sc, 0, 9319 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9320 9321 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9322 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9323 (void *)sc, 0, 9324 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9325 9326 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9327 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9328 (void *)sc, 0, 9329 bce_sysctl_reg_read, "I", "Register read"); 9330 9331 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9332 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9333 (void *)sc, 0, 9334 bce_sysctl_nvram_read, "I", "NVRAM read"); 9335 9336 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9337 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9338 (void *)sc, 0, 9339 bce_sysctl_phy_read, "I", "PHY register read"); 9340 9341 #endif 9342 9343 DBEXIT(BCE_VERBOSE_MISC); 9344 } 9345 9346 9347 /****************************************************************************/ 9348 /* BCE Debug Routines */ 9349 /****************************************************************************/ 9350 #ifdef BCE_DEBUG 9351 9352 /****************************************************************************/ 9353 /* Freezes the controller to allow for a cohesive state dump. */ 9354 /* */ 9355 /* Returns: */ 9356 /* Nothing. */ 9357 /****************************************************************************/ 9358 static __attribute__ ((noinline)) void 9359 bce_freeze_controller(struct bce_softc *sc) 9360 { 9361 u32 val; 9362 val = REG_RD(sc, BCE_MISC_COMMAND); 9363 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9364 REG_WR(sc, BCE_MISC_COMMAND, val); 9365 } 9366 9367 9368 /****************************************************************************/ 9369 /* Unfreezes the controller after a freeze operation. This may not always */ 9370 /* work and the controller will require a reset! */ 9371 /* */ 9372 /* Returns: */ 9373 /* Nothing. */ 9374 /****************************************************************************/ 9375 static __attribute__ ((noinline)) void 9376 bce_unfreeze_controller(struct bce_softc *sc) 9377 { 9378 u32 val; 9379 val = REG_RD(sc, BCE_MISC_COMMAND); 9380 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9381 REG_WR(sc, BCE_MISC_COMMAND, val); 9382 } 9383 9384 9385 /****************************************************************************/ 9386 /* Prints out Ethernet frame information from an mbuf. */ 9387 /* */ 9388 /* Partially decode an Ethernet frame to look at some important headers. */ 9389 /* */ 9390 /* Returns: */ 9391 /* Nothing. */ 9392 /****************************************************************************/ 9393 static __attribute__ ((noinline)) void 9394 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9395 { 9396 struct ether_vlan_header *eh; 9397 u16 etype; 9398 int ehlen; 9399 struct ip *ip; 9400 struct tcphdr *th; 9401 struct udphdr *uh; 9402 struct arphdr *ah; 9403 9404 BCE_PRINTF( 9405 "-----------------------------" 9406 " Frame Decode " 9407 "-----------------------------\n"); 9408 9409 eh = mtod(m, struct ether_vlan_header *); 9410 9411 /* Handle VLAN encapsulation if present. */ 9412 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9413 etype = ntohs(eh->evl_proto); 9414 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9415 } else { 9416 etype = ntohs(eh->evl_encap_proto); 9417 ehlen = ETHER_HDR_LEN; 9418 } 9419 9420 /* ToDo: Add VLAN output. */ 9421 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9422 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9423 9424 switch (etype) { 9425 case ETHERTYPE_IP: 9426 ip = (struct ip *)(m->m_data + ehlen); 9427 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9428 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9429 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9430 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9431 9432 switch (ip->ip_p) { 9433 case IPPROTO_TCP: 9434 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9435 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9436 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9437 ntohs(th->th_dport), ntohs(th->th_sport), 9438 (th->th_off << 2), th->th_flags, 9439 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9440 "\02SYN\01FIN", ntohs(th->th_sum)); 9441 break; 9442 case IPPROTO_UDP: 9443 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9444 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9445 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9446 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9447 ntohs(uh->uh_sum)); 9448 break; 9449 case IPPROTO_ICMP: 9450 BCE_PRINTF("icmp:\n"); 9451 break; 9452 default: 9453 BCE_PRINTF("----: Other IP protocol.\n"); 9454 } 9455 break; 9456 case ETHERTYPE_IPV6: 9457 BCE_PRINTF("ipv6: No decode supported.\n"); 9458 break; 9459 case ETHERTYPE_ARP: 9460 BCE_PRINTF("-arp: "); 9461 ah = (struct arphdr *) (m->m_data + ehlen); 9462 switch (ntohs(ah->ar_op)) { 9463 case ARPOP_REVREQUEST: 9464 printf("reverse ARP request\n"); 9465 break; 9466 case ARPOP_REVREPLY: 9467 printf("reverse ARP reply\n"); 9468 break; 9469 case ARPOP_REQUEST: 9470 printf("ARP request\n"); 9471 break; 9472 case ARPOP_REPLY: 9473 printf("ARP reply\n"); 9474 break; 9475 default: 9476 printf("other ARP operation\n"); 9477 } 9478 break; 9479 default: 9480 BCE_PRINTF("----: Other protocol.\n"); 9481 } 9482 9483 BCE_PRINTF( 9484 "-----------------------------" 9485 "--------------" 9486 "-----------------------------\n"); 9487 } 9488 9489 9490 /****************************************************************************/ 9491 /* Prints out information about an mbuf. */ 9492 /* */ 9493 /* Returns: */ 9494 /* Nothing. */ 9495 /****************************************************************************/ 9496 static __attribute__ ((noinline)) void 9497 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9498 { 9499 struct mbuf *mp = m; 9500 9501 if (m == NULL) { 9502 BCE_PRINTF("mbuf: null pointer\n"); 9503 return; 9504 } 9505 9506 while (mp) { 9507 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9508 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9509 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9510 9511 if (mp->m_flags & M_PKTHDR) { 9512 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9513 "csum_flags = %b\n", mp->m_pkthdr.len, 9514 mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" 9515 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9516 "\22M_PROMISC\23M_NOFREE", 9517 mp->m_pkthdr.csum_flags, 9518 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 9519 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9520 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9521 "\14CSUM_PSEUDO_HDR"); 9522 } 9523 9524 if (mp->m_flags & M_EXT) { 9525 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9526 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9527 switch (mp->m_ext.ext_type) { 9528 case EXT_CLUSTER: 9529 printf("EXT_CLUSTER\n"); break; 9530 case EXT_SFBUF: 9531 printf("EXT_SFBUF\n"); break; 9532 case EXT_JUMBO9: 9533 printf("EXT_JUMBO9\n"); break; 9534 case EXT_JUMBO16: 9535 printf("EXT_JUMBO16\n"); break; 9536 case EXT_PACKET: 9537 printf("EXT_PACKET\n"); break; 9538 case EXT_MBUF: 9539 printf("EXT_MBUF\n"); break; 9540 case EXT_NET_DRV: 9541 printf("EXT_NET_DRV\n"); break; 9542 case EXT_MOD_TYPE: 9543 printf("EXT_MDD_TYPE\n"); break; 9544 case EXT_DISPOSABLE: 9545 printf("EXT_DISPOSABLE\n"); break; 9546 case EXT_EXTREF: 9547 printf("EXT_EXTREF\n"); break; 9548 default: 9549 printf("UNKNOWN\n"); 9550 } 9551 } 9552 9553 mp = mp->m_next; 9554 } 9555 } 9556 9557 9558 /****************************************************************************/ 9559 /* Prints out the mbufs in the TX mbuf chain. */ 9560 /* */ 9561 /* Returns: */ 9562 /* Nothing. */ 9563 /****************************************************************************/ 9564 static __attribute__ ((noinline)) void 9565 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9566 { 9567 struct mbuf *m; 9568 9569 BCE_PRINTF( 9570 "----------------------------" 9571 " tx mbuf data " 9572 "----------------------------\n"); 9573 9574 for (int i = 0; i < count; i++) { 9575 m = sc->tx_mbuf_ptr[chain_prod]; 9576 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9577 bce_dump_mbuf(sc, m); 9578 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9579 } 9580 9581 BCE_PRINTF( 9582 "----------------------------" 9583 "----------------" 9584 "----------------------------\n"); 9585 } 9586 9587 9588 /****************************************************************************/ 9589 /* Prints out the mbufs in the RX mbuf chain. */ 9590 /* */ 9591 /* Returns: */ 9592 /* Nothing. */ 9593 /****************************************************************************/ 9594 static __attribute__ ((noinline)) void 9595 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9596 { 9597 struct mbuf *m; 9598 9599 BCE_PRINTF( 9600 "----------------------------" 9601 " rx mbuf data " 9602 "----------------------------\n"); 9603 9604 for (int i = 0; i < count; i++) { 9605 m = sc->rx_mbuf_ptr[chain_prod]; 9606 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9607 bce_dump_mbuf(sc, m); 9608 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9609 } 9610 9611 9612 BCE_PRINTF( 9613 "----------------------------" 9614 "----------------" 9615 "----------------------------\n"); 9616 } 9617 9618 9619 /****************************************************************************/ 9620 /* Prints out the mbufs in the mbuf page chain. */ 9621 /* */ 9622 /* Returns: */ 9623 /* Nothing. */ 9624 /****************************************************************************/ 9625 static __attribute__ ((noinline)) void 9626 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9627 { 9628 struct mbuf *m; 9629 9630 BCE_PRINTF( 9631 "----------------------------" 9632 " pg mbuf data " 9633 "----------------------------\n"); 9634 9635 for (int i = 0; i < count; i++) { 9636 m = sc->pg_mbuf_ptr[chain_prod]; 9637 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9638 bce_dump_mbuf(sc, m); 9639 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9640 } 9641 9642 9643 BCE_PRINTF( 9644 "----------------------------" 9645 "----------------" 9646 "----------------------------\n"); 9647 } 9648 9649 9650 /****************************************************************************/ 9651 /* Prints out a tx_bd structure. */ 9652 /* */ 9653 /* Returns: */ 9654 /* Nothing. */ 9655 /****************************************************************************/ 9656 static __attribute__ ((noinline)) void 9657 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9658 { 9659 int i = 0; 9660 9661 if (idx > MAX_TX_BD_ALLOC) 9662 /* Index out of range. */ 9663 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9664 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9665 /* TX Chain page pointer. */ 9666 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9667 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9668 txbd->tx_bd_haddr_lo); 9669 else { 9670 /* Normal tx_bd entry. */ 9671 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9672 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9673 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9674 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9675 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9676 9677 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9678 if (i>0) 9679 printf("|"); 9680 printf("CONN_FAULT"); 9681 i++; 9682 } 9683 9684 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9685 if (i>0) 9686 printf("|"); 9687 printf("TCP_UDP_CKSUM"); 9688 i++; 9689 } 9690 9691 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9692 if (i>0) 9693 printf("|"); 9694 printf("IP_CKSUM"); 9695 i++; 9696 } 9697 9698 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9699 if (i>0) 9700 printf("|"); 9701 printf("VLAN"); 9702 i++; 9703 } 9704 9705 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9706 if (i>0) 9707 printf("|"); 9708 printf("COAL_NOW"); 9709 i++; 9710 } 9711 9712 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9713 if (i>0) 9714 printf("|"); 9715 printf("DONT_GEN_CRC"); 9716 i++; 9717 } 9718 9719 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9720 if (i>0) 9721 printf("|"); 9722 printf("START"); 9723 i++; 9724 } 9725 9726 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9727 if (i>0) 9728 printf("|"); 9729 printf("END"); 9730 i++; 9731 } 9732 9733 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9734 if (i>0) 9735 printf("|"); 9736 printf("LSO"); 9737 i++; 9738 } 9739 9740 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9741 if (i>0) 9742 printf("|"); 9743 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9744 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9745 } 9746 9747 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9748 if (i>0) 9749 printf("|"); 9750 printf("SW_FLAGS"); 9751 i++; 9752 } 9753 9754 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9755 if (i>0) 9756 printf("|"); 9757 printf("SNAP)"); 9758 } else { 9759 printf(")\n"); 9760 } 9761 } 9762 } 9763 9764 9765 /****************************************************************************/ 9766 /* Prints out a rx_bd structure. */ 9767 /* */ 9768 /* Returns: */ 9769 /* Nothing. */ 9770 /****************************************************************************/ 9771 static __attribute__ ((noinline)) void 9772 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9773 { 9774 if (idx > MAX_RX_BD_ALLOC) 9775 /* Index out of range. */ 9776 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9777 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9778 /* RX Chain page pointer. */ 9779 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9780 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9781 rxbd->rx_bd_haddr_lo); 9782 else 9783 /* Normal rx_bd entry. */ 9784 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9785 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9786 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9787 rxbd->rx_bd_flags); 9788 } 9789 9790 9791 /****************************************************************************/ 9792 /* Prints out a rx_bd structure in the page chain. */ 9793 /* */ 9794 /* Returns: */ 9795 /* Nothing. */ 9796 /****************************************************************************/ 9797 static __attribute__ ((noinline)) void 9798 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9799 { 9800 if (idx > MAX_PG_BD_ALLOC) 9801 /* Index out of range. */ 9802 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9803 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9804 /* Page Chain page pointer. */ 9805 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9806 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9807 else 9808 /* Normal rx_bd entry. */ 9809 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9810 "flags = 0x%08X\n", idx, 9811 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9812 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9813 } 9814 9815 9816 /****************************************************************************/ 9817 /* Prints out a l2_fhdr structure. */ 9818 /* */ 9819 /* Returns: */ 9820 /* Nothing. */ 9821 /****************************************************************************/ 9822 static __attribute__ ((noinline)) void 9823 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9824 { 9825 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9826 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9827 "tcp_udp_xsum = 0x%04X\n", idx, 9828 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9829 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9830 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9831 } 9832 9833 9834 /****************************************************************************/ 9835 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9836 /* */ 9837 /* Returns: */ 9838 /* Nothing. */ 9839 /****************************************************************************/ 9840 static __attribute__ ((noinline)) void 9841 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9842 { 9843 if (cid > TX_CID) { 9844 BCE_PRINTF(" Unknown CID\n"); 9845 return; 9846 } 9847 9848 BCE_PRINTF( 9849 "----------------------------" 9850 " CTX Data " 9851 "----------------------------\n"); 9852 9853 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9854 9855 if (cid == RX_CID) { 9856 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9857 "producer index\n", 9858 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9859 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 9860 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9861 BCE_L2CTX_RX_HOST_BSEQ)); 9862 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9863 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9864 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9865 "descriptor address\n", 9866 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9867 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9868 "descriptor address\n", 9869 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 9870 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 9871 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9872 BCE_L2CTX_RX_NX_BDIDX)); 9873 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 9874 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9875 BCE_L2CTX_RX_HOST_PG_BDIDX)); 9876 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 9877 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 9878 BCE_L2CTX_RX_PG_BUF_SIZE)); 9879 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 9880 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9881 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 9882 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 9883 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9884 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 9885 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 9886 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9887 BCE_L2CTX_RX_NX_PG_BDIDX)); 9888 } else if (cid == TX_CID) { 9889 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 9890 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 9891 CTX_RD(sc, GET_CID_ADDR(cid), 9892 BCE_L2CTX_TX_TYPE_XI)); 9893 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 9894 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 9895 BCE_L2CTX_TX_CMD_TYPE_XI)); 9896 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 9897 "h/w buffer descriptor address\n", 9898 CTX_RD(sc, GET_CID_ADDR(cid), 9899 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 9900 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 9901 "h/w buffer descriptor address\n", 9902 CTX_RD(sc, GET_CID_ADDR(cid), 9903 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 9904 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 9905 "host producer index\n", 9906 CTX_RD(sc, GET_CID_ADDR(cid), 9907 BCE_L2CTX_TX_HOST_BIDX_XI)); 9908 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 9909 "host byte sequence\n", 9910 CTX_RD(sc, GET_CID_ADDR(cid), 9911 BCE_L2CTX_TX_HOST_BSEQ_XI)); 9912 } else { 9913 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 9914 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 9915 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 9916 CTX_RD(sc, GET_CID_ADDR(cid), 9917 BCE_L2CTX_TX_CMD_TYPE)); 9918 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 9919 "h/w buffer descriptor address\n", 9920 CTX_RD(sc, GET_CID_ADDR(cid), 9921 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 9922 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 9923 "h/w buffer descriptor address\n", 9924 CTX_RD(sc, GET_CID_ADDR(cid), 9925 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 9926 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 9927 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9928 BCE_L2CTX_TX_HOST_BIDX)); 9929 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 9930 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9931 BCE_L2CTX_TX_HOST_BSEQ)); 9932 } 9933 } 9934 9935 BCE_PRINTF( 9936 "----------------------------" 9937 " Raw CTX " 9938 "----------------------------\n"); 9939 9940 for (int i = 0x0; i < 0x300; i += 0x10) { 9941 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 9942 CTX_RD(sc, GET_CID_ADDR(cid), i), 9943 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 9944 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 9945 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 9946 } 9947 9948 9949 BCE_PRINTF( 9950 "----------------------------" 9951 "----------------" 9952 "----------------------------\n"); 9953 } 9954 9955 9956 /****************************************************************************/ 9957 /* Prints out the FTQ data. */ 9958 /* */ 9959 /* Returns: */ 9960 /* Nothing. */ 9961 /****************************************************************************/ 9962 static __attribute__ ((noinline)) void 9963 bce_dump_ftqs(struct bce_softc *sc) 9964 { 9965 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 9966 9967 BCE_PRINTF( 9968 "----------------------------" 9969 " FTQ Data " 9970 "----------------------------\n"); 9971 9972 BCE_PRINTF(" FTQ Command Control Depth_Now " 9973 "Max_Depth Valid_Cnt \n"); 9974 BCE_PRINTF(" ------- ---------- ---------- ---------- " 9975 "---------- ----------\n"); 9976 9977 /* Setup the generic statistic counters for the FTQ valid count. */ 9978 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 9979 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 9980 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 9981 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 9982 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9983 9984 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 9985 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 9986 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 9987 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 9988 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 9989 9990 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 9991 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 9992 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 9993 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 9994 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 9995 9996 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 9997 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 9998 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 9999 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10000 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10001 10002 /* Input queue to the Receive Lookup state machine */ 10003 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10004 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10005 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10006 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10007 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10008 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10009 cmd, ctl, cur_depth, max_depth, valid_cnt); 10010 10011 /* Input queue to the Receive Processor */ 10012 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10013 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10014 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10015 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10016 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10017 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10018 cmd, ctl, cur_depth, max_depth, valid_cnt); 10019 10020 /* Input queue to the Recevie Processor */ 10021 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10022 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10023 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10024 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10025 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10026 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10027 cmd, ctl, cur_depth, max_depth, valid_cnt); 10028 10029 /* Input queue to the Receive Virtual to Physical state machine */ 10030 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10031 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10032 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10033 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10034 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10035 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10036 cmd, ctl, cur_depth, max_depth, valid_cnt); 10037 10038 /* Input queue to the Recevie Virtual to Physical state machine */ 10039 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10040 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10041 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10042 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10043 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10044 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10045 cmd, ctl, cur_depth, max_depth, valid_cnt); 10046 10047 /* Input queue to the Receive Virtual to Physical state machine */ 10048 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10049 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10050 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10051 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10052 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10053 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10054 cmd, ctl, cur_depth, max_depth, valid_cnt); 10055 10056 /* Input queue to the Receive DMA state machine */ 10057 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10058 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10059 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10060 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10061 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10062 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10063 cmd, ctl, cur_depth, max_depth, valid_cnt); 10064 10065 /* Input queue to the Transmit Scheduler state machine */ 10066 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10067 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10068 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10069 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10070 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10071 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10072 cmd, ctl, cur_depth, max_depth, valid_cnt); 10073 10074 /* Input queue to the Transmit Buffer Descriptor state machine */ 10075 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10076 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10077 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10078 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10079 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10080 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10081 cmd, ctl, cur_depth, max_depth, valid_cnt); 10082 10083 /* Input queue to the Transmit Processor */ 10084 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10085 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10086 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10087 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10088 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10089 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10090 cmd, ctl, cur_depth, max_depth, valid_cnt); 10091 10092 /* Input queue to the Transmit DMA state machine */ 10093 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10094 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10095 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10096 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10097 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10098 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10099 cmd, ctl, cur_depth, max_depth, valid_cnt); 10100 10101 /* Input queue to the Transmit Patch-Up Processor */ 10102 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10103 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10104 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10105 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10106 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10107 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10108 cmd, ctl, cur_depth, max_depth, valid_cnt); 10109 10110 /* Input queue to the Transmit Assembler state machine */ 10111 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10112 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10113 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10114 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10115 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10116 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10117 cmd, ctl, cur_depth, max_depth, valid_cnt); 10118 10119 /* Input queue to the Completion Processor */ 10120 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10121 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10122 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10123 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10124 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10125 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10126 cmd, ctl, cur_depth, max_depth, valid_cnt); 10127 10128 /* Input queue to the Completion Processor */ 10129 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10130 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10131 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10132 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10133 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10134 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10135 cmd, ctl, cur_depth, max_depth, valid_cnt); 10136 10137 /* Input queue to the Completion Processor */ 10138 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10139 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10140 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10141 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10142 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10143 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10144 cmd, ctl, cur_depth, max_depth, valid_cnt); 10145 10146 /* Setup the generic statistic counters for the FTQ valid count. */ 10147 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10148 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10149 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10150 10151 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10152 val = val | 10153 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10154 24); 10155 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10156 10157 /* Input queue to the Management Control Processor */ 10158 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10159 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10160 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10161 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10162 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10163 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10164 cmd, ctl, cur_depth, max_depth, valid_cnt); 10165 10166 /* Input queue to the Command Processor */ 10167 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10168 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10169 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10170 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10171 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10172 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10173 cmd, ctl, cur_depth, max_depth, valid_cnt); 10174 10175 /* Input queue to the Completion Scheduler state machine */ 10176 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10177 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10178 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10179 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10180 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10181 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10182 cmd, ctl, cur_depth, max_depth, valid_cnt); 10183 10184 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10185 /* Input queue to the RV2P Command Scheduler */ 10186 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10187 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10188 cur_depth = (ctl & 0xFFC00000) >> 22; 10189 max_depth = (ctl & 0x003FF000) >> 12; 10190 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10191 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10192 cmd, ctl, cur_depth, max_depth, valid_cnt); 10193 } 10194 10195 BCE_PRINTF( 10196 "----------------------------" 10197 "----------------" 10198 "----------------------------\n"); 10199 } 10200 10201 10202 /****************************************************************************/ 10203 /* Prints out the TX chain. */ 10204 /* */ 10205 /* Returns: */ 10206 /* Nothing. */ 10207 /****************************************************************************/ 10208 static __attribute__ ((noinline)) void 10209 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10210 { 10211 struct tx_bd *txbd; 10212 10213 /* First some info about the tx_bd chain structure. */ 10214 BCE_PRINTF( 10215 "----------------------------" 10216 " tx_bd chain " 10217 "----------------------------\n"); 10218 10219 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10220 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10221 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10222 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10223 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10224 10225 BCE_PRINTF( 10226 "----------------------------" 10227 " tx_bd data " 10228 "----------------------------\n"); 10229 10230 /* Now print out a decoded list of TX buffer descriptors. */ 10231 for (int i = 0; i < count; i++) { 10232 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10233 bce_dump_txbd(sc, tx_prod, txbd); 10234 tx_prod++; 10235 } 10236 10237 BCE_PRINTF( 10238 "----------------------------" 10239 "----------------" 10240 "----------------------------\n"); 10241 } 10242 10243 10244 /****************************************************************************/ 10245 /* Prints out the RX chain. */ 10246 /* */ 10247 /* Returns: */ 10248 /* Nothing. */ 10249 /****************************************************************************/ 10250 static __attribute__ ((noinline)) void 10251 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10252 { 10253 struct rx_bd *rxbd; 10254 10255 /* First some info about the rx_bd chain structure. */ 10256 BCE_PRINTF( 10257 "----------------------------" 10258 " rx_bd chain " 10259 "----------------------------\n"); 10260 10261 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10262 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10263 10264 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10265 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10266 10267 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10268 10269 BCE_PRINTF( 10270 "----------------------------" 10271 " rx_bd data " 10272 "----------------------------\n"); 10273 10274 /* Now print out the rx_bd's themselves. */ 10275 for (int i = 0; i < count; i++) { 10276 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10277 bce_dump_rxbd(sc, rx_prod, rxbd); 10278 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10279 } 10280 10281 BCE_PRINTF( 10282 "----------------------------" 10283 "----------------" 10284 "----------------------------\n"); 10285 } 10286 10287 10288 /****************************************************************************/ 10289 /* Prints out the page chain. */ 10290 /* */ 10291 /* Returns: */ 10292 /* Nothing. */ 10293 /****************************************************************************/ 10294 static __attribute__ ((noinline)) void 10295 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10296 { 10297 struct rx_bd *pgbd; 10298 10299 /* First some info about the page chain structure. */ 10300 BCE_PRINTF( 10301 "----------------------------" 10302 " page chain " 10303 "----------------------------\n"); 10304 10305 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10306 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10307 10308 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10309 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10310 10311 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10312 10313 BCE_PRINTF( 10314 "----------------------------" 10315 " page data " 10316 "----------------------------\n"); 10317 10318 /* Now print out the rx_bd's themselves. */ 10319 for (int i = 0; i < count; i++) { 10320 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10321 bce_dump_pgbd(sc, pg_prod, pgbd); 10322 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10323 } 10324 10325 BCE_PRINTF( 10326 "----------------------------" 10327 "----------------" 10328 "----------------------------\n"); 10329 } 10330 10331 10332 #define BCE_PRINT_RX_CONS(arg) \ 10333 if (sblk->status_rx_quick_consumer_index##arg) \ 10334 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10335 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10336 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10337 arg); 10338 10339 10340 #define BCE_PRINT_TX_CONS(arg) \ 10341 if (sblk->status_tx_quick_consumer_index##arg) \ 10342 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10343 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10344 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10345 arg); 10346 10347 /****************************************************************************/ 10348 /* Prints out the status block from host memory. */ 10349 /* */ 10350 /* Returns: */ 10351 /* Nothing. */ 10352 /****************************************************************************/ 10353 static __attribute__ ((noinline)) void 10354 bce_dump_status_block(struct bce_softc *sc) 10355 { 10356 struct status_block *sblk; 10357 10358 sblk = sc->status_block; 10359 10360 BCE_PRINTF( 10361 "----------------------------" 10362 " Status Block " 10363 "----------------------------\n"); 10364 10365 /* Theses indices are used for normal L2 drivers. */ 10366 BCE_PRINTF(" 0x%08X - attn_bits\n", 10367 sblk->status_attn_bits); 10368 10369 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10370 sblk->status_attn_bits_ack); 10371 10372 BCE_PRINT_RX_CONS(0); 10373 BCE_PRINT_TX_CONS(0) 10374 10375 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10376 10377 /* Theses indices are not used for normal L2 drivers. */ 10378 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10379 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10380 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10381 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10382 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10383 10384 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10385 10386 if (sblk->status_completion_producer_index || 10387 sblk->status_cmd_consumer_index) 10388 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10389 sblk->status_completion_producer_index, 10390 sblk->status_cmd_consumer_index); 10391 10392 BCE_PRINTF( 10393 "----------------------------" 10394 "----------------" 10395 "----------------------------\n"); 10396 } 10397 10398 10399 #define BCE_PRINT_64BIT_STAT(arg) \ 10400 if (sblk->arg##_lo || sblk->arg##_hi) \ 10401 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10402 sblk->arg##_lo, #arg); 10403 10404 #define BCE_PRINT_32BIT_STAT(arg) \ 10405 if (sblk->arg) \ 10406 BCE_PRINTF(" 0x%08X : %s\n", \ 10407 sblk->arg, #arg); 10408 10409 /****************************************************************************/ 10410 /* Prints out the statistics block from host memory. */ 10411 /* */ 10412 /* Returns: */ 10413 /* Nothing. */ 10414 /****************************************************************************/ 10415 static __attribute__ ((noinline)) void 10416 bce_dump_stats_block(struct bce_softc *sc) 10417 { 10418 struct statistics_block *sblk; 10419 10420 sblk = sc->stats_block; 10421 10422 BCE_PRINTF( 10423 "---------------" 10424 " Stats Block (All Stats Not Shown Are 0) " 10425 "---------------\n"); 10426 10427 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10428 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10429 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10430 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10431 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10432 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10433 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10434 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10435 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10436 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10437 BCE_PRINT_32BIT_STAT( 10438 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10439 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10440 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10441 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10442 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10443 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10444 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10445 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10446 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10447 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10448 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10449 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10450 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10451 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10452 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10453 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10454 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10455 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10456 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10457 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10458 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10459 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10460 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10461 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10462 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10463 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10464 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10465 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10466 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10467 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10468 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10469 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10470 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10471 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10472 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10473 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10474 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10475 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10476 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10477 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10478 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10479 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10480 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10481 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10482 10483 BCE_PRINTF( 10484 "----------------------------" 10485 "----------------" 10486 "----------------------------\n"); 10487 } 10488 10489 10490 /****************************************************************************/ 10491 /* Prints out a summary of the driver state. */ 10492 /* */ 10493 /* Returns: */ 10494 /* Nothing. */ 10495 /****************************************************************************/ 10496 static __attribute__ ((noinline)) void 10497 bce_dump_driver_state(struct bce_softc *sc) 10498 { 10499 u32 val_hi, val_lo; 10500 10501 BCE_PRINTF( 10502 "-----------------------------" 10503 " Driver State " 10504 "-----------------------------\n"); 10505 10506 val_hi = BCE_ADDR_HI(sc); 10507 val_lo = BCE_ADDR_LO(sc); 10508 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10509 "address\n", val_hi, val_lo); 10510 10511 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10512 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10513 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10514 "address\n", val_hi, val_lo); 10515 10516 val_hi = BCE_ADDR_HI(sc->status_block); 10517 val_lo = BCE_ADDR_LO(sc->status_block); 10518 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10519 "virtual address\n", val_hi, val_lo); 10520 10521 val_hi = BCE_ADDR_HI(sc->stats_block); 10522 val_lo = BCE_ADDR_LO(sc->stats_block); 10523 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10524 "virtual address\n", val_hi, val_lo); 10525 10526 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10527 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10528 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10529 "virtual adddress\n", val_hi, val_lo); 10530 10531 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10532 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10533 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10534 "virtual address\n", val_hi, val_lo); 10535 10536 if (bce_hdr_split == TRUE) { 10537 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10538 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10539 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10540 "virtual address\n", val_hi, val_lo); 10541 } 10542 10543 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10544 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10545 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10546 "virtual address\n", val_hi, val_lo); 10547 10548 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10549 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10550 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10551 "virtual address\n", val_hi, val_lo); 10552 10553 if (bce_hdr_split == TRUE) { 10554 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10555 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10556 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10557 "virtual address\n", val_hi, val_lo); 10558 } 10559 10560 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10561 "h/w intrs\n", 10562 (long long unsigned int) sc->interrupts_generated); 10563 10564 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10565 "rx interrupts handled\n", 10566 (long long unsigned int) sc->interrupts_rx); 10567 10568 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10569 "tx interrupts handled\n", 10570 (long long unsigned int) sc->interrupts_tx); 10571 10572 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10573 "phy interrupts handled\n", 10574 (long long unsigned int) sc->phy_interrupts); 10575 10576 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10577 "status block index\n", sc->last_status_idx); 10578 10579 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10580 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10581 10582 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10583 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10584 10585 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10586 "byte seq index\n", sc->tx_prod_bseq); 10587 10588 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10589 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10590 10591 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10592 "tx_bd's\n", sc->used_tx_bd); 10593 10594 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10595 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10596 10597 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10598 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10599 10600 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10601 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10602 10603 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10604 "byte seq index\n", sc->rx_prod_bseq); 10605 10606 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10607 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10608 10609 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10610 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10611 10612 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10613 "rx_bd's\n", sc->free_rx_bd); 10614 10615 if (bce_hdr_split == TRUE) { 10616 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10617 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10618 10619 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10620 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10621 10622 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10623 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10624 } 10625 10626 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10627 "rx_bd's\n", sc->free_pg_bd); 10628 10629 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10630 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10631 10632 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10633 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10634 10635 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10636 "bce mac flags\n", sc->bce_flags); 10637 10638 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10639 "bce phy flags\n", sc->bce_phy_flags); 10640 10641 BCE_PRINTF( 10642 "----------------------------" 10643 "----------------" 10644 "----------------------------\n"); 10645 } 10646 10647 10648 /****************************************************************************/ 10649 /* Prints out the hardware state through a summary of important register, */ 10650 /* followed by a complete register dump. */ 10651 /* */ 10652 /* Returns: */ 10653 /* Nothing. */ 10654 /****************************************************************************/ 10655 static __attribute__ ((noinline)) void 10656 bce_dump_hw_state(struct bce_softc *sc) 10657 { 10658 u32 val; 10659 10660 BCE_PRINTF( 10661 "----------------------------" 10662 " Hardware State " 10663 "----------------------------\n"); 10664 10665 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10666 10667 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10668 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10669 val, BCE_MISC_ENABLE_STATUS_BITS); 10670 10671 val = REG_RD(sc, BCE_DMA_STATUS); 10672 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10673 val, BCE_DMA_STATUS); 10674 10675 val = REG_RD(sc, BCE_CTX_STATUS); 10676 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10677 val, BCE_CTX_STATUS); 10678 10679 val = REG_RD(sc, BCE_EMAC_STATUS); 10680 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10681 val, BCE_EMAC_STATUS); 10682 10683 val = REG_RD(sc, BCE_RPM_STATUS); 10684 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10685 val, BCE_RPM_STATUS); 10686 10687 /* ToDo: Create a #define for this constant. */ 10688 val = REG_RD(sc, 0x2004); 10689 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10690 val, 0x2004); 10691 10692 val = REG_RD(sc, BCE_RV2P_STATUS); 10693 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10694 val, BCE_RV2P_STATUS); 10695 10696 /* ToDo: Create a #define for this constant. */ 10697 val = REG_RD(sc, 0x2c04); 10698 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10699 val, 0x2c04); 10700 10701 val = REG_RD(sc, BCE_TBDR_STATUS); 10702 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10703 val, BCE_TBDR_STATUS); 10704 10705 val = REG_RD(sc, BCE_TDMA_STATUS); 10706 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10707 val, BCE_TDMA_STATUS); 10708 10709 val = REG_RD(sc, BCE_HC_STATUS); 10710 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10711 val, BCE_HC_STATUS); 10712 10713 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10714 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10715 val, BCE_TXP_CPU_STATE); 10716 10717 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10718 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10719 val, BCE_TPAT_CPU_STATE); 10720 10721 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10722 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10723 val, BCE_RXP_CPU_STATE); 10724 10725 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10726 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10727 val, BCE_COM_CPU_STATE); 10728 10729 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10730 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10731 val, BCE_MCP_CPU_STATE); 10732 10733 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10734 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10735 val, BCE_CP_CPU_STATE); 10736 10737 BCE_PRINTF( 10738 "----------------------------" 10739 "----------------" 10740 "----------------------------\n"); 10741 10742 BCE_PRINTF( 10743 "----------------------------" 10744 " Register Dump " 10745 "----------------------------\n"); 10746 10747 for (int i = 0x400; i < 0x8000; i += 0x10) { 10748 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10749 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10750 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10751 } 10752 10753 BCE_PRINTF( 10754 "----------------------------" 10755 "----------------" 10756 "----------------------------\n"); 10757 } 10758 10759 10760 /****************************************************************************/ 10761 /* Prints out the contentst of shared memory which is used for host driver */ 10762 /* to bootcode firmware communication. */ 10763 /* */ 10764 /* Returns: */ 10765 /* Nothing. */ 10766 /****************************************************************************/ 10767 static __attribute__ ((noinline)) void 10768 bce_dump_shmem_state(struct bce_softc *sc) 10769 { 10770 BCE_PRINTF( 10771 "----------------------------" 10772 " Hardware State " 10773 "----------------------------\n"); 10774 10775 BCE_PRINTF("0x%08X - Shared memory base address\n", 10776 sc->bce_shmem_base); 10777 BCE_PRINTF("%s - bootcode version\n", 10778 sc->bce_bc_ver); 10779 10780 BCE_PRINTF( 10781 "----------------------------" 10782 " Shared Mem " 10783 "----------------------------\n"); 10784 10785 for (int i = 0x0; i < 0x200; i += 0x10) { 10786 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10787 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 10788 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 10789 } 10790 10791 BCE_PRINTF( 10792 "----------------------------" 10793 "----------------" 10794 "----------------------------\n"); 10795 } 10796 10797 10798 /****************************************************************************/ 10799 /* Prints out the mailbox queue registers. */ 10800 /* */ 10801 /* Returns: */ 10802 /* Nothing. */ 10803 /****************************************************************************/ 10804 static __attribute__ ((noinline)) void 10805 bce_dump_mq_regs(struct bce_softc *sc) 10806 { 10807 BCE_PRINTF( 10808 "----------------------------" 10809 " MQ Regs " 10810 "----------------------------\n"); 10811 10812 BCE_PRINTF( 10813 "----------------------------" 10814 "----------------" 10815 "----------------------------\n"); 10816 10817 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10818 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10819 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10820 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10821 } 10822 10823 BCE_PRINTF( 10824 "----------------------------" 10825 "----------------" 10826 "----------------------------\n"); 10827 } 10828 10829 10830 /****************************************************************************/ 10831 /* Prints out the bootcode state. */ 10832 /* */ 10833 /* Returns: */ 10834 /* Nothing. */ 10835 /****************************************************************************/ 10836 static __attribute__ ((noinline)) void 10837 bce_dump_bc_state(struct bce_softc *sc) 10838 { 10839 u32 val; 10840 10841 BCE_PRINTF( 10842 "----------------------------" 10843 " Bootcode State " 10844 "----------------------------\n"); 10845 10846 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10847 10848 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10849 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10850 val, BCE_BC_RESET_TYPE); 10851 10852 val = bce_shmem_rd(sc, BCE_BC_STATE); 10853 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10854 val, BCE_BC_STATE); 10855 10856 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10857 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10858 val, BCE_BC_STATE_CONDITION); 10859 10860 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10861 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10862 val, BCE_BC_STATE_DEBUG_CMD); 10863 10864 BCE_PRINTF( 10865 "----------------------------" 10866 "----------------" 10867 "----------------------------\n"); 10868 } 10869 10870 10871 /****************************************************************************/ 10872 /* Prints out the TXP processor state. */ 10873 /* */ 10874 /* Returns: */ 10875 /* Nothing. */ 10876 /****************************************************************************/ 10877 static __attribute__ ((noinline)) void 10878 bce_dump_txp_state(struct bce_softc *sc, int regs) 10879 { 10880 u32 val; 10881 u32 fw_version[3]; 10882 10883 BCE_PRINTF( 10884 "----------------------------" 10885 " TXP State " 10886 "----------------------------\n"); 10887 10888 for (int i = 0; i < 3; i++) 10889 fw_version[i] = htonl(REG_RD_IND(sc, 10890 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10891 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10892 10893 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10894 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 10895 val, BCE_TXP_CPU_MODE); 10896 10897 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10898 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10899 val, BCE_TXP_CPU_STATE); 10900 10901 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10902 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 10903 val, BCE_TXP_CPU_EVENT_MASK); 10904 10905 if (regs) { 10906 BCE_PRINTF( 10907 "----------------------------" 10908 " Register Dump " 10909 "----------------------------\n"); 10910 10911 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10912 /* Skip the big blank spaces */ 10913 if (i < 0x454000 && i > 0x5ffff) 10914 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10915 "0x%08X 0x%08X\n", i, 10916 REG_RD_IND(sc, i), 10917 REG_RD_IND(sc, i + 0x4), 10918 REG_RD_IND(sc, i + 0x8), 10919 REG_RD_IND(sc, i + 0xC)); 10920 } 10921 } 10922 10923 BCE_PRINTF( 10924 "----------------------------" 10925 "----------------" 10926 "----------------------------\n"); 10927 } 10928 10929 10930 /****************************************************************************/ 10931 /* Prints out the RXP processor state. */ 10932 /* */ 10933 /* Returns: */ 10934 /* Nothing. */ 10935 /****************************************************************************/ 10936 static __attribute__ ((noinline)) void 10937 bce_dump_rxp_state(struct bce_softc *sc, int regs) 10938 { 10939 u32 val; 10940 u32 fw_version[3]; 10941 10942 BCE_PRINTF( 10943 "----------------------------" 10944 " RXP State " 10945 "----------------------------\n"); 10946 10947 for (int i = 0; i < 3; i++) 10948 fw_version[i] = htonl(REG_RD_IND(sc, 10949 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10950 10951 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10952 10953 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10954 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 10955 val, BCE_RXP_CPU_MODE); 10956 10957 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10958 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10959 val, BCE_RXP_CPU_STATE); 10960 10961 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10962 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 10963 val, BCE_RXP_CPU_EVENT_MASK); 10964 10965 if (regs) { 10966 BCE_PRINTF( 10967 "----------------------------" 10968 " Register Dump " 10969 "----------------------------\n"); 10970 10971 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 10972 /* Skip the big blank sapces */ 10973 if (i < 0xc5400 && i > 0xdffff) 10974 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10975 "0x%08X 0x%08X\n", i, 10976 REG_RD_IND(sc, i), 10977 REG_RD_IND(sc, i + 0x4), 10978 REG_RD_IND(sc, i + 0x8), 10979 REG_RD_IND(sc, i + 0xC)); 10980 } 10981 } 10982 10983 BCE_PRINTF( 10984 "----------------------------" 10985 "----------------" 10986 "----------------------------\n"); 10987 } 10988 10989 10990 /****************************************************************************/ 10991 /* Prints out the TPAT processor state. */ 10992 /* */ 10993 /* Returns: */ 10994 /* Nothing. */ 10995 /****************************************************************************/ 10996 static __attribute__ ((noinline)) void 10997 bce_dump_tpat_state(struct bce_softc *sc, int regs) 10998 { 10999 u32 val; 11000 u32 fw_version[3]; 11001 11002 BCE_PRINTF( 11003 "----------------------------" 11004 " TPAT State " 11005 "----------------------------\n"); 11006 11007 for (int i = 0; i < 3; i++) 11008 fw_version[i] = htonl(REG_RD_IND(sc, 11009 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11010 11011 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11012 11013 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11014 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11015 val, BCE_TPAT_CPU_MODE); 11016 11017 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11018 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11019 val, BCE_TPAT_CPU_STATE); 11020 11021 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11022 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11023 val, BCE_TPAT_CPU_EVENT_MASK); 11024 11025 if (regs) { 11026 BCE_PRINTF( 11027 "----------------------------" 11028 " Register Dump " 11029 "----------------------------\n"); 11030 11031 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11032 /* Skip the big blank spaces */ 11033 if (i < 0x854000 && i > 0x9ffff) 11034 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11035 "0x%08X 0x%08X\n", i, 11036 REG_RD_IND(sc, i), 11037 REG_RD_IND(sc, i + 0x4), 11038 REG_RD_IND(sc, i + 0x8), 11039 REG_RD_IND(sc, i + 0xC)); 11040 } 11041 } 11042 11043 BCE_PRINTF( 11044 "----------------------------" 11045 "----------------" 11046 "----------------------------\n"); 11047 } 11048 11049 11050 /****************************************************************************/ 11051 /* Prints out the Command Procesor (CP) state. */ 11052 /* */ 11053 /* Returns: */ 11054 /* Nothing. */ 11055 /****************************************************************************/ 11056 static __attribute__ ((noinline)) void 11057 bce_dump_cp_state(struct bce_softc *sc, int regs) 11058 { 11059 u32 val; 11060 u32 fw_version[3]; 11061 11062 BCE_PRINTF( 11063 "----------------------------" 11064 " CP State " 11065 "----------------------------\n"); 11066 11067 for (int i = 0; i < 3; i++) 11068 fw_version[i] = htonl(REG_RD_IND(sc, 11069 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11070 11071 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11072 11073 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11074 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11075 val, BCE_CP_CPU_MODE); 11076 11077 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11078 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11079 val, BCE_CP_CPU_STATE); 11080 11081 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11082 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11083 BCE_CP_CPU_EVENT_MASK); 11084 11085 if (regs) { 11086 BCE_PRINTF( 11087 "----------------------------" 11088 " Register Dump " 11089 "----------------------------\n"); 11090 11091 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11092 /* Skip the big blank spaces */ 11093 if (i < 0x185400 && i > 0x19ffff) 11094 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11095 "0x%08X 0x%08X\n", i, 11096 REG_RD_IND(sc, i), 11097 REG_RD_IND(sc, i + 0x4), 11098 REG_RD_IND(sc, i + 0x8), 11099 REG_RD_IND(sc, i + 0xC)); 11100 } 11101 } 11102 11103 BCE_PRINTF( 11104 "----------------------------" 11105 "----------------" 11106 "----------------------------\n"); 11107 } 11108 11109 11110 /****************************************************************************/ 11111 /* Prints out the Completion Procesor (COM) state. */ 11112 /* */ 11113 /* Returns: */ 11114 /* Nothing. */ 11115 /****************************************************************************/ 11116 static __attribute__ ((noinline)) void 11117 bce_dump_com_state(struct bce_softc *sc, int regs) 11118 { 11119 u32 val; 11120 u32 fw_version[4]; 11121 11122 BCE_PRINTF( 11123 "----------------------------" 11124 " COM State " 11125 "----------------------------\n"); 11126 11127 for (int i = 0; i < 3; i++) 11128 fw_version[i] = htonl(REG_RD_IND(sc, 11129 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11130 11131 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11132 11133 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11134 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11135 val, BCE_COM_CPU_MODE); 11136 11137 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11138 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11139 val, BCE_COM_CPU_STATE); 11140 11141 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11142 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11143 BCE_COM_CPU_EVENT_MASK); 11144 11145 if (regs) { 11146 BCE_PRINTF( 11147 "----------------------------" 11148 " Register Dump " 11149 "----------------------------\n"); 11150 11151 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11152 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11153 "0x%08X 0x%08X\n", i, 11154 REG_RD_IND(sc, i), 11155 REG_RD_IND(sc, i + 0x4), 11156 REG_RD_IND(sc, i + 0x8), 11157 REG_RD_IND(sc, i + 0xC)); 11158 } 11159 } 11160 11161 BCE_PRINTF( 11162 "----------------------------" 11163 "----------------" 11164 "----------------------------\n"); 11165 } 11166 11167 11168 /****************************************************************************/ 11169 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11170 /* */ 11171 /* Returns: */ 11172 /* Nothing. */ 11173 /****************************************************************************/ 11174 static __attribute__ ((noinline)) void 11175 bce_dump_rv2p_state(struct bce_softc *sc) 11176 { 11177 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11178 11179 BCE_PRINTF( 11180 "----------------------------" 11181 " RV2P State " 11182 "----------------------------\n"); 11183 11184 /* Stall the RV2P processors. */ 11185 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11186 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11187 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11188 11189 /* Read the firmware version. */ 11190 val = 0x00000001; 11191 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11192 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11193 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11194 BCE_RV2P_INSTR_HIGH_HIGH; 11195 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11196 fw_ver_high, fw_ver_low); 11197 11198 val = 0x00000001; 11199 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11200 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11201 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11202 BCE_RV2P_INSTR_HIGH_HIGH; 11203 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11204 fw_ver_high, fw_ver_low); 11205 11206 /* Resume the RV2P processors. */ 11207 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11208 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11209 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11210 11211 /* Fetch the program counter value. */ 11212 val = 0x68007800; 11213 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11214 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11215 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11216 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11217 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11218 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11219 11220 /* Fetch the program counter value again to see if it is advancing. */ 11221 val = 0x68007800; 11222 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11223 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11224 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11225 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11226 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11227 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11228 11229 BCE_PRINTF( 11230 "----------------------------" 11231 "----------------" 11232 "----------------------------\n"); 11233 } 11234 11235 11236 /****************************************************************************/ 11237 /* Prints out the driver state and then enters the debugger. */ 11238 /* */ 11239 /* Returns: */ 11240 /* Nothing. */ 11241 /****************************************************************************/ 11242 static __attribute__ ((noinline)) void 11243 bce_breakpoint(struct bce_softc *sc) 11244 { 11245 11246 /* 11247 * Unreachable code to silence compiler warnings 11248 * about unused functions. 11249 */ 11250 if (0) { 11251 bce_freeze_controller(sc); 11252 bce_unfreeze_controller(sc); 11253 bce_dump_enet(sc, NULL); 11254 bce_dump_txbd(sc, 0, NULL); 11255 bce_dump_rxbd(sc, 0, NULL); 11256 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11257 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11258 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11259 bce_dump_l2fhdr(sc, 0, NULL); 11260 bce_dump_ctx(sc, RX_CID); 11261 bce_dump_ftqs(sc); 11262 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11263 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11264 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11265 bce_dump_status_block(sc); 11266 bce_dump_stats_block(sc); 11267 bce_dump_driver_state(sc); 11268 bce_dump_hw_state(sc); 11269 bce_dump_bc_state(sc); 11270 bce_dump_txp_state(sc, 0); 11271 bce_dump_rxp_state(sc, 0); 11272 bce_dump_tpat_state(sc, 0); 11273 bce_dump_cp_state(sc, 0); 11274 bce_dump_com_state(sc, 0); 11275 bce_dump_rv2p_state(sc); 11276 bce_dump_pgbd(sc, 0, NULL); 11277 } 11278 11279 bce_dump_status_block(sc); 11280 bce_dump_driver_state(sc); 11281 11282 /* Call the debugger. */ 11283 breakpoint(); 11284 11285 return; 11286 } 11287 #endif 11288 11289