1 /*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54 #include "opt_bce.h" 55 56 #include <dev/bce/if_bcereg.h> 57 #include <dev/bce/if_bcefw.h> 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89 #endif 90 91 /****************************************************************************/ 92 /* PCI Device ID Table */ 93 /* */ 94 /* Used by bce_probe() to identify the devices supported by this driver. */ 95 /****************************************************************************/ 96 #define BCE_DEVDESC_MAX 64 97 98 static const struct bce_type bce_devs[] = { 99 /* BCM5706C Controllers and OEM boards. */ 100 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 101 "HP NC370T Multifunction Gigabit Server Adapter" }, 102 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 103 "HP NC370i Multifunction Gigabit Server Adapter" }, 104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 105 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 107 "HP NC371i Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 109 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 110 111 /* BCM5706S controllers and OEM boards. */ 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 113 "HP NC370F Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 116 117 /* BCM5708C controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 119 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 121 "HP NC373i Multifunction Gigabit Server Adapter" }, 122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 123 "HP NC374m PCIe Multifunction Adapter" }, 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 125 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 126 127 /* BCM5708S controllers and OEM boards. */ 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 129 "HP NC373m Multifunction Gigabit Server Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 131 "HP NC373i Multifunction Gigabit Server Adapter" }, 132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 133 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 135 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 136 137 /* BCM5709C controllers and OEM boards. */ 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 139 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 141 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 143 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 144 145 /* BCM5709S controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 147 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 149 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 151 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 152 153 /* BCM5716 controllers and OEM boards. */ 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 155 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 156 157 { 0, 0, 0, 0, NULL } 158 }; 159 160 161 /****************************************************************************/ 162 /* Supported Flash NVRAM device data. */ 163 /****************************************************************************/ 164 static const struct flash_spec flash_table[] = 165 { 166 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 167 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 168 169 /* Slow EEPROM */ 170 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 171 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 172 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 173 "EEPROM - slow"}, 174 /* Expansion entry 0001 */ 175 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 178 "Entry 0001"}, 179 /* Saifun SA25F010 (non-buffered flash) */ 180 /* strap, cfg1, & write1 need updates */ 181 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 184 "Non-buffered flash (128kB)"}, 185 /* Saifun SA25F020 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 190 "Non-buffered flash (256kB)"}, 191 /* Expansion entry 0100 */ 192 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0100"}, 196 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 197 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 198 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 199 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 200 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 201 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 202 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 204 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 205 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 206 /* Saifun SA25F005 (non-buffered flash) */ 207 /* strap, cfg1, & write1 need updates */ 208 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 210 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 211 "Non-buffered flash (64kB)"}, 212 /* Fast EEPROM */ 213 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 214 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 215 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 216 "EEPROM - fast"}, 217 /* Expansion entry 1001 */ 218 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 221 "Entry 1001"}, 222 /* Expansion entry 1010 */ 223 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 226 "Entry 1010"}, 227 /* ATMEL AT45DB011B (buffered flash) */ 228 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 230 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 231 "Buffered flash (128kB)"}, 232 /* Expansion entry 1100 */ 233 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 236 "Entry 1100"}, 237 /* Expansion entry 1101 */ 238 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 1101"}, 242 /* Ateml Expansion entry 1110 */ 243 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 244 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 245 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 246 "Entry 1110 (Atmel)"}, 247 /* ATMEL AT45DB021B (buffered flash) */ 248 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 251 "Buffered flash (256kB)"}, 252 }; 253 254 /* 255 * The BCM5709 controllers transparently handle the 256 * differences between Atmel 264 byte pages and all 257 * flash devices which use 256 byte pages, so no 258 * logical-to-physical mapping is required in the 259 * driver. 260 */ 261 static const struct flash_spec flash_5709 = { 262 .flags = BCE_NV_BUFFERED, 263 .page_bits = BCM5709_FLASH_PAGE_BITS, 264 .page_size = BCM5709_FLASH_PAGE_SIZE, 265 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 266 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 267 .name = "5709/5716 buffered flash (256kB)", 268 }; 269 270 271 /****************************************************************************/ 272 /* FreeBSD device entry points. */ 273 /****************************************************************************/ 274 static int bce_probe (device_t); 275 static int bce_attach (device_t); 276 static int bce_detach (device_t); 277 static int bce_shutdown (device_t); 278 279 280 /****************************************************************************/ 281 /* BCE Debug Data Structure Dump Routines */ 282 /****************************************************************************/ 283 #ifdef BCE_DEBUG 284 static u32 bce_reg_rd (struct bce_softc *, u32); 285 static void bce_reg_wr (struct bce_softc *, u32, u32); 286 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 287 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 288 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 289 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 290 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 291 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 292 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 293 static void bce_dump_txbd (struct bce_softc *, 294 int, struct tx_bd *); 295 static void bce_dump_rxbd (struct bce_softc *, 296 int, struct rx_bd *); 297 static void bce_dump_pgbd (struct bce_softc *, 298 int, struct rx_bd *); 299 static void bce_dump_l2fhdr (struct bce_softc *, 300 int, struct l2_fhdr *); 301 static void bce_dump_ctx (struct bce_softc *, u16); 302 static void bce_dump_ftqs (struct bce_softc *); 303 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 304 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 305 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 306 static void bce_dump_status_block (struct bce_softc *); 307 static void bce_dump_stats_block (struct bce_softc *); 308 static void bce_dump_driver_state (struct bce_softc *); 309 static void bce_dump_hw_state (struct bce_softc *); 310 static void bce_dump_shmem_state (struct bce_softc *); 311 static void bce_dump_mq_regs (struct bce_softc *); 312 static void bce_dump_bc_state (struct bce_softc *); 313 static void bce_dump_txp_state (struct bce_softc *, int); 314 static void bce_dump_rxp_state (struct bce_softc *, int); 315 static void bce_dump_tpat_state (struct bce_softc *, int); 316 static void bce_dump_cp_state (struct bce_softc *, int); 317 static void bce_dump_com_state (struct bce_softc *, int); 318 static void bce_dump_rv2p_state (struct bce_softc *); 319 static void bce_breakpoint (struct bce_softc *); 320 #endif /*BCE_DEBUG */ 321 322 323 /****************************************************************************/ 324 /* BCE Register/Memory Access Routines */ 325 /****************************************************************************/ 326 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 327 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 328 static void bce_shmem_wr (struct bce_softc *, u32, u32); 329 static u32 bce_shmem_rd (struct bce_softc *, u32); 330 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 331 static int bce_miibus_read_reg (device_t, int, int); 332 static int bce_miibus_write_reg (device_t, int, int, int); 333 static void bce_miibus_statchg (device_t); 334 335 #ifdef BCE_DEBUG 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 337 #ifdef BCE_NVRAM_WRITE_SUPPORT 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 339 #endif 340 #endif 341 342 /****************************************************************************/ 343 /* BCE NVRAM Access Routines */ 344 /****************************************************************************/ 345 static int bce_acquire_nvram_lock (struct bce_softc *); 346 static int bce_release_nvram_lock (struct bce_softc *); 347 static void bce_enable_nvram_access(struct bce_softc *); 348 static void bce_disable_nvram_access(struct bce_softc *); 349 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 350 static int bce_init_nvram (struct bce_softc *); 351 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 352 static int bce_nvram_test (struct bce_softc *); 353 #ifdef BCE_NVRAM_WRITE_SUPPORT 354 static int bce_enable_nvram_write (struct bce_softc *); 355 static void bce_disable_nvram_write(struct bce_softc *); 356 static int bce_nvram_erase_page (struct bce_softc *, u32); 357 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 358 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 359 #endif 360 361 /****************************************************************************/ 362 /* */ 363 /****************************************************************************/ 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 365 static void bce_get_media (struct bce_softc *); 366 static void bce_init_media (struct bce_softc *); 367 static u32 bce_get_rphy_link (struct bce_softc *); 368 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 369 static int bce_dma_alloc (device_t); 370 static void bce_dma_free (struct bce_softc *); 371 static void bce_release_resources (struct bce_softc *); 372 373 /****************************************************************************/ 374 /* BCE Firmware Synchronization and Load */ 375 /****************************************************************************/ 376 static void bce_fw_cap_init (struct bce_softc *); 377 static int bce_fw_sync (struct bce_softc *, u32); 378 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 379 u32); 380 static void bce_load_cpu_fw (struct bce_softc *, 381 struct cpu_reg *, struct fw_info *); 382 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 383 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 384 static void bce_start_rxp_cpu (struct bce_softc *); 385 static void bce_init_rxp_cpu (struct bce_softc *); 386 static void bce_init_txp_cpu (struct bce_softc *); 387 static void bce_init_tpat_cpu (struct bce_softc *); 388 static void bce_init_cp_cpu (struct bce_softc *); 389 static void bce_init_com_cpu (struct bce_softc *); 390 static void bce_init_cpus (struct bce_softc *); 391 392 static void bce_print_adapter_info (struct bce_softc *); 393 static void bce_probe_pci_caps (device_t, struct bce_softc *); 394 static void bce_stop (struct bce_softc *); 395 static int bce_reset (struct bce_softc *, u32); 396 static int bce_chipinit (struct bce_softc *); 397 static int bce_blockinit (struct bce_softc *); 398 399 static int bce_init_tx_chain (struct bce_softc *); 400 static void bce_free_tx_chain (struct bce_softc *); 401 402 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 403 static int bce_init_rx_chain (struct bce_softc *); 404 static void bce_fill_rx_chain (struct bce_softc *); 405 static void bce_free_rx_chain (struct bce_softc *); 406 407 static int bce_get_pg_buf (struct bce_softc *, u16, u16); 408 static int bce_init_pg_chain (struct bce_softc *); 409 static void bce_fill_pg_chain (struct bce_softc *); 410 static void bce_free_pg_chain (struct bce_softc *); 411 412 static struct mbuf *bce_tso_setup (struct bce_softc *, 413 struct mbuf **, u16 *); 414 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 415 static void bce_start_locked (struct ifnet *); 416 static void bce_start (struct ifnet *); 417 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 418 static void bce_watchdog (struct bce_softc *); 419 static int bce_ifmedia_upd (struct ifnet *); 420 static int bce_ifmedia_upd_locked (struct ifnet *); 421 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 422 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 423 static void bce_init_locked (struct bce_softc *); 424 static void bce_init (void *); 425 static void bce_mgmt_init_locked (struct bce_softc *sc); 426 427 static int bce_init_ctx (struct bce_softc *); 428 static void bce_get_mac_addr (struct bce_softc *); 429 static void bce_set_mac_addr (struct bce_softc *); 430 static void bce_phy_intr (struct bce_softc *); 431 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 432 static void bce_rx_intr (struct bce_softc *); 433 static void bce_tx_intr (struct bce_softc *); 434 static void bce_disable_intr (struct bce_softc *); 435 static void bce_enable_intr (struct bce_softc *, int); 436 437 static void bce_intr (void *); 438 static void bce_set_rx_mode (struct bce_softc *); 439 static void bce_stats_update (struct bce_softc *); 440 static void bce_tick (void *); 441 static void bce_pulse (void *); 442 static void bce_add_sysctls (struct bce_softc *); 443 444 445 /****************************************************************************/ 446 /* FreeBSD device dispatch table. */ 447 /****************************************************************************/ 448 static device_method_t bce_methods[] = { 449 /* Device interface (device_if.h) */ 450 DEVMETHOD(device_probe, bce_probe), 451 DEVMETHOD(device_attach, bce_attach), 452 DEVMETHOD(device_detach, bce_detach), 453 DEVMETHOD(device_shutdown, bce_shutdown), 454 /* Supported by device interface but not used here. */ 455 /* DEVMETHOD(device_identify, bce_identify), */ 456 /* DEVMETHOD(device_suspend, bce_suspend), */ 457 /* DEVMETHOD(device_resume, bce_resume), */ 458 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 459 460 /* MII interface (miibus_if.h) */ 461 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 462 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 463 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 464 /* Supported by MII interface but not used here. */ 465 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 466 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 467 468 DEVMETHOD_END 469 }; 470 471 static driver_t bce_driver = { 472 "bce", 473 bce_methods, 474 sizeof(struct bce_softc) 475 }; 476 477 static devclass_t bce_devclass; 478 479 MODULE_DEPEND(bce, pci, 1, 1, 1); 480 MODULE_DEPEND(bce, ether, 1, 1, 1); 481 MODULE_DEPEND(bce, miibus, 1, 1, 1); 482 483 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL); 484 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL); 485 486 487 /****************************************************************************/ 488 /* Tunable device values */ 489 /****************************************************************************/ 490 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 491 492 /* Allowable values are TRUE or FALSE */ 493 static int bce_verbose = TRUE; 494 TUNABLE_INT("hw.bce.verbose", &bce_verbose); 495 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 496 "Verbose output enable/disable"); 497 498 /* Allowable values are TRUE or FALSE */ 499 static int bce_tso_enable = TRUE; 500 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 501 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 502 "TSO Enable/Disable"); 503 504 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 505 /* ToDo: Add MSI-X support. */ 506 static int bce_msi_enable = 1; 507 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 508 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 509 "MSI-X|MSI|INTx selector"); 510 511 /* Allowable values are 1, 2, 4, 8. */ 512 static int bce_rx_pages = DEFAULT_RX_PAGES; 513 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 514 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 515 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 516 517 /* Allowable values are 1, 2, 4, 8. */ 518 static int bce_tx_pages = DEFAULT_TX_PAGES; 519 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 520 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 521 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 522 523 /* Allowable values are TRUE or FALSE. */ 524 static int bce_hdr_split = TRUE; 525 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 526 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 527 "Frame header/payload splitting Enable/Disable"); 528 529 /* Allowable values are TRUE or FALSE. */ 530 static int bce_strict_rx_mtu = FALSE; 531 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 532 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 533 &bce_strict_rx_mtu, 0, 534 "Enable/Disable strict RX frame size checking"); 535 536 /* Allowable values are 0 ... 100 */ 537 #ifdef BCE_DEBUG 538 /* Generate 1 interrupt for every transmit completion. */ 539 static int bce_tx_quick_cons_trip_int = 1; 540 #else 541 /* Generate 1 interrupt for every 20 transmit completions. */ 542 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 543 #endif 544 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 545 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 546 &bce_tx_quick_cons_trip_int, 0, 547 "Transmit BD trip point during interrupts"); 548 549 /* Allowable values are 0 ... 100 */ 550 /* Generate 1 interrupt for every transmit completion. */ 551 #ifdef BCE_DEBUG 552 static int bce_tx_quick_cons_trip = 1; 553 #else 554 /* Generate 1 interrupt for every 20 transmit completions. */ 555 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 556 #endif 557 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 558 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 559 &bce_tx_quick_cons_trip, 0, 560 "Transmit BD trip point"); 561 562 /* Allowable values are 0 ... 100 */ 563 #ifdef BCE_DEBUG 564 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 565 static int bce_tx_ticks_int = 0; 566 #else 567 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 568 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 569 #endif 570 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 571 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 572 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 573 574 /* Allowable values are 0 ... 100 */ 575 #ifdef BCE_DEBUG 576 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 577 static int bce_tx_ticks = 0; 578 #else 579 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 580 static int bce_tx_ticks = DEFAULT_TX_TICKS; 581 #endif 582 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 583 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 584 &bce_tx_ticks, 0, "Transmit ticks count"); 585 586 /* Allowable values are 1 ... 100 */ 587 #ifdef BCE_DEBUG 588 /* Generate 1 interrupt for every received frame. */ 589 static int bce_rx_quick_cons_trip_int = 1; 590 #else 591 /* Generate 1 interrupt for every 6 received frames. */ 592 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 593 #endif 594 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 595 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 596 &bce_rx_quick_cons_trip_int, 0, 597 "Receive BD trip point duirng interrupts"); 598 599 /* Allowable values are 1 ... 100 */ 600 #ifdef BCE_DEBUG 601 /* Generate 1 interrupt for every received frame. */ 602 static int bce_rx_quick_cons_trip = 1; 603 #else 604 /* Generate 1 interrupt for every 6 received frames. */ 605 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 606 #endif 607 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 608 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 609 &bce_rx_quick_cons_trip, 0, 610 "Receive BD trip point"); 611 612 /* Allowable values are 0 ... 100 */ 613 #ifdef BCE_DEBUG 614 /* Generate an int. if 0us have elapsed since the last received frame. */ 615 static int bce_rx_ticks_int = 0; 616 #else 617 /* Generate an int. if 18us have elapsed since the last received frame. */ 618 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 619 #endif 620 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 621 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 622 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 623 624 /* Allowable values are 0 ... 100 */ 625 #ifdef BCE_DEBUG 626 /* Generate an int. if 0us have elapsed since the last received frame. */ 627 static int bce_rx_ticks = 0; 628 #else 629 /* Generate an int. if 18us have elapsed since the last received frame. */ 630 static int bce_rx_ticks = DEFAULT_RX_TICKS; 631 #endif 632 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 633 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 634 &bce_rx_ticks, 0, "Receive ticks count"); 635 636 637 /****************************************************************************/ 638 /* Device probe function. */ 639 /* */ 640 /* Compares the device to the driver's list of supported devices and */ 641 /* reports back to the OS whether this is the right driver for the device. */ 642 /* */ 643 /* Returns: */ 644 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 645 /****************************************************************************/ 646 static int 647 bce_probe(device_t dev) 648 { 649 const struct bce_type *t; 650 struct bce_softc *sc; 651 char *descbuf; 652 u16 vid = 0, did = 0, svid = 0, sdid = 0; 653 654 t = bce_devs; 655 656 sc = device_get_softc(dev); 657 sc->bce_unit = device_get_unit(dev); 658 sc->bce_dev = dev; 659 660 /* Get the data for the device to be probed. */ 661 vid = pci_get_vendor(dev); 662 did = pci_get_device(dev); 663 svid = pci_get_subvendor(dev); 664 sdid = pci_get_subdevice(dev); 665 666 DBPRINT(sc, BCE_EXTREME_LOAD, 667 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 668 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 669 670 /* Look through the list of known devices for a match. */ 671 while(t->bce_name != NULL) { 672 673 if ((vid == t->bce_vid) && (did == t->bce_did) && 674 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 675 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 676 677 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 678 679 if (descbuf == NULL) 680 return(ENOMEM); 681 682 /* Print out the device identity. */ 683 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 684 t->bce_name, (((pci_read_config(dev, 685 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 686 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 687 688 device_set_desc_copy(dev, descbuf); 689 free(descbuf, M_TEMP); 690 return(BUS_PROBE_DEFAULT); 691 } 692 t++; 693 } 694 695 return(ENXIO); 696 } 697 698 699 /****************************************************************************/ 700 /* PCI Capabilities Probe Function. */ 701 /* */ 702 /* Walks the PCI capabiites list for the device to find what features are */ 703 /* supported. */ 704 /* */ 705 /* Returns: */ 706 /* None. */ 707 /****************************************************************************/ 708 static void 709 bce_print_adapter_info(struct bce_softc *sc) 710 { 711 int i = 0; 712 713 DBENTER(BCE_VERBOSE_LOAD); 714 715 if (bce_verbose || bootverbose) { 716 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 717 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 718 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 719 720 721 /* Bus info. */ 722 if (sc->bce_flags & BCE_PCIE_FLAG) { 723 printf("Bus (PCIe x%d, ", sc->link_width); 724 switch (sc->link_speed) { 725 case 1: printf("2.5Gbps); "); break; 726 case 2: printf("5Gbps); "); break; 727 default: printf("Unknown link speed); "); 728 } 729 } else { 730 printf("Bus (PCI%s, %s, %dMHz); ", 731 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 732 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 733 "32-bit" : "64-bit"), sc->bus_speed_mhz); 734 } 735 736 /* Firmware version and device features. */ 737 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 738 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 739 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 740 741 if (bce_hdr_split == TRUE) { 742 printf("SPLT"); 743 i++; 744 } 745 746 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 747 if (i > 0) printf("|"); 748 printf("MSI"); i++; 749 } 750 751 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 752 if (i > 0) printf("|"); 753 printf("MSI-X"); i++; 754 } 755 756 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 757 if (i > 0) printf("|"); 758 printf("2.5G"); i++; 759 } 760 761 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 762 if (i > 0) printf("|"); 763 printf("Remote PHY(%s)", 764 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 765 "FIBER" : "TP"); i++; 766 } 767 768 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 769 if (i > 0) printf("|"); 770 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 771 } else { 772 printf(")\n"); 773 } 774 775 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 776 sc->bce_rx_quick_cons_trip_int, 777 sc->bce_rx_quick_cons_trip, 778 sc->bce_rx_ticks_int, 779 sc->bce_rx_ticks, 780 sc->bce_tx_quick_cons_trip_int, 781 sc->bce_tx_quick_cons_trip, 782 sc->bce_tx_ticks_int, 783 sc->bce_tx_ticks); 784 785 } 786 787 DBEXIT(BCE_VERBOSE_LOAD); 788 } 789 790 791 /****************************************************************************/ 792 /* PCI Capabilities Probe Function. */ 793 /* */ 794 /* Walks the PCI capabiites list for the device to find what features are */ 795 /* supported. */ 796 /* */ 797 /* Returns: */ 798 /* None. */ 799 /****************************************************************************/ 800 static void 801 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 802 { 803 u32 reg; 804 805 DBENTER(BCE_VERBOSE_LOAD); 806 807 /* Check if PCI-X capability is enabled. */ 808 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 809 if (reg != 0) 810 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 811 } 812 813 /* Check if PCIe capability is enabled. */ 814 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 815 if (reg != 0) { 816 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 817 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 818 "0x%08X\n", link_status); 819 sc->link_speed = link_status & 0xf; 820 sc->link_width = (link_status >> 4) & 0x3f; 821 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 822 sc->bce_flags |= BCE_PCIE_FLAG; 823 } 824 } 825 826 /* Check if MSI capability is enabled. */ 827 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 828 if (reg != 0) 829 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 830 } 831 832 /* Check if MSI-X capability is enabled. */ 833 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 834 if (reg != 0) 835 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 836 } 837 838 DBEXIT(BCE_VERBOSE_LOAD); 839 } 840 841 842 /****************************************************************************/ 843 /* Load and validate user tunable settings. */ 844 /* */ 845 /* Returns: */ 846 /* Nothing. */ 847 /****************************************************************************/ 848 static void 849 bce_set_tunables(struct bce_softc *sc) 850 { 851 /* Set sysctl values for RX page count. */ 852 switch (bce_rx_pages) { 853 case 1: 854 /* fall-through */ 855 case 2: 856 /* fall-through */ 857 case 4: 858 /* fall-through */ 859 case 8: 860 sc->rx_pages = bce_rx_pages; 861 break; 862 default: 863 sc->rx_pages = DEFAULT_RX_PAGES; 864 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 865 "hw.bce.rx_pages! Setting default of %d.\n", 866 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 867 } 868 869 /* ToDo: Consider allowing user setting for pg_pages. */ 870 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 871 872 /* Set sysctl values for TX page count. */ 873 switch (bce_tx_pages) { 874 case 1: 875 /* fall-through */ 876 case 2: 877 /* fall-through */ 878 case 4: 879 /* fall-through */ 880 case 8: 881 sc->tx_pages = bce_tx_pages; 882 break; 883 default: 884 sc->tx_pages = DEFAULT_TX_PAGES; 885 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 886 "hw.bce.tx_pages! Setting default of %d.\n", 887 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 888 } 889 890 /* 891 * Validate the TX trip point (i.e. the number of 892 * TX completions before a status block update is 893 * generated and an interrupt is asserted. 894 */ 895 if (bce_tx_quick_cons_trip_int <= 100) { 896 sc->bce_tx_quick_cons_trip_int = 897 bce_tx_quick_cons_trip_int; 898 } else { 899 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 900 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 901 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 902 DEFAULT_TX_QUICK_CONS_TRIP_INT); 903 sc->bce_tx_quick_cons_trip_int = 904 DEFAULT_TX_QUICK_CONS_TRIP_INT; 905 } 906 907 if (bce_tx_quick_cons_trip <= 100) { 908 sc->bce_tx_quick_cons_trip = 909 bce_tx_quick_cons_trip; 910 } else { 911 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 912 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 913 __FILE__, __LINE__, bce_tx_quick_cons_trip, 914 DEFAULT_TX_QUICK_CONS_TRIP); 915 sc->bce_tx_quick_cons_trip = 916 DEFAULT_TX_QUICK_CONS_TRIP; 917 } 918 919 /* 920 * Validate the TX ticks count (i.e. the maximum amount 921 * of time to wait after the last TX completion has 922 * occurred before a status block update is generated 923 * and an interrupt is asserted. 924 */ 925 if (bce_tx_ticks_int <= 100) { 926 sc->bce_tx_ticks_int = 927 bce_tx_ticks_int; 928 } else { 929 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 930 "hw.bce.tx_ticks_int! Setting default of %d.\n", 931 __FILE__, __LINE__, bce_tx_ticks_int, 932 DEFAULT_TX_TICKS_INT); 933 sc->bce_tx_ticks_int = 934 DEFAULT_TX_TICKS_INT; 935 } 936 937 if (bce_tx_ticks <= 100) { 938 sc->bce_tx_ticks = 939 bce_tx_ticks; 940 } else { 941 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 942 "hw.bce.tx_ticks! Setting default of %d.\n", 943 __FILE__, __LINE__, bce_tx_ticks, 944 DEFAULT_TX_TICKS); 945 sc->bce_tx_ticks = 946 DEFAULT_TX_TICKS; 947 } 948 949 /* 950 * Validate the RX trip point (i.e. the number of 951 * RX frames received before a status block update is 952 * generated and an interrupt is asserted. 953 */ 954 if (bce_rx_quick_cons_trip_int <= 100) { 955 sc->bce_rx_quick_cons_trip_int = 956 bce_rx_quick_cons_trip_int; 957 } else { 958 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 959 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 960 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 961 DEFAULT_RX_QUICK_CONS_TRIP_INT); 962 sc->bce_rx_quick_cons_trip_int = 963 DEFAULT_RX_QUICK_CONS_TRIP_INT; 964 } 965 966 if (bce_rx_quick_cons_trip <= 100) { 967 sc->bce_rx_quick_cons_trip = 968 bce_rx_quick_cons_trip; 969 } else { 970 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 971 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 972 __FILE__, __LINE__, bce_rx_quick_cons_trip, 973 DEFAULT_RX_QUICK_CONS_TRIP); 974 sc->bce_rx_quick_cons_trip = 975 DEFAULT_RX_QUICK_CONS_TRIP; 976 } 977 978 /* 979 * Validate the RX ticks count (i.e. the maximum amount 980 * of time to wait after the last RX frame has been 981 * received before a status block update is generated 982 * and an interrupt is asserted. 983 */ 984 if (bce_rx_ticks_int <= 100) { 985 sc->bce_rx_ticks_int = bce_rx_ticks_int; 986 } else { 987 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 988 "hw.bce.rx_ticks_int! Setting default of %d.\n", 989 __FILE__, __LINE__, bce_rx_ticks_int, 990 DEFAULT_RX_TICKS_INT); 991 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 992 } 993 994 if (bce_rx_ticks <= 100) { 995 sc->bce_rx_ticks = bce_rx_ticks; 996 } else { 997 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 998 "hw.bce.rx_ticks! Setting default of %d.\n", 999 __FILE__, __LINE__, bce_rx_ticks, 1000 DEFAULT_RX_TICKS); 1001 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1002 } 1003 1004 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1005 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1006 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1007 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1008 __FILE__, __LINE__); 1009 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1010 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1011 } 1012 1013 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1014 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1015 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1016 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1017 __FILE__, __LINE__); 1018 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1019 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1020 } 1021 } 1022 1023 1024 /****************************************************************************/ 1025 /* Device attach function. */ 1026 /* */ 1027 /* Allocates device resources, performs secondary chip identification, */ 1028 /* resets and initializes the hardware, and initializes driver instance */ 1029 /* variables. */ 1030 /* */ 1031 /* Returns: */ 1032 /* 0 on success, positive value on failure. */ 1033 /****************************************************************************/ 1034 static int 1035 bce_attach(device_t dev) 1036 { 1037 struct bce_softc *sc; 1038 struct ifnet *ifp; 1039 u32 val; 1040 int count, error, rc = 0, rid; 1041 1042 sc = device_get_softc(dev); 1043 sc->bce_dev = dev; 1044 1045 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1046 1047 sc->bce_unit = device_get_unit(dev); 1048 1049 /* Set initial device and PHY flags */ 1050 sc->bce_flags = 0; 1051 sc->bce_phy_flags = 0; 1052 1053 bce_set_tunables(sc); 1054 1055 pci_enable_busmaster(dev); 1056 1057 /* Allocate PCI memory resources. */ 1058 rid = PCIR_BAR(0); 1059 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1060 &rid, RF_ACTIVE); 1061 1062 if (sc->bce_res_mem == NULL) { 1063 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1064 __FILE__, __LINE__); 1065 rc = ENXIO; 1066 goto bce_attach_fail; 1067 } 1068 1069 /* Get various resource handles. */ 1070 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1071 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1072 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1073 1074 bce_probe_pci_caps(dev, sc); 1075 1076 rid = 1; 1077 count = 0; 1078 #if 0 1079 /* Try allocating MSI-X interrupts. */ 1080 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1081 (bce_msi_enable >= 2) && 1082 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1083 &rid, RF_ACTIVE)) != NULL)) { 1084 1085 msi_needed = count = 1; 1086 1087 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1088 (count != msi_needed)) { 1089 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1090 "Received = %d, error = %d\n", __FILE__, __LINE__, 1091 msi_needed, count, error); 1092 count = 0; 1093 pci_release_msi(dev); 1094 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1095 sc->bce_res_irq); 1096 sc->bce_res_irq = NULL; 1097 } else { 1098 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1099 __FUNCTION__); 1100 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1101 } 1102 } 1103 #endif 1104 1105 /* Try allocating a MSI interrupt. */ 1106 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1107 (bce_msi_enable >= 1) && (count == 0)) { 1108 count = 1; 1109 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1110 BCE_PRINTF("%s(%d): MSI allocation failed! " 1111 "error = %d\n", __FILE__, __LINE__, error); 1112 count = 0; 1113 pci_release_msi(dev); 1114 } else { 1115 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1116 "interrupt.\n", __FUNCTION__); 1117 sc->bce_flags |= BCE_USING_MSI_FLAG; 1118 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1119 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1120 rid = 1; 1121 } 1122 } 1123 1124 /* Try allocating a legacy interrupt. */ 1125 if (count == 0) { 1126 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1127 __FUNCTION__); 1128 rid = 0; 1129 } 1130 1131 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1132 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1133 1134 /* Report any IRQ allocation errors. */ 1135 if (sc->bce_res_irq == NULL) { 1136 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1137 __FILE__, __LINE__); 1138 rc = ENXIO; 1139 goto bce_attach_fail; 1140 } 1141 1142 /* Initialize mutex for the current device instance. */ 1143 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1144 1145 /* 1146 * Configure byte swap and enable indirect register access. 1147 * Rely on CPU to do target byte swapping on big endian systems. 1148 * Access to registers outside of PCI configurtion space are not 1149 * valid until this is done. 1150 */ 1151 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1152 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1153 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1154 1155 /* Save ASIC revsion info. */ 1156 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1157 1158 /* Weed out any non-production controller revisions. */ 1159 switch(BCE_CHIP_ID(sc)) { 1160 case BCE_CHIP_ID_5706_A0: 1161 case BCE_CHIP_ID_5706_A1: 1162 case BCE_CHIP_ID_5708_A0: 1163 case BCE_CHIP_ID_5708_B0: 1164 case BCE_CHIP_ID_5709_A0: 1165 case BCE_CHIP_ID_5709_B0: 1166 case BCE_CHIP_ID_5709_B1: 1167 case BCE_CHIP_ID_5709_B2: 1168 BCE_PRINTF("%s(%d): Unsupported controller " 1169 "revision (%c%d)!\n", __FILE__, __LINE__, 1170 (((pci_read_config(dev, PCIR_REVID, 4) & 1171 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1172 PCIR_REVID, 4) & 0xf)); 1173 rc = ENODEV; 1174 goto bce_attach_fail; 1175 } 1176 1177 /* 1178 * The embedded PCIe to PCI-X bridge (EPB) 1179 * in the 5708 cannot address memory above 1180 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1181 */ 1182 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1183 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1184 else 1185 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1186 1187 /* 1188 * Find the base address for shared memory access. 1189 * Newer versions of bootcode use a signature and offset 1190 * while older versions use a fixed address. 1191 */ 1192 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1193 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1194 /* Multi-port devices use different offsets in shared memory. */ 1195 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1196 (pci_get_function(sc->bce_dev) << 2)); 1197 else 1198 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1199 1200 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1201 __FUNCTION__, sc->bce_shmem_base); 1202 1203 /* Fetch the bootcode revision. */ 1204 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1205 for (int i = 0, j = 0; i < 3; i++) { 1206 u8 num; 1207 1208 num = (u8) (val >> (24 - (i * 8))); 1209 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1210 if (num >= k || !skip0 || k == 1) { 1211 sc->bce_bc_ver[j++] = (num / k) + '0'; 1212 skip0 = 0; 1213 } 1214 } 1215 1216 if (i != 2) 1217 sc->bce_bc_ver[j++] = '.'; 1218 } 1219 1220 /* Check if any management firwmare is enabled. */ 1221 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1222 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1223 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1224 1225 /* Allow time for firmware to enter the running state. */ 1226 for (int i = 0; i < 30; i++) { 1227 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1228 if (val & BCE_CONDITION_MFW_RUN_MASK) 1229 break; 1230 DELAY(10000); 1231 } 1232 1233 /* Check if management firmware is running. */ 1234 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1235 val &= BCE_CONDITION_MFW_RUN_MASK; 1236 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1237 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1238 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1239 int i = 0; 1240 1241 /* Read the management firmware version string. */ 1242 for (int j = 0; j < 3; j++) { 1243 val = bce_reg_rd_ind(sc, addr + j * 4); 1244 val = bswap32(val); 1245 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1246 i += 4; 1247 } 1248 } else { 1249 /* May cause firmware synchronization timeouts. */ 1250 BCE_PRINTF("%s(%d): Management firmware enabled " 1251 "but not running!\n", __FILE__, __LINE__); 1252 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1253 1254 /* ToDo: Any action the driver should take? */ 1255 } 1256 } 1257 1258 /* Get PCI bus information (speed and type). */ 1259 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1260 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1261 u32 clkreg; 1262 1263 sc->bce_flags |= BCE_PCIX_FLAG; 1264 1265 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1266 1267 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1268 switch (clkreg) { 1269 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1270 sc->bus_speed_mhz = 133; 1271 break; 1272 1273 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1274 sc->bus_speed_mhz = 100; 1275 break; 1276 1277 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1278 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1279 sc->bus_speed_mhz = 66; 1280 break; 1281 1282 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1283 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1284 sc->bus_speed_mhz = 50; 1285 break; 1286 1287 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1288 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1289 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1290 sc->bus_speed_mhz = 33; 1291 break; 1292 } 1293 } else { 1294 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1295 sc->bus_speed_mhz = 66; 1296 else 1297 sc->bus_speed_mhz = 33; 1298 } 1299 1300 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1301 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1302 1303 /* Find the media type for the adapter. */ 1304 bce_get_media(sc); 1305 1306 /* Reset controller and announce to bootcode that driver is present. */ 1307 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1308 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1309 __FILE__, __LINE__); 1310 rc = ENXIO; 1311 goto bce_attach_fail; 1312 } 1313 1314 /* Initialize the controller. */ 1315 if (bce_chipinit(sc)) { 1316 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1317 __FILE__, __LINE__); 1318 rc = ENXIO; 1319 goto bce_attach_fail; 1320 } 1321 1322 /* Perform NVRAM test. */ 1323 if (bce_nvram_test(sc)) { 1324 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1325 __FILE__, __LINE__); 1326 rc = ENXIO; 1327 goto bce_attach_fail; 1328 } 1329 1330 /* Fetch the permanent Ethernet MAC address. */ 1331 bce_get_mac_addr(sc); 1332 1333 /* Update statistics once every second. */ 1334 sc->bce_stats_ticks = 1000000 & 0xffff00; 1335 1336 /* Store data needed by PHY driver for backplane applications */ 1337 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1338 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1339 1340 /* Allocate DMA memory resources. */ 1341 if (bce_dma_alloc(dev)) { 1342 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1343 __FILE__, __LINE__); 1344 rc = ENXIO; 1345 goto bce_attach_fail; 1346 } 1347 1348 /* Allocate an ifnet structure. */ 1349 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1350 if (ifp == NULL) { 1351 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1352 __FILE__, __LINE__); 1353 rc = ENXIO; 1354 goto bce_attach_fail; 1355 } 1356 1357 /* Initialize the ifnet interface. */ 1358 ifp->if_softc = sc; 1359 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1360 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1361 ifp->if_ioctl = bce_ioctl; 1362 ifp->if_start = bce_start; 1363 ifp->if_init = bce_init; 1364 ifp->if_mtu = ETHERMTU; 1365 1366 if (bce_tso_enable) { 1367 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1368 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1369 IFCAP_VLAN_HWTSO; 1370 } else { 1371 ifp->if_hwassist = BCE_IF_HWASSIST; 1372 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1373 } 1374 1375 #if __FreeBSD_version >= 800505 1376 /* 1377 * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version 1378 * so it's approximate value. 1379 */ 1380 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1381 ifp->if_capabilities |= IFCAP_LINKSTATE; 1382 #endif 1383 1384 ifp->if_capenable = ifp->if_capabilities; 1385 1386 /* 1387 * Assume standard mbuf sizes for buffer allocation. 1388 * This may change later if the MTU size is set to 1389 * something other than 1500. 1390 */ 1391 bce_get_rx_buffer_sizes(sc, 1392 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1393 1394 /* Recalculate our buffer allocation sizes. */ 1395 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1396 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1397 IFQ_SET_READY(&ifp->if_snd); 1398 1399 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1400 ifp->if_baudrate = IF_Mbps(2500ULL); 1401 else 1402 ifp->if_baudrate = IF_Mbps(1000); 1403 1404 /* Handle any special PHY initialization for SerDes PHYs. */ 1405 bce_init_media(sc); 1406 1407 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1408 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1409 bce_ifmedia_sts); 1410 /* 1411 * We can't manually override remote PHY's link and assume 1412 * PHY port configuration(Fiber or TP) is not changed after 1413 * device attach. This may not be correct though. 1414 */ 1415 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1416 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1417 ifmedia_add(&sc->bce_ifmedia, 1418 IFM_ETHER | IFM_2500_SX, 0, NULL); 1419 ifmedia_add(&sc->bce_ifmedia, 1420 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1421 } 1422 ifmedia_add(&sc->bce_ifmedia, 1423 IFM_ETHER | IFM_1000_SX, 0, NULL); 1424 ifmedia_add(&sc->bce_ifmedia, 1425 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1426 } else { 1427 ifmedia_add(&sc->bce_ifmedia, 1428 IFM_ETHER | IFM_10_T, 0, NULL); 1429 ifmedia_add(&sc->bce_ifmedia, 1430 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1431 ifmedia_add(&sc->bce_ifmedia, 1432 IFM_ETHER | IFM_100_TX, 0, NULL); 1433 ifmedia_add(&sc->bce_ifmedia, 1434 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1435 ifmedia_add(&sc->bce_ifmedia, 1436 IFM_ETHER | IFM_1000_T, 0, NULL); 1437 ifmedia_add(&sc->bce_ifmedia, 1438 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1439 } 1440 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1441 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1442 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1443 } else { 1444 /* MII child bus by attaching the PHY. */ 1445 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1446 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1447 MII_OFFSET_ANY, MIIF_DOPAUSE); 1448 if (rc != 0) { 1449 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1450 __LINE__); 1451 goto bce_attach_fail; 1452 } 1453 } 1454 1455 /* Attach to the Ethernet interface list. */ 1456 ether_ifattach(ifp, sc->eaddr); 1457 1458 #if __FreeBSD_version < 500000 1459 callout_init(&sc->bce_tick_callout); 1460 callout_init(&sc->bce_pulse_callout); 1461 #else 1462 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1463 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1464 #endif 1465 1466 /* Hookup IRQ last. */ 1467 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1468 NULL, bce_intr, sc, &sc->bce_intrhand); 1469 1470 if (rc) { 1471 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1472 __FILE__, __LINE__); 1473 bce_detach(dev); 1474 goto bce_attach_exit; 1475 } 1476 1477 /* 1478 * At this point we've acquired all the resources 1479 * we need to run so there's no turning back, we're 1480 * cleared for launch. 1481 */ 1482 1483 /* Print some important debugging info. */ 1484 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1485 1486 /* Add the supported sysctls to the kernel. */ 1487 bce_add_sysctls(sc); 1488 1489 BCE_LOCK(sc); 1490 1491 /* 1492 * The chip reset earlier notified the bootcode that 1493 * a driver is present. We now need to start our pulse 1494 * routine so that the bootcode is reminded that we're 1495 * still running. 1496 */ 1497 bce_pulse(sc); 1498 1499 bce_mgmt_init_locked(sc); 1500 BCE_UNLOCK(sc); 1501 1502 /* Finally, print some useful adapter info */ 1503 bce_print_adapter_info(sc); 1504 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1505 __FUNCTION__, sc); 1506 1507 goto bce_attach_exit; 1508 1509 bce_attach_fail: 1510 bce_release_resources(sc); 1511 1512 bce_attach_exit: 1513 1514 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1515 1516 return(rc); 1517 } 1518 1519 1520 /****************************************************************************/ 1521 /* Device detach function. */ 1522 /* */ 1523 /* Stops the controller, resets the controller, and releases resources. */ 1524 /* */ 1525 /* Returns: */ 1526 /* 0 on success, positive value on failure. */ 1527 /****************************************************************************/ 1528 static int 1529 bce_detach(device_t dev) 1530 { 1531 struct bce_softc *sc = device_get_softc(dev); 1532 struct ifnet *ifp; 1533 u32 msg; 1534 1535 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1536 1537 ifp = sc->bce_ifp; 1538 1539 /* Stop and reset the controller. */ 1540 BCE_LOCK(sc); 1541 1542 /* Stop the pulse so the bootcode can go to driver absent state. */ 1543 callout_stop(&sc->bce_pulse_callout); 1544 1545 bce_stop(sc); 1546 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1547 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1548 else 1549 msg = BCE_DRV_MSG_CODE_UNLOAD; 1550 bce_reset(sc, msg); 1551 1552 BCE_UNLOCK(sc); 1553 1554 ether_ifdetach(ifp); 1555 1556 /* If we have a child device on the MII bus remove it too. */ 1557 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1558 ifmedia_removeall(&sc->bce_ifmedia); 1559 else { 1560 bus_generic_detach(dev); 1561 device_delete_child(dev, sc->bce_miibus); 1562 } 1563 1564 /* Release all remaining resources. */ 1565 bce_release_resources(sc); 1566 1567 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1568 1569 return(0); 1570 } 1571 1572 1573 /****************************************************************************/ 1574 /* Device shutdown function. */ 1575 /* */ 1576 /* Stops and resets the controller. */ 1577 /* */ 1578 /* Returns: */ 1579 /* 0 on success, positive value on failure. */ 1580 /****************************************************************************/ 1581 static int 1582 bce_shutdown(device_t dev) 1583 { 1584 struct bce_softc *sc = device_get_softc(dev); 1585 u32 msg; 1586 1587 DBENTER(BCE_VERBOSE); 1588 1589 BCE_LOCK(sc); 1590 bce_stop(sc); 1591 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1592 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1593 else 1594 msg = BCE_DRV_MSG_CODE_UNLOAD; 1595 bce_reset(sc, msg); 1596 BCE_UNLOCK(sc); 1597 1598 DBEXIT(BCE_VERBOSE); 1599 1600 return (0); 1601 } 1602 1603 1604 #ifdef BCE_DEBUG 1605 /****************************************************************************/ 1606 /* Register read. */ 1607 /* */ 1608 /* Returns: */ 1609 /* The value of the register. */ 1610 /****************************************************************************/ 1611 static u32 1612 bce_reg_rd(struct bce_softc *sc, u32 offset) 1613 { 1614 u32 val = REG_RD(sc, offset); 1615 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1616 __FUNCTION__, offset, val); 1617 return val; 1618 } 1619 1620 1621 /****************************************************************************/ 1622 /* Register write (16 bit). */ 1623 /* */ 1624 /* Returns: */ 1625 /* Nothing. */ 1626 /****************************************************************************/ 1627 static void 1628 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1629 { 1630 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1631 __FUNCTION__, offset, val); 1632 REG_WR16(sc, offset, val); 1633 } 1634 1635 1636 /****************************************************************************/ 1637 /* Register write. */ 1638 /* */ 1639 /* Returns: */ 1640 /* Nothing. */ 1641 /****************************************************************************/ 1642 static void 1643 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1644 { 1645 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1646 __FUNCTION__, offset, val); 1647 REG_WR(sc, offset, val); 1648 } 1649 #endif 1650 1651 /****************************************************************************/ 1652 /* Indirect register read. */ 1653 /* */ 1654 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1655 /* configuration space. Using this mechanism avoids issues with posted */ 1656 /* reads but is much slower than memory-mapped I/O. */ 1657 /* */ 1658 /* Returns: */ 1659 /* The value of the register. */ 1660 /****************************************************************************/ 1661 static u32 1662 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1663 { 1664 device_t dev; 1665 dev = sc->bce_dev; 1666 1667 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1668 #ifdef BCE_DEBUG 1669 { 1670 u32 val; 1671 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1672 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1673 __FUNCTION__, offset, val); 1674 return val; 1675 } 1676 #else 1677 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1678 #endif 1679 } 1680 1681 1682 /****************************************************************************/ 1683 /* Indirect register write. */ 1684 /* */ 1685 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1686 /* configuration space. Using this mechanism avoids issues with posted */ 1687 /* writes but is muchh slower than memory-mapped I/O. */ 1688 /* */ 1689 /* Returns: */ 1690 /* Nothing. */ 1691 /****************************************************************************/ 1692 static void 1693 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1694 { 1695 device_t dev; 1696 dev = sc->bce_dev; 1697 1698 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1699 __FUNCTION__, offset, val); 1700 1701 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1702 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1703 } 1704 1705 1706 /****************************************************************************/ 1707 /* Shared memory write. */ 1708 /* */ 1709 /* Writes NetXtreme II shared memory region. */ 1710 /* */ 1711 /* Returns: */ 1712 /* Nothing. */ 1713 /****************************************************************************/ 1714 static void 1715 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1716 { 1717 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1718 "0x%08X\n", __FUNCTION__, val, offset); 1719 1720 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1721 } 1722 1723 1724 /****************************************************************************/ 1725 /* Shared memory read. */ 1726 /* */ 1727 /* Reads NetXtreme II shared memory region. */ 1728 /* */ 1729 /* Returns: */ 1730 /* The 32 bit value read. */ 1731 /****************************************************************************/ 1732 static u32 1733 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1734 { 1735 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1736 1737 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1738 "0x%08X\n", __FUNCTION__, val, offset); 1739 1740 return val; 1741 } 1742 1743 1744 #ifdef BCE_DEBUG 1745 /****************************************************************************/ 1746 /* Context memory read. */ 1747 /* */ 1748 /* The NetXtreme II controller uses context memory to track connection */ 1749 /* information for L2 and higher network protocols. */ 1750 /* */ 1751 /* Returns: */ 1752 /* The requested 32 bit value of context memory. */ 1753 /****************************************************************************/ 1754 static u32 1755 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1756 { 1757 u32 idx, offset, retry_cnt = 5, val; 1758 1759 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1760 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1761 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1762 1763 offset = ctx_offset + cid_addr; 1764 1765 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1766 1767 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1768 1769 for (idx = 0; idx < retry_cnt; idx++) { 1770 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1771 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1772 break; 1773 DELAY(5); 1774 } 1775 1776 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1777 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1778 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1779 __FILE__, __LINE__, cid_addr, ctx_offset); 1780 1781 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1782 } else { 1783 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1784 val = REG_RD(sc, BCE_CTX_DATA); 1785 } 1786 1787 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1788 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1789 1790 return(val); 1791 } 1792 #endif 1793 1794 1795 /****************************************************************************/ 1796 /* Context memory write. */ 1797 /* */ 1798 /* The NetXtreme II controller uses context memory to track connection */ 1799 /* information for L2 and higher network protocols. */ 1800 /* */ 1801 /* Returns: */ 1802 /* Nothing. */ 1803 /****************************************************************************/ 1804 static void 1805 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1806 { 1807 u32 idx, offset = ctx_offset + cid_addr; 1808 u32 val, retry_cnt = 5; 1809 1810 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1811 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1812 1813 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1814 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1815 __FUNCTION__, cid_addr)); 1816 1817 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1818 1819 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1820 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1821 1822 for (idx = 0; idx < retry_cnt; idx++) { 1823 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1824 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1825 break; 1826 DELAY(5); 1827 } 1828 1829 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1830 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1831 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1832 __FILE__, __LINE__, cid_addr, ctx_offset); 1833 1834 } else { 1835 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1836 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1837 } 1838 } 1839 1840 1841 /****************************************************************************/ 1842 /* PHY register read. */ 1843 /* */ 1844 /* Implements register reads on the MII bus. */ 1845 /* */ 1846 /* Returns: */ 1847 /* The value of the register. */ 1848 /****************************************************************************/ 1849 static int 1850 bce_miibus_read_reg(device_t dev, int phy, int reg) 1851 { 1852 struct bce_softc *sc; 1853 u32 val; 1854 int i; 1855 1856 sc = device_get_softc(dev); 1857 1858 /* 1859 * The 5709S PHY is an IEEE Clause 45 PHY 1860 * with special mappings to work with IEEE 1861 * Clause 22 register accesses. 1862 */ 1863 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1864 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1865 reg += 0x10; 1866 } 1867 1868 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1869 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1870 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1871 1872 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1873 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1874 1875 DELAY(40); 1876 } 1877 1878 1879 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1880 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1881 BCE_EMAC_MDIO_COMM_START_BUSY; 1882 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1883 1884 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1885 DELAY(10); 1886 1887 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1888 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1889 DELAY(5); 1890 1891 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1892 val &= BCE_EMAC_MDIO_COMM_DATA; 1893 1894 break; 1895 } 1896 } 1897 1898 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1899 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1900 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1901 val = 0x0; 1902 } else { 1903 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1904 } 1905 1906 1907 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1908 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1909 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1910 1911 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1912 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1913 1914 DELAY(40); 1915 } 1916 1917 DB_PRINT_PHY_REG(reg, val); 1918 return (val & 0xffff); 1919 } 1920 1921 1922 /****************************************************************************/ 1923 /* PHY register write. */ 1924 /* */ 1925 /* Implements register writes on the MII bus. */ 1926 /* */ 1927 /* Returns: */ 1928 /* The value of the register. */ 1929 /****************************************************************************/ 1930 static int 1931 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1932 { 1933 struct bce_softc *sc; 1934 u32 val1; 1935 int i; 1936 1937 sc = device_get_softc(dev); 1938 1939 DB_PRINT_PHY_REG(reg, val); 1940 1941 /* 1942 * The 5709S PHY is an IEEE Clause 45 PHY 1943 * with special mappings to work with IEEE 1944 * Clause 22 register accesses. 1945 */ 1946 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1947 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1948 reg += 0x10; 1949 } 1950 1951 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1952 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1953 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1954 1955 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1956 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1957 1958 DELAY(40); 1959 } 1960 1961 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1962 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1963 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1964 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1965 1966 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1967 DELAY(10); 1968 1969 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1970 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1971 DELAY(5); 1972 break; 1973 } 1974 } 1975 1976 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1977 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1978 __FILE__, __LINE__); 1979 1980 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1981 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1982 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1983 1984 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1985 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1986 1987 DELAY(40); 1988 } 1989 1990 return 0; 1991 } 1992 1993 1994 /****************************************************************************/ 1995 /* MII bus status change. */ 1996 /* */ 1997 /* Called by the MII bus driver when the PHY establishes link to set the */ 1998 /* MAC interface registers. */ 1999 /* */ 2000 /* Returns: */ 2001 /* Nothing. */ 2002 /****************************************************************************/ 2003 static void 2004 bce_miibus_statchg(device_t dev) 2005 { 2006 struct bce_softc *sc; 2007 struct mii_data *mii; 2008 struct ifmediareq ifmr; 2009 int media_active, media_status, val; 2010 2011 sc = device_get_softc(dev); 2012 2013 DBENTER(BCE_VERBOSE_PHY); 2014 2015 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2016 bzero(&ifmr, sizeof(ifmr)); 2017 bce_ifmedia_sts_rphy(sc, &ifmr); 2018 media_active = ifmr.ifm_active; 2019 media_status = ifmr.ifm_status; 2020 } else { 2021 mii = device_get_softc(sc->bce_miibus); 2022 media_active = mii->mii_media_active; 2023 media_status = mii->mii_media_status; 2024 } 2025 2026 /* Ignore invalid media status. */ 2027 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2028 (IFM_ACTIVE | IFM_AVALID)) 2029 goto bce_miibus_statchg_exit; 2030 2031 val = REG_RD(sc, BCE_EMAC_MODE); 2032 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2033 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2034 BCE_EMAC_MODE_25G); 2035 2036 /* Set MII or GMII interface based on the PHY speed. */ 2037 switch (IFM_SUBTYPE(media_active)) { 2038 case IFM_10_T: 2039 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2040 DBPRINT(sc, BCE_INFO_PHY, 2041 "Enabling 10Mb interface.\n"); 2042 val |= BCE_EMAC_MODE_PORT_MII_10; 2043 break; 2044 } 2045 /* fall-through */ 2046 case IFM_100_TX: 2047 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2048 val |= BCE_EMAC_MODE_PORT_MII; 2049 break; 2050 case IFM_2500_SX: 2051 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2052 val |= BCE_EMAC_MODE_25G; 2053 /* fall-through */ 2054 case IFM_1000_T: 2055 case IFM_1000_SX: 2056 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2057 val |= BCE_EMAC_MODE_PORT_GMII; 2058 break; 2059 default: 2060 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2061 "default GMII interface.\n"); 2062 val |= BCE_EMAC_MODE_PORT_GMII; 2063 } 2064 2065 /* Set half or full duplex based on PHY settings. */ 2066 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2067 DBPRINT(sc, BCE_INFO_PHY, 2068 "Setting Half-Duplex interface.\n"); 2069 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2070 } else 2071 DBPRINT(sc, BCE_INFO_PHY, 2072 "Setting Full-Duplex interface.\n"); 2073 2074 REG_WR(sc, BCE_EMAC_MODE, val); 2075 2076 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2077 DBPRINT(sc, BCE_INFO_PHY, 2078 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2079 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2080 } else { 2081 DBPRINT(sc, BCE_INFO_PHY, 2082 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2083 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2084 } 2085 2086 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2087 DBPRINT(sc, BCE_INFO_PHY, 2088 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2089 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2090 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2091 } else { 2092 DBPRINT(sc, BCE_INFO_PHY, 2093 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2094 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2095 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2096 } 2097 2098 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2099 2100 bce_miibus_statchg_exit: 2101 DBEXIT(BCE_VERBOSE_PHY); 2102 } 2103 2104 2105 /****************************************************************************/ 2106 /* Acquire NVRAM lock. */ 2107 /* */ 2108 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2109 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2110 /* for use by the driver. */ 2111 /* */ 2112 /* Returns: */ 2113 /* 0 on success, positive value on failure. */ 2114 /****************************************************************************/ 2115 static int 2116 bce_acquire_nvram_lock(struct bce_softc *sc) 2117 { 2118 u32 val; 2119 int j, rc = 0; 2120 2121 DBENTER(BCE_VERBOSE_NVRAM); 2122 2123 /* Request access to the flash interface. */ 2124 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2125 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2126 val = REG_RD(sc, BCE_NVM_SW_ARB); 2127 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2128 break; 2129 2130 DELAY(5); 2131 } 2132 2133 if (j >= NVRAM_TIMEOUT_COUNT) { 2134 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2135 rc = EBUSY; 2136 } 2137 2138 DBEXIT(BCE_VERBOSE_NVRAM); 2139 return (rc); 2140 } 2141 2142 2143 /****************************************************************************/ 2144 /* Release NVRAM lock. */ 2145 /* */ 2146 /* When the caller is finished accessing NVRAM the lock must be released. */ 2147 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2148 /* for use by the driver. */ 2149 /* */ 2150 /* Returns: */ 2151 /* 0 on success, positive value on failure. */ 2152 /****************************************************************************/ 2153 static int 2154 bce_release_nvram_lock(struct bce_softc *sc) 2155 { 2156 u32 val; 2157 int j, rc = 0; 2158 2159 DBENTER(BCE_VERBOSE_NVRAM); 2160 2161 /* 2162 * Relinquish nvram interface. 2163 */ 2164 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2165 2166 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2167 val = REG_RD(sc, BCE_NVM_SW_ARB); 2168 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2169 break; 2170 2171 DELAY(5); 2172 } 2173 2174 if (j >= NVRAM_TIMEOUT_COUNT) { 2175 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2176 rc = EBUSY; 2177 } 2178 2179 DBEXIT(BCE_VERBOSE_NVRAM); 2180 return (rc); 2181 } 2182 2183 2184 #ifdef BCE_NVRAM_WRITE_SUPPORT 2185 /****************************************************************************/ 2186 /* Enable NVRAM write access. */ 2187 /* */ 2188 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2189 /* */ 2190 /* Returns: */ 2191 /* 0 on success, positive value on failure. */ 2192 /****************************************************************************/ 2193 static int 2194 bce_enable_nvram_write(struct bce_softc *sc) 2195 { 2196 u32 val; 2197 int rc = 0; 2198 2199 DBENTER(BCE_VERBOSE_NVRAM); 2200 2201 val = REG_RD(sc, BCE_MISC_CFG); 2202 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2203 2204 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2205 int j; 2206 2207 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2208 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2209 2210 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2211 DELAY(5); 2212 2213 val = REG_RD(sc, BCE_NVM_COMMAND); 2214 if (val & BCE_NVM_COMMAND_DONE) 2215 break; 2216 } 2217 2218 if (j >= NVRAM_TIMEOUT_COUNT) { 2219 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2220 rc = EBUSY; 2221 } 2222 } 2223 2224 DBENTER(BCE_VERBOSE_NVRAM); 2225 return (rc); 2226 } 2227 2228 2229 /****************************************************************************/ 2230 /* Disable NVRAM write access. */ 2231 /* */ 2232 /* When the caller is finished writing to NVRAM write access must be */ 2233 /* disabled. */ 2234 /* */ 2235 /* Returns: */ 2236 /* Nothing. */ 2237 /****************************************************************************/ 2238 static void 2239 bce_disable_nvram_write(struct bce_softc *sc) 2240 { 2241 u32 val; 2242 2243 DBENTER(BCE_VERBOSE_NVRAM); 2244 2245 val = REG_RD(sc, BCE_MISC_CFG); 2246 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2247 2248 DBEXIT(BCE_VERBOSE_NVRAM); 2249 2250 } 2251 #endif 2252 2253 2254 /****************************************************************************/ 2255 /* Enable NVRAM access. */ 2256 /* */ 2257 /* Before accessing NVRAM for read or write operations the caller must */ 2258 /* enabled NVRAM access. */ 2259 /* */ 2260 /* Returns: */ 2261 /* Nothing. */ 2262 /****************************************************************************/ 2263 static void 2264 bce_enable_nvram_access(struct bce_softc *sc) 2265 { 2266 u32 val; 2267 2268 DBENTER(BCE_VERBOSE_NVRAM); 2269 2270 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2271 /* Enable both bits, even on read. */ 2272 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2273 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2274 2275 DBEXIT(BCE_VERBOSE_NVRAM); 2276 } 2277 2278 2279 /****************************************************************************/ 2280 /* Disable NVRAM access. */ 2281 /* */ 2282 /* When the caller is finished accessing NVRAM access must be disabled. */ 2283 /* */ 2284 /* Returns: */ 2285 /* Nothing. */ 2286 /****************************************************************************/ 2287 static void 2288 bce_disable_nvram_access(struct bce_softc *sc) 2289 { 2290 u32 val; 2291 2292 DBENTER(BCE_VERBOSE_NVRAM); 2293 2294 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2295 2296 /* Disable both bits, even after read. */ 2297 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2298 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2299 2300 DBEXIT(BCE_VERBOSE_NVRAM); 2301 } 2302 2303 2304 #ifdef BCE_NVRAM_WRITE_SUPPORT 2305 /****************************************************************************/ 2306 /* Erase NVRAM page before writing. */ 2307 /* */ 2308 /* Non-buffered flash parts require that a page be erased before it is */ 2309 /* written. */ 2310 /* */ 2311 /* Returns: */ 2312 /* 0 on success, positive value on failure. */ 2313 /****************************************************************************/ 2314 static int 2315 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2316 { 2317 u32 cmd; 2318 int j, rc = 0; 2319 2320 DBENTER(BCE_VERBOSE_NVRAM); 2321 2322 /* Buffered flash doesn't require an erase. */ 2323 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2324 goto bce_nvram_erase_page_exit; 2325 2326 /* Build an erase command. */ 2327 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2328 BCE_NVM_COMMAND_DOIT; 2329 2330 /* 2331 * Clear the DONE bit separately, set the NVRAM adress to erase, 2332 * and issue the erase command. 2333 */ 2334 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2335 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2336 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2337 2338 /* Wait for completion. */ 2339 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2340 u32 val; 2341 2342 DELAY(5); 2343 2344 val = REG_RD(sc, BCE_NVM_COMMAND); 2345 if (val & BCE_NVM_COMMAND_DONE) 2346 break; 2347 } 2348 2349 if (j >= NVRAM_TIMEOUT_COUNT) { 2350 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2351 rc = EBUSY; 2352 } 2353 2354 bce_nvram_erase_page_exit: 2355 DBEXIT(BCE_VERBOSE_NVRAM); 2356 return (rc); 2357 } 2358 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2359 2360 2361 /****************************************************************************/ 2362 /* Read a dword (32 bits) from NVRAM. */ 2363 /* */ 2364 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2365 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2366 /* */ 2367 /* Returns: */ 2368 /* 0 on success and the 32 bit value read, positive value on failure. */ 2369 /****************************************************************************/ 2370 static int 2371 bce_nvram_read_dword(struct bce_softc *sc, 2372 u32 offset, u8 *ret_val, u32 cmd_flags) 2373 { 2374 u32 cmd; 2375 int i, rc = 0; 2376 2377 DBENTER(BCE_EXTREME_NVRAM); 2378 2379 /* Build the command word. */ 2380 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2381 2382 /* Calculate the offset for buffered flash if translation is used. */ 2383 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2384 offset = ((offset / sc->bce_flash_info->page_size) << 2385 sc->bce_flash_info->page_bits) + 2386 (offset % sc->bce_flash_info->page_size); 2387 } 2388 2389 /* 2390 * Clear the DONE bit separately, set the address to read, 2391 * and issue the read. 2392 */ 2393 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2394 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2395 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2396 2397 /* Wait for completion. */ 2398 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2399 u32 val; 2400 2401 DELAY(5); 2402 2403 val = REG_RD(sc, BCE_NVM_COMMAND); 2404 if (val & BCE_NVM_COMMAND_DONE) { 2405 val = REG_RD(sc, BCE_NVM_READ); 2406 2407 val = bce_be32toh(val); 2408 memcpy(ret_val, &val, 4); 2409 break; 2410 } 2411 } 2412 2413 /* Check for errors. */ 2414 if (i >= NVRAM_TIMEOUT_COUNT) { 2415 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2416 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2417 rc = EBUSY; 2418 } 2419 2420 DBEXIT(BCE_EXTREME_NVRAM); 2421 return(rc); 2422 } 2423 2424 2425 #ifdef BCE_NVRAM_WRITE_SUPPORT 2426 /****************************************************************************/ 2427 /* Write a dword (32 bits) to NVRAM. */ 2428 /* */ 2429 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2430 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2431 /* enabled NVRAM write access. */ 2432 /* */ 2433 /* Returns: */ 2434 /* 0 on success, positive value on failure. */ 2435 /****************************************************************************/ 2436 static int 2437 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2438 u32 cmd_flags) 2439 { 2440 u32 cmd, val32; 2441 int j, rc = 0; 2442 2443 DBENTER(BCE_VERBOSE_NVRAM); 2444 2445 /* Build the command word. */ 2446 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2447 2448 /* Calculate the offset for buffered flash if translation is used. */ 2449 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2450 offset = ((offset / sc->bce_flash_info->page_size) << 2451 sc->bce_flash_info->page_bits) + 2452 (offset % sc->bce_flash_info->page_size); 2453 } 2454 2455 /* 2456 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2457 * set the NVRAM address to write, and issue the write command 2458 */ 2459 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2460 memcpy(&val32, val, 4); 2461 val32 = htobe32(val32); 2462 REG_WR(sc, BCE_NVM_WRITE, val32); 2463 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2464 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2465 2466 /* Wait for completion. */ 2467 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2468 DELAY(5); 2469 2470 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2471 break; 2472 } 2473 if (j >= NVRAM_TIMEOUT_COUNT) { 2474 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2475 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2476 rc = EBUSY; 2477 } 2478 2479 DBEXIT(BCE_VERBOSE_NVRAM); 2480 return (rc); 2481 } 2482 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2483 2484 2485 /****************************************************************************/ 2486 /* Initialize NVRAM access. */ 2487 /* */ 2488 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2489 /* access that device. */ 2490 /* */ 2491 /* Returns: */ 2492 /* 0 on success, positive value on failure. */ 2493 /****************************************************************************/ 2494 static int 2495 bce_init_nvram(struct bce_softc *sc) 2496 { 2497 u32 val; 2498 int j, entry_count, rc = 0; 2499 const struct flash_spec *flash; 2500 2501 DBENTER(BCE_VERBOSE_NVRAM); 2502 2503 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2504 sc->bce_flash_info = &flash_5709; 2505 goto bce_init_nvram_get_flash_size; 2506 } 2507 2508 /* Determine the selected interface. */ 2509 val = REG_RD(sc, BCE_NVM_CFG1); 2510 2511 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2512 2513 /* 2514 * Flash reconfiguration is required to support additional 2515 * NVRAM devices not directly supported in hardware. 2516 * Check if the flash interface was reconfigured 2517 * by the bootcode. 2518 */ 2519 2520 if (val & 0x40000000) { 2521 /* Flash interface reconfigured by bootcode. */ 2522 2523 DBPRINT(sc,BCE_INFO_LOAD, 2524 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2525 2526 for (j = 0, flash = &flash_table[0]; j < entry_count; 2527 j++, flash++) { 2528 if ((val & FLASH_BACKUP_STRAP_MASK) == 2529 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2530 sc->bce_flash_info = flash; 2531 break; 2532 } 2533 } 2534 } else { 2535 /* Flash interface not yet reconfigured. */ 2536 u32 mask; 2537 2538 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2539 __FUNCTION__); 2540 2541 if (val & (1 << 23)) 2542 mask = FLASH_BACKUP_STRAP_MASK; 2543 else 2544 mask = FLASH_STRAP_MASK; 2545 2546 /* Look for the matching NVRAM device configuration data. */ 2547 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2548 2549 /* Check if the device matches any of the known devices. */ 2550 if ((val & mask) == (flash->strapping & mask)) { 2551 /* Found a device match. */ 2552 sc->bce_flash_info = flash; 2553 2554 /* Request access to the flash interface. */ 2555 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2556 return rc; 2557 2558 /* Reconfigure the flash interface. */ 2559 bce_enable_nvram_access(sc); 2560 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2561 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2562 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2563 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2564 bce_disable_nvram_access(sc); 2565 bce_release_nvram_lock(sc); 2566 2567 break; 2568 } 2569 } 2570 } 2571 2572 /* Check if a matching device was found. */ 2573 if (j == entry_count) { 2574 sc->bce_flash_info = NULL; 2575 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2576 __FILE__, __LINE__); 2577 DBEXIT(BCE_VERBOSE_NVRAM); 2578 return (ENODEV); 2579 } 2580 2581 bce_init_nvram_get_flash_size: 2582 /* Write the flash config data to the shared memory interface. */ 2583 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2584 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2585 if (val) 2586 sc->bce_flash_size = val; 2587 else 2588 sc->bce_flash_size = sc->bce_flash_info->total_size; 2589 2590 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2591 __FUNCTION__, sc->bce_flash_info->name, 2592 sc->bce_flash_info->total_size); 2593 2594 DBEXIT(BCE_VERBOSE_NVRAM); 2595 return rc; 2596 } 2597 2598 2599 /****************************************************************************/ 2600 /* Read an arbitrary range of data from NVRAM. */ 2601 /* */ 2602 /* Prepares the NVRAM interface for access and reads the requested data */ 2603 /* into the supplied buffer. */ 2604 /* */ 2605 /* Returns: */ 2606 /* 0 on success and the data read, positive value on failure. */ 2607 /****************************************************************************/ 2608 static int 2609 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2610 int buf_size) 2611 { 2612 int rc = 0; 2613 u32 cmd_flags, offset32, len32, extra; 2614 2615 DBENTER(BCE_VERBOSE_NVRAM); 2616 2617 if (buf_size == 0) 2618 goto bce_nvram_read_exit; 2619 2620 /* Request access to the flash interface. */ 2621 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2622 goto bce_nvram_read_exit; 2623 2624 /* Enable access to flash interface */ 2625 bce_enable_nvram_access(sc); 2626 2627 len32 = buf_size; 2628 offset32 = offset; 2629 extra = 0; 2630 2631 cmd_flags = 0; 2632 2633 if (offset32 & 3) { 2634 u8 buf[4]; 2635 u32 pre_len; 2636 2637 offset32 &= ~3; 2638 pre_len = 4 - (offset & 3); 2639 2640 if (pre_len >= len32) { 2641 pre_len = len32; 2642 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2643 } 2644 else { 2645 cmd_flags = BCE_NVM_COMMAND_FIRST; 2646 } 2647 2648 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2649 2650 if (rc) 2651 return rc; 2652 2653 memcpy(ret_buf, buf + (offset & 3), pre_len); 2654 2655 offset32 += 4; 2656 ret_buf += pre_len; 2657 len32 -= pre_len; 2658 } 2659 2660 if (len32 & 3) { 2661 extra = 4 - (len32 & 3); 2662 len32 = (len32 + 4) & ~3; 2663 } 2664 2665 if (len32 == 4) { 2666 u8 buf[4]; 2667 2668 if (cmd_flags) 2669 cmd_flags = BCE_NVM_COMMAND_LAST; 2670 else 2671 cmd_flags = BCE_NVM_COMMAND_FIRST | 2672 BCE_NVM_COMMAND_LAST; 2673 2674 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2675 2676 memcpy(ret_buf, buf, 4 - extra); 2677 } 2678 else if (len32 > 0) { 2679 u8 buf[4]; 2680 2681 /* Read the first word. */ 2682 if (cmd_flags) 2683 cmd_flags = 0; 2684 else 2685 cmd_flags = BCE_NVM_COMMAND_FIRST; 2686 2687 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2688 2689 /* Advance to the next dword. */ 2690 offset32 += 4; 2691 ret_buf += 4; 2692 len32 -= 4; 2693 2694 while (len32 > 4 && rc == 0) { 2695 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2696 2697 /* Advance to the next dword. */ 2698 offset32 += 4; 2699 ret_buf += 4; 2700 len32 -= 4; 2701 } 2702 2703 if (rc) 2704 goto bce_nvram_read_locked_exit; 2705 2706 cmd_flags = BCE_NVM_COMMAND_LAST; 2707 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2708 2709 memcpy(ret_buf, buf, 4 - extra); 2710 } 2711 2712 bce_nvram_read_locked_exit: 2713 /* Disable access to flash interface and release the lock. */ 2714 bce_disable_nvram_access(sc); 2715 bce_release_nvram_lock(sc); 2716 2717 bce_nvram_read_exit: 2718 DBEXIT(BCE_VERBOSE_NVRAM); 2719 return rc; 2720 } 2721 2722 2723 #ifdef BCE_NVRAM_WRITE_SUPPORT 2724 /****************************************************************************/ 2725 /* Write an arbitrary range of data from NVRAM. */ 2726 /* */ 2727 /* Prepares the NVRAM interface for write access and writes the requested */ 2728 /* data from the supplied buffer. The caller is responsible for */ 2729 /* calculating any appropriate CRCs. */ 2730 /* */ 2731 /* Returns: */ 2732 /* 0 on success, positive value on failure. */ 2733 /****************************************************************************/ 2734 static int 2735 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2736 int buf_size) 2737 { 2738 u32 written, offset32, len32; 2739 u8 *buf, start[4], end[4]; 2740 int rc = 0; 2741 int align_start, align_end; 2742 2743 DBENTER(BCE_VERBOSE_NVRAM); 2744 2745 buf = data_buf; 2746 offset32 = offset; 2747 len32 = buf_size; 2748 align_start = align_end = 0; 2749 2750 if ((align_start = (offset32 & 3))) { 2751 offset32 &= ~3; 2752 len32 += align_start; 2753 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2754 goto bce_nvram_write_exit; 2755 } 2756 2757 if (len32 & 3) { 2758 if ((len32 > 4) || !align_start) { 2759 align_end = 4 - (len32 & 3); 2760 len32 += align_end; 2761 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2762 end, 4))) { 2763 goto bce_nvram_write_exit; 2764 } 2765 } 2766 } 2767 2768 if (align_start || align_end) { 2769 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2770 if (buf == 0) { 2771 rc = ENOMEM; 2772 goto bce_nvram_write_exit; 2773 } 2774 2775 if (align_start) { 2776 memcpy(buf, start, 4); 2777 } 2778 2779 if (align_end) { 2780 memcpy(buf + len32 - 4, end, 4); 2781 } 2782 memcpy(buf + align_start, data_buf, buf_size); 2783 } 2784 2785 written = 0; 2786 while ((written < len32) && (rc == 0)) { 2787 u32 page_start, page_end, data_start, data_end; 2788 u32 addr, cmd_flags; 2789 int i; 2790 u8 flash_buffer[264]; 2791 2792 /* Find the page_start addr */ 2793 page_start = offset32 + written; 2794 page_start -= (page_start % sc->bce_flash_info->page_size); 2795 /* Find the page_end addr */ 2796 page_end = page_start + sc->bce_flash_info->page_size; 2797 /* Find the data_start addr */ 2798 data_start = (written == 0) ? offset32 : page_start; 2799 /* Find the data_end addr */ 2800 data_end = (page_end > offset32 + len32) ? 2801 (offset32 + len32) : page_end; 2802 2803 /* Request access to the flash interface. */ 2804 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2805 goto bce_nvram_write_exit; 2806 2807 /* Enable access to flash interface */ 2808 bce_enable_nvram_access(sc); 2809 2810 cmd_flags = BCE_NVM_COMMAND_FIRST; 2811 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2812 int j; 2813 2814 /* Read the whole page into the buffer 2815 * (non-buffer flash only) */ 2816 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2817 if (j == (sc->bce_flash_info->page_size - 4)) { 2818 cmd_flags |= BCE_NVM_COMMAND_LAST; 2819 } 2820 rc = bce_nvram_read_dword(sc, 2821 page_start + j, 2822 &flash_buffer[j], 2823 cmd_flags); 2824 2825 if (rc) 2826 goto bce_nvram_write_locked_exit; 2827 2828 cmd_flags = 0; 2829 } 2830 } 2831 2832 /* Enable writes to flash interface (unlock write-protect) */ 2833 if ((rc = bce_enable_nvram_write(sc)) != 0) 2834 goto bce_nvram_write_locked_exit; 2835 2836 /* Erase the page */ 2837 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2838 goto bce_nvram_write_locked_exit; 2839 2840 /* Re-enable the write again for the actual write */ 2841 bce_enable_nvram_write(sc); 2842 2843 /* Loop to write back the buffer data from page_start to 2844 * data_start */ 2845 i = 0; 2846 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2847 for (addr = page_start; addr < data_start; 2848 addr += 4, i += 4) { 2849 2850 rc = bce_nvram_write_dword(sc, addr, 2851 &flash_buffer[i], cmd_flags); 2852 2853 if (rc != 0) 2854 goto bce_nvram_write_locked_exit; 2855 2856 cmd_flags = 0; 2857 } 2858 } 2859 2860 /* Loop to write the new data from data_start to data_end */ 2861 for (addr = data_start; addr < data_end; addr += 4, i++) { 2862 if ((addr == page_end - 4) || 2863 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2864 (addr == data_end - 4))) { 2865 2866 cmd_flags |= BCE_NVM_COMMAND_LAST; 2867 } 2868 rc = bce_nvram_write_dword(sc, addr, buf, 2869 cmd_flags); 2870 2871 if (rc != 0) 2872 goto bce_nvram_write_locked_exit; 2873 2874 cmd_flags = 0; 2875 buf += 4; 2876 } 2877 2878 /* Loop to write back the buffer data from data_end 2879 * to page_end */ 2880 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2881 for (addr = data_end; addr < page_end; 2882 addr += 4, i += 4) { 2883 2884 if (addr == page_end-4) { 2885 cmd_flags = BCE_NVM_COMMAND_LAST; 2886 } 2887 rc = bce_nvram_write_dword(sc, addr, 2888 &flash_buffer[i], cmd_flags); 2889 2890 if (rc != 0) 2891 goto bce_nvram_write_locked_exit; 2892 2893 cmd_flags = 0; 2894 } 2895 } 2896 2897 /* Disable writes to flash interface (lock write-protect) */ 2898 bce_disable_nvram_write(sc); 2899 2900 /* Disable access to flash interface */ 2901 bce_disable_nvram_access(sc); 2902 bce_release_nvram_lock(sc); 2903 2904 /* Increment written */ 2905 written += data_end - data_start; 2906 } 2907 2908 goto bce_nvram_write_exit; 2909 2910 bce_nvram_write_locked_exit: 2911 bce_disable_nvram_write(sc); 2912 bce_disable_nvram_access(sc); 2913 bce_release_nvram_lock(sc); 2914 2915 bce_nvram_write_exit: 2916 if (align_start || align_end) 2917 free(buf, M_DEVBUF); 2918 2919 DBEXIT(BCE_VERBOSE_NVRAM); 2920 return (rc); 2921 } 2922 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2923 2924 2925 /****************************************************************************/ 2926 /* Verifies that NVRAM is accessible and contains valid data. */ 2927 /* */ 2928 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2929 /* correct. */ 2930 /* */ 2931 /* Returns: */ 2932 /* 0 on success, positive value on failure. */ 2933 /****************************************************************************/ 2934 static int 2935 bce_nvram_test(struct bce_softc *sc) 2936 { 2937 u32 buf[BCE_NVRAM_SIZE / 4]; 2938 u8 *data = (u8 *) buf; 2939 int rc = 0; 2940 u32 magic, csum; 2941 2942 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2943 2944 /* 2945 * Check that the device NVRAM is valid by reading 2946 * the magic value at offset 0. 2947 */ 2948 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2949 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2950 __FILE__, __LINE__); 2951 goto bce_nvram_test_exit; 2952 } 2953 2954 /* 2955 * Verify that offset 0 of the NVRAM contains 2956 * a valid magic number. 2957 */ 2958 magic = bce_be32toh(buf[0]); 2959 if (magic != BCE_NVRAM_MAGIC) { 2960 rc = ENODEV; 2961 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2962 "Expected: 0x%08X, Found: 0x%08X\n", 2963 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2964 goto bce_nvram_test_exit; 2965 } 2966 2967 /* 2968 * Verify that the device NVRAM includes valid 2969 * configuration data. 2970 */ 2971 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2972 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2973 "Information from NVRAM!\n", __FILE__, __LINE__); 2974 goto bce_nvram_test_exit; 2975 } 2976 2977 csum = ether_crc32_le(data, 0x100); 2978 if (csum != BCE_CRC32_RESIDUAL) { 2979 rc = ENODEV; 2980 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2981 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2982 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2983 goto bce_nvram_test_exit; 2984 } 2985 2986 csum = ether_crc32_le(data + 0x100, 0x100); 2987 if (csum != BCE_CRC32_RESIDUAL) { 2988 rc = ENODEV; 2989 BCE_PRINTF("%s(%d): Invalid feature configuration " 2990 "information NVRAM CRC! Expected: 0x%08X, " 2991 "Found: 08%08X\n", __FILE__, __LINE__, 2992 BCE_CRC32_RESIDUAL, csum); 2993 } 2994 2995 bce_nvram_test_exit: 2996 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2997 return rc; 2998 } 2999 3000 3001 /****************************************************************************/ 3002 /* Calculates the size of the buffers to allocate based on the MTU. */ 3003 /* */ 3004 /* Returns: */ 3005 /* Nothing. */ 3006 /****************************************************************************/ 3007 static void 3008 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 3009 { 3010 DBENTER(BCE_VERBOSE_LOAD); 3011 3012 /* Use a single allocation type when header splitting enabled. */ 3013 if (bce_hdr_split == TRUE) { 3014 sc->rx_bd_mbuf_alloc_size = MHLEN; 3015 /* Make sure offset is 16 byte aligned for hardware. */ 3016 sc->rx_bd_mbuf_align_pad = 3017 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 3018 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 3019 sc->rx_bd_mbuf_align_pad; 3020 } else { 3021 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 3022 ETHER_CRC_LEN) > MCLBYTES) { 3023 /* Setup for jumbo RX buffer allocations. */ 3024 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 3025 sc->rx_bd_mbuf_align_pad = 3026 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3027 sc->rx_bd_mbuf_data_len = 3028 sc->rx_bd_mbuf_alloc_size - 3029 sc->rx_bd_mbuf_align_pad; 3030 } else { 3031 /* Setup for standard RX buffer allocations. */ 3032 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3033 sc->rx_bd_mbuf_align_pad = 3034 roundup2(MCLBYTES, 16) - MCLBYTES; 3035 sc->rx_bd_mbuf_data_len = 3036 sc->rx_bd_mbuf_alloc_size - 3037 sc->rx_bd_mbuf_align_pad; 3038 } 3039 } 3040 3041 // DBPRINT(sc, BCE_INFO_LOAD, 3042 DBPRINT(sc, BCE_WARN, 3043 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3044 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3045 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3046 sc->rx_bd_mbuf_align_pad); 3047 3048 DBEXIT(BCE_VERBOSE_LOAD); 3049 } 3050 3051 /****************************************************************************/ 3052 /* Identifies the current media type of the controller and sets the PHY */ 3053 /* address. */ 3054 /* */ 3055 /* Returns: */ 3056 /* Nothing. */ 3057 /****************************************************************************/ 3058 static void 3059 bce_get_media(struct bce_softc *sc) 3060 { 3061 u32 val; 3062 3063 DBENTER(BCE_VERBOSE_PHY); 3064 3065 /* Assume PHY address for copper controllers. */ 3066 sc->bce_phy_addr = 1; 3067 3068 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3069 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3070 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3071 u32 strap; 3072 3073 /* 3074 * The BCM5709S is software configurable 3075 * for Copper or SerDes operation. 3076 */ 3077 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3078 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3079 "for copper.\n"); 3080 goto bce_get_media_exit; 3081 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3082 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3083 "for dual media.\n"); 3084 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3085 goto bce_get_media_exit; 3086 } 3087 3088 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3089 strap = (val & 3090 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3091 else 3092 strap = (val & 3093 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3094 3095 if (pci_get_function(sc->bce_dev) == 0) { 3096 switch (strap) { 3097 case 0x4: 3098 case 0x5: 3099 case 0x6: 3100 DBPRINT(sc, BCE_INFO_LOAD, 3101 "BCM5709 s/w configured for SerDes.\n"); 3102 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3103 break; 3104 default: 3105 DBPRINT(sc, BCE_INFO_LOAD, 3106 "BCM5709 s/w configured for Copper.\n"); 3107 break; 3108 } 3109 } else { 3110 switch (strap) { 3111 case 0x1: 3112 case 0x2: 3113 case 0x4: 3114 DBPRINT(sc, BCE_INFO_LOAD, 3115 "BCM5709 s/w configured for SerDes.\n"); 3116 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3117 break; 3118 default: 3119 DBPRINT(sc, BCE_INFO_LOAD, 3120 "BCM5709 s/w configured for Copper.\n"); 3121 break; 3122 } 3123 } 3124 3125 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3126 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3127 3128 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3129 3130 sc->bce_flags |= BCE_NO_WOL_FLAG; 3131 3132 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3133 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3134 3135 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3136 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3137 sc->bce_phy_addr = 2; 3138 3139 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3140 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3141 sc->bce_phy_flags |= 3142 BCE_PHY_2_5G_CAPABLE_FLAG; 3143 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3144 "capable adapter\n"); 3145 } 3146 } 3147 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3148 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3149 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3150 3151 bce_get_media_exit: 3152 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3153 "Using PHY address %d.\n", sc->bce_phy_addr); 3154 3155 DBEXIT(BCE_VERBOSE_PHY); 3156 } 3157 3158 3159 /****************************************************************************/ 3160 /* Performs PHY initialization required before MII drivers access the */ 3161 /* device. */ 3162 /* */ 3163 /* Returns: */ 3164 /* Nothing. */ 3165 /****************************************************************************/ 3166 static void 3167 bce_init_media(struct bce_softc *sc) 3168 { 3169 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3170 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3171 /* 3172 * Configure 5709S/5716S PHYs to use traditional IEEE 3173 * Clause 22 method. Otherwise we have no way to attach 3174 * the PHY in mii(4) layer. PHY specific configuration 3175 * is done in mii layer. 3176 */ 3177 3178 /* Select auto-negotiation MMD of the PHY. */ 3179 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3180 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3181 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3182 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3183 3184 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3185 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3186 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3187 } 3188 } 3189 3190 3191 /****************************************************************************/ 3192 /* Free any DMA memory owned by the driver. */ 3193 /* */ 3194 /* Scans through each data structre that requires DMA memory and frees */ 3195 /* the memory if allocated. */ 3196 /* */ 3197 /* Returns: */ 3198 /* Nothing. */ 3199 /****************************************************************************/ 3200 static void 3201 bce_dma_free(struct bce_softc *sc) 3202 { 3203 int i; 3204 3205 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3206 3207 /* Free, unmap, and destroy the status block. */ 3208 if (sc->status_block != NULL) { 3209 bus_dmamem_free( 3210 sc->status_tag, 3211 sc->status_block, 3212 sc->status_map); 3213 sc->status_block = NULL; 3214 } 3215 3216 if (sc->status_map != NULL) { 3217 bus_dmamap_unload( 3218 sc->status_tag, 3219 sc->status_map); 3220 bus_dmamap_destroy(sc->status_tag, 3221 sc->status_map); 3222 sc->status_map = NULL; 3223 } 3224 3225 if (sc->status_tag != NULL) { 3226 bus_dma_tag_destroy(sc->status_tag); 3227 sc->status_tag = NULL; 3228 } 3229 3230 3231 /* Free, unmap, and destroy the statistics block. */ 3232 if (sc->stats_block != NULL) { 3233 bus_dmamem_free( 3234 sc->stats_tag, 3235 sc->stats_block, 3236 sc->stats_map); 3237 sc->stats_block = NULL; 3238 } 3239 3240 if (sc->stats_map != NULL) { 3241 bus_dmamap_unload( 3242 sc->stats_tag, 3243 sc->stats_map); 3244 bus_dmamap_destroy(sc->stats_tag, 3245 sc->stats_map); 3246 sc->stats_map = NULL; 3247 } 3248 3249 if (sc->stats_tag != NULL) { 3250 bus_dma_tag_destroy(sc->stats_tag); 3251 sc->stats_tag = NULL; 3252 } 3253 3254 3255 /* Free, unmap and destroy all context memory pages. */ 3256 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3257 for (i = 0; i < sc->ctx_pages; i++ ) { 3258 if (sc->ctx_block[i] != NULL) { 3259 bus_dmamem_free( 3260 sc->ctx_tag, 3261 sc->ctx_block[i], 3262 sc->ctx_map[i]); 3263 sc->ctx_block[i] = NULL; 3264 } 3265 3266 if (sc->ctx_map[i] != NULL) { 3267 bus_dmamap_unload( 3268 sc->ctx_tag, 3269 sc->ctx_map[i]); 3270 bus_dmamap_destroy( 3271 sc->ctx_tag, 3272 sc->ctx_map[i]); 3273 sc->ctx_map[i] = NULL; 3274 } 3275 } 3276 3277 /* Destroy the context memory tag. */ 3278 if (sc->ctx_tag != NULL) { 3279 bus_dma_tag_destroy(sc->ctx_tag); 3280 sc->ctx_tag = NULL; 3281 } 3282 } 3283 3284 3285 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3286 for (i = 0; i < sc->tx_pages; i++ ) { 3287 if (sc->tx_bd_chain[i] != NULL) { 3288 bus_dmamem_free( 3289 sc->tx_bd_chain_tag, 3290 sc->tx_bd_chain[i], 3291 sc->tx_bd_chain_map[i]); 3292 sc->tx_bd_chain[i] = NULL; 3293 } 3294 3295 if (sc->tx_bd_chain_map[i] != NULL) { 3296 bus_dmamap_unload( 3297 sc->tx_bd_chain_tag, 3298 sc->tx_bd_chain_map[i]); 3299 bus_dmamap_destroy( 3300 sc->tx_bd_chain_tag, 3301 sc->tx_bd_chain_map[i]); 3302 sc->tx_bd_chain_map[i] = NULL; 3303 } 3304 } 3305 3306 /* Destroy the TX buffer descriptor tag. */ 3307 if (sc->tx_bd_chain_tag != NULL) { 3308 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3309 sc->tx_bd_chain_tag = NULL; 3310 } 3311 3312 3313 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3314 for (i = 0; i < sc->rx_pages; i++ ) { 3315 if (sc->rx_bd_chain[i] != NULL) { 3316 bus_dmamem_free( 3317 sc->rx_bd_chain_tag, 3318 sc->rx_bd_chain[i], 3319 sc->rx_bd_chain_map[i]); 3320 sc->rx_bd_chain[i] = NULL; 3321 } 3322 3323 if (sc->rx_bd_chain_map[i] != NULL) { 3324 bus_dmamap_unload( 3325 sc->rx_bd_chain_tag, 3326 sc->rx_bd_chain_map[i]); 3327 bus_dmamap_destroy( 3328 sc->rx_bd_chain_tag, 3329 sc->rx_bd_chain_map[i]); 3330 sc->rx_bd_chain_map[i] = NULL; 3331 } 3332 } 3333 3334 /* Destroy the RX buffer descriptor tag. */ 3335 if (sc->rx_bd_chain_tag != NULL) { 3336 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3337 sc->rx_bd_chain_tag = NULL; 3338 } 3339 3340 3341 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3342 if (bce_hdr_split == TRUE) { 3343 for (i = 0; i < sc->pg_pages; i++ ) { 3344 if (sc->pg_bd_chain[i] != NULL) { 3345 bus_dmamem_free( 3346 sc->pg_bd_chain_tag, 3347 sc->pg_bd_chain[i], 3348 sc->pg_bd_chain_map[i]); 3349 sc->pg_bd_chain[i] = NULL; 3350 } 3351 3352 if (sc->pg_bd_chain_map[i] != NULL) { 3353 bus_dmamap_unload( 3354 sc->pg_bd_chain_tag, 3355 sc->pg_bd_chain_map[i]); 3356 bus_dmamap_destroy( 3357 sc->pg_bd_chain_tag, 3358 sc->pg_bd_chain_map[i]); 3359 sc->pg_bd_chain_map[i] = NULL; 3360 } 3361 } 3362 3363 /* Destroy the page buffer descriptor tag. */ 3364 if (sc->pg_bd_chain_tag != NULL) { 3365 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3366 sc->pg_bd_chain_tag = NULL; 3367 } 3368 } 3369 3370 3371 /* Unload and destroy the TX mbuf maps. */ 3372 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3373 if (sc->tx_mbuf_map[i] != NULL) { 3374 bus_dmamap_unload(sc->tx_mbuf_tag, 3375 sc->tx_mbuf_map[i]); 3376 bus_dmamap_destroy(sc->tx_mbuf_tag, 3377 sc->tx_mbuf_map[i]); 3378 sc->tx_mbuf_map[i] = NULL; 3379 } 3380 } 3381 3382 /* Destroy the TX mbuf tag. */ 3383 if (sc->tx_mbuf_tag != NULL) { 3384 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3385 sc->tx_mbuf_tag = NULL; 3386 } 3387 3388 /* Unload and destroy the RX mbuf maps. */ 3389 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3390 if (sc->rx_mbuf_map[i] != NULL) { 3391 bus_dmamap_unload(sc->rx_mbuf_tag, 3392 sc->rx_mbuf_map[i]); 3393 bus_dmamap_destroy(sc->rx_mbuf_tag, 3394 sc->rx_mbuf_map[i]); 3395 sc->rx_mbuf_map[i] = NULL; 3396 } 3397 } 3398 3399 /* Destroy the RX mbuf tag. */ 3400 if (sc->rx_mbuf_tag != NULL) { 3401 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3402 sc->rx_mbuf_tag = NULL; 3403 } 3404 3405 /* Unload and destroy the page mbuf maps. */ 3406 if (bce_hdr_split == TRUE) { 3407 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3408 if (sc->pg_mbuf_map[i] != NULL) { 3409 bus_dmamap_unload(sc->pg_mbuf_tag, 3410 sc->pg_mbuf_map[i]); 3411 bus_dmamap_destroy(sc->pg_mbuf_tag, 3412 sc->pg_mbuf_map[i]); 3413 sc->pg_mbuf_map[i] = NULL; 3414 } 3415 } 3416 3417 /* Destroy the page mbuf tag. */ 3418 if (sc->pg_mbuf_tag != NULL) { 3419 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3420 sc->pg_mbuf_tag = NULL; 3421 } 3422 } 3423 3424 /* Destroy the parent tag */ 3425 if (sc->parent_tag != NULL) { 3426 bus_dma_tag_destroy(sc->parent_tag); 3427 sc->parent_tag = NULL; 3428 } 3429 3430 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3431 } 3432 3433 3434 /****************************************************************************/ 3435 /* Get DMA memory from the OS. */ 3436 /* */ 3437 /* Validates that the OS has provided DMA buffers in response to a */ 3438 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3439 /* When the callback is used the OS will return 0 for the mapping function */ 3440 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3441 /* failures back to the caller. */ 3442 /* */ 3443 /* Returns: */ 3444 /* Nothing. */ 3445 /****************************************************************************/ 3446 static void 3447 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3448 { 3449 bus_addr_t *busaddr = arg; 3450 3451 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3452 __FUNCTION__, nseg)); 3453 /* Simulate a mapping failure. */ 3454 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3455 error = ENOMEM); 3456 3457 /* ToDo: How to increment debug sim_count variable here? */ 3458 3459 /* Check for an error and signal the caller that an error occurred. */ 3460 if (error) { 3461 *busaddr = 0; 3462 } else { 3463 *busaddr = segs->ds_addr; 3464 } 3465 } 3466 3467 3468 /****************************************************************************/ 3469 /* Allocate any DMA memory needed by the driver. */ 3470 /* */ 3471 /* Allocates DMA memory needed for the various global structures needed by */ 3472 /* hardware. */ 3473 /* */ 3474 /* Memory alignment requirements: */ 3475 /* +-----------------+----------+----------+----------+----------+ */ 3476 /* | | 5706 | 5708 | 5709 | 5716 | */ 3477 /* +-----------------+----------+----------+----------+----------+ */ 3478 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3479 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3480 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3481 /* |PG Buffers | none | none | none | none | */ 3482 /* |TX Buffers | none | none | none | none | */ 3483 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3484 /* |Context Memory | | | | | */ 3485 /* +-----------------+----------+----------+----------+----------+ */ 3486 /* */ 3487 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3488 /* */ 3489 /* Returns: */ 3490 /* 0 for success, positive value for failure. */ 3491 /****************************************************************************/ 3492 static int 3493 bce_dma_alloc(device_t dev) 3494 { 3495 struct bce_softc *sc; 3496 int i, error, rc = 0; 3497 bus_size_t max_size, max_seg_size; 3498 int max_segments; 3499 3500 sc = device_get_softc(dev); 3501 3502 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3503 3504 /* 3505 * Allocate the parent bus DMA tag appropriate for PCI. 3506 */ 3507 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3508 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3509 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3510 &sc->parent_tag)) { 3511 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3512 __FILE__, __LINE__); 3513 rc = ENOMEM; 3514 goto bce_dma_alloc_exit; 3515 } 3516 3517 /* 3518 * Create a DMA tag for the status block, allocate and clear the 3519 * memory, map the memory into DMA space, and fetch the physical 3520 * address of the block. 3521 */ 3522 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3523 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3524 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3525 0, NULL, NULL, &sc->status_tag)) { 3526 BCE_PRINTF("%s(%d): Could not allocate status block " 3527 "DMA tag!\n", __FILE__, __LINE__); 3528 rc = ENOMEM; 3529 goto bce_dma_alloc_exit; 3530 } 3531 3532 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3533 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3534 &sc->status_map)) { 3535 BCE_PRINTF("%s(%d): Could not allocate status block " 3536 "DMA memory!\n", __FILE__, __LINE__); 3537 rc = ENOMEM; 3538 goto bce_dma_alloc_exit; 3539 } 3540 3541 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3542 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3543 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3544 3545 if (error || sc->status_block_paddr == 0) { 3546 BCE_PRINTF("%s(%d): Could not map status block " 3547 "DMA memory!\n", __FILE__, __LINE__); 3548 rc = ENOMEM; 3549 goto bce_dma_alloc_exit; 3550 } 3551 3552 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3553 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3554 3555 /* 3556 * Create a DMA tag for the statistics block, allocate and clear the 3557 * memory, map the memory into DMA space, and fetch the physical 3558 * address of the block. 3559 */ 3560 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3561 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3562 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3563 0, NULL, NULL, &sc->stats_tag)) { 3564 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3565 "DMA tag!\n", __FILE__, __LINE__); 3566 rc = ENOMEM; 3567 goto bce_dma_alloc_exit; 3568 } 3569 3570 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3571 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3572 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3573 "DMA memory!\n", __FILE__, __LINE__); 3574 rc = ENOMEM; 3575 goto bce_dma_alloc_exit; 3576 } 3577 3578 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3579 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3580 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3581 3582 if (error || sc->stats_block_paddr == 0) { 3583 BCE_PRINTF("%s(%d): Could not map statistics block " 3584 "DMA memory!\n", __FILE__, __LINE__); 3585 rc = ENOMEM; 3586 goto bce_dma_alloc_exit; 3587 } 3588 3589 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3590 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3591 3592 /* BCM5709 uses host memory as cache for context memory. */ 3593 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3594 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3595 if (sc->ctx_pages == 0) 3596 sc->ctx_pages = 1; 3597 3598 DBRUNIF((sc->ctx_pages > 512), 3599 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3600 __FILE__, __LINE__, sc->ctx_pages)); 3601 3602 /* 3603 * Create a DMA tag for the context pages, 3604 * allocate and clear the memory, map the 3605 * memory into DMA space, and fetch the 3606 * physical address of the block. 3607 */ 3608 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3609 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3610 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3611 0, NULL, NULL, &sc->ctx_tag)) { 3612 BCE_PRINTF("%s(%d): Could not allocate CTX " 3613 "DMA tag!\n", __FILE__, __LINE__); 3614 rc = ENOMEM; 3615 goto bce_dma_alloc_exit; 3616 } 3617 3618 for (i = 0; i < sc->ctx_pages; i++) { 3619 3620 if(bus_dmamem_alloc(sc->ctx_tag, 3621 (void **)&sc->ctx_block[i], 3622 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3623 &sc->ctx_map[i])) { 3624 BCE_PRINTF("%s(%d): Could not allocate CTX " 3625 "DMA memory!\n", __FILE__, __LINE__); 3626 rc = ENOMEM; 3627 goto bce_dma_alloc_exit; 3628 } 3629 3630 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3631 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3632 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3633 3634 if (error || sc->ctx_paddr[i] == 0) { 3635 BCE_PRINTF("%s(%d): Could not map CTX " 3636 "DMA memory!\n", __FILE__, __LINE__); 3637 rc = ENOMEM; 3638 goto bce_dma_alloc_exit; 3639 } 3640 3641 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3642 "= 0x%jX\n", __FUNCTION__, i, 3643 (uintmax_t) sc->ctx_paddr[i]); 3644 } 3645 } 3646 3647 /* 3648 * Create a DMA tag for the TX buffer descriptor chain, 3649 * allocate and clear the memory, and fetch the 3650 * physical address of the block. 3651 */ 3652 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3653 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3654 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3655 NULL, NULL, &sc->tx_bd_chain_tag)) { 3656 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3657 "chain DMA tag!\n", __FILE__, __LINE__); 3658 rc = ENOMEM; 3659 goto bce_dma_alloc_exit; 3660 } 3661 3662 for (i = 0; i < sc->tx_pages; i++) { 3663 3664 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3665 (void **)&sc->tx_bd_chain[i], 3666 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3667 &sc->tx_bd_chain_map[i])) { 3668 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3669 "chain DMA memory!\n", __FILE__, __LINE__); 3670 rc = ENOMEM; 3671 goto bce_dma_alloc_exit; 3672 } 3673 3674 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3675 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3676 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3677 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3678 3679 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3680 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3681 "chain DMA memory!\n", __FILE__, __LINE__); 3682 rc = ENOMEM; 3683 goto bce_dma_alloc_exit; 3684 } 3685 3686 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3687 "0x%jX\n", __FUNCTION__, i, 3688 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3689 } 3690 3691 /* Check the required size before mapping to conserve resources. */ 3692 if (bce_tso_enable) { 3693 max_size = BCE_TSO_MAX_SIZE; 3694 max_segments = BCE_MAX_SEGMENTS; 3695 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3696 } else { 3697 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3698 max_segments = BCE_MAX_SEGMENTS; 3699 max_seg_size = MCLBYTES; 3700 } 3701 3702 /* Create a DMA tag for TX mbufs. */ 3703 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3704 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3705 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3706 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3707 __FILE__, __LINE__); 3708 rc = ENOMEM; 3709 goto bce_dma_alloc_exit; 3710 } 3711 3712 /* Create DMA maps for the TX mbufs clusters. */ 3713 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3714 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3715 &sc->tx_mbuf_map[i])) { 3716 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3717 "map!\n", __FILE__, __LINE__); 3718 rc = ENOMEM; 3719 goto bce_dma_alloc_exit; 3720 } 3721 } 3722 3723 /* 3724 * Create a DMA tag for the RX buffer descriptor chain, 3725 * allocate and clear the memory, and fetch the physical 3726 * address of the blocks. 3727 */ 3728 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3729 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3730 sc->max_bus_addr, NULL, NULL, 3731 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3732 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3733 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3734 "DMA tag!\n", __FILE__, __LINE__); 3735 rc = ENOMEM; 3736 goto bce_dma_alloc_exit; 3737 } 3738 3739 for (i = 0; i < sc->rx_pages; i++) { 3740 3741 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3742 (void **)&sc->rx_bd_chain[i], 3743 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3744 &sc->rx_bd_chain_map[i])) { 3745 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3746 "chain DMA memory!\n", __FILE__, __LINE__); 3747 rc = ENOMEM; 3748 goto bce_dma_alloc_exit; 3749 } 3750 3751 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3752 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3753 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3754 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3755 3756 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3757 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3758 "chain DMA memory!\n", __FILE__, __LINE__); 3759 rc = ENOMEM; 3760 goto bce_dma_alloc_exit; 3761 } 3762 3763 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3764 "0x%jX\n", __FUNCTION__, i, 3765 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3766 } 3767 3768 /* 3769 * Create a DMA tag for RX mbufs. 3770 */ 3771 if (bce_hdr_split == TRUE) 3772 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3773 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3774 else 3775 max_size = MJUM9BYTES; 3776 3777 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3778 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3779 3780 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3781 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3782 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3783 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3784 __FILE__, __LINE__); 3785 rc = ENOMEM; 3786 goto bce_dma_alloc_exit; 3787 } 3788 3789 /* Create DMA maps for the RX mbuf clusters. */ 3790 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3791 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3792 &sc->rx_mbuf_map[i])) { 3793 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3794 "DMA map!\n", __FILE__, __LINE__); 3795 rc = ENOMEM; 3796 goto bce_dma_alloc_exit; 3797 } 3798 } 3799 3800 if (bce_hdr_split == TRUE) { 3801 /* 3802 * Create a DMA tag for the page buffer descriptor chain, 3803 * allocate and clear the memory, and fetch the physical 3804 * address of the blocks. 3805 */ 3806 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3807 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3808 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3809 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3810 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3811 "chain DMA tag!\n", __FILE__, __LINE__); 3812 rc = ENOMEM; 3813 goto bce_dma_alloc_exit; 3814 } 3815 3816 for (i = 0; i < sc->pg_pages; i++) { 3817 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3818 (void **)&sc->pg_bd_chain[i], 3819 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3820 &sc->pg_bd_chain_map[i])) { 3821 BCE_PRINTF("%s(%d): Could not allocate page " 3822 "descriptor chain DMA memory!\n", 3823 __FILE__, __LINE__); 3824 rc = ENOMEM; 3825 goto bce_dma_alloc_exit; 3826 } 3827 3828 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3829 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3830 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3831 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3832 3833 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3834 BCE_PRINTF("%s(%d): Could not map page descriptor " 3835 "chain DMA memory!\n", __FILE__, __LINE__); 3836 rc = ENOMEM; 3837 goto bce_dma_alloc_exit; 3838 } 3839 3840 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3841 "0x%jX\n", __FUNCTION__, i, 3842 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3843 } 3844 3845 /* 3846 * Create a DMA tag for page mbufs. 3847 */ 3848 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3849 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3850 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3851 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3852 "DMA tag!\n", __FILE__, __LINE__); 3853 rc = ENOMEM; 3854 goto bce_dma_alloc_exit; 3855 } 3856 3857 /* Create DMA maps for the page mbuf clusters. */ 3858 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3859 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3860 &sc->pg_mbuf_map[i])) { 3861 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3862 "DMA map!\n", __FILE__, __LINE__); 3863 rc = ENOMEM; 3864 goto bce_dma_alloc_exit; 3865 } 3866 } 3867 } 3868 3869 bce_dma_alloc_exit: 3870 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3871 return(rc); 3872 } 3873 3874 3875 /****************************************************************************/ 3876 /* Release all resources used by the driver. */ 3877 /* */ 3878 /* Releases all resources acquired by the driver including interrupts, */ 3879 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3880 /* */ 3881 /* Returns: */ 3882 /* Nothing. */ 3883 /****************************************************************************/ 3884 static void 3885 bce_release_resources(struct bce_softc *sc) 3886 { 3887 device_t dev; 3888 3889 DBENTER(BCE_VERBOSE_RESET); 3890 3891 dev = sc->bce_dev; 3892 3893 bce_dma_free(sc); 3894 3895 if (sc->bce_intrhand != NULL) { 3896 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3897 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3898 } 3899 3900 if (sc->bce_res_irq != NULL) { 3901 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3902 bus_release_resource(dev, SYS_RES_IRQ, 3903 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3904 } 3905 3906 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3907 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3908 pci_release_msi(dev); 3909 } 3910 3911 if (sc->bce_res_mem != NULL) { 3912 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3913 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3914 sc->bce_res_mem); 3915 } 3916 3917 if (sc->bce_ifp != NULL) { 3918 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3919 if_free(sc->bce_ifp); 3920 } 3921 3922 if (mtx_initialized(&sc->bce_mtx)) 3923 BCE_LOCK_DESTROY(sc); 3924 3925 DBEXIT(BCE_VERBOSE_RESET); 3926 } 3927 3928 3929 /****************************************************************************/ 3930 /* Firmware synchronization. */ 3931 /* */ 3932 /* Before performing certain events such as a chip reset, synchronize with */ 3933 /* the firmware first. */ 3934 /* */ 3935 /* Returns: */ 3936 /* 0 for success, positive value for failure. */ 3937 /****************************************************************************/ 3938 static int 3939 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3940 { 3941 int i, rc = 0; 3942 u32 val; 3943 3944 DBENTER(BCE_VERBOSE_RESET); 3945 3946 /* Don't waste any time if we've timed out before. */ 3947 if (sc->bce_fw_timed_out == TRUE) { 3948 rc = EBUSY; 3949 goto bce_fw_sync_exit; 3950 } 3951 3952 /* Increment the message sequence number. */ 3953 sc->bce_fw_wr_seq++; 3954 msg_data |= sc->bce_fw_wr_seq; 3955 3956 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3957 "0x%08X\n", msg_data); 3958 3959 /* Send the message to the bootcode driver mailbox. */ 3960 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3961 3962 /* Wait for the bootcode to acknowledge the message. */ 3963 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3964 /* Check for a response in the bootcode firmware mailbox. */ 3965 val = bce_shmem_rd(sc, BCE_FW_MB); 3966 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3967 break; 3968 DELAY(1000); 3969 } 3970 3971 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3972 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3973 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3974 3975 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3976 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3977 3978 msg_data &= ~BCE_DRV_MSG_CODE; 3979 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3980 3981 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3982 3983 sc->bce_fw_timed_out = TRUE; 3984 rc = EBUSY; 3985 } 3986 3987 bce_fw_sync_exit: 3988 DBEXIT(BCE_VERBOSE_RESET); 3989 return (rc); 3990 } 3991 3992 3993 /****************************************************************************/ 3994 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3995 /* */ 3996 /* Returns: */ 3997 /* Nothing. */ 3998 /****************************************************************************/ 3999 static void 4000 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 4001 u32 rv2p_code_len, u32 rv2p_proc) 4002 { 4003 int i; 4004 u32 val; 4005 4006 DBENTER(BCE_VERBOSE_RESET); 4007 4008 /* Set the page size used by RV2P. */ 4009 if (rv2p_proc == RV2P_PROC2) { 4010 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 4011 } 4012 4013 for (i = 0; i < rv2p_code_len; i += 8) { 4014 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 4015 rv2p_code++; 4016 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 4017 rv2p_code++; 4018 4019 if (rv2p_proc == RV2P_PROC1) { 4020 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4021 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4022 } 4023 else { 4024 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4025 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4026 } 4027 } 4028 4029 /* Reset the processor, un-stall is done later. */ 4030 if (rv2p_proc == RV2P_PROC1) { 4031 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4032 } 4033 else { 4034 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4035 } 4036 4037 DBEXIT(BCE_VERBOSE_RESET); 4038 } 4039 4040 4041 /****************************************************************************/ 4042 /* Load RISC processor firmware. */ 4043 /* */ 4044 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4045 /* associated with a particular processor. */ 4046 /* */ 4047 /* Returns: */ 4048 /* Nothing. */ 4049 /****************************************************************************/ 4050 static void 4051 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4052 struct fw_info *fw) 4053 { 4054 u32 offset; 4055 4056 DBENTER(BCE_VERBOSE_RESET); 4057 4058 bce_halt_cpu(sc, cpu_reg); 4059 4060 /* Load the Text area. */ 4061 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4062 if (fw->text) { 4063 int j; 4064 4065 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4066 REG_WR_IND(sc, offset, fw->text[j]); 4067 } 4068 } 4069 4070 /* Load the Data area. */ 4071 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4072 if (fw->data) { 4073 int j; 4074 4075 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4076 REG_WR_IND(sc, offset, fw->data[j]); 4077 } 4078 } 4079 4080 /* Load the SBSS area. */ 4081 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4082 if (fw->sbss) { 4083 int j; 4084 4085 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4086 REG_WR_IND(sc, offset, fw->sbss[j]); 4087 } 4088 } 4089 4090 /* Load the BSS area. */ 4091 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4092 if (fw->bss) { 4093 int j; 4094 4095 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4096 REG_WR_IND(sc, offset, fw->bss[j]); 4097 } 4098 } 4099 4100 /* Load the Read-Only area. */ 4101 offset = cpu_reg->spad_base + 4102 (fw->rodata_addr - cpu_reg->mips_view_base); 4103 if (fw->rodata) { 4104 int j; 4105 4106 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4107 REG_WR_IND(sc, offset, fw->rodata[j]); 4108 } 4109 } 4110 4111 /* Clear the pre-fetch instruction and set the FW start address. */ 4112 REG_WR_IND(sc, cpu_reg->inst, 0); 4113 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4114 4115 DBEXIT(BCE_VERBOSE_RESET); 4116 } 4117 4118 4119 /****************************************************************************/ 4120 /* Starts the RISC processor. */ 4121 /* */ 4122 /* Assumes the CPU starting address has already been set. */ 4123 /* */ 4124 /* Returns: */ 4125 /* Nothing. */ 4126 /****************************************************************************/ 4127 static void 4128 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4129 { 4130 u32 val; 4131 4132 DBENTER(BCE_VERBOSE_RESET); 4133 4134 /* Start the CPU. */ 4135 val = REG_RD_IND(sc, cpu_reg->mode); 4136 val &= ~cpu_reg->mode_value_halt; 4137 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4138 REG_WR_IND(sc, cpu_reg->mode, val); 4139 4140 DBEXIT(BCE_VERBOSE_RESET); 4141 } 4142 4143 4144 /****************************************************************************/ 4145 /* Halts the RISC processor. */ 4146 /* */ 4147 /* Returns: */ 4148 /* Nothing. */ 4149 /****************************************************************************/ 4150 static void 4151 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4152 { 4153 u32 val; 4154 4155 DBENTER(BCE_VERBOSE_RESET); 4156 4157 /* Halt the CPU. */ 4158 val = REG_RD_IND(sc, cpu_reg->mode); 4159 val |= cpu_reg->mode_value_halt; 4160 REG_WR_IND(sc, cpu_reg->mode, val); 4161 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4162 4163 DBEXIT(BCE_VERBOSE_RESET); 4164 } 4165 4166 4167 /****************************************************************************/ 4168 /* Initialize the RX CPU. */ 4169 /* */ 4170 /* Returns: */ 4171 /* Nothing. */ 4172 /****************************************************************************/ 4173 static void 4174 bce_start_rxp_cpu(struct bce_softc *sc) 4175 { 4176 struct cpu_reg cpu_reg; 4177 4178 DBENTER(BCE_VERBOSE_RESET); 4179 4180 cpu_reg.mode = BCE_RXP_CPU_MODE; 4181 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4182 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4183 cpu_reg.state = BCE_RXP_CPU_STATE; 4184 cpu_reg.state_value_clear = 0xffffff; 4185 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4186 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4187 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4188 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4189 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4190 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4191 cpu_reg.mips_view_base = 0x8000000; 4192 4193 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4194 bce_start_cpu(sc, &cpu_reg); 4195 4196 DBEXIT(BCE_VERBOSE_RESET); 4197 } 4198 4199 4200 /****************************************************************************/ 4201 /* Initialize the RX CPU. */ 4202 /* */ 4203 /* Returns: */ 4204 /* Nothing. */ 4205 /****************************************************************************/ 4206 static void 4207 bce_init_rxp_cpu(struct bce_softc *sc) 4208 { 4209 struct cpu_reg cpu_reg; 4210 struct fw_info fw; 4211 4212 DBENTER(BCE_VERBOSE_RESET); 4213 4214 cpu_reg.mode = BCE_RXP_CPU_MODE; 4215 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4216 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4217 cpu_reg.state = BCE_RXP_CPU_STATE; 4218 cpu_reg.state_value_clear = 0xffffff; 4219 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4220 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4221 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4222 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4223 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4224 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4225 cpu_reg.mips_view_base = 0x8000000; 4226 4227 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4228 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4229 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4230 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4231 fw.start_addr = bce_RXP_b09FwStartAddr; 4232 4233 fw.text_addr = bce_RXP_b09FwTextAddr; 4234 fw.text_len = bce_RXP_b09FwTextLen; 4235 fw.text_index = 0; 4236 fw.text = bce_RXP_b09FwText; 4237 4238 fw.data_addr = bce_RXP_b09FwDataAddr; 4239 fw.data_len = bce_RXP_b09FwDataLen; 4240 fw.data_index = 0; 4241 fw.data = bce_RXP_b09FwData; 4242 4243 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4244 fw.sbss_len = bce_RXP_b09FwSbssLen; 4245 fw.sbss_index = 0; 4246 fw.sbss = bce_RXP_b09FwSbss; 4247 4248 fw.bss_addr = bce_RXP_b09FwBssAddr; 4249 fw.bss_len = bce_RXP_b09FwBssLen; 4250 fw.bss_index = 0; 4251 fw.bss = bce_RXP_b09FwBss; 4252 4253 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4254 fw.rodata_len = bce_RXP_b09FwRodataLen; 4255 fw.rodata_index = 0; 4256 fw.rodata = bce_RXP_b09FwRodata; 4257 } else { 4258 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4259 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4260 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4261 fw.start_addr = bce_RXP_b06FwStartAddr; 4262 4263 fw.text_addr = bce_RXP_b06FwTextAddr; 4264 fw.text_len = bce_RXP_b06FwTextLen; 4265 fw.text_index = 0; 4266 fw.text = bce_RXP_b06FwText; 4267 4268 fw.data_addr = bce_RXP_b06FwDataAddr; 4269 fw.data_len = bce_RXP_b06FwDataLen; 4270 fw.data_index = 0; 4271 fw.data = bce_RXP_b06FwData; 4272 4273 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4274 fw.sbss_len = bce_RXP_b06FwSbssLen; 4275 fw.sbss_index = 0; 4276 fw.sbss = bce_RXP_b06FwSbss; 4277 4278 fw.bss_addr = bce_RXP_b06FwBssAddr; 4279 fw.bss_len = bce_RXP_b06FwBssLen; 4280 fw.bss_index = 0; 4281 fw.bss = bce_RXP_b06FwBss; 4282 4283 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4284 fw.rodata_len = bce_RXP_b06FwRodataLen; 4285 fw.rodata_index = 0; 4286 fw.rodata = bce_RXP_b06FwRodata; 4287 } 4288 4289 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4290 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4291 4292 /* Delay RXP start until initialization is complete. */ 4293 4294 DBEXIT(BCE_VERBOSE_RESET); 4295 } 4296 4297 4298 /****************************************************************************/ 4299 /* Initialize the TX CPU. */ 4300 /* */ 4301 /* Returns: */ 4302 /* Nothing. */ 4303 /****************************************************************************/ 4304 static void 4305 bce_init_txp_cpu(struct bce_softc *sc) 4306 { 4307 struct cpu_reg cpu_reg; 4308 struct fw_info fw; 4309 4310 DBENTER(BCE_VERBOSE_RESET); 4311 4312 cpu_reg.mode = BCE_TXP_CPU_MODE; 4313 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4314 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4315 cpu_reg.state = BCE_TXP_CPU_STATE; 4316 cpu_reg.state_value_clear = 0xffffff; 4317 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4318 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4319 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4320 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4321 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4322 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4323 cpu_reg.mips_view_base = 0x8000000; 4324 4325 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4326 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4327 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4328 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4329 fw.start_addr = bce_TXP_b09FwStartAddr; 4330 4331 fw.text_addr = bce_TXP_b09FwTextAddr; 4332 fw.text_len = bce_TXP_b09FwTextLen; 4333 fw.text_index = 0; 4334 fw.text = bce_TXP_b09FwText; 4335 4336 fw.data_addr = bce_TXP_b09FwDataAddr; 4337 fw.data_len = bce_TXP_b09FwDataLen; 4338 fw.data_index = 0; 4339 fw.data = bce_TXP_b09FwData; 4340 4341 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4342 fw.sbss_len = bce_TXP_b09FwSbssLen; 4343 fw.sbss_index = 0; 4344 fw.sbss = bce_TXP_b09FwSbss; 4345 4346 fw.bss_addr = bce_TXP_b09FwBssAddr; 4347 fw.bss_len = bce_TXP_b09FwBssLen; 4348 fw.bss_index = 0; 4349 fw.bss = bce_TXP_b09FwBss; 4350 4351 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4352 fw.rodata_len = bce_TXP_b09FwRodataLen; 4353 fw.rodata_index = 0; 4354 fw.rodata = bce_TXP_b09FwRodata; 4355 } else { 4356 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4357 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4358 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4359 fw.start_addr = bce_TXP_b06FwStartAddr; 4360 4361 fw.text_addr = bce_TXP_b06FwTextAddr; 4362 fw.text_len = bce_TXP_b06FwTextLen; 4363 fw.text_index = 0; 4364 fw.text = bce_TXP_b06FwText; 4365 4366 fw.data_addr = bce_TXP_b06FwDataAddr; 4367 fw.data_len = bce_TXP_b06FwDataLen; 4368 fw.data_index = 0; 4369 fw.data = bce_TXP_b06FwData; 4370 4371 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4372 fw.sbss_len = bce_TXP_b06FwSbssLen; 4373 fw.sbss_index = 0; 4374 fw.sbss = bce_TXP_b06FwSbss; 4375 4376 fw.bss_addr = bce_TXP_b06FwBssAddr; 4377 fw.bss_len = bce_TXP_b06FwBssLen; 4378 fw.bss_index = 0; 4379 fw.bss = bce_TXP_b06FwBss; 4380 4381 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4382 fw.rodata_len = bce_TXP_b06FwRodataLen; 4383 fw.rodata_index = 0; 4384 fw.rodata = bce_TXP_b06FwRodata; 4385 } 4386 4387 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4388 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4389 bce_start_cpu(sc, &cpu_reg); 4390 4391 DBEXIT(BCE_VERBOSE_RESET); 4392 } 4393 4394 4395 /****************************************************************************/ 4396 /* Initialize the TPAT CPU. */ 4397 /* */ 4398 /* Returns: */ 4399 /* Nothing. */ 4400 /****************************************************************************/ 4401 static void 4402 bce_init_tpat_cpu(struct bce_softc *sc) 4403 { 4404 struct cpu_reg cpu_reg; 4405 struct fw_info fw; 4406 4407 DBENTER(BCE_VERBOSE_RESET); 4408 4409 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4410 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4411 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4412 cpu_reg.state = BCE_TPAT_CPU_STATE; 4413 cpu_reg.state_value_clear = 0xffffff; 4414 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4415 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4416 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4417 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4418 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4419 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4420 cpu_reg.mips_view_base = 0x8000000; 4421 4422 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4423 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4424 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4425 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4426 fw.start_addr = bce_TPAT_b09FwStartAddr; 4427 4428 fw.text_addr = bce_TPAT_b09FwTextAddr; 4429 fw.text_len = bce_TPAT_b09FwTextLen; 4430 fw.text_index = 0; 4431 fw.text = bce_TPAT_b09FwText; 4432 4433 fw.data_addr = bce_TPAT_b09FwDataAddr; 4434 fw.data_len = bce_TPAT_b09FwDataLen; 4435 fw.data_index = 0; 4436 fw.data = bce_TPAT_b09FwData; 4437 4438 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4439 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4440 fw.sbss_index = 0; 4441 fw.sbss = bce_TPAT_b09FwSbss; 4442 4443 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4444 fw.bss_len = bce_TPAT_b09FwBssLen; 4445 fw.bss_index = 0; 4446 fw.bss = bce_TPAT_b09FwBss; 4447 4448 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4449 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4450 fw.rodata_index = 0; 4451 fw.rodata = bce_TPAT_b09FwRodata; 4452 } else { 4453 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4454 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4455 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4456 fw.start_addr = bce_TPAT_b06FwStartAddr; 4457 4458 fw.text_addr = bce_TPAT_b06FwTextAddr; 4459 fw.text_len = bce_TPAT_b06FwTextLen; 4460 fw.text_index = 0; 4461 fw.text = bce_TPAT_b06FwText; 4462 4463 fw.data_addr = bce_TPAT_b06FwDataAddr; 4464 fw.data_len = bce_TPAT_b06FwDataLen; 4465 fw.data_index = 0; 4466 fw.data = bce_TPAT_b06FwData; 4467 4468 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4469 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4470 fw.sbss_index = 0; 4471 fw.sbss = bce_TPAT_b06FwSbss; 4472 4473 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4474 fw.bss_len = bce_TPAT_b06FwBssLen; 4475 fw.bss_index = 0; 4476 fw.bss = bce_TPAT_b06FwBss; 4477 4478 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4479 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4480 fw.rodata_index = 0; 4481 fw.rodata = bce_TPAT_b06FwRodata; 4482 } 4483 4484 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4485 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4486 bce_start_cpu(sc, &cpu_reg); 4487 4488 DBEXIT(BCE_VERBOSE_RESET); 4489 } 4490 4491 4492 /****************************************************************************/ 4493 /* Initialize the CP CPU. */ 4494 /* */ 4495 /* Returns: */ 4496 /* Nothing. */ 4497 /****************************************************************************/ 4498 static void 4499 bce_init_cp_cpu(struct bce_softc *sc) 4500 { 4501 struct cpu_reg cpu_reg; 4502 struct fw_info fw; 4503 4504 DBENTER(BCE_VERBOSE_RESET); 4505 4506 cpu_reg.mode = BCE_CP_CPU_MODE; 4507 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4508 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4509 cpu_reg.state = BCE_CP_CPU_STATE; 4510 cpu_reg.state_value_clear = 0xffffff; 4511 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4512 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4513 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4514 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4515 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4516 cpu_reg.spad_base = BCE_CP_SCRATCH; 4517 cpu_reg.mips_view_base = 0x8000000; 4518 4519 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4520 fw.ver_major = bce_CP_b09FwReleaseMajor; 4521 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4522 fw.ver_fix = bce_CP_b09FwReleaseFix; 4523 fw.start_addr = bce_CP_b09FwStartAddr; 4524 4525 fw.text_addr = bce_CP_b09FwTextAddr; 4526 fw.text_len = bce_CP_b09FwTextLen; 4527 fw.text_index = 0; 4528 fw.text = bce_CP_b09FwText; 4529 4530 fw.data_addr = bce_CP_b09FwDataAddr; 4531 fw.data_len = bce_CP_b09FwDataLen; 4532 fw.data_index = 0; 4533 fw.data = bce_CP_b09FwData; 4534 4535 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4536 fw.sbss_len = bce_CP_b09FwSbssLen; 4537 fw.sbss_index = 0; 4538 fw.sbss = bce_CP_b09FwSbss; 4539 4540 fw.bss_addr = bce_CP_b09FwBssAddr; 4541 fw.bss_len = bce_CP_b09FwBssLen; 4542 fw.bss_index = 0; 4543 fw.bss = bce_CP_b09FwBss; 4544 4545 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4546 fw.rodata_len = bce_CP_b09FwRodataLen; 4547 fw.rodata_index = 0; 4548 fw.rodata = bce_CP_b09FwRodata; 4549 } else { 4550 fw.ver_major = bce_CP_b06FwReleaseMajor; 4551 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4552 fw.ver_fix = bce_CP_b06FwReleaseFix; 4553 fw.start_addr = bce_CP_b06FwStartAddr; 4554 4555 fw.text_addr = bce_CP_b06FwTextAddr; 4556 fw.text_len = bce_CP_b06FwTextLen; 4557 fw.text_index = 0; 4558 fw.text = bce_CP_b06FwText; 4559 4560 fw.data_addr = bce_CP_b06FwDataAddr; 4561 fw.data_len = bce_CP_b06FwDataLen; 4562 fw.data_index = 0; 4563 fw.data = bce_CP_b06FwData; 4564 4565 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4566 fw.sbss_len = bce_CP_b06FwSbssLen; 4567 fw.sbss_index = 0; 4568 fw.sbss = bce_CP_b06FwSbss; 4569 4570 fw.bss_addr = bce_CP_b06FwBssAddr; 4571 fw.bss_len = bce_CP_b06FwBssLen; 4572 fw.bss_index = 0; 4573 fw.bss = bce_CP_b06FwBss; 4574 4575 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4576 fw.rodata_len = bce_CP_b06FwRodataLen; 4577 fw.rodata_index = 0; 4578 fw.rodata = bce_CP_b06FwRodata; 4579 } 4580 4581 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4582 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4583 bce_start_cpu(sc, &cpu_reg); 4584 4585 DBEXIT(BCE_VERBOSE_RESET); 4586 } 4587 4588 4589 /****************************************************************************/ 4590 /* Initialize the COM CPU. */ 4591 /* */ 4592 /* Returns: */ 4593 /* Nothing. */ 4594 /****************************************************************************/ 4595 static void 4596 bce_init_com_cpu(struct bce_softc *sc) 4597 { 4598 struct cpu_reg cpu_reg; 4599 struct fw_info fw; 4600 4601 DBENTER(BCE_VERBOSE_RESET); 4602 4603 cpu_reg.mode = BCE_COM_CPU_MODE; 4604 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4605 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4606 cpu_reg.state = BCE_COM_CPU_STATE; 4607 cpu_reg.state_value_clear = 0xffffff; 4608 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4609 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4610 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4611 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4612 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4613 cpu_reg.spad_base = BCE_COM_SCRATCH; 4614 cpu_reg.mips_view_base = 0x8000000; 4615 4616 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4617 fw.ver_major = bce_COM_b09FwReleaseMajor; 4618 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4619 fw.ver_fix = bce_COM_b09FwReleaseFix; 4620 fw.start_addr = bce_COM_b09FwStartAddr; 4621 4622 fw.text_addr = bce_COM_b09FwTextAddr; 4623 fw.text_len = bce_COM_b09FwTextLen; 4624 fw.text_index = 0; 4625 fw.text = bce_COM_b09FwText; 4626 4627 fw.data_addr = bce_COM_b09FwDataAddr; 4628 fw.data_len = bce_COM_b09FwDataLen; 4629 fw.data_index = 0; 4630 fw.data = bce_COM_b09FwData; 4631 4632 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4633 fw.sbss_len = bce_COM_b09FwSbssLen; 4634 fw.sbss_index = 0; 4635 fw.sbss = bce_COM_b09FwSbss; 4636 4637 fw.bss_addr = bce_COM_b09FwBssAddr; 4638 fw.bss_len = bce_COM_b09FwBssLen; 4639 fw.bss_index = 0; 4640 fw.bss = bce_COM_b09FwBss; 4641 4642 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4643 fw.rodata_len = bce_COM_b09FwRodataLen; 4644 fw.rodata_index = 0; 4645 fw.rodata = bce_COM_b09FwRodata; 4646 } else { 4647 fw.ver_major = bce_COM_b06FwReleaseMajor; 4648 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4649 fw.ver_fix = bce_COM_b06FwReleaseFix; 4650 fw.start_addr = bce_COM_b06FwStartAddr; 4651 4652 fw.text_addr = bce_COM_b06FwTextAddr; 4653 fw.text_len = bce_COM_b06FwTextLen; 4654 fw.text_index = 0; 4655 fw.text = bce_COM_b06FwText; 4656 4657 fw.data_addr = bce_COM_b06FwDataAddr; 4658 fw.data_len = bce_COM_b06FwDataLen; 4659 fw.data_index = 0; 4660 fw.data = bce_COM_b06FwData; 4661 4662 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4663 fw.sbss_len = bce_COM_b06FwSbssLen; 4664 fw.sbss_index = 0; 4665 fw.sbss = bce_COM_b06FwSbss; 4666 4667 fw.bss_addr = bce_COM_b06FwBssAddr; 4668 fw.bss_len = bce_COM_b06FwBssLen; 4669 fw.bss_index = 0; 4670 fw.bss = bce_COM_b06FwBss; 4671 4672 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4673 fw.rodata_len = bce_COM_b06FwRodataLen; 4674 fw.rodata_index = 0; 4675 fw.rodata = bce_COM_b06FwRodata; 4676 } 4677 4678 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4679 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4680 bce_start_cpu(sc, &cpu_reg); 4681 4682 DBEXIT(BCE_VERBOSE_RESET); 4683 } 4684 4685 4686 /****************************************************************************/ 4687 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4688 /* */ 4689 /* Loads the firmware for each CPU and starts the CPU. */ 4690 /* */ 4691 /* Returns: */ 4692 /* Nothing. */ 4693 /****************************************************************************/ 4694 static void 4695 bce_init_cpus(struct bce_softc *sc) 4696 { 4697 DBENTER(BCE_VERBOSE_RESET); 4698 4699 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4700 4701 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4702 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4703 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4704 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4705 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4706 } else { 4707 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4708 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4709 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4710 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4711 } 4712 4713 } else { 4714 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4715 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4716 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4717 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4718 } 4719 4720 bce_init_rxp_cpu(sc); 4721 bce_init_txp_cpu(sc); 4722 bce_init_tpat_cpu(sc); 4723 bce_init_com_cpu(sc); 4724 bce_init_cp_cpu(sc); 4725 4726 DBEXIT(BCE_VERBOSE_RESET); 4727 } 4728 4729 4730 /****************************************************************************/ 4731 /* Initialize context memory. */ 4732 /* */ 4733 /* Clears the memory associated with each Context ID (CID). */ 4734 /* */ 4735 /* Returns: */ 4736 /* Nothing. */ 4737 /****************************************************************************/ 4738 static int 4739 bce_init_ctx(struct bce_softc *sc) 4740 { 4741 u32 offset, val, vcid_addr; 4742 int i, j, rc, retry_cnt; 4743 4744 rc = 0; 4745 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4746 4747 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4748 retry_cnt = CTX_INIT_RETRY_COUNT; 4749 4750 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4751 4752 /* 4753 * BCM5709 context memory may be cached 4754 * in host memory so prepare the host memory 4755 * for access. 4756 */ 4757 val = BCE_CTX_COMMAND_ENABLED | 4758 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4759 val |= (BCM_PAGE_BITS - 8) << 16; 4760 REG_WR(sc, BCE_CTX_COMMAND, val); 4761 4762 /* Wait for mem init command to complete. */ 4763 for (i = 0; i < retry_cnt; i++) { 4764 val = REG_RD(sc, BCE_CTX_COMMAND); 4765 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4766 break; 4767 DELAY(2); 4768 } 4769 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4770 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4771 __FUNCTION__); 4772 rc = EBUSY; 4773 goto init_ctx_fail; 4774 } 4775 4776 for (i = 0; i < sc->ctx_pages; i++) { 4777 /* Set the physical address of the context memory. */ 4778 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4779 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4780 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4781 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4782 BCE_ADDR_HI(sc->ctx_paddr[i])); 4783 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4784 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4785 4786 /* Verify the context memory write was successful. */ 4787 for (j = 0; j < retry_cnt; j++) { 4788 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4789 if ((val & 4790 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4791 break; 4792 DELAY(5); 4793 } 4794 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4795 BCE_PRINTF("%s(): Failed to initialize " 4796 "context page %d!\n", __FUNCTION__, i); 4797 rc = EBUSY; 4798 goto init_ctx_fail; 4799 } 4800 } 4801 } else { 4802 4803 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4804 4805 /* 4806 * For the 5706/5708, context memory is local to 4807 * the controller, so initialize the controller 4808 * context memory. 4809 */ 4810 4811 vcid_addr = GET_CID_ADDR(96); 4812 while (vcid_addr) { 4813 4814 vcid_addr -= PHY_CTX_SIZE; 4815 4816 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4817 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4818 4819 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4820 CTX_WR(sc, 0x00, offset, 0); 4821 } 4822 4823 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4824 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4825 } 4826 4827 } 4828 init_ctx_fail: 4829 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4830 return (rc); 4831 } 4832 4833 4834 /****************************************************************************/ 4835 /* Fetch the permanent MAC address of the controller. */ 4836 /* */ 4837 /* Returns: */ 4838 /* Nothing. */ 4839 /****************************************************************************/ 4840 static void 4841 bce_get_mac_addr(struct bce_softc *sc) 4842 { 4843 u32 mac_lo = 0, mac_hi = 0; 4844 4845 DBENTER(BCE_VERBOSE_RESET); 4846 4847 /* 4848 * The NetXtreme II bootcode populates various NIC 4849 * power-on and runtime configuration items in a 4850 * shared memory area. The factory configured MAC 4851 * address is available from both NVRAM and the 4852 * shared memory area so we'll read the value from 4853 * shared memory for speed. 4854 */ 4855 4856 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4857 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4858 4859 if ((mac_lo == 0) && (mac_hi == 0)) { 4860 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4861 __FILE__, __LINE__); 4862 } else { 4863 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4864 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4865 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4866 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4867 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4868 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4869 } 4870 4871 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4872 "address = %6D\n", sc->eaddr, ":"); 4873 DBEXIT(BCE_VERBOSE_RESET); 4874 } 4875 4876 4877 /****************************************************************************/ 4878 /* Program the MAC address. */ 4879 /* */ 4880 /* Returns: */ 4881 /* Nothing. */ 4882 /****************************************************************************/ 4883 static void 4884 bce_set_mac_addr(struct bce_softc *sc) 4885 { 4886 u32 val; 4887 u8 *mac_addr = sc->eaddr; 4888 4889 /* ToDo: Add support for setting multiple MAC addresses. */ 4890 4891 DBENTER(BCE_VERBOSE_RESET); 4892 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4893 "%6D\n", sc->eaddr, ":"); 4894 4895 val = (mac_addr[0] << 8) | mac_addr[1]; 4896 4897 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4898 4899 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4900 (mac_addr[4] << 8) | mac_addr[5]; 4901 4902 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4903 4904 DBEXIT(BCE_VERBOSE_RESET); 4905 } 4906 4907 4908 /****************************************************************************/ 4909 /* Stop the controller. */ 4910 /* */ 4911 /* Returns: */ 4912 /* Nothing. */ 4913 /****************************************************************************/ 4914 static void 4915 bce_stop(struct bce_softc *sc) 4916 { 4917 struct ifnet *ifp; 4918 4919 DBENTER(BCE_VERBOSE_RESET); 4920 4921 BCE_LOCK_ASSERT(sc); 4922 4923 ifp = sc->bce_ifp; 4924 4925 callout_stop(&sc->bce_tick_callout); 4926 4927 /* Disable the transmit/receive blocks. */ 4928 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4929 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4930 DELAY(20); 4931 4932 bce_disable_intr(sc); 4933 4934 /* Free RX buffers. */ 4935 if (bce_hdr_split == TRUE) { 4936 bce_free_pg_chain(sc); 4937 } 4938 bce_free_rx_chain(sc); 4939 4940 /* Free TX buffers. */ 4941 bce_free_tx_chain(sc); 4942 4943 sc->watchdog_timer = 0; 4944 4945 sc->bce_link_up = FALSE; 4946 4947 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4948 4949 DBEXIT(BCE_VERBOSE_RESET); 4950 } 4951 4952 4953 static int 4954 bce_reset(struct bce_softc *sc, u32 reset_code) 4955 { 4956 u32 emac_mode_save, val; 4957 int i, rc = 0; 4958 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 4959 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 4960 4961 DBENTER(BCE_VERBOSE_RESET); 4962 4963 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4964 __FUNCTION__, reset_code); 4965 4966 /* 4967 * If ASF/IPMI is operational, then the EMAC Mode register already 4968 * contains appropriate values for the link settings that have 4969 * been auto-negotiated. Resetting the chip will clobber those 4970 * values. Save the important bits so we can restore them after 4971 * the reset. 4972 */ 4973 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 4974 4975 /* Wait for pending PCI transactions to complete. */ 4976 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4977 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4978 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4979 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4980 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4981 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4982 DELAY(5); 4983 4984 /* Disable DMA */ 4985 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4986 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4987 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4988 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4989 } 4990 4991 /* Assume bootcode is running. */ 4992 sc->bce_fw_timed_out = FALSE; 4993 sc->bce_drv_cardiac_arrest = FALSE; 4994 4995 /* Give the firmware a chance to prepare for the reset. */ 4996 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4997 if (rc) 4998 goto bce_reset_exit; 4999 5000 /* Set a firmware reminder that this is a soft reset. */ 5001 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 5002 5003 /* Dummy read to force the chip to complete all current transactions. */ 5004 val = REG_RD(sc, BCE_MISC_ID); 5005 5006 /* Chip reset. */ 5007 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5008 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 5009 REG_RD(sc, BCE_MISC_COMMAND); 5010 DELAY(5); 5011 5012 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5013 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5014 5015 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 5016 } else { 5017 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5018 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5019 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5020 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 5021 5022 /* Allow up to 30us for reset to complete. */ 5023 for (i = 0; i < 10; i++) { 5024 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5025 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5026 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5027 break; 5028 } 5029 DELAY(10); 5030 } 5031 5032 /* Check that reset completed successfully. */ 5033 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5034 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5035 BCE_PRINTF("%s(%d): Reset failed!\n", 5036 __FILE__, __LINE__); 5037 rc = EBUSY; 5038 goto bce_reset_exit; 5039 } 5040 } 5041 5042 /* Make sure byte swapping is properly configured. */ 5043 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5044 if (val != 0x01020304) { 5045 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5046 __FILE__, __LINE__); 5047 rc = ENODEV; 5048 goto bce_reset_exit; 5049 } 5050 5051 /* Just completed a reset, assume that firmware is running again. */ 5052 sc->bce_fw_timed_out = FALSE; 5053 sc->bce_drv_cardiac_arrest = FALSE; 5054 5055 /* Wait for the firmware to finish its initialization. */ 5056 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5057 if (rc) 5058 BCE_PRINTF("%s(%d): Firmware did not complete " 5059 "initialization!\n", __FILE__, __LINE__); 5060 /* Get firmware capabilities. */ 5061 bce_fw_cap_init(sc); 5062 5063 bce_reset_exit: 5064 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 5065 val = REG_RD(sc, BCE_EMAC_MODE); 5066 val = (val & ~emac_mode_mask) | emac_mode_save; 5067 REG_WR(sc, BCE_EMAC_MODE, val); 5068 5069 DBEXIT(BCE_VERBOSE_RESET); 5070 return (rc); 5071 } 5072 5073 5074 static int 5075 bce_chipinit(struct bce_softc *sc) 5076 { 5077 u32 val; 5078 int rc = 0; 5079 5080 DBENTER(BCE_VERBOSE_RESET); 5081 5082 bce_disable_intr(sc); 5083 5084 /* 5085 * Initialize DMA byte/word swapping, configure the number of DMA 5086 * channels and PCI clock compensation delay. 5087 */ 5088 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5089 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5090 #if BYTE_ORDER == BIG_ENDIAN 5091 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5092 #endif 5093 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5094 DMA_READ_CHANS << 12 | 5095 DMA_WRITE_CHANS << 16; 5096 5097 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5098 5099 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5100 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5101 5102 /* 5103 * This setting resolves a problem observed on certain Intel PCI 5104 * chipsets that cannot handle multiple outstanding DMA operations. 5105 * See errata E9_5706A1_65. 5106 */ 5107 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5108 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5109 !(sc->bce_flags & BCE_PCIX_FLAG)) 5110 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5111 5112 REG_WR(sc, BCE_DMA_CONFIG, val); 5113 5114 /* Enable the RX_V2P and Context state machines before access. */ 5115 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5116 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5117 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5118 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5119 5120 /* Initialize context mapping and zero out the quick contexts. */ 5121 if ((rc = bce_init_ctx(sc)) != 0) 5122 goto bce_chipinit_exit; 5123 5124 /* Initialize the on-boards CPUs */ 5125 bce_init_cpus(sc); 5126 5127 /* Enable management frames (NC-SI) to flow to the MCP. */ 5128 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5129 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5130 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5131 } 5132 5133 /* Prepare NVRAM for access. */ 5134 if ((rc = bce_init_nvram(sc)) != 0) 5135 goto bce_chipinit_exit; 5136 5137 /* Set the kernel bypass block size */ 5138 val = REG_RD(sc, BCE_MQ_CONFIG); 5139 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5140 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5141 5142 /* Enable bins used on the 5709. */ 5143 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5144 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5145 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5146 val |= BCE_MQ_CONFIG_HALT_DIS; 5147 } 5148 5149 REG_WR(sc, BCE_MQ_CONFIG, val); 5150 5151 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5152 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5153 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5154 5155 /* Set the page size and clear the RV2P processor stall bits. */ 5156 val = (BCM_PAGE_BITS - 8) << 24; 5157 REG_WR(sc, BCE_RV2P_CONFIG, val); 5158 5159 /* Configure page size. */ 5160 val = REG_RD(sc, BCE_TBDR_CONFIG); 5161 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5162 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5163 REG_WR(sc, BCE_TBDR_CONFIG, val); 5164 5165 /* Set the perfect match control register to default. */ 5166 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5167 5168 bce_chipinit_exit: 5169 DBEXIT(BCE_VERBOSE_RESET); 5170 5171 return(rc); 5172 } 5173 5174 5175 /****************************************************************************/ 5176 /* Initialize the controller in preparation to send/receive traffic. */ 5177 /* */ 5178 /* Returns: */ 5179 /* 0 for success, positive value for failure. */ 5180 /****************************************************************************/ 5181 static int 5182 bce_blockinit(struct bce_softc *sc) 5183 { 5184 u32 reg, val; 5185 int rc = 0; 5186 5187 DBENTER(BCE_VERBOSE_RESET); 5188 5189 /* Load the hardware default MAC address. */ 5190 bce_set_mac_addr(sc); 5191 5192 /* Set the Ethernet backoff seed value */ 5193 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5194 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5195 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5196 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5197 5198 sc->last_status_idx = 0; 5199 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5200 5201 /* Set up link change interrupt generation. */ 5202 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5203 5204 /* Program the physical address of the status block. */ 5205 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5206 BCE_ADDR_LO(sc->status_block_paddr)); 5207 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5208 BCE_ADDR_HI(sc->status_block_paddr)); 5209 5210 /* Program the physical address of the statistics block. */ 5211 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5212 BCE_ADDR_LO(sc->stats_block_paddr)); 5213 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5214 BCE_ADDR_HI(sc->stats_block_paddr)); 5215 5216 /* 5217 * Program various host coalescing parameters. 5218 * Trip points control how many BDs should be ready before generating 5219 * an interrupt while ticks control how long a BD can sit in the chain 5220 * before generating an interrupt. 5221 */ 5222 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5223 (sc->bce_tx_quick_cons_trip_int << 16) | 5224 sc->bce_tx_quick_cons_trip); 5225 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5226 (sc->bce_rx_quick_cons_trip_int << 16) | 5227 sc->bce_rx_quick_cons_trip); 5228 REG_WR(sc, BCE_HC_TX_TICKS, 5229 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5230 REG_WR(sc, BCE_HC_RX_TICKS, 5231 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5232 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5233 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5234 /* Not used for L2. */ 5235 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5236 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5237 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5238 5239 /* Configure the Host Coalescing block. */ 5240 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5241 BCE_HC_CONFIG_COLLECT_STATS; 5242 5243 #if 0 5244 /* ToDo: Add MSI-X support. */ 5245 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5246 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5247 BCE_HC_SB_CONFIG_1; 5248 5249 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5250 5251 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5252 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5253 5254 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5255 (sc->tx_quick_cons_trip_int << 16) | 5256 sc->tx_quick_cons_trip); 5257 5258 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5259 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5260 5261 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5262 } 5263 5264 /* 5265 * Tell the HC block to automatically set the 5266 * INT_MASK bit after an MSI/MSI-X interrupt 5267 * is generated so the driver doesn't have to. 5268 */ 5269 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5270 val |= BCE_HC_CONFIG_ONE_SHOT; 5271 5272 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5273 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5274 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5275 #endif 5276 5277 REG_WR(sc, BCE_HC_CONFIG, val); 5278 5279 /* Clear the internal statistics counters. */ 5280 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5281 5282 /* Verify that bootcode is running. */ 5283 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5284 5285 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5286 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5287 __FILE__, __LINE__); 5288 reg = 0); 5289 5290 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5291 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5292 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5293 "Expected: 08%08X\n", __FILE__, __LINE__, 5294 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5295 BCE_DEV_INFO_SIGNATURE_MAGIC); 5296 rc = ENODEV; 5297 goto bce_blockinit_exit; 5298 } 5299 5300 /* Enable DMA */ 5301 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5302 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5303 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5304 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5305 } 5306 5307 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5308 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5309 BCE_DRV_MSG_CODE_RESET); 5310 5311 /* Enable link state change interrupt generation. */ 5312 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5313 5314 /* Enable the RXP. */ 5315 bce_start_rxp_cpu(sc); 5316 5317 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5318 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5319 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5320 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5321 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5322 } 5323 5324 /* Enable all remaining blocks in the MAC. */ 5325 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5326 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5327 BCE_MISC_ENABLE_DEFAULT_XI); 5328 else 5329 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5330 BCE_MISC_ENABLE_DEFAULT); 5331 5332 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5333 DELAY(20); 5334 5335 /* Save the current host coalescing block settings. */ 5336 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5337 5338 bce_blockinit_exit: 5339 DBEXIT(BCE_VERBOSE_RESET); 5340 5341 return (rc); 5342 } 5343 5344 5345 /****************************************************************************/ 5346 /* Encapsulate an mbuf into the rx_bd chain. */ 5347 /* */ 5348 /* Returns: */ 5349 /* 0 for success, positive value for failure. */ 5350 /****************************************************************************/ 5351 static int 5352 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5353 { 5354 bus_dma_segment_t segs[1]; 5355 struct mbuf *m_new = NULL; 5356 struct rx_bd *rxbd; 5357 int nsegs, error, rc = 0; 5358 #ifdef BCE_DEBUG 5359 u16 debug_chain_prod = chain_prod; 5360 #endif 5361 5362 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5363 5364 /* Make sure the inputs are valid. */ 5365 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5366 BCE_PRINTF("%s(%d): RX producer out of range: " 5367 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5368 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5369 5370 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5371 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5372 prod, chain_prod, *prod_bseq); 5373 5374 /* Update some debug statistic counters */ 5375 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5376 sc->rx_low_watermark = sc->free_rx_bd); 5377 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5378 sc->rx_empty_count++); 5379 5380 /* Simulate an mbuf allocation failure. */ 5381 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5382 sc->mbuf_alloc_failed_count++; 5383 sc->mbuf_alloc_failed_sim_count++; 5384 rc = ENOBUFS; 5385 goto bce_get_rx_buf_exit); 5386 5387 /* This is a new mbuf allocation. */ 5388 if (bce_hdr_split == TRUE) 5389 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5390 else 5391 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5392 sc->rx_bd_mbuf_alloc_size); 5393 5394 if (m_new == NULL) { 5395 sc->mbuf_alloc_failed_count++; 5396 rc = ENOBUFS; 5397 goto bce_get_rx_buf_exit; 5398 } 5399 5400 DBRUN(sc->debug_rx_mbuf_alloc++); 5401 5402 /* Make sure we have a valid packet header. */ 5403 M_ASSERTPKTHDR(m_new); 5404 5405 /* Initialize the mbuf size and pad if necessary for alignment. */ 5406 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5407 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5408 5409 /* ToDo: Consider calling m_fragment() to test error handling. */ 5410 5411 /* Map the mbuf cluster into device memory. */ 5412 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5413 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5414 5415 /* Handle any mapping errors. */ 5416 if (error) { 5417 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5418 "chain (%d)!\n", __FILE__, __LINE__, error); 5419 5420 sc->dma_map_addr_rx_failed_count++; 5421 m_freem(m_new); 5422 5423 DBRUN(sc->debug_rx_mbuf_alloc--); 5424 5425 rc = ENOBUFS; 5426 goto bce_get_rx_buf_exit; 5427 } 5428 5429 /* All mbufs must map to a single segment. */ 5430 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5431 __FUNCTION__, nsegs)); 5432 5433 /* Setup the rx_bd for the segment. */ 5434 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5435 5436 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5437 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5438 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5439 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5440 *prod_bseq += segs[0].ds_len; 5441 5442 /* Save the mbuf and update our counter. */ 5443 sc->rx_mbuf_ptr[chain_prod] = m_new; 5444 sc->free_rx_bd -= nsegs; 5445 5446 DBRUNMSG(BCE_INSANE_RECV, 5447 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5448 5449 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5450 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5451 chain_prod, *prod_bseq); 5452 5453 bce_get_rx_buf_exit: 5454 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5455 5456 return(rc); 5457 } 5458 5459 5460 /****************************************************************************/ 5461 /* Encapsulate an mbuf cluster into the page chain. */ 5462 /* */ 5463 /* Returns: */ 5464 /* 0 for success, positive value for failure. */ 5465 /****************************************************************************/ 5466 static int 5467 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5468 { 5469 bus_dma_segment_t segs[1]; 5470 struct mbuf *m_new = NULL; 5471 struct rx_bd *pgbd; 5472 int error, nsegs, rc = 0; 5473 #ifdef BCE_DEBUG 5474 u16 debug_prod_idx = prod_idx; 5475 #endif 5476 5477 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5478 5479 /* Make sure the inputs are valid. */ 5480 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5481 BCE_PRINTF("%s(%d): page producer out of range: " 5482 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5483 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5484 5485 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5486 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5487 5488 /* Update counters if we've hit a new low or run out of pages. */ 5489 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5490 sc->pg_low_watermark = sc->free_pg_bd); 5491 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5492 5493 /* Simulate an mbuf allocation failure. */ 5494 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5495 sc->mbuf_alloc_failed_count++; 5496 sc->mbuf_alloc_failed_sim_count++; 5497 rc = ENOBUFS; 5498 goto bce_get_pg_buf_exit); 5499 5500 /* This is a new mbuf allocation. */ 5501 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5502 if (m_new == NULL) { 5503 sc->mbuf_alloc_failed_count++; 5504 rc = ENOBUFS; 5505 goto bce_get_pg_buf_exit; 5506 } 5507 5508 DBRUN(sc->debug_pg_mbuf_alloc++); 5509 5510 m_new->m_len = MCLBYTES; 5511 5512 /* ToDo: Consider calling m_fragment() to test error handling. */ 5513 5514 /* Map the mbuf cluster into device memory. */ 5515 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5516 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5517 5518 /* Handle any mapping errors. */ 5519 if (error) { 5520 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5521 __FILE__, __LINE__); 5522 5523 m_freem(m_new); 5524 DBRUN(sc->debug_pg_mbuf_alloc--); 5525 5526 rc = ENOBUFS; 5527 goto bce_get_pg_buf_exit; 5528 } 5529 5530 /* All mbufs must map to a single segment. */ 5531 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5532 __FUNCTION__, nsegs)); 5533 5534 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5535 5536 /* 5537 * The page chain uses the same rx_bd data structure 5538 * as the receive chain but doesn't require a byte sequence (bseq). 5539 */ 5540 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5541 5542 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5543 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5544 pgbd->rx_bd_len = htole32(MCLBYTES); 5545 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5546 5547 /* Save the mbuf and update our counter. */ 5548 sc->pg_mbuf_ptr[prod_idx] = m_new; 5549 sc->free_pg_bd--; 5550 5551 DBRUNMSG(BCE_INSANE_RECV, 5552 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5553 5554 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5555 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5556 5557 bce_get_pg_buf_exit: 5558 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5559 5560 return(rc); 5561 } 5562 5563 5564 /****************************************************************************/ 5565 /* Initialize the TX context memory. */ 5566 /* */ 5567 /* Returns: */ 5568 /* Nothing */ 5569 /****************************************************************************/ 5570 static void 5571 bce_init_tx_context(struct bce_softc *sc) 5572 { 5573 u32 val; 5574 5575 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5576 5577 /* Initialize the context ID for an L2 TX chain. */ 5578 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5579 /* Set the CID type to support an L2 connection. */ 5580 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5581 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5582 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5583 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5584 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5585 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5586 5587 /* Point the hardware to the first page in the chain. */ 5588 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5589 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5590 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5591 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5592 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5593 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5594 } else { 5595 /* Set the CID type to support an L2 connection. */ 5596 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5597 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5598 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5599 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5600 5601 /* Point the hardware to the first page in the chain. */ 5602 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5603 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5604 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5605 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5606 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5607 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5608 } 5609 5610 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5611 } 5612 5613 5614 /****************************************************************************/ 5615 /* Allocate memory and initialize the TX data structures. */ 5616 /* */ 5617 /* Returns: */ 5618 /* 0 for success, positive value for failure. */ 5619 /****************************************************************************/ 5620 static int 5621 bce_init_tx_chain(struct bce_softc *sc) 5622 { 5623 struct tx_bd *txbd; 5624 int i, rc = 0; 5625 5626 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5627 5628 /* Set the initial TX producer/consumer indices. */ 5629 sc->tx_prod = 0; 5630 sc->tx_cons = 0; 5631 sc->tx_prod_bseq = 0; 5632 sc->used_tx_bd = 0; 5633 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5634 DBRUN(sc->tx_hi_watermark = 0); 5635 DBRUN(sc->tx_full_count = 0); 5636 5637 /* 5638 * The NetXtreme II supports a linked-list structre called 5639 * a Buffer Descriptor Chain (or BD chain). A BD chain 5640 * consists of a series of 1 or more chain pages, each of which 5641 * consists of a fixed number of BD entries. 5642 * The last BD entry on each page is a pointer to the next page 5643 * in the chain, and the last pointer in the BD chain 5644 * points back to the beginning of the chain. 5645 */ 5646 5647 /* Set the TX next pointer chain entries. */ 5648 for (i = 0; i < sc->tx_pages; i++) { 5649 int j; 5650 5651 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5652 5653 /* Check if we've reached the last page. */ 5654 if (i == (sc->tx_pages - 1)) 5655 j = 0; 5656 else 5657 j = i + 1; 5658 5659 txbd->tx_bd_haddr_hi = 5660 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5661 txbd->tx_bd_haddr_lo = 5662 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5663 } 5664 5665 bce_init_tx_context(sc); 5666 5667 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5668 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5669 5670 return(rc); 5671 } 5672 5673 5674 /****************************************************************************/ 5675 /* Free memory and clear the TX data structures. */ 5676 /* */ 5677 /* Returns: */ 5678 /* Nothing. */ 5679 /****************************************************************************/ 5680 static void 5681 bce_free_tx_chain(struct bce_softc *sc) 5682 { 5683 int i; 5684 5685 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5686 5687 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5688 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5689 if (sc->tx_mbuf_ptr[i] != NULL) { 5690 if (sc->tx_mbuf_map[i] != NULL) 5691 bus_dmamap_sync(sc->tx_mbuf_tag, 5692 sc->tx_mbuf_map[i], 5693 BUS_DMASYNC_POSTWRITE); 5694 m_freem(sc->tx_mbuf_ptr[i]); 5695 sc->tx_mbuf_ptr[i] = NULL; 5696 DBRUN(sc->debug_tx_mbuf_alloc--); 5697 } 5698 } 5699 5700 /* Clear each TX chain page. */ 5701 for (i = 0; i < sc->tx_pages; i++) 5702 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5703 5704 sc->used_tx_bd = 0; 5705 5706 /* Check if we lost any mbufs in the process. */ 5707 DBRUNIF((sc->debug_tx_mbuf_alloc), 5708 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5709 "from tx chain!\n", __FILE__, __LINE__, 5710 sc->debug_tx_mbuf_alloc)); 5711 5712 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5713 } 5714 5715 5716 /****************************************************************************/ 5717 /* Initialize the RX context memory. */ 5718 /* */ 5719 /* Returns: */ 5720 /* Nothing */ 5721 /****************************************************************************/ 5722 static void 5723 bce_init_rx_context(struct bce_softc *sc) 5724 { 5725 u32 val; 5726 5727 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5728 5729 /* Init the type, size, and BD cache levels for the RX context. */ 5730 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5731 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5732 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5733 5734 /* 5735 * Set the level for generating pause frames 5736 * when the number of available rx_bd's gets 5737 * too low (the low watermark) and the level 5738 * when pause frames can be stopped (the high 5739 * watermark). 5740 */ 5741 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5742 u32 lo_water, hi_water; 5743 5744 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5745 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5746 } else { 5747 lo_water = 0; 5748 } 5749 5750 if (lo_water >= USABLE_RX_BD_ALLOC) { 5751 lo_water = 0; 5752 } 5753 5754 hi_water = USABLE_RX_BD_ALLOC / 4; 5755 5756 if (hi_water <= lo_water) { 5757 lo_water = 0; 5758 } 5759 5760 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5761 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5762 5763 if (hi_water > 0xf) 5764 hi_water = 0xf; 5765 else if (hi_water == 0) 5766 lo_water = 0; 5767 5768 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5769 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5770 } 5771 5772 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5773 5774 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5775 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5776 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5777 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5778 } 5779 5780 /* Point the hardware to the first page in the chain. */ 5781 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5782 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5783 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5784 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5785 5786 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5787 } 5788 5789 5790 /****************************************************************************/ 5791 /* Allocate memory and initialize the RX data structures. */ 5792 /* */ 5793 /* Returns: */ 5794 /* 0 for success, positive value for failure. */ 5795 /****************************************************************************/ 5796 static int 5797 bce_init_rx_chain(struct bce_softc *sc) 5798 { 5799 struct rx_bd *rxbd; 5800 int i, rc = 0; 5801 5802 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5803 BCE_VERBOSE_CTX); 5804 5805 /* Initialize the RX producer and consumer indices. */ 5806 sc->rx_prod = 0; 5807 sc->rx_cons = 0; 5808 sc->rx_prod_bseq = 0; 5809 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5810 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5811 5812 /* Initialize the RX next pointer chain entries. */ 5813 for (i = 0; i < sc->rx_pages; i++) { 5814 int j; 5815 5816 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5817 5818 /* Check if we've reached the last page. */ 5819 if (i == (sc->rx_pages - 1)) 5820 j = 0; 5821 else 5822 j = i + 1; 5823 5824 /* Setup the chain page pointers. */ 5825 rxbd->rx_bd_haddr_hi = 5826 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5827 rxbd->rx_bd_haddr_lo = 5828 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5829 } 5830 5831 /* Fill up the RX chain. */ 5832 bce_fill_rx_chain(sc); 5833 5834 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5835 DBRUN(sc->rx_empty_count = 0); 5836 for (i = 0; i < sc->rx_pages; i++) { 5837 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5838 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5839 } 5840 5841 bce_init_rx_context(sc); 5842 5843 DBRUNMSG(BCE_EXTREME_RECV, 5844 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5845 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5846 BCE_VERBOSE_CTX); 5847 5848 /* ToDo: Are there possible failure modes here? */ 5849 5850 return(rc); 5851 } 5852 5853 5854 /****************************************************************************/ 5855 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5856 /* occurs. */ 5857 /* */ 5858 /* Returns: */ 5859 /* Nothing */ 5860 /****************************************************************************/ 5861 static void 5862 bce_fill_rx_chain(struct bce_softc *sc) 5863 { 5864 u16 prod, prod_idx; 5865 u32 prod_bseq; 5866 5867 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5868 BCE_VERBOSE_CTX); 5869 5870 /* Get the RX chain producer indices. */ 5871 prod = sc->rx_prod; 5872 prod_bseq = sc->rx_prod_bseq; 5873 5874 /* Keep filling the RX chain until it's full. */ 5875 while (sc->free_rx_bd > 0) { 5876 prod_idx = RX_CHAIN_IDX(prod); 5877 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5878 /* Bail out if we can't add an mbuf to the chain. */ 5879 break; 5880 } 5881 prod = NEXT_RX_BD(prod); 5882 } 5883 5884 /* Save the RX chain producer indices. */ 5885 sc->rx_prod = prod; 5886 sc->rx_prod_bseq = prod_bseq; 5887 5888 /* We should never end up pointing to a next page pointer. */ 5889 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5890 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5891 __FUNCTION__, rx_prod)); 5892 5893 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5894 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5895 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5896 5897 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5898 BCE_VERBOSE_CTX); 5899 } 5900 5901 5902 /****************************************************************************/ 5903 /* Free memory and clear the RX data structures. */ 5904 /* */ 5905 /* Returns: */ 5906 /* Nothing. */ 5907 /****************************************************************************/ 5908 static void 5909 bce_free_rx_chain(struct bce_softc *sc) 5910 { 5911 int i; 5912 5913 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5914 5915 /* Free any mbufs still in the RX mbuf chain. */ 5916 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5917 if (sc->rx_mbuf_ptr[i] != NULL) { 5918 if (sc->rx_mbuf_map[i] != NULL) 5919 bus_dmamap_sync(sc->rx_mbuf_tag, 5920 sc->rx_mbuf_map[i], 5921 BUS_DMASYNC_POSTREAD); 5922 m_freem(sc->rx_mbuf_ptr[i]); 5923 sc->rx_mbuf_ptr[i] = NULL; 5924 DBRUN(sc->debug_rx_mbuf_alloc--); 5925 } 5926 } 5927 5928 /* Clear each RX chain page. */ 5929 for (i = 0; i < sc->rx_pages; i++) 5930 if (sc->rx_bd_chain[i] != NULL) 5931 bzero((char *)sc->rx_bd_chain[i], 5932 BCE_RX_CHAIN_PAGE_SZ); 5933 5934 sc->free_rx_bd = sc->max_rx_bd; 5935 5936 /* Check if we lost any mbufs in the process. */ 5937 DBRUNIF((sc->debug_rx_mbuf_alloc), 5938 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5939 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5940 5941 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5942 } 5943 5944 5945 /****************************************************************************/ 5946 /* Allocate memory and initialize the page data structures. */ 5947 /* Assumes that bce_init_rx_chain() has not already been called. */ 5948 /* */ 5949 /* Returns: */ 5950 /* 0 for success, positive value for failure. */ 5951 /****************************************************************************/ 5952 static int 5953 bce_init_pg_chain(struct bce_softc *sc) 5954 { 5955 struct rx_bd *pgbd; 5956 int i, rc = 0; 5957 u32 val; 5958 5959 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5960 BCE_VERBOSE_CTX); 5961 5962 /* Initialize the page producer and consumer indices. */ 5963 sc->pg_prod = 0; 5964 sc->pg_cons = 0; 5965 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5966 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5967 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5968 DBRUN(sc->pg_empty_count = 0); 5969 5970 /* Initialize the page next pointer chain entries. */ 5971 for (i = 0; i < sc->pg_pages; i++) { 5972 int j; 5973 5974 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5975 5976 /* Check if we've reached the last page. */ 5977 if (i == (sc->pg_pages - 1)) 5978 j = 0; 5979 else 5980 j = i + 1; 5981 5982 /* Setup the chain page pointers. */ 5983 pgbd->rx_bd_haddr_hi = 5984 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5985 pgbd->rx_bd_haddr_lo = 5986 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5987 } 5988 5989 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5990 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5991 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5992 5993 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5994 5995 /* Configure the rx_bd and page chain mbuf cluster size. */ 5996 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 5997 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5998 5999 /* Configure the context reserved for jumbo support. */ 6000 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 6001 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 6002 6003 /* Point the hardware to the first page in the page chain. */ 6004 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 6005 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 6006 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 6007 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 6008 6009 /* Fill up the page chain. */ 6010 bce_fill_pg_chain(sc); 6011 6012 for (i = 0; i < sc->pg_pages; i++) { 6013 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6014 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6015 } 6016 6017 DBRUNMSG(BCE_EXTREME_RECV, 6018 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6019 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6020 BCE_VERBOSE_CTX); 6021 return(rc); 6022 } 6023 6024 6025 /****************************************************************************/ 6026 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 6027 /* occurs. */ 6028 /* */ 6029 /* Returns: */ 6030 /* Nothing */ 6031 /****************************************************************************/ 6032 static void 6033 bce_fill_pg_chain(struct bce_softc *sc) 6034 { 6035 u16 prod, prod_idx; 6036 6037 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6038 BCE_VERBOSE_CTX); 6039 6040 /* Get the page chain prodcuer index. */ 6041 prod = sc->pg_prod; 6042 6043 /* Keep filling the page chain until it's full. */ 6044 while (sc->free_pg_bd > 0) { 6045 prod_idx = PG_CHAIN_IDX(prod); 6046 if (bce_get_pg_buf(sc, prod, prod_idx)) { 6047 /* Bail out if we can't add an mbuf to the chain. */ 6048 break; 6049 } 6050 prod = NEXT_PG_BD(prod); 6051 } 6052 6053 /* Save the page chain producer index. */ 6054 sc->pg_prod = prod; 6055 6056 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6057 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6058 __FUNCTION__, pg_prod)); 6059 6060 /* 6061 * Write the mailbox and tell the chip about 6062 * the new rx_bd's in the page chain. 6063 */ 6064 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 6065 prod); 6066 6067 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6068 BCE_VERBOSE_CTX); 6069 } 6070 6071 6072 /****************************************************************************/ 6073 /* Free memory and clear the RX data structures. */ 6074 /* */ 6075 /* Returns: */ 6076 /* Nothing. */ 6077 /****************************************************************************/ 6078 static void 6079 bce_free_pg_chain(struct bce_softc *sc) 6080 { 6081 int i; 6082 6083 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6084 6085 /* Free any mbufs still in the mbuf page chain. */ 6086 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6087 if (sc->pg_mbuf_ptr[i] != NULL) { 6088 if (sc->pg_mbuf_map[i] != NULL) 6089 bus_dmamap_sync(sc->pg_mbuf_tag, 6090 sc->pg_mbuf_map[i], 6091 BUS_DMASYNC_POSTREAD); 6092 m_freem(sc->pg_mbuf_ptr[i]); 6093 sc->pg_mbuf_ptr[i] = NULL; 6094 DBRUN(sc->debug_pg_mbuf_alloc--); 6095 } 6096 } 6097 6098 /* Clear each page chain pages. */ 6099 for (i = 0; i < sc->pg_pages; i++) 6100 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6101 6102 sc->free_pg_bd = sc->max_pg_bd; 6103 6104 /* Check if we lost any mbufs in the process. */ 6105 DBRUNIF((sc->debug_pg_mbuf_alloc), 6106 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6107 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6108 6109 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6110 } 6111 6112 6113 static u32 6114 bce_get_rphy_link(struct bce_softc *sc) 6115 { 6116 u32 advertise, link; 6117 int fdpx; 6118 6119 advertise = 0; 6120 fdpx = 0; 6121 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6122 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6123 else 6124 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6125 if (link & BCE_NETLINK_ANEG_ENB) 6126 advertise |= BCE_NETLINK_ANEG_ENB; 6127 if (link & BCE_NETLINK_SPEED_10HALF) 6128 advertise |= BCE_NETLINK_SPEED_10HALF; 6129 if (link & BCE_NETLINK_SPEED_10FULL) { 6130 advertise |= BCE_NETLINK_SPEED_10FULL; 6131 fdpx++; 6132 } 6133 if (link & BCE_NETLINK_SPEED_100HALF) 6134 advertise |= BCE_NETLINK_SPEED_100HALF; 6135 if (link & BCE_NETLINK_SPEED_100FULL) { 6136 advertise |= BCE_NETLINK_SPEED_100FULL; 6137 fdpx++; 6138 } 6139 if (link & BCE_NETLINK_SPEED_1000HALF) 6140 advertise |= BCE_NETLINK_SPEED_1000HALF; 6141 if (link & BCE_NETLINK_SPEED_1000FULL) { 6142 advertise |= BCE_NETLINK_SPEED_1000FULL; 6143 fdpx++; 6144 } 6145 if (link & BCE_NETLINK_SPEED_2500HALF) 6146 advertise |= BCE_NETLINK_SPEED_2500HALF; 6147 if (link & BCE_NETLINK_SPEED_2500FULL) { 6148 advertise |= BCE_NETLINK_SPEED_2500FULL; 6149 fdpx++; 6150 } 6151 if (fdpx) 6152 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6153 BCE_NETLINK_FC_PAUSE_ASYM; 6154 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6155 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6156 BCE_NETLINK_ETH_AT_WIRESPEED; 6157 6158 return (advertise); 6159 } 6160 6161 6162 /****************************************************************************/ 6163 /* Set media options. */ 6164 /* */ 6165 /* Returns: */ 6166 /* 0 for success, positive value for failure. */ 6167 /****************************************************************************/ 6168 static int 6169 bce_ifmedia_upd(struct ifnet *ifp) 6170 { 6171 struct bce_softc *sc = ifp->if_softc; 6172 int error; 6173 6174 DBENTER(BCE_VERBOSE); 6175 6176 BCE_LOCK(sc); 6177 error = bce_ifmedia_upd_locked(ifp); 6178 BCE_UNLOCK(sc); 6179 6180 DBEXIT(BCE_VERBOSE); 6181 return (error); 6182 } 6183 6184 6185 /****************************************************************************/ 6186 /* Set media options. */ 6187 /* */ 6188 /* Returns: */ 6189 /* Nothing. */ 6190 /****************************************************************************/ 6191 static int 6192 bce_ifmedia_upd_locked(struct ifnet *ifp) 6193 { 6194 struct bce_softc *sc = ifp->if_softc; 6195 struct mii_data *mii; 6196 struct mii_softc *miisc; 6197 struct ifmedia *ifm; 6198 u32 link; 6199 int error, fdx; 6200 6201 DBENTER(BCE_VERBOSE_PHY); 6202 6203 error = 0; 6204 BCE_LOCK_ASSERT(sc); 6205 6206 sc->bce_link_up = FALSE; 6207 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6208 ifm = &sc->bce_ifmedia; 6209 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6210 return (EINVAL); 6211 link = 0; 6212 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6213 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6214 case IFM_AUTO: 6215 /* 6216 * Check advertised link of remote PHY by reading 6217 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6218 * Always use the same link type of remote PHY. 6219 */ 6220 link = bce_get_rphy_link(sc); 6221 break; 6222 case IFM_2500_SX: 6223 if ((sc->bce_phy_flags & 6224 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6225 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6226 return (EINVAL); 6227 /* 6228 * XXX 6229 * Have to enable forced 2.5Gbps configuration. 6230 */ 6231 if (fdx != 0) 6232 link |= BCE_NETLINK_SPEED_2500FULL; 6233 else 6234 link |= BCE_NETLINK_SPEED_2500HALF; 6235 break; 6236 case IFM_1000_SX: 6237 if ((sc->bce_phy_flags & 6238 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6239 return (EINVAL); 6240 /* 6241 * XXX 6242 * Have to disable 2.5Gbps configuration. 6243 */ 6244 if (fdx != 0) 6245 link = BCE_NETLINK_SPEED_1000FULL; 6246 else 6247 link = BCE_NETLINK_SPEED_1000HALF; 6248 break; 6249 case IFM_1000_T: 6250 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6251 return (EINVAL); 6252 if (fdx != 0) 6253 link = BCE_NETLINK_SPEED_1000FULL; 6254 else 6255 link = BCE_NETLINK_SPEED_1000HALF; 6256 break; 6257 case IFM_100_TX: 6258 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6259 return (EINVAL); 6260 if (fdx != 0) 6261 link = BCE_NETLINK_SPEED_100FULL; 6262 else 6263 link = BCE_NETLINK_SPEED_100HALF; 6264 break; 6265 case IFM_10_T: 6266 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6267 return (EINVAL); 6268 if (fdx != 0) 6269 link = BCE_NETLINK_SPEED_10FULL; 6270 else 6271 link = BCE_NETLINK_SPEED_10HALF; 6272 break; 6273 default: 6274 return (EINVAL); 6275 } 6276 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6277 /* 6278 * XXX 6279 * Advertise pause capability for full-duplex media. 6280 */ 6281 if (fdx != 0) 6282 link |= BCE_NETLINK_FC_PAUSE_SYM | 6283 BCE_NETLINK_FC_PAUSE_ASYM; 6284 if ((sc->bce_phy_flags & 6285 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6286 link |= BCE_NETLINK_PHY_APP_REMOTE | 6287 BCE_NETLINK_ETH_AT_WIRESPEED; 6288 } 6289 6290 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6291 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6292 } else { 6293 mii = device_get_softc(sc->bce_miibus); 6294 6295 /* Make sure the MII bus has been enumerated. */ 6296 if (mii) { 6297 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6298 PHY_RESET(miisc); 6299 error = mii_mediachg(mii); 6300 } 6301 } 6302 6303 DBEXIT(BCE_VERBOSE_PHY); 6304 return (error); 6305 } 6306 6307 6308 static void 6309 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6310 { 6311 struct ifnet *ifp; 6312 u32 link; 6313 6314 ifp = sc->bce_ifp; 6315 BCE_LOCK_ASSERT(sc); 6316 6317 ifmr->ifm_status = IFM_AVALID; 6318 ifmr->ifm_active = IFM_ETHER; 6319 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6320 /* XXX Handle heart beat status? */ 6321 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6322 ifmr->ifm_status |= IFM_ACTIVE; 6323 else { 6324 ifmr->ifm_active |= IFM_NONE; 6325 ifp->if_baudrate = 0; 6326 return; 6327 } 6328 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6329 case BCE_LINK_STATUS_10HALF: 6330 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6331 ifp->if_baudrate = IF_Mbps(10UL); 6332 break; 6333 case BCE_LINK_STATUS_10FULL: 6334 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6335 ifp->if_baudrate = IF_Mbps(10UL); 6336 break; 6337 case BCE_LINK_STATUS_100HALF: 6338 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6339 ifp->if_baudrate = IF_Mbps(100UL); 6340 break; 6341 case BCE_LINK_STATUS_100FULL: 6342 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6343 ifp->if_baudrate = IF_Mbps(100UL); 6344 break; 6345 case BCE_LINK_STATUS_1000HALF: 6346 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6347 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6348 else 6349 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6350 ifp->if_baudrate = IF_Mbps(1000UL); 6351 break; 6352 case BCE_LINK_STATUS_1000FULL: 6353 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6354 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6355 else 6356 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6357 ifp->if_baudrate = IF_Mbps(1000UL); 6358 break; 6359 case BCE_LINK_STATUS_2500HALF: 6360 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6361 ifmr->ifm_active |= IFM_NONE; 6362 return; 6363 } else 6364 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6365 ifp->if_baudrate = IF_Mbps(2500UL); 6366 break; 6367 case BCE_LINK_STATUS_2500FULL: 6368 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6369 ifmr->ifm_active |= IFM_NONE; 6370 return; 6371 } else 6372 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6373 ifp->if_baudrate = IF_Mbps(2500UL); 6374 break; 6375 default: 6376 ifmr->ifm_active |= IFM_NONE; 6377 return; 6378 } 6379 6380 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6381 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6382 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6383 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6384 } 6385 6386 6387 /****************************************************************************/ 6388 /* Reports current media status. */ 6389 /* */ 6390 /* Returns: */ 6391 /* Nothing. */ 6392 /****************************************************************************/ 6393 static void 6394 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6395 { 6396 struct bce_softc *sc = ifp->if_softc; 6397 struct mii_data *mii; 6398 6399 DBENTER(BCE_VERBOSE_PHY); 6400 6401 BCE_LOCK(sc); 6402 6403 if ((ifp->if_flags & IFF_UP) == 0) { 6404 BCE_UNLOCK(sc); 6405 return; 6406 } 6407 6408 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6409 bce_ifmedia_sts_rphy(sc, ifmr); 6410 else { 6411 mii = device_get_softc(sc->bce_miibus); 6412 mii_pollstat(mii); 6413 ifmr->ifm_active = mii->mii_media_active; 6414 ifmr->ifm_status = mii->mii_media_status; 6415 } 6416 6417 BCE_UNLOCK(sc); 6418 6419 DBEXIT(BCE_VERBOSE_PHY); 6420 } 6421 6422 6423 /****************************************************************************/ 6424 /* Handles PHY generated interrupt events. */ 6425 /* */ 6426 /* Returns: */ 6427 /* Nothing. */ 6428 /****************************************************************************/ 6429 static void 6430 bce_phy_intr(struct bce_softc *sc) 6431 { 6432 u32 new_link_state, old_link_state; 6433 6434 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6435 6436 DBRUN(sc->phy_interrupts++); 6437 6438 new_link_state = sc->status_block->status_attn_bits & 6439 STATUS_ATTN_BITS_LINK_STATE; 6440 old_link_state = sc->status_block->status_attn_bits_ack & 6441 STATUS_ATTN_BITS_LINK_STATE; 6442 6443 /* Handle any changes if the link state has changed. */ 6444 if (new_link_state != old_link_state) { 6445 6446 /* Update the status_attn_bits_ack field. */ 6447 if (new_link_state) { 6448 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6449 STATUS_ATTN_BITS_LINK_STATE); 6450 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6451 __FUNCTION__); 6452 } else { 6453 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6454 STATUS_ATTN_BITS_LINK_STATE); 6455 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6456 __FUNCTION__); 6457 } 6458 6459 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6460 if (new_link_state) { 6461 if (bootverbose) 6462 if_printf(sc->bce_ifp, "link UP\n"); 6463 if_link_state_change(sc->bce_ifp, 6464 LINK_STATE_UP); 6465 } else { 6466 if (bootverbose) 6467 if_printf(sc->bce_ifp, "link DOWN\n"); 6468 if_link_state_change(sc->bce_ifp, 6469 LINK_STATE_DOWN); 6470 } 6471 } 6472 /* 6473 * Assume link is down and allow 6474 * tick routine to update the state 6475 * based on the actual media state. 6476 */ 6477 sc->bce_link_up = FALSE; 6478 callout_stop(&sc->bce_tick_callout); 6479 bce_tick(sc); 6480 } 6481 6482 /* Acknowledge the link change interrupt. */ 6483 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6484 6485 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6486 } 6487 6488 6489 /****************************************************************************/ 6490 /* Reads the receive consumer value from the status block (skipping over */ 6491 /* chain page pointer if necessary). */ 6492 /* */ 6493 /* Returns: */ 6494 /* hw_cons */ 6495 /****************************************************************************/ 6496 static inline u16 6497 bce_get_hw_rx_cons(struct bce_softc *sc) 6498 { 6499 u16 hw_cons; 6500 6501 rmb(); 6502 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6503 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6504 hw_cons++; 6505 6506 return hw_cons; 6507 } 6508 6509 /****************************************************************************/ 6510 /* Handles received frame interrupt events. */ 6511 /* */ 6512 /* Returns: */ 6513 /* Nothing. */ 6514 /****************************************************************************/ 6515 static void 6516 bce_rx_intr(struct bce_softc *sc) 6517 { 6518 struct ifnet *ifp = sc->bce_ifp; 6519 struct l2_fhdr *l2fhdr; 6520 struct ether_vlan_header *vh; 6521 unsigned int pkt_len; 6522 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6523 u32 status; 6524 unsigned int rem_len; 6525 u16 sw_pg_cons, sw_pg_cons_idx; 6526 6527 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6528 DBRUN(sc->interrupts_rx++); 6529 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6530 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6531 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6532 6533 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6534 for (int i = 0; i < sc->rx_pages; i++) 6535 bus_dmamap_sync(sc->rx_bd_chain_tag, 6536 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6537 6538 /* Prepare the page chain pages to be accessed by the host CPU. */ 6539 if (bce_hdr_split == TRUE) { 6540 for (int i = 0; i < sc->pg_pages; i++) 6541 bus_dmamap_sync(sc->pg_bd_chain_tag, 6542 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6543 } 6544 6545 /* Get the hardware's view of the RX consumer index. */ 6546 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6547 6548 /* Get working copies of the driver's view of the consumer indices. */ 6549 sw_rx_cons = sc->rx_cons; 6550 sw_pg_cons = sc->pg_cons; 6551 6552 /* Update some debug statistics counters */ 6553 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6554 sc->rx_low_watermark = sc->free_rx_bd); 6555 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6556 sc->rx_empty_count++); 6557 6558 /* Scan through the receive chain as long as there is work to do */ 6559 /* ToDo: Consider setting a limit on the number of packets processed. */ 6560 rmb(); 6561 while (sw_rx_cons != hw_rx_cons) { 6562 struct mbuf *m0; 6563 6564 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6565 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6566 6567 /* Unmap the mbuf from DMA space. */ 6568 bus_dmamap_sync(sc->rx_mbuf_tag, 6569 sc->rx_mbuf_map[sw_rx_cons_idx], 6570 BUS_DMASYNC_POSTREAD); 6571 bus_dmamap_unload(sc->rx_mbuf_tag, 6572 sc->rx_mbuf_map[sw_rx_cons_idx]); 6573 6574 /* Remove the mbuf from the RX chain. */ 6575 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6576 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6577 DBRUN(sc->debug_rx_mbuf_alloc--); 6578 sc->free_rx_bd++; 6579 6580 /* 6581 * Frames received on the NetXteme II are prepended 6582 * with an l2_fhdr structure which provides status 6583 * information about the received frame (including 6584 * VLAN tags and checksum info). The frames are 6585 * also automatically adjusted to word align the IP 6586 * header (i.e. two null bytes are inserted before 6587 * the Ethernet header). As a result the data 6588 * DMA'd by the controller into the mbuf looks 6589 * like this: 6590 * 6591 * +---------+-----+---------------------+-----+ 6592 * | l2_fhdr | pad | packet data | FCS | 6593 * +---------+-----+---------------------+-----+ 6594 * 6595 * The l2_fhdr needs to be checked and skipped and 6596 * the FCS needs to be stripped before sending the 6597 * packet up the stack. 6598 */ 6599 l2fhdr = mtod(m0, struct l2_fhdr *); 6600 6601 /* Get the packet data + FCS length and the status. */ 6602 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6603 status = l2fhdr->l2_fhdr_status; 6604 6605 /* 6606 * Skip over the l2_fhdr and pad, resulting in the 6607 * following data in the mbuf: 6608 * +---------------------+-----+ 6609 * | packet data | FCS | 6610 * +---------------------+-----+ 6611 */ 6612 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6613 6614 /* 6615 * When split header mode is used, an ethernet frame 6616 * may be split across the receive chain and the 6617 * page chain. If that occurs an mbuf cluster must be 6618 * reassembled from the individual mbuf pieces. 6619 */ 6620 if (bce_hdr_split == TRUE) { 6621 /* 6622 * Check whether the received frame fits in a single 6623 * mbuf or not (i.e. packet data + FCS <= 6624 * sc->rx_bd_mbuf_data_len bytes). 6625 */ 6626 if (pkt_len > m0->m_len) { 6627 /* 6628 * The received frame is larger than a single mbuf. 6629 * If the frame was a TCP frame then only the TCP 6630 * header is placed in the mbuf, the remaining 6631 * payload (including FCS) is placed in the page 6632 * chain, the SPLIT flag is set, and the header 6633 * length is placed in the IP checksum field. 6634 * If the frame is not a TCP frame then the mbuf 6635 * is filled and the remaining bytes are placed 6636 * in the page chain. 6637 */ 6638 6639 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6640 "packet.\n", __FUNCTION__); 6641 DBRUN(sc->split_header_frames_rcvd++); 6642 6643 /* 6644 * When the page chain is enabled and the TCP 6645 * header has been split from the TCP payload, 6646 * the ip_xsum structure will reflect the length 6647 * of the TCP header, not the IP checksum. Set 6648 * the packet length of the mbuf accordingly. 6649 */ 6650 if (status & L2_FHDR_STATUS_SPLIT) { 6651 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6652 DBRUN(sc->split_header_tcp_frames_rcvd++); 6653 } 6654 6655 rem_len = pkt_len - m0->m_len; 6656 6657 /* Pull mbufs off the page chain for any remaining data. */ 6658 while (rem_len > 0) { 6659 struct mbuf *m_pg; 6660 6661 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6662 6663 /* Remove the mbuf from the page chain. */ 6664 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6665 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6666 DBRUN(sc->debug_pg_mbuf_alloc--); 6667 sc->free_pg_bd++; 6668 6669 /* Unmap the page chain mbuf from DMA space. */ 6670 bus_dmamap_sync(sc->pg_mbuf_tag, 6671 sc->pg_mbuf_map[sw_pg_cons_idx], 6672 BUS_DMASYNC_POSTREAD); 6673 bus_dmamap_unload(sc->pg_mbuf_tag, 6674 sc->pg_mbuf_map[sw_pg_cons_idx]); 6675 6676 /* Adjust the mbuf length. */ 6677 if (rem_len < m_pg->m_len) { 6678 /* The mbuf chain is complete. */ 6679 m_pg->m_len = rem_len; 6680 rem_len = 0; 6681 } else { 6682 /* More packet data is waiting. */ 6683 rem_len -= m_pg->m_len; 6684 } 6685 6686 /* Concatenate the mbuf cluster to the mbuf. */ 6687 m_cat(m0, m_pg); 6688 6689 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6690 } 6691 6692 /* Set the total packet length. */ 6693 m0->m_pkthdr.len = pkt_len; 6694 6695 } else { 6696 /* 6697 * The received packet is small and fits in a 6698 * single mbuf (i.e. the l2_fhdr + pad + packet + 6699 * FCS <= MHLEN). In other words, the packet is 6700 * 154 bytes or less in size. 6701 */ 6702 6703 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6704 "packet.\n", __FUNCTION__); 6705 6706 /* Set the total packet length. */ 6707 m0->m_pkthdr.len = m0->m_len = pkt_len; 6708 } 6709 } else 6710 /* Set the total packet length. */ 6711 m0->m_pkthdr.len = m0->m_len = pkt_len; 6712 6713 /* Remove the trailing Ethernet FCS. */ 6714 m_adj(m0, -ETHER_CRC_LEN); 6715 6716 /* Check that the resulting mbuf chain is valid. */ 6717 DBRUN(m_sanity(m0, FALSE)); 6718 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6719 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6720 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6721 m_print(m0, 128)); 6722 6723 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6724 sc->l2fhdr_error_sim_count++; 6725 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6726 6727 /* Check the received frame for errors. */ 6728 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6729 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6730 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6731 6732 /* Log the error and release the mbuf. */ 6733 ifp->if_ierrors++; 6734 sc->l2fhdr_error_count++; 6735 6736 m_freem(m0); 6737 m0 = NULL; 6738 goto bce_rx_intr_next_rx; 6739 } 6740 6741 /* Send the packet to the appropriate interface. */ 6742 m0->m_pkthdr.rcvif = ifp; 6743 6744 /* Assume no hardware checksum. */ 6745 m0->m_pkthdr.csum_flags = 0; 6746 6747 /* Validate the checksum if offload enabled. */ 6748 if (ifp->if_capenable & IFCAP_RXCSUM) { 6749 /* Check for an IP datagram. */ 6750 if (!(status & L2_FHDR_STATUS_SPLIT) && 6751 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6752 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6753 DBRUN(sc->csum_offload_ip++); 6754 /* Check if the IP checksum is valid. */ 6755 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6756 m0->m_pkthdr.csum_flags |= 6757 CSUM_IP_VALID; 6758 } 6759 6760 /* Check for a valid TCP/UDP frame. */ 6761 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6762 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6763 6764 /* Check for a good TCP/UDP checksum. */ 6765 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6766 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6767 DBRUN(sc->csum_offload_tcp_udp++); 6768 m0->m_pkthdr.csum_data = 6769 l2fhdr->l2_fhdr_tcp_udp_xsum; 6770 m0->m_pkthdr.csum_flags |= 6771 (CSUM_DATA_VALID 6772 | CSUM_PSEUDO_HDR); 6773 } 6774 } 6775 } 6776 6777 /* Attach the VLAN tag. */ 6778 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6779 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6780 DBRUN(sc->vlan_tagged_frames_rcvd++); 6781 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6782 DBRUN(sc->vlan_tagged_frames_stripped++); 6783 #if __FreeBSD_version < 700000 6784 VLAN_INPUT_TAG(ifp, m0, 6785 l2fhdr->l2_fhdr_vlan_tag, continue); 6786 #else 6787 m0->m_pkthdr.ether_vtag = 6788 l2fhdr->l2_fhdr_vlan_tag; 6789 m0->m_flags |= M_VLANTAG; 6790 #endif 6791 } else { 6792 /* 6793 * bce(4) controllers can't disable VLAN 6794 * tag stripping if management firmware 6795 * (ASF/IPMI/UMP) is running. So we always 6796 * strip VLAN tag and manually reconstruct 6797 * the VLAN frame by appending stripped 6798 * VLAN tag in driver if VLAN tag stripping 6799 * was disabled. 6800 * 6801 * TODO: LLC SNAP handling. 6802 */ 6803 bcopy(mtod(m0, uint8_t *), 6804 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6805 ETHER_ADDR_LEN * 2); 6806 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6807 vh = mtod(m0, struct ether_vlan_header *); 6808 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6809 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6810 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6811 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6812 } 6813 } 6814 6815 /* Increment received packet statistics. */ 6816 ifp->if_ipackets++; 6817 6818 bce_rx_intr_next_rx: 6819 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6820 6821 /* If we have a packet, pass it up the stack */ 6822 if (m0) { 6823 /* Make sure we don't lose our place when we release the lock. */ 6824 sc->rx_cons = sw_rx_cons; 6825 sc->pg_cons = sw_pg_cons; 6826 6827 BCE_UNLOCK(sc); 6828 (*ifp->if_input)(ifp, m0); 6829 BCE_LOCK(sc); 6830 6831 /* Recover our place. */ 6832 sw_rx_cons = sc->rx_cons; 6833 sw_pg_cons = sc->pg_cons; 6834 } 6835 6836 /* Refresh hw_cons to see if there's new work */ 6837 if (sw_rx_cons == hw_rx_cons) 6838 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6839 } 6840 6841 /* No new packets. Refill the page chain. */ 6842 if (bce_hdr_split == TRUE) { 6843 sc->pg_cons = sw_pg_cons; 6844 bce_fill_pg_chain(sc); 6845 } 6846 6847 /* No new packets. Refill the RX chain. */ 6848 sc->rx_cons = sw_rx_cons; 6849 bce_fill_rx_chain(sc); 6850 6851 /* Prepare the page chain pages to be accessed by the NIC. */ 6852 for (int i = 0; i < sc->rx_pages; i++) 6853 bus_dmamap_sync(sc->rx_bd_chain_tag, 6854 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6855 6856 if (bce_hdr_split == TRUE) { 6857 for (int i = 0; i < sc->pg_pages; i++) 6858 bus_dmamap_sync(sc->pg_bd_chain_tag, 6859 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6860 } 6861 6862 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6863 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6864 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6865 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6866 } 6867 6868 6869 /****************************************************************************/ 6870 /* Reads the transmit consumer value from the status block (skipping over */ 6871 /* chain page pointer if necessary). */ 6872 /* */ 6873 /* Returns: */ 6874 /* hw_cons */ 6875 /****************************************************************************/ 6876 static inline u16 6877 bce_get_hw_tx_cons(struct bce_softc *sc) 6878 { 6879 u16 hw_cons; 6880 6881 mb(); 6882 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6883 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6884 hw_cons++; 6885 6886 return hw_cons; 6887 } 6888 6889 6890 /****************************************************************************/ 6891 /* Handles transmit completion interrupt events. */ 6892 /* */ 6893 /* Returns: */ 6894 /* Nothing. */ 6895 /****************************************************************************/ 6896 static void 6897 bce_tx_intr(struct bce_softc *sc) 6898 { 6899 struct ifnet *ifp = sc->bce_ifp; 6900 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6901 6902 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6903 DBRUN(sc->interrupts_tx++); 6904 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6905 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6906 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6907 6908 BCE_LOCK_ASSERT(sc); 6909 6910 /* Get the hardware's view of the TX consumer index. */ 6911 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6912 sw_tx_cons = sc->tx_cons; 6913 6914 /* Prevent speculative reads of the status block. */ 6915 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6916 BUS_SPACE_BARRIER_READ); 6917 6918 /* Cycle through any completed TX chain page entries. */ 6919 while (sw_tx_cons != hw_tx_cons) { 6920 #ifdef BCE_DEBUG 6921 struct tx_bd *txbd = NULL; 6922 #endif 6923 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6924 6925 DBPRINT(sc, BCE_INFO_SEND, 6926 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6927 "sw_tx_chain_cons = 0x%04X\n", 6928 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6929 6930 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6931 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6932 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6933 (int) MAX_TX_BD_ALLOC); 6934 bce_breakpoint(sc)); 6935 6936 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6937 [TX_IDX(sw_tx_chain_cons)]); 6938 6939 DBRUNIF((txbd == NULL), 6940 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6941 __FILE__, __LINE__, sw_tx_chain_cons); 6942 bce_breakpoint(sc)); 6943 6944 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6945 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6946 6947 /* 6948 * Free the associated mbuf. Remember 6949 * that only the last tx_bd of a packet 6950 * has an mbuf pointer and DMA map. 6951 */ 6952 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6953 6954 /* Validate that this is the last tx_bd. */ 6955 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6956 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6957 "txmbuf == NULL!\n", __FILE__, __LINE__); 6958 bce_breakpoint(sc)); 6959 6960 DBRUNMSG(BCE_INFO_SEND, 6961 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6962 "from tx_bd[0x%04X]\n", __FUNCTION__, 6963 sw_tx_chain_cons)); 6964 6965 /* Unmap the mbuf. */ 6966 bus_dmamap_unload(sc->tx_mbuf_tag, 6967 sc->tx_mbuf_map[sw_tx_chain_cons]); 6968 6969 /* Free the mbuf. */ 6970 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6971 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6972 DBRUN(sc->debug_tx_mbuf_alloc--); 6973 6974 ifp->if_opackets++; 6975 } 6976 6977 sc->used_tx_bd--; 6978 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6979 6980 /* Refresh hw_cons to see if there's new work. */ 6981 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6982 6983 /* Prevent speculative reads of the status block. */ 6984 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6985 BUS_SPACE_BARRIER_READ); 6986 } 6987 6988 /* Clear the TX timeout timer. */ 6989 sc->watchdog_timer = 0; 6990 6991 /* Clear the tx hardware queue full flag. */ 6992 if (sc->used_tx_bd < sc->max_tx_bd) { 6993 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6994 DBPRINT(sc, BCE_INFO_SEND, 6995 "%s(): Open TX chain! %d/%d (used/total)\n", 6996 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6997 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6998 } 6999 7000 sc->tx_cons = sw_tx_cons; 7001 7002 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 7003 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 7004 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 7005 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 7006 } 7007 7008 7009 /****************************************************************************/ 7010 /* Disables interrupt generation. */ 7011 /* */ 7012 /* Returns: */ 7013 /* Nothing. */ 7014 /****************************************************************************/ 7015 static void 7016 bce_disable_intr(struct bce_softc *sc) 7017 { 7018 DBENTER(BCE_VERBOSE_INTR); 7019 7020 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7021 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 7022 7023 DBEXIT(BCE_VERBOSE_INTR); 7024 } 7025 7026 7027 /****************************************************************************/ 7028 /* Enables interrupt generation. */ 7029 /* */ 7030 /* Returns: */ 7031 /* Nothing. */ 7032 /****************************************************************************/ 7033 static void 7034 bce_enable_intr(struct bce_softc *sc, int coal_now) 7035 { 7036 DBENTER(BCE_VERBOSE_INTR); 7037 7038 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7039 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 7040 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 7041 7042 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7043 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 7044 7045 /* Force an immediate interrupt (whether there is new data or not). */ 7046 if (coal_now) 7047 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 7048 7049 DBEXIT(BCE_VERBOSE_INTR); 7050 } 7051 7052 7053 /****************************************************************************/ 7054 /* Handles controller initialization. */ 7055 /* */ 7056 /* Returns: */ 7057 /* Nothing. */ 7058 /****************************************************************************/ 7059 static void 7060 bce_init_locked(struct bce_softc *sc) 7061 { 7062 struct ifnet *ifp; 7063 u32 ether_mtu = 0; 7064 7065 DBENTER(BCE_VERBOSE_RESET); 7066 7067 BCE_LOCK_ASSERT(sc); 7068 7069 ifp = sc->bce_ifp; 7070 7071 /* Check if the driver is still running and bail out if it is. */ 7072 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7073 goto bce_init_locked_exit; 7074 7075 bce_stop(sc); 7076 7077 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 7078 BCE_PRINTF("%s(%d): Controller reset failed!\n", 7079 __FILE__, __LINE__); 7080 goto bce_init_locked_exit; 7081 } 7082 7083 if (bce_chipinit(sc)) { 7084 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 7085 __FILE__, __LINE__); 7086 goto bce_init_locked_exit; 7087 } 7088 7089 if (bce_blockinit(sc)) { 7090 BCE_PRINTF("%s(%d): Block initialization failed!\n", 7091 __FILE__, __LINE__); 7092 goto bce_init_locked_exit; 7093 } 7094 7095 /* Load our MAC address. */ 7096 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 7097 bce_set_mac_addr(sc); 7098 7099 if (bce_hdr_split == FALSE) 7100 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7101 /* 7102 * Calculate and program the hardware Ethernet MTU 7103 * size. Be generous on the receive if we have room 7104 * and allowed by the user. 7105 */ 7106 if (bce_strict_rx_mtu == TRUE) 7107 ether_mtu = ifp->if_mtu; 7108 else { 7109 if (bce_hdr_split == TRUE) { 7110 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES) 7111 ether_mtu = sc->rx_bd_mbuf_data_len + 7112 MCLBYTES; 7113 else 7114 ether_mtu = ifp->if_mtu; 7115 } else { 7116 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 7117 ether_mtu = sc->rx_bd_mbuf_data_len; 7118 else 7119 ether_mtu = ifp->if_mtu; 7120 } 7121 } 7122 7123 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7124 7125 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7126 __FUNCTION__, ether_mtu); 7127 7128 /* Program the mtu, enabling jumbo frame support if necessary. */ 7129 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7130 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7131 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7132 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7133 else 7134 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7135 7136 /* Program appropriate promiscuous/multicast filtering. */ 7137 bce_set_rx_mode(sc); 7138 7139 if (bce_hdr_split == TRUE) { 7140 /* Init page buffer descriptor chain. */ 7141 bce_init_pg_chain(sc); 7142 } 7143 7144 /* Init RX buffer descriptor chain. */ 7145 bce_init_rx_chain(sc); 7146 7147 /* Init TX buffer descriptor chain. */ 7148 bce_init_tx_chain(sc); 7149 7150 /* Enable host interrupts. */ 7151 bce_enable_intr(sc, 1); 7152 7153 bce_ifmedia_upd_locked(ifp); 7154 7155 /* Let the OS know the driver is up and running. */ 7156 ifp->if_drv_flags |= IFF_DRV_RUNNING; 7157 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7158 7159 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7160 7161 bce_init_locked_exit: 7162 DBEXIT(BCE_VERBOSE_RESET); 7163 } 7164 7165 7166 /****************************************************************************/ 7167 /* Initialize the controller just enough so that any management firmware */ 7168 /* running on the device will continue to operate correctly. */ 7169 /* */ 7170 /* Returns: */ 7171 /* Nothing. */ 7172 /****************************************************************************/ 7173 static void 7174 bce_mgmt_init_locked(struct bce_softc *sc) 7175 { 7176 struct ifnet *ifp; 7177 7178 DBENTER(BCE_VERBOSE_RESET); 7179 7180 BCE_LOCK_ASSERT(sc); 7181 7182 /* Bail out if management firmware is not running. */ 7183 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7184 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7185 "No management firmware running...\n"); 7186 goto bce_mgmt_init_locked_exit; 7187 } 7188 7189 ifp = sc->bce_ifp; 7190 7191 /* Enable all critical blocks in the MAC. */ 7192 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7193 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7194 DELAY(20); 7195 7196 bce_ifmedia_upd_locked(ifp); 7197 7198 bce_mgmt_init_locked_exit: 7199 DBEXIT(BCE_VERBOSE_RESET); 7200 } 7201 7202 7203 /****************************************************************************/ 7204 /* Handles controller initialization when called from an unlocked routine. */ 7205 /* */ 7206 /* Returns: */ 7207 /* Nothing. */ 7208 /****************************************************************************/ 7209 static void 7210 bce_init(void *xsc) 7211 { 7212 struct bce_softc *sc = xsc; 7213 7214 DBENTER(BCE_VERBOSE_RESET); 7215 7216 BCE_LOCK(sc); 7217 bce_init_locked(sc); 7218 BCE_UNLOCK(sc); 7219 7220 DBEXIT(BCE_VERBOSE_RESET); 7221 } 7222 7223 7224 /****************************************************************************/ 7225 /* Modifies an mbuf for TSO on the hardware. */ 7226 /* */ 7227 /* Returns: */ 7228 /* Pointer to a modified mbuf. */ 7229 /****************************************************************************/ 7230 static struct mbuf * 7231 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7232 { 7233 struct mbuf *m; 7234 struct ether_header *eh; 7235 struct ip *ip; 7236 struct tcphdr *th; 7237 u16 etype; 7238 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7239 7240 DBRUN(sc->tso_frames_requested++); 7241 7242 /* Controller may modify mbuf chains. */ 7243 if (M_WRITABLE(*m_head) == 0) { 7244 m = m_dup(*m_head, M_NOWAIT); 7245 m_freem(*m_head); 7246 if (m == NULL) { 7247 sc->mbuf_alloc_failed_count++; 7248 *m_head = NULL; 7249 return (NULL); 7250 } 7251 *m_head = m; 7252 } 7253 7254 /* 7255 * For TSO the controller needs two pieces of info, 7256 * the MSS and the IP+TCP options length. 7257 */ 7258 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7259 if (m == NULL) { 7260 *m_head = NULL; 7261 return (NULL); 7262 } 7263 eh = mtod(m, struct ether_header *); 7264 etype = ntohs(eh->ether_type); 7265 7266 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7267 switch (etype) { 7268 case ETHERTYPE_IP: 7269 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7270 /* TSO only supported for TCP protocol. */ 7271 if (ip->ip_p != IPPROTO_TCP) { 7272 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7273 __FILE__, __LINE__); 7274 m_freem(*m_head); 7275 *m_head = NULL; 7276 return (NULL); 7277 } 7278 7279 /* Get IP header length in bytes (min 20) */ 7280 ip_hlen = ip->ip_hl << 2; 7281 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7282 sizeof(struct tcphdr)); 7283 if (m == NULL) { 7284 *m_head = NULL; 7285 return (NULL); 7286 } 7287 7288 /* Get the TCP header length in bytes (min 20) */ 7289 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7290 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7291 tcp_hlen = (th->th_off << 2); 7292 7293 /* Make sure all IP/TCP options live in the same buffer. */ 7294 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7295 tcp_hlen); 7296 if (m == NULL) { 7297 *m_head = NULL; 7298 return (NULL); 7299 } 7300 7301 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7302 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7303 ip_len = ip->ip_len; 7304 ip->ip_len = 0; 7305 ip->ip_sum = 0; 7306 break; 7307 case ETHERTYPE_IPV6: 7308 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7309 __FILE__, __LINE__); 7310 m_freem(*m_head); 7311 *m_head = NULL; 7312 return (NULL); 7313 /* NOT REACHED */ 7314 default: 7315 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7316 __FILE__, __LINE__); 7317 m_freem(*m_head); 7318 *m_head = NULL; 7319 return (NULL); 7320 } 7321 7322 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7323 7324 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7325 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7326 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7327 tcp_hlen, ip_len); 7328 7329 /* Set the LSO flag in the TX BD */ 7330 *flags |= TX_BD_FLAGS_SW_LSO; 7331 7332 /* Set the length of IP + TCP options (in 32 bit words) */ 7333 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7334 sizeof(struct tcphdr)) >> 2) << 8); 7335 7336 DBRUN(sc->tso_frames_completed++); 7337 return (*m_head); 7338 } 7339 7340 7341 /****************************************************************************/ 7342 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7343 /* memory visible to the controller. */ 7344 /* */ 7345 /* Returns: */ 7346 /* 0 for success, positive value for failure. */ 7347 /* Modified: */ 7348 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7349 /****************************************************************************/ 7350 static int 7351 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7352 { 7353 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7354 bus_dmamap_t map; 7355 struct tx_bd *txbd = NULL; 7356 struct mbuf *m0; 7357 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7358 u32 prod_bseq; 7359 7360 #ifdef BCE_DEBUG 7361 u16 debug_prod; 7362 #endif 7363 7364 int i, error, nsegs, rc = 0; 7365 7366 DBENTER(BCE_VERBOSE_SEND); 7367 7368 /* Make sure we have room in the TX chain. */ 7369 if (sc->used_tx_bd >= sc->max_tx_bd) 7370 goto bce_tx_encap_exit; 7371 7372 /* Transfer any checksum offload flags to the bd. */ 7373 m0 = *m_head; 7374 if (m0->m_pkthdr.csum_flags) { 7375 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7376 m0 = bce_tso_setup(sc, m_head, &flags); 7377 if (m0 == NULL) { 7378 DBRUN(sc->tso_frames_failed++); 7379 goto bce_tx_encap_exit; 7380 } 7381 mss = htole16(m0->m_pkthdr.tso_segsz); 7382 } else { 7383 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7384 flags |= TX_BD_FLAGS_IP_CKSUM; 7385 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7386 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7387 } 7388 } 7389 7390 /* Transfer any VLAN tags to the bd. */ 7391 if (m0->m_flags & M_VLANTAG) { 7392 flags |= TX_BD_FLAGS_VLAN_TAG; 7393 vlan_tag = m0->m_pkthdr.ether_vtag; 7394 } 7395 7396 /* Map the mbuf into DMAable memory. */ 7397 prod = sc->tx_prod; 7398 chain_prod = TX_CHAIN_IDX(prod); 7399 map = sc->tx_mbuf_map[chain_prod]; 7400 7401 /* Map the mbuf into our DMA address space. */ 7402 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7403 segs, &nsegs, BUS_DMA_NOWAIT); 7404 7405 /* Check if the DMA mapping was successful */ 7406 if (error == EFBIG) { 7407 sc->mbuf_frag_count++; 7408 7409 /* Try to defrag the mbuf. */ 7410 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7411 if (m0 == NULL) { 7412 /* Defrag was unsuccessful */ 7413 m_freem(*m_head); 7414 *m_head = NULL; 7415 sc->mbuf_alloc_failed_count++; 7416 rc = ENOBUFS; 7417 goto bce_tx_encap_exit; 7418 } 7419 7420 /* Defrag was successful, try mapping again */ 7421 *m_head = m0; 7422 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7423 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7424 7425 /* Still getting an error after a defrag. */ 7426 if (error == ENOMEM) { 7427 /* Insufficient DMA buffers available. */ 7428 sc->dma_map_addr_tx_failed_count++; 7429 rc = error; 7430 goto bce_tx_encap_exit; 7431 } else if (error != 0) { 7432 /* Release it and return an error. */ 7433 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7434 "TX chain!\n", __FILE__, __LINE__); 7435 m_freem(m0); 7436 *m_head = NULL; 7437 sc->dma_map_addr_tx_failed_count++; 7438 rc = ENOBUFS; 7439 goto bce_tx_encap_exit; 7440 } 7441 } else if (error == ENOMEM) { 7442 /* Insufficient DMA buffers available. */ 7443 sc->dma_map_addr_tx_failed_count++; 7444 rc = error; 7445 goto bce_tx_encap_exit; 7446 } else if (error != 0) { 7447 m_freem(m0); 7448 *m_head = NULL; 7449 sc->dma_map_addr_tx_failed_count++; 7450 rc = error; 7451 goto bce_tx_encap_exit; 7452 } 7453 7454 /* Make sure there's room in the chain */ 7455 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7456 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7457 rc = ENOBUFS; 7458 goto bce_tx_encap_exit; 7459 } 7460 7461 /* prod points to an empty tx_bd at this point. */ 7462 prod_bseq = sc->tx_prod_bseq; 7463 7464 #ifdef BCE_DEBUG 7465 debug_prod = chain_prod; 7466 #endif 7467 7468 DBPRINT(sc, BCE_INFO_SEND, 7469 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7470 "prod_bseq = 0x%08X\n", 7471 __FUNCTION__, prod, chain_prod, prod_bseq); 7472 7473 /* 7474 * Cycle through each mbuf segment that makes up 7475 * the outgoing frame, gathering the mapping info 7476 * for that segment and creating a tx_bd for 7477 * the mbuf. 7478 */ 7479 for (i = 0; i < nsegs ; i++) { 7480 7481 chain_prod = TX_CHAIN_IDX(prod); 7482 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7483 [TX_IDX(chain_prod)]; 7484 7485 txbd->tx_bd_haddr_lo = 7486 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7487 txbd->tx_bd_haddr_hi = 7488 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7489 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7490 htole16(segs[i].ds_len); 7491 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7492 txbd->tx_bd_flags = htole16(flags); 7493 prod_bseq += segs[i].ds_len; 7494 if (i == 0) 7495 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7496 prod = NEXT_TX_BD(prod); 7497 } 7498 7499 /* Set the END flag on the last TX buffer descriptor. */ 7500 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7501 7502 DBRUNMSG(BCE_EXTREME_SEND, 7503 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7504 7505 /* 7506 * Ensure that the mbuf pointer for this transmission 7507 * is placed at the array index of the last 7508 * descriptor in this chain. This is done 7509 * because a single map is used for all 7510 * segments of the mbuf and we don't want to 7511 * unload the map before all of the segments 7512 * have been freed. 7513 */ 7514 sc->tx_mbuf_ptr[chain_prod] = m0; 7515 sc->used_tx_bd += nsegs; 7516 7517 /* Update some debug statistic counters */ 7518 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7519 sc->tx_hi_watermark = sc->used_tx_bd); 7520 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7521 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7522 7523 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7524 7525 /* prod points to the next free tx_bd at this point. */ 7526 sc->tx_prod = prod; 7527 sc->tx_prod_bseq = prod_bseq; 7528 7529 /* Tell the chip about the waiting TX frames. */ 7530 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7531 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7532 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7533 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7534 7535 bce_tx_encap_exit: 7536 DBEXIT(BCE_VERBOSE_SEND); 7537 return(rc); 7538 } 7539 7540 7541 /****************************************************************************/ 7542 /* Main transmit routine when called from another routine with a lock. */ 7543 /* */ 7544 /* Returns: */ 7545 /* Nothing. */ 7546 /****************************************************************************/ 7547 static void 7548 bce_start_locked(struct ifnet *ifp) 7549 { 7550 struct bce_softc *sc = ifp->if_softc; 7551 struct mbuf *m_head = NULL; 7552 int count = 0; 7553 u16 tx_prod, tx_chain_prod; 7554 7555 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7556 7557 BCE_LOCK_ASSERT(sc); 7558 7559 /* prod points to the next free tx_bd. */ 7560 tx_prod = sc->tx_prod; 7561 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7562 7563 DBPRINT(sc, BCE_INFO_SEND, 7564 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7565 "tx_prod_bseq = 0x%08X\n", 7566 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7567 7568 /* If there's no link or the transmit queue is empty then just exit. */ 7569 if (sc->bce_link_up == FALSE) { 7570 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7571 __FUNCTION__); 7572 goto bce_start_locked_exit; 7573 } 7574 7575 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7576 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7577 __FUNCTION__); 7578 goto bce_start_locked_exit; 7579 } 7580 7581 /* 7582 * Keep adding entries while there is space in the ring. 7583 */ 7584 while (sc->used_tx_bd < sc->max_tx_bd) { 7585 7586 /* Check for any frames to send. */ 7587 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7588 7589 /* Stop when the transmit queue is empty. */ 7590 if (m_head == NULL) 7591 break; 7592 7593 /* 7594 * Pack the data into the transmit ring. If we 7595 * don't have room, place the mbuf back at the 7596 * head of the queue and set the OACTIVE flag 7597 * to wait for the NIC to drain the chain. 7598 */ 7599 if (bce_tx_encap(sc, &m_head)) { 7600 if (m_head != NULL) 7601 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7602 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7603 DBPRINT(sc, BCE_INFO_SEND, 7604 "TX chain is closed for business! Total " 7605 "tx_bd used = %d\n", sc->used_tx_bd); 7606 break; 7607 } 7608 7609 count++; 7610 7611 /* Send a copy of the frame to any BPF listeners. */ 7612 ETHER_BPF_MTAP(ifp, m_head); 7613 } 7614 7615 /* Exit if no packets were dequeued. */ 7616 if (count == 0) { 7617 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7618 "dequeued\n", __FUNCTION__); 7619 goto bce_start_locked_exit; 7620 } 7621 7622 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7623 "send queue.\n", __FUNCTION__, count); 7624 7625 /* Set the tx timeout. */ 7626 sc->watchdog_timer = BCE_TX_TIMEOUT; 7627 7628 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7629 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7630 7631 bce_start_locked_exit: 7632 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7633 } 7634 7635 7636 /****************************************************************************/ 7637 /* Main transmit routine when called from another routine without a lock. */ 7638 /* */ 7639 /* Returns: */ 7640 /* Nothing. */ 7641 /****************************************************************************/ 7642 static void 7643 bce_start(struct ifnet *ifp) 7644 { 7645 struct bce_softc *sc = ifp->if_softc; 7646 7647 DBENTER(BCE_VERBOSE_SEND); 7648 7649 BCE_LOCK(sc); 7650 bce_start_locked(ifp); 7651 BCE_UNLOCK(sc); 7652 7653 DBEXIT(BCE_VERBOSE_SEND); 7654 } 7655 7656 7657 /****************************************************************************/ 7658 /* Handles any IOCTL calls from the operating system. */ 7659 /* */ 7660 /* Returns: */ 7661 /* 0 for success, positive value for failure. */ 7662 /****************************************************************************/ 7663 static int 7664 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7665 { 7666 struct bce_softc *sc = ifp->if_softc; 7667 struct ifreq *ifr = (struct ifreq *) data; 7668 struct mii_data *mii; 7669 int mask, error = 0; 7670 7671 DBENTER(BCE_VERBOSE_MISC); 7672 7673 switch(command) { 7674 7675 /* Set the interface MTU. */ 7676 case SIOCSIFMTU: 7677 /* Check that the MTU setting is supported. */ 7678 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7679 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7680 error = EINVAL; 7681 break; 7682 } 7683 7684 DBPRINT(sc, BCE_INFO_MISC, 7685 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7686 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7687 7688 BCE_LOCK(sc); 7689 ifp->if_mtu = ifr->ifr_mtu; 7690 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7691 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7692 bce_init_locked(sc); 7693 } 7694 BCE_UNLOCK(sc); 7695 break; 7696 7697 /* Set interface flags. */ 7698 case SIOCSIFFLAGS: 7699 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7700 7701 BCE_LOCK(sc); 7702 7703 /* Check if the interface is up. */ 7704 if (ifp->if_flags & IFF_UP) { 7705 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7706 /* Change promiscuous/multicast flags as necessary. */ 7707 bce_set_rx_mode(sc); 7708 } else { 7709 /* Start the HW */ 7710 bce_init_locked(sc); 7711 } 7712 } else { 7713 /* The interface is down, check if driver is running. */ 7714 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7715 bce_stop(sc); 7716 7717 /* If MFW is running, restart the controller a bit. */ 7718 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7719 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7720 bce_chipinit(sc); 7721 bce_mgmt_init_locked(sc); 7722 } 7723 } 7724 } 7725 7726 BCE_UNLOCK(sc); 7727 break; 7728 7729 /* Add/Delete multicast address */ 7730 case SIOCADDMULTI: 7731 case SIOCDELMULTI: 7732 DBPRINT(sc, BCE_VERBOSE_MISC, 7733 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7734 7735 BCE_LOCK(sc); 7736 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7737 bce_set_rx_mode(sc); 7738 BCE_UNLOCK(sc); 7739 7740 break; 7741 7742 /* Set/Get Interface media */ 7743 case SIOCSIFMEDIA: 7744 case SIOCGIFMEDIA: 7745 DBPRINT(sc, BCE_VERBOSE_MISC, 7746 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7747 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7748 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7749 command); 7750 else { 7751 mii = device_get_softc(sc->bce_miibus); 7752 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7753 command); 7754 } 7755 break; 7756 7757 /* Set interface capability */ 7758 case SIOCSIFCAP: 7759 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7760 DBPRINT(sc, BCE_INFO_MISC, 7761 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7762 7763 /* Toggle the TX checksum capabilities enable flag. */ 7764 if (mask & IFCAP_TXCSUM && 7765 ifp->if_capabilities & IFCAP_TXCSUM) { 7766 ifp->if_capenable ^= IFCAP_TXCSUM; 7767 if (IFCAP_TXCSUM & ifp->if_capenable) 7768 ifp->if_hwassist |= BCE_IF_HWASSIST; 7769 else 7770 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7771 } 7772 7773 /* Toggle the RX checksum capabilities enable flag. */ 7774 if (mask & IFCAP_RXCSUM && 7775 ifp->if_capabilities & IFCAP_RXCSUM) 7776 ifp->if_capenable ^= IFCAP_RXCSUM; 7777 7778 /* Toggle the TSO capabilities enable flag. */ 7779 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7780 ifp->if_capabilities & IFCAP_TSO4) { 7781 ifp->if_capenable ^= IFCAP_TSO4; 7782 if (IFCAP_TSO4 & ifp->if_capenable) 7783 ifp->if_hwassist |= CSUM_TSO; 7784 else 7785 ifp->if_hwassist &= ~CSUM_TSO; 7786 } 7787 7788 if (mask & IFCAP_VLAN_HWCSUM && 7789 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7790 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7791 7792 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7793 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7794 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7795 /* 7796 * Don't actually disable VLAN tag stripping as 7797 * management firmware (ASF/IPMI/UMP) requires the 7798 * feature. If VLAN tag stripping is disabled driver 7799 * will manually reconstruct the VLAN frame by 7800 * appending stripped VLAN tag. 7801 */ 7802 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7803 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7804 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7805 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7806 == 0) 7807 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7808 } 7809 VLAN_CAPABILITIES(ifp); 7810 break; 7811 default: 7812 /* We don't know how to handle the IOCTL, pass it on. */ 7813 error = ether_ioctl(ifp, command, data); 7814 break; 7815 } 7816 7817 DBEXIT(BCE_VERBOSE_MISC); 7818 return(error); 7819 } 7820 7821 7822 /****************************************************************************/ 7823 /* Transmit timeout handler. */ 7824 /* */ 7825 /* Returns: */ 7826 /* Nothing. */ 7827 /****************************************************************************/ 7828 static void 7829 bce_watchdog(struct bce_softc *sc) 7830 { 7831 DBENTER(BCE_EXTREME_SEND); 7832 7833 BCE_LOCK_ASSERT(sc); 7834 7835 /* If the watchdog timer hasn't expired then just exit. */ 7836 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7837 goto bce_watchdog_exit; 7838 7839 /* If pause frames are active then don't reset the hardware. */ 7840 /* ToDo: Should we reset the timer here? */ 7841 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7842 goto bce_watchdog_exit; 7843 7844 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7845 __FILE__, __LINE__); 7846 7847 DBRUNMSG(BCE_INFO, 7848 bce_dump_driver_state(sc); 7849 bce_dump_status_block(sc); 7850 bce_dump_stats_block(sc); 7851 bce_dump_ftqs(sc); 7852 bce_dump_txp_state(sc, 0); 7853 bce_dump_rxp_state(sc, 0); 7854 bce_dump_tpat_state(sc, 0); 7855 bce_dump_cp_state(sc, 0); 7856 bce_dump_com_state(sc, 0)); 7857 7858 DBRUN(bce_breakpoint(sc)); 7859 7860 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7861 7862 bce_init_locked(sc); 7863 sc->bce_ifp->if_oerrors++; 7864 7865 bce_watchdog_exit: 7866 DBEXIT(BCE_EXTREME_SEND); 7867 } 7868 7869 7870 /* 7871 * Interrupt handler. 7872 */ 7873 /****************************************************************************/ 7874 /* Main interrupt entry point. Verifies that the controller generated the */ 7875 /* interrupt and then calls a separate routine for handle the various */ 7876 /* interrupt causes (PHY, TX, RX). */ 7877 /* */ 7878 /* Returns: */ 7879 /* Nothing. */ 7880 /****************************************************************************/ 7881 static void 7882 bce_intr(void *xsc) 7883 { 7884 struct bce_softc *sc; 7885 struct ifnet *ifp; 7886 u32 status_attn_bits; 7887 u16 hw_rx_cons, hw_tx_cons; 7888 7889 sc = xsc; 7890 ifp = sc->bce_ifp; 7891 7892 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7893 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7894 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7895 7896 BCE_LOCK(sc); 7897 7898 DBRUN(sc->interrupts_generated++); 7899 7900 /* Synchnorize before we read from interface's status block */ 7901 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7902 7903 /* 7904 * If the hardware status block index matches the last value read 7905 * by the driver and we haven't asserted our interrupt then there's 7906 * nothing to do. This may only happen in case of INTx due to the 7907 * interrupt arriving at the CPU before the status block is updated. 7908 */ 7909 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7910 sc->status_block->status_idx == sc->last_status_idx && 7911 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7912 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7913 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7914 __FUNCTION__); 7915 goto bce_intr_exit; 7916 } 7917 7918 /* Ack the interrupt and stop others from occuring. */ 7919 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7920 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7921 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7922 7923 /* Check if the hardware has finished any work. */ 7924 hw_rx_cons = bce_get_hw_rx_cons(sc); 7925 hw_tx_cons = bce_get_hw_tx_cons(sc); 7926 7927 /* Keep processing data as long as there is work to do. */ 7928 for (;;) { 7929 7930 status_attn_bits = sc->status_block->status_attn_bits; 7931 7932 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7933 BCE_PRINTF("Simulating unexpected status attention " 7934 "bit set."); 7935 sc->unexpected_attention_sim_count++; 7936 status_attn_bits = status_attn_bits | 7937 STATUS_ATTN_BITS_PARITY_ERROR); 7938 7939 /* Was it a link change interrupt? */ 7940 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7941 (sc->status_block->status_attn_bits_ack & 7942 STATUS_ATTN_BITS_LINK_STATE)) { 7943 bce_phy_intr(sc); 7944 7945 /* Clear transient updates during link state change. */ 7946 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7947 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7948 REG_RD(sc, BCE_HC_COMMAND); 7949 } 7950 7951 /* If any other attention is asserted, the chip is toast. */ 7952 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7953 (sc->status_block->status_attn_bits_ack & 7954 ~STATUS_ATTN_BITS_LINK_STATE))) { 7955 7956 sc->unexpected_attention_count++; 7957 7958 BCE_PRINTF("%s(%d): Fatal attention detected: " 7959 "0x%08X\n", __FILE__, __LINE__, 7960 sc->status_block->status_attn_bits); 7961 7962 DBRUNMSG(BCE_FATAL, 7963 if (unexpected_attention_sim_control == 0) 7964 bce_breakpoint(sc)); 7965 7966 bce_init_locked(sc); 7967 goto bce_intr_exit; 7968 } 7969 7970 /* Check for any completed RX frames. */ 7971 if (hw_rx_cons != sc->hw_rx_cons) 7972 bce_rx_intr(sc); 7973 7974 /* Check for any completed TX frames. */ 7975 if (hw_tx_cons != sc->hw_tx_cons) 7976 bce_tx_intr(sc); 7977 7978 /* Save status block index value for the next interrupt. */ 7979 sc->last_status_idx = sc->status_block->status_idx; 7980 7981 /* 7982 * Prevent speculative reads from getting 7983 * ahead of the status block. 7984 */ 7985 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7986 BUS_SPACE_BARRIER_READ); 7987 7988 /* 7989 * If there's no work left then exit the 7990 * interrupt service routine. 7991 */ 7992 hw_rx_cons = bce_get_hw_rx_cons(sc); 7993 hw_tx_cons = bce_get_hw_tx_cons(sc); 7994 7995 if ((hw_rx_cons == sc->hw_rx_cons) && 7996 (hw_tx_cons == sc->hw_tx_cons)) 7997 break; 7998 } 7999 8000 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 8001 8002 /* Re-enable interrupts. */ 8003 bce_enable_intr(sc, 0); 8004 8005 /* Handle any frames that arrived while handling the interrupt. */ 8006 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 8007 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 8008 bce_start_locked(ifp); 8009 8010 bce_intr_exit: 8011 BCE_UNLOCK(sc); 8012 8013 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 8014 } 8015 8016 8017 /****************************************************************************/ 8018 /* Programs the various packet receive modes (broadcast and multicast). */ 8019 /* */ 8020 /* Returns: */ 8021 /* Nothing. */ 8022 /****************************************************************************/ 8023 static void 8024 bce_set_rx_mode(struct bce_softc *sc) 8025 { 8026 struct ifnet *ifp; 8027 struct ifmultiaddr *ifma; 8028 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 8029 u32 rx_mode, sort_mode; 8030 int h, i; 8031 8032 DBENTER(BCE_VERBOSE_MISC); 8033 8034 BCE_LOCK_ASSERT(sc); 8035 8036 ifp = sc->bce_ifp; 8037 8038 /* Initialize receive mode default settings. */ 8039 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 8040 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 8041 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 8042 8043 /* 8044 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 8045 * be enbled. 8046 */ 8047 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 8048 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 8049 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 8050 8051 /* 8052 * Check for promiscuous, all multicast, or selected 8053 * multicast address filtering. 8054 */ 8055 if (ifp->if_flags & IFF_PROMISC) { 8056 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 8057 8058 /* Enable promiscuous mode. */ 8059 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 8060 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 8061 } else if (ifp->if_flags & IFF_ALLMULTI) { 8062 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 8063 8064 /* Enable all multicast addresses. */ 8065 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 8066 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 8067 0xffffffff); 8068 } 8069 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 8070 } else { 8071 /* Accept one or more multicast(s). */ 8072 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 8073 8074 if_maddr_rlock(ifp); 8075 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 8076 if (ifma->ifma_addr->sa_family != AF_LINK) 8077 continue; 8078 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 8079 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 8080 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 8081 } 8082 if_maddr_runlock(ifp); 8083 8084 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 8085 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 8086 8087 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 8088 } 8089 8090 /* Only make changes if the recive mode has actually changed. */ 8091 if (rx_mode != sc->rx_mode) { 8092 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 8093 "0x%08X\n", rx_mode); 8094 8095 sc->rx_mode = rx_mode; 8096 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 8097 } 8098 8099 /* Disable and clear the exisitng sort before enabling a new sort. */ 8100 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 8101 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 8102 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8103 8104 DBEXIT(BCE_VERBOSE_MISC); 8105 } 8106 8107 8108 /****************************************************************************/ 8109 /* Called periodically to updates statistics from the controllers */ 8110 /* statistics block. */ 8111 /* */ 8112 /* Returns: */ 8113 /* Nothing. */ 8114 /****************************************************************************/ 8115 static void 8116 bce_stats_update(struct bce_softc *sc) 8117 { 8118 struct ifnet *ifp; 8119 struct statistics_block *stats; 8120 8121 DBENTER(BCE_EXTREME_MISC); 8122 8123 ifp = sc->bce_ifp; 8124 8125 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8126 8127 stats = (struct statistics_block *) sc->stats_block; 8128 8129 /* 8130 * Certain controllers don't report 8131 * carrier sense errors correctly. 8132 * See errata E11_5708CA0_1165. 8133 */ 8134 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8135 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8136 ifp->if_oerrors += 8137 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 8138 8139 /* 8140 * Update the sysctl statistics from the 8141 * hardware statistics. 8142 */ 8143 sc->stat_IfHCInOctets = 8144 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8145 (u64) stats->stat_IfHCInOctets_lo; 8146 8147 sc->stat_IfHCInBadOctets = 8148 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8149 (u64) stats->stat_IfHCInBadOctets_lo; 8150 8151 sc->stat_IfHCOutOctets = 8152 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8153 (u64) stats->stat_IfHCOutOctets_lo; 8154 8155 sc->stat_IfHCOutBadOctets = 8156 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8157 (u64) stats->stat_IfHCOutBadOctets_lo; 8158 8159 sc->stat_IfHCInUcastPkts = 8160 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8161 (u64) stats->stat_IfHCInUcastPkts_lo; 8162 8163 sc->stat_IfHCInMulticastPkts = 8164 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8165 (u64) stats->stat_IfHCInMulticastPkts_lo; 8166 8167 sc->stat_IfHCInBroadcastPkts = 8168 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8169 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8170 8171 sc->stat_IfHCOutUcastPkts = 8172 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8173 (u64) stats->stat_IfHCOutUcastPkts_lo; 8174 8175 sc->stat_IfHCOutMulticastPkts = 8176 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8177 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8178 8179 sc->stat_IfHCOutBroadcastPkts = 8180 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8181 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8182 8183 /* ToDo: Preserve counters beyond 32 bits? */ 8184 /* ToDo: Read the statistics from auto-clear regs? */ 8185 8186 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8187 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8188 8189 sc->stat_Dot3StatsCarrierSenseErrors = 8190 stats->stat_Dot3StatsCarrierSenseErrors; 8191 8192 sc->stat_Dot3StatsFCSErrors = 8193 stats->stat_Dot3StatsFCSErrors; 8194 8195 sc->stat_Dot3StatsAlignmentErrors = 8196 stats->stat_Dot3StatsAlignmentErrors; 8197 8198 sc->stat_Dot3StatsSingleCollisionFrames = 8199 stats->stat_Dot3StatsSingleCollisionFrames; 8200 8201 sc->stat_Dot3StatsMultipleCollisionFrames = 8202 stats->stat_Dot3StatsMultipleCollisionFrames; 8203 8204 sc->stat_Dot3StatsDeferredTransmissions = 8205 stats->stat_Dot3StatsDeferredTransmissions; 8206 8207 sc->stat_Dot3StatsExcessiveCollisions = 8208 stats->stat_Dot3StatsExcessiveCollisions; 8209 8210 sc->stat_Dot3StatsLateCollisions = 8211 stats->stat_Dot3StatsLateCollisions; 8212 8213 sc->stat_EtherStatsCollisions = 8214 stats->stat_EtherStatsCollisions; 8215 8216 sc->stat_EtherStatsFragments = 8217 stats->stat_EtherStatsFragments; 8218 8219 sc->stat_EtherStatsJabbers = 8220 stats->stat_EtherStatsJabbers; 8221 8222 sc->stat_EtherStatsUndersizePkts = 8223 stats->stat_EtherStatsUndersizePkts; 8224 8225 sc->stat_EtherStatsOversizePkts = 8226 stats->stat_EtherStatsOversizePkts; 8227 8228 sc->stat_EtherStatsPktsRx64Octets = 8229 stats->stat_EtherStatsPktsRx64Octets; 8230 8231 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8232 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8233 8234 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8235 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8236 8237 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8238 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8239 8240 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8241 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8242 8243 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8244 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8245 8246 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8247 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8248 8249 sc->stat_EtherStatsPktsTx64Octets = 8250 stats->stat_EtherStatsPktsTx64Octets; 8251 8252 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8253 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8254 8255 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8256 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8257 8258 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8259 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8260 8261 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8262 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8263 8264 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8265 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8266 8267 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8268 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8269 8270 sc->stat_XonPauseFramesReceived = 8271 stats->stat_XonPauseFramesReceived; 8272 8273 sc->stat_XoffPauseFramesReceived = 8274 stats->stat_XoffPauseFramesReceived; 8275 8276 sc->stat_OutXonSent = 8277 stats->stat_OutXonSent; 8278 8279 sc->stat_OutXoffSent = 8280 stats->stat_OutXoffSent; 8281 8282 sc->stat_FlowControlDone = 8283 stats->stat_FlowControlDone; 8284 8285 sc->stat_MacControlFramesReceived = 8286 stats->stat_MacControlFramesReceived; 8287 8288 sc->stat_XoffStateEntered = 8289 stats->stat_XoffStateEntered; 8290 8291 sc->stat_IfInFramesL2FilterDiscards = 8292 stats->stat_IfInFramesL2FilterDiscards; 8293 8294 sc->stat_IfInRuleCheckerDiscards = 8295 stats->stat_IfInRuleCheckerDiscards; 8296 8297 sc->stat_IfInFTQDiscards = 8298 stats->stat_IfInFTQDiscards; 8299 8300 sc->stat_IfInMBUFDiscards = 8301 stats->stat_IfInMBUFDiscards; 8302 8303 sc->stat_IfInRuleCheckerP4Hit = 8304 stats->stat_IfInRuleCheckerP4Hit; 8305 8306 sc->stat_CatchupInRuleCheckerDiscards = 8307 stats->stat_CatchupInRuleCheckerDiscards; 8308 8309 sc->stat_CatchupInFTQDiscards = 8310 stats->stat_CatchupInFTQDiscards; 8311 8312 sc->stat_CatchupInMBUFDiscards = 8313 stats->stat_CatchupInMBUFDiscards; 8314 8315 sc->stat_CatchupInRuleCheckerP4Hit = 8316 stats->stat_CatchupInRuleCheckerP4Hit; 8317 8318 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8319 8320 /* 8321 * Update the interface statistics from the 8322 * hardware statistics. 8323 */ 8324 ifp->if_collisions = 8325 (u_long) sc->stat_EtherStatsCollisions; 8326 8327 /* ToDo: This method loses soft errors. */ 8328 ifp->if_ierrors = 8329 (u_long) sc->stat_EtherStatsUndersizePkts + 8330 (u_long) sc->stat_EtherStatsOversizePkts + 8331 (u_long) sc->stat_IfInMBUFDiscards + 8332 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8333 (u_long) sc->stat_Dot3StatsFCSErrors + 8334 (u_long) sc->stat_IfInRuleCheckerDiscards + 8335 (u_long) sc->stat_IfInFTQDiscards + 8336 (u_long) sc->com_no_buffers; 8337 8338 /* ToDo: This method loses soft errors. */ 8339 ifp->if_oerrors = 8340 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8341 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8342 (u_long) sc->stat_Dot3StatsLateCollisions; 8343 8344 /* ToDo: Add additional statistics? */ 8345 8346 DBEXIT(BCE_EXTREME_MISC); 8347 } 8348 8349 8350 /****************************************************************************/ 8351 /* Periodic function to notify the bootcode that the driver is still */ 8352 /* present. */ 8353 /* */ 8354 /* Returns: */ 8355 /* Nothing. */ 8356 /****************************************************************************/ 8357 static void 8358 bce_pulse(void *xsc) 8359 { 8360 struct bce_softc *sc = xsc; 8361 u32 msg; 8362 8363 DBENTER(BCE_EXTREME_MISC); 8364 8365 BCE_LOCK_ASSERT(sc); 8366 8367 /* Tell the firmware that the driver is still running. */ 8368 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8369 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8370 8371 /* Update the bootcode condition. */ 8372 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8373 8374 /* Report whether the bootcode still knows the driver is running. */ 8375 if (bce_verbose || bootverbose) { 8376 if (sc->bce_drv_cardiac_arrest == FALSE) { 8377 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8378 sc->bce_drv_cardiac_arrest = TRUE; 8379 BCE_PRINTF("%s(): Warning: bootcode " 8380 "thinks driver is absent! " 8381 "(bc_state = 0x%08X)\n", 8382 __FUNCTION__, sc->bc_state); 8383 } 8384 } else { 8385 /* 8386 * Not supported by all bootcode versions. 8387 * (v5.0.11+ and v5.2.1+) Older bootcode 8388 * will require the driver to reset the 8389 * controller to clear this condition. 8390 */ 8391 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8392 sc->bce_drv_cardiac_arrest = FALSE; 8393 BCE_PRINTF("%s(): Bootcode found the " 8394 "driver pulse! (bc_state = 0x%08X)\n", 8395 __FUNCTION__, sc->bc_state); 8396 } 8397 } 8398 } 8399 8400 8401 /* Schedule the next pulse. */ 8402 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8403 8404 DBEXIT(BCE_EXTREME_MISC); 8405 } 8406 8407 8408 /****************************************************************************/ 8409 /* Periodic function to perform maintenance tasks. */ 8410 /* */ 8411 /* Returns: */ 8412 /* Nothing. */ 8413 /****************************************************************************/ 8414 static void 8415 bce_tick(void *xsc) 8416 { 8417 struct bce_softc *sc = xsc; 8418 struct mii_data *mii; 8419 struct ifnet *ifp; 8420 struct ifmediareq ifmr; 8421 8422 ifp = sc->bce_ifp; 8423 8424 DBENTER(BCE_EXTREME_MISC); 8425 8426 BCE_LOCK_ASSERT(sc); 8427 8428 /* Schedule the next tick. */ 8429 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8430 8431 /* Update the statistics from the hardware statistics block. */ 8432 bce_stats_update(sc); 8433 8434 /* Ensure page and RX chains get refilled in low-memory situations. */ 8435 if (bce_hdr_split == TRUE) 8436 bce_fill_pg_chain(sc); 8437 bce_fill_rx_chain(sc); 8438 8439 /* Check that chip hasn't hung. */ 8440 bce_watchdog(sc); 8441 8442 /* If link is up already up then we're done. */ 8443 if (sc->bce_link_up == TRUE) 8444 goto bce_tick_exit; 8445 8446 /* Link is down. Check what the PHY's doing. */ 8447 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8448 bzero(&ifmr, sizeof(ifmr)); 8449 bce_ifmedia_sts_rphy(sc, &ifmr); 8450 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8451 (IFM_ACTIVE | IFM_AVALID)) { 8452 sc->bce_link_up = TRUE; 8453 bce_miibus_statchg(sc->bce_dev); 8454 } 8455 } else { 8456 mii = device_get_softc(sc->bce_miibus); 8457 mii_tick(mii); 8458 /* Check if the link has come up. */ 8459 if ((mii->mii_media_status & IFM_ACTIVE) && 8460 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8461 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8462 __FUNCTION__); 8463 sc->bce_link_up = TRUE; 8464 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8465 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8466 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8467 (bce_verbose || bootverbose)) 8468 BCE_PRINTF("Gigabit link up!\n"); 8469 } 8470 8471 } 8472 if (sc->bce_link_up == TRUE) { 8473 /* Now that link is up, handle any outstanding TX traffic. */ 8474 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8475 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8476 "pending TX traffic.\n", __FUNCTION__); 8477 bce_start_locked(ifp); 8478 } 8479 } 8480 8481 bce_tick_exit: 8482 DBEXIT(BCE_EXTREME_MISC); 8483 } 8484 8485 static void 8486 bce_fw_cap_init(struct bce_softc *sc) 8487 { 8488 u32 ack, cap, link; 8489 8490 ack = 0; 8491 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8492 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8493 BCE_FW_CAP_SIGNATURE_MAGIC) 8494 return; 8495 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8496 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8497 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8498 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8499 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8500 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8501 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8502 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8503 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8504 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8505 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8506 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8507 BCE_FW_CAP_REMOTE_PHY_CAP; 8508 } 8509 8510 if (ack != 0) 8511 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8512 } 8513 8514 8515 #ifdef BCE_DEBUG 8516 /****************************************************************************/ 8517 /* Allows the driver state to be dumped through the sysctl interface. */ 8518 /* */ 8519 /* Returns: */ 8520 /* 0 for success, positive value for failure. */ 8521 /****************************************************************************/ 8522 static int 8523 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8524 { 8525 int error; 8526 int result; 8527 struct bce_softc *sc; 8528 8529 result = -1; 8530 error = sysctl_handle_int(oidp, &result, 0, req); 8531 8532 if (error || !req->newptr) 8533 return (error); 8534 8535 if (result == 1) { 8536 sc = (struct bce_softc *)arg1; 8537 bce_dump_driver_state(sc); 8538 } 8539 8540 return error; 8541 } 8542 8543 8544 /****************************************************************************/ 8545 /* Allows the hardware state to be dumped through the sysctl interface. */ 8546 /* */ 8547 /* Returns: */ 8548 /* 0 for success, positive value for failure. */ 8549 /****************************************************************************/ 8550 static int 8551 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8552 { 8553 int error; 8554 int result; 8555 struct bce_softc *sc; 8556 8557 result = -1; 8558 error = sysctl_handle_int(oidp, &result, 0, req); 8559 8560 if (error || !req->newptr) 8561 return (error); 8562 8563 if (result == 1) { 8564 sc = (struct bce_softc *)arg1; 8565 bce_dump_hw_state(sc); 8566 } 8567 8568 return error; 8569 } 8570 8571 8572 /****************************************************************************/ 8573 /* Allows the status block to be dumped through the sysctl interface. */ 8574 /* */ 8575 /* Returns: */ 8576 /* 0 for success, positive value for failure. */ 8577 /****************************************************************************/ 8578 static int 8579 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8580 { 8581 int error; 8582 int result; 8583 struct bce_softc *sc; 8584 8585 result = -1; 8586 error = sysctl_handle_int(oidp, &result, 0, req); 8587 8588 if (error || !req->newptr) 8589 return (error); 8590 8591 if (result == 1) { 8592 sc = (struct bce_softc *)arg1; 8593 bce_dump_status_block(sc); 8594 } 8595 8596 return error; 8597 } 8598 8599 8600 /****************************************************************************/ 8601 /* Allows the stats block to be dumped through the sysctl interface. */ 8602 /* */ 8603 /* Returns: */ 8604 /* 0 for success, positive value for failure. */ 8605 /****************************************************************************/ 8606 static int 8607 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8608 { 8609 int error; 8610 int result; 8611 struct bce_softc *sc; 8612 8613 result = -1; 8614 error = sysctl_handle_int(oidp, &result, 0, req); 8615 8616 if (error || !req->newptr) 8617 return (error); 8618 8619 if (result == 1) { 8620 sc = (struct bce_softc *)arg1; 8621 bce_dump_stats_block(sc); 8622 } 8623 8624 return error; 8625 } 8626 8627 8628 /****************************************************************************/ 8629 /* Allows the stat counters to be cleared without unloading/reloading the */ 8630 /* driver. */ 8631 /* */ 8632 /* Returns: */ 8633 /* 0 for success, positive value for failure. */ 8634 /****************************************************************************/ 8635 static int 8636 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8637 { 8638 int error; 8639 int result; 8640 struct bce_softc *sc; 8641 8642 result = -1; 8643 error = sysctl_handle_int(oidp, &result, 0, req); 8644 8645 if (error || !req->newptr) 8646 return (error); 8647 8648 if (result == 1) { 8649 sc = (struct bce_softc *)arg1; 8650 struct statistics_block *stats; 8651 8652 stats = (struct statistics_block *) sc->stats_block; 8653 bzero(stats, sizeof(struct statistics_block)); 8654 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8655 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8656 8657 /* Clear the internal H/W statistics counters. */ 8658 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8659 8660 /* Reset the driver maintained statistics. */ 8661 sc->interrupts_rx = 8662 sc->interrupts_tx = 0; 8663 sc->tso_frames_requested = 8664 sc->tso_frames_completed = 8665 sc->tso_frames_failed = 0; 8666 sc->rx_empty_count = 8667 sc->tx_full_count = 0; 8668 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8669 sc->tx_hi_watermark = 0; 8670 sc->l2fhdr_error_count = 8671 sc->l2fhdr_error_sim_count = 0; 8672 sc->mbuf_alloc_failed_count = 8673 sc->mbuf_alloc_failed_sim_count = 0; 8674 sc->dma_map_addr_rx_failed_count = 8675 sc->dma_map_addr_tx_failed_count = 0; 8676 sc->mbuf_frag_count = 0; 8677 sc->csum_offload_tcp_udp = 8678 sc->csum_offload_ip = 0; 8679 sc->vlan_tagged_frames_rcvd = 8680 sc->vlan_tagged_frames_stripped = 0; 8681 sc->split_header_frames_rcvd = 8682 sc->split_header_tcp_frames_rcvd = 0; 8683 8684 /* Clear firmware maintained statistics. */ 8685 REG_WR_IND(sc, 0x120084, 0); 8686 } 8687 8688 return error; 8689 } 8690 8691 8692 /****************************************************************************/ 8693 /* Allows the shared memory contents to be dumped through the sysctl . */ 8694 /* interface. */ 8695 /* */ 8696 /* Returns: */ 8697 /* 0 for success, positive value for failure. */ 8698 /****************************************************************************/ 8699 static int 8700 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8701 { 8702 int error; 8703 int result; 8704 struct bce_softc *sc; 8705 8706 result = -1; 8707 error = sysctl_handle_int(oidp, &result, 0, req); 8708 8709 if (error || !req->newptr) 8710 return (error); 8711 8712 if (result == 1) { 8713 sc = (struct bce_softc *)arg1; 8714 bce_dump_shmem_state(sc); 8715 } 8716 8717 return error; 8718 } 8719 8720 8721 /****************************************************************************/ 8722 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8723 /* */ 8724 /* Returns: */ 8725 /* 0 for success, positive value for failure. */ 8726 /****************************************************************************/ 8727 static int 8728 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8729 { 8730 int error; 8731 int result; 8732 struct bce_softc *sc; 8733 8734 result = -1; 8735 error = sysctl_handle_int(oidp, &result, 0, req); 8736 8737 if (error || !req->newptr) 8738 return (error); 8739 8740 if (result == 1) { 8741 sc = (struct bce_softc *)arg1; 8742 bce_dump_bc_state(sc); 8743 } 8744 8745 return error; 8746 } 8747 8748 8749 /****************************************************************************/ 8750 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8751 /* */ 8752 /* Returns: */ 8753 /* 0 for success, positive value for failure. */ 8754 /****************************************************************************/ 8755 static int 8756 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8757 { 8758 int error; 8759 int result; 8760 struct bce_softc *sc; 8761 8762 result = -1; 8763 error = sysctl_handle_int(oidp, &result, 0, req); 8764 8765 if (error || !req->newptr) 8766 return (error); 8767 8768 if (result == 1) { 8769 sc = (struct bce_softc *)arg1; 8770 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8771 } 8772 8773 return error; 8774 } 8775 8776 8777 /****************************************************************************/ 8778 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8779 /* */ 8780 /* Returns: */ 8781 /* 0 for success, positive value for failure. */ 8782 /****************************************************************************/ 8783 static int 8784 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8785 { 8786 int error; 8787 int result; 8788 struct bce_softc *sc; 8789 8790 result = -1; 8791 error = sysctl_handle_int(oidp, &result, 0, req); 8792 8793 if (error || !req->newptr) 8794 return (error); 8795 8796 if (result == 1) { 8797 sc = (struct bce_softc *)arg1; 8798 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8799 } 8800 8801 return error; 8802 } 8803 8804 8805 /****************************************************************************/ 8806 /* Provides a sysctl interface to allow dumping the TX chain. */ 8807 /* */ 8808 /* Returns: */ 8809 /* 0 for success, positive value for failure. */ 8810 /****************************************************************************/ 8811 static int 8812 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8813 { 8814 int error; 8815 int result; 8816 struct bce_softc *sc; 8817 8818 result = -1; 8819 error = sysctl_handle_int(oidp, &result, 0, req); 8820 8821 if (error || !req->newptr) 8822 return (error); 8823 8824 if (result == 1) { 8825 sc = (struct bce_softc *)arg1; 8826 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8827 } 8828 8829 return error; 8830 } 8831 8832 8833 /****************************************************************************/ 8834 /* Provides a sysctl interface to allow dumping the page chain. */ 8835 /* */ 8836 /* Returns: */ 8837 /* 0 for success, positive value for failure. */ 8838 /****************************************************************************/ 8839 static int 8840 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8841 { 8842 int error; 8843 int result; 8844 struct bce_softc *sc; 8845 8846 result = -1; 8847 error = sysctl_handle_int(oidp, &result, 0, req); 8848 8849 if (error || !req->newptr) 8850 return (error); 8851 8852 if (result == 1) { 8853 sc = (struct bce_softc *)arg1; 8854 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8855 } 8856 8857 return error; 8858 } 8859 8860 /****************************************************************************/ 8861 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8862 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8863 /* */ 8864 /* Returns: */ 8865 /* 0 for success, positive value for failure. */ 8866 /****************************************************************************/ 8867 static int 8868 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8869 { 8870 struct bce_softc *sc = (struct bce_softc *)arg1; 8871 int error; 8872 u32 result; 8873 u32 val[1]; 8874 u8 *data = (u8 *) val; 8875 8876 result = -1; 8877 error = sysctl_handle_int(oidp, &result, 0, req); 8878 if (error || (req->newptr == NULL)) 8879 return (error); 8880 8881 error = bce_nvram_read(sc, result, data, 4); 8882 8883 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8884 8885 return (error); 8886 } 8887 8888 8889 /****************************************************************************/ 8890 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8891 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8892 /* */ 8893 /* Returns: */ 8894 /* 0 for success, positive value for failure. */ 8895 /****************************************************************************/ 8896 static int 8897 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8898 { 8899 struct bce_softc *sc = (struct bce_softc *)arg1; 8900 int error; 8901 u32 val, result; 8902 8903 result = -1; 8904 error = sysctl_handle_int(oidp, &result, 0, req); 8905 if (error || (req->newptr == NULL)) 8906 return (error); 8907 8908 /* Make sure the register is accessible. */ 8909 if (result < 0x8000) { 8910 val = REG_RD(sc, result); 8911 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8912 } else if (result < 0x0280000) { 8913 val = REG_RD_IND(sc, result); 8914 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8915 } 8916 8917 return (error); 8918 } 8919 8920 8921 /****************************************************************************/ 8922 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8923 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8924 /* */ 8925 /* Returns: */ 8926 /* 0 for success, positive value for failure. */ 8927 /****************************************************************************/ 8928 static int 8929 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8930 { 8931 struct bce_softc *sc; 8932 device_t dev; 8933 int error, result; 8934 u16 val; 8935 8936 result = -1; 8937 error = sysctl_handle_int(oidp, &result, 0, req); 8938 if (error || (req->newptr == NULL)) 8939 return (error); 8940 8941 /* Make sure the register is accessible. */ 8942 if (result < 0x20) { 8943 sc = (struct bce_softc *)arg1; 8944 dev = sc->bce_dev; 8945 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8946 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8947 } 8948 return (error); 8949 } 8950 8951 8952 /****************************************************************************/ 8953 /* Provides a sysctl interface for dumping the nvram contents. */ 8954 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8955 /* */ 8956 /* Returns: */ 8957 /* 0 for success, positive errno for failure. */ 8958 /****************************************************************************/ 8959 static int 8960 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8961 { 8962 struct bce_softc *sc = (struct bce_softc *)arg1; 8963 int error, i; 8964 8965 if (sc->nvram_buf == NULL) 8966 sc->nvram_buf = malloc(sc->bce_flash_size, 8967 M_TEMP, M_ZERO | M_WAITOK); 8968 8969 error = 0; 8970 if (req->oldlen == sc->bce_flash_size) { 8971 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8972 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8973 } 8974 8975 if (error == 0) 8976 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8977 8978 return error; 8979 } 8980 8981 #ifdef BCE_NVRAM_WRITE_SUPPORT 8982 /****************************************************************************/ 8983 /* Provides a sysctl interface for writing to nvram. */ 8984 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8985 /* */ 8986 /* Returns: */ 8987 /* 0 for success, positive errno for failure. */ 8988 /****************************************************************************/ 8989 static int 8990 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8991 { 8992 struct bce_softc *sc = (struct bce_softc *)arg1; 8993 int error; 8994 8995 if (sc->nvram_buf == NULL) 8996 sc->nvram_buf = malloc(sc->bce_flash_size, 8997 M_TEMP, M_ZERO | M_WAITOK); 8998 else 8999 bzero(sc->nvram_buf, sc->bce_flash_size); 9000 9001 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 9002 if (error == 0) 9003 return (error); 9004 9005 if (req->newlen == sc->bce_flash_size) 9006 error = bce_nvram_write(sc, 0, sc->nvram_buf, 9007 sc->bce_flash_size); 9008 9009 9010 return error; 9011 } 9012 #endif 9013 9014 9015 /****************************************************************************/ 9016 /* Provides a sysctl interface to allow reading a CID. */ 9017 /* */ 9018 /* Returns: */ 9019 /* 0 for success, positive value for failure. */ 9020 /****************************************************************************/ 9021 static int 9022 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 9023 { 9024 struct bce_softc *sc; 9025 int error, result; 9026 9027 result = -1; 9028 error = sysctl_handle_int(oidp, &result, 0, req); 9029 if (error || (req->newptr == NULL)) 9030 return (error); 9031 9032 /* Make sure the register is accessible. */ 9033 if (result <= TX_CID) { 9034 sc = (struct bce_softc *)arg1; 9035 bce_dump_ctx(sc, result); 9036 } 9037 9038 return (error); 9039 } 9040 9041 9042 /****************************************************************************/ 9043 /* Provides a sysctl interface to forcing the driver to dump state and */ 9044 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9045 /* */ 9046 /* Returns: */ 9047 /* 0 for success, positive value for failure. */ 9048 /****************************************************************************/ 9049 static int 9050 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 9051 { 9052 int error; 9053 int result; 9054 struct bce_softc *sc; 9055 9056 result = -1; 9057 error = sysctl_handle_int(oidp, &result, 0, req); 9058 9059 if (error || !req->newptr) 9060 return (error); 9061 9062 if (result == 1) { 9063 sc = (struct bce_softc *)arg1; 9064 bce_breakpoint(sc); 9065 } 9066 9067 return error; 9068 } 9069 #endif 9070 9071 /****************************************************************************/ 9072 /* Adds any sysctl parameters for tuning or debugging purposes. */ 9073 /* */ 9074 /* Returns: */ 9075 /* 0 for success, positive value for failure. */ 9076 /****************************************************************************/ 9077 static void 9078 bce_add_sysctls(struct bce_softc *sc) 9079 { 9080 struct sysctl_ctx_list *ctx; 9081 struct sysctl_oid_list *children; 9082 9083 DBENTER(BCE_VERBOSE_MISC); 9084 9085 ctx = device_get_sysctl_ctx(sc->bce_dev); 9086 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 9087 9088 #ifdef BCE_DEBUG 9089 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9090 "l2fhdr_error_sim_control", 9091 CTLFLAG_RW, &l2fhdr_error_sim_control, 9092 0, "Debug control to force l2fhdr errors"); 9093 9094 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9095 "l2fhdr_error_sim_count", 9096 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 9097 0, "Number of simulated l2_fhdr errors"); 9098 #endif 9099 9100 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9101 "l2fhdr_error_count", 9102 CTLFLAG_RD, &sc->l2fhdr_error_count, 9103 0, "Number of l2_fhdr errors"); 9104 9105 #ifdef BCE_DEBUG 9106 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9107 "mbuf_alloc_failed_sim_control", 9108 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 9109 0, "Debug control to force mbuf allocation failures"); 9110 9111 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9112 "mbuf_alloc_failed_sim_count", 9113 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 9114 0, "Number of simulated mbuf cluster allocation failures"); 9115 #endif 9116 9117 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9118 "mbuf_alloc_failed_count", 9119 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 9120 0, "Number of mbuf allocation failures"); 9121 9122 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9123 "mbuf_frag_count", 9124 CTLFLAG_RD, &sc->mbuf_frag_count, 9125 0, "Number of fragmented mbufs"); 9126 9127 #ifdef BCE_DEBUG 9128 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9129 "dma_map_addr_failed_sim_control", 9130 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9131 0, "Debug control to force DMA mapping failures"); 9132 9133 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9134 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9135 "dma_map_addr_failed_sim_count", 9136 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9137 0, "Number of simulated DMA mapping failures"); 9138 9139 #endif 9140 9141 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9142 "dma_map_addr_rx_failed_count", 9143 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9144 0, "Number of RX DMA mapping failures"); 9145 9146 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9147 "dma_map_addr_tx_failed_count", 9148 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9149 0, "Number of TX DMA mapping failures"); 9150 9151 #ifdef BCE_DEBUG 9152 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9153 "unexpected_attention_sim_control", 9154 CTLFLAG_RW, &unexpected_attention_sim_control, 9155 0, "Debug control to simulate unexpected attentions"); 9156 9157 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9158 "unexpected_attention_sim_count", 9159 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9160 0, "Number of simulated unexpected attentions"); 9161 #endif 9162 9163 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9164 "unexpected_attention_count", 9165 CTLFLAG_RW, &sc->unexpected_attention_count, 9166 0, "Number of unexpected attentions"); 9167 9168 #ifdef BCE_DEBUG 9169 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9170 "debug_bootcode_running_failure", 9171 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9172 0, "Debug control to force bootcode running failures"); 9173 9174 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9175 "rx_low_watermark", 9176 CTLFLAG_RD, &sc->rx_low_watermark, 9177 0, "Lowest level of free rx_bd's"); 9178 9179 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9180 "rx_empty_count", 9181 CTLFLAG_RD, &sc->rx_empty_count, 9182 "Number of times the RX chain was empty"); 9183 9184 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9185 "tx_hi_watermark", 9186 CTLFLAG_RD, &sc->tx_hi_watermark, 9187 0, "Highest level of used tx_bd's"); 9188 9189 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9190 "tx_full_count", 9191 CTLFLAG_RD, &sc->tx_full_count, 9192 "Number of times the TX chain was full"); 9193 9194 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9195 "tso_frames_requested", 9196 CTLFLAG_RD, &sc->tso_frames_requested, 9197 "Number of TSO frames requested"); 9198 9199 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9200 "tso_frames_completed", 9201 CTLFLAG_RD, &sc->tso_frames_completed, 9202 "Number of TSO frames completed"); 9203 9204 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9205 "tso_frames_failed", 9206 CTLFLAG_RD, &sc->tso_frames_failed, 9207 "Number of TSO frames failed"); 9208 9209 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9210 "csum_offload_ip", 9211 CTLFLAG_RD, &sc->csum_offload_ip, 9212 "Number of IP checksum offload frames"); 9213 9214 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9215 "csum_offload_tcp_udp", 9216 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9217 "Number of TCP/UDP checksum offload frames"); 9218 9219 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9220 "vlan_tagged_frames_rcvd", 9221 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9222 "Number of VLAN tagged frames received"); 9223 9224 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9225 "vlan_tagged_frames_stripped", 9226 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9227 "Number of VLAN tagged frames stripped"); 9228 9229 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9230 "interrupts_rx", 9231 CTLFLAG_RD, &sc->interrupts_rx, 9232 "Number of RX interrupts"); 9233 9234 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9235 "interrupts_tx", 9236 CTLFLAG_RD, &sc->interrupts_tx, 9237 "Number of TX interrupts"); 9238 9239 if (bce_hdr_split == TRUE) { 9240 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9241 "split_header_frames_rcvd", 9242 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9243 "Number of split header frames received"); 9244 9245 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9246 "split_header_tcp_frames_rcvd", 9247 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9248 "Number of split header TCP frames received"); 9249 } 9250 9251 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9252 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 9253 (void *)sc, 0, 9254 bce_sysctl_nvram_dump, "S", ""); 9255 9256 #ifdef BCE_NVRAM_WRITE_SUPPORT 9257 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9258 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 9259 (void *)sc, 0, 9260 bce_sysctl_nvram_write, "S", ""); 9261 #endif 9262 #endif /* BCE_DEBUG */ 9263 9264 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9265 "stat_IfHcInOctets", 9266 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9267 "Bytes received"); 9268 9269 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9270 "stat_IfHCInBadOctets", 9271 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9272 "Bad bytes received"); 9273 9274 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9275 "stat_IfHCOutOctets", 9276 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9277 "Bytes sent"); 9278 9279 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9280 "stat_IfHCOutBadOctets", 9281 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9282 "Bad bytes sent"); 9283 9284 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9285 "stat_IfHCInUcastPkts", 9286 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9287 "Unicast packets received"); 9288 9289 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9290 "stat_IfHCInMulticastPkts", 9291 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9292 "Multicast packets received"); 9293 9294 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9295 "stat_IfHCInBroadcastPkts", 9296 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9297 "Broadcast packets received"); 9298 9299 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9300 "stat_IfHCOutUcastPkts", 9301 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9302 "Unicast packets sent"); 9303 9304 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9305 "stat_IfHCOutMulticastPkts", 9306 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9307 "Multicast packets sent"); 9308 9309 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9310 "stat_IfHCOutBroadcastPkts", 9311 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9312 "Broadcast packets sent"); 9313 9314 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9315 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9316 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9317 0, "Internal MAC transmit errors"); 9318 9319 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9320 "stat_Dot3StatsCarrierSenseErrors", 9321 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9322 0, "Carrier sense errors"); 9323 9324 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9325 "stat_Dot3StatsFCSErrors", 9326 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9327 0, "Frame check sequence errors"); 9328 9329 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9330 "stat_Dot3StatsAlignmentErrors", 9331 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9332 0, "Alignment errors"); 9333 9334 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9335 "stat_Dot3StatsSingleCollisionFrames", 9336 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9337 0, "Single Collision Frames"); 9338 9339 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9340 "stat_Dot3StatsMultipleCollisionFrames", 9341 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9342 0, "Multiple Collision Frames"); 9343 9344 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9345 "stat_Dot3StatsDeferredTransmissions", 9346 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9347 0, "Deferred Transmissions"); 9348 9349 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9350 "stat_Dot3StatsExcessiveCollisions", 9351 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9352 0, "Excessive Collisions"); 9353 9354 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9355 "stat_Dot3StatsLateCollisions", 9356 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9357 0, "Late Collisions"); 9358 9359 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9360 "stat_EtherStatsCollisions", 9361 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9362 0, "Collisions"); 9363 9364 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9365 "stat_EtherStatsFragments", 9366 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9367 0, "Fragments"); 9368 9369 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9370 "stat_EtherStatsJabbers", 9371 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9372 0, "Jabbers"); 9373 9374 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9375 "stat_EtherStatsUndersizePkts", 9376 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9377 0, "Undersize packets"); 9378 9379 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9380 "stat_EtherStatsOversizePkts", 9381 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9382 0, "stat_EtherStatsOversizePkts"); 9383 9384 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9385 "stat_EtherStatsPktsRx64Octets", 9386 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9387 0, "Bytes received in 64 byte packets"); 9388 9389 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9390 "stat_EtherStatsPktsRx65Octetsto127Octets", 9391 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9392 0, "Bytes received in 65 to 127 byte packets"); 9393 9394 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9395 "stat_EtherStatsPktsRx128Octetsto255Octets", 9396 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9397 0, "Bytes received in 128 to 255 byte packets"); 9398 9399 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9400 "stat_EtherStatsPktsRx256Octetsto511Octets", 9401 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9402 0, "Bytes received in 256 to 511 byte packets"); 9403 9404 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9405 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9406 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9407 0, "Bytes received in 512 to 1023 byte packets"); 9408 9409 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9410 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9411 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9412 0, "Bytes received in 1024 t0 1522 byte packets"); 9413 9414 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9415 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9416 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9417 0, "Bytes received in 1523 to 9022 byte packets"); 9418 9419 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9420 "stat_EtherStatsPktsTx64Octets", 9421 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9422 0, "Bytes sent in 64 byte packets"); 9423 9424 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9425 "stat_EtherStatsPktsTx65Octetsto127Octets", 9426 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9427 0, "Bytes sent in 65 to 127 byte packets"); 9428 9429 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9430 "stat_EtherStatsPktsTx128Octetsto255Octets", 9431 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9432 0, "Bytes sent in 128 to 255 byte packets"); 9433 9434 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9435 "stat_EtherStatsPktsTx256Octetsto511Octets", 9436 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9437 0, "Bytes sent in 256 to 511 byte packets"); 9438 9439 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9440 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9441 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9442 0, "Bytes sent in 512 to 1023 byte packets"); 9443 9444 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9445 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9446 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9447 0, "Bytes sent in 1024 to 1522 byte packets"); 9448 9449 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9450 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9451 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9452 0, "Bytes sent in 1523 to 9022 byte packets"); 9453 9454 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9455 "stat_XonPauseFramesReceived", 9456 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9457 0, "XON pause frames receved"); 9458 9459 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9460 "stat_XoffPauseFramesReceived", 9461 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9462 0, "XOFF pause frames received"); 9463 9464 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9465 "stat_OutXonSent", 9466 CTLFLAG_RD, &sc->stat_OutXonSent, 9467 0, "XON pause frames sent"); 9468 9469 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9470 "stat_OutXoffSent", 9471 CTLFLAG_RD, &sc->stat_OutXoffSent, 9472 0, "XOFF pause frames sent"); 9473 9474 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9475 "stat_FlowControlDone", 9476 CTLFLAG_RD, &sc->stat_FlowControlDone, 9477 0, "Flow control done"); 9478 9479 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9480 "stat_MacControlFramesReceived", 9481 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9482 0, "MAC control frames received"); 9483 9484 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9485 "stat_XoffStateEntered", 9486 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9487 0, "XOFF state entered"); 9488 9489 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9490 "stat_IfInFramesL2FilterDiscards", 9491 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9492 0, "Received L2 packets discarded"); 9493 9494 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9495 "stat_IfInRuleCheckerDiscards", 9496 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9497 0, "Received packets discarded by rule"); 9498 9499 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9500 "stat_IfInFTQDiscards", 9501 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9502 0, "Received packet FTQ discards"); 9503 9504 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9505 "stat_IfInMBUFDiscards", 9506 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9507 0, "Received packets discarded due to lack " 9508 "of controller buffer memory"); 9509 9510 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9511 "stat_IfInRuleCheckerP4Hit", 9512 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9513 0, "Received packets rule checker hits"); 9514 9515 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9516 "stat_CatchupInRuleCheckerDiscards", 9517 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9518 0, "Received packets discarded in Catchup path"); 9519 9520 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9521 "stat_CatchupInFTQDiscards", 9522 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9523 0, "Received packets discarded in FTQ in Catchup path"); 9524 9525 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9526 "stat_CatchupInMBUFDiscards", 9527 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9528 0, "Received packets discarded in controller " 9529 "buffer memory in Catchup path"); 9530 9531 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9532 "stat_CatchupInRuleCheckerP4Hit", 9533 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9534 0, "Received packets rule checker hits in Catchup path"); 9535 9536 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9537 "com_no_buffers", 9538 CTLFLAG_RD, &sc->com_no_buffers, 9539 0, "Valid packets received but no RX buffers available"); 9540 9541 #ifdef BCE_DEBUG 9542 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9543 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9544 (void *)sc, 0, 9545 bce_sysctl_driver_state, "I", "Drive state information"); 9546 9547 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9548 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9549 (void *)sc, 0, 9550 bce_sysctl_hw_state, "I", "Hardware state information"); 9551 9552 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9553 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9554 (void *)sc, 0, 9555 bce_sysctl_status_block, "I", "Dump status block"); 9556 9557 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9558 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9559 (void *)sc, 0, 9560 bce_sysctl_stats_block, "I", "Dump statistics block"); 9561 9562 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9563 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9564 (void *)sc, 0, 9565 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9566 9567 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9568 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9569 (void *)sc, 0, 9570 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9571 9572 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9573 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9574 (void *)sc, 0, 9575 bce_sysctl_bc_state, "I", "Bootcode state information"); 9576 9577 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9578 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9579 (void *)sc, 0, 9580 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9581 9582 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9583 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9584 (void *)sc, 0, 9585 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9586 9587 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9588 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9589 (void *)sc, 0, 9590 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9591 9592 if (bce_hdr_split == TRUE) { 9593 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9594 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9595 (void *)sc, 0, 9596 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9597 } 9598 9599 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9600 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9601 (void *)sc, 0, 9602 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9603 9604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9605 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9606 (void *)sc, 0, 9607 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9608 9609 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9610 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9611 (void *)sc, 0, 9612 bce_sysctl_reg_read, "I", "Register read"); 9613 9614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9615 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9616 (void *)sc, 0, 9617 bce_sysctl_nvram_read, "I", "NVRAM read"); 9618 9619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9620 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9621 (void *)sc, 0, 9622 bce_sysctl_phy_read, "I", "PHY register read"); 9623 9624 #endif 9625 9626 DBEXIT(BCE_VERBOSE_MISC); 9627 } 9628 9629 9630 /****************************************************************************/ 9631 /* BCE Debug Routines */ 9632 /****************************************************************************/ 9633 #ifdef BCE_DEBUG 9634 9635 /****************************************************************************/ 9636 /* Freezes the controller to allow for a cohesive state dump. */ 9637 /* */ 9638 /* Returns: */ 9639 /* Nothing. */ 9640 /****************************************************************************/ 9641 static __attribute__ ((noinline)) void 9642 bce_freeze_controller(struct bce_softc *sc) 9643 { 9644 u32 val; 9645 val = REG_RD(sc, BCE_MISC_COMMAND); 9646 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9647 REG_WR(sc, BCE_MISC_COMMAND, val); 9648 } 9649 9650 9651 /****************************************************************************/ 9652 /* Unfreezes the controller after a freeze operation. This may not always */ 9653 /* work and the controller will require a reset! */ 9654 /* */ 9655 /* Returns: */ 9656 /* Nothing. */ 9657 /****************************************************************************/ 9658 static __attribute__ ((noinline)) void 9659 bce_unfreeze_controller(struct bce_softc *sc) 9660 { 9661 u32 val; 9662 val = REG_RD(sc, BCE_MISC_COMMAND); 9663 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9664 REG_WR(sc, BCE_MISC_COMMAND, val); 9665 } 9666 9667 9668 /****************************************************************************/ 9669 /* Prints out Ethernet frame information from an mbuf. */ 9670 /* */ 9671 /* Partially decode an Ethernet frame to look at some important headers. */ 9672 /* */ 9673 /* Returns: */ 9674 /* Nothing. */ 9675 /****************************************************************************/ 9676 static __attribute__ ((noinline)) void 9677 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9678 { 9679 struct ether_vlan_header *eh; 9680 u16 etype; 9681 int ehlen; 9682 struct ip *ip; 9683 struct tcphdr *th; 9684 struct udphdr *uh; 9685 struct arphdr *ah; 9686 9687 BCE_PRINTF( 9688 "-----------------------------" 9689 " Frame Decode " 9690 "-----------------------------\n"); 9691 9692 eh = mtod(m, struct ether_vlan_header *); 9693 9694 /* Handle VLAN encapsulation if present. */ 9695 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9696 etype = ntohs(eh->evl_proto); 9697 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9698 } else { 9699 etype = ntohs(eh->evl_encap_proto); 9700 ehlen = ETHER_HDR_LEN; 9701 } 9702 9703 /* ToDo: Add VLAN output. */ 9704 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9705 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9706 9707 switch (etype) { 9708 case ETHERTYPE_IP: 9709 ip = (struct ip *)(m->m_data + ehlen); 9710 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9711 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9712 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9713 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9714 9715 switch (ip->ip_p) { 9716 case IPPROTO_TCP: 9717 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9718 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9719 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9720 ntohs(th->th_dport), ntohs(th->th_sport), 9721 (th->th_off << 2), th->th_flags, 9722 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9723 "\02SYN\01FIN", ntohs(th->th_sum)); 9724 break; 9725 case IPPROTO_UDP: 9726 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9727 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9728 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9729 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9730 ntohs(uh->uh_sum)); 9731 break; 9732 case IPPROTO_ICMP: 9733 BCE_PRINTF("icmp:\n"); 9734 break; 9735 default: 9736 BCE_PRINTF("----: Other IP protocol.\n"); 9737 } 9738 break; 9739 case ETHERTYPE_IPV6: 9740 BCE_PRINTF("ipv6: No decode supported.\n"); 9741 break; 9742 case ETHERTYPE_ARP: 9743 BCE_PRINTF("-arp: "); 9744 ah = (struct arphdr *) (m->m_data + ehlen); 9745 switch (ntohs(ah->ar_op)) { 9746 case ARPOP_REVREQUEST: 9747 printf("reverse ARP request\n"); 9748 break; 9749 case ARPOP_REVREPLY: 9750 printf("reverse ARP reply\n"); 9751 break; 9752 case ARPOP_REQUEST: 9753 printf("ARP request\n"); 9754 break; 9755 case ARPOP_REPLY: 9756 printf("ARP reply\n"); 9757 break; 9758 default: 9759 printf("other ARP operation\n"); 9760 } 9761 break; 9762 default: 9763 BCE_PRINTF("----: Other protocol.\n"); 9764 } 9765 9766 BCE_PRINTF( 9767 "-----------------------------" 9768 "--------------" 9769 "-----------------------------\n"); 9770 } 9771 9772 9773 /****************************************************************************/ 9774 /* Prints out information about an mbuf. */ 9775 /* */ 9776 /* Returns: */ 9777 /* Nothing. */ 9778 /****************************************************************************/ 9779 static __attribute__ ((noinline)) void 9780 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9781 { 9782 struct mbuf *mp = m; 9783 9784 if (m == NULL) { 9785 BCE_PRINTF("mbuf: null pointer\n"); 9786 return; 9787 } 9788 9789 while (mp) { 9790 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9791 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9792 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9793 9794 if (mp->m_flags & M_PKTHDR) { 9795 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9796 "csum_flags = %b\n", mp->m_pkthdr.len, 9797 mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" 9798 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9799 "\22M_PROMISC\23M_NOFREE", 9800 mp->m_pkthdr.csum_flags, 9801 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP" 9802 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9803 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9804 "\14CSUM_PSEUDO_HDR"); 9805 } 9806 9807 if (mp->m_flags & M_EXT) { 9808 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9809 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9810 switch (mp->m_ext.ext_type) { 9811 case EXT_CLUSTER: 9812 printf("EXT_CLUSTER\n"); break; 9813 case EXT_SFBUF: 9814 printf("EXT_SFBUF\n"); break; 9815 case EXT_JUMBO9: 9816 printf("EXT_JUMBO9\n"); break; 9817 case EXT_JUMBO16: 9818 printf("EXT_JUMBO16\n"); break; 9819 case EXT_PACKET: 9820 printf("EXT_PACKET\n"); break; 9821 case EXT_MBUF: 9822 printf("EXT_MBUF\n"); break; 9823 case EXT_NET_DRV: 9824 printf("EXT_NET_DRV\n"); break; 9825 case EXT_MOD_TYPE: 9826 printf("EXT_MDD_TYPE\n"); break; 9827 case EXT_DISPOSABLE: 9828 printf("EXT_DISPOSABLE\n"); break; 9829 case EXT_EXTREF: 9830 printf("EXT_EXTREF\n"); break; 9831 default: 9832 printf("UNKNOWN\n"); 9833 } 9834 } 9835 9836 mp = mp->m_next; 9837 } 9838 } 9839 9840 9841 /****************************************************************************/ 9842 /* Prints out the mbufs in the TX mbuf chain. */ 9843 /* */ 9844 /* Returns: */ 9845 /* Nothing. */ 9846 /****************************************************************************/ 9847 static __attribute__ ((noinline)) void 9848 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9849 { 9850 struct mbuf *m; 9851 9852 BCE_PRINTF( 9853 "----------------------------" 9854 " tx mbuf data " 9855 "----------------------------\n"); 9856 9857 for (int i = 0; i < count; i++) { 9858 m = sc->tx_mbuf_ptr[chain_prod]; 9859 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9860 bce_dump_mbuf(sc, m); 9861 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9862 } 9863 9864 BCE_PRINTF( 9865 "----------------------------" 9866 "----------------" 9867 "----------------------------\n"); 9868 } 9869 9870 9871 /****************************************************************************/ 9872 /* Prints out the mbufs in the RX mbuf chain. */ 9873 /* */ 9874 /* Returns: */ 9875 /* Nothing. */ 9876 /****************************************************************************/ 9877 static __attribute__ ((noinline)) void 9878 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9879 { 9880 struct mbuf *m; 9881 9882 BCE_PRINTF( 9883 "----------------------------" 9884 " rx mbuf data " 9885 "----------------------------\n"); 9886 9887 for (int i = 0; i < count; i++) { 9888 m = sc->rx_mbuf_ptr[chain_prod]; 9889 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9890 bce_dump_mbuf(sc, m); 9891 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9892 } 9893 9894 9895 BCE_PRINTF( 9896 "----------------------------" 9897 "----------------" 9898 "----------------------------\n"); 9899 } 9900 9901 9902 /****************************************************************************/ 9903 /* Prints out the mbufs in the mbuf page chain. */ 9904 /* */ 9905 /* Returns: */ 9906 /* Nothing. */ 9907 /****************************************************************************/ 9908 static __attribute__ ((noinline)) void 9909 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9910 { 9911 struct mbuf *m; 9912 9913 BCE_PRINTF( 9914 "----------------------------" 9915 " pg mbuf data " 9916 "----------------------------\n"); 9917 9918 for (int i = 0; i < count; i++) { 9919 m = sc->pg_mbuf_ptr[chain_prod]; 9920 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9921 bce_dump_mbuf(sc, m); 9922 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9923 } 9924 9925 9926 BCE_PRINTF( 9927 "----------------------------" 9928 "----------------" 9929 "----------------------------\n"); 9930 } 9931 9932 9933 /****************************************************************************/ 9934 /* Prints out a tx_bd structure. */ 9935 /* */ 9936 /* Returns: */ 9937 /* Nothing. */ 9938 /****************************************************************************/ 9939 static __attribute__ ((noinline)) void 9940 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9941 { 9942 int i = 0; 9943 9944 if (idx > MAX_TX_BD_ALLOC) 9945 /* Index out of range. */ 9946 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9947 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9948 /* TX Chain page pointer. */ 9949 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9950 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9951 txbd->tx_bd_haddr_lo); 9952 else { 9953 /* Normal tx_bd entry. */ 9954 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9955 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9956 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9957 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9958 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9959 9960 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9961 if (i>0) 9962 printf("|"); 9963 printf("CONN_FAULT"); 9964 i++; 9965 } 9966 9967 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9968 if (i>0) 9969 printf("|"); 9970 printf("TCP_UDP_CKSUM"); 9971 i++; 9972 } 9973 9974 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9975 if (i>0) 9976 printf("|"); 9977 printf("IP_CKSUM"); 9978 i++; 9979 } 9980 9981 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9982 if (i>0) 9983 printf("|"); 9984 printf("VLAN"); 9985 i++; 9986 } 9987 9988 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9989 if (i>0) 9990 printf("|"); 9991 printf("COAL_NOW"); 9992 i++; 9993 } 9994 9995 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9996 if (i>0) 9997 printf("|"); 9998 printf("DONT_GEN_CRC"); 9999 i++; 10000 } 10001 10002 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 10003 if (i>0) 10004 printf("|"); 10005 printf("START"); 10006 i++; 10007 } 10008 10009 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 10010 if (i>0) 10011 printf("|"); 10012 printf("END"); 10013 i++; 10014 } 10015 10016 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 10017 if (i>0) 10018 printf("|"); 10019 printf("LSO"); 10020 i++; 10021 } 10022 10023 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 10024 if (i>0) 10025 printf("|"); 10026 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 10027 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 10028 } 10029 10030 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 10031 if (i>0) 10032 printf("|"); 10033 printf("SW_FLAGS"); 10034 i++; 10035 } 10036 10037 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 10038 if (i>0) 10039 printf("|"); 10040 printf("SNAP)"); 10041 } else { 10042 printf(")\n"); 10043 } 10044 } 10045 } 10046 10047 10048 /****************************************************************************/ 10049 /* Prints out a rx_bd structure. */ 10050 /* */ 10051 /* Returns: */ 10052 /* Nothing. */ 10053 /****************************************************************************/ 10054 static __attribute__ ((noinline)) void 10055 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 10056 { 10057 if (idx > MAX_RX_BD_ALLOC) 10058 /* Index out of range. */ 10059 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 10060 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 10061 /* RX Chain page pointer. */ 10062 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10063 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 10064 rxbd->rx_bd_haddr_lo); 10065 else 10066 /* Normal rx_bd entry. */ 10067 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 10068 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 10069 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 10070 rxbd->rx_bd_flags); 10071 } 10072 10073 10074 /****************************************************************************/ 10075 /* Prints out a rx_bd structure in the page chain. */ 10076 /* */ 10077 /* Returns: */ 10078 /* Nothing. */ 10079 /****************************************************************************/ 10080 static __attribute__ ((noinline)) void 10081 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 10082 { 10083 if (idx > MAX_PG_BD_ALLOC) 10084 /* Index out of range. */ 10085 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 10086 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 10087 /* Page Chain page pointer. */ 10088 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 10089 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 10090 else 10091 /* Normal rx_bd entry. */ 10092 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 10093 "flags = 0x%08X\n", idx, 10094 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 10095 pgbd->rx_bd_len, pgbd->rx_bd_flags); 10096 } 10097 10098 10099 /****************************************************************************/ 10100 /* Prints out a l2_fhdr structure. */ 10101 /* */ 10102 /* Returns: */ 10103 /* Nothing. */ 10104 /****************************************************************************/ 10105 static __attribute__ ((noinline)) void 10106 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 10107 { 10108 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 10109 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 10110 "tcp_udp_xsum = 0x%04X\n", idx, 10111 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 10112 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 10113 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 10114 } 10115 10116 10117 /****************************************************************************/ 10118 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 10119 /* */ 10120 /* Returns: */ 10121 /* Nothing. */ 10122 /****************************************************************************/ 10123 static __attribute__ ((noinline)) void 10124 bce_dump_ctx(struct bce_softc *sc, u16 cid) 10125 { 10126 if (cid > TX_CID) { 10127 BCE_PRINTF(" Unknown CID\n"); 10128 return; 10129 } 10130 10131 BCE_PRINTF( 10132 "----------------------------" 10133 " CTX Data " 10134 "----------------------------\n"); 10135 10136 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 10137 10138 if (cid == RX_CID) { 10139 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 10140 "producer index\n", 10141 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10142 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10143 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10144 BCE_L2CTX_RX_HOST_BSEQ)); 10145 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10146 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10147 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10148 "descriptor address\n", 10149 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10150 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10151 "descriptor address\n", 10152 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10153 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10154 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10155 BCE_L2CTX_RX_NX_BDIDX)); 10156 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10157 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10158 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10159 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10160 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10161 BCE_L2CTX_RX_PG_BUF_SIZE)); 10162 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10163 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10164 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10165 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10166 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10167 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10168 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10169 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10170 BCE_L2CTX_RX_NX_PG_BDIDX)); 10171 } else if (cid == TX_CID) { 10172 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10173 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10174 CTX_RD(sc, GET_CID_ADDR(cid), 10175 BCE_L2CTX_TX_TYPE_XI)); 10176 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10177 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10178 BCE_L2CTX_TX_CMD_TYPE_XI)); 10179 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10180 "h/w buffer descriptor address\n", 10181 CTX_RD(sc, GET_CID_ADDR(cid), 10182 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10183 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10184 "h/w buffer descriptor address\n", 10185 CTX_RD(sc, GET_CID_ADDR(cid), 10186 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10187 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10188 "host producer index\n", 10189 CTX_RD(sc, GET_CID_ADDR(cid), 10190 BCE_L2CTX_TX_HOST_BIDX_XI)); 10191 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10192 "host byte sequence\n", 10193 CTX_RD(sc, GET_CID_ADDR(cid), 10194 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10195 } else { 10196 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10197 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10198 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10199 CTX_RD(sc, GET_CID_ADDR(cid), 10200 BCE_L2CTX_TX_CMD_TYPE)); 10201 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10202 "h/w buffer descriptor address\n", 10203 CTX_RD(sc, GET_CID_ADDR(cid), 10204 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10205 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10206 "h/w buffer descriptor address\n", 10207 CTX_RD(sc, GET_CID_ADDR(cid), 10208 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10209 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10210 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10211 BCE_L2CTX_TX_HOST_BIDX)); 10212 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10213 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10214 BCE_L2CTX_TX_HOST_BSEQ)); 10215 } 10216 } 10217 10218 BCE_PRINTF( 10219 "----------------------------" 10220 " Raw CTX " 10221 "----------------------------\n"); 10222 10223 for (int i = 0x0; i < 0x300; i += 0x10) { 10224 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10225 CTX_RD(sc, GET_CID_ADDR(cid), i), 10226 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10227 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10228 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10229 } 10230 10231 10232 BCE_PRINTF( 10233 "----------------------------" 10234 "----------------" 10235 "----------------------------\n"); 10236 } 10237 10238 10239 /****************************************************************************/ 10240 /* Prints out the FTQ data. */ 10241 /* */ 10242 /* Returns: */ 10243 /* Nothing. */ 10244 /****************************************************************************/ 10245 static __attribute__ ((noinline)) void 10246 bce_dump_ftqs(struct bce_softc *sc) 10247 { 10248 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10249 10250 BCE_PRINTF( 10251 "----------------------------" 10252 " FTQ Data " 10253 "----------------------------\n"); 10254 10255 BCE_PRINTF(" FTQ Command Control Depth_Now " 10256 "Max_Depth Valid_Cnt \n"); 10257 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10258 "---------- ----------\n"); 10259 10260 /* Setup the generic statistic counters for the FTQ valid count. */ 10261 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10262 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10263 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10264 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10265 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10266 10267 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10268 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10269 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10270 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10271 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10272 10273 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10274 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10275 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10276 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10277 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10278 10279 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10280 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10281 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10282 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10283 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10284 10285 /* Input queue to the Receive Lookup state machine */ 10286 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10287 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10288 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10289 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10290 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10291 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10292 cmd, ctl, cur_depth, max_depth, valid_cnt); 10293 10294 /* Input queue to the Receive Processor */ 10295 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10296 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10297 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10298 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10299 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10300 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10301 cmd, ctl, cur_depth, max_depth, valid_cnt); 10302 10303 /* Input queue to the Recevie Processor */ 10304 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10305 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10306 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10307 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10308 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10309 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10310 cmd, ctl, cur_depth, max_depth, valid_cnt); 10311 10312 /* Input queue to the Receive Virtual to Physical state machine */ 10313 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10314 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10315 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10316 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10317 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10318 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10319 cmd, ctl, cur_depth, max_depth, valid_cnt); 10320 10321 /* Input queue to the Recevie Virtual to Physical state machine */ 10322 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10323 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10324 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10325 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10326 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10327 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10328 cmd, ctl, cur_depth, max_depth, valid_cnt); 10329 10330 /* Input queue to the Receive Virtual to Physical state machine */ 10331 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10332 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10333 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10334 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10335 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10336 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10337 cmd, ctl, cur_depth, max_depth, valid_cnt); 10338 10339 /* Input queue to the Receive DMA state machine */ 10340 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10341 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10342 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10343 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10344 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10345 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10346 cmd, ctl, cur_depth, max_depth, valid_cnt); 10347 10348 /* Input queue to the Transmit Scheduler state machine */ 10349 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10350 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10351 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10352 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10353 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10354 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10355 cmd, ctl, cur_depth, max_depth, valid_cnt); 10356 10357 /* Input queue to the Transmit Buffer Descriptor state machine */ 10358 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10359 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10360 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10361 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10362 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10363 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10364 cmd, ctl, cur_depth, max_depth, valid_cnt); 10365 10366 /* Input queue to the Transmit Processor */ 10367 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10368 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10369 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10370 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10371 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10372 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10373 cmd, ctl, cur_depth, max_depth, valid_cnt); 10374 10375 /* Input queue to the Transmit DMA state machine */ 10376 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10377 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10378 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10379 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10380 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10381 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10382 cmd, ctl, cur_depth, max_depth, valid_cnt); 10383 10384 /* Input queue to the Transmit Patch-Up Processor */ 10385 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10386 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10387 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10388 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10389 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10390 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10391 cmd, ctl, cur_depth, max_depth, valid_cnt); 10392 10393 /* Input queue to the Transmit Assembler state machine */ 10394 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10395 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10396 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10397 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10398 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10399 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10400 cmd, ctl, cur_depth, max_depth, valid_cnt); 10401 10402 /* Input queue to the Completion Processor */ 10403 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10404 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10405 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10406 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10407 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10408 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10409 cmd, ctl, cur_depth, max_depth, valid_cnt); 10410 10411 /* Input queue to the Completion Processor */ 10412 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10413 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10414 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10415 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10416 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10417 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10418 cmd, ctl, cur_depth, max_depth, valid_cnt); 10419 10420 /* Input queue to the Completion Processor */ 10421 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10422 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10423 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10424 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10425 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10426 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10427 cmd, ctl, cur_depth, max_depth, valid_cnt); 10428 10429 /* Setup the generic statistic counters for the FTQ valid count. */ 10430 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10431 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10432 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10433 10434 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10435 val = val | 10436 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10437 24); 10438 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10439 10440 /* Input queue to the Management Control Processor */ 10441 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10442 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10443 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10444 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10445 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10446 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10447 cmd, ctl, cur_depth, max_depth, valid_cnt); 10448 10449 /* Input queue to the Command Processor */ 10450 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10451 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10452 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10453 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10454 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10455 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10456 cmd, ctl, cur_depth, max_depth, valid_cnt); 10457 10458 /* Input queue to the Completion Scheduler state machine */ 10459 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10460 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10461 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10462 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10463 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10464 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10465 cmd, ctl, cur_depth, max_depth, valid_cnt); 10466 10467 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10468 /* Input queue to the RV2P Command Scheduler */ 10469 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10470 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10471 cur_depth = (ctl & 0xFFC00000) >> 22; 10472 max_depth = (ctl & 0x003FF000) >> 12; 10473 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10474 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10475 cmd, ctl, cur_depth, max_depth, valid_cnt); 10476 } 10477 10478 BCE_PRINTF( 10479 "----------------------------" 10480 "----------------" 10481 "----------------------------\n"); 10482 } 10483 10484 10485 /****************************************************************************/ 10486 /* Prints out the TX chain. */ 10487 /* */ 10488 /* Returns: */ 10489 /* Nothing. */ 10490 /****************************************************************************/ 10491 static __attribute__ ((noinline)) void 10492 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10493 { 10494 struct tx_bd *txbd; 10495 10496 /* First some info about the tx_bd chain structure. */ 10497 BCE_PRINTF( 10498 "----------------------------" 10499 " tx_bd chain " 10500 "----------------------------\n"); 10501 10502 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10503 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10504 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10505 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10506 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10507 10508 BCE_PRINTF( 10509 "----------------------------" 10510 " tx_bd data " 10511 "----------------------------\n"); 10512 10513 /* Now print out a decoded list of TX buffer descriptors. */ 10514 for (int i = 0; i < count; i++) { 10515 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10516 bce_dump_txbd(sc, tx_prod, txbd); 10517 tx_prod++; 10518 } 10519 10520 BCE_PRINTF( 10521 "----------------------------" 10522 "----------------" 10523 "----------------------------\n"); 10524 } 10525 10526 10527 /****************************************************************************/ 10528 /* Prints out the RX chain. */ 10529 /* */ 10530 /* Returns: */ 10531 /* Nothing. */ 10532 /****************************************************************************/ 10533 static __attribute__ ((noinline)) void 10534 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10535 { 10536 struct rx_bd *rxbd; 10537 10538 /* First some info about the rx_bd chain structure. */ 10539 BCE_PRINTF( 10540 "----------------------------" 10541 " rx_bd chain " 10542 "----------------------------\n"); 10543 10544 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10545 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10546 10547 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10548 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10549 10550 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10551 10552 BCE_PRINTF( 10553 "----------------------------" 10554 " rx_bd data " 10555 "----------------------------\n"); 10556 10557 /* Now print out the rx_bd's themselves. */ 10558 for (int i = 0; i < count; i++) { 10559 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10560 bce_dump_rxbd(sc, rx_prod, rxbd); 10561 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10562 } 10563 10564 BCE_PRINTF( 10565 "----------------------------" 10566 "----------------" 10567 "----------------------------\n"); 10568 } 10569 10570 10571 /****************************************************************************/ 10572 /* Prints out the page chain. */ 10573 /* */ 10574 /* Returns: */ 10575 /* Nothing. */ 10576 /****************************************************************************/ 10577 static __attribute__ ((noinline)) void 10578 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10579 { 10580 struct rx_bd *pgbd; 10581 10582 /* First some info about the page chain structure. */ 10583 BCE_PRINTF( 10584 "----------------------------" 10585 " page chain " 10586 "----------------------------\n"); 10587 10588 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10589 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10590 10591 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10592 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10593 10594 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10595 10596 BCE_PRINTF( 10597 "----------------------------" 10598 " page data " 10599 "----------------------------\n"); 10600 10601 /* Now print out the rx_bd's themselves. */ 10602 for (int i = 0; i < count; i++) { 10603 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10604 bce_dump_pgbd(sc, pg_prod, pgbd); 10605 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10606 } 10607 10608 BCE_PRINTF( 10609 "----------------------------" 10610 "----------------" 10611 "----------------------------\n"); 10612 } 10613 10614 10615 #define BCE_PRINT_RX_CONS(arg) \ 10616 if (sblk->status_rx_quick_consumer_index##arg) \ 10617 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10618 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10619 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10620 arg); 10621 10622 10623 #define BCE_PRINT_TX_CONS(arg) \ 10624 if (sblk->status_tx_quick_consumer_index##arg) \ 10625 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10626 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10627 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10628 arg); 10629 10630 /****************************************************************************/ 10631 /* Prints out the status block from host memory. */ 10632 /* */ 10633 /* Returns: */ 10634 /* Nothing. */ 10635 /****************************************************************************/ 10636 static __attribute__ ((noinline)) void 10637 bce_dump_status_block(struct bce_softc *sc) 10638 { 10639 struct status_block *sblk; 10640 10641 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10642 10643 sblk = sc->status_block; 10644 10645 BCE_PRINTF( 10646 "----------------------------" 10647 " Status Block " 10648 "----------------------------\n"); 10649 10650 /* Theses indices are used for normal L2 drivers. */ 10651 BCE_PRINTF(" 0x%08X - attn_bits\n", 10652 sblk->status_attn_bits); 10653 10654 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10655 sblk->status_attn_bits_ack); 10656 10657 BCE_PRINT_RX_CONS(0); 10658 BCE_PRINT_TX_CONS(0) 10659 10660 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10661 10662 /* Theses indices are not used for normal L2 drivers. */ 10663 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10664 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10665 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10666 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10667 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10668 10669 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10670 10671 if (sblk->status_completion_producer_index || 10672 sblk->status_cmd_consumer_index) 10673 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10674 sblk->status_completion_producer_index, 10675 sblk->status_cmd_consumer_index); 10676 10677 BCE_PRINTF( 10678 "----------------------------" 10679 "----------------" 10680 "----------------------------\n"); 10681 } 10682 10683 10684 #define BCE_PRINT_64BIT_STAT(arg) \ 10685 if (sblk->arg##_lo || sblk->arg##_hi) \ 10686 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10687 sblk->arg##_lo, #arg); 10688 10689 #define BCE_PRINT_32BIT_STAT(arg) \ 10690 if (sblk->arg) \ 10691 BCE_PRINTF(" 0x%08X : %s\n", \ 10692 sblk->arg, #arg); 10693 10694 /****************************************************************************/ 10695 /* Prints out the statistics block from host memory. */ 10696 /* */ 10697 /* Returns: */ 10698 /* Nothing. */ 10699 /****************************************************************************/ 10700 static __attribute__ ((noinline)) void 10701 bce_dump_stats_block(struct bce_softc *sc) 10702 { 10703 struct statistics_block *sblk; 10704 10705 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10706 10707 sblk = sc->stats_block; 10708 10709 BCE_PRINTF( 10710 "---------------" 10711 " Stats Block (All Stats Not Shown Are 0) " 10712 "---------------\n"); 10713 10714 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10715 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10716 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10717 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10718 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10719 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10720 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10721 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10722 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10723 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10724 BCE_PRINT_32BIT_STAT( 10725 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10726 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10727 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10728 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10729 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10730 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10731 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10732 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10733 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10734 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10735 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10736 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10737 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10738 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10739 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10740 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10741 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10742 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10743 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10744 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10745 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10746 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10747 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10748 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10749 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10750 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10751 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10752 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10753 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10754 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10755 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10756 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10757 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10758 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10759 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10760 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10761 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10762 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10763 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10764 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10765 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10766 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10767 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10768 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10769 10770 BCE_PRINTF( 10771 "----------------------------" 10772 "----------------" 10773 "----------------------------\n"); 10774 } 10775 10776 10777 /****************************************************************************/ 10778 /* Prints out a summary of the driver state. */ 10779 /* */ 10780 /* Returns: */ 10781 /* Nothing. */ 10782 /****************************************************************************/ 10783 static __attribute__ ((noinline)) void 10784 bce_dump_driver_state(struct bce_softc *sc) 10785 { 10786 u32 val_hi, val_lo; 10787 10788 BCE_PRINTF( 10789 "-----------------------------" 10790 " Driver State " 10791 "-----------------------------\n"); 10792 10793 val_hi = BCE_ADDR_HI(sc); 10794 val_lo = BCE_ADDR_LO(sc); 10795 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10796 "address\n", val_hi, val_lo); 10797 10798 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10799 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10800 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10801 "address\n", val_hi, val_lo); 10802 10803 val_hi = BCE_ADDR_HI(sc->status_block); 10804 val_lo = BCE_ADDR_LO(sc->status_block); 10805 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10806 "virtual address\n", val_hi, val_lo); 10807 10808 val_hi = BCE_ADDR_HI(sc->stats_block); 10809 val_lo = BCE_ADDR_LO(sc->stats_block); 10810 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10811 "virtual address\n", val_hi, val_lo); 10812 10813 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10814 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10815 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10816 "virtual adddress\n", val_hi, val_lo); 10817 10818 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10819 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10820 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10821 "virtual address\n", val_hi, val_lo); 10822 10823 if (bce_hdr_split == TRUE) { 10824 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10825 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10826 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10827 "virtual address\n", val_hi, val_lo); 10828 } 10829 10830 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10831 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10832 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10833 "virtual address\n", val_hi, val_lo); 10834 10835 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10836 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10837 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10838 "virtual address\n", val_hi, val_lo); 10839 10840 if (bce_hdr_split == TRUE) { 10841 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10842 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10843 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10844 "virtual address\n", val_hi, val_lo); 10845 } 10846 10847 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10848 "h/w intrs\n", 10849 (long long unsigned int) sc->interrupts_generated); 10850 10851 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10852 "rx interrupts handled\n", 10853 (long long unsigned int) sc->interrupts_rx); 10854 10855 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10856 "tx interrupts handled\n", 10857 (long long unsigned int) sc->interrupts_tx); 10858 10859 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10860 "phy interrupts handled\n", 10861 (long long unsigned int) sc->phy_interrupts); 10862 10863 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10864 "status block index\n", sc->last_status_idx); 10865 10866 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10867 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10868 10869 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10870 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10871 10872 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10873 "byte seq index\n", sc->tx_prod_bseq); 10874 10875 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10876 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10877 10878 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10879 "tx_bd's\n", sc->used_tx_bd); 10880 10881 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10882 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10883 10884 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10885 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10886 10887 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10888 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10889 10890 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10891 "byte seq index\n", sc->rx_prod_bseq); 10892 10893 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10894 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10895 10896 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10897 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10898 10899 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10900 "rx_bd's\n", sc->free_rx_bd); 10901 10902 if (bce_hdr_split == TRUE) { 10903 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10904 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10905 10906 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10907 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10908 10909 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10910 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10911 } 10912 10913 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10914 "rx_bd's\n", sc->free_pg_bd); 10915 10916 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10917 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10918 10919 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10920 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10921 10922 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10923 "bce mac flags\n", sc->bce_flags); 10924 10925 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10926 "bce phy flags\n", sc->bce_phy_flags); 10927 10928 BCE_PRINTF( 10929 "----------------------------" 10930 "----------------" 10931 "----------------------------\n"); 10932 } 10933 10934 10935 /****************************************************************************/ 10936 /* Prints out the hardware state through a summary of important register, */ 10937 /* followed by a complete register dump. */ 10938 /* */ 10939 /* Returns: */ 10940 /* Nothing. */ 10941 /****************************************************************************/ 10942 static __attribute__ ((noinline)) void 10943 bce_dump_hw_state(struct bce_softc *sc) 10944 { 10945 u32 val; 10946 10947 BCE_PRINTF( 10948 "----------------------------" 10949 " Hardware State " 10950 "----------------------------\n"); 10951 10952 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10953 10954 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10955 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10956 val, BCE_MISC_ENABLE_STATUS_BITS); 10957 10958 val = REG_RD(sc, BCE_DMA_STATUS); 10959 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10960 val, BCE_DMA_STATUS); 10961 10962 val = REG_RD(sc, BCE_CTX_STATUS); 10963 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10964 val, BCE_CTX_STATUS); 10965 10966 val = REG_RD(sc, BCE_EMAC_STATUS); 10967 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10968 val, BCE_EMAC_STATUS); 10969 10970 val = REG_RD(sc, BCE_RPM_STATUS); 10971 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10972 val, BCE_RPM_STATUS); 10973 10974 /* ToDo: Create a #define for this constant. */ 10975 val = REG_RD(sc, 0x2004); 10976 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10977 val, 0x2004); 10978 10979 val = REG_RD(sc, BCE_RV2P_STATUS); 10980 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10981 val, BCE_RV2P_STATUS); 10982 10983 /* ToDo: Create a #define for this constant. */ 10984 val = REG_RD(sc, 0x2c04); 10985 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10986 val, 0x2c04); 10987 10988 val = REG_RD(sc, BCE_TBDR_STATUS); 10989 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10990 val, BCE_TBDR_STATUS); 10991 10992 val = REG_RD(sc, BCE_TDMA_STATUS); 10993 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10994 val, BCE_TDMA_STATUS); 10995 10996 val = REG_RD(sc, BCE_HC_STATUS); 10997 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10998 val, BCE_HC_STATUS); 10999 11000 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11001 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11002 val, BCE_TXP_CPU_STATE); 11003 11004 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11005 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11006 val, BCE_TPAT_CPU_STATE); 11007 11008 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11009 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11010 val, BCE_RXP_CPU_STATE); 11011 11012 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11013 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11014 val, BCE_COM_CPU_STATE); 11015 11016 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 11017 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 11018 val, BCE_MCP_CPU_STATE); 11019 11020 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11021 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11022 val, BCE_CP_CPU_STATE); 11023 11024 BCE_PRINTF( 11025 "----------------------------" 11026 "----------------" 11027 "----------------------------\n"); 11028 11029 BCE_PRINTF( 11030 "----------------------------" 11031 " Register Dump " 11032 "----------------------------\n"); 11033 11034 for (int i = 0x400; i < 0x8000; i += 0x10) { 11035 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11036 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11037 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11038 } 11039 11040 BCE_PRINTF( 11041 "----------------------------" 11042 "----------------" 11043 "----------------------------\n"); 11044 } 11045 11046 11047 /****************************************************************************/ 11048 /* Prints out the contentst of shared memory which is used for host driver */ 11049 /* to bootcode firmware communication. */ 11050 /* */ 11051 /* Returns: */ 11052 /* Nothing. */ 11053 /****************************************************************************/ 11054 static __attribute__ ((noinline)) void 11055 bce_dump_shmem_state(struct bce_softc *sc) 11056 { 11057 BCE_PRINTF( 11058 "----------------------------" 11059 " Hardware State " 11060 "----------------------------\n"); 11061 11062 BCE_PRINTF("0x%08X - Shared memory base address\n", 11063 sc->bce_shmem_base); 11064 BCE_PRINTF("%s - bootcode version\n", 11065 sc->bce_bc_ver); 11066 11067 BCE_PRINTF( 11068 "----------------------------" 11069 " Shared Mem " 11070 "----------------------------\n"); 11071 11072 for (int i = 0x0; i < 0x200; i += 0x10) { 11073 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11074 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 11075 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 11076 } 11077 11078 BCE_PRINTF( 11079 "----------------------------" 11080 "----------------" 11081 "----------------------------\n"); 11082 } 11083 11084 11085 /****************************************************************************/ 11086 /* Prints out the mailbox queue registers. */ 11087 /* */ 11088 /* Returns: */ 11089 /* Nothing. */ 11090 /****************************************************************************/ 11091 static __attribute__ ((noinline)) void 11092 bce_dump_mq_regs(struct bce_softc *sc) 11093 { 11094 BCE_PRINTF( 11095 "----------------------------" 11096 " MQ Regs " 11097 "----------------------------\n"); 11098 11099 BCE_PRINTF( 11100 "----------------------------" 11101 "----------------" 11102 "----------------------------\n"); 11103 11104 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 11105 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11106 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11107 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11108 } 11109 11110 BCE_PRINTF( 11111 "----------------------------" 11112 "----------------" 11113 "----------------------------\n"); 11114 } 11115 11116 11117 /****************************************************************************/ 11118 /* Prints out the bootcode state. */ 11119 /* */ 11120 /* Returns: */ 11121 /* Nothing. */ 11122 /****************************************************************************/ 11123 static __attribute__ ((noinline)) void 11124 bce_dump_bc_state(struct bce_softc *sc) 11125 { 11126 u32 val; 11127 11128 BCE_PRINTF( 11129 "----------------------------" 11130 " Bootcode State " 11131 "----------------------------\n"); 11132 11133 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11134 11135 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 11136 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 11137 val, BCE_BC_RESET_TYPE); 11138 11139 val = bce_shmem_rd(sc, BCE_BC_STATE); 11140 BCE_PRINTF("0x%08X - (0x%06X) state\n", 11141 val, BCE_BC_STATE); 11142 11143 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 11144 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 11145 val, BCE_BC_STATE_CONDITION); 11146 11147 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 11148 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 11149 val, BCE_BC_STATE_DEBUG_CMD); 11150 11151 BCE_PRINTF( 11152 "----------------------------" 11153 "----------------" 11154 "----------------------------\n"); 11155 } 11156 11157 11158 /****************************************************************************/ 11159 /* Prints out the TXP processor state. */ 11160 /* */ 11161 /* Returns: */ 11162 /* Nothing. */ 11163 /****************************************************************************/ 11164 static __attribute__ ((noinline)) void 11165 bce_dump_txp_state(struct bce_softc *sc, int regs) 11166 { 11167 u32 val; 11168 u32 fw_version[3]; 11169 11170 BCE_PRINTF( 11171 "----------------------------" 11172 " TXP State " 11173 "----------------------------\n"); 11174 11175 for (int i = 0; i < 3; i++) 11176 fw_version[i] = htonl(REG_RD_IND(sc, 11177 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11178 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11179 11180 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11181 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11182 val, BCE_TXP_CPU_MODE); 11183 11184 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11185 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11186 val, BCE_TXP_CPU_STATE); 11187 11188 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11189 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11190 val, BCE_TXP_CPU_EVENT_MASK); 11191 11192 if (regs) { 11193 BCE_PRINTF( 11194 "----------------------------" 11195 " Register Dump " 11196 "----------------------------\n"); 11197 11198 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11199 /* Skip the big blank spaces */ 11200 if (i < 0x454000 && i > 0x5ffff) 11201 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11202 "0x%08X 0x%08X\n", i, 11203 REG_RD_IND(sc, i), 11204 REG_RD_IND(sc, i + 0x4), 11205 REG_RD_IND(sc, i + 0x8), 11206 REG_RD_IND(sc, i + 0xC)); 11207 } 11208 } 11209 11210 BCE_PRINTF( 11211 "----------------------------" 11212 "----------------" 11213 "----------------------------\n"); 11214 } 11215 11216 11217 /****************************************************************************/ 11218 /* Prints out the RXP processor state. */ 11219 /* */ 11220 /* Returns: */ 11221 /* Nothing. */ 11222 /****************************************************************************/ 11223 static __attribute__ ((noinline)) void 11224 bce_dump_rxp_state(struct bce_softc *sc, int regs) 11225 { 11226 u32 val; 11227 u32 fw_version[3]; 11228 11229 BCE_PRINTF( 11230 "----------------------------" 11231 " RXP State " 11232 "----------------------------\n"); 11233 11234 for (int i = 0; i < 3; i++) 11235 fw_version[i] = htonl(REG_RD_IND(sc, 11236 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11237 11238 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11239 11240 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11241 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11242 val, BCE_RXP_CPU_MODE); 11243 11244 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11245 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11246 val, BCE_RXP_CPU_STATE); 11247 11248 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11249 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11250 val, BCE_RXP_CPU_EVENT_MASK); 11251 11252 if (regs) { 11253 BCE_PRINTF( 11254 "----------------------------" 11255 " Register Dump " 11256 "----------------------------\n"); 11257 11258 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11259 /* Skip the big blank sapces */ 11260 if (i < 0xc5400 && i > 0xdffff) 11261 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11262 "0x%08X 0x%08X\n", i, 11263 REG_RD_IND(sc, i), 11264 REG_RD_IND(sc, i + 0x4), 11265 REG_RD_IND(sc, i + 0x8), 11266 REG_RD_IND(sc, i + 0xC)); 11267 } 11268 } 11269 11270 BCE_PRINTF( 11271 "----------------------------" 11272 "----------------" 11273 "----------------------------\n"); 11274 } 11275 11276 11277 /****************************************************************************/ 11278 /* Prints out the TPAT processor state. */ 11279 /* */ 11280 /* Returns: */ 11281 /* Nothing. */ 11282 /****************************************************************************/ 11283 static __attribute__ ((noinline)) void 11284 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11285 { 11286 u32 val; 11287 u32 fw_version[3]; 11288 11289 BCE_PRINTF( 11290 "----------------------------" 11291 " TPAT State " 11292 "----------------------------\n"); 11293 11294 for (int i = 0; i < 3; i++) 11295 fw_version[i] = htonl(REG_RD_IND(sc, 11296 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11297 11298 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11299 11300 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11301 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11302 val, BCE_TPAT_CPU_MODE); 11303 11304 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11305 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11306 val, BCE_TPAT_CPU_STATE); 11307 11308 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11309 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11310 val, BCE_TPAT_CPU_EVENT_MASK); 11311 11312 if (regs) { 11313 BCE_PRINTF( 11314 "----------------------------" 11315 " Register Dump " 11316 "----------------------------\n"); 11317 11318 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11319 /* Skip the big blank spaces */ 11320 if (i < 0x854000 && i > 0x9ffff) 11321 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11322 "0x%08X 0x%08X\n", i, 11323 REG_RD_IND(sc, i), 11324 REG_RD_IND(sc, i + 0x4), 11325 REG_RD_IND(sc, i + 0x8), 11326 REG_RD_IND(sc, i + 0xC)); 11327 } 11328 } 11329 11330 BCE_PRINTF( 11331 "----------------------------" 11332 "----------------" 11333 "----------------------------\n"); 11334 } 11335 11336 11337 /****************************************************************************/ 11338 /* Prints out the Command Procesor (CP) state. */ 11339 /* */ 11340 /* Returns: */ 11341 /* Nothing. */ 11342 /****************************************************************************/ 11343 static __attribute__ ((noinline)) void 11344 bce_dump_cp_state(struct bce_softc *sc, int regs) 11345 { 11346 u32 val; 11347 u32 fw_version[3]; 11348 11349 BCE_PRINTF( 11350 "----------------------------" 11351 " CP State " 11352 "----------------------------\n"); 11353 11354 for (int i = 0; i < 3; i++) 11355 fw_version[i] = htonl(REG_RD_IND(sc, 11356 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11357 11358 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11359 11360 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11361 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11362 val, BCE_CP_CPU_MODE); 11363 11364 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11365 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11366 val, BCE_CP_CPU_STATE); 11367 11368 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11369 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11370 BCE_CP_CPU_EVENT_MASK); 11371 11372 if (regs) { 11373 BCE_PRINTF( 11374 "----------------------------" 11375 " Register Dump " 11376 "----------------------------\n"); 11377 11378 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11379 /* Skip the big blank spaces */ 11380 if (i < 0x185400 && i > 0x19ffff) 11381 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11382 "0x%08X 0x%08X\n", i, 11383 REG_RD_IND(sc, i), 11384 REG_RD_IND(sc, i + 0x4), 11385 REG_RD_IND(sc, i + 0x8), 11386 REG_RD_IND(sc, i + 0xC)); 11387 } 11388 } 11389 11390 BCE_PRINTF( 11391 "----------------------------" 11392 "----------------" 11393 "----------------------------\n"); 11394 } 11395 11396 11397 /****************************************************************************/ 11398 /* Prints out the Completion Procesor (COM) state. */ 11399 /* */ 11400 /* Returns: */ 11401 /* Nothing. */ 11402 /****************************************************************************/ 11403 static __attribute__ ((noinline)) void 11404 bce_dump_com_state(struct bce_softc *sc, int regs) 11405 { 11406 u32 val; 11407 u32 fw_version[4]; 11408 11409 BCE_PRINTF( 11410 "----------------------------" 11411 " COM State " 11412 "----------------------------\n"); 11413 11414 for (int i = 0; i < 3; i++) 11415 fw_version[i] = htonl(REG_RD_IND(sc, 11416 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11417 11418 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11419 11420 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11421 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11422 val, BCE_COM_CPU_MODE); 11423 11424 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11425 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11426 val, BCE_COM_CPU_STATE); 11427 11428 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11429 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11430 BCE_COM_CPU_EVENT_MASK); 11431 11432 if (regs) { 11433 BCE_PRINTF( 11434 "----------------------------" 11435 " Register Dump " 11436 "----------------------------\n"); 11437 11438 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11439 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11440 "0x%08X 0x%08X\n", i, 11441 REG_RD_IND(sc, i), 11442 REG_RD_IND(sc, i + 0x4), 11443 REG_RD_IND(sc, i + 0x8), 11444 REG_RD_IND(sc, i + 0xC)); 11445 } 11446 } 11447 11448 BCE_PRINTF( 11449 "----------------------------" 11450 "----------------" 11451 "----------------------------\n"); 11452 } 11453 11454 11455 /****************************************************************************/ 11456 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11457 /* */ 11458 /* Returns: */ 11459 /* Nothing. */ 11460 /****************************************************************************/ 11461 static __attribute__ ((noinline)) void 11462 bce_dump_rv2p_state(struct bce_softc *sc) 11463 { 11464 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11465 11466 BCE_PRINTF( 11467 "----------------------------" 11468 " RV2P State " 11469 "----------------------------\n"); 11470 11471 /* Stall the RV2P processors. */ 11472 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11473 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11474 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11475 11476 /* Read the firmware version. */ 11477 val = 0x00000001; 11478 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11479 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11480 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11481 BCE_RV2P_INSTR_HIGH_HIGH; 11482 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11483 fw_ver_high, fw_ver_low); 11484 11485 val = 0x00000001; 11486 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11487 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11488 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11489 BCE_RV2P_INSTR_HIGH_HIGH; 11490 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11491 fw_ver_high, fw_ver_low); 11492 11493 /* Resume the RV2P processors. */ 11494 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11495 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11496 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11497 11498 /* Fetch the program counter value. */ 11499 val = 0x68007800; 11500 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11501 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11502 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11503 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11504 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11505 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11506 11507 /* Fetch the program counter value again to see if it is advancing. */ 11508 val = 0x68007800; 11509 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11510 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11511 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11512 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11513 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11514 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11515 11516 BCE_PRINTF( 11517 "----------------------------" 11518 "----------------" 11519 "----------------------------\n"); 11520 } 11521 11522 11523 /****************************************************************************/ 11524 /* Prints out the driver state and then enters the debugger. */ 11525 /* */ 11526 /* Returns: */ 11527 /* Nothing. */ 11528 /****************************************************************************/ 11529 static __attribute__ ((noinline)) void 11530 bce_breakpoint(struct bce_softc *sc) 11531 { 11532 11533 /* 11534 * Unreachable code to silence compiler warnings 11535 * about unused functions. 11536 */ 11537 if (0) { 11538 bce_freeze_controller(sc); 11539 bce_unfreeze_controller(sc); 11540 bce_dump_enet(sc, NULL); 11541 bce_dump_txbd(sc, 0, NULL); 11542 bce_dump_rxbd(sc, 0, NULL); 11543 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11544 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11545 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11546 bce_dump_l2fhdr(sc, 0, NULL); 11547 bce_dump_ctx(sc, RX_CID); 11548 bce_dump_ftqs(sc); 11549 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11550 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11551 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11552 bce_dump_status_block(sc); 11553 bce_dump_stats_block(sc); 11554 bce_dump_driver_state(sc); 11555 bce_dump_hw_state(sc); 11556 bce_dump_bc_state(sc); 11557 bce_dump_txp_state(sc, 0); 11558 bce_dump_rxp_state(sc, 0); 11559 bce_dump_tpat_state(sc, 0); 11560 bce_dump_cp_state(sc, 0); 11561 bce_dump_com_state(sc, 0); 11562 bce_dump_rv2p_state(sc); 11563 bce_dump_pgbd(sc, 0, NULL); 11564 } 11565 11566 bce_dump_status_block(sc); 11567 bce_dump_driver_state(sc); 11568 11569 /* Call the debugger. */ 11570 breakpoint(); 11571 } 11572 #endif 11573