1 /*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54 #include "opt_bce.h" 55 56 #include <dev/bce/if_bcereg.h> 57 #include <dev/bce/if_bcefw.h> 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89 #endif 90 91 /****************************************************************************/ 92 /* PCI Device ID Table */ 93 /* */ 94 /* Used by bce_probe() to identify the devices supported by this driver. */ 95 /****************************************************************************/ 96 #define BCE_DEVDESC_MAX 64 97 98 static struct bce_type bce_devs[] = { 99 /* BCM5706C Controllers and OEM boards. */ 100 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 101 "HP NC370T Multifunction Gigabit Server Adapter" }, 102 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 103 "HP NC370i Multifunction Gigabit Server Adapter" }, 104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 105 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 107 "HP NC371i Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 109 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 110 111 /* BCM5706S controllers and OEM boards. */ 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 113 "HP NC370F Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 116 117 /* BCM5708C controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 119 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 121 "HP NC373i Multifunction Gigabit Server Adapter" }, 122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 123 "HP NC374m PCIe Multifunction Adapter" }, 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 125 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 126 127 /* BCM5708S controllers and OEM boards. */ 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 129 "HP NC373m Multifunction Gigabit Server Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 131 "HP NC373i Multifunction Gigabit Server Adapter" }, 132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 133 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 135 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 136 137 /* BCM5709C controllers and OEM boards. */ 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 139 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 141 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 143 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 144 145 /* BCM5709S controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 147 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 149 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 151 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 152 153 /* BCM5716 controllers and OEM boards. */ 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 155 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 156 157 { 0, 0, 0, 0, NULL } 158 }; 159 160 161 /****************************************************************************/ 162 /* Supported Flash NVRAM device data. */ 163 /****************************************************************************/ 164 static struct flash_spec flash_table[] = 165 { 166 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 167 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 168 169 /* Slow EEPROM */ 170 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 171 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 172 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 173 "EEPROM - slow"}, 174 /* Expansion entry 0001 */ 175 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 178 "Entry 0001"}, 179 /* Saifun SA25F010 (non-buffered flash) */ 180 /* strap, cfg1, & write1 need updates */ 181 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 184 "Non-buffered flash (128kB)"}, 185 /* Saifun SA25F020 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 190 "Non-buffered flash (256kB)"}, 191 /* Expansion entry 0100 */ 192 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0100"}, 196 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 197 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 198 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 199 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 200 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 201 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 202 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 204 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 205 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 206 /* Saifun SA25F005 (non-buffered flash) */ 207 /* strap, cfg1, & write1 need updates */ 208 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 210 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 211 "Non-buffered flash (64kB)"}, 212 /* Fast EEPROM */ 213 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 214 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 215 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 216 "EEPROM - fast"}, 217 /* Expansion entry 1001 */ 218 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 221 "Entry 1001"}, 222 /* Expansion entry 1010 */ 223 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 226 "Entry 1010"}, 227 /* ATMEL AT45DB011B (buffered flash) */ 228 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 230 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 231 "Buffered flash (128kB)"}, 232 /* Expansion entry 1100 */ 233 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 236 "Entry 1100"}, 237 /* Expansion entry 1101 */ 238 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 1101"}, 242 /* Ateml Expansion entry 1110 */ 243 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 244 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 245 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 246 "Entry 1110 (Atmel)"}, 247 /* ATMEL AT45DB021B (buffered flash) */ 248 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 251 "Buffered flash (256kB)"}, 252 }; 253 254 /* 255 * The BCM5709 controllers transparently handle the 256 * differences between Atmel 264 byte pages and all 257 * flash devices which use 256 byte pages, so no 258 * logical-to-physical mapping is required in the 259 * driver. 260 */ 261 static struct flash_spec flash_5709 = { 262 .flags = BCE_NV_BUFFERED, 263 .page_bits = BCM5709_FLASH_PAGE_BITS, 264 .page_size = BCM5709_FLASH_PAGE_SIZE, 265 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 266 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 267 .name = "5709/5716 buffered flash (256kB)", 268 }; 269 270 271 /****************************************************************************/ 272 /* FreeBSD device entry points. */ 273 /****************************************************************************/ 274 static int bce_probe (device_t); 275 static int bce_attach (device_t); 276 static int bce_detach (device_t); 277 static int bce_shutdown (device_t); 278 279 280 /****************************************************************************/ 281 /* BCE Debug Data Structure Dump Routines */ 282 /****************************************************************************/ 283 #ifdef BCE_DEBUG 284 static u32 bce_reg_rd (struct bce_softc *, u32); 285 static void bce_reg_wr (struct bce_softc *, u32, u32); 286 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 287 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 288 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 289 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 290 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 291 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 292 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 293 static void bce_dump_txbd (struct bce_softc *, 294 int, struct tx_bd *); 295 static void bce_dump_rxbd (struct bce_softc *, 296 int, struct rx_bd *); 297 static void bce_dump_pgbd (struct bce_softc *, 298 int, struct rx_bd *); 299 static void bce_dump_l2fhdr (struct bce_softc *, 300 int, struct l2_fhdr *); 301 static void bce_dump_ctx (struct bce_softc *, u16); 302 static void bce_dump_ftqs (struct bce_softc *); 303 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 304 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 305 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 306 static void bce_dump_status_block (struct bce_softc *); 307 static void bce_dump_stats_block (struct bce_softc *); 308 static void bce_dump_driver_state (struct bce_softc *); 309 static void bce_dump_hw_state (struct bce_softc *); 310 static void bce_dump_shmem_state (struct bce_softc *); 311 static void bce_dump_mq_regs (struct bce_softc *); 312 static void bce_dump_bc_state (struct bce_softc *); 313 static void bce_dump_txp_state (struct bce_softc *, int); 314 static void bce_dump_rxp_state (struct bce_softc *, int); 315 static void bce_dump_tpat_state (struct bce_softc *, int); 316 static void bce_dump_cp_state (struct bce_softc *, int); 317 static void bce_dump_com_state (struct bce_softc *, int); 318 static void bce_dump_rv2p_state (struct bce_softc *); 319 static void bce_breakpoint (struct bce_softc *); 320 #endif /*BCE_DEBUG */ 321 322 323 /****************************************************************************/ 324 /* BCE Register/Memory Access Routines */ 325 /****************************************************************************/ 326 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 327 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 328 static void bce_shmem_wr (struct bce_softc *, u32, u32); 329 static u32 bce_shmem_rd (struct bce_softc *, u32); 330 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 331 static int bce_miibus_read_reg (device_t, int, int); 332 static int bce_miibus_write_reg (device_t, int, int, int); 333 static void bce_miibus_statchg (device_t); 334 335 #ifdef BCE_DEBUG 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 337 #ifdef BCE_NVRAM_WRITE_SUPPORT 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 339 #endif 340 #endif 341 342 /****************************************************************************/ 343 /* BCE NVRAM Access Routines */ 344 /****************************************************************************/ 345 static int bce_acquire_nvram_lock (struct bce_softc *); 346 static int bce_release_nvram_lock (struct bce_softc *); 347 static void bce_enable_nvram_access(struct bce_softc *); 348 static void bce_disable_nvram_access(struct bce_softc *); 349 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 350 static int bce_init_nvram (struct bce_softc *); 351 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 352 static int bce_nvram_test (struct bce_softc *); 353 #ifdef BCE_NVRAM_WRITE_SUPPORT 354 static int bce_enable_nvram_write (struct bce_softc *); 355 static void bce_disable_nvram_write(struct bce_softc *); 356 static int bce_nvram_erase_page (struct bce_softc *, u32); 357 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 358 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 359 #endif 360 361 /****************************************************************************/ 362 /* */ 363 /****************************************************************************/ 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 365 static void bce_get_media (struct bce_softc *); 366 static void bce_init_media (struct bce_softc *); 367 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 368 static int bce_dma_alloc (device_t); 369 static void bce_dma_free (struct bce_softc *); 370 static void bce_release_resources (struct bce_softc *); 371 372 /****************************************************************************/ 373 /* BCE Firmware Synchronization and Load */ 374 /****************************************************************************/ 375 static int bce_fw_sync (struct bce_softc *, u32); 376 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 377 static void bce_load_cpu_fw (struct bce_softc *, 378 struct cpu_reg *, struct fw_info *); 379 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 380 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 381 static void bce_start_rxp_cpu (struct bce_softc *); 382 static void bce_init_rxp_cpu (struct bce_softc *); 383 static void bce_init_txp_cpu (struct bce_softc *); 384 static void bce_init_tpat_cpu (struct bce_softc *); 385 static void bce_init_cp_cpu (struct bce_softc *); 386 static void bce_init_com_cpu (struct bce_softc *); 387 static void bce_init_cpus (struct bce_softc *); 388 389 static void bce_print_adapter_info (struct bce_softc *); 390 static void bce_probe_pci_caps (device_t, struct bce_softc *); 391 static void bce_stop (struct bce_softc *); 392 static int bce_reset (struct bce_softc *, u32); 393 static int bce_chipinit (struct bce_softc *); 394 static int bce_blockinit (struct bce_softc *); 395 396 static int bce_init_tx_chain (struct bce_softc *); 397 static void bce_free_tx_chain (struct bce_softc *); 398 399 static int bce_get_rx_buf (struct bce_softc *, 400 struct mbuf *, u16 *, u16 *, u32 *); 401 static int bce_init_rx_chain (struct bce_softc *); 402 static void bce_fill_rx_chain (struct bce_softc *); 403 static void bce_free_rx_chain (struct bce_softc *); 404 405 static int bce_get_pg_buf (struct bce_softc *, 406 struct mbuf *, u16 *, u16 *); 407 static int bce_init_pg_chain (struct bce_softc *); 408 static void bce_fill_pg_chain (struct bce_softc *); 409 static void bce_free_pg_chain (struct bce_softc *); 410 411 static struct mbuf *bce_tso_setup (struct bce_softc *, 412 struct mbuf **, u16 *); 413 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 414 static void bce_start_locked (struct ifnet *); 415 static void bce_start (struct ifnet *); 416 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 417 static void bce_watchdog (struct bce_softc *); 418 static int bce_ifmedia_upd (struct ifnet *); 419 static int bce_ifmedia_upd_locked (struct ifnet *); 420 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 421 static void bce_init_locked (struct bce_softc *); 422 static void bce_init (void *); 423 static void bce_mgmt_init_locked (struct bce_softc *sc); 424 425 static int bce_init_ctx (struct bce_softc *); 426 static void bce_get_mac_addr (struct bce_softc *); 427 static void bce_set_mac_addr (struct bce_softc *); 428 static void bce_phy_intr (struct bce_softc *); 429 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 430 static void bce_rx_intr (struct bce_softc *); 431 static void bce_tx_intr (struct bce_softc *); 432 static void bce_disable_intr (struct bce_softc *); 433 static void bce_enable_intr (struct bce_softc *, int); 434 435 static void bce_intr (void *); 436 static void bce_set_rx_mode (struct bce_softc *); 437 static void bce_stats_update (struct bce_softc *); 438 static void bce_tick (void *); 439 static void bce_pulse (void *); 440 static void bce_add_sysctls (struct bce_softc *); 441 442 443 /****************************************************************************/ 444 /* FreeBSD device dispatch table. */ 445 /****************************************************************************/ 446 static device_method_t bce_methods[] = { 447 /* Device interface (device_if.h) */ 448 DEVMETHOD(device_probe, bce_probe), 449 DEVMETHOD(device_attach, bce_attach), 450 DEVMETHOD(device_detach, bce_detach), 451 DEVMETHOD(device_shutdown, bce_shutdown), 452 /* Supported by device interface but not used here. */ 453 /* DEVMETHOD(device_identify, bce_identify), */ 454 /* DEVMETHOD(device_suspend, bce_suspend), */ 455 /* DEVMETHOD(device_resume, bce_resume), */ 456 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 457 458 /* MII interface (miibus_if.h) */ 459 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 460 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 461 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 462 /* Supported by MII interface but not used here. */ 463 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 464 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 465 466 DEVMETHOD_END 467 }; 468 469 static driver_t bce_driver = { 470 "bce", 471 bce_methods, 472 sizeof(struct bce_softc) 473 }; 474 475 static devclass_t bce_devclass; 476 477 MODULE_DEPEND(bce, pci, 1, 1, 1); 478 MODULE_DEPEND(bce, ether, 1, 1, 1); 479 MODULE_DEPEND(bce, miibus, 1, 1, 1); 480 481 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 482 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 483 484 485 /****************************************************************************/ 486 /* Tunable device values */ 487 /****************************************************************************/ 488 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 489 490 /* Allowable values are TRUE or FALSE */ 491 static int bce_verbose = TRUE; 492 TUNABLE_INT("hw.bce.verbose", &bce_verbose); 493 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 494 "Verbose output enable/disable"); 495 496 /* Allowable values are TRUE or FALSE */ 497 static int bce_tso_enable = TRUE; 498 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 499 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 500 "TSO Enable/Disable"); 501 502 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 503 /* ToDo: Add MSI-X support. */ 504 static int bce_msi_enable = 1; 505 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 506 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 507 "MSI-X|MSI|INTx selector"); 508 509 /* Allowable values are 1, 2, 4, 8. */ 510 static int bce_rx_pages = DEFAULT_RX_PAGES; 511 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 512 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 513 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 514 515 /* Allowable values are 1, 2, 4, 8. */ 516 static int bce_tx_pages = DEFAULT_TX_PAGES; 517 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 518 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 519 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 520 521 /* Allowable values are TRUE or FALSE. */ 522 static int bce_hdr_split = TRUE; 523 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 524 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 525 "Frame header/payload splitting Enable/Disable"); 526 527 /* Allowable values are TRUE or FALSE. */ 528 static int bce_strict_rx_mtu = FALSE; 529 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 530 SYSCTL_UINT(_hw_bce, OID_AUTO, loose_rx_mtu, CTLFLAG_RDTUN, 531 &bce_strict_rx_mtu, 0, 532 "Enable/Disable strict RX frame size checking"); 533 534 /* Allowable values are 0 ... 100 */ 535 #ifdef BCE_DEBUG 536 /* Generate 1 interrupt for every transmit completion. */ 537 static int bce_tx_quick_cons_trip_int = 1; 538 #else 539 /* Generate 1 interrupt for every 20 transmit completions. */ 540 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 541 #endif 542 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 543 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 544 &bce_tx_quick_cons_trip_int, 0, 545 "Transmit BD trip point during interrupts"); 546 547 /* Allowable values are 0 ... 100 */ 548 /* Generate 1 interrupt for every transmit completion. */ 549 #ifdef BCE_DEBUG 550 static int bce_tx_quick_cons_trip = 1; 551 #else 552 /* Generate 1 interrupt for every 20 transmit completions. */ 553 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 554 #endif 555 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 556 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 557 &bce_tx_quick_cons_trip, 0, 558 "Transmit BD trip point"); 559 560 /* Allowable values are 0 ... 100 */ 561 #ifdef BCE_DEBUG 562 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 563 static int bce_tx_ticks_int = 0; 564 #else 565 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 566 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 567 #endif 568 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 569 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 570 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 571 572 /* Allowable values are 0 ... 100 */ 573 #ifdef BCE_DEBUG 574 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 575 static int bce_tx_ticks = 0; 576 #else 577 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 578 static int bce_tx_ticks = DEFAULT_TX_TICKS; 579 #endif 580 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 581 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 582 &bce_tx_ticks, 0, "Transmit ticks count"); 583 584 /* Allowable values are 1 ... 100 */ 585 #ifdef BCE_DEBUG 586 /* Generate 1 interrupt for every received frame. */ 587 static int bce_rx_quick_cons_trip_int = 1; 588 #else 589 /* Generate 1 interrupt for every 6 received frames. */ 590 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 591 #endif 592 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 593 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 594 &bce_rx_quick_cons_trip_int, 0, 595 "Receive BD trip point duirng interrupts"); 596 597 /* Allowable values are 1 ... 100 */ 598 #ifdef BCE_DEBUG 599 /* Generate 1 interrupt for every received frame. */ 600 static int bce_rx_quick_cons_trip = 1; 601 #else 602 /* Generate 1 interrupt for every 6 received frames. */ 603 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 604 #endif 605 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 606 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 607 &bce_rx_quick_cons_trip, 0, 608 "Receive BD trip point"); 609 610 /* Allowable values are 0 ... 100 */ 611 #ifdef BCE_DEBUG 612 /* Generate an int. if 0us have elapsed since the last received frame. */ 613 static int bce_rx_ticks_int = 0; 614 #else 615 /* Generate an int. if 18us have elapsed since the last received frame. */ 616 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 617 #endif 618 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 619 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 620 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 621 622 /* Allowable values are 0 ... 100 */ 623 #ifdef BCE_DEBUG 624 /* Generate an int. if 0us have elapsed since the last received frame. */ 625 static int bce_rx_ticks = 0; 626 #else 627 /* Generate an int. if 18us have elapsed since the last received frame. */ 628 static int bce_rx_ticks = DEFAULT_RX_TICKS; 629 #endif 630 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 631 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 632 &bce_rx_ticks, 0, "Receive ticks count"); 633 634 635 /****************************************************************************/ 636 /* Device probe function. */ 637 /* */ 638 /* Compares the device to the driver's list of supported devices and */ 639 /* reports back to the OS whether this is the right driver for the device. */ 640 /* */ 641 /* Returns: */ 642 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 643 /****************************************************************************/ 644 static int 645 bce_probe(device_t dev) 646 { 647 struct bce_type *t; 648 struct bce_softc *sc; 649 char *descbuf; 650 u16 vid = 0, did = 0, svid = 0, sdid = 0; 651 652 t = bce_devs; 653 654 sc = device_get_softc(dev); 655 bzero(sc, sizeof(struct bce_softc)); 656 sc->bce_unit = device_get_unit(dev); 657 sc->bce_dev = dev; 658 659 /* Get the data for the device to be probed. */ 660 vid = pci_get_vendor(dev); 661 did = pci_get_device(dev); 662 svid = pci_get_subvendor(dev); 663 sdid = pci_get_subdevice(dev); 664 665 DBPRINT(sc, BCE_EXTREME_LOAD, 666 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 667 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 668 669 /* Look through the list of known devices for a match. */ 670 while(t->bce_name != NULL) { 671 672 if ((vid == t->bce_vid) && (did == t->bce_did) && 673 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 674 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 675 676 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 677 678 if (descbuf == NULL) 679 return(ENOMEM); 680 681 /* Print out the device identity. */ 682 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 683 t->bce_name, (((pci_read_config(dev, 684 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 685 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 686 687 device_set_desc_copy(dev, descbuf); 688 free(descbuf, M_TEMP); 689 return(BUS_PROBE_DEFAULT); 690 } 691 t++; 692 } 693 694 return(ENXIO); 695 } 696 697 698 /****************************************************************************/ 699 /* PCI Capabilities Probe Function. */ 700 /* */ 701 /* Walks the PCI capabiites list for the device to find what features are */ 702 /* supported. */ 703 /* */ 704 /* Returns: */ 705 /* None. */ 706 /****************************************************************************/ 707 static void 708 bce_print_adapter_info(struct bce_softc *sc) 709 { 710 int i = 0; 711 712 DBENTER(BCE_VERBOSE_LOAD); 713 714 if (bce_verbose || bootverbose) { 715 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 716 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 717 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 718 719 720 /* Bus info. */ 721 if (sc->bce_flags & BCE_PCIE_FLAG) { 722 printf("Bus (PCIe x%d, ", sc->link_width); 723 switch (sc->link_speed) { 724 case 1: printf("2.5Gbps); "); break; 725 case 2: printf("5Gbps); "); break; 726 default: printf("Unknown link speed); "); 727 } 728 } else { 729 printf("Bus (PCI%s, %s, %dMHz); ", 730 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 731 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 732 "32-bit" : "64-bit"), sc->bus_speed_mhz); 733 } 734 735 /* Firmware version and device features. */ 736 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 737 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 738 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 739 740 if (bce_hdr_split == TRUE) { 741 printf("SPLT"); 742 i++; 743 } 744 745 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 746 if (i > 0) printf("|"); 747 printf("MSI"); i++; 748 } 749 750 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 751 if (i > 0) printf("|"); 752 printf("MSI-X"); i++; 753 } 754 755 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 756 if (i > 0) printf("|"); 757 printf("2.5G"); i++; 758 } 759 760 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 761 if (i > 0) printf("|"); 762 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 763 } else { 764 printf(")\n"); 765 } 766 767 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 768 sc->bce_rx_quick_cons_trip_int, 769 sc->bce_rx_quick_cons_trip, 770 sc->bce_rx_ticks_int, 771 sc->bce_rx_ticks, 772 sc->bce_tx_quick_cons_trip_int, 773 sc->bce_tx_quick_cons_trip, 774 sc->bce_tx_ticks_int, 775 sc->bce_tx_ticks); 776 777 } 778 779 DBEXIT(BCE_VERBOSE_LOAD); 780 } 781 782 783 /****************************************************************************/ 784 /* PCI Capabilities Probe Function. */ 785 /* */ 786 /* Walks the PCI capabiites list for the device to find what features are */ 787 /* supported. */ 788 /* */ 789 /* Returns: */ 790 /* None. */ 791 /****************************************************************************/ 792 static void 793 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 794 { 795 u32 reg; 796 797 DBENTER(BCE_VERBOSE_LOAD); 798 799 /* Check if PCI-X capability is enabled. */ 800 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 801 if (reg != 0) 802 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 803 } 804 805 /* Check if PCIe capability is enabled. */ 806 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 807 if (reg != 0) { 808 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 809 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 810 "0x%08X\n", link_status); 811 sc->link_speed = link_status & 0xf; 812 sc->link_width = (link_status >> 4) & 0x3f; 813 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 814 sc->bce_flags |= BCE_PCIE_FLAG; 815 } 816 } 817 818 /* Check if MSI capability is enabled. */ 819 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 820 if (reg != 0) 821 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 822 } 823 824 /* Check if MSI-X capability is enabled. */ 825 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 826 if (reg != 0) 827 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 828 } 829 830 DBEXIT(BCE_VERBOSE_LOAD); 831 } 832 833 834 /****************************************************************************/ 835 /* Load and validate user tunable settings. */ 836 /* */ 837 /* Returns: */ 838 /* Nothing. */ 839 /****************************************************************************/ 840 static void 841 bce_set_tunables(struct bce_softc *sc) 842 { 843 /* Set sysctl values for RX page count. */ 844 switch (bce_rx_pages) { 845 case 1: 846 /* fall-through */ 847 case 2: 848 /* fall-through */ 849 case 4: 850 /* fall-through */ 851 case 8: 852 sc->rx_pages = bce_rx_pages; 853 break; 854 default: 855 sc->rx_pages = DEFAULT_RX_PAGES; 856 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 857 "hw.bce.rx_pages! Setting default of %d.\n", 858 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 859 } 860 861 /* ToDo: Consider allowing user setting for pg_pages. */ 862 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 863 864 /* Set sysctl values for TX page count. */ 865 switch (bce_tx_pages) { 866 case 1: 867 /* fall-through */ 868 case 2: 869 /* fall-through */ 870 case 4: 871 /* fall-through */ 872 case 8: 873 sc->tx_pages = bce_tx_pages; 874 break; 875 default: 876 sc->tx_pages = DEFAULT_TX_PAGES; 877 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 878 "hw.bce.tx_pages! Setting default of %d.\n", 879 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 880 } 881 882 /* 883 * Validate the TX trip point (i.e. the number of 884 * TX completions before a status block update is 885 * generated and an interrupt is asserted. 886 */ 887 if (bce_tx_quick_cons_trip_int <= 100) { 888 sc->bce_tx_quick_cons_trip_int = 889 bce_tx_quick_cons_trip_int; 890 } else { 891 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 892 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 893 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 894 DEFAULT_TX_QUICK_CONS_TRIP_INT); 895 sc->bce_tx_quick_cons_trip_int = 896 DEFAULT_TX_QUICK_CONS_TRIP_INT; 897 } 898 899 if (bce_tx_quick_cons_trip <= 100) { 900 sc->bce_tx_quick_cons_trip = 901 bce_tx_quick_cons_trip; 902 } else { 903 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 904 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 905 __FILE__, __LINE__, bce_tx_quick_cons_trip, 906 DEFAULT_TX_QUICK_CONS_TRIP); 907 sc->bce_tx_quick_cons_trip = 908 DEFAULT_TX_QUICK_CONS_TRIP; 909 } 910 911 /* 912 * Validate the TX ticks count (i.e. the maximum amount 913 * of time to wait after the last TX completion has 914 * occurred before a status block update is generated 915 * and an interrupt is asserted. 916 */ 917 if (bce_tx_ticks_int <= 100) { 918 sc->bce_tx_ticks_int = 919 bce_tx_ticks_int; 920 } else { 921 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 922 "hw.bce.tx_ticks_int! Setting default of %d.\n", 923 __FILE__, __LINE__, bce_tx_ticks_int, 924 DEFAULT_TX_TICKS_INT); 925 sc->bce_tx_ticks_int = 926 DEFAULT_TX_TICKS_INT; 927 } 928 929 if (bce_tx_ticks <= 100) { 930 sc->bce_tx_ticks = 931 bce_tx_ticks; 932 } else { 933 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 934 "hw.bce.tx_ticks! Setting default of %d.\n", 935 __FILE__, __LINE__, bce_tx_ticks, 936 DEFAULT_TX_TICKS); 937 sc->bce_tx_ticks = 938 DEFAULT_TX_TICKS; 939 } 940 941 /* 942 * Validate the RX trip point (i.e. the number of 943 * RX frames received before a status block update is 944 * generated and an interrupt is asserted. 945 */ 946 if (bce_rx_quick_cons_trip_int <= 100) { 947 sc->bce_rx_quick_cons_trip_int = 948 bce_rx_quick_cons_trip_int; 949 } else { 950 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 951 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 952 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 953 DEFAULT_RX_QUICK_CONS_TRIP_INT); 954 sc->bce_rx_quick_cons_trip_int = 955 DEFAULT_RX_QUICK_CONS_TRIP_INT; 956 } 957 958 if (bce_rx_quick_cons_trip <= 100) { 959 sc->bce_rx_quick_cons_trip = 960 bce_rx_quick_cons_trip; 961 } else { 962 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 963 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 964 __FILE__, __LINE__, bce_rx_quick_cons_trip, 965 DEFAULT_RX_QUICK_CONS_TRIP); 966 sc->bce_rx_quick_cons_trip = 967 DEFAULT_RX_QUICK_CONS_TRIP; 968 } 969 970 /* 971 * Validate the RX ticks count (i.e. the maximum amount 972 * of time to wait after the last RX frame has been 973 * received before a status block update is generated 974 * and an interrupt is asserted. 975 */ 976 if (bce_rx_ticks_int <= 100) { 977 sc->bce_rx_ticks_int = bce_rx_ticks_int; 978 } else { 979 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 980 "hw.bce.rx_ticks_int! Setting default of %d.\n", 981 __FILE__, __LINE__, bce_rx_ticks_int, 982 DEFAULT_RX_TICKS_INT); 983 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 984 } 985 986 if (bce_rx_ticks <= 100) { 987 sc->bce_rx_ticks = bce_rx_ticks; 988 } else { 989 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 990 "hw.bce.rx_ticks! Setting default of %d.\n", 991 __FILE__, __LINE__, bce_rx_ticks, 992 DEFAULT_RX_TICKS); 993 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 994 } 995 996 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 997 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 998 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 999 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1000 __FILE__, __LINE__); 1001 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1002 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1003 } 1004 1005 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1006 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1007 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1008 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1009 __FILE__, __LINE__); 1010 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1011 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1012 } 1013 1014 } 1015 1016 1017 /****************************************************************************/ 1018 /* Device attach function. */ 1019 /* */ 1020 /* Allocates device resources, performs secondary chip identification, */ 1021 /* resets and initializes the hardware, and initializes driver instance */ 1022 /* variables. */ 1023 /* */ 1024 /* Returns: */ 1025 /* 0 on success, positive value on failure. */ 1026 /****************************************************************************/ 1027 static int 1028 bce_attach(device_t dev) 1029 { 1030 struct bce_softc *sc; 1031 struct ifnet *ifp; 1032 u32 val; 1033 int error, rid, rc = 0; 1034 1035 sc = device_get_softc(dev); 1036 sc->bce_dev = dev; 1037 1038 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1039 1040 sc->bce_unit = device_get_unit(dev); 1041 1042 /* Set initial device and PHY flags */ 1043 sc->bce_flags = 0; 1044 sc->bce_phy_flags = 0; 1045 1046 bce_set_tunables(sc); 1047 1048 pci_enable_busmaster(dev); 1049 1050 /* Allocate PCI memory resources. */ 1051 rid = PCIR_BAR(0); 1052 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1053 &rid, RF_ACTIVE); 1054 1055 if (sc->bce_res_mem == NULL) { 1056 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1057 __FILE__, __LINE__); 1058 rc = ENXIO; 1059 goto bce_attach_fail; 1060 } 1061 1062 /* Get various resource handles. */ 1063 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1064 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1065 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1066 1067 bce_probe_pci_caps(dev, sc); 1068 1069 rid = 1; 1070 #if 0 1071 /* Try allocating MSI-X interrupts. */ 1072 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1073 (bce_msi_enable >= 2) && 1074 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1075 &rid, RF_ACTIVE)) != NULL)) { 1076 1077 msi_needed = sc->bce_msi_count = 1; 1078 1079 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 1080 (sc->bce_msi_count != msi_needed)) { 1081 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1082 "Received = %d, error = %d\n", __FILE__, __LINE__, 1083 msi_needed, sc->bce_msi_count, error); 1084 sc->bce_msi_count = 0; 1085 pci_release_msi(dev); 1086 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1087 sc->bce_res_irq); 1088 sc->bce_res_irq = NULL; 1089 } else { 1090 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1091 __FUNCTION__); 1092 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1093 sc->bce_intr = bce_intr; 1094 } 1095 } 1096 #endif 1097 1098 /* Try allocating a MSI interrupt. */ 1099 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1100 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 1101 sc->bce_msi_count = 1; 1102 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 1103 BCE_PRINTF("%s(%d): MSI allocation failed! " 1104 "error = %d\n", __FILE__, __LINE__, error); 1105 sc->bce_msi_count = 0; 1106 pci_release_msi(dev); 1107 } else { 1108 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1109 "interrupt.\n", __FUNCTION__); 1110 sc->bce_flags |= BCE_USING_MSI_FLAG; 1111 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1112 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1113 sc->bce_irq_rid = 1; 1114 sc->bce_intr = bce_intr; 1115 } 1116 } 1117 1118 /* Try allocating a legacy interrupt. */ 1119 if (sc->bce_msi_count == 0) { 1120 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1121 __FUNCTION__); 1122 rid = 0; 1123 sc->bce_intr = bce_intr; 1124 } 1125 1126 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1127 &rid, RF_SHAREABLE | RF_ACTIVE); 1128 1129 sc->bce_irq_rid = rid; 1130 1131 /* Report any IRQ allocation errors. */ 1132 if (sc->bce_res_irq == NULL) { 1133 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1134 __FILE__, __LINE__); 1135 rc = ENXIO; 1136 goto bce_attach_fail; 1137 } 1138 1139 /* Initialize mutex for the current device instance. */ 1140 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1141 1142 /* 1143 * Configure byte swap and enable indirect register access. 1144 * Rely on CPU to do target byte swapping on big endian systems. 1145 * Access to registers outside of PCI configurtion space are not 1146 * valid until this is done. 1147 */ 1148 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1149 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1150 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1151 1152 /* Save ASIC revsion info. */ 1153 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1154 1155 /* Weed out any non-production controller revisions. */ 1156 switch(BCE_CHIP_ID(sc)) { 1157 case BCE_CHIP_ID_5706_A0: 1158 case BCE_CHIP_ID_5706_A1: 1159 case BCE_CHIP_ID_5708_A0: 1160 case BCE_CHIP_ID_5708_B0: 1161 case BCE_CHIP_ID_5709_A0: 1162 case BCE_CHIP_ID_5709_B0: 1163 case BCE_CHIP_ID_5709_B1: 1164 case BCE_CHIP_ID_5709_B2: 1165 BCE_PRINTF("%s(%d): Unsupported controller " 1166 "revision (%c%d)!\n", __FILE__, __LINE__, 1167 (((pci_read_config(dev, PCIR_REVID, 4) & 1168 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1169 PCIR_REVID, 4) & 0xf)); 1170 rc = ENODEV; 1171 goto bce_attach_fail; 1172 } 1173 1174 /* 1175 * The embedded PCIe to PCI-X bridge (EPB) 1176 * in the 5708 cannot address memory above 1177 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1178 */ 1179 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1180 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1181 else 1182 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1183 1184 /* 1185 * Find the base address for shared memory access. 1186 * Newer versions of bootcode use a signature and offset 1187 * while older versions use a fixed address. 1188 */ 1189 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1190 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1191 /* Multi-port devices use different offsets in shared memory. */ 1192 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1193 (pci_get_function(sc->bce_dev) << 2)); 1194 else 1195 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1196 1197 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1198 __FUNCTION__, sc->bce_shmem_base); 1199 1200 /* Fetch the bootcode revision. */ 1201 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1202 for (int i = 0, j = 0; i < 3; i++) { 1203 u8 num; 1204 1205 num = (u8) (val >> (24 - (i * 8))); 1206 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1207 if (num >= k || !skip0 || k == 1) { 1208 sc->bce_bc_ver[j++] = (num / k) + '0'; 1209 skip0 = 0; 1210 } 1211 } 1212 1213 if (i != 2) 1214 sc->bce_bc_ver[j++] = '.'; 1215 } 1216 1217 /* Check if any management firwmare is enabled. */ 1218 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1219 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1220 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1221 1222 /* Allow time for firmware to enter the running state. */ 1223 for (int i = 0; i < 30; i++) { 1224 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1225 if (val & BCE_CONDITION_MFW_RUN_MASK) 1226 break; 1227 DELAY(10000); 1228 } 1229 1230 /* Check if management firmware is running. */ 1231 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1232 val &= BCE_CONDITION_MFW_RUN_MASK; 1233 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1234 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1235 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1236 int i = 0; 1237 1238 /* Read the management firmware version string. */ 1239 for (int j = 0; j < 3; j++) { 1240 val = bce_reg_rd_ind(sc, addr + j * 4); 1241 val = bswap32(val); 1242 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1243 i += 4; 1244 } 1245 } else { 1246 /* May cause firmware synchronization timeouts. */ 1247 BCE_PRINTF("%s(%d): Management firmware enabled " 1248 "but not running!\n", __FILE__, __LINE__); 1249 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1250 1251 /* ToDo: Any action the driver should take? */ 1252 } 1253 } 1254 1255 /* Get PCI bus information (speed and type). */ 1256 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1257 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1258 u32 clkreg; 1259 1260 sc->bce_flags |= BCE_PCIX_FLAG; 1261 1262 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1263 1264 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1265 switch (clkreg) { 1266 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1267 sc->bus_speed_mhz = 133; 1268 break; 1269 1270 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1271 sc->bus_speed_mhz = 100; 1272 break; 1273 1274 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1275 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1276 sc->bus_speed_mhz = 66; 1277 break; 1278 1279 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1280 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1281 sc->bus_speed_mhz = 50; 1282 break; 1283 1284 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1285 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1286 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1287 sc->bus_speed_mhz = 33; 1288 break; 1289 } 1290 } else { 1291 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1292 sc->bus_speed_mhz = 66; 1293 else 1294 sc->bus_speed_mhz = 33; 1295 } 1296 1297 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1298 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1299 1300 /* Reset controller and announce to bootcode that driver is present. */ 1301 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1302 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1303 __FILE__, __LINE__); 1304 rc = ENXIO; 1305 goto bce_attach_fail; 1306 } 1307 1308 /* Initialize the controller. */ 1309 if (bce_chipinit(sc)) { 1310 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1311 __FILE__, __LINE__); 1312 rc = ENXIO; 1313 goto bce_attach_fail; 1314 } 1315 1316 /* Perform NVRAM test. */ 1317 if (bce_nvram_test(sc)) { 1318 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1319 __FILE__, __LINE__); 1320 rc = ENXIO; 1321 goto bce_attach_fail; 1322 } 1323 1324 /* Fetch the permanent Ethernet MAC address. */ 1325 bce_get_mac_addr(sc); 1326 1327 /* 1328 * Trip points control how many BDs 1329 * should be ready before generating an 1330 * interrupt while ticks control how long 1331 * a BD can sit in the chain before 1332 * generating an interrupt. Set the default 1333 * values for the RX and TX chains. 1334 */ 1335 1336 /* Not used for L2. */ 1337 sc->bce_comp_prod_trip_int = 0; 1338 sc->bce_comp_prod_trip = 0; 1339 sc->bce_com_ticks_int = 0; 1340 sc->bce_com_ticks = 0; 1341 sc->bce_cmd_ticks_int = 0; 1342 sc->bce_cmd_ticks = 0; 1343 1344 /* Update statistics once every second. */ 1345 sc->bce_stats_ticks = 1000000 & 0xffff00; 1346 1347 /* Find the media type for the adapter. */ 1348 bce_get_media(sc); 1349 1350 /* Store data needed by PHY driver for backplane applications */ 1351 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1352 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1353 1354 /* Allocate DMA memory resources. */ 1355 if (bce_dma_alloc(dev)) { 1356 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1357 __FILE__, __LINE__); 1358 rc = ENXIO; 1359 goto bce_attach_fail; 1360 } 1361 1362 /* Allocate an ifnet structure. */ 1363 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1364 if (ifp == NULL) { 1365 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1366 __FILE__, __LINE__); 1367 rc = ENXIO; 1368 goto bce_attach_fail; 1369 } 1370 1371 /* Initialize the ifnet interface. */ 1372 ifp->if_softc = sc; 1373 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1374 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1375 ifp->if_ioctl = bce_ioctl; 1376 ifp->if_start = bce_start; 1377 ifp->if_init = bce_init; 1378 ifp->if_mtu = ETHERMTU; 1379 1380 if (bce_tso_enable) { 1381 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1382 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1383 IFCAP_VLAN_HWTSO; 1384 } else { 1385 ifp->if_hwassist = BCE_IF_HWASSIST; 1386 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1387 } 1388 1389 ifp->if_capenable = ifp->if_capabilities; 1390 1391 /* 1392 * Assume standard mbuf sizes for buffer allocation. 1393 * This may change later if the MTU size is set to 1394 * something other than 1500. 1395 */ 1396 bce_get_rx_buffer_sizes(sc, 1397 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1398 1399 /* Recalculate our buffer allocation sizes. */ 1400 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1401 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1402 IFQ_SET_READY(&ifp->if_snd); 1403 1404 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1405 ifp->if_baudrate = IF_Mbps(2500ULL); 1406 else 1407 ifp->if_baudrate = IF_Mbps(1000); 1408 1409 /* Handle any special PHY initialization for SerDes PHYs. */ 1410 bce_init_media(sc); 1411 1412 /* MII child bus by attaching the PHY. */ 1413 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1414 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1415 MII_OFFSET_ANY, MIIF_DOPAUSE); 1416 if (rc != 0) { 1417 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1418 __LINE__); 1419 goto bce_attach_fail; 1420 } 1421 1422 /* Attach to the Ethernet interface list. */ 1423 ether_ifattach(ifp, sc->eaddr); 1424 1425 #if __FreeBSD_version < 500000 1426 callout_init(&sc->bce_tick_callout); 1427 callout_init(&sc->bce_pulse_callout); 1428 #else 1429 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1430 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1431 #endif 1432 1433 /* Hookup IRQ last. */ 1434 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1435 NULL, bce_intr, sc, &sc->bce_intrhand); 1436 1437 if (rc) { 1438 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1439 __FILE__, __LINE__); 1440 bce_detach(dev); 1441 goto bce_attach_exit; 1442 } 1443 1444 /* 1445 * At this point we've acquired all the resources 1446 * we need to run so there's no turning back, we're 1447 * cleared for launch. 1448 */ 1449 1450 /* Print some important debugging info. */ 1451 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1452 1453 /* Add the supported sysctls to the kernel. */ 1454 bce_add_sysctls(sc); 1455 1456 BCE_LOCK(sc); 1457 1458 /* 1459 * The chip reset earlier notified the bootcode that 1460 * a driver is present. We now need to start our pulse 1461 * routine so that the bootcode is reminded that we're 1462 * still running. 1463 */ 1464 bce_pulse(sc); 1465 1466 bce_mgmt_init_locked(sc); 1467 BCE_UNLOCK(sc); 1468 1469 /* Finally, print some useful adapter info */ 1470 bce_print_adapter_info(sc); 1471 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1472 __FUNCTION__, sc); 1473 1474 goto bce_attach_exit; 1475 1476 bce_attach_fail: 1477 bce_release_resources(sc); 1478 1479 bce_attach_exit: 1480 1481 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1482 1483 return(rc); 1484 } 1485 1486 1487 /****************************************************************************/ 1488 /* Device detach function. */ 1489 /* */ 1490 /* Stops the controller, resets the controller, and releases resources. */ 1491 /* */ 1492 /* Returns: */ 1493 /* 0 on success, positive value on failure. */ 1494 /****************************************************************************/ 1495 static int 1496 bce_detach(device_t dev) 1497 { 1498 struct bce_softc *sc = device_get_softc(dev); 1499 struct ifnet *ifp; 1500 u32 msg; 1501 1502 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1503 1504 ifp = sc->bce_ifp; 1505 1506 /* Stop and reset the controller. */ 1507 BCE_LOCK(sc); 1508 1509 /* Stop the pulse so the bootcode can go to driver absent state. */ 1510 callout_stop(&sc->bce_pulse_callout); 1511 1512 bce_stop(sc); 1513 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1514 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1515 else 1516 msg = BCE_DRV_MSG_CODE_UNLOAD; 1517 bce_reset(sc, msg); 1518 1519 BCE_UNLOCK(sc); 1520 1521 ether_ifdetach(ifp); 1522 1523 /* If we have a child device on the MII bus remove it too. */ 1524 bus_generic_detach(dev); 1525 device_delete_child(dev, sc->bce_miibus); 1526 1527 /* Release all remaining resources. */ 1528 bce_release_resources(sc); 1529 1530 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1531 1532 return(0); 1533 } 1534 1535 1536 /****************************************************************************/ 1537 /* Device shutdown function. */ 1538 /* */ 1539 /* Stops and resets the controller. */ 1540 /* */ 1541 /* Returns: */ 1542 /* 0 on success, positive value on failure. */ 1543 /****************************************************************************/ 1544 static int 1545 bce_shutdown(device_t dev) 1546 { 1547 struct bce_softc *sc = device_get_softc(dev); 1548 u32 msg; 1549 1550 DBENTER(BCE_VERBOSE); 1551 1552 BCE_LOCK(sc); 1553 bce_stop(sc); 1554 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1555 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1556 else 1557 msg = BCE_DRV_MSG_CODE_UNLOAD; 1558 bce_reset(sc, msg); 1559 BCE_UNLOCK(sc); 1560 1561 DBEXIT(BCE_VERBOSE); 1562 1563 return (0); 1564 } 1565 1566 1567 #ifdef BCE_DEBUG 1568 /****************************************************************************/ 1569 /* Register read. */ 1570 /* */ 1571 /* Returns: */ 1572 /* The value of the register. */ 1573 /****************************************************************************/ 1574 static u32 1575 bce_reg_rd(struct bce_softc *sc, u32 offset) 1576 { 1577 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1578 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1579 __FUNCTION__, offset, val); 1580 return val; 1581 } 1582 1583 1584 /****************************************************************************/ 1585 /* Register write (16 bit). */ 1586 /* */ 1587 /* Returns: */ 1588 /* Nothing. */ 1589 /****************************************************************************/ 1590 static void 1591 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1592 { 1593 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1594 __FUNCTION__, offset, val); 1595 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1596 } 1597 1598 1599 /****************************************************************************/ 1600 /* Register write. */ 1601 /* */ 1602 /* Returns: */ 1603 /* Nothing. */ 1604 /****************************************************************************/ 1605 static void 1606 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1607 { 1608 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1609 __FUNCTION__, offset, val); 1610 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1611 } 1612 #endif 1613 1614 /****************************************************************************/ 1615 /* Indirect register read. */ 1616 /* */ 1617 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1618 /* configuration space. Using this mechanism avoids issues with posted */ 1619 /* reads but is much slower than memory-mapped I/O. */ 1620 /* */ 1621 /* Returns: */ 1622 /* The value of the register. */ 1623 /****************************************************************************/ 1624 static u32 1625 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1626 { 1627 device_t dev; 1628 dev = sc->bce_dev; 1629 1630 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1631 #ifdef BCE_DEBUG 1632 { 1633 u32 val; 1634 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1635 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1636 __FUNCTION__, offset, val); 1637 return val; 1638 } 1639 #else 1640 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1641 #endif 1642 } 1643 1644 1645 /****************************************************************************/ 1646 /* Indirect register write. */ 1647 /* */ 1648 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1649 /* configuration space. Using this mechanism avoids issues with posted */ 1650 /* writes but is muchh slower than memory-mapped I/O. */ 1651 /* */ 1652 /* Returns: */ 1653 /* Nothing. */ 1654 /****************************************************************************/ 1655 static void 1656 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1657 { 1658 device_t dev; 1659 dev = sc->bce_dev; 1660 1661 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1662 __FUNCTION__, offset, val); 1663 1664 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1665 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1666 } 1667 1668 1669 /****************************************************************************/ 1670 /* Shared memory write. */ 1671 /* */ 1672 /* Writes NetXtreme II shared memory region. */ 1673 /* */ 1674 /* Returns: */ 1675 /* Nothing. */ 1676 /****************************************************************************/ 1677 static void 1678 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1679 { 1680 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1681 "0x%08X\n", __FUNCTION__, val, offset); 1682 1683 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1684 } 1685 1686 1687 /****************************************************************************/ 1688 /* Shared memory read. */ 1689 /* */ 1690 /* Reads NetXtreme II shared memory region. */ 1691 /* */ 1692 /* Returns: */ 1693 /* The 32 bit value read. */ 1694 /****************************************************************************/ 1695 static u32 1696 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1697 { 1698 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1699 1700 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1701 "0x%08X\n", __FUNCTION__, val, offset); 1702 1703 return val; 1704 } 1705 1706 1707 #ifdef BCE_DEBUG 1708 /****************************************************************************/ 1709 /* Context memory read. */ 1710 /* */ 1711 /* The NetXtreme II controller uses context memory to track connection */ 1712 /* information for L2 and higher network protocols. */ 1713 /* */ 1714 /* Returns: */ 1715 /* The requested 32 bit value of context memory. */ 1716 /****************************************************************************/ 1717 static u32 1718 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1719 { 1720 u32 idx, offset, retry_cnt = 5, val; 1721 1722 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1723 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1724 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1725 1726 offset = ctx_offset + cid_addr; 1727 1728 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1729 1730 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1731 1732 for (idx = 0; idx < retry_cnt; idx++) { 1733 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1734 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1735 break; 1736 DELAY(5); 1737 } 1738 1739 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1740 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1741 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1742 __FILE__, __LINE__, cid_addr, ctx_offset); 1743 1744 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1745 } else { 1746 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1747 val = REG_RD(sc, BCE_CTX_DATA); 1748 } 1749 1750 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1751 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1752 1753 return(val); 1754 } 1755 #endif 1756 1757 1758 /****************************************************************************/ 1759 /* Context memory write. */ 1760 /* */ 1761 /* The NetXtreme II controller uses context memory to track connection */ 1762 /* information for L2 and higher network protocols. */ 1763 /* */ 1764 /* Returns: */ 1765 /* Nothing. */ 1766 /****************************************************************************/ 1767 static void 1768 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1769 { 1770 u32 idx, offset = ctx_offset + cid_addr; 1771 u32 val, retry_cnt = 5; 1772 1773 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1774 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1775 1776 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1777 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1778 __FUNCTION__, cid_addr)); 1779 1780 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1781 1782 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1783 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1784 1785 for (idx = 0; idx < retry_cnt; idx++) { 1786 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1787 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1788 break; 1789 DELAY(5); 1790 } 1791 1792 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1793 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1794 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1795 __FILE__, __LINE__, cid_addr, ctx_offset); 1796 1797 } else { 1798 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1799 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1800 } 1801 } 1802 1803 1804 /****************************************************************************/ 1805 /* PHY register read. */ 1806 /* */ 1807 /* Implements register reads on the MII bus. */ 1808 /* */ 1809 /* Returns: */ 1810 /* The value of the register. */ 1811 /****************************************************************************/ 1812 static int 1813 bce_miibus_read_reg(device_t dev, int phy, int reg) 1814 { 1815 struct bce_softc *sc; 1816 u32 val; 1817 int i; 1818 1819 sc = device_get_softc(dev); 1820 1821 /* Make sure we are accessing the correct PHY address. */ 1822 if (phy != sc->bce_phy_addr) { 1823 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1824 "for PHY read!\n", phy); 1825 return(0); 1826 } 1827 1828 /* 1829 * The 5709S PHY is an IEEE Clause 45 PHY 1830 * with special mappings to work with IEEE 1831 * Clause 22 register accesses. 1832 */ 1833 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1834 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1835 reg += 0x10; 1836 } 1837 1838 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1839 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1840 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1841 1842 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1843 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1844 1845 DELAY(40); 1846 } 1847 1848 1849 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1850 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1851 BCE_EMAC_MDIO_COMM_START_BUSY; 1852 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1853 1854 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1855 DELAY(10); 1856 1857 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1858 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1859 DELAY(5); 1860 1861 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1862 val &= BCE_EMAC_MDIO_COMM_DATA; 1863 1864 break; 1865 } 1866 } 1867 1868 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1869 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1870 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1871 val = 0x0; 1872 } else { 1873 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1874 } 1875 1876 1877 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1878 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1879 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1880 1881 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1882 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1883 1884 DELAY(40); 1885 } 1886 1887 DB_PRINT_PHY_REG(reg, val); 1888 return (val & 0xffff); 1889 1890 } 1891 1892 1893 /****************************************************************************/ 1894 /* PHY register write. */ 1895 /* */ 1896 /* Implements register writes on the MII bus. */ 1897 /* */ 1898 /* Returns: */ 1899 /* The value of the register. */ 1900 /****************************************************************************/ 1901 static int 1902 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1903 { 1904 struct bce_softc *sc; 1905 u32 val1; 1906 int i; 1907 1908 sc = device_get_softc(dev); 1909 1910 /* Make sure we are accessing the correct PHY address. */ 1911 if (phy != sc->bce_phy_addr) { 1912 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1913 "for PHY write!\n", phy); 1914 return(0); 1915 } 1916 1917 DB_PRINT_PHY_REG(reg, val); 1918 1919 /* 1920 * The 5709S PHY is an IEEE Clause 45 PHY 1921 * with special mappings to work with IEEE 1922 * Clause 22 register accesses. 1923 */ 1924 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1925 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1926 reg += 0x10; 1927 } 1928 1929 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1930 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1931 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1932 1933 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1934 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1935 1936 DELAY(40); 1937 } 1938 1939 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1940 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1941 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1942 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1943 1944 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1945 DELAY(10); 1946 1947 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1948 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1949 DELAY(5); 1950 break; 1951 } 1952 } 1953 1954 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1955 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1956 __FILE__, __LINE__); 1957 1958 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1959 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1960 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1961 1962 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1963 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1964 1965 DELAY(40); 1966 } 1967 1968 return 0; 1969 } 1970 1971 1972 /****************************************************************************/ 1973 /* MII bus status change. */ 1974 /* */ 1975 /* Called by the MII bus driver when the PHY establishes link to set the */ 1976 /* MAC interface registers. */ 1977 /* */ 1978 /* Returns: */ 1979 /* Nothing. */ 1980 /****************************************************************************/ 1981 static void 1982 bce_miibus_statchg(device_t dev) 1983 { 1984 struct bce_softc *sc; 1985 struct ifnet *ifp; 1986 struct mii_data *mii; 1987 int val; 1988 1989 sc = device_get_softc(dev); 1990 1991 DBENTER(BCE_VERBOSE_PHY); 1992 1993 ifp = sc->bce_ifp; 1994 mii = device_get_softc(sc->bce_miibus); 1995 if (mii == NULL || ifp == NULL || 1996 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1997 return; 1998 1999 sc->bce_link_up = FALSE; 2000 val = REG_RD(sc, BCE_EMAC_MODE); 2001 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2002 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2003 BCE_EMAC_MODE_25G); 2004 2005 /* Set MII or GMII interface based on the PHY speed. */ 2006 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2007 (IFM_ACTIVE | IFM_AVALID)) { 2008 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2009 case IFM_10_T: 2010 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2011 DBPRINT(sc, BCE_INFO_PHY, 2012 "Enabling 10Mb interface.\n"); 2013 val |= BCE_EMAC_MODE_PORT_MII_10; 2014 sc->bce_link_up = TRUE; 2015 break; 2016 } 2017 /* FALLTHROUGH */ 2018 case IFM_100_TX: 2019 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2020 val |= BCE_EMAC_MODE_PORT_MII; 2021 sc->bce_link_up = TRUE; 2022 break; 2023 case IFM_2500_SX: 2024 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2025 val |= BCE_EMAC_MODE_25G; 2026 /* FALLTHROUGH */ 2027 case IFM_1000_T: 2028 case IFM_1000_SX: 2029 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2030 val |= BCE_EMAC_MODE_PORT_GMII; 2031 sc->bce_link_up = TRUE; 2032 if (bce_verbose || bootverbose) 2033 BCE_PRINTF("Gigabit link up!\n"); 2034 break; 2035 default: 2036 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed.\n"); 2037 break; 2038 } 2039 } 2040 2041 if (sc->bce_link_up == FALSE) 2042 return; 2043 2044 /* Set half or full duplex based on PHY settings. */ 2045 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 2046 DBPRINT(sc, BCE_INFO_PHY, 2047 "Setting Half-Duplex interface.\n"); 2048 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2049 } else 2050 DBPRINT(sc, BCE_INFO_PHY, 2051 "Setting Full-Duplex interface.\n"); 2052 2053 REG_WR(sc, BCE_EMAC_MODE, val); 2054 2055 if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) { 2056 DBPRINT(sc, BCE_INFO_PHY, 2057 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2058 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2059 } else { 2060 DBPRINT(sc, BCE_INFO_PHY, 2061 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2062 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2063 } 2064 2065 if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) { 2066 DBPRINT(sc, BCE_INFO_PHY, 2067 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2068 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2069 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2070 } else { 2071 DBPRINT(sc, BCE_INFO_PHY, 2072 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2073 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2074 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2075 } 2076 2077 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2078 2079 DBEXIT(BCE_VERBOSE_PHY); 2080 } 2081 2082 2083 /****************************************************************************/ 2084 /* Acquire NVRAM lock. */ 2085 /* */ 2086 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2087 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2088 /* for use by the driver. */ 2089 /* */ 2090 /* Returns: */ 2091 /* 0 on success, positive value on failure. */ 2092 /****************************************************************************/ 2093 static int 2094 bce_acquire_nvram_lock(struct bce_softc *sc) 2095 { 2096 u32 val; 2097 int j, rc = 0; 2098 2099 DBENTER(BCE_VERBOSE_NVRAM); 2100 2101 /* Request access to the flash interface. */ 2102 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2103 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2104 val = REG_RD(sc, BCE_NVM_SW_ARB); 2105 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2106 break; 2107 2108 DELAY(5); 2109 } 2110 2111 if (j >= NVRAM_TIMEOUT_COUNT) { 2112 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2113 rc = EBUSY; 2114 } 2115 2116 DBEXIT(BCE_VERBOSE_NVRAM); 2117 return (rc); 2118 } 2119 2120 2121 /****************************************************************************/ 2122 /* Release NVRAM lock. */ 2123 /* */ 2124 /* When the caller is finished accessing NVRAM the lock must be released. */ 2125 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2126 /* for use by the driver. */ 2127 /* */ 2128 /* Returns: */ 2129 /* 0 on success, positive value on failure. */ 2130 /****************************************************************************/ 2131 static int 2132 bce_release_nvram_lock(struct bce_softc *sc) 2133 { 2134 u32 val; 2135 int j, rc = 0; 2136 2137 DBENTER(BCE_VERBOSE_NVRAM); 2138 2139 /* 2140 * Relinquish nvram interface. 2141 */ 2142 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2143 2144 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2145 val = REG_RD(sc, BCE_NVM_SW_ARB); 2146 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2147 break; 2148 2149 DELAY(5); 2150 } 2151 2152 if (j >= NVRAM_TIMEOUT_COUNT) { 2153 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2154 rc = EBUSY; 2155 } 2156 2157 DBEXIT(BCE_VERBOSE_NVRAM); 2158 return (rc); 2159 } 2160 2161 2162 #ifdef BCE_NVRAM_WRITE_SUPPORT 2163 /****************************************************************************/ 2164 /* Enable NVRAM write access. */ 2165 /* */ 2166 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2167 /* */ 2168 /* Returns: */ 2169 /* 0 on success, positive value on failure. */ 2170 /****************************************************************************/ 2171 static int 2172 bce_enable_nvram_write(struct bce_softc *sc) 2173 { 2174 u32 val; 2175 int rc = 0; 2176 2177 DBENTER(BCE_VERBOSE_NVRAM); 2178 2179 val = REG_RD(sc, BCE_MISC_CFG); 2180 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2181 2182 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2183 int j; 2184 2185 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2186 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2187 2188 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2189 DELAY(5); 2190 2191 val = REG_RD(sc, BCE_NVM_COMMAND); 2192 if (val & BCE_NVM_COMMAND_DONE) 2193 break; 2194 } 2195 2196 if (j >= NVRAM_TIMEOUT_COUNT) { 2197 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2198 rc = EBUSY; 2199 } 2200 } 2201 2202 DBENTER(BCE_VERBOSE_NVRAM); 2203 return (rc); 2204 } 2205 2206 2207 /****************************************************************************/ 2208 /* Disable NVRAM write access. */ 2209 /* */ 2210 /* When the caller is finished writing to NVRAM write access must be */ 2211 /* disabled. */ 2212 /* */ 2213 /* Returns: */ 2214 /* Nothing. */ 2215 /****************************************************************************/ 2216 static void 2217 bce_disable_nvram_write(struct bce_softc *sc) 2218 { 2219 u32 val; 2220 2221 DBENTER(BCE_VERBOSE_NVRAM); 2222 2223 val = REG_RD(sc, BCE_MISC_CFG); 2224 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2225 2226 DBEXIT(BCE_VERBOSE_NVRAM); 2227 2228 } 2229 #endif 2230 2231 2232 /****************************************************************************/ 2233 /* Enable NVRAM access. */ 2234 /* */ 2235 /* Before accessing NVRAM for read or write operations the caller must */ 2236 /* enabled NVRAM access. */ 2237 /* */ 2238 /* Returns: */ 2239 /* Nothing. */ 2240 /****************************************************************************/ 2241 static void 2242 bce_enable_nvram_access(struct bce_softc *sc) 2243 { 2244 u32 val; 2245 2246 DBENTER(BCE_VERBOSE_NVRAM); 2247 2248 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2249 /* Enable both bits, even on read. */ 2250 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2251 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2252 2253 DBEXIT(BCE_VERBOSE_NVRAM); 2254 } 2255 2256 2257 /****************************************************************************/ 2258 /* Disable NVRAM access. */ 2259 /* */ 2260 /* When the caller is finished accessing NVRAM access must be disabled. */ 2261 /* */ 2262 /* Returns: */ 2263 /* Nothing. */ 2264 /****************************************************************************/ 2265 static void 2266 bce_disable_nvram_access(struct bce_softc *sc) 2267 { 2268 u32 val; 2269 2270 DBENTER(BCE_VERBOSE_NVRAM); 2271 2272 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2273 2274 /* Disable both bits, even after read. */ 2275 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2276 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2277 2278 DBEXIT(BCE_VERBOSE_NVRAM); 2279 } 2280 2281 2282 #ifdef BCE_NVRAM_WRITE_SUPPORT 2283 /****************************************************************************/ 2284 /* Erase NVRAM page before writing. */ 2285 /* */ 2286 /* Non-buffered flash parts require that a page be erased before it is */ 2287 /* written. */ 2288 /* */ 2289 /* Returns: */ 2290 /* 0 on success, positive value on failure. */ 2291 /****************************************************************************/ 2292 static int 2293 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2294 { 2295 u32 cmd; 2296 int j, rc = 0; 2297 2298 DBENTER(BCE_VERBOSE_NVRAM); 2299 2300 /* Buffered flash doesn't require an erase. */ 2301 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2302 goto bce_nvram_erase_page_exit; 2303 2304 /* Build an erase command. */ 2305 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2306 BCE_NVM_COMMAND_DOIT; 2307 2308 /* 2309 * Clear the DONE bit separately, set the NVRAM adress to erase, 2310 * and issue the erase command. 2311 */ 2312 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2313 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2314 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2315 2316 /* Wait for completion. */ 2317 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2318 u32 val; 2319 2320 DELAY(5); 2321 2322 val = REG_RD(sc, BCE_NVM_COMMAND); 2323 if (val & BCE_NVM_COMMAND_DONE) 2324 break; 2325 } 2326 2327 if (j >= NVRAM_TIMEOUT_COUNT) { 2328 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2329 rc = EBUSY; 2330 } 2331 2332 bce_nvram_erase_page_exit: 2333 DBEXIT(BCE_VERBOSE_NVRAM); 2334 return (rc); 2335 } 2336 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2337 2338 2339 /****************************************************************************/ 2340 /* Read a dword (32 bits) from NVRAM. */ 2341 /* */ 2342 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2343 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2344 /* */ 2345 /* Returns: */ 2346 /* 0 on success and the 32 bit value read, positive value on failure. */ 2347 /****************************************************************************/ 2348 static int 2349 bce_nvram_read_dword(struct bce_softc *sc, 2350 u32 offset, u8 *ret_val, u32 cmd_flags) 2351 { 2352 u32 cmd; 2353 int i, rc = 0; 2354 2355 DBENTER(BCE_EXTREME_NVRAM); 2356 2357 /* Build the command word. */ 2358 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2359 2360 /* Calculate the offset for buffered flash if translation is used. */ 2361 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2362 offset = ((offset / sc->bce_flash_info->page_size) << 2363 sc->bce_flash_info->page_bits) + 2364 (offset % sc->bce_flash_info->page_size); 2365 } 2366 2367 /* 2368 * Clear the DONE bit separately, set the address to read, 2369 * and issue the read. 2370 */ 2371 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2372 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2373 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2374 2375 /* Wait for completion. */ 2376 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2377 u32 val; 2378 2379 DELAY(5); 2380 2381 val = REG_RD(sc, BCE_NVM_COMMAND); 2382 if (val & BCE_NVM_COMMAND_DONE) { 2383 val = REG_RD(sc, BCE_NVM_READ); 2384 2385 val = bce_be32toh(val); 2386 memcpy(ret_val, &val, 4); 2387 break; 2388 } 2389 } 2390 2391 /* Check for errors. */ 2392 if (i >= NVRAM_TIMEOUT_COUNT) { 2393 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2394 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2395 rc = EBUSY; 2396 } 2397 2398 DBEXIT(BCE_EXTREME_NVRAM); 2399 return(rc); 2400 } 2401 2402 2403 #ifdef BCE_NVRAM_WRITE_SUPPORT 2404 /****************************************************************************/ 2405 /* Write a dword (32 bits) to NVRAM. */ 2406 /* */ 2407 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2408 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2409 /* enabled NVRAM write access. */ 2410 /* */ 2411 /* Returns: */ 2412 /* 0 on success, positive value on failure. */ 2413 /****************************************************************************/ 2414 static int 2415 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2416 u32 cmd_flags) 2417 { 2418 u32 cmd, val32; 2419 int j, rc = 0; 2420 2421 DBENTER(BCE_VERBOSE_NVRAM); 2422 2423 /* Build the command word. */ 2424 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2425 2426 /* Calculate the offset for buffered flash if translation is used. */ 2427 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2428 offset = ((offset / sc->bce_flash_info->page_size) << 2429 sc->bce_flash_info->page_bits) + 2430 (offset % sc->bce_flash_info->page_size); 2431 } 2432 2433 /* 2434 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2435 * set the NVRAM address to write, and issue the write command 2436 */ 2437 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2438 memcpy(&val32, val, 4); 2439 val32 = htobe32(val32); 2440 REG_WR(sc, BCE_NVM_WRITE, val32); 2441 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2442 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2443 2444 /* Wait for completion. */ 2445 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2446 DELAY(5); 2447 2448 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2449 break; 2450 } 2451 if (j >= NVRAM_TIMEOUT_COUNT) { 2452 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2453 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2454 rc = EBUSY; 2455 } 2456 2457 DBEXIT(BCE_VERBOSE_NVRAM); 2458 return (rc); 2459 } 2460 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2461 2462 2463 /****************************************************************************/ 2464 /* Initialize NVRAM access. */ 2465 /* */ 2466 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2467 /* access that device. */ 2468 /* */ 2469 /* Returns: */ 2470 /* 0 on success, positive value on failure. */ 2471 /****************************************************************************/ 2472 static int 2473 bce_init_nvram(struct bce_softc *sc) 2474 { 2475 u32 val; 2476 int j, entry_count, rc = 0; 2477 struct flash_spec *flash; 2478 2479 DBENTER(BCE_VERBOSE_NVRAM); 2480 2481 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2482 sc->bce_flash_info = &flash_5709; 2483 goto bce_init_nvram_get_flash_size; 2484 } 2485 2486 /* Determine the selected interface. */ 2487 val = REG_RD(sc, BCE_NVM_CFG1); 2488 2489 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2490 2491 /* 2492 * Flash reconfiguration is required to support additional 2493 * NVRAM devices not directly supported in hardware. 2494 * Check if the flash interface was reconfigured 2495 * by the bootcode. 2496 */ 2497 2498 if (val & 0x40000000) { 2499 /* Flash interface reconfigured by bootcode. */ 2500 2501 DBPRINT(sc,BCE_INFO_LOAD, 2502 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2503 2504 for (j = 0, flash = &flash_table[0]; j < entry_count; 2505 j++, flash++) { 2506 if ((val & FLASH_BACKUP_STRAP_MASK) == 2507 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2508 sc->bce_flash_info = flash; 2509 break; 2510 } 2511 } 2512 } else { 2513 /* Flash interface not yet reconfigured. */ 2514 u32 mask; 2515 2516 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2517 __FUNCTION__); 2518 2519 if (val & (1 << 23)) 2520 mask = FLASH_BACKUP_STRAP_MASK; 2521 else 2522 mask = FLASH_STRAP_MASK; 2523 2524 /* Look for the matching NVRAM device configuration data. */ 2525 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2526 2527 /* Check if the device matches any of the known devices. */ 2528 if ((val & mask) == (flash->strapping & mask)) { 2529 /* Found a device match. */ 2530 sc->bce_flash_info = flash; 2531 2532 /* Request access to the flash interface. */ 2533 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2534 return rc; 2535 2536 /* Reconfigure the flash interface. */ 2537 bce_enable_nvram_access(sc); 2538 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2539 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2540 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2541 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2542 bce_disable_nvram_access(sc); 2543 bce_release_nvram_lock(sc); 2544 2545 break; 2546 } 2547 } 2548 } 2549 2550 /* Check if a matching device was found. */ 2551 if (j == entry_count) { 2552 sc->bce_flash_info = NULL; 2553 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2554 __FILE__, __LINE__); 2555 DBEXIT(BCE_VERBOSE_NVRAM); 2556 return (ENODEV); 2557 } 2558 2559 bce_init_nvram_get_flash_size: 2560 /* Write the flash config data to the shared memory interface. */ 2561 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2562 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2563 if (val) 2564 sc->bce_flash_size = val; 2565 else 2566 sc->bce_flash_size = sc->bce_flash_info->total_size; 2567 2568 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2569 __FUNCTION__, sc->bce_flash_info->name, 2570 sc->bce_flash_info->total_size); 2571 2572 DBEXIT(BCE_VERBOSE_NVRAM); 2573 return rc; 2574 } 2575 2576 2577 /****************************************************************************/ 2578 /* Read an arbitrary range of data from NVRAM. */ 2579 /* */ 2580 /* Prepares the NVRAM interface for access and reads the requested data */ 2581 /* into the supplied buffer. */ 2582 /* */ 2583 /* Returns: */ 2584 /* 0 on success and the data read, positive value on failure. */ 2585 /****************************************************************************/ 2586 static int 2587 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2588 int buf_size) 2589 { 2590 int rc = 0; 2591 u32 cmd_flags, offset32, len32, extra; 2592 2593 DBENTER(BCE_VERBOSE_NVRAM); 2594 2595 if (buf_size == 0) 2596 goto bce_nvram_read_exit; 2597 2598 /* Request access to the flash interface. */ 2599 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2600 goto bce_nvram_read_exit; 2601 2602 /* Enable access to flash interface */ 2603 bce_enable_nvram_access(sc); 2604 2605 len32 = buf_size; 2606 offset32 = offset; 2607 extra = 0; 2608 2609 cmd_flags = 0; 2610 2611 if (offset32 & 3) { 2612 u8 buf[4]; 2613 u32 pre_len; 2614 2615 offset32 &= ~3; 2616 pre_len = 4 - (offset & 3); 2617 2618 if (pre_len >= len32) { 2619 pre_len = len32; 2620 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2621 } 2622 else { 2623 cmd_flags = BCE_NVM_COMMAND_FIRST; 2624 } 2625 2626 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2627 2628 if (rc) 2629 return rc; 2630 2631 memcpy(ret_buf, buf + (offset & 3), pre_len); 2632 2633 offset32 += 4; 2634 ret_buf += pre_len; 2635 len32 -= pre_len; 2636 } 2637 2638 if (len32 & 3) { 2639 extra = 4 - (len32 & 3); 2640 len32 = (len32 + 4) & ~3; 2641 } 2642 2643 if (len32 == 4) { 2644 u8 buf[4]; 2645 2646 if (cmd_flags) 2647 cmd_flags = BCE_NVM_COMMAND_LAST; 2648 else 2649 cmd_flags = BCE_NVM_COMMAND_FIRST | 2650 BCE_NVM_COMMAND_LAST; 2651 2652 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2653 2654 memcpy(ret_buf, buf, 4 - extra); 2655 } 2656 else if (len32 > 0) { 2657 u8 buf[4]; 2658 2659 /* Read the first word. */ 2660 if (cmd_flags) 2661 cmd_flags = 0; 2662 else 2663 cmd_flags = BCE_NVM_COMMAND_FIRST; 2664 2665 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2666 2667 /* Advance to the next dword. */ 2668 offset32 += 4; 2669 ret_buf += 4; 2670 len32 -= 4; 2671 2672 while (len32 > 4 && rc == 0) { 2673 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2674 2675 /* Advance to the next dword. */ 2676 offset32 += 4; 2677 ret_buf += 4; 2678 len32 -= 4; 2679 } 2680 2681 if (rc) 2682 goto bce_nvram_read_locked_exit; 2683 2684 cmd_flags = BCE_NVM_COMMAND_LAST; 2685 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2686 2687 memcpy(ret_buf, buf, 4 - extra); 2688 } 2689 2690 bce_nvram_read_locked_exit: 2691 /* Disable access to flash interface and release the lock. */ 2692 bce_disable_nvram_access(sc); 2693 bce_release_nvram_lock(sc); 2694 2695 bce_nvram_read_exit: 2696 DBEXIT(BCE_VERBOSE_NVRAM); 2697 return rc; 2698 } 2699 2700 2701 #ifdef BCE_NVRAM_WRITE_SUPPORT 2702 /****************************************************************************/ 2703 /* Write an arbitrary range of data from NVRAM. */ 2704 /* */ 2705 /* Prepares the NVRAM interface for write access and writes the requested */ 2706 /* data from the supplied buffer. The caller is responsible for */ 2707 /* calculating any appropriate CRCs. */ 2708 /* */ 2709 /* Returns: */ 2710 /* 0 on success, positive value on failure. */ 2711 /****************************************************************************/ 2712 static int 2713 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2714 int buf_size) 2715 { 2716 u32 written, offset32, len32; 2717 u8 *buf, start[4], end[4]; 2718 int rc = 0; 2719 int align_start, align_end; 2720 2721 DBENTER(BCE_VERBOSE_NVRAM); 2722 2723 buf = data_buf; 2724 offset32 = offset; 2725 len32 = buf_size; 2726 align_start = align_end = 0; 2727 2728 if ((align_start = (offset32 & 3))) { 2729 offset32 &= ~3; 2730 len32 += align_start; 2731 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2732 goto bce_nvram_write_exit; 2733 } 2734 2735 if (len32 & 3) { 2736 if ((len32 > 4) || !align_start) { 2737 align_end = 4 - (len32 & 3); 2738 len32 += align_end; 2739 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2740 end, 4))) { 2741 goto bce_nvram_write_exit; 2742 } 2743 } 2744 } 2745 2746 if (align_start || align_end) { 2747 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2748 if (buf == 0) { 2749 rc = ENOMEM; 2750 goto bce_nvram_write_exit; 2751 } 2752 2753 if (align_start) { 2754 memcpy(buf, start, 4); 2755 } 2756 2757 if (align_end) { 2758 memcpy(buf + len32 - 4, end, 4); 2759 } 2760 memcpy(buf + align_start, data_buf, buf_size); 2761 } 2762 2763 written = 0; 2764 while ((written < len32) && (rc == 0)) { 2765 u32 page_start, page_end, data_start, data_end; 2766 u32 addr, cmd_flags; 2767 int i; 2768 u8 flash_buffer[264]; 2769 2770 /* Find the page_start addr */ 2771 page_start = offset32 + written; 2772 page_start -= (page_start % sc->bce_flash_info->page_size); 2773 /* Find the page_end addr */ 2774 page_end = page_start + sc->bce_flash_info->page_size; 2775 /* Find the data_start addr */ 2776 data_start = (written == 0) ? offset32 : page_start; 2777 /* Find the data_end addr */ 2778 data_end = (page_end > offset32 + len32) ? 2779 (offset32 + len32) : page_end; 2780 2781 /* Request access to the flash interface. */ 2782 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2783 goto bce_nvram_write_exit; 2784 2785 /* Enable access to flash interface */ 2786 bce_enable_nvram_access(sc); 2787 2788 cmd_flags = BCE_NVM_COMMAND_FIRST; 2789 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2790 int j; 2791 2792 /* Read the whole page into the buffer 2793 * (non-buffer flash only) */ 2794 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2795 if (j == (sc->bce_flash_info->page_size - 4)) { 2796 cmd_flags |= BCE_NVM_COMMAND_LAST; 2797 } 2798 rc = bce_nvram_read_dword(sc, 2799 page_start + j, 2800 &flash_buffer[j], 2801 cmd_flags); 2802 2803 if (rc) 2804 goto bce_nvram_write_locked_exit; 2805 2806 cmd_flags = 0; 2807 } 2808 } 2809 2810 /* Enable writes to flash interface (unlock write-protect) */ 2811 if ((rc = bce_enable_nvram_write(sc)) != 0) 2812 goto bce_nvram_write_locked_exit; 2813 2814 /* Erase the page */ 2815 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2816 goto bce_nvram_write_locked_exit; 2817 2818 /* Re-enable the write again for the actual write */ 2819 bce_enable_nvram_write(sc); 2820 2821 /* Loop to write back the buffer data from page_start to 2822 * data_start */ 2823 i = 0; 2824 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2825 for (addr = page_start; addr < data_start; 2826 addr += 4, i += 4) { 2827 2828 rc = bce_nvram_write_dword(sc, addr, 2829 &flash_buffer[i], cmd_flags); 2830 2831 if (rc != 0) 2832 goto bce_nvram_write_locked_exit; 2833 2834 cmd_flags = 0; 2835 } 2836 } 2837 2838 /* Loop to write the new data from data_start to data_end */ 2839 for (addr = data_start; addr < data_end; addr += 4, i++) { 2840 if ((addr == page_end - 4) || 2841 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2842 (addr == data_end - 4))) { 2843 2844 cmd_flags |= BCE_NVM_COMMAND_LAST; 2845 } 2846 rc = bce_nvram_write_dword(sc, addr, buf, 2847 cmd_flags); 2848 2849 if (rc != 0) 2850 goto bce_nvram_write_locked_exit; 2851 2852 cmd_flags = 0; 2853 buf += 4; 2854 } 2855 2856 /* Loop to write back the buffer data from data_end 2857 * to page_end */ 2858 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2859 for (addr = data_end; addr < page_end; 2860 addr += 4, i += 4) { 2861 2862 if (addr == page_end-4) { 2863 cmd_flags = BCE_NVM_COMMAND_LAST; 2864 } 2865 rc = bce_nvram_write_dword(sc, addr, 2866 &flash_buffer[i], cmd_flags); 2867 2868 if (rc != 0) 2869 goto bce_nvram_write_locked_exit; 2870 2871 cmd_flags = 0; 2872 } 2873 } 2874 2875 /* Disable writes to flash interface (lock write-protect) */ 2876 bce_disable_nvram_write(sc); 2877 2878 /* Disable access to flash interface */ 2879 bce_disable_nvram_access(sc); 2880 bce_release_nvram_lock(sc); 2881 2882 /* Increment written */ 2883 written += data_end - data_start; 2884 } 2885 2886 goto bce_nvram_write_exit; 2887 2888 bce_nvram_write_locked_exit: 2889 bce_disable_nvram_write(sc); 2890 bce_disable_nvram_access(sc); 2891 bce_release_nvram_lock(sc); 2892 2893 bce_nvram_write_exit: 2894 if (align_start || align_end) 2895 free(buf, M_DEVBUF); 2896 2897 DBEXIT(BCE_VERBOSE_NVRAM); 2898 return (rc); 2899 } 2900 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2901 2902 2903 /****************************************************************************/ 2904 /* Verifies that NVRAM is accessible and contains valid data. */ 2905 /* */ 2906 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2907 /* correct. */ 2908 /* */ 2909 /* Returns: */ 2910 /* 0 on success, positive value on failure. */ 2911 /****************************************************************************/ 2912 static int 2913 bce_nvram_test(struct bce_softc *sc) 2914 { 2915 u32 buf[BCE_NVRAM_SIZE / 4]; 2916 u8 *data = (u8 *) buf; 2917 int rc = 0; 2918 u32 magic, csum; 2919 2920 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2921 2922 /* 2923 * Check that the device NVRAM is valid by reading 2924 * the magic value at offset 0. 2925 */ 2926 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2927 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2928 __FILE__, __LINE__); 2929 goto bce_nvram_test_exit; 2930 } 2931 2932 /* 2933 * Verify that offset 0 of the NVRAM contains 2934 * a valid magic number. 2935 */ 2936 magic = bce_be32toh(buf[0]); 2937 if (magic != BCE_NVRAM_MAGIC) { 2938 rc = ENODEV; 2939 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2940 "Expected: 0x%08X, Found: 0x%08X\n", 2941 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2942 goto bce_nvram_test_exit; 2943 } 2944 2945 /* 2946 * Verify that the device NVRAM includes valid 2947 * configuration data. 2948 */ 2949 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2950 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2951 "Information from NVRAM!\n", __FILE__, __LINE__); 2952 goto bce_nvram_test_exit; 2953 } 2954 2955 csum = ether_crc32_le(data, 0x100); 2956 if (csum != BCE_CRC32_RESIDUAL) { 2957 rc = ENODEV; 2958 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2959 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2960 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2961 goto bce_nvram_test_exit; 2962 } 2963 2964 csum = ether_crc32_le(data + 0x100, 0x100); 2965 if (csum != BCE_CRC32_RESIDUAL) { 2966 rc = ENODEV; 2967 BCE_PRINTF("%s(%d): Invalid feature configuration " 2968 "information NVRAM CRC! Expected: 0x%08X, " 2969 "Found: 08%08X\n", __FILE__, __LINE__, 2970 BCE_CRC32_RESIDUAL, csum); 2971 } 2972 2973 bce_nvram_test_exit: 2974 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2975 return rc; 2976 } 2977 2978 2979 /****************************************************************************/ 2980 /* Calculates the size of the buffers to allocate based on the MTU. */ 2981 /* */ 2982 /* Returns: */ 2983 /* Nothing. */ 2984 /****************************************************************************/ 2985 static void 2986 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 2987 { 2988 DBENTER(BCE_VERBOSE_LOAD); 2989 2990 /* Use a single allocation type when header splitting enabled. */ 2991 if (bce_hdr_split == TRUE) { 2992 sc->rx_bd_mbuf_alloc_size = MHLEN; 2993 /* Make sure offset is 16 byte aligned for hardware. */ 2994 sc->rx_bd_mbuf_align_pad = 2995 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 2996 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 2997 sc->rx_bd_mbuf_align_pad; 2998 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 2999 } else { 3000 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 3001 ETHER_CRC_LEN) > MCLBYTES) { 3002 /* Setup for jumbo RX buffer allocations. */ 3003 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 3004 sc->rx_bd_mbuf_align_pad = 3005 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3006 sc->rx_bd_mbuf_data_len = 3007 sc->rx_bd_mbuf_alloc_size - 3008 sc->rx_bd_mbuf_align_pad; 3009 } else { 3010 /* Setup for standard RX buffer allocations. */ 3011 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3012 sc->rx_bd_mbuf_align_pad = 3013 roundup2(MCLBYTES, 16) - MCLBYTES; 3014 sc->rx_bd_mbuf_data_len = 3015 sc->rx_bd_mbuf_alloc_size - 3016 sc->rx_bd_mbuf_align_pad; 3017 } 3018 } 3019 3020 // DBPRINT(sc, BCE_INFO_LOAD, 3021 DBPRINT(sc, BCE_WARN, 3022 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3023 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3024 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3025 sc->rx_bd_mbuf_align_pad); 3026 3027 DBEXIT(BCE_VERBOSE_LOAD); 3028 3029 } 3030 3031 /****************************************************************************/ 3032 /* Identifies the current media type of the controller and sets the PHY */ 3033 /* address. */ 3034 /* */ 3035 /* Returns: */ 3036 /* Nothing. */ 3037 /****************************************************************************/ 3038 static void 3039 bce_get_media(struct bce_softc *sc) 3040 { 3041 u32 val; 3042 3043 DBENTER(BCE_VERBOSE_PHY); 3044 3045 /* Assume PHY address for copper controllers. */ 3046 sc->bce_phy_addr = 1; 3047 3048 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3049 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3050 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3051 u32 strap; 3052 3053 /* 3054 * The BCM5709S is software configurable 3055 * for Copper or SerDes operation. 3056 */ 3057 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3058 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3059 "for copper.\n"); 3060 goto bce_get_media_exit; 3061 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3062 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3063 "for dual media.\n"); 3064 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3065 goto bce_get_media_exit; 3066 } 3067 3068 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3069 strap = (val & 3070 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3071 else 3072 strap = (val & 3073 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3074 3075 if (pci_get_function(sc->bce_dev) == 0) { 3076 switch (strap) { 3077 case 0x4: 3078 case 0x5: 3079 case 0x6: 3080 DBPRINT(sc, BCE_INFO_LOAD, 3081 "BCM5709 s/w configured for SerDes.\n"); 3082 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3083 break; 3084 default: 3085 DBPRINT(sc, BCE_INFO_LOAD, 3086 "BCM5709 s/w configured for Copper.\n"); 3087 break; 3088 } 3089 } else { 3090 switch (strap) { 3091 case 0x1: 3092 case 0x2: 3093 case 0x4: 3094 DBPRINT(sc, BCE_INFO_LOAD, 3095 "BCM5709 s/w configured for SerDes.\n"); 3096 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3097 break; 3098 default: 3099 DBPRINT(sc, BCE_INFO_LOAD, 3100 "BCM5709 s/w configured for Copper.\n"); 3101 break; 3102 } 3103 } 3104 3105 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3106 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3107 3108 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3109 3110 sc->bce_flags |= BCE_NO_WOL_FLAG; 3111 3112 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3113 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3114 3115 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3116 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3117 sc->bce_phy_addr = 2; 3118 3119 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3120 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3121 sc->bce_phy_flags |= 3122 BCE_PHY_2_5G_CAPABLE_FLAG; 3123 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3124 "capable adapter\n"); 3125 } 3126 } 3127 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3128 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3129 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3130 3131 bce_get_media_exit: 3132 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3133 "Using PHY address %d.\n", sc->bce_phy_addr); 3134 3135 DBEXIT(BCE_VERBOSE_PHY); 3136 } 3137 3138 3139 /****************************************************************************/ 3140 /* Performs PHY initialization required before MII drivers access the */ 3141 /* device. */ 3142 /* */ 3143 /* Returns: */ 3144 /* Nothing. */ 3145 /****************************************************************************/ 3146 static void 3147 bce_init_media(struct bce_softc *sc) 3148 { 3149 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 3150 /* 3151 * Configure 5709S/5716S PHYs to use traditional IEEE 3152 * Clause 22 method. Otherwise we have no way to attach 3153 * the PHY in mii(4) layer. PHY specific configuration 3154 * is done in mii layer. 3155 */ 3156 3157 /* Select auto-negotiation MMD of the PHY. */ 3158 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3159 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3160 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3161 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3162 3163 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3164 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3165 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3166 } 3167 } 3168 3169 3170 /****************************************************************************/ 3171 /* Free any DMA memory owned by the driver. */ 3172 /* */ 3173 /* Scans through each data structre that requires DMA memory and frees */ 3174 /* the memory if allocated. */ 3175 /* */ 3176 /* Returns: */ 3177 /* Nothing. */ 3178 /****************************************************************************/ 3179 static void 3180 bce_dma_free(struct bce_softc *sc) 3181 { 3182 int i; 3183 3184 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3185 3186 /* Free, unmap, and destroy the status block. */ 3187 if (sc->status_block != NULL) { 3188 bus_dmamem_free( 3189 sc->status_tag, 3190 sc->status_block, 3191 sc->status_map); 3192 sc->status_block = NULL; 3193 } 3194 3195 if (sc->status_map != NULL) { 3196 bus_dmamap_unload( 3197 sc->status_tag, 3198 sc->status_map); 3199 bus_dmamap_destroy(sc->status_tag, 3200 sc->status_map); 3201 sc->status_map = NULL; 3202 } 3203 3204 if (sc->status_tag != NULL) { 3205 bus_dma_tag_destroy(sc->status_tag); 3206 sc->status_tag = NULL; 3207 } 3208 3209 3210 /* Free, unmap, and destroy the statistics block. */ 3211 if (sc->stats_block != NULL) { 3212 bus_dmamem_free( 3213 sc->stats_tag, 3214 sc->stats_block, 3215 sc->stats_map); 3216 sc->stats_block = NULL; 3217 } 3218 3219 if (sc->stats_map != NULL) { 3220 bus_dmamap_unload( 3221 sc->stats_tag, 3222 sc->stats_map); 3223 bus_dmamap_destroy(sc->stats_tag, 3224 sc->stats_map); 3225 sc->stats_map = NULL; 3226 } 3227 3228 if (sc->stats_tag != NULL) { 3229 bus_dma_tag_destroy(sc->stats_tag); 3230 sc->stats_tag = NULL; 3231 } 3232 3233 3234 /* Free, unmap and destroy all context memory pages. */ 3235 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3236 for (i = 0; i < sc->ctx_pages; i++ ) { 3237 if (sc->ctx_block[i] != NULL) { 3238 bus_dmamem_free( 3239 sc->ctx_tag, 3240 sc->ctx_block[i], 3241 sc->ctx_map[i]); 3242 sc->ctx_block[i] = NULL; 3243 } 3244 3245 if (sc->ctx_map[i] != NULL) { 3246 bus_dmamap_unload( 3247 sc->ctx_tag, 3248 sc->ctx_map[i]); 3249 bus_dmamap_destroy( 3250 sc->ctx_tag, 3251 sc->ctx_map[i]); 3252 sc->ctx_map[i] = NULL; 3253 } 3254 } 3255 3256 /* Destroy the context memory tag. */ 3257 if (sc->ctx_tag != NULL) { 3258 bus_dma_tag_destroy(sc->ctx_tag); 3259 sc->ctx_tag = NULL; 3260 } 3261 } 3262 3263 3264 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3265 for (i = 0; i < sc->tx_pages; i++ ) { 3266 if (sc->tx_bd_chain[i] != NULL) { 3267 bus_dmamem_free( 3268 sc->tx_bd_chain_tag, 3269 sc->tx_bd_chain[i], 3270 sc->tx_bd_chain_map[i]); 3271 sc->tx_bd_chain[i] = NULL; 3272 } 3273 3274 if (sc->tx_bd_chain_map[i] != NULL) { 3275 bus_dmamap_unload( 3276 sc->tx_bd_chain_tag, 3277 sc->tx_bd_chain_map[i]); 3278 bus_dmamap_destroy( 3279 sc->tx_bd_chain_tag, 3280 sc->tx_bd_chain_map[i]); 3281 sc->tx_bd_chain_map[i] = NULL; 3282 } 3283 } 3284 3285 /* Destroy the TX buffer descriptor tag. */ 3286 if (sc->tx_bd_chain_tag != NULL) { 3287 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3288 sc->tx_bd_chain_tag = NULL; 3289 } 3290 3291 3292 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3293 for (i = 0; i < sc->rx_pages; i++ ) { 3294 if (sc->rx_bd_chain[i] != NULL) { 3295 bus_dmamem_free( 3296 sc->rx_bd_chain_tag, 3297 sc->rx_bd_chain[i], 3298 sc->rx_bd_chain_map[i]); 3299 sc->rx_bd_chain[i] = NULL; 3300 } 3301 3302 if (sc->rx_bd_chain_map[i] != NULL) { 3303 bus_dmamap_unload( 3304 sc->rx_bd_chain_tag, 3305 sc->rx_bd_chain_map[i]); 3306 bus_dmamap_destroy( 3307 sc->rx_bd_chain_tag, 3308 sc->rx_bd_chain_map[i]); 3309 sc->rx_bd_chain_map[i] = NULL; 3310 } 3311 } 3312 3313 /* Destroy the RX buffer descriptor tag. */ 3314 if (sc->rx_bd_chain_tag != NULL) { 3315 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3316 sc->rx_bd_chain_tag = NULL; 3317 } 3318 3319 3320 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3321 if (bce_hdr_split == TRUE) { 3322 for (i = 0; i < sc->pg_pages; i++ ) { 3323 if (sc->pg_bd_chain[i] != NULL) { 3324 bus_dmamem_free( 3325 sc->pg_bd_chain_tag, 3326 sc->pg_bd_chain[i], 3327 sc->pg_bd_chain_map[i]); 3328 sc->pg_bd_chain[i] = NULL; 3329 } 3330 3331 if (sc->pg_bd_chain_map[i] != NULL) { 3332 bus_dmamap_unload( 3333 sc->pg_bd_chain_tag, 3334 sc->pg_bd_chain_map[i]); 3335 bus_dmamap_destroy( 3336 sc->pg_bd_chain_tag, 3337 sc->pg_bd_chain_map[i]); 3338 sc->pg_bd_chain_map[i] = NULL; 3339 } 3340 } 3341 3342 /* Destroy the page buffer descriptor tag. */ 3343 if (sc->pg_bd_chain_tag != NULL) { 3344 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3345 sc->pg_bd_chain_tag = NULL; 3346 } 3347 } 3348 3349 3350 /* Unload and destroy the TX mbuf maps. */ 3351 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3352 if (sc->tx_mbuf_map[i] != NULL) { 3353 bus_dmamap_unload(sc->tx_mbuf_tag, 3354 sc->tx_mbuf_map[i]); 3355 bus_dmamap_destroy(sc->tx_mbuf_tag, 3356 sc->tx_mbuf_map[i]); 3357 sc->tx_mbuf_map[i] = NULL; 3358 } 3359 } 3360 3361 /* Destroy the TX mbuf tag. */ 3362 if (sc->tx_mbuf_tag != NULL) { 3363 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3364 sc->tx_mbuf_tag = NULL; 3365 } 3366 3367 /* Unload and destroy the RX mbuf maps. */ 3368 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3369 if (sc->rx_mbuf_map[i] != NULL) { 3370 bus_dmamap_unload(sc->rx_mbuf_tag, 3371 sc->rx_mbuf_map[i]); 3372 bus_dmamap_destroy(sc->rx_mbuf_tag, 3373 sc->rx_mbuf_map[i]); 3374 sc->rx_mbuf_map[i] = NULL; 3375 } 3376 } 3377 3378 /* Destroy the RX mbuf tag. */ 3379 if (sc->rx_mbuf_tag != NULL) { 3380 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3381 sc->rx_mbuf_tag = NULL; 3382 } 3383 3384 /* Unload and destroy the page mbuf maps. */ 3385 if (bce_hdr_split == TRUE) { 3386 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3387 if (sc->pg_mbuf_map[i] != NULL) { 3388 bus_dmamap_unload(sc->pg_mbuf_tag, 3389 sc->pg_mbuf_map[i]); 3390 bus_dmamap_destroy(sc->pg_mbuf_tag, 3391 sc->pg_mbuf_map[i]); 3392 sc->pg_mbuf_map[i] = NULL; 3393 } 3394 } 3395 3396 /* Destroy the page mbuf tag. */ 3397 if (sc->pg_mbuf_tag != NULL) { 3398 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3399 sc->pg_mbuf_tag = NULL; 3400 } 3401 } 3402 3403 /* Destroy the parent tag */ 3404 if (sc->parent_tag != NULL) { 3405 bus_dma_tag_destroy(sc->parent_tag); 3406 sc->parent_tag = NULL; 3407 } 3408 3409 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3410 } 3411 3412 3413 /****************************************************************************/ 3414 /* Get DMA memory from the OS. */ 3415 /* */ 3416 /* Validates that the OS has provided DMA buffers in response to a */ 3417 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3418 /* When the callback is used the OS will return 0 for the mapping function */ 3419 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3420 /* failures back to the caller. */ 3421 /* */ 3422 /* Returns: */ 3423 /* Nothing. */ 3424 /****************************************************************************/ 3425 static void 3426 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3427 { 3428 bus_addr_t *busaddr = arg; 3429 3430 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3431 __FUNCTION__, nseg)); 3432 /* Simulate a mapping failure. */ 3433 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3434 error = ENOMEM); 3435 3436 /* ToDo: How to increment debug sim_count variable here? */ 3437 3438 /* Check for an error and signal the caller that an error occurred. */ 3439 if (error) { 3440 *busaddr = 0; 3441 } else { 3442 *busaddr = segs->ds_addr; 3443 } 3444 3445 return; 3446 } 3447 3448 3449 /****************************************************************************/ 3450 /* Allocate any DMA memory needed by the driver. */ 3451 /* */ 3452 /* Allocates DMA memory needed for the various global structures needed by */ 3453 /* hardware. */ 3454 /* */ 3455 /* Memory alignment requirements: */ 3456 /* +-----------------+----------+----------+----------+----------+ */ 3457 /* | | 5706 | 5708 | 5709 | 5716 | */ 3458 /* +-----------------+----------+----------+----------+----------+ */ 3459 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3460 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3461 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3462 /* |PG Buffers | none | none | none | none | */ 3463 /* |TX Buffers | none | none | none | none | */ 3464 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3465 /* |Context Memory | | | | | */ 3466 /* +-----------------+----------+----------+----------+----------+ */ 3467 /* */ 3468 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3469 /* */ 3470 /* Returns: */ 3471 /* 0 for success, positive value for failure. */ 3472 /****************************************************************************/ 3473 static int 3474 bce_dma_alloc(device_t dev) 3475 { 3476 struct bce_softc *sc; 3477 int i, error, rc = 0; 3478 bus_size_t max_size, max_seg_size; 3479 int max_segments; 3480 3481 sc = device_get_softc(dev); 3482 3483 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3484 3485 /* 3486 * Allocate the parent bus DMA tag appropriate for PCI. 3487 */ 3488 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3489 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3490 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3491 &sc->parent_tag)) { 3492 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3493 __FILE__, __LINE__); 3494 rc = ENOMEM; 3495 goto bce_dma_alloc_exit; 3496 } 3497 3498 /* 3499 * Create a DMA tag for the status block, allocate and clear the 3500 * memory, map the memory into DMA space, and fetch the physical 3501 * address of the block. 3502 */ 3503 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3504 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3505 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3506 0, NULL, NULL, &sc->status_tag)) { 3507 BCE_PRINTF("%s(%d): Could not allocate status block " 3508 "DMA tag!\n", __FILE__, __LINE__); 3509 rc = ENOMEM; 3510 goto bce_dma_alloc_exit; 3511 } 3512 3513 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3514 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3515 &sc->status_map)) { 3516 BCE_PRINTF("%s(%d): Could not allocate status block " 3517 "DMA memory!\n", __FILE__, __LINE__); 3518 rc = ENOMEM; 3519 goto bce_dma_alloc_exit; 3520 } 3521 3522 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3523 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3524 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3525 3526 if (error) { 3527 BCE_PRINTF("%s(%d): Could not map status block " 3528 "DMA memory!\n", __FILE__, __LINE__); 3529 rc = ENOMEM; 3530 goto bce_dma_alloc_exit; 3531 } 3532 3533 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3534 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3535 3536 /* 3537 * Create a DMA tag for the statistics block, allocate and clear the 3538 * memory, map the memory into DMA space, and fetch the physical 3539 * address of the block. 3540 */ 3541 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3542 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3543 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3544 0, NULL, NULL, &sc->stats_tag)) { 3545 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3546 "DMA tag!\n", __FILE__, __LINE__); 3547 rc = ENOMEM; 3548 goto bce_dma_alloc_exit; 3549 } 3550 3551 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3552 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3553 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3554 "DMA memory!\n", __FILE__, __LINE__); 3555 rc = ENOMEM; 3556 goto bce_dma_alloc_exit; 3557 } 3558 3559 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3560 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3561 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3562 3563 if(error) { 3564 BCE_PRINTF("%s(%d): Could not map statistics block " 3565 "DMA memory!\n", __FILE__, __LINE__); 3566 rc = ENOMEM; 3567 goto bce_dma_alloc_exit; 3568 } 3569 3570 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3571 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3572 3573 /* BCM5709 uses host memory as cache for context memory. */ 3574 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3575 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3576 if (sc->ctx_pages == 0) 3577 sc->ctx_pages = 1; 3578 3579 DBRUNIF((sc->ctx_pages > 512), 3580 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3581 __FILE__, __LINE__, sc->ctx_pages)); 3582 3583 /* 3584 * Create a DMA tag for the context pages, 3585 * allocate and clear the memory, map the 3586 * memory into DMA space, and fetch the 3587 * physical address of the block. 3588 */ 3589 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3590 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3591 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3592 0, NULL, NULL, &sc->ctx_tag)) { 3593 BCE_PRINTF("%s(%d): Could not allocate CTX " 3594 "DMA tag!\n", __FILE__, __LINE__); 3595 rc = ENOMEM; 3596 goto bce_dma_alloc_exit; 3597 } 3598 3599 for (i = 0; i < sc->ctx_pages; i++) { 3600 3601 if(bus_dmamem_alloc(sc->ctx_tag, 3602 (void **)&sc->ctx_block[i], 3603 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3604 &sc->ctx_map[i])) { 3605 BCE_PRINTF("%s(%d): Could not allocate CTX " 3606 "DMA memory!\n", __FILE__, __LINE__); 3607 rc = ENOMEM; 3608 goto bce_dma_alloc_exit; 3609 } 3610 3611 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3612 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3613 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3614 3615 if (error) { 3616 BCE_PRINTF("%s(%d): Could not map CTX " 3617 "DMA memory!\n", __FILE__, __LINE__); 3618 rc = ENOMEM; 3619 goto bce_dma_alloc_exit; 3620 } 3621 3622 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3623 "= 0x%jX\n", __FUNCTION__, i, 3624 (uintmax_t) sc->ctx_paddr[i]); 3625 } 3626 } 3627 3628 /* 3629 * Create a DMA tag for the TX buffer descriptor chain, 3630 * allocate and clear the memory, and fetch the 3631 * physical address of the block. 3632 */ 3633 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3634 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3635 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3636 NULL, NULL, &sc->tx_bd_chain_tag)) { 3637 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3638 "chain DMA tag!\n", __FILE__, __LINE__); 3639 rc = ENOMEM; 3640 goto bce_dma_alloc_exit; 3641 } 3642 3643 for (i = 0; i < sc->tx_pages; i++) { 3644 3645 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3646 (void **)&sc->tx_bd_chain[i], 3647 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3648 &sc->tx_bd_chain_map[i])) { 3649 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3650 "chain DMA memory!\n", __FILE__, __LINE__); 3651 rc = ENOMEM; 3652 goto bce_dma_alloc_exit; 3653 } 3654 3655 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3656 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3657 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3658 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3659 3660 if (error) { 3661 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3662 "chain DMA memory!\n", __FILE__, __LINE__); 3663 rc = ENOMEM; 3664 goto bce_dma_alloc_exit; 3665 } 3666 3667 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3668 "0x%jX\n", __FUNCTION__, i, 3669 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3670 } 3671 3672 /* Check the required size before mapping to conserve resources. */ 3673 if (bce_tso_enable) { 3674 max_size = BCE_TSO_MAX_SIZE; 3675 max_segments = BCE_MAX_SEGMENTS; 3676 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3677 } else { 3678 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3679 max_segments = BCE_MAX_SEGMENTS; 3680 max_seg_size = MCLBYTES; 3681 } 3682 3683 /* Create a DMA tag for TX mbufs. */ 3684 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3685 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3686 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3687 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3688 __FILE__, __LINE__); 3689 rc = ENOMEM; 3690 goto bce_dma_alloc_exit; 3691 } 3692 3693 /* Create DMA maps for the TX mbufs clusters. */ 3694 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3695 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3696 &sc->tx_mbuf_map[i])) { 3697 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3698 "map!\n", __FILE__, __LINE__); 3699 rc = ENOMEM; 3700 goto bce_dma_alloc_exit; 3701 } 3702 } 3703 3704 /* 3705 * Create a DMA tag for the RX buffer descriptor chain, 3706 * allocate and clear the memory, and fetch the physical 3707 * address of the blocks. 3708 */ 3709 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3710 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3711 sc->max_bus_addr, NULL, NULL, 3712 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3713 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3714 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3715 "DMA tag!\n", __FILE__, __LINE__); 3716 rc = ENOMEM; 3717 goto bce_dma_alloc_exit; 3718 } 3719 3720 for (i = 0; i < sc->rx_pages; i++) { 3721 3722 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3723 (void **)&sc->rx_bd_chain[i], 3724 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3725 &sc->rx_bd_chain_map[i])) { 3726 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3727 "chain DMA memory!\n", __FILE__, __LINE__); 3728 rc = ENOMEM; 3729 goto bce_dma_alloc_exit; 3730 } 3731 3732 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3733 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3734 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3735 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3736 3737 if (error) { 3738 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3739 "chain DMA memory!\n", __FILE__, __LINE__); 3740 rc = ENOMEM; 3741 goto bce_dma_alloc_exit; 3742 } 3743 3744 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3745 "0x%jX\n", __FUNCTION__, i, 3746 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3747 } 3748 3749 /* 3750 * Create a DMA tag for RX mbufs. 3751 */ 3752 if (bce_hdr_split == TRUE) 3753 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3754 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3755 else 3756 max_size = max_seg_size = MJUM9BYTES; 3757 max_segments = 1; 3758 3759 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3760 "(max size = 0x%jX max segments = %d, max segment " 3761 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, 3762 max_segments, (uintmax_t) max_seg_size); 3763 3764 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3765 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3766 max_size, max_segments, max_seg_size, 0, NULL, NULL, 3767 &sc->rx_mbuf_tag)) { 3768 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3769 __FILE__, __LINE__); 3770 rc = ENOMEM; 3771 goto bce_dma_alloc_exit; 3772 } 3773 3774 /* Create DMA maps for the RX mbuf clusters. */ 3775 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3776 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3777 &sc->rx_mbuf_map[i])) { 3778 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3779 "DMA map!\n", __FILE__, __LINE__); 3780 rc = ENOMEM; 3781 goto bce_dma_alloc_exit; 3782 } 3783 } 3784 3785 if (bce_hdr_split == TRUE) { 3786 /* 3787 * Create a DMA tag for the page buffer descriptor chain, 3788 * allocate and clear the memory, and fetch the physical 3789 * address of the blocks. 3790 */ 3791 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3792 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3793 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3794 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3795 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3796 "chain DMA tag!\n", __FILE__, __LINE__); 3797 rc = ENOMEM; 3798 goto bce_dma_alloc_exit; 3799 } 3800 3801 for (i = 0; i < sc->pg_pages; i++) { 3802 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3803 (void **)&sc->pg_bd_chain[i], 3804 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3805 &sc->pg_bd_chain_map[i])) { 3806 BCE_PRINTF("%s(%d): Could not allocate page " 3807 "descriptor chain DMA memory!\n", 3808 __FILE__, __LINE__); 3809 rc = ENOMEM; 3810 goto bce_dma_alloc_exit; 3811 } 3812 3813 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3814 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3815 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3816 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3817 3818 if (error) { 3819 BCE_PRINTF("%s(%d): Could not map page descriptor " 3820 "chain DMA memory!\n", __FILE__, __LINE__); 3821 rc = ENOMEM; 3822 goto bce_dma_alloc_exit; 3823 } 3824 3825 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3826 "0x%jX\n", __FUNCTION__, i, 3827 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3828 } 3829 3830 /* 3831 * Create a DMA tag for page mbufs. 3832 */ 3833 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3834 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3835 3836 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3837 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3838 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3839 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3840 "DMA tag!\n", __FILE__, __LINE__); 3841 rc = ENOMEM; 3842 goto bce_dma_alloc_exit; 3843 } 3844 3845 /* Create DMA maps for the page mbuf clusters. */ 3846 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3847 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3848 &sc->pg_mbuf_map[i])) { 3849 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3850 "DMA map!\n", __FILE__, __LINE__); 3851 rc = ENOMEM; 3852 goto bce_dma_alloc_exit; 3853 } 3854 } 3855 } 3856 3857 bce_dma_alloc_exit: 3858 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3859 return(rc); 3860 } 3861 3862 3863 /****************************************************************************/ 3864 /* Release all resources used by the driver. */ 3865 /* */ 3866 /* Releases all resources acquired by the driver including interrupts, */ 3867 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3868 /* */ 3869 /* Returns: */ 3870 /* Nothing. */ 3871 /****************************************************************************/ 3872 static void 3873 bce_release_resources(struct bce_softc *sc) 3874 { 3875 device_t dev; 3876 3877 DBENTER(BCE_VERBOSE_RESET); 3878 3879 dev = sc->bce_dev; 3880 3881 bce_dma_free(sc); 3882 3883 if (sc->bce_intrhand != NULL) { 3884 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3885 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3886 } 3887 3888 if (sc->bce_res_irq != NULL) { 3889 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3890 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3891 sc->bce_res_irq); 3892 } 3893 3894 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3895 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3896 pci_release_msi(dev); 3897 } 3898 3899 if (sc->bce_res_mem != NULL) { 3900 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3901 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3902 sc->bce_res_mem); 3903 } 3904 3905 if (sc->bce_ifp != NULL) { 3906 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3907 if_free(sc->bce_ifp); 3908 } 3909 3910 if (mtx_initialized(&sc->bce_mtx)) 3911 BCE_LOCK_DESTROY(sc); 3912 3913 DBEXIT(BCE_VERBOSE_RESET); 3914 } 3915 3916 3917 /****************************************************************************/ 3918 /* Firmware synchronization. */ 3919 /* */ 3920 /* Before performing certain events such as a chip reset, synchronize with */ 3921 /* the firmware first. */ 3922 /* */ 3923 /* Returns: */ 3924 /* 0 for success, positive value for failure. */ 3925 /****************************************************************************/ 3926 static int 3927 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3928 { 3929 int i, rc = 0; 3930 u32 val; 3931 3932 DBENTER(BCE_VERBOSE_RESET); 3933 3934 /* Don't waste any time if we've timed out before. */ 3935 if (sc->bce_fw_timed_out == TRUE) { 3936 rc = EBUSY; 3937 goto bce_fw_sync_exit; 3938 } 3939 3940 /* Increment the message sequence number. */ 3941 sc->bce_fw_wr_seq++; 3942 msg_data |= sc->bce_fw_wr_seq; 3943 3944 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3945 "0x%08X\n", msg_data); 3946 3947 /* Send the message to the bootcode driver mailbox. */ 3948 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3949 3950 /* Wait for the bootcode to acknowledge the message. */ 3951 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3952 /* Check for a response in the bootcode firmware mailbox. */ 3953 val = bce_shmem_rd(sc, BCE_FW_MB); 3954 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3955 break; 3956 DELAY(1000); 3957 } 3958 3959 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3960 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3961 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3962 3963 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3964 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3965 3966 msg_data &= ~BCE_DRV_MSG_CODE; 3967 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3968 3969 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3970 3971 sc->bce_fw_timed_out = TRUE; 3972 rc = EBUSY; 3973 } 3974 3975 bce_fw_sync_exit: 3976 DBEXIT(BCE_VERBOSE_RESET); 3977 return (rc); 3978 } 3979 3980 3981 /****************************************************************************/ 3982 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3983 /* */ 3984 /* Returns: */ 3985 /* Nothing. */ 3986 /****************************************************************************/ 3987 static void 3988 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3989 u32 rv2p_code_len, u32 rv2p_proc) 3990 { 3991 int i; 3992 u32 val; 3993 3994 DBENTER(BCE_VERBOSE_RESET); 3995 3996 /* Set the page size used by RV2P. */ 3997 if (rv2p_proc == RV2P_PROC2) { 3998 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3999 } 4000 4001 for (i = 0; i < rv2p_code_len; i += 8) { 4002 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 4003 rv2p_code++; 4004 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 4005 rv2p_code++; 4006 4007 if (rv2p_proc == RV2P_PROC1) { 4008 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4009 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4010 } 4011 else { 4012 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4013 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4014 } 4015 } 4016 4017 /* Reset the processor, un-stall is done later. */ 4018 if (rv2p_proc == RV2P_PROC1) { 4019 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4020 } 4021 else { 4022 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4023 } 4024 4025 DBEXIT(BCE_VERBOSE_RESET); 4026 } 4027 4028 4029 /****************************************************************************/ 4030 /* Load RISC processor firmware. */ 4031 /* */ 4032 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4033 /* associated with a particular processor. */ 4034 /* */ 4035 /* Returns: */ 4036 /* Nothing. */ 4037 /****************************************************************************/ 4038 static void 4039 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4040 struct fw_info *fw) 4041 { 4042 u32 offset; 4043 4044 DBENTER(BCE_VERBOSE_RESET); 4045 4046 bce_halt_cpu(sc, cpu_reg); 4047 4048 /* Load the Text area. */ 4049 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4050 if (fw->text) { 4051 int j; 4052 4053 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4054 REG_WR_IND(sc, offset, fw->text[j]); 4055 } 4056 } 4057 4058 /* Load the Data area. */ 4059 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4060 if (fw->data) { 4061 int j; 4062 4063 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4064 REG_WR_IND(sc, offset, fw->data[j]); 4065 } 4066 } 4067 4068 /* Load the SBSS area. */ 4069 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4070 if (fw->sbss) { 4071 int j; 4072 4073 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4074 REG_WR_IND(sc, offset, fw->sbss[j]); 4075 } 4076 } 4077 4078 /* Load the BSS area. */ 4079 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4080 if (fw->bss) { 4081 int j; 4082 4083 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4084 REG_WR_IND(sc, offset, fw->bss[j]); 4085 } 4086 } 4087 4088 /* Load the Read-Only area. */ 4089 offset = cpu_reg->spad_base + 4090 (fw->rodata_addr - cpu_reg->mips_view_base); 4091 if (fw->rodata) { 4092 int j; 4093 4094 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4095 REG_WR_IND(sc, offset, fw->rodata[j]); 4096 } 4097 } 4098 4099 /* Clear the pre-fetch instruction and set the FW start address. */ 4100 REG_WR_IND(sc, cpu_reg->inst, 0); 4101 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4102 4103 DBEXIT(BCE_VERBOSE_RESET); 4104 } 4105 4106 4107 /****************************************************************************/ 4108 /* Starts the RISC processor. */ 4109 /* */ 4110 /* Assumes the CPU starting address has already been set. */ 4111 /* */ 4112 /* Returns: */ 4113 /* Nothing. */ 4114 /****************************************************************************/ 4115 static void 4116 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4117 { 4118 u32 val; 4119 4120 DBENTER(BCE_VERBOSE_RESET); 4121 4122 /* Start the CPU. */ 4123 val = REG_RD_IND(sc, cpu_reg->mode); 4124 val &= ~cpu_reg->mode_value_halt; 4125 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4126 REG_WR_IND(sc, cpu_reg->mode, val); 4127 4128 DBEXIT(BCE_VERBOSE_RESET); 4129 } 4130 4131 4132 /****************************************************************************/ 4133 /* Halts the RISC processor. */ 4134 /* */ 4135 /* Returns: */ 4136 /* Nothing. */ 4137 /****************************************************************************/ 4138 static void 4139 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4140 { 4141 u32 val; 4142 4143 DBENTER(BCE_VERBOSE_RESET); 4144 4145 /* Halt the CPU. */ 4146 val = REG_RD_IND(sc, cpu_reg->mode); 4147 val |= cpu_reg->mode_value_halt; 4148 REG_WR_IND(sc, cpu_reg->mode, val); 4149 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4150 4151 DBEXIT(BCE_VERBOSE_RESET); 4152 } 4153 4154 4155 /****************************************************************************/ 4156 /* Initialize the RX CPU. */ 4157 /* */ 4158 /* Returns: */ 4159 /* Nothing. */ 4160 /****************************************************************************/ 4161 static void 4162 bce_start_rxp_cpu(struct bce_softc *sc) 4163 { 4164 struct cpu_reg cpu_reg; 4165 4166 DBENTER(BCE_VERBOSE_RESET); 4167 4168 cpu_reg.mode = BCE_RXP_CPU_MODE; 4169 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4170 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4171 cpu_reg.state = BCE_RXP_CPU_STATE; 4172 cpu_reg.state_value_clear = 0xffffff; 4173 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4174 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4175 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4176 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4177 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4178 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4179 cpu_reg.mips_view_base = 0x8000000; 4180 4181 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4182 bce_start_cpu(sc, &cpu_reg); 4183 4184 DBEXIT(BCE_VERBOSE_RESET); 4185 } 4186 4187 4188 /****************************************************************************/ 4189 /* Initialize the RX CPU. */ 4190 /* */ 4191 /* Returns: */ 4192 /* Nothing. */ 4193 /****************************************************************************/ 4194 static void 4195 bce_init_rxp_cpu(struct bce_softc *sc) 4196 { 4197 struct cpu_reg cpu_reg; 4198 struct fw_info fw; 4199 4200 DBENTER(BCE_VERBOSE_RESET); 4201 4202 cpu_reg.mode = BCE_RXP_CPU_MODE; 4203 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4204 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4205 cpu_reg.state = BCE_RXP_CPU_STATE; 4206 cpu_reg.state_value_clear = 0xffffff; 4207 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4208 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4209 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4210 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4211 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4212 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4213 cpu_reg.mips_view_base = 0x8000000; 4214 4215 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4216 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4217 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4218 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4219 fw.start_addr = bce_RXP_b09FwStartAddr; 4220 4221 fw.text_addr = bce_RXP_b09FwTextAddr; 4222 fw.text_len = bce_RXP_b09FwTextLen; 4223 fw.text_index = 0; 4224 fw.text = bce_RXP_b09FwText; 4225 4226 fw.data_addr = bce_RXP_b09FwDataAddr; 4227 fw.data_len = bce_RXP_b09FwDataLen; 4228 fw.data_index = 0; 4229 fw.data = bce_RXP_b09FwData; 4230 4231 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4232 fw.sbss_len = bce_RXP_b09FwSbssLen; 4233 fw.sbss_index = 0; 4234 fw.sbss = bce_RXP_b09FwSbss; 4235 4236 fw.bss_addr = bce_RXP_b09FwBssAddr; 4237 fw.bss_len = bce_RXP_b09FwBssLen; 4238 fw.bss_index = 0; 4239 fw.bss = bce_RXP_b09FwBss; 4240 4241 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4242 fw.rodata_len = bce_RXP_b09FwRodataLen; 4243 fw.rodata_index = 0; 4244 fw.rodata = bce_RXP_b09FwRodata; 4245 } else { 4246 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4247 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4248 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4249 fw.start_addr = bce_RXP_b06FwStartAddr; 4250 4251 fw.text_addr = bce_RXP_b06FwTextAddr; 4252 fw.text_len = bce_RXP_b06FwTextLen; 4253 fw.text_index = 0; 4254 fw.text = bce_RXP_b06FwText; 4255 4256 fw.data_addr = bce_RXP_b06FwDataAddr; 4257 fw.data_len = bce_RXP_b06FwDataLen; 4258 fw.data_index = 0; 4259 fw.data = bce_RXP_b06FwData; 4260 4261 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4262 fw.sbss_len = bce_RXP_b06FwSbssLen; 4263 fw.sbss_index = 0; 4264 fw.sbss = bce_RXP_b06FwSbss; 4265 4266 fw.bss_addr = bce_RXP_b06FwBssAddr; 4267 fw.bss_len = bce_RXP_b06FwBssLen; 4268 fw.bss_index = 0; 4269 fw.bss = bce_RXP_b06FwBss; 4270 4271 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4272 fw.rodata_len = bce_RXP_b06FwRodataLen; 4273 fw.rodata_index = 0; 4274 fw.rodata = bce_RXP_b06FwRodata; 4275 } 4276 4277 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4278 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4279 4280 /* Delay RXP start until initialization is complete. */ 4281 4282 DBEXIT(BCE_VERBOSE_RESET); 4283 } 4284 4285 4286 /****************************************************************************/ 4287 /* Initialize the TX CPU. */ 4288 /* */ 4289 /* Returns: */ 4290 /* Nothing. */ 4291 /****************************************************************************/ 4292 static void 4293 bce_init_txp_cpu(struct bce_softc *sc) 4294 { 4295 struct cpu_reg cpu_reg; 4296 struct fw_info fw; 4297 4298 DBENTER(BCE_VERBOSE_RESET); 4299 4300 cpu_reg.mode = BCE_TXP_CPU_MODE; 4301 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4302 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4303 cpu_reg.state = BCE_TXP_CPU_STATE; 4304 cpu_reg.state_value_clear = 0xffffff; 4305 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4306 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4307 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4308 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4309 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4310 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4311 cpu_reg.mips_view_base = 0x8000000; 4312 4313 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4314 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4315 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4316 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4317 fw.start_addr = bce_TXP_b09FwStartAddr; 4318 4319 fw.text_addr = bce_TXP_b09FwTextAddr; 4320 fw.text_len = bce_TXP_b09FwTextLen; 4321 fw.text_index = 0; 4322 fw.text = bce_TXP_b09FwText; 4323 4324 fw.data_addr = bce_TXP_b09FwDataAddr; 4325 fw.data_len = bce_TXP_b09FwDataLen; 4326 fw.data_index = 0; 4327 fw.data = bce_TXP_b09FwData; 4328 4329 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4330 fw.sbss_len = bce_TXP_b09FwSbssLen; 4331 fw.sbss_index = 0; 4332 fw.sbss = bce_TXP_b09FwSbss; 4333 4334 fw.bss_addr = bce_TXP_b09FwBssAddr; 4335 fw.bss_len = bce_TXP_b09FwBssLen; 4336 fw.bss_index = 0; 4337 fw.bss = bce_TXP_b09FwBss; 4338 4339 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4340 fw.rodata_len = bce_TXP_b09FwRodataLen; 4341 fw.rodata_index = 0; 4342 fw.rodata = bce_TXP_b09FwRodata; 4343 } else { 4344 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4345 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4346 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4347 fw.start_addr = bce_TXP_b06FwStartAddr; 4348 4349 fw.text_addr = bce_TXP_b06FwTextAddr; 4350 fw.text_len = bce_TXP_b06FwTextLen; 4351 fw.text_index = 0; 4352 fw.text = bce_TXP_b06FwText; 4353 4354 fw.data_addr = bce_TXP_b06FwDataAddr; 4355 fw.data_len = bce_TXP_b06FwDataLen; 4356 fw.data_index = 0; 4357 fw.data = bce_TXP_b06FwData; 4358 4359 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4360 fw.sbss_len = bce_TXP_b06FwSbssLen; 4361 fw.sbss_index = 0; 4362 fw.sbss = bce_TXP_b06FwSbss; 4363 4364 fw.bss_addr = bce_TXP_b06FwBssAddr; 4365 fw.bss_len = bce_TXP_b06FwBssLen; 4366 fw.bss_index = 0; 4367 fw.bss = bce_TXP_b06FwBss; 4368 4369 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4370 fw.rodata_len = bce_TXP_b06FwRodataLen; 4371 fw.rodata_index = 0; 4372 fw.rodata = bce_TXP_b06FwRodata; 4373 } 4374 4375 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4376 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4377 bce_start_cpu(sc, &cpu_reg); 4378 4379 DBEXIT(BCE_VERBOSE_RESET); 4380 } 4381 4382 4383 /****************************************************************************/ 4384 /* Initialize the TPAT CPU. */ 4385 /* */ 4386 /* Returns: */ 4387 /* Nothing. */ 4388 /****************************************************************************/ 4389 static void 4390 bce_init_tpat_cpu(struct bce_softc *sc) 4391 { 4392 struct cpu_reg cpu_reg; 4393 struct fw_info fw; 4394 4395 DBENTER(BCE_VERBOSE_RESET); 4396 4397 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4398 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4399 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4400 cpu_reg.state = BCE_TPAT_CPU_STATE; 4401 cpu_reg.state_value_clear = 0xffffff; 4402 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4403 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4404 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4405 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4406 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4407 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4408 cpu_reg.mips_view_base = 0x8000000; 4409 4410 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4411 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4412 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4413 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4414 fw.start_addr = bce_TPAT_b09FwStartAddr; 4415 4416 fw.text_addr = bce_TPAT_b09FwTextAddr; 4417 fw.text_len = bce_TPAT_b09FwTextLen; 4418 fw.text_index = 0; 4419 fw.text = bce_TPAT_b09FwText; 4420 4421 fw.data_addr = bce_TPAT_b09FwDataAddr; 4422 fw.data_len = bce_TPAT_b09FwDataLen; 4423 fw.data_index = 0; 4424 fw.data = bce_TPAT_b09FwData; 4425 4426 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4427 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4428 fw.sbss_index = 0; 4429 fw.sbss = bce_TPAT_b09FwSbss; 4430 4431 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4432 fw.bss_len = bce_TPAT_b09FwBssLen; 4433 fw.bss_index = 0; 4434 fw.bss = bce_TPAT_b09FwBss; 4435 4436 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4437 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4438 fw.rodata_index = 0; 4439 fw.rodata = bce_TPAT_b09FwRodata; 4440 } else { 4441 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4442 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4443 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4444 fw.start_addr = bce_TPAT_b06FwStartAddr; 4445 4446 fw.text_addr = bce_TPAT_b06FwTextAddr; 4447 fw.text_len = bce_TPAT_b06FwTextLen; 4448 fw.text_index = 0; 4449 fw.text = bce_TPAT_b06FwText; 4450 4451 fw.data_addr = bce_TPAT_b06FwDataAddr; 4452 fw.data_len = bce_TPAT_b06FwDataLen; 4453 fw.data_index = 0; 4454 fw.data = bce_TPAT_b06FwData; 4455 4456 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4457 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4458 fw.sbss_index = 0; 4459 fw.sbss = bce_TPAT_b06FwSbss; 4460 4461 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4462 fw.bss_len = bce_TPAT_b06FwBssLen; 4463 fw.bss_index = 0; 4464 fw.bss = bce_TPAT_b06FwBss; 4465 4466 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4467 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4468 fw.rodata_index = 0; 4469 fw.rodata = bce_TPAT_b06FwRodata; 4470 } 4471 4472 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4473 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4474 bce_start_cpu(sc, &cpu_reg); 4475 4476 DBEXIT(BCE_VERBOSE_RESET); 4477 } 4478 4479 4480 /****************************************************************************/ 4481 /* Initialize the CP CPU. */ 4482 /* */ 4483 /* Returns: */ 4484 /* Nothing. */ 4485 /****************************************************************************/ 4486 static void 4487 bce_init_cp_cpu(struct bce_softc *sc) 4488 { 4489 struct cpu_reg cpu_reg; 4490 struct fw_info fw; 4491 4492 DBENTER(BCE_VERBOSE_RESET); 4493 4494 cpu_reg.mode = BCE_CP_CPU_MODE; 4495 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4496 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4497 cpu_reg.state = BCE_CP_CPU_STATE; 4498 cpu_reg.state_value_clear = 0xffffff; 4499 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4500 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4501 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4502 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4503 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4504 cpu_reg.spad_base = BCE_CP_SCRATCH; 4505 cpu_reg.mips_view_base = 0x8000000; 4506 4507 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4508 fw.ver_major = bce_CP_b09FwReleaseMajor; 4509 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4510 fw.ver_fix = bce_CP_b09FwReleaseFix; 4511 fw.start_addr = bce_CP_b09FwStartAddr; 4512 4513 fw.text_addr = bce_CP_b09FwTextAddr; 4514 fw.text_len = bce_CP_b09FwTextLen; 4515 fw.text_index = 0; 4516 fw.text = bce_CP_b09FwText; 4517 4518 fw.data_addr = bce_CP_b09FwDataAddr; 4519 fw.data_len = bce_CP_b09FwDataLen; 4520 fw.data_index = 0; 4521 fw.data = bce_CP_b09FwData; 4522 4523 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4524 fw.sbss_len = bce_CP_b09FwSbssLen; 4525 fw.sbss_index = 0; 4526 fw.sbss = bce_CP_b09FwSbss; 4527 4528 fw.bss_addr = bce_CP_b09FwBssAddr; 4529 fw.bss_len = bce_CP_b09FwBssLen; 4530 fw.bss_index = 0; 4531 fw.bss = bce_CP_b09FwBss; 4532 4533 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4534 fw.rodata_len = bce_CP_b09FwRodataLen; 4535 fw.rodata_index = 0; 4536 fw.rodata = bce_CP_b09FwRodata; 4537 } else { 4538 fw.ver_major = bce_CP_b06FwReleaseMajor; 4539 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4540 fw.ver_fix = bce_CP_b06FwReleaseFix; 4541 fw.start_addr = bce_CP_b06FwStartAddr; 4542 4543 fw.text_addr = bce_CP_b06FwTextAddr; 4544 fw.text_len = bce_CP_b06FwTextLen; 4545 fw.text_index = 0; 4546 fw.text = bce_CP_b06FwText; 4547 4548 fw.data_addr = bce_CP_b06FwDataAddr; 4549 fw.data_len = bce_CP_b06FwDataLen; 4550 fw.data_index = 0; 4551 fw.data = bce_CP_b06FwData; 4552 4553 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4554 fw.sbss_len = bce_CP_b06FwSbssLen; 4555 fw.sbss_index = 0; 4556 fw.sbss = bce_CP_b06FwSbss; 4557 4558 fw.bss_addr = bce_CP_b06FwBssAddr; 4559 fw.bss_len = bce_CP_b06FwBssLen; 4560 fw.bss_index = 0; 4561 fw.bss = bce_CP_b06FwBss; 4562 4563 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4564 fw.rodata_len = bce_CP_b06FwRodataLen; 4565 fw.rodata_index = 0; 4566 fw.rodata = bce_CP_b06FwRodata; 4567 } 4568 4569 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4570 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4571 bce_start_cpu(sc, &cpu_reg); 4572 4573 DBEXIT(BCE_VERBOSE_RESET); 4574 } 4575 4576 4577 /****************************************************************************/ 4578 /* Initialize the COM CPU. */ 4579 /* */ 4580 /* Returns: */ 4581 /* Nothing. */ 4582 /****************************************************************************/ 4583 static void 4584 bce_init_com_cpu(struct bce_softc *sc) 4585 { 4586 struct cpu_reg cpu_reg; 4587 struct fw_info fw; 4588 4589 DBENTER(BCE_VERBOSE_RESET); 4590 4591 cpu_reg.mode = BCE_COM_CPU_MODE; 4592 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4593 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4594 cpu_reg.state = BCE_COM_CPU_STATE; 4595 cpu_reg.state_value_clear = 0xffffff; 4596 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4597 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4598 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4599 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4600 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4601 cpu_reg.spad_base = BCE_COM_SCRATCH; 4602 cpu_reg.mips_view_base = 0x8000000; 4603 4604 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4605 fw.ver_major = bce_COM_b09FwReleaseMajor; 4606 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4607 fw.ver_fix = bce_COM_b09FwReleaseFix; 4608 fw.start_addr = bce_COM_b09FwStartAddr; 4609 4610 fw.text_addr = bce_COM_b09FwTextAddr; 4611 fw.text_len = bce_COM_b09FwTextLen; 4612 fw.text_index = 0; 4613 fw.text = bce_COM_b09FwText; 4614 4615 fw.data_addr = bce_COM_b09FwDataAddr; 4616 fw.data_len = bce_COM_b09FwDataLen; 4617 fw.data_index = 0; 4618 fw.data = bce_COM_b09FwData; 4619 4620 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4621 fw.sbss_len = bce_COM_b09FwSbssLen; 4622 fw.sbss_index = 0; 4623 fw.sbss = bce_COM_b09FwSbss; 4624 4625 fw.bss_addr = bce_COM_b09FwBssAddr; 4626 fw.bss_len = bce_COM_b09FwBssLen; 4627 fw.bss_index = 0; 4628 fw.bss = bce_COM_b09FwBss; 4629 4630 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4631 fw.rodata_len = bce_COM_b09FwRodataLen; 4632 fw.rodata_index = 0; 4633 fw.rodata = bce_COM_b09FwRodata; 4634 } else { 4635 fw.ver_major = bce_COM_b06FwReleaseMajor; 4636 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4637 fw.ver_fix = bce_COM_b06FwReleaseFix; 4638 fw.start_addr = bce_COM_b06FwStartAddr; 4639 4640 fw.text_addr = bce_COM_b06FwTextAddr; 4641 fw.text_len = bce_COM_b06FwTextLen; 4642 fw.text_index = 0; 4643 fw.text = bce_COM_b06FwText; 4644 4645 fw.data_addr = bce_COM_b06FwDataAddr; 4646 fw.data_len = bce_COM_b06FwDataLen; 4647 fw.data_index = 0; 4648 fw.data = bce_COM_b06FwData; 4649 4650 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4651 fw.sbss_len = bce_COM_b06FwSbssLen; 4652 fw.sbss_index = 0; 4653 fw.sbss = bce_COM_b06FwSbss; 4654 4655 fw.bss_addr = bce_COM_b06FwBssAddr; 4656 fw.bss_len = bce_COM_b06FwBssLen; 4657 fw.bss_index = 0; 4658 fw.bss = bce_COM_b06FwBss; 4659 4660 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4661 fw.rodata_len = bce_COM_b06FwRodataLen; 4662 fw.rodata_index = 0; 4663 fw.rodata = bce_COM_b06FwRodata; 4664 } 4665 4666 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4667 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4668 bce_start_cpu(sc, &cpu_reg); 4669 4670 DBEXIT(BCE_VERBOSE_RESET); 4671 } 4672 4673 4674 /****************************************************************************/ 4675 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4676 /* */ 4677 /* Loads the firmware for each CPU and starts the CPU. */ 4678 /* */ 4679 /* Returns: */ 4680 /* Nothing. */ 4681 /****************************************************************************/ 4682 static void 4683 bce_init_cpus(struct bce_softc *sc) 4684 { 4685 DBENTER(BCE_VERBOSE_RESET); 4686 4687 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4688 4689 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4690 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4691 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4692 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4693 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4694 } else { 4695 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4696 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4697 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4698 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4699 } 4700 4701 } else { 4702 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4703 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4704 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4705 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4706 } 4707 4708 bce_init_rxp_cpu(sc); 4709 bce_init_txp_cpu(sc); 4710 bce_init_tpat_cpu(sc); 4711 bce_init_com_cpu(sc); 4712 bce_init_cp_cpu(sc); 4713 4714 DBEXIT(BCE_VERBOSE_RESET); 4715 } 4716 4717 4718 /****************************************************************************/ 4719 /* Initialize context memory. */ 4720 /* */ 4721 /* Clears the memory associated with each Context ID (CID). */ 4722 /* */ 4723 /* Returns: */ 4724 /* Nothing. */ 4725 /****************************************************************************/ 4726 static int 4727 bce_init_ctx(struct bce_softc *sc) 4728 { 4729 u32 offset, val, vcid_addr; 4730 int i, j, rc, retry_cnt; 4731 4732 rc = 0; 4733 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4734 4735 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4736 retry_cnt = CTX_INIT_RETRY_COUNT; 4737 4738 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4739 4740 /* 4741 * BCM5709 context memory may be cached 4742 * in host memory so prepare the host memory 4743 * for access. 4744 */ 4745 val = BCE_CTX_COMMAND_ENABLED | 4746 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4747 val |= (BCM_PAGE_BITS - 8) << 16; 4748 REG_WR(sc, BCE_CTX_COMMAND, val); 4749 4750 /* Wait for mem init command to complete. */ 4751 for (i = 0; i < retry_cnt; i++) { 4752 val = REG_RD(sc, BCE_CTX_COMMAND); 4753 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4754 break; 4755 DELAY(2); 4756 } 4757 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4758 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4759 __FUNCTION__); 4760 rc = EBUSY; 4761 goto init_ctx_fail; 4762 } 4763 4764 for (i = 0; i < sc->ctx_pages; i++) { 4765 /* Set the physical address of the context memory. */ 4766 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4767 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4768 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4769 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4770 BCE_ADDR_HI(sc->ctx_paddr[i])); 4771 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4772 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4773 4774 /* Verify the context memory write was successful. */ 4775 for (j = 0; j < retry_cnt; j++) { 4776 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4777 if ((val & 4778 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4779 break; 4780 DELAY(5); 4781 } 4782 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4783 BCE_PRINTF("%s(): Failed to initialize " 4784 "context page %d!\n", __FUNCTION__, i); 4785 rc = EBUSY; 4786 goto init_ctx_fail; 4787 } 4788 } 4789 } else { 4790 4791 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4792 4793 /* 4794 * For the 5706/5708, context memory is local to 4795 * the controller, so initialize the controller 4796 * context memory. 4797 */ 4798 4799 vcid_addr = GET_CID_ADDR(96); 4800 while (vcid_addr) { 4801 4802 vcid_addr -= PHY_CTX_SIZE; 4803 4804 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4805 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4806 4807 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4808 CTX_WR(sc, 0x00, offset, 0); 4809 } 4810 4811 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4812 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4813 } 4814 4815 } 4816 init_ctx_fail: 4817 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4818 return (rc); 4819 } 4820 4821 4822 /****************************************************************************/ 4823 /* Fetch the permanent MAC address of the controller. */ 4824 /* */ 4825 /* Returns: */ 4826 /* Nothing. */ 4827 /****************************************************************************/ 4828 static void 4829 bce_get_mac_addr(struct bce_softc *sc) 4830 { 4831 u32 mac_lo = 0, mac_hi = 0; 4832 4833 DBENTER(BCE_VERBOSE_RESET); 4834 4835 /* 4836 * The NetXtreme II bootcode populates various NIC 4837 * power-on and runtime configuration items in a 4838 * shared memory area. The factory configured MAC 4839 * address is available from both NVRAM and the 4840 * shared memory area so we'll read the value from 4841 * shared memory for speed. 4842 */ 4843 4844 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4845 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4846 4847 if ((mac_lo == 0) && (mac_hi == 0)) { 4848 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4849 __FILE__, __LINE__); 4850 } else { 4851 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4852 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4853 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4854 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4855 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4856 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4857 } 4858 4859 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4860 "address = %6D\n", sc->eaddr, ":"); 4861 DBEXIT(BCE_VERBOSE_RESET); 4862 } 4863 4864 4865 /****************************************************************************/ 4866 /* Program the MAC address. */ 4867 /* */ 4868 /* Returns: */ 4869 /* Nothing. */ 4870 /****************************************************************************/ 4871 static void 4872 bce_set_mac_addr(struct bce_softc *sc) 4873 { 4874 u32 val; 4875 u8 *mac_addr = sc->eaddr; 4876 4877 /* ToDo: Add support for setting multiple MAC addresses. */ 4878 4879 DBENTER(BCE_VERBOSE_RESET); 4880 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4881 "%6D\n", sc->eaddr, ":"); 4882 4883 val = (mac_addr[0] << 8) | mac_addr[1]; 4884 4885 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4886 4887 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4888 (mac_addr[4] << 8) | mac_addr[5]; 4889 4890 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4891 4892 DBEXIT(BCE_VERBOSE_RESET); 4893 } 4894 4895 4896 /****************************************************************************/ 4897 /* Stop the controller. */ 4898 /* */ 4899 /* Returns: */ 4900 /* Nothing. */ 4901 /****************************************************************************/ 4902 static void 4903 bce_stop(struct bce_softc *sc) 4904 { 4905 struct ifnet *ifp; 4906 4907 DBENTER(BCE_VERBOSE_RESET); 4908 4909 BCE_LOCK_ASSERT(sc); 4910 4911 ifp = sc->bce_ifp; 4912 4913 callout_stop(&sc->bce_tick_callout); 4914 4915 /* Disable the transmit/receive blocks. */ 4916 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4917 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4918 DELAY(20); 4919 4920 bce_disable_intr(sc); 4921 4922 /* Free RX buffers. */ 4923 if (bce_hdr_split == TRUE) { 4924 bce_free_pg_chain(sc); 4925 } 4926 bce_free_rx_chain(sc); 4927 4928 /* Free TX buffers. */ 4929 bce_free_tx_chain(sc); 4930 4931 sc->watchdog_timer = 0; 4932 4933 sc->bce_link_up = FALSE; 4934 4935 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4936 4937 DBEXIT(BCE_VERBOSE_RESET); 4938 } 4939 4940 4941 static int 4942 bce_reset(struct bce_softc *sc, u32 reset_code) 4943 { 4944 u32 val; 4945 int i, rc = 0; 4946 4947 DBENTER(BCE_VERBOSE_RESET); 4948 4949 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4950 __FUNCTION__, reset_code); 4951 4952 /* Wait for pending PCI transactions to complete. */ 4953 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4954 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4955 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4956 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4957 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4958 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4959 DELAY(5); 4960 4961 /* Disable DMA */ 4962 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4963 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4964 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4965 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4966 } 4967 4968 /* Assume bootcode is running. */ 4969 sc->bce_fw_timed_out = FALSE; 4970 sc->bce_drv_cardiac_arrest = FALSE; 4971 4972 /* Give the firmware a chance to prepare for the reset. */ 4973 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4974 if (rc) 4975 goto bce_reset_exit; 4976 4977 /* Set a firmware reminder that this is a soft reset. */ 4978 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4979 4980 /* Dummy read to force the chip to complete all current transactions. */ 4981 val = REG_RD(sc, BCE_MISC_ID); 4982 4983 /* Chip reset. */ 4984 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4985 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4986 REG_RD(sc, BCE_MISC_COMMAND); 4987 DELAY(5); 4988 4989 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4990 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4991 4992 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4993 } else { 4994 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4995 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4996 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4997 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4998 4999 /* Allow up to 30us for reset to complete. */ 5000 for (i = 0; i < 10; i++) { 5001 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5002 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5003 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5004 break; 5005 } 5006 DELAY(10); 5007 } 5008 5009 /* Check that reset completed successfully. */ 5010 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5011 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5012 BCE_PRINTF("%s(%d): Reset failed!\n", 5013 __FILE__, __LINE__); 5014 rc = EBUSY; 5015 goto bce_reset_exit; 5016 } 5017 } 5018 5019 /* Make sure byte swapping is properly configured. */ 5020 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5021 if (val != 0x01020304) { 5022 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5023 __FILE__, __LINE__); 5024 rc = ENODEV; 5025 goto bce_reset_exit; 5026 } 5027 5028 /* Just completed a reset, assume that firmware is running again. */ 5029 sc->bce_fw_timed_out = FALSE; 5030 sc->bce_drv_cardiac_arrest = FALSE; 5031 5032 /* Wait for the firmware to finish its initialization. */ 5033 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5034 if (rc) 5035 BCE_PRINTF("%s(%d): Firmware did not complete " 5036 "initialization!\n", __FILE__, __LINE__); 5037 5038 bce_reset_exit: 5039 DBEXIT(BCE_VERBOSE_RESET); 5040 return (rc); 5041 } 5042 5043 5044 static int 5045 bce_chipinit(struct bce_softc *sc) 5046 { 5047 u32 val; 5048 int rc = 0; 5049 5050 DBENTER(BCE_VERBOSE_RESET); 5051 5052 bce_disable_intr(sc); 5053 5054 /* 5055 * Initialize DMA byte/word swapping, configure the number of DMA 5056 * channels and PCI clock compensation delay. 5057 */ 5058 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5059 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5060 #if BYTE_ORDER == BIG_ENDIAN 5061 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5062 #endif 5063 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5064 DMA_READ_CHANS << 12 | 5065 DMA_WRITE_CHANS << 16; 5066 5067 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5068 5069 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5070 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5071 5072 /* 5073 * This setting resolves a problem observed on certain Intel PCI 5074 * chipsets that cannot handle multiple outstanding DMA operations. 5075 * See errata E9_5706A1_65. 5076 */ 5077 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5078 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5079 !(sc->bce_flags & BCE_PCIX_FLAG)) 5080 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5081 5082 REG_WR(sc, BCE_DMA_CONFIG, val); 5083 5084 /* Enable the RX_V2P and Context state machines before access. */ 5085 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5086 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5087 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5088 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5089 5090 /* Initialize context mapping and zero out the quick contexts. */ 5091 if ((rc = bce_init_ctx(sc)) != 0) 5092 goto bce_chipinit_exit; 5093 5094 /* Initialize the on-boards CPUs */ 5095 bce_init_cpus(sc); 5096 5097 /* Enable management frames (NC-SI) to flow to the MCP. */ 5098 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5099 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5100 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5101 } 5102 5103 /* Prepare NVRAM for access. */ 5104 if ((rc = bce_init_nvram(sc)) != 0) 5105 goto bce_chipinit_exit; 5106 5107 /* Set the kernel bypass block size */ 5108 val = REG_RD(sc, BCE_MQ_CONFIG); 5109 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5110 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5111 5112 /* Enable bins used on the 5709. */ 5113 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5114 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5115 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5116 val |= BCE_MQ_CONFIG_HALT_DIS; 5117 } 5118 5119 REG_WR(sc, BCE_MQ_CONFIG, val); 5120 5121 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5122 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5123 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5124 5125 /* Set the page size and clear the RV2P processor stall bits. */ 5126 val = (BCM_PAGE_BITS - 8) << 24; 5127 REG_WR(sc, BCE_RV2P_CONFIG, val); 5128 5129 /* Configure page size. */ 5130 val = REG_RD(sc, BCE_TBDR_CONFIG); 5131 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5132 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5133 REG_WR(sc, BCE_TBDR_CONFIG, val); 5134 5135 /* Set the perfect match control register to default. */ 5136 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5137 5138 bce_chipinit_exit: 5139 DBEXIT(BCE_VERBOSE_RESET); 5140 5141 return(rc); 5142 } 5143 5144 5145 /****************************************************************************/ 5146 /* Initialize the controller in preparation to send/receive traffic. */ 5147 /* */ 5148 /* Returns: */ 5149 /* 0 for success, positive value for failure. */ 5150 /****************************************************************************/ 5151 static int 5152 bce_blockinit(struct bce_softc *sc) 5153 { 5154 u32 reg, val; 5155 int rc = 0; 5156 5157 DBENTER(BCE_VERBOSE_RESET); 5158 5159 /* Load the hardware default MAC address. */ 5160 bce_set_mac_addr(sc); 5161 5162 /* Set the Ethernet backoff seed value */ 5163 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5164 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5165 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5166 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5167 5168 sc->last_status_idx = 0; 5169 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5170 5171 /* Set up link change interrupt generation. */ 5172 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5173 5174 /* Program the physical address of the status block. */ 5175 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5176 BCE_ADDR_LO(sc->status_block_paddr)); 5177 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5178 BCE_ADDR_HI(sc->status_block_paddr)); 5179 5180 /* Program the physical address of the statistics block. */ 5181 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5182 BCE_ADDR_LO(sc->stats_block_paddr)); 5183 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5184 BCE_ADDR_HI(sc->stats_block_paddr)); 5185 5186 /* Program various host coalescing parameters. */ 5187 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5188 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 5189 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5190 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 5191 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 5192 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 5193 REG_WR(sc, BCE_HC_TX_TICKS, 5194 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5195 REG_WR(sc, BCE_HC_RX_TICKS, 5196 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5197 REG_WR(sc, BCE_HC_COM_TICKS, 5198 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 5199 REG_WR(sc, BCE_HC_CMD_TICKS, 5200 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 5201 REG_WR(sc, BCE_HC_STATS_TICKS, 5202 (sc->bce_stats_ticks & 0xffff00)); 5203 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5204 5205 /* Configure the Host Coalescing block. */ 5206 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5207 BCE_HC_CONFIG_COLLECT_STATS; 5208 5209 #if 0 5210 /* ToDo: Add MSI-X support. */ 5211 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5212 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5213 BCE_HC_SB_CONFIG_1; 5214 5215 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5216 5217 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5218 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5219 5220 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5221 (sc->tx_quick_cons_trip_int << 16) | 5222 sc->tx_quick_cons_trip); 5223 5224 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5225 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5226 5227 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5228 } 5229 5230 /* 5231 * Tell the HC block to automatically set the 5232 * INT_MASK bit after an MSI/MSI-X interrupt 5233 * is generated so the driver doesn't have to. 5234 */ 5235 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5236 val |= BCE_HC_CONFIG_ONE_SHOT; 5237 5238 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5239 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5240 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5241 #endif 5242 5243 REG_WR(sc, BCE_HC_CONFIG, val); 5244 5245 /* Clear the internal statistics counters. */ 5246 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5247 5248 /* Verify that bootcode is running. */ 5249 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5250 5251 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5252 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5253 __FILE__, __LINE__); 5254 reg = 0); 5255 5256 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5257 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5258 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5259 "Expected: 08%08X\n", __FILE__, __LINE__, 5260 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5261 BCE_DEV_INFO_SIGNATURE_MAGIC); 5262 rc = ENODEV; 5263 goto bce_blockinit_exit; 5264 } 5265 5266 /* Enable DMA */ 5267 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5268 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5269 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5270 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5271 } 5272 5273 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5274 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5275 BCE_DRV_MSG_CODE_RESET); 5276 5277 /* Enable link state change interrupt generation. */ 5278 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5279 5280 /* Enable the RXP. */ 5281 bce_start_rxp_cpu(sc); 5282 5283 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5284 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5285 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5286 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5287 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5288 } 5289 5290 /* Enable all remaining blocks in the MAC. */ 5291 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5292 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5293 BCE_MISC_ENABLE_DEFAULT_XI); 5294 else 5295 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5296 BCE_MISC_ENABLE_DEFAULT); 5297 5298 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5299 DELAY(20); 5300 5301 /* Save the current host coalescing block settings. */ 5302 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5303 5304 bce_blockinit_exit: 5305 DBEXIT(BCE_VERBOSE_RESET); 5306 5307 return (rc); 5308 } 5309 5310 5311 /****************************************************************************/ 5312 /* Encapsulate an mbuf into the rx_bd chain. */ 5313 /* */ 5314 /* Returns: */ 5315 /* 0 for success, positive value for failure. */ 5316 /****************************************************************************/ 5317 static int 5318 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5319 u16 *chain_prod, u32 *prod_bseq) 5320 { 5321 bus_dmamap_t map; 5322 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 5323 struct mbuf *m_new = NULL; 5324 struct rx_bd *rxbd; 5325 int nsegs, error, rc = 0; 5326 #ifdef BCE_DEBUG 5327 u16 debug_chain_prod = *chain_prod; 5328 #endif 5329 5330 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5331 5332 /* Make sure the inputs are valid. */ 5333 DBRUNIF((*chain_prod > MAX_RX_BD_ALLOC), 5334 BCE_PRINTF("%s(%d): RX producer out of range: " 5335 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5336 *chain_prod, (u16) MAX_RX_BD_ALLOC)); 5337 5338 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5339 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5340 *prod, *chain_prod, *prod_bseq); 5341 5342 /* Update some debug statistic counters */ 5343 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5344 sc->rx_low_watermark = sc->free_rx_bd); 5345 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5346 sc->rx_empty_count++); 5347 5348 /* Check whether this is a new mbuf allocation. */ 5349 if (m == NULL) { 5350 5351 /* Simulate an mbuf allocation failure. */ 5352 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5353 sc->mbuf_alloc_failed_count++; 5354 sc->mbuf_alloc_failed_sim_count++; 5355 rc = ENOBUFS; 5356 goto bce_get_rx_buf_exit); 5357 5358 /* This is a new mbuf allocation. */ 5359 if (bce_hdr_split == TRUE) 5360 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5361 else 5362 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 5363 sc->rx_bd_mbuf_alloc_size); 5364 5365 if (m_new == NULL) { 5366 sc->mbuf_alloc_failed_count++; 5367 rc = ENOBUFS; 5368 goto bce_get_rx_buf_exit; 5369 } 5370 5371 DBRUN(sc->debug_rx_mbuf_alloc++); 5372 } else { 5373 /* Reuse an existing mbuf. */ 5374 m_new = m; 5375 } 5376 5377 /* Make sure we have a valid packet header. */ 5378 M_ASSERTPKTHDR(m_new); 5379 5380 /* Initialize the mbuf size and pad if necessary for alignment. */ 5381 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5382 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5383 5384 /* ToDo: Consider calling m_fragment() to test error handling. */ 5385 5386 /* Map the mbuf cluster into device memory. */ 5387 map = sc->rx_mbuf_map[*chain_prod]; 5388 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5389 segs, &nsegs, BUS_DMA_NOWAIT); 5390 5391 /* Handle any mapping errors. */ 5392 if (error) { 5393 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5394 "chain (%d)!\n", __FILE__, __LINE__, error); 5395 5396 sc->dma_map_addr_rx_failed_count++; 5397 m_freem(m_new); 5398 5399 DBRUN(sc->debug_rx_mbuf_alloc--); 5400 5401 rc = ENOBUFS; 5402 goto bce_get_rx_buf_exit; 5403 } 5404 5405 /* All mbufs must map to a single segment. */ 5406 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5407 __FUNCTION__, nsegs)); 5408 5409 /* Setup the rx_bd for the segment. */ 5410 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5411 5412 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5413 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5414 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5415 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5416 *prod_bseq += segs[0].ds_len; 5417 5418 /* Save the mbuf and update our counter. */ 5419 sc->rx_mbuf_ptr[*chain_prod] = m_new; 5420 sc->free_rx_bd -= nsegs; 5421 5422 DBRUNMSG(BCE_INSANE_RECV, 5423 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5424 5425 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5426 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", 5427 __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5428 5429 bce_get_rx_buf_exit: 5430 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5431 5432 return(rc); 5433 } 5434 5435 5436 /****************************************************************************/ 5437 /* Encapsulate an mbuf cluster into the page chain. */ 5438 /* */ 5439 /* Returns: */ 5440 /* 0 for success, positive value for failure. */ 5441 /****************************************************************************/ 5442 static int 5443 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5444 u16 *prod_idx) 5445 { 5446 bus_dmamap_t map; 5447 bus_addr_t busaddr; 5448 struct mbuf *m_new = NULL; 5449 struct rx_bd *pgbd; 5450 int error, rc = 0; 5451 #ifdef BCE_DEBUG 5452 u16 debug_prod_idx = *prod_idx; 5453 #endif 5454 5455 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5456 5457 /* Make sure the inputs are valid. */ 5458 DBRUNIF((*prod_idx > MAX_PG_BD_ALLOC), 5459 BCE_PRINTF("%s(%d): page producer out of range: " 5460 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5461 *prod_idx, (u16) MAX_PG_BD_ALLOC)); 5462 5463 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5464 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5465 5466 /* Update counters if we've hit a new low or run out of pages. */ 5467 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5468 sc->pg_low_watermark = sc->free_pg_bd); 5469 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5470 5471 /* Check whether this is a new mbuf allocation. */ 5472 if (m == NULL) { 5473 5474 /* Simulate an mbuf allocation failure. */ 5475 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5476 sc->mbuf_alloc_failed_count++; 5477 sc->mbuf_alloc_failed_sim_count++; 5478 rc = ENOBUFS; 5479 goto bce_get_pg_buf_exit); 5480 5481 /* This is a new mbuf allocation. */ 5482 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5483 if (m_new == NULL) { 5484 sc->mbuf_alloc_failed_count++; 5485 rc = ENOBUFS; 5486 goto bce_get_pg_buf_exit; 5487 } 5488 5489 DBRUN(sc->debug_pg_mbuf_alloc++); 5490 } else { 5491 /* Reuse an existing mbuf. */ 5492 m_new = m; 5493 m_new->m_data = m_new->m_ext.ext_buf; 5494 } 5495 5496 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5497 5498 /* ToDo: Consider calling m_fragment() to test error handling. */ 5499 5500 /* Map the mbuf cluster into device memory. */ 5501 map = sc->pg_mbuf_map[*prod_idx]; 5502 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5503 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, 5504 &busaddr, BUS_DMA_NOWAIT); 5505 5506 /* Handle any mapping errors. */ 5507 if (error) { 5508 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5509 __FILE__, __LINE__); 5510 5511 m_freem(m_new); 5512 DBRUN(sc->debug_pg_mbuf_alloc--); 5513 5514 rc = ENOBUFS; 5515 goto bce_get_pg_buf_exit; 5516 } 5517 5518 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5519 5520 /* 5521 * The page chain uses the same rx_bd data structure 5522 * as the receive chain but doesn't require a byte sequence (bseq). 5523 */ 5524 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5525 5526 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5527 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5528 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5529 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5530 5531 /* Save the mbuf and update our counter. */ 5532 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5533 sc->free_pg_bd--; 5534 5535 DBRUNMSG(BCE_INSANE_RECV, 5536 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5537 5538 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5539 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5540 5541 bce_get_pg_buf_exit: 5542 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5543 5544 return(rc); 5545 } 5546 5547 5548 /****************************************************************************/ 5549 /* Initialize the TX context memory. */ 5550 /* */ 5551 /* Returns: */ 5552 /* Nothing */ 5553 /****************************************************************************/ 5554 static void 5555 bce_init_tx_context(struct bce_softc *sc) 5556 { 5557 u32 val; 5558 5559 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5560 5561 /* Initialize the context ID for an L2 TX chain. */ 5562 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5563 /* Set the CID type to support an L2 connection. */ 5564 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5565 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5566 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5567 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5568 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5569 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5570 5571 /* Point the hardware to the first page in the chain. */ 5572 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5573 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5574 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5575 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5576 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5577 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5578 } else { 5579 /* Set the CID type to support an L2 connection. */ 5580 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5581 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5582 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5583 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5584 5585 /* Point the hardware to the first page in the chain. */ 5586 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5587 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5588 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5589 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5590 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5591 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5592 } 5593 5594 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5595 } 5596 5597 5598 /****************************************************************************/ 5599 /* Allocate memory and initialize the TX data structures. */ 5600 /* */ 5601 /* Returns: */ 5602 /* 0 for success, positive value for failure. */ 5603 /****************************************************************************/ 5604 static int 5605 bce_init_tx_chain(struct bce_softc *sc) 5606 { 5607 struct tx_bd *txbd; 5608 int i, rc = 0; 5609 5610 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5611 5612 /* Set the initial TX producer/consumer indices. */ 5613 sc->tx_prod = 0; 5614 sc->tx_cons = 0; 5615 sc->tx_prod_bseq = 0; 5616 sc->used_tx_bd = 0; 5617 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5618 DBRUN(sc->tx_hi_watermark = 0); 5619 DBRUN(sc->tx_full_count = 0); 5620 5621 /* 5622 * The NetXtreme II supports a linked-list structre called 5623 * a Buffer Descriptor Chain (or BD chain). A BD chain 5624 * consists of a series of 1 or more chain pages, each of which 5625 * consists of a fixed number of BD entries. 5626 * The last BD entry on each page is a pointer to the next page 5627 * in the chain, and the last pointer in the BD chain 5628 * points back to the beginning of the chain. 5629 */ 5630 5631 /* Set the TX next pointer chain entries. */ 5632 for (i = 0; i < sc->tx_pages; i++) { 5633 int j; 5634 5635 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5636 5637 /* Check if we've reached the last page. */ 5638 if (i == (sc->tx_pages - 1)) 5639 j = 0; 5640 else 5641 j = i + 1; 5642 5643 txbd->tx_bd_haddr_hi = 5644 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5645 txbd->tx_bd_haddr_lo = 5646 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5647 } 5648 5649 bce_init_tx_context(sc); 5650 5651 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5652 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5653 5654 return(rc); 5655 } 5656 5657 5658 /****************************************************************************/ 5659 /* Free memory and clear the TX data structures. */ 5660 /* */ 5661 /* Returns: */ 5662 /* Nothing. */ 5663 /****************************************************************************/ 5664 static void 5665 bce_free_tx_chain(struct bce_softc *sc) 5666 { 5667 int i; 5668 5669 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5670 5671 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5672 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5673 if (sc->tx_mbuf_ptr[i] != NULL) { 5674 if (sc->tx_mbuf_map[i] != NULL) 5675 bus_dmamap_sync(sc->tx_mbuf_tag, 5676 sc->tx_mbuf_map[i], 5677 BUS_DMASYNC_POSTWRITE); 5678 m_freem(sc->tx_mbuf_ptr[i]); 5679 sc->tx_mbuf_ptr[i] = NULL; 5680 DBRUN(sc->debug_tx_mbuf_alloc--); 5681 } 5682 } 5683 5684 /* Clear each TX chain page. */ 5685 for (i = 0; i < sc->tx_pages; i++) 5686 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5687 5688 sc->used_tx_bd = 0; 5689 5690 /* Check if we lost any mbufs in the process. */ 5691 DBRUNIF((sc->debug_tx_mbuf_alloc), 5692 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5693 "from tx chain!\n", __FILE__, __LINE__, 5694 sc->debug_tx_mbuf_alloc)); 5695 5696 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5697 } 5698 5699 5700 /****************************************************************************/ 5701 /* Initialize the RX context memory. */ 5702 /* */ 5703 /* Returns: */ 5704 /* Nothing */ 5705 /****************************************************************************/ 5706 static void 5707 bce_init_rx_context(struct bce_softc *sc) 5708 { 5709 u32 val; 5710 5711 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5712 5713 /* Init the type, size, and BD cache levels for the RX context. */ 5714 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5715 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5716 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5717 5718 /* 5719 * Set the level for generating pause frames 5720 * when the number of available rx_bd's gets 5721 * too low (the low watermark) and the level 5722 * when pause frames can be stopped (the high 5723 * watermark). 5724 */ 5725 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5726 u32 lo_water, hi_water; 5727 5728 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5729 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5730 } else { 5731 lo_water = 0; 5732 } 5733 5734 if (lo_water >= USABLE_RX_BD_ALLOC) { 5735 lo_water = 0; 5736 } 5737 5738 hi_water = USABLE_RX_BD_ALLOC / 4; 5739 5740 if (hi_water <= lo_water) { 5741 lo_water = 0; 5742 } 5743 5744 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5745 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5746 5747 if (hi_water > 0xf) 5748 hi_water = 0xf; 5749 else if (hi_water == 0) 5750 lo_water = 0; 5751 5752 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5753 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5754 } 5755 5756 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5757 5758 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5759 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5760 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5761 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5762 } 5763 5764 /* Point the hardware to the first page in the chain. */ 5765 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5766 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5767 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5768 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5769 5770 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5771 } 5772 5773 5774 /****************************************************************************/ 5775 /* Allocate memory and initialize the RX data structures. */ 5776 /* */ 5777 /* Returns: */ 5778 /* 0 for success, positive value for failure. */ 5779 /****************************************************************************/ 5780 static int 5781 bce_init_rx_chain(struct bce_softc *sc) 5782 { 5783 struct rx_bd *rxbd; 5784 int i, rc = 0; 5785 5786 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5787 BCE_VERBOSE_CTX); 5788 5789 /* Initialize the RX producer and consumer indices. */ 5790 sc->rx_prod = 0; 5791 sc->rx_cons = 0; 5792 sc->rx_prod_bseq = 0; 5793 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5794 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5795 5796 /* Initialize the RX next pointer chain entries. */ 5797 for (i = 0; i < sc->rx_pages; i++) { 5798 int j; 5799 5800 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5801 5802 /* Check if we've reached the last page. */ 5803 if (i == (sc->rx_pages - 1)) 5804 j = 0; 5805 else 5806 j = i + 1; 5807 5808 /* Setup the chain page pointers. */ 5809 rxbd->rx_bd_haddr_hi = 5810 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5811 rxbd->rx_bd_haddr_lo = 5812 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5813 } 5814 5815 /* Fill up the RX chain. */ 5816 bce_fill_rx_chain(sc); 5817 5818 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5819 DBRUN(sc->rx_empty_count = 0); 5820 for (i = 0; i < sc->rx_pages; i++) { 5821 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5822 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5823 } 5824 5825 bce_init_rx_context(sc); 5826 5827 DBRUNMSG(BCE_EXTREME_RECV, 5828 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5829 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5830 BCE_VERBOSE_CTX); 5831 5832 /* ToDo: Are there possible failure modes here? */ 5833 5834 return(rc); 5835 } 5836 5837 5838 /****************************************************************************/ 5839 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5840 /* occurs. */ 5841 /* */ 5842 /* Returns: */ 5843 /* Nothing */ 5844 /****************************************************************************/ 5845 static void 5846 bce_fill_rx_chain(struct bce_softc *sc) 5847 { 5848 u16 prod, prod_idx; 5849 u32 prod_bseq; 5850 5851 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5852 BCE_VERBOSE_CTX); 5853 5854 /* Get the RX chain producer indices. */ 5855 prod = sc->rx_prod; 5856 prod_bseq = sc->rx_prod_bseq; 5857 5858 /* Keep filling the RX chain until it's full. */ 5859 while (sc->free_rx_bd > 0) { 5860 prod_idx = RX_CHAIN_IDX(prod); 5861 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5862 /* Bail out if we can't add an mbuf to the chain. */ 5863 break; 5864 } 5865 prod = NEXT_RX_BD(prod); 5866 } 5867 5868 /* Save the RX chain producer indices. */ 5869 sc->rx_prod = prod; 5870 sc->rx_prod_bseq = prod_bseq; 5871 5872 /* We should never end up pointing to a next page pointer. */ 5873 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5874 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5875 __FUNCTION__, sc->rx_prod)); 5876 5877 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5878 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5879 BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); 5880 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + 5881 BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); 5882 5883 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5884 BCE_VERBOSE_CTX); 5885 } 5886 5887 5888 /****************************************************************************/ 5889 /* Free memory and clear the RX data structures. */ 5890 /* */ 5891 /* Returns: */ 5892 /* Nothing. */ 5893 /****************************************************************************/ 5894 static void 5895 bce_free_rx_chain(struct bce_softc *sc) 5896 { 5897 int i; 5898 5899 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5900 5901 /* Free any mbufs still in the RX mbuf chain. */ 5902 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5903 if (sc->rx_mbuf_ptr[i] != NULL) { 5904 if (sc->rx_mbuf_map[i] != NULL) 5905 bus_dmamap_sync(sc->rx_mbuf_tag, 5906 sc->rx_mbuf_map[i], 5907 BUS_DMASYNC_POSTREAD); 5908 m_freem(sc->rx_mbuf_ptr[i]); 5909 sc->rx_mbuf_ptr[i] = NULL; 5910 DBRUN(sc->debug_rx_mbuf_alloc--); 5911 } 5912 } 5913 5914 /* Clear each RX chain page. */ 5915 for (i = 0; i < sc->rx_pages; i++) 5916 if (sc->rx_bd_chain[i] != NULL) { 5917 bzero((char *)sc->rx_bd_chain[i], 5918 BCE_RX_CHAIN_PAGE_SZ); 5919 } 5920 5921 sc->free_rx_bd = sc->max_rx_bd; 5922 5923 /* Check if we lost any mbufs in the process. */ 5924 DBRUNIF((sc->debug_rx_mbuf_alloc), 5925 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5926 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5927 5928 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5929 } 5930 5931 5932 /****************************************************************************/ 5933 /* Allocate memory and initialize the page data structures. */ 5934 /* Assumes that bce_init_rx_chain() has not already been called. */ 5935 /* */ 5936 /* Returns: */ 5937 /* 0 for success, positive value for failure. */ 5938 /****************************************************************************/ 5939 static int 5940 bce_init_pg_chain(struct bce_softc *sc) 5941 { 5942 struct rx_bd *pgbd; 5943 int i, rc = 0; 5944 u32 val; 5945 5946 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5947 BCE_VERBOSE_CTX); 5948 5949 /* Initialize the page producer and consumer indices. */ 5950 sc->pg_prod = 0; 5951 sc->pg_cons = 0; 5952 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5953 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5954 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5955 DBRUN(sc->pg_empty_count = 0); 5956 5957 /* Initialize the page next pointer chain entries. */ 5958 for (i = 0; i < sc->pg_pages; i++) { 5959 int j; 5960 5961 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5962 5963 /* Check if we've reached the last page. */ 5964 if (i == (sc->pg_pages - 1)) 5965 j = 0; 5966 else 5967 j = i + 1; 5968 5969 /* Setup the chain page pointers. */ 5970 pgbd->rx_bd_haddr_hi = 5971 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5972 pgbd->rx_bd_haddr_lo = 5973 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5974 } 5975 5976 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5977 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5978 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5979 5980 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5981 5982 /* Configure the rx_bd and page chain mbuf cluster size. */ 5983 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5984 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5985 5986 /* Configure the context reserved for jumbo support. */ 5987 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5988 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5989 5990 /* Point the hardware to the first page in the page chain. */ 5991 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5992 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5993 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5994 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5995 5996 /* Fill up the page chain. */ 5997 bce_fill_pg_chain(sc); 5998 5999 for (i = 0; i < sc->pg_pages; i++) { 6000 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6001 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6002 } 6003 6004 DBRUNMSG(BCE_EXTREME_RECV, 6005 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6006 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6007 BCE_VERBOSE_CTX); 6008 return(rc); 6009 } 6010 6011 6012 /****************************************************************************/ 6013 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 6014 /* occurs. */ 6015 /* */ 6016 /* Returns: */ 6017 /* Nothing */ 6018 /****************************************************************************/ 6019 static void 6020 bce_fill_pg_chain(struct bce_softc *sc) 6021 { 6022 u16 prod, prod_idx; 6023 6024 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6025 BCE_VERBOSE_CTX); 6026 6027 /* Get the page chain prodcuer index. */ 6028 prod = sc->pg_prod; 6029 6030 /* Keep filling the page chain until it's full. */ 6031 while (sc->free_pg_bd > 0) { 6032 prod_idx = PG_CHAIN_IDX(prod); 6033 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 6034 /* Bail out if we can't add an mbuf to the chain. */ 6035 break; 6036 } 6037 prod = NEXT_PG_BD(prod); 6038 } 6039 6040 /* Save the page chain producer index. */ 6041 sc->pg_prod = prod; 6042 6043 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6044 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6045 __FUNCTION__, sc->pg_prod)); 6046 6047 /* 6048 * Write the mailbox and tell the chip about 6049 * the new rx_bd's in the page chain. 6050 */ 6051 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 6052 BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); 6053 6054 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6055 BCE_VERBOSE_CTX); 6056 } 6057 6058 6059 /****************************************************************************/ 6060 /* Free memory and clear the RX data structures. */ 6061 /* */ 6062 /* Returns: */ 6063 /* Nothing. */ 6064 /****************************************************************************/ 6065 static void 6066 bce_free_pg_chain(struct bce_softc *sc) 6067 { 6068 int i; 6069 6070 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6071 6072 /* Free any mbufs still in the mbuf page chain. */ 6073 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6074 if (sc->pg_mbuf_ptr[i] != NULL) { 6075 if (sc->pg_mbuf_map[i] != NULL) 6076 bus_dmamap_sync(sc->pg_mbuf_tag, 6077 sc->pg_mbuf_map[i], 6078 BUS_DMASYNC_POSTREAD); 6079 m_freem(sc->pg_mbuf_ptr[i]); 6080 sc->pg_mbuf_ptr[i] = NULL; 6081 DBRUN(sc->debug_pg_mbuf_alloc--); 6082 } 6083 } 6084 6085 /* Clear each page chain pages. */ 6086 for (i = 0; i < sc->pg_pages; i++) 6087 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6088 6089 sc->free_pg_bd = sc->max_pg_bd; 6090 6091 /* Check if we lost any mbufs in the process. */ 6092 DBRUNIF((sc->debug_pg_mbuf_alloc), 6093 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6094 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6095 6096 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6097 } 6098 6099 6100 /****************************************************************************/ 6101 /* Set media options. */ 6102 /* */ 6103 /* Returns: */ 6104 /* 0 for success, positive value for failure. */ 6105 /****************************************************************************/ 6106 static int 6107 bce_ifmedia_upd(struct ifnet *ifp) 6108 { 6109 struct bce_softc *sc = ifp->if_softc; 6110 int error; 6111 6112 DBENTER(BCE_VERBOSE); 6113 6114 BCE_LOCK(sc); 6115 error = bce_ifmedia_upd_locked(ifp); 6116 BCE_UNLOCK(sc); 6117 6118 DBEXIT(BCE_VERBOSE); 6119 return (error); 6120 } 6121 6122 6123 /****************************************************************************/ 6124 /* Set media options. */ 6125 /* */ 6126 /* Returns: */ 6127 /* Nothing. */ 6128 /****************************************************************************/ 6129 static int 6130 bce_ifmedia_upd_locked(struct ifnet *ifp) 6131 { 6132 struct bce_softc *sc = ifp->if_softc; 6133 struct mii_data *mii; 6134 struct mii_softc *miisc; 6135 int error; 6136 6137 DBENTER(BCE_VERBOSE_PHY); 6138 6139 error = 0; 6140 BCE_LOCK_ASSERT(sc); 6141 6142 mii = device_get_softc(sc->bce_miibus); 6143 6144 /* Make sure the MII bus has been enumerated. */ 6145 if (mii) { 6146 sc->bce_link_up = FALSE; 6147 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6148 PHY_RESET(miisc); 6149 error = mii_mediachg(mii); 6150 } 6151 6152 DBEXIT(BCE_VERBOSE_PHY); 6153 return (error); 6154 } 6155 6156 6157 /****************************************************************************/ 6158 /* Reports current media status. */ 6159 /* */ 6160 /* Returns: */ 6161 /* Nothing. */ 6162 /****************************************************************************/ 6163 static void 6164 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6165 { 6166 struct bce_softc *sc = ifp->if_softc; 6167 struct mii_data *mii; 6168 6169 DBENTER(BCE_VERBOSE_PHY); 6170 6171 BCE_LOCK(sc); 6172 6173 if ((ifp->if_flags & IFF_UP) == 0) { 6174 BCE_UNLOCK(sc); 6175 return; 6176 } 6177 mii = device_get_softc(sc->bce_miibus); 6178 6179 mii_pollstat(mii); 6180 ifmr->ifm_active = mii->mii_media_active; 6181 ifmr->ifm_status = mii->mii_media_status; 6182 6183 BCE_UNLOCK(sc); 6184 6185 DBEXIT(BCE_VERBOSE_PHY); 6186 } 6187 6188 6189 /****************************************************************************/ 6190 /* Handles PHY generated interrupt events. */ 6191 /* */ 6192 /* Returns: */ 6193 /* Nothing. */ 6194 /****************************************************************************/ 6195 static void 6196 bce_phy_intr(struct bce_softc *sc) 6197 { 6198 u32 new_link_state, old_link_state; 6199 6200 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6201 6202 DBRUN(sc->phy_interrupts++); 6203 6204 new_link_state = sc->status_block->status_attn_bits & 6205 STATUS_ATTN_BITS_LINK_STATE; 6206 old_link_state = sc->status_block->status_attn_bits_ack & 6207 STATUS_ATTN_BITS_LINK_STATE; 6208 6209 /* Handle any changes if the link state has changed. */ 6210 if (new_link_state != old_link_state) { 6211 6212 /* Update the status_attn_bits_ack field. */ 6213 if (new_link_state) { 6214 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6215 STATUS_ATTN_BITS_LINK_STATE); 6216 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6217 __FUNCTION__); 6218 } 6219 else { 6220 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6221 STATUS_ATTN_BITS_LINK_STATE); 6222 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6223 __FUNCTION__); 6224 } 6225 /* 6226 * Link state changed, allow tick routine to update 6227 * the state baased on actual media state. 6228 */ 6229 sc->bce_link_tick = TRUE; 6230 } 6231 6232 /* Acknowledge the link change interrupt. */ 6233 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6234 6235 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6236 } 6237 6238 6239 /****************************************************************************/ 6240 /* Reads the receive consumer value from the status block (skipping over */ 6241 /* chain page pointer if necessary). */ 6242 /* */ 6243 /* Returns: */ 6244 /* hw_cons */ 6245 /****************************************************************************/ 6246 static inline u16 6247 bce_get_hw_rx_cons(struct bce_softc *sc) 6248 { 6249 u16 hw_cons; 6250 6251 rmb(); 6252 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6253 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6254 hw_cons++; 6255 6256 return hw_cons; 6257 } 6258 6259 /****************************************************************************/ 6260 /* Handles received frame interrupt events. */ 6261 /* */ 6262 /* Returns: */ 6263 /* Nothing. */ 6264 /****************************************************************************/ 6265 static void 6266 bce_rx_intr(struct bce_softc *sc) 6267 { 6268 struct ifnet *ifp = sc->bce_ifp; 6269 struct l2_fhdr *l2fhdr; 6270 struct ether_vlan_header *vh; 6271 unsigned int pkt_len; 6272 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6273 u32 status; 6274 unsigned int rem_len; 6275 u16 sw_pg_cons, sw_pg_cons_idx; 6276 6277 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6278 DBRUN(sc->interrupts_rx++); 6279 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6280 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6281 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6282 6283 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6284 for (int i = 0; i < sc->rx_pages; i++) 6285 bus_dmamap_sync(sc->rx_bd_chain_tag, 6286 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6287 6288 /* Prepare the page chain pages to be accessed by the host CPU. */ 6289 if (bce_hdr_split == TRUE) { 6290 for (int i = 0; i < sc->pg_pages; i++) 6291 bus_dmamap_sync(sc->pg_bd_chain_tag, 6292 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6293 } 6294 6295 /* Get the hardware's view of the RX consumer index. */ 6296 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6297 6298 /* Get working copies of the driver's view of the consumer indices. */ 6299 sw_rx_cons = sc->rx_cons; 6300 sw_pg_cons = sc->pg_cons; 6301 6302 /* Update some debug statistics counters */ 6303 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6304 sc->rx_low_watermark = sc->free_rx_bd); 6305 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6306 sc->rx_empty_count++); 6307 6308 /* Scan through the receive chain as long as there is work to do */ 6309 /* ToDo: Consider setting a limit on the number of packets processed. */ 6310 rmb(); 6311 while (sw_rx_cons != hw_rx_cons) { 6312 struct mbuf *m0; 6313 6314 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6315 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6316 6317 /* Unmap the mbuf from DMA space. */ 6318 bus_dmamap_sync(sc->rx_mbuf_tag, 6319 sc->rx_mbuf_map[sw_rx_cons_idx], 6320 BUS_DMASYNC_POSTREAD); 6321 bus_dmamap_unload(sc->rx_mbuf_tag, 6322 sc->rx_mbuf_map[sw_rx_cons_idx]); 6323 6324 /* Remove the mbuf from the RX chain. */ 6325 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6326 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6327 DBRUN(sc->debug_rx_mbuf_alloc--); 6328 sc->free_rx_bd++; 6329 6330 if(m0 == NULL) { 6331 DBPRINT(sc, BCE_EXTREME_RECV, 6332 "%s(): Oops! Empty mbuf pointer " 6333 "found in sc->rx_mbuf_ptr[0x%04X]!\n", 6334 __FUNCTION__, sw_rx_cons_idx); 6335 goto bce_rx_int_next_rx; 6336 } 6337 6338 /* 6339 * Frames received on the NetXteme II are prepended 6340 * with an l2_fhdr structure which provides status 6341 * information about the received frame (including 6342 * VLAN tags and checksum info). The frames are 6343 * also automatically adjusted to word align the IP 6344 * header (i.e. two null bytes are inserted before 6345 * the Ethernet header). As a result the data 6346 * DMA'd by the controller into the mbuf looks 6347 * like this: 6348 * 6349 * +---------+-----+---------------------+-----+ 6350 * | l2_fhdr | pad | packet data | FCS | 6351 * +---------+-----+---------------------+-----+ 6352 * 6353 * The l2_fhdr needs to be checked and skipped and 6354 * the FCS needs to be stripped before sending the 6355 * packet up the stack. 6356 */ 6357 l2fhdr = mtod(m0, struct l2_fhdr *); 6358 6359 /* Get the packet data + FCS length and the status. */ 6360 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6361 status = l2fhdr->l2_fhdr_status; 6362 6363 /* 6364 * Skip over the l2_fhdr and pad, resulting in the 6365 * following data in the mbuf: 6366 * +---------------------+-----+ 6367 * | packet data | FCS | 6368 * +---------------------+-----+ 6369 */ 6370 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6371 6372 /* 6373 * When split header mode is used, an ethernet frame 6374 * may be split across the receive chain and the 6375 * page chain. If that occurs an mbuf cluster must be 6376 * reassembled from the individual mbuf pieces. 6377 */ 6378 if (bce_hdr_split == TRUE) { 6379 /* 6380 * Check whether the received frame fits in a single 6381 * mbuf or not (i.e. packet data + FCS <= 6382 * sc->rx_bd_mbuf_data_len bytes). 6383 */ 6384 if (pkt_len > m0->m_len) { 6385 /* 6386 * The received frame is larger than a single mbuf. 6387 * If the frame was a TCP frame then only the TCP 6388 * header is placed in the mbuf, the remaining 6389 * payload (including FCS) is placed in the page 6390 * chain, the SPLIT flag is set, and the header 6391 * length is placed in the IP checksum field. 6392 * If the frame is not a TCP frame then the mbuf 6393 * is filled and the remaining bytes are placed 6394 * in the page chain. 6395 */ 6396 6397 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6398 "packet.\n", __FUNCTION__); 6399 DBRUN(sc->split_header_frames_rcvd++); 6400 6401 /* 6402 * When the page chain is enabled and the TCP 6403 * header has been split from the TCP payload, 6404 * the ip_xsum structure will reflect the length 6405 * of the TCP header, not the IP checksum. Set 6406 * the packet length of the mbuf accordingly. 6407 */ 6408 if (status & L2_FHDR_STATUS_SPLIT) { 6409 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6410 DBRUN(sc->split_header_tcp_frames_rcvd++); 6411 } 6412 6413 rem_len = pkt_len - m0->m_len; 6414 6415 /* Pull mbufs off the page chain for any remaining data. */ 6416 while (rem_len > 0) { 6417 struct mbuf *m_pg; 6418 6419 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6420 6421 /* Remove the mbuf from the page chain. */ 6422 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6423 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6424 DBRUN(sc->debug_pg_mbuf_alloc--); 6425 sc->free_pg_bd++; 6426 6427 /* Unmap the page chain mbuf from DMA space. */ 6428 bus_dmamap_sync(sc->pg_mbuf_tag, 6429 sc->pg_mbuf_map[sw_pg_cons_idx], 6430 BUS_DMASYNC_POSTREAD); 6431 bus_dmamap_unload(sc->pg_mbuf_tag, 6432 sc->pg_mbuf_map[sw_pg_cons_idx]); 6433 6434 /* Adjust the mbuf length. */ 6435 if (rem_len < m_pg->m_len) { 6436 /* The mbuf chain is complete. */ 6437 m_pg->m_len = rem_len; 6438 rem_len = 0; 6439 } else { 6440 /* More packet data is waiting. */ 6441 rem_len -= m_pg->m_len; 6442 } 6443 6444 /* Concatenate the mbuf cluster to the mbuf. */ 6445 m_cat(m0, m_pg); 6446 6447 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6448 } 6449 6450 /* Set the total packet length. */ 6451 m0->m_pkthdr.len = pkt_len; 6452 6453 } else { 6454 /* 6455 * The received packet is small and fits in a 6456 * single mbuf (i.e. the l2_fhdr + pad + packet + 6457 * FCS <= MHLEN). In other words, the packet is 6458 * 154 bytes or less in size. 6459 */ 6460 6461 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6462 "packet.\n", __FUNCTION__); 6463 6464 /* Set the total packet length. */ 6465 m0->m_pkthdr.len = m0->m_len = pkt_len; 6466 } 6467 } else 6468 /* Set the total packet length. */ 6469 m0->m_pkthdr.len = m0->m_len = pkt_len; 6470 6471 /* Remove the trailing Ethernet FCS. */ 6472 m_adj(m0, -ETHER_CRC_LEN); 6473 6474 /* Check that the resulting mbuf chain is valid. */ 6475 DBRUN(m_sanity(m0, FALSE)); 6476 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6477 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6478 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6479 m_print(m0, 128)); 6480 6481 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6482 sc->l2fhdr_error_sim_count++; 6483 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6484 6485 /* Check the received frame for errors. */ 6486 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6487 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6488 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6489 6490 /* Log the error and release the mbuf. */ 6491 ifp->if_ierrors++; 6492 sc->l2fhdr_error_count++; 6493 6494 m_freem(m0); 6495 m0 = NULL; 6496 goto bce_rx_int_next_rx; 6497 } 6498 6499 /* Send the packet to the appropriate interface. */ 6500 m0->m_pkthdr.rcvif = ifp; 6501 6502 /* Assume no hardware checksum. */ 6503 m0->m_pkthdr.csum_flags = 0; 6504 6505 /* Validate the checksum if offload enabled. */ 6506 if (ifp->if_capenable & IFCAP_RXCSUM) { 6507 6508 /* Check for an IP datagram. */ 6509 if (!(status & L2_FHDR_STATUS_SPLIT) && 6510 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6511 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6512 DBRUN(sc->csum_offload_ip++); 6513 /* Check if the IP checksum is valid. */ 6514 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6515 m0->m_pkthdr.csum_flags |= 6516 CSUM_IP_VALID; 6517 } 6518 6519 /* Check for a valid TCP/UDP frame. */ 6520 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6521 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6522 6523 /* Check for a good TCP/UDP checksum. */ 6524 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6525 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6526 DBRUN(sc->csum_offload_tcp_udp++); 6527 m0->m_pkthdr.csum_data = 6528 l2fhdr->l2_fhdr_tcp_udp_xsum; 6529 m0->m_pkthdr.csum_flags |= 6530 (CSUM_DATA_VALID 6531 | CSUM_PSEUDO_HDR); 6532 } 6533 } 6534 } 6535 6536 /* Attach the VLAN tag. */ 6537 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6538 DBRUN(sc->vlan_tagged_frames_rcvd++); 6539 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6540 DBRUN(sc->vlan_tagged_frames_stripped++); 6541 #if __FreeBSD_version < 700000 6542 VLAN_INPUT_TAG(ifp, m0, 6543 l2fhdr->l2_fhdr_vlan_tag, continue); 6544 #else 6545 m0->m_pkthdr.ether_vtag = 6546 l2fhdr->l2_fhdr_vlan_tag; 6547 m0->m_flags |= M_VLANTAG; 6548 #endif 6549 } else { 6550 /* 6551 * bce(4) controllers can't disable VLAN 6552 * tag stripping if management firmware 6553 * (ASF/IPMI/UMP) is running. So we always 6554 * strip VLAN tag and manually reconstruct 6555 * the VLAN frame by appending stripped 6556 * VLAN tag in driver if VLAN tag stripping 6557 * was disabled. 6558 * 6559 * TODO: LLC SNAP handling. 6560 */ 6561 bcopy(mtod(m0, uint8_t *), 6562 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6563 ETHER_ADDR_LEN * 2); 6564 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6565 vh = mtod(m0, struct ether_vlan_header *); 6566 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6567 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6568 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6569 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6570 } 6571 } 6572 6573 /* Increment received packet statistics. */ 6574 ifp->if_ipackets++; 6575 6576 bce_rx_int_next_rx: 6577 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6578 6579 /* If we have a packet, pass it up the stack */ 6580 if (m0) { 6581 /* Make sure we don't lose our place when we release the lock. */ 6582 sc->rx_cons = sw_rx_cons; 6583 sc->pg_cons = sw_pg_cons; 6584 6585 BCE_UNLOCK(sc); 6586 (*ifp->if_input)(ifp, m0); 6587 BCE_LOCK(sc); 6588 6589 /* Recover our place. */ 6590 sw_rx_cons = sc->rx_cons; 6591 sw_pg_cons = sc->pg_cons; 6592 } 6593 6594 /* Refresh hw_cons to see if there's new work */ 6595 if (sw_rx_cons == hw_rx_cons) 6596 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6597 } 6598 6599 /* No new packets. Refill the page chain. */ 6600 if (bce_hdr_split == TRUE) { 6601 sc->pg_cons = sw_pg_cons; 6602 bce_fill_pg_chain(sc); 6603 } 6604 6605 /* No new packets. Refill the RX chain. */ 6606 sc->rx_cons = sw_rx_cons; 6607 bce_fill_rx_chain(sc); 6608 6609 /* Prepare the page chain pages to be accessed by the NIC. */ 6610 for (int i = 0; i < sc->rx_pages; i++) 6611 bus_dmamap_sync(sc->rx_bd_chain_tag, 6612 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6613 6614 if (bce_hdr_split == TRUE) { 6615 for (int i = 0; i < sc->pg_pages; i++) 6616 bus_dmamap_sync(sc->pg_bd_chain_tag, 6617 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6618 } 6619 6620 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6621 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6622 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6623 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6624 } 6625 6626 6627 /****************************************************************************/ 6628 /* Reads the transmit consumer value from the status block (skipping over */ 6629 /* chain page pointer if necessary). */ 6630 /* */ 6631 /* Returns: */ 6632 /* hw_cons */ 6633 /****************************************************************************/ 6634 static inline u16 6635 bce_get_hw_tx_cons(struct bce_softc *sc) 6636 { 6637 u16 hw_cons; 6638 6639 mb(); 6640 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6641 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6642 hw_cons++; 6643 6644 return hw_cons; 6645 } 6646 6647 6648 /****************************************************************************/ 6649 /* Handles transmit completion interrupt events. */ 6650 /* */ 6651 /* Returns: */ 6652 /* Nothing. */ 6653 /****************************************************************************/ 6654 static void 6655 bce_tx_intr(struct bce_softc *sc) 6656 { 6657 struct ifnet *ifp = sc->bce_ifp; 6658 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6659 6660 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6661 DBRUN(sc->interrupts_tx++); 6662 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6663 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6664 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6665 6666 BCE_LOCK_ASSERT(sc); 6667 6668 /* Get the hardware's view of the TX consumer index. */ 6669 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6670 sw_tx_cons = sc->tx_cons; 6671 6672 /* Prevent speculative reads of the status block. */ 6673 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6674 BUS_SPACE_BARRIER_READ); 6675 6676 /* Cycle through any completed TX chain page entries. */ 6677 while (sw_tx_cons != hw_tx_cons) { 6678 #ifdef BCE_DEBUG 6679 struct tx_bd *txbd = NULL; 6680 #endif 6681 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6682 6683 DBPRINT(sc, BCE_INFO_SEND, 6684 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6685 "sw_tx_chain_cons = 0x%04X\n", 6686 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6687 6688 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6689 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6690 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6691 (int) MAX_TX_BD_ALLOC); 6692 bce_breakpoint(sc)); 6693 6694 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6695 [TX_IDX(sw_tx_chain_cons)]); 6696 6697 DBRUNIF((txbd == NULL), 6698 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6699 __FILE__, __LINE__, sw_tx_chain_cons); 6700 bce_breakpoint(sc)); 6701 6702 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6703 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6704 6705 /* 6706 * Free the associated mbuf. Remember 6707 * that only the last tx_bd of a packet 6708 * has an mbuf pointer and DMA map. 6709 */ 6710 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6711 6712 /* Validate that this is the last tx_bd. */ 6713 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6714 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6715 "txmbuf == NULL!\n", __FILE__, __LINE__); 6716 bce_breakpoint(sc)); 6717 6718 DBRUNMSG(BCE_INFO_SEND, 6719 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6720 "from tx_bd[0x%04X]\n", __FUNCTION__, 6721 sw_tx_chain_cons)); 6722 6723 /* Unmap the mbuf. */ 6724 bus_dmamap_unload(sc->tx_mbuf_tag, 6725 sc->tx_mbuf_map[sw_tx_chain_cons]); 6726 6727 /* Free the mbuf. */ 6728 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6729 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6730 DBRUN(sc->debug_tx_mbuf_alloc--); 6731 6732 ifp->if_opackets++; 6733 } 6734 6735 sc->used_tx_bd--; 6736 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6737 6738 /* Refresh hw_cons to see if there's new work. */ 6739 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6740 6741 /* Prevent speculative reads of the status block. */ 6742 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6743 BUS_SPACE_BARRIER_READ); 6744 } 6745 6746 /* Clear the TX timeout timer. */ 6747 sc->watchdog_timer = 0; 6748 6749 /* Clear the tx hardware queue full flag. */ 6750 if (sc->used_tx_bd < sc->max_tx_bd) { 6751 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6752 DBPRINT(sc, BCE_INFO_SEND, 6753 "%s(): Open TX chain! %d/%d (used/total)\n", 6754 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6755 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6756 } 6757 6758 sc->tx_cons = sw_tx_cons; 6759 6760 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6761 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6762 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6763 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6764 } 6765 6766 6767 /****************************************************************************/ 6768 /* Disables interrupt generation. */ 6769 /* */ 6770 /* Returns: */ 6771 /* Nothing. */ 6772 /****************************************************************************/ 6773 static void 6774 bce_disable_intr(struct bce_softc *sc) 6775 { 6776 DBENTER(BCE_VERBOSE_INTR); 6777 6778 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6779 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6780 6781 DBEXIT(BCE_VERBOSE_INTR); 6782 } 6783 6784 6785 /****************************************************************************/ 6786 /* Enables interrupt generation. */ 6787 /* */ 6788 /* Returns: */ 6789 /* Nothing. */ 6790 /****************************************************************************/ 6791 static void 6792 bce_enable_intr(struct bce_softc *sc, int coal_now) 6793 { 6794 DBENTER(BCE_VERBOSE_INTR); 6795 6796 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6797 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6798 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6799 6800 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6801 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6802 6803 /* Force an immediate interrupt (whether there is new data or not). */ 6804 if (coal_now) 6805 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6806 6807 DBEXIT(BCE_VERBOSE_INTR); 6808 } 6809 6810 6811 /****************************************************************************/ 6812 /* Handles controller initialization. */ 6813 /* */ 6814 /* Returns: */ 6815 /* Nothing. */ 6816 /****************************************************************************/ 6817 static void 6818 bce_init_locked(struct bce_softc *sc) 6819 { 6820 struct ifnet *ifp; 6821 u32 ether_mtu = 0; 6822 6823 DBENTER(BCE_VERBOSE_RESET); 6824 6825 BCE_LOCK_ASSERT(sc); 6826 6827 ifp = sc->bce_ifp; 6828 6829 /* Check if the driver is still running and bail out if it is. */ 6830 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6831 goto bce_init_locked_exit; 6832 6833 bce_stop(sc); 6834 6835 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6836 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6837 __FILE__, __LINE__); 6838 goto bce_init_locked_exit; 6839 } 6840 6841 if (bce_chipinit(sc)) { 6842 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6843 __FILE__, __LINE__); 6844 goto bce_init_locked_exit; 6845 } 6846 6847 if (bce_blockinit(sc)) { 6848 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6849 __FILE__, __LINE__); 6850 goto bce_init_locked_exit; 6851 } 6852 6853 /* Load our MAC address. */ 6854 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6855 bce_set_mac_addr(sc); 6856 6857 /* 6858 * Calculate and program the hardware Ethernet MTU 6859 * size. Be generous on the receive if we have room 6860 * and allowed by the user. 6861 */ 6862 if (bce_strict_rx_mtu == TRUE) 6863 ether_mtu = ifp->if_mtu; 6864 else { 6865 if (bce_hdr_split == TRUE) { 6866 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + 6867 sc->pg_bd_mbuf_alloc_size)) 6868 ether_mtu = sc->rx_bd_mbuf_data_len + 6869 sc->pg_bd_mbuf_alloc_size; 6870 else 6871 ether_mtu = ifp->if_mtu; 6872 } else { 6873 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6874 ether_mtu = sc->rx_bd_mbuf_data_len; 6875 else 6876 ether_mtu = ifp->if_mtu; 6877 } 6878 } 6879 6880 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6881 6882 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 6883 __FUNCTION__, ether_mtu); 6884 6885 /* Program the mtu, enabling jumbo frame support if necessary. */ 6886 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6887 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6888 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6889 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6890 else 6891 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6892 6893 /* Program appropriate promiscuous/multicast filtering. */ 6894 bce_set_rx_mode(sc); 6895 6896 if (bce_hdr_split == TRUE) { 6897 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6898 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6899 6900 /* Init page buffer descriptor chain. */ 6901 bce_init_pg_chain(sc); 6902 } 6903 6904 /* Init RX buffer descriptor chain. */ 6905 bce_init_rx_chain(sc); 6906 6907 /* Init TX buffer descriptor chain. */ 6908 bce_init_tx_chain(sc); 6909 6910 /* Enable host interrupts. */ 6911 bce_enable_intr(sc, 1); 6912 6913 /* Let the OS know the driver is up and running. */ 6914 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6915 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6916 6917 sc->bce_link_tick = TRUE; 6918 bce_ifmedia_upd_locked(ifp); 6919 6920 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6921 6922 bce_init_locked_exit: 6923 DBEXIT(BCE_VERBOSE_RESET); 6924 } 6925 6926 6927 /****************************************************************************/ 6928 /* Initialize the controller just enough so that any management firmware */ 6929 /* running on the device will continue to operate correctly. */ 6930 /* */ 6931 /* Returns: */ 6932 /* Nothing. */ 6933 /****************************************************************************/ 6934 static void 6935 bce_mgmt_init_locked(struct bce_softc *sc) 6936 { 6937 struct ifnet *ifp; 6938 6939 DBENTER(BCE_VERBOSE_RESET); 6940 6941 BCE_LOCK_ASSERT(sc); 6942 6943 /* Bail out if management firmware is not running. */ 6944 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6945 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6946 "No management firmware running...\n"); 6947 goto bce_mgmt_init_locked_exit; 6948 } 6949 6950 ifp = sc->bce_ifp; 6951 6952 /* Enable all critical blocks in the MAC. */ 6953 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6954 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6955 DELAY(20); 6956 6957 bce_ifmedia_upd_locked(ifp); 6958 6959 bce_mgmt_init_locked_exit: 6960 DBEXIT(BCE_VERBOSE_RESET); 6961 } 6962 6963 6964 /****************************************************************************/ 6965 /* Handles controller initialization when called from an unlocked routine. */ 6966 /* */ 6967 /* Returns: */ 6968 /* Nothing. */ 6969 /****************************************************************************/ 6970 static void 6971 bce_init(void *xsc) 6972 { 6973 struct bce_softc *sc = xsc; 6974 6975 DBENTER(BCE_VERBOSE_RESET); 6976 6977 BCE_LOCK(sc); 6978 bce_init_locked(sc); 6979 BCE_UNLOCK(sc); 6980 6981 DBEXIT(BCE_VERBOSE_RESET); 6982 } 6983 6984 6985 /****************************************************************************/ 6986 /* Modifies an mbuf for TSO on the hardware. */ 6987 /* */ 6988 /* Returns: */ 6989 /* Pointer to a modified mbuf. */ 6990 /****************************************************************************/ 6991 static struct mbuf * 6992 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 6993 { 6994 struct mbuf *m; 6995 struct ether_header *eh; 6996 struct ip *ip; 6997 struct tcphdr *th; 6998 u16 etype; 6999 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7000 7001 DBRUN(sc->tso_frames_requested++); 7002 7003 /* Controller may modify mbuf chains. */ 7004 if (M_WRITABLE(*m_head) == 0) { 7005 m = m_dup(*m_head, M_DONTWAIT); 7006 m_freem(*m_head); 7007 if (m == NULL) { 7008 sc->mbuf_alloc_failed_count++; 7009 *m_head = NULL; 7010 return (NULL); 7011 } 7012 *m_head = m; 7013 } 7014 7015 /* 7016 * For TSO the controller needs two pieces of info, 7017 * the MSS and the IP+TCP options length. 7018 */ 7019 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7020 if (m == NULL) { 7021 *m_head = NULL; 7022 return (NULL); 7023 } 7024 eh = mtod(m, struct ether_header *); 7025 etype = ntohs(eh->ether_type); 7026 7027 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7028 switch (etype) { 7029 case ETHERTYPE_IP: 7030 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7031 /* TSO only supported for TCP protocol. */ 7032 if (ip->ip_p != IPPROTO_TCP) { 7033 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7034 __FILE__, __LINE__); 7035 m_freem(*m_head); 7036 *m_head = NULL; 7037 return (NULL); 7038 } 7039 7040 /* Get IP header length in bytes (min 20) */ 7041 ip_hlen = ip->ip_hl << 2; 7042 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7043 sizeof(struct tcphdr)); 7044 if (m == NULL) { 7045 *m_head = NULL; 7046 return (NULL); 7047 } 7048 7049 /* Get the TCP header length in bytes (min 20) */ 7050 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7051 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7052 tcp_hlen = (th->th_off << 2); 7053 7054 /* Make sure all IP/TCP options live in the same buffer. */ 7055 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7056 tcp_hlen); 7057 if (m == NULL) { 7058 *m_head = NULL; 7059 return (NULL); 7060 } 7061 7062 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7063 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7064 ip_len = ip->ip_len; 7065 ip->ip_len = 0; 7066 ip->ip_sum = 0; 7067 break; 7068 case ETHERTYPE_IPV6: 7069 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7070 __FILE__, __LINE__); 7071 m_freem(*m_head); 7072 *m_head = NULL; 7073 return (NULL); 7074 /* NOT REACHED */ 7075 default: 7076 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7077 __FILE__, __LINE__); 7078 m_freem(*m_head); 7079 *m_head = NULL; 7080 return (NULL); 7081 } 7082 7083 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7084 7085 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7086 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7087 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7088 tcp_hlen, ip_len); 7089 7090 /* Set the LSO flag in the TX BD */ 7091 *flags |= TX_BD_FLAGS_SW_LSO; 7092 7093 /* Set the length of IP + TCP options (in 32 bit words) */ 7094 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7095 sizeof(struct tcphdr)) >> 2) << 8); 7096 7097 DBRUN(sc->tso_frames_completed++); 7098 return (*m_head); 7099 } 7100 7101 7102 /****************************************************************************/ 7103 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7104 /* memory visible to the controller. */ 7105 /* */ 7106 /* Returns: */ 7107 /* 0 for success, positive value for failure. */ 7108 /* Modified: */ 7109 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7110 /****************************************************************************/ 7111 static int 7112 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7113 { 7114 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7115 bus_dmamap_t map; 7116 struct tx_bd *txbd = NULL; 7117 struct mbuf *m0; 7118 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7119 u32 prod_bseq; 7120 7121 #ifdef BCE_DEBUG 7122 u16 debug_prod; 7123 #endif 7124 7125 int i, error, nsegs, rc = 0; 7126 7127 DBENTER(BCE_VERBOSE_SEND); 7128 7129 /* Make sure we have room in the TX chain. */ 7130 if (sc->used_tx_bd >= sc->max_tx_bd) 7131 goto bce_tx_encap_exit; 7132 7133 /* Transfer any checksum offload flags to the bd. */ 7134 m0 = *m_head; 7135 if (m0->m_pkthdr.csum_flags) { 7136 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7137 m0 = bce_tso_setup(sc, m_head, &flags); 7138 if (m0 == NULL) { 7139 DBRUN(sc->tso_frames_failed++); 7140 goto bce_tx_encap_exit; 7141 } 7142 mss = htole16(m0->m_pkthdr.tso_segsz); 7143 } else { 7144 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7145 flags |= TX_BD_FLAGS_IP_CKSUM; 7146 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7147 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7148 } 7149 } 7150 7151 /* Transfer any VLAN tags to the bd. */ 7152 if (m0->m_flags & M_VLANTAG) { 7153 flags |= TX_BD_FLAGS_VLAN_TAG; 7154 vlan_tag = m0->m_pkthdr.ether_vtag; 7155 } 7156 7157 /* Map the mbuf into DMAable memory. */ 7158 prod = sc->tx_prod; 7159 chain_prod = TX_CHAIN_IDX(prod); 7160 map = sc->tx_mbuf_map[chain_prod]; 7161 7162 /* Map the mbuf into our DMA address space. */ 7163 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7164 segs, &nsegs, BUS_DMA_NOWAIT); 7165 7166 /* Check if the DMA mapping was successful */ 7167 if (error == EFBIG) { 7168 sc->mbuf_frag_count++; 7169 7170 /* Try to defrag the mbuf. */ 7171 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 7172 if (m0 == NULL) { 7173 /* Defrag was unsuccessful */ 7174 m_freem(*m_head); 7175 *m_head = NULL; 7176 sc->mbuf_alloc_failed_count++; 7177 rc = ENOBUFS; 7178 goto bce_tx_encap_exit; 7179 } 7180 7181 /* Defrag was successful, try mapping again */ 7182 *m_head = m0; 7183 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7184 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7185 7186 /* Still getting an error after a defrag. */ 7187 if (error == ENOMEM) { 7188 /* Insufficient DMA buffers available. */ 7189 sc->dma_map_addr_tx_failed_count++; 7190 rc = error; 7191 goto bce_tx_encap_exit; 7192 } else if (error != 0) { 7193 /* Release it and return an error. */ 7194 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7195 "TX chain!\n", __FILE__, __LINE__); 7196 m_freem(m0); 7197 *m_head = NULL; 7198 sc->dma_map_addr_tx_failed_count++; 7199 rc = ENOBUFS; 7200 goto bce_tx_encap_exit; 7201 } 7202 } else if (error == ENOMEM) { 7203 /* Insufficient DMA buffers available. */ 7204 sc->dma_map_addr_tx_failed_count++; 7205 rc = error; 7206 goto bce_tx_encap_exit; 7207 } else if (error != 0) { 7208 m_freem(m0); 7209 *m_head = NULL; 7210 sc->dma_map_addr_tx_failed_count++; 7211 rc = error; 7212 goto bce_tx_encap_exit; 7213 } 7214 7215 /* Make sure there's room in the chain */ 7216 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7217 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7218 rc = ENOBUFS; 7219 goto bce_tx_encap_exit; 7220 } 7221 7222 /* prod points to an empty tx_bd at this point. */ 7223 prod_bseq = sc->tx_prod_bseq; 7224 7225 #ifdef BCE_DEBUG 7226 debug_prod = chain_prod; 7227 #endif 7228 7229 DBPRINT(sc, BCE_INFO_SEND, 7230 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7231 "prod_bseq = 0x%08X\n", 7232 __FUNCTION__, prod, chain_prod, prod_bseq); 7233 7234 /* 7235 * Cycle through each mbuf segment that makes up 7236 * the outgoing frame, gathering the mapping info 7237 * for that segment and creating a tx_bd for 7238 * the mbuf. 7239 */ 7240 for (i = 0; i < nsegs ; i++) { 7241 7242 chain_prod = TX_CHAIN_IDX(prod); 7243 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7244 [TX_IDX(chain_prod)]; 7245 7246 txbd->tx_bd_haddr_lo = 7247 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7248 txbd->tx_bd_haddr_hi = 7249 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7250 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7251 htole16(segs[i].ds_len); 7252 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7253 txbd->tx_bd_flags = htole16(flags); 7254 prod_bseq += segs[i].ds_len; 7255 if (i == 0) 7256 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7257 prod = NEXT_TX_BD(prod); 7258 } 7259 7260 /* Set the END flag on the last TX buffer descriptor. */ 7261 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7262 7263 DBRUNMSG(BCE_EXTREME_SEND, 7264 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7265 7266 /* 7267 * Ensure that the mbuf pointer for this transmission 7268 * is placed at the array index of the last 7269 * descriptor in this chain. This is done 7270 * because a single map is used for all 7271 * segments of the mbuf and we don't want to 7272 * unload the map before all of the segments 7273 * have been freed. 7274 */ 7275 sc->tx_mbuf_ptr[chain_prod] = m0; 7276 sc->used_tx_bd += nsegs; 7277 7278 /* Update some debug statistic counters */ 7279 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7280 sc->tx_hi_watermark = sc->used_tx_bd); 7281 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7282 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7283 7284 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7285 7286 /* prod points to the next free tx_bd at this point. */ 7287 sc->tx_prod = prod; 7288 sc->tx_prod_bseq = prod_bseq; 7289 7290 /* Tell the chip about the waiting TX frames. */ 7291 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7292 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7293 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7294 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7295 7296 bce_tx_encap_exit: 7297 DBEXIT(BCE_VERBOSE_SEND); 7298 return(rc); 7299 } 7300 7301 7302 /****************************************************************************/ 7303 /* Main transmit routine when called from another routine with a lock. */ 7304 /* */ 7305 /* Returns: */ 7306 /* Nothing. */ 7307 /****************************************************************************/ 7308 static void 7309 bce_start_locked(struct ifnet *ifp) 7310 { 7311 struct bce_softc *sc = ifp->if_softc; 7312 struct mbuf *m_head = NULL; 7313 int count = 0; 7314 u16 tx_prod, tx_chain_prod; 7315 7316 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7317 7318 BCE_LOCK_ASSERT(sc); 7319 7320 /* prod points to the next free tx_bd. */ 7321 tx_prod = sc->tx_prod; 7322 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7323 7324 DBPRINT(sc, BCE_INFO_SEND, 7325 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7326 "tx_prod_bseq = 0x%08X\n", 7327 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7328 7329 /* If there's no link or the transmit queue is empty then just exit. */ 7330 if (sc->bce_link_up == FALSE) { 7331 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7332 __FUNCTION__); 7333 goto bce_start_locked_exit; 7334 } 7335 7336 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7337 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7338 __FUNCTION__); 7339 goto bce_start_locked_exit; 7340 } 7341 7342 /* 7343 * Keep adding entries while there is space in the ring. 7344 */ 7345 while (sc->used_tx_bd < sc->max_tx_bd) { 7346 7347 /* Check for any frames to send. */ 7348 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7349 7350 /* Stop when the transmit queue is empty. */ 7351 if (m_head == NULL) 7352 break; 7353 7354 /* 7355 * Pack the data into the transmit ring. If we 7356 * don't have room, place the mbuf back at the 7357 * head of the queue and set the OACTIVE flag 7358 * to wait for the NIC to drain the chain. 7359 */ 7360 if (bce_tx_encap(sc, &m_head)) { 7361 if (m_head != NULL) 7362 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7363 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7364 DBPRINT(sc, BCE_INFO_SEND, 7365 "TX chain is closed for business! Total " 7366 "tx_bd used = %d\n", sc->used_tx_bd); 7367 break; 7368 } 7369 7370 count++; 7371 7372 /* Send a copy of the frame to any BPF listeners. */ 7373 ETHER_BPF_MTAP(ifp, m_head); 7374 } 7375 7376 /* Exit if no packets were dequeued. */ 7377 if (count == 0) { 7378 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7379 "dequeued\n", __FUNCTION__); 7380 goto bce_start_locked_exit; 7381 } 7382 7383 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7384 "send queue.\n", __FUNCTION__, count); 7385 7386 /* Set the tx timeout. */ 7387 sc->watchdog_timer = BCE_TX_TIMEOUT; 7388 7389 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7390 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7391 7392 bce_start_locked_exit: 7393 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7394 return; 7395 } 7396 7397 7398 /****************************************************************************/ 7399 /* Main transmit routine when called from another routine without a lock. */ 7400 /* */ 7401 /* Returns: */ 7402 /* Nothing. */ 7403 /****************************************************************************/ 7404 static void 7405 bce_start(struct ifnet *ifp) 7406 { 7407 struct bce_softc *sc = ifp->if_softc; 7408 7409 DBENTER(BCE_VERBOSE_SEND); 7410 7411 BCE_LOCK(sc); 7412 bce_start_locked(ifp); 7413 BCE_UNLOCK(sc); 7414 7415 DBEXIT(BCE_VERBOSE_SEND); 7416 } 7417 7418 7419 /****************************************************************************/ 7420 /* Handles any IOCTL calls from the operating system. */ 7421 /* */ 7422 /* Returns: */ 7423 /* 0 for success, positive value for failure. */ 7424 /****************************************************************************/ 7425 static int 7426 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7427 { 7428 struct bce_softc *sc = ifp->if_softc; 7429 struct ifreq *ifr = (struct ifreq *) data; 7430 struct mii_data *mii; 7431 int mask, error = 0; 7432 7433 DBENTER(BCE_VERBOSE_MISC); 7434 7435 switch(command) { 7436 7437 /* Set the interface MTU. */ 7438 case SIOCSIFMTU: 7439 /* Check that the MTU setting is supported. */ 7440 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7441 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7442 error = EINVAL; 7443 break; 7444 } 7445 7446 DBPRINT(sc, BCE_INFO_MISC, 7447 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7448 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7449 7450 BCE_LOCK(sc); 7451 ifp->if_mtu = ifr->ifr_mtu; 7452 7453 if (bce_hdr_split == FALSE) { 7454 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7455 /* 7456 * Because allocation size is used in RX 7457 * buffer allocation, stop controller if 7458 * it is already running. 7459 */ 7460 bce_stop(sc); 7461 } 7462 7463 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7464 7465 bce_init_locked(sc); 7466 } 7467 7468 BCE_UNLOCK(sc); 7469 break; 7470 7471 /* Set interface flags. */ 7472 case SIOCSIFFLAGS: 7473 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7474 7475 BCE_LOCK(sc); 7476 7477 /* Check if the interface is up. */ 7478 if (ifp->if_flags & IFF_UP) { 7479 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7480 /* Change promiscuous/multicast flags as necessary. */ 7481 bce_set_rx_mode(sc); 7482 } else { 7483 /* Start the HW */ 7484 bce_init_locked(sc); 7485 } 7486 } else { 7487 /* The interface is down, check if driver is running. */ 7488 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7489 bce_stop(sc); 7490 7491 /* If MFW is running, restart the controller a bit. */ 7492 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7493 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7494 bce_chipinit(sc); 7495 bce_mgmt_init_locked(sc); 7496 } 7497 } 7498 } 7499 7500 BCE_UNLOCK(sc); 7501 break; 7502 7503 /* Add/Delete multicast address */ 7504 case SIOCADDMULTI: 7505 case SIOCDELMULTI: 7506 DBPRINT(sc, BCE_VERBOSE_MISC, 7507 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7508 7509 BCE_LOCK(sc); 7510 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7511 bce_set_rx_mode(sc); 7512 BCE_UNLOCK(sc); 7513 7514 break; 7515 7516 /* Set/Get Interface media */ 7517 case SIOCSIFMEDIA: 7518 case SIOCGIFMEDIA: 7519 DBPRINT(sc, BCE_VERBOSE_MISC, 7520 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7521 7522 mii = device_get_softc(sc->bce_miibus); 7523 error = ifmedia_ioctl(ifp, ifr, 7524 &mii->mii_media, command); 7525 break; 7526 7527 /* Set interface capability */ 7528 case SIOCSIFCAP: 7529 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7530 DBPRINT(sc, BCE_INFO_MISC, 7531 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7532 7533 /* Toggle the TX checksum capabilities enable flag. */ 7534 if (mask & IFCAP_TXCSUM && 7535 ifp->if_capabilities & IFCAP_TXCSUM) { 7536 ifp->if_capenable ^= IFCAP_TXCSUM; 7537 if (IFCAP_TXCSUM & ifp->if_capenable) 7538 ifp->if_hwassist |= BCE_IF_HWASSIST; 7539 else 7540 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7541 } 7542 7543 /* Toggle the RX checksum capabilities enable flag. */ 7544 if (mask & IFCAP_RXCSUM && 7545 ifp->if_capabilities & IFCAP_RXCSUM) 7546 ifp->if_capenable ^= IFCAP_RXCSUM; 7547 7548 /* Toggle the TSO capabilities enable flag. */ 7549 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7550 ifp->if_capabilities & IFCAP_TSO4) { 7551 ifp->if_capenable ^= IFCAP_TSO4; 7552 if (IFCAP_TSO4 & ifp->if_capenable) 7553 ifp->if_hwassist |= CSUM_TSO; 7554 else 7555 ifp->if_hwassist &= ~CSUM_TSO; 7556 } 7557 7558 if (mask & IFCAP_VLAN_HWCSUM && 7559 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7560 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7561 7562 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7563 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7564 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7565 /* 7566 * Don't actually disable VLAN tag stripping as 7567 * management firmware (ASF/IPMI/UMP) requires the 7568 * feature. If VLAN tag stripping is disabled driver 7569 * will manually reconstruct the VLAN frame by 7570 * appending stripped VLAN tag. 7571 */ 7572 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7573 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7574 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7575 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7576 == 0) 7577 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7578 } 7579 VLAN_CAPABILITIES(ifp); 7580 break; 7581 default: 7582 /* We don't know how to handle the IOCTL, pass it on. */ 7583 error = ether_ioctl(ifp, command, data); 7584 break; 7585 } 7586 7587 DBEXIT(BCE_VERBOSE_MISC); 7588 return(error); 7589 } 7590 7591 7592 /****************************************************************************/ 7593 /* Transmit timeout handler. */ 7594 /* */ 7595 /* Returns: */ 7596 /* Nothing. */ 7597 /****************************************************************************/ 7598 static void 7599 bce_watchdog(struct bce_softc *sc) 7600 { 7601 DBENTER(BCE_EXTREME_SEND); 7602 7603 BCE_LOCK_ASSERT(sc); 7604 7605 /* If the watchdog timer hasn't expired then just exit. */ 7606 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7607 goto bce_watchdog_exit; 7608 7609 /* If pause frames are active then don't reset the hardware. */ 7610 /* ToDo: Should we reset the timer here? */ 7611 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7612 goto bce_watchdog_exit; 7613 7614 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7615 __FILE__, __LINE__); 7616 7617 DBRUNMSG(BCE_INFO, 7618 bce_dump_driver_state(sc); 7619 bce_dump_status_block(sc); 7620 bce_dump_stats_block(sc); 7621 bce_dump_ftqs(sc); 7622 bce_dump_txp_state(sc, 0); 7623 bce_dump_rxp_state(sc, 0); 7624 bce_dump_tpat_state(sc, 0); 7625 bce_dump_cp_state(sc, 0); 7626 bce_dump_com_state(sc, 0)); 7627 7628 DBRUN(bce_breakpoint(sc)); 7629 7630 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7631 7632 bce_init_locked(sc); 7633 sc->bce_ifp->if_oerrors++; 7634 7635 bce_watchdog_exit: 7636 DBEXIT(BCE_EXTREME_SEND); 7637 } 7638 7639 7640 /* 7641 * Interrupt handler. 7642 */ 7643 /****************************************************************************/ 7644 /* Main interrupt entry point. Verifies that the controller generated the */ 7645 /* interrupt and then calls a separate routine for handle the various */ 7646 /* interrupt causes (PHY, TX, RX). */ 7647 /* */ 7648 /* Returns: */ 7649 /* 0 for success, positive value for failure. */ 7650 /****************************************************************************/ 7651 static void 7652 bce_intr(void *xsc) 7653 { 7654 struct bce_softc *sc; 7655 struct ifnet *ifp; 7656 u32 status_attn_bits; 7657 u16 hw_rx_cons, hw_tx_cons; 7658 7659 sc = xsc; 7660 ifp = sc->bce_ifp; 7661 7662 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7663 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7664 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7665 7666 BCE_LOCK(sc); 7667 7668 DBRUN(sc->interrupts_generated++); 7669 7670 /* Synchnorize before we read from interface's status block */ 7671 bus_dmamap_sync(sc->status_tag, sc->status_map, 7672 BUS_DMASYNC_POSTREAD); 7673 7674 /* 7675 * If the hardware status block index 7676 * matches the last value read by the 7677 * driver and we haven't asserted our 7678 * interrupt then there's nothing to do. 7679 */ 7680 if ((sc->status_block->status_idx == sc->last_status_idx) && 7681 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7682 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7683 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7684 __FUNCTION__); 7685 goto bce_intr_exit; 7686 } 7687 7688 /* Ack the interrupt and stop others from occuring. */ 7689 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7690 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7691 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7692 7693 /* Check if the hardware has finished any work. */ 7694 hw_rx_cons = bce_get_hw_rx_cons(sc); 7695 hw_tx_cons = bce_get_hw_tx_cons(sc); 7696 7697 /* Keep processing data as long as there is work to do. */ 7698 for (;;) { 7699 7700 status_attn_bits = sc->status_block->status_attn_bits; 7701 7702 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7703 BCE_PRINTF("Simulating unexpected status attention " 7704 "bit set."); 7705 sc->unexpected_attention_sim_count++; 7706 status_attn_bits = status_attn_bits | 7707 STATUS_ATTN_BITS_PARITY_ERROR); 7708 7709 /* Was it a link change interrupt? */ 7710 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7711 (sc->status_block->status_attn_bits_ack & 7712 STATUS_ATTN_BITS_LINK_STATE)) { 7713 bce_phy_intr(sc); 7714 7715 /* Clear transient updates during link state change. */ 7716 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7717 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7718 REG_RD(sc, BCE_HC_COMMAND); 7719 } 7720 7721 /* If any other attention is asserted, the chip is toast. */ 7722 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7723 (sc->status_block->status_attn_bits_ack & 7724 ~STATUS_ATTN_BITS_LINK_STATE))) { 7725 7726 sc->unexpected_attention_count++; 7727 7728 BCE_PRINTF("%s(%d): Fatal attention detected: " 7729 "0x%08X\n", __FILE__, __LINE__, 7730 sc->status_block->status_attn_bits); 7731 7732 DBRUNMSG(BCE_FATAL, 7733 if (unexpected_attention_sim_control == 0) 7734 bce_breakpoint(sc)); 7735 7736 bce_init_locked(sc); 7737 goto bce_intr_exit; 7738 } 7739 7740 /* Check for any completed RX frames. */ 7741 if (hw_rx_cons != sc->hw_rx_cons) 7742 bce_rx_intr(sc); 7743 7744 /* Check for any completed TX frames. */ 7745 if (hw_tx_cons != sc->hw_tx_cons) 7746 bce_tx_intr(sc); 7747 7748 /* Save status block index value for the next interrupt. */ 7749 sc->last_status_idx = sc->status_block->status_idx; 7750 7751 /* 7752 * Prevent speculative reads from getting 7753 * ahead of the status block. 7754 */ 7755 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7756 BUS_SPACE_BARRIER_READ); 7757 7758 /* 7759 * If there's no work left then exit the 7760 * interrupt service routine. 7761 */ 7762 hw_rx_cons = bce_get_hw_rx_cons(sc); 7763 hw_tx_cons = bce_get_hw_tx_cons(sc); 7764 7765 if ((hw_rx_cons == sc->hw_rx_cons) && 7766 (hw_tx_cons == sc->hw_tx_cons)) 7767 break; 7768 7769 } 7770 7771 bus_dmamap_sync(sc->status_tag, sc->status_map, 7772 BUS_DMASYNC_PREREAD); 7773 7774 /* Re-enable interrupts. */ 7775 bce_enable_intr(sc, 0); 7776 7777 /* Handle any frames that arrived while handling the interrupt. */ 7778 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7779 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7780 bce_start_locked(ifp); 7781 7782 bce_intr_exit: 7783 BCE_UNLOCK(sc); 7784 7785 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7786 } 7787 7788 7789 /****************************************************************************/ 7790 /* Programs the various packet receive modes (broadcast and multicast). */ 7791 /* */ 7792 /* Returns: */ 7793 /* Nothing. */ 7794 /****************************************************************************/ 7795 static void 7796 bce_set_rx_mode(struct bce_softc *sc) 7797 { 7798 struct ifnet *ifp; 7799 struct ifmultiaddr *ifma; 7800 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7801 u32 rx_mode, sort_mode; 7802 int h, i; 7803 7804 DBENTER(BCE_VERBOSE_MISC); 7805 7806 BCE_LOCK_ASSERT(sc); 7807 7808 ifp = sc->bce_ifp; 7809 7810 /* Initialize receive mode default settings. */ 7811 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7812 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7813 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7814 7815 /* 7816 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7817 * be enbled. 7818 */ 7819 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7820 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7821 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7822 7823 /* 7824 * Check for promiscuous, all multicast, or selected 7825 * multicast address filtering. 7826 */ 7827 if (ifp->if_flags & IFF_PROMISC) { 7828 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7829 7830 /* Enable promiscuous mode. */ 7831 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7832 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7833 } else if (ifp->if_flags & IFF_ALLMULTI) { 7834 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7835 7836 /* Enable all multicast addresses. */ 7837 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7838 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7839 } 7840 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7841 } else { 7842 /* Accept one or more multicast(s). */ 7843 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7844 7845 if_maddr_rlock(ifp); 7846 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7847 if (ifma->ifma_addr->sa_family != AF_LINK) 7848 continue; 7849 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7850 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7851 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7852 } 7853 if_maddr_runlock(ifp); 7854 7855 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7856 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7857 7858 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7859 } 7860 7861 /* Only make changes if the recive mode has actually changed. */ 7862 if (rx_mode != sc->rx_mode) { 7863 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7864 "0x%08X\n", rx_mode); 7865 7866 sc->rx_mode = rx_mode; 7867 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7868 } 7869 7870 /* Disable and clear the exisitng sort before enabling a new sort. */ 7871 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7872 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7873 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7874 7875 DBEXIT(BCE_VERBOSE_MISC); 7876 } 7877 7878 7879 /****************************************************************************/ 7880 /* Called periodically to updates statistics from the controllers */ 7881 /* statistics block. */ 7882 /* */ 7883 /* Returns: */ 7884 /* Nothing. */ 7885 /****************************************************************************/ 7886 static void 7887 bce_stats_update(struct bce_softc *sc) 7888 { 7889 struct ifnet *ifp; 7890 struct statistics_block *stats; 7891 7892 DBENTER(BCE_EXTREME_MISC); 7893 7894 ifp = sc->bce_ifp; 7895 7896 stats = (struct statistics_block *) sc->stats_block; 7897 7898 /* 7899 * Certain controllers don't report 7900 * carrier sense errors correctly. 7901 * See errata E11_5708CA0_1165. 7902 */ 7903 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7904 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7905 ifp->if_oerrors += 7906 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7907 7908 /* 7909 * Update the sysctl statistics from the 7910 * hardware statistics. 7911 */ 7912 sc->stat_IfHCInOctets = 7913 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7914 (u64) stats->stat_IfHCInOctets_lo; 7915 7916 sc->stat_IfHCInBadOctets = 7917 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7918 (u64) stats->stat_IfHCInBadOctets_lo; 7919 7920 sc->stat_IfHCOutOctets = 7921 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7922 (u64) stats->stat_IfHCOutOctets_lo; 7923 7924 sc->stat_IfHCOutBadOctets = 7925 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7926 (u64) stats->stat_IfHCOutBadOctets_lo; 7927 7928 sc->stat_IfHCInUcastPkts = 7929 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7930 (u64) stats->stat_IfHCInUcastPkts_lo; 7931 7932 sc->stat_IfHCInMulticastPkts = 7933 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7934 (u64) stats->stat_IfHCInMulticastPkts_lo; 7935 7936 sc->stat_IfHCInBroadcastPkts = 7937 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7938 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7939 7940 sc->stat_IfHCOutUcastPkts = 7941 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7942 (u64) stats->stat_IfHCOutUcastPkts_lo; 7943 7944 sc->stat_IfHCOutMulticastPkts = 7945 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7946 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7947 7948 sc->stat_IfHCOutBroadcastPkts = 7949 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7950 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7951 7952 /* ToDo: Preserve counters beyond 32 bits? */ 7953 /* ToDo: Read the statistics from auto-clear regs? */ 7954 7955 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7956 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7957 7958 sc->stat_Dot3StatsCarrierSenseErrors = 7959 stats->stat_Dot3StatsCarrierSenseErrors; 7960 7961 sc->stat_Dot3StatsFCSErrors = 7962 stats->stat_Dot3StatsFCSErrors; 7963 7964 sc->stat_Dot3StatsAlignmentErrors = 7965 stats->stat_Dot3StatsAlignmentErrors; 7966 7967 sc->stat_Dot3StatsSingleCollisionFrames = 7968 stats->stat_Dot3StatsSingleCollisionFrames; 7969 7970 sc->stat_Dot3StatsMultipleCollisionFrames = 7971 stats->stat_Dot3StatsMultipleCollisionFrames; 7972 7973 sc->stat_Dot3StatsDeferredTransmissions = 7974 stats->stat_Dot3StatsDeferredTransmissions; 7975 7976 sc->stat_Dot3StatsExcessiveCollisions = 7977 stats->stat_Dot3StatsExcessiveCollisions; 7978 7979 sc->stat_Dot3StatsLateCollisions = 7980 stats->stat_Dot3StatsLateCollisions; 7981 7982 sc->stat_EtherStatsCollisions = 7983 stats->stat_EtherStatsCollisions; 7984 7985 sc->stat_EtherStatsFragments = 7986 stats->stat_EtherStatsFragments; 7987 7988 sc->stat_EtherStatsJabbers = 7989 stats->stat_EtherStatsJabbers; 7990 7991 sc->stat_EtherStatsUndersizePkts = 7992 stats->stat_EtherStatsUndersizePkts; 7993 7994 sc->stat_EtherStatsOversizePkts = 7995 stats->stat_EtherStatsOversizePkts; 7996 7997 sc->stat_EtherStatsPktsRx64Octets = 7998 stats->stat_EtherStatsPktsRx64Octets; 7999 8000 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8001 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8002 8003 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8004 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8005 8006 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8007 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8008 8009 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8010 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8011 8012 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8013 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8014 8015 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8016 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8017 8018 sc->stat_EtherStatsPktsTx64Octets = 8019 stats->stat_EtherStatsPktsTx64Octets; 8020 8021 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8022 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8023 8024 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8025 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8026 8027 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8028 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8029 8030 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8031 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8032 8033 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8034 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8035 8036 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8037 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8038 8039 sc->stat_XonPauseFramesReceived = 8040 stats->stat_XonPauseFramesReceived; 8041 8042 sc->stat_XoffPauseFramesReceived = 8043 stats->stat_XoffPauseFramesReceived; 8044 8045 sc->stat_OutXonSent = 8046 stats->stat_OutXonSent; 8047 8048 sc->stat_OutXoffSent = 8049 stats->stat_OutXoffSent; 8050 8051 sc->stat_FlowControlDone = 8052 stats->stat_FlowControlDone; 8053 8054 sc->stat_MacControlFramesReceived = 8055 stats->stat_MacControlFramesReceived; 8056 8057 sc->stat_XoffStateEntered = 8058 stats->stat_XoffStateEntered; 8059 8060 sc->stat_IfInFramesL2FilterDiscards = 8061 stats->stat_IfInFramesL2FilterDiscards; 8062 8063 sc->stat_IfInRuleCheckerDiscards = 8064 stats->stat_IfInRuleCheckerDiscards; 8065 8066 sc->stat_IfInFTQDiscards = 8067 stats->stat_IfInFTQDiscards; 8068 8069 sc->stat_IfInMBUFDiscards = 8070 stats->stat_IfInMBUFDiscards; 8071 8072 sc->stat_IfInRuleCheckerP4Hit = 8073 stats->stat_IfInRuleCheckerP4Hit; 8074 8075 sc->stat_CatchupInRuleCheckerDiscards = 8076 stats->stat_CatchupInRuleCheckerDiscards; 8077 8078 sc->stat_CatchupInFTQDiscards = 8079 stats->stat_CatchupInFTQDiscards; 8080 8081 sc->stat_CatchupInMBUFDiscards = 8082 stats->stat_CatchupInMBUFDiscards; 8083 8084 sc->stat_CatchupInRuleCheckerP4Hit = 8085 stats->stat_CatchupInRuleCheckerP4Hit; 8086 8087 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8088 8089 /* 8090 * Update the interface statistics from the 8091 * hardware statistics. 8092 */ 8093 ifp->if_collisions = 8094 (u_long) sc->stat_EtherStatsCollisions; 8095 8096 /* ToDo: This method loses soft errors. */ 8097 ifp->if_ierrors = 8098 (u_long) sc->stat_EtherStatsUndersizePkts + 8099 (u_long) sc->stat_EtherStatsOversizePkts + 8100 (u_long) sc->stat_IfInMBUFDiscards + 8101 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8102 (u_long) sc->stat_Dot3StatsFCSErrors + 8103 (u_long) sc->stat_IfInRuleCheckerDiscards + 8104 (u_long) sc->stat_IfInFTQDiscards + 8105 (u_long) sc->com_no_buffers; 8106 8107 /* ToDo: This method loses soft errors. */ 8108 ifp->if_oerrors = 8109 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8110 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8111 (u_long) sc->stat_Dot3StatsLateCollisions; 8112 8113 /* ToDo: Add additional statistics? */ 8114 8115 DBEXIT(BCE_EXTREME_MISC); 8116 } 8117 8118 8119 /****************************************************************************/ 8120 /* Periodic function to notify the bootcode that the driver is still */ 8121 /* present. */ 8122 /* */ 8123 /* Returns: */ 8124 /* Nothing. */ 8125 /****************************************************************************/ 8126 static void 8127 bce_pulse(void *xsc) 8128 { 8129 struct bce_softc *sc = xsc; 8130 u32 msg; 8131 8132 DBENTER(BCE_EXTREME_MISC); 8133 8134 BCE_LOCK_ASSERT(sc); 8135 8136 /* Tell the firmware that the driver is still running. */ 8137 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8138 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8139 8140 /* Update the bootcode condition. */ 8141 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8142 8143 /* Report whether the bootcode still knows the driver is running. */ 8144 if (bce_verbose || bootverbose) { 8145 if (sc->bce_drv_cardiac_arrest == FALSE) { 8146 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8147 sc->bce_drv_cardiac_arrest = TRUE; 8148 BCE_PRINTF("%s(): Warning: bootcode " 8149 "thinks driver is absent! " 8150 "(bc_state = 0x%08X)\n", 8151 __FUNCTION__, sc->bc_state); 8152 } 8153 } else { 8154 /* 8155 * Not supported by all bootcode versions. 8156 * (v5.0.11+ and v5.2.1+) Older bootcode 8157 * will require the driver to reset the 8158 * controller to clear this condition. 8159 */ 8160 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8161 sc->bce_drv_cardiac_arrest = FALSE; 8162 BCE_PRINTF("%s(): Bootcode found the " 8163 "driver pulse! (bc_state = 0x%08X)\n", 8164 __FUNCTION__, sc->bc_state); 8165 } 8166 } 8167 } 8168 8169 8170 /* Schedule the next pulse. */ 8171 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8172 8173 DBEXIT(BCE_EXTREME_MISC); 8174 } 8175 8176 8177 /****************************************************************************/ 8178 /* Periodic function to perform maintenance tasks. */ 8179 /* */ 8180 /* Returns: */ 8181 /* Nothing. */ 8182 /****************************************************************************/ 8183 static void 8184 bce_tick(void *xsc) 8185 { 8186 struct bce_softc *sc = xsc; 8187 struct mii_data *mii; 8188 struct ifnet *ifp; 8189 8190 ifp = sc->bce_ifp; 8191 8192 DBENTER(BCE_EXTREME_MISC); 8193 8194 BCE_LOCK_ASSERT(sc); 8195 8196 /* Schedule the next tick. */ 8197 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8198 8199 /* Update the statistics from the hardware statistics block. */ 8200 bce_stats_update(sc); 8201 8202 /* 8203 * ToDo: This is a safety measure. Need to re-evaluate 8204 * high level processing logic and eliminate this code. 8205 */ 8206 /* Top off the receive and page chains. */ 8207 if (bce_hdr_split == TRUE) 8208 bce_fill_pg_chain(sc); 8209 bce_fill_rx_chain(sc); 8210 8211 /* Check that chip hasn't hung. */ 8212 bce_watchdog(sc); 8213 8214 /* If link is up already up then we're done. */ 8215 if (sc->bce_link_tick == FALSE && sc->bce_link_up == TRUE) 8216 goto bce_tick_exit; 8217 8218 /* Link is down. Check what the PHY's doing. */ 8219 mii = device_get_softc(sc->bce_miibus); 8220 mii_tick(mii); 8221 8222 sc->bce_link_tick = FALSE; 8223 /* Now that link is up, handle any outstanding TX traffic. */ 8224 if (sc->bce_link_up == TRUE && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8225 DBPRINT(sc, BCE_VERBOSE_MISC, 8226 "%s(): Found pending TX traffic.\n", __FUNCTION__); 8227 bce_start_locked(ifp); 8228 } 8229 8230 bce_tick_exit: 8231 DBEXIT(BCE_EXTREME_MISC); 8232 return; 8233 } 8234 8235 #ifdef BCE_DEBUG 8236 /****************************************************************************/ 8237 /* Allows the driver state to be dumped through the sysctl interface. */ 8238 /* */ 8239 /* Returns: */ 8240 /* 0 for success, positive value for failure. */ 8241 /****************************************************************************/ 8242 static int 8243 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8244 { 8245 int error; 8246 int result; 8247 struct bce_softc *sc; 8248 8249 result = -1; 8250 error = sysctl_handle_int(oidp, &result, 0, req); 8251 8252 if (error || !req->newptr) 8253 return (error); 8254 8255 if (result == 1) { 8256 sc = (struct bce_softc *)arg1; 8257 bce_dump_driver_state(sc); 8258 } 8259 8260 return error; 8261 } 8262 8263 8264 /****************************************************************************/ 8265 /* Allows the hardware state to be dumped through the sysctl interface. */ 8266 /* */ 8267 /* Returns: */ 8268 /* 0 for success, positive value for failure. */ 8269 /****************************************************************************/ 8270 static int 8271 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8272 { 8273 int error; 8274 int result; 8275 struct bce_softc *sc; 8276 8277 result = -1; 8278 error = sysctl_handle_int(oidp, &result, 0, req); 8279 8280 if (error || !req->newptr) 8281 return (error); 8282 8283 if (result == 1) { 8284 sc = (struct bce_softc *)arg1; 8285 bce_dump_hw_state(sc); 8286 } 8287 8288 return error; 8289 } 8290 8291 8292 /****************************************************************************/ 8293 /* Allows the status block to be dumped through the sysctl interface. */ 8294 /* */ 8295 /* Returns: */ 8296 /* 0 for success, positive value for failure. */ 8297 /****************************************************************************/ 8298 static int 8299 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8300 { 8301 int error; 8302 int result; 8303 struct bce_softc *sc; 8304 8305 result = -1; 8306 error = sysctl_handle_int(oidp, &result, 0, req); 8307 8308 if (error || !req->newptr) 8309 return (error); 8310 8311 if (result == 1) { 8312 sc = (struct bce_softc *)arg1; 8313 bce_dump_status_block(sc); 8314 } 8315 8316 return error; 8317 } 8318 8319 8320 /****************************************************************************/ 8321 /* Allows the stats block to be dumped through the sysctl interface. */ 8322 /* */ 8323 /* Returns: */ 8324 /* 0 for success, positive value for failure. */ 8325 /****************************************************************************/ 8326 static int 8327 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8328 { 8329 int error; 8330 int result; 8331 struct bce_softc *sc; 8332 8333 result = -1; 8334 error = sysctl_handle_int(oidp, &result, 0, req); 8335 8336 if (error || !req->newptr) 8337 return (error); 8338 8339 if (result == 1) { 8340 sc = (struct bce_softc *)arg1; 8341 bce_dump_stats_block(sc); 8342 } 8343 8344 return error; 8345 } 8346 8347 8348 /****************************************************************************/ 8349 /* Allows the stat counters to be cleared without unloading/reloading the */ 8350 /* driver. */ 8351 /* */ 8352 /* Returns: */ 8353 /* 0 for success, positive value for failure. */ 8354 /****************************************************************************/ 8355 static int 8356 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8357 { 8358 int error; 8359 int result; 8360 struct bce_softc *sc; 8361 8362 result = -1; 8363 error = sysctl_handle_int(oidp, &result, 0, req); 8364 8365 if (error || !req->newptr) 8366 return (error); 8367 8368 if (result == 1) { 8369 sc = (struct bce_softc *)arg1; 8370 struct statistics_block *stats; 8371 8372 stats = (struct statistics_block *) sc->stats_block; 8373 bzero(stats, sizeof(struct statistics_block)); 8374 8375 /* Clear the internal H/W statistics counters. */ 8376 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8377 8378 /* Reset the driver maintained statistics. */ 8379 sc->interrupts_rx = 8380 sc->interrupts_tx = 0; 8381 sc->tso_frames_requested = 8382 sc->tso_frames_completed = 8383 sc->tso_frames_failed = 0; 8384 sc->rx_empty_count = 8385 sc->tx_full_count = 0; 8386 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8387 sc->tx_hi_watermark = 0; 8388 sc->l2fhdr_error_count = 8389 sc->l2fhdr_error_sim_count = 0; 8390 sc->mbuf_alloc_failed_count = 8391 sc->mbuf_alloc_failed_sim_count = 0; 8392 sc->dma_map_addr_rx_failed_count = 8393 sc->dma_map_addr_tx_failed_count = 0; 8394 sc->mbuf_frag_count = 0; 8395 sc->csum_offload_tcp_udp = 8396 sc->csum_offload_ip = 0; 8397 sc->vlan_tagged_frames_rcvd = 8398 sc->vlan_tagged_frames_stripped = 0; 8399 sc->split_header_frames_rcvd = 8400 sc->split_header_tcp_frames_rcvd = 0; 8401 8402 /* Clear firmware maintained statistics. */ 8403 REG_WR_IND(sc, 0x120084, 0); 8404 } 8405 8406 return error; 8407 } 8408 8409 8410 /****************************************************************************/ 8411 /* Allows the shared memory contents to be dumped through the sysctl . */ 8412 /* interface. */ 8413 /* */ 8414 /* Returns: */ 8415 /* 0 for success, positive value for failure. */ 8416 /****************************************************************************/ 8417 static int 8418 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8419 { 8420 int error; 8421 int result; 8422 struct bce_softc *sc; 8423 8424 result = -1; 8425 error = sysctl_handle_int(oidp, &result, 0, req); 8426 8427 if (error || !req->newptr) 8428 return (error); 8429 8430 if (result == 1) { 8431 sc = (struct bce_softc *)arg1; 8432 bce_dump_shmem_state(sc); 8433 } 8434 8435 return error; 8436 } 8437 8438 8439 /****************************************************************************/ 8440 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8441 /* */ 8442 /* Returns: */ 8443 /* 0 for success, positive value for failure. */ 8444 /****************************************************************************/ 8445 static int 8446 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8447 { 8448 int error; 8449 int result; 8450 struct bce_softc *sc; 8451 8452 result = -1; 8453 error = sysctl_handle_int(oidp, &result, 0, req); 8454 8455 if (error || !req->newptr) 8456 return (error); 8457 8458 if (result == 1) { 8459 sc = (struct bce_softc *)arg1; 8460 bce_dump_bc_state(sc); 8461 } 8462 8463 return error; 8464 } 8465 8466 8467 /****************************************************************************/ 8468 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8469 /* */ 8470 /* Returns: */ 8471 /* 0 for success, positive value for failure. */ 8472 /****************************************************************************/ 8473 static int 8474 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8475 { 8476 int error; 8477 int result; 8478 struct bce_softc *sc; 8479 8480 result = -1; 8481 error = sysctl_handle_int(oidp, &result, 0, req); 8482 8483 if (error || !req->newptr) 8484 return (error); 8485 8486 if (result == 1) { 8487 sc = (struct bce_softc *)arg1; 8488 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8489 } 8490 8491 return error; 8492 } 8493 8494 8495 /****************************************************************************/ 8496 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8497 /* */ 8498 /* Returns: */ 8499 /* 0 for success, positive value for failure. */ 8500 /****************************************************************************/ 8501 static int 8502 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8503 { 8504 int error; 8505 int result; 8506 struct bce_softc *sc; 8507 8508 result = -1; 8509 error = sysctl_handle_int(oidp, &result, 0, req); 8510 8511 if (error || !req->newptr) 8512 return (error); 8513 8514 if (result == 1) { 8515 sc = (struct bce_softc *)arg1; 8516 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8517 } 8518 8519 return error; 8520 } 8521 8522 8523 /****************************************************************************/ 8524 /* Provides a sysctl interface to allow dumping the TX chain. */ 8525 /* */ 8526 /* Returns: */ 8527 /* 0 for success, positive value for failure. */ 8528 /****************************************************************************/ 8529 static int 8530 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8531 { 8532 int error; 8533 int result; 8534 struct bce_softc *sc; 8535 8536 result = -1; 8537 error = sysctl_handle_int(oidp, &result, 0, req); 8538 8539 if (error || !req->newptr) 8540 return (error); 8541 8542 if (result == 1) { 8543 sc = (struct bce_softc *)arg1; 8544 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8545 } 8546 8547 return error; 8548 } 8549 8550 8551 /****************************************************************************/ 8552 /* Provides a sysctl interface to allow dumping the page chain. */ 8553 /* */ 8554 /* Returns: */ 8555 /* 0 for success, positive value for failure. */ 8556 /****************************************************************************/ 8557 static int 8558 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8559 { 8560 int error; 8561 int result; 8562 struct bce_softc *sc; 8563 8564 result = -1; 8565 error = sysctl_handle_int(oidp, &result, 0, req); 8566 8567 if (error || !req->newptr) 8568 return (error); 8569 8570 if (result == 1) { 8571 sc = (struct bce_softc *)arg1; 8572 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8573 } 8574 8575 return error; 8576 } 8577 8578 /****************************************************************************/ 8579 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8580 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8581 /* */ 8582 /* Returns: */ 8583 /* 0 for success, positive value for failure. */ 8584 /****************************************************************************/ 8585 static int 8586 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8587 { 8588 struct bce_softc *sc = (struct bce_softc *)arg1; 8589 int error; 8590 u32 result; 8591 u32 val[1]; 8592 u8 *data = (u8 *) val; 8593 8594 result = -1; 8595 error = sysctl_handle_int(oidp, &result, 0, req); 8596 if (error || (req->newptr == NULL)) 8597 return (error); 8598 8599 error = bce_nvram_read(sc, result, data, 4); 8600 8601 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8602 8603 return (error); 8604 } 8605 8606 8607 /****************************************************************************/ 8608 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8609 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8610 /* */ 8611 /* Returns: */ 8612 /* 0 for success, positive value for failure. */ 8613 /****************************************************************************/ 8614 static int 8615 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8616 { 8617 struct bce_softc *sc = (struct bce_softc *)arg1; 8618 int error; 8619 u32 val, result; 8620 8621 result = -1; 8622 error = sysctl_handle_int(oidp, &result, 0, req); 8623 if (error || (req->newptr == NULL)) 8624 return (error); 8625 8626 /* Make sure the register is accessible. */ 8627 if (result < 0x8000) { 8628 val = REG_RD(sc, result); 8629 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8630 } else if (result < 0x0280000) { 8631 val = REG_RD_IND(sc, result); 8632 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8633 } 8634 8635 return (error); 8636 } 8637 8638 8639 /****************************************************************************/ 8640 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8641 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8642 /* */ 8643 /* Returns: */ 8644 /* 0 for success, positive value for failure. */ 8645 /****************************************************************************/ 8646 static int 8647 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8648 { 8649 struct bce_softc *sc; 8650 device_t dev; 8651 int error, result; 8652 u16 val; 8653 8654 result = -1; 8655 error = sysctl_handle_int(oidp, &result, 0, req); 8656 if (error || (req->newptr == NULL)) 8657 return (error); 8658 8659 /* Make sure the register is accessible. */ 8660 if (result < 0x20) { 8661 sc = (struct bce_softc *)arg1; 8662 dev = sc->bce_dev; 8663 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8664 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8665 } 8666 return (error); 8667 } 8668 8669 8670 /****************************************************************************/ 8671 /* Provides a sysctl interface for dumping the nvram contents. */ 8672 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8673 /* */ 8674 /* Returns: */ 8675 /* 0 for success, positive errno for failure. */ 8676 /****************************************************************************/ 8677 static int 8678 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8679 { 8680 struct bce_softc *sc = (struct bce_softc *)arg1; 8681 int error, i; 8682 8683 if (sc->nvram_buf == NULL) 8684 sc->nvram_buf = malloc(sc->bce_flash_size, 8685 M_TEMP, M_ZERO | M_WAITOK); 8686 8687 error = 0; 8688 if (req->oldlen == sc->bce_flash_size) { 8689 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8690 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8691 } 8692 8693 if (error == 0) 8694 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8695 8696 return error; 8697 } 8698 8699 #ifdef BCE_NVRAM_WRITE_SUPPORT 8700 /****************************************************************************/ 8701 /* Provides a sysctl interface for writing to nvram. */ 8702 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8703 /* */ 8704 /* Returns: */ 8705 /* 0 for success, positive errno for failure. */ 8706 /****************************************************************************/ 8707 static int 8708 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8709 { 8710 struct bce_softc *sc = (struct bce_softc *)arg1; 8711 int error; 8712 8713 if (sc->nvram_buf == NULL) 8714 sc->nvram_buf = malloc(sc->bce_flash_size, 8715 M_TEMP, M_ZERO | M_WAITOK); 8716 else 8717 bzero(sc->nvram_buf, sc->bce_flash_size); 8718 8719 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 8720 if (error == 0) 8721 return (error); 8722 8723 if (req->newlen == sc->bce_flash_size) 8724 error = bce_nvram_write(sc, 0, sc->nvram_buf, 8725 sc->bce_flash_size); 8726 8727 8728 return error; 8729 } 8730 #endif 8731 8732 8733 /****************************************************************************/ 8734 /* Provides a sysctl interface to allow reading a CID. */ 8735 /* */ 8736 /* Returns: */ 8737 /* 0 for success, positive value for failure. */ 8738 /****************************************************************************/ 8739 static int 8740 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8741 { 8742 struct bce_softc *sc; 8743 int error, result; 8744 8745 result = -1; 8746 error = sysctl_handle_int(oidp, &result, 0, req); 8747 if (error || (req->newptr == NULL)) 8748 return (error); 8749 8750 /* Make sure the register is accessible. */ 8751 if (result <= TX_CID) { 8752 sc = (struct bce_softc *)arg1; 8753 bce_dump_ctx(sc, result); 8754 } 8755 8756 return (error); 8757 } 8758 8759 8760 /****************************************************************************/ 8761 /* Provides a sysctl interface to forcing the driver to dump state and */ 8762 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8763 /* */ 8764 /* Returns: */ 8765 /* 0 for success, positive value for failure. */ 8766 /****************************************************************************/ 8767 static int 8768 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8769 { 8770 int error; 8771 int result; 8772 struct bce_softc *sc; 8773 8774 result = -1; 8775 error = sysctl_handle_int(oidp, &result, 0, req); 8776 8777 if (error || !req->newptr) 8778 return (error); 8779 8780 if (result == 1) { 8781 sc = (struct bce_softc *)arg1; 8782 bce_breakpoint(sc); 8783 } 8784 8785 return error; 8786 } 8787 #endif 8788 8789 /****************************************************************************/ 8790 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8791 /* */ 8792 /* Returns: */ 8793 /* 0 for success, positive value for failure. */ 8794 /****************************************************************************/ 8795 static void 8796 bce_add_sysctls(struct bce_softc *sc) 8797 { 8798 struct sysctl_ctx_list *ctx; 8799 struct sysctl_oid_list *children; 8800 8801 DBENTER(BCE_VERBOSE_MISC); 8802 8803 ctx = device_get_sysctl_ctx(sc->bce_dev); 8804 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8805 8806 #ifdef BCE_DEBUG 8807 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8808 "l2fhdr_error_sim_control", 8809 CTLFLAG_RW, &l2fhdr_error_sim_control, 8810 0, "Debug control to force l2fhdr errors"); 8811 8812 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8813 "l2fhdr_error_sim_count", 8814 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8815 0, "Number of simulated l2_fhdr errors"); 8816 #endif 8817 8818 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8819 "l2fhdr_error_count", 8820 CTLFLAG_RD, &sc->l2fhdr_error_count, 8821 0, "Number of l2_fhdr errors"); 8822 8823 #ifdef BCE_DEBUG 8824 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8825 "mbuf_alloc_failed_sim_control", 8826 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8827 0, "Debug control to force mbuf allocation failures"); 8828 8829 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8830 "mbuf_alloc_failed_sim_count", 8831 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8832 0, "Number of simulated mbuf cluster allocation failures"); 8833 #endif 8834 8835 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8836 "mbuf_alloc_failed_count", 8837 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8838 0, "Number of mbuf allocation failures"); 8839 8840 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8841 "mbuf_frag_count", 8842 CTLFLAG_RD, &sc->mbuf_frag_count, 8843 0, "Number of fragmented mbufs"); 8844 8845 #ifdef BCE_DEBUG 8846 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8847 "dma_map_addr_failed_sim_control", 8848 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8849 0, "Debug control to force DMA mapping failures"); 8850 8851 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 8852 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8853 "dma_map_addr_failed_sim_count", 8854 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 8855 0, "Number of simulated DMA mapping failures"); 8856 8857 #endif 8858 8859 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8860 "dma_map_addr_rx_failed_count", 8861 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 8862 0, "Number of RX DMA mapping failures"); 8863 8864 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8865 "dma_map_addr_tx_failed_count", 8866 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 8867 0, "Number of TX DMA mapping failures"); 8868 8869 #ifdef BCE_DEBUG 8870 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8871 "unexpected_attention_sim_control", 8872 CTLFLAG_RW, &unexpected_attention_sim_control, 8873 0, "Debug control to simulate unexpected attentions"); 8874 8875 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8876 "unexpected_attention_sim_count", 8877 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 8878 0, "Number of simulated unexpected attentions"); 8879 #endif 8880 8881 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8882 "unexpected_attention_count", 8883 CTLFLAG_RW, &sc->unexpected_attention_count, 8884 0, "Number of unexpected attentions"); 8885 8886 #ifdef BCE_DEBUG 8887 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8888 "debug_bootcode_running_failure", 8889 CTLFLAG_RW, &bootcode_running_failure_sim_control, 8890 0, "Debug control to force bootcode running failures"); 8891 8892 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8893 "rx_low_watermark", 8894 CTLFLAG_RD, &sc->rx_low_watermark, 8895 0, "Lowest level of free rx_bd's"); 8896 8897 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8898 "rx_empty_count", 8899 CTLFLAG_RD, &sc->rx_empty_count, 8900 "Number of times the RX chain was empty"); 8901 8902 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8903 "tx_hi_watermark", 8904 CTLFLAG_RD, &sc->tx_hi_watermark, 8905 0, "Highest level of used tx_bd's"); 8906 8907 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8908 "tx_full_count", 8909 CTLFLAG_RD, &sc->tx_full_count, 8910 "Number of times the TX chain was full"); 8911 8912 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8913 "tso_frames_requested", 8914 CTLFLAG_RD, &sc->tso_frames_requested, 8915 "Number of TSO frames requested"); 8916 8917 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8918 "tso_frames_completed", 8919 CTLFLAG_RD, &sc->tso_frames_completed, 8920 "Number of TSO frames completed"); 8921 8922 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8923 "tso_frames_failed", 8924 CTLFLAG_RD, &sc->tso_frames_failed, 8925 "Number of TSO frames failed"); 8926 8927 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8928 "csum_offload_ip", 8929 CTLFLAG_RD, &sc->csum_offload_ip, 8930 "Number of IP checksum offload frames"); 8931 8932 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8933 "csum_offload_tcp_udp", 8934 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 8935 "Number of TCP/UDP checksum offload frames"); 8936 8937 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8938 "vlan_tagged_frames_rcvd", 8939 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 8940 "Number of VLAN tagged frames received"); 8941 8942 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8943 "vlan_tagged_frames_stripped", 8944 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 8945 "Number of VLAN tagged frames stripped"); 8946 8947 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8948 "interrupts_rx", 8949 CTLFLAG_RD, &sc->interrupts_rx, 8950 "Number of RX interrupts"); 8951 8952 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8953 "interrupts_tx", 8954 CTLFLAG_RD, &sc->interrupts_tx, 8955 "Number of TX interrupts"); 8956 8957 if (bce_hdr_split == TRUE) { 8958 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8959 "split_header_frames_rcvd", 8960 CTLFLAG_RD, &sc->split_header_frames_rcvd, 8961 "Number of split header frames received"); 8962 8963 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8964 "split_header_tcp_frames_rcvd", 8965 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 8966 "Number of split header TCP frames received"); 8967 } 8968 8969 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8970 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 8971 (void *)sc, 0, 8972 bce_sysctl_nvram_dump, "S", ""); 8973 8974 #ifdef BCE_NVRAM_WRITE_SUPPORT 8975 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8976 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 8977 (void *)sc, 0, 8978 bce_sysctl_nvram_write, "S", ""); 8979 #endif 8980 #endif /* BCE_DEBUG */ 8981 8982 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8983 "stat_IfHcInOctets", 8984 CTLFLAG_RD, &sc->stat_IfHCInOctets, 8985 "Bytes received"); 8986 8987 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8988 "stat_IfHCInBadOctets", 8989 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 8990 "Bad bytes received"); 8991 8992 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8993 "stat_IfHCOutOctets", 8994 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 8995 "Bytes sent"); 8996 8997 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8998 "stat_IfHCOutBadOctets", 8999 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9000 "Bad bytes sent"); 9001 9002 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9003 "stat_IfHCInUcastPkts", 9004 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9005 "Unicast packets received"); 9006 9007 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9008 "stat_IfHCInMulticastPkts", 9009 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9010 "Multicast packets received"); 9011 9012 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9013 "stat_IfHCInBroadcastPkts", 9014 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9015 "Broadcast packets received"); 9016 9017 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9018 "stat_IfHCOutUcastPkts", 9019 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9020 "Unicast packets sent"); 9021 9022 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9023 "stat_IfHCOutMulticastPkts", 9024 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9025 "Multicast packets sent"); 9026 9027 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9028 "stat_IfHCOutBroadcastPkts", 9029 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9030 "Broadcast packets sent"); 9031 9032 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9033 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9034 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9035 0, "Internal MAC transmit errors"); 9036 9037 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9038 "stat_Dot3StatsCarrierSenseErrors", 9039 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9040 0, "Carrier sense errors"); 9041 9042 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9043 "stat_Dot3StatsFCSErrors", 9044 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9045 0, "Frame check sequence errors"); 9046 9047 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9048 "stat_Dot3StatsAlignmentErrors", 9049 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9050 0, "Alignment errors"); 9051 9052 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9053 "stat_Dot3StatsSingleCollisionFrames", 9054 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9055 0, "Single Collision Frames"); 9056 9057 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9058 "stat_Dot3StatsMultipleCollisionFrames", 9059 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9060 0, "Multiple Collision Frames"); 9061 9062 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9063 "stat_Dot3StatsDeferredTransmissions", 9064 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9065 0, "Deferred Transmissions"); 9066 9067 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9068 "stat_Dot3StatsExcessiveCollisions", 9069 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9070 0, "Excessive Collisions"); 9071 9072 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9073 "stat_Dot3StatsLateCollisions", 9074 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9075 0, "Late Collisions"); 9076 9077 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9078 "stat_EtherStatsCollisions", 9079 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9080 0, "Collisions"); 9081 9082 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9083 "stat_EtherStatsFragments", 9084 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9085 0, "Fragments"); 9086 9087 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9088 "stat_EtherStatsJabbers", 9089 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9090 0, "Jabbers"); 9091 9092 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9093 "stat_EtherStatsUndersizePkts", 9094 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9095 0, "Undersize packets"); 9096 9097 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9098 "stat_EtherStatsOversizePkts", 9099 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9100 0, "stat_EtherStatsOversizePkts"); 9101 9102 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9103 "stat_EtherStatsPktsRx64Octets", 9104 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9105 0, "Bytes received in 64 byte packets"); 9106 9107 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9108 "stat_EtherStatsPktsRx65Octetsto127Octets", 9109 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9110 0, "Bytes received in 65 to 127 byte packets"); 9111 9112 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9113 "stat_EtherStatsPktsRx128Octetsto255Octets", 9114 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9115 0, "Bytes received in 128 to 255 byte packets"); 9116 9117 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9118 "stat_EtherStatsPktsRx256Octetsto511Octets", 9119 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9120 0, "Bytes received in 256 to 511 byte packets"); 9121 9122 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9123 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9124 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9125 0, "Bytes received in 512 to 1023 byte packets"); 9126 9127 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9128 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9129 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9130 0, "Bytes received in 1024 t0 1522 byte packets"); 9131 9132 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9133 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9134 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9135 0, "Bytes received in 1523 to 9022 byte packets"); 9136 9137 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9138 "stat_EtherStatsPktsTx64Octets", 9139 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9140 0, "Bytes sent in 64 byte packets"); 9141 9142 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9143 "stat_EtherStatsPktsTx65Octetsto127Octets", 9144 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9145 0, "Bytes sent in 65 to 127 byte packets"); 9146 9147 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9148 "stat_EtherStatsPktsTx128Octetsto255Octets", 9149 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9150 0, "Bytes sent in 128 to 255 byte packets"); 9151 9152 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9153 "stat_EtherStatsPktsTx256Octetsto511Octets", 9154 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9155 0, "Bytes sent in 256 to 511 byte packets"); 9156 9157 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9158 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9159 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9160 0, "Bytes sent in 512 to 1023 byte packets"); 9161 9162 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9163 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9164 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9165 0, "Bytes sent in 1024 to 1522 byte packets"); 9166 9167 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9168 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9169 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9170 0, "Bytes sent in 1523 to 9022 byte packets"); 9171 9172 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9173 "stat_XonPauseFramesReceived", 9174 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9175 0, "XON pause frames receved"); 9176 9177 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9178 "stat_XoffPauseFramesReceived", 9179 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9180 0, "XOFF pause frames received"); 9181 9182 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9183 "stat_OutXonSent", 9184 CTLFLAG_RD, &sc->stat_OutXonSent, 9185 0, "XON pause frames sent"); 9186 9187 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9188 "stat_OutXoffSent", 9189 CTLFLAG_RD, &sc->stat_OutXoffSent, 9190 0, "XOFF pause frames sent"); 9191 9192 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9193 "stat_FlowControlDone", 9194 CTLFLAG_RD, &sc->stat_FlowControlDone, 9195 0, "Flow control done"); 9196 9197 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9198 "stat_MacControlFramesReceived", 9199 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9200 0, "MAC control frames received"); 9201 9202 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9203 "stat_XoffStateEntered", 9204 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9205 0, "XOFF state entered"); 9206 9207 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9208 "stat_IfInFramesL2FilterDiscards", 9209 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9210 0, "Received L2 packets discarded"); 9211 9212 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9213 "stat_IfInRuleCheckerDiscards", 9214 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9215 0, "Received packets discarded by rule"); 9216 9217 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9218 "stat_IfInFTQDiscards", 9219 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9220 0, "Received packet FTQ discards"); 9221 9222 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9223 "stat_IfInMBUFDiscards", 9224 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9225 0, "Received packets discarded due to lack " 9226 "of controller buffer memory"); 9227 9228 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9229 "stat_IfInRuleCheckerP4Hit", 9230 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9231 0, "Received packets rule checker hits"); 9232 9233 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9234 "stat_CatchupInRuleCheckerDiscards", 9235 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9236 0, "Received packets discarded in Catchup path"); 9237 9238 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9239 "stat_CatchupInFTQDiscards", 9240 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9241 0, "Received packets discarded in FTQ in Catchup path"); 9242 9243 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9244 "stat_CatchupInMBUFDiscards", 9245 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9246 0, "Received packets discarded in controller " 9247 "buffer memory in Catchup path"); 9248 9249 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9250 "stat_CatchupInRuleCheckerP4Hit", 9251 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9252 0, "Received packets rule checker hits in Catchup path"); 9253 9254 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9255 "com_no_buffers", 9256 CTLFLAG_RD, &sc->com_no_buffers, 9257 0, "Valid packets received but no RX buffers available"); 9258 9259 #ifdef BCE_DEBUG 9260 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9261 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9262 (void *)sc, 0, 9263 bce_sysctl_driver_state, "I", "Drive state information"); 9264 9265 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9266 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9267 (void *)sc, 0, 9268 bce_sysctl_hw_state, "I", "Hardware state information"); 9269 9270 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9271 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9272 (void *)sc, 0, 9273 bce_sysctl_status_block, "I", "Dump status block"); 9274 9275 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9276 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9277 (void *)sc, 0, 9278 bce_sysctl_stats_block, "I", "Dump statistics block"); 9279 9280 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9281 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9282 (void *)sc, 0, 9283 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9284 9285 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9286 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9287 (void *)sc, 0, 9288 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9289 9290 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9291 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9292 (void *)sc, 0, 9293 bce_sysctl_bc_state, "I", "Bootcode state information"); 9294 9295 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9296 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9297 (void *)sc, 0, 9298 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9299 9300 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9301 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9302 (void *)sc, 0, 9303 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9304 9305 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9306 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9307 (void *)sc, 0, 9308 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9309 9310 if (bce_hdr_split == TRUE) { 9311 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9312 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9313 (void *)sc, 0, 9314 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9315 } 9316 9317 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9318 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9319 (void *)sc, 0, 9320 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9321 9322 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9323 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9324 (void *)sc, 0, 9325 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9326 9327 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9328 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9329 (void *)sc, 0, 9330 bce_sysctl_reg_read, "I", "Register read"); 9331 9332 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9333 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9334 (void *)sc, 0, 9335 bce_sysctl_nvram_read, "I", "NVRAM read"); 9336 9337 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9338 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9339 (void *)sc, 0, 9340 bce_sysctl_phy_read, "I", "PHY register read"); 9341 9342 #endif 9343 9344 DBEXIT(BCE_VERBOSE_MISC); 9345 } 9346 9347 9348 /****************************************************************************/ 9349 /* BCE Debug Routines */ 9350 /****************************************************************************/ 9351 #ifdef BCE_DEBUG 9352 9353 /****************************************************************************/ 9354 /* Freezes the controller to allow for a cohesive state dump. */ 9355 /* */ 9356 /* Returns: */ 9357 /* Nothing. */ 9358 /****************************************************************************/ 9359 static __attribute__ ((noinline)) void 9360 bce_freeze_controller(struct bce_softc *sc) 9361 { 9362 u32 val; 9363 val = REG_RD(sc, BCE_MISC_COMMAND); 9364 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9365 REG_WR(sc, BCE_MISC_COMMAND, val); 9366 } 9367 9368 9369 /****************************************************************************/ 9370 /* Unfreezes the controller after a freeze operation. This may not always */ 9371 /* work and the controller will require a reset! */ 9372 /* */ 9373 /* Returns: */ 9374 /* Nothing. */ 9375 /****************************************************************************/ 9376 static __attribute__ ((noinline)) void 9377 bce_unfreeze_controller(struct bce_softc *sc) 9378 { 9379 u32 val; 9380 val = REG_RD(sc, BCE_MISC_COMMAND); 9381 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9382 REG_WR(sc, BCE_MISC_COMMAND, val); 9383 } 9384 9385 9386 /****************************************************************************/ 9387 /* Prints out Ethernet frame information from an mbuf. */ 9388 /* */ 9389 /* Partially decode an Ethernet frame to look at some important headers. */ 9390 /* */ 9391 /* Returns: */ 9392 /* Nothing. */ 9393 /****************************************************************************/ 9394 static __attribute__ ((noinline)) void 9395 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9396 { 9397 struct ether_vlan_header *eh; 9398 u16 etype; 9399 int ehlen; 9400 struct ip *ip; 9401 struct tcphdr *th; 9402 struct udphdr *uh; 9403 struct arphdr *ah; 9404 9405 BCE_PRINTF( 9406 "-----------------------------" 9407 " Frame Decode " 9408 "-----------------------------\n"); 9409 9410 eh = mtod(m, struct ether_vlan_header *); 9411 9412 /* Handle VLAN encapsulation if present. */ 9413 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9414 etype = ntohs(eh->evl_proto); 9415 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9416 } else { 9417 etype = ntohs(eh->evl_encap_proto); 9418 ehlen = ETHER_HDR_LEN; 9419 } 9420 9421 /* ToDo: Add VLAN output. */ 9422 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9423 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9424 9425 switch (etype) { 9426 case ETHERTYPE_IP: 9427 ip = (struct ip *)(m->m_data + ehlen); 9428 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9429 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9430 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9431 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9432 9433 switch (ip->ip_p) { 9434 case IPPROTO_TCP: 9435 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9436 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9437 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9438 ntohs(th->th_dport), ntohs(th->th_sport), 9439 (th->th_off << 2), th->th_flags, 9440 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9441 "\02SYN\01FIN", ntohs(th->th_sum)); 9442 break; 9443 case IPPROTO_UDP: 9444 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9445 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9446 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9447 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9448 ntohs(uh->uh_sum)); 9449 break; 9450 case IPPROTO_ICMP: 9451 BCE_PRINTF("icmp:\n"); 9452 break; 9453 default: 9454 BCE_PRINTF("----: Other IP protocol.\n"); 9455 } 9456 break; 9457 case ETHERTYPE_IPV6: 9458 BCE_PRINTF("ipv6: No decode supported.\n"); 9459 break; 9460 case ETHERTYPE_ARP: 9461 BCE_PRINTF("-arp: "); 9462 ah = (struct arphdr *) (m->m_data + ehlen); 9463 switch (ntohs(ah->ar_op)) { 9464 case ARPOP_REVREQUEST: 9465 printf("reverse ARP request\n"); 9466 break; 9467 case ARPOP_REVREPLY: 9468 printf("reverse ARP reply\n"); 9469 break; 9470 case ARPOP_REQUEST: 9471 printf("ARP request\n"); 9472 break; 9473 case ARPOP_REPLY: 9474 printf("ARP reply\n"); 9475 break; 9476 default: 9477 printf("other ARP operation\n"); 9478 } 9479 break; 9480 default: 9481 BCE_PRINTF("----: Other protocol.\n"); 9482 } 9483 9484 BCE_PRINTF( 9485 "-----------------------------" 9486 "--------------" 9487 "-----------------------------\n"); 9488 } 9489 9490 9491 /****************************************************************************/ 9492 /* Prints out information about an mbuf. */ 9493 /* */ 9494 /* Returns: */ 9495 /* Nothing. */ 9496 /****************************************************************************/ 9497 static __attribute__ ((noinline)) void 9498 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9499 { 9500 struct mbuf *mp = m; 9501 9502 if (m == NULL) { 9503 BCE_PRINTF("mbuf: null pointer\n"); 9504 return; 9505 } 9506 9507 while (mp) { 9508 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9509 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9510 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9511 9512 if (mp->m_flags & M_PKTHDR) { 9513 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9514 "csum_flags = %b\n", mp->m_pkthdr.len, 9515 mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" 9516 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9517 "\22M_PROMISC\23M_NOFREE", 9518 mp->m_pkthdr.csum_flags, 9519 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 9520 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9521 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9522 "\14CSUM_PSEUDO_HDR"); 9523 } 9524 9525 if (mp->m_flags & M_EXT) { 9526 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9527 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9528 switch (mp->m_ext.ext_type) { 9529 case EXT_CLUSTER: 9530 printf("EXT_CLUSTER\n"); break; 9531 case EXT_SFBUF: 9532 printf("EXT_SFBUF\n"); break; 9533 case EXT_JUMBO9: 9534 printf("EXT_JUMBO9\n"); break; 9535 case EXT_JUMBO16: 9536 printf("EXT_JUMBO16\n"); break; 9537 case EXT_PACKET: 9538 printf("EXT_PACKET\n"); break; 9539 case EXT_MBUF: 9540 printf("EXT_MBUF\n"); break; 9541 case EXT_NET_DRV: 9542 printf("EXT_NET_DRV\n"); break; 9543 case EXT_MOD_TYPE: 9544 printf("EXT_MDD_TYPE\n"); break; 9545 case EXT_DISPOSABLE: 9546 printf("EXT_DISPOSABLE\n"); break; 9547 case EXT_EXTREF: 9548 printf("EXT_EXTREF\n"); break; 9549 default: 9550 printf("UNKNOWN\n"); 9551 } 9552 } 9553 9554 mp = mp->m_next; 9555 } 9556 } 9557 9558 9559 /****************************************************************************/ 9560 /* Prints out the mbufs in the TX mbuf chain. */ 9561 /* */ 9562 /* Returns: */ 9563 /* Nothing. */ 9564 /****************************************************************************/ 9565 static __attribute__ ((noinline)) void 9566 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9567 { 9568 struct mbuf *m; 9569 9570 BCE_PRINTF( 9571 "----------------------------" 9572 " tx mbuf data " 9573 "----------------------------\n"); 9574 9575 for (int i = 0; i < count; i++) { 9576 m = sc->tx_mbuf_ptr[chain_prod]; 9577 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9578 bce_dump_mbuf(sc, m); 9579 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9580 } 9581 9582 BCE_PRINTF( 9583 "----------------------------" 9584 "----------------" 9585 "----------------------------\n"); 9586 } 9587 9588 9589 /****************************************************************************/ 9590 /* Prints out the mbufs in the RX mbuf chain. */ 9591 /* */ 9592 /* Returns: */ 9593 /* Nothing. */ 9594 /****************************************************************************/ 9595 static __attribute__ ((noinline)) void 9596 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9597 { 9598 struct mbuf *m; 9599 9600 BCE_PRINTF( 9601 "----------------------------" 9602 " rx mbuf data " 9603 "----------------------------\n"); 9604 9605 for (int i = 0; i < count; i++) { 9606 m = sc->rx_mbuf_ptr[chain_prod]; 9607 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9608 bce_dump_mbuf(sc, m); 9609 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9610 } 9611 9612 9613 BCE_PRINTF( 9614 "----------------------------" 9615 "----------------" 9616 "----------------------------\n"); 9617 } 9618 9619 9620 /****************************************************************************/ 9621 /* Prints out the mbufs in the mbuf page chain. */ 9622 /* */ 9623 /* Returns: */ 9624 /* Nothing. */ 9625 /****************************************************************************/ 9626 static __attribute__ ((noinline)) void 9627 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9628 { 9629 struct mbuf *m; 9630 9631 BCE_PRINTF( 9632 "----------------------------" 9633 " pg mbuf data " 9634 "----------------------------\n"); 9635 9636 for (int i = 0; i < count; i++) { 9637 m = sc->pg_mbuf_ptr[chain_prod]; 9638 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9639 bce_dump_mbuf(sc, m); 9640 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9641 } 9642 9643 9644 BCE_PRINTF( 9645 "----------------------------" 9646 "----------------" 9647 "----------------------------\n"); 9648 } 9649 9650 9651 /****************************************************************************/ 9652 /* Prints out a tx_bd structure. */ 9653 /* */ 9654 /* Returns: */ 9655 /* Nothing. */ 9656 /****************************************************************************/ 9657 static __attribute__ ((noinline)) void 9658 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9659 { 9660 int i = 0; 9661 9662 if (idx > MAX_TX_BD_ALLOC) 9663 /* Index out of range. */ 9664 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9665 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9666 /* TX Chain page pointer. */ 9667 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9668 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9669 txbd->tx_bd_haddr_lo); 9670 else { 9671 /* Normal tx_bd entry. */ 9672 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9673 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9674 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9675 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9676 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9677 9678 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9679 if (i>0) 9680 printf("|"); 9681 printf("CONN_FAULT"); 9682 i++; 9683 } 9684 9685 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9686 if (i>0) 9687 printf("|"); 9688 printf("TCP_UDP_CKSUM"); 9689 i++; 9690 } 9691 9692 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9693 if (i>0) 9694 printf("|"); 9695 printf("IP_CKSUM"); 9696 i++; 9697 } 9698 9699 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9700 if (i>0) 9701 printf("|"); 9702 printf("VLAN"); 9703 i++; 9704 } 9705 9706 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9707 if (i>0) 9708 printf("|"); 9709 printf("COAL_NOW"); 9710 i++; 9711 } 9712 9713 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9714 if (i>0) 9715 printf("|"); 9716 printf("DONT_GEN_CRC"); 9717 i++; 9718 } 9719 9720 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9721 if (i>0) 9722 printf("|"); 9723 printf("START"); 9724 i++; 9725 } 9726 9727 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9728 if (i>0) 9729 printf("|"); 9730 printf("END"); 9731 i++; 9732 } 9733 9734 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9735 if (i>0) 9736 printf("|"); 9737 printf("LSO"); 9738 i++; 9739 } 9740 9741 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9742 if (i>0) 9743 printf("|"); 9744 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9745 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9746 } 9747 9748 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9749 if (i>0) 9750 printf("|"); 9751 printf("SW_FLAGS"); 9752 i++; 9753 } 9754 9755 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9756 if (i>0) 9757 printf("|"); 9758 printf("SNAP)"); 9759 } else { 9760 printf(")\n"); 9761 } 9762 } 9763 } 9764 9765 9766 /****************************************************************************/ 9767 /* Prints out a rx_bd structure. */ 9768 /* */ 9769 /* Returns: */ 9770 /* Nothing. */ 9771 /****************************************************************************/ 9772 static __attribute__ ((noinline)) void 9773 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9774 { 9775 if (idx > MAX_RX_BD_ALLOC) 9776 /* Index out of range. */ 9777 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9778 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9779 /* RX Chain page pointer. */ 9780 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9781 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9782 rxbd->rx_bd_haddr_lo); 9783 else 9784 /* Normal rx_bd entry. */ 9785 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9786 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9787 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9788 rxbd->rx_bd_flags); 9789 } 9790 9791 9792 /****************************************************************************/ 9793 /* Prints out a rx_bd structure in the page chain. */ 9794 /* */ 9795 /* Returns: */ 9796 /* Nothing. */ 9797 /****************************************************************************/ 9798 static __attribute__ ((noinline)) void 9799 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9800 { 9801 if (idx > MAX_PG_BD_ALLOC) 9802 /* Index out of range. */ 9803 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9804 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9805 /* Page Chain page pointer. */ 9806 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9807 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9808 else 9809 /* Normal rx_bd entry. */ 9810 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9811 "flags = 0x%08X\n", idx, 9812 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9813 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9814 } 9815 9816 9817 /****************************************************************************/ 9818 /* Prints out a l2_fhdr structure. */ 9819 /* */ 9820 /* Returns: */ 9821 /* Nothing. */ 9822 /****************************************************************************/ 9823 static __attribute__ ((noinline)) void 9824 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9825 { 9826 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9827 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9828 "tcp_udp_xsum = 0x%04X\n", idx, 9829 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9830 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9831 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9832 } 9833 9834 9835 /****************************************************************************/ 9836 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9837 /* */ 9838 /* Returns: */ 9839 /* Nothing. */ 9840 /****************************************************************************/ 9841 static __attribute__ ((noinline)) void 9842 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9843 { 9844 if (cid > TX_CID) { 9845 BCE_PRINTF(" Unknown CID\n"); 9846 return; 9847 } 9848 9849 BCE_PRINTF( 9850 "----------------------------" 9851 " CTX Data " 9852 "----------------------------\n"); 9853 9854 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9855 9856 if (cid == RX_CID) { 9857 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9858 "producer index\n", 9859 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9860 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 9861 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9862 BCE_L2CTX_RX_HOST_BSEQ)); 9863 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9864 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9865 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9866 "descriptor address\n", 9867 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9868 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9869 "descriptor address\n", 9870 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 9871 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 9872 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9873 BCE_L2CTX_RX_NX_BDIDX)); 9874 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 9875 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9876 BCE_L2CTX_RX_HOST_PG_BDIDX)); 9877 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 9878 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 9879 BCE_L2CTX_RX_PG_BUF_SIZE)); 9880 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 9881 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9882 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 9883 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 9884 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9885 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 9886 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 9887 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9888 BCE_L2CTX_RX_NX_PG_BDIDX)); 9889 } else if (cid == TX_CID) { 9890 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 9891 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 9892 CTX_RD(sc, GET_CID_ADDR(cid), 9893 BCE_L2CTX_TX_TYPE_XI)); 9894 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 9895 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 9896 BCE_L2CTX_TX_CMD_TYPE_XI)); 9897 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 9898 "h/w buffer descriptor address\n", 9899 CTX_RD(sc, GET_CID_ADDR(cid), 9900 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 9901 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 9902 "h/w buffer descriptor address\n", 9903 CTX_RD(sc, GET_CID_ADDR(cid), 9904 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 9905 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 9906 "host producer index\n", 9907 CTX_RD(sc, GET_CID_ADDR(cid), 9908 BCE_L2CTX_TX_HOST_BIDX_XI)); 9909 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 9910 "host byte sequence\n", 9911 CTX_RD(sc, GET_CID_ADDR(cid), 9912 BCE_L2CTX_TX_HOST_BSEQ_XI)); 9913 } else { 9914 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 9915 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 9916 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 9917 CTX_RD(sc, GET_CID_ADDR(cid), 9918 BCE_L2CTX_TX_CMD_TYPE)); 9919 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 9920 "h/w buffer descriptor address\n", 9921 CTX_RD(sc, GET_CID_ADDR(cid), 9922 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 9923 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 9924 "h/w buffer descriptor address\n", 9925 CTX_RD(sc, GET_CID_ADDR(cid), 9926 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 9927 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 9928 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9929 BCE_L2CTX_TX_HOST_BIDX)); 9930 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 9931 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9932 BCE_L2CTX_TX_HOST_BSEQ)); 9933 } 9934 } 9935 9936 BCE_PRINTF( 9937 "----------------------------" 9938 " Raw CTX " 9939 "----------------------------\n"); 9940 9941 for (int i = 0x0; i < 0x300; i += 0x10) { 9942 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 9943 CTX_RD(sc, GET_CID_ADDR(cid), i), 9944 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 9945 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 9946 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 9947 } 9948 9949 9950 BCE_PRINTF( 9951 "----------------------------" 9952 "----------------" 9953 "----------------------------\n"); 9954 } 9955 9956 9957 /****************************************************************************/ 9958 /* Prints out the FTQ data. */ 9959 /* */ 9960 /* Returns: */ 9961 /* Nothing. */ 9962 /****************************************************************************/ 9963 static __attribute__ ((noinline)) void 9964 bce_dump_ftqs(struct bce_softc *sc) 9965 { 9966 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 9967 9968 BCE_PRINTF( 9969 "----------------------------" 9970 " FTQ Data " 9971 "----------------------------\n"); 9972 9973 BCE_PRINTF(" FTQ Command Control Depth_Now " 9974 "Max_Depth Valid_Cnt \n"); 9975 BCE_PRINTF(" ------- ---------- ---------- ---------- " 9976 "---------- ----------\n"); 9977 9978 /* Setup the generic statistic counters for the FTQ valid count. */ 9979 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 9980 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 9981 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 9982 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 9983 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9984 9985 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 9986 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 9987 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 9988 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 9989 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 9990 9991 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 9992 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 9993 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 9994 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 9995 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 9996 9997 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 9998 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 9999 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10000 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10001 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10002 10003 /* Input queue to the Receive Lookup state machine */ 10004 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10005 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10006 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10007 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10008 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10009 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10010 cmd, ctl, cur_depth, max_depth, valid_cnt); 10011 10012 /* Input queue to the Receive Processor */ 10013 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10014 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10015 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10016 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10017 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10018 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10019 cmd, ctl, cur_depth, max_depth, valid_cnt); 10020 10021 /* Input queue to the Recevie Processor */ 10022 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10023 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10024 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10025 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10026 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10027 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10028 cmd, ctl, cur_depth, max_depth, valid_cnt); 10029 10030 /* Input queue to the Receive Virtual to Physical state machine */ 10031 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10032 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10033 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10034 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10035 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10036 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10037 cmd, ctl, cur_depth, max_depth, valid_cnt); 10038 10039 /* Input queue to the Recevie Virtual to Physical state machine */ 10040 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10041 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10042 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10043 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10044 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10045 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10046 cmd, ctl, cur_depth, max_depth, valid_cnt); 10047 10048 /* Input queue to the Receive Virtual to Physical state machine */ 10049 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10050 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10051 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10052 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10053 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10054 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10055 cmd, ctl, cur_depth, max_depth, valid_cnt); 10056 10057 /* Input queue to the Receive DMA state machine */ 10058 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10059 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10060 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10061 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10062 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10063 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10064 cmd, ctl, cur_depth, max_depth, valid_cnt); 10065 10066 /* Input queue to the Transmit Scheduler state machine */ 10067 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10068 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10069 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10070 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10071 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10072 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10073 cmd, ctl, cur_depth, max_depth, valid_cnt); 10074 10075 /* Input queue to the Transmit Buffer Descriptor state machine */ 10076 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10077 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10078 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10079 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10080 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10081 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10082 cmd, ctl, cur_depth, max_depth, valid_cnt); 10083 10084 /* Input queue to the Transmit Processor */ 10085 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10086 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10087 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10088 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10089 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10090 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10091 cmd, ctl, cur_depth, max_depth, valid_cnt); 10092 10093 /* Input queue to the Transmit DMA state machine */ 10094 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10095 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10096 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10097 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10098 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10099 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10100 cmd, ctl, cur_depth, max_depth, valid_cnt); 10101 10102 /* Input queue to the Transmit Patch-Up Processor */ 10103 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10104 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10105 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10106 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10107 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10108 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10109 cmd, ctl, cur_depth, max_depth, valid_cnt); 10110 10111 /* Input queue to the Transmit Assembler state machine */ 10112 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10113 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10114 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10115 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10116 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10117 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10118 cmd, ctl, cur_depth, max_depth, valid_cnt); 10119 10120 /* Input queue to the Completion Processor */ 10121 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10122 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10123 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10124 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10125 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10126 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10127 cmd, ctl, cur_depth, max_depth, valid_cnt); 10128 10129 /* Input queue to the Completion Processor */ 10130 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10131 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10132 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10133 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10134 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10135 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10136 cmd, ctl, cur_depth, max_depth, valid_cnt); 10137 10138 /* Input queue to the Completion Processor */ 10139 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10140 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10141 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10142 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10143 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10144 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10145 cmd, ctl, cur_depth, max_depth, valid_cnt); 10146 10147 /* Setup the generic statistic counters for the FTQ valid count. */ 10148 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10149 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10150 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10151 10152 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10153 val = val | 10154 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10155 24); 10156 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10157 10158 /* Input queue to the Management Control Processor */ 10159 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10160 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10161 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10162 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10163 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10164 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10165 cmd, ctl, cur_depth, max_depth, valid_cnt); 10166 10167 /* Input queue to the Command Processor */ 10168 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10169 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10170 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10171 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10172 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10173 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10174 cmd, ctl, cur_depth, max_depth, valid_cnt); 10175 10176 /* Input queue to the Completion Scheduler state machine */ 10177 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10178 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10179 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10180 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10181 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10182 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10183 cmd, ctl, cur_depth, max_depth, valid_cnt); 10184 10185 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10186 /* Input queue to the RV2P Command Scheduler */ 10187 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10188 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10189 cur_depth = (ctl & 0xFFC00000) >> 22; 10190 max_depth = (ctl & 0x003FF000) >> 12; 10191 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10192 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10193 cmd, ctl, cur_depth, max_depth, valid_cnt); 10194 } 10195 10196 BCE_PRINTF( 10197 "----------------------------" 10198 "----------------" 10199 "----------------------------\n"); 10200 } 10201 10202 10203 /****************************************************************************/ 10204 /* Prints out the TX chain. */ 10205 /* */ 10206 /* Returns: */ 10207 /* Nothing. */ 10208 /****************************************************************************/ 10209 static __attribute__ ((noinline)) void 10210 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10211 { 10212 struct tx_bd *txbd; 10213 10214 /* First some info about the tx_bd chain structure. */ 10215 BCE_PRINTF( 10216 "----------------------------" 10217 " tx_bd chain " 10218 "----------------------------\n"); 10219 10220 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10221 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10222 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10223 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10224 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10225 10226 BCE_PRINTF( 10227 "----------------------------" 10228 " tx_bd data " 10229 "----------------------------\n"); 10230 10231 /* Now print out a decoded list of TX buffer descriptors. */ 10232 for (int i = 0; i < count; i++) { 10233 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10234 bce_dump_txbd(sc, tx_prod, txbd); 10235 tx_prod++; 10236 } 10237 10238 BCE_PRINTF( 10239 "----------------------------" 10240 "----------------" 10241 "----------------------------\n"); 10242 } 10243 10244 10245 /****************************************************************************/ 10246 /* Prints out the RX chain. */ 10247 /* */ 10248 /* Returns: */ 10249 /* Nothing. */ 10250 /****************************************************************************/ 10251 static __attribute__ ((noinline)) void 10252 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10253 { 10254 struct rx_bd *rxbd; 10255 10256 /* First some info about the rx_bd chain structure. */ 10257 BCE_PRINTF( 10258 "----------------------------" 10259 " rx_bd chain " 10260 "----------------------------\n"); 10261 10262 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10263 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10264 10265 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10266 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10267 10268 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10269 10270 BCE_PRINTF( 10271 "----------------------------" 10272 " rx_bd data " 10273 "----------------------------\n"); 10274 10275 /* Now print out the rx_bd's themselves. */ 10276 for (int i = 0; i < count; i++) { 10277 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10278 bce_dump_rxbd(sc, rx_prod, rxbd); 10279 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10280 } 10281 10282 BCE_PRINTF( 10283 "----------------------------" 10284 "----------------" 10285 "----------------------------\n"); 10286 } 10287 10288 10289 /****************************************************************************/ 10290 /* Prints out the page chain. */ 10291 /* */ 10292 /* Returns: */ 10293 /* Nothing. */ 10294 /****************************************************************************/ 10295 static __attribute__ ((noinline)) void 10296 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10297 { 10298 struct rx_bd *pgbd; 10299 10300 /* First some info about the page chain structure. */ 10301 BCE_PRINTF( 10302 "----------------------------" 10303 " page chain " 10304 "----------------------------\n"); 10305 10306 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10307 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10308 10309 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10310 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10311 10312 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10313 10314 BCE_PRINTF( 10315 "----------------------------" 10316 " page data " 10317 "----------------------------\n"); 10318 10319 /* Now print out the rx_bd's themselves. */ 10320 for (int i = 0; i < count; i++) { 10321 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10322 bce_dump_pgbd(sc, pg_prod, pgbd); 10323 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10324 } 10325 10326 BCE_PRINTF( 10327 "----------------------------" 10328 "----------------" 10329 "----------------------------\n"); 10330 } 10331 10332 10333 #define BCE_PRINT_RX_CONS(arg) \ 10334 if (sblk->status_rx_quick_consumer_index##arg) \ 10335 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10336 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10337 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10338 arg); 10339 10340 10341 #define BCE_PRINT_TX_CONS(arg) \ 10342 if (sblk->status_tx_quick_consumer_index##arg) \ 10343 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10344 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10345 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10346 arg); 10347 10348 /****************************************************************************/ 10349 /* Prints out the status block from host memory. */ 10350 /* */ 10351 /* Returns: */ 10352 /* Nothing. */ 10353 /****************************************************************************/ 10354 static __attribute__ ((noinline)) void 10355 bce_dump_status_block(struct bce_softc *sc) 10356 { 10357 struct status_block *sblk; 10358 10359 sblk = sc->status_block; 10360 10361 BCE_PRINTF( 10362 "----------------------------" 10363 " Status Block " 10364 "----------------------------\n"); 10365 10366 /* Theses indices are used for normal L2 drivers. */ 10367 BCE_PRINTF(" 0x%08X - attn_bits\n", 10368 sblk->status_attn_bits); 10369 10370 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10371 sblk->status_attn_bits_ack); 10372 10373 BCE_PRINT_RX_CONS(0); 10374 BCE_PRINT_TX_CONS(0) 10375 10376 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10377 10378 /* Theses indices are not used for normal L2 drivers. */ 10379 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10380 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10381 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10382 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10383 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10384 10385 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10386 10387 if (sblk->status_completion_producer_index || 10388 sblk->status_cmd_consumer_index) 10389 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10390 sblk->status_completion_producer_index, 10391 sblk->status_cmd_consumer_index); 10392 10393 BCE_PRINTF( 10394 "----------------------------" 10395 "----------------" 10396 "----------------------------\n"); 10397 } 10398 10399 10400 #define BCE_PRINT_64BIT_STAT(arg) \ 10401 if (sblk->arg##_lo || sblk->arg##_hi) \ 10402 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10403 sblk->arg##_lo, #arg); 10404 10405 #define BCE_PRINT_32BIT_STAT(arg) \ 10406 if (sblk->arg) \ 10407 BCE_PRINTF(" 0x%08X : %s\n", \ 10408 sblk->arg, #arg); 10409 10410 /****************************************************************************/ 10411 /* Prints out the statistics block from host memory. */ 10412 /* */ 10413 /* Returns: */ 10414 /* Nothing. */ 10415 /****************************************************************************/ 10416 static __attribute__ ((noinline)) void 10417 bce_dump_stats_block(struct bce_softc *sc) 10418 { 10419 struct statistics_block *sblk; 10420 10421 sblk = sc->stats_block; 10422 10423 BCE_PRINTF( 10424 "---------------" 10425 " Stats Block (All Stats Not Shown Are 0) " 10426 "---------------\n"); 10427 10428 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10429 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10430 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10431 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10432 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10433 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10434 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10435 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10436 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10437 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10438 BCE_PRINT_32BIT_STAT( 10439 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10440 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10441 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10442 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10443 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10444 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10445 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10446 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10447 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10448 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10449 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10450 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10451 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10452 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10453 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10454 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10455 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10456 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10457 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10458 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10459 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10460 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10461 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10462 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10463 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10464 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10465 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10466 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10467 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10468 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10469 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10470 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10471 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10472 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10473 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10474 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10475 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10476 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10477 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10478 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10479 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10480 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10481 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10482 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10483 10484 BCE_PRINTF( 10485 "----------------------------" 10486 "----------------" 10487 "----------------------------\n"); 10488 } 10489 10490 10491 /****************************************************************************/ 10492 /* Prints out a summary of the driver state. */ 10493 /* */ 10494 /* Returns: */ 10495 /* Nothing. */ 10496 /****************************************************************************/ 10497 static __attribute__ ((noinline)) void 10498 bce_dump_driver_state(struct bce_softc *sc) 10499 { 10500 u32 val_hi, val_lo; 10501 10502 BCE_PRINTF( 10503 "-----------------------------" 10504 " Driver State " 10505 "-----------------------------\n"); 10506 10507 val_hi = BCE_ADDR_HI(sc); 10508 val_lo = BCE_ADDR_LO(sc); 10509 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10510 "address\n", val_hi, val_lo); 10511 10512 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10513 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10514 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10515 "address\n", val_hi, val_lo); 10516 10517 val_hi = BCE_ADDR_HI(sc->status_block); 10518 val_lo = BCE_ADDR_LO(sc->status_block); 10519 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10520 "virtual address\n", val_hi, val_lo); 10521 10522 val_hi = BCE_ADDR_HI(sc->stats_block); 10523 val_lo = BCE_ADDR_LO(sc->stats_block); 10524 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10525 "virtual address\n", val_hi, val_lo); 10526 10527 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10528 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10529 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10530 "virtual adddress\n", val_hi, val_lo); 10531 10532 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10533 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10534 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10535 "virtual address\n", val_hi, val_lo); 10536 10537 if (bce_hdr_split == TRUE) { 10538 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10539 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10540 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10541 "virtual address\n", val_hi, val_lo); 10542 } 10543 10544 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10545 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10546 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10547 "virtual address\n", val_hi, val_lo); 10548 10549 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10550 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10551 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10552 "virtual address\n", val_hi, val_lo); 10553 10554 if (bce_hdr_split == TRUE) { 10555 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10556 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10557 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10558 "virtual address\n", val_hi, val_lo); 10559 } 10560 10561 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10562 "h/w intrs\n", 10563 (long long unsigned int) sc->interrupts_generated); 10564 10565 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10566 "rx interrupts handled\n", 10567 (long long unsigned int) sc->interrupts_rx); 10568 10569 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10570 "tx interrupts handled\n", 10571 (long long unsigned int) sc->interrupts_tx); 10572 10573 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10574 "phy interrupts handled\n", 10575 (long long unsigned int) sc->phy_interrupts); 10576 10577 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10578 "status block index\n", sc->last_status_idx); 10579 10580 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10581 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10582 10583 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10584 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10585 10586 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10587 "byte seq index\n", sc->tx_prod_bseq); 10588 10589 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10590 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10591 10592 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10593 "tx_bd's\n", sc->used_tx_bd); 10594 10595 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10596 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10597 10598 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10599 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10600 10601 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10602 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10603 10604 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10605 "byte seq index\n", sc->rx_prod_bseq); 10606 10607 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10608 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10609 10610 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10611 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10612 10613 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10614 "rx_bd's\n", sc->free_rx_bd); 10615 10616 if (bce_hdr_split == TRUE) { 10617 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10618 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10619 10620 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10621 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10622 10623 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10624 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10625 } 10626 10627 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10628 "rx_bd's\n", sc->free_pg_bd); 10629 10630 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10631 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10632 10633 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10634 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10635 10636 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10637 "bce mac flags\n", sc->bce_flags); 10638 10639 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10640 "bce phy flags\n", sc->bce_phy_flags); 10641 10642 BCE_PRINTF( 10643 "----------------------------" 10644 "----------------" 10645 "----------------------------\n"); 10646 } 10647 10648 10649 /****************************************************************************/ 10650 /* Prints out the hardware state through a summary of important register, */ 10651 /* followed by a complete register dump. */ 10652 /* */ 10653 /* Returns: */ 10654 /* Nothing. */ 10655 /****************************************************************************/ 10656 static __attribute__ ((noinline)) void 10657 bce_dump_hw_state(struct bce_softc *sc) 10658 { 10659 u32 val; 10660 10661 BCE_PRINTF( 10662 "----------------------------" 10663 " Hardware State " 10664 "----------------------------\n"); 10665 10666 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10667 10668 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10669 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10670 val, BCE_MISC_ENABLE_STATUS_BITS); 10671 10672 val = REG_RD(sc, BCE_DMA_STATUS); 10673 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10674 val, BCE_DMA_STATUS); 10675 10676 val = REG_RD(sc, BCE_CTX_STATUS); 10677 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10678 val, BCE_CTX_STATUS); 10679 10680 val = REG_RD(sc, BCE_EMAC_STATUS); 10681 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10682 val, BCE_EMAC_STATUS); 10683 10684 val = REG_RD(sc, BCE_RPM_STATUS); 10685 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10686 val, BCE_RPM_STATUS); 10687 10688 /* ToDo: Create a #define for this constant. */ 10689 val = REG_RD(sc, 0x2004); 10690 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10691 val, 0x2004); 10692 10693 val = REG_RD(sc, BCE_RV2P_STATUS); 10694 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10695 val, BCE_RV2P_STATUS); 10696 10697 /* ToDo: Create a #define for this constant. */ 10698 val = REG_RD(sc, 0x2c04); 10699 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10700 val, 0x2c04); 10701 10702 val = REG_RD(sc, BCE_TBDR_STATUS); 10703 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10704 val, BCE_TBDR_STATUS); 10705 10706 val = REG_RD(sc, BCE_TDMA_STATUS); 10707 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10708 val, BCE_TDMA_STATUS); 10709 10710 val = REG_RD(sc, BCE_HC_STATUS); 10711 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10712 val, BCE_HC_STATUS); 10713 10714 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10715 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10716 val, BCE_TXP_CPU_STATE); 10717 10718 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10719 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10720 val, BCE_TPAT_CPU_STATE); 10721 10722 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10723 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10724 val, BCE_RXP_CPU_STATE); 10725 10726 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10727 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10728 val, BCE_COM_CPU_STATE); 10729 10730 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10731 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10732 val, BCE_MCP_CPU_STATE); 10733 10734 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10735 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10736 val, BCE_CP_CPU_STATE); 10737 10738 BCE_PRINTF( 10739 "----------------------------" 10740 "----------------" 10741 "----------------------------\n"); 10742 10743 BCE_PRINTF( 10744 "----------------------------" 10745 " Register Dump " 10746 "----------------------------\n"); 10747 10748 for (int i = 0x400; i < 0x8000; i += 0x10) { 10749 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10750 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10751 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10752 } 10753 10754 BCE_PRINTF( 10755 "----------------------------" 10756 "----------------" 10757 "----------------------------\n"); 10758 } 10759 10760 10761 /****************************************************************************/ 10762 /* Prints out the contentst of shared memory which is used for host driver */ 10763 /* to bootcode firmware communication. */ 10764 /* */ 10765 /* Returns: */ 10766 /* Nothing. */ 10767 /****************************************************************************/ 10768 static __attribute__ ((noinline)) void 10769 bce_dump_shmem_state(struct bce_softc *sc) 10770 { 10771 BCE_PRINTF( 10772 "----------------------------" 10773 " Hardware State " 10774 "----------------------------\n"); 10775 10776 BCE_PRINTF("0x%08X - Shared memory base address\n", 10777 sc->bce_shmem_base); 10778 BCE_PRINTF("%s - bootcode version\n", 10779 sc->bce_bc_ver); 10780 10781 BCE_PRINTF( 10782 "----------------------------" 10783 " Shared Mem " 10784 "----------------------------\n"); 10785 10786 for (int i = 0x0; i < 0x200; i += 0x10) { 10787 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10788 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 10789 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 10790 } 10791 10792 BCE_PRINTF( 10793 "----------------------------" 10794 "----------------" 10795 "----------------------------\n"); 10796 } 10797 10798 10799 /****************************************************************************/ 10800 /* Prints out the mailbox queue registers. */ 10801 /* */ 10802 /* Returns: */ 10803 /* Nothing. */ 10804 /****************************************************************************/ 10805 static __attribute__ ((noinline)) void 10806 bce_dump_mq_regs(struct bce_softc *sc) 10807 { 10808 BCE_PRINTF( 10809 "----------------------------" 10810 " MQ Regs " 10811 "----------------------------\n"); 10812 10813 BCE_PRINTF( 10814 "----------------------------" 10815 "----------------" 10816 "----------------------------\n"); 10817 10818 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10819 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10820 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10821 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10822 } 10823 10824 BCE_PRINTF( 10825 "----------------------------" 10826 "----------------" 10827 "----------------------------\n"); 10828 } 10829 10830 10831 /****************************************************************************/ 10832 /* Prints out the bootcode state. */ 10833 /* */ 10834 /* Returns: */ 10835 /* Nothing. */ 10836 /****************************************************************************/ 10837 static __attribute__ ((noinline)) void 10838 bce_dump_bc_state(struct bce_softc *sc) 10839 { 10840 u32 val; 10841 10842 BCE_PRINTF( 10843 "----------------------------" 10844 " Bootcode State " 10845 "----------------------------\n"); 10846 10847 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10848 10849 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10850 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10851 val, BCE_BC_RESET_TYPE); 10852 10853 val = bce_shmem_rd(sc, BCE_BC_STATE); 10854 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10855 val, BCE_BC_STATE); 10856 10857 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10858 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10859 val, BCE_BC_STATE_CONDITION); 10860 10861 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10862 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10863 val, BCE_BC_STATE_DEBUG_CMD); 10864 10865 BCE_PRINTF( 10866 "----------------------------" 10867 "----------------" 10868 "----------------------------\n"); 10869 } 10870 10871 10872 /****************************************************************************/ 10873 /* Prints out the TXP processor state. */ 10874 /* */ 10875 /* Returns: */ 10876 /* Nothing. */ 10877 /****************************************************************************/ 10878 static __attribute__ ((noinline)) void 10879 bce_dump_txp_state(struct bce_softc *sc, int regs) 10880 { 10881 u32 val; 10882 u32 fw_version[3]; 10883 10884 BCE_PRINTF( 10885 "----------------------------" 10886 " TXP State " 10887 "----------------------------\n"); 10888 10889 for (int i = 0; i < 3; i++) 10890 fw_version[i] = htonl(REG_RD_IND(sc, 10891 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10892 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10893 10894 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10895 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 10896 val, BCE_TXP_CPU_MODE); 10897 10898 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10899 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10900 val, BCE_TXP_CPU_STATE); 10901 10902 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10903 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 10904 val, BCE_TXP_CPU_EVENT_MASK); 10905 10906 if (regs) { 10907 BCE_PRINTF( 10908 "----------------------------" 10909 " Register Dump " 10910 "----------------------------\n"); 10911 10912 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10913 /* Skip the big blank spaces */ 10914 if (i < 0x454000 && i > 0x5ffff) 10915 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10916 "0x%08X 0x%08X\n", i, 10917 REG_RD_IND(sc, i), 10918 REG_RD_IND(sc, i + 0x4), 10919 REG_RD_IND(sc, i + 0x8), 10920 REG_RD_IND(sc, i + 0xC)); 10921 } 10922 } 10923 10924 BCE_PRINTF( 10925 "----------------------------" 10926 "----------------" 10927 "----------------------------\n"); 10928 } 10929 10930 10931 /****************************************************************************/ 10932 /* Prints out the RXP processor state. */ 10933 /* */ 10934 /* Returns: */ 10935 /* Nothing. */ 10936 /****************************************************************************/ 10937 static __attribute__ ((noinline)) void 10938 bce_dump_rxp_state(struct bce_softc *sc, int regs) 10939 { 10940 u32 val; 10941 u32 fw_version[3]; 10942 10943 BCE_PRINTF( 10944 "----------------------------" 10945 " RXP State " 10946 "----------------------------\n"); 10947 10948 for (int i = 0; i < 3; i++) 10949 fw_version[i] = htonl(REG_RD_IND(sc, 10950 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10951 10952 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10953 10954 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10955 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 10956 val, BCE_RXP_CPU_MODE); 10957 10958 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10959 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10960 val, BCE_RXP_CPU_STATE); 10961 10962 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10963 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 10964 val, BCE_RXP_CPU_EVENT_MASK); 10965 10966 if (regs) { 10967 BCE_PRINTF( 10968 "----------------------------" 10969 " Register Dump " 10970 "----------------------------\n"); 10971 10972 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 10973 /* Skip the big blank sapces */ 10974 if (i < 0xc5400 && i > 0xdffff) 10975 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10976 "0x%08X 0x%08X\n", i, 10977 REG_RD_IND(sc, i), 10978 REG_RD_IND(sc, i + 0x4), 10979 REG_RD_IND(sc, i + 0x8), 10980 REG_RD_IND(sc, i + 0xC)); 10981 } 10982 } 10983 10984 BCE_PRINTF( 10985 "----------------------------" 10986 "----------------" 10987 "----------------------------\n"); 10988 } 10989 10990 10991 /****************************************************************************/ 10992 /* Prints out the TPAT processor state. */ 10993 /* */ 10994 /* Returns: */ 10995 /* Nothing. */ 10996 /****************************************************************************/ 10997 static __attribute__ ((noinline)) void 10998 bce_dump_tpat_state(struct bce_softc *sc, int regs) 10999 { 11000 u32 val; 11001 u32 fw_version[3]; 11002 11003 BCE_PRINTF( 11004 "----------------------------" 11005 " TPAT State " 11006 "----------------------------\n"); 11007 11008 for (int i = 0; i < 3; i++) 11009 fw_version[i] = htonl(REG_RD_IND(sc, 11010 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11011 11012 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11013 11014 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11015 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11016 val, BCE_TPAT_CPU_MODE); 11017 11018 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11019 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11020 val, BCE_TPAT_CPU_STATE); 11021 11022 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11023 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11024 val, BCE_TPAT_CPU_EVENT_MASK); 11025 11026 if (regs) { 11027 BCE_PRINTF( 11028 "----------------------------" 11029 " Register Dump " 11030 "----------------------------\n"); 11031 11032 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11033 /* Skip the big blank spaces */ 11034 if (i < 0x854000 && i > 0x9ffff) 11035 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11036 "0x%08X 0x%08X\n", i, 11037 REG_RD_IND(sc, i), 11038 REG_RD_IND(sc, i + 0x4), 11039 REG_RD_IND(sc, i + 0x8), 11040 REG_RD_IND(sc, i + 0xC)); 11041 } 11042 } 11043 11044 BCE_PRINTF( 11045 "----------------------------" 11046 "----------------" 11047 "----------------------------\n"); 11048 } 11049 11050 11051 /****************************************************************************/ 11052 /* Prints out the Command Procesor (CP) state. */ 11053 /* */ 11054 /* Returns: */ 11055 /* Nothing. */ 11056 /****************************************************************************/ 11057 static __attribute__ ((noinline)) void 11058 bce_dump_cp_state(struct bce_softc *sc, int regs) 11059 { 11060 u32 val; 11061 u32 fw_version[3]; 11062 11063 BCE_PRINTF( 11064 "----------------------------" 11065 " CP State " 11066 "----------------------------\n"); 11067 11068 for (int i = 0; i < 3; i++) 11069 fw_version[i] = htonl(REG_RD_IND(sc, 11070 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11071 11072 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11073 11074 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11075 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11076 val, BCE_CP_CPU_MODE); 11077 11078 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11079 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11080 val, BCE_CP_CPU_STATE); 11081 11082 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11083 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11084 BCE_CP_CPU_EVENT_MASK); 11085 11086 if (regs) { 11087 BCE_PRINTF( 11088 "----------------------------" 11089 " Register Dump " 11090 "----------------------------\n"); 11091 11092 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11093 /* Skip the big blank spaces */ 11094 if (i < 0x185400 && i > 0x19ffff) 11095 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11096 "0x%08X 0x%08X\n", i, 11097 REG_RD_IND(sc, i), 11098 REG_RD_IND(sc, i + 0x4), 11099 REG_RD_IND(sc, i + 0x8), 11100 REG_RD_IND(sc, i + 0xC)); 11101 } 11102 } 11103 11104 BCE_PRINTF( 11105 "----------------------------" 11106 "----------------" 11107 "----------------------------\n"); 11108 } 11109 11110 11111 /****************************************************************************/ 11112 /* Prints out the Completion Procesor (COM) state. */ 11113 /* */ 11114 /* Returns: */ 11115 /* Nothing. */ 11116 /****************************************************************************/ 11117 static __attribute__ ((noinline)) void 11118 bce_dump_com_state(struct bce_softc *sc, int regs) 11119 { 11120 u32 val; 11121 u32 fw_version[4]; 11122 11123 BCE_PRINTF( 11124 "----------------------------" 11125 " COM State " 11126 "----------------------------\n"); 11127 11128 for (int i = 0; i < 3; i++) 11129 fw_version[i] = htonl(REG_RD_IND(sc, 11130 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11131 11132 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11133 11134 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11135 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11136 val, BCE_COM_CPU_MODE); 11137 11138 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11139 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11140 val, BCE_COM_CPU_STATE); 11141 11142 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11143 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11144 BCE_COM_CPU_EVENT_MASK); 11145 11146 if (regs) { 11147 BCE_PRINTF( 11148 "----------------------------" 11149 " Register Dump " 11150 "----------------------------\n"); 11151 11152 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11153 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11154 "0x%08X 0x%08X\n", i, 11155 REG_RD_IND(sc, i), 11156 REG_RD_IND(sc, i + 0x4), 11157 REG_RD_IND(sc, i + 0x8), 11158 REG_RD_IND(sc, i + 0xC)); 11159 } 11160 } 11161 11162 BCE_PRINTF( 11163 "----------------------------" 11164 "----------------" 11165 "----------------------------\n"); 11166 } 11167 11168 11169 /****************************************************************************/ 11170 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11171 /* */ 11172 /* Returns: */ 11173 /* Nothing. */ 11174 /****************************************************************************/ 11175 static __attribute__ ((noinline)) void 11176 bce_dump_rv2p_state(struct bce_softc *sc) 11177 { 11178 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11179 11180 BCE_PRINTF( 11181 "----------------------------" 11182 " RV2P State " 11183 "----------------------------\n"); 11184 11185 /* Stall the RV2P processors. */ 11186 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11187 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11188 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11189 11190 /* Read the firmware version. */ 11191 val = 0x00000001; 11192 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11193 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11194 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11195 BCE_RV2P_INSTR_HIGH_HIGH; 11196 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11197 fw_ver_high, fw_ver_low); 11198 11199 val = 0x00000001; 11200 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11201 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11202 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11203 BCE_RV2P_INSTR_HIGH_HIGH; 11204 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11205 fw_ver_high, fw_ver_low); 11206 11207 /* Resume the RV2P processors. */ 11208 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11209 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11210 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11211 11212 /* Fetch the program counter value. */ 11213 val = 0x68007800; 11214 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11215 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11216 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11217 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11218 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11219 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11220 11221 /* Fetch the program counter value again to see if it is advancing. */ 11222 val = 0x68007800; 11223 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11224 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11225 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11226 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11227 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11228 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11229 11230 BCE_PRINTF( 11231 "----------------------------" 11232 "----------------" 11233 "----------------------------\n"); 11234 } 11235 11236 11237 /****************************************************************************/ 11238 /* Prints out the driver state and then enters the debugger. */ 11239 /* */ 11240 /* Returns: */ 11241 /* Nothing. */ 11242 /****************************************************************************/ 11243 static __attribute__ ((noinline)) void 11244 bce_breakpoint(struct bce_softc *sc) 11245 { 11246 11247 /* 11248 * Unreachable code to silence compiler warnings 11249 * about unused functions. 11250 */ 11251 if (0) { 11252 bce_freeze_controller(sc); 11253 bce_unfreeze_controller(sc); 11254 bce_dump_enet(sc, NULL); 11255 bce_dump_txbd(sc, 0, NULL); 11256 bce_dump_rxbd(sc, 0, NULL); 11257 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11258 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11259 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11260 bce_dump_l2fhdr(sc, 0, NULL); 11261 bce_dump_ctx(sc, RX_CID); 11262 bce_dump_ftqs(sc); 11263 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11264 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11265 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11266 bce_dump_status_block(sc); 11267 bce_dump_stats_block(sc); 11268 bce_dump_driver_state(sc); 11269 bce_dump_hw_state(sc); 11270 bce_dump_bc_state(sc); 11271 bce_dump_txp_state(sc, 0); 11272 bce_dump_rxp_state(sc, 0); 11273 bce_dump_tpat_state(sc, 0); 11274 bce_dump_cp_state(sc, 0); 11275 bce_dump_com_state(sc, 0); 11276 bce_dump_rv2p_state(sc); 11277 bce_dump_pgbd(sc, 0, NULL); 11278 } 11279 11280 bce_dump_status_block(sc); 11281 bce_dump_driver_state(sc); 11282 11283 /* Call the debugger. */ 11284 breakpoint(); 11285 11286 return; 11287 } 11288 #endif 11289 11290