1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2014 QLogic Corporation 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * The following controllers are supported by this driver: 34 * BCM5706C A2, A3 35 * BCM5706S A2, A3 36 * BCM5708C B1, B2 37 * BCM5708S B1, B2 38 * BCM5709C A1, C0 39 * BCM5709S A1, C0 40 * BCM5716C C0 41 * BCM5716S C0 42 * 43 * The following controllers are not supported by this driver: 44 * BCM5706C A0, A1 (pre-production) 45 * BCM5706S A0, A1 (pre-production) 46 * BCM5708C A0, B0 (pre-production) 47 * BCM5708S A0, B0 (pre-production) 48 * BCM5709C A0 B0, B1, B2 (pre-production) 49 * BCM5709S A0, B0, B1, B2 (pre-production) 50 */ 51 52 #include "opt_bce.h" 53 54 #include <sys/param.h> 55 #include <sys/endian.h> 56 #include <sys/systm.h> 57 #include <sys/sockio.h> 58 #include <sys/lock.h> 59 #include <sys/mbuf.h> 60 #include <sys/malloc.h> 61 #include <sys/mutex.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/socket.h> 65 #include <sys/sysctl.h> 66 #include <sys/queue.h> 67 68 #include <net/bpf.h> 69 #include <net/ethernet.h> 70 #include <net/if.h> 71 #include <net/if_var.h> 72 #include <net/if_arp.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/if_types.h> 77 #include <net/if_vlan_var.h> 78 79 #include <netinet/in_systm.h> 80 #include <netinet/in.h> 81 #include <netinet/if_ether.h> 82 #include <netinet/ip.h> 83 #include <netinet/ip6.h> 84 #include <netinet/tcp.h> 85 #include <netinet/udp.h> 86 87 #include <machine/bus.h> 88 #include <machine/resource.h> 89 #include <sys/bus.h> 90 #include <sys/rman.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include "miidevs.h" 95 #include <dev/mii/brgphyreg.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 100 #include "miibus_if.h" 101 102 #include <dev/bce/if_bcereg.h> 103 #include <dev/bce/if_bcefw.h> 104 105 /****************************************************************************/ 106 /* BCE Debug Options */ 107 /****************************************************************************/ 108 #ifdef BCE_DEBUG 109 u32 bce_debug = BCE_WARN; 110 111 /* 0 = Never */ 112 /* 1 = 1 in 2,147,483,648 */ 113 /* 256 = 1 in 8,388,608 */ 114 /* 2048 = 1 in 1,048,576 */ 115 /* 65536 = 1 in 32,768 */ 116 /* 1048576 = 1 in 2,048 */ 117 /* 268435456 = 1 in 8 */ 118 /* 536870912 = 1 in 4 */ 119 /* 1073741824 = 1 in 2 */ 120 121 /* Controls how often the l2_fhdr frame error check will fail. */ 122 int l2fhdr_error_sim_control = 0; 123 124 /* Controls how often the unexpected attention check will fail. */ 125 int unexpected_attention_sim_control = 0; 126 127 /* Controls how often to simulate an mbuf allocation failure. */ 128 int mbuf_alloc_failed_sim_control = 0; 129 130 /* Controls how often to simulate a DMA mapping failure. */ 131 int dma_map_addr_failed_sim_control = 0; 132 133 /* Controls how often to simulate a bootcode failure. */ 134 int bootcode_running_failure_sim_control = 0; 135 #endif 136 137 /****************************************************************************/ 138 /* PCI Device ID Table */ 139 /* */ 140 /* Used by bce_probe() to identify the devices supported by this driver. */ 141 /****************************************************************************/ 142 #define BCE_DEVDESC_MAX 64 143 144 static const struct bce_type bce_devs[] = { 145 /* BCM5706C Controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 147 "HP NC370T Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 149 "HP NC370i Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 151 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 153 "HP NC371i Multifunction Gigabit Server Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 155 "QLogic NetXtreme II BCM5706 1000Base-T" }, 156 157 /* BCM5706S controllers and OEM boards. */ 158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 159 "HP NC370F Multifunction Gigabit Server Adapter" }, 160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 161 "QLogic NetXtreme II BCM5706 1000Base-SX" }, 162 163 /* BCM5708C controllers and OEM boards. */ 164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 165 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 167 "HP NC373i Multifunction Gigabit Server Adapter" }, 168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 169 "HP NC374m PCIe Multifunction Adapter" }, 170 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 171 "QLogic NetXtreme II BCM5708 1000Base-T" }, 172 173 /* BCM5708S controllers and OEM boards. */ 174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 175 "HP NC373m Multifunction Gigabit Server Adapter" }, 176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 177 "HP NC373i Multifunction Gigabit Server Adapter" }, 178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 179 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 180 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 181 "QLogic NetXtreme II BCM5708 1000Base-SX" }, 182 183 /* BCM5709C controllers and OEM boards. */ 184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 185 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 187 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 188 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 189 "QLogic NetXtreme II BCM5709 1000Base-T" }, 190 191 /* BCM5709S controllers and OEM boards. */ 192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 193 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 195 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 196 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 197 "QLogic NetXtreme II BCM5709 1000Base-SX" }, 198 199 /* BCM5716 controllers and OEM boards. */ 200 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 201 "QLogic NetXtreme II BCM5716 1000Base-T" }, 202 203 { 0, 0, 0, 0, NULL } 204 }; 205 206 207 /****************************************************************************/ 208 /* Supported Flash NVRAM device data. */ 209 /****************************************************************************/ 210 static const struct flash_spec flash_table[] = 211 { 212 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 213 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 214 215 /* Slow EEPROM */ 216 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 217 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 218 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 219 "EEPROM - slow"}, 220 /* Expansion entry 0001 */ 221 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 223 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 224 "Entry 0001"}, 225 /* Saifun SA25F010 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 230 "Non-buffered flash (128kB)"}, 231 /* Saifun SA25F020 (non-buffered flash) */ 232 /* strap, cfg1, & write1 need updates */ 233 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 236 "Non-buffered flash (256kB)"}, 237 /* Expansion entry 0100 */ 238 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 0100"}, 242 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 243 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 244 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 245 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 246 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 247 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 248 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 249 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 250 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 251 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 252 /* Saifun SA25F005 (non-buffered flash) */ 253 /* strap, cfg1, & write1 need updates */ 254 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 255 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 256 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 257 "Non-buffered flash (64kB)"}, 258 /* Fast EEPROM */ 259 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 260 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 261 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 262 "EEPROM - fast"}, 263 /* Expansion entry 1001 */ 264 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 265 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 266 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 267 "Entry 1001"}, 268 /* Expansion entry 1010 */ 269 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 270 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 271 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 272 "Entry 1010"}, 273 /* ATMEL AT45DB011B (buffered flash) */ 274 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 275 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 276 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 277 "Buffered flash (128kB)"}, 278 /* Expansion entry 1100 */ 279 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 280 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 281 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 282 "Entry 1100"}, 283 /* Expansion entry 1101 */ 284 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 285 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 286 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 287 "Entry 1101"}, 288 /* Ateml Expansion entry 1110 */ 289 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 290 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 291 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 292 "Entry 1110 (Atmel)"}, 293 /* ATMEL AT45DB021B (buffered flash) */ 294 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 295 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 296 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 297 "Buffered flash (256kB)"}, 298 }; 299 300 /* 301 * The BCM5709 controllers transparently handle the 302 * differences between Atmel 264 byte pages and all 303 * flash devices which use 256 byte pages, so no 304 * logical-to-physical mapping is required in the 305 * driver. 306 */ 307 static const struct flash_spec flash_5709 = { 308 .flags = BCE_NV_BUFFERED, 309 .page_bits = BCM5709_FLASH_PAGE_BITS, 310 .page_size = BCM5709_FLASH_PAGE_SIZE, 311 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 312 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 313 .name = "5709/5716 buffered flash (256kB)", 314 }; 315 316 317 /****************************************************************************/ 318 /* FreeBSD device entry points. */ 319 /****************************************************************************/ 320 static int bce_probe (device_t); 321 static int bce_attach (device_t); 322 static int bce_detach (device_t); 323 static int bce_shutdown (device_t); 324 325 326 /****************************************************************************/ 327 /* BCE Debug Data Structure Dump Routines */ 328 /****************************************************************************/ 329 #ifdef BCE_DEBUG 330 static u32 bce_reg_rd (struct bce_softc *, u32); 331 static void bce_reg_wr (struct bce_softc *, u32, u32); 332 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 333 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 334 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 335 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 336 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 337 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 338 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 339 static void bce_dump_txbd (struct bce_softc *, 340 int, struct tx_bd *); 341 static void bce_dump_rxbd (struct bce_softc *, 342 int, struct rx_bd *); 343 static void bce_dump_pgbd (struct bce_softc *, 344 int, struct rx_bd *); 345 static void bce_dump_l2fhdr (struct bce_softc *, 346 int, struct l2_fhdr *); 347 static void bce_dump_ctx (struct bce_softc *, u16); 348 static void bce_dump_ftqs (struct bce_softc *); 349 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 350 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 351 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 352 static void bce_dump_status_block (struct bce_softc *); 353 static void bce_dump_stats_block (struct bce_softc *); 354 static void bce_dump_driver_state (struct bce_softc *); 355 static void bce_dump_hw_state (struct bce_softc *); 356 static void bce_dump_shmem_state (struct bce_softc *); 357 static void bce_dump_mq_regs (struct bce_softc *); 358 static void bce_dump_bc_state (struct bce_softc *); 359 static void bce_dump_txp_state (struct bce_softc *, int); 360 static void bce_dump_rxp_state (struct bce_softc *, int); 361 static void bce_dump_tpat_state (struct bce_softc *, int); 362 static void bce_dump_cp_state (struct bce_softc *, int); 363 static void bce_dump_com_state (struct bce_softc *, int); 364 static void bce_dump_rv2p_state (struct bce_softc *); 365 static void bce_breakpoint (struct bce_softc *); 366 #endif /*BCE_DEBUG */ 367 368 369 /****************************************************************************/ 370 /* BCE Register/Memory Access Routines */ 371 /****************************************************************************/ 372 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 373 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 374 static void bce_shmem_wr (struct bce_softc *, u32, u32); 375 static u32 bce_shmem_rd (struct bce_softc *, u32); 376 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 377 static int bce_miibus_read_reg (device_t, int, int); 378 static int bce_miibus_write_reg (device_t, int, int, int); 379 static void bce_miibus_statchg (device_t); 380 381 #ifdef BCE_DEBUG 382 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 383 #ifdef BCE_NVRAM_WRITE_SUPPORT 384 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 385 #endif 386 #endif 387 388 /****************************************************************************/ 389 /* BCE NVRAM Access Routines */ 390 /****************************************************************************/ 391 static int bce_acquire_nvram_lock (struct bce_softc *); 392 static int bce_release_nvram_lock (struct bce_softc *); 393 static void bce_enable_nvram_access(struct bce_softc *); 394 static void bce_disable_nvram_access(struct bce_softc *); 395 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 396 static int bce_init_nvram (struct bce_softc *); 397 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 398 static int bce_nvram_test (struct bce_softc *); 399 #ifdef BCE_NVRAM_WRITE_SUPPORT 400 static int bce_enable_nvram_write (struct bce_softc *); 401 static void bce_disable_nvram_write(struct bce_softc *); 402 static int bce_nvram_erase_page (struct bce_softc *, u32); 403 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 404 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 405 #endif 406 407 /****************************************************************************/ 408 /* */ 409 /****************************************************************************/ 410 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 411 static void bce_get_media (struct bce_softc *); 412 static void bce_init_media (struct bce_softc *); 413 static u32 bce_get_rphy_link (struct bce_softc *); 414 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 415 static int bce_dma_alloc (device_t); 416 static void bce_dma_free (struct bce_softc *); 417 static void bce_release_resources (struct bce_softc *); 418 419 /****************************************************************************/ 420 /* BCE Firmware Synchronization and Load */ 421 /****************************************************************************/ 422 static void bce_fw_cap_init (struct bce_softc *); 423 static int bce_fw_sync (struct bce_softc *, u32); 424 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 425 u32); 426 static void bce_load_cpu_fw (struct bce_softc *, 427 struct cpu_reg *, struct fw_info *); 428 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 429 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 430 static void bce_start_rxp_cpu (struct bce_softc *); 431 static void bce_init_rxp_cpu (struct bce_softc *); 432 static void bce_init_txp_cpu (struct bce_softc *); 433 static void bce_init_tpat_cpu (struct bce_softc *); 434 static void bce_init_cp_cpu (struct bce_softc *); 435 static void bce_init_com_cpu (struct bce_softc *); 436 static void bce_init_cpus (struct bce_softc *); 437 438 static void bce_print_adapter_info (struct bce_softc *); 439 static void bce_probe_pci_caps (device_t, struct bce_softc *); 440 static void bce_stop (struct bce_softc *); 441 static int bce_reset (struct bce_softc *, u32); 442 static int bce_chipinit (struct bce_softc *); 443 static int bce_blockinit (struct bce_softc *); 444 445 static int bce_init_tx_chain (struct bce_softc *); 446 static void bce_free_tx_chain (struct bce_softc *); 447 448 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 449 static int bce_init_rx_chain (struct bce_softc *); 450 static void bce_fill_rx_chain (struct bce_softc *); 451 static void bce_free_rx_chain (struct bce_softc *); 452 453 static int bce_get_pg_buf (struct bce_softc *, u16, u16); 454 static int bce_init_pg_chain (struct bce_softc *); 455 static void bce_fill_pg_chain (struct bce_softc *); 456 static void bce_free_pg_chain (struct bce_softc *); 457 458 static struct mbuf *bce_tso_setup (struct bce_softc *, 459 struct mbuf **, u16 *); 460 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 461 static void bce_start_locked (struct ifnet *); 462 static void bce_start (struct ifnet *); 463 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 464 static uint64_t bce_get_counter (struct ifnet *, ift_counter); 465 static void bce_watchdog (struct bce_softc *); 466 static int bce_ifmedia_upd (struct ifnet *); 467 static int bce_ifmedia_upd_locked (struct ifnet *); 468 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 469 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 470 static void bce_init_locked (struct bce_softc *); 471 static void bce_init (void *); 472 static void bce_mgmt_init_locked (struct bce_softc *sc); 473 474 static int bce_init_ctx (struct bce_softc *); 475 static void bce_get_mac_addr (struct bce_softc *); 476 static void bce_set_mac_addr (struct bce_softc *); 477 static void bce_phy_intr (struct bce_softc *); 478 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 479 static void bce_rx_intr (struct bce_softc *); 480 static void bce_tx_intr (struct bce_softc *); 481 static void bce_disable_intr (struct bce_softc *); 482 static void bce_enable_intr (struct bce_softc *, int); 483 484 static void bce_intr (void *); 485 static void bce_set_rx_mode (struct bce_softc *); 486 static void bce_stats_update (struct bce_softc *); 487 static void bce_tick (void *); 488 static void bce_pulse (void *); 489 static void bce_add_sysctls (struct bce_softc *); 490 491 492 /****************************************************************************/ 493 /* FreeBSD device dispatch table. */ 494 /****************************************************************************/ 495 static device_method_t bce_methods[] = { 496 /* Device interface (device_if.h) */ 497 DEVMETHOD(device_probe, bce_probe), 498 DEVMETHOD(device_attach, bce_attach), 499 DEVMETHOD(device_detach, bce_detach), 500 DEVMETHOD(device_shutdown, bce_shutdown), 501 /* Supported by device interface but not used here. */ 502 /* DEVMETHOD(device_identify, bce_identify), */ 503 /* DEVMETHOD(device_suspend, bce_suspend), */ 504 /* DEVMETHOD(device_resume, bce_resume), */ 505 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 506 507 /* MII interface (miibus_if.h) */ 508 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 509 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 510 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 511 /* Supported by MII interface but not used here. */ 512 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 513 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 514 515 DEVMETHOD_END 516 }; 517 518 static driver_t bce_driver = { 519 "bce", 520 bce_methods, 521 sizeof(struct bce_softc) 522 }; 523 524 static devclass_t bce_devclass; 525 526 MODULE_DEPEND(bce, pci, 1, 1, 1); 527 MODULE_DEPEND(bce, ether, 1, 1, 1); 528 MODULE_DEPEND(bce, miibus, 1, 1, 1); 529 530 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL); 531 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL); 532 MODULE_PNP_INFO("U16:vendor;U16:device;U16:#;U16:#;D:#", pci, bce, 533 bce_devs, nitems(bce_devs) - 1); 534 535 /****************************************************************************/ 536 /* Tunable device values */ 537 /****************************************************************************/ 538 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 539 "bce driver parameters"); 540 541 /* Allowable values are TRUE or FALSE */ 542 static int bce_verbose = TRUE; 543 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 544 "Verbose output enable/disable"); 545 546 /* Allowable values are TRUE or FALSE */ 547 static int bce_tso_enable = TRUE; 548 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 549 "TSO Enable/Disable"); 550 551 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 552 /* ToDo: Add MSI-X support. */ 553 static int bce_msi_enable = 1; 554 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 555 "MSI-X|MSI|INTx selector"); 556 557 /* Allowable values are 1, 2, 4, 8. */ 558 static int bce_rx_pages = DEFAULT_RX_PAGES; 559 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 560 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 561 562 /* Allowable values are 1, 2, 4, 8. */ 563 static int bce_tx_pages = DEFAULT_TX_PAGES; 564 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 565 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 566 567 /* Allowable values are TRUE or FALSE. */ 568 static int bce_hdr_split = TRUE; 569 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 570 "Frame header/payload splitting Enable/Disable"); 571 572 /* Allowable values are TRUE or FALSE. */ 573 static int bce_strict_rx_mtu = FALSE; 574 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 575 &bce_strict_rx_mtu, 0, 576 "Enable/Disable strict RX frame size checking"); 577 578 /* Allowable values are 0 ... 100 */ 579 #ifdef BCE_DEBUG 580 /* Generate 1 interrupt for every transmit completion. */ 581 static int bce_tx_quick_cons_trip_int = 1; 582 #else 583 /* Generate 1 interrupt for every 20 transmit completions. */ 584 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 585 #endif 586 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 587 &bce_tx_quick_cons_trip_int, 0, 588 "Transmit BD trip point during interrupts"); 589 590 /* Allowable values are 0 ... 100 */ 591 /* Generate 1 interrupt for every transmit completion. */ 592 #ifdef BCE_DEBUG 593 static int bce_tx_quick_cons_trip = 1; 594 #else 595 /* Generate 1 interrupt for every 20 transmit completions. */ 596 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 597 #endif 598 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 599 &bce_tx_quick_cons_trip, 0, 600 "Transmit BD trip point"); 601 602 /* Allowable values are 0 ... 100 */ 603 #ifdef BCE_DEBUG 604 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 605 static int bce_tx_ticks_int = 0; 606 #else 607 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 608 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 609 #endif 610 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 611 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 612 613 /* Allowable values are 0 ... 100 */ 614 #ifdef BCE_DEBUG 615 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 616 static int bce_tx_ticks = 0; 617 #else 618 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 619 static int bce_tx_ticks = DEFAULT_TX_TICKS; 620 #endif 621 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 622 &bce_tx_ticks, 0, "Transmit ticks count"); 623 624 /* Allowable values are 1 ... 100 */ 625 #ifdef BCE_DEBUG 626 /* Generate 1 interrupt for every received frame. */ 627 static int bce_rx_quick_cons_trip_int = 1; 628 #else 629 /* Generate 1 interrupt for every 6 received frames. */ 630 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 631 #endif 632 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 633 &bce_rx_quick_cons_trip_int, 0, 634 "Receive BD trip point duirng interrupts"); 635 636 /* Allowable values are 1 ... 100 */ 637 #ifdef BCE_DEBUG 638 /* Generate 1 interrupt for every received frame. */ 639 static int bce_rx_quick_cons_trip = 1; 640 #else 641 /* Generate 1 interrupt for every 6 received frames. */ 642 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 643 #endif 644 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 645 &bce_rx_quick_cons_trip, 0, 646 "Receive BD trip point"); 647 648 /* Allowable values are 0 ... 100 */ 649 #ifdef BCE_DEBUG 650 /* Generate an int. if 0us have elapsed since the last received frame. */ 651 static int bce_rx_ticks_int = 0; 652 #else 653 /* Generate an int. if 18us have elapsed since the last received frame. */ 654 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 655 #endif 656 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 657 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 658 659 /* Allowable values are 0 ... 100 */ 660 #ifdef BCE_DEBUG 661 /* Generate an int. if 0us have elapsed since the last received frame. */ 662 static int bce_rx_ticks = 0; 663 #else 664 /* Generate an int. if 18us have elapsed since the last received frame. */ 665 static int bce_rx_ticks = DEFAULT_RX_TICKS; 666 #endif 667 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 668 &bce_rx_ticks, 0, "Receive ticks count"); 669 670 671 /****************************************************************************/ 672 /* Device probe function. */ 673 /* */ 674 /* Compares the device to the driver's list of supported devices and */ 675 /* reports back to the OS whether this is the right driver for the device. */ 676 /* */ 677 /* Returns: */ 678 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 679 /****************************************************************************/ 680 static int 681 bce_probe(device_t dev) 682 { 683 const struct bce_type *t; 684 struct bce_softc *sc; 685 char *descbuf; 686 u16 vid = 0, did = 0, svid = 0, sdid = 0; 687 688 t = bce_devs; 689 690 sc = device_get_softc(dev); 691 sc->bce_unit = device_get_unit(dev); 692 sc->bce_dev = dev; 693 694 /* Get the data for the device to be probed. */ 695 vid = pci_get_vendor(dev); 696 did = pci_get_device(dev); 697 svid = pci_get_subvendor(dev); 698 sdid = pci_get_subdevice(dev); 699 700 DBPRINT(sc, BCE_EXTREME_LOAD, 701 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 702 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 703 704 /* Look through the list of known devices for a match. */ 705 while(t->bce_name != NULL) { 706 707 if ((vid == t->bce_vid) && (did == t->bce_did) && 708 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 709 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 710 711 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 712 713 if (descbuf == NULL) 714 return(ENOMEM); 715 716 /* Print out the device identity. */ 717 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 718 t->bce_name, (((pci_read_config(dev, 719 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 720 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 721 722 device_set_desc_copy(dev, descbuf); 723 free(descbuf, M_TEMP); 724 return(BUS_PROBE_DEFAULT); 725 } 726 t++; 727 } 728 729 return(ENXIO); 730 } 731 732 733 /****************************************************************************/ 734 /* PCI Capabilities Probe Function. */ 735 /* */ 736 /* Walks the PCI capabiites list for the device to find what features are */ 737 /* supported. */ 738 /* */ 739 /* Returns: */ 740 /* None. */ 741 /****************************************************************************/ 742 static void 743 bce_print_adapter_info(struct bce_softc *sc) 744 { 745 int i = 0; 746 747 DBENTER(BCE_VERBOSE_LOAD); 748 749 if (bce_verbose || bootverbose) { 750 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 751 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 752 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 753 754 755 /* Bus info. */ 756 if (sc->bce_flags & BCE_PCIE_FLAG) { 757 printf("Bus (PCIe x%d, ", sc->link_width); 758 switch (sc->link_speed) { 759 case 1: printf("2.5Gbps); "); break; 760 case 2: printf("5Gbps); "); break; 761 default: printf("Unknown link speed); "); 762 } 763 } else { 764 printf("Bus (PCI%s, %s, %dMHz); ", 765 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 766 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 767 "32-bit" : "64-bit"), sc->bus_speed_mhz); 768 } 769 770 /* Firmware version and device features. */ 771 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 772 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 773 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 774 775 if (bce_hdr_split == TRUE) { 776 printf("SPLT"); 777 i++; 778 } 779 780 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 781 if (i > 0) printf("|"); 782 printf("MSI"); i++; 783 } 784 785 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 786 if (i > 0) printf("|"); 787 printf("MSI-X"); i++; 788 } 789 790 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 791 if (i > 0) printf("|"); 792 printf("2.5G"); i++; 793 } 794 795 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 796 if (i > 0) printf("|"); 797 printf("Remote PHY(%s)", 798 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 799 "FIBER" : "TP"); i++; 800 } 801 802 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 803 if (i > 0) printf("|"); 804 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 805 } else { 806 printf(")\n"); 807 } 808 809 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 810 sc->bce_rx_quick_cons_trip_int, 811 sc->bce_rx_quick_cons_trip, 812 sc->bce_rx_ticks_int, 813 sc->bce_rx_ticks, 814 sc->bce_tx_quick_cons_trip_int, 815 sc->bce_tx_quick_cons_trip, 816 sc->bce_tx_ticks_int, 817 sc->bce_tx_ticks); 818 819 } 820 821 DBEXIT(BCE_VERBOSE_LOAD); 822 } 823 824 825 /****************************************************************************/ 826 /* PCI Capabilities Probe Function. */ 827 /* */ 828 /* Walks the PCI capabiites list for the device to find what features are */ 829 /* supported. */ 830 /* */ 831 /* Returns: */ 832 /* None. */ 833 /****************************************************************************/ 834 static void 835 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 836 { 837 u32 reg; 838 839 DBENTER(BCE_VERBOSE_LOAD); 840 841 /* Check if PCI-X capability is enabled. */ 842 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 843 if (reg != 0) 844 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 845 } 846 847 /* Check if PCIe capability is enabled. */ 848 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 849 if (reg != 0) { 850 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 851 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 852 "0x%08X\n", link_status); 853 sc->link_speed = link_status & 0xf; 854 sc->link_width = (link_status >> 4) & 0x3f; 855 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 856 sc->bce_flags |= BCE_PCIE_FLAG; 857 } 858 } 859 860 /* Check if MSI capability is enabled. */ 861 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 862 if (reg != 0) 863 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 864 } 865 866 /* Check if MSI-X capability is enabled. */ 867 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 868 if (reg != 0) 869 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 870 } 871 872 DBEXIT(BCE_VERBOSE_LOAD); 873 } 874 875 876 /****************************************************************************/ 877 /* Load and validate user tunable settings. */ 878 /* */ 879 /* Returns: */ 880 /* Nothing. */ 881 /****************************************************************************/ 882 static void 883 bce_set_tunables(struct bce_softc *sc) 884 { 885 /* Set sysctl values for RX page count. */ 886 switch (bce_rx_pages) { 887 case 1: 888 /* fall-through */ 889 case 2: 890 /* fall-through */ 891 case 4: 892 /* fall-through */ 893 case 8: 894 sc->rx_pages = bce_rx_pages; 895 break; 896 default: 897 sc->rx_pages = DEFAULT_RX_PAGES; 898 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 899 "hw.bce.rx_pages! Setting default of %d.\n", 900 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 901 } 902 903 /* ToDo: Consider allowing user setting for pg_pages. */ 904 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 905 906 /* Set sysctl values for TX page count. */ 907 switch (bce_tx_pages) { 908 case 1: 909 /* fall-through */ 910 case 2: 911 /* fall-through */ 912 case 4: 913 /* fall-through */ 914 case 8: 915 sc->tx_pages = bce_tx_pages; 916 break; 917 default: 918 sc->tx_pages = DEFAULT_TX_PAGES; 919 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 920 "hw.bce.tx_pages! Setting default of %d.\n", 921 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 922 } 923 924 /* 925 * Validate the TX trip point (i.e. the number of 926 * TX completions before a status block update is 927 * generated and an interrupt is asserted. 928 */ 929 if (bce_tx_quick_cons_trip_int <= 100) { 930 sc->bce_tx_quick_cons_trip_int = 931 bce_tx_quick_cons_trip_int; 932 } else { 933 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 934 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 935 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 936 DEFAULT_TX_QUICK_CONS_TRIP_INT); 937 sc->bce_tx_quick_cons_trip_int = 938 DEFAULT_TX_QUICK_CONS_TRIP_INT; 939 } 940 941 if (bce_tx_quick_cons_trip <= 100) { 942 sc->bce_tx_quick_cons_trip = 943 bce_tx_quick_cons_trip; 944 } else { 945 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 946 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 947 __FILE__, __LINE__, bce_tx_quick_cons_trip, 948 DEFAULT_TX_QUICK_CONS_TRIP); 949 sc->bce_tx_quick_cons_trip = 950 DEFAULT_TX_QUICK_CONS_TRIP; 951 } 952 953 /* 954 * Validate the TX ticks count (i.e. the maximum amount 955 * of time to wait after the last TX completion has 956 * occurred before a status block update is generated 957 * and an interrupt is asserted. 958 */ 959 if (bce_tx_ticks_int <= 100) { 960 sc->bce_tx_ticks_int = 961 bce_tx_ticks_int; 962 } else { 963 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 964 "hw.bce.tx_ticks_int! Setting default of %d.\n", 965 __FILE__, __LINE__, bce_tx_ticks_int, 966 DEFAULT_TX_TICKS_INT); 967 sc->bce_tx_ticks_int = 968 DEFAULT_TX_TICKS_INT; 969 } 970 971 if (bce_tx_ticks <= 100) { 972 sc->bce_tx_ticks = 973 bce_tx_ticks; 974 } else { 975 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 976 "hw.bce.tx_ticks! Setting default of %d.\n", 977 __FILE__, __LINE__, bce_tx_ticks, 978 DEFAULT_TX_TICKS); 979 sc->bce_tx_ticks = 980 DEFAULT_TX_TICKS; 981 } 982 983 /* 984 * Validate the RX trip point (i.e. the number of 985 * RX frames received before a status block update is 986 * generated and an interrupt is asserted. 987 */ 988 if (bce_rx_quick_cons_trip_int <= 100) { 989 sc->bce_rx_quick_cons_trip_int = 990 bce_rx_quick_cons_trip_int; 991 } else { 992 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 993 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 994 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 995 DEFAULT_RX_QUICK_CONS_TRIP_INT); 996 sc->bce_rx_quick_cons_trip_int = 997 DEFAULT_RX_QUICK_CONS_TRIP_INT; 998 } 999 1000 if (bce_rx_quick_cons_trip <= 100) { 1001 sc->bce_rx_quick_cons_trip = 1002 bce_rx_quick_cons_trip; 1003 } else { 1004 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1005 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 1006 __FILE__, __LINE__, bce_rx_quick_cons_trip, 1007 DEFAULT_RX_QUICK_CONS_TRIP); 1008 sc->bce_rx_quick_cons_trip = 1009 DEFAULT_RX_QUICK_CONS_TRIP; 1010 } 1011 1012 /* 1013 * Validate the RX ticks count (i.e. the maximum amount 1014 * of time to wait after the last RX frame has been 1015 * received before a status block update is generated 1016 * and an interrupt is asserted. 1017 */ 1018 if (bce_rx_ticks_int <= 100) { 1019 sc->bce_rx_ticks_int = bce_rx_ticks_int; 1020 } else { 1021 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1022 "hw.bce.rx_ticks_int! Setting default of %d.\n", 1023 __FILE__, __LINE__, bce_rx_ticks_int, 1024 DEFAULT_RX_TICKS_INT); 1025 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 1026 } 1027 1028 if (bce_rx_ticks <= 100) { 1029 sc->bce_rx_ticks = bce_rx_ticks; 1030 } else { 1031 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1032 "hw.bce.rx_ticks! Setting default of %d.\n", 1033 __FILE__, __LINE__, bce_rx_ticks, 1034 DEFAULT_RX_TICKS); 1035 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1036 } 1037 1038 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1039 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1040 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1041 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1042 __FILE__, __LINE__); 1043 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1044 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1045 } 1046 1047 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1048 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1049 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1050 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1051 __FILE__, __LINE__); 1052 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1053 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1054 } 1055 } 1056 1057 1058 /****************************************************************************/ 1059 /* Device attach function. */ 1060 /* */ 1061 /* Allocates device resources, performs secondary chip identification, */ 1062 /* resets and initializes the hardware, and initializes driver instance */ 1063 /* variables. */ 1064 /* */ 1065 /* Returns: */ 1066 /* 0 on success, positive value on failure. */ 1067 /****************************************************************************/ 1068 static int 1069 bce_attach(device_t dev) 1070 { 1071 struct bce_softc *sc; 1072 struct ifnet *ifp; 1073 u32 val; 1074 int count, error, rc = 0, rid; 1075 1076 sc = device_get_softc(dev); 1077 sc->bce_dev = dev; 1078 1079 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1080 1081 sc->bce_unit = device_get_unit(dev); 1082 1083 /* Set initial device and PHY flags */ 1084 sc->bce_flags = 0; 1085 sc->bce_phy_flags = 0; 1086 1087 bce_set_tunables(sc); 1088 1089 pci_enable_busmaster(dev); 1090 1091 /* Allocate PCI memory resources. */ 1092 rid = PCIR_BAR(0); 1093 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1094 &rid, RF_ACTIVE); 1095 1096 if (sc->bce_res_mem == NULL) { 1097 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1098 __FILE__, __LINE__); 1099 rc = ENXIO; 1100 goto bce_attach_fail; 1101 } 1102 1103 /* Get various resource handles. */ 1104 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1105 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1106 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1107 1108 bce_probe_pci_caps(dev, sc); 1109 1110 rid = 1; 1111 count = 0; 1112 #if 0 1113 /* Try allocating MSI-X interrupts. */ 1114 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1115 (bce_msi_enable >= 2) && 1116 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1117 &rid, RF_ACTIVE)) != NULL)) { 1118 1119 msi_needed = count = 1; 1120 1121 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1122 (count != msi_needed)) { 1123 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1124 "Received = %d, error = %d\n", __FILE__, __LINE__, 1125 msi_needed, count, error); 1126 count = 0; 1127 pci_release_msi(dev); 1128 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1129 sc->bce_res_irq); 1130 sc->bce_res_irq = NULL; 1131 } else { 1132 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1133 __FUNCTION__); 1134 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1135 } 1136 } 1137 #endif 1138 1139 /* Try allocating a MSI interrupt. */ 1140 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1141 (bce_msi_enable >= 1) && (count == 0)) { 1142 count = 1; 1143 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1144 BCE_PRINTF("%s(%d): MSI allocation failed! " 1145 "error = %d\n", __FILE__, __LINE__, error); 1146 count = 0; 1147 pci_release_msi(dev); 1148 } else { 1149 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1150 "interrupt.\n", __FUNCTION__); 1151 sc->bce_flags |= BCE_USING_MSI_FLAG; 1152 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1153 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1154 rid = 1; 1155 } 1156 } 1157 1158 /* Try allocating a legacy interrupt. */ 1159 if (count == 0) { 1160 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1161 __FUNCTION__); 1162 rid = 0; 1163 } 1164 1165 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1166 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1167 1168 /* Report any IRQ allocation errors. */ 1169 if (sc->bce_res_irq == NULL) { 1170 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1171 __FILE__, __LINE__); 1172 rc = ENXIO; 1173 goto bce_attach_fail; 1174 } 1175 1176 /* Initialize mutex for the current device instance. */ 1177 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1178 1179 /* 1180 * Configure byte swap and enable indirect register access. 1181 * Rely on CPU to do target byte swapping on big endian systems. 1182 * Access to registers outside of PCI configurtion space are not 1183 * valid until this is done. 1184 */ 1185 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1186 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1187 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1188 1189 /* Save ASIC revsion info. */ 1190 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1191 1192 /* Weed out any non-production controller revisions. */ 1193 switch(BCE_CHIP_ID(sc)) { 1194 case BCE_CHIP_ID_5706_A0: 1195 case BCE_CHIP_ID_5706_A1: 1196 case BCE_CHIP_ID_5708_A0: 1197 case BCE_CHIP_ID_5708_B0: 1198 case BCE_CHIP_ID_5709_A0: 1199 case BCE_CHIP_ID_5709_B0: 1200 case BCE_CHIP_ID_5709_B1: 1201 case BCE_CHIP_ID_5709_B2: 1202 BCE_PRINTF("%s(%d): Unsupported controller " 1203 "revision (%c%d)!\n", __FILE__, __LINE__, 1204 (((pci_read_config(dev, PCIR_REVID, 4) & 1205 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1206 PCIR_REVID, 4) & 0xf)); 1207 rc = ENODEV; 1208 goto bce_attach_fail; 1209 } 1210 1211 /* 1212 * The embedded PCIe to PCI-X bridge (EPB) 1213 * in the 5708 cannot address memory above 1214 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1215 */ 1216 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1217 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1218 else 1219 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1220 1221 /* 1222 * Find the base address for shared memory access. 1223 * Newer versions of bootcode use a signature and offset 1224 * while older versions use a fixed address. 1225 */ 1226 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1227 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1228 /* Multi-port devices use different offsets in shared memory. */ 1229 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1230 (pci_get_function(sc->bce_dev) << 2)); 1231 else 1232 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1233 1234 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1235 __FUNCTION__, sc->bce_shmem_base); 1236 1237 /* Fetch the bootcode revision. */ 1238 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1239 for (int i = 0, j = 0; i < 3; i++) { 1240 u8 num; 1241 1242 num = (u8) (val >> (24 - (i * 8))); 1243 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1244 if (num >= k || !skip0 || k == 1) { 1245 sc->bce_bc_ver[j++] = (num / k) + '0'; 1246 skip0 = 0; 1247 } 1248 } 1249 1250 if (i != 2) 1251 sc->bce_bc_ver[j++] = '.'; 1252 } 1253 1254 /* Check if any management firwmare is enabled. */ 1255 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1256 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1257 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1258 1259 /* Allow time for firmware to enter the running state. */ 1260 for (int i = 0; i < 30; i++) { 1261 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1262 if (val & BCE_CONDITION_MFW_RUN_MASK) 1263 break; 1264 DELAY(10000); 1265 } 1266 1267 /* Check if management firmware is running. */ 1268 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1269 val &= BCE_CONDITION_MFW_RUN_MASK; 1270 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1271 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1272 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1273 int i = 0; 1274 1275 /* Read the management firmware version string. */ 1276 for (int j = 0; j < 3; j++) { 1277 val = bce_reg_rd_ind(sc, addr + j * 4); 1278 val = bswap32(val); 1279 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1280 i += 4; 1281 } 1282 } else { 1283 /* May cause firmware synchronization timeouts. */ 1284 BCE_PRINTF("%s(%d): Management firmware enabled " 1285 "but not running!\n", __FILE__, __LINE__); 1286 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1287 1288 /* ToDo: Any action the driver should take? */ 1289 } 1290 } 1291 1292 /* Get PCI bus information (speed and type). */ 1293 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1294 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1295 u32 clkreg; 1296 1297 sc->bce_flags |= BCE_PCIX_FLAG; 1298 1299 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1300 1301 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1302 switch (clkreg) { 1303 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1304 sc->bus_speed_mhz = 133; 1305 break; 1306 1307 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1308 sc->bus_speed_mhz = 100; 1309 break; 1310 1311 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1312 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1313 sc->bus_speed_mhz = 66; 1314 break; 1315 1316 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1317 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1318 sc->bus_speed_mhz = 50; 1319 break; 1320 1321 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1322 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1323 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1324 sc->bus_speed_mhz = 33; 1325 break; 1326 } 1327 } else { 1328 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1329 sc->bus_speed_mhz = 66; 1330 else 1331 sc->bus_speed_mhz = 33; 1332 } 1333 1334 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1335 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1336 1337 /* Find the media type for the adapter. */ 1338 bce_get_media(sc); 1339 1340 /* Reset controller and announce to bootcode that driver is present. */ 1341 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1342 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1343 __FILE__, __LINE__); 1344 rc = ENXIO; 1345 goto bce_attach_fail; 1346 } 1347 1348 /* Initialize the controller. */ 1349 if (bce_chipinit(sc)) { 1350 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1351 __FILE__, __LINE__); 1352 rc = ENXIO; 1353 goto bce_attach_fail; 1354 } 1355 1356 /* Perform NVRAM test. */ 1357 if (bce_nvram_test(sc)) { 1358 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1359 __FILE__, __LINE__); 1360 rc = ENXIO; 1361 goto bce_attach_fail; 1362 } 1363 1364 /* Fetch the permanent Ethernet MAC address. */ 1365 bce_get_mac_addr(sc); 1366 1367 /* Update statistics once every second. */ 1368 sc->bce_stats_ticks = 1000000 & 0xffff00; 1369 1370 /* Store data needed by PHY driver for backplane applications */ 1371 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1372 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1373 1374 /* Allocate DMA memory resources. */ 1375 if (bce_dma_alloc(dev)) { 1376 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1377 __FILE__, __LINE__); 1378 rc = ENXIO; 1379 goto bce_attach_fail; 1380 } 1381 1382 /* Allocate an ifnet structure. */ 1383 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1384 if (ifp == NULL) { 1385 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1386 __FILE__, __LINE__); 1387 rc = ENXIO; 1388 goto bce_attach_fail; 1389 } 1390 1391 /* Initialize the ifnet interface. */ 1392 ifp->if_softc = sc; 1393 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1394 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1395 ifp->if_ioctl = bce_ioctl; 1396 ifp->if_start = bce_start; 1397 ifp->if_get_counter = bce_get_counter; 1398 ifp->if_init = bce_init; 1399 ifp->if_mtu = ETHERMTU; 1400 1401 if (bce_tso_enable) { 1402 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1403 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1404 IFCAP_VLAN_HWTSO; 1405 } else { 1406 ifp->if_hwassist = BCE_IF_HWASSIST; 1407 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1408 } 1409 1410 #if __FreeBSD_version >= 800505 1411 /* 1412 * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version 1413 * so it's approximate value. 1414 */ 1415 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1416 ifp->if_capabilities |= IFCAP_LINKSTATE; 1417 #endif 1418 1419 ifp->if_capenable = ifp->if_capabilities; 1420 1421 /* 1422 * Assume standard mbuf sizes for buffer allocation. 1423 * This may change later if the MTU size is set to 1424 * something other than 1500. 1425 */ 1426 bce_get_rx_buffer_sizes(sc, 1427 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1428 1429 /* Recalculate our buffer allocation sizes. */ 1430 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1431 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1432 IFQ_SET_READY(&ifp->if_snd); 1433 1434 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1435 ifp->if_baudrate = IF_Mbps(2500ULL); 1436 else 1437 ifp->if_baudrate = IF_Mbps(1000); 1438 1439 /* Handle any special PHY initialization for SerDes PHYs. */ 1440 bce_init_media(sc); 1441 1442 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1443 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1444 bce_ifmedia_sts); 1445 /* 1446 * We can't manually override remote PHY's link and assume 1447 * PHY port configuration(Fiber or TP) is not changed after 1448 * device attach. This may not be correct though. 1449 */ 1450 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1451 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1452 ifmedia_add(&sc->bce_ifmedia, 1453 IFM_ETHER | IFM_2500_SX, 0, NULL); 1454 ifmedia_add(&sc->bce_ifmedia, 1455 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1456 } 1457 ifmedia_add(&sc->bce_ifmedia, 1458 IFM_ETHER | IFM_1000_SX, 0, NULL); 1459 ifmedia_add(&sc->bce_ifmedia, 1460 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1461 } else { 1462 ifmedia_add(&sc->bce_ifmedia, 1463 IFM_ETHER | IFM_10_T, 0, NULL); 1464 ifmedia_add(&sc->bce_ifmedia, 1465 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1466 ifmedia_add(&sc->bce_ifmedia, 1467 IFM_ETHER | IFM_100_TX, 0, NULL); 1468 ifmedia_add(&sc->bce_ifmedia, 1469 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1470 ifmedia_add(&sc->bce_ifmedia, 1471 IFM_ETHER | IFM_1000_T, 0, NULL); 1472 ifmedia_add(&sc->bce_ifmedia, 1473 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1474 } 1475 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1476 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1477 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1478 } else { 1479 /* MII child bus by attaching the PHY. */ 1480 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1481 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1482 MII_OFFSET_ANY, MIIF_DOPAUSE); 1483 if (rc != 0) { 1484 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1485 __LINE__); 1486 goto bce_attach_fail; 1487 } 1488 } 1489 1490 /* Attach to the Ethernet interface list. */ 1491 ether_ifattach(ifp, sc->eaddr); 1492 1493 #if __FreeBSD_version < 500000 1494 callout_init(&sc->bce_tick_callout); 1495 callout_init(&sc->bce_pulse_callout); 1496 #else 1497 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1498 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1499 #endif 1500 1501 /* Hookup IRQ last. */ 1502 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1503 NULL, bce_intr, sc, &sc->bce_intrhand); 1504 1505 if (rc) { 1506 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1507 __FILE__, __LINE__); 1508 bce_detach(dev); 1509 goto bce_attach_exit; 1510 } 1511 1512 /* 1513 * At this point we've acquired all the resources 1514 * we need to run so there's no turning back, we're 1515 * cleared for launch. 1516 */ 1517 1518 /* Print some important debugging info. */ 1519 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1520 1521 /* Add the supported sysctls to the kernel. */ 1522 bce_add_sysctls(sc); 1523 1524 BCE_LOCK(sc); 1525 1526 /* 1527 * The chip reset earlier notified the bootcode that 1528 * a driver is present. We now need to start our pulse 1529 * routine so that the bootcode is reminded that we're 1530 * still running. 1531 */ 1532 bce_pulse(sc); 1533 1534 bce_mgmt_init_locked(sc); 1535 BCE_UNLOCK(sc); 1536 1537 /* Finally, print some useful adapter info */ 1538 bce_print_adapter_info(sc); 1539 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1540 __FUNCTION__, sc); 1541 1542 goto bce_attach_exit; 1543 1544 bce_attach_fail: 1545 bce_release_resources(sc); 1546 1547 bce_attach_exit: 1548 1549 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1550 1551 return(rc); 1552 } 1553 1554 1555 /****************************************************************************/ 1556 /* Device detach function. */ 1557 /* */ 1558 /* Stops the controller, resets the controller, and releases resources. */ 1559 /* */ 1560 /* Returns: */ 1561 /* 0 on success, positive value on failure. */ 1562 /****************************************************************************/ 1563 static int 1564 bce_detach(device_t dev) 1565 { 1566 struct bce_softc *sc = device_get_softc(dev); 1567 struct ifnet *ifp; 1568 u32 msg; 1569 1570 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1571 1572 ifp = sc->bce_ifp; 1573 1574 /* Stop and reset the controller. */ 1575 BCE_LOCK(sc); 1576 1577 /* Stop the pulse so the bootcode can go to driver absent state. */ 1578 callout_stop(&sc->bce_pulse_callout); 1579 1580 bce_stop(sc); 1581 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1582 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1583 else 1584 msg = BCE_DRV_MSG_CODE_UNLOAD; 1585 bce_reset(sc, msg); 1586 1587 BCE_UNLOCK(sc); 1588 1589 ether_ifdetach(ifp); 1590 1591 /* If we have a child device on the MII bus remove it too. */ 1592 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1593 ifmedia_removeall(&sc->bce_ifmedia); 1594 else { 1595 bus_generic_detach(dev); 1596 device_delete_child(dev, sc->bce_miibus); 1597 } 1598 1599 /* Release all remaining resources. */ 1600 bce_release_resources(sc); 1601 1602 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1603 1604 return(0); 1605 } 1606 1607 1608 /****************************************************************************/ 1609 /* Device shutdown function. */ 1610 /* */ 1611 /* Stops and resets the controller. */ 1612 /* */ 1613 /* Returns: */ 1614 /* 0 on success, positive value on failure. */ 1615 /****************************************************************************/ 1616 static int 1617 bce_shutdown(device_t dev) 1618 { 1619 struct bce_softc *sc = device_get_softc(dev); 1620 u32 msg; 1621 1622 DBENTER(BCE_VERBOSE); 1623 1624 BCE_LOCK(sc); 1625 bce_stop(sc); 1626 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1627 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1628 else 1629 msg = BCE_DRV_MSG_CODE_UNLOAD; 1630 bce_reset(sc, msg); 1631 BCE_UNLOCK(sc); 1632 1633 DBEXIT(BCE_VERBOSE); 1634 1635 return (0); 1636 } 1637 1638 1639 #ifdef BCE_DEBUG 1640 /****************************************************************************/ 1641 /* Register read. */ 1642 /* */ 1643 /* Returns: */ 1644 /* The value of the register. */ 1645 /****************************************************************************/ 1646 static u32 1647 bce_reg_rd(struct bce_softc *sc, u32 offset) 1648 { 1649 u32 val = REG_RD(sc, offset); 1650 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1651 __FUNCTION__, offset, val); 1652 return val; 1653 } 1654 1655 1656 /****************************************************************************/ 1657 /* Register write (16 bit). */ 1658 /* */ 1659 /* Returns: */ 1660 /* Nothing. */ 1661 /****************************************************************************/ 1662 static void 1663 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1664 { 1665 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1666 __FUNCTION__, offset, val); 1667 REG_WR16(sc, offset, val); 1668 } 1669 1670 1671 /****************************************************************************/ 1672 /* Register write. */ 1673 /* */ 1674 /* Returns: */ 1675 /* Nothing. */ 1676 /****************************************************************************/ 1677 static void 1678 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1679 { 1680 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1681 __FUNCTION__, offset, val); 1682 REG_WR(sc, offset, val); 1683 } 1684 #endif 1685 1686 /****************************************************************************/ 1687 /* Indirect register read. */ 1688 /* */ 1689 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1690 /* configuration space. Using this mechanism avoids issues with posted */ 1691 /* reads but is much slower than memory-mapped I/O. */ 1692 /* */ 1693 /* Returns: */ 1694 /* The value of the register. */ 1695 /****************************************************************************/ 1696 static u32 1697 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1698 { 1699 device_t dev; 1700 dev = sc->bce_dev; 1701 1702 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1703 #ifdef BCE_DEBUG 1704 { 1705 u32 val; 1706 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1707 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1708 __FUNCTION__, offset, val); 1709 return val; 1710 } 1711 #else 1712 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1713 #endif 1714 } 1715 1716 1717 /****************************************************************************/ 1718 /* Indirect register write. */ 1719 /* */ 1720 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1721 /* configuration space. Using this mechanism avoids issues with posted */ 1722 /* writes but is muchh slower than memory-mapped I/O. */ 1723 /* */ 1724 /* Returns: */ 1725 /* Nothing. */ 1726 /****************************************************************************/ 1727 static void 1728 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1729 { 1730 device_t dev; 1731 dev = sc->bce_dev; 1732 1733 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1734 __FUNCTION__, offset, val); 1735 1736 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1737 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1738 } 1739 1740 1741 /****************************************************************************/ 1742 /* Shared memory write. */ 1743 /* */ 1744 /* Writes NetXtreme II shared memory region. */ 1745 /* */ 1746 /* Returns: */ 1747 /* Nothing. */ 1748 /****************************************************************************/ 1749 static void 1750 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1751 { 1752 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1753 "0x%08X\n", __FUNCTION__, val, offset); 1754 1755 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1756 } 1757 1758 1759 /****************************************************************************/ 1760 /* Shared memory read. */ 1761 /* */ 1762 /* Reads NetXtreme II shared memory region. */ 1763 /* */ 1764 /* Returns: */ 1765 /* The 32 bit value read. */ 1766 /****************************************************************************/ 1767 static u32 1768 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1769 { 1770 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1771 1772 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1773 "0x%08X\n", __FUNCTION__, val, offset); 1774 1775 return val; 1776 } 1777 1778 1779 #ifdef BCE_DEBUG 1780 /****************************************************************************/ 1781 /* Context memory read. */ 1782 /* */ 1783 /* The NetXtreme II controller uses context memory to track connection */ 1784 /* information for L2 and higher network protocols. */ 1785 /* */ 1786 /* Returns: */ 1787 /* The requested 32 bit value of context memory. */ 1788 /****************************************************************************/ 1789 static u32 1790 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1791 { 1792 u32 idx, offset, retry_cnt = 5, val; 1793 1794 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1795 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1796 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1797 1798 offset = ctx_offset + cid_addr; 1799 1800 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1801 1802 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1803 1804 for (idx = 0; idx < retry_cnt; idx++) { 1805 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1806 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1807 break; 1808 DELAY(5); 1809 } 1810 1811 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1812 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1813 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1814 __FILE__, __LINE__, cid_addr, ctx_offset); 1815 1816 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1817 } else { 1818 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1819 val = REG_RD(sc, BCE_CTX_DATA); 1820 } 1821 1822 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1823 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1824 1825 return(val); 1826 } 1827 #endif 1828 1829 1830 /****************************************************************************/ 1831 /* Context memory write. */ 1832 /* */ 1833 /* The NetXtreme II controller uses context memory to track connection */ 1834 /* information for L2 and higher network protocols. */ 1835 /* */ 1836 /* Returns: */ 1837 /* Nothing. */ 1838 /****************************************************************************/ 1839 static void 1840 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1841 { 1842 u32 idx, offset = ctx_offset + cid_addr; 1843 u32 val, retry_cnt = 5; 1844 1845 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1846 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1847 1848 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1849 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1850 __FUNCTION__, cid_addr)); 1851 1852 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1853 1854 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1855 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1856 1857 for (idx = 0; idx < retry_cnt; idx++) { 1858 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1859 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1860 break; 1861 DELAY(5); 1862 } 1863 1864 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1865 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1866 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1867 __FILE__, __LINE__, cid_addr, ctx_offset); 1868 1869 } else { 1870 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1871 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1872 } 1873 } 1874 1875 1876 /****************************************************************************/ 1877 /* PHY register read. */ 1878 /* */ 1879 /* Implements register reads on the MII bus. */ 1880 /* */ 1881 /* Returns: */ 1882 /* The value of the register. */ 1883 /****************************************************************************/ 1884 static int 1885 bce_miibus_read_reg(device_t dev, int phy, int reg) 1886 { 1887 struct bce_softc *sc; 1888 u32 val; 1889 int i; 1890 1891 sc = device_get_softc(dev); 1892 1893 /* 1894 * The 5709S PHY is an IEEE Clause 45 PHY 1895 * with special mappings to work with IEEE 1896 * Clause 22 register accesses. 1897 */ 1898 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1899 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1900 reg += 0x10; 1901 } 1902 1903 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1904 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1905 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1906 1907 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1908 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1909 1910 DELAY(40); 1911 } 1912 1913 1914 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1915 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1916 BCE_EMAC_MDIO_COMM_START_BUSY; 1917 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1918 1919 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1920 DELAY(10); 1921 1922 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1923 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1924 DELAY(5); 1925 1926 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1927 val &= BCE_EMAC_MDIO_COMM_DATA; 1928 1929 break; 1930 } 1931 } 1932 1933 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1934 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1935 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1936 val = 0x0; 1937 } else { 1938 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1939 } 1940 1941 1942 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1943 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1944 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1945 1946 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1947 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1948 1949 DELAY(40); 1950 } 1951 1952 DB_PRINT_PHY_REG(reg, val); 1953 return (val & 0xffff); 1954 } 1955 1956 1957 /****************************************************************************/ 1958 /* PHY register write. */ 1959 /* */ 1960 /* Implements register writes on the MII bus. */ 1961 /* */ 1962 /* Returns: */ 1963 /* The value of the register. */ 1964 /****************************************************************************/ 1965 static int 1966 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1967 { 1968 struct bce_softc *sc; 1969 u32 val1; 1970 int i; 1971 1972 sc = device_get_softc(dev); 1973 1974 DB_PRINT_PHY_REG(reg, val); 1975 1976 /* 1977 * The 5709S PHY is an IEEE Clause 45 PHY 1978 * with special mappings to work with IEEE 1979 * Clause 22 register accesses. 1980 */ 1981 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1982 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1983 reg += 0x10; 1984 } 1985 1986 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1987 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1988 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1989 1990 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1991 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1992 1993 DELAY(40); 1994 } 1995 1996 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1997 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1998 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1999 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 2000 2001 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 2002 DELAY(10); 2003 2004 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 2005 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 2006 DELAY(5); 2007 break; 2008 } 2009 } 2010 2011 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 2012 BCE_PRINTF("%s(%d): PHY write timeout!\n", 2013 __FILE__, __LINE__); 2014 2015 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 2016 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 2017 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 2018 2019 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 2020 REG_RD(sc, BCE_EMAC_MDIO_MODE); 2021 2022 DELAY(40); 2023 } 2024 2025 return 0; 2026 } 2027 2028 2029 /****************************************************************************/ 2030 /* MII bus status change. */ 2031 /* */ 2032 /* Called by the MII bus driver when the PHY establishes link to set the */ 2033 /* MAC interface registers. */ 2034 /* */ 2035 /* Returns: */ 2036 /* Nothing. */ 2037 /****************************************************************************/ 2038 static void 2039 bce_miibus_statchg(device_t dev) 2040 { 2041 struct bce_softc *sc; 2042 struct mii_data *mii; 2043 struct ifmediareq ifmr; 2044 int media_active, media_status, val; 2045 2046 sc = device_get_softc(dev); 2047 2048 DBENTER(BCE_VERBOSE_PHY); 2049 2050 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2051 bzero(&ifmr, sizeof(ifmr)); 2052 bce_ifmedia_sts_rphy(sc, &ifmr); 2053 media_active = ifmr.ifm_active; 2054 media_status = ifmr.ifm_status; 2055 } else { 2056 mii = device_get_softc(sc->bce_miibus); 2057 media_active = mii->mii_media_active; 2058 media_status = mii->mii_media_status; 2059 } 2060 2061 /* Ignore invalid media status. */ 2062 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2063 (IFM_ACTIVE | IFM_AVALID)) 2064 goto bce_miibus_statchg_exit; 2065 2066 val = REG_RD(sc, BCE_EMAC_MODE); 2067 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2068 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2069 BCE_EMAC_MODE_25G); 2070 2071 /* Set MII or GMII interface based on the PHY speed. */ 2072 switch (IFM_SUBTYPE(media_active)) { 2073 case IFM_10_T: 2074 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2075 DBPRINT(sc, BCE_INFO_PHY, 2076 "Enabling 10Mb interface.\n"); 2077 val |= BCE_EMAC_MODE_PORT_MII_10; 2078 break; 2079 } 2080 /* fall-through */ 2081 case IFM_100_TX: 2082 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2083 val |= BCE_EMAC_MODE_PORT_MII; 2084 break; 2085 case IFM_2500_SX: 2086 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2087 val |= BCE_EMAC_MODE_25G; 2088 /* fall-through */ 2089 case IFM_1000_T: 2090 case IFM_1000_SX: 2091 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2092 val |= BCE_EMAC_MODE_PORT_GMII; 2093 break; 2094 default: 2095 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2096 "default GMII interface.\n"); 2097 val |= BCE_EMAC_MODE_PORT_GMII; 2098 } 2099 2100 /* Set half or full duplex based on PHY settings. */ 2101 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2102 DBPRINT(sc, BCE_INFO_PHY, 2103 "Setting Half-Duplex interface.\n"); 2104 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2105 } else 2106 DBPRINT(sc, BCE_INFO_PHY, 2107 "Setting Full-Duplex interface.\n"); 2108 2109 REG_WR(sc, BCE_EMAC_MODE, val); 2110 2111 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2112 DBPRINT(sc, BCE_INFO_PHY, 2113 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2114 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2115 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL; 2116 } else { 2117 DBPRINT(sc, BCE_INFO_PHY, 2118 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2119 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2120 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL; 2121 } 2122 2123 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2124 DBPRINT(sc, BCE_INFO_PHY, 2125 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2126 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2127 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2128 } else { 2129 DBPRINT(sc, BCE_INFO_PHY, 2130 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2131 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2132 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2133 } 2134 2135 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2136 2137 bce_miibus_statchg_exit: 2138 DBEXIT(BCE_VERBOSE_PHY); 2139 } 2140 2141 2142 /****************************************************************************/ 2143 /* Acquire NVRAM lock. */ 2144 /* */ 2145 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2146 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2147 /* for use by the driver. */ 2148 /* */ 2149 /* Returns: */ 2150 /* 0 on success, positive value on failure. */ 2151 /****************************************************************************/ 2152 static int 2153 bce_acquire_nvram_lock(struct bce_softc *sc) 2154 { 2155 u32 val; 2156 int j, rc = 0; 2157 2158 DBENTER(BCE_VERBOSE_NVRAM); 2159 2160 /* Request access to the flash interface. */ 2161 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2162 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2163 val = REG_RD(sc, BCE_NVM_SW_ARB); 2164 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2165 break; 2166 2167 DELAY(5); 2168 } 2169 2170 if (j >= NVRAM_TIMEOUT_COUNT) { 2171 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2172 rc = EBUSY; 2173 } 2174 2175 DBEXIT(BCE_VERBOSE_NVRAM); 2176 return (rc); 2177 } 2178 2179 2180 /****************************************************************************/ 2181 /* Release NVRAM lock. */ 2182 /* */ 2183 /* When the caller is finished accessing NVRAM the lock must be released. */ 2184 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2185 /* for use by the driver. */ 2186 /* */ 2187 /* Returns: */ 2188 /* 0 on success, positive value on failure. */ 2189 /****************************************************************************/ 2190 static int 2191 bce_release_nvram_lock(struct bce_softc *sc) 2192 { 2193 u32 val; 2194 int j, rc = 0; 2195 2196 DBENTER(BCE_VERBOSE_NVRAM); 2197 2198 /* 2199 * Relinquish nvram interface. 2200 */ 2201 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2202 2203 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2204 val = REG_RD(sc, BCE_NVM_SW_ARB); 2205 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2206 break; 2207 2208 DELAY(5); 2209 } 2210 2211 if (j >= NVRAM_TIMEOUT_COUNT) { 2212 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2213 rc = EBUSY; 2214 } 2215 2216 DBEXIT(BCE_VERBOSE_NVRAM); 2217 return (rc); 2218 } 2219 2220 2221 #ifdef BCE_NVRAM_WRITE_SUPPORT 2222 /****************************************************************************/ 2223 /* Enable NVRAM write access. */ 2224 /* */ 2225 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2226 /* */ 2227 /* Returns: */ 2228 /* 0 on success, positive value on failure. */ 2229 /****************************************************************************/ 2230 static int 2231 bce_enable_nvram_write(struct bce_softc *sc) 2232 { 2233 u32 val; 2234 int rc = 0; 2235 2236 DBENTER(BCE_VERBOSE_NVRAM); 2237 2238 val = REG_RD(sc, BCE_MISC_CFG); 2239 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2240 2241 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2242 int j; 2243 2244 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2245 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2246 2247 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2248 DELAY(5); 2249 2250 val = REG_RD(sc, BCE_NVM_COMMAND); 2251 if (val & BCE_NVM_COMMAND_DONE) 2252 break; 2253 } 2254 2255 if (j >= NVRAM_TIMEOUT_COUNT) { 2256 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2257 rc = EBUSY; 2258 } 2259 } 2260 2261 DBENTER(BCE_VERBOSE_NVRAM); 2262 return (rc); 2263 } 2264 2265 2266 /****************************************************************************/ 2267 /* Disable NVRAM write access. */ 2268 /* */ 2269 /* When the caller is finished writing to NVRAM write access must be */ 2270 /* disabled. */ 2271 /* */ 2272 /* Returns: */ 2273 /* Nothing. */ 2274 /****************************************************************************/ 2275 static void 2276 bce_disable_nvram_write(struct bce_softc *sc) 2277 { 2278 u32 val; 2279 2280 DBENTER(BCE_VERBOSE_NVRAM); 2281 2282 val = REG_RD(sc, BCE_MISC_CFG); 2283 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2284 2285 DBEXIT(BCE_VERBOSE_NVRAM); 2286 2287 } 2288 #endif 2289 2290 2291 /****************************************************************************/ 2292 /* Enable NVRAM access. */ 2293 /* */ 2294 /* Before accessing NVRAM for read or write operations the caller must */ 2295 /* enabled NVRAM access. */ 2296 /* */ 2297 /* Returns: */ 2298 /* Nothing. */ 2299 /****************************************************************************/ 2300 static void 2301 bce_enable_nvram_access(struct bce_softc *sc) 2302 { 2303 u32 val; 2304 2305 DBENTER(BCE_VERBOSE_NVRAM); 2306 2307 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2308 /* Enable both bits, even on read. */ 2309 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2310 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2311 2312 DBEXIT(BCE_VERBOSE_NVRAM); 2313 } 2314 2315 2316 /****************************************************************************/ 2317 /* Disable NVRAM access. */ 2318 /* */ 2319 /* When the caller is finished accessing NVRAM access must be disabled. */ 2320 /* */ 2321 /* Returns: */ 2322 /* Nothing. */ 2323 /****************************************************************************/ 2324 static void 2325 bce_disable_nvram_access(struct bce_softc *sc) 2326 { 2327 u32 val; 2328 2329 DBENTER(BCE_VERBOSE_NVRAM); 2330 2331 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2332 2333 /* Disable both bits, even after read. */ 2334 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2335 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2336 2337 DBEXIT(BCE_VERBOSE_NVRAM); 2338 } 2339 2340 2341 #ifdef BCE_NVRAM_WRITE_SUPPORT 2342 /****************************************************************************/ 2343 /* Erase NVRAM page before writing. */ 2344 /* */ 2345 /* Non-buffered flash parts require that a page be erased before it is */ 2346 /* written. */ 2347 /* */ 2348 /* Returns: */ 2349 /* 0 on success, positive value on failure. */ 2350 /****************************************************************************/ 2351 static int 2352 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2353 { 2354 u32 cmd; 2355 int j, rc = 0; 2356 2357 DBENTER(BCE_VERBOSE_NVRAM); 2358 2359 /* Buffered flash doesn't require an erase. */ 2360 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2361 goto bce_nvram_erase_page_exit; 2362 2363 /* Build an erase command. */ 2364 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2365 BCE_NVM_COMMAND_DOIT; 2366 2367 /* 2368 * Clear the DONE bit separately, set the NVRAM address to erase, 2369 * and issue the erase command. 2370 */ 2371 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2372 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2373 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2374 2375 /* Wait for completion. */ 2376 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2377 u32 val; 2378 2379 DELAY(5); 2380 2381 val = REG_RD(sc, BCE_NVM_COMMAND); 2382 if (val & BCE_NVM_COMMAND_DONE) 2383 break; 2384 } 2385 2386 if (j >= NVRAM_TIMEOUT_COUNT) { 2387 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2388 rc = EBUSY; 2389 } 2390 2391 bce_nvram_erase_page_exit: 2392 DBEXIT(BCE_VERBOSE_NVRAM); 2393 return (rc); 2394 } 2395 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2396 2397 2398 /****************************************************************************/ 2399 /* Read a dword (32 bits) from NVRAM. */ 2400 /* */ 2401 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2402 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2403 /* */ 2404 /* Returns: */ 2405 /* 0 on success and the 32 bit value read, positive value on failure. */ 2406 /****************************************************************************/ 2407 static int 2408 bce_nvram_read_dword(struct bce_softc *sc, 2409 u32 offset, u8 *ret_val, u32 cmd_flags) 2410 { 2411 u32 cmd; 2412 int i, rc = 0; 2413 2414 DBENTER(BCE_EXTREME_NVRAM); 2415 2416 /* Build the command word. */ 2417 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2418 2419 /* Calculate the offset for buffered flash if translation is used. */ 2420 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2421 offset = ((offset / sc->bce_flash_info->page_size) << 2422 sc->bce_flash_info->page_bits) + 2423 (offset % sc->bce_flash_info->page_size); 2424 } 2425 2426 /* 2427 * Clear the DONE bit separately, set the address to read, 2428 * and issue the read. 2429 */ 2430 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2431 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2432 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2433 2434 /* Wait for completion. */ 2435 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2436 u32 val; 2437 2438 DELAY(5); 2439 2440 val = REG_RD(sc, BCE_NVM_COMMAND); 2441 if (val & BCE_NVM_COMMAND_DONE) { 2442 val = REG_RD(sc, BCE_NVM_READ); 2443 2444 val = bce_be32toh(val); 2445 memcpy(ret_val, &val, 4); 2446 break; 2447 } 2448 } 2449 2450 /* Check for errors. */ 2451 if (i >= NVRAM_TIMEOUT_COUNT) { 2452 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2453 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2454 rc = EBUSY; 2455 } 2456 2457 DBEXIT(BCE_EXTREME_NVRAM); 2458 return(rc); 2459 } 2460 2461 2462 #ifdef BCE_NVRAM_WRITE_SUPPORT 2463 /****************************************************************************/ 2464 /* Write a dword (32 bits) to NVRAM. */ 2465 /* */ 2466 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2467 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2468 /* enabled NVRAM write access. */ 2469 /* */ 2470 /* Returns: */ 2471 /* 0 on success, positive value on failure. */ 2472 /****************************************************************************/ 2473 static int 2474 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2475 u32 cmd_flags) 2476 { 2477 u32 cmd, val32; 2478 int j, rc = 0; 2479 2480 DBENTER(BCE_VERBOSE_NVRAM); 2481 2482 /* Build the command word. */ 2483 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2484 2485 /* Calculate the offset for buffered flash if translation is used. */ 2486 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2487 offset = ((offset / sc->bce_flash_info->page_size) << 2488 sc->bce_flash_info->page_bits) + 2489 (offset % sc->bce_flash_info->page_size); 2490 } 2491 2492 /* 2493 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2494 * set the NVRAM address to write, and issue the write command 2495 */ 2496 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2497 memcpy(&val32, val, 4); 2498 val32 = htobe32(val32); 2499 REG_WR(sc, BCE_NVM_WRITE, val32); 2500 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2501 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2502 2503 /* Wait for completion. */ 2504 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2505 DELAY(5); 2506 2507 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2508 break; 2509 } 2510 if (j >= NVRAM_TIMEOUT_COUNT) { 2511 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2512 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2513 rc = EBUSY; 2514 } 2515 2516 DBEXIT(BCE_VERBOSE_NVRAM); 2517 return (rc); 2518 } 2519 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2520 2521 2522 /****************************************************************************/ 2523 /* Initialize NVRAM access. */ 2524 /* */ 2525 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2526 /* access that device. */ 2527 /* */ 2528 /* Returns: */ 2529 /* 0 on success, positive value on failure. */ 2530 /****************************************************************************/ 2531 static int 2532 bce_init_nvram(struct bce_softc *sc) 2533 { 2534 u32 val; 2535 int j, entry_count, rc = 0; 2536 const struct flash_spec *flash; 2537 2538 DBENTER(BCE_VERBOSE_NVRAM); 2539 2540 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2541 sc->bce_flash_info = &flash_5709; 2542 goto bce_init_nvram_get_flash_size; 2543 } 2544 2545 /* Determine the selected interface. */ 2546 val = REG_RD(sc, BCE_NVM_CFG1); 2547 2548 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2549 2550 /* 2551 * Flash reconfiguration is required to support additional 2552 * NVRAM devices not directly supported in hardware. 2553 * Check if the flash interface was reconfigured 2554 * by the bootcode. 2555 */ 2556 2557 if (val & 0x40000000) { 2558 /* Flash interface reconfigured by bootcode. */ 2559 2560 DBPRINT(sc,BCE_INFO_LOAD, 2561 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2562 2563 for (j = 0, flash = &flash_table[0]; j < entry_count; 2564 j++, flash++) { 2565 if ((val & FLASH_BACKUP_STRAP_MASK) == 2566 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2567 sc->bce_flash_info = flash; 2568 break; 2569 } 2570 } 2571 } else { 2572 /* Flash interface not yet reconfigured. */ 2573 u32 mask; 2574 2575 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2576 __FUNCTION__); 2577 2578 if (val & (1 << 23)) 2579 mask = FLASH_BACKUP_STRAP_MASK; 2580 else 2581 mask = FLASH_STRAP_MASK; 2582 2583 /* Look for the matching NVRAM device configuration data. */ 2584 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2585 2586 /* Check if the device matches any of the known devices. */ 2587 if ((val & mask) == (flash->strapping & mask)) { 2588 /* Found a device match. */ 2589 sc->bce_flash_info = flash; 2590 2591 /* Request access to the flash interface. */ 2592 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2593 return rc; 2594 2595 /* Reconfigure the flash interface. */ 2596 bce_enable_nvram_access(sc); 2597 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2598 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2599 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2600 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2601 bce_disable_nvram_access(sc); 2602 bce_release_nvram_lock(sc); 2603 2604 break; 2605 } 2606 } 2607 } 2608 2609 /* Check if a matching device was found. */ 2610 if (j == entry_count) { 2611 sc->bce_flash_info = NULL; 2612 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2613 __FILE__, __LINE__); 2614 DBEXIT(BCE_VERBOSE_NVRAM); 2615 return (ENODEV); 2616 } 2617 2618 bce_init_nvram_get_flash_size: 2619 /* Write the flash config data to the shared memory interface. */ 2620 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2621 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2622 if (val) 2623 sc->bce_flash_size = val; 2624 else 2625 sc->bce_flash_size = sc->bce_flash_info->total_size; 2626 2627 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2628 __FUNCTION__, sc->bce_flash_info->name, 2629 sc->bce_flash_info->total_size); 2630 2631 DBEXIT(BCE_VERBOSE_NVRAM); 2632 return rc; 2633 } 2634 2635 2636 /****************************************************************************/ 2637 /* Read an arbitrary range of data from NVRAM. */ 2638 /* */ 2639 /* Prepares the NVRAM interface for access and reads the requested data */ 2640 /* into the supplied buffer. */ 2641 /* */ 2642 /* Returns: */ 2643 /* 0 on success and the data read, positive value on failure. */ 2644 /****************************************************************************/ 2645 static int 2646 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2647 int buf_size) 2648 { 2649 int rc = 0; 2650 u32 cmd_flags, offset32, len32, extra; 2651 2652 DBENTER(BCE_VERBOSE_NVRAM); 2653 2654 if (buf_size == 0) 2655 goto bce_nvram_read_exit; 2656 2657 /* Request access to the flash interface. */ 2658 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2659 goto bce_nvram_read_exit; 2660 2661 /* Enable access to flash interface */ 2662 bce_enable_nvram_access(sc); 2663 2664 len32 = buf_size; 2665 offset32 = offset; 2666 extra = 0; 2667 2668 cmd_flags = 0; 2669 2670 if (offset32 & 3) { 2671 u8 buf[4]; 2672 u32 pre_len; 2673 2674 offset32 &= ~3; 2675 pre_len = 4 - (offset & 3); 2676 2677 if (pre_len >= len32) { 2678 pre_len = len32; 2679 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2680 } 2681 else { 2682 cmd_flags = BCE_NVM_COMMAND_FIRST; 2683 } 2684 2685 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2686 2687 if (rc) 2688 return rc; 2689 2690 memcpy(ret_buf, buf + (offset & 3), pre_len); 2691 2692 offset32 += 4; 2693 ret_buf += pre_len; 2694 len32 -= pre_len; 2695 } 2696 2697 if (len32 & 3) { 2698 extra = 4 - (len32 & 3); 2699 len32 = (len32 + 4) & ~3; 2700 } 2701 2702 if (len32 == 4) { 2703 u8 buf[4]; 2704 2705 if (cmd_flags) 2706 cmd_flags = BCE_NVM_COMMAND_LAST; 2707 else 2708 cmd_flags = BCE_NVM_COMMAND_FIRST | 2709 BCE_NVM_COMMAND_LAST; 2710 2711 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2712 2713 memcpy(ret_buf, buf, 4 - extra); 2714 } 2715 else if (len32 > 0) { 2716 u8 buf[4]; 2717 2718 /* Read the first word. */ 2719 if (cmd_flags) 2720 cmd_flags = 0; 2721 else 2722 cmd_flags = BCE_NVM_COMMAND_FIRST; 2723 2724 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2725 2726 /* Advance to the next dword. */ 2727 offset32 += 4; 2728 ret_buf += 4; 2729 len32 -= 4; 2730 2731 while (len32 > 4 && rc == 0) { 2732 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2733 2734 /* Advance to the next dword. */ 2735 offset32 += 4; 2736 ret_buf += 4; 2737 len32 -= 4; 2738 } 2739 2740 if (rc) 2741 goto bce_nvram_read_locked_exit; 2742 2743 cmd_flags = BCE_NVM_COMMAND_LAST; 2744 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2745 2746 memcpy(ret_buf, buf, 4 - extra); 2747 } 2748 2749 bce_nvram_read_locked_exit: 2750 /* Disable access to flash interface and release the lock. */ 2751 bce_disable_nvram_access(sc); 2752 bce_release_nvram_lock(sc); 2753 2754 bce_nvram_read_exit: 2755 DBEXIT(BCE_VERBOSE_NVRAM); 2756 return rc; 2757 } 2758 2759 2760 #ifdef BCE_NVRAM_WRITE_SUPPORT 2761 /****************************************************************************/ 2762 /* Write an arbitrary range of data from NVRAM. */ 2763 /* */ 2764 /* Prepares the NVRAM interface for write access and writes the requested */ 2765 /* data from the supplied buffer. The caller is responsible for */ 2766 /* calculating any appropriate CRCs. */ 2767 /* */ 2768 /* Returns: */ 2769 /* 0 on success, positive value on failure. */ 2770 /****************************************************************************/ 2771 static int 2772 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2773 int buf_size) 2774 { 2775 u32 written, offset32, len32; 2776 u8 *buf, start[4], end[4]; 2777 int rc = 0; 2778 int align_start, align_end; 2779 2780 DBENTER(BCE_VERBOSE_NVRAM); 2781 2782 buf = data_buf; 2783 offset32 = offset; 2784 len32 = buf_size; 2785 align_start = align_end = 0; 2786 2787 if ((align_start = (offset32 & 3))) { 2788 offset32 &= ~3; 2789 len32 += align_start; 2790 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2791 goto bce_nvram_write_exit; 2792 } 2793 2794 if (len32 & 3) { 2795 if ((len32 > 4) || !align_start) { 2796 align_end = 4 - (len32 & 3); 2797 len32 += align_end; 2798 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2799 end, 4))) { 2800 goto bce_nvram_write_exit; 2801 } 2802 } 2803 } 2804 2805 if (align_start || align_end) { 2806 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2807 if (buf == NULL) { 2808 rc = ENOMEM; 2809 goto bce_nvram_write_exit; 2810 } 2811 2812 if (align_start) { 2813 memcpy(buf, start, 4); 2814 } 2815 2816 if (align_end) { 2817 memcpy(buf + len32 - 4, end, 4); 2818 } 2819 memcpy(buf + align_start, data_buf, buf_size); 2820 } 2821 2822 written = 0; 2823 while ((written < len32) && (rc == 0)) { 2824 u32 page_start, page_end, data_start, data_end; 2825 u32 addr, cmd_flags; 2826 int i; 2827 u8 flash_buffer[264]; 2828 2829 /* Find the page_start addr */ 2830 page_start = offset32 + written; 2831 page_start -= (page_start % sc->bce_flash_info->page_size); 2832 /* Find the page_end addr */ 2833 page_end = page_start + sc->bce_flash_info->page_size; 2834 /* Find the data_start addr */ 2835 data_start = (written == 0) ? offset32 : page_start; 2836 /* Find the data_end addr */ 2837 data_end = (page_end > offset32 + len32) ? 2838 (offset32 + len32) : page_end; 2839 2840 /* Request access to the flash interface. */ 2841 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2842 goto bce_nvram_write_exit; 2843 2844 /* Enable access to flash interface */ 2845 bce_enable_nvram_access(sc); 2846 2847 cmd_flags = BCE_NVM_COMMAND_FIRST; 2848 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2849 int j; 2850 2851 /* Read the whole page into the buffer 2852 * (non-buffer flash only) */ 2853 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2854 if (j == (sc->bce_flash_info->page_size - 4)) { 2855 cmd_flags |= BCE_NVM_COMMAND_LAST; 2856 } 2857 rc = bce_nvram_read_dword(sc, 2858 page_start + j, 2859 &flash_buffer[j], 2860 cmd_flags); 2861 2862 if (rc) 2863 goto bce_nvram_write_locked_exit; 2864 2865 cmd_flags = 0; 2866 } 2867 } 2868 2869 /* Enable writes to flash interface (unlock write-protect) */ 2870 if ((rc = bce_enable_nvram_write(sc)) != 0) 2871 goto bce_nvram_write_locked_exit; 2872 2873 /* Erase the page */ 2874 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2875 goto bce_nvram_write_locked_exit; 2876 2877 /* Re-enable the write again for the actual write */ 2878 bce_enable_nvram_write(sc); 2879 2880 /* Loop to write back the buffer data from page_start to 2881 * data_start */ 2882 i = 0; 2883 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2884 for (addr = page_start; addr < data_start; 2885 addr += 4, i += 4) { 2886 2887 rc = bce_nvram_write_dword(sc, addr, 2888 &flash_buffer[i], cmd_flags); 2889 2890 if (rc != 0) 2891 goto bce_nvram_write_locked_exit; 2892 2893 cmd_flags = 0; 2894 } 2895 } 2896 2897 /* Loop to write the new data from data_start to data_end */ 2898 for (addr = data_start; addr < data_end; addr += 4, i++) { 2899 if ((addr == page_end - 4) || 2900 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2901 (addr == data_end - 4))) { 2902 2903 cmd_flags |= BCE_NVM_COMMAND_LAST; 2904 } 2905 rc = bce_nvram_write_dword(sc, addr, buf, 2906 cmd_flags); 2907 2908 if (rc != 0) 2909 goto bce_nvram_write_locked_exit; 2910 2911 cmd_flags = 0; 2912 buf += 4; 2913 } 2914 2915 /* Loop to write back the buffer data from data_end 2916 * to page_end */ 2917 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2918 for (addr = data_end; addr < page_end; 2919 addr += 4, i += 4) { 2920 2921 if (addr == page_end-4) { 2922 cmd_flags = BCE_NVM_COMMAND_LAST; 2923 } 2924 rc = bce_nvram_write_dword(sc, addr, 2925 &flash_buffer[i], cmd_flags); 2926 2927 if (rc != 0) 2928 goto bce_nvram_write_locked_exit; 2929 2930 cmd_flags = 0; 2931 } 2932 } 2933 2934 /* Disable writes to flash interface (lock write-protect) */ 2935 bce_disable_nvram_write(sc); 2936 2937 /* Disable access to flash interface */ 2938 bce_disable_nvram_access(sc); 2939 bce_release_nvram_lock(sc); 2940 2941 /* Increment written */ 2942 written += data_end - data_start; 2943 } 2944 2945 goto bce_nvram_write_exit; 2946 2947 bce_nvram_write_locked_exit: 2948 bce_disable_nvram_write(sc); 2949 bce_disable_nvram_access(sc); 2950 bce_release_nvram_lock(sc); 2951 2952 bce_nvram_write_exit: 2953 if (align_start || align_end) 2954 free(buf, M_DEVBUF); 2955 2956 DBEXIT(BCE_VERBOSE_NVRAM); 2957 return (rc); 2958 } 2959 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2960 2961 2962 /****************************************************************************/ 2963 /* Verifies that NVRAM is accessible and contains valid data. */ 2964 /* */ 2965 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2966 /* correct. */ 2967 /* */ 2968 /* Returns: */ 2969 /* 0 on success, positive value on failure. */ 2970 /****************************************************************************/ 2971 static int 2972 bce_nvram_test(struct bce_softc *sc) 2973 { 2974 u32 buf[BCE_NVRAM_SIZE / 4]; 2975 u8 *data = (u8 *) buf; 2976 int rc = 0; 2977 u32 magic, csum; 2978 2979 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2980 2981 /* 2982 * Check that the device NVRAM is valid by reading 2983 * the magic value at offset 0. 2984 */ 2985 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2986 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2987 __FILE__, __LINE__); 2988 goto bce_nvram_test_exit; 2989 } 2990 2991 /* 2992 * Verify that offset 0 of the NVRAM contains 2993 * a valid magic number. 2994 */ 2995 magic = bce_be32toh(buf[0]); 2996 if (magic != BCE_NVRAM_MAGIC) { 2997 rc = ENODEV; 2998 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2999 "Expected: 0x%08X, Found: 0x%08X\n", 3000 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 3001 goto bce_nvram_test_exit; 3002 } 3003 3004 /* 3005 * Verify that the device NVRAM includes valid 3006 * configuration data. 3007 */ 3008 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 3009 BCE_PRINTF("%s(%d): Unable to read manufacturing " 3010 "Information from NVRAM!\n", __FILE__, __LINE__); 3011 goto bce_nvram_test_exit; 3012 } 3013 3014 csum = ether_crc32_le(data, 0x100); 3015 if (csum != BCE_CRC32_RESIDUAL) { 3016 rc = ENODEV; 3017 BCE_PRINTF("%s(%d): Invalid manufacturing information " 3018 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 3019 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 3020 goto bce_nvram_test_exit; 3021 } 3022 3023 csum = ether_crc32_le(data + 0x100, 0x100); 3024 if (csum != BCE_CRC32_RESIDUAL) { 3025 rc = ENODEV; 3026 BCE_PRINTF("%s(%d): Invalid feature configuration " 3027 "information NVRAM CRC! Expected: 0x%08X, " 3028 "Found: 08%08X\n", __FILE__, __LINE__, 3029 BCE_CRC32_RESIDUAL, csum); 3030 } 3031 3032 bce_nvram_test_exit: 3033 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 3034 return rc; 3035 } 3036 3037 3038 /****************************************************************************/ 3039 /* Calculates the size of the buffers to allocate based on the MTU. */ 3040 /* */ 3041 /* Returns: */ 3042 /* Nothing. */ 3043 /****************************************************************************/ 3044 static void 3045 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 3046 { 3047 DBENTER(BCE_VERBOSE_LOAD); 3048 3049 /* Use a single allocation type when header splitting enabled. */ 3050 if (bce_hdr_split == TRUE) { 3051 sc->rx_bd_mbuf_alloc_size = MHLEN; 3052 /* Make sure offset is 16 byte aligned for hardware. */ 3053 sc->rx_bd_mbuf_align_pad = 3054 roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN); 3055 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 3056 sc->rx_bd_mbuf_align_pad; 3057 } else { 3058 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 3059 ETHER_CRC_LEN) > MCLBYTES) { 3060 /* Setup for jumbo RX buffer allocations. */ 3061 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 3062 sc->rx_bd_mbuf_align_pad = 3063 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3064 sc->rx_bd_mbuf_data_len = 3065 sc->rx_bd_mbuf_alloc_size - 3066 sc->rx_bd_mbuf_align_pad; 3067 } else { 3068 /* Setup for standard RX buffer allocations. */ 3069 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3070 sc->rx_bd_mbuf_align_pad = 3071 roundup2(MCLBYTES, 16) - MCLBYTES; 3072 sc->rx_bd_mbuf_data_len = 3073 sc->rx_bd_mbuf_alloc_size - 3074 sc->rx_bd_mbuf_align_pad; 3075 } 3076 } 3077 3078 // DBPRINT(sc, BCE_INFO_LOAD, 3079 DBPRINT(sc, BCE_WARN, 3080 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3081 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3082 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3083 sc->rx_bd_mbuf_align_pad); 3084 3085 DBEXIT(BCE_VERBOSE_LOAD); 3086 } 3087 3088 /****************************************************************************/ 3089 /* Identifies the current media type of the controller and sets the PHY */ 3090 /* address. */ 3091 /* */ 3092 /* Returns: */ 3093 /* Nothing. */ 3094 /****************************************************************************/ 3095 static void 3096 bce_get_media(struct bce_softc *sc) 3097 { 3098 u32 val; 3099 3100 DBENTER(BCE_VERBOSE_PHY); 3101 3102 /* Assume PHY address for copper controllers. */ 3103 sc->bce_phy_addr = 1; 3104 3105 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3106 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3107 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3108 u32 strap; 3109 3110 /* 3111 * The BCM5709S is software configurable 3112 * for Copper or SerDes operation. 3113 */ 3114 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3115 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3116 "for copper.\n"); 3117 goto bce_get_media_exit; 3118 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3119 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3120 "for dual media.\n"); 3121 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3122 goto bce_get_media_exit; 3123 } 3124 3125 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3126 strap = (val & 3127 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3128 else 3129 strap = (val & 3130 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3131 3132 if (pci_get_function(sc->bce_dev) == 0) { 3133 switch (strap) { 3134 case 0x4: 3135 case 0x5: 3136 case 0x6: 3137 DBPRINT(sc, BCE_INFO_LOAD, 3138 "BCM5709 s/w configured for SerDes.\n"); 3139 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3140 break; 3141 default: 3142 DBPRINT(sc, BCE_INFO_LOAD, 3143 "BCM5709 s/w configured for Copper.\n"); 3144 break; 3145 } 3146 } else { 3147 switch (strap) { 3148 case 0x1: 3149 case 0x2: 3150 case 0x4: 3151 DBPRINT(sc, BCE_INFO_LOAD, 3152 "BCM5709 s/w configured for SerDes.\n"); 3153 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3154 break; 3155 default: 3156 DBPRINT(sc, BCE_INFO_LOAD, 3157 "BCM5709 s/w configured for Copper.\n"); 3158 break; 3159 } 3160 } 3161 3162 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3163 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3164 3165 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3166 3167 sc->bce_flags |= BCE_NO_WOL_FLAG; 3168 3169 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3170 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3171 3172 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3173 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3174 sc->bce_phy_addr = 2; 3175 3176 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3177 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3178 sc->bce_phy_flags |= 3179 BCE_PHY_2_5G_CAPABLE_FLAG; 3180 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3181 "capable adapter\n"); 3182 } 3183 } 3184 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3185 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3186 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3187 3188 bce_get_media_exit: 3189 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3190 "Using PHY address %d.\n", sc->bce_phy_addr); 3191 3192 DBEXIT(BCE_VERBOSE_PHY); 3193 } 3194 3195 3196 /****************************************************************************/ 3197 /* Performs PHY initialization required before MII drivers access the */ 3198 /* device. */ 3199 /* */ 3200 /* Returns: */ 3201 /* Nothing. */ 3202 /****************************************************************************/ 3203 static void 3204 bce_init_media(struct bce_softc *sc) 3205 { 3206 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3207 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3208 /* 3209 * Configure 5709S/5716S PHYs to use traditional IEEE 3210 * Clause 22 method. Otherwise we have no way to attach 3211 * the PHY in mii(4) layer. PHY specific configuration 3212 * is done in mii layer. 3213 */ 3214 3215 /* Select auto-negotiation MMD of the PHY. */ 3216 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3217 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3218 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3219 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3220 3221 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3222 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3223 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3224 } 3225 } 3226 3227 3228 /****************************************************************************/ 3229 /* Free any DMA memory owned by the driver. */ 3230 /* */ 3231 /* Scans through each data structre that requires DMA memory and frees */ 3232 /* the memory if allocated. */ 3233 /* */ 3234 /* Returns: */ 3235 /* Nothing. */ 3236 /****************************************************************************/ 3237 static void 3238 bce_dma_free(struct bce_softc *sc) 3239 { 3240 int i; 3241 3242 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3243 3244 /* Free, unmap, and destroy the status block. */ 3245 if (sc->status_block_paddr != 0) { 3246 bus_dmamap_unload( 3247 sc->status_tag, 3248 sc->status_map); 3249 sc->status_block_paddr = 0; 3250 } 3251 3252 if (sc->status_block != NULL) { 3253 bus_dmamem_free( 3254 sc->status_tag, 3255 sc->status_block, 3256 sc->status_map); 3257 sc->status_block = NULL; 3258 } 3259 3260 if (sc->status_tag != NULL) { 3261 bus_dma_tag_destroy(sc->status_tag); 3262 sc->status_tag = NULL; 3263 } 3264 3265 3266 /* Free, unmap, and destroy the statistics block. */ 3267 if (sc->stats_block_paddr != 0) { 3268 bus_dmamap_unload( 3269 sc->stats_tag, 3270 sc->stats_map); 3271 sc->stats_block_paddr = 0; 3272 } 3273 3274 if (sc->stats_block != NULL) { 3275 bus_dmamem_free( 3276 sc->stats_tag, 3277 sc->stats_block, 3278 sc->stats_map); 3279 sc->stats_block = NULL; 3280 } 3281 3282 if (sc->stats_tag != NULL) { 3283 bus_dma_tag_destroy(sc->stats_tag); 3284 sc->stats_tag = NULL; 3285 } 3286 3287 3288 /* Free, unmap and destroy all context memory pages. */ 3289 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3290 for (i = 0; i < sc->ctx_pages; i++ ) { 3291 if (sc->ctx_paddr[i] != 0) { 3292 bus_dmamap_unload( 3293 sc->ctx_tag, 3294 sc->ctx_map[i]); 3295 sc->ctx_paddr[i] = 0; 3296 } 3297 3298 if (sc->ctx_block[i] != NULL) { 3299 bus_dmamem_free( 3300 sc->ctx_tag, 3301 sc->ctx_block[i], 3302 sc->ctx_map[i]); 3303 sc->ctx_block[i] = NULL; 3304 } 3305 } 3306 3307 /* Destroy the context memory tag. */ 3308 if (sc->ctx_tag != NULL) { 3309 bus_dma_tag_destroy(sc->ctx_tag); 3310 sc->ctx_tag = NULL; 3311 } 3312 } 3313 3314 3315 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3316 for (i = 0; i < sc->tx_pages; i++ ) { 3317 if (sc->tx_bd_chain_paddr[i] != 0) { 3318 bus_dmamap_unload( 3319 sc->tx_bd_chain_tag, 3320 sc->tx_bd_chain_map[i]); 3321 sc->tx_bd_chain_paddr[i] = 0; 3322 } 3323 3324 if (sc->tx_bd_chain[i] != NULL) { 3325 bus_dmamem_free( 3326 sc->tx_bd_chain_tag, 3327 sc->tx_bd_chain[i], 3328 sc->tx_bd_chain_map[i]); 3329 sc->tx_bd_chain[i] = NULL; 3330 } 3331 } 3332 3333 /* Destroy the TX buffer descriptor tag. */ 3334 if (sc->tx_bd_chain_tag != NULL) { 3335 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3336 sc->tx_bd_chain_tag = NULL; 3337 } 3338 3339 3340 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3341 for (i = 0; i < sc->rx_pages; i++ ) { 3342 if (sc->rx_bd_chain_paddr[i] != 0) { 3343 bus_dmamap_unload( 3344 sc->rx_bd_chain_tag, 3345 sc->rx_bd_chain_map[i]); 3346 sc->rx_bd_chain_paddr[i] = 0; 3347 } 3348 3349 if (sc->rx_bd_chain[i] != NULL) { 3350 bus_dmamem_free( 3351 sc->rx_bd_chain_tag, 3352 sc->rx_bd_chain[i], 3353 sc->rx_bd_chain_map[i]); 3354 sc->rx_bd_chain[i] = NULL; 3355 } 3356 } 3357 3358 /* Destroy the RX buffer descriptor tag. */ 3359 if (sc->rx_bd_chain_tag != NULL) { 3360 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3361 sc->rx_bd_chain_tag = NULL; 3362 } 3363 3364 3365 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3366 if (bce_hdr_split == TRUE) { 3367 for (i = 0; i < sc->pg_pages; i++ ) { 3368 if (sc->pg_bd_chain_paddr[i] != 0) { 3369 bus_dmamap_unload( 3370 sc->pg_bd_chain_tag, 3371 sc->pg_bd_chain_map[i]); 3372 sc->pg_bd_chain_paddr[i] = 0; 3373 } 3374 3375 if (sc->pg_bd_chain[i] != NULL) { 3376 bus_dmamem_free( 3377 sc->pg_bd_chain_tag, 3378 sc->pg_bd_chain[i], 3379 sc->pg_bd_chain_map[i]); 3380 sc->pg_bd_chain[i] = NULL; 3381 } 3382 } 3383 3384 /* Destroy the page buffer descriptor tag. */ 3385 if (sc->pg_bd_chain_tag != NULL) { 3386 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3387 sc->pg_bd_chain_tag = NULL; 3388 } 3389 } 3390 3391 3392 /* Unload and destroy the TX mbuf maps. */ 3393 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3394 if (sc->tx_mbuf_map[i] != NULL) { 3395 bus_dmamap_unload(sc->tx_mbuf_tag, 3396 sc->tx_mbuf_map[i]); 3397 bus_dmamap_destroy(sc->tx_mbuf_tag, 3398 sc->tx_mbuf_map[i]); 3399 sc->tx_mbuf_map[i] = NULL; 3400 } 3401 } 3402 3403 /* Destroy the TX mbuf tag. */ 3404 if (sc->tx_mbuf_tag != NULL) { 3405 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3406 sc->tx_mbuf_tag = NULL; 3407 } 3408 3409 /* Unload and destroy the RX mbuf maps. */ 3410 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3411 if (sc->rx_mbuf_map[i] != NULL) { 3412 bus_dmamap_unload(sc->rx_mbuf_tag, 3413 sc->rx_mbuf_map[i]); 3414 bus_dmamap_destroy(sc->rx_mbuf_tag, 3415 sc->rx_mbuf_map[i]); 3416 sc->rx_mbuf_map[i] = NULL; 3417 } 3418 } 3419 3420 /* Destroy the RX mbuf tag. */ 3421 if (sc->rx_mbuf_tag != NULL) { 3422 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3423 sc->rx_mbuf_tag = NULL; 3424 } 3425 3426 /* Unload and destroy the page mbuf maps. */ 3427 if (bce_hdr_split == TRUE) { 3428 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3429 if (sc->pg_mbuf_map[i] != NULL) { 3430 bus_dmamap_unload(sc->pg_mbuf_tag, 3431 sc->pg_mbuf_map[i]); 3432 bus_dmamap_destroy(sc->pg_mbuf_tag, 3433 sc->pg_mbuf_map[i]); 3434 sc->pg_mbuf_map[i] = NULL; 3435 } 3436 } 3437 3438 /* Destroy the page mbuf tag. */ 3439 if (sc->pg_mbuf_tag != NULL) { 3440 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3441 sc->pg_mbuf_tag = NULL; 3442 } 3443 } 3444 3445 /* Destroy the parent tag */ 3446 if (sc->parent_tag != NULL) { 3447 bus_dma_tag_destroy(sc->parent_tag); 3448 sc->parent_tag = NULL; 3449 } 3450 3451 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3452 } 3453 3454 3455 /****************************************************************************/ 3456 /* Get DMA memory from the OS. */ 3457 /* */ 3458 /* Validates that the OS has provided DMA buffers in response to a */ 3459 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3460 /* When the callback is used the OS will return 0 for the mapping function */ 3461 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3462 /* failures back to the caller. */ 3463 /* */ 3464 /* Returns: */ 3465 /* Nothing. */ 3466 /****************************************************************************/ 3467 static void 3468 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3469 { 3470 bus_addr_t *busaddr = arg; 3471 3472 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3473 __FUNCTION__, nseg)); 3474 /* Simulate a mapping failure. */ 3475 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3476 error = ENOMEM); 3477 3478 /* ToDo: How to increment debug sim_count variable here? */ 3479 3480 /* Check for an error and signal the caller that an error occurred. */ 3481 if (error) { 3482 *busaddr = 0; 3483 } else { 3484 *busaddr = segs->ds_addr; 3485 } 3486 } 3487 3488 3489 /****************************************************************************/ 3490 /* Allocate any DMA memory needed by the driver. */ 3491 /* */ 3492 /* Allocates DMA memory needed for the various global structures needed by */ 3493 /* hardware. */ 3494 /* */ 3495 /* Memory alignment requirements: */ 3496 /* +-----------------+----------+----------+----------+----------+ */ 3497 /* | | 5706 | 5708 | 5709 | 5716 | */ 3498 /* +-----------------+----------+----------+----------+----------+ */ 3499 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3500 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3501 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3502 /* |PG Buffers | none | none | none | none | */ 3503 /* |TX Buffers | none | none | none | none | */ 3504 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3505 /* |Context Memory | | | | | */ 3506 /* +-----------------+----------+----------+----------+----------+ */ 3507 /* */ 3508 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3509 /* */ 3510 /* Returns: */ 3511 /* 0 for success, positive value for failure. */ 3512 /****************************************************************************/ 3513 static int 3514 bce_dma_alloc(device_t dev) 3515 { 3516 struct bce_softc *sc; 3517 int i, error, rc = 0; 3518 bus_size_t max_size, max_seg_size; 3519 int max_segments; 3520 3521 sc = device_get_softc(dev); 3522 3523 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3524 3525 /* 3526 * Allocate the parent bus DMA tag appropriate for PCI. 3527 */ 3528 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3529 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3530 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3531 &sc->parent_tag)) { 3532 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3533 __FILE__, __LINE__); 3534 rc = ENOMEM; 3535 goto bce_dma_alloc_exit; 3536 } 3537 3538 /* 3539 * Create a DMA tag for the status block, allocate and clear the 3540 * memory, map the memory into DMA space, and fetch the physical 3541 * address of the block. 3542 */ 3543 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3544 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3545 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3546 0, NULL, NULL, &sc->status_tag)) { 3547 BCE_PRINTF("%s(%d): Could not allocate status block " 3548 "DMA tag!\n", __FILE__, __LINE__); 3549 rc = ENOMEM; 3550 goto bce_dma_alloc_exit; 3551 } 3552 3553 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3554 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3555 &sc->status_map)) { 3556 BCE_PRINTF("%s(%d): Could not allocate status block " 3557 "DMA memory!\n", __FILE__, __LINE__); 3558 rc = ENOMEM; 3559 goto bce_dma_alloc_exit; 3560 } 3561 3562 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3563 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3564 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3565 3566 if (error || sc->status_block_paddr == 0) { 3567 BCE_PRINTF("%s(%d): Could not map status block " 3568 "DMA memory!\n", __FILE__, __LINE__); 3569 rc = ENOMEM; 3570 goto bce_dma_alloc_exit; 3571 } 3572 3573 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3574 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3575 3576 /* 3577 * Create a DMA tag for the statistics block, allocate and clear the 3578 * memory, map the memory into DMA space, and fetch the physical 3579 * address of the block. 3580 */ 3581 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3582 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3583 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3584 0, NULL, NULL, &sc->stats_tag)) { 3585 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3586 "DMA tag!\n", __FILE__, __LINE__); 3587 rc = ENOMEM; 3588 goto bce_dma_alloc_exit; 3589 } 3590 3591 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3592 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3593 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3594 "DMA memory!\n", __FILE__, __LINE__); 3595 rc = ENOMEM; 3596 goto bce_dma_alloc_exit; 3597 } 3598 3599 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3600 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3601 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3602 3603 if (error || sc->stats_block_paddr == 0) { 3604 BCE_PRINTF("%s(%d): Could not map statistics block " 3605 "DMA memory!\n", __FILE__, __LINE__); 3606 rc = ENOMEM; 3607 goto bce_dma_alloc_exit; 3608 } 3609 3610 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3611 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3612 3613 /* BCM5709 uses host memory as cache for context memory. */ 3614 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3615 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3616 if (sc->ctx_pages == 0) 3617 sc->ctx_pages = 1; 3618 3619 DBRUNIF((sc->ctx_pages > 512), 3620 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3621 __FILE__, __LINE__, sc->ctx_pages)); 3622 3623 /* 3624 * Create a DMA tag for the context pages, 3625 * allocate and clear the memory, map the 3626 * memory into DMA space, and fetch the 3627 * physical address of the block. 3628 */ 3629 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3630 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3631 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3632 0, NULL, NULL, &sc->ctx_tag)) { 3633 BCE_PRINTF("%s(%d): Could not allocate CTX " 3634 "DMA tag!\n", __FILE__, __LINE__); 3635 rc = ENOMEM; 3636 goto bce_dma_alloc_exit; 3637 } 3638 3639 for (i = 0; i < sc->ctx_pages; i++) { 3640 3641 if(bus_dmamem_alloc(sc->ctx_tag, 3642 (void **)&sc->ctx_block[i], 3643 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3644 &sc->ctx_map[i])) { 3645 BCE_PRINTF("%s(%d): Could not allocate CTX " 3646 "DMA memory!\n", __FILE__, __LINE__); 3647 rc = ENOMEM; 3648 goto bce_dma_alloc_exit; 3649 } 3650 3651 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3652 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3653 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3654 3655 if (error || sc->ctx_paddr[i] == 0) { 3656 BCE_PRINTF("%s(%d): Could not map CTX " 3657 "DMA memory!\n", __FILE__, __LINE__); 3658 rc = ENOMEM; 3659 goto bce_dma_alloc_exit; 3660 } 3661 3662 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3663 "= 0x%jX\n", __FUNCTION__, i, 3664 (uintmax_t) sc->ctx_paddr[i]); 3665 } 3666 } 3667 3668 /* 3669 * Create a DMA tag for the TX buffer descriptor chain, 3670 * allocate and clear the memory, and fetch the 3671 * physical address of the block. 3672 */ 3673 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3674 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3675 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3676 NULL, NULL, &sc->tx_bd_chain_tag)) { 3677 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3678 "chain DMA tag!\n", __FILE__, __LINE__); 3679 rc = ENOMEM; 3680 goto bce_dma_alloc_exit; 3681 } 3682 3683 for (i = 0; i < sc->tx_pages; i++) { 3684 3685 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3686 (void **)&sc->tx_bd_chain[i], 3687 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3688 &sc->tx_bd_chain_map[i])) { 3689 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3690 "chain DMA memory!\n", __FILE__, __LINE__); 3691 rc = ENOMEM; 3692 goto bce_dma_alloc_exit; 3693 } 3694 3695 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3696 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3697 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3698 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3699 3700 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3701 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3702 "chain DMA memory!\n", __FILE__, __LINE__); 3703 rc = ENOMEM; 3704 goto bce_dma_alloc_exit; 3705 } 3706 3707 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3708 "0x%jX\n", __FUNCTION__, i, 3709 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3710 } 3711 3712 /* Check the required size before mapping to conserve resources. */ 3713 if (bce_tso_enable) { 3714 max_size = BCE_TSO_MAX_SIZE; 3715 max_segments = BCE_MAX_SEGMENTS; 3716 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3717 } else { 3718 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3719 max_segments = BCE_MAX_SEGMENTS; 3720 max_seg_size = MCLBYTES; 3721 } 3722 3723 /* Create a DMA tag for TX mbufs. */ 3724 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3725 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3726 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3727 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3728 __FILE__, __LINE__); 3729 rc = ENOMEM; 3730 goto bce_dma_alloc_exit; 3731 } 3732 3733 /* Create DMA maps for the TX mbufs clusters. */ 3734 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3735 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3736 &sc->tx_mbuf_map[i])) { 3737 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3738 "map!\n", __FILE__, __LINE__); 3739 rc = ENOMEM; 3740 goto bce_dma_alloc_exit; 3741 } 3742 } 3743 3744 /* 3745 * Create a DMA tag for the RX buffer descriptor chain, 3746 * allocate and clear the memory, and fetch the physical 3747 * address of the blocks. 3748 */ 3749 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3750 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3751 sc->max_bus_addr, NULL, NULL, 3752 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3753 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3754 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3755 "DMA tag!\n", __FILE__, __LINE__); 3756 rc = ENOMEM; 3757 goto bce_dma_alloc_exit; 3758 } 3759 3760 for (i = 0; i < sc->rx_pages; i++) { 3761 3762 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3763 (void **)&sc->rx_bd_chain[i], 3764 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3765 &sc->rx_bd_chain_map[i])) { 3766 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3767 "chain DMA memory!\n", __FILE__, __LINE__); 3768 rc = ENOMEM; 3769 goto bce_dma_alloc_exit; 3770 } 3771 3772 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3773 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3774 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3775 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3776 3777 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3778 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3779 "chain DMA memory!\n", __FILE__, __LINE__); 3780 rc = ENOMEM; 3781 goto bce_dma_alloc_exit; 3782 } 3783 3784 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3785 "0x%jX\n", __FUNCTION__, i, 3786 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3787 } 3788 3789 /* 3790 * Create a DMA tag for RX mbufs. 3791 */ 3792 if (bce_hdr_split == TRUE) 3793 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3794 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3795 else 3796 max_size = MJUM9BYTES; 3797 3798 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3799 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3800 3801 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3802 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3803 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3804 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3805 __FILE__, __LINE__); 3806 rc = ENOMEM; 3807 goto bce_dma_alloc_exit; 3808 } 3809 3810 /* Create DMA maps for the RX mbuf clusters. */ 3811 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3812 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3813 &sc->rx_mbuf_map[i])) { 3814 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3815 "DMA map!\n", __FILE__, __LINE__); 3816 rc = ENOMEM; 3817 goto bce_dma_alloc_exit; 3818 } 3819 } 3820 3821 if (bce_hdr_split == TRUE) { 3822 /* 3823 * Create a DMA tag for the page buffer descriptor chain, 3824 * allocate and clear the memory, and fetch the physical 3825 * address of the blocks. 3826 */ 3827 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3828 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3829 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3830 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3831 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3832 "chain DMA tag!\n", __FILE__, __LINE__); 3833 rc = ENOMEM; 3834 goto bce_dma_alloc_exit; 3835 } 3836 3837 for (i = 0; i < sc->pg_pages; i++) { 3838 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3839 (void **)&sc->pg_bd_chain[i], 3840 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3841 &sc->pg_bd_chain_map[i])) { 3842 BCE_PRINTF("%s(%d): Could not allocate page " 3843 "descriptor chain DMA memory!\n", 3844 __FILE__, __LINE__); 3845 rc = ENOMEM; 3846 goto bce_dma_alloc_exit; 3847 } 3848 3849 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3850 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3851 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3852 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3853 3854 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3855 BCE_PRINTF("%s(%d): Could not map page descriptor " 3856 "chain DMA memory!\n", __FILE__, __LINE__); 3857 rc = ENOMEM; 3858 goto bce_dma_alloc_exit; 3859 } 3860 3861 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3862 "0x%jX\n", __FUNCTION__, i, 3863 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3864 } 3865 3866 /* 3867 * Create a DMA tag for page mbufs. 3868 */ 3869 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3870 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3871 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3872 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3873 "DMA tag!\n", __FILE__, __LINE__); 3874 rc = ENOMEM; 3875 goto bce_dma_alloc_exit; 3876 } 3877 3878 /* Create DMA maps for the page mbuf clusters. */ 3879 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3880 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3881 &sc->pg_mbuf_map[i])) { 3882 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3883 "DMA map!\n", __FILE__, __LINE__); 3884 rc = ENOMEM; 3885 goto bce_dma_alloc_exit; 3886 } 3887 } 3888 } 3889 3890 bce_dma_alloc_exit: 3891 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3892 return(rc); 3893 } 3894 3895 3896 /****************************************************************************/ 3897 /* Release all resources used by the driver. */ 3898 /* */ 3899 /* Releases all resources acquired by the driver including interrupts, */ 3900 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3901 /* */ 3902 /* Returns: */ 3903 /* Nothing. */ 3904 /****************************************************************************/ 3905 static void 3906 bce_release_resources(struct bce_softc *sc) 3907 { 3908 device_t dev; 3909 3910 DBENTER(BCE_VERBOSE_RESET); 3911 3912 dev = sc->bce_dev; 3913 3914 bce_dma_free(sc); 3915 3916 if (sc->bce_intrhand != NULL) { 3917 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3918 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3919 } 3920 3921 if (sc->bce_res_irq != NULL) { 3922 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3923 bus_release_resource(dev, SYS_RES_IRQ, 3924 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3925 } 3926 3927 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3928 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3929 pci_release_msi(dev); 3930 } 3931 3932 if (sc->bce_res_mem != NULL) { 3933 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3934 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3935 sc->bce_res_mem); 3936 } 3937 3938 if (sc->bce_ifp != NULL) { 3939 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3940 if_free(sc->bce_ifp); 3941 } 3942 3943 if (mtx_initialized(&sc->bce_mtx)) 3944 BCE_LOCK_DESTROY(sc); 3945 3946 DBEXIT(BCE_VERBOSE_RESET); 3947 } 3948 3949 3950 /****************************************************************************/ 3951 /* Firmware synchronization. */ 3952 /* */ 3953 /* Before performing certain events such as a chip reset, synchronize with */ 3954 /* the firmware first. */ 3955 /* */ 3956 /* Returns: */ 3957 /* 0 for success, positive value for failure. */ 3958 /****************************************************************************/ 3959 static int 3960 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3961 { 3962 int i, rc = 0; 3963 u32 val; 3964 3965 DBENTER(BCE_VERBOSE_RESET); 3966 3967 /* Don't waste any time if we've timed out before. */ 3968 if (sc->bce_fw_timed_out == TRUE) { 3969 rc = EBUSY; 3970 goto bce_fw_sync_exit; 3971 } 3972 3973 /* Increment the message sequence number. */ 3974 sc->bce_fw_wr_seq++; 3975 msg_data |= sc->bce_fw_wr_seq; 3976 3977 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3978 "0x%08X\n", msg_data); 3979 3980 /* Send the message to the bootcode driver mailbox. */ 3981 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3982 3983 /* Wait for the bootcode to acknowledge the message. */ 3984 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3985 /* Check for a response in the bootcode firmware mailbox. */ 3986 val = bce_shmem_rd(sc, BCE_FW_MB); 3987 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3988 break; 3989 DELAY(1000); 3990 } 3991 3992 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3993 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3994 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3995 3996 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3997 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3998 3999 msg_data &= ~BCE_DRV_MSG_CODE; 4000 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 4001 4002 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 4003 4004 sc->bce_fw_timed_out = TRUE; 4005 rc = EBUSY; 4006 } 4007 4008 bce_fw_sync_exit: 4009 DBEXIT(BCE_VERBOSE_RESET); 4010 return (rc); 4011 } 4012 4013 4014 /****************************************************************************/ 4015 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 4016 /* */ 4017 /* Returns: */ 4018 /* Nothing. */ 4019 /****************************************************************************/ 4020 static void 4021 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 4022 u32 rv2p_code_len, u32 rv2p_proc) 4023 { 4024 int i; 4025 u32 val; 4026 4027 DBENTER(BCE_VERBOSE_RESET); 4028 4029 /* Set the page size used by RV2P. */ 4030 if (rv2p_proc == RV2P_PROC2) { 4031 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 4032 } 4033 4034 for (i = 0; i < rv2p_code_len; i += 8) { 4035 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 4036 rv2p_code++; 4037 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 4038 rv2p_code++; 4039 4040 if (rv2p_proc == RV2P_PROC1) { 4041 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4042 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4043 } 4044 else { 4045 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4046 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4047 } 4048 } 4049 4050 /* Reset the processor, un-stall is done later. */ 4051 if (rv2p_proc == RV2P_PROC1) { 4052 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4053 } 4054 else { 4055 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4056 } 4057 4058 DBEXIT(BCE_VERBOSE_RESET); 4059 } 4060 4061 4062 /****************************************************************************/ 4063 /* Load RISC processor firmware. */ 4064 /* */ 4065 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4066 /* associated with a particular processor. */ 4067 /* */ 4068 /* Returns: */ 4069 /* Nothing. */ 4070 /****************************************************************************/ 4071 static void 4072 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4073 struct fw_info *fw) 4074 { 4075 u32 offset; 4076 4077 DBENTER(BCE_VERBOSE_RESET); 4078 4079 bce_halt_cpu(sc, cpu_reg); 4080 4081 /* Load the Text area. */ 4082 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4083 if (fw->text) { 4084 int j; 4085 4086 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4087 REG_WR_IND(sc, offset, fw->text[j]); 4088 } 4089 } 4090 4091 /* Load the Data area. */ 4092 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4093 if (fw->data) { 4094 int j; 4095 4096 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4097 REG_WR_IND(sc, offset, fw->data[j]); 4098 } 4099 } 4100 4101 /* Load the SBSS area. */ 4102 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4103 if (fw->sbss) { 4104 int j; 4105 4106 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4107 REG_WR_IND(sc, offset, fw->sbss[j]); 4108 } 4109 } 4110 4111 /* Load the BSS area. */ 4112 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4113 if (fw->bss) { 4114 int j; 4115 4116 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4117 REG_WR_IND(sc, offset, fw->bss[j]); 4118 } 4119 } 4120 4121 /* Load the Read-Only area. */ 4122 offset = cpu_reg->spad_base + 4123 (fw->rodata_addr - cpu_reg->mips_view_base); 4124 if (fw->rodata) { 4125 int j; 4126 4127 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4128 REG_WR_IND(sc, offset, fw->rodata[j]); 4129 } 4130 } 4131 4132 /* Clear the pre-fetch instruction and set the FW start address. */ 4133 REG_WR_IND(sc, cpu_reg->inst, 0); 4134 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4135 4136 DBEXIT(BCE_VERBOSE_RESET); 4137 } 4138 4139 4140 /****************************************************************************/ 4141 /* Starts the RISC processor. */ 4142 /* */ 4143 /* Assumes the CPU starting address has already been set. */ 4144 /* */ 4145 /* Returns: */ 4146 /* Nothing. */ 4147 /****************************************************************************/ 4148 static void 4149 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4150 { 4151 u32 val; 4152 4153 DBENTER(BCE_VERBOSE_RESET); 4154 4155 /* Start the CPU. */ 4156 val = REG_RD_IND(sc, cpu_reg->mode); 4157 val &= ~cpu_reg->mode_value_halt; 4158 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4159 REG_WR_IND(sc, cpu_reg->mode, val); 4160 4161 DBEXIT(BCE_VERBOSE_RESET); 4162 } 4163 4164 4165 /****************************************************************************/ 4166 /* Halts the RISC processor. */ 4167 /* */ 4168 /* Returns: */ 4169 /* Nothing. */ 4170 /****************************************************************************/ 4171 static void 4172 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4173 { 4174 u32 val; 4175 4176 DBENTER(BCE_VERBOSE_RESET); 4177 4178 /* Halt the CPU. */ 4179 val = REG_RD_IND(sc, cpu_reg->mode); 4180 val |= cpu_reg->mode_value_halt; 4181 REG_WR_IND(sc, cpu_reg->mode, val); 4182 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4183 4184 DBEXIT(BCE_VERBOSE_RESET); 4185 } 4186 4187 4188 /****************************************************************************/ 4189 /* Initialize the RX CPU. */ 4190 /* */ 4191 /* Returns: */ 4192 /* Nothing. */ 4193 /****************************************************************************/ 4194 static void 4195 bce_start_rxp_cpu(struct bce_softc *sc) 4196 { 4197 struct cpu_reg cpu_reg; 4198 4199 DBENTER(BCE_VERBOSE_RESET); 4200 4201 cpu_reg.mode = BCE_RXP_CPU_MODE; 4202 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4203 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4204 cpu_reg.state = BCE_RXP_CPU_STATE; 4205 cpu_reg.state_value_clear = 0xffffff; 4206 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4207 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4208 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4209 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4210 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4211 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4212 cpu_reg.mips_view_base = 0x8000000; 4213 4214 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4215 bce_start_cpu(sc, &cpu_reg); 4216 4217 DBEXIT(BCE_VERBOSE_RESET); 4218 } 4219 4220 4221 /****************************************************************************/ 4222 /* Initialize the RX CPU. */ 4223 /* */ 4224 /* Returns: */ 4225 /* Nothing. */ 4226 /****************************************************************************/ 4227 static void 4228 bce_init_rxp_cpu(struct bce_softc *sc) 4229 { 4230 struct cpu_reg cpu_reg; 4231 struct fw_info fw; 4232 4233 DBENTER(BCE_VERBOSE_RESET); 4234 4235 cpu_reg.mode = BCE_RXP_CPU_MODE; 4236 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4237 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4238 cpu_reg.state = BCE_RXP_CPU_STATE; 4239 cpu_reg.state_value_clear = 0xffffff; 4240 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4241 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4242 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4243 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4244 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4245 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4246 cpu_reg.mips_view_base = 0x8000000; 4247 4248 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4249 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4250 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4251 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4252 fw.start_addr = bce_RXP_b09FwStartAddr; 4253 4254 fw.text_addr = bce_RXP_b09FwTextAddr; 4255 fw.text_len = bce_RXP_b09FwTextLen; 4256 fw.text_index = 0; 4257 fw.text = bce_RXP_b09FwText; 4258 4259 fw.data_addr = bce_RXP_b09FwDataAddr; 4260 fw.data_len = bce_RXP_b09FwDataLen; 4261 fw.data_index = 0; 4262 fw.data = bce_RXP_b09FwData; 4263 4264 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4265 fw.sbss_len = bce_RXP_b09FwSbssLen; 4266 fw.sbss_index = 0; 4267 fw.sbss = bce_RXP_b09FwSbss; 4268 4269 fw.bss_addr = bce_RXP_b09FwBssAddr; 4270 fw.bss_len = bce_RXP_b09FwBssLen; 4271 fw.bss_index = 0; 4272 fw.bss = bce_RXP_b09FwBss; 4273 4274 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4275 fw.rodata_len = bce_RXP_b09FwRodataLen; 4276 fw.rodata_index = 0; 4277 fw.rodata = bce_RXP_b09FwRodata; 4278 } else { 4279 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4280 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4281 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4282 fw.start_addr = bce_RXP_b06FwStartAddr; 4283 4284 fw.text_addr = bce_RXP_b06FwTextAddr; 4285 fw.text_len = bce_RXP_b06FwTextLen; 4286 fw.text_index = 0; 4287 fw.text = bce_RXP_b06FwText; 4288 4289 fw.data_addr = bce_RXP_b06FwDataAddr; 4290 fw.data_len = bce_RXP_b06FwDataLen; 4291 fw.data_index = 0; 4292 fw.data = bce_RXP_b06FwData; 4293 4294 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4295 fw.sbss_len = bce_RXP_b06FwSbssLen; 4296 fw.sbss_index = 0; 4297 fw.sbss = bce_RXP_b06FwSbss; 4298 4299 fw.bss_addr = bce_RXP_b06FwBssAddr; 4300 fw.bss_len = bce_RXP_b06FwBssLen; 4301 fw.bss_index = 0; 4302 fw.bss = bce_RXP_b06FwBss; 4303 4304 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4305 fw.rodata_len = bce_RXP_b06FwRodataLen; 4306 fw.rodata_index = 0; 4307 fw.rodata = bce_RXP_b06FwRodata; 4308 } 4309 4310 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4311 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4312 4313 /* Delay RXP start until initialization is complete. */ 4314 4315 DBEXIT(BCE_VERBOSE_RESET); 4316 } 4317 4318 4319 /****************************************************************************/ 4320 /* Initialize the TX CPU. */ 4321 /* */ 4322 /* Returns: */ 4323 /* Nothing. */ 4324 /****************************************************************************/ 4325 static void 4326 bce_init_txp_cpu(struct bce_softc *sc) 4327 { 4328 struct cpu_reg cpu_reg; 4329 struct fw_info fw; 4330 4331 DBENTER(BCE_VERBOSE_RESET); 4332 4333 cpu_reg.mode = BCE_TXP_CPU_MODE; 4334 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4335 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4336 cpu_reg.state = BCE_TXP_CPU_STATE; 4337 cpu_reg.state_value_clear = 0xffffff; 4338 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4339 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4340 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4341 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4342 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4343 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4344 cpu_reg.mips_view_base = 0x8000000; 4345 4346 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4347 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4348 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4349 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4350 fw.start_addr = bce_TXP_b09FwStartAddr; 4351 4352 fw.text_addr = bce_TXP_b09FwTextAddr; 4353 fw.text_len = bce_TXP_b09FwTextLen; 4354 fw.text_index = 0; 4355 fw.text = bce_TXP_b09FwText; 4356 4357 fw.data_addr = bce_TXP_b09FwDataAddr; 4358 fw.data_len = bce_TXP_b09FwDataLen; 4359 fw.data_index = 0; 4360 fw.data = bce_TXP_b09FwData; 4361 4362 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4363 fw.sbss_len = bce_TXP_b09FwSbssLen; 4364 fw.sbss_index = 0; 4365 fw.sbss = bce_TXP_b09FwSbss; 4366 4367 fw.bss_addr = bce_TXP_b09FwBssAddr; 4368 fw.bss_len = bce_TXP_b09FwBssLen; 4369 fw.bss_index = 0; 4370 fw.bss = bce_TXP_b09FwBss; 4371 4372 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4373 fw.rodata_len = bce_TXP_b09FwRodataLen; 4374 fw.rodata_index = 0; 4375 fw.rodata = bce_TXP_b09FwRodata; 4376 } else { 4377 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4378 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4379 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4380 fw.start_addr = bce_TXP_b06FwStartAddr; 4381 4382 fw.text_addr = bce_TXP_b06FwTextAddr; 4383 fw.text_len = bce_TXP_b06FwTextLen; 4384 fw.text_index = 0; 4385 fw.text = bce_TXP_b06FwText; 4386 4387 fw.data_addr = bce_TXP_b06FwDataAddr; 4388 fw.data_len = bce_TXP_b06FwDataLen; 4389 fw.data_index = 0; 4390 fw.data = bce_TXP_b06FwData; 4391 4392 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4393 fw.sbss_len = bce_TXP_b06FwSbssLen; 4394 fw.sbss_index = 0; 4395 fw.sbss = bce_TXP_b06FwSbss; 4396 4397 fw.bss_addr = bce_TXP_b06FwBssAddr; 4398 fw.bss_len = bce_TXP_b06FwBssLen; 4399 fw.bss_index = 0; 4400 fw.bss = bce_TXP_b06FwBss; 4401 4402 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4403 fw.rodata_len = bce_TXP_b06FwRodataLen; 4404 fw.rodata_index = 0; 4405 fw.rodata = bce_TXP_b06FwRodata; 4406 } 4407 4408 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4409 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4410 bce_start_cpu(sc, &cpu_reg); 4411 4412 DBEXIT(BCE_VERBOSE_RESET); 4413 } 4414 4415 4416 /****************************************************************************/ 4417 /* Initialize the TPAT CPU. */ 4418 /* */ 4419 /* Returns: */ 4420 /* Nothing. */ 4421 /****************************************************************************/ 4422 static void 4423 bce_init_tpat_cpu(struct bce_softc *sc) 4424 { 4425 struct cpu_reg cpu_reg; 4426 struct fw_info fw; 4427 4428 DBENTER(BCE_VERBOSE_RESET); 4429 4430 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4431 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4432 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4433 cpu_reg.state = BCE_TPAT_CPU_STATE; 4434 cpu_reg.state_value_clear = 0xffffff; 4435 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4436 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4437 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4438 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4439 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4440 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4441 cpu_reg.mips_view_base = 0x8000000; 4442 4443 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4444 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4445 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4446 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4447 fw.start_addr = bce_TPAT_b09FwStartAddr; 4448 4449 fw.text_addr = bce_TPAT_b09FwTextAddr; 4450 fw.text_len = bce_TPAT_b09FwTextLen; 4451 fw.text_index = 0; 4452 fw.text = bce_TPAT_b09FwText; 4453 4454 fw.data_addr = bce_TPAT_b09FwDataAddr; 4455 fw.data_len = bce_TPAT_b09FwDataLen; 4456 fw.data_index = 0; 4457 fw.data = bce_TPAT_b09FwData; 4458 4459 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4460 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4461 fw.sbss_index = 0; 4462 fw.sbss = bce_TPAT_b09FwSbss; 4463 4464 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4465 fw.bss_len = bce_TPAT_b09FwBssLen; 4466 fw.bss_index = 0; 4467 fw.bss = bce_TPAT_b09FwBss; 4468 4469 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4470 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4471 fw.rodata_index = 0; 4472 fw.rodata = bce_TPAT_b09FwRodata; 4473 } else { 4474 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4475 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4476 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4477 fw.start_addr = bce_TPAT_b06FwStartAddr; 4478 4479 fw.text_addr = bce_TPAT_b06FwTextAddr; 4480 fw.text_len = bce_TPAT_b06FwTextLen; 4481 fw.text_index = 0; 4482 fw.text = bce_TPAT_b06FwText; 4483 4484 fw.data_addr = bce_TPAT_b06FwDataAddr; 4485 fw.data_len = bce_TPAT_b06FwDataLen; 4486 fw.data_index = 0; 4487 fw.data = bce_TPAT_b06FwData; 4488 4489 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4490 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4491 fw.sbss_index = 0; 4492 fw.sbss = bce_TPAT_b06FwSbss; 4493 4494 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4495 fw.bss_len = bce_TPAT_b06FwBssLen; 4496 fw.bss_index = 0; 4497 fw.bss = bce_TPAT_b06FwBss; 4498 4499 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4500 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4501 fw.rodata_index = 0; 4502 fw.rodata = bce_TPAT_b06FwRodata; 4503 } 4504 4505 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4506 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4507 bce_start_cpu(sc, &cpu_reg); 4508 4509 DBEXIT(BCE_VERBOSE_RESET); 4510 } 4511 4512 4513 /****************************************************************************/ 4514 /* Initialize the CP CPU. */ 4515 /* */ 4516 /* Returns: */ 4517 /* Nothing. */ 4518 /****************************************************************************/ 4519 static void 4520 bce_init_cp_cpu(struct bce_softc *sc) 4521 { 4522 struct cpu_reg cpu_reg; 4523 struct fw_info fw; 4524 4525 DBENTER(BCE_VERBOSE_RESET); 4526 4527 cpu_reg.mode = BCE_CP_CPU_MODE; 4528 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4529 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4530 cpu_reg.state = BCE_CP_CPU_STATE; 4531 cpu_reg.state_value_clear = 0xffffff; 4532 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4533 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4534 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4535 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4536 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4537 cpu_reg.spad_base = BCE_CP_SCRATCH; 4538 cpu_reg.mips_view_base = 0x8000000; 4539 4540 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4541 fw.ver_major = bce_CP_b09FwReleaseMajor; 4542 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4543 fw.ver_fix = bce_CP_b09FwReleaseFix; 4544 fw.start_addr = bce_CP_b09FwStartAddr; 4545 4546 fw.text_addr = bce_CP_b09FwTextAddr; 4547 fw.text_len = bce_CP_b09FwTextLen; 4548 fw.text_index = 0; 4549 fw.text = bce_CP_b09FwText; 4550 4551 fw.data_addr = bce_CP_b09FwDataAddr; 4552 fw.data_len = bce_CP_b09FwDataLen; 4553 fw.data_index = 0; 4554 fw.data = bce_CP_b09FwData; 4555 4556 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4557 fw.sbss_len = bce_CP_b09FwSbssLen; 4558 fw.sbss_index = 0; 4559 fw.sbss = bce_CP_b09FwSbss; 4560 4561 fw.bss_addr = bce_CP_b09FwBssAddr; 4562 fw.bss_len = bce_CP_b09FwBssLen; 4563 fw.bss_index = 0; 4564 fw.bss = bce_CP_b09FwBss; 4565 4566 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4567 fw.rodata_len = bce_CP_b09FwRodataLen; 4568 fw.rodata_index = 0; 4569 fw.rodata = bce_CP_b09FwRodata; 4570 } else { 4571 fw.ver_major = bce_CP_b06FwReleaseMajor; 4572 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4573 fw.ver_fix = bce_CP_b06FwReleaseFix; 4574 fw.start_addr = bce_CP_b06FwStartAddr; 4575 4576 fw.text_addr = bce_CP_b06FwTextAddr; 4577 fw.text_len = bce_CP_b06FwTextLen; 4578 fw.text_index = 0; 4579 fw.text = bce_CP_b06FwText; 4580 4581 fw.data_addr = bce_CP_b06FwDataAddr; 4582 fw.data_len = bce_CP_b06FwDataLen; 4583 fw.data_index = 0; 4584 fw.data = bce_CP_b06FwData; 4585 4586 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4587 fw.sbss_len = bce_CP_b06FwSbssLen; 4588 fw.sbss_index = 0; 4589 fw.sbss = bce_CP_b06FwSbss; 4590 4591 fw.bss_addr = bce_CP_b06FwBssAddr; 4592 fw.bss_len = bce_CP_b06FwBssLen; 4593 fw.bss_index = 0; 4594 fw.bss = bce_CP_b06FwBss; 4595 4596 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4597 fw.rodata_len = bce_CP_b06FwRodataLen; 4598 fw.rodata_index = 0; 4599 fw.rodata = bce_CP_b06FwRodata; 4600 } 4601 4602 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4603 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4604 bce_start_cpu(sc, &cpu_reg); 4605 4606 DBEXIT(BCE_VERBOSE_RESET); 4607 } 4608 4609 4610 /****************************************************************************/ 4611 /* Initialize the COM CPU. */ 4612 /* */ 4613 /* Returns: */ 4614 /* Nothing. */ 4615 /****************************************************************************/ 4616 static void 4617 bce_init_com_cpu(struct bce_softc *sc) 4618 { 4619 struct cpu_reg cpu_reg; 4620 struct fw_info fw; 4621 4622 DBENTER(BCE_VERBOSE_RESET); 4623 4624 cpu_reg.mode = BCE_COM_CPU_MODE; 4625 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4626 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4627 cpu_reg.state = BCE_COM_CPU_STATE; 4628 cpu_reg.state_value_clear = 0xffffff; 4629 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4630 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4631 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4632 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4633 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4634 cpu_reg.spad_base = BCE_COM_SCRATCH; 4635 cpu_reg.mips_view_base = 0x8000000; 4636 4637 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4638 fw.ver_major = bce_COM_b09FwReleaseMajor; 4639 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4640 fw.ver_fix = bce_COM_b09FwReleaseFix; 4641 fw.start_addr = bce_COM_b09FwStartAddr; 4642 4643 fw.text_addr = bce_COM_b09FwTextAddr; 4644 fw.text_len = bce_COM_b09FwTextLen; 4645 fw.text_index = 0; 4646 fw.text = bce_COM_b09FwText; 4647 4648 fw.data_addr = bce_COM_b09FwDataAddr; 4649 fw.data_len = bce_COM_b09FwDataLen; 4650 fw.data_index = 0; 4651 fw.data = bce_COM_b09FwData; 4652 4653 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4654 fw.sbss_len = bce_COM_b09FwSbssLen; 4655 fw.sbss_index = 0; 4656 fw.sbss = bce_COM_b09FwSbss; 4657 4658 fw.bss_addr = bce_COM_b09FwBssAddr; 4659 fw.bss_len = bce_COM_b09FwBssLen; 4660 fw.bss_index = 0; 4661 fw.bss = bce_COM_b09FwBss; 4662 4663 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4664 fw.rodata_len = bce_COM_b09FwRodataLen; 4665 fw.rodata_index = 0; 4666 fw.rodata = bce_COM_b09FwRodata; 4667 } else { 4668 fw.ver_major = bce_COM_b06FwReleaseMajor; 4669 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4670 fw.ver_fix = bce_COM_b06FwReleaseFix; 4671 fw.start_addr = bce_COM_b06FwStartAddr; 4672 4673 fw.text_addr = bce_COM_b06FwTextAddr; 4674 fw.text_len = bce_COM_b06FwTextLen; 4675 fw.text_index = 0; 4676 fw.text = bce_COM_b06FwText; 4677 4678 fw.data_addr = bce_COM_b06FwDataAddr; 4679 fw.data_len = bce_COM_b06FwDataLen; 4680 fw.data_index = 0; 4681 fw.data = bce_COM_b06FwData; 4682 4683 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4684 fw.sbss_len = bce_COM_b06FwSbssLen; 4685 fw.sbss_index = 0; 4686 fw.sbss = bce_COM_b06FwSbss; 4687 4688 fw.bss_addr = bce_COM_b06FwBssAddr; 4689 fw.bss_len = bce_COM_b06FwBssLen; 4690 fw.bss_index = 0; 4691 fw.bss = bce_COM_b06FwBss; 4692 4693 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4694 fw.rodata_len = bce_COM_b06FwRodataLen; 4695 fw.rodata_index = 0; 4696 fw.rodata = bce_COM_b06FwRodata; 4697 } 4698 4699 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4700 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4701 bce_start_cpu(sc, &cpu_reg); 4702 4703 DBEXIT(BCE_VERBOSE_RESET); 4704 } 4705 4706 4707 /****************************************************************************/ 4708 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4709 /* */ 4710 /* Loads the firmware for each CPU and starts the CPU. */ 4711 /* */ 4712 /* Returns: */ 4713 /* Nothing. */ 4714 /****************************************************************************/ 4715 static void 4716 bce_init_cpus(struct bce_softc *sc) 4717 { 4718 DBENTER(BCE_VERBOSE_RESET); 4719 4720 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4721 4722 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4723 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4724 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4725 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4726 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4727 } else { 4728 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4729 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4730 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4731 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4732 } 4733 4734 } else { 4735 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4736 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4737 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4738 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4739 } 4740 4741 bce_init_rxp_cpu(sc); 4742 bce_init_txp_cpu(sc); 4743 bce_init_tpat_cpu(sc); 4744 bce_init_com_cpu(sc); 4745 bce_init_cp_cpu(sc); 4746 4747 DBEXIT(BCE_VERBOSE_RESET); 4748 } 4749 4750 4751 /****************************************************************************/ 4752 /* Initialize context memory. */ 4753 /* */ 4754 /* Clears the memory associated with each Context ID (CID). */ 4755 /* */ 4756 /* Returns: */ 4757 /* Nothing. */ 4758 /****************************************************************************/ 4759 static int 4760 bce_init_ctx(struct bce_softc *sc) 4761 { 4762 u32 offset, val, vcid_addr; 4763 int i, j, rc, retry_cnt; 4764 4765 rc = 0; 4766 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4767 4768 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4769 retry_cnt = CTX_INIT_RETRY_COUNT; 4770 4771 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4772 4773 /* 4774 * BCM5709 context memory may be cached 4775 * in host memory so prepare the host memory 4776 * for access. 4777 */ 4778 val = BCE_CTX_COMMAND_ENABLED | 4779 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4780 val |= (BCM_PAGE_BITS - 8) << 16; 4781 REG_WR(sc, BCE_CTX_COMMAND, val); 4782 4783 /* Wait for mem init command to complete. */ 4784 for (i = 0; i < retry_cnt; i++) { 4785 val = REG_RD(sc, BCE_CTX_COMMAND); 4786 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4787 break; 4788 DELAY(2); 4789 } 4790 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4791 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4792 __FUNCTION__); 4793 rc = EBUSY; 4794 goto init_ctx_fail; 4795 } 4796 4797 for (i = 0; i < sc->ctx_pages; i++) { 4798 /* Set the physical address of the context memory. */ 4799 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4800 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4801 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4802 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4803 BCE_ADDR_HI(sc->ctx_paddr[i])); 4804 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4805 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4806 4807 /* Verify the context memory write was successful. */ 4808 for (j = 0; j < retry_cnt; j++) { 4809 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4810 if ((val & 4811 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4812 break; 4813 DELAY(5); 4814 } 4815 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4816 BCE_PRINTF("%s(): Failed to initialize " 4817 "context page %d!\n", __FUNCTION__, i); 4818 rc = EBUSY; 4819 goto init_ctx_fail; 4820 } 4821 } 4822 } else { 4823 4824 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4825 4826 /* 4827 * For the 5706/5708, context memory is local to 4828 * the controller, so initialize the controller 4829 * context memory. 4830 */ 4831 4832 vcid_addr = GET_CID_ADDR(96); 4833 while (vcid_addr) { 4834 4835 vcid_addr -= PHY_CTX_SIZE; 4836 4837 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4838 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4839 4840 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4841 CTX_WR(sc, 0x00, offset, 0); 4842 } 4843 4844 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4845 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4846 } 4847 4848 } 4849 init_ctx_fail: 4850 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4851 return (rc); 4852 } 4853 4854 4855 /****************************************************************************/ 4856 /* Fetch the permanent MAC address of the controller. */ 4857 /* */ 4858 /* Returns: */ 4859 /* Nothing. */ 4860 /****************************************************************************/ 4861 static void 4862 bce_get_mac_addr(struct bce_softc *sc) 4863 { 4864 u32 mac_lo = 0, mac_hi = 0; 4865 4866 DBENTER(BCE_VERBOSE_RESET); 4867 4868 /* 4869 * The NetXtreme II bootcode populates various NIC 4870 * power-on and runtime configuration items in a 4871 * shared memory area. The factory configured MAC 4872 * address is available from both NVRAM and the 4873 * shared memory area so we'll read the value from 4874 * shared memory for speed. 4875 */ 4876 4877 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4878 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4879 4880 if ((mac_lo == 0) && (mac_hi == 0)) { 4881 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4882 __FILE__, __LINE__); 4883 } else { 4884 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4885 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4886 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4887 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4888 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4889 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4890 } 4891 4892 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4893 "address = %6D\n", sc->eaddr, ":"); 4894 DBEXIT(BCE_VERBOSE_RESET); 4895 } 4896 4897 4898 /****************************************************************************/ 4899 /* Program the MAC address. */ 4900 /* */ 4901 /* Returns: */ 4902 /* Nothing. */ 4903 /****************************************************************************/ 4904 static void 4905 bce_set_mac_addr(struct bce_softc *sc) 4906 { 4907 u32 val; 4908 u8 *mac_addr = sc->eaddr; 4909 4910 /* ToDo: Add support for setting multiple MAC addresses. */ 4911 4912 DBENTER(BCE_VERBOSE_RESET); 4913 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4914 "%6D\n", sc->eaddr, ":"); 4915 4916 val = (mac_addr[0] << 8) | mac_addr[1]; 4917 4918 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4919 4920 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4921 (mac_addr[4] << 8) | mac_addr[5]; 4922 4923 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4924 4925 DBEXIT(BCE_VERBOSE_RESET); 4926 } 4927 4928 4929 /****************************************************************************/ 4930 /* Stop the controller. */ 4931 /* */ 4932 /* Returns: */ 4933 /* Nothing. */ 4934 /****************************************************************************/ 4935 static void 4936 bce_stop(struct bce_softc *sc) 4937 { 4938 struct ifnet *ifp; 4939 4940 DBENTER(BCE_VERBOSE_RESET); 4941 4942 BCE_LOCK_ASSERT(sc); 4943 4944 ifp = sc->bce_ifp; 4945 4946 callout_stop(&sc->bce_tick_callout); 4947 4948 /* Disable the transmit/receive blocks. */ 4949 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4950 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4951 DELAY(20); 4952 4953 bce_disable_intr(sc); 4954 4955 /* Free RX buffers. */ 4956 if (bce_hdr_split == TRUE) { 4957 bce_free_pg_chain(sc); 4958 } 4959 bce_free_rx_chain(sc); 4960 4961 /* Free TX buffers. */ 4962 bce_free_tx_chain(sc); 4963 4964 sc->watchdog_timer = 0; 4965 4966 sc->bce_link_up = FALSE; 4967 4968 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4969 4970 DBEXIT(BCE_VERBOSE_RESET); 4971 } 4972 4973 4974 static int 4975 bce_reset(struct bce_softc *sc, u32 reset_code) 4976 { 4977 u32 emac_mode_save, val; 4978 int i, rc = 0; 4979 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 4980 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 4981 4982 DBENTER(BCE_VERBOSE_RESET); 4983 4984 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4985 __FUNCTION__, reset_code); 4986 4987 /* 4988 * If ASF/IPMI is operational, then the EMAC Mode register already 4989 * contains appropriate values for the link settings that have 4990 * been auto-negotiated. Resetting the chip will clobber those 4991 * values. Save the important bits so we can restore them after 4992 * the reset. 4993 */ 4994 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 4995 4996 /* Wait for pending PCI transactions to complete. */ 4997 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4998 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4999 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 5000 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 5001 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 5002 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 5003 DELAY(5); 5004 5005 /* Disable DMA */ 5006 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5007 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5008 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5009 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5010 } 5011 5012 /* Assume bootcode is running. */ 5013 sc->bce_fw_timed_out = FALSE; 5014 sc->bce_drv_cardiac_arrest = FALSE; 5015 5016 /* Give the firmware a chance to prepare for the reset. */ 5017 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 5018 if (rc) 5019 goto bce_reset_exit; 5020 5021 /* Set a firmware reminder that this is a soft reset. */ 5022 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 5023 5024 /* Dummy read to force the chip to complete all current transactions. */ 5025 val = REG_RD(sc, BCE_MISC_ID); 5026 5027 /* Chip reset. */ 5028 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5029 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 5030 REG_RD(sc, BCE_MISC_COMMAND); 5031 DELAY(5); 5032 5033 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5034 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5035 5036 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 5037 } else { 5038 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5039 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5040 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5041 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 5042 5043 /* Allow up to 30us for reset to complete. */ 5044 for (i = 0; i < 10; i++) { 5045 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5046 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5047 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5048 break; 5049 } 5050 DELAY(10); 5051 } 5052 5053 /* Check that reset completed successfully. */ 5054 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5055 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5056 BCE_PRINTF("%s(%d): Reset failed!\n", 5057 __FILE__, __LINE__); 5058 rc = EBUSY; 5059 goto bce_reset_exit; 5060 } 5061 } 5062 5063 /* Make sure byte swapping is properly configured. */ 5064 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5065 if (val != 0x01020304) { 5066 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5067 __FILE__, __LINE__); 5068 rc = ENODEV; 5069 goto bce_reset_exit; 5070 } 5071 5072 /* Just completed a reset, assume that firmware is running again. */ 5073 sc->bce_fw_timed_out = FALSE; 5074 sc->bce_drv_cardiac_arrest = FALSE; 5075 5076 /* Wait for the firmware to finish its initialization. */ 5077 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5078 if (rc) 5079 BCE_PRINTF("%s(%d): Firmware did not complete " 5080 "initialization!\n", __FILE__, __LINE__); 5081 /* Get firmware capabilities. */ 5082 bce_fw_cap_init(sc); 5083 5084 bce_reset_exit: 5085 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 5086 if (reset_code == BCE_DRV_MSG_CODE_RESET) { 5087 val = REG_RD(sc, BCE_EMAC_MODE); 5088 val = (val & ~emac_mode_mask) | emac_mode_save; 5089 REG_WR(sc, BCE_EMAC_MODE, val); 5090 } 5091 5092 DBEXIT(BCE_VERBOSE_RESET); 5093 return (rc); 5094 } 5095 5096 5097 static int 5098 bce_chipinit(struct bce_softc *sc) 5099 { 5100 u32 val; 5101 int rc = 0; 5102 5103 DBENTER(BCE_VERBOSE_RESET); 5104 5105 bce_disable_intr(sc); 5106 5107 /* 5108 * Initialize DMA byte/word swapping, configure the number of DMA 5109 * channels and PCI clock compensation delay. 5110 */ 5111 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5112 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5113 #if BYTE_ORDER == BIG_ENDIAN 5114 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5115 #endif 5116 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5117 DMA_READ_CHANS << 12 | 5118 DMA_WRITE_CHANS << 16; 5119 5120 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5121 5122 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5123 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5124 5125 /* 5126 * This setting resolves a problem observed on certain Intel PCI 5127 * chipsets that cannot handle multiple outstanding DMA operations. 5128 * See errata E9_5706A1_65. 5129 */ 5130 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5131 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5132 !(sc->bce_flags & BCE_PCIX_FLAG)) 5133 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5134 5135 REG_WR(sc, BCE_DMA_CONFIG, val); 5136 5137 /* Enable the RX_V2P and Context state machines before access. */ 5138 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5139 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5140 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5141 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5142 5143 /* Initialize context mapping and zero out the quick contexts. */ 5144 if ((rc = bce_init_ctx(sc)) != 0) 5145 goto bce_chipinit_exit; 5146 5147 /* Initialize the on-boards CPUs */ 5148 bce_init_cpus(sc); 5149 5150 /* Enable management frames (NC-SI) to flow to the MCP. */ 5151 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5152 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5153 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5154 } 5155 5156 /* Prepare NVRAM for access. */ 5157 if ((rc = bce_init_nvram(sc)) != 0) 5158 goto bce_chipinit_exit; 5159 5160 /* Set the kernel bypass block size */ 5161 val = REG_RD(sc, BCE_MQ_CONFIG); 5162 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5163 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5164 5165 /* Enable bins used on the 5709. */ 5166 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5167 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5168 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5169 val |= BCE_MQ_CONFIG_HALT_DIS; 5170 } 5171 5172 REG_WR(sc, BCE_MQ_CONFIG, val); 5173 5174 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5175 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5176 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5177 5178 /* Set the page size and clear the RV2P processor stall bits. */ 5179 val = (BCM_PAGE_BITS - 8) << 24; 5180 REG_WR(sc, BCE_RV2P_CONFIG, val); 5181 5182 /* Configure page size. */ 5183 val = REG_RD(sc, BCE_TBDR_CONFIG); 5184 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5185 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5186 REG_WR(sc, BCE_TBDR_CONFIG, val); 5187 5188 /* Set the perfect match control register to default. */ 5189 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5190 5191 bce_chipinit_exit: 5192 DBEXIT(BCE_VERBOSE_RESET); 5193 5194 return(rc); 5195 } 5196 5197 5198 /****************************************************************************/ 5199 /* Initialize the controller in preparation to send/receive traffic. */ 5200 /* */ 5201 /* Returns: */ 5202 /* 0 for success, positive value for failure. */ 5203 /****************************************************************************/ 5204 static int 5205 bce_blockinit(struct bce_softc *sc) 5206 { 5207 u32 reg, val; 5208 int rc = 0; 5209 5210 DBENTER(BCE_VERBOSE_RESET); 5211 5212 /* Load the hardware default MAC address. */ 5213 bce_set_mac_addr(sc); 5214 5215 /* Set the Ethernet backoff seed value */ 5216 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5217 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5218 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5219 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5220 5221 sc->last_status_idx = 0; 5222 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5223 5224 /* Set up link change interrupt generation. */ 5225 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5226 5227 /* Program the physical address of the status block. */ 5228 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5229 BCE_ADDR_LO(sc->status_block_paddr)); 5230 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5231 BCE_ADDR_HI(sc->status_block_paddr)); 5232 5233 /* Program the physical address of the statistics block. */ 5234 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5235 BCE_ADDR_LO(sc->stats_block_paddr)); 5236 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5237 BCE_ADDR_HI(sc->stats_block_paddr)); 5238 5239 /* 5240 * Program various host coalescing parameters. 5241 * Trip points control how many BDs should be ready before generating 5242 * an interrupt while ticks control how long a BD can sit in the chain 5243 * before generating an interrupt. 5244 */ 5245 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5246 (sc->bce_tx_quick_cons_trip_int << 16) | 5247 sc->bce_tx_quick_cons_trip); 5248 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5249 (sc->bce_rx_quick_cons_trip_int << 16) | 5250 sc->bce_rx_quick_cons_trip); 5251 REG_WR(sc, BCE_HC_TX_TICKS, 5252 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5253 REG_WR(sc, BCE_HC_RX_TICKS, 5254 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5255 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5256 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5257 /* Not used for L2. */ 5258 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5259 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5260 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5261 5262 /* Configure the Host Coalescing block. */ 5263 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5264 BCE_HC_CONFIG_COLLECT_STATS; 5265 5266 #if 0 5267 /* ToDo: Add MSI-X support. */ 5268 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5269 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5270 BCE_HC_SB_CONFIG_1; 5271 5272 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5273 5274 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5275 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5276 5277 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5278 (sc->tx_quick_cons_trip_int << 16) | 5279 sc->tx_quick_cons_trip); 5280 5281 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5282 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5283 5284 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5285 } 5286 5287 /* 5288 * Tell the HC block to automatically set the 5289 * INT_MASK bit after an MSI/MSI-X interrupt 5290 * is generated so the driver doesn't have to. 5291 */ 5292 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5293 val |= BCE_HC_CONFIG_ONE_SHOT; 5294 5295 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5296 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5297 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5298 #endif 5299 5300 REG_WR(sc, BCE_HC_CONFIG, val); 5301 5302 /* Clear the internal statistics counters. */ 5303 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5304 5305 /* Verify that bootcode is running. */ 5306 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5307 5308 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5309 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5310 __FILE__, __LINE__); 5311 reg = 0); 5312 5313 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5314 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5315 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5316 "Expected: 08%08X\n", __FILE__, __LINE__, 5317 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5318 BCE_DEV_INFO_SIGNATURE_MAGIC); 5319 rc = ENODEV; 5320 goto bce_blockinit_exit; 5321 } 5322 5323 /* Enable DMA */ 5324 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5325 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5326 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5327 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5328 } 5329 5330 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5331 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5332 BCE_DRV_MSG_CODE_RESET); 5333 5334 /* Enable link state change interrupt generation. */ 5335 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5336 5337 /* Enable the RXP. */ 5338 bce_start_rxp_cpu(sc); 5339 5340 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5341 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5342 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5343 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5344 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5345 } 5346 5347 /* Enable all remaining blocks in the MAC. */ 5348 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5349 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5350 BCE_MISC_ENABLE_DEFAULT_XI); 5351 else 5352 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5353 BCE_MISC_ENABLE_DEFAULT); 5354 5355 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5356 DELAY(20); 5357 5358 /* Save the current host coalescing block settings. */ 5359 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5360 5361 bce_blockinit_exit: 5362 DBEXIT(BCE_VERBOSE_RESET); 5363 5364 return (rc); 5365 } 5366 5367 5368 /****************************************************************************/ 5369 /* Encapsulate an mbuf into the rx_bd chain. */ 5370 /* */ 5371 /* Returns: */ 5372 /* 0 for success, positive value for failure. */ 5373 /****************************************************************************/ 5374 static int 5375 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5376 { 5377 bus_dma_segment_t segs[1]; 5378 struct mbuf *m_new = NULL; 5379 struct rx_bd *rxbd; 5380 int nsegs, error, rc = 0; 5381 #ifdef BCE_DEBUG 5382 u16 debug_chain_prod = chain_prod; 5383 #endif 5384 5385 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5386 5387 /* Make sure the inputs are valid. */ 5388 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5389 BCE_PRINTF("%s(%d): RX producer out of range: " 5390 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5391 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5392 5393 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5394 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5395 prod, chain_prod, *prod_bseq); 5396 5397 /* Update some debug statistic counters */ 5398 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5399 sc->rx_low_watermark = sc->free_rx_bd); 5400 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5401 sc->rx_empty_count++); 5402 5403 /* Simulate an mbuf allocation failure. */ 5404 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5405 sc->mbuf_alloc_failed_count++; 5406 sc->mbuf_alloc_failed_sim_count++; 5407 rc = ENOBUFS; 5408 goto bce_get_rx_buf_exit); 5409 5410 /* This is a new mbuf allocation. */ 5411 if (bce_hdr_split == TRUE) 5412 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5413 else 5414 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5415 sc->rx_bd_mbuf_alloc_size); 5416 5417 if (m_new == NULL) { 5418 sc->mbuf_alloc_failed_count++; 5419 rc = ENOBUFS; 5420 goto bce_get_rx_buf_exit; 5421 } 5422 5423 DBRUN(sc->debug_rx_mbuf_alloc++); 5424 5425 /* Make sure we have a valid packet header. */ 5426 M_ASSERTPKTHDR(m_new); 5427 5428 /* Initialize the mbuf size and pad if necessary for alignment. */ 5429 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5430 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5431 5432 /* ToDo: Consider calling m_fragment() to test error handling. */ 5433 5434 /* Map the mbuf cluster into device memory. */ 5435 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5436 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5437 5438 /* Handle any mapping errors. */ 5439 if (error) { 5440 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5441 "chain (%d)!\n", __FILE__, __LINE__, error); 5442 5443 sc->dma_map_addr_rx_failed_count++; 5444 m_freem(m_new); 5445 5446 DBRUN(sc->debug_rx_mbuf_alloc--); 5447 5448 rc = ENOBUFS; 5449 goto bce_get_rx_buf_exit; 5450 } 5451 5452 /* All mbufs must map to a single segment. */ 5453 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5454 __FUNCTION__, nsegs)); 5455 5456 /* Setup the rx_bd for the segment. */ 5457 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5458 5459 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5460 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5461 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5462 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5463 *prod_bseq += segs[0].ds_len; 5464 5465 /* Save the mbuf and update our counter. */ 5466 sc->rx_mbuf_ptr[chain_prod] = m_new; 5467 sc->free_rx_bd -= nsegs; 5468 5469 DBRUNMSG(BCE_INSANE_RECV, 5470 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5471 5472 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5473 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5474 chain_prod, *prod_bseq); 5475 5476 bce_get_rx_buf_exit: 5477 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5478 5479 return(rc); 5480 } 5481 5482 5483 /****************************************************************************/ 5484 /* Encapsulate an mbuf cluster into the page chain. */ 5485 /* */ 5486 /* Returns: */ 5487 /* 0 for success, positive value for failure. */ 5488 /****************************************************************************/ 5489 static int 5490 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5491 { 5492 bus_dma_segment_t segs[1]; 5493 struct mbuf *m_new = NULL; 5494 struct rx_bd *pgbd; 5495 int error, nsegs, rc = 0; 5496 #ifdef BCE_DEBUG 5497 u16 debug_prod_idx = prod_idx; 5498 #endif 5499 5500 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5501 5502 /* Make sure the inputs are valid. */ 5503 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5504 BCE_PRINTF("%s(%d): page producer out of range: " 5505 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5506 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5507 5508 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5509 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5510 5511 /* Update counters if we've hit a new low or run out of pages. */ 5512 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5513 sc->pg_low_watermark = sc->free_pg_bd); 5514 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5515 5516 /* Simulate an mbuf allocation failure. */ 5517 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5518 sc->mbuf_alloc_failed_count++; 5519 sc->mbuf_alloc_failed_sim_count++; 5520 rc = ENOBUFS; 5521 goto bce_get_pg_buf_exit); 5522 5523 /* This is a new mbuf allocation. */ 5524 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5525 if (m_new == NULL) { 5526 sc->mbuf_alloc_failed_count++; 5527 rc = ENOBUFS; 5528 goto bce_get_pg_buf_exit; 5529 } 5530 5531 DBRUN(sc->debug_pg_mbuf_alloc++); 5532 5533 m_new->m_len = MCLBYTES; 5534 5535 /* ToDo: Consider calling m_fragment() to test error handling. */ 5536 5537 /* Map the mbuf cluster into device memory. */ 5538 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5539 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5540 5541 /* Handle any mapping errors. */ 5542 if (error) { 5543 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5544 __FILE__, __LINE__); 5545 5546 m_freem(m_new); 5547 DBRUN(sc->debug_pg_mbuf_alloc--); 5548 5549 rc = ENOBUFS; 5550 goto bce_get_pg_buf_exit; 5551 } 5552 5553 /* All mbufs must map to a single segment. */ 5554 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5555 __FUNCTION__, nsegs)); 5556 5557 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5558 5559 /* 5560 * The page chain uses the same rx_bd data structure 5561 * as the receive chain but doesn't require a byte sequence (bseq). 5562 */ 5563 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5564 5565 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5566 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5567 pgbd->rx_bd_len = htole32(MCLBYTES); 5568 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5569 5570 /* Save the mbuf and update our counter. */ 5571 sc->pg_mbuf_ptr[prod_idx] = m_new; 5572 sc->free_pg_bd--; 5573 5574 DBRUNMSG(BCE_INSANE_RECV, 5575 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5576 5577 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5578 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5579 5580 bce_get_pg_buf_exit: 5581 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5582 5583 return(rc); 5584 } 5585 5586 5587 /****************************************************************************/ 5588 /* Initialize the TX context memory. */ 5589 /* */ 5590 /* Returns: */ 5591 /* Nothing */ 5592 /****************************************************************************/ 5593 static void 5594 bce_init_tx_context(struct bce_softc *sc) 5595 { 5596 u32 val; 5597 5598 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5599 5600 /* Initialize the context ID for an L2 TX chain. */ 5601 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5602 /* Set the CID type to support an L2 connection. */ 5603 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5604 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5605 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5606 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5607 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5608 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5609 5610 /* Point the hardware to the first page in the chain. */ 5611 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5612 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5613 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5614 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5615 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5616 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5617 } else { 5618 /* Set the CID type to support an L2 connection. */ 5619 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5620 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5621 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5622 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5623 5624 /* Point the hardware to the first page in the chain. */ 5625 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5626 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5627 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5628 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5629 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5630 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5631 } 5632 5633 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5634 } 5635 5636 5637 /****************************************************************************/ 5638 /* Allocate memory and initialize the TX data structures. */ 5639 /* */ 5640 /* Returns: */ 5641 /* 0 for success, positive value for failure. */ 5642 /****************************************************************************/ 5643 static int 5644 bce_init_tx_chain(struct bce_softc *sc) 5645 { 5646 struct tx_bd *txbd; 5647 int i, rc = 0; 5648 5649 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5650 5651 /* Set the initial TX producer/consumer indices. */ 5652 sc->tx_prod = 0; 5653 sc->tx_cons = 0; 5654 sc->tx_prod_bseq = 0; 5655 sc->used_tx_bd = 0; 5656 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5657 DBRUN(sc->tx_hi_watermark = 0); 5658 DBRUN(sc->tx_full_count = 0); 5659 5660 /* 5661 * The NetXtreme II supports a linked-list structre called 5662 * a Buffer Descriptor Chain (or BD chain). A BD chain 5663 * consists of a series of 1 or more chain pages, each of which 5664 * consists of a fixed number of BD entries. 5665 * The last BD entry on each page is a pointer to the next page 5666 * in the chain, and the last pointer in the BD chain 5667 * points back to the beginning of the chain. 5668 */ 5669 5670 /* Set the TX next pointer chain entries. */ 5671 for (i = 0; i < sc->tx_pages; i++) { 5672 int j; 5673 5674 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5675 5676 /* Check if we've reached the last page. */ 5677 if (i == (sc->tx_pages - 1)) 5678 j = 0; 5679 else 5680 j = i + 1; 5681 5682 txbd->tx_bd_haddr_hi = 5683 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5684 txbd->tx_bd_haddr_lo = 5685 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5686 } 5687 5688 bce_init_tx_context(sc); 5689 5690 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5691 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5692 5693 return(rc); 5694 } 5695 5696 5697 /****************************************************************************/ 5698 /* Free memory and clear the TX data structures. */ 5699 /* */ 5700 /* Returns: */ 5701 /* Nothing. */ 5702 /****************************************************************************/ 5703 static void 5704 bce_free_tx_chain(struct bce_softc *sc) 5705 { 5706 int i; 5707 5708 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5709 5710 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5711 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5712 if (sc->tx_mbuf_ptr[i] != NULL) { 5713 if (sc->tx_mbuf_map[i] != NULL) 5714 bus_dmamap_sync(sc->tx_mbuf_tag, 5715 sc->tx_mbuf_map[i], 5716 BUS_DMASYNC_POSTWRITE); 5717 m_freem(sc->tx_mbuf_ptr[i]); 5718 sc->tx_mbuf_ptr[i] = NULL; 5719 DBRUN(sc->debug_tx_mbuf_alloc--); 5720 } 5721 } 5722 5723 /* Clear each TX chain page. */ 5724 for (i = 0; i < sc->tx_pages; i++) 5725 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5726 5727 sc->used_tx_bd = 0; 5728 5729 /* Check if we lost any mbufs in the process. */ 5730 DBRUNIF((sc->debug_tx_mbuf_alloc), 5731 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5732 "from tx chain!\n", __FILE__, __LINE__, 5733 sc->debug_tx_mbuf_alloc)); 5734 5735 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5736 } 5737 5738 5739 /****************************************************************************/ 5740 /* Initialize the RX context memory. */ 5741 /* */ 5742 /* Returns: */ 5743 /* Nothing */ 5744 /****************************************************************************/ 5745 static void 5746 bce_init_rx_context(struct bce_softc *sc) 5747 { 5748 u32 val; 5749 5750 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5751 5752 /* Init the type, size, and BD cache levels for the RX context. */ 5753 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5754 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5755 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5756 5757 /* 5758 * Set the level for generating pause frames 5759 * when the number of available rx_bd's gets 5760 * too low (the low watermark) and the level 5761 * when pause frames can be stopped (the high 5762 * watermark). 5763 */ 5764 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5765 u32 lo_water, hi_water; 5766 5767 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5768 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5769 } else { 5770 lo_water = 0; 5771 } 5772 5773 if (lo_water >= USABLE_RX_BD_ALLOC) { 5774 lo_water = 0; 5775 } 5776 5777 hi_water = USABLE_RX_BD_ALLOC / 4; 5778 5779 if (hi_water <= lo_water) { 5780 lo_water = 0; 5781 } 5782 5783 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5784 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5785 5786 if (hi_water > 0xf) 5787 hi_water = 0xf; 5788 else if (hi_water == 0) 5789 lo_water = 0; 5790 5791 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5792 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5793 } 5794 5795 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5796 5797 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5798 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5799 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5800 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5801 } 5802 5803 /* Point the hardware to the first page in the chain. */ 5804 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5805 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5806 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5807 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5808 5809 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5810 } 5811 5812 5813 /****************************************************************************/ 5814 /* Allocate memory and initialize the RX data structures. */ 5815 /* */ 5816 /* Returns: */ 5817 /* 0 for success, positive value for failure. */ 5818 /****************************************************************************/ 5819 static int 5820 bce_init_rx_chain(struct bce_softc *sc) 5821 { 5822 struct rx_bd *rxbd; 5823 int i, rc = 0; 5824 5825 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5826 BCE_VERBOSE_CTX); 5827 5828 /* Initialize the RX producer and consumer indices. */ 5829 sc->rx_prod = 0; 5830 sc->rx_cons = 0; 5831 sc->rx_prod_bseq = 0; 5832 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5833 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5834 5835 /* Initialize the RX next pointer chain entries. */ 5836 for (i = 0; i < sc->rx_pages; i++) { 5837 int j; 5838 5839 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5840 5841 /* Check if we've reached the last page. */ 5842 if (i == (sc->rx_pages - 1)) 5843 j = 0; 5844 else 5845 j = i + 1; 5846 5847 /* Setup the chain page pointers. */ 5848 rxbd->rx_bd_haddr_hi = 5849 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5850 rxbd->rx_bd_haddr_lo = 5851 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5852 } 5853 5854 /* Fill up the RX chain. */ 5855 bce_fill_rx_chain(sc); 5856 5857 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5858 DBRUN(sc->rx_empty_count = 0); 5859 for (i = 0; i < sc->rx_pages; i++) { 5860 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5861 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5862 } 5863 5864 bce_init_rx_context(sc); 5865 5866 DBRUNMSG(BCE_EXTREME_RECV, 5867 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5868 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5869 BCE_VERBOSE_CTX); 5870 5871 /* ToDo: Are there possible failure modes here? */ 5872 5873 return(rc); 5874 } 5875 5876 5877 /****************************************************************************/ 5878 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5879 /* occurs. */ 5880 /* */ 5881 /* Returns: */ 5882 /* Nothing */ 5883 /****************************************************************************/ 5884 static void 5885 bce_fill_rx_chain(struct bce_softc *sc) 5886 { 5887 u16 prod, prod_idx; 5888 u32 prod_bseq; 5889 5890 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5891 BCE_VERBOSE_CTX); 5892 5893 /* Get the RX chain producer indices. */ 5894 prod = sc->rx_prod; 5895 prod_bseq = sc->rx_prod_bseq; 5896 5897 /* Keep filling the RX chain until it's full. */ 5898 while (sc->free_rx_bd > 0) { 5899 prod_idx = RX_CHAIN_IDX(prod); 5900 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5901 /* Bail out if we can't add an mbuf to the chain. */ 5902 break; 5903 } 5904 prod = NEXT_RX_BD(prod); 5905 } 5906 5907 /* Save the RX chain producer indices. */ 5908 sc->rx_prod = prod; 5909 sc->rx_prod_bseq = prod_bseq; 5910 5911 /* We should never end up pointing to a next page pointer. */ 5912 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5913 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5914 __FUNCTION__, rx_prod)); 5915 5916 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5917 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5918 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5919 5920 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5921 BCE_VERBOSE_CTX); 5922 } 5923 5924 5925 /****************************************************************************/ 5926 /* Free memory and clear the RX data structures. */ 5927 /* */ 5928 /* Returns: */ 5929 /* Nothing. */ 5930 /****************************************************************************/ 5931 static void 5932 bce_free_rx_chain(struct bce_softc *sc) 5933 { 5934 int i; 5935 5936 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5937 5938 /* Free any mbufs still in the RX mbuf chain. */ 5939 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5940 if (sc->rx_mbuf_ptr[i] != NULL) { 5941 if (sc->rx_mbuf_map[i] != NULL) 5942 bus_dmamap_sync(sc->rx_mbuf_tag, 5943 sc->rx_mbuf_map[i], 5944 BUS_DMASYNC_POSTREAD); 5945 m_freem(sc->rx_mbuf_ptr[i]); 5946 sc->rx_mbuf_ptr[i] = NULL; 5947 DBRUN(sc->debug_rx_mbuf_alloc--); 5948 } 5949 } 5950 5951 /* Clear each RX chain page. */ 5952 for (i = 0; i < sc->rx_pages; i++) 5953 if (sc->rx_bd_chain[i] != NULL) 5954 bzero((char *)sc->rx_bd_chain[i], 5955 BCE_RX_CHAIN_PAGE_SZ); 5956 5957 sc->free_rx_bd = sc->max_rx_bd; 5958 5959 /* Check if we lost any mbufs in the process. */ 5960 DBRUNIF((sc->debug_rx_mbuf_alloc), 5961 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5962 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5963 5964 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5965 } 5966 5967 5968 /****************************************************************************/ 5969 /* Allocate memory and initialize the page data structures. */ 5970 /* Assumes that bce_init_rx_chain() has not already been called. */ 5971 /* */ 5972 /* Returns: */ 5973 /* 0 for success, positive value for failure. */ 5974 /****************************************************************************/ 5975 static int 5976 bce_init_pg_chain(struct bce_softc *sc) 5977 { 5978 struct rx_bd *pgbd; 5979 int i, rc = 0; 5980 u32 val; 5981 5982 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5983 BCE_VERBOSE_CTX); 5984 5985 /* Initialize the page producer and consumer indices. */ 5986 sc->pg_prod = 0; 5987 sc->pg_cons = 0; 5988 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5989 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5990 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5991 DBRUN(sc->pg_empty_count = 0); 5992 5993 /* Initialize the page next pointer chain entries. */ 5994 for (i = 0; i < sc->pg_pages; i++) { 5995 int j; 5996 5997 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5998 5999 /* Check if we've reached the last page. */ 6000 if (i == (sc->pg_pages - 1)) 6001 j = 0; 6002 else 6003 j = i + 1; 6004 6005 /* Setup the chain page pointers. */ 6006 pgbd->rx_bd_haddr_hi = 6007 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 6008 pgbd->rx_bd_haddr_lo = 6009 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 6010 } 6011 6012 /* Setup the MQ BIN mapping for host_pg_bidx. */ 6013 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 6014 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 6015 6016 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 6017 6018 /* Configure the rx_bd and page chain mbuf cluster size. */ 6019 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 6020 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 6021 6022 /* Configure the context reserved for jumbo support. */ 6023 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 6024 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 6025 6026 /* Point the hardware to the first page in the page chain. */ 6027 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 6028 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 6029 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 6030 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 6031 6032 /* Fill up the page chain. */ 6033 bce_fill_pg_chain(sc); 6034 6035 for (i = 0; i < sc->pg_pages; i++) { 6036 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6037 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6038 } 6039 6040 DBRUNMSG(BCE_EXTREME_RECV, 6041 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6042 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6043 BCE_VERBOSE_CTX); 6044 return(rc); 6045 } 6046 6047 6048 /****************************************************************************/ 6049 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 6050 /* occurs. */ 6051 /* */ 6052 /* Returns: */ 6053 /* Nothing */ 6054 /****************************************************************************/ 6055 static void 6056 bce_fill_pg_chain(struct bce_softc *sc) 6057 { 6058 u16 prod, prod_idx; 6059 6060 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6061 BCE_VERBOSE_CTX); 6062 6063 /* Get the page chain prodcuer index. */ 6064 prod = sc->pg_prod; 6065 6066 /* Keep filling the page chain until it's full. */ 6067 while (sc->free_pg_bd > 0) { 6068 prod_idx = PG_CHAIN_IDX(prod); 6069 if (bce_get_pg_buf(sc, prod, prod_idx)) { 6070 /* Bail out if we can't add an mbuf to the chain. */ 6071 break; 6072 } 6073 prod = NEXT_PG_BD(prod); 6074 } 6075 6076 /* Save the page chain producer index. */ 6077 sc->pg_prod = prod; 6078 6079 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6080 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6081 __FUNCTION__, pg_prod)); 6082 6083 /* 6084 * Write the mailbox and tell the chip about 6085 * the new rx_bd's in the page chain. 6086 */ 6087 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 6088 prod); 6089 6090 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6091 BCE_VERBOSE_CTX); 6092 } 6093 6094 6095 /****************************************************************************/ 6096 /* Free memory and clear the RX data structures. */ 6097 /* */ 6098 /* Returns: */ 6099 /* Nothing. */ 6100 /****************************************************************************/ 6101 static void 6102 bce_free_pg_chain(struct bce_softc *sc) 6103 { 6104 int i; 6105 6106 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6107 6108 /* Free any mbufs still in the mbuf page chain. */ 6109 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6110 if (sc->pg_mbuf_ptr[i] != NULL) { 6111 if (sc->pg_mbuf_map[i] != NULL) 6112 bus_dmamap_sync(sc->pg_mbuf_tag, 6113 sc->pg_mbuf_map[i], 6114 BUS_DMASYNC_POSTREAD); 6115 m_freem(sc->pg_mbuf_ptr[i]); 6116 sc->pg_mbuf_ptr[i] = NULL; 6117 DBRUN(sc->debug_pg_mbuf_alloc--); 6118 } 6119 } 6120 6121 /* Clear each page chain pages. */ 6122 for (i = 0; i < sc->pg_pages; i++) 6123 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6124 6125 sc->free_pg_bd = sc->max_pg_bd; 6126 6127 /* Check if we lost any mbufs in the process. */ 6128 DBRUNIF((sc->debug_pg_mbuf_alloc), 6129 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6130 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6131 6132 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6133 } 6134 6135 6136 static u32 6137 bce_get_rphy_link(struct bce_softc *sc) 6138 { 6139 u32 advertise, link; 6140 int fdpx; 6141 6142 advertise = 0; 6143 fdpx = 0; 6144 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6145 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6146 else 6147 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6148 if (link & BCE_NETLINK_ANEG_ENB) 6149 advertise |= BCE_NETLINK_ANEG_ENB; 6150 if (link & BCE_NETLINK_SPEED_10HALF) 6151 advertise |= BCE_NETLINK_SPEED_10HALF; 6152 if (link & BCE_NETLINK_SPEED_10FULL) { 6153 advertise |= BCE_NETLINK_SPEED_10FULL; 6154 fdpx++; 6155 } 6156 if (link & BCE_NETLINK_SPEED_100HALF) 6157 advertise |= BCE_NETLINK_SPEED_100HALF; 6158 if (link & BCE_NETLINK_SPEED_100FULL) { 6159 advertise |= BCE_NETLINK_SPEED_100FULL; 6160 fdpx++; 6161 } 6162 if (link & BCE_NETLINK_SPEED_1000HALF) 6163 advertise |= BCE_NETLINK_SPEED_1000HALF; 6164 if (link & BCE_NETLINK_SPEED_1000FULL) { 6165 advertise |= BCE_NETLINK_SPEED_1000FULL; 6166 fdpx++; 6167 } 6168 if (link & BCE_NETLINK_SPEED_2500HALF) 6169 advertise |= BCE_NETLINK_SPEED_2500HALF; 6170 if (link & BCE_NETLINK_SPEED_2500FULL) { 6171 advertise |= BCE_NETLINK_SPEED_2500FULL; 6172 fdpx++; 6173 } 6174 if (fdpx) 6175 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6176 BCE_NETLINK_FC_PAUSE_ASYM; 6177 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6178 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6179 BCE_NETLINK_ETH_AT_WIRESPEED; 6180 6181 return (advertise); 6182 } 6183 6184 6185 /****************************************************************************/ 6186 /* Set media options. */ 6187 /* */ 6188 /* Returns: */ 6189 /* 0 for success, positive value for failure. */ 6190 /****************************************************************************/ 6191 static int 6192 bce_ifmedia_upd(struct ifnet *ifp) 6193 { 6194 struct bce_softc *sc = ifp->if_softc; 6195 int error; 6196 6197 DBENTER(BCE_VERBOSE); 6198 6199 BCE_LOCK(sc); 6200 error = bce_ifmedia_upd_locked(ifp); 6201 BCE_UNLOCK(sc); 6202 6203 DBEXIT(BCE_VERBOSE); 6204 return (error); 6205 } 6206 6207 6208 /****************************************************************************/ 6209 /* Set media options. */ 6210 /* */ 6211 /* Returns: */ 6212 /* Nothing. */ 6213 /****************************************************************************/ 6214 static int 6215 bce_ifmedia_upd_locked(struct ifnet *ifp) 6216 { 6217 struct bce_softc *sc = ifp->if_softc; 6218 struct mii_data *mii; 6219 struct mii_softc *miisc; 6220 struct ifmedia *ifm; 6221 u32 link; 6222 int error, fdx; 6223 6224 DBENTER(BCE_VERBOSE_PHY); 6225 6226 error = 0; 6227 BCE_LOCK_ASSERT(sc); 6228 6229 sc->bce_link_up = FALSE; 6230 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6231 ifm = &sc->bce_ifmedia; 6232 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6233 return (EINVAL); 6234 link = 0; 6235 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6236 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6237 case IFM_AUTO: 6238 /* 6239 * Check advertised link of remote PHY by reading 6240 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6241 * Always use the same link type of remote PHY. 6242 */ 6243 link = bce_get_rphy_link(sc); 6244 break; 6245 case IFM_2500_SX: 6246 if ((sc->bce_phy_flags & 6247 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6248 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6249 return (EINVAL); 6250 /* 6251 * XXX 6252 * Have to enable forced 2.5Gbps configuration. 6253 */ 6254 if (fdx != 0) 6255 link |= BCE_NETLINK_SPEED_2500FULL; 6256 else 6257 link |= BCE_NETLINK_SPEED_2500HALF; 6258 break; 6259 case IFM_1000_SX: 6260 if ((sc->bce_phy_flags & 6261 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6262 return (EINVAL); 6263 /* 6264 * XXX 6265 * Have to disable 2.5Gbps configuration. 6266 */ 6267 if (fdx != 0) 6268 link = BCE_NETLINK_SPEED_1000FULL; 6269 else 6270 link = BCE_NETLINK_SPEED_1000HALF; 6271 break; 6272 case IFM_1000_T: 6273 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6274 return (EINVAL); 6275 if (fdx != 0) 6276 link = BCE_NETLINK_SPEED_1000FULL; 6277 else 6278 link = BCE_NETLINK_SPEED_1000HALF; 6279 break; 6280 case IFM_100_TX: 6281 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6282 return (EINVAL); 6283 if (fdx != 0) 6284 link = BCE_NETLINK_SPEED_100FULL; 6285 else 6286 link = BCE_NETLINK_SPEED_100HALF; 6287 break; 6288 case IFM_10_T: 6289 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6290 return (EINVAL); 6291 if (fdx != 0) 6292 link = BCE_NETLINK_SPEED_10FULL; 6293 else 6294 link = BCE_NETLINK_SPEED_10HALF; 6295 break; 6296 default: 6297 return (EINVAL); 6298 } 6299 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6300 /* 6301 * XXX 6302 * Advertise pause capability for full-duplex media. 6303 */ 6304 if (fdx != 0) 6305 link |= BCE_NETLINK_FC_PAUSE_SYM | 6306 BCE_NETLINK_FC_PAUSE_ASYM; 6307 if ((sc->bce_phy_flags & 6308 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6309 link |= BCE_NETLINK_PHY_APP_REMOTE | 6310 BCE_NETLINK_ETH_AT_WIRESPEED; 6311 } 6312 6313 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6314 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6315 } else { 6316 mii = device_get_softc(sc->bce_miibus); 6317 6318 /* Make sure the MII bus has been enumerated. */ 6319 if (mii) { 6320 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6321 PHY_RESET(miisc); 6322 error = mii_mediachg(mii); 6323 } 6324 } 6325 6326 DBEXIT(BCE_VERBOSE_PHY); 6327 return (error); 6328 } 6329 6330 6331 static void 6332 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6333 { 6334 struct ifnet *ifp; 6335 u32 link; 6336 6337 ifp = sc->bce_ifp; 6338 BCE_LOCK_ASSERT(sc); 6339 6340 ifmr->ifm_status = IFM_AVALID; 6341 ifmr->ifm_active = IFM_ETHER; 6342 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6343 /* XXX Handle heart beat status? */ 6344 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6345 ifmr->ifm_status |= IFM_ACTIVE; 6346 else { 6347 ifmr->ifm_active |= IFM_NONE; 6348 ifp->if_baudrate = 0; 6349 return; 6350 } 6351 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6352 case BCE_LINK_STATUS_10HALF: 6353 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6354 ifp->if_baudrate = IF_Mbps(10UL); 6355 break; 6356 case BCE_LINK_STATUS_10FULL: 6357 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6358 ifp->if_baudrate = IF_Mbps(10UL); 6359 break; 6360 case BCE_LINK_STATUS_100HALF: 6361 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6362 ifp->if_baudrate = IF_Mbps(100UL); 6363 break; 6364 case BCE_LINK_STATUS_100FULL: 6365 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6366 ifp->if_baudrate = IF_Mbps(100UL); 6367 break; 6368 case BCE_LINK_STATUS_1000HALF: 6369 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6370 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6371 else 6372 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6373 ifp->if_baudrate = IF_Mbps(1000UL); 6374 break; 6375 case BCE_LINK_STATUS_1000FULL: 6376 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6377 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6378 else 6379 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6380 ifp->if_baudrate = IF_Mbps(1000UL); 6381 break; 6382 case BCE_LINK_STATUS_2500HALF: 6383 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6384 ifmr->ifm_active |= IFM_NONE; 6385 return; 6386 } else 6387 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6388 ifp->if_baudrate = IF_Mbps(2500UL); 6389 break; 6390 case BCE_LINK_STATUS_2500FULL: 6391 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6392 ifmr->ifm_active |= IFM_NONE; 6393 return; 6394 } else 6395 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6396 ifp->if_baudrate = IF_Mbps(2500UL); 6397 break; 6398 default: 6399 ifmr->ifm_active |= IFM_NONE; 6400 return; 6401 } 6402 6403 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6404 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6405 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6406 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6407 } 6408 6409 6410 /****************************************************************************/ 6411 /* Reports current media status. */ 6412 /* */ 6413 /* Returns: */ 6414 /* Nothing. */ 6415 /****************************************************************************/ 6416 static void 6417 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6418 { 6419 struct bce_softc *sc = ifp->if_softc; 6420 struct mii_data *mii; 6421 6422 DBENTER(BCE_VERBOSE_PHY); 6423 6424 BCE_LOCK(sc); 6425 6426 if ((ifp->if_flags & IFF_UP) == 0) { 6427 BCE_UNLOCK(sc); 6428 return; 6429 } 6430 6431 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6432 bce_ifmedia_sts_rphy(sc, ifmr); 6433 else { 6434 mii = device_get_softc(sc->bce_miibus); 6435 mii_pollstat(mii); 6436 ifmr->ifm_active = mii->mii_media_active; 6437 ifmr->ifm_status = mii->mii_media_status; 6438 } 6439 6440 BCE_UNLOCK(sc); 6441 6442 DBEXIT(BCE_VERBOSE_PHY); 6443 } 6444 6445 6446 /****************************************************************************/ 6447 /* Handles PHY generated interrupt events. */ 6448 /* */ 6449 /* Returns: */ 6450 /* Nothing. */ 6451 /****************************************************************************/ 6452 static void 6453 bce_phy_intr(struct bce_softc *sc) 6454 { 6455 u32 new_link_state, old_link_state; 6456 6457 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6458 6459 DBRUN(sc->phy_interrupts++); 6460 6461 new_link_state = sc->status_block->status_attn_bits & 6462 STATUS_ATTN_BITS_LINK_STATE; 6463 old_link_state = sc->status_block->status_attn_bits_ack & 6464 STATUS_ATTN_BITS_LINK_STATE; 6465 6466 /* Handle any changes if the link state has changed. */ 6467 if (new_link_state != old_link_state) { 6468 6469 /* Update the status_attn_bits_ack field. */ 6470 if (new_link_state) { 6471 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6472 STATUS_ATTN_BITS_LINK_STATE); 6473 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6474 __FUNCTION__); 6475 } else { 6476 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6477 STATUS_ATTN_BITS_LINK_STATE); 6478 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6479 __FUNCTION__); 6480 } 6481 6482 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6483 if (new_link_state) { 6484 if (bootverbose) 6485 if_printf(sc->bce_ifp, "link UP\n"); 6486 if_link_state_change(sc->bce_ifp, 6487 LINK_STATE_UP); 6488 } else { 6489 if (bootverbose) 6490 if_printf(sc->bce_ifp, "link DOWN\n"); 6491 if_link_state_change(sc->bce_ifp, 6492 LINK_STATE_DOWN); 6493 } 6494 } 6495 /* 6496 * Assume link is down and allow 6497 * tick routine to update the state 6498 * based on the actual media state. 6499 */ 6500 sc->bce_link_up = FALSE; 6501 callout_stop(&sc->bce_tick_callout); 6502 bce_tick(sc); 6503 } 6504 6505 /* Acknowledge the link change interrupt. */ 6506 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6507 6508 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6509 } 6510 6511 6512 /****************************************************************************/ 6513 /* Reads the receive consumer value from the status block (skipping over */ 6514 /* chain page pointer if necessary). */ 6515 /* */ 6516 /* Returns: */ 6517 /* hw_cons */ 6518 /****************************************************************************/ 6519 static inline u16 6520 bce_get_hw_rx_cons(struct bce_softc *sc) 6521 { 6522 u16 hw_cons; 6523 6524 rmb(); 6525 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6526 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6527 hw_cons++; 6528 6529 return hw_cons; 6530 } 6531 6532 /****************************************************************************/ 6533 /* Handles received frame interrupt events. */ 6534 /* */ 6535 /* Returns: */ 6536 /* Nothing. */ 6537 /****************************************************************************/ 6538 static void 6539 bce_rx_intr(struct bce_softc *sc) 6540 { 6541 struct ifnet *ifp = sc->bce_ifp; 6542 struct l2_fhdr *l2fhdr; 6543 struct ether_vlan_header *vh; 6544 unsigned int pkt_len; 6545 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6546 u32 status; 6547 unsigned int rem_len; 6548 u16 sw_pg_cons, sw_pg_cons_idx; 6549 6550 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6551 DBRUN(sc->interrupts_rx++); 6552 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6553 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6554 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6555 6556 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6557 for (int i = 0; i < sc->rx_pages; i++) 6558 bus_dmamap_sync(sc->rx_bd_chain_tag, 6559 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6560 6561 /* Prepare the page chain pages to be accessed by the host CPU. */ 6562 if (bce_hdr_split == TRUE) { 6563 for (int i = 0; i < sc->pg_pages; i++) 6564 bus_dmamap_sync(sc->pg_bd_chain_tag, 6565 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6566 } 6567 6568 /* Get the hardware's view of the RX consumer index. */ 6569 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6570 6571 /* Get working copies of the driver's view of the consumer indices. */ 6572 sw_rx_cons = sc->rx_cons; 6573 sw_pg_cons = sc->pg_cons; 6574 6575 /* Update some debug statistics counters */ 6576 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6577 sc->rx_low_watermark = sc->free_rx_bd); 6578 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6579 sc->rx_empty_count++); 6580 6581 /* Scan through the receive chain as long as there is work to do */ 6582 /* ToDo: Consider setting a limit on the number of packets processed. */ 6583 rmb(); 6584 while (sw_rx_cons != hw_rx_cons) { 6585 struct mbuf *m0; 6586 6587 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6588 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6589 6590 /* Unmap the mbuf from DMA space. */ 6591 bus_dmamap_sync(sc->rx_mbuf_tag, 6592 sc->rx_mbuf_map[sw_rx_cons_idx], 6593 BUS_DMASYNC_POSTREAD); 6594 bus_dmamap_unload(sc->rx_mbuf_tag, 6595 sc->rx_mbuf_map[sw_rx_cons_idx]); 6596 6597 /* Remove the mbuf from the RX chain. */ 6598 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6599 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6600 DBRUN(sc->debug_rx_mbuf_alloc--); 6601 sc->free_rx_bd++; 6602 6603 /* 6604 * Frames received on the NetXteme II are prepended 6605 * with an l2_fhdr structure which provides status 6606 * information about the received frame (including 6607 * VLAN tags and checksum info). The frames are 6608 * also automatically adjusted to word align the IP 6609 * header (i.e. two null bytes are inserted before 6610 * the Ethernet header). As a result the data 6611 * DMA'd by the controller into the mbuf looks 6612 * like this: 6613 * 6614 * +---------+-----+---------------------+-----+ 6615 * | l2_fhdr | pad | packet data | FCS | 6616 * +---------+-----+---------------------+-----+ 6617 * 6618 * The l2_fhdr needs to be checked and skipped and 6619 * the FCS needs to be stripped before sending the 6620 * packet up the stack. 6621 */ 6622 l2fhdr = mtod(m0, struct l2_fhdr *); 6623 6624 /* Get the packet data + FCS length and the status. */ 6625 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6626 status = l2fhdr->l2_fhdr_status; 6627 6628 /* 6629 * Skip over the l2_fhdr and pad, resulting in the 6630 * following data in the mbuf: 6631 * +---------------------+-----+ 6632 * | packet data | FCS | 6633 * +---------------------+-----+ 6634 */ 6635 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6636 6637 /* 6638 * When split header mode is used, an ethernet frame 6639 * may be split across the receive chain and the 6640 * page chain. If that occurs an mbuf cluster must be 6641 * reassembled from the individual mbuf pieces. 6642 */ 6643 if (bce_hdr_split == TRUE) { 6644 /* 6645 * Check whether the received frame fits in a single 6646 * mbuf or not (i.e. packet data + FCS <= 6647 * sc->rx_bd_mbuf_data_len bytes). 6648 */ 6649 if (pkt_len > m0->m_len) { 6650 /* 6651 * The received frame is larger than a single mbuf. 6652 * If the frame was a TCP frame then only the TCP 6653 * header is placed in the mbuf, the remaining 6654 * payload (including FCS) is placed in the page 6655 * chain, the SPLIT flag is set, and the header 6656 * length is placed in the IP checksum field. 6657 * If the frame is not a TCP frame then the mbuf 6658 * is filled and the remaining bytes are placed 6659 * in the page chain. 6660 */ 6661 6662 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6663 "packet.\n", __FUNCTION__); 6664 DBRUN(sc->split_header_frames_rcvd++); 6665 6666 /* 6667 * When the page chain is enabled and the TCP 6668 * header has been split from the TCP payload, 6669 * the ip_xsum structure will reflect the length 6670 * of the TCP header, not the IP checksum. Set 6671 * the packet length of the mbuf accordingly. 6672 */ 6673 if (status & L2_FHDR_STATUS_SPLIT) { 6674 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6675 DBRUN(sc->split_header_tcp_frames_rcvd++); 6676 } 6677 6678 rem_len = pkt_len - m0->m_len; 6679 6680 /* Pull mbufs off the page chain for any remaining data. */ 6681 while (rem_len > 0) { 6682 struct mbuf *m_pg; 6683 6684 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6685 6686 /* Remove the mbuf from the page chain. */ 6687 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6688 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6689 DBRUN(sc->debug_pg_mbuf_alloc--); 6690 sc->free_pg_bd++; 6691 6692 /* Unmap the page chain mbuf from DMA space. */ 6693 bus_dmamap_sync(sc->pg_mbuf_tag, 6694 sc->pg_mbuf_map[sw_pg_cons_idx], 6695 BUS_DMASYNC_POSTREAD); 6696 bus_dmamap_unload(sc->pg_mbuf_tag, 6697 sc->pg_mbuf_map[sw_pg_cons_idx]); 6698 6699 /* Adjust the mbuf length. */ 6700 if (rem_len < m_pg->m_len) { 6701 /* The mbuf chain is complete. */ 6702 m_pg->m_len = rem_len; 6703 rem_len = 0; 6704 } else { 6705 /* More packet data is waiting. */ 6706 rem_len -= m_pg->m_len; 6707 } 6708 6709 /* Concatenate the mbuf cluster to the mbuf. */ 6710 m_cat(m0, m_pg); 6711 6712 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6713 } 6714 6715 /* Set the total packet length. */ 6716 m0->m_pkthdr.len = pkt_len; 6717 6718 } else { 6719 /* 6720 * The received packet is small and fits in a 6721 * single mbuf (i.e. the l2_fhdr + pad + packet + 6722 * FCS <= MHLEN). In other words, the packet is 6723 * 154 bytes or less in size. 6724 */ 6725 6726 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6727 "packet.\n", __FUNCTION__); 6728 6729 /* Set the total packet length. */ 6730 m0->m_pkthdr.len = m0->m_len = pkt_len; 6731 } 6732 } else 6733 /* Set the total packet length. */ 6734 m0->m_pkthdr.len = m0->m_len = pkt_len; 6735 6736 /* Remove the trailing Ethernet FCS. */ 6737 m_adj(m0, -ETHER_CRC_LEN); 6738 6739 /* Check that the resulting mbuf chain is valid. */ 6740 DBRUN(m_sanity(m0, FALSE)); 6741 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6742 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6743 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6744 m_print(m0, 128)); 6745 6746 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6747 sc->l2fhdr_error_sim_count++; 6748 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6749 6750 /* Check the received frame for errors. */ 6751 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6752 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6753 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6754 6755 /* Log the error and release the mbuf. */ 6756 sc->l2fhdr_error_count++; 6757 m_freem(m0); 6758 m0 = NULL; 6759 goto bce_rx_intr_next_rx; 6760 } 6761 6762 /* Send the packet to the appropriate interface. */ 6763 m0->m_pkthdr.rcvif = ifp; 6764 6765 /* Assume no hardware checksum. */ 6766 m0->m_pkthdr.csum_flags = 0; 6767 6768 /* Validate the checksum if offload enabled. */ 6769 if (ifp->if_capenable & IFCAP_RXCSUM) { 6770 /* Check for an IP datagram. */ 6771 if (!(status & L2_FHDR_STATUS_SPLIT) && 6772 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6773 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6774 DBRUN(sc->csum_offload_ip++); 6775 /* Check if the IP checksum is valid. */ 6776 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6777 m0->m_pkthdr.csum_flags |= 6778 CSUM_IP_VALID; 6779 } 6780 6781 /* Check for a valid TCP/UDP frame. */ 6782 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6783 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6784 6785 /* Check for a good TCP/UDP checksum. */ 6786 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6787 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6788 DBRUN(sc->csum_offload_tcp_udp++); 6789 m0->m_pkthdr.csum_data = 6790 l2fhdr->l2_fhdr_tcp_udp_xsum; 6791 m0->m_pkthdr.csum_flags |= 6792 (CSUM_DATA_VALID 6793 | CSUM_PSEUDO_HDR); 6794 } 6795 } 6796 } 6797 6798 /* Attach the VLAN tag. */ 6799 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6800 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6801 DBRUN(sc->vlan_tagged_frames_rcvd++); 6802 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6803 DBRUN(sc->vlan_tagged_frames_stripped++); 6804 #if __FreeBSD_version < 700000 6805 VLAN_INPUT_TAG(ifp, m0, 6806 l2fhdr->l2_fhdr_vlan_tag, continue); 6807 #else 6808 m0->m_pkthdr.ether_vtag = 6809 l2fhdr->l2_fhdr_vlan_tag; 6810 m0->m_flags |= M_VLANTAG; 6811 #endif 6812 } else { 6813 /* 6814 * bce(4) controllers can't disable VLAN 6815 * tag stripping if management firmware 6816 * (ASF/IPMI/UMP) is running. So we always 6817 * strip VLAN tag and manually reconstruct 6818 * the VLAN frame by appending stripped 6819 * VLAN tag in driver if VLAN tag stripping 6820 * was disabled. 6821 * 6822 * TODO: LLC SNAP handling. 6823 */ 6824 bcopy(mtod(m0, uint8_t *), 6825 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6826 ETHER_ADDR_LEN * 2); 6827 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6828 vh = mtod(m0, struct ether_vlan_header *); 6829 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6830 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6831 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6832 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6833 } 6834 } 6835 6836 /* Increment received packet statistics. */ 6837 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 6838 6839 bce_rx_intr_next_rx: 6840 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6841 6842 /* If we have a packet, pass it up the stack */ 6843 if (m0) { 6844 /* Make sure we don't lose our place when we release the lock. */ 6845 sc->rx_cons = sw_rx_cons; 6846 sc->pg_cons = sw_pg_cons; 6847 6848 BCE_UNLOCK(sc); 6849 (*ifp->if_input)(ifp, m0); 6850 BCE_LOCK(sc); 6851 6852 /* Recover our place. */ 6853 sw_rx_cons = sc->rx_cons; 6854 sw_pg_cons = sc->pg_cons; 6855 } 6856 6857 /* Refresh hw_cons to see if there's new work */ 6858 if (sw_rx_cons == hw_rx_cons) 6859 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6860 } 6861 6862 /* No new packets. Refill the page chain. */ 6863 if (bce_hdr_split == TRUE) { 6864 sc->pg_cons = sw_pg_cons; 6865 bce_fill_pg_chain(sc); 6866 } 6867 6868 /* No new packets. Refill the RX chain. */ 6869 sc->rx_cons = sw_rx_cons; 6870 bce_fill_rx_chain(sc); 6871 6872 /* Prepare the page chain pages to be accessed by the NIC. */ 6873 for (int i = 0; i < sc->rx_pages; i++) 6874 bus_dmamap_sync(sc->rx_bd_chain_tag, 6875 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6876 6877 if (bce_hdr_split == TRUE) { 6878 for (int i = 0; i < sc->pg_pages; i++) 6879 bus_dmamap_sync(sc->pg_bd_chain_tag, 6880 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6881 } 6882 6883 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6884 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6885 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6886 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6887 } 6888 6889 6890 /****************************************************************************/ 6891 /* Reads the transmit consumer value from the status block (skipping over */ 6892 /* chain page pointer if necessary). */ 6893 /* */ 6894 /* Returns: */ 6895 /* hw_cons */ 6896 /****************************************************************************/ 6897 static inline u16 6898 bce_get_hw_tx_cons(struct bce_softc *sc) 6899 { 6900 u16 hw_cons; 6901 6902 mb(); 6903 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6904 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6905 hw_cons++; 6906 6907 return hw_cons; 6908 } 6909 6910 6911 /****************************************************************************/ 6912 /* Handles transmit completion interrupt events. */ 6913 /* */ 6914 /* Returns: */ 6915 /* Nothing. */ 6916 /****************************************************************************/ 6917 static void 6918 bce_tx_intr(struct bce_softc *sc) 6919 { 6920 struct ifnet *ifp = sc->bce_ifp; 6921 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6922 6923 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6924 DBRUN(sc->interrupts_tx++); 6925 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6926 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6927 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6928 6929 BCE_LOCK_ASSERT(sc); 6930 6931 /* Get the hardware's view of the TX consumer index. */ 6932 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6933 sw_tx_cons = sc->tx_cons; 6934 6935 /* Prevent speculative reads of the status block. */ 6936 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6937 BUS_SPACE_BARRIER_READ); 6938 6939 /* Cycle through any completed TX chain page entries. */ 6940 while (sw_tx_cons != hw_tx_cons) { 6941 #ifdef BCE_DEBUG 6942 struct tx_bd *txbd = NULL; 6943 #endif 6944 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6945 6946 DBPRINT(sc, BCE_INFO_SEND, 6947 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6948 "sw_tx_chain_cons = 0x%04X\n", 6949 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6950 6951 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6952 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6953 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6954 (int) MAX_TX_BD_ALLOC); 6955 bce_breakpoint(sc)); 6956 6957 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6958 [TX_IDX(sw_tx_chain_cons)]); 6959 6960 DBRUNIF((txbd == NULL), 6961 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6962 __FILE__, __LINE__, sw_tx_chain_cons); 6963 bce_breakpoint(sc)); 6964 6965 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6966 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6967 6968 /* 6969 * Free the associated mbuf. Remember 6970 * that only the last tx_bd of a packet 6971 * has an mbuf pointer and DMA map. 6972 */ 6973 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6974 6975 /* Validate that this is the last tx_bd. */ 6976 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6977 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6978 "txmbuf == NULL!\n", __FILE__, __LINE__); 6979 bce_breakpoint(sc)); 6980 6981 DBRUNMSG(BCE_INFO_SEND, 6982 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6983 "from tx_bd[0x%04X]\n", __FUNCTION__, 6984 sw_tx_chain_cons)); 6985 6986 /* Unmap the mbuf. */ 6987 bus_dmamap_unload(sc->tx_mbuf_tag, 6988 sc->tx_mbuf_map[sw_tx_chain_cons]); 6989 6990 /* Free the mbuf. */ 6991 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6992 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6993 DBRUN(sc->debug_tx_mbuf_alloc--); 6994 6995 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 6996 } 6997 6998 sc->used_tx_bd--; 6999 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 7000 7001 /* Refresh hw_cons to see if there's new work. */ 7002 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 7003 7004 /* Prevent speculative reads of the status block. */ 7005 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7006 BUS_SPACE_BARRIER_READ); 7007 } 7008 7009 /* Clear the TX timeout timer. */ 7010 sc->watchdog_timer = 0; 7011 7012 /* Clear the tx hardware queue full flag. */ 7013 if (sc->used_tx_bd < sc->max_tx_bd) { 7014 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 7015 DBPRINT(sc, BCE_INFO_SEND, 7016 "%s(): Open TX chain! %d/%d (used/total)\n", 7017 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 7018 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7019 } 7020 7021 sc->tx_cons = sw_tx_cons; 7022 7023 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 7024 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 7025 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 7026 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 7027 } 7028 7029 7030 /****************************************************************************/ 7031 /* Disables interrupt generation. */ 7032 /* */ 7033 /* Returns: */ 7034 /* Nothing. */ 7035 /****************************************************************************/ 7036 static void 7037 bce_disable_intr(struct bce_softc *sc) 7038 { 7039 DBENTER(BCE_VERBOSE_INTR); 7040 7041 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7042 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 7043 7044 DBEXIT(BCE_VERBOSE_INTR); 7045 } 7046 7047 7048 /****************************************************************************/ 7049 /* Enables interrupt generation. */ 7050 /* */ 7051 /* Returns: */ 7052 /* Nothing. */ 7053 /****************************************************************************/ 7054 static void 7055 bce_enable_intr(struct bce_softc *sc, int coal_now) 7056 { 7057 DBENTER(BCE_VERBOSE_INTR); 7058 7059 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7060 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 7061 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 7062 7063 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7064 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 7065 7066 /* Force an immediate interrupt (whether there is new data or not). */ 7067 if (coal_now) 7068 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 7069 7070 DBEXIT(BCE_VERBOSE_INTR); 7071 } 7072 7073 7074 /****************************************************************************/ 7075 /* Handles controller initialization. */ 7076 /* */ 7077 /* Returns: */ 7078 /* Nothing. */ 7079 /****************************************************************************/ 7080 static void 7081 bce_init_locked(struct bce_softc *sc) 7082 { 7083 struct ifnet *ifp; 7084 u32 ether_mtu = 0; 7085 7086 DBENTER(BCE_VERBOSE_RESET); 7087 7088 BCE_LOCK_ASSERT(sc); 7089 7090 ifp = sc->bce_ifp; 7091 7092 /* Check if the driver is still running and bail out if it is. */ 7093 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7094 goto bce_init_locked_exit; 7095 7096 bce_stop(sc); 7097 7098 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 7099 BCE_PRINTF("%s(%d): Controller reset failed!\n", 7100 __FILE__, __LINE__); 7101 goto bce_init_locked_exit; 7102 } 7103 7104 if (bce_chipinit(sc)) { 7105 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 7106 __FILE__, __LINE__); 7107 goto bce_init_locked_exit; 7108 } 7109 7110 if (bce_blockinit(sc)) { 7111 BCE_PRINTF("%s(%d): Block initialization failed!\n", 7112 __FILE__, __LINE__); 7113 goto bce_init_locked_exit; 7114 } 7115 7116 /* Load our MAC address. */ 7117 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 7118 bce_set_mac_addr(sc); 7119 7120 if (bce_hdr_split == FALSE) 7121 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7122 /* 7123 * Calculate and program the hardware Ethernet MTU 7124 * size. Be generous on the receive if we have room 7125 * and allowed by the user. 7126 */ 7127 if (bce_strict_rx_mtu == TRUE) 7128 ether_mtu = ifp->if_mtu; 7129 else { 7130 if (bce_hdr_split == TRUE) { 7131 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES) 7132 ether_mtu = sc->rx_bd_mbuf_data_len + 7133 MCLBYTES; 7134 else 7135 ether_mtu = ifp->if_mtu; 7136 } else { 7137 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 7138 ether_mtu = sc->rx_bd_mbuf_data_len; 7139 else 7140 ether_mtu = ifp->if_mtu; 7141 } 7142 } 7143 7144 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7145 7146 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7147 __FUNCTION__, ether_mtu); 7148 7149 /* Program the mtu, enabling jumbo frame support if necessary. */ 7150 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7151 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7152 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7153 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7154 else 7155 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7156 7157 /* Program appropriate promiscuous/multicast filtering. */ 7158 bce_set_rx_mode(sc); 7159 7160 if (bce_hdr_split == TRUE) { 7161 /* Init page buffer descriptor chain. */ 7162 bce_init_pg_chain(sc); 7163 } 7164 7165 /* Init RX buffer descriptor chain. */ 7166 bce_init_rx_chain(sc); 7167 7168 /* Init TX buffer descriptor chain. */ 7169 bce_init_tx_chain(sc); 7170 7171 /* Enable host interrupts. */ 7172 bce_enable_intr(sc, 1); 7173 7174 bce_ifmedia_upd_locked(ifp); 7175 7176 /* Let the OS know the driver is up and running. */ 7177 ifp->if_drv_flags |= IFF_DRV_RUNNING; 7178 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7179 7180 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7181 7182 bce_init_locked_exit: 7183 DBEXIT(BCE_VERBOSE_RESET); 7184 } 7185 7186 7187 /****************************************************************************/ 7188 /* Initialize the controller just enough so that any management firmware */ 7189 /* running on the device will continue to operate correctly. */ 7190 /* */ 7191 /* Returns: */ 7192 /* Nothing. */ 7193 /****************************************************************************/ 7194 static void 7195 bce_mgmt_init_locked(struct bce_softc *sc) 7196 { 7197 struct ifnet *ifp; 7198 7199 DBENTER(BCE_VERBOSE_RESET); 7200 7201 BCE_LOCK_ASSERT(sc); 7202 7203 /* Bail out if management firmware is not running. */ 7204 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7205 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7206 "No management firmware running...\n"); 7207 goto bce_mgmt_init_locked_exit; 7208 } 7209 7210 ifp = sc->bce_ifp; 7211 7212 /* Enable all critical blocks in the MAC. */ 7213 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7214 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7215 DELAY(20); 7216 7217 bce_ifmedia_upd_locked(ifp); 7218 7219 bce_mgmt_init_locked_exit: 7220 DBEXIT(BCE_VERBOSE_RESET); 7221 } 7222 7223 7224 /****************************************************************************/ 7225 /* Handles controller initialization when called from an unlocked routine. */ 7226 /* */ 7227 /* Returns: */ 7228 /* Nothing. */ 7229 /****************************************************************************/ 7230 static void 7231 bce_init(void *xsc) 7232 { 7233 struct bce_softc *sc = xsc; 7234 7235 DBENTER(BCE_VERBOSE_RESET); 7236 7237 BCE_LOCK(sc); 7238 bce_init_locked(sc); 7239 BCE_UNLOCK(sc); 7240 7241 DBEXIT(BCE_VERBOSE_RESET); 7242 } 7243 7244 7245 /****************************************************************************/ 7246 /* Modifies an mbuf for TSO on the hardware. */ 7247 /* */ 7248 /* Returns: */ 7249 /* Pointer to a modified mbuf. */ 7250 /****************************************************************************/ 7251 static struct mbuf * 7252 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7253 { 7254 struct mbuf *m; 7255 struct ether_header *eh; 7256 struct ip *ip; 7257 struct tcphdr *th; 7258 u16 etype; 7259 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7260 7261 DBRUN(sc->tso_frames_requested++); 7262 7263 /* Controller may modify mbuf chains. */ 7264 if (M_WRITABLE(*m_head) == 0) { 7265 m = m_dup(*m_head, M_NOWAIT); 7266 m_freem(*m_head); 7267 if (m == NULL) { 7268 sc->mbuf_alloc_failed_count++; 7269 *m_head = NULL; 7270 return (NULL); 7271 } 7272 *m_head = m; 7273 } 7274 7275 /* 7276 * For TSO the controller needs two pieces of info, 7277 * the MSS and the IP+TCP options length. 7278 */ 7279 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7280 if (m == NULL) { 7281 *m_head = NULL; 7282 return (NULL); 7283 } 7284 eh = mtod(m, struct ether_header *); 7285 etype = ntohs(eh->ether_type); 7286 7287 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7288 switch (etype) { 7289 case ETHERTYPE_IP: 7290 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7291 /* TSO only supported for TCP protocol. */ 7292 if (ip->ip_p != IPPROTO_TCP) { 7293 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7294 __FILE__, __LINE__); 7295 m_freem(*m_head); 7296 *m_head = NULL; 7297 return (NULL); 7298 } 7299 7300 /* Get IP header length in bytes (min 20) */ 7301 ip_hlen = ip->ip_hl << 2; 7302 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7303 sizeof(struct tcphdr)); 7304 if (m == NULL) { 7305 *m_head = NULL; 7306 return (NULL); 7307 } 7308 7309 /* Get the TCP header length in bytes (min 20) */ 7310 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7311 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7312 tcp_hlen = (th->th_off << 2); 7313 7314 /* Make sure all IP/TCP options live in the same buffer. */ 7315 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7316 tcp_hlen); 7317 if (m == NULL) { 7318 *m_head = NULL; 7319 return (NULL); 7320 } 7321 7322 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7323 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7324 ip_len = ip->ip_len; 7325 ip->ip_len = 0; 7326 ip->ip_sum = 0; 7327 break; 7328 case ETHERTYPE_IPV6: 7329 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7330 __FILE__, __LINE__); 7331 m_freem(*m_head); 7332 *m_head = NULL; 7333 return (NULL); 7334 /* NOT REACHED */ 7335 default: 7336 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7337 __FILE__, __LINE__); 7338 m_freem(*m_head); 7339 *m_head = NULL; 7340 return (NULL); 7341 } 7342 7343 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7344 7345 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7346 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7347 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7348 tcp_hlen, ip_len); 7349 7350 /* Set the LSO flag in the TX BD */ 7351 *flags |= TX_BD_FLAGS_SW_LSO; 7352 7353 /* Set the length of IP + TCP options (in 32 bit words) */ 7354 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7355 sizeof(struct tcphdr)) >> 2) << 8); 7356 7357 DBRUN(sc->tso_frames_completed++); 7358 return (*m_head); 7359 } 7360 7361 7362 /****************************************************************************/ 7363 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7364 /* memory visible to the controller. */ 7365 /* */ 7366 /* Returns: */ 7367 /* 0 for success, positive value for failure. */ 7368 /* Modified: */ 7369 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7370 /****************************************************************************/ 7371 static int 7372 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7373 { 7374 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7375 bus_dmamap_t map; 7376 struct tx_bd *txbd = NULL; 7377 struct mbuf *m0; 7378 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7379 u32 prod_bseq; 7380 7381 #ifdef BCE_DEBUG 7382 u16 debug_prod; 7383 #endif 7384 7385 int i, error, nsegs, rc = 0; 7386 7387 DBENTER(BCE_VERBOSE_SEND); 7388 7389 /* Make sure we have room in the TX chain. */ 7390 if (sc->used_tx_bd >= sc->max_tx_bd) 7391 goto bce_tx_encap_exit; 7392 7393 /* Transfer any checksum offload flags to the bd. */ 7394 m0 = *m_head; 7395 if (m0->m_pkthdr.csum_flags) { 7396 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7397 m0 = bce_tso_setup(sc, m_head, &flags); 7398 if (m0 == NULL) { 7399 DBRUN(sc->tso_frames_failed++); 7400 goto bce_tx_encap_exit; 7401 } 7402 mss = htole16(m0->m_pkthdr.tso_segsz); 7403 } else { 7404 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7405 flags |= TX_BD_FLAGS_IP_CKSUM; 7406 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7407 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7408 } 7409 } 7410 7411 /* Transfer any VLAN tags to the bd. */ 7412 if (m0->m_flags & M_VLANTAG) { 7413 flags |= TX_BD_FLAGS_VLAN_TAG; 7414 vlan_tag = m0->m_pkthdr.ether_vtag; 7415 } 7416 7417 /* Map the mbuf into DMAable memory. */ 7418 prod = sc->tx_prod; 7419 chain_prod = TX_CHAIN_IDX(prod); 7420 map = sc->tx_mbuf_map[chain_prod]; 7421 7422 /* Map the mbuf into our DMA address space. */ 7423 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7424 segs, &nsegs, BUS_DMA_NOWAIT); 7425 7426 /* Check if the DMA mapping was successful */ 7427 if (error == EFBIG) { 7428 sc->mbuf_frag_count++; 7429 7430 /* Try to defrag the mbuf. */ 7431 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7432 if (m0 == NULL) { 7433 /* Defrag was unsuccessful */ 7434 m_freem(*m_head); 7435 *m_head = NULL; 7436 sc->mbuf_alloc_failed_count++; 7437 rc = ENOBUFS; 7438 goto bce_tx_encap_exit; 7439 } 7440 7441 /* Defrag was successful, try mapping again */ 7442 *m_head = m0; 7443 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7444 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7445 7446 /* Still getting an error after a defrag. */ 7447 if (error == ENOMEM) { 7448 /* Insufficient DMA buffers available. */ 7449 sc->dma_map_addr_tx_failed_count++; 7450 rc = error; 7451 goto bce_tx_encap_exit; 7452 } else if (error != 0) { 7453 /* Release it and return an error. */ 7454 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7455 "TX chain!\n", __FILE__, __LINE__); 7456 m_freem(m0); 7457 *m_head = NULL; 7458 sc->dma_map_addr_tx_failed_count++; 7459 rc = ENOBUFS; 7460 goto bce_tx_encap_exit; 7461 } 7462 } else if (error == ENOMEM) { 7463 /* Insufficient DMA buffers available. */ 7464 sc->dma_map_addr_tx_failed_count++; 7465 rc = error; 7466 goto bce_tx_encap_exit; 7467 } else if (error != 0) { 7468 m_freem(m0); 7469 *m_head = NULL; 7470 sc->dma_map_addr_tx_failed_count++; 7471 rc = error; 7472 goto bce_tx_encap_exit; 7473 } 7474 7475 /* Make sure there's room in the chain */ 7476 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7477 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7478 rc = ENOBUFS; 7479 goto bce_tx_encap_exit; 7480 } 7481 7482 /* prod points to an empty tx_bd at this point. */ 7483 prod_bseq = sc->tx_prod_bseq; 7484 7485 #ifdef BCE_DEBUG 7486 debug_prod = chain_prod; 7487 #endif 7488 7489 DBPRINT(sc, BCE_INFO_SEND, 7490 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7491 "prod_bseq = 0x%08X\n", 7492 __FUNCTION__, prod, chain_prod, prod_bseq); 7493 7494 /* 7495 * Cycle through each mbuf segment that makes up 7496 * the outgoing frame, gathering the mapping info 7497 * for that segment and creating a tx_bd for 7498 * the mbuf. 7499 */ 7500 for (i = 0; i < nsegs ; i++) { 7501 7502 chain_prod = TX_CHAIN_IDX(prod); 7503 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7504 [TX_IDX(chain_prod)]; 7505 7506 txbd->tx_bd_haddr_lo = 7507 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7508 txbd->tx_bd_haddr_hi = 7509 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7510 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7511 htole16(segs[i].ds_len); 7512 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7513 txbd->tx_bd_flags = htole16(flags); 7514 prod_bseq += segs[i].ds_len; 7515 if (i == 0) 7516 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7517 prod = NEXT_TX_BD(prod); 7518 } 7519 7520 /* Set the END flag on the last TX buffer descriptor. */ 7521 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7522 7523 DBRUNMSG(BCE_EXTREME_SEND, 7524 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7525 7526 /* 7527 * Ensure that the mbuf pointer for this transmission 7528 * is placed at the array index of the last 7529 * descriptor in this chain. This is done 7530 * because a single map is used for all 7531 * segments of the mbuf and we don't want to 7532 * unload the map before all of the segments 7533 * have been freed. 7534 */ 7535 sc->tx_mbuf_ptr[chain_prod] = m0; 7536 sc->used_tx_bd += nsegs; 7537 7538 /* Update some debug statistic counters */ 7539 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7540 sc->tx_hi_watermark = sc->used_tx_bd); 7541 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7542 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7543 7544 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7545 7546 /* prod points to the next free tx_bd at this point. */ 7547 sc->tx_prod = prod; 7548 sc->tx_prod_bseq = prod_bseq; 7549 7550 /* Tell the chip about the waiting TX frames. */ 7551 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7552 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7553 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7554 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7555 7556 bce_tx_encap_exit: 7557 DBEXIT(BCE_VERBOSE_SEND); 7558 return(rc); 7559 } 7560 7561 7562 /****************************************************************************/ 7563 /* Main transmit routine when called from another routine with a lock. */ 7564 /* */ 7565 /* Returns: */ 7566 /* Nothing. */ 7567 /****************************************************************************/ 7568 static void 7569 bce_start_locked(struct ifnet *ifp) 7570 { 7571 struct bce_softc *sc = ifp->if_softc; 7572 struct mbuf *m_head = NULL; 7573 int count = 0; 7574 u16 tx_prod, tx_chain_prod; 7575 7576 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7577 7578 BCE_LOCK_ASSERT(sc); 7579 7580 /* prod points to the next free tx_bd. */ 7581 tx_prod = sc->tx_prod; 7582 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7583 7584 DBPRINT(sc, BCE_INFO_SEND, 7585 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7586 "tx_prod_bseq = 0x%08X\n", 7587 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7588 7589 /* If there's no link or the transmit queue is empty then just exit. */ 7590 if (sc->bce_link_up == FALSE) { 7591 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7592 __FUNCTION__); 7593 goto bce_start_locked_exit; 7594 } 7595 7596 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7597 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7598 __FUNCTION__); 7599 goto bce_start_locked_exit; 7600 } 7601 7602 /* 7603 * Keep adding entries while there is space in the ring. 7604 */ 7605 while (sc->used_tx_bd < sc->max_tx_bd) { 7606 7607 /* Check for any frames to send. */ 7608 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7609 7610 /* Stop when the transmit queue is empty. */ 7611 if (m_head == NULL) 7612 break; 7613 7614 /* 7615 * Pack the data into the transmit ring. If we 7616 * don't have room, place the mbuf back at the 7617 * head of the queue and set the OACTIVE flag 7618 * to wait for the NIC to drain the chain. 7619 */ 7620 if (bce_tx_encap(sc, &m_head)) { 7621 if (m_head != NULL) 7622 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7623 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7624 DBPRINT(sc, BCE_INFO_SEND, 7625 "TX chain is closed for business! Total " 7626 "tx_bd used = %d\n", sc->used_tx_bd); 7627 break; 7628 } 7629 7630 count++; 7631 7632 /* Send a copy of the frame to any BPF listeners. */ 7633 ETHER_BPF_MTAP(ifp, m_head); 7634 } 7635 7636 /* Exit if no packets were dequeued. */ 7637 if (count == 0) { 7638 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7639 "dequeued\n", __FUNCTION__); 7640 goto bce_start_locked_exit; 7641 } 7642 7643 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7644 "send queue.\n", __FUNCTION__, count); 7645 7646 /* Set the tx timeout. */ 7647 sc->watchdog_timer = BCE_TX_TIMEOUT; 7648 7649 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7650 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7651 7652 bce_start_locked_exit: 7653 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7654 } 7655 7656 7657 /****************************************************************************/ 7658 /* Main transmit routine when called from another routine without a lock. */ 7659 /* */ 7660 /* Returns: */ 7661 /* Nothing. */ 7662 /****************************************************************************/ 7663 static void 7664 bce_start(struct ifnet *ifp) 7665 { 7666 struct bce_softc *sc = ifp->if_softc; 7667 7668 DBENTER(BCE_VERBOSE_SEND); 7669 7670 BCE_LOCK(sc); 7671 bce_start_locked(ifp); 7672 BCE_UNLOCK(sc); 7673 7674 DBEXIT(BCE_VERBOSE_SEND); 7675 } 7676 7677 7678 /****************************************************************************/ 7679 /* Handles any IOCTL calls from the operating system. */ 7680 /* */ 7681 /* Returns: */ 7682 /* 0 for success, positive value for failure. */ 7683 /****************************************************************************/ 7684 static int 7685 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7686 { 7687 struct bce_softc *sc = ifp->if_softc; 7688 struct ifreq *ifr = (struct ifreq *) data; 7689 struct mii_data *mii; 7690 int mask, error = 0; 7691 7692 DBENTER(BCE_VERBOSE_MISC); 7693 7694 switch(command) { 7695 7696 /* Set the interface MTU. */ 7697 case SIOCSIFMTU: 7698 /* Check that the MTU setting is supported. */ 7699 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7700 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7701 error = EINVAL; 7702 break; 7703 } 7704 7705 DBPRINT(sc, BCE_INFO_MISC, 7706 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7707 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7708 7709 BCE_LOCK(sc); 7710 ifp->if_mtu = ifr->ifr_mtu; 7711 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7712 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7713 bce_init_locked(sc); 7714 } 7715 BCE_UNLOCK(sc); 7716 break; 7717 7718 /* Set interface flags. */ 7719 case SIOCSIFFLAGS: 7720 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7721 7722 BCE_LOCK(sc); 7723 7724 /* Check if the interface is up. */ 7725 if (ifp->if_flags & IFF_UP) { 7726 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7727 /* Change promiscuous/multicast flags as necessary. */ 7728 bce_set_rx_mode(sc); 7729 } else { 7730 /* Start the HW */ 7731 bce_init_locked(sc); 7732 } 7733 } else { 7734 /* The interface is down, check if driver is running. */ 7735 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7736 bce_stop(sc); 7737 7738 /* If MFW is running, restart the controller a bit. */ 7739 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7740 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7741 bce_chipinit(sc); 7742 bce_mgmt_init_locked(sc); 7743 } 7744 } 7745 } 7746 7747 BCE_UNLOCK(sc); 7748 break; 7749 7750 /* Add/Delete multicast address */ 7751 case SIOCADDMULTI: 7752 case SIOCDELMULTI: 7753 DBPRINT(sc, BCE_VERBOSE_MISC, 7754 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7755 7756 BCE_LOCK(sc); 7757 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7758 bce_set_rx_mode(sc); 7759 BCE_UNLOCK(sc); 7760 7761 break; 7762 7763 /* Set/Get Interface media */ 7764 case SIOCSIFMEDIA: 7765 case SIOCGIFMEDIA: 7766 DBPRINT(sc, BCE_VERBOSE_MISC, 7767 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7768 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7769 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7770 command); 7771 else { 7772 mii = device_get_softc(sc->bce_miibus); 7773 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7774 command); 7775 } 7776 break; 7777 7778 /* Set interface capability */ 7779 case SIOCSIFCAP: 7780 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7781 DBPRINT(sc, BCE_INFO_MISC, 7782 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7783 7784 /* Toggle the TX checksum capabilities enable flag. */ 7785 if (mask & IFCAP_TXCSUM && 7786 ifp->if_capabilities & IFCAP_TXCSUM) { 7787 ifp->if_capenable ^= IFCAP_TXCSUM; 7788 if (IFCAP_TXCSUM & ifp->if_capenable) 7789 ifp->if_hwassist |= BCE_IF_HWASSIST; 7790 else 7791 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7792 } 7793 7794 /* Toggle the RX checksum capabilities enable flag. */ 7795 if (mask & IFCAP_RXCSUM && 7796 ifp->if_capabilities & IFCAP_RXCSUM) 7797 ifp->if_capenable ^= IFCAP_RXCSUM; 7798 7799 /* Toggle the TSO capabilities enable flag. */ 7800 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7801 ifp->if_capabilities & IFCAP_TSO4) { 7802 ifp->if_capenable ^= IFCAP_TSO4; 7803 if (IFCAP_TSO4 & ifp->if_capenable) 7804 ifp->if_hwassist |= CSUM_TSO; 7805 else 7806 ifp->if_hwassist &= ~CSUM_TSO; 7807 } 7808 7809 if (mask & IFCAP_VLAN_HWCSUM && 7810 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7811 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7812 7813 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7814 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7815 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7816 /* 7817 * Don't actually disable VLAN tag stripping as 7818 * management firmware (ASF/IPMI/UMP) requires the 7819 * feature. If VLAN tag stripping is disabled driver 7820 * will manually reconstruct the VLAN frame by 7821 * appending stripped VLAN tag. 7822 */ 7823 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7824 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7825 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7826 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7827 == 0) 7828 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7829 } 7830 VLAN_CAPABILITIES(ifp); 7831 break; 7832 default: 7833 /* We don't know how to handle the IOCTL, pass it on. */ 7834 error = ether_ioctl(ifp, command, data); 7835 break; 7836 } 7837 7838 DBEXIT(BCE_VERBOSE_MISC); 7839 return(error); 7840 } 7841 7842 7843 /****************************************************************************/ 7844 /* Transmit timeout handler. */ 7845 /* */ 7846 /* Returns: */ 7847 /* Nothing. */ 7848 /****************************************************************************/ 7849 static void 7850 bce_watchdog(struct bce_softc *sc) 7851 { 7852 uint32_t status; 7853 7854 DBENTER(BCE_EXTREME_SEND); 7855 7856 BCE_LOCK_ASSERT(sc); 7857 7858 status = 0; 7859 /* If the watchdog timer hasn't expired then just exit. */ 7860 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7861 goto bce_watchdog_exit; 7862 7863 status = REG_RD(sc, BCE_EMAC_RX_STATUS); 7864 /* If pause frames are active then don't reset the hardware. */ 7865 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) { 7866 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) { 7867 /* 7868 * If link partner has us in XOFF state then wait for 7869 * the condition to clear. 7870 */ 7871 sc->watchdog_timer = BCE_TX_TIMEOUT; 7872 goto bce_watchdog_exit; 7873 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 && 7874 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) { 7875 /* 7876 * If we're not currently XOFF'ed but have recently 7877 * been XOFF'd/XON'd then assume that's delaying TX 7878 * this time around. 7879 */ 7880 sc->watchdog_timer = BCE_TX_TIMEOUT; 7881 goto bce_watchdog_exit; 7882 } 7883 /* 7884 * Any other condition is unexpected and the controller 7885 * should be reset. 7886 */ 7887 } 7888 7889 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7890 __FILE__, __LINE__); 7891 7892 DBRUNMSG(BCE_INFO, 7893 bce_dump_driver_state(sc); 7894 bce_dump_status_block(sc); 7895 bce_dump_stats_block(sc); 7896 bce_dump_ftqs(sc); 7897 bce_dump_txp_state(sc, 0); 7898 bce_dump_rxp_state(sc, 0); 7899 bce_dump_tpat_state(sc, 0); 7900 bce_dump_cp_state(sc, 0); 7901 bce_dump_com_state(sc, 0)); 7902 7903 DBRUN(bce_breakpoint(sc)); 7904 7905 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7906 7907 bce_init_locked(sc); 7908 sc->watchdog_timeouts++; 7909 7910 bce_watchdog_exit: 7911 REG_WR(sc, BCE_EMAC_RX_STATUS, status); 7912 DBEXIT(BCE_EXTREME_SEND); 7913 } 7914 7915 7916 /* 7917 * Interrupt handler. 7918 */ 7919 /****************************************************************************/ 7920 /* Main interrupt entry point. Verifies that the controller generated the */ 7921 /* interrupt and then calls a separate routine for handle the various */ 7922 /* interrupt causes (PHY, TX, RX). */ 7923 /* */ 7924 /* Returns: */ 7925 /* Nothing. */ 7926 /****************************************************************************/ 7927 static void 7928 bce_intr(void *xsc) 7929 { 7930 struct bce_softc *sc; 7931 struct ifnet *ifp; 7932 u32 status_attn_bits; 7933 u16 hw_rx_cons, hw_tx_cons; 7934 7935 sc = xsc; 7936 ifp = sc->bce_ifp; 7937 7938 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7939 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7940 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7941 7942 BCE_LOCK(sc); 7943 7944 DBRUN(sc->interrupts_generated++); 7945 7946 /* Synchnorize before we read from interface's status block */ 7947 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7948 7949 /* 7950 * If the hardware status block index matches the last value read 7951 * by the driver and we haven't asserted our interrupt then there's 7952 * nothing to do. This may only happen in case of INTx due to the 7953 * interrupt arriving at the CPU before the status block is updated. 7954 */ 7955 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7956 sc->status_block->status_idx == sc->last_status_idx && 7957 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7958 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7959 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7960 __FUNCTION__); 7961 goto bce_intr_exit; 7962 } 7963 7964 /* Ack the interrupt and stop others from occurring. */ 7965 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7966 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7967 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7968 7969 /* Check if the hardware has finished any work. */ 7970 hw_rx_cons = bce_get_hw_rx_cons(sc); 7971 hw_tx_cons = bce_get_hw_tx_cons(sc); 7972 7973 /* Keep processing data as long as there is work to do. */ 7974 for (;;) { 7975 7976 status_attn_bits = sc->status_block->status_attn_bits; 7977 7978 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7979 BCE_PRINTF("Simulating unexpected status attention " 7980 "bit set."); 7981 sc->unexpected_attention_sim_count++; 7982 status_attn_bits = status_attn_bits | 7983 STATUS_ATTN_BITS_PARITY_ERROR); 7984 7985 /* Was it a link change interrupt? */ 7986 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7987 (sc->status_block->status_attn_bits_ack & 7988 STATUS_ATTN_BITS_LINK_STATE)) { 7989 bce_phy_intr(sc); 7990 7991 /* Clear transient updates during link state change. */ 7992 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7993 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7994 REG_RD(sc, BCE_HC_COMMAND); 7995 } 7996 7997 /* If any other attention is asserted, the chip is toast. */ 7998 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7999 (sc->status_block->status_attn_bits_ack & 8000 ~STATUS_ATTN_BITS_LINK_STATE))) { 8001 8002 sc->unexpected_attention_count++; 8003 8004 BCE_PRINTF("%s(%d): Fatal attention detected: " 8005 "0x%08X\n", __FILE__, __LINE__, 8006 sc->status_block->status_attn_bits); 8007 8008 DBRUNMSG(BCE_FATAL, 8009 if (unexpected_attention_sim_control == 0) 8010 bce_breakpoint(sc)); 8011 8012 bce_init_locked(sc); 8013 goto bce_intr_exit; 8014 } 8015 8016 /* Check for any completed RX frames. */ 8017 if (hw_rx_cons != sc->hw_rx_cons) 8018 bce_rx_intr(sc); 8019 8020 /* Check for any completed TX frames. */ 8021 if (hw_tx_cons != sc->hw_tx_cons) 8022 bce_tx_intr(sc); 8023 8024 /* Save status block index value for the next interrupt. */ 8025 sc->last_status_idx = sc->status_block->status_idx; 8026 8027 /* 8028 * Prevent speculative reads from getting 8029 * ahead of the status block. 8030 */ 8031 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 8032 BUS_SPACE_BARRIER_READ); 8033 8034 /* 8035 * If there's no work left then exit the 8036 * interrupt service routine. 8037 */ 8038 hw_rx_cons = bce_get_hw_rx_cons(sc); 8039 hw_tx_cons = bce_get_hw_tx_cons(sc); 8040 8041 if ((hw_rx_cons == sc->hw_rx_cons) && 8042 (hw_tx_cons == sc->hw_tx_cons)) 8043 break; 8044 } 8045 8046 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 8047 8048 /* Re-enable interrupts. */ 8049 bce_enable_intr(sc, 0); 8050 8051 /* Handle any frames that arrived while handling the interrupt. */ 8052 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 8053 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 8054 bce_start_locked(ifp); 8055 8056 bce_intr_exit: 8057 BCE_UNLOCK(sc); 8058 8059 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 8060 } 8061 8062 8063 /****************************************************************************/ 8064 /* Programs the various packet receive modes (broadcast and multicast). */ 8065 /* */ 8066 /* Returns: */ 8067 /* Nothing. */ 8068 /****************************************************************************/ 8069 static u_int 8070 bce_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 8071 { 8072 u32 *hashes = arg; 8073 int h; 8074 8075 h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF; 8076 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 8077 8078 return (1); 8079 } 8080 8081 static void 8082 bce_set_rx_mode(struct bce_softc *sc) 8083 { 8084 struct ifnet *ifp; 8085 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 8086 u32 rx_mode, sort_mode; 8087 int i; 8088 8089 DBENTER(BCE_VERBOSE_MISC); 8090 8091 BCE_LOCK_ASSERT(sc); 8092 8093 ifp = sc->bce_ifp; 8094 8095 /* Initialize receive mode default settings. */ 8096 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 8097 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 8098 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 8099 8100 /* 8101 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 8102 * be enbled. 8103 */ 8104 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 8105 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 8106 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 8107 8108 /* 8109 * Check for promiscuous, all multicast, or selected 8110 * multicast address filtering. 8111 */ 8112 if (ifp->if_flags & IFF_PROMISC) { 8113 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 8114 8115 /* Enable promiscuous mode. */ 8116 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 8117 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 8118 } else if (ifp->if_flags & IFF_ALLMULTI) { 8119 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 8120 8121 /* Enable all multicast addresses. */ 8122 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 8123 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 8124 0xffffffff); 8125 } 8126 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 8127 } else { 8128 /* Accept one or more multicast(s). */ 8129 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 8130 if_foreach_llmaddr(ifp, bce_hash_maddr, hashes); 8131 8132 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 8133 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 8134 8135 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 8136 } 8137 8138 /* Only make changes if the recive mode has actually changed. */ 8139 if (rx_mode != sc->rx_mode) { 8140 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 8141 "0x%08X\n", rx_mode); 8142 8143 sc->rx_mode = rx_mode; 8144 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 8145 } 8146 8147 /* Disable and clear the exisitng sort before enabling a new sort. */ 8148 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 8149 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 8150 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8151 8152 DBEXIT(BCE_VERBOSE_MISC); 8153 } 8154 8155 8156 /****************************************************************************/ 8157 /* Called periodically to updates statistics from the controllers */ 8158 /* statistics block. */ 8159 /* */ 8160 /* Returns: */ 8161 /* Nothing. */ 8162 /****************************************************************************/ 8163 static void 8164 bce_stats_update(struct bce_softc *sc) 8165 { 8166 struct statistics_block *stats; 8167 8168 DBENTER(BCE_EXTREME_MISC); 8169 8170 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8171 8172 stats = (struct statistics_block *) sc->stats_block; 8173 8174 /* 8175 * Update the sysctl statistics from the 8176 * hardware statistics. 8177 */ 8178 sc->stat_IfHCInOctets = 8179 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8180 (u64) stats->stat_IfHCInOctets_lo; 8181 8182 sc->stat_IfHCInBadOctets = 8183 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8184 (u64) stats->stat_IfHCInBadOctets_lo; 8185 8186 sc->stat_IfHCOutOctets = 8187 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8188 (u64) stats->stat_IfHCOutOctets_lo; 8189 8190 sc->stat_IfHCOutBadOctets = 8191 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8192 (u64) stats->stat_IfHCOutBadOctets_lo; 8193 8194 sc->stat_IfHCInUcastPkts = 8195 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8196 (u64) stats->stat_IfHCInUcastPkts_lo; 8197 8198 sc->stat_IfHCInMulticastPkts = 8199 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8200 (u64) stats->stat_IfHCInMulticastPkts_lo; 8201 8202 sc->stat_IfHCInBroadcastPkts = 8203 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8204 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8205 8206 sc->stat_IfHCOutUcastPkts = 8207 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8208 (u64) stats->stat_IfHCOutUcastPkts_lo; 8209 8210 sc->stat_IfHCOutMulticastPkts = 8211 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8212 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8213 8214 sc->stat_IfHCOutBroadcastPkts = 8215 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8216 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8217 8218 /* ToDo: Preserve counters beyond 32 bits? */ 8219 /* ToDo: Read the statistics from auto-clear regs? */ 8220 8221 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8222 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8223 8224 sc->stat_Dot3StatsCarrierSenseErrors = 8225 stats->stat_Dot3StatsCarrierSenseErrors; 8226 8227 sc->stat_Dot3StatsFCSErrors = 8228 stats->stat_Dot3StatsFCSErrors; 8229 8230 sc->stat_Dot3StatsAlignmentErrors = 8231 stats->stat_Dot3StatsAlignmentErrors; 8232 8233 sc->stat_Dot3StatsSingleCollisionFrames = 8234 stats->stat_Dot3StatsSingleCollisionFrames; 8235 8236 sc->stat_Dot3StatsMultipleCollisionFrames = 8237 stats->stat_Dot3StatsMultipleCollisionFrames; 8238 8239 sc->stat_Dot3StatsDeferredTransmissions = 8240 stats->stat_Dot3StatsDeferredTransmissions; 8241 8242 sc->stat_Dot3StatsExcessiveCollisions = 8243 stats->stat_Dot3StatsExcessiveCollisions; 8244 8245 sc->stat_Dot3StatsLateCollisions = 8246 stats->stat_Dot3StatsLateCollisions; 8247 8248 sc->stat_EtherStatsCollisions = 8249 stats->stat_EtherStatsCollisions; 8250 8251 sc->stat_EtherStatsFragments = 8252 stats->stat_EtherStatsFragments; 8253 8254 sc->stat_EtherStatsJabbers = 8255 stats->stat_EtherStatsJabbers; 8256 8257 sc->stat_EtherStatsUndersizePkts = 8258 stats->stat_EtherStatsUndersizePkts; 8259 8260 sc->stat_EtherStatsOversizePkts = 8261 stats->stat_EtherStatsOversizePkts; 8262 8263 sc->stat_EtherStatsPktsRx64Octets = 8264 stats->stat_EtherStatsPktsRx64Octets; 8265 8266 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8267 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8268 8269 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8270 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8271 8272 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8273 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8274 8275 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8276 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8277 8278 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8279 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8280 8281 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8282 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8283 8284 sc->stat_EtherStatsPktsTx64Octets = 8285 stats->stat_EtherStatsPktsTx64Octets; 8286 8287 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8288 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8289 8290 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8291 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8292 8293 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8294 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8295 8296 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8297 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8298 8299 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8300 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8301 8302 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8303 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8304 8305 sc->stat_XonPauseFramesReceived = 8306 stats->stat_XonPauseFramesReceived; 8307 8308 sc->stat_XoffPauseFramesReceived = 8309 stats->stat_XoffPauseFramesReceived; 8310 8311 sc->stat_OutXonSent = 8312 stats->stat_OutXonSent; 8313 8314 sc->stat_OutXoffSent = 8315 stats->stat_OutXoffSent; 8316 8317 sc->stat_FlowControlDone = 8318 stats->stat_FlowControlDone; 8319 8320 sc->stat_MacControlFramesReceived = 8321 stats->stat_MacControlFramesReceived; 8322 8323 sc->stat_XoffStateEntered = 8324 stats->stat_XoffStateEntered; 8325 8326 sc->stat_IfInFramesL2FilterDiscards = 8327 stats->stat_IfInFramesL2FilterDiscards; 8328 8329 sc->stat_IfInRuleCheckerDiscards = 8330 stats->stat_IfInRuleCheckerDiscards; 8331 8332 sc->stat_IfInFTQDiscards = 8333 stats->stat_IfInFTQDiscards; 8334 8335 sc->stat_IfInMBUFDiscards = 8336 stats->stat_IfInMBUFDiscards; 8337 8338 sc->stat_IfInRuleCheckerP4Hit = 8339 stats->stat_IfInRuleCheckerP4Hit; 8340 8341 sc->stat_CatchupInRuleCheckerDiscards = 8342 stats->stat_CatchupInRuleCheckerDiscards; 8343 8344 sc->stat_CatchupInFTQDiscards = 8345 stats->stat_CatchupInFTQDiscards; 8346 8347 sc->stat_CatchupInMBUFDiscards = 8348 stats->stat_CatchupInMBUFDiscards; 8349 8350 sc->stat_CatchupInRuleCheckerP4Hit = 8351 stats->stat_CatchupInRuleCheckerP4Hit; 8352 8353 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8354 8355 /* ToDo: Add additional statistics? */ 8356 8357 DBEXIT(BCE_EXTREME_MISC); 8358 } 8359 8360 static uint64_t 8361 bce_get_counter(struct ifnet *ifp, ift_counter cnt) 8362 { 8363 struct bce_softc *sc; 8364 uint64_t rv; 8365 8366 sc = if_getsoftc(ifp); 8367 8368 switch (cnt) { 8369 case IFCOUNTER_COLLISIONS: 8370 return (sc->stat_EtherStatsCollisions); 8371 case IFCOUNTER_IERRORS: 8372 return (sc->stat_EtherStatsUndersizePkts + 8373 sc->stat_EtherStatsOversizePkts + 8374 sc->stat_IfInMBUFDiscards + 8375 sc->stat_Dot3StatsAlignmentErrors + 8376 sc->stat_Dot3StatsFCSErrors + 8377 sc->stat_IfInRuleCheckerDiscards + 8378 sc->stat_IfInFTQDiscards + 8379 sc->l2fhdr_error_count + 8380 sc->com_no_buffers); 8381 case IFCOUNTER_OERRORS: 8382 rv = sc->stat_Dot3StatsExcessiveCollisions + 8383 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8384 sc->stat_Dot3StatsLateCollisions + 8385 sc->watchdog_timeouts; 8386 /* 8387 * Certain controllers don't report 8388 * carrier sense errors correctly. 8389 * See errata E11_5708CA0_1165. 8390 */ 8391 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8392 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8393 rv += sc->stat_Dot3StatsCarrierSenseErrors; 8394 return (rv); 8395 default: 8396 return (if_get_counter_default(ifp, cnt)); 8397 } 8398 } 8399 8400 8401 /****************************************************************************/ 8402 /* Periodic function to notify the bootcode that the driver is still */ 8403 /* present. */ 8404 /* */ 8405 /* Returns: */ 8406 /* Nothing. */ 8407 /****************************************************************************/ 8408 static void 8409 bce_pulse(void *xsc) 8410 { 8411 struct bce_softc *sc = xsc; 8412 u32 msg; 8413 8414 DBENTER(BCE_EXTREME_MISC); 8415 8416 BCE_LOCK_ASSERT(sc); 8417 8418 /* Tell the firmware that the driver is still running. */ 8419 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8420 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8421 8422 /* Update the bootcode condition. */ 8423 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8424 8425 /* Report whether the bootcode still knows the driver is running. */ 8426 if (bce_verbose || bootverbose) { 8427 if (sc->bce_drv_cardiac_arrest == FALSE) { 8428 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8429 sc->bce_drv_cardiac_arrest = TRUE; 8430 BCE_PRINTF("%s(): Warning: bootcode " 8431 "thinks driver is absent! " 8432 "(bc_state = 0x%08X)\n", 8433 __FUNCTION__, sc->bc_state); 8434 } 8435 } else { 8436 /* 8437 * Not supported by all bootcode versions. 8438 * (v5.0.11+ and v5.2.1+) Older bootcode 8439 * will require the driver to reset the 8440 * controller to clear this condition. 8441 */ 8442 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8443 sc->bce_drv_cardiac_arrest = FALSE; 8444 BCE_PRINTF("%s(): Bootcode found the " 8445 "driver pulse! (bc_state = 0x%08X)\n", 8446 __FUNCTION__, sc->bc_state); 8447 } 8448 } 8449 } 8450 8451 8452 /* Schedule the next pulse. */ 8453 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8454 8455 DBEXIT(BCE_EXTREME_MISC); 8456 } 8457 8458 8459 /****************************************************************************/ 8460 /* Periodic function to perform maintenance tasks. */ 8461 /* */ 8462 /* Returns: */ 8463 /* Nothing. */ 8464 /****************************************************************************/ 8465 static void 8466 bce_tick(void *xsc) 8467 { 8468 struct bce_softc *sc = xsc; 8469 struct mii_data *mii; 8470 struct ifnet *ifp; 8471 struct ifmediareq ifmr; 8472 8473 ifp = sc->bce_ifp; 8474 8475 DBENTER(BCE_EXTREME_MISC); 8476 8477 BCE_LOCK_ASSERT(sc); 8478 8479 /* Schedule the next tick. */ 8480 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8481 8482 /* Update the statistics from the hardware statistics block. */ 8483 bce_stats_update(sc); 8484 8485 /* Ensure page and RX chains get refilled in low-memory situations. */ 8486 if (bce_hdr_split == TRUE) 8487 bce_fill_pg_chain(sc); 8488 bce_fill_rx_chain(sc); 8489 8490 /* Check that chip hasn't hung. */ 8491 bce_watchdog(sc); 8492 8493 /* If link is up already up then we're done. */ 8494 if (sc->bce_link_up == TRUE) 8495 goto bce_tick_exit; 8496 8497 /* Link is down. Check what the PHY's doing. */ 8498 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8499 bzero(&ifmr, sizeof(ifmr)); 8500 bce_ifmedia_sts_rphy(sc, &ifmr); 8501 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8502 (IFM_ACTIVE | IFM_AVALID)) { 8503 sc->bce_link_up = TRUE; 8504 bce_miibus_statchg(sc->bce_dev); 8505 } 8506 } else { 8507 mii = device_get_softc(sc->bce_miibus); 8508 mii_tick(mii); 8509 /* Check if the link has come up. */ 8510 if ((mii->mii_media_status & IFM_ACTIVE) && 8511 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8512 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8513 __FUNCTION__); 8514 sc->bce_link_up = TRUE; 8515 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8516 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8517 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8518 (bce_verbose || bootverbose)) 8519 BCE_PRINTF("Gigabit link up!\n"); 8520 } 8521 8522 } 8523 if (sc->bce_link_up == TRUE) { 8524 /* Now that link is up, handle any outstanding TX traffic. */ 8525 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8526 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8527 "pending TX traffic.\n", __FUNCTION__); 8528 bce_start_locked(ifp); 8529 } 8530 } 8531 8532 bce_tick_exit: 8533 DBEXIT(BCE_EXTREME_MISC); 8534 } 8535 8536 static void 8537 bce_fw_cap_init(struct bce_softc *sc) 8538 { 8539 u32 ack, cap, link; 8540 8541 ack = 0; 8542 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8543 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8544 BCE_FW_CAP_SIGNATURE_MAGIC) 8545 return; 8546 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8547 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8548 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8549 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8550 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8551 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8552 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8553 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8554 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8555 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8556 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8557 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8558 BCE_FW_CAP_REMOTE_PHY_CAP; 8559 } 8560 8561 if (ack != 0) 8562 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8563 } 8564 8565 8566 #ifdef BCE_DEBUG 8567 /****************************************************************************/ 8568 /* Allows the driver state to be dumped through the sysctl interface. */ 8569 /* */ 8570 /* Returns: */ 8571 /* 0 for success, positive value for failure. */ 8572 /****************************************************************************/ 8573 static int 8574 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8575 { 8576 int error; 8577 int result; 8578 struct bce_softc *sc; 8579 8580 result = -1; 8581 error = sysctl_handle_int(oidp, &result, 0, req); 8582 8583 if (error || !req->newptr) 8584 return (error); 8585 8586 if (result == 1) { 8587 sc = (struct bce_softc *)arg1; 8588 bce_dump_driver_state(sc); 8589 } 8590 8591 return error; 8592 } 8593 8594 8595 /****************************************************************************/ 8596 /* Allows the hardware state to be dumped through the sysctl interface. */ 8597 /* */ 8598 /* Returns: */ 8599 /* 0 for success, positive value for failure. */ 8600 /****************************************************************************/ 8601 static int 8602 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8603 { 8604 int error; 8605 int result; 8606 struct bce_softc *sc; 8607 8608 result = -1; 8609 error = sysctl_handle_int(oidp, &result, 0, req); 8610 8611 if (error || !req->newptr) 8612 return (error); 8613 8614 if (result == 1) { 8615 sc = (struct bce_softc *)arg1; 8616 bce_dump_hw_state(sc); 8617 } 8618 8619 return error; 8620 } 8621 8622 8623 /****************************************************************************/ 8624 /* Allows the status block to be dumped through the sysctl interface. */ 8625 /* */ 8626 /* Returns: */ 8627 /* 0 for success, positive value for failure. */ 8628 /****************************************************************************/ 8629 static int 8630 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8631 { 8632 int error; 8633 int result; 8634 struct bce_softc *sc; 8635 8636 result = -1; 8637 error = sysctl_handle_int(oidp, &result, 0, req); 8638 8639 if (error || !req->newptr) 8640 return (error); 8641 8642 if (result == 1) { 8643 sc = (struct bce_softc *)arg1; 8644 bce_dump_status_block(sc); 8645 } 8646 8647 return error; 8648 } 8649 8650 8651 /****************************************************************************/ 8652 /* Allows the stats block to be dumped through the sysctl interface. */ 8653 /* */ 8654 /* Returns: */ 8655 /* 0 for success, positive value for failure. */ 8656 /****************************************************************************/ 8657 static int 8658 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8659 { 8660 int error; 8661 int result; 8662 struct bce_softc *sc; 8663 8664 result = -1; 8665 error = sysctl_handle_int(oidp, &result, 0, req); 8666 8667 if (error || !req->newptr) 8668 return (error); 8669 8670 if (result == 1) { 8671 sc = (struct bce_softc *)arg1; 8672 bce_dump_stats_block(sc); 8673 } 8674 8675 return error; 8676 } 8677 8678 8679 /****************************************************************************/ 8680 /* Allows the stat counters to be cleared without unloading/reloading the */ 8681 /* driver. */ 8682 /* */ 8683 /* Returns: */ 8684 /* 0 for success, positive value for failure. */ 8685 /****************************************************************************/ 8686 static int 8687 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8688 { 8689 int error; 8690 int result; 8691 struct bce_softc *sc; 8692 8693 result = -1; 8694 error = sysctl_handle_int(oidp, &result, 0, req); 8695 8696 if (error || !req->newptr) 8697 return (error); 8698 8699 if (result == 1) { 8700 sc = (struct bce_softc *)arg1; 8701 struct statistics_block *stats; 8702 8703 stats = (struct statistics_block *) sc->stats_block; 8704 bzero(stats, sizeof(struct statistics_block)); 8705 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8706 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8707 8708 /* Clear the internal H/W statistics counters. */ 8709 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8710 8711 /* Reset the driver maintained statistics. */ 8712 sc->interrupts_rx = 8713 sc->interrupts_tx = 0; 8714 sc->tso_frames_requested = 8715 sc->tso_frames_completed = 8716 sc->tso_frames_failed = 0; 8717 sc->rx_empty_count = 8718 sc->tx_full_count = 0; 8719 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8720 sc->tx_hi_watermark = 0; 8721 sc->l2fhdr_error_count = 8722 sc->l2fhdr_error_sim_count = 0; 8723 sc->mbuf_alloc_failed_count = 8724 sc->mbuf_alloc_failed_sim_count = 0; 8725 sc->dma_map_addr_rx_failed_count = 8726 sc->dma_map_addr_tx_failed_count = 0; 8727 sc->mbuf_frag_count = 0; 8728 sc->csum_offload_tcp_udp = 8729 sc->csum_offload_ip = 0; 8730 sc->vlan_tagged_frames_rcvd = 8731 sc->vlan_tagged_frames_stripped = 0; 8732 sc->split_header_frames_rcvd = 8733 sc->split_header_tcp_frames_rcvd = 0; 8734 8735 /* Clear firmware maintained statistics. */ 8736 REG_WR_IND(sc, 0x120084, 0); 8737 } 8738 8739 return error; 8740 } 8741 8742 8743 /****************************************************************************/ 8744 /* Allows the shared memory contents to be dumped through the sysctl . */ 8745 /* interface. */ 8746 /* */ 8747 /* Returns: */ 8748 /* 0 for success, positive value for failure. */ 8749 /****************************************************************************/ 8750 static int 8751 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8752 { 8753 int error; 8754 int result; 8755 struct bce_softc *sc; 8756 8757 result = -1; 8758 error = sysctl_handle_int(oidp, &result, 0, req); 8759 8760 if (error || !req->newptr) 8761 return (error); 8762 8763 if (result == 1) { 8764 sc = (struct bce_softc *)arg1; 8765 bce_dump_shmem_state(sc); 8766 } 8767 8768 return error; 8769 } 8770 8771 8772 /****************************************************************************/ 8773 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8774 /* */ 8775 /* Returns: */ 8776 /* 0 for success, positive value for failure. */ 8777 /****************************************************************************/ 8778 static int 8779 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8780 { 8781 int error; 8782 int result; 8783 struct bce_softc *sc; 8784 8785 result = -1; 8786 error = sysctl_handle_int(oidp, &result, 0, req); 8787 8788 if (error || !req->newptr) 8789 return (error); 8790 8791 if (result == 1) { 8792 sc = (struct bce_softc *)arg1; 8793 bce_dump_bc_state(sc); 8794 } 8795 8796 return error; 8797 } 8798 8799 8800 /****************************************************************************/ 8801 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8802 /* */ 8803 /* Returns: */ 8804 /* 0 for success, positive value for failure. */ 8805 /****************************************************************************/ 8806 static int 8807 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8808 { 8809 int error; 8810 int result; 8811 struct bce_softc *sc; 8812 8813 result = -1; 8814 error = sysctl_handle_int(oidp, &result, 0, req); 8815 8816 if (error || !req->newptr) 8817 return (error); 8818 8819 if (result == 1) { 8820 sc = (struct bce_softc *)arg1; 8821 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8822 } 8823 8824 return error; 8825 } 8826 8827 8828 /****************************************************************************/ 8829 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8830 /* */ 8831 /* Returns: */ 8832 /* 0 for success, positive value for failure. */ 8833 /****************************************************************************/ 8834 static int 8835 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8836 { 8837 int error; 8838 int result; 8839 struct bce_softc *sc; 8840 8841 result = -1; 8842 error = sysctl_handle_int(oidp, &result, 0, req); 8843 8844 if (error || !req->newptr) 8845 return (error); 8846 8847 if (result == 1) { 8848 sc = (struct bce_softc *)arg1; 8849 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8850 } 8851 8852 return error; 8853 } 8854 8855 8856 /****************************************************************************/ 8857 /* Provides a sysctl interface to allow dumping the TX chain. */ 8858 /* */ 8859 /* Returns: */ 8860 /* 0 for success, positive value for failure. */ 8861 /****************************************************************************/ 8862 static int 8863 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8864 { 8865 int error; 8866 int result; 8867 struct bce_softc *sc; 8868 8869 result = -1; 8870 error = sysctl_handle_int(oidp, &result, 0, req); 8871 8872 if (error || !req->newptr) 8873 return (error); 8874 8875 if (result == 1) { 8876 sc = (struct bce_softc *)arg1; 8877 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8878 } 8879 8880 return error; 8881 } 8882 8883 8884 /****************************************************************************/ 8885 /* Provides a sysctl interface to allow dumping the page chain. */ 8886 /* */ 8887 /* Returns: */ 8888 /* 0 for success, positive value for failure. */ 8889 /****************************************************************************/ 8890 static int 8891 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8892 { 8893 int error; 8894 int result; 8895 struct bce_softc *sc; 8896 8897 result = -1; 8898 error = sysctl_handle_int(oidp, &result, 0, req); 8899 8900 if (error || !req->newptr) 8901 return (error); 8902 8903 if (result == 1) { 8904 sc = (struct bce_softc *)arg1; 8905 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8906 } 8907 8908 return error; 8909 } 8910 8911 /****************************************************************************/ 8912 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8913 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8914 /* */ 8915 /* Returns: */ 8916 /* 0 for success, positive value for failure. */ 8917 /****************************************************************************/ 8918 static int 8919 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8920 { 8921 struct bce_softc *sc = (struct bce_softc *)arg1; 8922 int error; 8923 u32 result; 8924 u32 val[1]; 8925 u8 *data = (u8 *) val; 8926 8927 result = -1; 8928 error = sysctl_handle_int(oidp, &result, 0, req); 8929 if (error || (req->newptr == NULL)) 8930 return (error); 8931 8932 error = bce_nvram_read(sc, result, data, 4); 8933 8934 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8935 8936 return (error); 8937 } 8938 8939 8940 /****************************************************************************/ 8941 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8942 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8943 /* */ 8944 /* Returns: */ 8945 /* 0 for success, positive value for failure. */ 8946 /****************************************************************************/ 8947 static int 8948 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8949 { 8950 struct bce_softc *sc = (struct bce_softc *)arg1; 8951 int error; 8952 u32 val, result; 8953 8954 result = -1; 8955 error = sysctl_handle_int(oidp, &result, 0, req); 8956 if (error || (req->newptr == NULL)) 8957 return (error); 8958 8959 /* Make sure the register is accessible. */ 8960 if (result < 0x8000) { 8961 val = REG_RD(sc, result); 8962 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8963 } else if (result < 0x0280000) { 8964 val = REG_RD_IND(sc, result); 8965 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8966 } 8967 8968 return (error); 8969 } 8970 8971 8972 /****************************************************************************/ 8973 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8974 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8975 /* */ 8976 /* Returns: */ 8977 /* 0 for success, positive value for failure. */ 8978 /****************************************************************************/ 8979 static int 8980 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8981 { 8982 struct bce_softc *sc; 8983 device_t dev; 8984 int error, result; 8985 u16 val; 8986 8987 result = -1; 8988 error = sysctl_handle_int(oidp, &result, 0, req); 8989 if (error || (req->newptr == NULL)) 8990 return (error); 8991 8992 /* Make sure the register is accessible. */ 8993 if (result < 0x20) { 8994 sc = (struct bce_softc *)arg1; 8995 dev = sc->bce_dev; 8996 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8997 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8998 } 8999 return (error); 9000 } 9001 9002 9003 /****************************************************************************/ 9004 /* Provides a sysctl interface for dumping the nvram contents. */ 9005 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9006 /* */ 9007 /* Returns: */ 9008 /* 0 for success, positive errno for failure. */ 9009 /****************************************************************************/ 9010 static int 9011 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 9012 { 9013 struct bce_softc *sc = (struct bce_softc *)arg1; 9014 int error, i; 9015 9016 if (sc->nvram_buf == NULL) 9017 sc->nvram_buf = malloc(sc->bce_flash_size, 9018 M_TEMP, M_ZERO | M_WAITOK); 9019 9020 error = 0; 9021 if (req->oldlen == sc->bce_flash_size) { 9022 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 9023 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 9024 } 9025 9026 if (error == 0) 9027 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 9028 9029 return error; 9030 } 9031 9032 #ifdef BCE_NVRAM_WRITE_SUPPORT 9033 /****************************************************************************/ 9034 /* Provides a sysctl interface for writing to nvram. */ 9035 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9036 /* */ 9037 /* Returns: */ 9038 /* 0 for success, positive errno for failure. */ 9039 /****************************************************************************/ 9040 static int 9041 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 9042 { 9043 struct bce_softc *sc = (struct bce_softc *)arg1; 9044 int error; 9045 9046 if (sc->nvram_buf == NULL) 9047 sc->nvram_buf = malloc(sc->bce_flash_size, 9048 M_TEMP, M_ZERO | M_WAITOK); 9049 else 9050 bzero(sc->nvram_buf, sc->bce_flash_size); 9051 9052 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 9053 if (error == 0) 9054 return (error); 9055 9056 if (req->newlen == sc->bce_flash_size) 9057 error = bce_nvram_write(sc, 0, sc->nvram_buf, 9058 sc->bce_flash_size); 9059 9060 9061 return error; 9062 } 9063 #endif 9064 9065 9066 /****************************************************************************/ 9067 /* Provides a sysctl interface to allow reading a CID. */ 9068 /* */ 9069 /* Returns: */ 9070 /* 0 for success, positive value for failure. */ 9071 /****************************************************************************/ 9072 static int 9073 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 9074 { 9075 struct bce_softc *sc; 9076 int error, result; 9077 9078 result = -1; 9079 error = sysctl_handle_int(oidp, &result, 0, req); 9080 if (error || (req->newptr == NULL)) 9081 return (error); 9082 9083 /* Make sure the register is accessible. */ 9084 if (result <= TX_CID) { 9085 sc = (struct bce_softc *)arg1; 9086 bce_dump_ctx(sc, result); 9087 } 9088 9089 return (error); 9090 } 9091 9092 9093 /****************************************************************************/ 9094 /* Provides a sysctl interface to forcing the driver to dump state and */ 9095 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9096 /* */ 9097 /* Returns: */ 9098 /* 0 for success, positive value for failure. */ 9099 /****************************************************************************/ 9100 static int 9101 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 9102 { 9103 int error; 9104 int result; 9105 struct bce_softc *sc; 9106 9107 result = -1; 9108 error = sysctl_handle_int(oidp, &result, 0, req); 9109 9110 if (error || !req->newptr) 9111 return (error); 9112 9113 if (result == 1) { 9114 sc = (struct bce_softc *)arg1; 9115 bce_breakpoint(sc); 9116 } 9117 9118 return error; 9119 } 9120 #endif 9121 9122 /****************************************************************************/ 9123 /* Adds any sysctl parameters for tuning or debugging purposes. */ 9124 /* */ 9125 /* Returns: */ 9126 /* 0 for success, positive value for failure. */ 9127 /****************************************************************************/ 9128 static void 9129 bce_add_sysctls(struct bce_softc *sc) 9130 { 9131 struct sysctl_ctx_list *ctx; 9132 struct sysctl_oid_list *children; 9133 9134 DBENTER(BCE_VERBOSE_MISC); 9135 9136 ctx = device_get_sysctl_ctx(sc->bce_dev); 9137 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 9138 9139 #ifdef BCE_DEBUG 9140 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9141 "l2fhdr_error_sim_control", 9142 CTLFLAG_RW, &l2fhdr_error_sim_control, 9143 0, "Debug control to force l2fhdr errors"); 9144 9145 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9146 "l2fhdr_error_sim_count", 9147 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 9148 0, "Number of simulated l2_fhdr errors"); 9149 #endif 9150 9151 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9152 "l2fhdr_error_count", 9153 CTLFLAG_RD, &sc->l2fhdr_error_count, 9154 0, "Number of l2_fhdr errors"); 9155 9156 #ifdef BCE_DEBUG 9157 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9158 "mbuf_alloc_failed_sim_control", 9159 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 9160 0, "Debug control to force mbuf allocation failures"); 9161 9162 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9163 "mbuf_alloc_failed_sim_count", 9164 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 9165 0, "Number of simulated mbuf cluster allocation failures"); 9166 #endif 9167 9168 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9169 "mbuf_alloc_failed_count", 9170 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 9171 0, "Number of mbuf allocation failures"); 9172 9173 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9174 "mbuf_frag_count", 9175 CTLFLAG_RD, &sc->mbuf_frag_count, 9176 0, "Number of fragmented mbufs"); 9177 9178 #ifdef BCE_DEBUG 9179 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9180 "dma_map_addr_failed_sim_control", 9181 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9182 0, "Debug control to force DMA mapping failures"); 9183 9184 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9185 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9186 "dma_map_addr_failed_sim_count", 9187 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9188 0, "Number of simulated DMA mapping failures"); 9189 9190 #endif 9191 9192 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9193 "dma_map_addr_rx_failed_count", 9194 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9195 0, "Number of RX DMA mapping failures"); 9196 9197 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9198 "dma_map_addr_tx_failed_count", 9199 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9200 0, "Number of TX DMA mapping failures"); 9201 9202 #ifdef BCE_DEBUG 9203 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9204 "unexpected_attention_sim_control", 9205 CTLFLAG_RW, &unexpected_attention_sim_control, 9206 0, "Debug control to simulate unexpected attentions"); 9207 9208 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9209 "unexpected_attention_sim_count", 9210 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9211 0, "Number of simulated unexpected attentions"); 9212 #endif 9213 9214 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9215 "unexpected_attention_count", 9216 CTLFLAG_RW, &sc->unexpected_attention_count, 9217 0, "Number of unexpected attentions"); 9218 9219 #ifdef BCE_DEBUG 9220 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9221 "debug_bootcode_running_failure", 9222 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9223 0, "Debug control to force bootcode running failures"); 9224 9225 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9226 "rx_low_watermark", 9227 CTLFLAG_RD, &sc->rx_low_watermark, 9228 0, "Lowest level of free rx_bd's"); 9229 9230 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9231 "rx_empty_count", 9232 CTLFLAG_RD, &sc->rx_empty_count, 9233 "Number of times the RX chain was empty"); 9234 9235 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9236 "tx_hi_watermark", 9237 CTLFLAG_RD, &sc->tx_hi_watermark, 9238 0, "Highest level of used tx_bd's"); 9239 9240 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9241 "tx_full_count", 9242 CTLFLAG_RD, &sc->tx_full_count, 9243 "Number of times the TX chain was full"); 9244 9245 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9246 "tso_frames_requested", 9247 CTLFLAG_RD, &sc->tso_frames_requested, 9248 "Number of TSO frames requested"); 9249 9250 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9251 "tso_frames_completed", 9252 CTLFLAG_RD, &sc->tso_frames_completed, 9253 "Number of TSO frames completed"); 9254 9255 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9256 "tso_frames_failed", 9257 CTLFLAG_RD, &sc->tso_frames_failed, 9258 "Number of TSO frames failed"); 9259 9260 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9261 "csum_offload_ip", 9262 CTLFLAG_RD, &sc->csum_offload_ip, 9263 "Number of IP checksum offload frames"); 9264 9265 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9266 "csum_offload_tcp_udp", 9267 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9268 "Number of TCP/UDP checksum offload frames"); 9269 9270 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9271 "vlan_tagged_frames_rcvd", 9272 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9273 "Number of VLAN tagged frames received"); 9274 9275 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9276 "vlan_tagged_frames_stripped", 9277 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9278 "Number of VLAN tagged frames stripped"); 9279 9280 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9281 "interrupts_rx", 9282 CTLFLAG_RD, &sc->interrupts_rx, 9283 "Number of RX interrupts"); 9284 9285 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9286 "interrupts_tx", 9287 CTLFLAG_RD, &sc->interrupts_tx, 9288 "Number of TX interrupts"); 9289 9290 if (bce_hdr_split == TRUE) { 9291 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9292 "split_header_frames_rcvd", 9293 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9294 "Number of split header frames received"); 9295 9296 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9297 "split_header_tcp_frames_rcvd", 9298 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9299 "Number of split header TCP frames received"); 9300 } 9301 9302 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9303 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 9304 (void *)sc, 0, 9305 bce_sysctl_nvram_dump, "S", ""); 9306 9307 #ifdef BCE_NVRAM_WRITE_SUPPORT 9308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9309 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR | CTLFLAG_NEEDGIANT, 9310 (void *)sc, 0, 9311 bce_sysctl_nvram_write, "S", ""); 9312 #endif 9313 #endif /* BCE_DEBUG */ 9314 9315 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9316 "stat_IfHcInOctets", 9317 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9318 "Bytes received"); 9319 9320 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9321 "stat_IfHCInBadOctets", 9322 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9323 "Bad bytes received"); 9324 9325 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9326 "stat_IfHCOutOctets", 9327 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9328 "Bytes sent"); 9329 9330 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9331 "stat_IfHCOutBadOctets", 9332 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9333 "Bad bytes sent"); 9334 9335 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9336 "stat_IfHCInUcastPkts", 9337 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9338 "Unicast packets received"); 9339 9340 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9341 "stat_IfHCInMulticastPkts", 9342 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9343 "Multicast packets received"); 9344 9345 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9346 "stat_IfHCInBroadcastPkts", 9347 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9348 "Broadcast packets received"); 9349 9350 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9351 "stat_IfHCOutUcastPkts", 9352 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9353 "Unicast packets sent"); 9354 9355 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9356 "stat_IfHCOutMulticastPkts", 9357 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9358 "Multicast packets sent"); 9359 9360 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9361 "stat_IfHCOutBroadcastPkts", 9362 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9363 "Broadcast packets sent"); 9364 9365 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9366 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9367 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9368 0, "Internal MAC transmit errors"); 9369 9370 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9371 "stat_Dot3StatsCarrierSenseErrors", 9372 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9373 0, "Carrier sense errors"); 9374 9375 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9376 "stat_Dot3StatsFCSErrors", 9377 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9378 0, "Frame check sequence errors"); 9379 9380 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9381 "stat_Dot3StatsAlignmentErrors", 9382 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9383 0, "Alignment errors"); 9384 9385 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9386 "stat_Dot3StatsSingleCollisionFrames", 9387 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9388 0, "Single Collision Frames"); 9389 9390 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9391 "stat_Dot3StatsMultipleCollisionFrames", 9392 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9393 0, "Multiple Collision Frames"); 9394 9395 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9396 "stat_Dot3StatsDeferredTransmissions", 9397 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9398 0, "Deferred Transmissions"); 9399 9400 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9401 "stat_Dot3StatsExcessiveCollisions", 9402 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9403 0, "Excessive Collisions"); 9404 9405 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9406 "stat_Dot3StatsLateCollisions", 9407 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9408 0, "Late Collisions"); 9409 9410 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9411 "stat_EtherStatsCollisions", 9412 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9413 0, "Collisions"); 9414 9415 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9416 "stat_EtherStatsFragments", 9417 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9418 0, "Fragments"); 9419 9420 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9421 "stat_EtherStatsJabbers", 9422 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9423 0, "Jabbers"); 9424 9425 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9426 "stat_EtherStatsUndersizePkts", 9427 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9428 0, "Undersize packets"); 9429 9430 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9431 "stat_EtherStatsOversizePkts", 9432 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9433 0, "stat_EtherStatsOversizePkts"); 9434 9435 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9436 "stat_EtherStatsPktsRx64Octets", 9437 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9438 0, "Bytes received in 64 byte packets"); 9439 9440 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9441 "stat_EtherStatsPktsRx65Octetsto127Octets", 9442 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9443 0, "Bytes received in 65 to 127 byte packets"); 9444 9445 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9446 "stat_EtherStatsPktsRx128Octetsto255Octets", 9447 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9448 0, "Bytes received in 128 to 255 byte packets"); 9449 9450 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9451 "stat_EtherStatsPktsRx256Octetsto511Octets", 9452 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9453 0, "Bytes received in 256 to 511 byte packets"); 9454 9455 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9456 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9457 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9458 0, "Bytes received in 512 to 1023 byte packets"); 9459 9460 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9461 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9462 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9463 0, "Bytes received in 1024 t0 1522 byte packets"); 9464 9465 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9466 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9467 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9468 0, "Bytes received in 1523 to 9022 byte packets"); 9469 9470 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9471 "stat_EtherStatsPktsTx64Octets", 9472 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9473 0, "Bytes sent in 64 byte packets"); 9474 9475 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9476 "stat_EtherStatsPktsTx65Octetsto127Octets", 9477 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9478 0, "Bytes sent in 65 to 127 byte packets"); 9479 9480 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9481 "stat_EtherStatsPktsTx128Octetsto255Octets", 9482 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9483 0, "Bytes sent in 128 to 255 byte packets"); 9484 9485 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9486 "stat_EtherStatsPktsTx256Octetsto511Octets", 9487 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9488 0, "Bytes sent in 256 to 511 byte packets"); 9489 9490 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9491 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9492 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9493 0, "Bytes sent in 512 to 1023 byte packets"); 9494 9495 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9496 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9497 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9498 0, "Bytes sent in 1024 to 1522 byte packets"); 9499 9500 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9501 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9502 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9503 0, "Bytes sent in 1523 to 9022 byte packets"); 9504 9505 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9506 "stat_XonPauseFramesReceived", 9507 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9508 0, "XON pause frames receved"); 9509 9510 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9511 "stat_XoffPauseFramesReceived", 9512 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9513 0, "XOFF pause frames received"); 9514 9515 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9516 "stat_OutXonSent", 9517 CTLFLAG_RD, &sc->stat_OutXonSent, 9518 0, "XON pause frames sent"); 9519 9520 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9521 "stat_OutXoffSent", 9522 CTLFLAG_RD, &sc->stat_OutXoffSent, 9523 0, "XOFF pause frames sent"); 9524 9525 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9526 "stat_FlowControlDone", 9527 CTLFLAG_RD, &sc->stat_FlowControlDone, 9528 0, "Flow control done"); 9529 9530 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9531 "stat_MacControlFramesReceived", 9532 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9533 0, "MAC control frames received"); 9534 9535 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9536 "stat_XoffStateEntered", 9537 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9538 0, "XOFF state entered"); 9539 9540 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9541 "stat_IfInFramesL2FilterDiscards", 9542 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9543 0, "Received L2 packets discarded"); 9544 9545 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9546 "stat_IfInRuleCheckerDiscards", 9547 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9548 0, "Received packets discarded by rule"); 9549 9550 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9551 "stat_IfInFTQDiscards", 9552 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9553 0, "Received packet FTQ discards"); 9554 9555 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9556 "stat_IfInMBUFDiscards", 9557 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9558 0, "Received packets discarded due to lack " 9559 "of controller buffer memory"); 9560 9561 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9562 "stat_IfInRuleCheckerP4Hit", 9563 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9564 0, "Received packets rule checker hits"); 9565 9566 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9567 "stat_CatchupInRuleCheckerDiscards", 9568 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9569 0, "Received packets discarded in Catchup path"); 9570 9571 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9572 "stat_CatchupInFTQDiscards", 9573 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9574 0, "Received packets discarded in FTQ in Catchup path"); 9575 9576 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9577 "stat_CatchupInMBUFDiscards", 9578 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9579 0, "Received packets discarded in controller " 9580 "buffer memory in Catchup path"); 9581 9582 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9583 "stat_CatchupInRuleCheckerP4Hit", 9584 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9585 0, "Received packets rule checker hits in Catchup path"); 9586 9587 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9588 "com_no_buffers", 9589 CTLFLAG_RD, &sc->com_no_buffers, 9590 0, "Valid packets received but no RX buffers available"); 9591 9592 #ifdef BCE_DEBUG 9593 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9594 "driver_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9595 (void *)sc, 0, 9596 bce_sysctl_driver_state, "I", "Drive state information"); 9597 9598 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9599 "hw_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9600 (void *)sc, 0, 9601 bce_sysctl_hw_state, "I", "Hardware state information"); 9602 9603 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9604 "status_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9605 (void *)sc, 0, 9606 bce_sysctl_status_block, "I", "Dump status block"); 9607 9608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9609 "stats_block", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9610 (void *)sc, 0, 9611 bce_sysctl_stats_block, "I", "Dump statistics block"); 9612 9613 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9614 "stats_clear", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9615 (void *)sc, 0, 9616 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9617 9618 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9619 "shmem_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9620 (void *)sc, 0, 9621 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9622 9623 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9624 "bc_state", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9625 (void *)sc, 0, 9626 bce_sysctl_bc_state, "I", "Bootcode state information"); 9627 9628 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9629 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9630 (void *)sc, 0, 9631 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9632 9633 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9634 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9635 (void *)sc, 0, 9636 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9637 9638 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9639 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9640 (void *)sc, 0, 9641 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9642 9643 if (bce_hdr_split == TRUE) { 9644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9645 "dump_pg_chain", 9646 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9647 (void *)sc, 0, 9648 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9649 } 9650 9651 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9652 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9653 (void *)sc, 0, 9654 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9655 9656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9657 "breakpoint", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9658 (void *)sc, 0, 9659 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9660 9661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9662 "reg_read", CTLTYPE_INT | CTLFLAG_RW| CTLFLAG_NEEDGIANT, 9663 (void *)sc, 0, 9664 bce_sysctl_reg_read, "I", "Register read"); 9665 9666 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9667 "nvram_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9668 (void *)sc, 0, 9669 bce_sysctl_nvram_read, "I", "NVRAM read"); 9670 9671 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9672 "phy_read", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 9673 (void *)sc, 0, 9674 bce_sysctl_phy_read, "I", "PHY register read"); 9675 9676 #endif 9677 9678 DBEXIT(BCE_VERBOSE_MISC); 9679 } 9680 9681 9682 /****************************************************************************/ 9683 /* BCE Debug Routines */ 9684 /****************************************************************************/ 9685 #ifdef BCE_DEBUG 9686 9687 /****************************************************************************/ 9688 /* Freezes the controller to allow for a cohesive state dump. */ 9689 /* */ 9690 /* Returns: */ 9691 /* Nothing. */ 9692 /****************************************************************************/ 9693 static __attribute__ ((noinline)) void 9694 bce_freeze_controller(struct bce_softc *sc) 9695 { 9696 u32 val; 9697 val = REG_RD(sc, BCE_MISC_COMMAND); 9698 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9699 REG_WR(sc, BCE_MISC_COMMAND, val); 9700 } 9701 9702 9703 /****************************************************************************/ 9704 /* Unfreezes the controller after a freeze operation. This may not always */ 9705 /* work and the controller will require a reset! */ 9706 /* */ 9707 /* Returns: */ 9708 /* Nothing. */ 9709 /****************************************************************************/ 9710 static __attribute__ ((noinline)) void 9711 bce_unfreeze_controller(struct bce_softc *sc) 9712 { 9713 u32 val; 9714 val = REG_RD(sc, BCE_MISC_COMMAND); 9715 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9716 REG_WR(sc, BCE_MISC_COMMAND, val); 9717 } 9718 9719 9720 /****************************************************************************/ 9721 /* Prints out Ethernet frame information from an mbuf. */ 9722 /* */ 9723 /* Partially decode an Ethernet frame to look at some important headers. */ 9724 /* */ 9725 /* Returns: */ 9726 /* Nothing. */ 9727 /****************************************************************************/ 9728 static __attribute__ ((noinline)) void 9729 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9730 { 9731 struct ether_vlan_header *eh; 9732 u16 etype; 9733 int ehlen; 9734 struct ip *ip; 9735 struct tcphdr *th; 9736 struct udphdr *uh; 9737 struct arphdr *ah; 9738 9739 BCE_PRINTF( 9740 "-----------------------------" 9741 " Frame Decode " 9742 "-----------------------------\n"); 9743 9744 eh = mtod(m, struct ether_vlan_header *); 9745 9746 /* Handle VLAN encapsulation if present. */ 9747 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9748 etype = ntohs(eh->evl_proto); 9749 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9750 } else { 9751 etype = ntohs(eh->evl_encap_proto); 9752 ehlen = ETHER_HDR_LEN; 9753 } 9754 9755 /* ToDo: Add VLAN output. */ 9756 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9757 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9758 9759 switch (etype) { 9760 case ETHERTYPE_IP: 9761 ip = (struct ip *)(m->m_data + ehlen); 9762 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9763 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9764 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9765 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9766 9767 switch (ip->ip_p) { 9768 case IPPROTO_TCP: 9769 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9770 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9771 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9772 ntohs(th->th_dport), ntohs(th->th_sport), 9773 (th->th_off << 2), th->th_flags, 9774 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9775 "\02SYN\01FIN", ntohs(th->th_sum)); 9776 break; 9777 case IPPROTO_UDP: 9778 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9779 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9780 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9781 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9782 ntohs(uh->uh_sum)); 9783 break; 9784 case IPPROTO_ICMP: 9785 BCE_PRINTF("icmp:\n"); 9786 break; 9787 default: 9788 BCE_PRINTF("----: Other IP protocol.\n"); 9789 } 9790 break; 9791 case ETHERTYPE_IPV6: 9792 BCE_PRINTF("ipv6: No decode supported.\n"); 9793 break; 9794 case ETHERTYPE_ARP: 9795 BCE_PRINTF("-arp: "); 9796 ah = (struct arphdr *) (m->m_data + ehlen); 9797 switch (ntohs(ah->ar_op)) { 9798 case ARPOP_REVREQUEST: 9799 printf("reverse ARP request\n"); 9800 break; 9801 case ARPOP_REVREPLY: 9802 printf("reverse ARP reply\n"); 9803 break; 9804 case ARPOP_REQUEST: 9805 printf("ARP request\n"); 9806 break; 9807 case ARPOP_REPLY: 9808 printf("ARP reply\n"); 9809 break; 9810 default: 9811 printf("other ARP operation\n"); 9812 } 9813 break; 9814 default: 9815 BCE_PRINTF("----: Other protocol.\n"); 9816 } 9817 9818 BCE_PRINTF( 9819 "-----------------------------" 9820 "--------------" 9821 "-----------------------------\n"); 9822 } 9823 9824 9825 /****************************************************************************/ 9826 /* Prints out information about an mbuf. */ 9827 /* */ 9828 /* Returns: */ 9829 /* Nothing. */ 9830 /****************************************************************************/ 9831 static __attribute__ ((noinline)) void 9832 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9833 { 9834 struct mbuf *mp = m; 9835 9836 if (m == NULL) { 9837 BCE_PRINTF("mbuf: null pointer\n"); 9838 return; 9839 } 9840 9841 while (mp) { 9842 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9843 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9844 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9845 9846 if (mp->m_flags & M_PKTHDR) { 9847 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9848 "csum_flags = %b\n", mp->m_pkthdr.len, 9849 mp->m_flags, M_FLAG_PRINTF, 9850 mp->m_pkthdr.csum_flags, CSUM_BITS); 9851 } 9852 9853 if (mp->m_flags & M_EXT) { 9854 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9855 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9856 switch (mp->m_ext.ext_type) { 9857 case EXT_CLUSTER: 9858 printf("EXT_CLUSTER\n"); break; 9859 case EXT_SFBUF: 9860 printf("EXT_SFBUF\n"); break; 9861 case EXT_JUMBO9: 9862 printf("EXT_JUMBO9\n"); break; 9863 case EXT_JUMBO16: 9864 printf("EXT_JUMBO16\n"); break; 9865 case EXT_PACKET: 9866 printf("EXT_PACKET\n"); break; 9867 case EXT_MBUF: 9868 printf("EXT_MBUF\n"); break; 9869 case EXT_NET_DRV: 9870 printf("EXT_NET_DRV\n"); break; 9871 case EXT_MOD_TYPE: 9872 printf("EXT_MDD_TYPE\n"); break; 9873 case EXT_DISPOSABLE: 9874 printf("EXT_DISPOSABLE\n"); break; 9875 case EXT_EXTREF: 9876 printf("EXT_EXTREF\n"); break; 9877 default: 9878 printf("UNKNOWN\n"); 9879 } 9880 } 9881 9882 mp = mp->m_next; 9883 } 9884 } 9885 9886 9887 /****************************************************************************/ 9888 /* Prints out the mbufs in the TX mbuf chain. */ 9889 /* */ 9890 /* Returns: */ 9891 /* Nothing. */ 9892 /****************************************************************************/ 9893 static __attribute__ ((noinline)) void 9894 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9895 { 9896 struct mbuf *m; 9897 9898 BCE_PRINTF( 9899 "----------------------------" 9900 " tx mbuf data " 9901 "----------------------------\n"); 9902 9903 for (int i = 0; i < count; i++) { 9904 m = sc->tx_mbuf_ptr[chain_prod]; 9905 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9906 bce_dump_mbuf(sc, m); 9907 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9908 } 9909 9910 BCE_PRINTF( 9911 "----------------------------" 9912 "----------------" 9913 "----------------------------\n"); 9914 } 9915 9916 9917 /****************************************************************************/ 9918 /* Prints out the mbufs in the RX mbuf chain. */ 9919 /* */ 9920 /* Returns: */ 9921 /* Nothing. */ 9922 /****************************************************************************/ 9923 static __attribute__ ((noinline)) void 9924 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9925 { 9926 struct mbuf *m; 9927 9928 BCE_PRINTF( 9929 "----------------------------" 9930 " rx mbuf data " 9931 "----------------------------\n"); 9932 9933 for (int i = 0; i < count; i++) { 9934 m = sc->rx_mbuf_ptr[chain_prod]; 9935 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9936 bce_dump_mbuf(sc, m); 9937 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9938 } 9939 9940 9941 BCE_PRINTF( 9942 "----------------------------" 9943 "----------------" 9944 "----------------------------\n"); 9945 } 9946 9947 9948 /****************************************************************************/ 9949 /* Prints out the mbufs in the mbuf page chain. */ 9950 /* */ 9951 /* Returns: */ 9952 /* Nothing. */ 9953 /****************************************************************************/ 9954 static __attribute__ ((noinline)) void 9955 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9956 { 9957 struct mbuf *m; 9958 9959 BCE_PRINTF( 9960 "----------------------------" 9961 " pg mbuf data " 9962 "----------------------------\n"); 9963 9964 for (int i = 0; i < count; i++) { 9965 m = sc->pg_mbuf_ptr[chain_prod]; 9966 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9967 bce_dump_mbuf(sc, m); 9968 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9969 } 9970 9971 9972 BCE_PRINTF( 9973 "----------------------------" 9974 "----------------" 9975 "----------------------------\n"); 9976 } 9977 9978 9979 /****************************************************************************/ 9980 /* Prints out a tx_bd structure. */ 9981 /* */ 9982 /* Returns: */ 9983 /* Nothing. */ 9984 /****************************************************************************/ 9985 static __attribute__ ((noinline)) void 9986 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9987 { 9988 int i = 0; 9989 9990 if (idx > MAX_TX_BD_ALLOC) 9991 /* Index out of range. */ 9992 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9993 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9994 /* TX Chain page pointer. */ 9995 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9996 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9997 txbd->tx_bd_haddr_lo); 9998 else { 9999 /* Normal tx_bd entry. */ 10000 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 10001 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 10002 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 10003 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 10004 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 10005 10006 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 10007 if (i>0) 10008 printf("|"); 10009 printf("CONN_FAULT"); 10010 i++; 10011 } 10012 10013 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 10014 if (i>0) 10015 printf("|"); 10016 printf("TCP_UDP_CKSUM"); 10017 i++; 10018 } 10019 10020 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 10021 if (i>0) 10022 printf("|"); 10023 printf("IP_CKSUM"); 10024 i++; 10025 } 10026 10027 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 10028 if (i>0) 10029 printf("|"); 10030 printf("VLAN"); 10031 i++; 10032 } 10033 10034 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 10035 if (i>0) 10036 printf("|"); 10037 printf("COAL_NOW"); 10038 i++; 10039 } 10040 10041 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 10042 if (i>0) 10043 printf("|"); 10044 printf("DONT_GEN_CRC"); 10045 i++; 10046 } 10047 10048 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 10049 if (i>0) 10050 printf("|"); 10051 printf("START"); 10052 i++; 10053 } 10054 10055 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 10056 if (i>0) 10057 printf("|"); 10058 printf("END"); 10059 i++; 10060 } 10061 10062 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 10063 if (i>0) 10064 printf("|"); 10065 printf("LSO"); 10066 i++; 10067 } 10068 10069 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 10070 if (i>0) 10071 printf("|"); 10072 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 10073 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 10074 } 10075 10076 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 10077 if (i>0) 10078 printf("|"); 10079 printf("SW_FLAGS"); 10080 i++; 10081 } 10082 10083 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 10084 if (i>0) 10085 printf("|"); 10086 printf("SNAP)"); 10087 } else { 10088 printf(")\n"); 10089 } 10090 } 10091 } 10092 10093 10094 /****************************************************************************/ 10095 /* Prints out a rx_bd structure. */ 10096 /* */ 10097 /* Returns: */ 10098 /* Nothing. */ 10099 /****************************************************************************/ 10100 static __attribute__ ((noinline)) void 10101 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 10102 { 10103 if (idx > MAX_RX_BD_ALLOC) 10104 /* Index out of range. */ 10105 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 10106 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 10107 /* RX Chain page pointer. */ 10108 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10109 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 10110 rxbd->rx_bd_haddr_lo); 10111 else 10112 /* Normal rx_bd entry. */ 10113 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 10114 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 10115 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 10116 rxbd->rx_bd_flags); 10117 } 10118 10119 10120 /****************************************************************************/ 10121 /* Prints out a rx_bd structure in the page chain. */ 10122 /* */ 10123 /* Returns: */ 10124 /* Nothing. */ 10125 /****************************************************************************/ 10126 static __attribute__ ((noinline)) void 10127 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 10128 { 10129 if (idx > MAX_PG_BD_ALLOC) 10130 /* Index out of range. */ 10131 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 10132 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 10133 /* Page Chain page pointer. */ 10134 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 10135 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 10136 else 10137 /* Normal rx_bd entry. */ 10138 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 10139 "flags = 0x%08X\n", idx, 10140 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 10141 pgbd->rx_bd_len, pgbd->rx_bd_flags); 10142 } 10143 10144 10145 /****************************************************************************/ 10146 /* Prints out a l2_fhdr structure. */ 10147 /* */ 10148 /* Returns: */ 10149 /* Nothing. */ 10150 /****************************************************************************/ 10151 static __attribute__ ((noinline)) void 10152 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 10153 { 10154 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 10155 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 10156 "tcp_udp_xsum = 0x%04X\n", idx, 10157 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 10158 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 10159 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 10160 } 10161 10162 10163 /****************************************************************************/ 10164 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 10165 /* */ 10166 /* Returns: */ 10167 /* Nothing. */ 10168 /****************************************************************************/ 10169 static __attribute__ ((noinline)) void 10170 bce_dump_ctx(struct bce_softc *sc, u16 cid) 10171 { 10172 if (cid > TX_CID) { 10173 BCE_PRINTF(" Unknown CID\n"); 10174 return; 10175 } 10176 10177 BCE_PRINTF( 10178 "----------------------------" 10179 " CTX Data " 10180 "----------------------------\n"); 10181 10182 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 10183 10184 if (cid == RX_CID) { 10185 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 10186 "producer index\n", 10187 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10188 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10189 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10190 BCE_L2CTX_RX_HOST_BSEQ)); 10191 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10192 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10193 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10194 "descriptor address\n", 10195 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10196 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10197 "descriptor address\n", 10198 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10199 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10200 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10201 BCE_L2CTX_RX_NX_BDIDX)); 10202 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10203 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10204 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10205 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10206 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10207 BCE_L2CTX_RX_PG_BUF_SIZE)); 10208 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10209 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10210 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10211 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10212 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10213 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10214 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10215 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10216 BCE_L2CTX_RX_NX_PG_BDIDX)); 10217 } else if (cid == TX_CID) { 10218 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10219 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10220 CTX_RD(sc, GET_CID_ADDR(cid), 10221 BCE_L2CTX_TX_TYPE_XI)); 10222 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10223 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10224 BCE_L2CTX_TX_CMD_TYPE_XI)); 10225 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10226 "h/w buffer descriptor address\n", 10227 CTX_RD(sc, GET_CID_ADDR(cid), 10228 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10229 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10230 "h/w buffer descriptor address\n", 10231 CTX_RD(sc, GET_CID_ADDR(cid), 10232 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10233 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10234 "host producer index\n", 10235 CTX_RD(sc, GET_CID_ADDR(cid), 10236 BCE_L2CTX_TX_HOST_BIDX_XI)); 10237 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10238 "host byte sequence\n", 10239 CTX_RD(sc, GET_CID_ADDR(cid), 10240 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10241 } else { 10242 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10243 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10244 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10245 CTX_RD(sc, GET_CID_ADDR(cid), 10246 BCE_L2CTX_TX_CMD_TYPE)); 10247 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10248 "h/w buffer descriptor address\n", 10249 CTX_RD(sc, GET_CID_ADDR(cid), 10250 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10251 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10252 "h/w buffer descriptor address\n", 10253 CTX_RD(sc, GET_CID_ADDR(cid), 10254 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10255 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10256 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10257 BCE_L2CTX_TX_HOST_BIDX)); 10258 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10259 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10260 BCE_L2CTX_TX_HOST_BSEQ)); 10261 } 10262 } 10263 10264 BCE_PRINTF( 10265 "----------------------------" 10266 " Raw CTX " 10267 "----------------------------\n"); 10268 10269 for (int i = 0x0; i < 0x300; i += 0x10) { 10270 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10271 CTX_RD(sc, GET_CID_ADDR(cid), i), 10272 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10273 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10274 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10275 } 10276 10277 10278 BCE_PRINTF( 10279 "----------------------------" 10280 "----------------" 10281 "----------------------------\n"); 10282 } 10283 10284 10285 /****************************************************************************/ 10286 /* Prints out the FTQ data. */ 10287 /* */ 10288 /* Returns: */ 10289 /* Nothing. */ 10290 /****************************************************************************/ 10291 static __attribute__ ((noinline)) void 10292 bce_dump_ftqs(struct bce_softc *sc) 10293 { 10294 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10295 10296 BCE_PRINTF( 10297 "----------------------------" 10298 " FTQ Data " 10299 "----------------------------\n"); 10300 10301 BCE_PRINTF(" FTQ Command Control Depth_Now " 10302 "Max_Depth Valid_Cnt \n"); 10303 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10304 "---------- ----------\n"); 10305 10306 /* Setup the generic statistic counters for the FTQ valid count. */ 10307 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10308 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10309 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10310 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10311 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10312 10313 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10314 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10315 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10316 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10317 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10318 10319 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10320 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10321 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10322 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10323 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10324 10325 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10326 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10327 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10328 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10329 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10330 10331 /* Input queue to the Receive Lookup state machine */ 10332 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10333 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10334 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10335 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10336 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10337 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10338 cmd, ctl, cur_depth, max_depth, valid_cnt); 10339 10340 /* Input queue to the Receive Processor */ 10341 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10342 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10343 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10344 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10345 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10346 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10347 cmd, ctl, cur_depth, max_depth, valid_cnt); 10348 10349 /* Input queue to the Recevie Processor */ 10350 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10351 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10352 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10353 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10354 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10355 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10356 cmd, ctl, cur_depth, max_depth, valid_cnt); 10357 10358 /* Input queue to the Receive Virtual to Physical state machine */ 10359 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10360 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10361 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10362 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10363 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10364 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10365 cmd, ctl, cur_depth, max_depth, valid_cnt); 10366 10367 /* Input queue to the Recevie Virtual to Physical state machine */ 10368 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10369 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10370 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10371 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10372 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10373 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10374 cmd, ctl, cur_depth, max_depth, valid_cnt); 10375 10376 /* Input queue to the Receive Virtual to Physical state machine */ 10377 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10378 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10379 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10380 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10381 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10382 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10383 cmd, ctl, cur_depth, max_depth, valid_cnt); 10384 10385 /* Input queue to the Receive DMA state machine */ 10386 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10387 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10388 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10389 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10390 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10391 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10392 cmd, ctl, cur_depth, max_depth, valid_cnt); 10393 10394 /* Input queue to the Transmit Scheduler state machine */ 10395 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10396 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10397 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10398 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10399 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10400 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10401 cmd, ctl, cur_depth, max_depth, valid_cnt); 10402 10403 /* Input queue to the Transmit Buffer Descriptor state machine */ 10404 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10405 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10406 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10407 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10408 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10409 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10410 cmd, ctl, cur_depth, max_depth, valid_cnt); 10411 10412 /* Input queue to the Transmit Processor */ 10413 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10414 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10415 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10416 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10417 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10418 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10419 cmd, ctl, cur_depth, max_depth, valid_cnt); 10420 10421 /* Input queue to the Transmit DMA state machine */ 10422 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10423 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10424 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10425 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10426 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10427 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10428 cmd, ctl, cur_depth, max_depth, valid_cnt); 10429 10430 /* Input queue to the Transmit Patch-Up Processor */ 10431 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10432 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10433 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10434 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10435 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10436 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10437 cmd, ctl, cur_depth, max_depth, valid_cnt); 10438 10439 /* Input queue to the Transmit Assembler state machine */ 10440 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10441 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10442 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10443 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10444 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10445 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10446 cmd, ctl, cur_depth, max_depth, valid_cnt); 10447 10448 /* Input queue to the Completion Processor */ 10449 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10450 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10451 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10452 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10453 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10454 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10455 cmd, ctl, cur_depth, max_depth, valid_cnt); 10456 10457 /* Input queue to the Completion Processor */ 10458 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10459 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10460 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10461 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10462 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10463 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10464 cmd, ctl, cur_depth, max_depth, valid_cnt); 10465 10466 /* Input queue to the Completion Processor */ 10467 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10468 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10469 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10470 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10471 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10472 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10473 cmd, ctl, cur_depth, max_depth, valid_cnt); 10474 10475 /* Setup the generic statistic counters for the FTQ valid count. */ 10476 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10477 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10478 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10479 10480 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10481 val = val | 10482 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10483 24); 10484 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10485 10486 /* Input queue to the Management Control Processor */ 10487 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10488 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10489 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10490 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10491 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10492 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10493 cmd, ctl, cur_depth, max_depth, valid_cnt); 10494 10495 /* Input queue to the Command Processor */ 10496 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10497 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10498 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10499 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10500 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10501 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10502 cmd, ctl, cur_depth, max_depth, valid_cnt); 10503 10504 /* Input queue to the Completion Scheduler state machine */ 10505 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10506 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10507 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10508 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10509 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10510 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10511 cmd, ctl, cur_depth, max_depth, valid_cnt); 10512 10513 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10514 /* Input queue to the RV2P Command Scheduler */ 10515 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10516 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10517 cur_depth = (ctl & 0xFFC00000) >> 22; 10518 max_depth = (ctl & 0x003FF000) >> 12; 10519 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10520 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10521 cmd, ctl, cur_depth, max_depth, valid_cnt); 10522 } 10523 10524 BCE_PRINTF( 10525 "----------------------------" 10526 "----------------" 10527 "----------------------------\n"); 10528 } 10529 10530 10531 /****************************************************************************/ 10532 /* Prints out the TX chain. */ 10533 /* */ 10534 /* Returns: */ 10535 /* Nothing. */ 10536 /****************************************************************************/ 10537 static __attribute__ ((noinline)) void 10538 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10539 { 10540 struct tx_bd *txbd; 10541 10542 /* First some info about the tx_bd chain structure. */ 10543 BCE_PRINTF( 10544 "----------------------------" 10545 " tx_bd chain " 10546 "----------------------------\n"); 10547 10548 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10549 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10550 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10551 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10552 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10553 10554 BCE_PRINTF( 10555 "----------------------------" 10556 " tx_bd data " 10557 "----------------------------\n"); 10558 10559 /* Now print out a decoded list of TX buffer descriptors. */ 10560 for (int i = 0; i < count; i++) { 10561 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10562 bce_dump_txbd(sc, tx_prod, txbd); 10563 tx_prod++; 10564 } 10565 10566 BCE_PRINTF( 10567 "----------------------------" 10568 "----------------" 10569 "----------------------------\n"); 10570 } 10571 10572 10573 /****************************************************************************/ 10574 /* Prints out the RX chain. */ 10575 /* */ 10576 /* Returns: */ 10577 /* Nothing. */ 10578 /****************************************************************************/ 10579 static __attribute__ ((noinline)) void 10580 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10581 { 10582 struct rx_bd *rxbd; 10583 10584 /* First some info about the rx_bd chain structure. */ 10585 BCE_PRINTF( 10586 "----------------------------" 10587 " rx_bd chain " 10588 "----------------------------\n"); 10589 10590 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10591 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10592 10593 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10594 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10595 10596 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10597 10598 BCE_PRINTF( 10599 "----------------------------" 10600 " rx_bd data " 10601 "----------------------------\n"); 10602 10603 /* Now print out the rx_bd's themselves. */ 10604 for (int i = 0; i < count; i++) { 10605 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10606 bce_dump_rxbd(sc, rx_prod, rxbd); 10607 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10608 } 10609 10610 BCE_PRINTF( 10611 "----------------------------" 10612 "----------------" 10613 "----------------------------\n"); 10614 } 10615 10616 10617 /****************************************************************************/ 10618 /* Prints out the page chain. */ 10619 /* */ 10620 /* Returns: */ 10621 /* Nothing. */ 10622 /****************************************************************************/ 10623 static __attribute__ ((noinline)) void 10624 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10625 { 10626 struct rx_bd *pgbd; 10627 10628 /* First some info about the page chain structure. */ 10629 BCE_PRINTF( 10630 "----------------------------" 10631 " page chain " 10632 "----------------------------\n"); 10633 10634 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10635 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10636 10637 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10638 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10639 10640 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10641 10642 BCE_PRINTF( 10643 "----------------------------" 10644 " page data " 10645 "----------------------------\n"); 10646 10647 /* Now print out the rx_bd's themselves. */ 10648 for (int i = 0; i < count; i++) { 10649 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10650 bce_dump_pgbd(sc, pg_prod, pgbd); 10651 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10652 } 10653 10654 BCE_PRINTF( 10655 "----------------------------" 10656 "----------------" 10657 "----------------------------\n"); 10658 } 10659 10660 10661 #define BCE_PRINT_RX_CONS(arg) \ 10662 if (sblk->status_rx_quick_consumer_index##arg) \ 10663 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10664 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10665 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10666 arg); 10667 10668 10669 #define BCE_PRINT_TX_CONS(arg) \ 10670 if (sblk->status_tx_quick_consumer_index##arg) \ 10671 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10672 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10673 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10674 arg); 10675 10676 /****************************************************************************/ 10677 /* Prints out the status block from host memory. */ 10678 /* */ 10679 /* Returns: */ 10680 /* Nothing. */ 10681 /****************************************************************************/ 10682 static __attribute__ ((noinline)) void 10683 bce_dump_status_block(struct bce_softc *sc) 10684 { 10685 struct status_block *sblk; 10686 10687 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10688 10689 sblk = sc->status_block; 10690 10691 BCE_PRINTF( 10692 "----------------------------" 10693 " Status Block " 10694 "----------------------------\n"); 10695 10696 /* Theses indices are used for normal L2 drivers. */ 10697 BCE_PRINTF(" 0x%08X - attn_bits\n", 10698 sblk->status_attn_bits); 10699 10700 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10701 sblk->status_attn_bits_ack); 10702 10703 BCE_PRINT_RX_CONS(0); 10704 BCE_PRINT_TX_CONS(0) 10705 10706 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10707 10708 /* Theses indices are not used for normal L2 drivers. */ 10709 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10710 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10711 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10712 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10713 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10714 10715 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10716 10717 if (sblk->status_completion_producer_index || 10718 sblk->status_cmd_consumer_index) 10719 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10720 sblk->status_completion_producer_index, 10721 sblk->status_cmd_consumer_index); 10722 10723 BCE_PRINTF( 10724 "----------------------------" 10725 "----------------" 10726 "----------------------------\n"); 10727 } 10728 10729 10730 #define BCE_PRINT_64BIT_STAT(arg) \ 10731 if (sblk->arg##_lo || sblk->arg##_hi) \ 10732 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10733 sblk->arg##_lo, #arg); 10734 10735 #define BCE_PRINT_32BIT_STAT(arg) \ 10736 if (sblk->arg) \ 10737 BCE_PRINTF(" 0x%08X : %s\n", \ 10738 sblk->arg, #arg); 10739 10740 /****************************************************************************/ 10741 /* Prints out the statistics block from host memory. */ 10742 /* */ 10743 /* Returns: */ 10744 /* Nothing. */ 10745 /****************************************************************************/ 10746 static __attribute__ ((noinline)) void 10747 bce_dump_stats_block(struct bce_softc *sc) 10748 { 10749 struct statistics_block *sblk; 10750 10751 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10752 10753 sblk = sc->stats_block; 10754 10755 BCE_PRINTF( 10756 "---------------" 10757 " Stats Block (All Stats Not Shown Are 0) " 10758 "---------------\n"); 10759 10760 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10761 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10762 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10763 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10764 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10765 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10766 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10767 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10768 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10769 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10770 BCE_PRINT_32BIT_STAT( 10771 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10772 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10773 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10774 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10775 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10776 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10777 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10778 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10779 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10780 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10781 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10782 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10783 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10784 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10785 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10786 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10787 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10788 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10789 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10790 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10791 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10792 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10793 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10794 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10795 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10796 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10797 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10798 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10799 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10800 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10801 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10802 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10803 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10804 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10805 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10806 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10807 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10808 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10809 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10810 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10811 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10812 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10813 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10814 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10815 10816 BCE_PRINTF( 10817 "----------------------------" 10818 "----------------" 10819 "----------------------------\n"); 10820 } 10821 10822 10823 /****************************************************************************/ 10824 /* Prints out a summary of the driver state. */ 10825 /* */ 10826 /* Returns: */ 10827 /* Nothing. */ 10828 /****************************************************************************/ 10829 static __attribute__ ((noinline)) void 10830 bce_dump_driver_state(struct bce_softc *sc) 10831 { 10832 u32 val_hi, val_lo; 10833 10834 BCE_PRINTF( 10835 "-----------------------------" 10836 " Driver State " 10837 "-----------------------------\n"); 10838 10839 val_hi = BCE_ADDR_HI(sc); 10840 val_lo = BCE_ADDR_LO(sc); 10841 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10842 "address\n", val_hi, val_lo); 10843 10844 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10845 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10846 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10847 "address\n", val_hi, val_lo); 10848 10849 val_hi = BCE_ADDR_HI(sc->status_block); 10850 val_lo = BCE_ADDR_LO(sc->status_block); 10851 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10852 "virtual address\n", val_hi, val_lo); 10853 10854 val_hi = BCE_ADDR_HI(sc->stats_block); 10855 val_lo = BCE_ADDR_LO(sc->stats_block); 10856 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10857 "virtual address\n", val_hi, val_lo); 10858 10859 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10860 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10861 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10862 "virtual adddress\n", val_hi, val_lo); 10863 10864 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10865 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10866 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10867 "virtual address\n", val_hi, val_lo); 10868 10869 if (bce_hdr_split == TRUE) { 10870 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10871 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10872 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10873 "virtual address\n", val_hi, val_lo); 10874 } 10875 10876 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10877 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10878 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10879 "virtual address\n", val_hi, val_lo); 10880 10881 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10882 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10883 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10884 "virtual address\n", val_hi, val_lo); 10885 10886 if (bce_hdr_split == TRUE) { 10887 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10888 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10889 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10890 "virtual address\n", val_hi, val_lo); 10891 } 10892 10893 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10894 "h/w intrs\n", 10895 (long long unsigned int) sc->interrupts_generated); 10896 10897 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10898 "rx interrupts handled\n", 10899 (long long unsigned int) sc->interrupts_rx); 10900 10901 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10902 "tx interrupts handled\n", 10903 (long long unsigned int) sc->interrupts_tx); 10904 10905 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10906 "phy interrupts handled\n", 10907 (long long unsigned int) sc->phy_interrupts); 10908 10909 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10910 "status block index\n", sc->last_status_idx); 10911 10912 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10913 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10914 10915 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10916 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10917 10918 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10919 "byte seq index\n", sc->tx_prod_bseq); 10920 10921 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10922 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10923 10924 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10925 "tx_bd's\n", sc->used_tx_bd); 10926 10927 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10928 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10929 10930 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10931 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10932 10933 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10934 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10935 10936 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10937 "byte seq index\n", sc->rx_prod_bseq); 10938 10939 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10940 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10941 10942 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10943 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10944 10945 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10946 "rx_bd's\n", sc->free_rx_bd); 10947 10948 if (bce_hdr_split == TRUE) { 10949 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10950 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10951 10952 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10953 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10954 10955 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10956 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10957 } 10958 10959 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10960 "rx_bd's\n", sc->free_pg_bd); 10961 10962 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10963 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10964 10965 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10966 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10967 10968 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10969 "bce mac flags\n", sc->bce_flags); 10970 10971 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10972 "bce phy flags\n", sc->bce_phy_flags); 10973 10974 BCE_PRINTF( 10975 "----------------------------" 10976 "----------------" 10977 "----------------------------\n"); 10978 } 10979 10980 10981 /****************************************************************************/ 10982 /* Prints out the hardware state through a summary of important register, */ 10983 /* followed by a complete register dump. */ 10984 /* */ 10985 /* Returns: */ 10986 /* Nothing. */ 10987 /****************************************************************************/ 10988 static __attribute__ ((noinline)) void 10989 bce_dump_hw_state(struct bce_softc *sc) 10990 { 10991 u32 val; 10992 10993 BCE_PRINTF( 10994 "----------------------------" 10995 " Hardware State " 10996 "----------------------------\n"); 10997 10998 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10999 11000 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 11001 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 11002 val, BCE_MISC_ENABLE_STATUS_BITS); 11003 11004 val = REG_RD(sc, BCE_DMA_STATUS); 11005 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 11006 val, BCE_DMA_STATUS); 11007 11008 val = REG_RD(sc, BCE_CTX_STATUS); 11009 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 11010 val, BCE_CTX_STATUS); 11011 11012 val = REG_RD(sc, BCE_EMAC_STATUS); 11013 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 11014 val, BCE_EMAC_STATUS); 11015 11016 val = REG_RD(sc, BCE_RPM_STATUS); 11017 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 11018 val, BCE_RPM_STATUS); 11019 11020 /* ToDo: Create a #define for this constant. */ 11021 val = REG_RD(sc, 0x2004); 11022 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 11023 val, 0x2004); 11024 11025 val = REG_RD(sc, BCE_RV2P_STATUS); 11026 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 11027 val, BCE_RV2P_STATUS); 11028 11029 /* ToDo: Create a #define for this constant. */ 11030 val = REG_RD(sc, 0x2c04); 11031 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 11032 val, 0x2c04); 11033 11034 val = REG_RD(sc, BCE_TBDR_STATUS); 11035 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 11036 val, BCE_TBDR_STATUS); 11037 11038 val = REG_RD(sc, BCE_TDMA_STATUS); 11039 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 11040 val, BCE_TDMA_STATUS); 11041 11042 val = REG_RD(sc, BCE_HC_STATUS); 11043 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 11044 val, BCE_HC_STATUS); 11045 11046 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11047 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11048 val, BCE_TXP_CPU_STATE); 11049 11050 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11051 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11052 val, BCE_TPAT_CPU_STATE); 11053 11054 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11055 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11056 val, BCE_RXP_CPU_STATE); 11057 11058 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11059 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11060 val, BCE_COM_CPU_STATE); 11061 11062 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 11063 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 11064 val, BCE_MCP_CPU_STATE); 11065 11066 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11067 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11068 val, BCE_CP_CPU_STATE); 11069 11070 BCE_PRINTF( 11071 "----------------------------" 11072 "----------------" 11073 "----------------------------\n"); 11074 11075 BCE_PRINTF( 11076 "----------------------------" 11077 " Register Dump " 11078 "----------------------------\n"); 11079 11080 for (int i = 0x400; i < 0x8000; i += 0x10) { 11081 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11082 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11083 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11084 } 11085 11086 BCE_PRINTF( 11087 "----------------------------" 11088 "----------------" 11089 "----------------------------\n"); 11090 } 11091 11092 11093 /****************************************************************************/ 11094 /* Prints out the contentst of shared memory which is used for host driver */ 11095 /* to bootcode firmware communication. */ 11096 /* */ 11097 /* Returns: */ 11098 /* Nothing. */ 11099 /****************************************************************************/ 11100 static __attribute__ ((noinline)) void 11101 bce_dump_shmem_state(struct bce_softc *sc) 11102 { 11103 BCE_PRINTF( 11104 "----------------------------" 11105 " Hardware State " 11106 "----------------------------\n"); 11107 11108 BCE_PRINTF("0x%08X - Shared memory base address\n", 11109 sc->bce_shmem_base); 11110 BCE_PRINTF("%s - bootcode version\n", 11111 sc->bce_bc_ver); 11112 11113 BCE_PRINTF( 11114 "----------------------------" 11115 " Shared Mem " 11116 "----------------------------\n"); 11117 11118 for (int i = 0x0; i < 0x200; i += 0x10) { 11119 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11120 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 11121 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 11122 } 11123 11124 BCE_PRINTF( 11125 "----------------------------" 11126 "----------------" 11127 "----------------------------\n"); 11128 } 11129 11130 11131 /****************************************************************************/ 11132 /* Prints out the mailbox queue registers. */ 11133 /* */ 11134 /* Returns: */ 11135 /* Nothing. */ 11136 /****************************************************************************/ 11137 static __attribute__ ((noinline)) void 11138 bce_dump_mq_regs(struct bce_softc *sc) 11139 { 11140 BCE_PRINTF( 11141 "----------------------------" 11142 " MQ Regs " 11143 "----------------------------\n"); 11144 11145 BCE_PRINTF( 11146 "----------------------------" 11147 "----------------" 11148 "----------------------------\n"); 11149 11150 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 11151 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11152 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11153 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11154 } 11155 11156 BCE_PRINTF( 11157 "----------------------------" 11158 "----------------" 11159 "----------------------------\n"); 11160 } 11161 11162 11163 /****************************************************************************/ 11164 /* Prints out the bootcode state. */ 11165 /* */ 11166 /* Returns: */ 11167 /* Nothing. */ 11168 /****************************************************************************/ 11169 static __attribute__ ((noinline)) void 11170 bce_dump_bc_state(struct bce_softc *sc) 11171 { 11172 u32 val; 11173 11174 BCE_PRINTF( 11175 "----------------------------" 11176 " Bootcode State " 11177 "----------------------------\n"); 11178 11179 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11180 11181 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 11182 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 11183 val, BCE_BC_RESET_TYPE); 11184 11185 val = bce_shmem_rd(sc, BCE_BC_STATE); 11186 BCE_PRINTF("0x%08X - (0x%06X) state\n", 11187 val, BCE_BC_STATE); 11188 11189 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 11190 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 11191 val, BCE_BC_STATE_CONDITION); 11192 11193 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 11194 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 11195 val, BCE_BC_STATE_DEBUG_CMD); 11196 11197 BCE_PRINTF( 11198 "----------------------------" 11199 "----------------" 11200 "----------------------------\n"); 11201 } 11202 11203 11204 /****************************************************************************/ 11205 /* Prints out the TXP processor state. */ 11206 /* */ 11207 /* Returns: */ 11208 /* Nothing. */ 11209 /****************************************************************************/ 11210 static __attribute__ ((noinline)) void 11211 bce_dump_txp_state(struct bce_softc *sc, int regs) 11212 { 11213 u32 val; 11214 u32 fw_version[3]; 11215 11216 BCE_PRINTF( 11217 "----------------------------" 11218 " TXP State " 11219 "----------------------------\n"); 11220 11221 for (int i = 0; i < 3; i++) 11222 fw_version[i] = htonl(REG_RD_IND(sc, 11223 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11224 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11225 11226 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11227 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11228 val, BCE_TXP_CPU_MODE); 11229 11230 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11231 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11232 val, BCE_TXP_CPU_STATE); 11233 11234 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11235 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11236 val, BCE_TXP_CPU_EVENT_MASK); 11237 11238 if (regs) { 11239 BCE_PRINTF( 11240 "----------------------------" 11241 " Register Dump " 11242 "----------------------------\n"); 11243 11244 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11245 /* Skip the big blank spaces */ 11246 if (i < 0x454000 && i > 0x5ffff) 11247 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11248 "0x%08X 0x%08X\n", i, 11249 REG_RD_IND(sc, i), 11250 REG_RD_IND(sc, i + 0x4), 11251 REG_RD_IND(sc, i + 0x8), 11252 REG_RD_IND(sc, i + 0xC)); 11253 } 11254 } 11255 11256 BCE_PRINTF( 11257 "----------------------------" 11258 "----------------" 11259 "----------------------------\n"); 11260 } 11261 11262 11263 /****************************************************************************/ 11264 /* Prints out the RXP processor state. */ 11265 /* */ 11266 /* Returns: */ 11267 /* Nothing. */ 11268 /****************************************************************************/ 11269 static __attribute__ ((noinline)) void 11270 bce_dump_rxp_state(struct bce_softc *sc, int regs) 11271 { 11272 u32 val; 11273 u32 fw_version[3]; 11274 11275 BCE_PRINTF( 11276 "----------------------------" 11277 " RXP State " 11278 "----------------------------\n"); 11279 11280 for (int i = 0; i < 3; i++) 11281 fw_version[i] = htonl(REG_RD_IND(sc, 11282 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11283 11284 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11285 11286 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11287 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11288 val, BCE_RXP_CPU_MODE); 11289 11290 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11291 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11292 val, BCE_RXP_CPU_STATE); 11293 11294 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11295 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11296 val, BCE_RXP_CPU_EVENT_MASK); 11297 11298 if (regs) { 11299 BCE_PRINTF( 11300 "----------------------------" 11301 " Register Dump " 11302 "----------------------------\n"); 11303 11304 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11305 /* Skip the big blank sapces */ 11306 if (i < 0xc5400 && i > 0xdffff) 11307 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11308 "0x%08X 0x%08X\n", i, 11309 REG_RD_IND(sc, i), 11310 REG_RD_IND(sc, i + 0x4), 11311 REG_RD_IND(sc, i + 0x8), 11312 REG_RD_IND(sc, i + 0xC)); 11313 } 11314 } 11315 11316 BCE_PRINTF( 11317 "----------------------------" 11318 "----------------" 11319 "----------------------------\n"); 11320 } 11321 11322 11323 /****************************************************************************/ 11324 /* Prints out the TPAT processor state. */ 11325 /* */ 11326 /* Returns: */ 11327 /* Nothing. */ 11328 /****************************************************************************/ 11329 static __attribute__ ((noinline)) void 11330 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11331 { 11332 u32 val; 11333 u32 fw_version[3]; 11334 11335 BCE_PRINTF( 11336 "----------------------------" 11337 " TPAT State " 11338 "----------------------------\n"); 11339 11340 for (int i = 0; i < 3; i++) 11341 fw_version[i] = htonl(REG_RD_IND(sc, 11342 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11343 11344 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11345 11346 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11347 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11348 val, BCE_TPAT_CPU_MODE); 11349 11350 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11351 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11352 val, BCE_TPAT_CPU_STATE); 11353 11354 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11355 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11356 val, BCE_TPAT_CPU_EVENT_MASK); 11357 11358 if (regs) { 11359 BCE_PRINTF( 11360 "----------------------------" 11361 " Register Dump " 11362 "----------------------------\n"); 11363 11364 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11365 /* Skip the big blank spaces */ 11366 if (i < 0x854000 && i > 0x9ffff) 11367 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11368 "0x%08X 0x%08X\n", i, 11369 REG_RD_IND(sc, i), 11370 REG_RD_IND(sc, i + 0x4), 11371 REG_RD_IND(sc, i + 0x8), 11372 REG_RD_IND(sc, i + 0xC)); 11373 } 11374 } 11375 11376 BCE_PRINTF( 11377 "----------------------------" 11378 "----------------" 11379 "----------------------------\n"); 11380 } 11381 11382 11383 /****************************************************************************/ 11384 /* Prints out the Command Procesor (CP) state. */ 11385 /* */ 11386 /* Returns: */ 11387 /* Nothing. */ 11388 /****************************************************************************/ 11389 static __attribute__ ((noinline)) void 11390 bce_dump_cp_state(struct bce_softc *sc, int regs) 11391 { 11392 u32 val; 11393 u32 fw_version[3]; 11394 11395 BCE_PRINTF( 11396 "----------------------------" 11397 " CP State " 11398 "----------------------------\n"); 11399 11400 for (int i = 0; i < 3; i++) 11401 fw_version[i] = htonl(REG_RD_IND(sc, 11402 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11403 11404 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11405 11406 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11407 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11408 val, BCE_CP_CPU_MODE); 11409 11410 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11411 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11412 val, BCE_CP_CPU_STATE); 11413 11414 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11415 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11416 BCE_CP_CPU_EVENT_MASK); 11417 11418 if (regs) { 11419 BCE_PRINTF( 11420 "----------------------------" 11421 " Register Dump " 11422 "----------------------------\n"); 11423 11424 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11425 /* Skip the big blank spaces */ 11426 if (i < 0x185400 && i > 0x19ffff) 11427 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11428 "0x%08X 0x%08X\n", i, 11429 REG_RD_IND(sc, i), 11430 REG_RD_IND(sc, i + 0x4), 11431 REG_RD_IND(sc, i + 0x8), 11432 REG_RD_IND(sc, i + 0xC)); 11433 } 11434 } 11435 11436 BCE_PRINTF( 11437 "----------------------------" 11438 "----------------" 11439 "----------------------------\n"); 11440 } 11441 11442 11443 /****************************************************************************/ 11444 /* Prints out the Completion Procesor (COM) state. */ 11445 /* */ 11446 /* Returns: */ 11447 /* Nothing. */ 11448 /****************************************************************************/ 11449 static __attribute__ ((noinline)) void 11450 bce_dump_com_state(struct bce_softc *sc, int regs) 11451 { 11452 u32 val; 11453 u32 fw_version[4]; 11454 11455 BCE_PRINTF( 11456 "----------------------------" 11457 " COM State " 11458 "----------------------------\n"); 11459 11460 for (int i = 0; i < 3; i++) 11461 fw_version[i] = htonl(REG_RD_IND(sc, 11462 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11463 11464 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11465 11466 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11467 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11468 val, BCE_COM_CPU_MODE); 11469 11470 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11471 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11472 val, BCE_COM_CPU_STATE); 11473 11474 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11475 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11476 BCE_COM_CPU_EVENT_MASK); 11477 11478 if (regs) { 11479 BCE_PRINTF( 11480 "----------------------------" 11481 " Register Dump " 11482 "----------------------------\n"); 11483 11484 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11485 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11486 "0x%08X 0x%08X\n", i, 11487 REG_RD_IND(sc, i), 11488 REG_RD_IND(sc, i + 0x4), 11489 REG_RD_IND(sc, i + 0x8), 11490 REG_RD_IND(sc, i + 0xC)); 11491 } 11492 } 11493 11494 BCE_PRINTF( 11495 "----------------------------" 11496 "----------------" 11497 "----------------------------\n"); 11498 } 11499 11500 11501 /****************************************************************************/ 11502 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11503 /* */ 11504 /* Returns: */ 11505 /* Nothing. */ 11506 /****************************************************************************/ 11507 static __attribute__ ((noinline)) void 11508 bce_dump_rv2p_state(struct bce_softc *sc) 11509 { 11510 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11511 11512 BCE_PRINTF( 11513 "----------------------------" 11514 " RV2P State " 11515 "----------------------------\n"); 11516 11517 /* Stall the RV2P processors. */ 11518 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11519 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11520 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11521 11522 /* Read the firmware version. */ 11523 val = 0x00000001; 11524 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11525 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11526 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11527 BCE_RV2P_INSTR_HIGH_HIGH; 11528 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11529 fw_ver_high, fw_ver_low); 11530 11531 val = 0x00000001; 11532 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11533 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11534 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11535 BCE_RV2P_INSTR_HIGH_HIGH; 11536 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11537 fw_ver_high, fw_ver_low); 11538 11539 /* Resume the RV2P processors. */ 11540 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11541 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11542 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11543 11544 /* Fetch the program counter value. */ 11545 val = 0x68007800; 11546 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11547 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11548 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11549 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11550 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11551 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11552 11553 /* Fetch the program counter value again to see if it is advancing. */ 11554 val = 0x68007800; 11555 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11556 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11557 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11558 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11559 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11560 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11561 11562 BCE_PRINTF( 11563 "----------------------------" 11564 "----------------" 11565 "----------------------------\n"); 11566 } 11567 11568 11569 /****************************************************************************/ 11570 /* Prints out the driver state and then enters the debugger. */ 11571 /* */ 11572 /* Returns: */ 11573 /* Nothing. */ 11574 /****************************************************************************/ 11575 static __attribute__ ((noinline)) void 11576 bce_breakpoint(struct bce_softc *sc) 11577 { 11578 11579 /* 11580 * Unreachable code to silence compiler warnings 11581 * about unused functions. 11582 */ 11583 if (0) { 11584 bce_freeze_controller(sc); 11585 bce_unfreeze_controller(sc); 11586 bce_dump_enet(sc, NULL); 11587 bce_dump_txbd(sc, 0, NULL); 11588 bce_dump_rxbd(sc, 0, NULL); 11589 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11590 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11591 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11592 bce_dump_l2fhdr(sc, 0, NULL); 11593 bce_dump_ctx(sc, RX_CID); 11594 bce_dump_ftqs(sc); 11595 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11596 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11597 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11598 bce_dump_status_block(sc); 11599 bce_dump_stats_block(sc); 11600 bce_dump_driver_state(sc); 11601 bce_dump_hw_state(sc); 11602 bce_dump_bc_state(sc); 11603 bce_dump_txp_state(sc, 0); 11604 bce_dump_rxp_state(sc, 0); 11605 bce_dump_tpat_state(sc, 0); 11606 bce_dump_cp_state(sc, 0); 11607 bce_dump_com_state(sc, 0); 11608 bce_dump_rv2p_state(sc); 11609 bce_dump_pgbd(sc, 0, NULL); 11610 } 11611 11612 bce_dump_status_block(sc); 11613 bce_dump_driver_state(sc); 11614 11615 /* Call the debugger. */ 11616 breakpoint(); 11617 } 11618 #endif 11619