1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2014 QLogic Corporation 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * The following controllers are supported by this driver: 34 * BCM5706C A2, A3 35 * BCM5706S A2, A3 36 * BCM5708C B1, B2 37 * BCM5708S B1, B2 38 * BCM5709C A1, C0 39 * BCM5709S A1, C0 40 * BCM5716C C0 41 * BCM5716S C0 42 * 43 * The following controllers are not supported by this driver: 44 * BCM5706C A0, A1 (pre-production) 45 * BCM5706S A0, A1 (pre-production) 46 * BCM5708C A0, B0 (pre-production) 47 * BCM5708S A0, B0 (pre-production) 48 * BCM5709C A0 B0, B1, B2 (pre-production) 49 * BCM5709S A0, B0, B1, B2 (pre-production) 50 */ 51 52 #include "opt_bce.h" 53 54 #include <sys/param.h> 55 #include <sys/endian.h> 56 #include <sys/systm.h> 57 #include <sys/sockio.h> 58 #include <sys/lock.h> 59 #include <sys/mbuf.h> 60 #include <sys/malloc.h> 61 #include <sys/mutex.h> 62 #include <sys/kernel.h> 63 #include <sys/module.h> 64 #include <sys/socket.h> 65 #include <sys/sysctl.h> 66 #include <sys/queue.h> 67 68 #include <net/bpf.h> 69 #include <net/ethernet.h> 70 #include <net/if.h> 71 #include <net/if_var.h> 72 #include <net/if_arp.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/if_types.h> 77 #include <net/if_vlan_var.h> 78 79 #include <netinet/in_systm.h> 80 #include <netinet/in.h> 81 #include <netinet/if_ether.h> 82 #include <netinet/ip.h> 83 #include <netinet/ip6.h> 84 #include <netinet/tcp.h> 85 #include <netinet/udp.h> 86 87 #include <machine/bus.h> 88 #include <machine/resource.h> 89 #include <sys/bus.h> 90 #include <sys/rman.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 #include "miidevs.h" 95 #include <dev/mii/brgphyreg.h> 96 97 #include <dev/pci/pcireg.h> 98 #include <dev/pci/pcivar.h> 99 100 #include "miibus_if.h" 101 102 #include <dev/bce/if_bcereg.h> 103 #include <dev/bce/if_bcefw.h> 104 105 /****************************************************************************/ 106 /* BCE Debug Options */ 107 /****************************************************************************/ 108 #ifdef BCE_DEBUG 109 u32 bce_debug = BCE_WARN; 110 111 /* 0 = Never */ 112 /* 1 = 1 in 2,147,483,648 */ 113 /* 256 = 1 in 8,388,608 */ 114 /* 2048 = 1 in 1,048,576 */ 115 /* 65536 = 1 in 32,768 */ 116 /* 1048576 = 1 in 2,048 */ 117 /* 268435456 = 1 in 8 */ 118 /* 536870912 = 1 in 4 */ 119 /* 1073741824 = 1 in 2 */ 120 121 /* Controls how often the l2_fhdr frame error check will fail. */ 122 int l2fhdr_error_sim_control = 0; 123 124 /* Controls how often the unexpected attention check will fail. */ 125 int unexpected_attention_sim_control = 0; 126 127 /* Controls how often to simulate an mbuf allocation failure. */ 128 int mbuf_alloc_failed_sim_control = 0; 129 130 /* Controls how often to simulate a DMA mapping failure. */ 131 int dma_map_addr_failed_sim_control = 0; 132 133 /* Controls how often to simulate a bootcode failure. */ 134 int bootcode_running_failure_sim_control = 0; 135 #endif 136 137 /****************************************************************************/ 138 /* PCI Device ID Table */ 139 /* */ 140 /* Used by bce_probe() to identify the devices supported by this driver. */ 141 /****************************************************************************/ 142 #define BCE_DEVDESC_MAX 64 143 144 static const struct bce_type bce_devs[] = { 145 /* BCM5706C Controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 147 "HP NC370T Multifunction Gigabit Server Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 149 "HP NC370i Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 151 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 153 "HP NC371i Multifunction Gigabit Server Adapter" }, 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 155 "QLogic NetXtreme II BCM5706 1000Base-T" }, 156 157 /* BCM5706S controllers and OEM boards. */ 158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 159 "HP NC370F Multifunction Gigabit Server Adapter" }, 160 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 161 "QLogic NetXtreme II BCM5706 1000Base-SX" }, 162 163 /* BCM5708C controllers and OEM boards. */ 164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 165 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 167 "HP NC373i Multifunction Gigabit Server Adapter" }, 168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 169 "HP NC374m PCIe Multifunction Adapter" }, 170 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 171 "QLogic NetXtreme II BCM5708 1000Base-T" }, 172 173 /* BCM5708S controllers and OEM boards. */ 174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 175 "HP NC373m Multifunction Gigabit Server Adapter" }, 176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 177 "HP NC373i Multifunction Gigabit Server Adapter" }, 178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 179 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 180 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 181 "QLogic NetXtreme II BCM5708 1000Base-SX" }, 182 183 /* BCM5709C controllers and OEM boards. */ 184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 185 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 187 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 188 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 189 "QLogic NetXtreme II BCM5709 1000Base-T" }, 190 191 /* BCM5709S controllers and OEM boards. */ 192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 193 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 195 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 196 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 197 "QLogic NetXtreme II BCM5709 1000Base-SX" }, 198 199 /* BCM5716 controllers and OEM boards. */ 200 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 201 "QLogic NetXtreme II BCM5716 1000Base-T" }, 202 203 { 0, 0, 0, 0, NULL } 204 }; 205 206 207 /****************************************************************************/ 208 /* Supported Flash NVRAM device data. */ 209 /****************************************************************************/ 210 static const struct flash_spec flash_table[] = 211 { 212 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 213 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 214 215 /* Slow EEPROM */ 216 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 217 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 218 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 219 "EEPROM - slow"}, 220 /* Expansion entry 0001 */ 221 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 222 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 223 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 224 "Entry 0001"}, 225 /* Saifun SA25F010 (non-buffered flash) */ 226 /* strap, cfg1, & write1 need updates */ 227 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 228 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 229 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 230 "Non-buffered flash (128kB)"}, 231 /* Saifun SA25F020 (non-buffered flash) */ 232 /* strap, cfg1, & write1 need updates */ 233 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 236 "Non-buffered flash (256kB)"}, 237 /* Expansion entry 0100 */ 238 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 0100"}, 242 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 243 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 244 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 245 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 246 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 247 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 248 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 249 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 250 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 251 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 252 /* Saifun SA25F005 (non-buffered flash) */ 253 /* strap, cfg1, & write1 need updates */ 254 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 255 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 256 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 257 "Non-buffered flash (64kB)"}, 258 /* Fast EEPROM */ 259 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 260 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 261 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 262 "EEPROM - fast"}, 263 /* Expansion entry 1001 */ 264 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 265 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 266 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 267 "Entry 1001"}, 268 /* Expansion entry 1010 */ 269 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 270 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 271 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 272 "Entry 1010"}, 273 /* ATMEL AT45DB011B (buffered flash) */ 274 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 275 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 276 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 277 "Buffered flash (128kB)"}, 278 /* Expansion entry 1100 */ 279 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 280 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 281 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 282 "Entry 1100"}, 283 /* Expansion entry 1101 */ 284 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 285 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 286 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 287 "Entry 1101"}, 288 /* Ateml Expansion entry 1110 */ 289 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 290 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 291 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 292 "Entry 1110 (Atmel)"}, 293 /* ATMEL AT45DB021B (buffered flash) */ 294 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 295 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 296 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 297 "Buffered flash (256kB)"}, 298 }; 299 300 /* 301 * The BCM5709 controllers transparently handle the 302 * differences between Atmel 264 byte pages and all 303 * flash devices which use 256 byte pages, so no 304 * logical-to-physical mapping is required in the 305 * driver. 306 */ 307 static const struct flash_spec flash_5709 = { 308 .flags = BCE_NV_BUFFERED, 309 .page_bits = BCM5709_FLASH_PAGE_BITS, 310 .page_size = BCM5709_FLASH_PAGE_SIZE, 311 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 312 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 313 .name = "5709/5716 buffered flash (256kB)", 314 }; 315 316 317 /****************************************************************************/ 318 /* FreeBSD device entry points. */ 319 /****************************************************************************/ 320 static int bce_probe (device_t); 321 static int bce_attach (device_t); 322 static int bce_detach (device_t); 323 static int bce_shutdown (device_t); 324 325 326 /****************************************************************************/ 327 /* BCE Debug Data Structure Dump Routines */ 328 /****************************************************************************/ 329 #ifdef BCE_DEBUG 330 static u32 bce_reg_rd (struct bce_softc *, u32); 331 static void bce_reg_wr (struct bce_softc *, u32, u32); 332 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 333 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 334 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 335 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 336 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 337 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 338 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 339 static void bce_dump_txbd (struct bce_softc *, 340 int, struct tx_bd *); 341 static void bce_dump_rxbd (struct bce_softc *, 342 int, struct rx_bd *); 343 static void bce_dump_pgbd (struct bce_softc *, 344 int, struct rx_bd *); 345 static void bce_dump_l2fhdr (struct bce_softc *, 346 int, struct l2_fhdr *); 347 static void bce_dump_ctx (struct bce_softc *, u16); 348 static void bce_dump_ftqs (struct bce_softc *); 349 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 350 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 351 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 352 static void bce_dump_status_block (struct bce_softc *); 353 static void bce_dump_stats_block (struct bce_softc *); 354 static void bce_dump_driver_state (struct bce_softc *); 355 static void bce_dump_hw_state (struct bce_softc *); 356 static void bce_dump_shmem_state (struct bce_softc *); 357 static void bce_dump_mq_regs (struct bce_softc *); 358 static void bce_dump_bc_state (struct bce_softc *); 359 static void bce_dump_txp_state (struct bce_softc *, int); 360 static void bce_dump_rxp_state (struct bce_softc *, int); 361 static void bce_dump_tpat_state (struct bce_softc *, int); 362 static void bce_dump_cp_state (struct bce_softc *, int); 363 static void bce_dump_com_state (struct bce_softc *, int); 364 static void bce_dump_rv2p_state (struct bce_softc *); 365 static void bce_breakpoint (struct bce_softc *); 366 #endif /*BCE_DEBUG */ 367 368 369 /****************************************************************************/ 370 /* BCE Register/Memory Access Routines */ 371 /****************************************************************************/ 372 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 373 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 374 static void bce_shmem_wr (struct bce_softc *, u32, u32); 375 static u32 bce_shmem_rd (struct bce_softc *, u32); 376 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 377 static int bce_miibus_read_reg (device_t, int, int); 378 static int bce_miibus_write_reg (device_t, int, int, int); 379 static void bce_miibus_statchg (device_t); 380 381 #ifdef BCE_DEBUG 382 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 383 #ifdef BCE_NVRAM_WRITE_SUPPORT 384 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 385 #endif 386 #endif 387 388 /****************************************************************************/ 389 /* BCE NVRAM Access Routines */ 390 /****************************************************************************/ 391 static int bce_acquire_nvram_lock (struct bce_softc *); 392 static int bce_release_nvram_lock (struct bce_softc *); 393 static void bce_enable_nvram_access(struct bce_softc *); 394 static void bce_disable_nvram_access(struct bce_softc *); 395 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 396 static int bce_init_nvram (struct bce_softc *); 397 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 398 static int bce_nvram_test (struct bce_softc *); 399 #ifdef BCE_NVRAM_WRITE_SUPPORT 400 static int bce_enable_nvram_write (struct bce_softc *); 401 static void bce_disable_nvram_write(struct bce_softc *); 402 static int bce_nvram_erase_page (struct bce_softc *, u32); 403 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 404 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 405 #endif 406 407 /****************************************************************************/ 408 /* */ 409 /****************************************************************************/ 410 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 411 static void bce_get_media (struct bce_softc *); 412 static void bce_init_media (struct bce_softc *); 413 static u32 bce_get_rphy_link (struct bce_softc *); 414 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 415 static int bce_dma_alloc (device_t); 416 static void bce_dma_free (struct bce_softc *); 417 static void bce_release_resources (struct bce_softc *); 418 419 /****************************************************************************/ 420 /* BCE Firmware Synchronization and Load */ 421 /****************************************************************************/ 422 static void bce_fw_cap_init (struct bce_softc *); 423 static int bce_fw_sync (struct bce_softc *, u32); 424 static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32, 425 u32); 426 static void bce_load_cpu_fw (struct bce_softc *, 427 struct cpu_reg *, struct fw_info *); 428 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 429 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 430 static void bce_start_rxp_cpu (struct bce_softc *); 431 static void bce_init_rxp_cpu (struct bce_softc *); 432 static void bce_init_txp_cpu (struct bce_softc *); 433 static void bce_init_tpat_cpu (struct bce_softc *); 434 static void bce_init_cp_cpu (struct bce_softc *); 435 static void bce_init_com_cpu (struct bce_softc *); 436 static void bce_init_cpus (struct bce_softc *); 437 438 static void bce_print_adapter_info (struct bce_softc *); 439 static void bce_probe_pci_caps (device_t, struct bce_softc *); 440 static void bce_stop (struct bce_softc *); 441 static int bce_reset (struct bce_softc *, u32); 442 static int bce_chipinit (struct bce_softc *); 443 static int bce_blockinit (struct bce_softc *); 444 445 static int bce_init_tx_chain (struct bce_softc *); 446 static void bce_free_tx_chain (struct bce_softc *); 447 448 static int bce_get_rx_buf (struct bce_softc *, u16, u16, u32 *); 449 static int bce_init_rx_chain (struct bce_softc *); 450 static void bce_fill_rx_chain (struct bce_softc *); 451 static void bce_free_rx_chain (struct bce_softc *); 452 453 static int bce_get_pg_buf (struct bce_softc *, u16, u16); 454 static int bce_init_pg_chain (struct bce_softc *); 455 static void bce_fill_pg_chain (struct bce_softc *); 456 static void bce_free_pg_chain (struct bce_softc *); 457 458 static struct mbuf *bce_tso_setup (struct bce_softc *, 459 struct mbuf **, u16 *); 460 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 461 static void bce_start_locked (struct ifnet *); 462 static void bce_start (struct ifnet *); 463 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 464 static uint64_t bce_get_counter (struct ifnet *, ift_counter); 465 static void bce_watchdog (struct bce_softc *); 466 static int bce_ifmedia_upd (struct ifnet *); 467 static int bce_ifmedia_upd_locked (struct ifnet *); 468 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 469 static void bce_ifmedia_sts_rphy (struct bce_softc *, struct ifmediareq *); 470 static void bce_init_locked (struct bce_softc *); 471 static void bce_init (void *); 472 static void bce_mgmt_init_locked (struct bce_softc *sc); 473 474 static int bce_init_ctx (struct bce_softc *); 475 static void bce_get_mac_addr (struct bce_softc *); 476 static void bce_set_mac_addr (struct bce_softc *); 477 static void bce_phy_intr (struct bce_softc *); 478 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 479 static void bce_rx_intr (struct bce_softc *); 480 static void bce_tx_intr (struct bce_softc *); 481 static void bce_disable_intr (struct bce_softc *); 482 static void bce_enable_intr (struct bce_softc *, int); 483 484 static void bce_intr (void *); 485 static void bce_set_rx_mode (struct bce_softc *); 486 static void bce_stats_update (struct bce_softc *); 487 static void bce_tick (void *); 488 static void bce_pulse (void *); 489 static void bce_add_sysctls (struct bce_softc *); 490 491 492 /****************************************************************************/ 493 /* FreeBSD device dispatch table. */ 494 /****************************************************************************/ 495 static device_method_t bce_methods[] = { 496 /* Device interface (device_if.h) */ 497 DEVMETHOD(device_probe, bce_probe), 498 DEVMETHOD(device_attach, bce_attach), 499 DEVMETHOD(device_detach, bce_detach), 500 DEVMETHOD(device_shutdown, bce_shutdown), 501 /* Supported by device interface but not used here. */ 502 /* DEVMETHOD(device_identify, bce_identify), */ 503 /* DEVMETHOD(device_suspend, bce_suspend), */ 504 /* DEVMETHOD(device_resume, bce_resume), */ 505 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 506 507 /* MII interface (miibus_if.h) */ 508 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 509 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 510 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 511 /* Supported by MII interface but not used here. */ 512 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 513 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 514 515 DEVMETHOD_END 516 }; 517 518 static driver_t bce_driver = { 519 "bce", 520 bce_methods, 521 sizeof(struct bce_softc) 522 }; 523 524 static devclass_t bce_devclass; 525 526 MODULE_DEPEND(bce, pci, 1, 1, 1); 527 MODULE_DEPEND(bce, ether, 1, 1, 1); 528 MODULE_DEPEND(bce, miibus, 1, 1, 1); 529 530 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL); 531 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL); 532 533 534 /****************************************************************************/ 535 /* Tunable device values */ 536 /****************************************************************************/ 537 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 538 539 /* Allowable values are TRUE or FALSE */ 540 static int bce_verbose = TRUE; 541 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 542 "Verbose output enable/disable"); 543 544 /* Allowable values are TRUE or FALSE */ 545 static int bce_tso_enable = TRUE; 546 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 547 "TSO Enable/Disable"); 548 549 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 550 /* ToDo: Add MSI-X support. */ 551 static int bce_msi_enable = 1; 552 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 553 "MSI-X|MSI|INTx selector"); 554 555 /* Allowable values are 1, 2, 4, 8. */ 556 static int bce_rx_pages = DEFAULT_RX_PAGES; 557 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 558 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 559 560 /* Allowable values are 1, 2, 4, 8. */ 561 static int bce_tx_pages = DEFAULT_TX_PAGES; 562 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 563 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 564 565 /* Allowable values are TRUE or FALSE. */ 566 static int bce_hdr_split = TRUE; 567 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 568 "Frame header/payload splitting Enable/Disable"); 569 570 /* Allowable values are TRUE or FALSE. */ 571 static int bce_strict_rx_mtu = FALSE; 572 SYSCTL_UINT(_hw_bce, OID_AUTO, strict_rx_mtu, CTLFLAG_RDTUN, 573 &bce_strict_rx_mtu, 0, 574 "Enable/Disable strict RX frame size checking"); 575 576 /* Allowable values are 0 ... 100 */ 577 #ifdef BCE_DEBUG 578 /* Generate 1 interrupt for every transmit completion. */ 579 static int bce_tx_quick_cons_trip_int = 1; 580 #else 581 /* Generate 1 interrupt for every 20 transmit completions. */ 582 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 583 #endif 584 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 585 &bce_tx_quick_cons_trip_int, 0, 586 "Transmit BD trip point during interrupts"); 587 588 /* Allowable values are 0 ... 100 */ 589 /* Generate 1 interrupt for every transmit completion. */ 590 #ifdef BCE_DEBUG 591 static int bce_tx_quick_cons_trip = 1; 592 #else 593 /* Generate 1 interrupt for every 20 transmit completions. */ 594 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 595 #endif 596 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 597 &bce_tx_quick_cons_trip, 0, 598 "Transmit BD trip point"); 599 600 /* Allowable values are 0 ... 100 */ 601 #ifdef BCE_DEBUG 602 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 603 static int bce_tx_ticks_int = 0; 604 #else 605 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 606 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 607 #endif 608 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 609 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 610 611 /* Allowable values are 0 ... 100 */ 612 #ifdef BCE_DEBUG 613 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 614 static int bce_tx_ticks = 0; 615 #else 616 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 617 static int bce_tx_ticks = DEFAULT_TX_TICKS; 618 #endif 619 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 620 &bce_tx_ticks, 0, "Transmit ticks count"); 621 622 /* Allowable values are 1 ... 100 */ 623 #ifdef BCE_DEBUG 624 /* Generate 1 interrupt for every received frame. */ 625 static int bce_rx_quick_cons_trip_int = 1; 626 #else 627 /* Generate 1 interrupt for every 6 received frames. */ 628 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 629 #endif 630 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 631 &bce_rx_quick_cons_trip_int, 0, 632 "Receive BD trip point duirng interrupts"); 633 634 /* Allowable values are 1 ... 100 */ 635 #ifdef BCE_DEBUG 636 /* Generate 1 interrupt for every received frame. */ 637 static int bce_rx_quick_cons_trip = 1; 638 #else 639 /* Generate 1 interrupt for every 6 received frames. */ 640 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 641 #endif 642 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 643 &bce_rx_quick_cons_trip, 0, 644 "Receive BD trip point"); 645 646 /* Allowable values are 0 ... 100 */ 647 #ifdef BCE_DEBUG 648 /* Generate an int. if 0us have elapsed since the last received frame. */ 649 static int bce_rx_ticks_int = 0; 650 #else 651 /* Generate an int. if 18us have elapsed since the last received frame. */ 652 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 653 #endif 654 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 655 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 656 657 /* Allowable values are 0 ... 100 */ 658 #ifdef BCE_DEBUG 659 /* Generate an int. if 0us have elapsed since the last received frame. */ 660 static int bce_rx_ticks = 0; 661 #else 662 /* Generate an int. if 18us have elapsed since the last received frame. */ 663 static int bce_rx_ticks = DEFAULT_RX_TICKS; 664 #endif 665 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 666 &bce_rx_ticks, 0, "Receive ticks count"); 667 668 669 /****************************************************************************/ 670 /* Device probe function. */ 671 /* */ 672 /* Compares the device to the driver's list of supported devices and */ 673 /* reports back to the OS whether this is the right driver for the device. */ 674 /* */ 675 /* Returns: */ 676 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 677 /****************************************************************************/ 678 static int 679 bce_probe(device_t dev) 680 { 681 const struct bce_type *t; 682 struct bce_softc *sc; 683 char *descbuf; 684 u16 vid = 0, did = 0, svid = 0, sdid = 0; 685 686 t = bce_devs; 687 688 sc = device_get_softc(dev); 689 sc->bce_unit = device_get_unit(dev); 690 sc->bce_dev = dev; 691 692 /* Get the data for the device to be probed. */ 693 vid = pci_get_vendor(dev); 694 did = pci_get_device(dev); 695 svid = pci_get_subvendor(dev); 696 sdid = pci_get_subdevice(dev); 697 698 DBPRINT(sc, BCE_EXTREME_LOAD, 699 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 700 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 701 702 /* Look through the list of known devices for a match. */ 703 while(t->bce_name != NULL) { 704 705 if ((vid == t->bce_vid) && (did == t->bce_did) && 706 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 707 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 708 709 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 710 711 if (descbuf == NULL) 712 return(ENOMEM); 713 714 /* Print out the device identity. */ 715 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 716 t->bce_name, (((pci_read_config(dev, 717 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 718 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 719 720 device_set_desc_copy(dev, descbuf); 721 free(descbuf, M_TEMP); 722 return(BUS_PROBE_DEFAULT); 723 } 724 t++; 725 } 726 727 return(ENXIO); 728 } 729 730 731 /****************************************************************************/ 732 /* PCI Capabilities Probe Function. */ 733 /* */ 734 /* Walks the PCI capabiites list for the device to find what features are */ 735 /* supported. */ 736 /* */ 737 /* Returns: */ 738 /* None. */ 739 /****************************************************************************/ 740 static void 741 bce_print_adapter_info(struct bce_softc *sc) 742 { 743 int i = 0; 744 745 DBENTER(BCE_VERBOSE_LOAD); 746 747 if (bce_verbose || bootverbose) { 748 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 749 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 750 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 751 752 753 /* Bus info. */ 754 if (sc->bce_flags & BCE_PCIE_FLAG) { 755 printf("Bus (PCIe x%d, ", sc->link_width); 756 switch (sc->link_speed) { 757 case 1: printf("2.5Gbps); "); break; 758 case 2: printf("5Gbps); "); break; 759 default: printf("Unknown link speed); "); 760 } 761 } else { 762 printf("Bus (PCI%s, %s, %dMHz); ", 763 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 764 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 765 "32-bit" : "64-bit"), sc->bus_speed_mhz); 766 } 767 768 /* Firmware version and device features. */ 769 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 770 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 771 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 772 773 if (bce_hdr_split == TRUE) { 774 printf("SPLT"); 775 i++; 776 } 777 778 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 779 if (i > 0) printf("|"); 780 printf("MSI"); i++; 781 } 782 783 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 784 if (i > 0) printf("|"); 785 printf("MSI-X"); i++; 786 } 787 788 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 789 if (i > 0) printf("|"); 790 printf("2.5G"); i++; 791 } 792 793 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) { 794 if (i > 0) printf("|"); 795 printf("Remote PHY(%s)", 796 sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ? 797 "FIBER" : "TP"); i++; 798 } 799 800 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 801 if (i > 0) printf("|"); 802 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 803 } else { 804 printf(")\n"); 805 } 806 807 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 808 sc->bce_rx_quick_cons_trip_int, 809 sc->bce_rx_quick_cons_trip, 810 sc->bce_rx_ticks_int, 811 sc->bce_rx_ticks, 812 sc->bce_tx_quick_cons_trip_int, 813 sc->bce_tx_quick_cons_trip, 814 sc->bce_tx_ticks_int, 815 sc->bce_tx_ticks); 816 817 } 818 819 DBEXIT(BCE_VERBOSE_LOAD); 820 } 821 822 823 /****************************************************************************/ 824 /* PCI Capabilities Probe Function. */ 825 /* */ 826 /* Walks the PCI capabiites list for the device to find what features are */ 827 /* supported. */ 828 /* */ 829 /* Returns: */ 830 /* None. */ 831 /****************************************************************************/ 832 static void 833 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 834 { 835 u32 reg; 836 837 DBENTER(BCE_VERBOSE_LOAD); 838 839 /* Check if PCI-X capability is enabled. */ 840 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 841 if (reg != 0) 842 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 843 } 844 845 /* Check if PCIe capability is enabled. */ 846 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 847 if (reg != 0) { 848 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 849 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 850 "0x%08X\n", link_status); 851 sc->link_speed = link_status & 0xf; 852 sc->link_width = (link_status >> 4) & 0x3f; 853 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 854 sc->bce_flags |= BCE_PCIE_FLAG; 855 } 856 } 857 858 /* Check if MSI capability is enabled. */ 859 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 860 if (reg != 0) 861 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 862 } 863 864 /* Check if MSI-X capability is enabled. */ 865 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 866 if (reg != 0) 867 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 868 } 869 870 DBEXIT(BCE_VERBOSE_LOAD); 871 } 872 873 874 /****************************************************************************/ 875 /* Load and validate user tunable settings. */ 876 /* */ 877 /* Returns: */ 878 /* Nothing. */ 879 /****************************************************************************/ 880 static void 881 bce_set_tunables(struct bce_softc *sc) 882 { 883 /* Set sysctl values for RX page count. */ 884 switch (bce_rx_pages) { 885 case 1: 886 /* fall-through */ 887 case 2: 888 /* fall-through */ 889 case 4: 890 /* fall-through */ 891 case 8: 892 sc->rx_pages = bce_rx_pages; 893 break; 894 default: 895 sc->rx_pages = DEFAULT_RX_PAGES; 896 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 897 "hw.bce.rx_pages! Setting default of %d.\n", 898 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 899 } 900 901 /* ToDo: Consider allowing user setting for pg_pages. */ 902 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 903 904 /* Set sysctl values for TX page count. */ 905 switch (bce_tx_pages) { 906 case 1: 907 /* fall-through */ 908 case 2: 909 /* fall-through */ 910 case 4: 911 /* fall-through */ 912 case 8: 913 sc->tx_pages = bce_tx_pages; 914 break; 915 default: 916 sc->tx_pages = DEFAULT_TX_PAGES; 917 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 918 "hw.bce.tx_pages! Setting default of %d.\n", 919 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 920 } 921 922 /* 923 * Validate the TX trip point (i.e. the number of 924 * TX completions before a status block update is 925 * generated and an interrupt is asserted. 926 */ 927 if (bce_tx_quick_cons_trip_int <= 100) { 928 sc->bce_tx_quick_cons_trip_int = 929 bce_tx_quick_cons_trip_int; 930 } else { 931 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 932 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 933 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 934 DEFAULT_TX_QUICK_CONS_TRIP_INT); 935 sc->bce_tx_quick_cons_trip_int = 936 DEFAULT_TX_QUICK_CONS_TRIP_INT; 937 } 938 939 if (bce_tx_quick_cons_trip <= 100) { 940 sc->bce_tx_quick_cons_trip = 941 bce_tx_quick_cons_trip; 942 } else { 943 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 944 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 945 __FILE__, __LINE__, bce_tx_quick_cons_trip, 946 DEFAULT_TX_QUICK_CONS_TRIP); 947 sc->bce_tx_quick_cons_trip = 948 DEFAULT_TX_QUICK_CONS_TRIP; 949 } 950 951 /* 952 * Validate the TX ticks count (i.e. the maximum amount 953 * of time to wait after the last TX completion has 954 * occurred before a status block update is generated 955 * and an interrupt is asserted. 956 */ 957 if (bce_tx_ticks_int <= 100) { 958 sc->bce_tx_ticks_int = 959 bce_tx_ticks_int; 960 } else { 961 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 962 "hw.bce.tx_ticks_int! Setting default of %d.\n", 963 __FILE__, __LINE__, bce_tx_ticks_int, 964 DEFAULT_TX_TICKS_INT); 965 sc->bce_tx_ticks_int = 966 DEFAULT_TX_TICKS_INT; 967 } 968 969 if (bce_tx_ticks <= 100) { 970 sc->bce_tx_ticks = 971 bce_tx_ticks; 972 } else { 973 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 974 "hw.bce.tx_ticks! Setting default of %d.\n", 975 __FILE__, __LINE__, bce_tx_ticks, 976 DEFAULT_TX_TICKS); 977 sc->bce_tx_ticks = 978 DEFAULT_TX_TICKS; 979 } 980 981 /* 982 * Validate the RX trip point (i.e. the number of 983 * RX frames received before a status block update is 984 * generated and an interrupt is asserted. 985 */ 986 if (bce_rx_quick_cons_trip_int <= 100) { 987 sc->bce_rx_quick_cons_trip_int = 988 bce_rx_quick_cons_trip_int; 989 } else { 990 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 991 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 992 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 993 DEFAULT_RX_QUICK_CONS_TRIP_INT); 994 sc->bce_rx_quick_cons_trip_int = 995 DEFAULT_RX_QUICK_CONS_TRIP_INT; 996 } 997 998 if (bce_rx_quick_cons_trip <= 100) { 999 sc->bce_rx_quick_cons_trip = 1000 bce_rx_quick_cons_trip; 1001 } else { 1002 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1003 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 1004 __FILE__, __LINE__, bce_rx_quick_cons_trip, 1005 DEFAULT_RX_QUICK_CONS_TRIP); 1006 sc->bce_rx_quick_cons_trip = 1007 DEFAULT_RX_QUICK_CONS_TRIP; 1008 } 1009 1010 /* 1011 * Validate the RX ticks count (i.e. the maximum amount 1012 * of time to wait after the last RX frame has been 1013 * received before a status block update is generated 1014 * and an interrupt is asserted. 1015 */ 1016 if (bce_rx_ticks_int <= 100) { 1017 sc->bce_rx_ticks_int = bce_rx_ticks_int; 1018 } else { 1019 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1020 "hw.bce.rx_ticks_int! Setting default of %d.\n", 1021 __FILE__, __LINE__, bce_rx_ticks_int, 1022 DEFAULT_RX_TICKS_INT); 1023 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 1024 } 1025 1026 if (bce_rx_ticks <= 100) { 1027 sc->bce_rx_ticks = bce_rx_ticks; 1028 } else { 1029 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 1030 "hw.bce.rx_ticks! Setting default of %d.\n", 1031 __FILE__, __LINE__, bce_rx_ticks, 1032 DEFAULT_RX_TICKS); 1033 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1034 } 1035 1036 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1037 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1038 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1039 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1040 __FILE__, __LINE__); 1041 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1042 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1043 } 1044 1045 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1046 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1047 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1048 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1049 __FILE__, __LINE__); 1050 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1051 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1052 } 1053 } 1054 1055 1056 /****************************************************************************/ 1057 /* Device attach function. */ 1058 /* */ 1059 /* Allocates device resources, performs secondary chip identification, */ 1060 /* resets and initializes the hardware, and initializes driver instance */ 1061 /* variables. */ 1062 /* */ 1063 /* Returns: */ 1064 /* 0 on success, positive value on failure. */ 1065 /****************************************************************************/ 1066 static int 1067 bce_attach(device_t dev) 1068 { 1069 struct bce_softc *sc; 1070 struct ifnet *ifp; 1071 u32 val; 1072 int count, error, rc = 0, rid; 1073 1074 sc = device_get_softc(dev); 1075 sc->bce_dev = dev; 1076 1077 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1078 1079 sc->bce_unit = device_get_unit(dev); 1080 1081 /* Set initial device and PHY flags */ 1082 sc->bce_flags = 0; 1083 sc->bce_phy_flags = 0; 1084 1085 bce_set_tunables(sc); 1086 1087 pci_enable_busmaster(dev); 1088 1089 /* Allocate PCI memory resources. */ 1090 rid = PCIR_BAR(0); 1091 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1092 &rid, RF_ACTIVE); 1093 1094 if (sc->bce_res_mem == NULL) { 1095 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1096 __FILE__, __LINE__); 1097 rc = ENXIO; 1098 goto bce_attach_fail; 1099 } 1100 1101 /* Get various resource handles. */ 1102 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1103 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1104 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1105 1106 bce_probe_pci_caps(dev, sc); 1107 1108 rid = 1; 1109 count = 0; 1110 #if 0 1111 /* Try allocating MSI-X interrupts. */ 1112 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1113 (bce_msi_enable >= 2) && 1114 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1115 &rid, RF_ACTIVE)) != NULL)) { 1116 1117 msi_needed = count = 1; 1118 1119 if (((error = pci_alloc_msix(dev, &count)) != 0) || 1120 (count != msi_needed)) { 1121 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1122 "Received = %d, error = %d\n", __FILE__, __LINE__, 1123 msi_needed, count, error); 1124 count = 0; 1125 pci_release_msi(dev); 1126 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1127 sc->bce_res_irq); 1128 sc->bce_res_irq = NULL; 1129 } else { 1130 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1131 __FUNCTION__); 1132 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1133 } 1134 } 1135 #endif 1136 1137 /* Try allocating a MSI interrupt. */ 1138 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1139 (bce_msi_enable >= 1) && (count == 0)) { 1140 count = 1; 1141 if ((error = pci_alloc_msi(dev, &count)) != 0) { 1142 BCE_PRINTF("%s(%d): MSI allocation failed! " 1143 "error = %d\n", __FILE__, __LINE__, error); 1144 count = 0; 1145 pci_release_msi(dev); 1146 } else { 1147 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1148 "interrupt.\n", __FUNCTION__); 1149 sc->bce_flags |= BCE_USING_MSI_FLAG; 1150 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1151 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1152 rid = 1; 1153 } 1154 } 1155 1156 /* Try allocating a legacy interrupt. */ 1157 if (count == 0) { 1158 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1159 __FUNCTION__); 1160 rid = 0; 1161 } 1162 1163 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1164 &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE)); 1165 1166 /* Report any IRQ allocation errors. */ 1167 if (sc->bce_res_irq == NULL) { 1168 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1169 __FILE__, __LINE__); 1170 rc = ENXIO; 1171 goto bce_attach_fail; 1172 } 1173 1174 /* Initialize mutex for the current device instance. */ 1175 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1176 1177 /* 1178 * Configure byte swap and enable indirect register access. 1179 * Rely on CPU to do target byte swapping on big endian systems. 1180 * Access to registers outside of PCI configurtion space are not 1181 * valid until this is done. 1182 */ 1183 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1184 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1185 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1186 1187 /* Save ASIC revsion info. */ 1188 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1189 1190 /* Weed out any non-production controller revisions. */ 1191 switch(BCE_CHIP_ID(sc)) { 1192 case BCE_CHIP_ID_5706_A0: 1193 case BCE_CHIP_ID_5706_A1: 1194 case BCE_CHIP_ID_5708_A0: 1195 case BCE_CHIP_ID_5708_B0: 1196 case BCE_CHIP_ID_5709_A0: 1197 case BCE_CHIP_ID_5709_B0: 1198 case BCE_CHIP_ID_5709_B1: 1199 case BCE_CHIP_ID_5709_B2: 1200 BCE_PRINTF("%s(%d): Unsupported controller " 1201 "revision (%c%d)!\n", __FILE__, __LINE__, 1202 (((pci_read_config(dev, PCIR_REVID, 4) & 1203 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1204 PCIR_REVID, 4) & 0xf)); 1205 rc = ENODEV; 1206 goto bce_attach_fail; 1207 } 1208 1209 /* 1210 * The embedded PCIe to PCI-X bridge (EPB) 1211 * in the 5708 cannot address memory above 1212 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1213 */ 1214 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1215 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1216 else 1217 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1218 1219 /* 1220 * Find the base address for shared memory access. 1221 * Newer versions of bootcode use a signature and offset 1222 * while older versions use a fixed address. 1223 */ 1224 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1225 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1226 /* Multi-port devices use different offsets in shared memory. */ 1227 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1228 (pci_get_function(sc->bce_dev) << 2)); 1229 else 1230 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1231 1232 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1233 __FUNCTION__, sc->bce_shmem_base); 1234 1235 /* Fetch the bootcode revision. */ 1236 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1237 for (int i = 0, j = 0; i < 3; i++) { 1238 u8 num; 1239 1240 num = (u8) (val >> (24 - (i * 8))); 1241 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1242 if (num >= k || !skip0 || k == 1) { 1243 sc->bce_bc_ver[j++] = (num / k) + '0'; 1244 skip0 = 0; 1245 } 1246 } 1247 1248 if (i != 2) 1249 sc->bce_bc_ver[j++] = '.'; 1250 } 1251 1252 /* Check if any management firwmare is enabled. */ 1253 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1254 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1255 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1256 1257 /* Allow time for firmware to enter the running state. */ 1258 for (int i = 0; i < 30; i++) { 1259 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1260 if (val & BCE_CONDITION_MFW_RUN_MASK) 1261 break; 1262 DELAY(10000); 1263 } 1264 1265 /* Check if management firmware is running. */ 1266 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1267 val &= BCE_CONDITION_MFW_RUN_MASK; 1268 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1269 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1270 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1271 int i = 0; 1272 1273 /* Read the management firmware version string. */ 1274 for (int j = 0; j < 3; j++) { 1275 val = bce_reg_rd_ind(sc, addr + j * 4); 1276 val = bswap32(val); 1277 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1278 i += 4; 1279 } 1280 } else { 1281 /* May cause firmware synchronization timeouts. */ 1282 BCE_PRINTF("%s(%d): Management firmware enabled " 1283 "but not running!\n", __FILE__, __LINE__); 1284 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1285 1286 /* ToDo: Any action the driver should take? */ 1287 } 1288 } 1289 1290 /* Get PCI bus information (speed and type). */ 1291 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1292 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1293 u32 clkreg; 1294 1295 sc->bce_flags |= BCE_PCIX_FLAG; 1296 1297 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1298 1299 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1300 switch (clkreg) { 1301 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1302 sc->bus_speed_mhz = 133; 1303 break; 1304 1305 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1306 sc->bus_speed_mhz = 100; 1307 break; 1308 1309 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1310 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1311 sc->bus_speed_mhz = 66; 1312 break; 1313 1314 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1315 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1316 sc->bus_speed_mhz = 50; 1317 break; 1318 1319 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1320 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1321 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1322 sc->bus_speed_mhz = 33; 1323 break; 1324 } 1325 } else { 1326 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1327 sc->bus_speed_mhz = 66; 1328 else 1329 sc->bus_speed_mhz = 33; 1330 } 1331 1332 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1333 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1334 1335 /* Find the media type for the adapter. */ 1336 bce_get_media(sc); 1337 1338 /* Reset controller and announce to bootcode that driver is present. */ 1339 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1340 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1341 __FILE__, __LINE__); 1342 rc = ENXIO; 1343 goto bce_attach_fail; 1344 } 1345 1346 /* Initialize the controller. */ 1347 if (bce_chipinit(sc)) { 1348 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1349 __FILE__, __LINE__); 1350 rc = ENXIO; 1351 goto bce_attach_fail; 1352 } 1353 1354 /* Perform NVRAM test. */ 1355 if (bce_nvram_test(sc)) { 1356 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1357 __FILE__, __LINE__); 1358 rc = ENXIO; 1359 goto bce_attach_fail; 1360 } 1361 1362 /* Fetch the permanent Ethernet MAC address. */ 1363 bce_get_mac_addr(sc); 1364 1365 /* Update statistics once every second. */ 1366 sc->bce_stats_ticks = 1000000 & 0xffff00; 1367 1368 /* Store data needed by PHY driver for backplane applications */ 1369 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1370 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1371 1372 /* Allocate DMA memory resources. */ 1373 if (bce_dma_alloc(dev)) { 1374 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1375 __FILE__, __LINE__); 1376 rc = ENXIO; 1377 goto bce_attach_fail; 1378 } 1379 1380 /* Allocate an ifnet structure. */ 1381 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1382 if (ifp == NULL) { 1383 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1384 __FILE__, __LINE__); 1385 rc = ENXIO; 1386 goto bce_attach_fail; 1387 } 1388 1389 /* Initialize the ifnet interface. */ 1390 ifp->if_softc = sc; 1391 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1392 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1393 ifp->if_ioctl = bce_ioctl; 1394 ifp->if_start = bce_start; 1395 ifp->if_get_counter = bce_get_counter; 1396 ifp->if_init = bce_init; 1397 ifp->if_mtu = ETHERMTU; 1398 1399 if (bce_tso_enable) { 1400 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1401 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1402 IFCAP_VLAN_HWTSO; 1403 } else { 1404 ifp->if_hwassist = BCE_IF_HWASSIST; 1405 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1406 } 1407 1408 #if __FreeBSD_version >= 800505 1409 /* 1410 * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version 1411 * so it's approximate value. 1412 */ 1413 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1414 ifp->if_capabilities |= IFCAP_LINKSTATE; 1415 #endif 1416 1417 ifp->if_capenable = ifp->if_capabilities; 1418 1419 /* 1420 * Assume standard mbuf sizes for buffer allocation. 1421 * This may change later if the MTU size is set to 1422 * something other than 1500. 1423 */ 1424 bce_get_rx_buffer_sizes(sc, 1425 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1426 1427 /* Recalculate our buffer allocation sizes. */ 1428 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1429 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1430 IFQ_SET_READY(&ifp->if_snd); 1431 1432 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1433 ifp->if_baudrate = IF_Mbps(2500ULL); 1434 else 1435 ifp->if_baudrate = IF_Mbps(1000); 1436 1437 /* Handle any special PHY initialization for SerDes PHYs. */ 1438 bce_init_media(sc); 1439 1440 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 1441 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd, 1442 bce_ifmedia_sts); 1443 /* 1444 * We can't manually override remote PHY's link and assume 1445 * PHY port configuration(Fiber or TP) is not changed after 1446 * device attach. This may not be correct though. 1447 */ 1448 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) { 1449 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 1450 ifmedia_add(&sc->bce_ifmedia, 1451 IFM_ETHER | IFM_2500_SX, 0, NULL); 1452 ifmedia_add(&sc->bce_ifmedia, 1453 IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL); 1454 } 1455 ifmedia_add(&sc->bce_ifmedia, 1456 IFM_ETHER | IFM_1000_SX, 0, NULL); 1457 ifmedia_add(&sc->bce_ifmedia, 1458 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1459 } else { 1460 ifmedia_add(&sc->bce_ifmedia, 1461 IFM_ETHER | IFM_10_T, 0, NULL); 1462 ifmedia_add(&sc->bce_ifmedia, 1463 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1464 ifmedia_add(&sc->bce_ifmedia, 1465 IFM_ETHER | IFM_100_TX, 0, NULL); 1466 ifmedia_add(&sc->bce_ifmedia, 1467 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1468 ifmedia_add(&sc->bce_ifmedia, 1469 IFM_ETHER | IFM_1000_T, 0, NULL); 1470 ifmedia_add(&sc->bce_ifmedia, 1471 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1472 } 1473 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1474 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO); 1475 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media; 1476 } else { 1477 /* MII child bus by attaching the PHY. */ 1478 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1479 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1480 MII_OFFSET_ANY, MIIF_DOPAUSE); 1481 if (rc != 0) { 1482 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1483 __LINE__); 1484 goto bce_attach_fail; 1485 } 1486 } 1487 1488 /* Attach to the Ethernet interface list. */ 1489 ether_ifattach(ifp, sc->eaddr); 1490 1491 #if __FreeBSD_version < 500000 1492 callout_init(&sc->bce_tick_callout); 1493 callout_init(&sc->bce_pulse_callout); 1494 #else 1495 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1496 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1497 #endif 1498 1499 /* Hookup IRQ last. */ 1500 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1501 NULL, bce_intr, sc, &sc->bce_intrhand); 1502 1503 if (rc) { 1504 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1505 __FILE__, __LINE__); 1506 bce_detach(dev); 1507 goto bce_attach_exit; 1508 } 1509 1510 /* 1511 * At this point we've acquired all the resources 1512 * we need to run so there's no turning back, we're 1513 * cleared for launch. 1514 */ 1515 1516 /* Print some important debugging info. */ 1517 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1518 1519 /* Add the supported sysctls to the kernel. */ 1520 bce_add_sysctls(sc); 1521 1522 BCE_LOCK(sc); 1523 1524 /* 1525 * The chip reset earlier notified the bootcode that 1526 * a driver is present. We now need to start our pulse 1527 * routine so that the bootcode is reminded that we're 1528 * still running. 1529 */ 1530 bce_pulse(sc); 1531 1532 bce_mgmt_init_locked(sc); 1533 BCE_UNLOCK(sc); 1534 1535 /* Finally, print some useful adapter info */ 1536 bce_print_adapter_info(sc); 1537 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1538 __FUNCTION__, sc); 1539 1540 goto bce_attach_exit; 1541 1542 bce_attach_fail: 1543 bce_release_resources(sc); 1544 1545 bce_attach_exit: 1546 1547 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1548 1549 return(rc); 1550 } 1551 1552 1553 /****************************************************************************/ 1554 /* Device detach function. */ 1555 /* */ 1556 /* Stops the controller, resets the controller, and releases resources. */ 1557 /* */ 1558 /* Returns: */ 1559 /* 0 on success, positive value on failure. */ 1560 /****************************************************************************/ 1561 static int 1562 bce_detach(device_t dev) 1563 { 1564 struct bce_softc *sc = device_get_softc(dev); 1565 struct ifnet *ifp; 1566 u32 msg; 1567 1568 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1569 1570 ifp = sc->bce_ifp; 1571 1572 /* Stop and reset the controller. */ 1573 BCE_LOCK(sc); 1574 1575 /* Stop the pulse so the bootcode can go to driver absent state. */ 1576 callout_stop(&sc->bce_pulse_callout); 1577 1578 bce_stop(sc); 1579 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1580 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1581 else 1582 msg = BCE_DRV_MSG_CODE_UNLOAD; 1583 bce_reset(sc, msg); 1584 1585 BCE_UNLOCK(sc); 1586 1587 ether_ifdetach(ifp); 1588 1589 /* If we have a child device on the MII bus remove it too. */ 1590 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 1591 ifmedia_removeall(&sc->bce_ifmedia); 1592 else { 1593 bus_generic_detach(dev); 1594 device_delete_child(dev, sc->bce_miibus); 1595 } 1596 1597 /* Release all remaining resources. */ 1598 bce_release_resources(sc); 1599 1600 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1601 1602 return(0); 1603 } 1604 1605 1606 /****************************************************************************/ 1607 /* Device shutdown function. */ 1608 /* */ 1609 /* Stops and resets the controller. */ 1610 /* */ 1611 /* Returns: */ 1612 /* 0 on success, positive value on failure. */ 1613 /****************************************************************************/ 1614 static int 1615 bce_shutdown(device_t dev) 1616 { 1617 struct bce_softc *sc = device_get_softc(dev); 1618 u32 msg; 1619 1620 DBENTER(BCE_VERBOSE); 1621 1622 BCE_LOCK(sc); 1623 bce_stop(sc); 1624 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1625 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1626 else 1627 msg = BCE_DRV_MSG_CODE_UNLOAD; 1628 bce_reset(sc, msg); 1629 BCE_UNLOCK(sc); 1630 1631 DBEXIT(BCE_VERBOSE); 1632 1633 return (0); 1634 } 1635 1636 1637 #ifdef BCE_DEBUG 1638 /****************************************************************************/ 1639 /* Register read. */ 1640 /* */ 1641 /* Returns: */ 1642 /* The value of the register. */ 1643 /****************************************************************************/ 1644 static u32 1645 bce_reg_rd(struct bce_softc *sc, u32 offset) 1646 { 1647 u32 val = REG_RD(sc, offset); 1648 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1649 __FUNCTION__, offset, val); 1650 return val; 1651 } 1652 1653 1654 /****************************************************************************/ 1655 /* Register write (16 bit). */ 1656 /* */ 1657 /* Returns: */ 1658 /* Nothing. */ 1659 /****************************************************************************/ 1660 static void 1661 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1662 { 1663 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1664 __FUNCTION__, offset, val); 1665 REG_WR16(sc, offset, val); 1666 } 1667 1668 1669 /****************************************************************************/ 1670 /* Register write. */ 1671 /* */ 1672 /* Returns: */ 1673 /* Nothing. */ 1674 /****************************************************************************/ 1675 static void 1676 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1677 { 1678 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1679 __FUNCTION__, offset, val); 1680 REG_WR(sc, offset, val); 1681 } 1682 #endif 1683 1684 /****************************************************************************/ 1685 /* Indirect register read. */ 1686 /* */ 1687 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1688 /* configuration space. Using this mechanism avoids issues with posted */ 1689 /* reads but is much slower than memory-mapped I/O. */ 1690 /* */ 1691 /* Returns: */ 1692 /* The value of the register. */ 1693 /****************************************************************************/ 1694 static u32 1695 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1696 { 1697 device_t dev; 1698 dev = sc->bce_dev; 1699 1700 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1701 #ifdef BCE_DEBUG 1702 { 1703 u32 val; 1704 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1705 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1706 __FUNCTION__, offset, val); 1707 return val; 1708 } 1709 #else 1710 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1711 #endif 1712 } 1713 1714 1715 /****************************************************************************/ 1716 /* Indirect register write. */ 1717 /* */ 1718 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1719 /* configuration space. Using this mechanism avoids issues with posted */ 1720 /* writes but is muchh slower than memory-mapped I/O. */ 1721 /* */ 1722 /* Returns: */ 1723 /* Nothing. */ 1724 /****************************************************************************/ 1725 static void 1726 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1727 { 1728 device_t dev; 1729 dev = sc->bce_dev; 1730 1731 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1732 __FUNCTION__, offset, val); 1733 1734 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1735 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1736 } 1737 1738 1739 /****************************************************************************/ 1740 /* Shared memory write. */ 1741 /* */ 1742 /* Writes NetXtreme II shared memory region. */ 1743 /* */ 1744 /* Returns: */ 1745 /* Nothing. */ 1746 /****************************************************************************/ 1747 static void 1748 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1749 { 1750 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1751 "0x%08X\n", __FUNCTION__, val, offset); 1752 1753 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1754 } 1755 1756 1757 /****************************************************************************/ 1758 /* Shared memory read. */ 1759 /* */ 1760 /* Reads NetXtreme II shared memory region. */ 1761 /* */ 1762 /* Returns: */ 1763 /* The 32 bit value read. */ 1764 /****************************************************************************/ 1765 static u32 1766 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1767 { 1768 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1769 1770 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1771 "0x%08X\n", __FUNCTION__, val, offset); 1772 1773 return val; 1774 } 1775 1776 1777 #ifdef BCE_DEBUG 1778 /****************************************************************************/ 1779 /* Context memory read. */ 1780 /* */ 1781 /* The NetXtreme II controller uses context memory to track connection */ 1782 /* information for L2 and higher network protocols. */ 1783 /* */ 1784 /* Returns: */ 1785 /* The requested 32 bit value of context memory. */ 1786 /****************************************************************************/ 1787 static u32 1788 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1789 { 1790 u32 idx, offset, retry_cnt = 5, val; 1791 1792 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1793 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1794 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1795 1796 offset = ctx_offset + cid_addr; 1797 1798 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1799 1800 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1801 1802 for (idx = 0; idx < retry_cnt; idx++) { 1803 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1804 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1805 break; 1806 DELAY(5); 1807 } 1808 1809 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1810 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1811 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1812 __FILE__, __LINE__, cid_addr, ctx_offset); 1813 1814 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1815 } else { 1816 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1817 val = REG_RD(sc, BCE_CTX_DATA); 1818 } 1819 1820 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1821 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1822 1823 return(val); 1824 } 1825 #endif 1826 1827 1828 /****************************************************************************/ 1829 /* Context memory write. */ 1830 /* */ 1831 /* The NetXtreme II controller uses context memory to track connection */ 1832 /* information for L2 and higher network protocols. */ 1833 /* */ 1834 /* Returns: */ 1835 /* Nothing. */ 1836 /****************************************************************************/ 1837 static void 1838 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1839 { 1840 u32 idx, offset = ctx_offset + cid_addr; 1841 u32 val, retry_cnt = 5; 1842 1843 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1844 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1845 1846 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1847 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1848 __FUNCTION__, cid_addr)); 1849 1850 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1851 1852 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1853 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1854 1855 for (idx = 0; idx < retry_cnt; idx++) { 1856 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1857 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1858 break; 1859 DELAY(5); 1860 } 1861 1862 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1863 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1864 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1865 __FILE__, __LINE__, cid_addr, ctx_offset); 1866 1867 } else { 1868 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1869 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1870 } 1871 } 1872 1873 1874 /****************************************************************************/ 1875 /* PHY register read. */ 1876 /* */ 1877 /* Implements register reads on the MII bus. */ 1878 /* */ 1879 /* Returns: */ 1880 /* The value of the register. */ 1881 /****************************************************************************/ 1882 static int 1883 bce_miibus_read_reg(device_t dev, int phy, int reg) 1884 { 1885 struct bce_softc *sc; 1886 u32 val; 1887 int i; 1888 1889 sc = device_get_softc(dev); 1890 1891 /* 1892 * The 5709S PHY is an IEEE Clause 45 PHY 1893 * with special mappings to work with IEEE 1894 * Clause 22 register accesses. 1895 */ 1896 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1897 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1898 reg += 0x10; 1899 } 1900 1901 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1902 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1903 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1904 1905 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1906 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1907 1908 DELAY(40); 1909 } 1910 1911 1912 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1913 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1914 BCE_EMAC_MDIO_COMM_START_BUSY; 1915 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1916 1917 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1918 DELAY(10); 1919 1920 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1921 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1922 DELAY(5); 1923 1924 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1925 val &= BCE_EMAC_MDIO_COMM_DATA; 1926 1927 break; 1928 } 1929 } 1930 1931 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1932 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1933 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1934 val = 0x0; 1935 } else { 1936 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1937 } 1938 1939 1940 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1941 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1942 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1943 1944 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1945 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1946 1947 DELAY(40); 1948 } 1949 1950 DB_PRINT_PHY_REG(reg, val); 1951 return (val & 0xffff); 1952 } 1953 1954 1955 /****************************************************************************/ 1956 /* PHY register write. */ 1957 /* */ 1958 /* Implements register writes on the MII bus. */ 1959 /* */ 1960 /* Returns: */ 1961 /* The value of the register. */ 1962 /****************************************************************************/ 1963 static int 1964 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1965 { 1966 struct bce_softc *sc; 1967 u32 val1; 1968 int i; 1969 1970 sc = device_get_softc(dev); 1971 1972 DB_PRINT_PHY_REG(reg, val); 1973 1974 /* 1975 * The 5709S PHY is an IEEE Clause 45 PHY 1976 * with special mappings to work with IEEE 1977 * Clause 22 register accesses. 1978 */ 1979 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1980 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1981 reg += 0x10; 1982 } 1983 1984 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1985 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1986 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1987 1988 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1989 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1990 1991 DELAY(40); 1992 } 1993 1994 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1995 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1996 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1997 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1998 1999 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 2000 DELAY(10); 2001 2002 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 2003 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 2004 DELAY(5); 2005 break; 2006 } 2007 } 2008 2009 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 2010 BCE_PRINTF("%s(%d): PHY write timeout!\n", 2011 __FILE__, __LINE__); 2012 2013 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 2014 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 2015 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 2016 2017 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 2018 REG_RD(sc, BCE_EMAC_MDIO_MODE); 2019 2020 DELAY(40); 2021 } 2022 2023 return 0; 2024 } 2025 2026 2027 /****************************************************************************/ 2028 /* MII bus status change. */ 2029 /* */ 2030 /* Called by the MII bus driver when the PHY establishes link to set the */ 2031 /* MAC interface registers. */ 2032 /* */ 2033 /* Returns: */ 2034 /* Nothing. */ 2035 /****************************************************************************/ 2036 static void 2037 bce_miibus_statchg(device_t dev) 2038 { 2039 struct bce_softc *sc; 2040 struct mii_data *mii; 2041 struct ifmediareq ifmr; 2042 int media_active, media_status, val; 2043 2044 sc = device_get_softc(dev); 2045 2046 DBENTER(BCE_VERBOSE_PHY); 2047 2048 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 2049 bzero(&ifmr, sizeof(ifmr)); 2050 bce_ifmedia_sts_rphy(sc, &ifmr); 2051 media_active = ifmr.ifm_active; 2052 media_status = ifmr.ifm_status; 2053 } else { 2054 mii = device_get_softc(sc->bce_miibus); 2055 media_active = mii->mii_media_active; 2056 media_status = mii->mii_media_status; 2057 } 2058 2059 /* Ignore invalid media status. */ 2060 if ((media_status & (IFM_ACTIVE | IFM_AVALID)) != 2061 (IFM_ACTIVE | IFM_AVALID)) 2062 goto bce_miibus_statchg_exit; 2063 2064 val = REG_RD(sc, BCE_EMAC_MODE); 2065 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2066 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2067 BCE_EMAC_MODE_25G); 2068 2069 /* Set MII or GMII interface based on the PHY speed. */ 2070 switch (IFM_SUBTYPE(media_active)) { 2071 case IFM_10_T: 2072 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2073 DBPRINT(sc, BCE_INFO_PHY, 2074 "Enabling 10Mb interface.\n"); 2075 val |= BCE_EMAC_MODE_PORT_MII_10; 2076 break; 2077 } 2078 /* fall-through */ 2079 case IFM_100_TX: 2080 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2081 val |= BCE_EMAC_MODE_PORT_MII; 2082 break; 2083 case IFM_2500_SX: 2084 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2085 val |= BCE_EMAC_MODE_25G; 2086 /* fall-through */ 2087 case IFM_1000_T: 2088 case IFM_1000_SX: 2089 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2090 val |= BCE_EMAC_MODE_PORT_GMII; 2091 break; 2092 default: 2093 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2094 "default GMII interface.\n"); 2095 val |= BCE_EMAC_MODE_PORT_GMII; 2096 } 2097 2098 /* Set half or full duplex based on PHY settings. */ 2099 if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) { 2100 DBPRINT(sc, BCE_INFO_PHY, 2101 "Setting Half-Duplex interface.\n"); 2102 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2103 } else 2104 DBPRINT(sc, BCE_INFO_PHY, 2105 "Setting Full-Duplex interface.\n"); 2106 2107 REG_WR(sc, BCE_EMAC_MODE, val); 2108 2109 if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) { 2110 DBPRINT(sc, BCE_INFO_PHY, 2111 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2112 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2113 sc->bce_flags |= BCE_USING_RX_FLOW_CONTROL; 2114 } else { 2115 DBPRINT(sc, BCE_INFO_PHY, 2116 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2117 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2118 sc->bce_flags &= ~BCE_USING_RX_FLOW_CONTROL; 2119 } 2120 2121 if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) { 2122 DBPRINT(sc, BCE_INFO_PHY, 2123 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2124 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2125 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2126 } else { 2127 DBPRINT(sc, BCE_INFO_PHY, 2128 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2129 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2130 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2131 } 2132 2133 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2134 2135 bce_miibus_statchg_exit: 2136 DBEXIT(BCE_VERBOSE_PHY); 2137 } 2138 2139 2140 /****************************************************************************/ 2141 /* Acquire NVRAM lock. */ 2142 /* */ 2143 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2144 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2145 /* for use by the driver. */ 2146 /* */ 2147 /* Returns: */ 2148 /* 0 on success, positive value on failure. */ 2149 /****************************************************************************/ 2150 static int 2151 bce_acquire_nvram_lock(struct bce_softc *sc) 2152 { 2153 u32 val; 2154 int j, rc = 0; 2155 2156 DBENTER(BCE_VERBOSE_NVRAM); 2157 2158 /* Request access to the flash interface. */ 2159 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2160 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2161 val = REG_RD(sc, BCE_NVM_SW_ARB); 2162 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2163 break; 2164 2165 DELAY(5); 2166 } 2167 2168 if (j >= NVRAM_TIMEOUT_COUNT) { 2169 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2170 rc = EBUSY; 2171 } 2172 2173 DBEXIT(BCE_VERBOSE_NVRAM); 2174 return (rc); 2175 } 2176 2177 2178 /****************************************************************************/ 2179 /* Release NVRAM lock. */ 2180 /* */ 2181 /* When the caller is finished accessing NVRAM the lock must be released. */ 2182 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2183 /* for use by the driver. */ 2184 /* */ 2185 /* Returns: */ 2186 /* 0 on success, positive value on failure. */ 2187 /****************************************************************************/ 2188 static int 2189 bce_release_nvram_lock(struct bce_softc *sc) 2190 { 2191 u32 val; 2192 int j, rc = 0; 2193 2194 DBENTER(BCE_VERBOSE_NVRAM); 2195 2196 /* 2197 * Relinquish nvram interface. 2198 */ 2199 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2200 2201 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2202 val = REG_RD(sc, BCE_NVM_SW_ARB); 2203 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2204 break; 2205 2206 DELAY(5); 2207 } 2208 2209 if (j >= NVRAM_TIMEOUT_COUNT) { 2210 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2211 rc = EBUSY; 2212 } 2213 2214 DBEXIT(BCE_VERBOSE_NVRAM); 2215 return (rc); 2216 } 2217 2218 2219 #ifdef BCE_NVRAM_WRITE_SUPPORT 2220 /****************************************************************************/ 2221 /* Enable NVRAM write access. */ 2222 /* */ 2223 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2224 /* */ 2225 /* Returns: */ 2226 /* 0 on success, positive value on failure. */ 2227 /****************************************************************************/ 2228 static int 2229 bce_enable_nvram_write(struct bce_softc *sc) 2230 { 2231 u32 val; 2232 int rc = 0; 2233 2234 DBENTER(BCE_VERBOSE_NVRAM); 2235 2236 val = REG_RD(sc, BCE_MISC_CFG); 2237 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2238 2239 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2240 int j; 2241 2242 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2243 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2244 2245 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2246 DELAY(5); 2247 2248 val = REG_RD(sc, BCE_NVM_COMMAND); 2249 if (val & BCE_NVM_COMMAND_DONE) 2250 break; 2251 } 2252 2253 if (j >= NVRAM_TIMEOUT_COUNT) { 2254 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2255 rc = EBUSY; 2256 } 2257 } 2258 2259 DBENTER(BCE_VERBOSE_NVRAM); 2260 return (rc); 2261 } 2262 2263 2264 /****************************************************************************/ 2265 /* Disable NVRAM write access. */ 2266 /* */ 2267 /* When the caller is finished writing to NVRAM write access must be */ 2268 /* disabled. */ 2269 /* */ 2270 /* Returns: */ 2271 /* Nothing. */ 2272 /****************************************************************************/ 2273 static void 2274 bce_disable_nvram_write(struct bce_softc *sc) 2275 { 2276 u32 val; 2277 2278 DBENTER(BCE_VERBOSE_NVRAM); 2279 2280 val = REG_RD(sc, BCE_MISC_CFG); 2281 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2282 2283 DBEXIT(BCE_VERBOSE_NVRAM); 2284 2285 } 2286 #endif 2287 2288 2289 /****************************************************************************/ 2290 /* Enable NVRAM access. */ 2291 /* */ 2292 /* Before accessing NVRAM for read or write operations the caller must */ 2293 /* enabled NVRAM access. */ 2294 /* */ 2295 /* Returns: */ 2296 /* Nothing. */ 2297 /****************************************************************************/ 2298 static void 2299 bce_enable_nvram_access(struct bce_softc *sc) 2300 { 2301 u32 val; 2302 2303 DBENTER(BCE_VERBOSE_NVRAM); 2304 2305 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2306 /* Enable both bits, even on read. */ 2307 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2308 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2309 2310 DBEXIT(BCE_VERBOSE_NVRAM); 2311 } 2312 2313 2314 /****************************************************************************/ 2315 /* Disable NVRAM access. */ 2316 /* */ 2317 /* When the caller is finished accessing NVRAM access must be disabled. */ 2318 /* */ 2319 /* Returns: */ 2320 /* Nothing. */ 2321 /****************************************************************************/ 2322 static void 2323 bce_disable_nvram_access(struct bce_softc *sc) 2324 { 2325 u32 val; 2326 2327 DBENTER(BCE_VERBOSE_NVRAM); 2328 2329 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2330 2331 /* Disable both bits, even after read. */ 2332 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2333 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2334 2335 DBEXIT(BCE_VERBOSE_NVRAM); 2336 } 2337 2338 2339 #ifdef BCE_NVRAM_WRITE_SUPPORT 2340 /****************************************************************************/ 2341 /* Erase NVRAM page before writing. */ 2342 /* */ 2343 /* Non-buffered flash parts require that a page be erased before it is */ 2344 /* written. */ 2345 /* */ 2346 /* Returns: */ 2347 /* 0 on success, positive value on failure. */ 2348 /****************************************************************************/ 2349 static int 2350 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2351 { 2352 u32 cmd; 2353 int j, rc = 0; 2354 2355 DBENTER(BCE_VERBOSE_NVRAM); 2356 2357 /* Buffered flash doesn't require an erase. */ 2358 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2359 goto bce_nvram_erase_page_exit; 2360 2361 /* Build an erase command. */ 2362 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2363 BCE_NVM_COMMAND_DOIT; 2364 2365 /* 2366 * Clear the DONE bit separately, set the NVRAM address to erase, 2367 * and issue the erase command. 2368 */ 2369 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2370 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2371 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2372 2373 /* Wait for completion. */ 2374 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2375 u32 val; 2376 2377 DELAY(5); 2378 2379 val = REG_RD(sc, BCE_NVM_COMMAND); 2380 if (val & BCE_NVM_COMMAND_DONE) 2381 break; 2382 } 2383 2384 if (j >= NVRAM_TIMEOUT_COUNT) { 2385 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2386 rc = EBUSY; 2387 } 2388 2389 bce_nvram_erase_page_exit: 2390 DBEXIT(BCE_VERBOSE_NVRAM); 2391 return (rc); 2392 } 2393 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2394 2395 2396 /****************************************************************************/ 2397 /* Read a dword (32 bits) from NVRAM. */ 2398 /* */ 2399 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2400 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2401 /* */ 2402 /* Returns: */ 2403 /* 0 on success and the 32 bit value read, positive value on failure. */ 2404 /****************************************************************************/ 2405 static int 2406 bce_nvram_read_dword(struct bce_softc *sc, 2407 u32 offset, u8 *ret_val, u32 cmd_flags) 2408 { 2409 u32 cmd; 2410 int i, rc = 0; 2411 2412 DBENTER(BCE_EXTREME_NVRAM); 2413 2414 /* Build the command word. */ 2415 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2416 2417 /* Calculate the offset for buffered flash if translation is used. */ 2418 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2419 offset = ((offset / sc->bce_flash_info->page_size) << 2420 sc->bce_flash_info->page_bits) + 2421 (offset % sc->bce_flash_info->page_size); 2422 } 2423 2424 /* 2425 * Clear the DONE bit separately, set the address to read, 2426 * and issue the read. 2427 */ 2428 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2429 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2430 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2431 2432 /* Wait for completion. */ 2433 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2434 u32 val; 2435 2436 DELAY(5); 2437 2438 val = REG_RD(sc, BCE_NVM_COMMAND); 2439 if (val & BCE_NVM_COMMAND_DONE) { 2440 val = REG_RD(sc, BCE_NVM_READ); 2441 2442 val = bce_be32toh(val); 2443 memcpy(ret_val, &val, 4); 2444 break; 2445 } 2446 } 2447 2448 /* Check for errors. */ 2449 if (i >= NVRAM_TIMEOUT_COUNT) { 2450 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2451 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2452 rc = EBUSY; 2453 } 2454 2455 DBEXIT(BCE_EXTREME_NVRAM); 2456 return(rc); 2457 } 2458 2459 2460 #ifdef BCE_NVRAM_WRITE_SUPPORT 2461 /****************************************************************************/ 2462 /* Write a dword (32 bits) to NVRAM. */ 2463 /* */ 2464 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2465 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2466 /* enabled NVRAM write access. */ 2467 /* */ 2468 /* Returns: */ 2469 /* 0 on success, positive value on failure. */ 2470 /****************************************************************************/ 2471 static int 2472 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2473 u32 cmd_flags) 2474 { 2475 u32 cmd, val32; 2476 int j, rc = 0; 2477 2478 DBENTER(BCE_VERBOSE_NVRAM); 2479 2480 /* Build the command word. */ 2481 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2482 2483 /* Calculate the offset for buffered flash if translation is used. */ 2484 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2485 offset = ((offset / sc->bce_flash_info->page_size) << 2486 sc->bce_flash_info->page_bits) + 2487 (offset % sc->bce_flash_info->page_size); 2488 } 2489 2490 /* 2491 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2492 * set the NVRAM address to write, and issue the write command 2493 */ 2494 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2495 memcpy(&val32, val, 4); 2496 val32 = htobe32(val32); 2497 REG_WR(sc, BCE_NVM_WRITE, val32); 2498 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2499 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2500 2501 /* Wait for completion. */ 2502 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2503 DELAY(5); 2504 2505 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2506 break; 2507 } 2508 if (j >= NVRAM_TIMEOUT_COUNT) { 2509 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2510 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2511 rc = EBUSY; 2512 } 2513 2514 DBEXIT(BCE_VERBOSE_NVRAM); 2515 return (rc); 2516 } 2517 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2518 2519 2520 /****************************************************************************/ 2521 /* Initialize NVRAM access. */ 2522 /* */ 2523 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2524 /* access that device. */ 2525 /* */ 2526 /* Returns: */ 2527 /* 0 on success, positive value on failure. */ 2528 /****************************************************************************/ 2529 static int 2530 bce_init_nvram(struct bce_softc *sc) 2531 { 2532 u32 val; 2533 int j, entry_count, rc = 0; 2534 const struct flash_spec *flash; 2535 2536 DBENTER(BCE_VERBOSE_NVRAM); 2537 2538 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2539 sc->bce_flash_info = &flash_5709; 2540 goto bce_init_nvram_get_flash_size; 2541 } 2542 2543 /* Determine the selected interface. */ 2544 val = REG_RD(sc, BCE_NVM_CFG1); 2545 2546 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2547 2548 /* 2549 * Flash reconfiguration is required to support additional 2550 * NVRAM devices not directly supported in hardware. 2551 * Check if the flash interface was reconfigured 2552 * by the bootcode. 2553 */ 2554 2555 if (val & 0x40000000) { 2556 /* Flash interface reconfigured by bootcode. */ 2557 2558 DBPRINT(sc,BCE_INFO_LOAD, 2559 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2560 2561 for (j = 0, flash = &flash_table[0]; j < entry_count; 2562 j++, flash++) { 2563 if ((val & FLASH_BACKUP_STRAP_MASK) == 2564 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2565 sc->bce_flash_info = flash; 2566 break; 2567 } 2568 } 2569 } else { 2570 /* Flash interface not yet reconfigured. */ 2571 u32 mask; 2572 2573 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2574 __FUNCTION__); 2575 2576 if (val & (1 << 23)) 2577 mask = FLASH_BACKUP_STRAP_MASK; 2578 else 2579 mask = FLASH_STRAP_MASK; 2580 2581 /* Look for the matching NVRAM device configuration data. */ 2582 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2583 2584 /* Check if the device matches any of the known devices. */ 2585 if ((val & mask) == (flash->strapping & mask)) { 2586 /* Found a device match. */ 2587 sc->bce_flash_info = flash; 2588 2589 /* Request access to the flash interface. */ 2590 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2591 return rc; 2592 2593 /* Reconfigure the flash interface. */ 2594 bce_enable_nvram_access(sc); 2595 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2596 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2597 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2598 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2599 bce_disable_nvram_access(sc); 2600 bce_release_nvram_lock(sc); 2601 2602 break; 2603 } 2604 } 2605 } 2606 2607 /* Check if a matching device was found. */ 2608 if (j == entry_count) { 2609 sc->bce_flash_info = NULL; 2610 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2611 __FILE__, __LINE__); 2612 DBEXIT(BCE_VERBOSE_NVRAM); 2613 return (ENODEV); 2614 } 2615 2616 bce_init_nvram_get_flash_size: 2617 /* Write the flash config data to the shared memory interface. */ 2618 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2619 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2620 if (val) 2621 sc->bce_flash_size = val; 2622 else 2623 sc->bce_flash_size = sc->bce_flash_info->total_size; 2624 2625 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2626 __FUNCTION__, sc->bce_flash_info->name, 2627 sc->bce_flash_info->total_size); 2628 2629 DBEXIT(BCE_VERBOSE_NVRAM); 2630 return rc; 2631 } 2632 2633 2634 /****************************************************************************/ 2635 /* Read an arbitrary range of data from NVRAM. */ 2636 /* */ 2637 /* Prepares the NVRAM interface for access and reads the requested data */ 2638 /* into the supplied buffer. */ 2639 /* */ 2640 /* Returns: */ 2641 /* 0 on success and the data read, positive value on failure. */ 2642 /****************************************************************************/ 2643 static int 2644 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2645 int buf_size) 2646 { 2647 int rc = 0; 2648 u32 cmd_flags, offset32, len32, extra; 2649 2650 DBENTER(BCE_VERBOSE_NVRAM); 2651 2652 if (buf_size == 0) 2653 goto bce_nvram_read_exit; 2654 2655 /* Request access to the flash interface. */ 2656 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2657 goto bce_nvram_read_exit; 2658 2659 /* Enable access to flash interface */ 2660 bce_enable_nvram_access(sc); 2661 2662 len32 = buf_size; 2663 offset32 = offset; 2664 extra = 0; 2665 2666 cmd_flags = 0; 2667 2668 if (offset32 & 3) { 2669 u8 buf[4]; 2670 u32 pre_len; 2671 2672 offset32 &= ~3; 2673 pre_len = 4 - (offset & 3); 2674 2675 if (pre_len >= len32) { 2676 pre_len = len32; 2677 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2678 } 2679 else { 2680 cmd_flags = BCE_NVM_COMMAND_FIRST; 2681 } 2682 2683 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2684 2685 if (rc) 2686 return rc; 2687 2688 memcpy(ret_buf, buf + (offset & 3), pre_len); 2689 2690 offset32 += 4; 2691 ret_buf += pre_len; 2692 len32 -= pre_len; 2693 } 2694 2695 if (len32 & 3) { 2696 extra = 4 - (len32 & 3); 2697 len32 = (len32 + 4) & ~3; 2698 } 2699 2700 if (len32 == 4) { 2701 u8 buf[4]; 2702 2703 if (cmd_flags) 2704 cmd_flags = BCE_NVM_COMMAND_LAST; 2705 else 2706 cmd_flags = BCE_NVM_COMMAND_FIRST | 2707 BCE_NVM_COMMAND_LAST; 2708 2709 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2710 2711 memcpy(ret_buf, buf, 4 - extra); 2712 } 2713 else if (len32 > 0) { 2714 u8 buf[4]; 2715 2716 /* Read the first word. */ 2717 if (cmd_flags) 2718 cmd_flags = 0; 2719 else 2720 cmd_flags = BCE_NVM_COMMAND_FIRST; 2721 2722 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2723 2724 /* Advance to the next dword. */ 2725 offset32 += 4; 2726 ret_buf += 4; 2727 len32 -= 4; 2728 2729 while (len32 > 4 && rc == 0) { 2730 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2731 2732 /* Advance to the next dword. */ 2733 offset32 += 4; 2734 ret_buf += 4; 2735 len32 -= 4; 2736 } 2737 2738 if (rc) 2739 goto bce_nvram_read_locked_exit; 2740 2741 cmd_flags = BCE_NVM_COMMAND_LAST; 2742 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2743 2744 memcpy(ret_buf, buf, 4 - extra); 2745 } 2746 2747 bce_nvram_read_locked_exit: 2748 /* Disable access to flash interface and release the lock. */ 2749 bce_disable_nvram_access(sc); 2750 bce_release_nvram_lock(sc); 2751 2752 bce_nvram_read_exit: 2753 DBEXIT(BCE_VERBOSE_NVRAM); 2754 return rc; 2755 } 2756 2757 2758 #ifdef BCE_NVRAM_WRITE_SUPPORT 2759 /****************************************************************************/ 2760 /* Write an arbitrary range of data from NVRAM. */ 2761 /* */ 2762 /* Prepares the NVRAM interface for write access and writes the requested */ 2763 /* data from the supplied buffer. The caller is responsible for */ 2764 /* calculating any appropriate CRCs. */ 2765 /* */ 2766 /* Returns: */ 2767 /* 0 on success, positive value on failure. */ 2768 /****************************************************************************/ 2769 static int 2770 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2771 int buf_size) 2772 { 2773 u32 written, offset32, len32; 2774 u8 *buf, start[4], end[4]; 2775 int rc = 0; 2776 int align_start, align_end; 2777 2778 DBENTER(BCE_VERBOSE_NVRAM); 2779 2780 buf = data_buf; 2781 offset32 = offset; 2782 len32 = buf_size; 2783 align_start = align_end = 0; 2784 2785 if ((align_start = (offset32 & 3))) { 2786 offset32 &= ~3; 2787 len32 += align_start; 2788 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2789 goto bce_nvram_write_exit; 2790 } 2791 2792 if (len32 & 3) { 2793 if ((len32 > 4) || !align_start) { 2794 align_end = 4 - (len32 & 3); 2795 len32 += align_end; 2796 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2797 end, 4))) { 2798 goto bce_nvram_write_exit; 2799 } 2800 } 2801 } 2802 2803 if (align_start || align_end) { 2804 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2805 if (buf == NULL) { 2806 rc = ENOMEM; 2807 goto bce_nvram_write_exit; 2808 } 2809 2810 if (align_start) { 2811 memcpy(buf, start, 4); 2812 } 2813 2814 if (align_end) { 2815 memcpy(buf + len32 - 4, end, 4); 2816 } 2817 memcpy(buf + align_start, data_buf, buf_size); 2818 } 2819 2820 written = 0; 2821 while ((written < len32) && (rc == 0)) { 2822 u32 page_start, page_end, data_start, data_end; 2823 u32 addr, cmd_flags; 2824 int i; 2825 u8 flash_buffer[264]; 2826 2827 /* Find the page_start addr */ 2828 page_start = offset32 + written; 2829 page_start -= (page_start % sc->bce_flash_info->page_size); 2830 /* Find the page_end addr */ 2831 page_end = page_start + sc->bce_flash_info->page_size; 2832 /* Find the data_start addr */ 2833 data_start = (written == 0) ? offset32 : page_start; 2834 /* Find the data_end addr */ 2835 data_end = (page_end > offset32 + len32) ? 2836 (offset32 + len32) : page_end; 2837 2838 /* Request access to the flash interface. */ 2839 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2840 goto bce_nvram_write_exit; 2841 2842 /* Enable access to flash interface */ 2843 bce_enable_nvram_access(sc); 2844 2845 cmd_flags = BCE_NVM_COMMAND_FIRST; 2846 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2847 int j; 2848 2849 /* Read the whole page into the buffer 2850 * (non-buffer flash only) */ 2851 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2852 if (j == (sc->bce_flash_info->page_size - 4)) { 2853 cmd_flags |= BCE_NVM_COMMAND_LAST; 2854 } 2855 rc = bce_nvram_read_dword(sc, 2856 page_start + j, 2857 &flash_buffer[j], 2858 cmd_flags); 2859 2860 if (rc) 2861 goto bce_nvram_write_locked_exit; 2862 2863 cmd_flags = 0; 2864 } 2865 } 2866 2867 /* Enable writes to flash interface (unlock write-protect) */ 2868 if ((rc = bce_enable_nvram_write(sc)) != 0) 2869 goto bce_nvram_write_locked_exit; 2870 2871 /* Erase the page */ 2872 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2873 goto bce_nvram_write_locked_exit; 2874 2875 /* Re-enable the write again for the actual write */ 2876 bce_enable_nvram_write(sc); 2877 2878 /* Loop to write back the buffer data from page_start to 2879 * data_start */ 2880 i = 0; 2881 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2882 for (addr = page_start; addr < data_start; 2883 addr += 4, i += 4) { 2884 2885 rc = bce_nvram_write_dword(sc, addr, 2886 &flash_buffer[i], cmd_flags); 2887 2888 if (rc != 0) 2889 goto bce_nvram_write_locked_exit; 2890 2891 cmd_flags = 0; 2892 } 2893 } 2894 2895 /* Loop to write the new data from data_start to data_end */ 2896 for (addr = data_start; addr < data_end; addr += 4, i++) { 2897 if ((addr == page_end - 4) || 2898 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2899 (addr == data_end - 4))) { 2900 2901 cmd_flags |= BCE_NVM_COMMAND_LAST; 2902 } 2903 rc = bce_nvram_write_dword(sc, addr, buf, 2904 cmd_flags); 2905 2906 if (rc != 0) 2907 goto bce_nvram_write_locked_exit; 2908 2909 cmd_flags = 0; 2910 buf += 4; 2911 } 2912 2913 /* Loop to write back the buffer data from data_end 2914 * to page_end */ 2915 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2916 for (addr = data_end; addr < page_end; 2917 addr += 4, i += 4) { 2918 2919 if (addr == page_end-4) { 2920 cmd_flags = BCE_NVM_COMMAND_LAST; 2921 } 2922 rc = bce_nvram_write_dword(sc, addr, 2923 &flash_buffer[i], cmd_flags); 2924 2925 if (rc != 0) 2926 goto bce_nvram_write_locked_exit; 2927 2928 cmd_flags = 0; 2929 } 2930 } 2931 2932 /* Disable writes to flash interface (lock write-protect) */ 2933 bce_disable_nvram_write(sc); 2934 2935 /* Disable access to flash interface */ 2936 bce_disable_nvram_access(sc); 2937 bce_release_nvram_lock(sc); 2938 2939 /* Increment written */ 2940 written += data_end - data_start; 2941 } 2942 2943 goto bce_nvram_write_exit; 2944 2945 bce_nvram_write_locked_exit: 2946 bce_disable_nvram_write(sc); 2947 bce_disable_nvram_access(sc); 2948 bce_release_nvram_lock(sc); 2949 2950 bce_nvram_write_exit: 2951 if (align_start || align_end) 2952 free(buf, M_DEVBUF); 2953 2954 DBEXIT(BCE_VERBOSE_NVRAM); 2955 return (rc); 2956 } 2957 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2958 2959 2960 /****************************************************************************/ 2961 /* Verifies that NVRAM is accessible and contains valid data. */ 2962 /* */ 2963 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2964 /* correct. */ 2965 /* */ 2966 /* Returns: */ 2967 /* 0 on success, positive value on failure. */ 2968 /****************************************************************************/ 2969 static int 2970 bce_nvram_test(struct bce_softc *sc) 2971 { 2972 u32 buf[BCE_NVRAM_SIZE / 4]; 2973 u8 *data = (u8 *) buf; 2974 int rc = 0; 2975 u32 magic, csum; 2976 2977 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2978 2979 /* 2980 * Check that the device NVRAM is valid by reading 2981 * the magic value at offset 0. 2982 */ 2983 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2984 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2985 __FILE__, __LINE__); 2986 goto bce_nvram_test_exit; 2987 } 2988 2989 /* 2990 * Verify that offset 0 of the NVRAM contains 2991 * a valid magic number. 2992 */ 2993 magic = bce_be32toh(buf[0]); 2994 if (magic != BCE_NVRAM_MAGIC) { 2995 rc = ENODEV; 2996 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2997 "Expected: 0x%08X, Found: 0x%08X\n", 2998 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2999 goto bce_nvram_test_exit; 3000 } 3001 3002 /* 3003 * Verify that the device NVRAM includes valid 3004 * configuration data. 3005 */ 3006 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 3007 BCE_PRINTF("%s(%d): Unable to read manufacturing " 3008 "Information from NVRAM!\n", __FILE__, __LINE__); 3009 goto bce_nvram_test_exit; 3010 } 3011 3012 csum = ether_crc32_le(data, 0x100); 3013 if (csum != BCE_CRC32_RESIDUAL) { 3014 rc = ENODEV; 3015 BCE_PRINTF("%s(%d): Invalid manufacturing information " 3016 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 3017 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 3018 goto bce_nvram_test_exit; 3019 } 3020 3021 csum = ether_crc32_le(data + 0x100, 0x100); 3022 if (csum != BCE_CRC32_RESIDUAL) { 3023 rc = ENODEV; 3024 BCE_PRINTF("%s(%d): Invalid feature configuration " 3025 "information NVRAM CRC! Expected: 0x%08X, " 3026 "Found: 08%08X\n", __FILE__, __LINE__, 3027 BCE_CRC32_RESIDUAL, csum); 3028 } 3029 3030 bce_nvram_test_exit: 3031 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 3032 return rc; 3033 } 3034 3035 3036 /****************************************************************************/ 3037 /* Calculates the size of the buffers to allocate based on the MTU. */ 3038 /* */ 3039 /* Returns: */ 3040 /* Nothing. */ 3041 /****************************************************************************/ 3042 static void 3043 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 3044 { 3045 DBENTER(BCE_VERBOSE_LOAD); 3046 3047 /* Use a single allocation type when header splitting enabled. */ 3048 if (bce_hdr_split == TRUE) { 3049 sc->rx_bd_mbuf_alloc_size = MHLEN; 3050 /* Make sure offset is 16 byte aligned for hardware. */ 3051 sc->rx_bd_mbuf_align_pad = 3052 roundup2(MSIZE - MHLEN, 16) - (MSIZE - MHLEN); 3053 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 3054 sc->rx_bd_mbuf_align_pad; 3055 } else { 3056 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 3057 ETHER_CRC_LEN) > MCLBYTES) { 3058 /* Setup for jumbo RX buffer allocations. */ 3059 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 3060 sc->rx_bd_mbuf_align_pad = 3061 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 3062 sc->rx_bd_mbuf_data_len = 3063 sc->rx_bd_mbuf_alloc_size - 3064 sc->rx_bd_mbuf_align_pad; 3065 } else { 3066 /* Setup for standard RX buffer allocations. */ 3067 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3068 sc->rx_bd_mbuf_align_pad = 3069 roundup2(MCLBYTES, 16) - MCLBYTES; 3070 sc->rx_bd_mbuf_data_len = 3071 sc->rx_bd_mbuf_alloc_size - 3072 sc->rx_bd_mbuf_align_pad; 3073 } 3074 } 3075 3076 // DBPRINT(sc, BCE_INFO_LOAD, 3077 DBPRINT(sc, BCE_WARN, 3078 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3079 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3080 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3081 sc->rx_bd_mbuf_align_pad); 3082 3083 DBEXIT(BCE_VERBOSE_LOAD); 3084 } 3085 3086 /****************************************************************************/ 3087 /* Identifies the current media type of the controller and sets the PHY */ 3088 /* address. */ 3089 /* */ 3090 /* Returns: */ 3091 /* Nothing. */ 3092 /****************************************************************************/ 3093 static void 3094 bce_get_media(struct bce_softc *sc) 3095 { 3096 u32 val; 3097 3098 DBENTER(BCE_VERBOSE_PHY); 3099 3100 /* Assume PHY address for copper controllers. */ 3101 sc->bce_phy_addr = 1; 3102 3103 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3104 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3105 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3106 u32 strap; 3107 3108 /* 3109 * The BCM5709S is software configurable 3110 * for Copper or SerDes operation. 3111 */ 3112 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3113 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3114 "for copper.\n"); 3115 goto bce_get_media_exit; 3116 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3117 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3118 "for dual media.\n"); 3119 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3120 goto bce_get_media_exit; 3121 } 3122 3123 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3124 strap = (val & 3125 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3126 else 3127 strap = (val & 3128 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3129 3130 if (pci_get_function(sc->bce_dev) == 0) { 3131 switch (strap) { 3132 case 0x4: 3133 case 0x5: 3134 case 0x6: 3135 DBPRINT(sc, BCE_INFO_LOAD, 3136 "BCM5709 s/w configured for SerDes.\n"); 3137 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3138 break; 3139 default: 3140 DBPRINT(sc, BCE_INFO_LOAD, 3141 "BCM5709 s/w configured for Copper.\n"); 3142 break; 3143 } 3144 } else { 3145 switch (strap) { 3146 case 0x1: 3147 case 0x2: 3148 case 0x4: 3149 DBPRINT(sc, BCE_INFO_LOAD, 3150 "BCM5709 s/w configured for SerDes.\n"); 3151 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3152 break; 3153 default: 3154 DBPRINT(sc, BCE_INFO_LOAD, 3155 "BCM5709 s/w configured for Copper.\n"); 3156 break; 3157 } 3158 } 3159 3160 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3161 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3162 3163 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3164 3165 sc->bce_flags |= BCE_NO_WOL_FLAG; 3166 3167 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3168 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3169 3170 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3171 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3172 sc->bce_phy_addr = 2; 3173 3174 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3175 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3176 sc->bce_phy_flags |= 3177 BCE_PHY_2_5G_CAPABLE_FLAG; 3178 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3179 "capable adapter\n"); 3180 } 3181 } 3182 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3183 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3184 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3185 3186 bce_get_media_exit: 3187 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3188 "Using PHY address %d.\n", sc->bce_phy_addr); 3189 3190 DBEXIT(BCE_VERBOSE_PHY); 3191 } 3192 3193 3194 /****************************************************************************/ 3195 /* Performs PHY initialization required before MII drivers access the */ 3196 /* device. */ 3197 /* */ 3198 /* Returns: */ 3199 /* Nothing. */ 3200 /****************************************************************************/ 3201 static void 3202 bce_init_media(struct bce_softc *sc) 3203 { 3204 if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG | 3205 BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) { 3206 /* 3207 * Configure 5709S/5716S PHYs to use traditional IEEE 3208 * Clause 22 method. Otherwise we have no way to attach 3209 * the PHY in mii(4) layer. PHY specific configuration 3210 * is done in mii layer. 3211 */ 3212 3213 /* Select auto-negotiation MMD of the PHY. */ 3214 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3215 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3216 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3217 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3218 3219 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3220 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3221 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3222 } 3223 } 3224 3225 3226 /****************************************************************************/ 3227 /* Free any DMA memory owned by the driver. */ 3228 /* */ 3229 /* Scans through each data structre that requires DMA memory and frees */ 3230 /* the memory if allocated. */ 3231 /* */ 3232 /* Returns: */ 3233 /* Nothing. */ 3234 /****************************************************************************/ 3235 static void 3236 bce_dma_free(struct bce_softc *sc) 3237 { 3238 int i; 3239 3240 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3241 3242 /* Free, unmap, and destroy the status block. */ 3243 if (sc->status_block_paddr != 0) { 3244 bus_dmamap_unload( 3245 sc->status_tag, 3246 sc->status_map); 3247 sc->status_block_paddr = 0; 3248 } 3249 3250 if (sc->status_block != NULL) { 3251 bus_dmamem_free( 3252 sc->status_tag, 3253 sc->status_block, 3254 sc->status_map); 3255 sc->status_block = NULL; 3256 } 3257 3258 if (sc->status_tag != NULL) { 3259 bus_dma_tag_destroy(sc->status_tag); 3260 sc->status_tag = NULL; 3261 } 3262 3263 3264 /* Free, unmap, and destroy the statistics block. */ 3265 if (sc->stats_block_paddr != 0) { 3266 bus_dmamap_unload( 3267 sc->stats_tag, 3268 sc->stats_map); 3269 sc->stats_block_paddr = 0; 3270 } 3271 3272 if (sc->stats_block != NULL) { 3273 bus_dmamem_free( 3274 sc->stats_tag, 3275 sc->stats_block, 3276 sc->stats_map); 3277 sc->stats_block = NULL; 3278 } 3279 3280 if (sc->stats_tag != NULL) { 3281 bus_dma_tag_destroy(sc->stats_tag); 3282 sc->stats_tag = NULL; 3283 } 3284 3285 3286 /* Free, unmap and destroy all context memory pages. */ 3287 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3288 for (i = 0; i < sc->ctx_pages; i++ ) { 3289 if (sc->ctx_paddr[i] != 0) { 3290 bus_dmamap_unload( 3291 sc->ctx_tag, 3292 sc->ctx_map[i]); 3293 sc->ctx_paddr[i] = 0; 3294 } 3295 3296 if (sc->ctx_block[i] != NULL) { 3297 bus_dmamem_free( 3298 sc->ctx_tag, 3299 sc->ctx_block[i], 3300 sc->ctx_map[i]); 3301 sc->ctx_block[i] = NULL; 3302 } 3303 } 3304 3305 /* Destroy the context memory tag. */ 3306 if (sc->ctx_tag != NULL) { 3307 bus_dma_tag_destroy(sc->ctx_tag); 3308 sc->ctx_tag = NULL; 3309 } 3310 } 3311 3312 3313 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3314 for (i = 0; i < sc->tx_pages; i++ ) { 3315 if (sc->tx_bd_chain_paddr[i] != 0) { 3316 bus_dmamap_unload( 3317 sc->tx_bd_chain_tag, 3318 sc->tx_bd_chain_map[i]); 3319 sc->tx_bd_chain_paddr[i] = 0; 3320 } 3321 3322 if (sc->tx_bd_chain[i] != NULL) { 3323 bus_dmamem_free( 3324 sc->tx_bd_chain_tag, 3325 sc->tx_bd_chain[i], 3326 sc->tx_bd_chain_map[i]); 3327 sc->tx_bd_chain[i] = NULL; 3328 } 3329 } 3330 3331 /* Destroy the TX buffer descriptor tag. */ 3332 if (sc->tx_bd_chain_tag != NULL) { 3333 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3334 sc->tx_bd_chain_tag = NULL; 3335 } 3336 3337 3338 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3339 for (i = 0; i < sc->rx_pages; i++ ) { 3340 if (sc->rx_bd_chain_paddr[i] != 0) { 3341 bus_dmamap_unload( 3342 sc->rx_bd_chain_tag, 3343 sc->rx_bd_chain_map[i]); 3344 sc->rx_bd_chain_paddr[i] = 0; 3345 } 3346 3347 if (sc->rx_bd_chain[i] != NULL) { 3348 bus_dmamem_free( 3349 sc->rx_bd_chain_tag, 3350 sc->rx_bd_chain[i], 3351 sc->rx_bd_chain_map[i]); 3352 sc->rx_bd_chain[i] = NULL; 3353 } 3354 } 3355 3356 /* Destroy the RX buffer descriptor tag. */ 3357 if (sc->rx_bd_chain_tag != NULL) { 3358 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3359 sc->rx_bd_chain_tag = NULL; 3360 } 3361 3362 3363 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3364 if (bce_hdr_split == TRUE) { 3365 for (i = 0; i < sc->pg_pages; i++ ) { 3366 if (sc->pg_bd_chain_paddr[i] != 0) { 3367 bus_dmamap_unload( 3368 sc->pg_bd_chain_tag, 3369 sc->pg_bd_chain_map[i]); 3370 sc->pg_bd_chain_paddr[i] = 0; 3371 } 3372 3373 if (sc->pg_bd_chain[i] != NULL) { 3374 bus_dmamem_free( 3375 sc->pg_bd_chain_tag, 3376 sc->pg_bd_chain[i], 3377 sc->pg_bd_chain_map[i]); 3378 sc->pg_bd_chain[i] = NULL; 3379 } 3380 } 3381 3382 /* Destroy the page buffer descriptor tag. */ 3383 if (sc->pg_bd_chain_tag != NULL) { 3384 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3385 sc->pg_bd_chain_tag = NULL; 3386 } 3387 } 3388 3389 3390 /* Unload and destroy the TX mbuf maps. */ 3391 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3392 if (sc->tx_mbuf_map[i] != NULL) { 3393 bus_dmamap_unload(sc->tx_mbuf_tag, 3394 sc->tx_mbuf_map[i]); 3395 bus_dmamap_destroy(sc->tx_mbuf_tag, 3396 sc->tx_mbuf_map[i]); 3397 sc->tx_mbuf_map[i] = NULL; 3398 } 3399 } 3400 3401 /* Destroy the TX mbuf tag. */ 3402 if (sc->tx_mbuf_tag != NULL) { 3403 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3404 sc->tx_mbuf_tag = NULL; 3405 } 3406 3407 /* Unload and destroy the RX mbuf maps. */ 3408 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3409 if (sc->rx_mbuf_map[i] != NULL) { 3410 bus_dmamap_unload(sc->rx_mbuf_tag, 3411 sc->rx_mbuf_map[i]); 3412 bus_dmamap_destroy(sc->rx_mbuf_tag, 3413 sc->rx_mbuf_map[i]); 3414 sc->rx_mbuf_map[i] = NULL; 3415 } 3416 } 3417 3418 /* Destroy the RX mbuf tag. */ 3419 if (sc->rx_mbuf_tag != NULL) { 3420 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3421 sc->rx_mbuf_tag = NULL; 3422 } 3423 3424 /* Unload and destroy the page mbuf maps. */ 3425 if (bce_hdr_split == TRUE) { 3426 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3427 if (sc->pg_mbuf_map[i] != NULL) { 3428 bus_dmamap_unload(sc->pg_mbuf_tag, 3429 sc->pg_mbuf_map[i]); 3430 bus_dmamap_destroy(sc->pg_mbuf_tag, 3431 sc->pg_mbuf_map[i]); 3432 sc->pg_mbuf_map[i] = NULL; 3433 } 3434 } 3435 3436 /* Destroy the page mbuf tag. */ 3437 if (sc->pg_mbuf_tag != NULL) { 3438 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3439 sc->pg_mbuf_tag = NULL; 3440 } 3441 } 3442 3443 /* Destroy the parent tag */ 3444 if (sc->parent_tag != NULL) { 3445 bus_dma_tag_destroy(sc->parent_tag); 3446 sc->parent_tag = NULL; 3447 } 3448 3449 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3450 } 3451 3452 3453 /****************************************************************************/ 3454 /* Get DMA memory from the OS. */ 3455 /* */ 3456 /* Validates that the OS has provided DMA buffers in response to a */ 3457 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3458 /* When the callback is used the OS will return 0 for the mapping function */ 3459 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3460 /* failures back to the caller. */ 3461 /* */ 3462 /* Returns: */ 3463 /* Nothing. */ 3464 /****************************************************************************/ 3465 static void 3466 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3467 { 3468 bus_addr_t *busaddr = arg; 3469 3470 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3471 __FUNCTION__, nseg)); 3472 /* Simulate a mapping failure. */ 3473 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3474 error = ENOMEM); 3475 3476 /* ToDo: How to increment debug sim_count variable here? */ 3477 3478 /* Check for an error and signal the caller that an error occurred. */ 3479 if (error) { 3480 *busaddr = 0; 3481 } else { 3482 *busaddr = segs->ds_addr; 3483 } 3484 } 3485 3486 3487 /****************************************************************************/ 3488 /* Allocate any DMA memory needed by the driver. */ 3489 /* */ 3490 /* Allocates DMA memory needed for the various global structures needed by */ 3491 /* hardware. */ 3492 /* */ 3493 /* Memory alignment requirements: */ 3494 /* +-----------------+----------+----------+----------+----------+ */ 3495 /* | | 5706 | 5708 | 5709 | 5716 | */ 3496 /* +-----------------+----------+----------+----------+----------+ */ 3497 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3498 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3499 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3500 /* |PG Buffers | none | none | none | none | */ 3501 /* |TX Buffers | none | none | none | none | */ 3502 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3503 /* |Context Memory | | | | | */ 3504 /* +-----------------+----------+----------+----------+----------+ */ 3505 /* */ 3506 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3507 /* */ 3508 /* Returns: */ 3509 /* 0 for success, positive value for failure. */ 3510 /****************************************************************************/ 3511 static int 3512 bce_dma_alloc(device_t dev) 3513 { 3514 struct bce_softc *sc; 3515 int i, error, rc = 0; 3516 bus_size_t max_size, max_seg_size; 3517 int max_segments; 3518 3519 sc = device_get_softc(dev); 3520 3521 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3522 3523 /* 3524 * Allocate the parent bus DMA tag appropriate for PCI. 3525 */ 3526 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3527 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3528 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3529 &sc->parent_tag)) { 3530 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3531 __FILE__, __LINE__); 3532 rc = ENOMEM; 3533 goto bce_dma_alloc_exit; 3534 } 3535 3536 /* 3537 * Create a DMA tag for the status block, allocate and clear the 3538 * memory, map the memory into DMA space, and fetch the physical 3539 * address of the block. 3540 */ 3541 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3542 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3543 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3544 0, NULL, NULL, &sc->status_tag)) { 3545 BCE_PRINTF("%s(%d): Could not allocate status block " 3546 "DMA tag!\n", __FILE__, __LINE__); 3547 rc = ENOMEM; 3548 goto bce_dma_alloc_exit; 3549 } 3550 3551 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3552 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3553 &sc->status_map)) { 3554 BCE_PRINTF("%s(%d): Could not allocate status block " 3555 "DMA memory!\n", __FILE__, __LINE__); 3556 rc = ENOMEM; 3557 goto bce_dma_alloc_exit; 3558 } 3559 3560 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3561 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3562 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3563 3564 if (error || sc->status_block_paddr == 0) { 3565 BCE_PRINTF("%s(%d): Could not map status block " 3566 "DMA memory!\n", __FILE__, __LINE__); 3567 rc = ENOMEM; 3568 goto bce_dma_alloc_exit; 3569 } 3570 3571 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3572 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3573 3574 /* 3575 * Create a DMA tag for the statistics block, allocate and clear the 3576 * memory, map the memory into DMA space, and fetch the physical 3577 * address of the block. 3578 */ 3579 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3580 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3581 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3582 0, NULL, NULL, &sc->stats_tag)) { 3583 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3584 "DMA tag!\n", __FILE__, __LINE__); 3585 rc = ENOMEM; 3586 goto bce_dma_alloc_exit; 3587 } 3588 3589 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3590 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3591 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3592 "DMA memory!\n", __FILE__, __LINE__); 3593 rc = ENOMEM; 3594 goto bce_dma_alloc_exit; 3595 } 3596 3597 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3598 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3599 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3600 3601 if (error || sc->stats_block_paddr == 0) { 3602 BCE_PRINTF("%s(%d): Could not map statistics block " 3603 "DMA memory!\n", __FILE__, __LINE__); 3604 rc = ENOMEM; 3605 goto bce_dma_alloc_exit; 3606 } 3607 3608 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3609 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3610 3611 /* BCM5709 uses host memory as cache for context memory. */ 3612 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3613 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3614 if (sc->ctx_pages == 0) 3615 sc->ctx_pages = 1; 3616 3617 DBRUNIF((sc->ctx_pages > 512), 3618 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3619 __FILE__, __LINE__, sc->ctx_pages)); 3620 3621 /* 3622 * Create a DMA tag for the context pages, 3623 * allocate and clear the memory, map the 3624 * memory into DMA space, and fetch the 3625 * physical address of the block. 3626 */ 3627 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3628 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3629 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3630 0, NULL, NULL, &sc->ctx_tag)) { 3631 BCE_PRINTF("%s(%d): Could not allocate CTX " 3632 "DMA tag!\n", __FILE__, __LINE__); 3633 rc = ENOMEM; 3634 goto bce_dma_alloc_exit; 3635 } 3636 3637 for (i = 0; i < sc->ctx_pages; i++) { 3638 3639 if(bus_dmamem_alloc(sc->ctx_tag, 3640 (void **)&sc->ctx_block[i], 3641 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3642 &sc->ctx_map[i])) { 3643 BCE_PRINTF("%s(%d): Could not allocate CTX " 3644 "DMA memory!\n", __FILE__, __LINE__); 3645 rc = ENOMEM; 3646 goto bce_dma_alloc_exit; 3647 } 3648 3649 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3650 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3651 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3652 3653 if (error || sc->ctx_paddr[i] == 0) { 3654 BCE_PRINTF("%s(%d): Could not map CTX " 3655 "DMA memory!\n", __FILE__, __LINE__); 3656 rc = ENOMEM; 3657 goto bce_dma_alloc_exit; 3658 } 3659 3660 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3661 "= 0x%jX\n", __FUNCTION__, i, 3662 (uintmax_t) sc->ctx_paddr[i]); 3663 } 3664 } 3665 3666 /* 3667 * Create a DMA tag for the TX buffer descriptor chain, 3668 * allocate and clear the memory, and fetch the 3669 * physical address of the block. 3670 */ 3671 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3672 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3673 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3674 NULL, NULL, &sc->tx_bd_chain_tag)) { 3675 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3676 "chain DMA tag!\n", __FILE__, __LINE__); 3677 rc = ENOMEM; 3678 goto bce_dma_alloc_exit; 3679 } 3680 3681 for (i = 0; i < sc->tx_pages; i++) { 3682 3683 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3684 (void **)&sc->tx_bd_chain[i], 3685 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3686 &sc->tx_bd_chain_map[i])) { 3687 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3688 "chain DMA memory!\n", __FILE__, __LINE__); 3689 rc = ENOMEM; 3690 goto bce_dma_alloc_exit; 3691 } 3692 3693 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3694 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3695 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3696 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3697 3698 if (error || sc->tx_bd_chain_paddr[i] == 0) { 3699 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3700 "chain DMA memory!\n", __FILE__, __LINE__); 3701 rc = ENOMEM; 3702 goto bce_dma_alloc_exit; 3703 } 3704 3705 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3706 "0x%jX\n", __FUNCTION__, i, 3707 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3708 } 3709 3710 /* Check the required size before mapping to conserve resources. */ 3711 if (bce_tso_enable) { 3712 max_size = BCE_TSO_MAX_SIZE; 3713 max_segments = BCE_MAX_SEGMENTS; 3714 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3715 } else { 3716 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3717 max_segments = BCE_MAX_SEGMENTS; 3718 max_seg_size = MCLBYTES; 3719 } 3720 3721 /* Create a DMA tag for TX mbufs. */ 3722 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3723 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3724 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3725 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3726 __FILE__, __LINE__); 3727 rc = ENOMEM; 3728 goto bce_dma_alloc_exit; 3729 } 3730 3731 /* Create DMA maps for the TX mbufs clusters. */ 3732 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3733 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3734 &sc->tx_mbuf_map[i])) { 3735 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3736 "map!\n", __FILE__, __LINE__); 3737 rc = ENOMEM; 3738 goto bce_dma_alloc_exit; 3739 } 3740 } 3741 3742 /* 3743 * Create a DMA tag for the RX buffer descriptor chain, 3744 * allocate and clear the memory, and fetch the physical 3745 * address of the blocks. 3746 */ 3747 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3748 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3749 sc->max_bus_addr, NULL, NULL, 3750 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3751 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3752 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3753 "DMA tag!\n", __FILE__, __LINE__); 3754 rc = ENOMEM; 3755 goto bce_dma_alloc_exit; 3756 } 3757 3758 for (i = 0; i < sc->rx_pages; i++) { 3759 3760 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3761 (void **)&sc->rx_bd_chain[i], 3762 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3763 &sc->rx_bd_chain_map[i])) { 3764 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3765 "chain DMA memory!\n", __FILE__, __LINE__); 3766 rc = ENOMEM; 3767 goto bce_dma_alloc_exit; 3768 } 3769 3770 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3771 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3772 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3773 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3774 3775 if (error || sc->rx_bd_chain_paddr[i] == 0) { 3776 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3777 "chain DMA memory!\n", __FILE__, __LINE__); 3778 rc = ENOMEM; 3779 goto bce_dma_alloc_exit; 3780 } 3781 3782 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3783 "0x%jX\n", __FUNCTION__, i, 3784 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3785 } 3786 3787 /* 3788 * Create a DMA tag for RX mbufs. 3789 */ 3790 if (bce_hdr_split == TRUE) 3791 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3792 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3793 else 3794 max_size = MJUM9BYTES; 3795 3796 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3797 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size); 3798 3799 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3800 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3801 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) { 3802 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3803 __FILE__, __LINE__); 3804 rc = ENOMEM; 3805 goto bce_dma_alloc_exit; 3806 } 3807 3808 /* Create DMA maps for the RX mbuf clusters. */ 3809 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3810 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3811 &sc->rx_mbuf_map[i])) { 3812 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3813 "DMA map!\n", __FILE__, __LINE__); 3814 rc = ENOMEM; 3815 goto bce_dma_alloc_exit; 3816 } 3817 } 3818 3819 if (bce_hdr_split == TRUE) { 3820 /* 3821 * Create a DMA tag for the page buffer descriptor chain, 3822 * allocate and clear the memory, and fetch the physical 3823 * address of the blocks. 3824 */ 3825 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3826 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3827 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3828 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3829 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3830 "chain DMA tag!\n", __FILE__, __LINE__); 3831 rc = ENOMEM; 3832 goto bce_dma_alloc_exit; 3833 } 3834 3835 for (i = 0; i < sc->pg_pages; i++) { 3836 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3837 (void **)&sc->pg_bd_chain[i], 3838 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3839 &sc->pg_bd_chain_map[i])) { 3840 BCE_PRINTF("%s(%d): Could not allocate page " 3841 "descriptor chain DMA memory!\n", 3842 __FILE__, __LINE__); 3843 rc = ENOMEM; 3844 goto bce_dma_alloc_exit; 3845 } 3846 3847 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3848 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3849 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3850 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3851 3852 if (error || sc->pg_bd_chain_paddr[i] == 0) { 3853 BCE_PRINTF("%s(%d): Could not map page descriptor " 3854 "chain DMA memory!\n", __FILE__, __LINE__); 3855 rc = ENOMEM; 3856 goto bce_dma_alloc_exit; 3857 } 3858 3859 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3860 "0x%jX\n", __FUNCTION__, i, 3861 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3862 } 3863 3864 /* 3865 * Create a DMA tag for page mbufs. 3866 */ 3867 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3868 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 3869 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3870 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3871 "DMA tag!\n", __FILE__, __LINE__); 3872 rc = ENOMEM; 3873 goto bce_dma_alloc_exit; 3874 } 3875 3876 /* Create DMA maps for the page mbuf clusters. */ 3877 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3878 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3879 &sc->pg_mbuf_map[i])) { 3880 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3881 "DMA map!\n", __FILE__, __LINE__); 3882 rc = ENOMEM; 3883 goto bce_dma_alloc_exit; 3884 } 3885 } 3886 } 3887 3888 bce_dma_alloc_exit: 3889 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3890 return(rc); 3891 } 3892 3893 3894 /****************************************************************************/ 3895 /* Release all resources used by the driver. */ 3896 /* */ 3897 /* Releases all resources acquired by the driver including interrupts, */ 3898 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3899 /* */ 3900 /* Returns: */ 3901 /* Nothing. */ 3902 /****************************************************************************/ 3903 static void 3904 bce_release_resources(struct bce_softc *sc) 3905 { 3906 device_t dev; 3907 3908 DBENTER(BCE_VERBOSE_RESET); 3909 3910 dev = sc->bce_dev; 3911 3912 bce_dma_free(sc); 3913 3914 if (sc->bce_intrhand != NULL) { 3915 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3916 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3917 } 3918 3919 if (sc->bce_res_irq != NULL) { 3920 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3921 bus_release_resource(dev, SYS_RES_IRQ, 3922 rman_get_rid(sc->bce_res_irq), sc->bce_res_irq); 3923 } 3924 3925 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3926 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3927 pci_release_msi(dev); 3928 } 3929 3930 if (sc->bce_res_mem != NULL) { 3931 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3932 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3933 sc->bce_res_mem); 3934 } 3935 3936 if (sc->bce_ifp != NULL) { 3937 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3938 if_free(sc->bce_ifp); 3939 } 3940 3941 if (mtx_initialized(&sc->bce_mtx)) 3942 BCE_LOCK_DESTROY(sc); 3943 3944 DBEXIT(BCE_VERBOSE_RESET); 3945 } 3946 3947 3948 /****************************************************************************/ 3949 /* Firmware synchronization. */ 3950 /* */ 3951 /* Before performing certain events such as a chip reset, synchronize with */ 3952 /* the firmware first. */ 3953 /* */ 3954 /* Returns: */ 3955 /* 0 for success, positive value for failure. */ 3956 /****************************************************************************/ 3957 static int 3958 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3959 { 3960 int i, rc = 0; 3961 u32 val; 3962 3963 DBENTER(BCE_VERBOSE_RESET); 3964 3965 /* Don't waste any time if we've timed out before. */ 3966 if (sc->bce_fw_timed_out == TRUE) { 3967 rc = EBUSY; 3968 goto bce_fw_sync_exit; 3969 } 3970 3971 /* Increment the message sequence number. */ 3972 sc->bce_fw_wr_seq++; 3973 msg_data |= sc->bce_fw_wr_seq; 3974 3975 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3976 "0x%08X\n", msg_data); 3977 3978 /* Send the message to the bootcode driver mailbox. */ 3979 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3980 3981 /* Wait for the bootcode to acknowledge the message. */ 3982 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3983 /* Check for a response in the bootcode firmware mailbox. */ 3984 val = bce_shmem_rd(sc, BCE_FW_MB); 3985 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3986 break; 3987 DELAY(1000); 3988 } 3989 3990 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3991 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3992 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3993 3994 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3995 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3996 3997 msg_data &= ~BCE_DRV_MSG_CODE; 3998 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3999 4000 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 4001 4002 sc->bce_fw_timed_out = TRUE; 4003 rc = EBUSY; 4004 } 4005 4006 bce_fw_sync_exit: 4007 DBEXIT(BCE_VERBOSE_RESET); 4008 return (rc); 4009 } 4010 4011 4012 /****************************************************************************/ 4013 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 4014 /* */ 4015 /* Returns: */ 4016 /* Nothing. */ 4017 /****************************************************************************/ 4018 static void 4019 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code, 4020 u32 rv2p_code_len, u32 rv2p_proc) 4021 { 4022 int i; 4023 u32 val; 4024 4025 DBENTER(BCE_VERBOSE_RESET); 4026 4027 /* Set the page size used by RV2P. */ 4028 if (rv2p_proc == RV2P_PROC2) { 4029 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 4030 } 4031 4032 for (i = 0; i < rv2p_code_len; i += 8) { 4033 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 4034 rv2p_code++; 4035 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 4036 rv2p_code++; 4037 4038 if (rv2p_proc == RV2P_PROC1) { 4039 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 4040 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 4041 } 4042 else { 4043 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4044 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4045 } 4046 } 4047 4048 /* Reset the processor, un-stall is done later. */ 4049 if (rv2p_proc == RV2P_PROC1) { 4050 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4051 } 4052 else { 4053 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4054 } 4055 4056 DBEXIT(BCE_VERBOSE_RESET); 4057 } 4058 4059 4060 /****************************************************************************/ 4061 /* Load RISC processor firmware. */ 4062 /* */ 4063 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4064 /* associated with a particular processor. */ 4065 /* */ 4066 /* Returns: */ 4067 /* Nothing. */ 4068 /****************************************************************************/ 4069 static void 4070 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4071 struct fw_info *fw) 4072 { 4073 u32 offset; 4074 4075 DBENTER(BCE_VERBOSE_RESET); 4076 4077 bce_halt_cpu(sc, cpu_reg); 4078 4079 /* Load the Text area. */ 4080 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4081 if (fw->text) { 4082 int j; 4083 4084 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4085 REG_WR_IND(sc, offset, fw->text[j]); 4086 } 4087 } 4088 4089 /* Load the Data area. */ 4090 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4091 if (fw->data) { 4092 int j; 4093 4094 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4095 REG_WR_IND(sc, offset, fw->data[j]); 4096 } 4097 } 4098 4099 /* Load the SBSS area. */ 4100 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4101 if (fw->sbss) { 4102 int j; 4103 4104 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4105 REG_WR_IND(sc, offset, fw->sbss[j]); 4106 } 4107 } 4108 4109 /* Load the BSS area. */ 4110 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4111 if (fw->bss) { 4112 int j; 4113 4114 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4115 REG_WR_IND(sc, offset, fw->bss[j]); 4116 } 4117 } 4118 4119 /* Load the Read-Only area. */ 4120 offset = cpu_reg->spad_base + 4121 (fw->rodata_addr - cpu_reg->mips_view_base); 4122 if (fw->rodata) { 4123 int j; 4124 4125 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4126 REG_WR_IND(sc, offset, fw->rodata[j]); 4127 } 4128 } 4129 4130 /* Clear the pre-fetch instruction and set the FW start address. */ 4131 REG_WR_IND(sc, cpu_reg->inst, 0); 4132 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4133 4134 DBEXIT(BCE_VERBOSE_RESET); 4135 } 4136 4137 4138 /****************************************************************************/ 4139 /* Starts the RISC processor. */ 4140 /* */ 4141 /* Assumes the CPU starting address has already been set. */ 4142 /* */ 4143 /* Returns: */ 4144 /* Nothing. */ 4145 /****************************************************************************/ 4146 static void 4147 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4148 { 4149 u32 val; 4150 4151 DBENTER(BCE_VERBOSE_RESET); 4152 4153 /* Start the CPU. */ 4154 val = REG_RD_IND(sc, cpu_reg->mode); 4155 val &= ~cpu_reg->mode_value_halt; 4156 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4157 REG_WR_IND(sc, cpu_reg->mode, val); 4158 4159 DBEXIT(BCE_VERBOSE_RESET); 4160 } 4161 4162 4163 /****************************************************************************/ 4164 /* Halts the RISC processor. */ 4165 /* */ 4166 /* Returns: */ 4167 /* Nothing. */ 4168 /****************************************************************************/ 4169 static void 4170 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4171 { 4172 u32 val; 4173 4174 DBENTER(BCE_VERBOSE_RESET); 4175 4176 /* Halt the CPU. */ 4177 val = REG_RD_IND(sc, cpu_reg->mode); 4178 val |= cpu_reg->mode_value_halt; 4179 REG_WR_IND(sc, cpu_reg->mode, val); 4180 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4181 4182 DBEXIT(BCE_VERBOSE_RESET); 4183 } 4184 4185 4186 /****************************************************************************/ 4187 /* Initialize the RX CPU. */ 4188 /* */ 4189 /* Returns: */ 4190 /* Nothing. */ 4191 /****************************************************************************/ 4192 static void 4193 bce_start_rxp_cpu(struct bce_softc *sc) 4194 { 4195 struct cpu_reg cpu_reg; 4196 4197 DBENTER(BCE_VERBOSE_RESET); 4198 4199 cpu_reg.mode = BCE_RXP_CPU_MODE; 4200 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4201 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4202 cpu_reg.state = BCE_RXP_CPU_STATE; 4203 cpu_reg.state_value_clear = 0xffffff; 4204 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4205 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4206 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4207 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4208 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4209 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4210 cpu_reg.mips_view_base = 0x8000000; 4211 4212 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4213 bce_start_cpu(sc, &cpu_reg); 4214 4215 DBEXIT(BCE_VERBOSE_RESET); 4216 } 4217 4218 4219 /****************************************************************************/ 4220 /* Initialize the RX CPU. */ 4221 /* */ 4222 /* Returns: */ 4223 /* Nothing. */ 4224 /****************************************************************************/ 4225 static void 4226 bce_init_rxp_cpu(struct bce_softc *sc) 4227 { 4228 struct cpu_reg cpu_reg; 4229 struct fw_info fw; 4230 4231 DBENTER(BCE_VERBOSE_RESET); 4232 4233 cpu_reg.mode = BCE_RXP_CPU_MODE; 4234 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4235 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4236 cpu_reg.state = BCE_RXP_CPU_STATE; 4237 cpu_reg.state_value_clear = 0xffffff; 4238 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4239 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4240 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4241 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4242 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4243 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4244 cpu_reg.mips_view_base = 0x8000000; 4245 4246 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4247 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4248 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4249 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4250 fw.start_addr = bce_RXP_b09FwStartAddr; 4251 4252 fw.text_addr = bce_RXP_b09FwTextAddr; 4253 fw.text_len = bce_RXP_b09FwTextLen; 4254 fw.text_index = 0; 4255 fw.text = bce_RXP_b09FwText; 4256 4257 fw.data_addr = bce_RXP_b09FwDataAddr; 4258 fw.data_len = bce_RXP_b09FwDataLen; 4259 fw.data_index = 0; 4260 fw.data = bce_RXP_b09FwData; 4261 4262 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4263 fw.sbss_len = bce_RXP_b09FwSbssLen; 4264 fw.sbss_index = 0; 4265 fw.sbss = bce_RXP_b09FwSbss; 4266 4267 fw.bss_addr = bce_RXP_b09FwBssAddr; 4268 fw.bss_len = bce_RXP_b09FwBssLen; 4269 fw.bss_index = 0; 4270 fw.bss = bce_RXP_b09FwBss; 4271 4272 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4273 fw.rodata_len = bce_RXP_b09FwRodataLen; 4274 fw.rodata_index = 0; 4275 fw.rodata = bce_RXP_b09FwRodata; 4276 } else { 4277 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4278 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4279 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4280 fw.start_addr = bce_RXP_b06FwStartAddr; 4281 4282 fw.text_addr = bce_RXP_b06FwTextAddr; 4283 fw.text_len = bce_RXP_b06FwTextLen; 4284 fw.text_index = 0; 4285 fw.text = bce_RXP_b06FwText; 4286 4287 fw.data_addr = bce_RXP_b06FwDataAddr; 4288 fw.data_len = bce_RXP_b06FwDataLen; 4289 fw.data_index = 0; 4290 fw.data = bce_RXP_b06FwData; 4291 4292 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4293 fw.sbss_len = bce_RXP_b06FwSbssLen; 4294 fw.sbss_index = 0; 4295 fw.sbss = bce_RXP_b06FwSbss; 4296 4297 fw.bss_addr = bce_RXP_b06FwBssAddr; 4298 fw.bss_len = bce_RXP_b06FwBssLen; 4299 fw.bss_index = 0; 4300 fw.bss = bce_RXP_b06FwBss; 4301 4302 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4303 fw.rodata_len = bce_RXP_b06FwRodataLen; 4304 fw.rodata_index = 0; 4305 fw.rodata = bce_RXP_b06FwRodata; 4306 } 4307 4308 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4309 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4310 4311 /* Delay RXP start until initialization is complete. */ 4312 4313 DBEXIT(BCE_VERBOSE_RESET); 4314 } 4315 4316 4317 /****************************************************************************/ 4318 /* Initialize the TX CPU. */ 4319 /* */ 4320 /* Returns: */ 4321 /* Nothing. */ 4322 /****************************************************************************/ 4323 static void 4324 bce_init_txp_cpu(struct bce_softc *sc) 4325 { 4326 struct cpu_reg cpu_reg; 4327 struct fw_info fw; 4328 4329 DBENTER(BCE_VERBOSE_RESET); 4330 4331 cpu_reg.mode = BCE_TXP_CPU_MODE; 4332 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4333 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4334 cpu_reg.state = BCE_TXP_CPU_STATE; 4335 cpu_reg.state_value_clear = 0xffffff; 4336 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4337 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4338 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4339 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4340 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4341 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4342 cpu_reg.mips_view_base = 0x8000000; 4343 4344 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4345 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4346 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4347 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4348 fw.start_addr = bce_TXP_b09FwStartAddr; 4349 4350 fw.text_addr = bce_TXP_b09FwTextAddr; 4351 fw.text_len = bce_TXP_b09FwTextLen; 4352 fw.text_index = 0; 4353 fw.text = bce_TXP_b09FwText; 4354 4355 fw.data_addr = bce_TXP_b09FwDataAddr; 4356 fw.data_len = bce_TXP_b09FwDataLen; 4357 fw.data_index = 0; 4358 fw.data = bce_TXP_b09FwData; 4359 4360 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4361 fw.sbss_len = bce_TXP_b09FwSbssLen; 4362 fw.sbss_index = 0; 4363 fw.sbss = bce_TXP_b09FwSbss; 4364 4365 fw.bss_addr = bce_TXP_b09FwBssAddr; 4366 fw.bss_len = bce_TXP_b09FwBssLen; 4367 fw.bss_index = 0; 4368 fw.bss = bce_TXP_b09FwBss; 4369 4370 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4371 fw.rodata_len = bce_TXP_b09FwRodataLen; 4372 fw.rodata_index = 0; 4373 fw.rodata = bce_TXP_b09FwRodata; 4374 } else { 4375 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4376 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4377 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4378 fw.start_addr = bce_TXP_b06FwStartAddr; 4379 4380 fw.text_addr = bce_TXP_b06FwTextAddr; 4381 fw.text_len = bce_TXP_b06FwTextLen; 4382 fw.text_index = 0; 4383 fw.text = bce_TXP_b06FwText; 4384 4385 fw.data_addr = bce_TXP_b06FwDataAddr; 4386 fw.data_len = bce_TXP_b06FwDataLen; 4387 fw.data_index = 0; 4388 fw.data = bce_TXP_b06FwData; 4389 4390 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4391 fw.sbss_len = bce_TXP_b06FwSbssLen; 4392 fw.sbss_index = 0; 4393 fw.sbss = bce_TXP_b06FwSbss; 4394 4395 fw.bss_addr = bce_TXP_b06FwBssAddr; 4396 fw.bss_len = bce_TXP_b06FwBssLen; 4397 fw.bss_index = 0; 4398 fw.bss = bce_TXP_b06FwBss; 4399 4400 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4401 fw.rodata_len = bce_TXP_b06FwRodataLen; 4402 fw.rodata_index = 0; 4403 fw.rodata = bce_TXP_b06FwRodata; 4404 } 4405 4406 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4407 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4408 bce_start_cpu(sc, &cpu_reg); 4409 4410 DBEXIT(BCE_VERBOSE_RESET); 4411 } 4412 4413 4414 /****************************************************************************/ 4415 /* Initialize the TPAT CPU. */ 4416 /* */ 4417 /* Returns: */ 4418 /* Nothing. */ 4419 /****************************************************************************/ 4420 static void 4421 bce_init_tpat_cpu(struct bce_softc *sc) 4422 { 4423 struct cpu_reg cpu_reg; 4424 struct fw_info fw; 4425 4426 DBENTER(BCE_VERBOSE_RESET); 4427 4428 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4429 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4430 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4431 cpu_reg.state = BCE_TPAT_CPU_STATE; 4432 cpu_reg.state_value_clear = 0xffffff; 4433 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4434 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4435 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4436 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4437 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4438 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4439 cpu_reg.mips_view_base = 0x8000000; 4440 4441 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4442 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4443 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4444 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4445 fw.start_addr = bce_TPAT_b09FwStartAddr; 4446 4447 fw.text_addr = bce_TPAT_b09FwTextAddr; 4448 fw.text_len = bce_TPAT_b09FwTextLen; 4449 fw.text_index = 0; 4450 fw.text = bce_TPAT_b09FwText; 4451 4452 fw.data_addr = bce_TPAT_b09FwDataAddr; 4453 fw.data_len = bce_TPAT_b09FwDataLen; 4454 fw.data_index = 0; 4455 fw.data = bce_TPAT_b09FwData; 4456 4457 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4458 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4459 fw.sbss_index = 0; 4460 fw.sbss = bce_TPAT_b09FwSbss; 4461 4462 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4463 fw.bss_len = bce_TPAT_b09FwBssLen; 4464 fw.bss_index = 0; 4465 fw.bss = bce_TPAT_b09FwBss; 4466 4467 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4468 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4469 fw.rodata_index = 0; 4470 fw.rodata = bce_TPAT_b09FwRodata; 4471 } else { 4472 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4473 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4474 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4475 fw.start_addr = bce_TPAT_b06FwStartAddr; 4476 4477 fw.text_addr = bce_TPAT_b06FwTextAddr; 4478 fw.text_len = bce_TPAT_b06FwTextLen; 4479 fw.text_index = 0; 4480 fw.text = bce_TPAT_b06FwText; 4481 4482 fw.data_addr = bce_TPAT_b06FwDataAddr; 4483 fw.data_len = bce_TPAT_b06FwDataLen; 4484 fw.data_index = 0; 4485 fw.data = bce_TPAT_b06FwData; 4486 4487 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4488 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4489 fw.sbss_index = 0; 4490 fw.sbss = bce_TPAT_b06FwSbss; 4491 4492 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4493 fw.bss_len = bce_TPAT_b06FwBssLen; 4494 fw.bss_index = 0; 4495 fw.bss = bce_TPAT_b06FwBss; 4496 4497 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4498 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4499 fw.rodata_index = 0; 4500 fw.rodata = bce_TPAT_b06FwRodata; 4501 } 4502 4503 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4504 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4505 bce_start_cpu(sc, &cpu_reg); 4506 4507 DBEXIT(BCE_VERBOSE_RESET); 4508 } 4509 4510 4511 /****************************************************************************/ 4512 /* Initialize the CP CPU. */ 4513 /* */ 4514 /* Returns: */ 4515 /* Nothing. */ 4516 /****************************************************************************/ 4517 static void 4518 bce_init_cp_cpu(struct bce_softc *sc) 4519 { 4520 struct cpu_reg cpu_reg; 4521 struct fw_info fw; 4522 4523 DBENTER(BCE_VERBOSE_RESET); 4524 4525 cpu_reg.mode = BCE_CP_CPU_MODE; 4526 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4527 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4528 cpu_reg.state = BCE_CP_CPU_STATE; 4529 cpu_reg.state_value_clear = 0xffffff; 4530 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4531 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4532 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4533 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4534 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4535 cpu_reg.spad_base = BCE_CP_SCRATCH; 4536 cpu_reg.mips_view_base = 0x8000000; 4537 4538 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4539 fw.ver_major = bce_CP_b09FwReleaseMajor; 4540 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4541 fw.ver_fix = bce_CP_b09FwReleaseFix; 4542 fw.start_addr = bce_CP_b09FwStartAddr; 4543 4544 fw.text_addr = bce_CP_b09FwTextAddr; 4545 fw.text_len = bce_CP_b09FwTextLen; 4546 fw.text_index = 0; 4547 fw.text = bce_CP_b09FwText; 4548 4549 fw.data_addr = bce_CP_b09FwDataAddr; 4550 fw.data_len = bce_CP_b09FwDataLen; 4551 fw.data_index = 0; 4552 fw.data = bce_CP_b09FwData; 4553 4554 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4555 fw.sbss_len = bce_CP_b09FwSbssLen; 4556 fw.sbss_index = 0; 4557 fw.sbss = bce_CP_b09FwSbss; 4558 4559 fw.bss_addr = bce_CP_b09FwBssAddr; 4560 fw.bss_len = bce_CP_b09FwBssLen; 4561 fw.bss_index = 0; 4562 fw.bss = bce_CP_b09FwBss; 4563 4564 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4565 fw.rodata_len = bce_CP_b09FwRodataLen; 4566 fw.rodata_index = 0; 4567 fw.rodata = bce_CP_b09FwRodata; 4568 } else { 4569 fw.ver_major = bce_CP_b06FwReleaseMajor; 4570 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4571 fw.ver_fix = bce_CP_b06FwReleaseFix; 4572 fw.start_addr = bce_CP_b06FwStartAddr; 4573 4574 fw.text_addr = bce_CP_b06FwTextAddr; 4575 fw.text_len = bce_CP_b06FwTextLen; 4576 fw.text_index = 0; 4577 fw.text = bce_CP_b06FwText; 4578 4579 fw.data_addr = bce_CP_b06FwDataAddr; 4580 fw.data_len = bce_CP_b06FwDataLen; 4581 fw.data_index = 0; 4582 fw.data = bce_CP_b06FwData; 4583 4584 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4585 fw.sbss_len = bce_CP_b06FwSbssLen; 4586 fw.sbss_index = 0; 4587 fw.sbss = bce_CP_b06FwSbss; 4588 4589 fw.bss_addr = bce_CP_b06FwBssAddr; 4590 fw.bss_len = bce_CP_b06FwBssLen; 4591 fw.bss_index = 0; 4592 fw.bss = bce_CP_b06FwBss; 4593 4594 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4595 fw.rodata_len = bce_CP_b06FwRodataLen; 4596 fw.rodata_index = 0; 4597 fw.rodata = bce_CP_b06FwRodata; 4598 } 4599 4600 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4601 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4602 bce_start_cpu(sc, &cpu_reg); 4603 4604 DBEXIT(BCE_VERBOSE_RESET); 4605 } 4606 4607 4608 /****************************************************************************/ 4609 /* Initialize the COM CPU. */ 4610 /* */ 4611 /* Returns: */ 4612 /* Nothing. */ 4613 /****************************************************************************/ 4614 static void 4615 bce_init_com_cpu(struct bce_softc *sc) 4616 { 4617 struct cpu_reg cpu_reg; 4618 struct fw_info fw; 4619 4620 DBENTER(BCE_VERBOSE_RESET); 4621 4622 cpu_reg.mode = BCE_COM_CPU_MODE; 4623 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4624 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4625 cpu_reg.state = BCE_COM_CPU_STATE; 4626 cpu_reg.state_value_clear = 0xffffff; 4627 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4628 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4629 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4630 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4631 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4632 cpu_reg.spad_base = BCE_COM_SCRATCH; 4633 cpu_reg.mips_view_base = 0x8000000; 4634 4635 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4636 fw.ver_major = bce_COM_b09FwReleaseMajor; 4637 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4638 fw.ver_fix = bce_COM_b09FwReleaseFix; 4639 fw.start_addr = bce_COM_b09FwStartAddr; 4640 4641 fw.text_addr = bce_COM_b09FwTextAddr; 4642 fw.text_len = bce_COM_b09FwTextLen; 4643 fw.text_index = 0; 4644 fw.text = bce_COM_b09FwText; 4645 4646 fw.data_addr = bce_COM_b09FwDataAddr; 4647 fw.data_len = bce_COM_b09FwDataLen; 4648 fw.data_index = 0; 4649 fw.data = bce_COM_b09FwData; 4650 4651 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4652 fw.sbss_len = bce_COM_b09FwSbssLen; 4653 fw.sbss_index = 0; 4654 fw.sbss = bce_COM_b09FwSbss; 4655 4656 fw.bss_addr = bce_COM_b09FwBssAddr; 4657 fw.bss_len = bce_COM_b09FwBssLen; 4658 fw.bss_index = 0; 4659 fw.bss = bce_COM_b09FwBss; 4660 4661 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4662 fw.rodata_len = bce_COM_b09FwRodataLen; 4663 fw.rodata_index = 0; 4664 fw.rodata = bce_COM_b09FwRodata; 4665 } else { 4666 fw.ver_major = bce_COM_b06FwReleaseMajor; 4667 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4668 fw.ver_fix = bce_COM_b06FwReleaseFix; 4669 fw.start_addr = bce_COM_b06FwStartAddr; 4670 4671 fw.text_addr = bce_COM_b06FwTextAddr; 4672 fw.text_len = bce_COM_b06FwTextLen; 4673 fw.text_index = 0; 4674 fw.text = bce_COM_b06FwText; 4675 4676 fw.data_addr = bce_COM_b06FwDataAddr; 4677 fw.data_len = bce_COM_b06FwDataLen; 4678 fw.data_index = 0; 4679 fw.data = bce_COM_b06FwData; 4680 4681 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4682 fw.sbss_len = bce_COM_b06FwSbssLen; 4683 fw.sbss_index = 0; 4684 fw.sbss = bce_COM_b06FwSbss; 4685 4686 fw.bss_addr = bce_COM_b06FwBssAddr; 4687 fw.bss_len = bce_COM_b06FwBssLen; 4688 fw.bss_index = 0; 4689 fw.bss = bce_COM_b06FwBss; 4690 4691 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4692 fw.rodata_len = bce_COM_b06FwRodataLen; 4693 fw.rodata_index = 0; 4694 fw.rodata = bce_COM_b06FwRodata; 4695 } 4696 4697 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4698 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4699 bce_start_cpu(sc, &cpu_reg); 4700 4701 DBEXIT(BCE_VERBOSE_RESET); 4702 } 4703 4704 4705 /****************************************************************************/ 4706 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4707 /* */ 4708 /* Loads the firmware for each CPU and starts the CPU. */ 4709 /* */ 4710 /* Returns: */ 4711 /* Nothing. */ 4712 /****************************************************************************/ 4713 static void 4714 bce_init_cpus(struct bce_softc *sc) 4715 { 4716 DBENTER(BCE_VERBOSE_RESET); 4717 4718 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4719 4720 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4721 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4722 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4723 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4724 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4725 } else { 4726 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4727 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4728 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4729 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4730 } 4731 4732 } else { 4733 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4734 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4735 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4736 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4737 } 4738 4739 bce_init_rxp_cpu(sc); 4740 bce_init_txp_cpu(sc); 4741 bce_init_tpat_cpu(sc); 4742 bce_init_com_cpu(sc); 4743 bce_init_cp_cpu(sc); 4744 4745 DBEXIT(BCE_VERBOSE_RESET); 4746 } 4747 4748 4749 /****************************************************************************/ 4750 /* Initialize context memory. */ 4751 /* */ 4752 /* Clears the memory associated with each Context ID (CID). */ 4753 /* */ 4754 /* Returns: */ 4755 /* Nothing. */ 4756 /****************************************************************************/ 4757 static int 4758 bce_init_ctx(struct bce_softc *sc) 4759 { 4760 u32 offset, val, vcid_addr; 4761 int i, j, rc, retry_cnt; 4762 4763 rc = 0; 4764 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4765 4766 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4767 retry_cnt = CTX_INIT_RETRY_COUNT; 4768 4769 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4770 4771 /* 4772 * BCM5709 context memory may be cached 4773 * in host memory so prepare the host memory 4774 * for access. 4775 */ 4776 val = BCE_CTX_COMMAND_ENABLED | 4777 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4778 val |= (BCM_PAGE_BITS - 8) << 16; 4779 REG_WR(sc, BCE_CTX_COMMAND, val); 4780 4781 /* Wait for mem init command to complete. */ 4782 for (i = 0; i < retry_cnt; i++) { 4783 val = REG_RD(sc, BCE_CTX_COMMAND); 4784 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4785 break; 4786 DELAY(2); 4787 } 4788 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4789 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4790 __FUNCTION__); 4791 rc = EBUSY; 4792 goto init_ctx_fail; 4793 } 4794 4795 for (i = 0; i < sc->ctx_pages; i++) { 4796 /* Set the physical address of the context memory. */ 4797 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4798 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4799 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4800 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4801 BCE_ADDR_HI(sc->ctx_paddr[i])); 4802 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4803 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4804 4805 /* Verify the context memory write was successful. */ 4806 for (j = 0; j < retry_cnt; j++) { 4807 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4808 if ((val & 4809 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4810 break; 4811 DELAY(5); 4812 } 4813 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4814 BCE_PRINTF("%s(): Failed to initialize " 4815 "context page %d!\n", __FUNCTION__, i); 4816 rc = EBUSY; 4817 goto init_ctx_fail; 4818 } 4819 } 4820 } else { 4821 4822 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4823 4824 /* 4825 * For the 5706/5708, context memory is local to 4826 * the controller, so initialize the controller 4827 * context memory. 4828 */ 4829 4830 vcid_addr = GET_CID_ADDR(96); 4831 while (vcid_addr) { 4832 4833 vcid_addr -= PHY_CTX_SIZE; 4834 4835 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4836 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4837 4838 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4839 CTX_WR(sc, 0x00, offset, 0); 4840 } 4841 4842 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4843 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4844 } 4845 4846 } 4847 init_ctx_fail: 4848 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4849 return (rc); 4850 } 4851 4852 4853 /****************************************************************************/ 4854 /* Fetch the permanent MAC address of the controller. */ 4855 /* */ 4856 /* Returns: */ 4857 /* Nothing. */ 4858 /****************************************************************************/ 4859 static void 4860 bce_get_mac_addr(struct bce_softc *sc) 4861 { 4862 u32 mac_lo = 0, mac_hi = 0; 4863 4864 DBENTER(BCE_VERBOSE_RESET); 4865 4866 /* 4867 * The NetXtreme II bootcode populates various NIC 4868 * power-on and runtime configuration items in a 4869 * shared memory area. The factory configured MAC 4870 * address is available from both NVRAM and the 4871 * shared memory area so we'll read the value from 4872 * shared memory for speed. 4873 */ 4874 4875 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4876 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4877 4878 if ((mac_lo == 0) && (mac_hi == 0)) { 4879 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4880 __FILE__, __LINE__); 4881 } else { 4882 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4883 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4884 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4885 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4886 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4887 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4888 } 4889 4890 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4891 "address = %6D\n", sc->eaddr, ":"); 4892 DBEXIT(BCE_VERBOSE_RESET); 4893 } 4894 4895 4896 /****************************************************************************/ 4897 /* Program the MAC address. */ 4898 /* */ 4899 /* Returns: */ 4900 /* Nothing. */ 4901 /****************************************************************************/ 4902 static void 4903 bce_set_mac_addr(struct bce_softc *sc) 4904 { 4905 u32 val; 4906 u8 *mac_addr = sc->eaddr; 4907 4908 /* ToDo: Add support for setting multiple MAC addresses. */ 4909 4910 DBENTER(BCE_VERBOSE_RESET); 4911 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4912 "%6D\n", sc->eaddr, ":"); 4913 4914 val = (mac_addr[0] << 8) | mac_addr[1]; 4915 4916 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4917 4918 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4919 (mac_addr[4] << 8) | mac_addr[5]; 4920 4921 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4922 4923 DBEXIT(BCE_VERBOSE_RESET); 4924 } 4925 4926 4927 /****************************************************************************/ 4928 /* Stop the controller. */ 4929 /* */ 4930 /* Returns: */ 4931 /* Nothing. */ 4932 /****************************************************************************/ 4933 static void 4934 bce_stop(struct bce_softc *sc) 4935 { 4936 struct ifnet *ifp; 4937 4938 DBENTER(BCE_VERBOSE_RESET); 4939 4940 BCE_LOCK_ASSERT(sc); 4941 4942 ifp = sc->bce_ifp; 4943 4944 callout_stop(&sc->bce_tick_callout); 4945 4946 /* Disable the transmit/receive blocks. */ 4947 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4948 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4949 DELAY(20); 4950 4951 bce_disable_intr(sc); 4952 4953 /* Free RX buffers. */ 4954 if (bce_hdr_split == TRUE) { 4955 bce_free_pg_chain(sc); 4956 } 4957 bce_free_rx_chain(sc); 4958 4959 /* Free TX buffers. */ 4960 bce_free_tx_chain(sc); 4961 4962 sc->watchdog_timer = 0; 4963 4964 sc->bce_link_up = FALSE; 4965 4966 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4967 4968 DBEXIT(BCE_VERBOSE_RESET); 4969 } 4970 4971 4972 static int 4973 bce_reset(struct bce_softc *sc, u32 reset_code) 4974 { 4975 u32 emac_mode_save, val; 4976 int i, rc = 0; 4977 static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT | 4978 BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G; 4979 4980 DBENTER(BCE_VERBOSE_RESET); 4981 4982 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4983 __FUNCTION__, reset_code); 4984 4985 /* 4986 * If ASF/IPMI is operational, then the EMAC Mode register already 4987 * contains appropriate values for the link settings that have 4988 * been auto-negotiated. Resetting the chip will clobber those 4989 * values. Save the important bits so we can restore them after 4990 * the reset. 4991 */ 4992 emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask; 4993 4994 /* Wait for pending PCI transactions to complete. */ 4995 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4996 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4997 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4998 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4999 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 5000 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 5001 DELAY(5); 5002 5003 /* Disable DMA */ 5004 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5005 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5006 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5007 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5008 } 5009 5010 /* Assume bootcode is running. */ 5011 sc->bce_fw_timed_out = FALSE; 5012 sc->bce_drv_cardiac_arrest = FALSE; 5013 5014 /* Give the firmware a chance to prepare for the reset. */ 5015 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 5016 if (rc) 5017 goto bce_reset_exit; 5018 5019 /* Set a firmware reminder that this is a soft reset. */ 5020 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 5021 5022 /* Dummy read to force the chip to complete all current transactions. */ 5023 val = REG_RD(sc, BCE_MISC_ID); 5024 5025 /* Chip reset. */ 5026 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5027 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 5028 REG_RD(sc, BCE_MISC_COMMAND); 5029 DELAY(5); 5030 5031 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5032 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5033 5034 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 5035 } else { 5036 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5037 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 5038 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 5039 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 5040 5041 /* Allow up to 30us for reset to complete. */ 5042 for (i = 0; i < 10; i++) { 5043 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 5044 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5045 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 5046 break; 5047 } 5048 DELAY(10); 5049 } 5050 5051 /* Check that reset completed successfully. */ 5052 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 5053 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5054 BCE_PRINTF("%s(%d): Reset failed!\n", 5055 __FILE__, __LINE__); 5056 rc = EBUSY; 5057 goto bce_reset_exit; 5058 } 5059 } 5060 5061 /* Make sure byte swapping is properly configured. */ 5062 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5063 if (val != 0x01020304) { 5064 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5065 __FILE__, __LINE__); 5066 rc = ENODEV; 5067 goto bce_reset_exit; 5068 } 5069 5070 /* Just completed a reset, assume that firmware is running again. */ 5071 sc->bce_fw_timed_out = FALSE; 5072 sc->bce_drv_cardiac_arrest = FALSE; 5073 5074 /* Wait for the firmware to finish its initialization. */ 5075 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5076 if (rc) 5077 BCE_PRINTF("%s(%d): Firmware did not complete " 5078 "initialization!\n", __FILE__, __LINE__); 5079 /* Get firmware capabilities. */ 5080 bce_fw_cap_init(sc); 5081 5082 bce_reset_exit: 5083 /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */ 5084 if (reset_code == BCE_DRV_MSG_CODE_RESET) { 5085 val = REG_RD(sc, BCE_EMAC_MODE); 5086 val = (val & ~emac_mode_mask) | emac_mode_save; 5087 REG_WR(sc, BCE_EMAC_MODE, val); 5088 } 5089 5090 DBEXIT(BCE_VERBOSE_RESET); 5091 return (rc); 5092 } 5093 5094 5095 static int 5096 bce_chipinit(struct bce_softc *sc) 5097 { 5098 u32 val; 5099 int rc = 0; 5100 5101 DBENTER(BCE_VERBOSE_RESET); 5102 5103 bce_disable_intr(sc); 5104 5105 /* 5106 * Initialize DMA byte/word swapping, configure the number of DMA 5107 * channels and PCI clock compensation delay. 5108 */ 5109 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5110 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5111 #if BYTE_ORDER == BIG_ENDIAN 5112 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5113 #endif 5114 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5115 DMA_READ_CHANS << 12 | 5116 DMA_WRITE_CHANS << 16; 5117 5118 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5119 5120 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5121 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5122 5123 /* 5124 * This setting resolves a problem observed on certain Intel PCI 5125 * chipsets that cannot handle multiple outstanding DMA operations. 5126 * See errata E9_5706A1_65. 5127 */ 5128 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5129 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5130 !(sc->bce_flags & BCE_PCIX_FLAG)) 5131 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5132 5133 REG_WR(sc, BCE_DMA_CONFIG, val); 5134 5135 /* Enable the RX_V2P and Context state machines before access. */ 5136 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5137 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5138 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5139 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5140 5141 /* Initialize context mapping and zero out the quick contexts. */ 5142 if ((rc = bce_init_ctx(sc)) != 0) 5143 goto bce_chipinit_exit; 5144 5145 /* Initialize the on-boards CPUs */ 5146 bce_init_cpus(sc); 5147 5148 /* Enable management frames (NC-SI) to flow to the MCP. */ 5149 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5150 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5151 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5152 } 5153 5154 /* Prepare NVRAM for access. */ 5155 if ((rc = bce_init_nvram(sc)) != 0) 5156 goto bce_chipinit_exit; 5157 5158 /* Set the kernel bypass block size */ 5159 val = REG_RD(sc, BCE_MQ_CONFIG); 5160 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5161 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5162 5163 /* Enable bins used on the 5709. */ 5164 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5165 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5166 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5167 val |= BCE_MQ_CONFIG_HALT_DIS; 5168 } 5169 5170 REG_WR(sc, BCE_MQ_CONFIG, val); 5171 5172 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5173 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5174 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5175 5176 /* Set the page size and clear the RV2P processor stall bits. */ 5177 val = (BCM_PAGE_BITS - 8) << 24; 5178 REG_WR(sc, BCE_RV2P_CONFIG, val); 5179 5180 /* Configure page size. */ 5181 val = REG_RD(sc, BCE_TBDR_CONFIG); 5182 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5183 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5184 REG_WR(sc, BCE_TBDR_CONFIG, val); 5185 5186 /* Set the perfect match control register to default. */ 5187 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5188 5189 bce_chipinit_exit: 5190 DBEXIT(BCE_VERBOSE_RESET); 5191 5192 return(rc); 5193 } 5194 5195 5196 /****************************************************************************/ 5197 /* Initialize the controller in preparation to send/receive traffic. */ 5198 /* */ 5199 /* Returns: */ 5200 /* 0 for success, positive value for failure. */ 5201 /****************************************************************************/ 5202 static int 5203 bce_blockinit(struct bce_softc *sc) 5204 { 5205 u32 reg, val; 5206 int rc = 0; 5207 5208 DBENTER(BCE_VERBOSE_RESET); 5209 5210 /* Load the hardware default MAC address. */ 5211 bce_set_mac_addr(sc); 5212 5213 /* Set the Ethernet backoff seed value */ 5214 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5215 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5216 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5217 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5218 5219 sc->last_status_idx = 0; 5220 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5221 5222 /* Set up link change interrupt generation. */ 5223 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5224 5225 /* Program the physical address of the status block. */ 5226 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5227 BCE_ADDR_LO(sc->status_block_paddr)); 5228 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5229 BCE_ADDR_HI(sc->status_block_paddr)); 5230 5231 /* Program the physical address of the statistics block. */ 5232 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5233 BCE_ADDR_LO(sc->stats_block_paddr)); 5234 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5235 BCE_ADDR_HI(sc->stats_block_paddr)); 5236 5237 /* 5238 * Program various host coalescing parameters. 5239 * Trip points control how many BDs should be ready before generating 5240 * an interrupt while ticks control how long a BD can sit in the chain 5241 * before generating an interrupt. 5242 */ 5243 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5244 (sc->bce_tx_quick_cons_trip_int << 16) | 5245 sc->bce_tx_quick_cons_trip); 5246 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5247 (sc->bce_rx_quick_cons_trip_int << 16) | 5248 sc->bce_rx_quick_cons_trip); 5249 REG_WR(sc, BCE_HC_TX_TICKS, 5250 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5251 REG_WR(sc, BCE_HC_RX_TICKS, 5252 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5253 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00); 5254 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5255 /* Not used for L2. */ 5256 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0); 5257 REG_WR(sc, BCE_HC_COM_TICKS, 0); 5258 REG_WR(sc, BCE_HC_CMD_TICKS, 0); 5259 5260 /* Configure the Host Coalescing block. */ 5261 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5262 BCE_HC_CONFIG_COLLECT_STATS; 5263 5264 #if 0 5265 /* ToDo: Add MSI-X support. */ 5266 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5267 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5268 BCE_HC_SB_CONFIG_1; 5269 5270 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5271 5272 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5273 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5274 5275 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5276 (sc->tx_quick_cons_trip_int << 16) | 5277 sc->tx_quick_cons_trip); 5278 5279 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5280 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5281 5282 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5283 } 5284 5285 /* 5286 * Tell the HC block to automatically set the 5287 * INT_MASK bit after an MSI/MSI-X interrupt 5288 * is generated so the driver doesn't have to. 5289 */ 5290 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5291 val |= BCE_HC_CONFIG_ONE_SHOT; 5292 5293 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5294 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5295 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5296 #endif 5297 5298 REG_WR(sc, BCE_HC_CONFIG, val); 5299 5300 /* Clear the internal statistics counters. */ 5301 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5302 5303 /* Verify that bootcode is running. */ 5304 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5305 5306 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5307 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5308 __FILE__, __LINE__); 5309 reg = 0); 5310 5311 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5312 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5313 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5314 "Expected: 08%08X\n", __FILE__, __LINE__, 5315 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5316 BCE_DEV_INFO_SIGNATURE_MAGIC); 5317 rc = ENODEV; 5318 goto bce_blockinit_exit; 5319 } 5320 5321 /* Enable DMA */ 5322 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5323 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5324 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5325 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5326 } 5327 5328 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5329 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5330 BCE_DRV_MSG_CODE_RESET); 5331 5332 /* Enable link state change interrupt generation. */ 5333 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5334 5335 /* Enable the RXP. */ 5336 bce_start_rxp_cpu(sc); 5337 5338 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5339 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5340 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5341 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5342 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5343 } 5344 5345 /* Enable all remaining blocks in the MAC. */ 5346 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5347 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5348 BCE_MISC_ENABLE_DEFAULT_XI); 5349 else 5350 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5351 BCE_MISC_ENABLE_DEFAULT); 5352 5353 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5354 DELAY(20); 5355 5356 /* Save the current host coalescing block settings. */ 5357 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5358 5359 bce_blockinit_exit: 5360 DBEXIT(BCE_VERBOSE_RESET); 5361 5362 return (rc); 5363 } 5364 5365 5366 /****************************************************************************/ 5367 /* Encapsulate an mbuf into the rx_bd chain. */ 5368 /* */ 5369 /* Returns: */ 5370 /* 0 for success, positive value for failure. */ 5371 /****************************************************************************/ 5372 static int 5373 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq) 5374 { 5375 bus_dma_segment_t segs[1]; 5376 struct mbuf *m_new = NULL; 5377 struct rx_bd *rxbd; 5378 int nsegs, error, rc = 0; 5379 #ifdef BCE_DEBUG 5380 u16 debug_chain_prod = chain_prod; 5381 #endif 5382 5383 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5384 5385 /* Make sure the inputs are valid. */ 5386 DBRUNIF((chain_prod > MAX_RX_BD_ALLOC), 5387 BCE_PRINTF("%s(%d): RX producer out of range: " 5388 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5389 chain_prod, (u16)MAX_RX_BD_ALLOC)); 5390 5391 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5392 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5393 prod, chain_prod, *prod_bseq); 5394 5395 /* Update some debug statistic counters */ 5396 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5397 sc->rx_low_watermark = sc->free_rx_bd); 5398 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5399 sc->rx_empty_count++); 5400 5401 /* Simulate an mbuf allocation failure. */ 5402 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5403 sc->mbuf_alloc_failed_count++; 5404 sc->mbuf_alloc_failed_sim_count++; 5405 rc = ENOBUFS; 5406 goto bce_get_rx_buf_exit); 5407 5408 /* This is a new mbuf allocation. */ 5409 if (bce_hdr_split == TRUE) 5410 MGETHDR(m_new, M_NOWAIT, MT_DATA); 5411 else 5412 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, 5413 sc->rx_bd_mbuf_alloc_size); 5414 5415 if (m_new == NULL) { 5416 sc->mbuf_alloc_failed_count++; 5417 rc = ENOBUFS; 5418 goto bce_get_rx_buf_exit; 5419 } 5420 5421 DBRUN(sc->debug_rx_mbuf_alloc++); 5422 5423 /* Make sure we have a valid packet header. */ 5424 M_ASSERTPKTHDR(m_new); 5425 5426 /* Initialize the mbuf size and pad if necessary for alignment. */ 5427 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5428 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5429 5430 /* ToDo: Consider calling m_fragment() to test error handling. */ 5431 5432 /* Map the mbuf cluster into device memory. */ 5433 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, 5434 sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5435 5436 /* Handle any mapping errors. */ 5437 if (error) { 5438 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5439 "chain (%d)!\n", __FILE__, __LINE__, error); 5440 5441 sc->dma_map_addr_rx_failed_count++; 5442 m_freem(m_new); 5443 5444 DBRUN(sc->debug_rx_mbuf_alloc--); 5445 5446 rc = ENOBUFS; 5447 goto bce_get_rx_buf_exit; 5448 } 5449 5450 /* All mbufs must map to a single segment. */ 5451 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5452 __FUNCTION__, nsegs)); 5453 5454 /* Setup the rx_bd for the segment. */ 5455 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)]; 5456 5457 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5458 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5459 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5460 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5461 *prod_bseq += segs[0].ds_len; 5462 5463 /* Save the mbuf and update our counter. */ 5464 sc->rx_mbuf_ptr[chain_prod] = m_new; 5465 sc->free_rx_bd -= nsegs; 5466 5467 DBRUNMSG(BCE_INSANE_RECV, 5468 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5469 5470 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5471 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod, 5472 chain_prod, *prod_bseq); 5473 5474 bce_get_rx_buf_exit: 5475 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5476 5477 return(rc); 5478 } 5479 5480 5481 /****************************************************************************/ 5482 /* Encapsulate an mbuf cluster into the page chain. */ 5483 /* */ 5484 /* Returns: */ 5485 /* 0 for success, positive value for failure. */ 5486 /****************************************************************************/ 5487 static int 5488 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx) 5489 { 5490 bus_dma_segment_t segs[1]; 5491 struct mbuf *m_new = NULL; 5492 struct rx_bd *pgbd; 5493 int error, nsegs, rc = 0; 5494 #ifdef BCE_DEBUG 5495 u16 debug_prod_idx = prod_idx; 5496 #endif 5497 5498 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5499 5500 /* Make sure the inputs are valid. */ 5501 DBRUNIF((prod_idx > MAX_PG_BD_ALLOC), 5502 BCE_PRINTF("%s(%d): page producer out of range: " 5503 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5504 prod_idx, (u16)MAX_PG_BD_ALLOC)); 5505 5506 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5507 "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5508 5509 /* Update counters if we've hit a new low or run out of pages. */ 5510 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5511 sc->pg_low_watermark = sc->free_pg_bd); 5512 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5513 5514 /* Simulate an mbuf allocation failure. */ 5515 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5516 sc->mbuf_alloc_failed_count++; 5517 sc->mbuf_alloc_failed_sim_count++; 5518 rc = ENOBUFS; 5519 goto bce_get_pg_buf_exit); 5520 5521 /* This is a new mbuf allocation. */ 5522 m_new = m_getcl(M_NOWAIT, MT_DATA, 0); 5523 if (m_new == NULL) { 5524 sc->mbuf_alloc_failed_count++; 5525 rc = ENOBUFS; 5526 goto bce_get_pg_buf_exit; 5527 } 5528 5529 DBRUN(sc->debug_pg_mbuf_alloc++); 5530 5531 m_new->m_len = MCLBYTES; 5532 5533 /* ToDo: Consider calling m_fragment() to test error handling. */ 5534 5535 /* Map the mbuf cluster into device memory. */ 5536 error = bus_dmamap_load_mbuf_sg(sc->pg_mbuf_tag, 5537 sc->pg_mbuf_map[prod_idx], m_new, segs, &nsegs, BUS_DMA_NOWAIT); 5538 5539 /* Handle any mapping errors. */ 5540 if (error) { 5541 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5542 __FILE__, __LINE__); 5543 5544 m_freem(m_new); 5545 DBRUN(sc->debug_pg_mbuf_alloc--); 5546 5547 rc = ENOBUFS; 5548 goto bce_get_pg_buf_exit; 5549 } 5550 5551 /* All mbufs must map to a single segment. */ 5552 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5553 __FUNCTION__, nsegs)); 5554 5555 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5556 5557 /* 5558 * The page chain uses the same rx_bd data structure 5559 * as the receive chain but doesn't require a byte sequence (bseq). 5560 */ 5561 pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)]; 5562 5563 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5564 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5565 pgbd->rx_bd_len = htole32(MCLBYTES); 5566 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5567 5568 /* Save the mbuf and update our counter. */ 5569 sc->pg_mbuf_ptr[prod_idx] = m_new; 5570 sc->free_pg_bd--; 5571 5572 DBRUNMSG(BCE_INSANE_RECV, 5573 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5574 5575 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5576 "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx); 5577 5578 bce_get_pg_buf_exit: 5579 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5580 5581 return(rc); 5582 } 5583 5584 5585 /****************************************************************************/ 5586 /* Initialize the TX context memory. */ 5587 /* */ 5588 /* Returns: */ 5589 /* Nothing */ 5590 /****************************************************************************/ 5591 static void 5592 bce_init_tx_context(struct bce_softc *sc) 5593 { 5594 u32 val; 5595 5596 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5597 5598 /* Initialize the context ID for an L2 TX chain. */ 5599 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5600 /* Set the CID type to support an L2 connection. */ 5601 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5602 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5603 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5604 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5605 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5606 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5607 5608 /* Point the hardware to the first page in the chain. */ 5609 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5610 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5611 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5612 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5613 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5614 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5615 } else { 5616 /* Set the CID type to support an L2 connection. */ 5617 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5618 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5619 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5620 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5621 5622 /* Point the hardware to the first page in the chain. */ 5623 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5624 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5625 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5626 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5627 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5628 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5629 } 5630 5631 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5632 } 5633 5634 5635 /****************************************************************************/ 5636 /* Allocate memory and initialize the TX data structures. */ 5637 /* */ 5638 /* Returns: */ 5639 /* 0 for success, positive value for failure. */ 5640 /****************************************************************************/ 5641 static int 5642 bce_init_tx_chain(struct bce_softc *sc) 5643 { 5644 struct tx_bd *txbd; 5645 int i, rc = 0; 5646 5647 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5648 5649 /* Set the initial TX producer/consumer indices. */ 5650 sc->tx_prod = 0; 5651 sc->tx_cons = 0; 5652 sc->tx_prod_bseq = 0; 5653 sc->used_tx_bd = 0; 5654 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5655 DBRUN(sc->tx_hi_watermark = 0); 5656 DBRUN(sc->tx_full_count = 0); 5657 5658 /* 5659 * The NetXtreme II supports a linked-list structre called 5660 * a Buffer Descriptor Chain (or BD chain). A BD chain 5661 * consists of a series of 1 or more chain pages, each of which 5662 * consists of a fixed number of BD entries. 5663 * The last BD entry on each page is a pointer to the next page 5664 * in the chain, and the last pointer in the BD chain 5665 * points back to the beginning of the chain. 5666 */ 5667 5668 /* Set the TX next pointer chain entries. */ 5669 for (i = 0; i < sc->tx_pages; i++) { 5670 int j; 5671 5672 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5673 5674 /* Check if we've reached the last page. */ 5675 if (i == (sc->tx_pages - 1)) 5676 j = 0; 5677 else 5678 j = i + 1; 5679 5680 txbd->tx_bd_haddr_hi = 5681 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5682 txbd->tx_bd_haddr_lo = 5683 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5684 } 5685 5686 bce_init_tx_context(sc); 5687 5688 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5689 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5690 5691 return(rc); 5692 } 5693 5694 5695 /****************************************************************************/ 5696 /* Free memory and clear the TX data structures. */ 5697 /* */ 5698 /* Returns: */ 5699 /* Nothing. */ 5700 /****************************************************************************/ 5701 static void 5702 bce_free_tx_chain(struct bce_softc *sc) 5703 { 5704 int i; 5705 5706 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5707 5708 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5709 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5710 if (sc->tx_mbuf_ptr[i] != NULL) { 5711 if (sc->tx_mbuf_map[i] != NULL) 5712 bus_dmamap_sync(sc->tx_mbuf_tag, 5713 sc->tx_mbuf_map[i], 5714 BUS_DMASYNC_POSTWRITE); 5715 m_freem(sc->tx_mbuf_ptr[i]); 5716 sc->tx_mbuf_ptr[i] = NULL; 5717 DBRUN(sc->debug_tx_mbuf_alloc--); 5718 } 5719 } 5720 5721 /* Clear each TX chain page. */ 5722 for (i = 0; i < sc->tx_pages; i++) 5723 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5724 5725 sc->used_tx_bd = 0; 5726 5727 /* Check if we lost any mbufs in the process. */ 5728 DBRUNIF((sc->debug_tx_mbuf_alloc), 5729 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5730 "from tx chain!\n", __FILE__, __LINE__, 5731 sc->debug_tx_mbuf_alloc)); 5732 5733 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5734 } 5735 5736 5737 /****************************************************************************/ 5738 /* Initialize the RX context memory. */ 5739 /* */ 5740 /* Returns: */ 5741 /* Nothing */ 5742 /****************************************************************************/ 5743 static void 5744 bce_init_rx_context(struct bce_softc *sc) 5745 { 5746 u32 val; 5747 5748 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5749 5750 /* Init the type, size, and BD cache levels for the RX context. */ 5751 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5752 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5753 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5754 5755 /* 5756 * Set the level for generating pause frames 5757 * when the number of available rx_bd's gets 5758 * too low (the low watermark) and the level 5759 * when pause frames can be stopped (the high 5760 * watermark). 5761 */ 5762 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5763 u32 lo_water, hi_water; 5764 5765 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5766 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5767 } else { 5768 lo_water = 0; 5769 } 5770 5771 if (lo_water >= USABLE_RX_BD_ALLOC) { 5772 lo_water = 0; 5773 } 5774 5775 hi_water = USABLE_RX_BD_ALLOC / 4; 5776 5777 if (hi_water <= lo_water) { 5778 lo_water = 0; 5779 } 5780 5781 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5782 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5783 5784 if (hi_water > 0xf) 5785 hi_water = 0xf; 5786 else if (hi_water == 0) 5787 lo_water = 0; 5788 5789 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5790 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5791 } 5792 5793 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5794 5795 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5796 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5797 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5798 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5799 } 5800 5801 /* Point the hardware to the first page in the chain. */ 5802 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5803 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5804 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5805 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5806 5807 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5808 } 5809 5810 5811 /****************************************************************************/ 5812 /* Allocate memory and initialize the RX data structures. */ 5813 /* */ 5814 /* Returns: */ 5815 /* 0 for success, positive value for failure. */ 5816 /****************************************************************************/ 5817 static int 5818 bce_init_rx_chain(struct bce_softc *sc) 5819 { 5820 struct rx_bd *rxbd; 5821 int i, rc = 0; 5822 5823 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5824 BCE_VERBOSE_CTX); 5825 5826 /* Initialize the RX producer and consumer indices. */ 5827 sc->rx_prod = 0; 5828 sc->rx_cons = 0; 5829 sc->rx_prod_bseq = 0; 5830 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5831 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5832 5833 /* Initialize the RX next pointer chain entries. */ 5834 for (i = 0; i < sc->rx_pages; i++) { 5835 int j; 5836 5837 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5838 5839 /* Check if we've reached the last page. */ 5840 if (i == (sc->rx_pages - 1)) 5841 j = 0; 5842 else 5843 j = i + 1; 5844 5845 /* Setup the chain page pointers. */ 5846 rxbd->rx_bd_haddr_hi = 5847 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5848 rxbd->rx_bd_haddr_lo = 5849 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5850 } 5851 5852 /* Fill up the RX chain. */ 5853 bce_fill_rx_chain(sc); 5854 5855 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5856 DBRUN(sc->rx_empty_count = 0); 5857 for (i = 0; i < sc->rx_pages; i++) { 5858 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5859 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5860 } 5861 5862 bce_init_rx_context(sc); 5863 5864 DBRUNMSG(BCE_EXTREME_RECV, 5865 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5866 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5867 BCE_VERBOSE_CTX); 5868 5869 /* ToDo: Are there possible failure modes here? */ 5870 5871 return(rc); 5872 } 5873 5874 5875 /****************************************************************************/ 5876 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5877 /* occurs. */ 5878 /* */ 5879 /* Returns: */ 5880 /* Nothing */ 5881 /****************************************************************************/ 5882 static void 5883 bce_fill_rx_chain(struct bce_softc *sc) 5884 { 5885 u16 prod, prod_idx; 5886 u32 prod_bseq; 5887 5888 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5889 BCE_VERBOSE_CTX); 5890 5891 /* Get the RX chain producer indices. */ 5892 prod = sc->rx_prod; 5893 prod_bseq = sc->rx_prod_bseq; 5894 5895 /* Keep filling the RX chain until it's full. */ 5896 while (sc->free_rx_bd > 0) { 5897 prod_idx = RX_CHAIN_IDX(prod); 5898 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) { 5899 /* Bail out if we can't add an mbuf to the chain. */ 5900 break; 5901 } 5902 prod = NEXT_RX_BD(prod); 5903 } 5904 5905 /* Save the RX chain producer indices. */ 5906 sc->rx_prod = prod; 5907 sc->rx_prod_bseq = prod_bseq; 5908 5909 /* We should never end up pointing to a next page pointer. */ 5910 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5911 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5912 __FUNCTION__, rx_prod)); 5913 5914 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5915 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod); 5916 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq); 5917 5918 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5919 BCE_VERBOSE_CTX); 5920 } 5921 5922 5923 /****************************************************************************/ 5924 /* Free memory and clear the RX data structures. */ 5925 /* */ 5926 /* Returns: */ 5927 /* Nothing. */ 5928 /****************************************************************************/ 5929 static void 5930 bce_free_rx_chain(struct bce_softc *sc) 5931 { 5932 int i; 5933 5934 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5935 5936 /* Free any mbufs still in the RX mbuf chain. */ 5937 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5938 if (sc->rx_mbuf_ptr[i] != NULL) { 5939 if (sc->rx_mbuf_map[i] != NULL) 5940 bus_dmamap_sync(sc->rx_mbuf_tag, 5941 sc->rx_mbuf_map[i], 5942 BUS_DMASYNC_POSTREAD); 5943 m_freem(sc->rx_mbuf_ptr[i]); 5944 sc->rx_mbuf_ptr[i] = NULL; 5945 DBRUN(sc->debug_rx_mbuf_alloc--); 5946 } 5947 } 5948 5949 /* Clear each RX chain page. */ 5950 for (i = 0; i < sc->rx_pages; i++) 5951 if (sc->rx_bd_chain[i] != NULL) 5952 bzero((char *)sc->rx_bd_chain[i], 5953 BCE_RX_CHAIN_PAGE_SZ); 5954 5955 sc->free_rx_bd = sc->max_rx_bd; 5956 5957 /* Check if we lost any mbufs in the process. */ 5958 DBRUNIF((sc->debug_rx_mbuf_alloc), 5959 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5960 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5961 5962 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5963 } 5964 5965 5966 /****************************************************************************/ 5967 /* Allocate memory and initialize the page data structures. */ 5968 /* Assumes that bce_init_rx_chain() has not already been called. */ 5969 /* */ 5970 /* Returns: */ 5971 /* 0 for success, positive value for failure. */ 5972 /****************************************************************************/ 5973 static int 5974 bce_init_pg_chain(struct bce_softc *sc) 5975 { 5976 struct rx_bd *pgbd; 5977 int i, rc = 0; 5978 u32 val; 5979 5980 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5981 BCE_VERBOSE_CTX); 5982 5983 /* Initialize the page producer and consumer indices. */ 5984 sc->pg_prod = 0; 5985 sc->pg_cons = 0; 5986 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5987 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5988 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5989 DBRUN(sc->pg_empty_count = 0); 5990 5991 /* Initialize the page next pointer chain entries. */ 5992 for (i = 0; i < sc->pg_pages; i++) { 5993 int j; 5994 5995 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5996 5997 /* Check if we've reached the last page. */ 5998 if (i == (sc->pg_pages - 1)) 5999 j = 0; 6000 else 6001 j = i + 1; 6002 6003 /* Setup the chain page pointers. */ 6004 pgbd->rx_bd_haddr_hi = 6005 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 6006 pgbd->rx_bd_haddr_lo = 6007 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 6008 } 6009 6010 /* Setup the MQ BIN mapping for host_pg_bidx. */ 6011 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 6012 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 6013 6014 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 6015 6016 /* Configure the rx_bd and page chain mbuf cluster size. */ 6017 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES; 6018 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 6019 6020 /* Configure the context reserved for jumbo support. */ 6021 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 6022 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 6023 6024 /* Point the hardware to the first page in the page chain. */ 6025 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 6026 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 6027 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 6028 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 6029 6030 /* Fill up the page chain. */ 6031 bce_fill_pg_chain(sc); 6032 6033 for (i = 0; i < sc->pg_pages; i++) { 6034 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 6035 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6036 } 6037 6038 DBRUNMSG(BCE_EXTREME_RECV, 6039 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 6040 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 6041 BCE_VERBOSE_CTX); 6042 return(rc); 6043 } 6044 6045 6046 /****************************************************************************/ 6047 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 6048 /* occurs. */ 6049 /* */ 6050 /* Returns: */ 6051 /* Nothing */ 6052 /****************************************************************************/ 6053 static void 6054 bce_fill_pg_chain(struct bce_softc *sc) 6055 { 6056 u16 prod, prod_idx; 6057 6058 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6059 BCE_VERBOSE_CTX); 6060 6061 /* Get the page chain prodcuer index. */ 6062 prod = sc->pg_prod; 6063 6064 /* Keep filling the page chain until it's full. */ 6065 while (sc->free_pg_bd > 0) { 6066 prod_idx = PG_CHAIN_IDX(prod); 6067 if (bce_get_pg_buf(sc, prod, prod_idx)) { 6068 /* Bail out if we can't add an mbuf to the chain. */ 6069 break; 6070 } 6071 prod = NEXT_PG_BD(prod); 6072 } 6073 6074 /* Save the page chain producer index. */ 6075 sc->pg_prod = prod; 6076 6077 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6078 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6079 __FUNCTION__, pg_prod)); 6080 6081 /* 6082 * Write the mailbox and tell the chip about 6083 * the new rx_bd's in the page chain. 6084 */ 6085 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX, 6086 prod); 6087 6088 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6089 BCE_VERBOSE_CTX); 6090 } 6091 6092 6093 /****************************************************************************/ 6094 /* Free memory and clear the RX data structures. */ 6095 /* */ 6096 /* Returns: */ 6097 /* Nothing. */ 6098 /****************************************************************************/ 6099 static void 6100 bce_free_pg_chain(struct bce_softc *sc) 6101 { 6102 int i; 6103 6104 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6105 6106 /* Free any mbufs still in the mbuf page chain. */ 6107 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6108 if (sc->pg_mbuf_ptr[i] != NULL) { 6109 if (sc->pg_mbuf_map[i] != NULL) 6110 bus_dmamap_sync(sc->pg_mbuf_tag, 6111 sc->pg_mbuf_map[i], 6112 BUS_DMASYNC_POSTREAD); 6113 m_freem(sc->pg_mbuf_ptr[i]); 6114 sc->pg_mbuf_ptr[i] = NULL; 6115 DBRUN(sc->debug_pg_mbuf_alloc--); 6116 } 6117 } 6118 6119 /* Clear each page chain pages. */ 6120 for (i = 0; i < sc->pg_pages; i++) 6121 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6122 6123 sc->free_pg_bd = sc->max_pg_bd; 6124 6125 /* Check if we lost any mbufs in the process. */ 6126 DBRUNIF((sc->debug_pg_mbuf_alloc), 6127 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6128 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6129 6130 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6131 } 6132 6133 6134 static u32 6135 bce_get_rphy_link(struct bce_softc *sc) 6136 { 6137 u32 advertise, link; 6138 int fdpx; 6139 6140 advertise = 0; 6141 fdpx = 0; 6142 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) 6143 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK); 6144 else 6145 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK); 6146 if (link & BCE_NETLINK_ANEG_ENB) 6147 advertise |= BCE_NETLINK_ANEG_ENB; 6148 if (link & BCE_NETLINK_SPEED_10HALF) 6149 advertise |= BCE_NETLINK_SPEED_10HALF; 6150 if (link & BCE_NETLINK_SPEED_10FULL) { 6151 advertise |= BCE_NETLINK_SPEED_10FULL; 6152 fdpx++; 6153 } 6154 if (link & BCE_NETLINK_SPEED_100HALF) 6155 advertise |= BCE_NETLINK_SPEED_100HALF; 6156 if (link & BCE_NETLINK_SPEED_100FULL) { 6157 advertise |= BCE_NETLINK_SPEED_100FULL; 6158 fdpx++; 6159 } 6160 if (link & BCE_NETLINK_SPEED_1000HALF) 6161 advertise |= BCE_NETLINK_SPEED_1000HALF; 6162 if (link & BCE_NETLINK_SPEED_1000FULL) { 6163 advertise |= BCE_NETLINK_SPEED_1000FULL; 6164 fdpx++; 6165 } 6166 if (link & BCE_NETLINK_SPEED_2500HALF) 6167 advertise |= BCE_NETLINK_SPEED_2500HALF; 6168 if (link & BCE_NETLINK_SPEED_2500FULL) { 6169 advertise |= BCE_NETLINK_SPEED_2500FULL; 6170 fdpx++; 6171 } 6172 if (fdpx) 6173 advertise |= BCE_NETLINK_FC_PAUSE_SYM | 6174 BCE_NETLINK_FC_PAUSE_ASYM; 6175 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6176 advertise |= BCE_NETLINK_PHY_APP_REMOTE | 6177 BCE_NETLINK_ETH_AT_WIRESPEED; 6178 6179 return (advertise); 6180 } 6181 6182 6183 /****************************************************************************/ 6184 /* Set media options. */ 6185 /* */ 6186 /* Returns: */ 6187 /* 0 for success, positive value for failure. */ 6188 /****************************************************************************/ 6189 static int 6190 bce_ifmedia_upd(struct ifnet *ifp) 6191 { 6192 struct bce_softc *sc = ifp->if_softc; 6193 int error; 6194 6195 DBENTER(BCE_VERBOSE); 6196 6197 BCE_LOCK(sc); 6198 error = bce_ifmedia_upd_locked(ifp); 6199 BCE_UNLOCK(sc); 6200 6201 DBEXIT(BCE_VERBOSE); 6202 return (error); 6203 } 6204 6205 6206 /****************************************************************************/ 6207 /* Set media options. */ 6208 /* */ 6209 /* Returns: */ 6210 /* Nothing. */ 6211 /****************************************************************************/ 6212 static int 6213 bce_ifmedia_upd_locked(struct ifnet *ifp) 6214 { 6215 struct bce_softc *sc = ifp->if_softc; 6216 struct mii_data *mii; 6217 struct mii_softc *miisc; 6218 struct ifmedia *ifm; 6219 u32 link; 6220 int error, fdx; 6221 6222 DBENTER(BCE_VERBOSE_PHY); 6223 6224 error = 0; 6225 BCE_LOCK_ASSERT(sc); 6226 6227 sc->bce_link_up = FALSE; 6228 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6229 ifm = &sc->bce_ifmedia; 6230 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 6231 return (EINVAL); 6232 link = 0; 6233 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX; 6234 switch(IFM_SUBTYPE(ifm->ifm_media)) { 6235 case IFM_AUTO: 6236 /* 6237 * Check advertised link of remote PHY by reading 6238 * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK. 6239 * Always use the same link type of remote PHY. 6240 */ 6241 link = bce_get_rphy_link(sc); 6242 break; 6243 case IFM_2500_SX: 6244 if ((sc->bce_phy_flags & 6245 (BCE_PHY_REMOTE_PORT_FIBER_FLAG | 6246 BCE_PHY_2_5G_CAPABLE_FLAG)) == 0) 6247 return (EINVAL); 6248 /* 6249 * XXX 6250 * Have to enable forced 2.5Gbps configuration. 6251 */ 6252 if (fdx != 0) 6253 link |= BCE_NETLINK_SPEED_2500FULL; 6254 else 6255 link |= BCE_NETLINK_SPEED_2500HALF; 6256 break; 6257 case IFM_1000_SX: 6258 if ((sc->bce_phy_flags & 6259 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6260 return (EINVAL); 6261 /* 6262 * XXX 6263 * Have to disable 2.5Gbps configuration. 6264 */ 6265 if (fdx != 0) 6266 link = BCE_NETLINK_SPEED_1000FULL; 6267 else 6268 link = BCE_NETLINK_SPEED_1000HALF; 6269 break; 6270 case IFM_1000_T: 6271 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6272 return (EINVAL); 6273 if (fdx != 0) 6274 link = BCE_NETLINK_SPEED_1000FULL; 6275 else 6276 link = BCE_NETLINK_SPEED_1000HALF; 6277 break; 6278 case IFM_100_TX: 6279 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6280 return (EINVAL); 6281 if (fdx != 0) 6282 link = BCE_NETLINK_SPEED_100FULL; 6283 else 6284 link = BCE_NETLINK_SPEED_100HALF; 6285 break; 6286 case IFM_10_T: 6287 if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) 6288 return (EINVAL); 6289 if (fdx != 0) 6290 link = BCE_NETLINK_SPEED_10FULL; 6291 else 6292 link = BCE_NETLINK_SPEED_10HALF; 6293 break; 6294 default: 6295 return (EINVAL); 6296 } 6297 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) { 6298 /* 6299 * XXX 6300 * Advertise pause capability for full-duplex media. 6301 */ 6302 if (fdx != 0) 6303 link |= BCE_NETLINK_FC_PAUSE_SYM | 6304 BCE_NETLINK_FC_PAUSE_ASYM; 6305 if ((sc->bce_phy_flags & 6306 BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6307 link |= BCE_NETLINK_PHY_APP_REMOTE | 6308 BCE_NETLINK_ETH_AT_WIRESPEED; 6309 } 6310 6311 bce_shmem_wr(sc, BCE_MB_ARGS_0, link); 6312 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK); 6313 } else { 6314 mii = device_get_softc(sc->bce_miibus); 6315 6316 /* Make sure the MII bus has been enumerated. */ 6317 if (mii) { 6318 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6319 PHY_RESET(miisc); 6320 error = mii_mediachg(mii); 6321 } 6322 } 6323 6324 DBEXIT(BCE_VERBOSE_PHY); 6325 return (error); 6326 } 6327 6328 6329 static void 6330 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr) 6331 { 6332 struct ifnet *ifp; 6333 u32 link; 6334 6335 ifp = sc->bce_ifp; 6336 BCE_LOCK_ASSERT(sc); 6337 6338 ifmr->ifm_status = IFM_AVALID; 6339 ifmr->ifm_active = IFM_ETHER; 6340 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 6341 /* XXX Handle heart beat status? */ 6342 if ((link & BCE_LINK_STATUS_LINK_UP) != 0) 6343 ifmr->ifm_status |= IFM_ACTIVE; 6344 else { 6345 ifmr->ifm_active |= IFM_NONE; 6346 ifp->if_baudrate = 0; 6347 return; 6348 } 6349 switch (link & BCE_LINK_STATUS_SPEED_MASK) { 6350 case BCE_LINK_STATUS_10HALF: 6351 ifmr->ifm_active |= IFM_10_T | IFM_HDX; 6352 ifp->if_baudrate = IF_Mbps(10UL); 6353 break; 6354 case BCE_LINK_STATUS_10FULL: 6355 ifmr->ifm_active |= IFM_10_T | IFM_FDX; 6356 ifp->if_baudrate = IF_Mbps(10UL); 6357 break; 6358 case BCE_LINK_STATUS_100HALF: 6359 ifmr->ifm_active |= IFM_100_TX | IFM_HDX; 6360 ifp->if_baudrate = IF_Mbps(100UL); 6361 break; 6362 case BCE_LINK_STATUS_100FULL: 6363 ifmr->ifm_active |= IFM_100_TX | IFM_FDX; 6364 ifp->if_baudrate = IF_Mbps(100UL); 6365 break; 6366 case BCE_LINK_STATUS_1000HALF: 6367 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6368 ifmr->ifm_active |= IFM_1000_T | IFM_HDX; 6369 else 6370 ifmr->ifm_active |= IFM_1000_SX | IFM_HDX; 6371 ifp->if_baudrate = IF_Mbps(1000UL); 6372 break; 6373 case BCE_LINK_STATUS_1000FULL: 6374 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) 6375 ifmr->ifm_active |= IFM_1000_T | IFM_FDX; 6376 else 6377 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX; 6378 ifp->if_baudrate = IF_Mbps(1000UL); 6379 break; 6380 case BCE_LINK_STATUS_2500HALF: 6381 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6382 ifmr->ifm_active |= IFM_NONE; 6383 return; 6384 } else 6385 ifmr->ifm_active |= IFM_2500_SX | IFM_HDX; 6386 ifp->if_baudrate = IF_Mbps(2500UL); 6387 break; 6388 case BCE_LINK_STATUS_2500FULL: 6389 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) { 6390 ifmr->ifm_active |= IFM_NONE; 6391 return; 6392 } else 6393 ifmr->ifm_active |= IFM_2500_SX | IFM_FDX; 6394 ifp->if_baudrate = IF_Mbps(2500UL); 6395 break; 6396 default: 6397 ifmr->ifm_active |= IFM_NONE; 6398 return; 6399 } 6400 6401 if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0) 6402 ifmr->ifm_active |= IFM_ETH_RXPAUSE; 6403 if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0) 6404 ifmr->ifm_active |= IFM_ETH_TXPAUSE; 6405 } 6406 6407 6408 /****************************************************************************/ 6409 /* Reports current media status. */ 6410 /* */ 6411 /* Returns: */ 6412 /* Nothing. */ 6413 /****************************************************************************/ 6414 static void 6415 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6416 { 6417 struct bce_softc *sc = ifp->if_softc; 6418 struct mii_data *mii; 6419 6420 DBENTER(BCE_VERBOSE_PHY); 6421 6422 BCE_LOCK(sc); 6423 6424 if ((ifp->if_flags & IFF_UP) == 0) { 6425 BCE_UNLOCK(sc); 6426 return; 6427 } 6428 6429 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 6430 bce_ifmedia_sts_rphy(sc, ifmr); 6431 else { 6432 mii = device_get_softc(sc->bce_miibus); 6433 mii_pollstat(mii); 6434 ifmr->ifm_active = mii->mii_media_active; 6435 ifmr->ifm_status = mii->mii_media_status; 6436 } 6437 6438 BCE_UNLOCK(sc); 6439 6440 DBEXIT(BCE_VERBOSE_PHY); 6441 } 6442 6443 6444 /****************************************************************************/ 6445 /* Handles PHY generated interrupt events. */ 6446 /* */ 6447 /* Returns: */ 6448 /* Nothing. */ 6449 /****************************************************************************/ 6450 static void 6451 bce_phy_intr(struct bce_softc *sc) 6452 { 6453 u32 new_link_state, old_link_state; 6454 6455 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6456 6457 DBRUN(sc->phy_interrupts++); 6458 6459 new_link_state = sc->status_block->status_attn_bits & 6460 STATUS_ATTN_BITS_LINK_STATE; 6461 old_link_state = sc->status_block->status_attn_bits_ack & 6462 STATUS_ATTN_BITS_LINK_STATE; 6463 6464 /* Handle any changes if the link state has changed. */ 6465 if (new_link_state != old_link_state) { 6466 6467 /* Update the status_attn_bits_ack field. */ 6468 if (new_link_state) { 6469 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6470 STATUS_ATTN_BITS_LINK_STATE); 6471 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6472 __FUNCTION__); 6473 } else { 6474 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6475 STATUS_ATTN_BITS_LINK_STATE); 6476 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6477 __FUNCTION__); 6478 } 6479 6480 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 6481 if (new_link_state) { 6482 if (bootverbose) 6483 if_printf(sc->bce_ifp, "link UP\n"); 6484 if_link_state_change(sc->bce_ifp, 6485 LINK_STATE_UP); 6486 } else { 6487 if (bootverbose) 6488 if_printf(sc->bce_ifp, "link DOWN\n"); 6489 if_link_state_change(sc->bce_ifp, 6490 LINK_STATE_DOWN); 6491 } 6492 } 6493 /* 6494 * Assume link is down and allow 6495 * tick routine to update the state 6496 * based on the actual media state. 6497 */ 6498 sc->bce_link_up = FALSE; 6499 callout_stop(&sc->bce_tick_callout); 6500 bce_tick(sc); 6501 } 6502 6503 /* Acknowledge the link change interrupt. */ 6504 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6505 6506 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6507 } 6508 6509 6510 /****************************************************************************/ 6511 /* Reads the receive consumer value from the status block (skipping over */ 6512 /* chain page pointer if necessary). */ 6513 /* */ 6514 /* Returns: */ 6515 /* hw_cons */ 6516 /****************************************************************************/ 6517 static inline u16 6518 bce_get_hw_rx_cons(struct bce_softc *sc) 6519 { 6520 u16 hw_cons; 6521 6522 rmb(); 6523 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6524 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6525 hw_cons++; 6526 6527 return hw_cons; 6528 } 6529 6530 /****************************************************************************/ 6531 /* Handles received frame interrupt events. */ 6532 /* */ 6533 /* Returns: */ 6534 /* Nothing. */ 6535 /****************************************************************************/ 6536 static void 6537 bce_rx_intr(struct bce_softc *sc) 6538 { 6539 struct ifnet *ifp = sc->bce_ifp; 6540 struct l2_fhdr *l2fhdr; 6541 struct ether_vlan_header *vh; 6542 unsigned int pkt_len; 6543 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6544 u32 status; 6545 unsigned int rem_len; 6546 u16 sw_pg_cons, sw_pg_cons_idx; 6547 6548 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6549 DBRUN(sc->interrupts_rx++); 6550 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6551 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6552 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6553 6554 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6555 for (int i = 0; i < sc->rx_pages; i++) 6556 bus_dmamap_sync(sc->rx_bd_chain_tag, 6557 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6558 6559 /* Prepare the page chain pages to be accessed by the host CPU. */ 6560 if (bce_hdr_split == TRUE) { 6561 for (int i = 0; i < sc->pg_pages; i++) 6562 bus_dmamap_sync(sc->pg_bd_chain_tag, 6563 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6564 } 6565 6566 /* Get the hardware's view of the RX consumer index. */ 6567 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6568 6569 /* Get working copies of the driver's view of the consumer indices. */ 6570 sw_rx_cons = sc->rx_cons; 6571 sw_pg_cons = sc->pg_cons; 6572 6573 /* Update some debug statistics counters */ 6574 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6575 sc->rx_low_watermark = sc->free_rx_bd); 6576 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6577 sc->rx_empty_count++); 6578 6579 /* Scan through the receive chain as long as there is work to do */ 6580 /* ToDo: Consider setting a limit on the number of packets processed. */ 6581 rmb(); 6582 while (sw_rx_cons != hw_rx_cons) { 6583 struct mbuf *m0; 6584 6585 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6586 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6587 6588 /* Unmap the mbuf from DMA space. */ 6589 bus_dmamap_sync(sc->rx_mbuf_tag, 6590 sc->rx_mbuf_map[sw_rx_cons_idx], 6591 BUS_DMASYNC_POSTREAD); 6592 bus_dmamap_unload(sc->rx_mbuf_tag, 6593 sc->rx_mbuf_map[sw_rx_cons_idx]); 6594 6595 /* Remove the mbuf from the RX chain. */ 6596 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6597 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6598 DBRUN(sc->debug_rx_mbuf_alloc--); 6599 sc->free_rx_bd++; 6600 6601 /* 6602 * Frames received on the NetXteme II are prepended 6603 * with an l2_fhdr structure which provides status 6604 * information about the received frame (including 6605 * VLAN tags and checksum info). The frames are 6606 * also automatically adjusted to word align the IP 6607 * header (i.e. two null bytes are inserted before 6608 * the Ethernet header). As a result the data 6609 * DMA'd by the controller into the mbuf looks 6610 * like this: 6611 * 6612 * +---------+-----+---------------------+-----+ 6613 * | l2_fhdr | pad | packet data | FCS | 6614 * +---------+-----+---------------------+-----+ 6615 * 6616 * The l2_fhdr needs to be checked and skipped and 6617 * the FCS needs to be stripped before sending the 6618 * packet up the stack. 6619 */ 6620 l2fhdr = mtod(m0, struct l2_fhdr *); 6621 6622 /* Get the packet data + FCS length and the status. */ 6623 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6624 status = l2fhdr->l2_fhdr_status; 6625 6626 /* 6627 * Skip over the l2_fhdr and pad, resulting in the 6628 * following data in the mbuf: 6629 * +---------------------+-----+ 6630 * | packet data | FCS | 6631 * +---------------------+-----+ 6632 */ 6633 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6634 6635 /* 6636 * When split header mode is used, an ethernet frame 6637 * may be split across the receive chain and the 6638 * page chain. If that occurs an mbuf cluster must be 6639 * reassembled from the individual mbuf pieces. 6640 */ 6641 if (bce_hdr_split == TRUE) { 6642 /* 6643 * Check whether the received frame fits in a single 6644 * mbuf or not (i.e. packet data + FCS <= 6645 * sc->rx_bd_mbuf_data_len bytes). 6646 */ 6647 if (pkt_len > m0->m_len) { 6648 /* 6649 * The received frame is larger than a single mbuf. 6650 * If the frame was a TCP frame then only the TCP 6651 * header is placed in the mbuf, the remaining 6652 * payload (including FCS) is placed in the page 6653 * chain, the SPLIT flag is set, and the header 6654 * length is placed in the IP checksum field. 6655 * If the frame is not a TCP frame then the mbuf 6656 * is filled and the remaining bytes are placed 6657 * in the page chain. 6658 */ 6659 6660 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6661 "packet.\n", __FUNCTION__); 6662 DBRUN(sc->split_header_frames_rcvd++); 6663 6664 /* 6665 * When the page chain is enabled and the TCP 6666 * header has been split from the TCP payload, 6667 * the ip_xsum structure will reflect the length 6668 * of the TCP header, not the IP checksum. Set 6669 * the packet length of the mbuf accordingly. 6670 */ 6671 if (status & L2_FHDR_STATUS_SPLIT) { 6672 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6673 DBRUN(sc->split_header_tcp_frames_rcvd++); 6674 } 6675 6676 rem_len = pkt_len - m0->m_len; 6677 6678 /* Pull mbufs off the page chain for any remaining data. */ 6679 while (rem_len > 0) { 6680 struct mbuf *m_pg; 6681 6682 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6683 6684 /* Remove the mbuf from the page chain. */ 6685 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6686 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6687 DBRUN(sc->debug_pg_mbuf_alloc--); 6688 sc->free_pg_bd++; 6689 6690 /* Unmap the page chain mbuf from DMA space. */ 6691 bus_dmamap_sync(sc->pg_mbuf_tag, 6692 sc->pg_mbuf_map[sw_pg_cons_idx], 6693 BUS_DMASYNC_POSTREAD); 6694 bus_dmamap_unload(sc->pg_mbuf_tag, 6695 sc->pg_mbuf_map[sw_pg_cons_idx]); 6696 6697 /* Adjust the mbuf length. */ 6698 if (rem_len < m_pg->m_len) { 6699 /* The mbuf chain is complete. */ 6700 m_pg->m_len = rem_len; 6701 rem_len = 0; 6702 } else { 6703 /* More packet data is waiting. */ 6704 rem_len -= m_pg->m_len; 6705 } 6706 6707 /* Concatenate the mbuf cluster to the mbuf. */ 6708 m_cat(m0, m_pg); 6709 6710 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6711 } 6712 6713 /* Set the total packet length. */ 6714 m0->m_pkthdr.len = pkt_len; 6715 6716 } else { 6717 /* 6718 * The received packet is small and fits in a 6719 * single mbuf (i.e. the l2_fhdr + pad + packet + 6720 * FCS <= MHLEN). In other words, the packet is 6721 * 154 bytes or less in size. 6722 */ 6723 6724 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6725 "packet.\n", __FUNCTION__); 6726 6727 /* Set the total packet length. */ 6728 m0->m_pkthdr.len = m0->m_len = pkt_len; 6729 } 6730 } else 6731 /* Set the total packet length. */ 6732 m0->m_pkthdr.len = m0->m_len = pkt_len; 6733 6734 /* Remove the trailing Ethernet FCS. */ 6735 m_adj(m0, -ETHER_CRC_LEN); 6736 6737 /* Check that the resulting mbuf chain is valid. */ 6738 DBRUN(m_sanity(m0, FALSE)); 6739 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6740 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6741 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6742 m_print(m0, 128)); 6743 6744 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6745 sc->l2fhdr_error_sim_count++; 6746 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6747 6748 /* Check the received frame for errors. */ 6749 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6750 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6751 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6752 6753 /* Log the error and release the mbuf. */ 6754 sc->l2fhdr_error_count++; 6755 m_freem(m0); 6756 m0 = NULL; 6757 goto bce_rx_intr_next_rx; 6758 } 6759 6760 /* Send the packet to the appropriate interface. */ 6761 m0->m_pkthdr.rcvif = ifp; 6762 6763 /* Assume no hardware checksum. */ 6764 m0->m_pkthdr.csum_flags = 0; 6765 6766 /* Validate the checksum if offload enabled. */ 6767 if (ifp->if_capenable & IFCAP_RXCSUM) { 6768 /* Check for an IP datagram. */ 6769 if (!(status & L2_FHDR_STATUS_SPLIT) && 6770 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6771 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6772 DBRUN(sc->csum_offload_ip++); 6773 /* Check if the IP checksum is valid. */ 6774 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6775 m0->m_pkthdr.csum_flags |= 6776 CSUM_IP_VALID; 6777 } 6778 6779 /* Check for a valid TCP/UDP frame. */ 6780 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6781 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6782 6783 /* Check for a good TCP/UDP checksum. */ 6784 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6785 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6786 DBRUN(sc->csum_offload_tcp_udp++); 6787 m0->m_pkthdr.csum_data = 6788 l2fhdr->l2_fhdr_tcp_udp_xsum; 6789 m0->m_pkthdr.csum_flags |= 6790 (CSUM_DATA_VALID 6791 | CSUM_PSEUDO_HDR); 6792 } 6793 } 6794 } 6795 6796 /* Attach the VLAN tag. */ 6797 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && 6798 !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) { 6799 DBRUN(sc->vlan_tagged_frames_rcvd++); 6800 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6801 DBRUN(sc->vlan_tagged_frames_stripped++); 6802 #if __FreeBSD_version < 700000 6803 VLAN_INPUT_TAG(ifp, m0, 6804 l2fhdr->l2_fhdr_vlan_tag, continue); 6805 #else 6806 m0->m_pkthdr.ether_vtag = 6807 l2fhdr->l2_fhdr_vlan_tag; 6808 m0->m_flags |= M_VLANTAG; 6809 #endif 6810 } else { 6811 /* 6812 * bce(4) controllers can't disable VLAN 6813 * tag stripping if management firmware 6814 * (ASF/IPMI/UMP) is running. So we always 6815 * strip VLAN tag and manually reconstruct 6816 * the VLAN frame by appending stripped 6817 * VLAN tag in driver if VLAN tag stripping 6818 * was disabled. 6819 * 6820 * TODO: LLC SNAP handling. 6821 */ 6822 bcopy(mtod(m0, uint8_t *), 6823 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6824 ETHER_ADDR_LEN * 2); 6825 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6826 vh = mtod(m0, struct ether_vlan_header *); 6827 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6828 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6829 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6830 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6831 } 6832 } 6833 6834 /* Increment received packet statistics. */ 6835 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 6836 6837 bce_rx_intr_next_rx: 6838 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6839 6840 /* If we have a packet, pass it up the stack */ 6841 if (m0) { 6842 /* Make sure we don't lose our place when we release the lock. */ 6843 sc->rx_cons = sw_rx_cons; 6844 sc->pg_cons = sw_pg_cons; 6845 6846 BCE_UNLOCK(sc); 6847 (*ifp->if_input)(ifp, m0); 6848 BCE_LOCK(sc); 6849 6850 /* Recover our place. */ 6851 sw_rx_cons = sc->rx_cons; 6852 sw_pg_cons = sc->pg_cons; 6853 } 6854 6855 /* Refresh hw_cons to see if there's new work */ 6856 if (sw_rx_cons == hw_rx_cons) 6857 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6858 } 6859 6860 /* No new packets. Refill the page chain. */ 6861 if (bce_hdr_split == TRUE) { 6862 sc->pg_cons = sw_pg_cons; 6863 bce_fill_pg_chain(sc); 6864 } 6865 6866 /* No new packets. Refill the RX chain. */ 6867 sc->rx_cons = sw_rx_cons; 6868 bce_fill_rx_chain(sc); 6869 6870 /* Prepare the page chain pages to be accessed by the NIC. */ 6871 for (int i = 0; i < sc->rx_pages; i++) 6872 bus_dmamap_sync(sc->rx_bd_chain_tag, 6873 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6874 6875 if (bce_hdr_split == TRUE) { 6876 for (int i = 0; i < sc->pg_pages; i++) 6877 bus_dmamap_sync(sc->pg_bd_chain_tag, 6878 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6879 } 6880 6881 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6882 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6883 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6884 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6885 } 6886 6887 6888 /****************************************************************************/ 6889 /* Reads the transmit consumer value from the status block (skipping over */ 6890 /* chain page pointer if necessary). */ 6891 /* */ 6892 /* Returns: */ 6893 /* hw_cons */ 6894 /****************************************************************************/ 6895 static inline u16 6896 bce_get_hw_tx_cons(struct bce_softc *sc) 6897 { 6898 u16 hw_cons; 6899 6900 mb(); 6901 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6902 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6903 hw_cons++; 6904 6905 return hw_cons; 6906 } 6907 6908 6909 /****************************************************************************/ 6910 /* Handles transmit completion interrupt events. */ 6911 /* */ 6912 /* Returns: */ 6913 /* Nothing. */ 6914 /****************************************************************************/ 6915 static void 6916 bce_tx_intr(struct bce_softc *sc) 6917 { 6918 struct ifnet *ifp = sc->bce_ifp; 6919 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6920 6921 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6922 DBRUN(sc->interrupts_tx++); 6923 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6924 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6925 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6926 6927 BCE_LOCK_ASSERT(sc); 6928 6929 /* Get the hardware's view of the TX consumer index. */ 6930 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6931 sw_tx_cons = sc->tx_cons; 6932 6933 /* Prevent speculative reads of the status block. */ 6934 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6935 BUS_SPACE_BARRIER_READ); 6936 6937 /* Cycle through any completed TX chain page entries. */ 6938 while (sw_tx_cons != hw_tx_cons) { 6939 #ifdef BCE_DEBUG 6940 struct tx_bd *txbd = NULL; 6941 #endif 6942 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6943 6944 DBPRINT(sc, BCE_INFO_SEND, 6945 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6946 "sw_tx_chain_cons = 0x%04X\n", 6947 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6948 6949 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6950 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6951 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6952 (int) MAX_TX_BD_ALLOC); 6953 bce_breakpoint(sc)); 6954 6955 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6956 [TX_IDX(sw_tx_chain_cons)]); 6957 6958 DBRUNIF((txbd == NULL), 6959 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6960 __FILE__, __LINE__, sw_tx_chain_cons); 6961 bce_breakpoint(sc)); 6962 6963 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6964 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6965 6966 /* 6967 * Free the associated mbuf. Remember 6968 * that only the last tx_bd of a packet 6969 * has an mbuf pointer and DMA map. 6970 */ 6971 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6972 6973 /* Validate that this is the last tx_bd. */ 6974 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6975 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6976 "txmbuf == NULL!\n", __FILE__, __LINE__); 6977 bce_breakpoint(sc)); 6978 6979 DBRUNMSG(BCE_INFO_SEND, 6980 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6981 "from tx_bd[0x%04X]\n", __FUNCTION__, 6982 sw_tx_chain_cons)); 6983 6984 /* Unmap the mbuf. */ 6985 bus_dmamap_unload(sc->tx_mbuf_tag, 6986 sc->tx_mbuf_map[sw_tx_chain_cons]); 6987 6988 /* Free the mbuf. */ 6989 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6990 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6991 DBRUN(sc->debug_tx_mbuf_alloc--); 6992 6993 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 6994 } 6995 6996 sc->used_tx_bd--; 6997 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6998 6999 /* Refresh hw_cons to see if there's new work. */ 7000 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 7001 7002 /* Prevent speculative reads of the status block. */ 7003 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7004 BUS_SPACE_BARRIER_READ); 7005 } 7006 7007 /* Clear the TX timeout timer. */ 7008 sc->watchdog_timer = 0; 7009 7010 /* Clear the tx hardware queue full flag. */ 7011 if (sc->used_tx_bd < sc->max_tx_bd) { 7012 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 7013 DBPRINT(sc, BCE_INFO_SEND, 7014 "%s(): Open TX chain! %d/%d (used/total)\n", 7015 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 7016 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7017 } 7018 7019 sc->tx_cons = sw_tx_cons; 7020 7021 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 7022 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 7023 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 7024 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 7025 } 7026 7027 7028 /****************************************************************************/ 7029 /* Disables interrupt generation. */ 7030 /* */ 7031 /* Returns: */ 7032 /* Nothing. */ 7033 /****************************************************************************/ 7034 static void 7035 bce_disable_intr(struct bce_softc *sc) 7036 { 7037 DBENTER(BCE_VERBOSE_INTR); 7038 7039 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7040 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 7041 7042 DBEXIT(BCE_VERBOSE_INTR); 7043 } 7044 7045 7046 /****************************************************************************/ 7047 /* Enables interrupt generation. */ 7048 /* */ 7049 /* Returns: */ 7050 /* Nothing. */ 7051 /****************************************************************************/ 7052 static void 7053 bce_enable_intr(struct bce_softc *sc, int coal_now) 7054 { 7055 DBENTER(BCE_VERBOSE_INTR); 7056 7057 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7058 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 7059 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 7060 7061 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7062 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 7063 7064 /* Force an immediate interrupt (whether there is new data or not). */ 7065 if (coal_now) 7066 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 7067 7068 DBEXIT(BCE_VERBOSE_INTR); 7069 } 7070 7071 7072 /****************************************************************************/ 7073 /* Handles controller initialization. */ 7074 /* */ 7075 /* Returns: */ 7076 /* Nothing. */ 7077 /****************************************************************************/ 7078 static void 7079 bce_init_locked(struct bce_softc *sc) 7080 { 7081 struct ifnet *ifp; 7082 u32 ether_mtu = 0; 7083 7084 DBENTER(BCE_VERBOSE_RESET); 7085 7086 BCE_LOCK_ASSERT(sc); 7087 7088 ifp = sc->bce_ifp; 7089 7090 /* Check if the driver is still running and bail out if it is. */ 7091 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7092 goto bce_init_locked_exit; 7093 7094 bce_stop(sc); 7095 7096 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 7097 BCE_PRINTF("%s(%d): Controller reset failed!\n", 7098 __FILE__, __LINE__); 7099 goto bce_init_locked_exit; 7100 } 7101 7102 if (bce_chipinit(sc)) { 7103 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 7104 __FILE__, __LINE__); 7105 goto bce_init_locked_exit; 7106 } 7107 7108 if (bce_blockinit(sc)) { 7109 BCE_PRINTF("%s(%d): Block initialization failed!\n", 7110 __FILE__, __LINE__); 7111 goto bce_init_locked_exit; 7112 } 7113 7114 /* Load our MAC address. */ 7115 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 7116 bce_set_mac_addr(sc); 7117 7118 if (bce_hdr_split == FALSE) 7119 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7120 /* 7121 * Calculate and program the hardware Ethernet MTU 7122 * size. Be generous on the receive if we have room 7123 * and allowed by the user. 7124 */ 7125 if (bce_strict_rx_mtu == TRUE) 7126 ether_mtu = ifp->if_mtu; 7127 else { 7128 if (bce_hdr_split == TRUE) { 7129 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES) 7130 ether_mtu = sc->rx_bd_mbuf_data_len + 7131 MCLBYTES; 7132 else 7133 ether_mtu = ifp->if_mtu; 7134 } else { 7135 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 7136 ether_mtu = sc->rx_bd_mbuf_data_len; 7137 else 7138 ether_mtu = ifp->if_mtu; 7139 } 7140 } 7141 7142 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 7143 7144 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 7145 __FUNCTION__, ether_mtu); 7146 7147 /* Program the mtu, enabling jumbo frame support if necessary. */ 7148 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 7149 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 7150 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 7151 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 7152 else 7153 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 7154 7155 /* Program appropriate promiscuous/multicast filtering. */ 7156 bce_set_rx_mode(sc); 7157 7158 if (bce_hdr_split == TRUE) { 7159 /* Init page buffer descriptor chain. */ 7160 bce_init_pg_chain(sc); 7161 } 7162 7163 /* Init RX buffer descriptor chain. */ 7164 bce_init_rx_chain(sc); 7165 7166 /* Init TX buffer descriptor chain. */ 7167 bce_init_tx_chain(sc); 7168 7169 /* Enable host interrupts. */ 7170 bce_enable_intr(sc, 1); 7171 7172 bce_ifmedia_upd_locked(ifp); 7173 7174 /* Let the OS know the driver is up and running. */ 7175 ifp->if_drv_flags |= IFF_DRV_RUNNING; 7176 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 7177 7178 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 7179 7180 bce_init_locked_exit: 7181 DBEXIT(BCE_VERBOSE_RESET); 7182 } 7183 7184 7185 /****************************************************************************/ 7186 /* Initialize the controller just enough so that any management firmware */ 7187 /* running on the device will continue to operate correctly. */ 7188 /* */ 7189 /* Returns: */ 7190 /* Nothing. */ 7191 /****************************************************************************/ 7192 static void 7193 bce_mgmt_init_locked(struct bce_softc *sc) 7194 { 7195 struct ifnet *ifp; 7196 7197 DBENTER(BCE_VERBOSE_RESET); 7198 7199 BCE_LOCK_ASSERT(sc); 7200 7201 /* Bail out if management firmware is not running. */ 7202 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 7203 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 7204 "No management firmware running...\n"); 7205 goto bce_mgmt_init_locked_exit; 7206 } 7207 7208 ifp = sc->bce_ifp; 7209 7210 /* Enable all critical blocks in the MAC. */ 7211 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 7212 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 7213 DELAY(20); 7214 7215 bce_ifmedia_upd_locked(ifp); 7216 7217 bce_mgmt_init_locked_exit: 7218 DBEXIT(BCE_VERBOSE_RESET); 7219 } 7220 7221 7222 /****************************************************************************/ 7223 /* Handles controller initialization when called from an unlocked routine. */ 7224 /* */ 7225 /* Returns: */ 7226 /* Nothing. */ 7227 /****************************************************************************/ 7228 static void 7229 bce_init(void *xsc) 7230 { 7231 struct bce_softc *sc = xsc; 7232 7233 DBENTER(BCE_VERBOSE_RESET); 7234 7235 BCE_LOCK(sc); 7236 bce_init_locked(sc); 7237 BCE_UNLOCK(sc); 7238 7239 DBEXIT(BCE_VERBOSE_RESET); 7240 } 7241 7242 7243 /****************************************************************************/ 7244 /* Modifies an mbuf for TSO on the hardware. */ 7245 /* */ 7246 /* Returns: */ 7247 /* Pointer to a modified mbuf. */ 7248 /****************************************************************************/ 7249 static struct mbuf * 7250 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 7251 { 7252 struct mbuf *m; 7253 struct ether_header *eh; 7254 struct ip *ip; 7255 struct tcphdr *th; 7256 u16 etype; 7257 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 7258 7259 DBRUN(sc->tso_frames_requested++); 7260 7261 /* Controller may modify mbuf chains. */ 7262 if (M_WRITABLE(*m_head) == 0) { 7263 m = m_dup(*m_head, M_NOWAIT); 7264 m_freem(*m_head); 7265 if (m == NULL) { 7266 sc->mbuf_alloc_failed_count++; 7267 *m_head = NULL; 7268 return (NULL); 7269 } 7270 *m_head = m; 7271 } 7272 7273 /* 7274 * For TSO the controller needs two pieces of info, 7275 * the MSS and the IP+TCP options length. 7276 */ 7277 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7278 if (m == NULL) { 7279 *m_head = NULL; 7280 return (NULL); 7281 } 7282 eh = mtod(m, struct ether_header *); 7283 etype = ntohs(eh->ether_type); 7284 7285 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7286 switch (etype) { 7287 case ETHERTYPE_IP: 7288 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7289 /* TSO only supported for TCP protocol. */ 7290 if (ip->ip_p != IPPROTO_TCP) { 7291 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7292 __FILE__, __LINE__); 7293 m_freem(*m_head); 7294 *m_head = NULL; 7295 return (NULL); 7296 } 7297 7298 /* Get IP header length in bytes (min 20) */ 7299 ip_hlen = ip->ip_hl << 2; 7300 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7301 sizeof(struct tcphdr)); 7302 if (m == NULL) { 7303 *m_head = NULL; 7304 return (NULL); 7305 } 7306 7307 /* Get the TCP header length in bytes (min 20) */ 7308 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7309 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7310 tcp_hlen = (th->th_off << 2); 7311 7312 /* Make sure all IP/TCP options live in the same buffer. */ 7313 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7314 tcp_hlen); 7315 if (m == NULL) { 7316 *m_head = NULL; 7317 return (NULL); 7318 } 7319 7320 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7321 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7322 ip_len = ip->ip_len; 7323 ip->ip_len = 0; 7324 ip->ip_sum = 0; 7325 break; 7326 case ETHERTYPE_IPV6: 7327 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7328 __FILE__, __LINE__); 7329 m_freem(*m_head); 7330 *m_head = NULL; 7331 return (NULL); 7332 /* NOT REACHED */ 7333 default: 7334 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7335 __FILE__, __LINE__); 7336 m_freem(*m_head); 7337 *m_head = NULL; 7338 return (NULL); 7339 } 7340 7341 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7342 7343 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7344 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7345 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7346 tcp_hlen, ip_len); 7347 7348 /* Set the LSO flag in the TX BD */ 7349 *flags |= TX_BD_FLAGS_SW_LSO; 7350 7351 /* Set the length of IP + TCP options (in 32 bit words) */ 7352 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7353 sizeof(struct tcphdr)) >> 2) << 8); 7354 7355 DBRUN(sc->tso_frames_completed++); 7356 return (*m_head); 7357 } 7358 7359 7360 /****************************************************************************/ 7361 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7362 /* memory visible to the controller. */ 7363 /* */ 7364 /* Returns: */ 7365 /* 0 for success, positive value for failure. */ 7366 /* Modified: */ 7367 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7368 /****************************************************************************/ 7369 static int 7370 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7371 { 7372 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7373 bus_dmamap_t map; 7374 struct tx_bd *txbd = NULL; 7375 struct mbuf *m0; 7376 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7377 u32 prod_bseq; 7378 7379 #ifdef BCE_DEBUG 7380 u16 debug_prod; 7381 #endif 7382 7383 int i, error, nsegs, rc = 0; 7384 7385 DBENTER(BCE_VERBOSE_SEND); 7386 7387 /* Make sure we have room in the TX chain. */ 7388 if (sc->used_tx_bd >= sc->max_tx_bd) 7389 goto bce_tx_encap_exit; 7390 7391 /* Transfer any checksum offload flags to the bd. */ 7392 m0 = *m_head; 7393 if (m0->m_pkthdr.csum_flags) { 7394 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7395 m0 = bce_tso_setup(sc, m_head, &flags); 7396 if (m0 == NULL) { 7397 DBRUN(sc->tso_frames_failed++); 7398 goto bce_tx_encap_exit; 7399 } 7400 mss = htole16(m0->m_pkthdr.tso_segsz); 7401 } else { 7402 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7403 flags |= TX_BD_FLAGS_IP_CKSUM; 7404 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7405 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7406 } 7407 } 7408 7409 /* Transfer any VLAN tags to the bd. */ 7410 if (m0->m_flags & M_VLANTAG) { 7411 flags |= TX_BD_FLAGS_VLAN_TAG; 7412 vlan_tag = m0->m_pkthdr.ether_vtag; 7413 } 7414 7415 /* Map the mbuf into DMAable memory. */ 7416 prod = sc->tx_prod; 7417 chain_prod = TX_CHAIN_IDX(prod); 7418 map = sc->tx_mbuf_map[chain_prod]; 7419 7420 /* Map the mbuf into our DMA address space. */ 7421 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7422 segs, &nsegs, BUS_DMA_NOWAIT); 7423 7424 /* Check if the DMA mapping was successful */ 7425 if (error == EFBIG) { 7426 sc->mbuf_frag_count++; 7427 7428 /* Try to defrag the mbuf. */ 7429 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS); 7430 if (m0 == NULL) { 7431 /* Defrag was unsuccessful */ 7432 m_freem(*m_head); 7433 *m_head = NULL; 7434 sc->mbuf_alloc_failed_count++; 7435 rc = ENOBUFS; 7436 goto bce_tx_encap_exit; 7437 } 7438 7439 /* Defrag was successful, try mapping again */ 7440 *m_head = m0; 7441 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7442 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7443 7444 /* Still getting an error after a defrag. */ 7445 if (error == ENOMEM) { 7446 /* Insufficient DMA buffers available. */ 7447 sc->dma_map_addr_tx_failed_count++; 7448 rc = error; 7449 goto bce_tx_encap_exit; 7450 } else if (error != 0) { 7451 /* Release it and return an error. */ 7452 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7453 "TX chain!\n", __FILE__, __LINE__); 7454 m_freem(m0); 7455 *m_head = NULL; 7456 sc->dma_map_addr_tx_failed_count++; 7457 rc = ENOBUFS; 7458 goto bce_tx_encap_exit; 7459 } 7460 } else if (error == ENOMEM) { 7461 /* Insufficient DMA buffers available. */ 7462 sc->dma_map_addr_tx_failed_count++; 7463 rc = error; 7464 goto bce_tx_encap_exit; 7465 } else if (error != 0) { 7466 m_freem(m0); 7467 *m_head = NULL; 7468 sc->dma_map_addr_tx_failed_count++; 7469 rc = error; 7470 goto bce_tx_encap_exit; 7471 } 7472 7473 /* Make sure there's room in the chain */ 7474 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7475 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7476 rc = ENOBUFS; 7477 goto bce_tx_encap_exit; 7478 } 7479 7480 /* prod points to an empty tx_bd at this point. */ 7481 prod_bseq = sc->tx_prod_bseq; 7482 7483 #ifdef BCE_DEBUG 7484 debug_prod = chain_prod; 7485 #endif 7486 7487 DBPRINT(sc, BCE_INFO_SEND, 7488 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7489 "prod_bseq = 0x%08X\n", 7490 __FUNCTION__, prod, chain_prod, prod_bseq); 7491 7492 /* 7493 * Cycle through each mbuf segment that makes up 7494 * the outgoing frame, gathering the mapping info 7495 * for that segment and creating a tx_bd for 7496 * the mbuf. 7497 */ 7498 for (i = 0; i < nsegs ; i++) { 7499 7500 chain_prod = TX_CHAIN_IDX(prod); 7501 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7502 [TX_IDX(chain_prod)]; 7503 7504 txbd->tx_bd_haddr_lo = 7505 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7506 txbd->tx_bd_haddr_hi = 7507 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7508 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7509 htole16(segs[i].ds_len); 7510 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7511 txbd->tx_bd_flags = htole16(flags); 7512 prod_bseq += segs[i].ds_len; 7513 if (i == 0) 7514 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7515 prod = NEXT_TX_BD(prod); 7516 } 7517 7518 /* Set the END flag on the last TX buffer descriptor. */ 7519 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7520 7521 DBRUNMSG(BCE_EXTREME_SEND, 7522 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7523 7524 /* 7525 * Ensure that the mbuf pointer for this transmission 7526 * is placed at the array index of the last 7527 * descriptor in this chain. This is done 7528 * because a single map is used for all 7529 * segments of the mbuf and we don't want to 7530 * unload the map before all of the segments 7531 * have been freed. 7532 */ 7533 sc->tx_mbuf_ptr[chain_prod] = m0; 7534 sc->used_tx_bd += nsegs; 7535 7536 /* Update some debug statistic counters */ 7537 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7538 sc->tx_hi_watermark = sc->used_tx_bd); 7539 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7540 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7541 7542 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7543 7544 /* prod points to the next free tx_bd at this point. */ 7545 sc->tx_prod = prod; 7546 sc->tx_prod_bseq = prod_bseq; 7547 7548 /* Tell the chip about the waiting TX frames. */ 7549 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7550 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7551 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7552 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7553 7554 bce_tx_encap_exit: 7555 DBEXIT(BCE_VERBOSE_SEND); 7556 return(rc); 7557 } 7558 7559 7560 /****************************************************************************/ 7561 /* Main transmit routine when called from another routine with a lock. */ 7562 /* */ 7563 /* Returns: */ 7564 /* Nothing. */ 7565 /****************************************************************************/ 7566 static void 7567 bce_start_locked(struct ifnet *ifp) 7568 { 7569 struct bce_softc *sc = ifp->if_softc; 7570 struct mbuf *m_head = NULL; 7571 int count = 0; 7572 u16 tx_prod, tx_chain_prod; 7573 7574 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7575 7576 BCE_LOCK_ASSERT(sc); 7577 7578 /* prod points to the next free tx_bd. */ 7579 tx_prod = sc->tx_prod; 7580 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7581 7582 DBPRINT(sc, BCE_INFO_SEND, 7583 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7584 "tx_prod_bseq = 0x%08X\n", 7585 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7586 7587 /* If there's no link or the transmit queue is empty then just exit. */ 7588 if (sc->bce_link_up == FALSE) { 7589 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7590 __FUNCTION__); 7591 goto bce_start_locked_exit; 7592 } 7593 7594 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7595 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7596 __FUNCTION__); 7597 goto bce_start_locked_exit; 7598 } 7599 7600 /* 7601 * Keep adding entries while there is space in the ring. 7602 */ 7603 while (sc->used_tx_bd < sc->max_tx_bd) { 7604 7605 /* Check for any frames to send. */ 7606 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7607 7608 /* Stop when the transmit queue is empty. */ 7609 if (m_head == NULL) 7610 break; 7611 7612 /* 7613 * Pack the data into the transmit ring. If we 7614 * don't have room, place the mbuf back at the 7615 * head of the queue and set the OACTIVE flag 7616 * to wait for the NIC to drain the chain. 7617 */ 7618 if (bce_tx_encap(sc, &m_head)) { 7619 if (m_head != NULL) 7620 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7621 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7622 DBPRINT(sc, BCE_INFO_SEND, 7623 "TX chain is closed for business! Total " 7624 "tx_bd used = %d\n", sc->used_tx_bd); 7625 break; 7626 } 7627 7628 count++; 7629 7630 /* Send a copy of the frame to any BPF listeners. */ 7631 ETHER_BPF_MTAP(ifp, m_head); 7632 } 7633 7634 /* Exit if no packets were dequeued. */ 7635 if (count == 0) { 7636 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7637 "dequeued\n", __FUNCTION__); 7638 goto bce_start_locked_exit; 7639 } 7640 7641 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7642 "send queue.\n", __FUNCTION__, count); 7643 7644 /* Set the tx timeout. */ 7645 sc->watchdog_timer = BCE_TX_TIMEOUT; 7646 7647 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7648 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7649 7650 bce_start_locked_exit: 7651 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7652 } 7653 7654 7655 /****************************************************************************/ 7656 /* Main transmit routine when called from another routine without a lock. */ 7657 /* */ 7658 /* Returns: */ 7659 /* Nothing. */ 7660 /****************************************************************************/ 7661 static void 7662 bce_start(struct ifnet *ifp) 7663 { 7664 struct bce_softc *sc = ifp->if_softc; 7665 7666 DBENTER(BCE_VERBOSE_SEND); 7667 7668 BCE_LOCK(sc); 7669 bce_start_locked(ifp); 7670 BCE_UNLOCK(sc); 7671 7672 DBEXIT(BCE_VERBOSE_SEND); 7673 } 7674 7675 7676 /****************************************************************************/ 7677 /* Handles any IOCTL calls from the operating system. */ 7678 /* */ 7679 /* Returns: */ 7680 /* 0 for success, positive value for failure. */ 7681 /****************************************************************************/ 7682 static int 7683 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7684 { 7685 struct bce_softc *sc = ifp->if_softc; 7686 struct ifreq *ifr = (struct ifreq *) data; 7687 struct mii_data *mii; 7688 int mask, error = 0; 7689 7690 DBENTER(BCE_VERBOSE_MISC); 7691 7692 switch(command) { 7693 7694 /* Set the interface MTU. */ 7695 case SIOCSIFMTU: 7696 /* Check that the MTU setting is supported. */ 7697 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7698 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7699 error = EINVAL; 7700 break; 7701 } 7702 7703 DBPRINT(sc, BCE_INFO_MISC, 7704 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7705 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7706 7707 BCE_LOCK(sc); 7708 ifp->if_mtu = ifr->ifr_mtu; 7709 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7710 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7711 bce_init_locked(sc); 7712 } 7713 BCE_UNLOCK(sc); 7714 break; 7715 7716 /* Set interface flags. */ 7717 case SIOCSIFFLAGS: 7718 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7719 7720 BCE_LOCK(sc); 7721 7722 /* Check if the interface is up. */ 7723 if (ifp->if_flags & IFF_UP) { 7724 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7725 /* Change promiscuous/multicast flags as necessary. */ 7726 bce_set_rx_mode(sc); 7727 } else { 7728 /* Start the HW */ 7729 bce_init_locked(sc); 7730 } 7731 } else { 7732 /* The interface is down, check if driver is running. */ 7733 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7734 bce_stop(sc); 7735 7736 /* If MFW is running, restart the controller a bit. */ 7737 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7738 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7739 bce_chipinit(sc); 7740 bce_mgmt_init_locked(sc); 7741 } 7742 } 7743 } 7744 7745 BCE_UNLOCK(sc); 7746 break; 7747 7748 /* Add/Delete multicast address */ 7749 case SIOCADDMULTI: 7750 case SIOCDELMULTI: 7751 DBPRINT(sc, BCE_VERBOSE_MISC, 7752 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7753 7754 BCE_LOCK(sc); 7755 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7756 bce_set_rx_mode(sc); 7757 BCE_UNLOCK(sc); 7758 7759 break; 7760 7761 /* Set/Get Interface media */ 7762 case SIOCSIFMEDIA: 7763 case SIOCGIFMEDIA: 7764 DBPRINT(sc, BCE_VERBOSE_MISC, 7765 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7766 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) 7767 error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia, 7768 command); 7769 else { 7770 mii = device_get_softc(sc->bce_miibus); 7771 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 7772 command); 7773 } 7774 break; 7775 7776 /* Set interface capability */ 7777 case SIOCSIFCAP: 7778 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7779 DBPRINT(sc, BCE_INFO_MISC, 7780 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7781 7782 /* Toggle the TX checksum capabilities enable flag. */ 7783 if (mask & IFCAP_TXCSUM && 7784 ifp->if_capabilities & IFCAP_TXCSUM) { 7785 ifp->if_capenable ^= IFCAP_TXCSUM; 7786 if (IFCAP_TXCSUM & ifp->if_capenable) 7787 ifp->if_hwassist |= BCE_IF_HWASSIST; 7788 else 7789 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7790 } 7791 7792 /* Toggle the RX checksum capabilities enable flag. */ 7793 if (mask & IFCAP_RXCSUM && 7794 ifp->if_capabilities & IFCAP_RXCSUM) 7795 ifp->if_capenable ^= IFCAP_RXCSUM; 7796 7797 /* Toggle the TSO capabilities enable flag. */ 7798 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7799 ifp->if_capabilities & IFCAP_TSO4) { 7800 ifp->if_capenable ^= IFCAP_TSO4; 7801 if (IFCAP_TSO4 & ifp->if_capenable) 7802 ifp->if_hwassist |= CSUM_TSO; 7803 else 7804 ifp->if_hwassist &= ~CSUM_TSO; 7805 } 7806 7807 if (mask & IFCAP_VLAN_HWCSUM && 7808 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7809 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7810 7811 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7812 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7813 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7814 /* 7815 * Don't actually disable VLAN tag stripping as 7816 * management firmware (ASF/IPMI/UMP) requires the 7817 * feature. If VLAN tag stripping is disabled driver 7818 * will manually reconstruct the VLAN frame by 7819 * appending stripped VLAN tag. 7820 */ 7821 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7822 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7823 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7824 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7825 == 0) 7826 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7827 } 7828 VLAN_CAPABILITIES(ifp); 7829 break; 7830 default: 7831 /* We don't know how to handle the IOCTL, pass it on. */ 7832 error = ether_ioctl(ifp, command, data); 7833 break; 7834 } 7835 7836 DBEXIT(BCE_VERBOSE_MISC); 7837 return(error); 7838 } 7839 7840 7841 /****************************************************************************/ 7842 /* Transmit timeout handler. */ 7843 /* */ 7844 /* Returns: */ 7845 /* Nothing. */ 7846 /****************************************************************************/ 7847 static void 7848 bce_watchdog(struct bce_softc *sc) 7849 { 7850 uint32_t status; 7851 7852 DBENTER(BCE_EXTREME_SEND); 7853 7854 BCE_LOCK_ASSERT(sc); 7855 7856 status = 0; 7857 /* If the watchdog timer hasn't expired then just exit. */ 7858 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7859 goto bce_watchdog_exit; 7860 7861 status = REG_RD(sc, BCE_EMAC_RX_STATUS); 7862 /* If pause frames are active then don't reset the hardware. */ 7863 if ((sc->bce_flags & BCE_USING_RX_FLOW_CONTROL) != 0) { 7864 if ((status & BCE_EMAC_RX_STATUS_FFED) != 0) { 7865 /* 7866 * If link partner has us in XOFF state then wait for 7867 * the condition to clear. 7868 */ 7869 sc->watchdog_timer = BCE_TX_TIMEOUT; 7870 goto bce_watchdog_exit; 7871 } else if ((status & BCE_EMAC_RX_STATUS_FF_RECEIVED) != 0 && 7872 (status & BCE_EMAC_RX_STATUS_N_RECEIVED) != 0) { 7873 /* 7874 * If we're not currently XOFF'ed but have recently 7875 * been XOFF'd/XON'd then assume that's delaying TX 7876 * this time around. 7877 */ 7878 sc->watchdog_timer = BCE_TX_TIMEOUT; 7879 goto bce_watchdog_exit; 7880 } 7881 /* 7882 * Any other condition is unexpected and the controller 7883 * should be reset. 7884 */ 7885 } 7886 7887 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7888 __FILE__, __LINE__); 7889 7890 DBRUNMSG(BCE_INFO, 7891 bce_dump_driver_state(sc); 7892 bce_dump_status_block(sc); 7893 bce_dump_stats_block(sc); 7894 bce_dump_ftqs(sc); 7895 bce_dump_txp_state(sc, 0); 7896 bce_dump_rxp_state(sc, 0); 7897 bce_dump_tpat_state(sc, 0); 7898 bce_dump_cp_state(sc, 0); 7899 bce_dump_com_state(sc, 0)); 7900 7901 DBRUN(bce_breakpoint(sc)); 7902 7903 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7904 7905 bce_init_locked(sc); 7906 sc->watchdog_timeouts++; 7907 7908 bce_watchdog_exit: 7909 REG_WR(sc, BCE_EMAC_RX_STATUS, status); 7910 DBEXIT(BCE_EXTREME_SEND); 7911 } 7912 7913 7914 /* 7915 * Interrupt handler. 7916 */ 7917 /****************************************************************************/ 7918 /* Main interrupt entry point. Verifies that the controller generated the */ 7919 /* interrupt and then calls a separate routine for handle the various */ 7920 /* interrupt causes (PHY, TX, RX). */ 7921 /* */ 7922 /* Returns: */ 7923 /* Nothing. */ 7924 /****************************************************************************/ 7925 static void 7926 bce_intr(void *xsc) 7927 { 7928 struct bce_softc *sc; 7929 struct ifnet *ifp; 7930 u32 status_attn_bits; 7931 u16 hw_rx_cons, hw_tx_cons; 7932 7933 sc = xsc; 7934 ifp = sc->bce_ifp; 7935 7936 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7937 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7938 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7939 7940 BCE_LOCK(sc); 7941 7942 DBRUN(sc->interrupts_generated++); 7943 7944 /* Synchnorize before we read from interface's status block */ 7945 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 7946 7947 /* 7948 * If the hardware status block index matches the last value read 7949 * by the driver and we haven't asserted our interrupt then there's 7950 * nothing to do. This may only happen in case of INTx due to the 7951 * interrupt arriving at the CPU before the status block is updated. 7952 */ 7953 if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 && 7954 sc->status_block->status_idx == sc->last_status_idx && 7955 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7956 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7957 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7958 __FUNCTION__); 7959 goto bce_intr_exit; 7960 } 7961 7962 /* Ack the interrupt and stop others from occurring. */ 7963 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7964 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7965 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7966 7967 /* Check if the hardware has finished any work. */ 7968 hw_rx_cons = bce_get_hw_rx_cons(sc); 7969 hw_tx_cons = bce_get_hw_tx_cons(sc); 7970 7971 /* Keep processing data as long as there is work to do. */ 7972 for (;;) { 7973 7974 status_attn_bits = sc->status_block->status_attn_bits; 7975 7976 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7977 BCE_PRINTF("Simulating unexpected status attention " 7978 "bit set."); 7979 sc->unexpected_attention_sim_count++; 7980 status_attn_bits = status_attn_bits | 7981 STATUS_ATTN_BITS_PARITY_ERROR); 7982 7983 /* Was it a link change interrupt? */ 7984 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7985 (sc->status_block->status_attn_bits_ack & 7986 STATUS_ATTN_BITS_LINK_STATE)) { 7987 bce_phy_intr(sc); 7988 7989 /* Clear transient updates during link state change. */ 7990 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7991 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7992 REG_RD(sc, BCE_HC_COMMAND); 7993 } 7994 7995 /* If any other attention is asserted, the chip is toast. */ 7996 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7997 (sc->status_block->status_attn_bits_ack & 7998 ~STATUS_ATTN_BITS_LINK_STATE))) { 7999 8000 sc->unexpected_attention_count++; 8001 8002 BCE_PRINTF("%s(%d): Fatal attention detected: " 8003 "0x%08X\n", __FILE__, __LINE__, 8004 sc->status_block->status_attn_bits); 8005 8006 DBRUNMSG(BCE_FATAL, 8007 if (unexpected_attention_sim_control == 0) 8008 bce_breakpoint(sc)); 8009 8010 bce_init_locked(sc); 8011 goto bce_intr_exit; 8012 } 8013 8014 /* Check for any completed RX frames. */ 8015 if (hw_rx_cons != sc->hw_rx_cons) 8016 bce_rx_intr(sc); 8017 8018 /* Check for any completed TX frames. */ 8019 if (hw_tx_cons != sc->hw_tx_cons) 8020 bce_tx_intr(sc); 8021 8022 /* Save status block index value for the next interrupt. */ 8023 sc->last_status_idx = sc->status_block->status_idx; 8024 8025 /* 8026 * Prevent speculative reads from getting 8027 * ahead of the status block. 8028 */ 8029 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 8030 BUS_SPACE_BARRIER_READ); 8031 8032 /* 8033 * If there's no work left then exit the 8034 * interrupt service routine. 8035 */ 8036 hw_rx_cons = bce_get_hw_rx_cons(sc); 8037 hw_tx_cons = bce_get_hw_tx_cons(sc); 8038 8039 if ((hw_rx_cons == sc->hw_rx_cons) && 8040 (hw_tx_cons == sc->hw_tx_cons)) 8041 break; 8042 } 8043 8044 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD); 8045 8046 /* Re-enable interrupts. */ 8047 bce_enable_intr(sc, 0); 8048 8049 /* Handle any frames that arrived while handling the interrupt. */ 8050 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 8051 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 8052 bce_start_locked(ifp); 8053 8054 bce_intr_exit: 8055 BCE_UNLOCK(sc); 8056 8057 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 8058 } 8059 8060 8061 /****************************************************************************/ 8062 /* Programs the various packet receive modes (broadcast and multicast). */ 8063 /* */ 8064 /* Returns: */ 8065 /* Nothing. */ 8066 /****************************************************************************/ 8067 static void 8068 bce_set_rx_mode(struct bce_softc *sc) 8069 { 8070 struct ifnet *ifp; 8071 struct ifmultiaddr *ifma; 8072 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 8073 u32 rx_mode, sort_mode; 8074 int h, i; 8075 8076 DBENTER(BCE_VERBOSE_MISC); 8077 8078 BCE_LOCK_ASSERT(sc); 8079 8080 ifp = sc->bce_ifp; 8081 8082 /* Initialize receive mode default settings. */ 8083 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 8084 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 8085 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 8086 8087 /* 8088 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 8089 * be enbled. 8090 */ 8091 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 8092 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 8093 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 8094 8095 /* 8096 * Check for promiscuous, all multicast, or selected 8097 * multicast address filtering. 8098 */ 8099 if (ifp->if_flags & IFF_PROMISC) { 8100 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 8101 8102 /* Enable promiscuous mode. */ 8103 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 8104 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 8105 } else if (ifp->if_flags & IFF_ALLMULTI) { 8106 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 8107 8108 /* Enable all multicast addresses. */ 8109 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 8110 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 8111 0xffffffff); 8112 } 8113 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 8114 } else { 8115 /* Accept one or more multicast(s). */ 8116 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 8117 8118 if_maddr_rlock(ifp); 8119 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 8120 if (ifma->ifma_addr->sa_family != AF_LINK) 8121 continue; 8122 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 8123 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 8124 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 8125 } 8126 if_maddr_runlock(ifp); 8127 8128 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 8129 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 8130 8131 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 8132 } 8133 8134 /* Only make changes if the recive mode has actually changed. */ 8135 if (rx_mode != sc->rx_mode) { 8136 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 8137 "0x%08X\n", rx_mode); 8138 8139 sc->rx_mode = rx_mode; 8140 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 8141 } 8142 8143 /* Disable and clear the exisitng sort before enabling a new sort. */ 8144 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 8145 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 8146 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 8147 8148 DBEXIT(BCE_VERBOSE_MISC); 8149 } 8150 8151 8152 /****************************************************************************/ 8153 /* Called periodically to updates statistics from the controllers */ 8154 /* statistics block. */ 8155 /* */ 8156 /* Returns: */ 8157 /* Nothing. */ 8158 /****************************************************************************/ 8159 static void 8160 bce_stats_update(struct bce_softc *sc) 8161 { 8162 struct statistics_block *stats; 8163 8164 DBENTER(BCE_EXTREME_MISC); 8165 8166 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 8167 8168 stats = (struct statistics_block *) sc->stats_block; 8169 8170 /* 8171 * Update the sysctl statistics from the 8172 * hardware statistics. 8173 */ 8174 sc->stat_IfHCInOctets = 8175 ((u64) stats->stat_IfHCInOctets_hi << 32) + 8176 (u64) stats->stat_IfHCInOctets_lo; 8177 8178 sc->stat_IfHCInBadOctets = 8179 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 8180 (u64) stats->stat_IfHCInBadOctets_lo; 8181 8182 sc->stat_IfHCOutOctets = 8183 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 8184 (u64) stats->stat_IfHCOutOctets_lo; 8185 8186 sc->stat_IfHCOutBadOctets = 8187 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 8188 (u64) stats->stat_IfHCOutBadOctets_lo; 8189 8190 sc->stat_IfHCInUcastPkts = 8191 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 8192 (u64) stats->stat_IfHCInUcastPkts_lo; 8193 8194 sc->stat_IfHCInMulticastPkts = 8195 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 8196 (u64) stats->stat_IfHCInMulticastPkts_lo; 8197 8198 sc->stat_IfHCInBroadcastPkts = 8199 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 8200 (u64) stats->stat_IfHCInBroadcastPkts_lo; 8201 8202 sc->stat_IfHCOutUcastPkts = 8203 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 8204 (u64) stats->stat_IfHCOutUcastPkts_lo; 8205 8206 sc->stat_IfHCOutMulticastPkts = 8207 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 8208 (u64) stats->stat_IfHCOutMulticastPkts_lo; 8209 8210 sc->stat_IfHCOutBroadcastPkts = 8211 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 8212 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 8213 8214 /* ToDo: Preserve counters beyond 32 bits? */ 8215 /* ToDo: Read the statistics from auto-clear regs? */ 8216 8217 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 8218 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 8219 8220 sc->stat_Dot3StatsCarrierSenseErrors = 8221 stats->stat_Dot3StatsCarrierSenseErrors; 8222 8223 sc->stat_Dot3StatsFCSErrors = 8224 stats->stat_Dot3StatsFCSErrors; 8225 8226 sc->stat_Dot3StatsAlignmentErrors = 8227 stats->stat_Dot3StatsAlignmentErrors; 8228 8229 sc->stat_Dot3StatsSingleCollisionFrames = 8230 stats->stat_Dot3StatsSingleCollisionFrames; 8231 8232 sc->stat_Dot3StatsMultipleCollisionFrames = 8233 stats->stat_Dot3StatsMultipleCollisionFrames; 8234 8235 sc->stat_Dot3StatsDeferredTransmissions = 8236 stats->stat_Dot3StatsDeferredTransmissions; 8237 8238 sc->stat_Dot3StatsExcessiveCollisions = 8239 stats->stat_Dot3StatsExcessiveCollisions; 8240 8241 sc->stat_Dot3StatsLateCollisions = 8242 stats->stat_Dot3StatsLateCollisions; 8243 8244 sc->stat_EtherStatsCollisions = 8245 stats->stat_EtherStatsCollisions; 8246 8247 sc->stat_EtherStatsFragments = 8248 stats->stat_EtherStatsFragments; 8249 8250 sc->stat_EtherStatsJabbers = 8251 stats->stat_EtherStatsJabbers; 8252 8253 sc->stat_EtherStatsUndersizePkts = 8254 stats->stat_EtherStatsUndersizePkts; 8255 8256 sc->stat_EtherStatsOversizePkts = 8257 stats->stat_EtherStatsOversizePkts; 8258 8259 sc->stat_EtherStatsPktsRx64Octets = 8260 stats->stat_EtherStatsPktsRx64Octets; 8261 8262 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 8263 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 8264 8265 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 8266 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 8267 8268 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 8269 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 8270 8271 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8272 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8273 8274 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8275 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8276 8277 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8278 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8279 8280 sc->stat_EtherStatsPktsTx64Octets = 8281 stats->stat_EtherStatsPktsTx64Octets; 8282 8283 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8284 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8285 8286 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8287 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8288 8289 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8290 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8291 8292 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8293 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8294 8295 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8296 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8297 8298 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8299 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8300 8301 sc->stat_XonPauseFramesReceived = 8302 stats->stat_XonPauseFramesReceived; 8303 8304 sc->stat_XoffPauseFramesReceived = 8305 stats->stat_XoffPauseFramesReceived; 8306 8307 sc->stat_OutXonSent = 8308 stats->stat_OutXonSent; 8309 8310 sc->stat_OutXoffSent = 8311 stats->stat_OutXoffSent; 8312 8313 sc->stat_FlowControlDone = 8314 stats->stat_FlowControlDone; 8315 8316 sc->stat_MacControlFramesReceived = 8317 stats->stat_MacControlFramesReceived; 8318 8319 sc->stat_XoffStateEntered = 8320 stats->stat_XoffStateEntered; 8321 8322 sc->stat_IfInFramesL2FilterDiscards = 8323 stats->stat_IfInFramesL2FilterDiscards; 8324 8325 sc->stat_IfInRuleCheckerDiscards = 8326 stats->stat_IfInRuleCheckerDiscards; 8327 8328 sc->stat_IfInFTQDiscards = 8329 stats->stat_IfInFTQDiscards; 8330 8331 sc->stat_IfInMBUFDiscards = 8332 stats->stat_IfInMBUFDiscards; 8333 8334 sc->stat_IfInRuleCheckerP4Hit = 8335 stats->stat_IfInRuleCheckerP4Hit; 8336 8337 sc->stat_CatchupInRuleCheckerDiscards = 8338 stats->stat_CatchupInRuleCheckerDiscards; 8339 8340 sc->stat_CatchupInFTQDiscards = 8341 stats->stat_CatchupInFTQDiscards; 8342 8343 sc->stat_CatchupInMBUFDiscards = 8344 stats->stat_CatchupInMBUFDiscards; 8345 8346 sc->stat_CatchupInRuleCheckerP4Hit = 8347 stats->stat_CatchupInRuleCheckerP4Hit; 8348 8349 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8350 8351 /* ToDo: Add additional statistics? */ 8352 8353 DBEXIT(BCE_EXTREME_MISC); 8354 } 8355 8356 static uint64_t 8357 bce_get_counter(struct ifnet *ifp, ift_counter cnt) 8358 { 8359 struct bce_softc *sc; 8360 uint64_t rv; 8361 8362 sc = if_getsoftc(ifp); 8363 8364 switch (cnt) { 8365 case IFCOUNTER_COLLISIONS: 8366 return (sc->stat_EtherStatsCollisions); 8367 case IFCOUNTER_IERRORS: 8368 return (sc->stat_EtherStatsUndersizePkts + 8369 sc->stat_EtherStatsOversizePkts + 8370 sc->stat_IfInMBUFDiscards + 8371 sc->stat_Dot3StatsAlignmentErrors + 8372 sc->stat_Dot3StatsFCSErrors + 8373 sc->stat_IfInRuleCheckerDiscards + 8374 sc->stat_IfInFTQDiscards + 8375 sc->l2fhdr_error_count + 8376 sc->com_no_buffers); 8377 case IFCOUNTER_OERRORS: 8378 rv = sc->stat_Dot3StatsExcessiveCollisions + 8379 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8380 sc->stat_Dot3StatsLateCollisions + 8381 sc->watchdog_timeouts; 8382 /* 8383 * Certain controllers don't report 8384 * carrier sense errors correctly. 8385 * See errata E11_5708CA0_1165. 8386 */ 8387 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 8388 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 8389 rv += sc->stat_Dot3StatsCarrierSenseErrors; 8390 return (rv); 8391 default: 8392 return (if_get_counter_default(ifp, cnt)); 8393 } 8394 } 8395 8396 8397 /****************************************************************************/ 8398 /* Periodic function to notify the bootcode that the driver is still */ 8399 /* present. */ 8400 /* */ 8401 /* Returns: */ 8402 /* Nothing. */ 8403 /****************************************************************************/ 8404 static void 8405 bce_pulse(void *xsc) 8406 { 8407 struct bce_softc *sc = xsc; 8408 u32 msg; 8409 8410 DBENTER(BCE_EXTREME_MISC); 8411 8412 BCE_LOCK_ASSERT(sc); 8413 8414 /* Tell the firmware that the driver is still running. */ 8415 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8416 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8417 8418 /* Update the bootcode condition. */ 8419 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8420 8421 /* Report whether the bootcode still knows the driver is running. */ 8422 if (bce_verbose || bootverbose) { 8423 if (sc->bce_drv_cardiac_arrest == FALSE) { 8424 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8425 sc->bce_drv_cardiac_arrest = TRUE; 8426 BCE_PRINTF("%s(): Warning: bootcode " 8427 "thinks driver is absent! " 8428 "(bc_state = 0x%08X)\n", 8429 __FUNCTION__, sc->bc_state); 8430 } 8431 } else { 8432 /* 8433 * Not supported by all bootcode versions. 8434 * (v5.0.11+ and v5.2.1+) Older bootcode 8435 * will require the driver to reset the 8436 * controller to clear this condition. 8437 */ 8438 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8439 sc->bce_drv_cardiac_arrest = FALSE; 8440 BCE_PRINTF("%s(): Bootcode found the " 8441 "driver pulse! (bc_state = 0x%08X)\n", 8442 __FUNCTION__, sc->bc_state); 8443 } 8444 } 8445 } 8446 8447 8448 /* Schedule the next pulse. */ 8449 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8450 8451 DBEXIT(BCE_EXTREME_MISC); 8452 } 8453 8454 8455 /****************************************************************************/ 8456 /* Periodic function to perform maintenance tasks. */ 8457 /* */ 8458 /* Returns: */ 8459 /* Nothing. */ 8460 /****************************************************************************/ 8461 static void 8462 bce_tick(void *xsc) 8463 { 8464 struct bce_softc *sc = xsc; 8465 struct mii_data *mii; 8466 struct ifnet *ifp; 8467 struct ifmediareq ifmr; 8468 8469 ifp = sc->bce_ifp; 8470 8471 DBENTER(BCE_EXTREME_MISC); 8472 8473 BCE_LOCK_ASSERT(sc); 8474 8475 /* Schedule the next tick. */ 8476 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8477 8478 /* Update the statistics from the hardware statistics block. */ 8479 bce_stats_update(sc); 8480 8481 /* Ensure page and RX chains get refilled in low-memory situations. */ 8482 if (bce_hdr_split == TRUE) 8483 bce_fill_pg_chain(sc); 8484 bce_fill_rx_chain(sc); 8485 8486 /* Check that chip hasn't hung. */ 8487 bce_watchdog(sc); 8488 8489 /* If link is up already up then we're done. */ 8490 if (sc->bce_link_up == TRUE) 8491 goto bce_tick_exit; 8492 8493 /* Link is down. Check what the PHY's doing. */ 8494 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) { 8495 bzero(&ifmr, sizeof(ifmr)); 8496 bce_ifmedia_sts_rphy(sc, &ifmr); 8497 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) == 8498 (IFM_ACTIVE | IFM_AVALID)) { 8499 sc->bce_link_up = TRUE; 8500 bce_miibus_statchg(sc->bce_dev); 8501 } 8502 } else { 8503 mii = device_get_softc(sc->bce_miibus); 8504 mii_tick(mii); 8505 /* Check if the link has come up. */ 8506 if ((mii->mii_media_status & IFM_ACTIVE) && 8507 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8508 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", 8509 __FUNCTION__); 8510 sc->bce_link_up = TRUE; 8511 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8512 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8513 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8514 (bce_verbose || bootverbose)) 8515 BCE_PRINTF("Gigabit link up!\n"); 8516 } 8517 8518 } 8519 if (sc->bce_link_up == TRUE) { 8520 /* Now that link is up, handle any outstanding TX traffic. */ 8521 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8522 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8523 "pending TX traffic.\n", __FUNCTION__); 8524 bce_start_locked(ifp); 8525 } 8526 } 8527 8528 bce_tick_exit: 8529 DBEXIT(BCE_EXTREME_MISC); 8530 } 8531 8532 static void 8533 bce_fw_cap_init(struct bce_softc *sc) 8534 { 8535 u32 ack, cap, link; 8536 8537 ack = 0; 8538 cap = bce_shmem_rd(sc, BCE_FW_CAP_MB); 8539 if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) != 8540 BCE_FW_CAP_SIGNATURE_MAGIC) 8541 return; 8542 if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) == 8543 (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) 8544 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8545 BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN; 8546 if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 && 8547 (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) { 8548 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8549 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG; 8550 link = bce_shmem_rd(sc, BCE_LINK_STATUS); 8551 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0) 8552 sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG; 8553 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC | 8554 BCE_FW_CAP_REMOTE_PHY_CAP; 8555 } 8556 8557 if (ack != 0) 8558 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack); 8559 } 8560 8561 8562 #ifdef BCE_DEBUG 8563 /****************************************************************************/ 8564 /* Allows the driver state to be dumped through the sysctl interface. */ 8565 /* */ 8566 /* Returns: */ 8567 /* 0 for success, positive value for failure. */ 8568 /****************************************************************************/ 8569 static int 8570 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8571 { 8572 int error; 8573 int result; 8574 struct bce_softc *sc; 8575 8576 result = -1; 8577 error = sysctl_handle_int(oidp, &result, 0, req); 8578 8579 if (error || !req->newptr) 8580 return (error); 8581 8582 if (result == 1) { 8583 sc = (struct bce_softc *)arg1; 8584 bce_dump_driver_state(sc); 8585 } 8586 8587 return error; 8588 } 8589 8590 8591 /****************************************************************************/ 8592 /* Allows the hardware state to be dumped through the sysctl interface. */ 8593 /* */ 8594 /* Returns: */ 8595 /* 0 for success, positive value for failure. */ 8596 /****************************************************************************/ 8597 static int 8598 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8599 { 8600 int error; 8601 int result; 8602 struct bce_softc *sc; 8603 8604 result = -1; 8605 error = sysctl_handle_int(oidp, &result, 0, req); 8606 8607 if (error || !req->newptr) 8608 return (error); 8609 8610 if (result == 1) { 8611 sc = (struct bce_softc *)arg1; 8612 bce_dump_hw_state(sc); 8613 } 8614 8615 return error; 8616 } 8617 8618 8619 /****************************************************************************/ 8620 /* Allows the status block to be dumped through the sysctl interface. */ 8621 /* */ 8622 /* Returns: */ 8623 /* 0 for success, positive value for failure. */ 8624 /****************************************************************************/ 8625 static int 8626 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8627 { 8628 int error; 8629 int result; 8630 struct bce_softc *sc; 8631 8632 result = -1; 8633 error = sysctl_handle_int(oidp, &result, 0, req); 8634 8635 if (error || !req->newptr) 8636 return (error); 8637 8638 if (result == 1) { 8639 sc = (struct bce_softc *)arg1; 8640 bce_dump_status_block(sc); 8641 } 8642 8643 return error; 8644 } 8645 8646 8647 /****************************************************************************/ 8648 /* Allows the stats block to be dumped through the sysctl interface. */ 8649 /* */ 8650 /* Returns: */ 8651 /* 0 for success, positive value for failure. */ 8652 /****************************************************************************/ 8653 static int 8654 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8655 { 8656 int error; 8657 int result; 8658 struct bce_softc *sc; 8659 8660 result = -1; 8661 error = sysctl_handle_int(oidp, &result, 0, req); 8662 8663 if (error || !req->newptr) 8664 return (error); 8665 8666 if (result == 1) { 8667 sc = (struct bce_softc *)arg1; 8668 bce_dump_stats_block(sc); 8669 } 8670 8671 return error; 8672 } 8673 8674 8675 /****************************************************************************/ 8676 /* Allows the stat counters to be cleared without unloading/reloading the */ 8677 /* driver. */ 8678 /* */ 8679 /* Returns: */ 8680 /* 0 for success, positive value for failure. */ 8681 /****************************************************************************/ 8682 static int 8683 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8684 { 8685 int error; 8686 int result; 8687 struct bce_softc *sc; 8688 8689 result = -1; 8690 error = sysctl_handle_int(oidp, &result, 0, req); 8691 8692 if (error || !req->newptr) 8693 return (error); 8694 8695 if (result == 1) { 8696 sc = (struct bce_softc *)arg1; 8697 struct statistics_block *stats; 8698 8699 stats = (struct statistics_block *) sc->stats_block; 8700 bzero(stats, sizeof(struct statistics_block)); 8701 bus_dmamap_sync(sc->stats_tag, sc->stats_map, 8702 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 8703 8704 /* Clear the internal H/W statistics counters. */ 8705 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8706 8707 /* Reset the driver maintained statistics. */ 8708 sc->interrupts_rx = 8709 sc->interrupts_tx = 0; 8710 sc->tso_frames_requested = 8711 sc->tso_frames_completed = 8712 sc->tso_frames_failed = 0; 8713 sc->rx_empty_count = 8714 sc->tx_full_count = 0; 8715 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8716 sc->tx_hi_watermark = 0; 8717 sc->l2fhdr_error_count = 8718 sc->l2fhdr_error_sim_count = 0; 8719 sc->mbuf_alloc_failed_count = 8720 sc->mbuf_alloc_failed_sim_count = 0; 8721 sc->dma_map_addr_rx_failed_count = 8722 sc->dma_map_addr_tx_failed_count = 0; 8723 sc->mbuf_frag_count = 0; 8724 sc->csum_offload_tcp_udp = 8725 sc->csum_offload_ip = 0; 8726 sc->vlan_tagged_frames_rcvd = 8727 sc->vlan_tagged_frames_stripped = 0; 8728 sc->split_header_frames_rcvd = 8729 sc->split_header_tcp_frames_rcvd = 0; 8730 8731 /* Clear firmware maintained statistics. */ 8732 REG_WR_IND(sc, 0x120084, 0); 8733 } 8734 8735 return error; 8736 } 8737 8738 8739 /****************************************************************************/ 8740 /* Allows the shared memory contents to be dumped through the sysctl . */ 8741 /* interface. */ 8742 /* */ 8743 /* Returns: */ 8744 /* 0 for success, positive value for failure. */ 8745 /****************************************************************************/ 8746 static int 8747 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8748 { 8749 int error; 8750 int result; 8751 struct bce_softc *sc; 8752 8753 result = -1; 8754 error = sysctl_handle_int(oidp, &result, 0, req); 8755 8756 if (error || !req->newptr) 8757 return (error); 8758 8759 if (result == 1) { 8760 sc = (struct bce_softc *)arg1; 8761 bce_dump_shmem_state(sc); 8762 } 8763 8764 return error; 8765 } 8766 8767 8768 /****************************************************************************/ 8769 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8770 /* */ 8771 /* Returns: */ 8772 /* 0 for success, positive value for failure. */ 8773 /****************************************************************************/ 8774 static int 8775 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8776 { 8777 int error; 8778 int result; 8779 struct bce_softc *sc; 8780 8781 result = -1; 8782 error = sysctl_handle_int(oidp, &result, 0, req); 8783 8784 if (error || !req->newptr) 8785 return (error); 8786 8787 if (result == 1) { 8788 sc = (struct bce_softc *)arg1; 8789 bce_dump_bc_state(sc); 8790 } 8791 8792 return error; 8793 } 8794 8795 8796 /****************************************************************************/ 8797 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8798 /* */ 8799 /* Returns: */ 8800 /* 0 for success, positive value for failure. */ 8801 /****************************************************************************/ 8802 static int 8803 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8804 { 8805 int error; 8806 int result; 8807 struct bce_softc *sc; 8808 8809 result = -1; 8810 error = sysctl_handle_int(oidp, &result, 0, req); 8811 8812 if (error || !req->newptr) 8813 return (error); 8814 8815 if (result == 1) { 8816 sc = (struct bce_softc *)arg1; 8817 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8818 } 8819 8820 return error; 8821 } 8822 8823 8824 /****************************************************************************/ 8825 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8826 /* */ 8827 /* Returns: */ 8828 /* 0 for success, positive value for failure. */ 8829 /****************************************************************************/ 8830 static int 8831 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8832 { 8833 int error; 8834 int result; 8835 struct bce_softc *sc; 8836 8837 result = -1; 8838 error = sysctl_handle_int(oidp, &result, 0, req); 8839 8840 if (error || !req->newptr) 8841 return (error); 8842 8843 if (result == 1) { 8844 sc = (struct bce_softc *)arg1; 8845 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8846 } 8847 8848 return error; 8849 } 8850 8851 8852 /****************************************************************************/ 8853 /* Provides a sysctl interface to allow dumping the TX chain. */ 8854 /* */ 8855 /* Returns: */ 8856 /* 0 for success, positive value for failure. */ 8857 /****************************************************************************/ 8858 static int 8859 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8860 { 8861 int error; 8862 int result; 8863 struct bce_softc *sc; 8864 8865 result = -1; 8866 error = sysctl_handle_int(oidp, &result, 0, req); 8867 8868 if (error || !req->newptr) 8869 return (error); 8870 8871 if (result == 1) { 8872 sc = (struct bce_softc *)arg1; 8873 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8874 } 8875 8876 return error; 8877 } 8878 8879 8880 /****************************************************************************/ 8881 /* Provides a sysctl interface to allow dumping the page chain. */ 8882 /* */ 8883 /* Returns: */ 8884 /* 0 for success, positive value for failure. */ 8885 /****************************************************************************/ 8886 static int 8887 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8888 { 8889 int error; 8890 int result; 8891 struct bce_softc *sc; 8892 8893 result = -1; 8894 error = sysctl_handle_int(oidp, &result, 0, req); 8895 8896 if (error || !req->newptr) 8897 return (error); 8898 8899 if (result == 1) { 8900 sc = (struct bce_softc *)arg1; 8901 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8902 } 8903 8904 return error; 8905 } 8906 8907 /****************************************************************************/ 8908 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8909 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8910 /* */ 8911 /* Returns: */ 8912 /* 0 for success, positive value for failure. */ 8913 /****************************************************************************/ 8914 static int 8915 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8916 { 8917 struct bce_softc *sc = (struct bce_softc *)arg1; 8918 int error; 8919 u32 result; 8920 u32 val[1]; 8921 u8 *data = (u8 *) val; 8922 8923 result = -1; 8924 error = sysctl_handle_int(oidp, &result, 0, req); 8925 if (error || (req->newptr == NULL)) 8926 return (error); 8927 8928 error = bce_nvram_read(sc, result, data, 4); 8929 8930 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8931 8932 return (error); 8933 } 8934 8935 8936 /****************************************************************************/ 8937 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8938 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8939 /* */ 8940 /* Returns: */ 8941 /* 0 for success, positive value for failure. */ 8942 /****************************************************************************/ 8943 static int 8944 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8945 { 8946 struct bce_softc *sc = (struct bce_softc *)arg1; 8947 int error; 8948 u32 val, result; 8949 8950 result = -1; 8951 error = sysctl_handle_int(oidp, &result, 0, req); 8952 if (error || (req->newptr == NULL)) 8953 return (error); 8954 8955 /* Make sure the register is accessible. */ 8956 if (result < 0x8000) { 8957 val = REG_RD(sc, result); 8958 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8959 } else if (result < 0x0280000) { 8960 val = REG_RD_IND(sc, result); 8961 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8962 } 8963 8964 return (error); 8965 } 8966 8967 8968 /****************************************************************************/ 8969 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8970 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8971 /* */ 8972 /* Returns: */ 8973 /* 0 for success, positive value for failure. */ 8974 /****************************************************************************/ 8975 static int 8976 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8977 { 8978 struct bce_softc *sc; 8979 device_t dev; 8980 int error, result; 8981 u16 val; 8982 8983 result = -1; 8984 error = sysctl_handle_int(oidp, &result, 0, req); 8985 if (error || (req->newptr == NULL)) 8986 return (error); 8987 8988 /* Make sure the register is accessible. */ 8989 if (result < 0x20) { 8990 sc = (struct bce_softc *)arg1; 8991 dev = sc->bce_dev; 8992 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8993 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8994 } 8995 return (error); 8996 } 8997 8998 8999 /****************************************************************************/ 9000 /* Provides a sysctl interface for dumping the nvram contents. */ 9001 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9002 /* */ 9003 /* Returns: */ 9004 /* 0 for success, positive errno for failure. */ 9005 /****************************************************************************/ 9006 static int 9007 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 9008 { 9009 struct bce_softc *sc = (struct bce_softc *)arg1; 9010 int error, i; 9011 9012 if (sc->nvram_buf == NULL) 9013 sc->nvram_buf = malloc(sc->bce_flash_size, 9014 M_TEMP, M_ZERO | M_WAITOK); 9015 9016 error = 0; 9017 if (req->oldlen == sc->bce_flash_size) { 9018 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 9019 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 9020 } 9021 9022 if (error == 0) 9023 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 9024 9025 return error; 9026 } 9027 9028 #ifdef BCE_NVRAM_WRITE_SUPPORT 9029 /****************************************************************************/ 9030 /* Provides a sysctl interface for writing to nvram. */ 9031 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9032 /* */ 9033 /* Returns: */ 9034 /* 0 for success, positive errno for failure. */ 9035 /****************************************************************************/ 9036 static int 9037 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 9038 { 9039 struct bce_softc *sc = (struct bce_softc *)arg1; 9040 int error; 9041 9042 if (sc->nvram_buf == NULL) 9043 sc->nvram_buf = malloc(sc->bce_flash_size, 9044 M_TEMP, M_ZERO | M_WAITOK); 9045 else 9046 bzero(sc->nvram_buf, sc->bce_flash_size); 9047 9048 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 9049 if (error == 0) 9050 return (error); 9051 9052 if (req->newlen == sc->bce_flash_size) 9053 error = bce_nvram_write(sc, 0, sc->nvram_buf, 9054 sc->bce_flash_size); 9055 9056 9057 return error; 9058 } 9059 #endif 9060 9061 9062 /****************************************************************************/ 9063 /* Provides a sysctl interface to allow reading a CID. */ 9064 /* */ 9065 /* Returns: */ 9066 /* 0 for success, positive value for failure. */ 9067 /****************************************************************************/ 9068 static int 9069 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 9070 { 9071 struct bce_softc *sc; 9072 int error, result; 9073 9074 result = -1; 9075 error = sysctl_handle_int(oidp, &result, 0, req); 9076 if (error || (req->newptr == NULL)) 9077 return (error); 9078 9079 /* Make sure the register is accessible. */ 9080 if (result <= TX_CID) { 9081 sc = (struct bce_softc *)arg1; 9082 bce_dump_ctx(sc, result); 9083 } 9084 9085 return (error); 9086 } 9087 9088 9089 /****************************************************************************/ 9090 /* Provides a sysctl interface to forcing the driver to dump state and */ 9091 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 9092 /* */ 9093 /* Returns: */ 9094 /* 0 for success, positive value for failure. */ 9095 /****************************************************************************/ 9096 static int 9097 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 9098 { 9099 int error; 9100 int result; 9101 struct bce_softc *sc; 9102 9103 result = -1; 9104 error = sysctl_handle_int(oidp, &result, 0, req); 9105 9106 if (error || !req->newptr) 9107 return (error); 9108 9109 if (result == 1) { 9110 sc = (struct bce_softc *)arg1; 9111 bce_breakpoint(sc); 9112 } 9113 9114 return error; 9115 } 9116 #endif 9117 9118 /****************************************************************************/ 9119 /* Adds any sysctl parameters for tuning or debugging purposes. */ 9120 /* */ 9121 /* Returns: */ 9122 /* 0 for success, positive value for failure. */ 9123 /****************************************************************************/ 9124 static void 9125 bce_add_sysctls(struct bce_softc *sc) 9126 { 9127 struct sysctl_ctx_list *ctx; 9128 struct sysctl_oid_list *children; 9129 9130 DBENTER(BCE_VERBOSE_MISC); 9131 9132 ctx = device_get_sysctl_ctx(sc->bce_dev); 9133 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 9134 9135 #ifdef BCE_DEBUG 9136 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9137 "l2fhdr_error_sim_control", 9138 CTLFLAG_RW, &l2fhdr_error_sim_control, 9139 0, "Debug control to force l2fhdr errors"); 9140 9141 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9142 "l2fhdr_error_sim_count", 9143 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 9144 0, "Number of simulated l2_fhdr errors"); 9145 #endif 9146 9147 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9148 "l2fhdr_error_count", 9149 CTLFLAG_RD, &sc->l2fhdr_error_count, 9150 0, "Number of l2_fhdr errors"); 9151 9152 #ifdef BCE_DEBUG 9153 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9154 "mbuf_alloc_failed_sim_control", 9155 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 9156 0, "Debug control to force mbuf allocation failures"); 9157 9158 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9159 "mbuf_alloc_failed_sim_count", 9160 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 9161 0, "Number of simulated mbuf cluster allocation failures"); 9162 #endif 9163 9164 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9165 "mbuf_alloc_failed_count", 9166 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 9167 0, "Number of mbuf allocation failures"); 9168 9169 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9170 "mbuf_frag_count", 9171 CTLFLAG_RD, &sc->mbuf_frag_count, 9172 0, "Number of fragmented mbufs"); 9173 9174 #ifdef BCE_DEBUG 9175 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9176 "dma_map_addr_failed_sim_control", 9177 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 9178 0, "Debug control to force DMA mapping failures"); 9179 9180 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 9181 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9182 "dma_map_addr_failed_sim_count", 9183 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 9184 0, "Number of simulated DMA mapping failures"); 9185 9186 #endif 9187 9188 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9189 "dma_map_addr_rx_failed_count", 9190 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 9191 0, "Number of RX DMA mapping failures"); 9192 9193 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9194 "dma_map_addr_tx_failed_count", 9195 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 9196 0, "Number of TX DMA mapping failures"); 9197 9198 #ifdef BCE_DEBUG 9199 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9200 "unexpected_attention_sim_control", 9201 CTLFLAG_RW, &unexpected_attention_sim_control, 9202 0, "Debug control to simulate unexpected attentions"); 9203 9204 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9205 "unexpected_attention_sim_count", 9206 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 9207 0, "Number of simulated unexpected attentions"); 9208 #endif 9209 9210 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9211 "unexpected_attention_count", 9212 CTLFLAG_RW, &sc->unexpected_attention_count, 9213 0, "Number of unexpected attentions"); 9214 9215 #ifdef BCE_DEBUG 9216 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9217 "debug_bootcode_running_failure", 9218 CTLFLAG_RW, &bootcode_running_failure_sim_control, 9219 0, "Debug control to force bootcode running failures"); 9220 9221 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9222 "rx_low_watermark", 9223 CTLFLAG_RD, &sc->rx_low_watermark, 9224 0, "Lowest level of free rx_bd's"); 9225 9226 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9227 "rx_empty_count", 9228 CTLFLAG_RD, &sc->rx_empty_count, 9229 "Number of times the RX chain was empty"); 9230 9231 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 9232 "tx_hi_watermark", 9233 CTLFLAG_RD, &sc->tx_hi_watermark, 9234 0, "Highest level of used tx_bd's"); 9235 9236 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9237 "tx_full_count", 9238 CTLFLAG_RD, &sc->tx_full_count, 9239 "Number of times the TX chain was full"); 9240 9241 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9242 "tso_frames_requested", 9243 CTLFLAG_RD, &sc->tso_frames_requested, 9244 "Number of TSO frames requested"); 9245 9246 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9247 "tso_frames_completed", 9248 CTLFLAG_RD, &sc->tso_frames_completed, 9249 "Number of TSO frames completed"); 9250 9251 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9252 "tso_frames_failed", 9253 CTLFLAG_RD, &sc->tso_frames_failed, 9254 "Number of TSO frames failed"); 9255 9256 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9257 "csum_offload_ip", 9258 CTLFLAG_RD, &sc->csum_offload_ip, 9259 "Number of IP checksum offload frames"); 9260 9261 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9262 "csum_offload_tcp_udp", 9263 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 9264 "Number of TCP/UDP checksum offload frames"); 9265 9266 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9267 "vlan_tagged_frames_rcvd", 9268 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 9269 "Number of VLAN tagged frames received"); 9270 9271 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9272 "vlan_tagged_frames_stripped", 9273 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 9274 "Number of VLAN tagged frames stripped"); 9275 9276 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9277 "interrupts_rx", 9278 CTLFLAG_RD, &sc->interrupts_rx, 9279 "Number of RX interrupts"); 9280 9281 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9282 "interrupts_tx", 9283 CTLFLAG_RD, &sc->interrupts_tx, 9284 "Number of TX interrupts"); 9285 9286 if (bce_hdr_split == TRUE) { 9287 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9288 "split_header_frames_rcvd", 9289 CTLFLAG_RD, &sc->split_header_frames_rcvd, 9290 "Number of split header frames received"); 9291 9292 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9293 "split_header_tcp_frames_rcvd", 9294 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 9295 "Number of split header TCP frames received"); 9296 } 9297 9298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9299 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 9300 (void *)sc, 0, 9301 bce_sysctl_nvram_dump, "S", ""); 9302 9303 #ifdef BCE_NVRAM_WRITE_SUPPORT 9304 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9305 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 9306 (void *)sc, 0, 9307 bce_sysctl_nvram_write, "S", ""); 9308 #endif 9309 #endif /* BCE_DEBUG */ 9310 9311 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9312 "stat_IfHcInOctets", 9313 CTLFLAG_RD, &sc->stat_IfHCInOctets, 9314 "Bytes received"); 9315 9316 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9317 "stat_IfHCInBadOctets", 9318 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 9319 "Bad bytes received"); 9320 9321 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9322 "stat_IfHCOutOctets", 9323 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 9324 "Bytes sent"); 9325 9326 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9327 "stat_IfHCOutBadOctets", 9328 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9329 "Bad bytes sent"); 9330 9331 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9332 "stat_IfHCInUcastPkts", 9333 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9334 "Unicast packets received"); 9335 9336 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9337 "stat_IfHCInMulticastPkts", 9338 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9339 "Multicast packets received"); 9340 9341 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9342 "stat_IfHCInBroadcastPkts", 9343 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9344 "Broadcast packets received"); 9345 9346 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9347 "stat_IfHCOutUcastPkts", 9348 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9349 "Unicast packets sent"); 9350 9351 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9352 "stat_IfHCOutMulticastPkts", 9353 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9354 "Multicast packets sent"); 9355 9356 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9357 "stat_IfHCOutBroadcastPkts", 9358 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9359 "Broadcast packets sent"); 9360 9361 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9362 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9363 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9364 0, "Internal MAC transmit errors"); 9365 9366 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9367 "stat_Dot3StatsCarrierSenseErrors", 9368 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9369 0, "Carrier sense errors"); 9370 9371 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9372 "stat_Dot3StatsFCSErrors", 9373 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9374 0, "Frame check sequence errors"); 9375 9376 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9377 "stat_Dot3StatsAlignmentErrors", 9378 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9379 0, "Alignment errors"); 9380 9381 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9382 "stat_Dot3StatsSingleCollisionFrames", 9383 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9384 0, "Single Collision Frames"); 9385 9386 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9387 "stat_Dot3StatsMultipleCollisionFrames", 9388 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9389 0, "Multiple Collision Frames"); 9390 9391 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9392 "stat_Dot3StatsDeferredTransmissions", 9393 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9394 0, "Deferred Transmissions"); 9395 9396 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9397 "stat_Dot3StatsExcessiveCollisions", 9398 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9399 0, "Excessive Collisions"); 9400 9401 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9402 "stat_Dot3StatsLateCollisions", 9403 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9404 0, "Late Collisions"); 9405 9406 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9407 "stat_EtherStatsCollisions", 9408 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9409 0, "Collisions"); 9410 9411 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9412 "stat_EtherStatsFragments", 9413 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9414 0, "Fragments"); 9415 9416 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9417 "stat_EtherStatsJabbers", 9418 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9419 0, "Jabbers"); 9420 9421 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9422 "stat_EtherStatsUndersizePkts", 9423 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9424 0, "Undersize packets"); 9425 9426 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9427 "stat_EtherStatsOversizePkts", 9428 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9429 0, "stat_EtherStatsOversizePkts"); 9430 9431 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9432 "stat_EtherStatsPktsRx64Octets", 9433 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9434 0, "Bytes received in 64 byte packets"); 9435 9436 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9437 "stat_EtherStatsPktsRx65Octetsto127Octets", 9438 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9439 0, "Bytes received in 65 to 127 byte packets"); 9440 9441 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9442 "stat_EtherStatsPktsRx128Octetsto255Octets", 9443 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9444 0, "Bytes received in 128 to 255 byte packets"); 9445 9446 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9447 "stat_EtherStatsPktsRx256Octetsto511Octets", 9448 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9449 0, "Bytes received in 256 to 511 byte packets"); 9450 9451 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9452 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9453 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9454 0, "Bytes received in 512 to 1023 byte packets"); 9455 9456 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9457 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9458 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9459 0, "Bytes received in 1024 t0 1522 byte packets"); 9460 9461 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9462 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9463 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9464 0, "Bytes received in 1523 to 9022 byte packets"); 9465 9466 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9467 "stat_EtherStatsPktsTx64Octets", 9468 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9469 0, "Bytes sent in 64 byte packets"); 9470 9471 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9472 "stat_EtherStatsPktsTx65Octetsto127Octets", 9473 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9474 0, "Bytes sent in 65 to 127 byte packets"); 9475 9476 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9477 "stat_EtherStatsPktsTx128Octetsto255Octets", 9478 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9479 0, "Bytes sent in 128 to 255 byte packets"); 9480 9481 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9482 "stat_EtherStatsPktsTx256Octetsto511Octets", 9483 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9484 0, "Bytes sent in 256 to 511 byte packets"); 9485 9486 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9487 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9488 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9489 0, "Bytes sent in 512 to 1023 byte packets"); 9490 9491 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9492 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9493 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9494 0, "Bytes sent in 1024 to 1522 byte packets"); 9495 9496 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9497 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9498 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9499 0, "Bytes sent in 1523 to 9022 byte packets"); 9500 9501 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9502 "stat_XonPauseFramesReceived", 9503 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9504 0, "XON pause frames receved"); 9505 9506 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9507 "stat_XoffPauseFramesReceived", 9508 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9509 0, "XOFF pause frames received"); 9510 9511 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9512 "stat_OutXonSent", 9513 CTLFLAG_RD, &sc->stat_OutXonSent, 9514 0, "XON pause frames sent"); 9515 9516 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9517 "stat_OutXoffSent", 9518 CTLFLAG_RD, &sc->stat_OutXoffSent, 9519 0, "XOFF pause frames sent"); 9520 9521 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9522 "stat_FlowControlDone", 9523 CTLFLAG_RD, &sc->stat_FlowControlDone, 9524 0, "Flow control done"); 9525 9526 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9527 "stat_MacControlFramesReceived", 9528 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9529 0, "MAC control frames received"); 9530 9531 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9532 "stat_XoffStateEntered", 9533 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9534 0, "XOFF state entered"); 9535 9536 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9537 "stat_IfInFramesL2FilterDiscards", 9538 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9539 0, "Received L2 packets discarded"); 9540 9541 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9542 "stat_IfInRuleCheckerDiscards", 9543 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9544 0, "Received packets discarded by rule"); 9545 9546 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9547 "stat_IfInFTQDiscards", 9548 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9549 0, "Received packet FTQ discards"); 9550 9551 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9552 "stat_IfInMBUFDiscards", 9553 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9554 0, "Received packets discarded due to lack " 9555 "of controller buffer memory"); 9556 9557 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9558 "stat_IfInRuleCheckerP4Hit", 9559 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9560 0, "Received packets rule checker hits"); 9561 9562 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9563 "stat_CatchupInRuleCheckerDiscards", 9564 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9565 0, "Received packets discarded in Catchup path"); 9566 9567 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9568 "stat_CatchupInFTQDiscards", 9569 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9570 0, "Received packets discarded in FTQ in Catchup path"); 9571 9572 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9573 "stat_CatchupInMBUFDiscards", 9574 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9575 0, "Received packets discarded in controller " 9576 "buffer memory in Catchup path"); 9577 9578 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9579 "stat_CatchupInRuleCheckerP4Hit", 9580 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9581 0, "Received packets rule checker hits in Catchup path"); 9582 9583 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9584 "com_no_buffers", 9585 CTLFLAG_RD, &sc->com_no_buffers, 9586 0, "Valid packets received but no RX buffers available"); 9587 9588 #ifdef BCE_DEBUG 9589 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9590 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9591 (void *)sc, 0, 9592 bce_sysctl_driver_state, "I", "Drive state information"); 9593 9594 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9595 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9596 (void *)sc, 0, 9597 bce_sysctl_hw_state, "I", "Hardware state information"); 9598 9599 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9600 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9601 (void *)sc, 0, 9602 bce_sysctl_status_block, "I", "Dump status block"); 9603 9604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9605 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9606 (void *)sc, 0, 9607 bce_sysctl_stats_block, "I", "Dump statistics block"); 9608 9609 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9610 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9611 (void *)sc, 0, 9612 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9613 9614 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9615 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9616 (void *)sc, 0, 9617 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9618 9619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9620 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9621 (void *)sc, 0, 9622 bce_sysctl_bc_state, "I", "Bootcode state information"); 9623 9624 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9625 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9626 (void *)sc, 0, 9627 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9628 9629 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9630 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9631 (void *)sc, 0, 9632 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9633 9634 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9635 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9636 (void *)sc, 0, 9637 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9638 9639 if (bce_hdr_split == TRUE) { 9640 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9641 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9642 (void *)sc, 0, 9643 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9644 } 9645 9646 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9647 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9648 (void *)sc, 0, 9649 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9650 9651 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9652 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9653 (void *)sc, 0, 9654 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9655 9656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9657 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9658 (void *)sc, 0, 9659 bce_sysctl_reg_read, "I", "Register read"); 9660 9661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9662 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9663 (void *)sc, 0, 9664 bce_sysctl_nvram_read, "I", "NVRAM read"); 9665 9666 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9667 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9668 (void *)sc, 0, 9669 bce_sysctl_phy_read, "I", "PHY register read"); 9670 9671 #endif 9672 9673 DBEXIT(BCE_VERBOSE_MISC); 9674 } 9675 9676 9677 /****************************************************************************/ 9678 /* BCE Debug Routines */ 9679 /****************************************************************************/ 9680 #ifdef BCE_DEBUG 9681 9682 /****************************************************************************/ 9683 /* Freezes the controller to allow for a cohesive state dump. */ 9684 /* */ 9685 /* Returns: */ 9686 /* Nothing. */ 9687 /****************************************************************************/ 9688 static __attribute__ ((noinline)) void 9689 bce_freeze_controller(struct bce_softc *sc) 9690 { 9691 u32 val; 9692 val = REG_RD(sc, BCE_MISC_COMMAND); 9693 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9694 REG_WR(sc, BCE_MISC_COMMAND, val); 9695 } 9696 9697 9698 /****************************************************************************/ 9699 /* Unfreezes the controller after a freeze operation. This may not always */ 9700 /* work and the controller will require a reset! */ 9701 /* */ 9702 /* Returns: */ 9703 /* Nothing. */ 9704 /****************************************************************************/ 9705 static __attribute__ ((noinline)) void 9706 bce_unfreeze_controller(struct bce_softc *sc) 9707 { 9708 u32 val; 9709 val = REG_RD(sc, BCE_MISC_COMMAND); 9710 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9711 REG_WR(sc, BCE_MISC_COMMAND, val); 9712 } 9713 9714 9715 /****************************************************************************/ 9716 /* Prints out Ethernet frame information from an mbuf. */ 9717 /* */ 9718 /* Partially decode an Ethernet frame to look at some important headers. */ 9719 /* */ 9720 /* Returns: */ 9721 /* Nothing. */ 9722 /****************************************************************************/ 9723 static __attribute__ ((noinline)) void 9724 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9725 { 9726 struct ether_vlan_header *eh; 9727 u16 etype; 9728 int ehlen; 9729 struct ip *ip; 9730 struct tcphdr *th; 9731 struct udphdr *uh; 9732 struct arphdr *ah; 9733 9734 BCE_PRINTF( 9735 "-----------------------------" 9736 " Frame Decode " 9737 "-----------------------------\n"); 9738 9739 eh = mtod(m, struct ether_vlan_header *); 9740 9741 /* Handle VLAN encapsulation if present. */ 9742 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9743 etype = ntohs(eh->evl_proto); 9744 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9745 } else { 9746 etype = ntohs(eh->evl_encap_proto); 9747 ehlen = ETHER_HDR_LEN; 9748 } 9749 9750 /* ToDo: Add VLAN output. */ 9751 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9752 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9753 9754 switch (etype) { 9755 case ETHERTYPE_IP: 9756 ip = (struct ip *)(m->m_data + ehlen); 9757 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9758 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9759 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9760 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9761 9762 switch (ip->ip_p) { 9763 case IPPROTO_TCP: 9764 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9765 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9766 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9767 ntohs(th->th_dport), ntohs(th->th_sport), 9768 (th->th_off << 2), th->th_flags, 9769 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9770 "\02SYN\01FIN", ntohs(th->th_sum)); 9771 break; 9772 case IPPROTO_UDP: 9773 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9774 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9775 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9776 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9777 ntohs(uh->uh_sum)); 9778 break; 9779 case IPPROTO_ICMP: 9780 BCE_PRINTF("icmp:\n"); 9781 break; 9782 default: 9783 BCE_PRINTF("----: Other IP protocol.\n"); 9784 } 9785 break; 9786 case ETHERTYPE_IPV6: 9787 BCE_PRINTF("ipv6: No decode supported.\n"); 9788 break; 9789 case ETHERTYPE_ARP: 9790 BCE_PRINTF("-arp: "); 9791 ah = (struct arphdr *) (m->m_data + ehlen); 9792 switch (ntohs(ah->ar_op)) { 9793 case ARPOP_REVREQUEST: 9794 printf("reverse ARP request\n"); 9795 break; 9796 case ARPOP_REVREPLY: 9797 printf("reverse ARP reply\n"); 9798 break; 9799 case ARPOP_REQUEST: 9800 printf("ARP request\n"); 9801 break; 9802 case ARPOP_REPLY: 9803 printf("ARP reply\n"); 9804 break; 9805 default: 9806 printf("other ARP operation\n"); 9807 } 9808 break; 9809 default: 9810 BCE_PRINTF("----: Other protocol.\n"); 9811 } 9812 9813 BCE_PRINTF( 9814 "-----------------------------" 9815 "--------------" 9816 "-----------------------------\n"); 9817 } 9818 9819 9820 /****************************************************************************/ 9821 /* Prints out information about an mbuf. */ 9822 /* */ 9823 /* Returns: */ 9824 /* Nothing. */ 9825 /****************************************************************************/ 9826 static __attribute__ ((noinline)) void 9827 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9828 { 9829 struct mbuf *mp = m; 9830 9831 if (m == NULL) { 9832 BCE_PRINTF("mbuf: null pointer\n"); 9833 return; 9834 } 9835 9836 while (mp) { 9837 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9838 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9839 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9840 9841 if (mp->m_flags & M_PKTHDR) { 9842 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9843 "csum_flags = %b\n", mp->m_pkthdr.len, 9844 mp->m_flags, M_FLAG_PRINTF, 9845 mp->m_pkthdr.csum_flags, CSUM_BITS); 9846 } 9847 9848 if (mp->m_flags & M_EXT) { 9849 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9850 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9851 switch (mp->m_ext.ext_type) { 9852 case EXT_CLUSTER: 9853 printf("EXT_CLUSTER\n"); break; 9854 case EXT_SFBUF: 9855 printf("EXT_SFBUF\n"); break; 9856 case EXT_JUMBO9: 9857 printf("EXT_JUMBO9\n"); break; 9858 case EXT_JUMBO16: 9859 printf("EXT_JUMBO16\n"); break; 9860 case EXT_PACKET: 9861 printf("EXT_PACKET\n"); break; 9862 case EXT_MBUF: 9863 printf("EXT_MBUF\n"); break; 9864 case EXT_NET_DRV: 9865 printf("EXT_NET_DRV\n"); break; 9866 case EXT_MOD_TYPE: 9867 printf("EXT_MDD_TYPE\n"); break; 9868 case EXT_DISPOSABLE: 9869 printf("EXT_DISPOSABLE\n"); break; 9870 case EXT_EXTREF: 9871 printf("EXT_EXTREF\n"); break; 9872 default: 9873 printf("UNKNOWN\n"); 9874 } 9875 } 9876 9877 mp = mp->m_next; 9878 } 9879 } 9880 9881 9882 /****************************************************************************/ 9883 /* Prints out the mbufs in the TX mbuf chain. */ 9884 /* */ 9885 /* Returns: */ 9886 /* Nothing. */ 9887 /****************************************************************************/ 9888 static __attribute__ ((noinline)) void 9889 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9890 { 9891 struct mbuf *m; 9892 9893 BCE_PRINTF( 9894 "----------------------------" 9895 " tx mbuf data " 9896 "----------------------------\n"); 9897 9898 for (int i = 0; i < count; i++) { 9899 m = sc->tx_mbuf_ptr[chain_prod]; 9900 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9901 bce_dump_mbuf(sc, m); 9902 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9903 } 9904 9905 BCE_PRINTF( 9906 "----------------------------" 9907 "----------------" 9908 "----------------------------\n"); 9909 } 9910 9911 9912 /****************************************************************************/ 9913 /* Prints out the mbufs in the RX mbuf chain. */ 9914 /* */ 9915 /* Returns: */ 9916 /* Nothing. */ 9917 /****************************************************************************/ 9918 static __attribute__ ((noinline)) void 9919 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9920 { 9921 struct mbuf *m; 9922 9923 BCE_PRINTF( 9924 "----------------------------" 9925 " rx mbuf data " 9926 "----------------------------\n"); 9927 9928 for (int i = 0; i < count; i++) { 9929 m = sc->rx_mbuf_ptr[chain_prod]; 9930 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9931 bce_dump_mbuf(sc, m); 9932 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9933 } 9934 9935 9936 BCE_PRINTF( 9937 "----------------------------" 9938 "----------------" 9939 "----------------------------\n"); 9940 } 9941 9942 9943 /****************************************************************************/ 9944 /* Prints out the mbufs in the mbuf page chain. */ 9945 /* */ 9946 /* Returns: */ 9947 /* Nothing. */ 9948 /****************************************************************************/ 9949 static __attribute__ ((noinline)) void 9950 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9951 { 9952 struct mbuf *m; 9953 9954 BCE_PRINTF( 9955 "----------------------------" 9956 " pg mbuf data " 9957 "----------------------------\n"); 9958 9959 for (int i = 0; i < count; i++) { 9960 m = sc->pg_mbuf_ptr[chain_prod]; 9961 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9962 bce_dump_mbuf(sc, m); 9963 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9964 } 9965 9966 9967 BCE_PRINTF( 9968 "----------------------------" 9969 "----------------" 9970 "----------------------------\n"); 9971 } 9972 9973 9974 /****************************************************************************/ 9975 /* Prints out a tx_bd structure. */ 9976 /* */ 9977 /* Returns: */ 9978 /* Nothing. */ 9979 /****************************************************************************/ 9980 static __attribute__ ((noinline)) void 9981 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9982 { 9983 int i = 0; 9984 9985 if (idx > MAX_TX_BD_ALLOC) 9986 /* Index out of range. */ 9987 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9988 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9989 /* TX Chain page pointer. */ 9990 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9991 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9992 txbd->tx_bd_haddr_lo); 9993 else { 9994 /* Normal tx_bd entry. */ 9995 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9996 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9997 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9998 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9999 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 10000 10001 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 10002 if (i>0) 10003 printf("|"); 10004 printf("CONN_FAULT"); 10005 i++; 10006 } 10007 10008 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 10009 if (i>0) 10010 printf("|"); 10011 printf("TCP_UDP_CKSUM"); 10012 i++; 10013 } 10014 10015 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 10016 if (i>0) 10017 printf("|"); 10018 printf("IP_CKSUM"); 10019 i++; 10020 } 10021 10022 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 10023 if (i>0) 10024 printf("|"); 10025 printf("VLAN"); 10026 i++; 10027 } 10028 10029 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 10030 if (i>0) 10031 printf("|"); 10032 printf("COAL_NOW"); 10033 i++; 10034 } 10035 10036 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 10037 if (i>0) 10038 printf("|"); 10039 printf("DONT_GEN_CRC"); 10040 i++; 10041 } 10042 10043 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 10044 if (i>0) 10045 printf("|"); 10046 printf("START"); 10047 i++; 10048 } 10049 10050 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 10051 if (i>0) 10052 printf("|"); 10053 printf("END"); 10054 i++; 10055 } 10056 10057 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 10058 if (i>0) 10059 printf("|"); 10060 printf("LSO"); 10061 i++; 10062 } 10063 10064 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 10065 if (i>0) 10066 printf("|"); 10067 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 10068 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 10069 } 10070 10071 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 10072 if (i>0) 10073 printf("|"); 10074 printf("SW_FLAGS"); 10075 i++; 10076 } 10077 10078 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 10079 if (i>0) 10080 printf("|"); 10081 printf("SNAP)"); 10082 } else { 10083 printf(")\n"); 10084 } 10085 } 10086 } 10087 10088 10089 /****************************************************************************/ 10090 /* Prints out a rx_bd structure. */ 10091 /* */ 10092 /* Returns: */ 10093 /* Nothing. */ 10094 /****************************************************************************/ 10095 static __attribute__ ((noinline)) void 10096 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 10097 { 10098 if (idx > MAX_RX_BD_ALLOC) 10099 /* Index out of range. */ 10100 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 10101 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 10102 /* RX Chain page pointer. */ 10103 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 10104 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 10105 rxbd->rx_bd_haddr_lo); 10106 else 10107 /* Normal rx_bd entry. */ 10108 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 10109 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 10110 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 10111 rxbd->rx_bd_flags); 10112 } 10113 10114 10115 /****************************************************************************/ 10116 /* Prints out a rx_bd structure in the page chain. */ 10117 /* */ 10118 /* Returns: */ 10119 /* Nothing. */ 10120 /****************************************************************************/ 10121 static __attribute__ ((noinline)) void 10122 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 10123 { 10124 if (idx > MAX_PG_BD_ALLOC) 10125 /* Index out of range. */ 10126 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 10127 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 10128 /* Page Chain page pointer. */ 10129 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 10130 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 10131 else 10132 /* Normal rx_bd entry. */ 10133 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 10134 "flags = 0x%08X\n", idx, 10135 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 10136 pgbd->rx_bd_len, pgbd->rx_bd_flags); 10137 } 10138 10139 10140 /****************************************************************************/ 10141 /* Prints out a l2_fhdr structure. */ 10142 /* */ 10143 /* Returns: */ 10144 /* Nothing. */ 10145 /****************************************************************************/ 10146 static __attribute__ ((noinline)) void 10147 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 10148 { 10149 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 10150 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 10151 "tcp_udp_xsum = 0x%04X\n", idx, 10152 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 10153 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 10154 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 10155 } 10156 10157 10158 /****************************************************************************/ 10159 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 10160 /* */ 10161 /* Returns: */ 10162 /* Nothing. */ 10163 /****************************************************************************/ 10164 static __attribute__ ((noinline)) void 10165 bce_dump_ctx(struct bce_softc *sc, u16 cid) 10166 { 10167 if (cid > TX_CID) { 10168 BCE_PRINTF(" Unknown CID\n"); 10169 return; 10170 } 10171 10172 BCE_PRINTF( 10173 "----------------------------" 10174 " CTX Data " 10175 "----------------------------\n"); 10176 10177 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 10178 10179 if (cid == RX_CID) { 10180 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 10181 "producer index\n", 10182 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 10183 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 10184 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10185 BCE_L2CTX_RX_HOST_BSEQ)); 10186 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 10187 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 10188 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 10189 "descriptor address\n", 10190 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 10191 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 10192 "descriptor address\n", 10193 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 10194 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 10195 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10196 BCE_L2CTX_RX_NX_BDIDX)); 10197 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 10198 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10199 BCE_L2CTX_RX_HOST_PG_BDIDX)); 10200 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 10201 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 10202 BCE_L2CTX_RX_PG_BUF_SIZE)); 10203 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 10204 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10205 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 10206 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 10207 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 10208 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 10209 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 10210 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10211 BCE_L2CTX_RX_NX_PG_BDIDX)); 10212 } else if (cid == TX_CID) { 10213 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10214 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 10215 CTX_RD(sc, GET_CID_ADDR(cid), 10216 BCE_L2CTX_TX_TYPE_XI)); 10217 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 10218 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 10219 BCE_L2CTX_TX_CMD_TYPE_XI)); 10220 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 10221 "h/w buffer descriptor address\n", 10222 CTX_RD(sc, GET_CID_ADDR(cid), 10223 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 10224 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 10225 "h/w buffer descriptor address\n", 10226 CTX_RD(sc, GET_CID_ADDR(cid), 10227 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 10228 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 10229 "host producer index\n", 10230 CTX_RD(sc, GET_CID_ADDR(cid), 10231 BCE_L2CTX_TX_HOST_BIDX_XI)); 10232 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 10233 "host byte sequence\n", 10234 CTX_RD(sc, GET_CID_ADDR(cid), 10235 BCE_L2CTX_TX_HOST_BSEQ_XI)); 10236 } else { 10237 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 10238 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 10239 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 10240 CTX_RD(sc, GET_CID_ADDR(cid), 10241 BCE_L2CTX_TX_CMD_TYPE)); 10242 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 10243 "h/w buffer descriptor address\n", 10244 CTX_RD(sc, GET_CID_ADDR(cid), 10245 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 10246 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 10247 "h/w buffer descriptor address\n", 10248 CTX_RD(sc, GET_CID_ADDR(cid), 10249 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 10250 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 10251 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 10252 BCE_L2CTX_TX_HOST_BIDX)); 10253 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 10254 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 10255 BCE_L2CTX_TX_HOST_BSEQ)); 10256 } 10257 } 10258 10259 BCE_PRINTF( 10260 "----------------------------" 10261 " Raw CTX " 10262 "----------------------------\n"); 10263 10264 for (int i = 0x0; i < 0x300; i += 0x10) { 10265 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 10266 CTX_RD(sc, GET_CID_ADDR(cid), i), 10267 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 10268 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 10269 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 10270 } 10271 10272 10273 BCE_PRINTF( 10274 "----------------------------" 10275 "----------------" 10276 "----------------------------\n"); 10277 } 10278 10279 10280 /****************************************************************************/ 10281 /* Prints out the FTQ data. */ 10282 /* */ 10283 /* Returns: */ 10284 /* Nothing. */ 10285 /****************************************************************************/ 10286 static __attribute__ ((noinline)) void 10287 bce_dump_ftqs(struct bce_softc *sc) 10288 { 10289 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 10290 10291 BCE_PRINTF( 10292 "----------------------------" 10293 " FTQ Data " 10294 "----------------------------\n"); 10295 10296 BCE_PRINTF(" FTQ Command Control Depth_Now " 10297 "Max_Depth Valid_Cnt \n"); 10298 BCE_PRINTF(" ------- ---------- ---------- ---------- " 10299 "---------- ----------\n"); 10300 10301 /* Setup the generic statistic counters for the FTQ valid count. */ 10302 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 10303 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 10304 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 10305 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 10306 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10307 10308 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 10309 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 10310 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 10311 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 10312 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 10313 10314 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 10315 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 10316 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 10317 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 10318 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 10319 10320 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10321 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10322 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10323 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10324 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10325 10326 /* Input queue to the Receive Lookup state machine */ 10327 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10328 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10329 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10330 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10331 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10332 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10333 cmd, ctl, cur_depth, max_depth, valid_cnt); 10334 10335 /* Input queue to the Receive Processor */ 10336 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10337 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10338 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10339 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10340 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10341 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10342 cmd, ctl, cur_depth, max_depth, valid_cnt); 10343 10344 /* Input queue to the Recevie Processor */ 10345 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10346 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10347 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10348 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10349 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10350 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10351 cmd, ctl, cur_depth, max_depth, valid_cnt); 10352 10353 /* Input queue to the Receive Virtual to Physical state machine */ 10354 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10355 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10356 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10357 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10358 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10359 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10360 cmd, ctl, cur_depth, max_depth, valid_cnt); 10361 10362 /* Input queue to the Recevie Virtual to Physical state machine */ 10363 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10364 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10365 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10366 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10367 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10368 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10369 cmd, ctl, cur_depth, max_depth, valid_cnt); 10370 10371 /* Input queue to the Receive Virtual to Physical state machine */ 10372 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10373 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10374 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10375 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10376 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10377 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10378 cmd, ctl, cur_depth, max_depth, valid_cnt); 10379 10380 /* Input queue to the Receive DMA state machine */ 10381 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10382 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10383 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10384 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10385 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10386 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10387 cmd, ctl, cur_depth, max_depth, valid_cnt); 10388 10389 /* Input queue to the Transmit Scheduler state machine */ 10390 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10391 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10392 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10393 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10394 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10395 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10396 cmd, ctl, cur_depth, max_depth, valid_cnt); 10397 10398 /* Input queue to the Transmit Buffer Descriptor state machine */ 10399 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10400 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10401 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10402 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10403 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10404 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10405 cmd, ctl, cur_depth, max_depth, valid_cnt); 10406 10407 /* Input queue to the Transmit Processor */ 10408 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10409 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10410 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10411 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10412 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10413 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10414 cmd, ctl, cur_depth, max_depth, valid_cnt); 10415 10416 /* Input queue to the Transmit DMA state machine */ 10417 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10418 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10419 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10420 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10421 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10422 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10423 cmd, ctl, cur_depth, max_depth, valid_cnt); 10424 10425 /* Input queue to the Transmit Patch-Up Processor */ 10426 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10427 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10428 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10429 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10430 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10431 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10432 cmd, ctl, cur_depth, max_depth, valid_cnt); 10433 10434 /* Input queue to the Transmit Assembler state machine */ 10435 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10436 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10437 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10438 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10439 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10440 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10441 cmd, ctl, cur_depth, max_depth, valid_cnt); 10442 10443 /* Input queue to the Completion Processor */ 10444 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10445 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10446 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10447 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10448 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10449 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10450 cmd, ctl, cur_depth, max_depth, valid_cnt); 10451 10452 /* Input queue to the Completion Processor */ 10453 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10454 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10455 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10456 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10457 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10458 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10459 cmd, ctl, cur_depth, max_depth, valid_cnt); 10460 10461 /* Input queue to the Completion Processor */ 10462 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10463 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10464 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10465 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10466 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10467 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10468 cmd, ctl, cur_depth, max_depth, valid_cnt); 10469 10470 /* Setup the generic statistic counters for the FTQ valid count. */ 10471 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10472 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10473 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10474 10475 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10476 val = val | 10477 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10478 24); 10479 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10480 10481 /* Input queue to the Management Control Processor */ 10482 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10483 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10484 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10485 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10486 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10487 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10488 cmd, ctl, cur_depth, max_depth, valid_cnt); 10489 10490 /* Input queue to the Command Processor */ 10491 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10492 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10493 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10494 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10495 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10496 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10497 cmd, ctl, cur_depth, max_depth, valid_cnt); 10498 10499 /* Input queue to the Completion Scheduler state machine */ 10500 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10501 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10502 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10503 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10504 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10505 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10506 cmd, ctl, cur_depth, max_depth, valid_cnt); 10507 10508 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10509 /* Input queue to the RV2P Command Scheduler */ 10510 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10511 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10512 cur_depth = (ctl & 0xFFC00000) >> 22; 10513 max_depth = (ctl & 0x003FF000) >> 12; 10514 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10515 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10516 cmd, ctl, cur_depth, max_depth, valid_cnt); 10517 } 10518 10519 BCE_PRINTF( 10520 "----------------------------" 10521 "----------------" 10522 "----------------------------\n"); 10523 } 10524 10525 10526 /****************************************************************************/ 10527 /* Prints out the TX chain. */ 10528 /* */ 10529 /* Returns: */ 10530 /* Nothing. */ 10531 /****************************************************************************/ 10532 static __attribute__ ((noinline)) void 10533 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10534 { 10535 struct tx_bd *txbd; 10536 10537 /* First some info about the tx_bd chain structure. */ 10538 BCE_PRINTF( 10539 "----------------------------" 10540 " tx_bd chain " 10541 "----------------------------\n"); 10542 10543 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10544 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10545 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10546 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10547 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10548 10549 BCE_PRINTF( 10550 "----------------------------" 10551 " tx_bd data " 10552 "----------------------------\n"); 10553 10554 /* Now print out a decoded list of TX buffer descriptors. */ 10555 for (int i = 0; i < count; i++) { 10556 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10557 bce_dump_txbd(sc, tx_prod, txbd); 10558 tx_prod++; 10559 } 10560 10561 BCE_PRINTF( 10562 "----------------------------" 10563 "----------------" 10564 "----------------------------\n"); 10565 } 10566 10567 10568 /****************************************************************************/ 10569 /* Prints out the RX chain. */ 10570 /* */ 10571 /* Returns: */ 10572 /* Nothing. */ 10573 /****************************************************************************/ 10574 static __attribute__ ((noinline)) void 10575 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10576 { 10577 struct rx_bd *rxbd; 10578 10579 /* First some info about the rx_bd chain structure. */ 10580 BCE_PRINTF( 10581 "----------------------------" 10582 " rx_bd chain " 10583 "----------------------------\n"); 10584 10585 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10586 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10587 10588 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10589 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10590 10591 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10592 10593 BCE_PRINTF( 10594 "----------------------------" 10595 " rx_bd data " 10596 "----------------------------\n"); 10597 10598 /* Now print out the rx_bd's themselves. */ 10599 for (int i = 0; i < count; i++) { 10600 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10601 bce_dump_rxbd(sc, rx_prod, rxbd); 10602 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10603 } 10604 10605 BCE_PRINTF( 10606 "----------------------------" 10607 "----------------" 10608 "----------------------------\n"); 10609 } 10610 10611 10612 /****************************************************************************/ 10613 /* Prints out the page chain. */ 10614 /* */ 10615 /* Returns: */ 10616 /* Nothing. */ 10617 /****************************************************************************/ 10618 static __attribute__ ((noinline)) void 10619 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10620 { 10621 struct rx_bd *pgbd; 10622 10623 /* First some info about the page chain structure. */ 10624 BCE_PRINTF( 10625 "----------------------------" 10626 " page chain " 10627 "----------------------------\n"); 10628 10629 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10630 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10631 10632 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10633 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10634 10635 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10636 10637 BCE_PRINTF( 10638 "----------------------------" 10639 " page data " 10640 "----------------------------\n"); 10641 10642 /* Now print out the rx_bd's themselves. */ 10643 for (int i = 0; i < count; i++) { 10644 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10645 bce_dump_pgbd(sc, pg_prod, pgbd); 10646 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10647 } 10648 10649 BCE_PRINTF( 10650 "----------------------------" 10651 "----------------" 10652 "----------------------------\n"); 10653 } 10654 10655 10656 #define BCE_PRINT_RX_CONS(arg) \ 10657 if (sblk->status_rx_quick_consumer_index##arg) \ 10658 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10659 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10660 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10661 arg); 10662 10663 10664 #define BCE_PRINT_TX_CONS(arg) \ 10665 if (sblk->status_tx_quick_consumer_index##arg) \ 10666 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10667 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10668 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10669 arg); 10670 10671 /****************************************************************************/ 10672 /* Prints out the status block from host memory. */ 10673 /* */ 10674 /* Returns: */ 10675 /* Nothing. */ 10676 /****************************************************************************/ 10677 static __attribute__ ((noinline)) void 10678 bce_dump_status_block(struct bce_softc *sc) 10679 { 10680 struct status_block *sblk; 10681 10682 bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD); 10683 10684 sblk = sc->status_block; 10685 10686 BCE_PRINTF( 10687 "----------------------------" 10688 " Status Block " 10689 "----------------------------\n"); 10690 10691 /* Theses indices are used for normal L2 drivers. */ 10692 BCE_PRINTF(" 0x%08X - attn_bits\n", 10693 sblk->status_attn_bits); 10694 10695 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10696 sblk->status_attn_bits_ack); 10697 10698 BCE_PRINT_RX_CONS(0); 10699 BCE_PRINT_TX_CONS(0) 10700 10701 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10702 10703 /* Theses indices are not used for normal L2 drivers. */ 10704 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10705 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10706 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10707 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10708 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10709 10710 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10711 10712 if (sblk->status_completion_producer_index || 10713 sblk->status_cmd_consumer_index) 10714 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10715 sblk->status_completion_producer_index, 10716 sblk->status_cmd_consumer_index); 10717 10718 BCE_PRINTF( 10719 "----------------------------" 10720 "----------------" 10721 "----------------------------\n"); 10722 } 10723 10724 10725 #define BCE_PRINT_64BIT_STAT(arg) \ 10726 if (sblk->arg##_lo || sblk->arg##_hi) \ 10727 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10728 sblk->arg##_lo, #arg); 10729 10730 #define BCE_PRINT_32BIT_STAT(arg) \ 10731 if (sblk->arg) \ 10732 BCE_PRINTF(" 0x%08X : %s\n", \ 10733 sblk->arg, #arg); 10734 10735 /****************************************************************************/ 10736 /* Prints out the statistics block from host memory. */ 10737 /* */ 10738 /* Returns: */ 10739 /* Nothing. */ 10740 /****************************************************************************/ 10741 static __attribute__ ((noinline)) void 10742 bce_dump_stats_block(struct bce_softc *sc) 10743 { 10744 struct statistics_block *sblk; 10745 10746 bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD); 10747 10748 sblk = sc->stats_block; 10749 10750 BCE_PRINTF( 10751 "---------------" 10752 " Stats Block (All Stats Not Shown Are 0) " 10753 "---------------\n"); 10754 10755 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10756 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10757 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10758 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10759 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10760 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10761 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10762 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10763 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10764 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10765 BCE_PRINT_32BIT_STAT( 10766 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10767 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10768 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10769 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10770 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10771 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10772 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10773 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10774 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10775 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10776 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10777 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10778 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10779 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10780 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10781 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10782 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10783 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10784 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10785 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10786 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10787 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10788 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10789 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10790 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10791 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10792 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10793 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10794 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10795 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10796 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10797 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10798 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10799 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10800 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10801 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10802 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10803 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10804 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10805 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10806 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10807 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10808 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10809 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10810 10811 BCE_PRINTF( 10812 "----------------------------" 10813 "----------------" 10814 "----------------------------\n"); 10815 } 10816 10817 10818 /****************************************************************************/ 10819 /* Prints out a summary of the driver state. */ 10820 /* */ 10821 /* Returns: */ 10822 /* Nothing. */ 10823 /****************************************************************************/ 10824 static __attribute__ ((noinline)) void 10825 bce_dump_driver_state(struct bce_softc *sc) 10826 { 10827 u32 val_hi, val_lo; 10828 10829 BCE_PRINTF( 10830 "-----------------------------" 10831 " Driver State " 10832 "-----------------------------\n"); 10833 10834 val_hi = BCE_ADDR_HI(sc); 10835 val_lo = BCE_ADDR_LO(sc); 10836 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10837 "address\n", val_hi, val_lo); 10838 10839 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10840 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10841 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10842 "address\n", val_hi, val_lo); 10843 10844 val_hi = BCE_ADDR_HI(sc->status_block); 10845 val_lo = BCE_ADDR_LO(sc->status_block); 10846 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10847 "virtual address\n", val_hi, val_lo); 10848 10849 val_hi = BCE_ADDR_HI(sc->stats_block); 10850 val_lo = BCE_ADDR_LO(sc->stats_block); 10851 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10852 "virtual address\n", val_hi, val_lo); 10853 10854 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10855 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10856 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10857 "virtual adddress\n", val_hi, val_lo); 10858 10859 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10860 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10861 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10862 "virtual address\n", val_hi, val_lo); 10863 10864 if (bce_hdr_split == TRUE) { 10865 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10866 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10867 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10868 "virtual address\n", val_hi, val_lo); 10869 } 10870 10871 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10872 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10873 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10874 "virtual address\n", val_hi, val_lo); 10875 10876 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10877 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10878 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10879 "virtual address\n", val_hi, val_lo); 10880 10881 if (bce_hdr_split == TRUE) { 10882 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10883 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10884 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10885 "virtual address\n", val_hi, val_lo); 10886 } 10887 10888 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10889 "h/w intrs\n", 10890 (long long unsigned int) sc->interrupts_generated); 10891 10892 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10893 "rx interrupts handled\n", 10894 (long long unsigned int) sc->interrupts_rx); 10895 10896 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10897 "tx interrupts handled\n", 10898 (long long unsigned int) sc->interrupts_tx); 10899 10900 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10901 "phy interrupts handled\n", 10902 (long long unsigned int) sc->phy_interrupts); 10903 10904 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10905 "status block index\n", sc->last_status_idx); 10906 10907 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10908 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10909 10910 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10911 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10912 10913 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10914 "byte seq index\n", sc->tx_prod_bseq); 10915 10916 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10917 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10918 10919 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10920 "tx_bd's\n", sc->used_tx_bd); 10921 10922 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10923 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10924 10925 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10926 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10927 10928 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10929 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10930 10931 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10932 "byte seq index\n", sc->rx_prod_bseq); 10933 10934 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10935 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10936 10937 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10938 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10939 10940 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10941 "rx_bd's\n", sc->free_rx_bd); 10942 10943 if (bce_hdr_split == TRUE) { 10944 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10945 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10946 10947 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10948 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10949 10950 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10951 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10952 } 10953 10954 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10955 "rx_bd's\n", sc->free_pg_bd); 10956 10957 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10958 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10959 10960 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10961 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10962 10963 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10964 "bce mac flags\n", sc->bce_flags); 10965 10966 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10967 "bce phy flags\n", sc->bce_phy_flags); 10968 10969 BCE_PRINTF( 10970 "----------------------------" 10971 "----------------" 10972 "----------------------------\n"); 10973 } 10974 10975 10976 /****************************************************************************/ 10977 /* Prints out the hardware state through a summary of important register, */ 10978 /* followed by a complete register dump. */ 10979 /* */ 10980 /* Returns: */ 10981 /* Nothing. */ 10982 /****************************************************************************/ 10983 static __attribute__ ((noinline)) void 10984 bce_dump_hw_state(struct bce_softc *sc) 10985 { 10986 u32 val; 10987 10988 BCE_PRINTF( 10989 "----------------------------" 10990 " Hardware State " 10991 "----------------------------\n"); 10992 10993 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10994 10995 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10996 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10997 val, BCE_MISC_ENABLE_STATUS_BITS); 10998 10999 val = REG_RD(sc, BCE_DMA_STATUS); 11000 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 11001 val, BCE_DMA_STATUS); 11002 11003 val = REG_RD(sc, BCE_CTX_STATUS); 11004 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 11005 val, BCE_CTX_STATUS); 11006 11007 val = REG_RD(sc, BCE_EMAC_STATUS); 11008 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 11009 val, BCE_EMAC_STATUS); 11010 11011 val = REG_RD(sc, BCE_RPM_STATUS); 11012 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 11013 val, BCE_RPM_STATUS); 11014 11015 /* ToDo: Create a #define for this constant. */ 11016 val = REG_RD(sc, 0x2004); 11017 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 11018 val, 0x2004); 11019 11020 val = REG_RD(sc, BCE_RV2P_STATUS); 11021 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 11022 val, BCE_RV2P_STATUS); 11023 11024 /* ToDo: Create a #define for this constant. */ 11025 val = REG_RD(sc, 0x2c04); 11026 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 11027 val, 0x2c04); 11028 11029 val = REG_RD(sc, BCE_TBDR_STATUS); 11030 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 11031 val, BCE_TBDR_STATUS); 11032 11033 val = REG_RD(sc, BCE_TDMA_STATUS); 11034 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 11035 val, BCE_TDMA_STATUS); 11036 11037 val = REG_RD(sc, BCE_HC_STATUS); 11038 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 11039 val, BCE_HC_STATUS); 11040 11041 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11042 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11043 val, BCE_TXP_CPU_STATE); 11044 11045 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11046 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11047 val, BCE_TPAT_CPU_STATE); 11048 11049 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11050 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11051 val, BCE_RXP_CPU_STATE); 11052 11053 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11054 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11055 val, BCE_COM_CPU_STATE); 11056 11057 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 11058 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 11059 val, BCE_MCP_CPU_STATE); 11060 11061 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11062 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11063 val, BCE_CP_CPU_STATE); 11064 11065 BCE_PRINTF( 11066 "----------------------------" 11067 "----------------" 11068 "----------------------------\n"); 11069 11070 BCE_PRINTF( 11071 "----------------------------" 11072 " Register Dump " 11073 "----------------------------\n"); 11074 11075 for (int i = 0x400; i < 0x8000; i += 0x10) { 11076 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11077 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11078 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11079 } 11080 11081 BCE_PRINTF( 11082 "----------------------------" 11083 "----------------" 11084 "----------------------------\n"); 11085 } 11086 11087 11088 /****************************************************************************/ 11089 /* Prints out the contentst of shared memory which is used for host driver */ 11090 /* to bootcode firmware communication. */ 11091 /* */ 11092 /* Returns: */ 11093 /* Nothing. */ 11094 /****************************************************************************/ 11095 static __attribute__ ((noinline)) void 11096 bce_dump_shmem_state(struct bce_softc *sc) 11097 { 11098 BCE_PRINTF( 11099 "----------------------------" 11100 " Hardware State " 11101 "----------------------------\n"); 11102 11103 BCE_PRINTF("0x%08X - Shared memory base address\n", 11104 sc->bce_shmem_base); 11105 BCE_PRINTF("%s - bootcode version\n", 11106 sc->bce_bc_ver); 11107 11108 BCE_PRINTF( 11109 "----------------------------" 11110 " Shared Mem " 11111 "----------------------------\n"); 11112 11113 for (int i = 0x0; i < 0x200; i += 0x10) { 11114 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11115 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 11116 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 11117 } 11118 11119 BCE_PRINTF( 11120 "----------------------------" 11121 "----------------" 11122 "----------------------------\n"); 11123 } 11124 11125 11126 /****************************************************************************/ 11127 /* Prints out the mailbox queue registers. */ 11128 /* */ 11129 /* Returns: */ 11130 /* Nothing. */ 11131 /****************************************************************************/ 11132 static __attribute__ ((noinline)) void 11133 bce_dump_mq_regs(struct bce_softc *sc) 11134 { 11135 BCE_PRINTF( 11136 "----------------------------" 11137 " MQ Regs " 11138 "----------------------------\n"); 11139 11140 BCE_PRINTF( 11141 "----------------------------" 11142 "----------------" 11143 "----------------------------\n"); 11144 11145 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 11146 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 11147 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 11148 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 11149 } 11150 11151 BCE_PRINTF( 11152 "----------------------------" 11153 "----------------" 11154 "----------------------------\n"); 11155 } 11156 11157 11158 /****************************************************************************/ 11159 /* Prints out the bootcode state. */ 11160 /* */ 11161 /* Returns: */ 11162 /* Nothing. */ 11163 /****************************************************************************/ 11164 static __attribute__ ((noinline)) void 11165 bce_dump_bc_state(struct bce_softc *sc) 11166 { 11167 u32 val; 11168 11169 BCE_PRINTF( 11170 "----------------------------" 11171 " Bootcode State " 11172 "----------------------------\n"); 11173 11174 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 11175 11176 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 11177 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 11178 val, BCE_BC_RESET_TYPE); 11179 11180 val = bce_shmem_rd(sc, BCE_BC_STATE); 11181 BCE_PRINTF("0x%08X - (0x%06X) state\n", 11182 val, BCE_BC_STATE); 11183 11184 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 11185 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 11186 val, BCE_BC_STATE_CONDITION); 11187 11188 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 11189 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 11190 val, BCE_BC_STATE_DEBUG_CMD); 11191 11192 BCE_PRINTF( 11193 "----------------------------" 11194 "----------------" 11195 "----------------------------\n"); 11196 } 11197 11198 11199 /****************************************************************************/ 11200 /* Prints out the TXP processor state. */ 11201 /* */ 11202 /* Returns: */ 11203 /* Nothing. */ 11204 /****************************************************************************/ 11205 static __attribute__ ((noinline)) void 11206 bce_dump_txp_state(struct bce_softc *sc, int regs) 11207 { 11208 u32 val; 11209 u32 fw_version[3]; 11210 11211 BCE_PRINTF( 11212 "----------------------------" 11213 " TXP State " 11214 "----------------------------\n"); 11215 11216 for (int i = 0; i < 3; i++) 11217 fw_version[i] = htonl(REG_RD_IND(sc, 11218 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 11219 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11220 11221 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 11222 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 11223 val, BCE_TXP_CPU_MODE); 11224 11225 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 11226 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 11227 val, BCE_TXP_CPU_STATE); 11228 11229 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 11230 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 11231 val, BCE_TXP_CPU_EVENT_MASK); 11232 11233 if (regs) { 11234 BCE_PRINTF( 11235 "----------------------------" 11236 " Register Dump " 11237 "----------------------------\n"); 11238 11239 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 11240 /* Skip the big blank spaces */ 11241 if (i < 0x454000 && i > 0x5ffff) 11242 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11243 "0x%08X 0x%08X\n", i, 11244 REG_RD_IND(sc, i), 11245 REG_RD_IND(sc, i + 0x4), 11246 REG_RD_IND(sc, i + 0x8), 11247 REG_RD_IND(sc, i + 0xC)); 11248 } 11249 } 11250 11251 BCE_PRINTF( 11252 "----------------------------" 11253 "----------------" 11254 "----------------------------\n"); 11255 } 11256 11257 11258 /****************************************************************************/ 11259 /* Prints out the RXP processor state. */ 11260 /* */ 11261 /* Returns: */ 11262 /* Nothing. */ 11263 /****************************************************************************/ 11264 static __attribute__ ((noinline)) void 11265 bce_dump_rxp_state(struct bce_softc *sc, int regs) 11266 { 11267 u32 val; 11268 u32 fw_version[3]; 11269 11270 BCE_PRINTF( 11271 "----------------------------" 11272 " RXP State " 11273 "----------------------------\n"); 11274 11275 for (int i = 0; i < 3; i++) 11276 fw_version[i] = htonl(REG_RD_IND(sc, 11277 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 11278 11279 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11280 11281 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 11282 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 11283 val, BCE_RXP_CPU_MODE); 11284 11285 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 11286 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 11287 val, BCE_RXP_CPU_STATE); 11288 11289 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 11290 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 11291 val, BCE_RXP_CPU_EVENT_MASK); 11292 11293 if (regs) { 11294 BCE_PRINTF( 11295 "----------------------------" 11296 " Register Dump " 11297 "----------------------------\n"); 11298 11299 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 11300 /* Skip the big blank sapces */ 11301 if (i < 0xc5400 && i > 0xdffff) 11302 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11303 "0x%08X 0x%08X\n", i, 11304 REG_RD_IND(sc, i), 11305 REG_RD_IND(sc, i + 0x4), 11306 REG_RD_IND(sc, i + 0x8), 11307 REG_RD_IND(sc, i + 0xC)); 11308 } 11309 } 11310 11311 BCE_PRINTF( 11312 "----------------------------" 11313 "----------------" 11314 "----------------------------\n"); 11315 } 11316 11317 11318 /****************************************************************************/ 11319 /* Prints out the TPAT processor state. */ 11320 /* */ 11321 /* Returns: */ 11322 /* Nothing. */ 11323 /****************************************************************************/ 11324 static __attribute__ ((noinline)) void 11325 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11326 { 11327 u32 val; 11328 u32 fw_version[3]; 11329 11330 BCE_PRINTF( 11331 "----------------------------" 11332 " TPAT State " 11333 "----------------------------\n"); 11334 11335 for (int i = 0; i < 3; i++) 11336 fw_version[i] = htonl(REG_RD_IND(sc, 11337 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11338 11339 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11340 11341 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11342 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11343 val, BCE_TPAT_CPU_MODE); 11344 11345 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11346 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11347 val, BCE_TPAT_CPU_STATE); 11348 11349 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11350 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11351 val, BCE_TPAT_CPU_EVENT_MASK); 11352 11353 if (regs) { 11354 BCE_PRINTF( 11355 "----------------------------" 11356 " Register Dump " 11357 "----------------------------\n"); 11358 11359 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11360 /* Skip the big blank spaces */ 11361 if (i < 0x854000 && i > 0x9ffff) 11362 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11363 "0x%08X 0x%08X\n", i, 11364 REG_RD_IND(sc, i), 11365 REG_RD_IND(sc, i + 0x4), 11366 REG_RD_IND(sc, i + 0x8), 11367 REG_RD_IND(sc, i + 0xC)); 11368 } 11369 } 11370 11371 BCE_PRINTF( 11372 "----------------------------" 11373 "----------------" 11374 "----------------------------\n"); 11375 } 11376 11377 11378 /****************************************************************************/ 11379 /* Prints out the Command Procesor (CP) state. */ 11380 /* */ 11381 /* Returns: */ 11382 /* Nothing. */ 11383 /****************************************************************************/ 11384 static __attribute__ ((noinline)) void 11385 bce_dump_cp_state(struct bce_softc *sc, int regs) 11386 { 11387 u32 val; 11388 u32 fw_version[3]; 11389 11390 BCE_PRINTF( 11391 "----------------------------" 11392 " CP State " 11393 "----------------------------\n"); 11394 11395 for (int i = 0; i < 3; i++) 11396 fw_version[i] = htonl(REG_RD_IND(sc, 11397 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11398 11399 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11400 11401 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11402 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11403 val, BCE_CP_CPU_MODE); 11404 11405 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11406 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11407 val, BCE_CP_CPU_STATE); 11408 11409 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11410 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11411 BCE_CP_CPU_EVENT_MASK); 11412 11413 if (regs) { 11414 BCE_PRINTF( 11415 "----------------------------" 11416 " Register Dump " 11417 "----------------------------\n"); 11418 11419 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11420 /* Skip the big blank spaces */ 11421 if (i < 0x185400 && i > 0x19ffff) 11422 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11423 "0x%08X 0x%08X\n", i, 11424 REG_RD_IND(sc, i), 11425 REG_RD_IND(sc, i + 0x4), 11426 REG_RD_IND(sc, i + 0x8), 11427 REG_RD_IND(sc, i + 0xC)); 11428 } 11429 } 11430 11431 BCE_PRINTF( 11432 "----------------------------" 11433 "----------------" 11434 "----------------------------\n"); 11435 } 11436 11437 11438 /****************************************************************************/ 11439 /* Prints out the Completion Procesor (COM) state. */ 11440 /* */ 11441 /* Returns: */ 11442 /* Nothing. */ 11443 /****************************************************************************/ 11444 static __attribute__ ((noinline)) void 11445 bce_dump_com_state(struct bce_softc *sc, int regs) 11446 { 11447 u32 val; 11448 u32 fw_version[4]; 11449 11450 BCE_PRINTF( 11451 "----------------------------" 11452 " COM State " 11453 "----------------------------\n"); 11454 11455 for (int i = 0; i < 3; i++) 11456 fw_version[i] = htonl(REG_RD_IND(sc, 11457 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11458 11459 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11460 11461 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11462 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11463 val, BCE_COM_CPU_MODE); 11464 11465 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11466 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11467 val, BCE_COM_CPU_STATE); 11468 11469 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11470 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11471 BCE_COM_CPU_EVENT_MASK); 11472 11473 if (regs) { 11474 BCE_PRINTF( 11475 "----------------------------" 11476 " Register Dump " 11477 "----------------------------\n"); 11478 11479 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11480 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11481 "0x%08X 0x%08X\n", i, 11482 REG_RD_IND(sc, i), 11483 REG_RD_IND(sc, i + 0x4), 11484 REG_RD_IND(sc, i + 0x8), 11485 REG_RD_IND(sc, i + 0xC)); 11486 } 11487 } 11488 11489 BCE_PRINTF( 11490 "----------------------------" 11491 "----------------" 11492 "----------------------------\n"); 11493 } 11494 11495 11496 /****************************************************************************/ 11497 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11498 /* */ 11499 /* Returns: */ 11500 /* Nothing. */ 11501 /****************************************************************************/ 11502 static __attribute__ ((noinline)) void 11503 bce_dump_rv2p_state(struct bce_softc *sc) 11504 { 11505 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11506 11507 BCE_PRINTF( 11508 "----------------------------" 11509 " RV2P State " 11510 "----------------------------\n"); 11511 11512 /* Stall the RV2P processors. */ 11513 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11514 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11515 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11516 11517 /* Read the firmware version. */ 11518 val = 0x00000001; 11519 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11520 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11521 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11522 BCE_RV2P_INSTR_HIGH_HIGH; 11523 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11524 fw_ver_high, fw_ver_low); 11525 11526 val = 0x00000001; 11527 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11528 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11529 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11530 BCE_RV2P_INSTR_HIGH_HIGH; 11531 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11532 fw_ver_high, fw_ver_low); 11533 11534 /* Resume the RV2P processors. */ 11535 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11536 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11537 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11538 11539 /* Fetch the program counter value. */ 11540 val = 0x68007800; 11541 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11542 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11543 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11544 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11545 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11546 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11547 11548 /* Fetch the program counter value again to see if it is advancing. */ 11549 val = 0x68007800; 11550 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11551 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11552 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11553 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11554 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11555 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11556 11557 BCE_PRINTF( 11558 "----------------------------" 11559 "----------------" 11560 "----------------------------\n"); 11561 } 11562 11563 11564 /****************************************************************************/ 11565 /* Prints out the driver state and then enters the debugger. */ 11566 /* */ 11567 /* Returns: */ 11568 /* Nothing. */ 11569 /****************************************************************************/ 11570 static __attribute__ ((noinline)) void 11571 bce_breakpoint(struct bce_softc *sc) 11572 { 11573 11574 /* 11575 * Unreachable code to silence compiler warnings 11576 * about unused functions. 11577 */ 11578 if (0) { 11579 bce_freeze_controller(sc); 11580 bce_unfreeze_controller(sc); 11581 bce_dump_enet(sc, NULL); 11582 bce_dump_txbd(sc, 0, NULL); 11583 bce_dump_rxbd(sc, 0, NULL); 11584 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11585 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11586 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11587 bce_dump_l2fhdr(sc, 0, NULL); 11588 bce_dump_ctx(sc, RX_CID); 11589 bce_dump_ftqs(sc); 11590 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11591 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11592 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11593 bce_dump_status_block(sc); 11594 bce_dump_stats_block(sc); 11595 bce_dump_driver_state(sc); 11596 bce_dump_hw_state(sc); 11597 bce_dump_bc_state(sc); 11598 bce_dump_txp_state(sc, 0); 11599 bce_dump_rxp_state(sc, 0); 11600 bce_dump_tpat_state(sc, 0); 11601 bce_dump_cp_state(sc, 0); 11602 bce_dump_com_state(sc, 0); 11603 bce_dump_rv2p_state(sc); 11604 bce_dump_pgbd(sc, 0, NULL); 11605 } 11606 11607 bce_dump_status_block(sc); 11608 bce_dump_driver_state(sc); 11609 11610 /* Call the debugger. */ 11611 breakpoint(); 11612 } 11613 #endif 11614