1 /*- 2 * Copyright (c) 2006-2010 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5706S A2, A3 38 * BCM5708C B1, B2 39 * BCM5708S B1, B2 40 * BCM5709C A1, C0 41 * BCM5709S A1, C0 42 * BCM5716C C0 43 * BCM5716S C0 44 * 45 * The following controllers are not supported by this driver: 46 * BCM5706C A0, A1 (pre-production) 47 * BCM5706S A0, A1 (pre-production) 48 * BCM5708C A0, B0 (pre-production) 49 * BCM5708S A0, B0 (pre-production) 50 * BCM5709C A0 B0, B1, B2 (pre-production) 51 * BCM5709S A0, B0, B1, B2 (pre-production) 52 */ 53 54 #include "opt_bce.h" 55 56 #include <dev/bce/if_bcereg.h> 57 #include <dev/bce/if_bcefw.h> 58 59 /****************************************************************************/ 60 /* BCE Debug Options */ 61 /****************************************************************************/ 62 #ifdef BCE_DEBUG 63 u32 bce_debug = BCE_WARN; 64 65 /* 0 = Never */ 66 /* 1 = 1 in 2,147,483,648 */ 67 /* 256 = 1 in 8,388,608 */ 68 /* 2048 = 1 in 1,048,576 */ 69 /* 65536 = 1 in 32,768 */ 70 /* 1048576 = 1 in 2,048 */ 71 /* 268435456 = 1 in 8 */ 72 /* 536870912 = 1 in 4 */ 73 /* 1073741824 = 1 in 2 */ 74 75 /* Controls how often the l2_fhdr frame error check will fail. */ 76 int l2fhdr_error_sim_control = 0; 77 78 /* Controls how often the unexpected attention check will fail. */ 79 int unexpected_attention_sim_control = 0; 80 81 /* Controls how often to simulate an mbuf allocation failure. */ 82 int mbuf_alloc_failed_sim_control = 0; 83 84 /* Controls how often to simulate a DMA mapping failure. */ 85 int dma_map_addr_failed_sim_control = 0; 86 87 /* Controls how often to simulate a bootcode failure. */ 88 int bootcode_running_failure_sim_control = 0; 89 #endif 90 91 /****************************************************************************/ 92 /* PCI Device ID Table */ 93 /* */ 94 /* Used by bce_probe() to identify the devices supported by this driver. */ 95 /****************************************************************************/ 96 #define BCE_DEVDESC_MAX 64 97 98 static struct bce_type bce_devs[] = { 99 /* BCM5706C Controllers and OEM boards. */ 100 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 101 "HP NC370T Multifunction Gigabit Server Adapter" }, 102 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 103 "HP NC370i Multifunction Gigabit Server Adapter" }, 104 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070, 105 "HP NC380T PCIe DP Multifunc Gig Server Adapter" }, 106 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709, 107 "HP NC371i Multifunction Gigabit Server Adapter" }, 108 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 109 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 110 111 /* BCM5706S controllers and OEM boards. */ 112 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 113 "HP NC370F Multifunction Gigabit Server Adapter" }, 114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 115 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 116 117 /* BCM5708C controllers and OEM boards. */ 118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037, 119 "HP NC373T PCIe Multifunction Gig Server Adapter" }, 120 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038, 121 "HP NC373i Multifunction Gigabit Server Adapter" }, 122 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045, 123 "HP NC374m PCIe Multifunction Adapter" }, 124 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 125 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 126 127 /* BCM5708S controllers and OEM boards. */ 128 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706, 129 "HP NC373m Multifunction Gigabit Server Adapter" }, 130 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b, 131 "HP NC373i Multifunction Gigabit Server Adapter" }, 132 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d, 133 "HP NC373F PCIe Multifunc Giga Server Adapter" }, 134 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 135 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 136 137 /* BCM5709C controllers and OEM boards. */ 138 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055, 139 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 140 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059, 141 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" }, 142 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID, 143 "Broadcom NetXtreme II BCM5709 1000Base-T" }, 144 145 /* BCM5709S controllers and OEM boards. */ 146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d, 147 "HP NC382m DP 1GbE Multifunction BL-c Adapter" }, 148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056, 149 "HP NC382i DP Multifunction Gigabit Server Adapter" }, 150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID, 151 "Broadcom NetXtreme II BCM5709 1000Base-SX" }, 152 153 /* BCM5716 controllers and OEM boards. */ 154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID, 155 "Broadcom NetXtreme II BCM5716 1000Base-T" }, 156 157 { 0, 0, 0, 0, NULL } 158 }; 159 160 161 /****************************************************************************/ 162 /* Supported Flash NVRAM device data. */ 163 /****************************************************************************/ 164 static struct flash_spec flash_table[] = 165 { 166 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE) 167 #define NONBUFFERED_FLAGS (BCE_NV_WREN) 168 169 /* Slow EEPROM */ 170 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 171 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 172 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 173 "EEPROM - slow"}, 174 /* Expansion entry 0001 */ 175 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 176 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 177 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 178 "Entry 0001"}, 179 /* Saifun SA25F010 (non-buffered flash) */ 180 /* strap, cfg1, & write1 need updates */ 181 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 184 "Non-buffered flash (128kB)"}, 185 /* Saifun SA25F020 (non-buffered flash) */ 186 /* strap, cfg1, & write1 need updates */ 187 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 189 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 190 "Non-buffered flash (256kB)"}, 191 /* Expansion entry 0100 */ 192 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 195 "Entry 0100"}, 196 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 197 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 198 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 199 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 200 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 201 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 202 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 203 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 204 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 205 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 206 /* Saifun SA25F005 (non-buffered flash) */ 207 /* strap, cfg1, & write1 need updates */ 208 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 210 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 211 "Non-buffered flash (64kB)"}, 212 /* Fast EEPROM */ 213 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 214 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 215 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 216 "EEPROM - fast"}, 217 /* Expansion entry 1001 */ 218 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 221 "Entry 1001"}, 222 /* Expansion entry 1010 */ 223 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 226 "Entry 1010"}, 227 /* ATMEL AT45DB011B (buffered flash) */ 228 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 230 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 231 "Buffered flash (128kB)"}, 232 /* Expansion entry 1100 */ 233 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 234 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 235 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 236 "Entry 1100"}, 237 /* Expansion entry 1101 */ 238 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 241 "Entry 1101"}, 242 /* Ateml Expansion entry 1110 */ 243 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 244 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 245 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 246 "Entry 1110 (Atmel)"}, 247 /* ATMEL AT45DB021B (buffered flash) */ 248 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 251 "Buffered flash (256kB)"}, 252 }; 253 254 /* 255 * The BCM5709 controllers transparently handle the 256 * differences between Atmel 264 byte pages and all 257 * flash devices which use 256 byte pages, so no 258 * logical-to-physical mapping is required in the 259 * driver. 260 */ 261 static struct flash_spec flash_5709 = { 262 .flags = BCE_NV_BUFFERED, 263 .page_bits = BCM5709_FLASH_PAGE_BITS, 264 .page_size = BCM5709_FLASH_PAGE_SIZE, 265 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK, 266 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2, 267 .name = "5709/5716 buffered flash (256kB)", 268 }; 269 270 271 /****************************************************************************/ 272 /* FreeBSD device entry points. */ 273 /****************************************************************************/ 274 static int bce_probe (device_t); 275 static int bce_attach (device_t); 276 static int bce_detach (device_t); 277 static int bce_shutdown (device_t); 278 279 280 /****************************************************************************/ 281 /* BCE Debug Data Structure Dump Routines */ 282 /****************************************************************************/ 283 #ifdef BCE_DEBUG 284 static u32 bce_reg_rd (struct bce_softc *, u32); 285 static void bce_reg_wr (struct bce_softc *, u32, u32); 286 static void bce_reg_wr16 (struct bce_softc *, u32, u16); 287 static u32 bce_ctx_rd (struct bce_softc *, u32, u32); 288 static void bce_dump_enet (struct bce_softc *, struct mbuf *); 289 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 290 static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int); 291 static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int); 292 static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int); 293 static void bce_dump_txbd (struct bce_softc *, 294 int, struct tx_bd *); 295 static void bce_dump_rxbd (struct bce_softc *, 296 int, struct rx_bd *); 297 static void bce_dump_pgbd (struct bce_softc *, 298 int, struct rx_bd *); 299 static void bce_dump_l2fhdr (struct bce_softc *, 300 int, struct l2_fhdr *); 301 static void bce_dump_ctx (struct bce_softc *, u16); 302 static void bce_dump_ftqs (struct bce_softc *); 303 static void bce_dump_tx_chain (struct bce_softc *, u16, int); 304 static void bce_dump_rx_bd_chain (struct bce_softc *, u16, int); 305 static void bce_dump_pg_chain (struct bce_softc *, u16, int); 306 static void bce_dump_status_block (struct bce_softc *); 307 static void bce_dump_stats_block (struct bce_softc *); 308 static void bce_dump_driver_state (struct bce_softc *); 309 static void bce_dump_hw_state (struct bce_softc *); 310 static void bce_dump_shmem_state (struct bce_softc *); 311 static void bce_dump_mq_regs (struct bce_softc *); 312 static void bce_dump_bc_state (struct bce_softc *); 313 static void bce_dump_txp_state (struct bce_softc *, int); 314 static void bce_dump_rxp_state (struct bce_softc *, int); 315 static void bce_dump_tpat_state (struct bce_softc *, int); 316 static void bce_dump_cp_state (struct bce_softc *, int); 317 static void bce_dump_com_state (struct bce_softc *, int); 318 static void bce_dump_rv2p_state (struct bce_softc *); 319 static void bce_breakpoint (struct bce_softc *); 320 #endif /*BCE_DEBUG */ 321 322 323 /****************************************************************************/ 324 /* BCE Register/Memory Access Routines */ 325 /****************************************************************************/ 326 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 327 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 328 static void bce_shmem_wr (struct bce_softc *, u32, u32); 329 static u32 bce_shmem_rd (struct bce_softc *, u32); 330 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 331 static int bce_miibus_read_reg (device_t, int, int); 332 static int bce_miibus_write_reg (device_t, int, int, int); 333 static void bce_miibus_statchg (device_t); 334 335 #ifdef BCE_DEBUG 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS); 337 #ifdef BCE_NVRAM_WRITE_SUPPORT 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS); 339 #endif 340 #endif 341 342 /****************************************************************************/ 343 /* BCE NVRAM Access Routines */ 344 /****************************************************************************/ 345 static int bce_acquire_nvram_lock (struct bce_softc *); 346 static int bce_release_nvram_lock (struct bce_softc *); 347 static void bce_enable_nvram_access(struct bce_softc *); 348 static void bce_disable_nvram_access(struct bce_softc *); 349 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 350 static int bce_init_nvram (struct bce_softc *); 351 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 352 static int bce_nvram_test (struct bce_softc *); 353 #ifdef BCE_NVRAM_WRITE_SUPPORT 354 static int bce_enable_nvram_write (struct bce_softc *); 355 static void bce_disable_nvram_write(struct bce_softc *); 356 static int bce_nvram_erase_page (struct bce_softc *, u32); 357 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 358 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 359 #endif 360 361 /****************************************************************************/ 362 /* */ 363 /****************************************************************************/ 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int); 365 static void bce_get_media (struct bce_softc *); 366 static void bce_init_media (struct bce_softc *); 367 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 368 static int bce_dma_alloc (device_t); 369 static void bce_dma_free (struct bce_softc *); 370 static void bce_release_resources (struct bce_softc *); 371 372 /****************************************************************************/ 373 /* BCE Firmware Synchronization and Load */ 374 /****************************************************************************/ 375 static int bce_fw_sync (struct bce_softc *, u32); 376 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 377 static void bce_load_cpu_fw (struct bce_softc *, 378 struct cpu_reg *, struct fw_info *); 379 static void bce_start_cpu (struct bce_softc *, struct cpu_reg *); 380 static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *); 381 static void bce_start_rxp_cpu (struct bce_softc *); 382 static void bce_init_rxp_cpu (struct bce_softc *); 383 static void bce_init_txp_cpu (struct bce_softc *); 384 static void bce_init_tpat_cpu (struct bce_softc *); 385 static void bce_init_cp_cpu (struct bce_softc *); 386 static void bce_init_com_cpu (struct bce_softc *); 387 static void bce_init_cpus (struct bce_softc *); 388 389 static void bce_print_adapter_info (struct bce_softc *); 390 static void bce_probe_pci_caps (device_t, struct bce_softc *); 391 static void bce_stop (struct bce_softc *); 392 static int bce_reset (struct bce_softc *, u32); 393 static int bce_chipinit (struct bce_softc *); 394 static int bce_blockinit (struct bce_softc *); 395 396 static int bce_init_tx_chain (struct bce_softc *); 397 static void bce_free_tx_chain (struct bce_softc *); 398 399 static int bce_get_rx_buf (struct bce_softc *, 400 struct mbuf *, u16 *, u16 *, u32 *); 401 static int bce_init_rx_chain (struct bce_softc *); 402 static void bce_fill_rx_chain (struct bce_softc *); 403 static void bce_free_rx_chain (struct bce_softc *); 404 405 static int bce_get_pg_buf (struct bce_softc *, 406 struct mbuf *, u16 *, u16 *); 407 static int bce_init_pg_chain (struct bce_softc *); 408 static void bce_fill_pg_chain (struct bce_softc *); 409 static void bce_free_pg_chain (struct bce_softc *); 410 411 static struct mbuf *bce_tso_setup (struct bce_softc *, 412 struct mbuf **, u16 *); 413 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 414 static void bce_start_locked (struct ifnet *); 415 static void bce_start (struct ifnet *); 416 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 417 static void bce_watchdog (struct bce_softc *); 418 static int bce_ifmedia_upd (struct ifnet *); 419 static int bce_ifmedia_upd_locked (struct ifnet *); 420 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 421 static void bce_init_locked (struct bce_softc *); 422 static void bce_init (void *); 423 static void bce_mgmt_init_locked (struct bce_softc *sc); 424 425 static int bce_init_ctx (struct bce_softc *); 426 static void bce_get_mac_addr (struct bce_softc *); 427 static void bce_set_mac_addr (struct bce_softc *); 428 static void bce_phy_intr (struct bce_softc *); 429 static inline u16 bce_get_hw_rx_cons (struct bce_softc *); 430 static void bce_rx_intr (struct bce_softc *); 431 static void bce_tx_intr (struct bce_softc *); 432 static void bce_disable_intr (struct bce_softc *); 433 static void bce_enable_intr (struct bce_softc *, int); 434 435 static void bce_intr (void *); 436 static void bce_set_rx_mode (struct bce_softc *); 437 static void bce_stats_update (struct bce_softc *); 438 static void bce_tick (void *); 439 static void bce_pulse (void *); 440 static void bce_add_sysctls (struct bce_softc *); 441 442 443 /****************************************************************************/ 444 /* FreeBSD device dispatch table. */ 445 /****************************************************************************/ 446 static device_method_t bce_methods[] = { 447 /* Device interface (device_if.h) */ 448 DEVMETHOD(device_probe, bce_probe), 449 DEVMETHOD(device_attach, bce_attach), 450 DEVMETHOD(device_detach, bce_detach), 451 DEVMETHOD(device_shutdown, bce_shutdown), 452 /* Supported by device interface but not used here. */ 453 /* DEVMETHOD(device_identify, bce_identify), */ 454 /* DEVMETHOD(device_suspend, bce_suspend), */ 455 /* DEVMETHOD(device_resume, bce_resume), */ 456 /* DEVMETHOD(device_quiesce, bce_quiesce), */ 457 458 /* Bus interface (bus_if.h) */ 459 DEVMETHOD(bus_print_child, bus_generic_print_child), 460 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 461 462 /* MII interface (miibus_if.h) */ 463 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 464 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 465 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 466 /* Supported by MII interface but not used here. */ 467 /* DEVMETHOD(miibus_linkchg, bce_miibus_linkchg), */ 468 /* DEVMETHOD(miibus_mediainit, bce_miibus_mediainit), */ 469 470 { 0, 0 } 471 }; 472 473 static driver_t bce_driver = { 474 "bce", 475 bce_methods, 476 sizeof(struct bce_softc) 477 }; 478 479 static devclass_t bce_devclass; 480 481 MODULE_DEPEND(bce, pci, 1, 1, 1); 482 MODULE_DEPEND(bce, ether, 1, 1, 1); 483 MODULE_DEPEND(bce, miibus, 1, 1, 1); 484 485 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 486 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 487 488 489 /****************************************************************************/ 490 /* Tunable device values */ 491 /****************************************************************************/ 492 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 493 494 /* Allowable values are TRUE or FALSE */ 495 static int bce_verbose = TRUE; 496 TUNABLE_INT("hw.bce.verbose", &bce_verbose); 497 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0, 498 "Verbose output enable/disable"); 499 500 /* Allowable values are TRUE or FALSE */ 501 static int bce_tso_enable = TRUE; 502 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 503 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 504 "TSO Enable/Disable"); 505 506 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 507 /* ToDo: Add MSI-X support. */ 508 static int bce_msi_enable = 1; 509 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 510 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 511 "MSI-X|MSI|INTx selector"); 512 513 /* Allowable values are 1, 2, 4, 8. */ 514 static int bce_rx_pages = DEFAULT_RX_PAGES; 515 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages); 516 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0, 517 "Receive buffer descriptor pages (1 page = 255 buffer descriptors)"); 518 519 /* Allowable values are 1, 2, 4, 8. */ 520 static int bce_tx_pages = DEFAULT_TX_PAGES; 521 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages); 522 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0, 523 "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)"); 524 525 /* Allowable values are TRUE or FALSE. */ 526 static int bce_hdr_split = TRUE; 527 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split); 528 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0, 529 "Frame header/payload splitting Enable/Disable"); 530 531 /* Allowable values are TRUE or FALSE. */ 532 static int bce_strict_rx_mtu = FALSE; 533 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu); 534 SYSCTL_UINT(_hw_bce, OID_AUTO, loose_rx_mtu, CTLFLAG_RDTUN, 535 &bce_strict_rx_mtu, 0, 536 "Enable/Disable strict RX frame size checking"); 537 538 /* Allowable values are 0 ... 100 */ 539 #ifdef BCE_DEBUG 540 /* Generate 1 interrupt for every transmit completion. */ 541 static int bce_tx_quick_cons_trip_int = 1; 542 #else 543 /* Generate 1 interrupt for every 20 transmit completions. */ 544 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT; 545 #endif 546 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int); 547 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN, 548 &bce_tx_quick_cons_trip_int, 0, 549 "Transmit BD trip point during interrupts"); 550 551 /* Allowable values are 0 ... 100 */ 552 /* Generate 1 interrupt for every transmit completion. */ 553 #ifdef BCE_DEBUG 554 static int bce_tx_quick_cons_trip = 1; 555 #else 556 /* Generate 1 interrupt for every 20 transmit completions. */ 557 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 558 #endif 559 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip); 560 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN, 561 &bce_tx_quick_cons_trip, 0, 562 "Transmit BD trip point"); 563 564 /* Allowable values are 0 ... 100 */ 565 #ifdef BCE_DEBUG 566 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 567 static int bce_tx_ticks_int = 0; 568 #else 569 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 570 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT; 571 #endif 572 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int); 573 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN, 574 &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt"); 575 576 /* Allowable values are 0 ... 100 */ 577 #ifdef BCE_DEBUG 578 /* Generate an interrupt if 0us have elapsed since the last TX completion. */ 579 static int bce_tx_ticks = 0; 580 #else 581 /* Generate an interrupt if 80us have elapsed since the last TX completion. */ 582 static int bce_tx_ticks = DEFAULT_TX_TICKS; 583 #endif 584 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks); 585 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, 586 &bce_tx_ticks, 0, "Transmit ticks count"); 587 588 /* Allowable values are 1 ... 100 */ 589 #ifdef BCE_DEBUG 590 /* Generate 1 interrupt for every received frame. */ 591 static int bce_rx_quick_cons_trip_int = 1; 592 #else 593 /* Generate 1 interrupt for every 6 received frames. */ 594 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT; 595 #endif 596 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int); 597 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN, 598 &bce_rx_quick_cons_trip_int, 0, 599 "Receive BD trip point duirng interrupts"); 600 601 /* Allowable values are 1 ... 100 */ 602 #ifdef BCE_DEBUG 603 /* Generate 1 interrupt for every received frame. */ 604 static int bce_rx_quick_cons_trip = 1; 605 #else 606 /* Generate 1 interrupt for every 6 received frames. */ 607 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 608 #endif 609 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip); 610 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN, 611 &bce_rx_quick_cons_trip, 0, 612 "Receive BD trip point"); 613 614 /* Allowable values are 0 ... 100 */ 615 #ifdef BCE_DEBUG 616 /* Generate an int. if 0us have elapsed since the last received frame. */ 617 static int bce_rx_ticks_int = 0; 618 #else 619 /* Generate an int. if 18us have elapsed since the last received frame. */ 620 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 621 #endif 622 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int); 623 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN, 624 &bce_rx_ticks_int, 0, "Receive ticks count during interrupt"); 625 626 /* Allowable values are 0 ... 100 */ 627 #ifdef BCE_DEBUG 628 /* Generate an int. if 0us have elapsed since the last received frame. */ 629 static int bce_rx_ticks = 0; 630 #else 631 /* Generate an int. if 18us have elapsed since the last received frame. */ 632 static int bce_rx_ticks = DEFAULT_RX_TICKS; 633 #endif 634 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks); 635 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, 636 &bce_rx_ticks, 0, "Receive ticks count"); 637 638 639 /****************************************************************************/ 640 /* Device probe function. */ 641 /* */ 642 /* Compares the device to the driver's list of supported devices and */ 643 /* reports back to the OS whether this is the right driver for the device. */ 644 /* */ 645 /* Returns: */ 646 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 647 /****************************************************************************/ 648 static int 649 bce_probe(device_t dev) 650 { 651 struct bce_type *t; 652 struct bce_softc *sc; 653 char *descbuf; 654 u16 vid = 0, did = 0, svid = 0, sdid = 0; 655 656 t = bce_devs; 657 658 sc = device_get_softc(dev); 659 bzero(sc, sizeof(struct bce_softc)); 660 sc->bce_unit = device_get_unit(dev); 661 sc->bce_dev = dev; 662 663 /* Get the data for the device to be probed. */ 664 vid = pci_get_vendor(dev); 665 did = pci_get_device(dev); 666 svid = pci_get_subvendor(dev); 667 sdid = pci_get_subdevice(dev); 668 669 DBPRINT(sc, BCE_EXTREME_LOAD, 670 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 671 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 672 673 /* Look through the list of known devices for a match. */ 674 while(t->bce_name != NULL) { 675 676 if ((vid == t->bce_vid) && (did == t->bce_did) && 677 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 678 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 679 680 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 681 682 if (descbuf == NULL) 683 return(ENOMEM); 684 685 /* Print out the device identity. */ 686 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 687 t->bce_name, (((pci_read_config(dev, 688 PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 689 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 690 691 device_set_desc_copy(dev, descbuf); 692 free(descbuf, M_TEMP); 693 return(BUS_PROBE_DEFAULT); 694 } 695 t++; 696 } 697 698 return(ENXIO); 699 } 700 701 702 /****************************************************************************/ 703 /* PCI Capabilities Probe Function. */ 704 /* */ 705 /* Walks the PCI capabiites list for the device to find what features are */ 706 /* supported. */ 707 /* */ 708 /* Returns: */ 709 /* None. */ 710 /****************************************************************************/ 711 static void 712 bce_print_adapter_info(struct bce_softc *sc) 713 { 714 int i = 0; 715 716 DBENTER(BCE_VERBOSE_LOAD); 717 718 if (bce_verbose || bootverbose) { 719 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 720 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 721 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 722 723 724 /* Bus info. */ 725 if (sc->bce_flags & BCE_PCIE_FLAG) { 726 printf("Bus (PCIe x%d, ", sc->link_width); 727 switch (sc->link_speed) { 728 case 1: printf("2.5Gbps); "); break; 729 case 2: printf("5Gbps); "); break; 730 default: printf("Unknown link speed); "); 731 } 732 } else { 733 printf("Bus (PCI%s, %s, %dMHz); ", 734 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 735 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? 736 "32-bit" : "64-bit"), sc->bus_speed_mhz); 737 } 738 739 /* Firmware version and device features. */ 740 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (", 741 sc->bce_bc_ver, sc->rx_pages, sc->tx_pages, 742 (bce_hdr_split == TRUE ? sc->pg_pages: 0)); 743 744 if (bce_hdr_split == TRUE) { 745 printf("SPLT"); 746 i++; 747 } 748 749 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 750 if (i > 0) printf("|"); 751 printf("MSI"); i++; 752 } 753 754 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 755 if (i > 0) printf("|"); 756 printf("MSI-X"); i++; 757 } 758 759 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) { 760 if (i > 0) printf("|"); 761 printf("2.5G"); i++; 762 } 763 764 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 765 if (i > 0) printf("|"); 766 printf("MFW); MFW (%s)\n", sc->bce_mfw_ver); 767 } else { 768 printf(")\n"); 769 } 770 771 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n", 772 sc->bce_rx_quick_cons_trip_int, 773 sc->bce_rx_quick_cons_trip, 774 sc->bce_rx_ticks_int, 775 sc->bce_rx_ticks, 776 sc->bce_tx_quick_cons_trip_int, 777 sc->bce_tx_quick_cons_trip, 778 sc->bce_tx_ticks_int, 779 sc->bce_tx_ticks); 780 781 } 782 783 DBEXIT(BCE_VERBOSE_LOAD); 784 } 785 786 787 /****************************************************************************/ 788 /* PCI Capabilities Probe Function. */ 789 /* */ 790 /* Walks the PCI capabiites list for the device to find what features are */ 791 /* supported. */ 792 /* */ 793 /* Returns: */ 794 /* None. */ 795 /****************************************************************************/ 796 static void 797 bce_probe_pci_caps(device_t dev, struct bce_softc *sc) 798 { 799 u32 reg; 800 801 DBENTER(BCE_VERBOSE_LOAD); 802 803 /* Check if PCI-X capability is enabled. */ 804 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) { 805 if (reg != 0) 806 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG; 807 } 808 809 /* Check if PCIe capability is enabled. */ 810 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 811 if (reg != 0) { 812 u16 link_status = pci_read_config(dev, reg + 0x12, 2); 813 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = " 814 "0x%08X\n", link_status); 815 sc->link_speed = link_status & 0xf; 816 sc->link_width = (link_status >> 4) & 0x3f; 817 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG; 818 sc->bce_flags |= BCE_PCIE_FLAG; 819 } 820 } 821 822 /* Check if MSI capability is enabled. */ 823 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) { 824 if (reg != 0) 825 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG; 826 } 827 828 /* Check if MSI-X capability is enabled. */ 829 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) { 830 if (reg != 0) 831 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG; 832 } 833 834 DBEXIT(BCE_VERBOSE_LOAD); 835 } 836 837 838 /****************************************************************************/ 839 /* Load and validate user tunable settings. */ 840 /* */ 841 /* Returns: */ 842 /* Nothing. */ 843 /****************************************************************************/ 844 static void 845 bce_set_tunables(struct bce_softc *sc) 846 { 847 /* Set sysctl values for RX page count. */ 848 switch (bce_rx_pages) { 849 case 1: 850 /* fall-through */ 851 case 2: 852 /* fall-through */ 853 case 4: 854 /* fall-through */ 855 case 8: 856 sc->rx_pages = bce_rx_pages; 857 break; 858 default: 859 sc->rx_pages = DEFAULT_RX_PAGES; 860 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 861 "hw.bce.rx_pages! Setting default of %d.\n", 862 __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES); 863 } 864 865 /* ToDo: Consider allowing user setting for pg_pages. */ 866 sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES); 867 868 /* Set sysctl values for TX page count. */ 869 switch (bce_tx_pages) { 870 case 1: 871 /* fall-through */ 872 case 2: 873 /* fall-through */ 874 case 4: 875 /* fall-through */ 876 case 8: 877 sc->tx_pages = bce_tx_pages; 878 break; 879 default: 880 sc->tx_pages = DEFAULT_TX_PAGES; 881 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 882 "hw.bce.tx_pages! Setting default of %d.\n", 883 __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES); 884 } 885 886 /* 887 * Validate the TX trip point (i.e. the number of 888 * TX completions before a status block update is 889 * generated and an interrupt is asserted. 890 */ 891 if (bce_tx_quick_cons_trip_int <= 100) { 892 sc->bce_tx_quick_cons_trip_int = 893 bce_tx_quick_cons_trip_int; 894 } else { 895 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 896 "hw.bce.tx_quick_cons_trip_int! Setting default of %d.\n", 897 __FILE__, __LINE__, bce_tx_quick_cons_trip_int, 898 DEFAULT_TX_QUICK_CONS_TRIP_INT); 899 sc->bce_tx_quick_cons_trip_int = 900 DEFAULT_TX_QUICK_CONS_TRIP_INT; 901 } 902 903 if (bce_tx_quick_cons_trip <= 100) { 904 sc->bce_tx_quick_cons_trip = 905 bce_tx_quick_cons_trip; 906 } else { 907 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 908 "hw.bce.tx_quick_cons_trip! Setting default of %d.\n", 909 __FILE__, __LINE__, bce_tx_quick_cons_trip, 910 DEFAULT_TX_QUICK_CONS_TRIP); 911 sc->bce_tx_quick_cons_trip = 912 DEFAULT_TX_QUICK_CONS_TRIP; 913 } 914 915 /* 916 * Validate the TX ticks count (i.e. the maximum amount 917 * of time to wait after the last TX completion has 918 * occurred before a status block update is generated 919 * and an interrupt is asserted. 920 */ 921 if (bce_tx_ticks_int <= 100) { 922 sc->bce_tx_ticks_int = 923 bce_tx_ticks_int; 924 } else { 925 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 926 "hw.bce.tx_ticks_int! Setting default of %d.\n", 927 __FILE__, __LINE__, bce_tx_ticks_int, 928 DEFAULT_TX_TICKS_INT); 929 sc->bce_tx_ticks_int = 930 DEFAULT_TX_TICKS_INT; 931 } 932 933 if (bce_tx_ticks <= 100) { 934 sc->bce_tx_ticks = 935 bce_tx_ticks; 936 } else { 937 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 938 "hw.bce.tx_ticks! Setting default of %d.\n", 939 __FILE__, __LINE__, bce_tx_ticks, 940 DEFAULT_TX_TICKS); 941 sc->bce_tx_ticks = 942 DEFAULT_TX_TICKS; 943 } 944 945 /* 946 * Validate the RX trip point (i.e. the number of 947 * RX frames received before a status block update is 948 * generated and an interrupt is asserted. 949 */ 950 if (bce_rx_quick_cons_trip_int <= 100) { 951 sc->bce_rx_quick_cons_trip_int = 952 bce_rx_quick_cons_trip_int; 953 } else { 954 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 955 "hw.bce.rx_quick_cons_trip_int! Setting default of %d.\n", 956 __FILE__, __LINE__, bce_rx_quick_cons_trip_int, 957 DEFAULT_RX_QUICK_CONS_TRIP_INT); 958 sc->bce_rx_quick_cons_trip_int = 959 DEFAULT_RX_QUICK_CONS_TRIP_INT; 960 } 961 962 if (bce_rx_quick_cons_trip <= 100) { 963 sc->bce_rx_quick_cons_trip = 964 bce_rx_quick_cons_trip; 965 } else { 966 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 967 "hw.bce.rx_quick_cons_trip! Setting default of %d.\n", 968 __FILE__, __LINE__, bce_rx_quick_cons_trip, 969 DEFAULT_RX_QUICK_CONS_TRIP); 970 sc->bce_rx_quick_cons_trip = 971 DEFAULT_RX_QUICK_CONS_TRIP; 972 } 973 974 /* 975 * Validate the RX ticks count (i.e. the maximum amount 976 * of time to wait after the last RX frame has been 977 * received before a status block update is generated 978 * and an interrupt is asserted. 979 */ 980 if (bce_rx_ticks_int <= 100) { 981 sc->bce_rx_ticks_int = bce_rx_ticks_int; 982 } else { 983 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 984 "hw.bce.rx_ticks_int! Setting default of %d.\n", 985 __FILE__, __LINE__, bce_rx_ticks_int, 986 DEFAULT_RX_TICKS_INT); 987 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT; 988 } 989 990 if (bce_rx_ticks <= 100) { 991 sc->bce_rx_ticks = bce_rx_ticks; 992 } else { 993 BCE_PRINTF("%s(%d): Illegal value (%d) specified for " 994 "hw.bce.rx_ticks! Setting default of %d.\n", 995 __FILE__, __LINE__, bce_rx_ticks, 996 DEFAULT_RX_TICKS); 997 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 998 } 999 1000 /* Disabling both RX ticks and RX trips will prevent interrupts. */ 1001 if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) { 1002 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and " 1003 "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n", 1004 __FILE__, __LINE__); 1005 sc->bce_rx_ticks = DEFAULT_RX_TICKS; 1006 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP; 1007 } 1008 1009 /* Disabling both TX ticks and TX trips will prevent interrupts. */ 1010 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) { 1011 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and " 1012 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n", 1013 __FILE__, __LINE__); 1014 sc->bce_tx_ticks = DEFAULT_TX_TICKS; 1015 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP; 1016 } 1017 1018 } 1019 1020 1021 /****************************************************************************/ 1022 /* Device attach function. */ 1023 /* */ 1024 /* Allocates device resources, performs secondary chip identification, */ 1025 /* resets and initializes the hardware, and initializes driver instance */ 1026 /* variables. */ 1027 /* */ 1028 /* Returns: */ 1029 /* 0 on success, positive value on failure. */ 1030 /****************************************************************************/ 1031 static int 1032 bce_attach(device_t dev) 1033 { 1034 struct bce_softc *sc; 1035 struct ifnet *ifp; 1036 u32 val; 1037 int error, rid, rc = 0; 1038 1039 sc = device_get_softc(dev); 1040 sc->bce_dev = dev; 1041 1042 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1043 1044 sc->bce_unit = device_get_unit(dev); 1045 1046 /* Set initial device and PHY flags */ 1047 sc->bce_flags = 0; 1048 sc->bce_phy_flags = 0; 1049 1050 bce_set_tunables(sc); 1051 1052 pci_enable_busmaster(dev); 1053 1054 /* Allocate PCI memory resources. */ 1055 rid = PCIR_BAR(0); 1056 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1057 &rid, RF_ACTIVE); 1058 1059 if (sc->bce_res_mem == NULL) { 1060 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 1061 __FILE__, __LINE__); 1062 rc = ENXIO; 1063 goto bce_attach_fail; 1064 } 1065 1066 /* Get various resource handles. */ 1067 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 1068 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 1069 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 1070 1071 bce_probe_pci_caps(dev, sc); 1072 1073 rid = 1; 1074 #if 0 1075 /* Try allocating MSI-X interrupts. */ 1076 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) && 1077 (bce_msi_enable >= 2) && 1078 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1079 &rid, RF_ACTIVE)) != NULL)) { 1080 1081 msi_needed = sc->bce_msi_count = 1; 1082 1083 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) || 1084 (sc->bce_msi_count != msi_needed)) { 1085 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d," 1086 "Received = %d, error = %d\n", __FILE__, __LINE__, 1087 msi_needed, sc->bce_msi_count, error); 1088 sc->bce_msi_count = 0; 1089 pci_release_msi(dev); 1090 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1091 sc->bce_res_irq); 1092 sc->bce_res_irq = NULL; 1093 } else { 1094 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n", 1095 __FUNCTION__); 1096 sc->bce_flags |= BCE_USING_MSIX_FLAG; 1097 sc->bce_intr = bce_intr; 1098 } 1099 } 1100 #endif 1101 1102 /* Try allocating a MSI interrupt. */ 1103 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) && 1104 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) { 1105 sc->bce_msi_count = 1; 1106 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) { 1107 BCE_PRINTF("%s(%d): MSI allocation failed! " 1108 "error = %d\n", __FILE__, __LINE__, error); 1109 sc->bce_msi_count = 0; 1110 pci_release_msi(dev); 1111 } else { 1112 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI " 1113 "interrupt.\n", __FUNCTION__); 1114 sc->bce_flags |= BCE_USING_MSI_FLAG; 1115 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 1116 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG; 1117 sc->bce_irq_rid = 1; 1118 sc->bce_intr = bce_intr; 1119 } 1120 } 1121 1122 /* Try allocating a legacy interrupt. */ 1123 if (sc->bce_msi_count == 0) { 1124 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n", 1125 __FUNCTION__); 1126 rid = 0; 1127 sc->bce_intr = bce_intr; 1128 } 1129 1130 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 1131 &rid, RF_SHAREABLE | RF_ACTIVE); 1132 1133 sc->bce_irq_rid = rid; 1134 1135 /* Report any IRQ allocation errors. */ 1136 if (sc->bce_res_irq == NULL) { 1137 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 1138 __FILE__, __LINE__); 1139 rc = ENXIO; 1140 goto bce_attach_fail; 1141 } 1142 1143 /* Initialize mutex for the current device instance. */ 1144 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 1145 1146 /* 1147 * Configure byte swap and enable indirect register access. 1148 * Rely on CPU to do target byte swapping on big endian systems. 1149 * Access to registers outside of PCI configurtion space are not 1150 * valid until this is done. 1151 */ 1152 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 1153 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 1154 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 1155 1156 /* Save ASIC revsion info. */ 1157 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 1158 1159 /* Weed out any non-production controller revisions. */ 1160 switch(BCE_CHIP_ID(sc)) { 1161 case BCE_CHIP_ID_5706_A0: 1162 case BCE_CHIP_ID_5706_A1: 1163 case BCE_CHIP_ID_5708_A0: 1164 case BCE_CHIP_ID_5708_B0: 1165 case BCE_CHIP_ID_5709_A0: 1166 case BCE_CHIP_ID_5709_B0: 1167 case BCE_CHIP_ID_5709_B1: 1168 case BCE_CHIP_ID_5709_B2: 1169 BCE_PRINTF("%s(%d): Unsupported controller " 1170 "revision (%c%d)!\n", __FILE__, __LINE__, 1171 (((pci_read_config(dev, PCIR_REVID, 4) & 1172 0xf0) >> 4) + 'A'), (pci_read_config(dev, 1173 PCIR_REVID, 4) & 0xf)); 1174 rc = ENODEV; 1175 goto bce_attach_fail; 1176 } 1177 1178 /* 1179 * The embedded PCIe to PCI-X bridge (EPB) 1180 * in the 5708 cannot address memory above 1181 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 1182 */ 1183 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 1184 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 1185 else 1186 sc->max_bus_addr = BUS_SPACE_MAXADDR; 1187 1188 /* 1189 * Find the base address for shared memory access. 1190 * Newer versions of bootcode use a signature and offset 1191 * while older versions use a fixed address. 1192 */ 1193 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 1194 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 1195 /* Multi-port devices use different offsets in shared memory. */ 1196 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 + 1197 (pci_get_function(sc->bce_dev) << 2)); 1198 else 1199 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 1200 1201 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 1202 __FUNCTION__, sc->bce_shmem_base); 1203 1204 /* Fetch the bootcode revision. */ 1205 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV); 1206 for (int i = 0, j = 0; i < 3; i++) { 1207 u8 num; 1208 1209 num = (u8) (val >> (24 - (i * 8))); 1210 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) { 1211 if (num >= k || !skip0 || k == 1) { 1212 sc->bce_bc_ver[j++] = (num / k) + '0'; 1213 skip0 = 0; 1214 } 1215 } 1216 1217 if (i != 2) 1218 sc->bce_bc_ver[j++] = '.'; 1219 } 1220 1221 /* Check if any management firwmare is enabled. */ 1222 val = bce_shmem_rd(sc, BCE_PORT_FEATURE); 1223 if (val & BCE_PORT_FEATURE_ASF_ENABLED) { 1224 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 1225 1226 /* Allow time for firmware to enter the running state. */ 1227 for (int i = 0; i < 30; i++) { 1228 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1229 if (val & BCE_CONDITION_MFW_RUN_MASK) 1230 break; 1231 DELAY(10000); 1232 } 1233 1234 /* Check if management firmware is running. */ 1235 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 1236 val &= BCE_CONDITION_MFW_RUN_MASK; 1237 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) && 1238 (val != BCE_CONDITION_MFW_RUN_NONE)) { 1239 u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR); 1240 int i = 0; 1241 1242 /* Read the management firmware version string. */ 1243 for (int j = 0; j < 3; j++) { 1244 val = bce_reg_rd_ind(sc, addr + j * 4); 1245 val = bswap32(val); 1246 memcpy(&sc->bce_mfw_ver[i], &val, 4); 1247 i += 4; 1248 } 1249 } else { 1250 /* May cause firmware synchronization timeouts. */ 1251 BCE_PRINTF("%s(%d): Management firmware enabled " 1252 "but not running!\n", __FILE__, __LINE__); 1253 strcpy(sc->bce_mfw_ver, "NOT RUNNING!"); 1254 1255 /* ToDo: Any action the driver should take? */ 1256 } 1257 } 1258 1259 /* Get PCI bus information (speed and type). */ 1260 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 1261 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 1262 u32 clkreg; 1263 1264 sc->bce_flags |= BCE_PCIX_FLAG; 1265 1266 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 1267 1268 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 1269 switch (clkreg) { 1270 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 1271 sc->bus_speed_mhz = 133; 1272 break; 1273 1274 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 1275 sc->bus_speed_mhz = 100; 1276 break; 1277 1278 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 1279 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 1280 sc->bus_speed_mhz = 66; 1281 break; 1282 1283 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 1284 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 1285 sc->bus_speed_mhz = 50; 1286 break; 1287 1288 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 1289 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 1290 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 1291 sc->bus_speed_mhz = 33; 1292 break; 1293 } 1294 } else { 1295 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 1296 sc->bus_speed_mhz = 66; 1297 else 1298 sc->bus_speed_mhz = 33; 1299 } 1300 1301 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 1302 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 1303 1304 /* Reset controller and announce to bootcode that driver is present. */ 1305 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 1306 BCE_PRINTF("%s(%d): Controller reset failed!\n", 1307 __FILE__, __LINE__); 1308 rc = ENXIO; 1309 goto bce_attach_fail; 1310 } 1311 1312 /* Initialize the controller. */ 1313 if (bce_chipinit(sc)) { 1314 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 1315 __FILE__, __LINE__); 1316 rc = ENXIO; 1317 goto bce_attach_fail; 1318 } 1319 1320 /* Perform NVRAM test. */ 1321 if (bce_nvram_test(sc)) { 1322 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 1323 __FILE__, __LINE__); 1324 rc = ENXIO; 1325 goto bce_attach_fail; 1326 } 1327 1328 /* Fetch the permanent Ethernet MAC address. */ 1329 bce_get_mac_addr(sc); 1330 1331 /* 1332 * Trip points control how many BDs 1333 * should be ready before generating an 1334 * interrupt while ticks control how long 1335 * a BD can sit in the chain before 1336 * generating an interrupt. Set the default 1337 * values for the RX and TX chains. 1338 */ 1339 1340 /* Not used for L2. */ 1341 sc->bce_comp_prod_trip_int = 0; 1342 sc->bce_comp_prod_trip = 0; 1343 sc->bce_com_ticks_int = 0; 1344 sc->bce_com_ticks = 0; 1345 sc->bce_cmd_ticks_int = 0; 1346 sc->bce_cmd_ticks = 0; 1347 1348 /* Update statistics once every second. */ 1349 sc->bce_stats_ticks = 1000000 & 0xffff00; 1350 1351 /* Find the media type for the adapter. */ 1352 bce_get_media(sc); 1353 1354 /* Store data needed by PHY driver for backplane applications */ 1355 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 1356 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG); 1357 1358 /* Allocate DMA memory resources. */ 1359 if (bce_dma_alloc(dev)) { 1360 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 1361 __FILE__, __LINE__); 1362 rc = ENXIO; 1363 goto bce_attach_fail; 1364 } 1365 1366 /* Allocate an ifnet structure. */ 1367 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 1368 if (ifp == NULL) { 1369 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 1370 __FILE__, __LINE__); 1371 rc = ENXIO; 1372 goto bce_attach_fail; 1373 } 1374 1375 /* Initialize the ifnet interface. */ 1376 ifp->if_softc = sc; 1377 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1378 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1379 ifp->if_ioctl = bce_ioctl; 1380 ifp->if_start = bce_start; 1381 ifp->if_init = bce_init; 1382 ifp->if_mtu = ETHERMTU; 1383 1384 if (bce_tso_enable) { 1385 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 1386 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 | 1387 IFCAP_VLAN_HWTSO; 1388 } else { 1389 ifp->if_hwassist = BCE_IF_HWASSIST; 1390 ifp->if_capabilities = BCE_IF_CAPABILITIES; 1391 } 1392 1393 ifp->if_capenable = ifp->if_capabilities; 1394 1395 /* 1396 * Assume standard mbuf sizes for buffer allocation. 1397 * This may change later if the MTU size is set to 1398 * something other than 1500. 1399 */ 1400 bce_get_rx_buffer_sizes(sc, 1401 (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)); 1402 1403 /* Recalculate our buffer allocation sizes. */ 1404 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC; 1405 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1406 IFQ_SET_READY(&ifp->if_snd); 1407 1408 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 1409 ifp->if_baudrate = IF_Mbps(2500ULL); 1410 else 1411 ifp->if_baudrate = IF_Mbps(1000); 1412 1413 /* Handle any special PHY initialization for SerDes PHYs. */ 1414 bce_init_media(sc); 1415 1416 /* MII child bus by attaching the PHY. */ 1417 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd, 1418 bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr, 1419 MII_OFFSET_ANY, MIIF_DOPAUSE); 1420 if (rc != 0) { 1421 BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__, 1422 __LINE__); 1423 goto bce_attach_fail; 1424 } 1425 1426 /* Attach to the Ethernet interface list. */ 1427 ether_ifattach(ifp, sc->eaddr); 1428 1429 #if __FreeBSD_version < 500000 1430 callout_init(&sc->bce_tick_callout); 1431 callout_init(&sc->bce_pulse_callout); 1432 #else 1433 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 1434 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 1435 #endif 1436 1437 /* Hookup IRQ last. */ 1438 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, 1439 NULL, bce_intr, sc, &sc->bce_intrhand); 1440 1441 if (rc) { 1442 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 1443 __FILE__, __LINE__); 1444 bce_detach(dev); 1445 goto bce_attach_exit; 1446 } 1447 1448 /* 1449 * At this point we've acquired all the resources 1450 * we need to run so there's no turning back, we're 1451 * cleared for launch. 1452 */ 1453 1454 /* Print some important debugging info. */ 1455 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc)); 1456 1457 /* Add the supported sysctls to the kernel. */ 1458 bce_add_sysctls(sc); 1459 1460 BCE_LOCK(sc); 1461 1462 /* 1463 * The chip reset earlier notified the bootcode that 1464 * a driver is present. We now need to start our pulse 1465 * routine so that the bootcode is reminded that we're 1466 * still running. 1467 */ 1468 bce_pulse(sc); 1469 1470 bce_mgmt_init_locked(sc); 1471 BCE_UNLOCK(sc); 1472 1473 /* Finally, print some useful adapter info */ 1474 bce_print_adapter_info(sc); 1475 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n", 1476 __FUNCTION__, sc); 1477 1478 goto bce_attach_exit; 1479 1480 bce_attach_fail: 1481 bce_release_resources(sc); 1482 1483 bce_attach_exit: 1484 1485 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 1486 1487 return(rc); 1488 } 1489 1490 1491 /****************************************************************************/ 1492 /* Device detach function. */ 1493 /* */ 1494 /* Stops the controller, resets the controller, and releases resources. */ 1495 /* */ 1496 /* Returns: */ 1497 /* 0 on success, positive value on failure. */ 1498 /****************************************************************************/ 1499 static int 1500 bce_detach(device_t dev) 1501 { 1502 struct bce_softc *sc = device_get_softc(dev); 1503 struct ifnet *ifp; 1504 u32 msg; 1505 1506 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1507 1508 ifp = sc->bce_ifp; 1509 1510 /* Stop and reset the controller. */ 1511 BCE_LOCK(sc); 1512 1513 /* Stop the pulse so the bootcode can go to driver absent state. */ 1514 callout_stop(&sc->bce_pulse_callout); 1515 1516 bce_stop(sc); 1517 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1518 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1519 else 1520 msg = BCE_DRV_MSG_CODE_UNLOAD; 1521 bce_reset(sc, msg); 1522 1523 BCE_UNLOCK(sc); 1524 1525 ether_ifdetach(ifp); 1526 1527 /* If we have a child device on the MII bus remove it too. */ 1528 bus_generic_detach(dev); 1529 device_delete_child(dev, sc->bce_miibus); 1530 1531 /* Release all remaining resources. */ 1532 bce_release_resources(sc); 1533 1534 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET); 1535 1536 return(0); 1537 } 1538 1539 1540 /****************************************************************************/ 1541 /* Device shutdown function. */ 1542 /* */ 1543 /* Stops and resets the controller. */ 1544 /* */ 1545 /* Returns: */ 1546 /* 0 on success, positive value on failure. */ 1547 /****************************************************************************/ 1548 static int 1549 bce_shutdown(device_t dev) 1550 { 1551 struct bce_softc *sc = device_get_softc(dev); 1552 u32 msg; 1553 1554 DBENTER(BCE_VERBOSE); 1555 1556 BCE_LOCK(sc); 1557 bce_stop(sc); 1558 if (sc->bce_flags & BCE_NO_WOL_FLAG) 1559 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 1560 else 1561 msg = BCE_DRV_MSG_CODE_UNLOAD; 1562 bce_reset(sc, msg); 1563 BCE_UNLOCK(sc); 1564 1565 DBEXIT(BCE_VERBOSE); 1566 1567 return (0); 1568 } 1569 1570 1571 #ifdef BCE_DEBUG 1572 /****************************************************************************/ 1573 /* Register read. */ 1574 /* */ 1575 /* Returns: */ 1576 /* The value of the register. */ 1577 /****************************************************************************/ 1578 static u32 1579 bce_reg_rd(struct bce_softc *sc, u32 offset) 1580 { 1581 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset); 1582 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1583 __FUNCTION__, offset, val); 1584 return val; 1585 } 1586 1587 1588 /****************************************************************************/ 1589 /* Register write (16 bit). */ 1590 /* */ 1591 /* Returns: */ 1592 /* Nothing. */ 1593 /****************************************************************************/ 1594 static void 1595 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val) 1596 { 1597 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n", 1598 __FUNCTION__, offset, val); 1599 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val); 1600 } 1601 1602 1603 /****************************************************************************/ 1604 /* Register write. */ 1605 /* */ 1606 /* Returns: */ 1607 /* Nothing. */ 1608 /****************************************************************************/ 1609 static void 1610 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val) 1611 { 1612 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1613 __FUNCTION__, offset, val); 1614 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val); 1615 } 1616 #endif 1617 1618 /****************************************************************************/ 1619 /* Indirect register read. */ 1620 /* */ 1621 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 1622 /* configuration space. Using this mechanism avoids issues with posted */ 1623 /* reads but is much slower than memory-mapped I/O. */ 1624 /* */ 1625 /* Returns: */ 1626 /* The value of the register. */ 1627 /****************************************************************************/ 1628 static u32 1629 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 1630 { 1631 device_t dev; 1632 dev = sc->bce_dev; 1633 1634 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1635 #ifdef BCE_DEBUG 1636 { 1637 u32 val; 1638 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1639 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1640 __FUNCTION__, offset, val); 1641 return val; 1642 } 1643 #else 1644 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 1645 #endif 1646 } 1647 1648 1649 /****************************************************************************/ 1650 /* Indirect register write. */ 1651 /* */ 1652 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 1653 /* configuration space. Using this mechanism avoids issues with posted */ 1654 /* writes but is muchh slower than memory-mapped I/O. */ 1655 /* */ 1656 /* Returns: */ 1657 /* Nothing. */ 1658 /****************************************************************************/ 1659 static void 1660 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 1661 { 1662 device_t dev; 1663 dev = sc->bce_dev; 1664 1665 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n", 1666 __FUNCTION__, offset, val); 1667 1668 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 1669 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 1670 } 1671 1672 1673 /****************************************************************************/ 1674 /* Shared memory write. */ 1675 /* */ 1676 /* Writes NetXtreme II shared memory region. */ 1677 /* */ 1678 /* Returns: */ 1679 /* Nothing. */ 1680 /****************************************************************************/ 1681 static void 1682 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val) 1683 { 1684 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to " 1685 "0x%08X\n", __FUNCTION__, val, offset); 1686 1687 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val); 1688 } 1689 1690 1691 /****************************************************************************/ 1692 /* Shared memory read. */ 1693 /* */ 1694 /* Reads NetXtreme II shared memory region. */ 1695 /* */ 1696 /* Returns: */ 1697 /* The 32 bit value read. */ 1698 /****************************************************************************/ 1699 static u32 1700 bce_shmem_rd(struct bce_softc *sc, u32 offset) 1701 { 1702 u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset); 1703 1704 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from " 1705 "0x%08X\n", __FUNCTION__, val, offset); 1706 1707 return val; 1708 } 1709 1710 1711 #ifdef BCE_DEBUG 1712 /****************************************************************************/ 1713 /* Context memory read. */ 1714 /* */ 1715 /* The NetXtreme II controller uses context memory to track connection */ 1716 /* information for L2 and higher network protocols. */ 1717 /* */ 1718 /* Returns: */ 1719 /* The requested 32 bit value of context memory. */ 1720 /****************************************************************************/ 1721 static u32 1722 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset) 1723 { 1724 u32 idx, offset, retry_cnt = 5, val; 1725 1726 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || 1727 cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID " 1728 "address: 0x%08X.\n", __FUNCTION__, cid_addr)); 1729 1730 offset = ctx_offset + cid_addr; 1731 1732 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1733 1734 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ)); 1735 1736 for (idx = 0; idx < retry_cnt; idx++) { 1737 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1738 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0) 1739 break; 1740 DELAY(5); 1741 } 1742 1743 if (val & BCE_CTX_CTX_CTRL_READ_REQ) 1744 BCE_PRINTF("%s(%d); Unable to read CTX memory: " 1745 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1746 __FILE__, __LINE__, cid_addr, ctx_offset); 1747 1748 val = REG_RD(sc, BCE_CTX_CTX_DATA); 1749 } else { 1750 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1751 val = REG_RD(sc, BCE_CTX_DATA); 1752 } 1753 1754 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1755 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val); 1756 1757 return(val); 1758 } 1759 #endif 1760 1761 1762 /****************************************************************************/ 1763 /* Context memory write. */ 1764 /* */ 1765 /* The NetXtreme II controller uses context memory to track connection */ 1766 /* information for L2 and higher network protocols. */ 1767 /* */ 1768 /* Returns: */ 1769 /* Nothing. */ 1770 /****************************************************************************/ 1771 static void 1772 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val) 1773 { 1774 u32 idx, offset = ctx_offset + cid_addr; 1775 u32 val, retry_cnt = 5; 1776 1777 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1778 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val); 1779 1780 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK), 1781 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n", 1782 __FUNCTION__, cid_addr)); 1783 1784 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 1785 1786 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val); 1787 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ)); 1788 1789 for (idx = 0; idx < retry_cnt; idx++) { 1790 val = REG_RD(sc, BCE_CTX_CTX_CTRL); 1791 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0) 1792 break; 1793 DELAY(5); 1794 } 1795 1796 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) 1797 BCE_PRINTF("%s(%d); Unable to write CTX memory: " 1798 "cid_addr = 0x%08X, offset = 0x%08X!\n", 1799 __FILE__, __LINE__, cid_addr, ctx_offset); 1800 1801 } else { 1802 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1803 REG_WR(sc, BCE_CTX_DATA, ctx_val); 1804 } 1805 } 1806 1807 1808 /****************************************************************************/ 1809 /* PHY register read. */ 1810 /* */ 1811 /* Implements register reads on the MII bus. */ 1812 /* */ 1813 /* Returns: */ 1814 /* The value of the register. */ 1815 /****************************************************************************/ 1816 static int 1817 bce_miibus_read_reg(device_t dev, int phy, int reg) 1818 { 1819 struct bce_softc *sc; 1820 u32 val; 1821 int i; 1822 1823 sc = device_get_softc(dev); 1824 1825 /* Make sure we are accessing the correct PHY address. */ 1826 if (phy != sc->bce_phy_addr) { 1827 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1828 "for PHY read!\n", phy); 1829 return(0); 1830 } 1831 1832 /* 1833 * The 5709S PHY is an IEEE Clause 45 PHY 1834 * with special mappings to work with IEEE 1835 * Clause 22 register accesses. 1836 */ 1837 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1838 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1839 reg += 0x10; 1840 } 1841 1842 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1843 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1844 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1845 1846 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1847 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1848 1849 DELAY(40); 1850 } 1851 1852 1853 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1854 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1855 BCE_EMAC_MDIO_COMM_START_BUSY; 1856 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1857 1858 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1859 DELAY(10); 1860 1861 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1862 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1863 DELAY(5); 1864 1865 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1866 val &= BCE_EMAC_MDIO_COMM_DATA; 1867 1868 break; 1869 } 1870 } 1871 1872 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1873 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, " 1874 "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg); 1875 val = 0x0; 1876 } else { 1877 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1878 } 1879 1880 1881 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1882 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1883 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1884 1885 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1886 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1887 1888 DELAY(40); 1889 } 1890 1891 DB_PRINT_PHY_REG(reg, val); 1892 return (val & 0xffff); 1893 1894 } 1895 1896 1897 /****************************************************************************/ 1898 /* PHY register write. */ 1899 /* */ 1900 /* Implements register writes on the MII bus. */ 1901 /* */ 1902 /* Returns: */ 1903 /* The value of the register. */ 1904 /****************************************************************************/ 1905 static int 1906 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1907 { 1908 struct bce_softc *sc; 1909 u32 val1; 1910 int i; 1911 1912 sc = device_get_softc(dev); 1913 1914 /* Make sure we are accessing the correct PHY address. */ 1915 if (phy != sc->bce_phy_addr) { 1916 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d " 1917 "for PHY write!\n", phy); 1918 return(0); 1919 } 1920 1921 DB_PRINT_PHY_REG(reg, val); 1922 1923 /* 1924 * The 5709S PHY is an IEEE Clause 45 PHY 1925 * with special mappings to work with IEEE 1926 * Clause 22 register accesses. 1927 */ 1928 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 1929 if (reg >= MII_BMCR && reg <= MII_ANLPRNP) 1930 reg += 0x10; 1931 } 1932 1933 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1934 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1935 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1936 1937 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1938 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1939 1940 DELAY(40); 1941 } 1942 1943 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1944 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1945 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1946 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1947 1948 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1949 DELAY(10); 1950 1951 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1952 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1953 DELAY(5); 1954 break; 1955 } 1956 } 1957 1958 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1959 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1960 __FILE__, __LINE__); 1961 1962 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1963 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1964 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1965 1966 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1967 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1968 1969 DELAY(40); 1970 } 1971 1972 return 0; 1973 } 1974 1975 1976 /****************************************************************************/ 1977 /* MII bus status change. */ 1978 /* */ 1979 /* Called by the MII bus driver when the PHY establishes link to set the */ 1980 /* MAC interface registers. */ 1981 /* */ 1982 /* Returns: */ 1983 /* Nothing. */ 1984 /****************************************************************************/ 1985 static void 1986 bce_miibus_statchg(device_t dev) 1987 { 1988 struct bce_softc *sc; 1989 struct mii_data *mii; 1990 int val; 1991 1992 sc = device_get_softc(dev); 1993 1994 DBENTER(BCE_VERBOSE_PHY); 1995 1996 mii = device_get_softc(sc->bce_miibus); 1997 1998 val = REG_RD(sc, BCE_EMAC_MODE); 1999 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 2000 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 2001 BCE_EMAC_MODE_25G); 2002 2003 /* Set MII or GMII interface based on the PHY speed. */ 2004 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2005 case IFM_10_T: 2006 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 2007 DBPRINT(sc, BCE_INFO_PHY, 2008 "Enabling 10Mb interface.\n"); 2009 val |= BCE_EMAC_MODE_PORT_MII_10; 2010 break; 2011 } 2012 /* fall-through */ 2013 case IFM_100_TX: 2014 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n"); 2015 val |= BCE_EMAC_MODE_PORT_MII; 2016 break; 2017 case IFM_2500_SX: 2018 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n"); 2019 val |= BCE_EMAC_MODE_25G; 2020 /* fall-through */ 2021 case IFM_1000_T: 2022 case IFM_1000_SX: 2023 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n"); 2024 val |= BCE_EMAC_MODE_PORT_GMII; 2025 break; 2026 default: 2027 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling " 2028 "default GMII interface.\n"); 2029 val |= BCE_EMAC_MODE_PORT_GMII; 2030 } 2031 2032 /* Set half or full duplex based on PHY settings. */ 2033 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 2034 DBPRINT(sc, BCE_INFO_PHY, 2035 "Setting Half-Duplex interface.\n"); 2036 val |= BCE_EMAC_MODE_HALF_DUPLEX; 2037 } else 2038 DBPRINT(sc, BCE_INFO_PHY, 2039 "Setting Full-Duplex interface.\n"); 2040 2041 REG_WR(sc, BCE_EMAC_MODE, val); 2042 2043 if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) { 2044 DBPRINT(sc, BCE_INFO_PHY, 2045 "%s(): Enabling RX flow control.\n", __FUNCTION__); 2046 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2047 } else { 2048 DBPRINT(sc, BCE_INFO_PHY, 2049 "%s(): Disabling RX flow control.\n", __FUNCTION__); 2050 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 2051 } 2052 2053 if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) { 2054 DBPRINT(sc, BCE_INFO_PHY, 2055 "%s(): Enabling TX flow control.\n", __FUNCTION__); 2056 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2057 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL; 2058 } else { 2059 DBPRINT(sc, BCE_INFO_PHY, 2060 "%s(): Disabling TX flow control.\n", __FUNCTION__); 2061 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 2062 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL; 2063 } 2064 2065 /* ToDo: Update watermarks in bce_init_rx_context(). */ 2066 2067 DBEXIT(BCE_VERBOSE_PHY); 2068 } 2069 2070 2071 /****************************************************************************/ 2072 /* Acquire NVRAM lock. */ 2073 /* */ 2074 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 2075 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2076 /* for use by the driver. */ 2077 /* */ 2078 /* Returns: */ 2079 /* 0 on success, positive value on failure. */ 2080 /****************************************************************************/ 2081 static int 2082 bce_acquire_nvram_lock(struct bce_softc *sc) 2083 { 2084 u32 val; 2085 int j, rc = 0; 2086 2087 DBENTER(BCE_VERBOSE_NVRAM); 2088 2089 /* Request access to the flash interface. */ 2090 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 2091 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2092 val = REG_RD(sc, BCE_NVM_SW_ARB); 2093 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 2094 break; 2095 2096 DELAY(5); 2097 } 2098 2099 if (j >= NVRAM_TIMEOUT_COUNT) { 2100 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 2101 rc = EBUSY; 2102 } 2103 2104 DBEXIT(BCE_VERBOSE_NVRAM); 2105 return (rc); 2106 } 2107 2108 2109 /****************************************************************************/ 2110 /* Release NVRAM lock. */ 2111 /* */ 2112 /* When the caller is finished accessing NVRAM the lock must be released. */ 2113 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 2114 /* for use by the driver. */ 2115 /* */ 2116 /* Returns: */ 2117 /* 0 on success, positive value on failure. */ 2118 /****************************************************************************/ 2119 static int 2120 bce_release_nvram_lock(struct bce_softc *sc) 2121 { 2122 u32 val; 2123 int j, rc = 0; 2124 2125 DBENTER(BCE_VERBOSE_NVRAM); 2126 2127 /* 2128 * Relinquish nvram interface. 2129 */ 2130 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 2131 2132 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2133 val = REG_RD(sc, BCE_NVM_SW_ARB); 2134 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 2135 break; 2136 2137 DELAY(5); 2138 } 2139 2140 if (j >= NVRAM_TIMEOUT_COUNT) { 2141 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n"); 2142 rc = EBUSY; 2143 } 2144 2145 DBEXIT(BCE_VERBOSE_NVRAM); 2146 return (rc); 2147 } 2148 2149 2150 #ifdef BCE_NVRAM_WRITE_SUPPORT 2151 /****************************************************************************/ 2152 /* Enable NVRAM write access. */ 2153 /* */ 2154 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 2155 /* */ 2156 /* Returns: */ 2157 /* 0 on success, positive value on failure. */ 2158 /****************************************************************************/ 2159 static int 2160 bce_enable_nvram_write(struct bce_softc *sc) 2161 { 2162 u32 val; 2163 int rc = 0; 2164 2165 DBENTER(BCE_VERBOSE_NVRAM); 2166 2167 val = REG_RD(sc, BCE_MISC_CFG); 2168 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 2169 2170 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2171 int j; 2172 2173 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2174 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 2175 2176 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2177 DELAY(5); 2178 2179 val = REG_RD(sc, BCE_NVM_COMMAND); 2180 if (val & BCE_NVM_COMMAND_DONE) 2181 break; 2182 } 2183 2184 if (j >= NVRAM_TIMEOUT_COUNT) { 2185 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 2186 rc = EBUSY; 2187 } 2188 } 2189 2190 DBENTER(BCE_VERBOSE_NVRAM); 2191 return (rc); 2192 } 2193 2194 2195 /****************************************************************************/ 2196 /* Disable NVRAM write access. */ 2197 /* */ 2198 /* When the caller is finished writing to NVRAM write access must be */ 2199 /* disabled. */ 2200 /* */ 2201 /* Returns: */ 2202 /* Nothing. */ 2203 /****************************************************************************/ 2204 static void 2205 bce_disable_nvram_write(struct bce_softc *sc) 2206 { 2207 u32 val; 2208 2209 DBENTER(BCE_VERBOSE_NVRAM); 2210 2211 val = REG_RD(sc, BCE_MISC_CFG); 2212 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 2213 2214 DBEXIT(BCE_VERBOSE_NVRAM); 2215 2216 } 2217 #endif 2218 2219 2220 /****************************************************************************/ 2221 /* Enable NVRAM access. */ 2222 /* */ 2223 /* Before accessing NVRAM for read or write operations the caller must */ 2224 /* enabled NVRAM access. */ 2225 /* */ 2226 /* Returns: */ 2227 /* Nothing. */ 2228 /****************************************************************************/ 2229 static void 2230 bce_enable_nvram_access(struct bce_softc *sc) 2231 { 2232 u32 val; 2233 2234 DBENTER(BCE_VERBOSE_NVRAM); 2235 2236 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2237 /* Enable both bits, even on read. */ 2238 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val | 2239 BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 2240 2241 DBEXIT(BCE_VERBOSE_NVRAM); 2242 } 2243 2244 2245 /****************************************************************************/ 2246 /* Disable NVRAM access. */ 2247 /* */ 2248 /* When the caller is finished accessing NVRAM access must be disabled. */ 2249 /* */ 2250 /* Returns: */ 2251 /* Nothing. */ 2252 /****************************************************************************/ 2253 static void 2254 bce_disable_nvram_access(struct bce_softc *sc) 2255 { 2256 u32 val; 2257 2258 DBENTER(BCE_VERBOSE_NVRAM); 2259 2260 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 2261 2262 /* Disable both bits, even after read. */ 2263 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val & 2264 ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN)); 2265 2266 DBEXIT(BCE_VERBOSE_NVRAM); 2267 } 2268 2269 2270 #ifdef BCE_NVRAM_WRITE_SUPPORT 2271 /****************************************************************************/ 2272 /* Erase NVRAM page before writing. */ 2273 /* */ 2274 /* Non-buffered flash parts require that a page be erased before it is */ 2275 /* written. */ 2276 /* */ 2277 /* Returns: */ 2278 /* 0 on success, positive value on failure. */ 2279 /****************************************************************************/ 2280 static int 2281 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 2282 { 2283 u32 cmd; 2284 int j, rc = 0; 2285 2286 DBENTER(BCE_VERBOSE_NVRAM); 2287 2288 /* Buffered flash doesn't require an erase. */ 2289 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED) 2290 goto bce_nvram_erase_page_exit; 2291 2292 /* Build an erase command. */ 2293 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 2294 BCE_NVM_COMMAND_DOIT; 2295 2296 /* 2297 * Clear the DONE bit separately, set the NVRAM adress to erase, 2298 * and issue the erase command. 2299 */ 2300 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2301 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2302 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2303 2304 /* Wait for completion. */ 2305 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2306 u32 val; 2307 2308 DELAY(5); 2309 2310 val = REG_RD(sc, BCE_NVM_COMMAND); 2311 if (val & BCE_NVM_COMMAND_DONE) 2312 break; 2313 } 2314 2315 if (j >= NVRAM_TIMEOUT_COUNT) { 2316 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 2317 rc = EBUSY; 2318 } 2319 2320 bce_nvram_erase_page_exit: 2321 DBEXIT(BCE_VERBOSE_NVRAM); 2322 return (rc); 2323 } 2324 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2325 2326 2327 /****************************************************************************/ 2328 /* Read a dword (32 bits) from NVRAM. */ 2329 /* */ 2330 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 2331 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 2332 /* */ 2333 /* Returns: */ 2334 /* 0 on success and the 32 bit value read, positive value on failure. */ 2335 /****************************************************************************/ 2336 static int 2337 bce_nvram_read_dword(struct bce_softc *sc, 2338 u32 offset, u8 *ret_val, u32 cmd_flags) 2339 { 2340 u32 cmd; 2341 int i, rc = 0; 2342 2343 DBENTER(BCE_EXTREME_NVRAM); 2344 2345 /* Build the command word. */ 2346 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 2347 2348 /* Calculate the offset for buffered flash if translation is used. */ 2349 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2350 offset = ((offset / sc->bce_flash_info->page_size) << 2351 sc->bce_flash_info->page_bits) + 2352 (offset % sc->bce_flash_info->page_size); 2353 } 2354 2355 /* 2356 * Clear the DONE bit separately, set the address to read, 2357 * and issue the read. 2358 */ 2359 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2360 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2361 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2362 2363 /* Wait for completion. */ 2364 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 2365 u32 val; 2366 2367 DELAY(5); 2368 2369 val = REG_RD(sc, BCE_NVM_COMMAND); 2370 if (val & BCE_NVM_COMMAND_DONE) { 2371 val = REG_RD(sc, BCE_NVM_READ); 2372 2373 val = bce_be32toh(val); 2374 memcpy(ret_val, &val, 4); 2375 break; 2376 } 2377 } 2378 2379 /* Check for errors. */ 2380 if (i >= NVRAM_TIMEOUT_COUNT) { 2381 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at " 2382 "offset 0x%08X!\n", __FILE__, __LINE__, offset); 2383 rc = EBUSY; 2384 } 2385 2386 DBEXIT(BCE_EXTREME_NVRAM); 2387 return(rc); 2388 } 2389 2390 2391 #ifdef BCE_NVRAM_WRITE_SUPPORT 2392 /****************************************************************************/ 2393 /* Write a dword (32 bits) to NVRAM. */ 2394 /* */ 2395 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 2396 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 2397 /* enabled NVRAM write access. */ 2398 /* */ 2399 /* Returns: */ 2400 /* 0 on success, positive value on failure. */ 2401 /****************************************************************************/ 2402 static int 2403 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 2404 u32 cmd_flags) 2405 { 2406 u32 cmd, val32; 2407 int j, rc = 0; 2408 2409 DBENTER(BCE_VERBOSE_NVRAM); 2410 2411 /* Build the command word. */ 2412 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 2413 2414 /* Calculate the offset for buffered flash if translation is used. */ 2415 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) { 2416 offset = ((offset / sc->bce_flash_info->page_size) << 2417 sc->bce_flash_info->page_bits) + 2418 (offset % sc->bce_flash_info->page_size); 2419 } 2420 2421 /* 2422 * Clear the DONE bit separately, convert NVRAM data to big-endian, 2423 * set the NVRAM address to write, and issue the write command 2424 */ 2425 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 2426 memcpy(&val32, val, 4); 2427 val32 = htobe32(val32); 2428 REG_WR(sc, BCE_NVM_WRITE, val32); 2429 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 2430 REG_WR(sc, BCE_NVM_COMMAND, cmd); 2431 2432 /* Wait for completion. */ 2433 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 2434 DELAY(5); 2435 2436 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 2437 break; 2438 } 2439 if (j >= NVRAM_TIMEOUT_COUNT) { 2440 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at " 2441 "offset 0x%08X\n", __FILE__, __LINE__, offset); 2442 rc = EBUSY; 2443 } 2444 2445 DBEXIT(BCE_VERBOSE_NVRAM); 2446 return (rc); 2447 } 2448 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2449 2450 2451 /****************************************************************************/ 2452 /* Initialize NVRAM access. */ 2453 /* */ 2454 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 2455 /* access that device. */ 2456 /* */ 2457 /* Returns: */ 2458 /* 0 on success, positive value on failure. */ 2459 /****************************************************************************/ 2460 static int 2461 bce_init_nvram(struct bce_softc *sc) 2462 { 2463 u32 val; 2464 int j, entry_count, rc = 0; 2465 struct flash_spec *flash; 2466 2467 DBENTER(BCE_VERBOSE_NVRAM); 2468 2469 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 2470 sc->bce_flash_info = &flash_5709; 2471 goto bce_init_nvram_get_flash_size; 2472 } 2473 2474 /* Determine the selected interface. */ 2475 val = REG_RD(sc, BCE_NVM_CFG1); 2476 2477 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 2478 2479 /* 2480 * Flash reconfiguration is required to support additional 2481 * NVRAM devices not directly supported in hardware. 2482 * Check if the flash interface was reconfigured 2483 * by the bootcode. 2484 */ 2485 2486 if (val & 0x40000000) { 2487 /* Flash interface reconfigured by bootcode. */ 2488 2489 DBPRINT(sc,BCE_INFO_LOAD, 2490 "bce_init_nvram(): Flash WAS reconfigured.\n"); 2491 2492 for (j = 0, flash = &flash_table[0]; j < entry_count; 2493 j++, flash++) { 2494 if ((val & FLASH_BACKUP_STRAP_MASK) == 2495 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 2496 sc->bce_flash_info = flash; 2497 break; 2498 } 2499 } 2500 } else { 2501 /* Flash interface not yet reconfigured. */ 2502 u32 mask; 2503 2504 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n", 2505 __FUNCTION__); 2506 2507 if (val & (1 << 23)) 2508 mask = FLASH_BACKUP_STRAP_MASK; 2509 else 2510 mask = FLASH_STRAP_MASK; 2511 2512 /* Look for the matching NVRAM device configuration data. */ 2513 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 2514 2515 /* Check if the device matches any of the known devices. */ 2516 if ((val & mask) == (flash->strapping & mask)) { 2517 /* Found a device match. */ 2518 sc->bce_flash_info = flash; 2519 2520 /* Request access to the flash interface. */ 2521 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2522 return rc; 2523 2524 /* Reconfigure the flash interface. */ 2525 bce_enable_nvram_access(sc); 2526 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 2527 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 2528 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 2529 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 2530 bce_disable_nvram_access(sc); 2531 bce_release_nvram_lock(sc); 2532 2533 break; 2534 } 2535 } 2536 } 2537 2538 /* Check if a matching device was found. */ 2539 if (j == entry_count) { 2540 sc->bce_flash_info = NULL; 2541 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 2542 __FILE__, __LINE__); 2543 DBEXIT(BCE_VERBOSE_NVRAM); 2544 return (ENODEV); 2545 } 2546 2547 bce_init_nvram_get_flash_size: 2548 /* Write the flash config data to the shared memory interface. */ 2549 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2); 2550 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 2551 if (val) 2552 sc->bce_flash_size = val; 2553 else 2554 sc->bce_flash_size = sc->bce_flash_info->total_size; 2555 2556 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n", 2557 __FUNCTION__, sc->bce_flash_info->name, 2558 sc->bce_flash_info->total_size); 2559 2560 DBEXIT(BCE_VERBOSE_NVRAM); 2561 return rc; 2562 } 2563 2564 2565 /****************************************************************************/ 2566 /* Read an arbitrary range of data from NVRAM. */ 2567 /* */ 2568 /* Prepares the NVRAM interface for access and reads the requested data */ 2569 /* into the supplied buffer. */ 2570 /* */ 2571 /* Returns: */ 2572 /* 0 on success and the data read, positive value on failure. */ 2573 /****************************************************************************/ 2574 static int 2575 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 2576 int buf_size) 2577 { 2578 int rc = 0; 2579 u32 cmd_flags, offset32, len32, extra; 2580 2581 DBENTER(BCE_VERBOSE_NVRAM); 2582 2583 if (buf_size == 0) 2584 goto bce_nvram_read_exit; 2585 2586 /* Request access to the flash interface. */ 2587 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2588 goto bce_nvram_read_exit; 2589 2590 /* Enable access to flash interface */ 2591 bce_enable_nvram_access(sc); 2592 2593 len32 = buf_size; 2594 offset32 = offset; 2595 extra = 0; 2596 2597 cmd_flags = 0; 2598 2599 if (offset32 & 3) { 2600 u8 buf[4]; 2601 u32 pre_len; 2602 2603 offset32 &= ~3; 2604 pre_len = 4 - (offset & 3); 2605 2606 if (pre_len >= len32) { 2607 pre_len = len32; 2608 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 2609 } 2610 else { 2611 cmd_flags = BCE_NVM_COMMAND_FIRST; 2612 } 2613 2614 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2615 2616 if (rc) 2617 return rc; 2618 2619 memcpy(ret_buf, buf + (offset & 3), pre_len); 2620 2621 offset32 += 4; 2622 ret_buf += pre_len; 2623 len32 -= pre_len; 2624 } 2625 2626 if (len32 & 3) { 2627 extra = 4 - (len32 & 3); 2628 len32 = (len32 + 4) & ~3; 2629 } 2630 2631 if (len32 == 4) { 2632 u8 buf[4]; 2633 2634 if (cmd_flags) 2635 cmd_flags = BCE_NVM_COMMAND_LAST; 2636 else 2637 cmd_flags = BCE_NVM_COMMAND_FIRST | 2638 BCE_NVM_COMMAND_LAST; 2639 2640 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2641 2642 memcpy(ret_buf, buf, 4 - extra); 2643 } 2644 else if (len32 > 0) { 2645 u8 buf[4]; 2646 2647 /* Read the first word. */ 2648 if (cmd_flags) 2649 cmd_flags = 0; 2650 else 2651 cmd_flags = BCE_NVM_COMMAND_FIRST; 2652 2653 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 2654 2655 /* Advance to the next dword. */ 2656 offset32 += 4; 2657 ret_buf += 4; 2658 len32 -= 4; 2659 2660 while (len32 > 4 && rc == 0) { 2661 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 2662 2663 /* Advance to the next dword. */ 2664 offset32 += 4; 2665 ret_buf += 4; 2666 len32 -= 4; 2667 } 2668 2669 if (rc) 2670 goto bce_nvram_read_locked_exit; 2671 2672 cmd_flags = BCE_NVM_COMMAND_LAST; 2673 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 2674 2675 memcpy(ret_buf, buf, 4 - extra); 2676 } 2677 2678 bce_nvram_read_locked_exit: 2679 /* Disable access to flash interface and release the lock. */ 2680 bce_disable_nvram_access(sc); 2681 bce_release_nvram_lock(sc); 2682 2683 bce_nvram_read_exit: 2684 DBEXIT(BCE_VERBOSE_NVRAM); 2685 return rc; 2686 } 2687 2688 2689 #ifdef BCE_NVRAM_WRITE_SUPPORT 2690 /****************************************************************************/ 2691 /* Write an arbitrary range of data from NVRAM. */ 2692 /* */ 2693 /* Prepares the NVRAM interface for write access and writes the requested */ 2694 /* data from the supplied buffer. The caller is responsible for */ 2695 /* calculating any appropriate CRCs. */ 2696 /* */ 2697 /* Returns: */ 2698 /* 0 on success, positive value on failure. */ 2699 /****************************************************************************/ 2700 static int 2701 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 2702 int buf_size) 2703 { 2704 u32 written, offset32, len32; 2705 u8 *buf, start[4], end[4]; 2706 int rc = 0; 2707 int align_start, align_end; 2708 2709 DBENTER(BCE_VERBOSE_NVRAM); 2710 2711 buf = data_buf; 2712 offset32 = offset; 2713 len32 = buf_size; 2714 align_start = align_end = 0; 2715 2716 if ((align_start = (offset32 & 3))) { 2717 offset32 &= ~3; 2718 len32 += align_start; 2719 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 2720 goto bce_nvram_write_exit; 2721 } 2722 2723 if (len32 & 3) { 2724 if ((len32 > 4) || !align_start) { 2725 align_end = 4 - (len32 & 3); 2726 len32 += align_end; 2727 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 2728 end, 4))) { 2729 goto bce_nvram_write_exit; 2730 } 2731 } 2732 } 2733 2734 if (align_start || align_end) { 2735 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 2736 if (buf == 0) { 2737 rc = ENOMEM; 2738 goto bce_nvram_write_exit; 2739 } 2740 2741 if (align_start) { 2742 memcpy(buf, start, 4); 2743 } 2744 2745 if (align_end) { 2746 memcpy(buf + len32 - 4, end, 4); 2747 } 2748 memcpy(buf + align_start, data_buf, buf_size); 2749 } 2750 2751 written = 0; 2752 while ((written < len32) && (rc == 0)) { 2753 u32 page_start, page_end, data_start, data_end; 2754 u32 addr, cmd_flags; 2755 int i; 2756 u8 flash_buffer[264]; 2757 2758 /* Find the page_start addr */ 2759 page_start = offset32 + written; 2760 page_start -= (page_start % sc->bce_flash_info->page_size); 2761 /* Find the page_end addr */ 2762 page_end = page_start + sc->bce_flash_info->page_size; 2763 /* Find the data_start addr */ 2764 data_start = (written == 0) ? offset32 : page_start; 2765 /* Find the data_end addr */ 2766 data_end = (page_end > offset32 + len32) ? 2767 (offset32 + len32) : page_end; 2768 2769 /* Request access to the flash interface. */ 2770 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 2771 goto bce_nvram_write_exit; 2772 2773 /* Enable access to flash interface */ 2774 bce_enable_nvram_access(sc); 2775 2776 cmd_flags = BCE_NVM_COMMAND_FIRST; 2777 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2778 int j; 2779 2780 /* Read the whole page into the buffer 2781 * (non-buffer flash only) */ 2782 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 2783 if (j == (sc->bce_flash_info->page_size - 4)) { 2784 cmd_flags |= BCE_NVM_COMMAND_LAST; 2785 } 2786 rc = bce_nvram_read_dword(sc, 2787 page_start + j, 2788 &flash_buffer[j], 2789 cmd_flags); 2790 2791 if (rc) 2792 goto bce_nvram_write_locked_exit; 2793 2794 cmd_flags = 0; 2795 } 2796 } 2797 2798 /* Enable writes to flash interface (unlock write-protect) */ 2799 if ((rc = bce_enable_nvram_write(sc)) != 0) 2800 goto bce_nvram_write_locked_exit; 2801 2802 /* Erase the page */ 2803 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 2804 goto bce_nvram_write_locked_exit; 2805 2806 /* Re-enable the write again for the actual write */ 2807 bce_enable_nvram_write(sc); 2808 2809 /* Loop to write back the buffer data from page_start to 2810 * data_start */ 2811 i = 0; 2812 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2813 for (addr = page_start; addr < data_start; 2814 addr += 4, i += 4) { 2815 2816 rc = bce_nvram_write_dword(sc, addr, 2817 &flash_buffer[i], cmd_flags); 2818 2819 if (rc != 0) 2820 goto bce_nvram_write_locked_exit; 2821 2822 cmd_flags = 0; 2823 } 2824 } 2825 2826 /* Loop to write the new data from data_start to data_end */ 2827 for (addr = data_start; addr < data_end; addr += 4, i++) { 2828 if ((addr == page_end - 4) || 2829 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) && 2830 (addr == data_end - 4))) { 2831 2832 cmd_flags |= BCE_NVM_COMMAND_LAST; 2833 } 2834 rc = bce_nvram_write_dword(sc, addr, buf, 2835 cmd_flags); 2836 2837 if (rc != 0) 2838 goto bce_nvram_write_locked_exit; 2839 2840 cmd_flags = 0; 2841 buf += 4; 2842 } 2843 2844 /* Loop to write back the buffer data from data_end 2845 * to page_end */ 2846 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) { 2847 for (addr = data_end; addr < page_end; 2848 addr += 4, i += 4) { 2849 2850 if (addr == page_end-4) { 2851 cmd_flags = BCE_NVM_COMMAND_LAST; 2852 } 2853 rc = bce_nvram_write_dword(sc, addr, 2854 &flash_buffer[i], cmd_flags); 2855 2856 if (rc != 0) 2857 goto bce_nvram_write_locked_exit; 2858 2859 cmd_flags = 0; 2860 } 2861 } 2862 2863 /* Disable writes to flash interface (lock write-protect) */ 2864 bce_disable_nvram_write(sc); 2865 2866 /* Disable access to flash interface */ 2867 bce_disable_nvram_access(sc); 2868 bce_release_nvram_lock(sc); 2869 2870 /* Increment written */ 2871 written += data_end - data_start; 2872 } 2873 2874 goto bce_nvram_write_exit; 2875 2876 bce_nvram_write_locked_exit: 2877 bce_disable_nvram_write(sc); 2878 bce_disable_nvram_access(sc); 2879 bce_release_nvram_lock(sc); 2880 2881 bce_nvram_write_exit: 2882 if (align_start || align_end) 2883 free(buf, M_DEVBUF); 2884 2885 DBEXIT(BCE_VERBOSE_NVRAM); 2886 return (rc); 2887 } 2888 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2889 2890 2891 /****************************************************************************/ 2892 /* Verifies that NVRAM is accessible and contains valid data. */ 2893 /* */ 2894 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2895 /* correct. */ 2896 /* */ 2897 /* Returns: */ 2898 /* 0 on success, positive value on failure. */ 2899 /****************************************************************************/ 2900 static int 2901 bce_nvram_test(struct bce_softc *sc) 2902 { 2903 u32 buf[BCE_NVRAM_SIZE / 4]; 2904 u8 *data = (u8 *) buf; 2905 int rc = 0; 2906 u32 magic, csum; 2907 2908 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2909 2910 /* 2911 * Check that the device NVRAM is valid by reading 2912 * the magic value at offset 0. 2913 */ 2914 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) { 2915 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", 2916 __FILE__, __LINE__); 2917 goto bce_nvram_test_exit; 2918 } 2919 2920 /* 2921 * Verify that offset 0 of the NVRAM contains 2922 * a valid magic number. 2923 */ 2924 magic = bce_be32toh(buf[0]); 2925 if (magic != BCE_NVRAM_MAGIC) { 2926 rc = ENODEV; 2927 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! " 2928 "Expected: 0x%08X, Found: 0x%08X\n", 2929 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2930 goto bce_nvram_test_exit; 2931 } 2932 2933 /* 2934 * Verify that the device NVRAM includes valid 2935 * configuration data. 2936 */ 2937 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) { 2938 BCE_PRINTF("%s(%d): Unable to read manufacturing " 2939 "Information from NVRAM!\n", __FILE__, __LINE__); 2940 goto bce_nvram_test_exit; 2941 } 2942 2943 csum = ether_crc32_le(data, 0x100); 2944 if (csum != BCE_CRC32_RESIDUAL) { 2945 rc = ENODEV; 2946 BCE_PRINTF("%s(%d): Invalid manufacturing information " 2947 "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n", 2948 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2949 goto bce_nvram_test_exit; 2950 } 2951 2952 csum = ether_crc32_le(data + 0x100, 0x100); 2953 if (csum != BCE_CRC32_RESIDUAL) { 2954 rc = ENODEV; 2955 BCE_PRINTF("%s(%d): Invalid feature configuration " 2956 "information NVRAM CRC! Expected: 0x%08X, " 2957 "Found: 08%08X\n", __FILE__, __LINE__, 2958 BCE_CRC32_RESIDUAL, csum); 2959 } 2960 2961 bce_nvram_test_exit: 2962 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET); 2963 return rc; 2964 } 2965 2966 2967 /****************************************************************************/ 2968 /* Calculates the size of the buffers to allocate based on the MTU. */ 2969 /* */ 2970 /* Returns: */ 2971 /* Nothing. */ 2972 /****************************************************************************/ 2973 static void 2974 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu) 2975 { 2976 DBENTER(BCE_VERBOSE_LOAD); 2977 2978 /* Use a single allocation type when header splitting enabled. */ 2979 if (bce_hdr_split == TRUE) { 2980 sc->rx_bd_mbuf_alloc_size = MHLEN; 2981 /* Make sure offset is 16 byte aligned for hardware. */ 2982 sc->rx_bd_mbuf_align_pad = 2983 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN); 2984 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size - 2985 sc->rx_bd_mbuf_align_pad; 2986 sc->pg_bd_mbuf_alloc_size = MCLBYTES; 2987 } else { 2988 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2989 ETHER_CRC_LEN) > MCLBYTES) { 2990 /* Setup for jumbo RX buffer allocations. */ 2991 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES; 2992 sc->rx_bd_mbuf_align_pad = 2993 roundup2(MJUM9BYTES, 16) - MJUM9BYTES; 2994 sc->rx_bd_mbuf_data_len = 2995 sc->rx_bd_mbuf_alloc_size - 2996 sc->rx_bd_mbuf_align_pad; 2997 } else { 2998 /* Setup for standard RX buffer allocations. */ 2999 sc->rx_bd_mbuf_alloc_size = MCLBYTES; 3000 sc->rx_bd_mbuf_align_pad = 3001 roundup2(MCLBYTES, 16) - MCLBYTES; 3002 sc->rx_bd_mbuf_data_len = 3003 sc->rx_bd_mbuf_alloc_size - 3004 sc->rx_bd_mbuf_align_pad; 3005 } 3006 } 3007 3008 // DBPRINT(sc, BCE_INFO_LOAD, 3009 DBPRINT(sc, BCE_WARN, 3010 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, " 3011 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__, 3012 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len, 3013 sc->rx_bd_mbuf_align_pad); 3014 3015 DBEXIT(BCE_VERBOSE_LOAD); 3016 3017 } 3018 3019 /****************************************************************************/ 3020 /* Identifies the current media type of the controller and sets the PHY */ 3021 /* address. */ 3022 /* */ 3023 /* Returns: */ 3024 /* Nothing. */ 3025 /****************************************************************************/ 3026 static void 3027 bce_get_media(struct bce_softc *sc) 3028 { 3029 u32 val; 3030 3031 DBENTER(BCE_VERBOSE_PHY); 3032 3033 /* Assume PHY address for copper controllers. */ 3034 sc->bce_phy_addr = 1; 3035 3036 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3037 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL); 3038 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID; 3039 u32 strap; 3040 3041 /* 3042 * The BCM5709S is software configurable 3043 * for Copper or SerDes operation. 3044 */ 3045 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) { 3046 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3047 "for copper.\n"); 3048 goto bce_get_media_exit; 3049 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { 3050 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded " 3051 "for dual media.\n"); 3052 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3053 goto bce_get_media_exit; 3054 } 3055 3056 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) 3057 strap = (val & 3058 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21; 3059 else 3060 strap = (val & 3061 BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8; 3062 3063 if (pci_get_function(sc->bce_dev) == 0) { 3064 switch (strap) { 3065 case 0x4: 3066 case 0x5: 3067 case 0x6: 3068 DBPRINT(sc, BCE_INFO_LOAD, 3069 "BCM5709 s/w configured for SerDes.\n"); 3070 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3071 break; 3072 default: 3073 DBPRINT(sc, BCE_INFO_LOAD, 3074 "BCM5709 s/w configured for Copper.\n"); 3075 break; 3076 } 3077 } else { 3078 switch (strap) { 3079 case 0x1: 3080 case 0x2: 3081 case 0x4: 3082 DBPRINT(sc, BCE_INFO_LOAD, 3083 "BCM5709 s/w configured for SerDes.\n"); 3084 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3085 break; 3086 default: 3087 DBPRINT(sc, BCE_INFO_LOAD, 3088 "BCM5709 s/w configured for Copper.\n"); 3089 break; 3090 } 3091 } 3092 3093 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) 3094 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 3095 3096 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) { 3097 3098 sc->bce_flags |= BCE_NO_WOL_FLAG; 3099 3100 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 3101 sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG; 3102 3103 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 3104 /* 5708S/09S/16S use a separate PHY for SerDes. */ 3105 sc->bce_phy_addr = 2; 3106 3107 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG); 3108 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 3109 sc->bce_phy_flags |= 3110 BCE_PHY_2_5G_CAPABLE_FLAG; 3111 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb " 3112 "capable adapter\n"); 3113 } 3114 } 3115 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) || 3116 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) 3117 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG; 3118 3119 bce_get_media_exit: 3120 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY), 3121 "Using PHY address %d.\n", sc->bce_phy_addr); 3122 3123 DBEXIT(BCE_VERBOSE_PHY); 3124 } 3125 3126 3127 /****************************************************************************/ 3128 /* Performs PHY initialization required before MII drivers access the */ 3129 /* device. */ 3130 /* */ 3131 /* Returns: */ 3132 /* Nothing. */ 3133 /****************************************************************************/ 3134 static void 3135 bce_init_media(struct bce_softc *sc) 3136 { 3137 if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) { 3138 /* 3139 * Configure 5709S/5716S PHYs to use traditional IEEE 3140 * Clause 22 method. Otherwise we have no way to attach 3141 * the PHY in mii(4) layer. PHY specific configuration 3142 * is done in mii layer. 3143 */ 3144 3145 /* Select auto-negotiation MMD of the PHY. */ 3146 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3147 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT); 3148 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3149 BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD); 3150 3151 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */ 3152 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr, 3153 BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 3154 } 3155 } 3156 3157 3158 /****************************************************************************/ 3159 /* Free any DMA memory owned by the driver. */ 3160 /* */ 3161 /* Scans through each data structre that requires DMA memory and frees */ 3162 /* the memory if allocated. */ 3163 /* */ 3164 /* Returns: */ 3165 /* Nothing. */ 3166 /****************************************************************************/ 3167 static void 3168 bce_dma_free(struct bce_softc *sc) 3169 { 3170 int i; 3171 3172 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3173 3174 /* Free, unmap, and destroy the status block. */ 3175 if (sc->status_block != NULL) { 3176 bus_dmamem_free( 3177 sc->status_tag, 3178 sc->status_block, 3179 sc->status_map); 3180 sc->status_block = NULL; 3181 } 3182 3183 if (sc->status_map != NULL) { 3184 bus_dmamap_unload( 3185 sc->status_tag, 3186 sc->status_map); 3187 bus_dmamap_destroy(sc->status_tag, 3188 sc->status_map); 3189 sc->status_map = NULL; 3190 } 3191 3192 if (sc->status_tag != NULL) { 3193 bus_dma_tag_destroy(sc->status_tag); 3194 sc->status_tag = NULL; 3195 } 3196 3197 3198 /* Free, unmap, and destroy the statistics block. */ 3199 if (sc->stats_block != NULL) { 3200 bus_dmamem_free( 3201 sc->stats_tag, 3202 sc->stats_block, 3203 sc->stats_map); 3204 sc->stats_block = NULL; 3205 } 3206 3207 if (sc->stats_map != NULL) { 3208 bus_dmamap_unload( 3209 sc->stats_tag, 3210 sc->stats_map); 3211 bus_dmamap_destroy(sc->stats_tag, 3212 sc->stats_map); 3213 sc->stats_map = NULL; 3214 } 3215 3216 if (sc->stats_tag != NULL) { 3217 bus_dma_tag_destroy(sc->stats_tag); 3218 sc->stats_tag = NULL; 3219 } 3220 3221 3222 /* Free, unmap and destroy all context memory pages. */ 3223 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3224 for (i = 0; i < sc->ctx_pages; i++ ) { 3225 if (sc->ctx_block[i] != NULL) { 3226 bus_dmamem_free( 3227 sc->ctx_tag, 3228 sc->ctx_block[i], 3229 sc->ctx_map[i]); 3230 sc->ctx_block[i] = NULL; 3231 } 3232 3233 if (sc->ctx_map[i] != NULL) { 3234 bus_dmamap_unload( 3235 sc->ctx_tag, 3236 sc->ctx_map[i]); 3237 bus_dmamap_destroy( 3238 sc->ctx_tag, 3239 sc->ctx_map[i]); 3240 sc->ctx_map[i] = NULL; 3241 } 3242 } 3243 3244 /* Destroy the context memory tag. */ 3245 if (sc->ctx_tag != NULL) { 3246 bus_dma_tag_destroy(sc->ctx_tag); 3247 sc->ctx_tag = NULL; 3248 } 3249 } 3250 3251 3252 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 3253 for (i = 0; i < sc->tx_pages; i++ ) { 3254 if (sc->tx_bd_chain[i] != NULL) { 3255 bus_dmamem_free( 3256 sc->tx_bd_chain_tag, 3257 sc->tx_bd_chain[i], 3258 sc->tx_bd_chain_map[i]); 3259 sc->tx_bd_chain[i] = NULL; 3260 } 3261 3262 if (sc->tx_bd_chain_map[i] != NULL) { 3263 bus_dmamap_unload( 3264 sc->tx_bd_chain_tag, 3265 sc->tx_bd_chain_map[i]); 3266 bus_dmamap_destroy( 3267 sc->tx_bd_chain_tag, 3268 sc->tx_bd_chain_map[i]); 3269 sc->tx_bd_chain_map[i] = NULL; 3270 } 3271 } 3272 3273 /* Destroy the TX buffer descriptor tag. */ 3274 if (sc->tx_bd_chain_tag != NULL) { 3275 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 3276 sc->tx_bd_chain_tag = NULL; 3277 } 3278 3279 3280 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 3281 for (i = 0; i < sc->rx_pages; i++ ) { 3282 if (sc->rx_bd_chain[i] != NULL) { 3283 bus_dmamem_free( 3284 sc->rx_bd_chain_tag, 3285 sc->rx_bd_chain[i], 3286 sc->rx_bd_chain_map[i]); 3287 sc->rx_bd_chain[i] = NULL; 3288 } 3289 3290 if (sc->rx_bd_chain_map[i] != NULL) { 3291 bus_dmamap_unload( 3292 sc->rx_bd_chain_tag, 3293 sc->rx_bd_chain_map[i]); 3294 bus_dmamap_destroy( 3295 sc->rx_bd_chain_tag, 3296 sc->rx_bd_chain_map[i]); 3297 sc->rx_bd_chain_map[i] = NULL; 3298 } 3299 } 3300 3301 /* Destroy the RX buffer descriptor tag. */ 3302 if (sc->rx_bd_chain_tag != NULL) { 3303 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 3304 sc->rx_bd_chain_tag = NULL; 3305 } 3306 3307 3308 /* Free, unmap and destroy all page buffer descriptor chain pages. */ 3309 if (bce_hdr_split == TRUE) { 3310 for (i = 0; i < sc->pg_pages; i++ ) { 3311 if (sc->pg_bd_chain[i] != NULL) { 3312 bus_dmamem_free( 3313 sc->pg_bd_chain_tag, 3314 sc->pg_bd_chain[i], 3315 sc->pg_bd_chain_map[i]); 3316 sc->pg_bd_chain[i] = NULL; 3317 } 3318 3319 if (sc->pg_bd_chain_map[i] != NULL) { 3320 bus_dmamap_unload( 3321 sc->pg_bd_chain_tag, 3322 sc->pg_bd_chain_map[i]); 3323 bus_dmamap_destroy( 3324 sc->pg_bd_chain_tag, 3325 sc->pg_bd_chain_map[i]); 3326 sc->pg_bd_chain_map[i] = NULL; 3327 } 3328 } 3329 3330 /* Destroy the page buffer descriptor tag. */ 3331 if (sc->pg_bd_chain_tag != NULL) { 3332 bus_dma_tag_destroy(sc->pg_bd_chain_tag); 3333 sc->pg_bd_chain_tag = NULL; 3334 } 3335 } 3336 3337 3338 /* Unload and destroy the TX mbuf maps. */ 3339 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 3340 if (sc->tx_mbuf_map[i] != NULL) { 3341 bus_dmamap_unload(sc->tx_mbuf_tag, 3342 sc->tx_mbuf_map[i]); 3343 bus_dmamap_destroy(sc->tx_mbuf_tag, 3344 sc->tx_mbuf_map[i]); 3345 sc->tx_mbuf_map[i] = NULL; 3346 } 3347 } 3348 3349 /* Destroy the TX mbuf tag. */ 3350 if (sc->tx_mbuf_tag != NULL) { 3351 bus_dma_tag_destroy(sc->tx_mbuf_tag); 3352 sc->tx_mbuf_tag = NULL; 3353 } 3354 3355 /* Unload and destroy the RX mbuf maps. */ 3356 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 3357 if (sc->rx_mbuf_map[i] != NULL) { 3358 bus_dmamap_unload(sc->rx_mbuf_tag, 3359 sc->rx_mbuf_map[i]); 3360 bus_dmamap_destroy(sc->rx_mbuf_tag, 3361 sc->rx_mbuf_map[i]); 3362 sc->rx_mbuf_map[i] = NULL; 3363 } 3364 } 3365 3366 /* Destroy the RX mbuf tag. */ 3367 if (sc->rx_mbuf_tag != NULL) { 3368 bus_dma_tag_destroy(sc->rx_mbuf_tag); 3369 sc->rx_mbuf_tag = NULL; 3370 } 3371 3372 /* Unload and destroy the page mbuf maps. */ 3373 if (bce_hdr_split == TRUE) { 3374 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 3375 if (sc->pg_mbuf_map[i] != NULL) { 3376 bus_dmamap_unload(sc->pg_mbuf_tag, 3377 sc->pg_mbuf_map[i]); 3378 bus_dmamap_destroy(sc->pg_mbuf_tag, 3379 sc->pg_mbuf_map[i]); 3380 sc->pg_mbuf_map[i] = NULL; 3381 } 3382 } 3383 3384 /* Destroy the page mbuf tag. */ 3385 if (sc->pg_mbuf_tag != NULL) { 3386 bus_dma_tag_destroy(sc->pg_mbuf_tag); 3387 sc->pg_mbuf_tag = NULL; 3388 } 3389 } 3390 3391 /* Destroy the parent tag */ 3392 if (sc->parent_tag != NULL) { 3393 bus_dma_tag_destroy(sc->parent_tag); 3394 sc->parent_tag = NULL; 3395 } 3396 3397 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX); 3398 } 3399 3400 3401 /****************************************************************************/ 3402 /* Get DMA memory from the OS. */ 3403 /* */ 3404 /* Validates that the OS has provided DMA buffers in response to a */ 3405 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 3406 /* When the callback is used the OS will return 0 for the mapping function */ 3407 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 3408 /* failures back to the caller. */ 3409 /* */ 3410 /* Returns: */ 3411 /* Nothing. */ 3412 /****************************************************************************/ 3413 static void 3414 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3415 { 3416 bus_addr_t *busaddr = arg; 3417 3418 KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!", 3419 __FUNCTION__, nseg)); 3420 /* Simulate a mapping failure. */ 3421 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control), 3422 error = ENOMEM); 3423 3424 /* ToDo: How to increment debug sim_count variable here? */ 3425 3426 /* Check for an error and signal the caller that an error occurred. */ 3427 if (error) { 3428 *busaddr = 0; 3429 } else { 3430 *busaddr = segs->ds_addr; 3431 } 3432 3433 return; 3434 } 3435 3436 3437 /****************************************************************************/ 3438 /* Allocate any DMA memory needed by the driver. */ 3439 /* */ 3440 /* Allocates DMA memory needed for the various global structures needed by */ 3441 /* hardware. */ 3442 /* */ 3443 /* Memory alignment requirements: */ 3444 /* +-----------------+----------+----------+----------+----------+ */ 3445 /* | | 5706 | 5708 | 5709 | 5716 | */ 3446 /* +-----------------+----------+----------+----------+----------+ */ 3447 /* |Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3448 /* |Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */ 3449 /* |RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */ 3450 /* |PG Buffers | none | none | none | none | */ 3451 /* |TX Buffers | none | none | none | none | */ 3452 /* |Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */ 3453 /* |Context Memory | | | | | */ 3454 /* +-----------------+----------+----------+----------+----------+ */ 3455 /* */ 3456 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */ 3457 /* */ 3458 /* Returns: */ 3459 /* 0 for success, positive value for failure. */ 3460 /****************************************************************************/ 3461 static int 3462 bce_dma_alloc(device_t dev) 3463 { 3464 struct bce_softc *sc; 3465 int i, error, rc = 0; 3466 bus_size_t max_size, max_seg_size; 3467 int max_segments; 3468 3469 sc = device_get_softc(dev); 3470 3471 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3472 3473 /* 3474 * Allocate the parent bus DMA tag appropriate for PCI. 3475 */ 3476 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY, 3477 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3478 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3479 &sc->parent_tag)) { 3480 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 3481 __FILE__, __LINE__); 3482 rc = ENOMEM; 3483 goto bce_dma_alloc_exit; 3484 } 3485 3486 /* 3487 * Create a DMA tag for the status block, allocate and clear the 3488 * memory, map the memory into DMA space, and fetch the physical 3489 * address of the block. 3490 */ 3491 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3492 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3493 NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ, 3494 0, NULL, NULL, &sc->status_tag)) { 3495 BCE_PRINTF("%s(%d): Could not allocate status block " 3496 "DMA tag!\n", __FILE__, __LINE__); 3497 rc = ENOMEM; 3498 goto bce_dma_alloc_exit; 3499 } 3500 3501 if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block, 3502 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3503 &sc->status_map)) { 3504 BCE_PRINTF("%s(%d): Could not allocate status block " 3505 "DMA memory!\n", __FILE__, __LINE__); 3506 rc = ENOMEM; 3507 goto bce_dma_alloc_exit; 3508 } 3509 3510 error = bus_dmamap_load(sc->status_tag, sc->status_map, 3511 sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr, 3512 &sc->status_block_paddr, BUS_DMA_NOWAIT); 3513 3514 if (error) { 3515 BCE_PRINTF("%s(%d): Could not map status block " 3516 "DMA memory!\n", __FILE__, __LINE__); 3517 rc = ENOMEM; 3518 goto bce_dma_alloc_exit; 3519 } 3520 3521 DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n", 3522 __FUNCTION__, (uintmax_t) sc->status_block_paddr); 3523 3524 /* 3525 * Create a DMA tag for the statistics block, allocate and clear the 3526 * memory, map the memory into DMA space, and fetch the physical 3527 * address of the block. 3528 */ 3529 if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN, 3530 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3531 NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ, 3532 0, NULL, NULL, &sc->stats_tag)) { 3533 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3534 "DMA tag!\n", __FILE__, __LINE__); 3535 rc = ENOMEM; 3536 goto bce_dma_alloc_exit; 3537 } 3538 3539 if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block, 3540 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) { 3541 BCE_PRINTF("%s(%d): Could not allocate statistics block " 3542 "DMA memory!\n", __FILE__, __LINE__); 3543 rc = ENOMEM; 3544 goto bce_dma_alloc_exit; 3545 } 3546 3547 error = bus_dmamap_load(sc->stats_tag, sc->stats_map, 3548 sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr, 3549 &sc->stats_block_paddr, BUS_DMA_NOWAIT); 3550 3551 if(error) { 3552 BCE_PRINTF("%s(%d): Could not map statistics block " 3553 "DMA memory!\n", __FILE__, __LINE__); 3554 rc = ENOMEM; 3555 goto bce_dma_alloc_exit; 3556 } 3557 3558 DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n", 3559 __FUNCTION__, (uintmax_t) sc->stats_block_paddr); 3560 3561 /* BCM5709 uses host memory as cache for context memory. */ 3562 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 3563 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE; 3564 if (sc->ctx_pages == 0) 3565 sc->ctx_pages = 1; 3566 3567 DBRUNIF((sc->ctx_pages > 512), 3568 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n", 3569 __FILE__, __LINE__, sc->ctx_pages)); 3570 3571 /* 3572 * Create a DMA tag for the context pages, 3573 * allocate and clear the memory, map the 3574 * memory into DMA space, and fetch the 3575 * physical address of the block. 3576 */ 3577 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3578 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, 3579 NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE, 3580 0, NULL, NULL, &sc->ctx_tag)) { 3581 BCE_PRINTF("%s(%d): Could not allocate CTX " 3582 "DMA tag!\n", __FILE__, __LINE__); 3583 rc = ENOMEM; 3584 goto bce_dma_alloc_exit; 3585 } 3586 3587 for (i = 0; i < sc->ctx_pages; i++) { 3588 3589 if(bus_dmamem_alloc(sc->ctx_tag, 3590 (void **)&sc->ctx_block[i], 3591 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3592 &sc->ctx_map[i])) { 3593 BCE_PRINTF("%s(%d): Could not allocate CTX " 3594 "DMA memory!\n", __FILE__, __LINE__); 3595 rc = ENOMEM; 3596 goto bce_dma_alloc_exit; 3597 } 3598 3599 error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i], 3600 sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr, 3601 &sc->ctx_paddr[i], BUS_DMA_NOWAIT); 3602 3603 if (error) { 3604 BCE_PRINTF("%s(%d): Could not map CTX " 3605 "DMA memory!\n", __FILE__, __LINE__); 3606 rc = ENOMEM; 3607 goto bce_dma_alloc_exit; 3608 } 3609 3610 DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] " 3611 "= 0x%jX\n", __FUNCTION__, i, 3612 (uintmax_t) sc->ctx_paddr[i]); 3613 } 3614 } 3615 3616 /* 3617 * Create a DMA tag for the TX buffer descriptor chain, 3618 * allocate and clear the memory, and fetch the 3619 * physical address of the block. 3620 */ 3621 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY, 3622 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3623 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0, 3624 NULL, NULL, &sc->tx_bd_chain_tag)) { 3625 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3626 "chain DMA tag!\n", __FILE__, __LINE__); 3627 rc = ENOMEM; 3628 goto bce_dma_alloc_exit; 3629 } 3630 3631 for (i = 0; i < sc->tx_pages; i++) { 3632 3633 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 3634 (void **)&sc->tx_bd_chain[i], 3635 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3636 &sc->tx_bd_chain_map[i])) { 3637 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 3638 "chain DMA memory!\n", __FILE__, __LINE__); 3639 rc = ENOMEM; 3640 goto bce_dma_alloc_exit; 3641 } 3642 3643 error = bus_dmamap_load(sc->tx_bd_chain_tag, 3644 sc->tx_bd_chain_map[i], sc->tx_bd_chain[i], 3645 BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3646 &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3647 3648 if (error) { 3649 BCE_PRINTF("%s(%d): Could not map TX descriptor " 3650 "chain DMA memory!\n", __FILE__, __LINE__); 3651 rc = ENOMEM; 3652 goto bce_dma_alloc_exit; 3653 } 3654 3655 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = " 3656 "0x%jX\n", __FUNCTION__, i, 3657 (uintmax_t) sc->tx_bd_chain_paddr[i]); 3658 } 3659 3660 /* Check the required size before mapping to conserve resources. */ 3661 if (bce_tso_enable) { 3662 max_size = BCE_TSO_MAX_SIZE; 3663 max_segments = BCE_MAX_SEGMENTS; 3664 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 3665 } else { 3666 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 3667 max_segments = BCE_MAX_SEGMENTS; 3668 max_seg_size = MCLBYTES; 3669 } 3670 3671 /* Create a DMA tag for TX mbufs. */ 3672 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3673 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size, 3674 max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) { 3675 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 3676 __FILE__, __LINE__); 3677 rc = ENOMEM; 3678 goto bce_dma_alloc_exit; 3679 } 3680 3681 /* Create DMA maps for the TX mbufs clusters. */ 3682 for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) { 3683 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 3684 &sc->tx_mbuf_map[i])) { 3685 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA " 3686 "map!\n", __FILE__, __LINE__); 3687 rc = ENOMEM; 3688 goto bce_dma_alloc_exit; 3689 } 3690 } 3691 3692 /* 3693 * Create a DMA tag for the RX buffer descriptor chain, 3694 * allocate and clear the memory, and fetch the physical 3695 * address of the blocks. 3696 */ 3697 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3698 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, 3699 sc->max_bus_addr, NULL, NULL, 3700 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ, 3701 0, NULL, NULL, &sc->rx_bd_chain_tag)) { 3702 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 3703 "DMA tag!\n", __FILE__, __LINE__); 3704 rc = ENOMEM; 3705 goto bce_dma_alloc_exit; 3706 } 3707 3708 for (i = 0; i < sc->rx_pages; i++) { 3709 3710 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 3711 (void **)&sc->rx_bd_chain[i], 3712 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3713 &sc->rx_bd_chain_map[i])) { 3714 BCE_PRINTF("%s(%d): Could not allocate RX descriptor " 3715 "chain DMA memory!\n", __FILE__, __LINE__); 3716 rc = ENOMEM; 3717 goto bce_dma_alloc_exit; 3718 } 3719 3720 error = bus_dmamap_load(sc->rx_bd_chain_tag, 3721 sc->rx_bd_chain_map[i], sc->rx_bd_chain[i], 3722 BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr, 3723 &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3724 3725 if (error) { 3726 BCE_PRINTF("%s(%d): Could not map RX descriptor " 3727 "chain DMA memory!\n", __FILE__, __LINE__); 3728 rc = ENOMEM; 3729 goto bce_dma_alloc_exit; 3730 } 3731 3732 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = " 3733 "0x%jX\n", __FUNCTION__, i, 3734 (uintmax_t) sc->rx_bd_chain_paddr[i]); 3735 } 3736 3737 /* 3738 * Create a DMA tag for RX mbufs. 3739 */ 3740 if (bce_hdr_split == TRUE) 3741 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ? 3742 MCLBYTES : sc->rx_bd_mbuf_alloc_size); 3743 else 3744 max_size = max_seg_size = MJUM9BYTES; 3745 max_segments = 1; 3746 3747 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag " 3748 "(max size = 0x%jX max segments = %d, max segment " 3749 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size, 3750 max_segments, (uintmax_t) max_seg_size); 3751 3752 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN, 3753 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3754 max_size, max_segments, max_seg_size, 0, NULL, NULL, 3755 &sc->rx_mbuf_tag)) { 3756 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 3757 __FILE__, __LINE__); 3758 rc = ENOMEM; 3759 goto bce_dma_alloc_exit; 3760 } 3761 3762 /* Create DMA maps for the RX mbuf clusters. */ 3763 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) { 3764 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 3765 &sc->rx_mbuf_map[i])) { 3766 BCE_PRINTF("%s(%d): Unable to create RX mbuf " 3767 "DMA map!\n", __FILE__, __LINE__); 3768 rc = ENOMEM; 3769 goto bce_dma_alloc_exit; 3770 } 3771 } 3772 3773 if (bce_hdr_split == TRUE) { 3774 /* 3775 * Create a DMA tag for the page buffer descriptor chain, 3776 * allocate and clear the memory, and fetch the physical 3777 * address of the blocks. 3778 */ 3779 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 3780 BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr, 3781 NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ, 3782 0, NULL, NULL, &sc->pg_bd_chain_tag)) { 3783 BCE_PRINTF("%s(%d): Could not allocate page descriptor " 3784 "chain DMA tag!\n", __FILE__, __LINE__); 3785 rc = ENOMEM; 3786 goto bce_dma_alloc_exit; 3787 } 3788 3789 for (i = 0; i < sc->pg_pages; i++) { 3790 if (bus_dmamem_alloc(sc->pg_bd_chain_tag, 3791 (void **)&sc->pg_bd_chain[i], 3792 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 3793 &sc->pg_bd_chain_map[i])) { 3794 BCE_PRINTF("%s(%d): Could not allocate page " 3795 "descriptor chain DMA memory!\n", 3796 __FILE__, __LINE__); 3797 rc = ENOMEM; 3798 goto bce_dma_alloc_exit; 3799 } 3800 3801 error = bus_dmamap_load(sc->pg_bd_chain_tag, 3802 sc->pg_bd_chain_map[i], sc->pg_bd_chain[i], 3803 BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr, 3804 &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT); 3805 3806 if (error) { 3807 BCE_PRINTF("%s(%d): Could not map page descriptor " 3808 "chain DMA memory!\n", __FILE__, __LINE__); 3809 rc = ENOMEM; 3810 goto bce_dma_alloc_exit; 3811 } 3812 3813 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = " 3814 "0x%jX\n", __FUNCTION__, i, 3815 (uintmax_t) sc->pg_bd_chain_paddr[i]); 3816 } 3817 3818 /* 3819 * Create a DMA tag for page mbufs. 3820 */ 3821 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ? 3822 MCLBYTES : sc->pg_bd_mbuf_alloc_size); 3823 3824 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY, 3825 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, 3826 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) { 3827 BCE_PRINTF("%s(%d): Could not allocate page mbuf " 3828 "DMA tag!\n", __FILE__, __LINE__); 3829 rc = ENOMEM; 3830 goto bce_dma_alloc_exit; 3831 } 3832 3833 /* Create DMA maps for the page mbuf clusters. */ 3834 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) { 3835 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT, 3836 &sc->pg_mbuf_map[i])) { 3837 BCE_PRINTF("%s(%d): Unable to create page mbuf " 3838 "DMA map!\n", __FILE__, __LINE__); 3839 rc = ENOMEM; 3840 goto bce_dma_alloc_exit; 3841 } 3842 } 3843 } 3844 3845 bce_dma_alloc_exit: 3846 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 3847 return(rc); 3848 } 3849 3850 3851 /****************************************************************************/ 3852 /* Release all resources used by the driver. */ 3853 /* */ 3854 /* Releases all resources acquired by the driver including interrupts, */ 3855 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 3856 /* */ 3857 /* Returns: */ 3858 /* Nothing. */ 3859 /****************************************************************************/ 3860 static void 3861 bce_release_resources(struct bce_softc *sc) 3862 { 3863 device_t dev; 3864 3865 DBENTER(BCE_VERBOSE_RESET); 3866 3867 dev = sc->bce_dev; 3868 3869 bce_dma_free(sc); 3870 3871 if (sc->bce_intrhand != NULL) { 3872 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 3873 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 3874 } 3875 3876 if (sc->bce_res_irq != NULL) { 3877 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 3878 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid, 3879 sc->bce_res_irq); 3880 } 3881 3882 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) { 3883 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n"); 3884 pci_release_msi(dev); 3885 } 3886 3887 if (sc->bce_res_mem != NULL) { 3888 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 3889 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 3890 sc->bce_res_mem); 3891 } 3892 3893 if (sc->bce_ifp != NULL) { 3894 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 3895 if_free(sc->bce_ifp); 3896 } 3897 3898 if (mtx_initialized(&sc->bce_mtx)) 3899 BCE_LOCK_DESTROY(sc); 3900 3901 DBEXIT(BCE_VERBOSE_RESET); 3902 } 3903 3904 3905 /****************************************************************************/ 3906 /* Firmware synchronization. */ 3907 /* */ 3908 /* Before performing certain events such as a chip reset, synchronize with */ 3909 /* the firmware first. */ 3910 /* */ 3911 /* Returns: */ 3912 /* 0 for success, positive value for failure. */ 3913 /****************************************************************************/ 3914 static int 3915 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 3916 { 3917 int i, rc = 0; 3918 u32 val; 3919 3920 DBENTER(BCE_VERBOSE_RESET); 3921 3922 /* Don't waste any time if we've timed out before. */ 3923 if (sc->bce_fw_timed_out == TRUE) { 3924 rc = EBUSY; 3925 goto bce_fw_sync_exit; 3926 } 3927 3928 /* Increment the message sequence number. */ 3929 sc->bce_fw_wr_seq++; 3930 msg_data |= sc->bce_fw_wr_seq; 3931 3932 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = " 3933 "0x%08X\n", msg_data); 3934 3935 /* Send the message to the bootcode driver mailbox. */ 3936 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3937 3938 /* Wait for the bootcode to acknowledge the message. */ 3939 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 3940 /* Check for a response in the bootcode firmware mailbox. */ 3941 val = bce_shmem_rd(sc, BCE_FW_MB); 3942 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 3943 break; 3944 DELAY(1000); 3945 } 3946 3947 /* If we've timed out, tell bootcode that we've stopped waiting. */ 3948 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 3949 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 3950 3951 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 3952 "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data); 3953 3954 msg_data &= ~BCE_DRV_MSG_CODE; 3955 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 3956 3957 bce_shmem_wr(sc, BCE_DRV_MB, msg_data); 3958 3959 sc->bce_fw_timed_out = TRUE; 3960 rc = EBUSY; 3961 } 3962 3963 bce_fw_sync_exit: 3964 DBEXIT(BCE_VERBOSE_RESET); 3965 return (rc); 3966 } 3967 3968 3969 /****************************************************************************/ 3970 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 3971 /* */ 3972 /* Returns: */ 3973 /* Nothing. */ 3974 /****************************************************************************/ 3975 static void 3976 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 3977 u32 rv2p_code_len, u32 rv2p_proc) 3978 { 3979 int i; 3980 u32 val; 3981 3982 DBENTER(BCE_VERBOSE_RESET); 3983 3984 /* Set the page size used by RV2P. */ 3985 if (rv2p_proc == RV2P_PROC2) { 3986 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE); 3987 } 3988 3989 for (i = 0; i < rv2p_code_len; i += 8) { 3990 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 3991 rv2p_code++; 3992 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 3993 rv2p_code++; 3994 3995 if (rv2p_proc == RV2P_PROC1) { 3996 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 3997 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 3998 } 3999 else { 4000 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 4001 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 4002 } 4003 } 4004 4005 /* Reset the processor, un-stall is done later. */ 4006 if (rv2p_proc == RV2P_PROC1) { 4007 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 4008 } 4009 else { 4010 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 4011 } 4012 4013 DBEXIT(BCE_VERBOSE_RESET); 4014 } 4015 4016 4017 /****************************************************************************/ 4018 /* Load RISC processor firmware. */ 4019 /* */ 4020 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 4021 /* associated with a particular processor. */ 4022 /* */ 4023 /* Returns: */ 4024 /* Nothing. */ 4025 /****************************************************************************/ 4026 static void 4027 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 4028 struct fw_info *fw) 4029 { 4030 u32 offset; 4031 4032 DBENTER(BCE_VERBOSE_RESET); 4033 4034 bce_halt_cpu(sc, cpu_reg); 4035 4036 /* Load the Text area. */ 4037 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 4038 if (fw->text) { 4039 int j; 4040 4041 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 4042 REG_WR_IND(sc, offset, fw->text[j]); 4043 } 4044 } 4045 4046 /* Load the Data area. */ 4047 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 4048 if (fw->data) { 4049 int j; 4050 4051 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 4052 REG_WR_IND(sc, offset, fw->data[j]); 4053 } 4054 } 4055 4056 /* Load the SBSS area. */ 4057 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 4058 if (fw->sbss) { 4059 int j; 4060 4061 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 4062 REG_WR_IND(sc, offset, fw->sbss[j]); 4063 } 4064 } 4065 4066 /* Load the BSS area. */ 4067 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 4068 if (fw->bss) { 4069 int j; 4070 4071 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 4072 REG_WR_IND(sc, offset, fw->bss[j]); 4073 } 4074 } 4075 4076 /* Load the Read-Only area. */ 4077 offset = cpu_reg->spad_base + 4078 (fw->rodata_addr - cpu_reg->mips_view_base); 4079 if (fw->rodata) { 4080 int j; 4081 4082 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 4083 REG_WR_IND(sc, offset, fw->rodata[j]); 4084 } 4085 } 4086 4087 /* Clear the pre-fetch instruction and set the FW start address. */ 4088 REG_WR_IND(sc, cpu_reg->inst, 0); 4089 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 4090 4091 DBEXIT(BCE_VERBOSE_RESET); 4092 } 4093 4094 4095 /****************************************************************************/ 4096 /* Starts the RISC processor. */ 4097 /* */ 4098 /* Assumes the CPU starting address has already been set. */ 4099 /* */ 4100 /* Returns: */ 4101 /* Nothing. */ 4102 /****************************************************************************/ 4103 static void 4104 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4105 { 4106 u32 val; 4107 4108 DBENTER(BCE_VERBOSE_RESET); 4109 4110 /* Start the CPU. */ 4111 val = REG_RD_IND(sc, cpu_reg->mode); 4112 val &= ~cpu_reg->mode_value_halt; 4113 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4114 REG_WR_IND(sc, cpu_reg->mode, val); 4115 4116 DBEXIT(BCE_VERBOSE_RESET); 4117 } 4118 4119 4120 /****************************************************************************/ 4121 /* Halts the RISC processor. */ 4122 /* */ 4123 /* Returns: */ 4124 /* Nothing. */ 4125 /****************************************************************************/ 4126 static void 4127 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg) 4128 { 4129 u32 val; 4130 4131 DBENTER(BCE_VERBOSE_RESET); 4132 4133 /* Halt the CPU. */ 4134 val = REG_RD_IND(sc, cpu_reg->mode); 4135 val |= cpu_reg->mode_value_halt; 4136 REG_WR_IND(sc, cpu_reg->mode, val); 4137 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 4138 4139 DBEXIT(BCE_VERBOSE_RESET); 4140 } 4141 4142 4143 /****************************************************************************/ 4144 /* Initialize the RX CPU. */ 4145 /* */ 4146 /* Returns: */ 4147 /* Nothing. */ 4148 /****************************************************************************/ 4149 static void 4150 bce_start_rxp_cpu(struct bce_softc *sc) 4151 { 4152 struct cpu_reg cpu_reg; 4153 4154 DBENTER(BCE_VERBOSE_RESET); 4155 4156 cpu_reg.mode = BCE_RXP_CPU_MODE; 4157 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4158 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4159 cpu_reg.state = BCE_RXP_CPU_STATE; 4160 cpu_reg.state_value_clear = 0xffffff; 4161 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4162 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4163 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4164 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4165 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4166 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4167 cpu_reg.mips_view_base = 0x8000000; 4168 4169 DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n"); 4170 bce_start_cpu(sc, &cpu_reg); 4171 4172 DBEXIT(BCE_VERBOSE_RESET); 4173 } 4174 4175 4176 /****************************************************************************/ 4177 /* Initialize the RX CPU. */ 4178 /* */ 4179 /* Returns: */ 4180 /* Nothing. */ 4181 /****************************************************************************/ 4182 static void 4183 bce_init_rxp_cpu(struct bce_softc *sc) 4184 { 4185 struct cpu_reg cpu_reg; 4186 struct fw_info fw; 4187 4188 DBENTER(BCE_VERBOSE_RESET); 4189 4190 cpu_reg.mode = BCE_RXP_CPU_MODE; 4191 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 4192 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 4193 cpu_reg.state = BCE_RXP_CPU_STATE; 4194 cpu_reg.state_value_clear = 0xffffff; 4195 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 4196 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 4197 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 4198 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 4199 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 4200 cpu_reg.spad_base = BCE_RXP_SCRATCH; 4201 cpu_reg.mips_view_base = 0x8000000; 4202 4203 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4204 fw.ver_major = bce_RXP_b09FwReleaseMajor; 4205 fw.ver_minor = bce_RXP_b09FwReleaseMinor; 4206 fw.ver_fix = bce_RXP_b09FwReleaseFix; 4207 fw.start_addr = bce_RXP_b09FwStartAddr; 4208 4209 fw.text_addr = bce_RXP_b09FwTextAddr; 4210 fw.text_len = bce_RXP_b09FwTextLen; 4211 fw.text_index = 0; 4212 fw.text = bce_RXP_b09FwText; 4213 4214 fw.data_addr = bce_RXP_b09FwDataAddr; 4215 fw.data_len = bce_RXP_b09FwDataLen; 4216 fw.data_index = 0; 4217 fw.data = bce_RXP_b09FwData; 4218 4219 fw.sbss_addr = bce_RXP_b09FwSbssAddr; 4220 fw.sbss_len = bce_RXP_b09FwSbssLen; 4221 fw.sbss_index = 0; 4222 fw.sbss = bce_RXP_b09FwSbss; 4223 4224 fw.bss_addr = bce_RXP_b09FwBssAddr; 4225 fw.bss_len = bce_RXP_b09FwBssLen; 4226 fw.bss_index = 0; 4227 fw.bss = bce_RXP_b09FwBss; 4228 4229 fw.rodata_addr = bce_RXP_b09FwRodataAddr; 4230 fw.rodata_len = bce_RXP_b09FwRodataLen; 4231 fw.rodata_index = 0; 4232 fw.rodata = bce_RXP_b09FwRodata; 4233 } else { 4234 fw.ver_major = bce_RXP_b06FwReleaseMajor; 4235 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 4236 fw.ver_fix = bce_RXP_b06FwReleaseFix; 4237 fw.start_addr = bce_RXP_b06FwStartAddr; 4238 4239 fw.text_addr = bce_RXP_b06FwTextAddr; 4240 fw.text_len = bce_RXP_b06FwTextLen; 4241 fw.text_index = 0; 4242 fw.text = bce_RXP_b06FwText; 4243 4244 fw.data_addr = bce_RXP_b06FwDataAddr; 4245 fw.data_len = bce_RXP_b06FwDataLen; 4246 fw.data_index = 0; 4247 fw.data = bce_RXP_b06FwData; 4248 4249 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 4250 fw.sbss_len = bce_RXP_b06FwSbssLen; 4251 fw.sbss_index = 0; 4252 fw.sbss = bce_RXP_b06FwSbss; 4253 4254 fw.bss_addr = bce_RXP_b06FwBssAddr; 4255 fw.bss_len = bce_RXP_b06FwBssLen; 4256 fw.bss_index = 0; 4257 fw.bss = bce_RXP_b06FwBss; 4258 4259 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 4260 fw.rodata_len = bce_RXP_b06FwRodataLen; 4261 fw.rodata_index = 0; 4262 fw.rodata = bce_RXP_b06FwRodata; 4263 } 4264 4265 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 4266 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4267 4268 /* Delay RXP start until initialization is complete. */ 4269 4270 DBEXIT(BCE_VERBOSE_RESET); 4271 } 4272 4273 4274 /****************************************************************************/ 4275 /* Initialize the TX CPU. */ 4276 /* */ 4277 /* Returns: */ 4278 /* Nothing. */ 4279 /****************************************************************************/ 4280 static void 4281 bce_init_txp_cpu(struct bce_softc *sc) 4282 { 4283 struct cpu_reg cpu_reg; 4284 struct fw_info fw; 4285 4286 DBENTER(BCE_VERBOSE_RESET); 4287 4288 cpu_reg.mode = BCE_TXP_CPU_MODE; 4289 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 4290 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 4291 cpu_reg.state = BCE_TXP_CPU_STATE; 4292 cpu_reg.state_value_clear = 0xffffff; 4293 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 4294 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 4295 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 4296 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 4297 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 4298 cpu_reg.spad_base = BCE_TXP_SCRATCH; 4299 cpu_reg.mips_view_base = 0x8000000; 4300 4301 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4302 fw.ver_major = bce_TXP_b09FwReleaseMajor; 4303 fw.ver_minor = bce_TXP_b09FwReleaseMinor; 4304 fw.ver_fix = bce_TXP_b09FwReleaseFix; 4305 fw.start_addr = bce_TXP_b09FwStartAddr; 4306 4307 fw.text_addr = bce_TXP_b09FwTextAddr; 4308 fw.text_len = bce_TXP_b09FwTextLen; 4309 fw.text_index = 0; 4310 fw.text = bce_TXP_b09FwText; 4311 4312 fw.data_addr = bce_TXP_b09FwDataAddr; 4313 fw.data_len = bce_TXP_b09FwDataLen; 4314 fw.data_index = 0; 4315 fw.data = bce_TXP_b09FwData; 4316 4317 fw.sbss_addr = bce_TXP_b09FwSbssAddr; 4318 fw.sbss_len = bce_TXP_b09FwSbssLen; 4319 fw.sbss_index = 0; 4320 fw.sbss = bce_TXP_b09FwSbss; 4321 4322 fw.bss_addr = bce_TXP_b09FwBssAddr; 4323 fw.bss_len = bce_TXP_b09FwBssLen; 4324 fw.bss_index = 0; 4325 fw.bss = bce_TXP_b09FwBss; 4326 4327 fw.rodata_addr = bce_TXP_b09FwRodataAddr; 4328 fw.rodata_len = bce_TXP_b09FwRodataLen; 4329 fw.rodata_index = 0; 4330 fw.rodata = bce_TXP_b09FwRodata; 4331 } else { 4332 fw.ver_major = bce_TXP_b06FwReleaseMajor; 4333 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 4334 fw.ver_fix = bce_TXP_b06FwReleaseFix; 4335 fw.start_addr = bce_TXP_b06FwStartAddr; 4336 4337 fw.text_addr = bce_TXP_b06FwTextAddr; 4338 fw.text_len = bce_TXP_b06FwTextLen; 4339 fw.text_index = 0; 4340 fw.text = bce_TXP_b06FwText; 4341 4342 fw.data_addr = bce_TXP_b06FwDataAddr; 4343 fw.data_len = bce_TXP_b06FwDataLen; 4344 fw.data_index = 0; 4345 fw.data = bce_TXP_b06FwData; 4346 4347 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 4348 fw.sbss_len = bce_TXP_b06FwSbssLen; 4349 fw.sbss_index = 0; 4350 fw.sbss = bce_TXP_b06FwSbss; 4351 4352 fw.bss_addr = bce_TXP_b06FwBssAddr; 4353 fw.bss_len = bce_TXP_b06FwBssLen; 4354 fw.bss_index = 0; 4355 fw.bss = bce_TXP_b06FwBss; 4356 4357 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 4358 fw.rodata_len = bce_TXP_b06FwRodataLen; 4359 fw.rodata_index = 0; 4360 fw.rodata = bce_TXP_b06FwRodata; 4361 } 4362 4363 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 4364 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4365 bce_start_cpu(sc, &cpu_reg); 4366 4367 DBEXIT(BCE_VERBOSE_RESET); 4368 } 4369 4370 4371 /****************************************************************************/ 4372 /* Initialize the TPAT CPU. */ 4373 /* */ 4374 /* Returns: */ 4375 /* Nothing. */ 4376 /****************************************************************************/ 4377 static void 4378 bce_init_tpat_cpu(struct bce_softc *sc) 4379 { 4380 struct cpu_reg cpu_reg; 4381 struct fw_info fw; 4382 4383 DBENTER(BCE_VERBOSE_RESET); 4384 4385 cpu_reg.mode = BCE_TPAT_CPU_MODE; 4386 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 4387 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 4388 cpu_reg.state = BCE_TPAT_CPU_STATE; 4389 cpu_reg.state_value_clear = 0xffffff; 4390 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 4391 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 4392 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 4393 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 4394 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 4395 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 4396 cpu_reg.mips_view_base = 0x8000000; 4397 4398 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4399 fw.ver_major = bce_TPAT_b09FwReleaseMajor; 4400 fw.ver_minor = bce_TPAT_b09FwReleaseMinor; 4401 fw.ver_fix = bce_TPAT_b09FwReleaseFix; 4402 fw.start_addr = bce_TPAT_b09FwStartAddr; 4403 4404 fw.text_addr = bce_TPAT_b09FwTextAddr; 4405 fw.text_len = bce_TPAT_b09FwTextLen; 4406 fw.text_index = 0; 4407 fw.text = bce_TPAT_b09FwText; 4408 4409 fw.data_addr = bce_TPAT_b09FwDataAddr; 4410 fw.data_len = bce_TPAT_b09FwDataLen; 4411 fw.data_index = 0; 4412 fw.data = bce_TPAT_b09FwData; 4413 4414 fw.sbss_addr = bce_TPAT_b09FwSbssAddr; 4415 fw.sbss_len = bce_TPAT_b09FwSbssLen; 4416 fw.sbss_index = 0; 4417 fw.sbss = bce_TPAT_b09FwSbss; 4418 4419 fw.bss_addr = bce_TPAT_b09FwBssAddr; 4420 fw.bss_len = bce_TPAT_b09FwBssLen; 4421 fw.bss_index = 0; 4422 fw.bss = bce_TPAT_b09FwBss; 4423 4424 fw.rodata_addr = bce_TPAT_b09FwRodataAddr; 4425 fw.rodata_len = bce_TPAT_b09FwRodataLen; 4426 fw.rodata_index = 0; 4427 fw.rodata = bce_TPAT_b09FwRodata; 4428 } else { 4429 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 4430 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 4431 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 4432 fw.start_addr = bce_TPAT_b06FwStartAddr; 4433 4434 fw.text_addr = bce_TPAT_b06FwTextAddr; 4435 fw.text_len = bce_TPAT_b06FwTextLen; 4436 fw.text_index = 0; 4437 fw.text = bce_TPAT_b06FwText; 4438 4439 fw.data_addr = bce_TPAT_b06FwDataAddr; 4440 fw.data_len = bce_TPAT_b06FwDataLen; 4441 fw.data_index = 0; 4442 fw.data = bce_TPAT_b06FwData; 4443 4444 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 4445 fw.sbss_len = bce_TPAT_b06FwSbssLen; 4446 fw.sbss_index = 0; 4447 fw.sbss = bce_TPAT_b06FwSbss; 4448 4449 fw.bss_addr = bce_TPAT_b06FwBssAddr; 4450 fw.bss_len = bce_TPAT_b06FwBssLen; 4451 fw.bss_index = 0; 4452 fw.bss = bce_TPAT_b06FwBss; 4453 4454 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 4455 fw.rodata_len = bce_TPAT_b06FwRodataLen; 4456 fw.rodata_index = 0; 4457 fw.rodata = bce_TPAT_b06FwRodata; 4458 } 4459 4460 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 4461 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4462 bce_start_cpu(sc, &cpu_reg); 4463 4464 DBEXIT(BCE_VERBOSE_RESET); 4465 } 4466 4467 4468 /****************************************************************************/ 4469 /* Initialize the CP CPU. */ 4470 /* */ 4471 /* Returns: */ 4472 /* Nothing. */ 4473 /****************************************************************************/ 4474 static void 4475 bce_init_cp_cpu(struct bce_softc *sc) 4476 { 4477 struct cpu_reg cpu_reg; 4478 struct fw_info fw; 4479 4480 DBENTER(BCE_VERBOSE_RESET); 4481 4482 cpu_reg.mode = BCE_CP_CPU_MODE; 4483 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT; 4484 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA; 4485 cpu_reg.state = BCE_CP_CPU_STATE; 4486 cpu_reg.state_value_clear = 0xffffff; 4487 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE; 4488 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK; 4489 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER; 4490 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION; 4491 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT; 4492 cpu_reg.spad_base = BCE_CP_SCRATCH; 4493 cpu_reg.mips_view_base = 0x8000000; 4494 4495 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4496 fw.ver_major = bce_CP_b09FwReleaseMajor; 4497 fw.ver_minor = bce_CP_b09FwReleaseMinor; 4498 fw.ver_fix = bce_CP_b09FwReleaseFix; 4499 fw.start_addr = bce_CP_b09FwStartAddr; 4500 4501 fw.text_addr = bce_CP_b09FwTextAddr; 4502 fw.text_len = bce_CP_b09FwTextLen; 4503 fw.text_index = 0; 4504 fw.text = bce_CP_b09FwText; 4505 4506 fw.data_addr = bce_CP_b09FwDataAddr; 4507 fw.data_len = bce_CP_b09FwDataLen; 4508 fw.data_index = 0; 4509 fw.data = bce_CP_b09FwData; 4510 4511 fw.sbss_addr = bce_CP_b09FwSbssAddr; 4512 fw.sbss_len = bce_CP_b09FwSbssLen; 4513 fw.sbss_index = 0; 4514 fw.sbss = bce_CP_b09FwSbss; 4515 4516 fw.bss_addr = bce_CP_b09FwBssAddr; 4517 fw.bss_len = bce_CP_b09FwBssLen; 4518 fw.bss_index = 0; 4519 fw.bss = bce_CP_b09FwBss; 4520 4521 fw.rodata_addr = bce_CP_b09FwRodataAddr; 4522 fw.rodata_len = bce_CP_b09FwRodataLen; 4523 fw.rodata_index = 0; 4524 fw.rodata = bce_CP_b09FwRodata; 4525 } else { 4526 fw.ver_major = bce_CP_b06FwReleaseMajor; 4527 fw.ver_minor = bce_CP_b06FwReleaseMinor; 4528 fw.ver_fix = bce_CP_b06FwReleaseFix; 4529 fw.start_addr = bce_CP_b06FwStartAddr; 4530 4531 fw.text_addr = bce_CP_b06FwTextAddr; 4532 fw.text_len = bce_CP_b06FwTextLen; 4533 fw.text_index = 0; 4534 fw.text = bce_CP_b06FwText; 4535 4536 fw.data_addr = bce_CP_b06FwDataAddr; 4537 fw.data_len = bce_CP_b06FwDataLen; 4538 fw.data_index = 0; 4539 fw.data = bce_CP_b06FwData; 4540 4541 fw.sbss_addr = bce_CP_b06FwSbssAddr; 4542 fw.sbss_len = bce_CP_b06FwSbssLen; 4543 fw.sbss_index = 0; 4544 fw.sbss = bce_CP_b06FwSbss; 4545 4546 fw.bss_addr = bce_CP_b06FwBssAddr; 4547 fw.bss_len = bce_CP_b06FwBssLen; 4548 fw.bss_index = 0; 4549 fw.bss = bce_CP_b06FwBss; 4550 4551 fw.rodata_addr = bce_CP_b06FwRodataAddr; 4552 fw.rodata_len = bce_CP_b06FwRodataLen; 4553 fw.rodata_index = 0; 4554 fw.rodata = bce_CP_b06FwRodata; 4555 } 4556 4557 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n"); 4558 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4559 bce_start_cpu(sc, &cpu_reg); 4560 4561 DBEXIT(BCE_VERBOSE_RESET); 4562 } 4563 4564 4565 /****************************************************************************/ 4566 /* Initialize the COM CPU. */ 4567 /* */ 4568 /* Returns: */ 4569 /* Nothing. */ 4570 /****************************************************************************/ 4571 static void 4572 bce_init_com_cpu(struct bce_softc *sc) 4573 { 4574 struct cpu_reg cpu_reg; 4575 struct fw_info fw; 4576 4577 DBENTER(BCE_VERBOSE_RESET); 4578 4579 cpu_reg.mode = BCE_COM_CPU_MODE; 4580 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 4581 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 4582 cpu_reg.state = BCE_COM_CPU_STATE; 4583 cpu_reg.state_value_clear = 0xffffff; 4584 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 4585 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 4586 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 4587 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 4588 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 4589 cpu_reg.spad_base = BCE_COM_SCRATCH; 4590 cpu_reg.mips_view_base = 0x8000000; 4591 4592 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4593 fw.ver_major = bce_COM_b09FwReleaseMajor; 4594 fw.ver_minor = bce_COM_b09FwReleaseMinor; 4595 fw.ver_fix = bce_COM_b09FwReleaseFix; 4596 fw.start_addr = bce_COM_b09FwStartAddr; 4597 4598 fw.text_addr = bce_COM_b09FwTextAddr; 4599 fw.text_len = bce_COM_b09FwTextLen; 4600 fw.text_index = 0; 4601 fw.text = bce_COM_b09FwText; 4602 4603 fw.data_addr = bce_COM_b09FwDataAddr; 4604 fw.data_len = bce_COM_b09FwDataLen; 4605 fw.data_index = 0; 4606 fw.data = bce_COM_b09FwData; 4607 4608 fw.sbss_addr = bce_COM_b09FwSbssAddr; 4609 fw.sbss_len = bce_COM_b09FwSbssLen; 4610 fw.sbss_index = 0; 4611 fw.sbss = bce_COM_b09FwSbss; 4612 4613 fw.bss_addr = bce_COM_b09FwBssAddr; 4614 fw.bss_len = bce_COM_b09FwBssLen; 4615 fw.bss_index = 0; 4616 fw.bss = bce_COM_b09FwBss; 4617 4618 fw.rodata_addr = bce_COM_b09FwRodataAddr; 4619 fw.rodata_len = bce_COM_b09FwRodataLen; 4620 fw.rodata_index = 0; 4621 fw.rodata = bce_COM_b09FwRodata; 4622 } else { 4623 fw.ver_major = bce_COM_b06FwReleaseMajor; 4624 fw.ver_minor = bce_COM_b06FwReleaseMinor; 4625 fw.ver_fix = bce_COM_b06FwReleaseFix; 4626 fw.start_addr = bce_COM_b06FwStartAddr; 4627 4628 fw.text_addr = bce_COM_b06FwTextAddr; 4629 fw.text_len = bce_COM_b06FwTextLen; 4630 fw.text_index = 0; 4631 fw.text = bce_COM_b06FwText; 4632 4633 fw.data_addr = bce_COM_b06FwDataAddr; 4634 fw.data_len = bce_COM_b06FwDataLen; 4635 fw.data_index = 0; 4636 fw.data = bce_COM_b06FwData; 4637 4638 fw.sbss_addr = bce_COM_b06FwSbssAddr; 4639 fw.sbss_len = bce_COM_b06FwSbssLen; 4640 fw.sbss_index = 0; 4641 fw.sbss = bce_COM_b06FwSbss; 4642 4643 fw.bss_addr = bce_COM_b06FwBssAddr; 4644 fw.bss_len = bce_COM_b06FwBssLen; 4645 fw.bss_index = 0; 4646 fw.bss = bce_COM_b06FwBss; 4647 4648 fw.rodata_addr = bce_COM_b06FwRodataAddr; 4649 fw.rodata_len = bce_COM_b06FwRodataLen; 4650 fw.rodata_index = 0; 4651 fw.rodata = bce_COM_b06FwRodata; 4652 } 4653 4654 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 4655 bce_load_cpu_fw(sc, &cpu_reg, &fw); 4656 bce_start_cpu(sc, &cpu_reg); 4657 4658 DBEXIT(BCE_VERBOSE_RESET); 4659 } 4660 4661 4662 /****************************************************************************/ 4663 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */ 4664 /* */ 4665 /* Loads the firmware for each CPU and starts the CPU. */ 4666 /* */ 4667 /* Returns: */ 4668 /* Nothing. */ 4669 /****************************************************************************/ 4670 static void 4671 bce_init_cpus(struct bce_softc *sc) 4672 { 4673 DBENTER(BCE_VERBOSE_RESET); 4674 4675 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4676 4677 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) { 4678 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1, 4679 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1); 4680 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2, 4681 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2); 4682 } else { 4683 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, 4684 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1); 4685 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, 4686 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2); 4687 } 4688 4689 } else { 4690 bce_load_rv2p_fw(sc, bce_rv2p_proc1, 4691 sizeof(bce_rv2p_proc1), RV2P_PROC1); 4692 bce_load_rv2p_fw(sc, bce_rv2p_proc2, 4693 sizeof(bce_rv2p_proc2), RV2P_PROC2); 4694 } 4695 4696 bce_init_rxp_cpu(sc); 4697 bce_init_txp_cpu(sc); 4698 bce_init_tpat_cpu(sc); 4699 bce_init_com_cpu(sc); 4700 bce_init_cp_cpu(sc); 4701 4702 DBEXIT(BCE_VERBOSE_RESET); 4703 } 4704 4705 4706 /****************************************************************************/ 4707 /* Initialize context memory. */ 4708 /* */ 4709 /* Clears the memory associated with each Context ID (CID). */ 4710 /* */ 4711 /* Returns: */ 4712 /* Nothing. */ 4713 /****************************************************************************/ 4714 static int 4715 bce_init_ctx(struct bce_softc *sc) 4716 { 4717 u32 offset, val, vcid_addr; 4718 int i, j, rc, retry_cnt; 4719 4720 rc = 0; 4721 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4722 4723 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4724 retry_cnt = CTX_INIT_RETRY_COUNT; 4725 4726 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n"); 4727 4728 /* 4729 * BCM5709 context memory may be cached 4730 * in host memory so prepare the host memory 4731 * for access. 4732 */ 4733 val = BCE_CTX_COMMAND_ENABLED | 4734 BCE_CTX_COMMAND_MEM_INIT | (1 << 12); 4735 val |= (BCM_PAGE_BITS - 8) << 16; 4736 REG_WR(sc, BCE_CTX_COMMAND, val); 4737 4738 /* Wait for mem init command to complete. */ 4739 for (i = 0; i < retry_cnt; i++) { 4740 val = REG_RD(sc, BCE_CTX_COMMAND); 4741 if (!(val & BCE_CTX_COMMAND_MEM_INIT)) 4742 break; 4743 DELAY(2); 4744 } 4745 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) { 4746 BCE_PRINTF("%s(): Context memory initialization failed!\n", 4747 __FUNCTION__); 4748 rc = EBUSY; 4749 goto init_ctx_fail; 4750 } 4751 4752 for (i = 0; i < sc->ctx_pages; i++) { 4753 /* Set the physical address of the context memory. */ 4754 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0, 4755 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) | 4756 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID); 4757 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1, 4758 BCE_ADDR_HI(sc->ctx_paddr[i])); 4759 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i | 4760 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ); 4761 4762 /* Verify the context memory write was successful. */ 4763 for (j = 0; j < retry_cnt; j++) { 4764 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL); 4765 if ((val & 4766 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0) 4767 break; 4768 DELAY(5); 4769 } 4770 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) { 4771 BCE_PRINTF("%s(): Failed to initialize " 4772 "context page %d!\n", __FUNCTION__, i); 4773 rc = EBUSY; 4774 goto init_ctx_fail; 4775 } 4776 } 4777 } else { 4778 4779 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n"); 4780 4781 /* 4782 * For the 5706/5708, context memory is local to 4783 * the controller, so initialize the controller 4784 * context memory. 4785 */ 4786 4787 vcid_addr = GET_CID_ADDR(96); 4788 while (vcid_addr) { 4789 4790 vcid_addr -= PHY_CTX_SIZE; 4791 4792 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0); 4793 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4794 4795 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 4796 CTX_WR(sc, 0x00, offset, 0); 4797 } 4798 4799 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 4800 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr); 4801 } 4802 4803 } 4804 init_ctx_fail: 4805 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX); 4806 return (rc); 4807 } 4808 4809 4810 /****************************************************************************/ 4811 /* Fetch the permanent MAC address of the controller. */ 4812 /* */ 4813 /* Returns: */ 4814 /* Nothing. */ 4815 /****************************************************************************/ 4816 static void 4817 bce_get_mac_addr(struct bce_softc *sc) 4818 { 4819 u32 mac_lo = 0, mac_hi = 0; 4820 4821 DBENTER(BCE_VERBOSE_RESET); 4822 4823 /* 4824 * The NetXtreme II bootcode populates various NIC 4825 * power-on and runtime configuration items in a 4826 * shared memory area. The factory configured MAC 4827 * address is available from both NVRAM and the 4828 * shared memory area so we'll read the value from 4829 * shared memory for speed. 4830 */ 4831 4832 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER); 4833 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER); 4834 4835 if ((mac_lo == 0) && (mac_hi == 0)) { 4836 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 4837 __FILE__, __LINE__); 4838 } else { 4839 sc->eaddr[0] = (u_char)(mac_hi >> 8); 4840 sc->eaddr[1] = (u_char)(mac_hi >> 0); 4841 sc->eaddr[2] = (u_char)(mac_lo >> 24); 4842 sc->eaddr[3] = (u_char)(mac_lo >> 16); 4843 sc->eaddr[4] = (u_char)(mac_lo >> 8); 4844 sc->eaddr[5] = (u_char)(mac_lo >> 0); 4845 } 4846 4847 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet " 4848 "address = %6D\n", sc->eaddr, ":"); 4849 DBEXIT(BCE_VERBOSE_RESET); 4850 } 4851 4852 4853 /****************************************************************************/ 4854 /* Program the MAC address. */ 4855 /* */ 4856 /* Returns: */ 4857 /* Nothing. */ 4858 /****************************************************************************/ 4859 static void 4860 bce_set_mac_addr(struct bce_softc *sc) 4861 { 4862 u32 val; 4863 u8 *mac_addr = sc->eaddr; 4864 4865 /* ToDo: Add support for setting multiple MAC addresses. */ 4866 4867 DBENTER(BCE_VERBOSE_RESET); 4868 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = " 4869 "%6D\n", sc->eaddr, ":"); 4870 4871 val = (mac_addr[0] << 8) | mac_addr[1]; 4872 4873 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 4874 4875 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 4876 (mac_addr[4] << 8) | mac_addr[5]; 4877 4878 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 4879 4880 DBEXIT(BCE_VERBOSE_RESET); 4881 } 4882 4883 4884 /****************************************************************************/ 4885 /* Stop the controller. */ 4886 /* */ 4887 /* Returns: */ 4888 /* Nothing. */ 4889 /****************************************************************************/ 4890 static void 4891 bce_stop(struct bce_softc *sc) 4892 { 4893 struct ifnet *ifp; 4894 4895 DBENTER(BCE_VERBOSE_RESET); 4896 4897 BCE_LOCK_ASSERT(sc); 4898 4899 ifp = sc->bce_ifp; 4900 4901 callout_stop(&sc->bce_tick_callout); 4902 4903 /* Disable the transmit/receive blocks. */ 4904 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT); 4905 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4906 DELAY(20); 4907 4908 bce_disable_intr(sc); 4909 4910 /* Free RX buffers. */ 4911 if (bce_hdr_split == TRUE) { 4912 bce_free_pg_chain(sc); 4913 } 4914 bce_free_rx_chain(sc); 4915 4916 /* Free TX buffers. */ 4917 bce_free_tx_chain(sc); 4918 4919 sc->watchdog_timer = 0; 4920 4921 sc->bce_link_up = FALSE; 4922 4923 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4924 4925 DBEXIT(BCE_VERBOSE_RESET); 4926 } 4927 4928 4929 static int 4930 bce_reset(struct bce_softc *sc, u32 reset_code) 4931 { 4932 u32 val; 4933 int i, rc = 0; 4934 4935 DBENTER(BCE_VERBOSE_RESET); 4936 4937 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 4938 __FUNCTION__, reset_code); 4939 4940 /* Wait for pending PCI transactions to complete. */ 4941 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 4942 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 4943 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 4944 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 4945 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 4946 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 4947 DELAY(5); 4948 4949 /* Disable DMA */ 4950 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4951 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 4952 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 4953 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 4954 } 4955 4956 /* Assume bootcode is running. */ 4957 sc->bce_fw_timed_out = FALSE; 4958 sc->bce_drv_cardiac_arrest = FALSE; 4959 4960 /* Give the firmware a chance to prepare for the reset. */ 4961 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 4962 if (rc) 4963 goto bce_reset_exit; 4964 4965 /* Set a firmware reminder that this is a soft reset. */ 4966 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC); 4967 4968 /* Dummy read to force the chip to complete all current transactions. */ 4969 val = REG_RD(sc, BCE_MISC_ID); 4970 4971 /* Chip reset. */ 4972 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 4973 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET); 4974 REG_RD(sc, BCE_MISC_COMMAND); 4975 DELAY(5); 4976 4977 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4978 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4979 4980 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4); 4981 } else { 4982 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4983 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 4984 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 4985 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 4986 4987 /* Allow up to 30us for reset to complete. */ 4988 for (i = 0; i < 10; i++) { 4989 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 4990 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4991 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 4992 break; 4993 } 4994 DELAY(10); 4995 } 4996 4997 /* Check that reset completed successfully. */ 4998 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 4999 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 5000 BCE_PRINTF("%s(%d): Reset failed!\n", 5001 __FILE__, __LINE__); 5002 rc = EBUSY; 5003 goto bce_reset_exit; 5004 } 5005 } 5006 5007 /* Make sure byte swapping is properly configured. */ 5008 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 5009 if (val != 0x01020304) { 5010 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 5011 __FILE__, __LINE__); 5012 rc = ENODEV; 5013 goto bce_reset_exit; 5014 } 5015 5016 /* Just completed a reset, assume that firmware is running again. */ 5017 sc->bce_fw_timed_out = FALSE; 5018 sc->bce_drv_cardiac_arrest = FALSE; 5019 5020 /* Wait for the firmware to finish its initialization. */ 5021 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 5022 if (rc) 5023 BCE_PRINTF("%s(%d): Firmware did not complete " 5024 "initialization!\n", __FILE__, __LINE__); 5025 5026 bce_reset_exit: 5027 DBEXIT(BCE_VERBOSE_RESET); 5028 return (rc); 5029 } 5030 5031 5032 static int 5033 bce_chipinit(struct bce_softc *sc) 5034 { 5035 u32 val; 5036 int rc = 0; 5037 5038 DBENTER(BCE_VERBOSE_RESET); 5039 5040 bce_disable_intr(sc); 5041 5042 /* 5043 * Initialize DMA byte/word swapping, configure the number of DMA 5044 * channels and PCI clock compensation delay. 5045 */ 5046 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 5047 BCE_DMA_CONFIG_DATA_WORD_SWAP | 5048 #if BYTE_ORDER == BIG_ENDIAN 5049 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 5050 #endif 5051 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 5052 DMA_READ_CHANS << 12 | 5053 DMA_WRITE_CHANS << 16; 5054 5055 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 5056 5057 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 5058 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 5059 5060 /* 5061 * This setting resolves a problem observed on certain Intel PCI 5062 * chipsets that cannot handle multiple outstanding DMA operations. 5063 * See errata E9_5706A1_65. 5064 */ 5065 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5066 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 5067 !(sc->bce_flags & BCE_PCIX_FLAG)) 5068 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 5069 5070 REG_WR(sc, BCE_DMA_CONFIG, val); 5071 5072 /* Enable the RX_V2P and Context state machines before access. */ 5073 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5074 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 5075 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 5076 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 5077 5078 /* Initialize context mapping and zero out the quick contexts. */ 5079 if ((rc = bce_init_ctx(sc)) != 0) 5080 goto bce_chipinit_exit; 5081 5082 /* Initialize the on-boards CPUs */ 5083 bce_init_cpus(sc); 5084 5085 /* Enable management frames (NC-SI) to flow to the MCP. */ 5086 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5087 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5088 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5089 } 5090 5091 /* Prepare NVRAM for access. */ 5092 if ((rc = bce_init_nvram(sc)) != 0) 5093 goto bce_chipinit_exit; 5094 5095 /* Set the kernel bypass block size */ 5096 val = REG_RD(sc, BCE_MQ_CONFIG); 5097 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 5098 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 5099 5100 /* Enable bins used on the 5709. */ 5101 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5102 val |= BCE_MQ_CONFIG_BIN_MQ_MODE; 5103 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1) 5104 val |= BCE_MQ_CONFIG_HALT_DIS; 5105 } 5106 5107 REG_WR(sc, BCE_MQ_CONFIG, val); 5108 5109 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 5110 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 5111 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 5112 5113 /* Set the page size and clear the RV2P processor stall bits. */ 5114 val = (BCM_PAGE_BITS - 8) << 24; 5115 REG_WR(sc, BCE_RV2P_CONFIG, val); 5116 5117 /* Configure page size. */ 5118 val = REG_RD(sc, BCE_TBDR_CONFIG); 5119 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 5120 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 5121 REG_WR(sc, BCE_TBDR_CONFIG, val); 5122 5123 /* Set the perfect match control register to default. */ 5124 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0); 5125 5126 bce_chipinit_exit: 5127 DBEXIT(BCE_VERBOSE_RESET); 5128 5129 return(rc); 5130 } 5131 5132 5133 /****************************************************************************/ 5134 /* Initialize the controller in preparation to send/receive traffic. */ 5135 /* */ 5136 /* Returns: */ 5137 /* 0 for success, positive value for failure. */ 5138 /****************************************************************************/ 5139 static int 5140 bce_blockinit(struct bce_softc *sc) 5141 { 5142 u32 reg, val; 5143 int rc = 0; 5144 5145 DBENTER(BCE_VERBOSE_RESET); 5146 5147 /* Load the hardware default MAC address. */ 5148 bce_set_mac_addr(sc); 5149 5150 /* Set the Ethernet backoff seed value */ 5151 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 5152 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 5153 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 5154 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 5155 5156 sc->last_status_idx = 0; 5157 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 5158 5159 /* Set up link change interrupt generation. */ 5160 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 5161 5162 /* Program the physical address of the status block. */ 5163 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 5164 BCE_ADDR_LO(sc->status_block_paddr)); 5165 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 5166 BCE_ADDR_HI(sc->status_block_paddr)); 5167 5168 /* Program the physical address of the statistics block. */ 5169 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 5170 BCE_ADDR_LO(sc->stats_block_paddr)); 5171 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 5172 BCE_ADDR_HI(sc->stats_block_paddr)); 5173 5174 /* Program various host coalescing parameters. */ 5175 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5176 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 5177 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5178 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 5179 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 5180 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 5181 REG_WR(sc, BCE_HC_TX_TICKS, 5182 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 5183 REG_WR(sc, BCE_HC_RX_TICKS, 5184 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 5185 REG_WR(sc, BCE_HC_COM_TICKS, 5186 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 5187 REG_WR(sc, BCE_HC_CMD_TICKS, 5188 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 5189 REG_WR(sc, BCE_HC_STATS_TICKS, 5190 (sc->bce_stats_ticks & 0xffff00)); 5191 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ 5192 5193 /* Configure the Host Coalescing block. */ 5194 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 5195 BCE_HC_CONFIG_COLLECT_STATS; 5196 5197 #if 0 5198 /* ToDo: Add MSI-X support. */ 5199 if (sc->bce_flags & BCE_USING_MSIX_FLAG) { 5200 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) + 5201 BCE_HC_SB_CONFIG_1; 5202 5203 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL); 5204 5205 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE | 5206 BCE_HC_SB_CONFIG_1_ONE_SHOT); 5207 5208 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF, 5209 (sc->tx_quick_cons_trip_int << 16) | 5210 sc->tx_quick_cons_trip); 5211 5212 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF, 5213 (sc->tx_ticks_int << 16) | sc->tx_ticks); 5214 5215 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5216 } 5217 5218 /* 5219 * Tell the HC block to automatically set the 5220 * INT_MASK bit after an MSI/MSI-X interrupt 5221 * is generated so the driver doesn't have to. 5222 */ 5223 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG) 5224 val |= BCE_HC_CONFIG_ONE_SHOT; 5225 5226 /* Set the MSI-X status blocks to 128 byte boundaries. */ 5227 if (sc->bce_flags & BCE_USING_MSIX_FLAG) 5228 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B; 5229 #endif 5230 5231 REG_WR(sc, BCE_HC_CONFIG, val); 5232 5233 /* Clear the internal statistics counters. */ 5234 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 5235 5236 /* Verify that bootcode is running. */ 5237 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE); 5238 5239 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control), 5240 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 5241 __FILE__, __LINE__); 5242 reg = 0); 5243 5244 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 5245 BCE_DEV_INFO_SIGNATURE_MAGIC) { 5246 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 5247 "Expected: 08%08X\n", __FILE__, __LINE__, 5248 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 5249 BCE_DEV_INFO_SIGNATURE_MAGIC); 5250 rc = ENODEV; 5251 goto bce_blockinit_exit; 5252 } 5253 5254 /* Enable DMA */ 5255 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5256 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL); 5257 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE; 5258 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val); 5259 } 5260 5261 /* Allow bootcode to apply additional fixes before enabling MAC. */ 5262 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | 5263 BCE_DRV_MSG_CODE_RESET); 5264 5265 /* Enable link state change interrupt generation. */ 5266 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 5267 5268 /* Enable the RXP. */ 5269 bce_start_rxp_cpu(sc); 5270 5271 /* Disable management frames (NC-SI) from flowing to the MCP. */ 5272 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5273 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) & 5274 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN; 5275 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val); 5276 } 5277 5278 /* Enable all remaining blocks in the MAC. */ 5279 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5280 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5281 BCE_MISC_ENABLE_DEFAULT_XI); 5282 else 5283 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 5284 BCE_MISC_ENABLE_DEFAULT); 5285 5286 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 5287 DELAY(20); 5288 5289 /* Save the current host coalescing block settings. */ 5290 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND); 5291 5292 bce_blockinit_exit: 5293 DBEXIT(BCE_VERBOSE_RESET); 5294 5295 return (rc); 5296 } 5297 5298 5299 /****************************************************************************/ 5300 /* Encapsulate an mbuf into the rx_bd chain. */ 5301 /* */ 5302 /* Returns: */ 5303 /* 0 for success, positive value for failure. */ 5304 /****************************************************************************/ 5305 static int 5306 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5307 u16 *chain_prod, u32 *prod_bseq) 5308 { 5309 bus_dmamap_t map; 5310 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 5311 struct mbuf *m_new = NULL; 5312 struct rx_bd *rxbd; 5313 int nsegs, error, rc = 0; 5314 #ifdef BCE_DEBUG 5315 u16 debug_chain_prod = *chain_prod; 5316 #endif 5317 5318 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5319 5320 /* Make sure the inputs are valid. */ 5321 DBRUNIF((*chain_prod > MAX_RX_BD_ALLOC), 5322 BCE_PRINTF("%s(%d): RX producer out of range: " 5323 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5324 *chain_prod, (u16) MAX_RX_BD_ALLOC)); 5325 5326 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5327 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, 5328 *prod, *chain_prod, *prod_bseq); 5329 5330 /* Update some debug statistic counters */ 5331 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 5332 sc->rx_low_watermark = sc->free_rx_bd); 5333 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 5334 sc->rx_empty_count++); 5335 5336 /* Check whether this is a new mbuf allocation. */ 5337 if (m == NULL) { 5338 5339 /* Simulate an mbuf allocation failure. */ 5340 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5341 sc->mbuf_alloc_failed_count++; 5342 sc->mbuf_alloc_failed_sim_count++; 5343 rc = ENOBUFS; 5344 goto bce_get_rx_buf_exit); 5345 5346 /* This is a new mbuf allocation. */ 5347 if (bce_hdr_split == TRUE) 5348 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 5349 else 5350 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, 5351 sc->rx_bd_mbuf_alloc_size); 5352 5353 if (m_new == NULL) { 5354 sc->mbuf_alloc_failed_count++; 5355 rc = ENOBUFS; 5356 goto bce_get_rx_buf_exit; 5357 } 5358 5359 DBRUN(sc->debug_rx_mbuf_alloc++); 5360 } else { 5361 /* Reuse an existing mbuf. */ 5362 m_new = m; 5363 } 5364 5365 /* Make sure we have a valid packet header. */ 5366 M_ASSERTPKTHDR(m_new); 5367 5368 /* Initialize the mbuf size and pad if necessary for alignment. */ 5369 m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size; 5370 m_adj(m_new, sc->rx_bd_mbuf_align_pad); 5371 5372 /* ToDo: Consider calling m_fragment() to test error handling. */ 5373 5374 /* Map the mbuf cluster into device memory. */ 5375 map = sc->rx_mbuf_map[*chain_prod]; 5376 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 5377 segs, &nsegs, BUS_DMA_NOWAIT); 5378 5379 /* Handle any mapping errors. */ 5380 if (error) { 5381 BCE_PRINTF("%s(%d): Error mapping mbuf into RX " 5382 "chain (%d)!\n", __FILE__, __LINE__, error); 5383 5384 sc->dma_map_addr_rx_failed_count++; 5385 m_freem(m_new); 5386 5387 DBRUN(sc->debug_rx_mbuf_alloc--); 5388 5389 rc = ENOBUFS; 5390 goto bce_get_rx_buf_exit; 5391 } 5392 5393 /* All mbufs must map to a single segment. */ 5394 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!", 5395 __FUNCTION__, nsegs)); 5396 5397 /* Setup the rx_bd for the segment. */ 5398 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 5399 5400 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 5401 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 5402 rxbd->rx_bd_len = htole32(segs[0].ds_len); 5403 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5404 *prod_bseq += segs[0].ds_len; 5405 5406 /* Save the mbuf and update our counter. */ 5407 sc->rx_mbuf_ptr[*chain_prod] = m_new; 5408 sc->free_rx_bd -= nsegs; 5409 5410 DBRUNMSG(BCE_INSANE_RECV, 5411 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs)); 5412 5413 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5414 "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", 5415 __FUNCTION__, *prod, *chain_prod, *prod_bseq); 5416 5417 bce_get_rx_buf_exit: 5418 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5419 5420 return(rc); 5421 } 5422 5423 5424 /****************************************************************************/ 5425 /* Encapsulate an mbuf cluster into the page chain. */ 5426 /* */ 5427 /* Returns: */ 5428 /* 0 for success, positive value for failure. */ 5429 /****************************************************************************/ 5430 static int 5431 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, 5432 u16 *prod_idx) 5433 { 5434 bus_dmamap_t map; 5435 bus_addr_t busaddr; 5436 struct mbuf *m_new = NULL; 5437 struct rx_bd *pgbd; 5438 int error, rc = 0; 5439 #ifdef BCE_DEBUG 5440 u16 debug_prod_idx = *prod_idx; 5441 #endif 5442 5443 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5444 5445 /* Make sure the inputs are valid. */ 5446 DBRUNIF((*prod_idx > MAX_PG_BD_ALLOC), 5447 BCE_PRINTF("%s(%d): page producer out of range: " 5448 "0x%04X > 0x%04X\n", __FILE__, __LINE__, 5449 *prod_idx, (u16) MAX_PG_BD_ALLOC)); 5450 5451 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, " 5452 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5453 5454 /* Update counters if we've hit a new low or run out of pages. */ 5455 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark), 5456 sc->pg_low_watermark = sc->free_pg_bd); 5457 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++); 5458 5459 /* Check whether this is a new mbuf allocation. */ 5460 if (m == NULL) { 5461 5462 /* Simulate an mbuf allocation failure. */ 5463 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control), 5464 sc->mbuf_alloc_failed_count++; 5465 sc->mbuf_alloc_failed_sim_count++; 5466 rc = ENOBUFS; 5467 goto bce_get_pg_buf_exit); 5468 5469 /* This is a new mbuf allocation. */ 5470 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0); 5471 if (m_new == NULL) { 5472 sc->mbuf_alloc_failed_count++; 5473 rc = ENOBUFS; 5474 goto bce_get_pg_buf_exit; 5475 } 5476 5477 DBRUN(sc->debug_pg_mbuf_alloc++); 5478 } else { 5479 /* Reuse an existing mbuf. */ 5480 m_new = m; 5481 m_new->m_data = m_new->m_ext.ext_buf; 5482 } 5483 5484 m_new->m_len = sc->pg_bd_mbuf_alloc_size; 5485 5486 /* ToDo: Consider calling m_fragment() to test error handling. */ 5487 5488 /* Map the mbuf cluster into device memory. */ 5489 map = sc->pg_mbuf_map[*prod_idx]; 5490 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *), 5491 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr, 5492 &busaddr, BUS_DMA_NOWAIT); 5493 5494 /* Handle any mapping errors. */ 5495 if (error) { 5496 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n", 5497 __FILE__, __LINE__); 5498 5499 m_freem(m_new); 5500 DBRUN(sc->debug_pg_mbuf_alloc--); 5501 5502 rc = ENOBUFS; 5503 goto bce_get_pg_buf_exit; 5504 } 5505 5506 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */ 5507 5508 /* 5509 * The page chain uses the same rx_bd data structure 5510 * as the receive chain but doesn't require a byte sequence (bseq). 5511 */ 5512 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)]; 5513 5514 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr)); 5515 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr)); 5516 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size); 5517 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END); 5518 5519 /* Save the mbuf and update our counter. */ 5520 sc->pg_mbuf_ptr[*prod_idx] = m_new; 5521 sc->free_pg_bd--; 5522 5523 DBRUNMSG(BCE_INSANE_RECV, 5524 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1)); 5525 5526 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, " 5527 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx); 5528 5529 bce_get_pg_buf_exit: 5530 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD); 5531 5532 return(rc); 5533 } 5534 5535 5536 /****************************************************************************/ 5537 /* Initialize the TX context memory. */ 5538 /* */ 5539 /* Returns: */ 5540 /* Nothing */ 5541 /****************************************************************************/ 5542 static void 5543 bce_init_tx_context(struct bce_softc *sc) 5544 { 5545 u32 val; 5546 5547 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5548 5549 /* Initialize the context ID for an L2 TX chain. */ 5550 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5551 /* Set the CID type to support an L2 connection. */ 5552 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI | 5553 BCE_L2CTX_TX_TYPE_SIZE_L2_XI; 5554 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val); 5555 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16); 5556 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5557 BCE_L2CTX_TX_CMD_TYPE_XI, val); 5558 5559 /* Point the hardware to the first page in the chain. */ 5560 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5561 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5562 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val); 5563 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5564 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5565 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val); 5566 } else { 5567 /* Set the CID type to support an L2 connection. */ 5568 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2; 5569 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val); 5570 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16); 5571 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val); 5572 5573 /* Point the hardware to the first page in the chain. */ 5574 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 5575 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5576 BCE_L2CTX_TX_TBDR_BHADDR_HI, val); 5577 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 5578 CTX_WR(sc, GET_CID_ADDR(TX_CID), 5579 BCE_L2CTX_TX_TBDR_BHADDR_LO, val); 5580 } 5581 5582 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 5583 } 5584 5585 5586 /****************************************************************************/ 5587 /* Allocate memory and initialize the TX data structures. */ 5588 /* */ 5589 /* Returns: */ 5590 /* 0 for success, positive value for failure. */ 5591 /****************************************************************************/ 5592 static int 5593 bce_init_tx_chain(struct bce_softc *sc) 5594 { 5595 struct tx_bd *txbd; 5596 int i, rc = 0; 5597 5598 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5599 5600 /* Set the initial TX producer/consumer indices. */ 5601 sc->tx_prod = 0; 5602 sc->tx_cons = 0; 5603 sc->tx_prod_bseq = 0; 5604 sc->used_tx_bd = 0; 5605 sc->max_tx_bd = USABLE_TX_BD_ALLOC; 5606 DBRUN(sc->tx_hi_watermark = 0); 5607 DBRUN(sc->tx_full_count = 0); 5608 5609 /* 5610 * The NetXtreme II supports a linked-list structre called 5611 * a Buffer Descriptor Chain (or BD chain). A BD chain 5612 * consists of a series of 1 or more chain pages, each of which 5613 * consists of a fixed number of BD entries. 5614 * The last BD entry on each page is a pointer to the next page 5615 * in the chain, and the last pointer in the BD chain 5616 * points back to the beginning of the chain. 5617 */ 5618 5619 /* Set the TX next pointer chain entries. */ 5620 for (i = 0; i < sc->tx_pages; i++) { 5621 int j; 5622 5623 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 5624 5625 /* Check if we've reached the last page. */ 5626 if (i == (sc->tx_pages - 1)) 5627 j = 0; 5628 else 5629 j = i + 1; 5630 5631 txbd->tx_bd_haddr_hi = 5632 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 5633 txbd->tx_bd_haddr_lo = 5634 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 5635 } 5636 5637 bce_init_tx_context(sc); 5638 5639 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC)); 5640 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD); 5641 5642 return(rc); 5643 } 5644 5645 5646 /****************************************************************************/ 5647 /* Free memory and clear the TX data structures. */ 5648 /* */ 5649 /* Returns: */ 5650 /* Nothing. */ 5651 /****************************************************************************/ 5652 static void 5653 bce_free_tx_chain(struct bce_softc *sc) 5654 { 5655 int i; 5656 5657 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5658 5659 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 5660 for (i = 0; i < MAX_TX_BD_AVAIL; i++) { 5661 if (sc->tx_mbuf_ptr[i] != NULL) { 5662 if (sc->tx_mbuf_map[i] != NULL) 5663 bus_dmamap_sync(sc->tx_mbuf_tag, 5664 sc->tx_mbuf_map[i], 5665 BUS_DMASYNC_POSTWRITE); 5666 m_freem(sc->tx_mbuf_ptr[i]); 5667 sc->tx_mbuf_ptr[i] = NULL; 5668 DBRUN(sc->debug_tx_mbuf_alloc--); 5669 } 5670 } 5671 5672 /* Clear each TX chain page. */ 5673 for (i = 0; i < sc->tx_pages; i++) 5674 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 5675 5676 sc->used_tx_bd = 0; 5677 5678 /* Check if we lost any mbufs in the process. */ 5679 DBRUNIF((sc->debug_tx_mbuf_alloc), 5680 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 5681 "from tx chain!\n", __FILE__, __LINE__, 5682 sc->debug_tx_mbuf_alloc)); 5683 5684 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD); 5685 } 5686 5687 5688 /****************************************************************************/ 5689 /* Initialize the RX context memory. */ 5690 /* */ 5691 /* Returns: */ 5692 /* Nothing */ 5693 /****************************************************************************/ 5694 static void 5695 bce_init_rx_context(struct bce_softc *sc) 5696 { 5697 u32 val; 5698 5699 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5700 5701 /* Init the type, size, and BD cache levels for the RX context. */ 5702 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE | 5703 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | 5704 (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT); 5705 5706 /* 5707 * Set the level for generating pause frames 5708 * when the number of available rx_bd's gets 5709 * too low (the low watermark) and the level 5710 * when pause frames can be stopped (the high 5711 * watermark). 5712 */ 5713 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5714 u32 lo_water, hi_water; 5715 5716 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) { 5717 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT; 5718 } else { 5719 lo_water = 0; 5720 } 5721 5722 if (lo_water >= USABLE_RX_BD_ALLOC) { 5723 lo_water = 0; 5724 } 5725 5726 hi_water = USABLE_RX_BD_ALLOC / 4; 5727 5728 if (hi_water <= lo_water) { 5729 lo_water = 0; 5730 } 5731 5732 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE; 5733 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE; 5734 5735 if (hi_water > 0xf) 5736 hi_water = 0xf; 5737 else if (hi_water == 0) 5738 lo_water = 0; 5739 5740 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) | 5741 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT); 5742 } 5743 5744 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val); 5745 5746 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */ 5747 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 5748 val = REG_RD(sc, BCE_MQ_MAP_L2_5); 5749 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM); 5750 } 5751 5752 /* Point the hardware to the first page in the chain. */ 5753 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 5754 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val); 5755 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 5756 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val); 5757 5758 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX); 5759 } 5760 5761 5762 /****************************************************************************/ 5763 /* Allocate memory and initialize the RX data structures. */ 5764 /* */ 5765 /* Returns: */ 5766 /* 0 for success, positive value for failure. */ 5767 /****************************************************************************/ 5768 static int 5769 bce_init_rx_chain(struct bce_softc *sc) 5770 { 5771 struct rx_bd *rxbd; 5772 int i, rc = 0; 5773 5774 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5775 BCE_VERBOSE_CTX); 5776 5777 /* Initialize the RX producer and consumer indices. */ 5778 sc->rx_prod = 0; 5779 sc->rx_cons = 0; 5780 sc->rx_prod_bseq = 0; 5781 sc->free_rx_bd = USABLE_RX_BD_ALLOC; 5782 sc->max_rx_bd = USABLE_RX_BD_ALLOC; 5783 5784 /* Initialize the RX next pointer chain entries. */ 5785 for (i = 0; i < sc->rx_pages; i++) { 5786 int j; 5787 5788 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 5789 5790 /* Check if we've reached the last page. */ 5791 if (i == (sc->rx_pages - 1)) 5792 j = 0; 5793 else 5794 j = i + 1; 5795 5796 /* Setup the chain page pointers. */ 5797 rxbd->rx_bd_haddr_hi = 5798 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 5799 rxbd->rx_bd_haddr_lo = 5800 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 5801 } 5802 5803 /* Fill up the RX chain. */ 5804 bce_fill_rx_chain(sc); 5805 5806 DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC); 5807 DBRUN(sc->rx_empty_count = 0); 5808 for (i = 0; i < sc->rx_pages; i++) { 5809 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i], 5810 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5811 } 5812 5813 bce_init_rx_context(sc); 5814 5815 DBRUNMSG(BCE_EXTREME_RECV, 5816 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC)); 5817 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5818 BCE_VERBOSE_CTX); 5819 5820 /* ToDo: Are there possible failure modes here? */ 5821 5822 return(rc); 5823 } 5824 5825 5826 /****************************************************************************/ 5827 /* Add mbufs to the RX chain until its full or an mbuf allocation error */ 5828 /* occurs. */ 5829 /* */ 5830 /* Returns: */ 5831 /* Nothing */ 5832 /****************************************************************************/ 5833 static void 5834 bce_fill_rx_chain(struct bce_softc *sc) 5835 { 5836 u16 prod, prod_idx; 5837 u32 prod_bseq; 5838 5839 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5840 BCE_VERBOSE_CTX); 5841 5842 /* Get the RX chain producer indices. */ 5843 prod = sc->rx_prod; 5844 prod_bseq = sc->rx_prod_bseq; 5845 5846 /* Keep filling the RX chain until it's full. */ 5847 while (sc->free_rx_bd > 0) { 5848 prod_idx = RX_CHAIN_IDX(prod); 5849 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) { 5850 /* Bail out if we can't add an mbuf to the chain. */ 5851 break; 5852 } 5853 prod = NEXT_RX_BD(prod); 5854 } 5855 5856 /* Save the RX chain producer indices. */ 5857 sc->rx_prod = prod; 5858 sc->rx_prod_bseq = prod_bseq; 5859 5860 /* We should never end up pointing to a next page pointer. */ 5861 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 5862 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n", 5863 __FUNCTION__, sc->rx_prod)); 5864 5865 /* Write the mailbox and tell the chip about the waiting rx_bd's. */ 5866 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 5867 BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod); 5868 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + 5869 BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq); 5870 5871 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 5872 BCE_VERBOSE_CTX); 5873 } 5874 5875 5876 /****************************************************************************/ 5877 /* Free memory and clear the RX data structures. */ 5878 /* */ 5879 /* Returns: */ 5880 /* Nothing. */ 5881 /****************************************************************************/ 5882 static void 5883 bce_free_rx_chain(struct bce_softc *sc) 5884 { 5885 int i; 5886 5887 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5888 5889 /* Free any mbufs still in the RX mbuf chain. */ 5890 for (i = 0; i < MAX_RX_BD_AVAIL; i++) { 5891 if (sc->rx_mbuf_ptr[i] != NULL) { 5892 if (sc->rx_mbuf_map[i] != NULL) 5893 bus_dmamap_sync(sc->rx_mbuf_tag, 5894 sc->rx_mbuf_map[i], 5895 BUS_DMASYNC_POSTREAD); 5896 m_freem(sc->rx_mbuf_ptr[i]); 5897 sc->rx_mbuf_ptr[i] = NULL; 5898 DBRUN(sc->debug_rx_mbuf_alloc--); 5899 } 5900 } 5901 5902 /* Clear each RX chain page. */ 5903 for (i = 0; i < sc->rx_pages; i++) 5904 if (sc->rx_bd_chain[i] != NULL) { 5905 bzero((char *)sc->rx_bd_chain[i], 5906 BCE_RX_CHAIN_PAGE_SZ); 5907 } 5908 5909 sc->free_rx_bd = sc->max_rx_bd; 5910 5911 /* Check if we lost any mbufs in the process. */ 5912 DBRUNIF((sc->debug_rx_mbuf_alloc), 5913 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n", 5914 __FUNCTION__, sc->debug_rx_mbuf_alloc)); 5915 5916 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 5917 } 5918 5919 5920 /****************************************************************************/ 5921 /* Allocate memory and initialize the page data structures. */ 5922 /* Assumes that bce_init_rx_chain() has not already been called. */ 5923 /* */ 5924 /* Returns: */ 5925 /* 0 for success, positive value for failure. */ 5926 /****************************************************************************/ 5927 static int 5928 bce_init_pg_chain(struct bce_softc *sc) 5929 { 5930 struct rx_bd *pgbd; 5931 int i, rc = 0; 5932 u32 val; 5933 5934 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5935 BCE_VERBOSE_CTX); 5936 5937 /* Initialize the page producer and consumer indices. */ 5938 sc->pg_prod = 0; 5939 sc->pg_cons = 0; 5940 sc->free_pg_bd = USABLE_PG_BD_ALLOC; 5941 sc->max_pg_bd = USABLE_PG_BD_ALLOC; 5942 DBRUN(sc->pg_low_watermark = sc->max_pg_bd); 5943 DBRUN(sc->pg_empty_count = 0); 5944 5945 /* Initialize the page next pointer chain entries. */ 5946 for (i = 0; i < sc->pg_pages; i++) { 5947 int j; 5948 5949 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE]; 5950 5951 /* Check if we've reached the last page. */ 5952 if (i == (sc->pg_pages - 1)) 5953 j = 0; 5954 else 5955 j = i + 1; 5956 5957 /* Setup the chain page pointers. */ 5958 pgbd->rx_bd_haddr_hi = 5959 htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j])); 5960 pgbd->rx_bd_haddr_lo = 5961 htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j])); 5962 } 5963 5964 /* Setup the MQ BIN mapping for host_pg_bidx. */ 5965 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 5966 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT); 5967 5968 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0); 5969 5970 /* Configure the rx_bd and page chain mbuf cluster size. */ 5971 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size; 5972 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val); 5973 5974 /* Configure the context reserved for jumbo support. */ 5975 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY, 5976 BCE_L2CTX_RX_RBDC_JUMBO_KEY); 5977 5978 /* Point the hardware to the first page in the page chain. */ 5979 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]); 5980 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val); 5981 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]); 5982 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val); 5983 5984 /* Fill up the page chain. */ 5985 bce_fill_pg_chain(sc); 5986 5987 for (i = 0; i < sc->pg_pages; i++) { 5988 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i], 5989 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 5990 } 5991 5992 DBRUNMSG(BCE_EXTREME_RECV, 5993 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC)); 5994 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD | 5995 BCE_VERBOSE_CTX); 5996 return(rc); 5997 } 5998 5999 6000 /****************************************************************************/ 6001 /* Add mbufs to the page chain until its full or an mbuf allocation error */ 6002 /* occurs. */ 6003 /* */ 6004 /* Returns: */ 6005 /* Nothing */ 6006 /****************************************************************************/ 6007 static void 6008 bce_fill_pg_chain(struct bce_softc *sc) 6009 { 6010 u16 prod, prod_idx; 6011 6012 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6013 BCE_VERBOSE_CTX); 6014 6015 /* Get the page chain prodcuer index. */ 6016 prod = sc->pg_prod; 6017 6018 /* Keep filling the page chain until it's full. */ 6019 while (sc->free_pg_bd > 0) { 6020 prod_idx = PG_CHAIN_IDX(prod); 6021 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) { 6022 /* Bail out if we can't add an mbuf to the chain. */ 6023 break; 6024 } 6025 prod = NEXT_PG_BD(prod); 6026 } 6027 6028 /* Save the page chain producer index. */ 6029 sc->pg_prod = prod; 6030 6031 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE), 6032 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n", 6033 __FUNCTION__, sc->pg_prod)); 6034 6035 /* 6036 * Write the mailbox and tell the chip about 6037 * the new rx_bd's in the page chain. 6038 */ 6039 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + 6040 BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod); 6041 6042 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD | 6043 BCE_VERBOSE_CTX); 6044 } 6045 6046 6047 /****************************************************************************/ 6048 /* Free memory and clear the RX data structures. */ 6049 /* */ 6050 /* Returns: */ 6051 /* Nothing. */ 6052 /****************************************************************************/ 6053 static void 6054 bce_free_pg_chain(struct bce_softc *sc) 6055 { 6056 int i; 6057 6058 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6059 6060 /* Free any mbufs still in the mbuf page chain. */ 6061 for (i = 0; i < MAX_PG_BD_AVAIL; i++) { 6062 if (sc->pg_mbuf_ptr[i] != NULL) { 6063 if (sc->pg_mbuf_map[i] != NULL) 6064 bus_dmamap_sync(sc->pg_mbuf_tag, 6065 sc->pg_mbuf_map[i], 6066 BUS_DMASYNC_POSTREAD); 6067 m_freem(sc->pg_mbuf_ptr[i]); 6068 sc->pg_mbuf_ptr[i] = NULL; 6069 DBRUN(sc->debug_pg_mbuf_alloc--); 6070 } 6071 } 6072 6073 /* Clear each page chain pages. */ 6074 for (i = 0; i < sc->pg_pages; i++) 6075 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ); 6076 6077 sc->free_pg_bd = sc->max_pg_bd; 6078 6079 /* Check if we lost any mbufs in the process. */ 6080 DBRUNIF((sc->debug_pg_mbuf_alloc), 6081 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n", 6082 __FUNCTION__, sc->debug_pg_mbuf_alloc)); 6083 6084 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD); 6085 } 6086 6087 6088 /****************************************************************************/ 6089 /* Set media options. */ 6090 /* */ 6091 /* Returns: */ 6092 /* 0 for success, positive value for failure. */ 6093 /****************************************************************************/ 6094 static int 6095 bce_ifmedia_upd(struct ifnet *ifp) 6096 { 6097 struct bce_softc *sc = ifp->if_softc; 6098 int error; 6099 6100 DBENTER(BCE_VERBOSE); 6101 6102 BCE_LOCK(sc); 6103 error = bce_ifmedia_upd_locked(ifp); 6104 BCE_UNLOCK(sc); 6105 6106 DBEXIT(BCE_VERBOSE); 6107 return (error); 6108 } 6109 6110 6111 /****************************************************************************/ 6112 /* Set media options. */ 6113 /* */ 6114 /* Returns: */ 6115 /* Nothing. */ 6116 /****************************************************************************/ 6117 static int 6118 bce_ifmedia_upd_locked(struct ifnet *ifp) 6119 { 6120 struct bce_softc *sc = ifp->if_softc; 6121 struct mii_data *mii; 6122 struct mii_softc *miisc; 6123 int error; 6124 6125 DBENTER(BCE_VERBOSE_PHY); 6126 6127 error = 0; 6128 BCE_LOCK_ASSERT(sc); 6129 6130 mii = device_get_softc(sc->bce_miibus); 6131 6132 /* Make sure the MII bus has been enumerated. */ 6133 if (mii) { 6134 sc->bce_link_up = FALSE; 6135 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 6136 PHY_RESET(miisc); 6137 error = mii_mediachg(mii); 6138 } 6139 6140 DBEXIT(BCE_VERBOSE_PHY); 6141 return (error); 6142 } 6143 6144 6145 /****************************************************************************/ 6146 /* Reports current media status. */ 6147 /* */ 6148 /* Returns: */ 6149 /* Nothing. */ 6150 /****************************************************************************/ 6151 static void 6152 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 6153 { 6154 struct bce_softc *sc = ifp->if_softc; 6155 struct mii_data *mii; 6156 6157 DBENTER(BCE_VERBOSE_PHY); 6158 6159 BCE_LOCK(sc); 6160 6161 if ((ifp->if_flags & IFF_UP) == 0) { 6162 BCE_UNLOCK(sc); 6163 return; 6164 } 6165 mii = device_get_softc(sc->bce_miibus); 6166 6167 mii_pollstat(mii); 6168 ifmr->ifm_active = mii->mii_media_active; 6169 ifmr->ifm_status = mii->mii_media_status; 6170 6171 BCE_UNLOCK(sc); 6172 6173 DBEXIT(BCE_VERBOSE_PHY); 6174 } 6175 6176 6177 /****************************************************************************/ 6178 /* Handles PHY generated interrupt events. */ 6179 /* */ 6180 /* Returns: */ 6181 /* Nothing. */ 6182 /****************************************************************************/ 6183 static void 6184 bce_phy_intr(struct bce_softc *sc) 6185 { 6186 u32 new_link_state, old_link_state; 6187 6188 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6189 6190 DBRUN(sc->phy_interrupts++); 6191 6192 new_link_state = sc->status_block->status_attn_bits & 6193 STATUS_ATTN_BITS_LINK_STATE; 6194 old_link_state = sc->status_block->status_attn_bits_ack & 6195 STATUS_ATTN_BITS_LINK_STATE; 6196 6197 /* Handle any changes if the link state has changed. */ 6198 if (new_link_state != old_link_state) { 6199 6200 /* Update the status_attn_bits_ack field. */ 6201 if (new_link_state) { 6202 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 6203 STATUS_ATTN_BITS_LINK_STATE); 6204 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n", 6205 __FUNCTION__); 6206 } 6207 else { 6208 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 6209 STATUS_ATTN_BITS_LINK_STATE); 6210 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n", 6211 __FUNCTION__); 6212 } 6213 6214 /* 6215 * Assume link is down and allow 6216 * tick routine to update the state 6217 * based on the actual media state. 6218 */ 6219 sc->bce_link_up = FALSE; 6220 callout_stop(&sc->bce_tick_callout); 6221 bce_tick(sc); 6222 } 6223 6224 /* Acknowledge the link change interrupt. */ 6225 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 6226 6227 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR); 6228 } 6229 6230 6231 /****************************************************************************/ 6232 /* Reads the receive consumer value from the status block (skipping over */ 6233 /* chain page pointer if necessary). */ 6234 /* */ 6235 /* Returns: */ 6236 /* hw_cons */ 6237 /****************************************************************************/ 6238 static inline u16 6239 bce_get_hw_rx_cons(struct bce_softc *sc) 6240 { 6241 u16 hw_cons; 6242 6243 rmb(); 6244 hw_cons = sc->status_block->status_rx_quick_consumer_index0; 6245 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6246 hw_cons++; 6247 6248 return hw_cons; 6249 } 6250 6251 /****************************************************************************/ 6252 /* Handles received frame interrupt events. */ 6253 /* */ 6254 /* Returns: */ 6255 /* Nothing. */ 6256 /****************************************************************************/ 6257 static void 6258 bce_rx_intr(struct bce_softc *sc) 6259 { 6260 struct ifnet *ifp = sc->bce_ifp; 6261 struct l2_fhdr *l2fhdr; 6262 struct ether_vlan_header *vh; 6263 unsigned int pkt_len; 6264 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons; 6265 u32 status; 6266 unsigned int rem_len; 6267 u16 sw_pg_cons, sw_pg_cons_idx; 6268 6269 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6270 DBRUN(sc->interrupts_rx++); 6271 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, " 6272 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6273 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6274 6275 /* Prepare the RX chain pages to be accessed by the host CPU. */ 6276 for (int i = 0; i < sc->rx_pages; i++) 6277 bus_dmamap_sync(sc->rx_bd_chain_tag, 6278 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6279 6280 /* Prepare the page chain pages to be accessed by the host CPU. */ 6281 if (bce_hdr_split == TRUE) { 6282 for (int i = 0; i < sc->pg_pages; i++) 6283 bus_dmamap_sync(sc->pg_bd_chain_tag, 6284 sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD); 6285 } 6286 6287 /* Get the hardware's view of the RX consumer index. */ 6288 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6289 6290 /* Get working copies of the driver's view of the consumer indices. */ 6291 sw_rx_cons = sc->rx_cons; 6292 sw_pg_cons = sc->pg_cons; 6293 6294 /* Update some debug statistics counters */ 6295 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 6296 sc->rx_low_watermark = sc->free_rx_bd); 6297 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), 6298 sc->rx_empty_count++); 6299 6300 /* Scan through the receive chain as long as there is work to do */ 6301 /* ToDo: Consider setting a limit on the number of packets processed. */ 6302 rmb(); 6303 while (sw_rx_cons != hw_rx_cons) { 6304 struct mbuf *m0; 6305 6306 /* Convert the producer/consumer indices to an actual rx_bd index. */ 6307 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons); 6308 6309 /* Unmap the mbuf from DMA space. */ 6310 bus_dmamap_sync(sc->rx_mbuf_tag, 6311 sc->rx_mbuf_map[sw_rx_cons_idx], 6312 BUS_DMASYNC_POSTREAD); 6313 bus_dmamap_unload(sc->rx_mbuf_tag, 6314 sc->rx_mbuf_map[sw_rx_cons_idx]); 6315 6316 /* Remove the mbuf from the RX chain. */ 6317 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx]; 6318 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL; 6319 DBRUN(sc->debug_rx_mbuf_alloc--); 6320 sc->free_rx_bd++; 6321 6322 if(m0 == NULL) { 6323 DBPRINT(sc, BCE_EXTREME_RECV, 6324 "%s(): Oops! Empty mbuf pointer " 6325 "found in sc->rx_mbuf_ptr[0x%04X]!\n", 6326 __FUNCTION__, sw_rx_cons_idx); 6327 goto bce_rx_int_next_rx; 6328 } 6329 6330 /* 6331 * Frames received on the NetXteme II are prepended 6332 * with an l2_fhdr structure which provides status 6333 * information about the received frame (including 6334 * VLAN tags and checksum info). The frames are 6335 * also automatically adjusted to word align the IP 6336 * header (i.e. two null bytes are inserted before 6337 * the Ethernet header). As a result the data 6338 * DMA'd by the controller into the mbuf looks 6339 * like this: 6340 * 6341 * +---------+-----+---------------------+-----+ 6342 * | l2_fhdr | pad | packet data | FCS | 6343 * +---------+-----+---------------------+-----+ 6344 * 6345 * The l2_fhdr needs to be checked and skipped and 6346 * the FCS needs to be stripped before sending the 6347 * packet up the stack. 6348 */ 6349 l2fhdr = mtod(m0, struct l2_fhdr *); 6350 6351 /* Get the packet data + FCS length and the status. */ 6352 pkt_len = l2fhdr->l2_fhdr_pkt_len; 6353 status = l2fhdr->l2_fhdr_status; 6354 6355 /* 6356 * Skip over the l2_fhdr and pad, resulting in the 6357 * following data in the mbuf: 6358 * +---------------------+-----+ 6359 * | packet data | FCS | 6360 * +---------------------+-----+ 6361 */ 6362 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN); 6363 6364 /* 6365 * When split header mode is used, an ethernet frame 6366 * may be split across the receive chain and the 6367 * page chain. If that occurs an mbuf cluster must be 6368 * reassembled from the individual mbuf pieces. 6369 */ 6370 if (bce_hdr_split == TRUE) { 6371 /* 6372 * Check whether the received frame fits in a single 6373 * mbuf or not (i.e. packet data + FCS <= 6374 * sc->rx_bd_mbuf_data_len bytes). 6375 */ 6376 if (pkt_len > m0->m_len) { 6377 /* 6378 * The received frame is larger than a single mbuf. 6379 * If the frame was a TCP frame then only the TCP 6380 * header is placed in the mbuf, the remaining 6381 * payload (including FCS) is placed in the page 6382 * chain, the SPLIT flag is set, and the header 6383 * length is placed in the IP checksum field. 6384 * If the frame is not a TCP frame then the mbuf 6385 * is filled and the remaining bytes are placed 6386 * in the page chain. 6387 */ 6388 6389 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large " 6390 "packet.\n", __FUNCTION__); 6391 DBRUN(sc->split_header_frames_rcvd++); 6392 6393 /* 6394 * When the page chain is enabled and the TCP 6395 * header has been split from the TCP payload, 6396 * the ip_xsum structure will reflect the length 6397 * of the TCP header, not the IP checksum. Set 6398 * the packet length of the mbuf accordingly. 6399 */ 6400 if (status & L2_FHDR_STATUS_SPLIT) { 6401 m0->m_len = l2fhdr->l2_fhdr_ip_xsum; 6402 DBRUN(sc->split_header_tcp_frames_rcvd++); 6403 } 6404 6405 rem_len = pkt_len - m0->m_len; 6406 6407 /* Pull mbufs off the page chain for any remaining data. */ 6408 while (rem_len > 0) { 6409 struct mbuf *m_pg; 6410 6411 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons); 6412 6413 /* Remove the mbuf from the page chain. */ 6414 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx]; 6415 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL; 6416 DBRUN(sc->debug_pg_mbuf_alloc--); 6417 sc->free_pg_bd++; 6418 6419 /* Unmap the page chain mbuf from DMA space. */ 6420 bus_dmamap_sync(sc->pg_mbuf_tag, 6421 sc->pg_mbuf_map[sw_pg_cons_idx], 6422 BUS_DMASYNC_POSTREAD); 6423 bus_dmamap_unload(sc->pg_mbuf_tag, 6424 sc->pg_mbuf_map[sw_pg_cons_idx]); 6425 6426 /* Adjust the mbuf length. */ 6427 if (rem_len < m_pg->m_len) { 6428 /* The mbuf chain is complete. */ 6429 m_pg->m_len = rem_len; 6430 rem_len = 0; 6431 } else { 6432 /* More packet data is waiting. */ 6433 rem_len -= m_pg->m_len; 6434 } 6435 6436 /* Concatenate the mbuf cluster to the mbuf. */ 6437 m_cat(m0, m_pg); 6438 6439 sw_pg_cons = NEXT_PG_BD(sw_pg_cons); 6440 } 6441 6442 /* Set the total packet length. */ 6443 m0->m_pkthdr.len = pkt_len; 6444 6445 } else { 6446 /* 6447 * The received packet is small and fits in a 6448 * single mbuf (i.e. the l2_fhdr + pad + packet + 6449 * FCS <= MHLEN). In other words, the packet is 6450 * 154 bytes or less in size. 6451 */ 6452 6453 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small " 6454 "packet.\n", __FUNCTION__); 6455 6456 /* Set the total packet length. */ 6457 m0->m_pkthdr.len = m0->m_len = pkt_len; 6458 } 6459 } else 6460 /* Set the total packet length. */ 6461 m0->m_pkthdr.len = m0->m_len = pkt_len; 6462 6463 /* Remove the trailing Ethernet FCS. */ 6464 m_adj(m0, -ETHER_CRC_LEN); 6465 6466 /* Check that the resulting mbuf chain is valid. */ 6467 DBRUN(m_sanity(m0, FALSE)); 6468 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) | 6469 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 6470 BCE_PRINTF("Invalid Ethernet frame size!\n"); 6471 m_print(m0, 128)); 6472 6473 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control), 6474 sc->l2fhdr_error_sim_count++; 6475 status = status | L2_FHDR_ERRORS_PHY_DECODE); 6476 6477 /* Check the received frame for errors. */ 6478 if (status & (L2_FHDR_ERRORS_BAD_CRC | 6479 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 6480 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 6481 6482 /* Log the error and release the mbuf. */ 6483 ifp->if_ierrors++; 6484 sc->l2fhdr_error_count++; 6485 6486 m_freem(m0); 6487 m0 = NULL; 6488 goto bce_rx_int_next_rx; 6489 } 6490 6491 /* Send the packet to the appropriate interface. */ 6492 m0->m_pkthdr.rcvif = ifp; 6493 6494 /* Assume no hardware checksum. */ 6495 m0->m_pkthdr.csum_flags = 0; 6496 6497 /* Validate the checksum if offload enabled. */ 6498 if (ifp->if_capenable & IFCAP_RXCSUM) { 6499 6500 /* Check for an IP datagram. */ 6501 if (!(status & L2_FHDR_STATUS_SPLIT) && 6502 (status & L2_FHDR_STATUS_IP_DATAGRAM)) { 6503 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 6504 DBRUN(sc->csum_offload_ip++); 6505 /* Check if the IP checksum is valid. */ 6506 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 6507 m0->m_pkthdr.csum_flags |= 6508 CSUM_IP_VALID; 6509 } 6510 6511 /* Check for a valid TCP/UDP frame. */ 6512 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 6513 L2_FHDR_STATUS_UDP_DATAGRAM)) { 6514 6515 /* Check for a good TCP/UDP checksum. */ 6516 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 6517 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 6518 DBRUN(sc->csum_offload_tcp_udp++); 6519 m0->m_pkthdr.csum_data = 6520 l2fhdr->l2_fhdr_tcp_udp_xsum; 6521 m0->m_pkthdr.csum_flags |= 6522 (CSUM_DATA_VALID 6523 | CSUM_PSEUDO_HDR); 6524 } 6525 } 6526 } 6527 6528 /* Attach the VLAN tag. */ 6529 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 6530 DBRUN(sc->vlan_tagged_frames_rcvd++); 6531 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) { 6532 DBRUN(sc->vlan_tagged_frames_stripped++); 6533 #if __FreeBSD_version < 700000 6534 VLAN_INPUT_TAG(ifp, m0, 6535 l2fhdr->l2_fhdr_vlan_tag, continue); 6536 #else 6537 m0->m_pkthdr.ether_vtag = 6538 l2fhdr->l2_fhdr_vlan_tag; 6539 m0->m_flags |= M_VLANTAG; 6540 #endif 6541 } else { 6542 /* 6543 * bce(4) controllers can't disable VLAN 6544 * tag stripping if management firmware 6545 * (ASF/IPMI/UMP) is running. So we always 6546 * strip VLAN tag and manually reconstruct 6547 * the VLAN frame by appending stripped 6548 * VLAN tag in driver if VLAN tag stripping 6549 * was disabled. 6550 * 6551 * TODO: LLC SNAP handling. 6552 */ 6553 bcopy(mtod(m0, uint8_t *), 6554 mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN, 6555 ETHER_ADDR_LEN * 2); 6556 m0->m_data -= ETHER_VLAN_ENCAP_LEN; 6557 vh = mtod(m0, struct ether_vlan_header *); 6558 vh->evl_encap_proto = htons(ETHERTYPE_VLAN); 6559 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag); 6560 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN; 6561 m0->m_len += ETHER_VLAN_ENCAP_LEN; 6562 } 6563 } 6564 6565 /* Increment received packet statistics. */ 6566 ifp->if_ipackets++; 6567 6568 bce_rx_int_next_rx: 6569 sw_rx_cons = NEXT_RX_BD(sw_rx_cons); 6570 6571 /* If we have a packet, pass it up the stack */ 6572 if (m0) { 6573 /* Make sure we don't lose our place when we release the lock. */ 6574 sc->rx_cons = sw_rx_cons; 6575 sc->pg_cons = sw_pg_cons; 6576 6577 BCE_UNLOCK(sc); 6578 (*ifp->if_input)(ifp, m0); 6579 BCE_LOCK(sc); 6580 6581 /* Recover our place. */ 6582 sw_rx_cons = sc->rx_cons; 6583 sw_pg_cons = sc->pg_cons; 6584 } 6585 6586 /* Refresh hw_cons to see if there's new work */ 6587 if (sw_rx_cons == hw_rx_cons) 6588 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc); 6589 } 6590 6591 /* No new packets. Refill the page chain. */ 6592 if (bce_hdr_split == TRUE) { 6593 sc->pg_cons = sw_pg_cons; 6594 bce_fill_pg_chain(sc); 6595 } 6596 6597 /* No new packets. Refill the RX chain. */ 6598 sc->rx_cons = sw_rx_cons; 6599 bce_fill_rx_chain(sc); 6600 6601 /* Prepare the page chain pages to be accessed by the NIC. */ 6602 for (int i = 0; i < sc->rx_pages; i++) 6603 bus_dmamap_sync(sc->rx_bd_chain_tag, 6604 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6605 6606 if (bce_hdr_split == TRUE) { 6607 for (int i = 0; i < sc->pg_pages; i++) 6608 bus_dmamap_sync(sc->pg_bd_chain_tag, 6609 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 6610 } 6611 6612 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, " 6613 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 6614 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 6615 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 6616 } 6617 6618 6619 /****************************************************************************/ 6620 /* Reads the transmit consumer value from the status block (skipping over */ 6621 /* chain page pointer if necessary). */ 6622 /* */ 6623 /* Returns: */ 6624 /* hw_cons */ 6625 /****************************************************************************/ 6626 static inline u16 6627 bce_get_hw_tx_cons(struct bce_softc *sc) 6628 { 6629 u16 hw_cons; 6630 6631 mb(); 6632 hw_cons = sc->status_block->status_tx_quick_consumer_index0; 6633 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6634 hw_cons++; 6635 6636 return hw_cons; 6637 } 6638 6639 6640 /****************************************************************************/ 6641 /* Handles transmit completion interrupt events. */ 6642 /* */ 6643 /* Returns: */ 6644 /* Nothing. */ 6645 /****************************************************************************/ 6646 static void 6647 bce_tx_intr(struct bce_softc *sc) 6648 { 6649 struct ifnet *ifp = sc->bce_ifp; 6650 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 6651 6652 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6653 DBRUN(sc->interrupts_tx++); 6654 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, " 6655 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6656 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6657 6658 BCE_LOCK_ASSERT(sc); 6659 6660 /* Get the hardware's view of the TX consumer index. */ 6661 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6662 sw_tx_cons = sc->tx_cons; 6663 6664 /* Prevent speculative reads of the status block. */ 6665 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6666 BUS_SPACE_BARRIER_READ); 6667 6668 /* Cycle through any completed TX chain page entries. */ 6669 while (sw_tx_cons != hw_tx_cons) { 6670 #ifdef BCE_DEBUG 6671 struct tx_bd *txbd = NULL; 6672 #endif 6673 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 6674 6675 DBPRINT(sc, BCE_INFO_SEND, 6676 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 6677 "sw_tx_chain_cons = 0x%04X\n", 6678 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 6679 6680 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC), 6681 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 6682 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 6683 (int) MAX_TX_BD_ALLOC); 6684 bce_breakpoint(sc)); 6685 6686 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 6687 [TX_IDX(sw_tx_chain_cons)]); 6688 6689 DBRUNIF((txbd == NULL), 6690 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 6691 __FILE__, __LINE__, sw_tx_chain_cons); 6692 bce_breakpoint(sc)); 6693 6694 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 6695 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 6696 6697 /* 6698 * Free the associated mbuf. Remember 6699 * that only the last tx_bd of a packet 6700 * has an mbuf pointer and DMA map. 6701 */ 6702 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 6703 6704 /* Validate that this is the last tx_bd. */ 6705 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 6706 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 6707 "txmbuf == NULL!\n", __FILE__, __LINE__); 6708 bce_breakpoint(sc)); 6709 6710 DBRUNMSG(BCE_INFO_SEND, 6711 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 6712 "from tx_bd[0x%04X]\n", __FUNCTION__, 6713 sw_tx_chain_cons)); 6714 6715 /* Unmap the mbuf. */ 6716 bus_dmamap_unload(sc->tx_mbuf_tag, 6717 sc->tx_mbuf_map[sw_tx_chain_cons]); 6718 6719 /* Free the mbuf. */ 6720 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 6721 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 6722 DBRUN(sc->debug_tx_mbuf_alloc--); 6723 6724 ifp->if_opackets++; 6725 } 6726 6727 sc->used_tx_bd--; 6728 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 6729 6730 /* Refresh hw_cons to see if there's new work. */ 6731 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc); 6732 6733 /* Prevent speculative reads of the status block. */ 6734 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 6735 BUS_SPACE_BARRIER_READ); 6736 } 6737 6738 /* Clear the TX timeout timer. */ 6739 sc->watchdog_timer = 0; 6740 6741 /* Clear the tx hardware queue full flag. */ 6742 if (sc->used_tx_bd < sc->max_tx_bd) { 6743 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 6744 DBPRINT(sc, BCE_INFO_SEND, 6745 "%s(): Open TX chain! %d/%d (used/total)\n", 6746 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 6747 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6748 } 6749 6750 sc->tx_cons = sw_tx_cons; 6751 6752 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, " 6753 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n", 6754 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq); 6755 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR); 6756 } 6757 6758 6759 /****************************************************************************/ 6760 /* Disables interrupt generation. */ 6761 /* */ 6762 /* Returns: */ 6763 /* Nothing. */ 6764 /****************************************************************************/ 6765 static void 6766 bce_disable_intr(struct bce_softc *sc) 6767 { 6768 DBENTER(BCE_VERBOSE_INTR); 6769 6770 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 6771 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 6772 6773 DBEXIT(BCE_VERBOSE_INTR); 6774 } 6775 6776 6777 /****************************************************************************/ 6778 /* Enables interrupt generation. */ 6779 /* */ 6780 /* Returns: */ 6781 /* Nothing. */ 6782 /****************************************************************************/ 6783 static void 6784 bce_enable_intr(struct bce_softc *sc, int coal_now) 6785 { 6786 DBENTER(BCE_VERBOSE_INTR); 6787 6788 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6789 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 6790 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 6791 6792 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 6793 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 6794 6795 /* Force an immediate interrupt (whether there is new data or not). */ 6796 if (coal_now) 6797 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW); 6798 6799 DBEXIT(BCE_VERBOSE_INTR); 6800 } 6801 6802 6803 /****************************************************************************/ 6804 /* Handles controller initialization. */ 6805 /* */ 6806 /* Returns: */ 6807 /* Nothing. */ 6808 /****************************************************************************/ 6809 static void 6810 bce_init_locked(struct bce_softc *sc) 6811 { 6812 struct ifnet *ifp; 6813 u32 ether_mtu = 0; 6814 6815 DBENTER(BCE_VERBOSE_RESET); 6816 6817 BCE_LOCK_ASSERT(sc); 6818 6819 ifp = sc->bce_ifp; 6820 6821 /* Check if the driver is still running and bail out if it is. */ 6822 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6823 goto bce_init_locked_exit; 6824 6825 bce_stop(sc); 6826 6827 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 6828 BCE_PRINTF("%s(%d): Controller reset failed!\n", 6829 __FILE__, __LINE__); 6830 goto bce_init_locked_exit; 6831 } 6832 6833 if (bce_chipinit(sc)) { 6834 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 6835 __FILE__, __LINE__); 6836 goto bce_init_locked_exit; 6837 } 6838 6839 if (bce_blockinit(sc)) { 6840 BCE_PRINTF("%s(%d): Block initialization failed!\n", 6841 __FILE__, __LINE__); 6842 goto bce_init_locked_exit; 6843 } 6844 6845 /* Load our MAC address. */ 6846 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 6847 bce_set_mac_addr(sc); 6848 6849 /* 6850 * Calculate and program the hardware Ethernet MTU 6851 * size. Be generous on the receive if we have room 6852 * and allowed by the user. 6853 */ 6854 if (bce_strict_rx_mtu == TRUE) 6855 ether_mtu = ifp->if_mtu; 6856 else { 6857 if (bce_hdr_split == TRUE) { 6858 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len + 6859 sc->pg_bd_mbuf_alloc_size)) 6860 ether_mtu = sc->rx_bd_mbuf_data_len + 6861 sc->pg_bd_mbuf_alloc_size; 6862 else 6863 ether_mtu = ifp->if_mtu; 6864 } else { 6865 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len) 6866 ether_mtu = sc->rx_bd_mbuf_data_len; 6867 else 6868 ether_mtu = ifp->if_mtu; 6869 } 6870 } 6871 6872 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 6873 6874 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", 6875 __FUNCTION__, ether_mtu); 6876 6877 /* Program the mtu, enabling jumbo frame support if necessary. */ 6878 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)) 6879 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, 6880 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 6881 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 6882 else 6883 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 6884 6885 /* Program appropriate promiscuous/multicast filtering. */ 6886 bce_set_rx_mode(sc); 6887 6888 if (bce_hdr_split == TRUE) { 6889 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n", 6890 __FUNCTION__, sc->pg_bd_mbuf_alloc_size); 6891 6892 /* Init page buffer descriptor chain. */ 6893 bce_init_pg_chain(sc); 6894 } 6895 6896 /* Init RX buffer descriptor chain. */ 6897 bce_init_rx_chain(sc); 6898 6899 /* Init TX buffer descriptor chain. */ 6900 bce_init_tx_chain(sc); 6901 6902 /* Enable host interrupts. */ 6903 bce_enable_intr(sc, 1); 6904 6905 bce_ifmedia_upd_locked(ifp); 6906 6907 /* Let the OS know the driver is up and running. */ 6908 ifp->if_drv_flags |= IFF_DRV_RUNNING; 6909 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 6910 6911 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 6912 6913 bce_init_locked_exit: 6914 DBEXIT(BCE_VERBOSE_RESET); 6915 } 6916 6917 6918 /****************************************************************************/ 6919 /* Initialize the controller just enough so that any management firmware */ 6920 /* running on the device will continue to operate correctly. */ 6921 /* */ 6922 /* Returns: */ 6923 /* Nothing. */ 6924 /****************************************************************************/ 6925 static void 6926 bce_mgmt_init_locked(struct bce_softc *sc) 6927 { 6928 struct ifnet *ifp; 6929 6930 DBENTER(BCE_VERBOSE_RESET); 6931 6932 BCE_LOCK_ASSERT(sc); 6933 6934 /* Bail out if management firmware is not running. */ 6935 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 6936 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 6937 "No management firmware running...\n"); 6938 goto bce_mgmt_init_locked_exit; 6939 } 6940 6941 ifp = sc->bce_ifp; 6942 6943 /* Enable all critical blocks in the MAC. */ 6944 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT); 6945 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 6946 DELAY(20); 6947 6948 bce_ifmedia_upd_locked(ifp); 6949 6950 bce_mgmt_init_locked_exit: 6951 DBEXIT(BCE_VERBOSE_RESET); 6952 } 6953 6954 6955 /****************************************************************************/ 6956 /* Handles controller initialization when called from an unlocked routine. */ 6957 /* */ 6958 /* Returns: */ 6959 /* Nothing. */ 6960 /****************************************************************************/ 6961 static void 6962 bce_init(void *xsc) 6963 { 6964 struct bce_softc *sc = xsc; 6965 6966 DBENTER(BCE_VERBOSE_RESET); 6967 6968 BCE_LOCK(sc); 6969 bce_init_locked(sc); 6970 BCE_UNLOCK(sc); 6971 6972 DBEXIT(BCE_VERBOSE_RESET); 6973 } 6974 6975 6976 /****************************************************************************/ 6977 /* Modifies an mbuf for TSO on the hardware. */ 6978 /* */ 6979 /* Returns: */ 6980 /* Pointer to a modified mbuf. */ 6981 /****************************************************************************/ 6982 static struct mbuf * 6983 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags) 6984 { 6985 struct mbuf *m; 6986 struct ether_header *eh; 6987 struct ip *ip; 6988 struct tcphdr *th; 6989 u16 etype; 6990 int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 6991 6992 DBRUN(sc->tso_frames_requested++); 6993 6994 /* Controller may modify mbuf chains. */ 6995 if (M_WRITABLE(*m_head) == 0) { 6996 m = m_dup(*m_head, M_DONTWAIT); 6997 m_freem(*m_head); 6998 if (m == NULL) { 6999 sc->mbuf_alloc_failed_count++; 7000 *m_head = NULL; 7001 return (NULL); 7002 } 7003 *m_head = m; 7004 } 7005 7006 /* 7007 * For TSO the controller needs two pieces of info, 7008 * the MSS and the IP+TCP options length. 7009 */ 7010 m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip)); 7011 if (m == NULL) { 7012 *m_head = NULL; 7013 return (NULL); 7014 } 7015 eh = mtod(m, struct ether_header *); 7016 etype = ntohs(eh->ether_type); 7017 7018 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 7019 switch (etype) { 7020 case ETHERTYPE_IP: 7021 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7022 /* TSO only supported for TCP protocol. */ 7023 if (ip->ip_p != IPPROTO_TCP) { 7024 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 7025 __FILE__, __LINE__); 7026 m_freem(*m_head); 7027 *m_head = NULL; 7028 return (NULL); 7029 } 7030 7031 /* Get IP header length in bytes (min 20) */ 7032 ip_hlen = ip->ip_hl << 2; 7033 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen + 7034 sizeof(struct tcphdr)); 7035 if (m == NULL) { 7036 *m_head = NULL; 7037 return (NULL); 7038 } 7039 7040 /* Get the TCP header length in bytes (min 20) */ 7041 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7042 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 7043 tcp_hlen = (th->th_off << 2); 7044 7045 /* Make sure all IP/TCP options live in the same buffer. */ 7046 m = m_pullup(*m_head, sizeof(struct ether_header)+ ip_hlen + 7047 tcp_hlen); 7048 if (m == NULL) { 7049 *m_head = NULL; 7050 return (NULL); 7051 } 7052 7053 /* Clear IP header length and checksum, will be calc'd by h/w. */ 7054 ip = (struct ip *)(m->m_data + sizeof(struct ether_header)); 7055 ip_len = ip->ip_len; 7056 ip->ip_len = 0; 7057 ip->ip_sum = 0; 7058 break; 7059 case ETHERTYPE_IPV6: 7060 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 7061 __FILE__, __LINE__); 7062 m_freem(*m_head); 7063 *m_head = NULL; 7064 return (NULL); 7065 /* NOT REACHED */ 7066 default: 7067 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 7068 __FILE__, __LINE__); 7069 m_freem(*m_head); 7070 *m_head = NULL; 7071 return (NULL); 7072 } 7073 7074 hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen; 7075 7076 DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, " 7077 "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 7078 __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen, 7079 tcp_hlen, ip_len); 7080 7081 /* Set the LSO flag in the TX BD */ 7082 *flags |= TX_BD_FLAGS_SW_LSO; 7083 7084 /* Set the length of IP + TCP options (in 32 bit words) */ 7085 *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) - 7086 sizeof(struct tcphdr)) >> 2) << 8); 7087 7088 DBRUN(sc->tso_frames_completed++); 7089 return (*m_head); 7090 } 7091 7092 7093 /****************************************************************************/ 7094 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 7095 /* memory visible to the controller. */ 7096 /* */ 7097 /* Returns: */ 7098 /* 0 for success, positive value for failure. */ 7099 /* Modified: */ 7100 /* m_head: May be set to NULL if MBUF is excessively fragmented. */ 7101 /****************************************************************************/ 7102 static int 7103 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 7104 { 7105 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 7106 bus_dmamap_t map; 7107 struct tx_bd *txbd = NULL; 7108 struct mbuf *m0; 7109 u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0; 7110 u32 prod_bseq; 7111 7112 #ifdef BCE_DEBUG 7113 u16 debug_prod; 7114 #endif 7115 7116 int i, error, nsegs, rc = 0; 7117 7118 DBENTER(BCE_VERBOSE_SEND); 7119 7120 /* Make sure we have room in the TX chain. */ 7121 if (sc->used_tx_bd >= sc->max_tx_bd) 7122 goto bce_tx_encap_exit; 7123 7124 /* Transfer any checksum offload flags to the bd. */ 7125 m0 = *m_head; 7126 if (m0->m_pkthdr.csum_flags) { 7127 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 7128 m0 = bce_tso_setup(sc, m_head, &flags); 7129 if (m0 == NULL) { 7130 DBRUN(sc->tso_frames_failed++); 7131 goto bce_tx_encap_exit; 7132 } 7133 mss = htole16(m0->m_pkthdr.tso_segsz); 7134 } else { 7135 if (m0->m_pkthdr.csum_flags & CSUM_IP) 7136 flags |= TX_BD_FLAGS_IP_CKSUM; 7137 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 7138 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 7139 } 7140 } 7141 7142 /* Transfer any VLAN tags to the bd. */ 7143 if (m0->m_flags & M_VLANTAG) { 7144 flags |= TX_BD_FLAGS_VLAN_TAG; 7145 vlan_tag = m0->m_pkthdr.ether_vtag; 7146 } 7147 7148 /* Map the mbuf into DMAable memory. */ 7149 prod = sc->tx_prod; 7150 chain_prod = TX_CHAIN_IDX(prod); 7151 map = sc->tx_mbuf_map[chain_prod]; 7152 7153 /* Map the mbuf into our DMA address space. */ 7154 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 7155 segs, &nsegs, BUS_DMA_NOWAIT); 7156 7157 /* Check if the DMA mapping was successful */ 7158 if (error == EFBIG) { 7159 sc->mbuf_frag_count++; 7160 7161 /* Try to defrag the mbuf. */ 7162 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS); 7163 if (m0 == NULL) { 7164 /* Defrag was unsuccessful */ 7165 m_freem(*m_head); 7166 *m_head = NULL; 7167 sc->mbuf_alloc_failed_count++; 7168 rc = ENOBUFS; 7169 goto bce_tx_encap_exit; 7170 } 7171 7172 /* Defrag was successful, try mapping again */ 7173 *m_head = m0; 7174 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, 7175 map, m0, segs, &nsegs, BUS_DMA_NOWAIT); 7176 7177 /* Still getting an error after a defrag. */ 7178 if (error == ENOMEM) { 7179 /* Insufficient DMA buffers available. */ 7180 sc->dma_map_addr_tx_failed_count++; 7181 rc = error; 7182 goto bce_tx_encap_exit; 7183 } else if (error != 0) { 7184 /* Release it and return an error. */ 7185 BCE_PRINTF("%s(%d): Unknown error mapping mbuf into " 7186 "TX chain!\n", __FILE__, __LINE__); 7187 m_freem(m0); 7188 *m_head = NULL; 7189 sc->dma_map_addr_tx_failed_count++; 7190 rc = ENOBUFS; 7191 goto bce_tx_encap_exit; 7192 } 7193 } else if (error == ENOMEM) { 7194 /* Insufficient DMA buffers available. */ 7195 sc->dma_map_addr_tx_failed_count++; 7196 rc = error; 7197 goto bce_tx_encap_exit; 7198 } else if (error != 0) { 7199 m_freem(m0); 7200 *m_head = NULL; 7201 sc->dma_map_addr_tx_failed_count++; 7202 rc = error; 7203 goto bce_tx_encap_exit; 7204 } 7205 7206 /* Make sure there's room in the chain */ 7207 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 7208 bus_dmamap_unload(sc->tx_mbuf_tag, map); 7209 rc = ENOBUFS; 7210 goto bce_tx_encap_exit; 7211 } 7212 7213 /* prod points to an empty tx_bd at this point. */ 7214 prod_bseq = sc->tx_prod_bseq; 7215 7216 #ifdef BCE_DEBUG 7217 debug_prod = chain_prod; 7218 #endif 7219 7220 DBPRINT(sc, BCE_INFO_SEND, 7221 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, " 7222 "prod_bseq = 0x%08X\n", 7223 __FUNCTION__, prod, chain_prod, prod_bseq); 7224 7225 /* 7226 * Cycle through each mbuf segment that makes up 7227 * the outgoing frame, gathering the mapping info 7228 * for that segment and creating a tx_bd for 7229 * the mbuf. 7230 */ 7231 for (i = 0; i < nsegs ; i++) { 7232 7233 chain_prod = TX_CHAIN_IDX(prod); 7234 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)] 7235 [TX_IDX(chain_prod)]; 7236 7237 txbd->tx_bd_haddr_lo = 7238 htole32(BCE_ADDR_LO(segs[i].ds_addr)); 7239 txbd->tx_bd_haddr_hi = 7240 htole32(BCE_ADDR_HI(segs[i].ds_addr)); 7241 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | 7242 htole16(segs[i].ds_len); 7243 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 7244 txbd->tx_bd_flags = htole16(flags); 7245 prod_bseq += segs[i].ds_len; 7246 if (i == 0) 7247 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 7248 prod = NEXT_TX_BD(prod); 7249 } 7250 7251 /* Set the END flag on the last TX buffer descriptor. */ 7252 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 7253 7254 DBRUNMSG(BCE_EXTREME_SEND, 7255 bce_dump_tx_chain(sc, debug_prod, nsegs)); 7256 7257 /* 7258 * Ensure that the mbuf pointer for this transmission 7259 * is placed at the array index of the last 7260 * descriptor in this chain. This is done 7261 * because a single map is used for all 7262 * segments of the mbuf and we don't want to 7263 * unload the map before all of the segments 7264 * have been freed. 7265 */ 7266 sc->tx_mbuf_ptr[chain_prod] = m0; 7267 sc->used_tx_bd += nsegs; 7268 7269 /* Update some debug statistic counters */ 7270 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 7271 sc->tx_hi_watermark = sc->used_tx_bd); 7272 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 7273 DBRUNIF(sc->debug_tx_mbuf_alloc++); 7274 7275 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1)); 7276 7277 /* prod points to the next free tx_bd at this point. */ 7278 sc->tx_prod = prod; 7279 sc->tx_prod_bseq = prod_bseq; 7280 7281 /* Tell the chip about the waiting TX frames. */ 7282 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + 7283 BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod); 7284 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + 7285 BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq); 7286 7287 bce_tx_encap_exit: 7288 DBEXIT(BCE_VERBOSE_SEND); 7289 return(rc); 7290 } 7291 7292 7293 /****************************************************************************/ 7294 /* Main transmit routine when called from another routine with a lock. */ 7295 /* */ 7296 /* Returns: */ 7297 /* Nothing. */ 7298 /****************************************************************************/ 7299 static void 7300 bce_start_locked(struct ifnet *ifp) 7301 { 7302 struct bce_softc *sc = ifp->if_softc; 7303 struct mbuf *m_head = NULL; 7304 int count = 0; 7305 u16 tx_prod, tx_chain_prod; 7306 7307 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7308 7309 BCE_LOCK_ASSERT(sc); 7310 7311 /* prod points to the next free tx_bd. */ 7312 tx_prod = sc->tx_prod; 7313 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 7314 7315 DBPRINT(sc, BCE_INFO_SEND, 7316 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 7317 "tx_prod_bseq = 0x%08X\n", 7318 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 7319 7320 /* If there's no link or the transmit queue is empty then just exit. */ 7321 if (sc->bce_link_up == FALSE) { 7322 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n", 7323 __FUNCTION__); 7324 goto bce_start_locked_exit; 7325 } 7326 7327 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 7328 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n", 7329 __FUNCTION__); 7330 goto bce_start_locked_exit; 7331 } 7332 7333 /* 7334 * Keep adding entries while there is space in the ring. 7335 */ 7336 while (sc->used_tx_bd < sc->max_tx_bd) { 7337 7338 /* Check for any frames to send. */ 7339 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 7340 7341 /* Stop when the transmit queue is empty. */ 7342 if (m_head == NULL) 7343 break; 7344 7345 /* 7346 * Pack the data into the transmit ring. If we 7347 * don't have room, place the mbuf back at the 7348 * head of the queue and set the OACTIVE flag 7349 * to wait for the NIC to drain the chain. 7350 */ 7351 if (bce_tx_encap(sc, &m_head)) { 7352 if (m_head != NULL) 7353 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 7354 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 7355 DBPRINT(sc, BCE_INFO_SEND, 7356 "TX chain is closed for business! Total " 7357 "tx_bd used = %d\n", sc->used_tx_bd); 7358 break; 7359 } 7360 7361 count++; 7362 7363 /* Send a copy of the frame to any BPF listeners. */ 7364 ETHER_BPF_MTAP(ifp, m_head); 7365 } 7366 7367 /* Exit if no packets were dequeued. */ 7368 if (count == 0) { 7369 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were " 7370 "dequeued\n", __FUNCTION__); 7371 goto bce_start_locked_exit; 7372 } 7373 7374 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into " 7375 "send queue.\n", __FUNCTION__, count); 7376 7377 /* Set the tx timeout. */ 7378 sc->watchdog_timer = BCE_TX_TIMEOUT; 7379 7380 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID)); 7381 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc)); 7382 7383 bce_start_locked_exit: 7384 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX); 7385 return; 7386 } 7387 7388 7389 /****************************************************************************/ 7390 /* Main transmit routine when called from another routine without a lock. */ 7391 /* */ 7392 /* Returns: */ 7393 /* Nothing. */ 7394 /****************************************************************************/ 7395 static void 7396 bce_start(struct ifnet *ifp) 7397 { 7398 struct bce_softc *sc = ifp->if_softc; 7399 7400 DBENTER(BCE_VERBOSE_SEND); 7401 7402 BCE_LOCK(sc); 7403 bce_start_locked(ifp); 7404 BCE_UNLOCK(sc); 7405 7406 DBEXIT(BCE_VERBOSE_SEND); 7407 } 7408 7409 7410 /****************************************************************************/ 7411 /* Handles any IOCTL calls from the operating system. */ 7412 /* */ 7413 /* Returns: */ 7414 /* 0 for success, positive value for failure. */ 7415 /****************************************************************************/ 7416 static int 7417 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 7418 { 7419 struct bce_softc *sc = ifp->if_softc; 7420 struct ifreq *ifr = (struct ifreq *) data; 7421 struct mii_data *mii; 7422 int mask, error = 0; 7423 7424 DBENTER(BCE_VERBOSE_MISC); 7425 7426 switch(command) { 7427 7428 /* Set the interface MTU. */ 7429 case SIOCSIFMTU: 7430 /* Check that the MTU setting is supported. */ 7431 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 7432 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 7433 error = EINVAL; 7434 break; 7435 } 7436 7437 DBPRINT(sc, BCE_INFO_MISC, 7438 "SIOCSIFMTU: Changing MTU from %d to %d\n", 7439 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 7440 7441 BCE_LOCK(sc); 7442 ifp->if_mtu = ifr->ifr_mtu; 7443 7444 if (bce_hdr_split == FALSE) { 7445 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7446 /* 7447 * Because allocation size is used in RX 7448 * buffer allocation, stop controller if 7449 * it is already running. 7450 */ 7451 bce_stop(sc); 7452 } 7453 7454 bce_get_rx_buffer_sizes(sc, ifp->if_mtu); 7455 7456 bce_init_locked(sc); 7457 } 7458 7459 BCE_UNLOCK(sc); 7460 break; 7461 7462 /* Set interface flags. */ 7463 case SIOCSIFFLAGS: 7464 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 7465 7466 BCE_LOCK(sc); 7467 7468 /* Check if the interface is up. */ 7469 if (ifp->if_flags & IFF_UP) { 7470 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7471 /* Change promiscuous/multicast flags as necessary. */ 7472 bce_set_rx_mode(sc); 7473 } else { 7474 /* Start the HW */ 7475 bce_init_locked(sc); 7476 } 7477 } else { 7478 /* The interface is down, check if driver is running. */ 7479 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 7480 bce_stop(sc); 7481 7482 /* If MFW is running, restart the controller a bit. */ 7483 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 7484 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 7485 bce_chipinit(sc); 7486 bce_mgmt_init_locked(sc); 7487 } 7488 } 7489 } 7490 7491 BCE_UNLOCK(sc); 7492 break; 7493 7494 /* Add/Delete multicast address */ 7495 case SIOCADDMULTI: 7496 case SIOCDELMULTI: 7497 DBPRINT(sc, BCE_VERBOSE_MISC, 7498 "Received SIOCADDMULTI/SIOCDELMULTI\n"); 7499 7500 BCE_LOCK(sc); 7501 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 7502 bce_set_rx_mode(sc); 7503 BCE_UNLOCK(sc); 7504 7505 break; 7506 7507 /* Set/Get Interface media */ 7508 case SIOCSIFMEDIA: 7509 case SIOCGIFMEDIA: 7510 DBPRINT(sc, BCE_VERBOSE_MISC, 7511 "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 7512 7513 mii = device_get_softc(sc->bce_miibus); 7514 error = ifmedia_ioctl(ifp, ifr, 7515 &mii->mii_media, command); 7516 break; 7517 7518 /* Set interface capability */ 7519 case SIOCSIFCAP: 7520 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 7521 DBPRINT(sc, BCE_INFO_MISC, 7522 "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 7523 7524 /* Toggle the TX checksum capabilities enable flag. */ 7525 if (mask & IFCAP_TXCSUM && 7526 ifp->if_capabilities & IFCAP_TXCSUM) { 7527 ifp->if_capenable ^= IFCAP_TXCSUM; 7528 if (IFCAP_TXCSUM & ifp->if_capenable) 7529 ifp->if_hwassist |= BCE_IF_HWASSIST; 7530 else 7531 ifp->if_hwassist &= ~BCE_IF_HWASSIST; 7532 } 7533 7534 /* Toggle the RX checksum capabilities enable flag. */ 7535 if (mask & IFCAP_RXCSUM && 7536 ifp->if_capabilities & IFCAP_RXCSUM) 7537 ifp->if_capenable ^= IFCAP_RXCSUM; 7538 7539 /* Toggle the TSO capabilities enable flag. */ 7540 if (bce_tso_enable && (mask & IFCAP_TSO4) && 7541 ifp->if_capabilities & IFCAP_TSO4) { 7542 ifp->if_capenable ^= IFCAP_TSO4; 7543 if (IFCAP_TSO4 & ifp->if_capenable) 7544 ifp->if_hwassist |= CSUM_TSO; 7545 else 7546 ifp->if_hwassist &= ~CSUM_TSO; 7547 } 7548 7549 if (mask & IFCAP_VLAN_HWCSUM && 7550 ifp->if_capabilities & IFCAP_VLAN_HWCSUM) 7551 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 7552 7553 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 7554 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 7555 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 7556 /* 7557 * Don't actually disable VLAN tag stripping as 7558 * management firmware (ASF/IPMI/UMP) requires the 7559 * feature. If VLAN tag stripping is disabled driver 7560 * will manually reconstruct the VLAN frame by 7561 * appending stripped VLAN tag. 7562 */ 7563 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 7564 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 7565 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 7566 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 7567 == 0) 7568 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 7569 } 7570 VLAN_CAPABILITIES(ifp); 7571 break; 7572 default: 7573 /* We don't know how to handle the IOCTL, pass it on. */ 7574 error = ether_ioctl(ifp, command, data); 7575 break; 7576 } 7577 7578 DBEXIT(BCE_VERBOSE_MISC); 7579 return(error); 7580 } 7581 7582 7583 /****************************************************************************/ 7584 /* Transmit timeout handler. */ 7585 /* */ 7586 /* Returns: */ 7587 /* Nothing. */ 7588 /****************************************************************************/ 7589 static void 7590 bce_watchdog(struct bce_softc *sc) 7591 { 7592 DBENTER(BCE_EXTREME_SEND); 7593 7594 BCE_LOCK_ASSERT(sc); 7595 7596 /* If the watchdog timer hasn't expired then just exit. */ 7597 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 7598 goto bce_watchdog_exit; 7599 7600 /* If pause frames are active then don't reset the hardware. */ 7601 /* ToDo: Should we reset the timer here? */ 7602 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 7603 goto bce_watchdog_exit; 7604 7605 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 7606 __FILE__, __LINE__); 7607 7608 DBRUNMSG(BCE_INFO, 7609 bce_dump_driver_state(sc); 7610 bce_dump_status_block(sc); 7611 bce_dump_stats_block(sc); 7612 bce_dump_ftqs(sc); 7613 bce_dump_txp_state(sc, 0); 7614 bce_dump_rxp_state(sc, 0); 7615 bce_dump_tpat_state(sc, 0); 7616 bce_dump_cp_state(sc, 0); 7617 bce_dump_com_state(sc, 0)); 7618 7619 DBRUN(bce_breakpoint(sc)); 7620 7621 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 7622 7623 bce_init_locked(sc); 7624 sc->bce_ifp->if_oerrors++; 7625 7626 bce_watchdog_exit: 7627 DBEXIT(BCE_EXTREME_SEND); 7628 } 7629 7630 7631 /* 7632 * Interrupt handler. 7633 */ 7634 /****************************************************************************/ 7635 /* Main interrupt entry point. Verifies that the controller generated the */ 7636 /* interrupt and then calls a separate routine for handle the various */ 7637 /* interrupt causes (PHY, TX, RX). */ 7638 /* */ 7639 /* Returns: */ 7640 /* 0 for success, positive value for failure. */ 7641 /****************************************************************************/ 7642 static void 7643 bce_intr(void *xsc) 7644 { 7645 struct bce_softc *sc; 7646 struct ifnet *ifp; 7647 u32 status_attn_bits; 7648 u16 hw_rx_cons, hw_tx_cons; 7649 7650 sc = xsc; 7651 ifp = sc->bce_ifp; 7652 7653 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7654 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 7655 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc)); 7656 7657 BCE_LOCK(sc); 7658 7659 DBRUN(sc->interrupts_generated++); 7660 7661 /* Synchnorize before we read from interface's status block */ 7662 bus_dmamap_sync(sc->status_tag, sc->status_map, 7663 BUS_DMASYNC_POSTREAD); 7664 7665 /* 7666 * If the hardware status block index 7667 * matches the last value read by the 7668 * driver and we haven't asserted our 7669 * interrupt then there's nothing to do. 7670 */ 7671 if ((sc->status_block->status_idx == sc->last_status_idx) && 7672 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & 7673 BCE_PCICFG_MISC_STATUS_INTA_VALUE)) { 7674 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n", 7675 __FUNCTION__); 7676 goto bce_intr_exit; 7677 } 7678 7679 /* Ack the interrupt and stop others from occuring. */ 7680 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 7681 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 7682 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 7683 7684 /* Check if the hardware has finished any work. */ 7685 hw_rx_cons = bce_get_hw_rx_cons(sc); 7686 hw_tx_cons = bce_get_hw_tx_cons(sc); 7687 7688 /* Keep processing data as long as there is work to do. */ 7689 for (;;) { 7690 7691 status_attn_bits = sc->status_block->status_attn_bits; 7692 7693 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control), 7694 BCE_PRINTF("Simulating unexpected status attention " 7695 "bit set."); 7696 sc->unexpected_attention_sim_count++; 7697 status_attn_bits = status_attn_bits | 7698 STATUS_ATTN_BITS_PARITY_ERROR); 7699 7700 /* Was it a link change interrupt? */ 7701 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 7702 (sc->status_block->status_attn_bits_ack & 7703 STATUS_ATTN_BITS_LINK_STATE)) { 7704 bce_phy_intr(sc); 7705 7706 /* Clear transient updates during link state change. */ 7707 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | 7708 BCE_HC_COMMAND_COAL_NOW_WO_INT); 7709 REG_RD(sc, BCE_HC_COMMAND); 7710 } 7711 7712 /* If any other attention is asserted, the chip is toast. */ 7713 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 7714 (sc->status_block->status_attn_bits_ack & 7715 ~STATUS_ATTN_BITS_LINK_STATE))) { 7716 7717 sc->unexpected_attention_count++; 7718 7719 BCE_PRINTF("%s(%d): Fatal attention detected: " 7720 "0x%08X\n", __FILE__, __LINE__, 7721 sc->status_block->status_attn_bits); 7722 7723 DBRUNMSG(BCE_FATAL, 7724 if (unexpected_attention_sim_control == 0) 7725 bce_breakpoint(sc)); 7726 7727 bce_init_locked(sc); 7728 goto bce_intr_exit; 7729 } 7730 7731 /* Check for any completed RX frames. */ 7732 if (hw_rx_cons != sc->hw_rx_cons) 7733 bce_rx_intr(sc); 7734 7735 /* Check for any completed TX frames. */ 7736 if (hw_tx_cons != sc->hw_tx_cons) 7737 bce_tx_intr(sc); 7738 7739 /* Save status block index value for the next interrupt. */ 7740 sc->last_status_idx = sc->status_block->status_idx; 7741 7742 /* 7743 * Prevent speculative reads from getting 7744 * ahead of the status block. 7745 */ 7746 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 7747 BUS_SPACE_BARRIER_READ); 7748 7749 /* 7750 * If there's no work left then exit the 7751 * interrupt service routine. 7752 */ 7753 hw_rx_cons = bce_get_hw_rx_cons(sc); 7754 hw_tx_cons = bce_get_hw_tx_cons(sc); 7755 7756 if ((hw_rx_cons == sc->hw_rx_cons) && 7757 (hw_tx_cons == sc->hw_tx_cons)) 7758 break; 7759 7760 } 7761 7762 bus_dmamap_sync(sc->status_tag, sc->status_map, 7763 BUS_DMASYNC_PREREAD); 7764 7765 /* Re-enable interrupts. */ 7766 bce_enable_intr(sc, 0); 7767 7768 /* Handle any frames that arrived while handling the interrupt. */ 7769 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 7770 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 7771 bce_start_locked(ifp); 7772 7773 bce_intr_exit: 7774 BCE_UNLOCK(sc); 7775 7776 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR); 7777 } 7778 7779 7780 /****************************************************************************/ 7781 /* Programs the various packet receive modes (broadcast and multicast). */ 7782 /* */ 7783 /* Returns: */ 7784 /* Nothing. */ 7785 /****************************************************************************/ 7786 static void 7787 bce_set_rx_mode(struct bce_softc *sc) 7788 { 7789 struct ifnet *ifp; 7790 struct ifmultiaddr *ifma; 7791 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 7792 u32 rx_mode, sort_mode; 7793 int h, i; 7794 7795 DBENTER(BCE_VERBOSE_MISC); 7796 7797 BCE_LOCK_ASSERT(sc); 7798 7799 ifp = sc->bce_ifp; 7800 7801 /* Initialize receive mode default settings. */ 7802 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 7803 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 7804 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 7805 7806 /* 7807 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 7808 * be enbled. 7809 */ 7810 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 7811 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 7812 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 7813 7814 /* 7815 * Check for promiscuous, all multicast, or selected 7816 * multicast address filtering. 7817 */ 7818 if (ifp->if_flags & IFF_PROMISC) { 7819 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 7820 7821 /* Enable promiscuous mode. */ 7822 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 7823 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 7824 } else if (ifp->if_flags & IFF_ALLMULTI) { 7825 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 7826 7827 /* Enable all multicast addresses. */ 7828 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 7829 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 7830 } 7831 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 7832 } else { 7833 /* Accept one or more multicast(s). */ 7834 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 7835 7836 if_maddr_rlock(ifp); 7837 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 7838 if (ifma->ifma_addr->sa_family != AF_LINK) 7839 continue; 7840 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 7841 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 7842 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 7843 } 7844 if_maddr_runlock(ifp); 7845 7846 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 7847 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 7848 7849 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 7850 } 7851 7852 /* Only make changes if the recive mode has actually changed. */ 7853 if (rx_mode != sc->rx_mode) { 7854 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: " 7855 "0x%08X\n", rx_mode); 7856 7857 sc->rx_mode = rx_mode; 7858 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 7859 } 7860 7861 /* Disable and clear the exisitng sort before enabling a new sort. */ 7862 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 7863 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 7864 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 7865 7866 DBEXIT(BCE_VERBOSE_MISC); 7867 } 7868 7869 7870 /****************************************************************************/ 7871 /* Called periodically to updates statistics from the controllers */ 7872 /* statistics block. */ 7873 /* */ 7874 /* Returns: */ 7875 /* Nothing. */ 7876 /****************************************************************************/ 7877 static void 7878 bce_stats_update(struct bce_softc *sc) 7879 { 7880 struct ifnet *ifp; 7881 struct statistics_block *stats; 7882 7883 DBENTER(BCE_EXTREME_MISC); 7884 7885 ifp = sc->bce_ifp; 7886 7887 stats = (struct statistics_block *) sc->stats_block; 7888 7889 /* 7890 * Certain controllers don't report 7891 * carrier sense errors correctly. 7892 * See errata E11_5708CA0_1165. 7893 */ 7894 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 7895 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 7896 ifp->if_oerrors += 7897 (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 7898 7899 /* 7900 * Update the sysctl statistics from the 7901 * hardware statistics. 7902 */ 7903 sc->stat_IfHCInOctets = 7904 ((u64) stats->stat_IfHCInOctets_hi << 32) + 7905 (u64) stats->stat_IfHCInOctets_lo; 7906 7907 sc->stat_IfHCInBadOctets = 7908 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 7909 (u64) stats->stat_IfHCInBadOctets_lo; 7910 7911 sc->stat_IfHCOutOctets = 7912 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 7913 (u64) stats->stat_IfHCOutOctets_lo; 7914 7915 sc->stat_IfHCOutBadOctets = 7916 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 7917 (u64) stats->stat_IfHCOutBadOctets_lo; 7918 7919 sc->stat_IfHCInUcastPkts = 7920 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 7921 (u64) stats->stat_IfHCInUcastPkts_lo; 7922 7923 sc->stat_IfHCInMulticastPkts = 7924 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 7925 (u64) stats->stat_IfHCInMulticastPkts_lo; 7926 7927 sc->stat_IfHCInBroadcastPkts = 7928 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 7929 (u64) stats->stat_IfHCInBroadcastPkts_lo; 7930 7931 sc->stat_IfHCOutUcastPkts = 7932 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 7933 (u64) stats->stat_IfHCOutUcastPkts_lo; 7934 7935 sc->stat_IfHCOutMulticastPkts = 7936 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 7937 (u64) stats->stat_IfHCOutMulticastPkts_lo; 7938 7939 sc->stat_IfHCOutBroadcastPkts = 7940 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 7941 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 7942 7943 /* ToDo: Preserve counters beyond 32 bits? */ 7944 /* ToDo: Read the statistics from auto-clear regs? */ 7945 7946 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 7947 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 7948 7949 sc->stat_Dot3StatsCarrierSenseErrors = 7950 stats->stat_Dot3StatsCarrierSenseErrors; 7951 7952 sc->stat_Dot3StatsFCSErrors = 7953 stats->stat_Dot3StatsFCSErrors; 7954 7955 sc->stat_Dot3StatsAlignmentErrors = 7956 stats->stat_Dot3StatsAlignmentErrors; 7957 7958 sc->stat_Dot3StatsSingleCollisionFrames = 7959 stats->stat_Dot3StatsSingleCollisionFrames; 7960 7961 sc->stat_Dot3StatsMultipleCollisionFrames = 7962 stats->stat_Dot3StatsMultipleCollisionFrames; 7963 7964 sc->stat_Dot3StatsDeferredTransmissions = 7965 stats->stat_Dot3StatsDeferredTransmissions; 7966 7967 sc->stat_Dot3StatsExcessiveCollisions = 7968 stats->stat_Dot3StatsExcessiveCollisions; 7969 7970 sc->stat_Dot3StatsLateCollisions = 7971 stats->stat_Dot3StatsLateCollisions; 7972 7973 sc->stat_EtherStatsCollisions = 7974 stats->stat_EtherStatsCollisions; 7975 7976 sc->stat_EtherStatsFragments = 7977 stats->stat_EtherStatsFragments; 7978 7979 sc->stat_EtherStatsJabbers = 7980 stats->stat_EtherStatsJabbers; 7981 7982 sc->stat_EtherStatsUndersizePkts = 7983 stats->stat_EtherStatsUndersizePkts; 7984 7985 sc->stat_EtherStatsOversizePkts = 7986 stats->stat_EtherStatsOversizePkts; 7987 7988 sc->stat_EtherStatsPktsRx64Octets = 7989 stats->stat_EtherStatsPktsRx64Octets; 7990 7991 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 7992 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 7993 7994 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 7995 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 7996 7997 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 7998 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 7999 8000 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 8001 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 8002 8003 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 8004 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 8005 8006 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 8007 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 8008 8009 sc->stat_EtherStatsPktsTx64Octets = 8010 stats->stat_EtherStatsPktsTx64Octets; 8011 8012 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 8013 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 8014 8015 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 8016 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 8017 8018 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 8019 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 8020 8021 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 8022 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 8023 8024 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 8025 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 8026 8027 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 8028 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 8029 8030 sc->stat_XonPauseFramesReceived = 8031 stats->stat_XonPauseFramesReceived; 8032 8033 sc->stat_XoffPauseFramesReceived = 8034 stats->stat_XoffPauseFramesReceived; 8035 8036 sc->stat_OutXonSent = 8037 stats->stat_OutXonSent; 8038 8039 sc->stat_OutXoffSent = 8040 stats->stat_OutXoffSent; 8041 8042 sc->stat_FlowControlDone = 8043 stats->stat_FlowControlDone; 8044 8045 sc->stat_MacControlFramesReceived = 8046 stats->stat_MacControlFramesReceived; 8047 8048 sc->stat_XoffStateEntered = 8049 stats->stat_XoffStateEntered; 8050 8051 sc->stat_IfInFramesL2FilterDiscards = 8052 stats->stat_IfInFramesL2FilterDiscards; 8053 8054 sc->stat_IfInRuleCheckerDiscards = 8055 stats->stat_IfInRuleCheckerDiscards; 8056 8057 sc->stat_IfInFTQDiscards = 8058 stats->stat_IfInFTQDiscards; 8059 8060 sc->stat_IfInMBUFDiscards = 8061 stats->stat_IfInMBUFDiscards; 8062 8063 sc->stat_IfInRuleCheckerP4Hit = 8064 stats->stat_IfInRuleCheckerP4Hit; 8065 8066 sc->stat_CatchupInRuleCheckerDiscards = 8067 stats->stat_CatchupInRuleCheckerDiscards; 8068 8069 sc->stat_CatchupInFTQDiscards = 8070 stats->stat_CatchupInFTQDiscards; 8071 8072 sc->stat_CatchupInMBUFDiscards = 8073 stats->stat_CatchupInMBUFDiscards; 8074 8075 sc->stat_CatchupInRuleCheckerP4Hit = 8076 stats->stat_CatchupInRuleCheckerP4Hit; 8077 8078 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 8079 8080 /* 8081 * Update the interface statistics from the 8082 * hardware statistics. 8083 */ 8084 ifp->if_collisions = 8085 (u_long) sc->stat_EtherStatsCollisions; 8086 8087 /* ToDo: This method loses soft errors. */ 8088 ifp->if_ierrors = 8089 (u_long) sc->stat_EtherStatsUndersizePkts + 8090 (u_long) sc->stat_EtherStatsOversizePkts + 8091 (u_long) sc->stat_IfInMBUFDiscards + 8092 (u_long) sc->stat_Dot3StatsAlignmentErrors + 8093 (u_long) sc->stat_Dot3StatsFCSErrors + 8094 (u_long) sc->stat_IfInRuleCheckerDiscards + 8095 (u_long) sc->stat_IfInFTQDiscards + 8096 (u_long) sc->com_no_buffers; 8097 8098 /* ToDo: This method loses soft errors. */ 8099 ifp->if_oerrors = 8100 (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 8101 (u_long) sc->stat_Dot3StatsExcessiveCollisions + 8102 (u_long) sc->stat_Dot3StatsLateCollisions; 8103 8104 /* ToDo: Add additional statistics? */ 8105 8106 DBEXIT(BCE_EXTREME_MISC); 8107 } 8108 8109 8110 /****************************************************************************/ 8111 /* Periodic function to notify the bootcode that the driver is still */ 8112 /* present. */ 8113 /* */ 8114 /* Returns: */ 8115 /* Nothing. */ 8116 /****************************************************************************/ 8117 static void 8118 bce_pulse(void *xsc) 8119 { 8120 struct bce_softc *sc = xsc; 8121 u32 msg; 8122 8123 DBENTER(BCE_EXTREME_MISC); 8124 8125 BCE_LOCK_ASSERT(sc); 8126 8127 /* Tell the firmware that the driver is still running. */ 8128 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 8129 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg); 8130 8131 /* Update the bootcode condition. */ 8132 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 8133 8134 /* Report whether the bootcode still knows the driver is running. */ 8135 if (bce_verbose || bootverbose) { 8136 if (sc->bce_drv_cardiac_arrest == FALSE) { 8137 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) { 8138 sc->bce_drv_cardiac_arrest = TRUE; 8139 BCE_PRINTF("%s(): Warning: bootcode " 8140 "thinks driver is absent! " 8141 "(bc_state = 0x%08X)\n", 8142 __FUNCTION__, sc->bc_state); 8143 } 8144 } else { 8145 /* 8146 * Not supported by all bootcode versions. 8147 * (v5.0.11+ and v5.2.1+) Older bootcode 8148 * will require the driver to reset the 8149 * controller to clear this condition. 8150 */ 8151 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) { 8152 sc->bce_drv_cardiac_arrest = FALSE; 8153 BCE_PRINTF("%s(): Bootcode found the " 8154 "driver pulse! (bc_state = 0x%08X)\n", 8155 __FUNCTION__, sc->bc_state); 8156 } 8157 } 8158 } 8159 8160 8161 /* Schedule the next pulse. */ 8162 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 8163 8164 DBEXIT(BCE_EXTREME_MISC); 8165 } 8166 8167 8168 /****************************************************************************/ 8169 /* Periodic function to perform maintenance tasks. */ 8170 /* */ 8171 /* Returns: */ 8172 /* Nothing. */ 8173 /****************************************************************************/ 8174 static void 8175 bce_tick(void *xsc) 8176 { 8177 struct bce_softc *sc = xsc; 8178 struct mii_data *mii; 8179 struct ifnet *ifp; 8180 8181 ifp = sc->bce_ifp; 8182 8183 DBENTER(BCE_EXTREME_MISC); 8184 8185 BCE_LOCK_ASSERT(sc); 8186 8187 /* Schedule the next tick. */ 8188 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 8189 8190 /* Update the statistics from the hardware statistics block. */ 8191 bce_stats_update(sc); 8192 8193 /* 8194 * ToDo: This is a safety measure. Need to re-evaluate 8195 * high level processing logic and eliminate this code. 8196 */ 8197 /* Top off the receive and page chains. */ 8198 if (bce_hdr_split == TRUE) 8199 bce_fill_pg_chain(sc); 8200 bce_fill_rx_chain(sc); 8201 8202 /* Check that chip hasn't hung. */ 8203 bce_watchdog(sc); 8204 8205 /* If link is up already up then we're done. */ 8206 if (sc->bce_link_up == TRUE) 8207 goto bce_tick_exit; 8208 8209 /* Link is down. Check what the PHY's doing. */ 8210 mii = device_get_softc(sc->bce_miibus); 8211 mii_tick(mii); 8212 8213 /* Check if the link has come up. */ 8214 if ((mii->mii_media_status & IFM_ACTIVE) && 8215 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) { 8216 DBPRINT(sc, BCE_VERBOSE_MISC, 8217 "%s(): Link up!\n", __FUNCTION__); 8218 sc->bce_link_up = TRUE; 8219 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 8220 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX || 8221 IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) && 8222 (bce_verbose || bootverbose)) 8223 BCE_PRINTF("Gigabit link up!\n"); 8224 8225 /* Now that link is up, handle any outstanding TX traffic. */ 8226 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 8227 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found " 8228 "pending TX traffic.\n", __FUNCTION__); 8229 bce_start_locked(ifp); 8230 } 8231 } 8232 8233 bce_tick_exit: 8234 DBEXIT(BCE_EXTREME_MISC); 8235 return; 8236 } 8237 8238 #ifdef BCE_DEBUG 8239 /****************************************************************************/ 8240 /* Allows the driver state to be dumped through the sysctl interface. */ 8241 /* */ 8242 /* Returns: */ 8243 /* 0 for success, positive value for failure. */ 8244 /****************************************************************************/ 8245 static int 8246 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 8247 { 8248 int error; 8249 int result; 8250 struct bce_softc *sc; 8251 8252 result = -1; 8253 error = sysctl_handle_int(oidp, &result, 0, req); 8254 8255 if (error || !req->newptr) 8256 return (error); 8257 8258 if (result == 1) { 8259 sc = (struct bce_softc *)arg1; 8260 bce_dump_driver_state(sc); 8261 } 8262 8263 return error; 8264 } 8265 8266 8267 /****************************************************************************/ 8268 /* Allows the hardware state to be dumped through the sysctl interface. */ 8269 /* */ 8270 /* Returns: */ 8271 /* 0 for success, positive value for failure. */ 8272 /****************************************************************************/ 8273 static int 8274 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 8275 { 8276 int error; 8277 int result; 8278 struct bce_softc *sc; 8279 8280 result = -1; 8281 error = sysctl_handle_int(oidp, &result, 0, req); 8282 8283 if (error || !req->newptr) 8284 return (error); 8285 8286 if (result == 1) { 8287 sc = (struct bce_softc *)arg1; 8288 bce_dump_hw_state(sc); 8289 } 8290 8291 return error; 8292 } 8293 8294 8295 /****************************************************************************/ 8296 /* Allows the status block to be dumped through the sysctl interface. */ 8297 /* */ 8298 /* Returns: */ 8299 /* 0 for success, positive value for failure. */ 8300 /****************************************************************************/ 8301 static int 8302 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS) 8303 { 8304 int error; 8305 int result; 8306 struct bce_softc *sc; 8307 8308 result = -1; 8309 error = sysctl_handle_int(oidp, &result, 0, req); 8310 8311 if (error || !req->newptr) 8312 return (error); 8313 8314 if (result == 1) { 8315 sc = (struct bce_softc *)arg1; 8316 bce_dump_status_block(sc); 8317 } 8318 8319 return error; 8320 } 8321 8322 8323 /****************************************************************************/ 8324 /* Allows the stats block to be dumped through the sysctl interface. */ 8325 /* */ 8326 /* Returns: */ 8327 /* 0 for success, positive value for failure. */ 8328 /****************************************************************************/ 8329 static int 8330 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS) 8331 { 8332 int error; 8333 int result; 8334 struct bce_softc *sc; 8335 8336 result = -1; 8337 error = sysctl_handle_int(oidp, &result, 0, req); 8338 8339 if (error || !req->newptr) 8340 return (error); 8341 8342 if (result == 1) { 8343 sc = (struct bce_softc *)arg1; 8344 bce_dump_stats_block(sc); 8345 } 8346 8347 return error; 8348 } 8349 8350 8351 /****************************************************************************/ 8352 /* Allows the stat counters to be cleared without unloading/reloading the */ 8353 /* driver. */ 8354 /* */ 8355 /* Returns: */ 8356 /* 0 for success, positive value for failure. */ 8357 /****************************************************************************/ 8358 static int 8359 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS) 8360 { 8361 int error; 8362 int result; 8363 struct bce_softc *sc; 8364 8365 result = -1; 8366 error = sysctl_handle_int(oidp, &result, 0, req); 8367 8368 if (error || !req->newptr) 8369 return (error); 8370 8371 if (result == 1) { 8372 sc = (struct bce_softc *)arg1; 8373 struct statistics_block *stats; 8374 8375 stats = (struct statistics_block *) sc->stats_block; 8376 bzero(stats, sizeof(struct statistics_block)); 8377 8378 /* Clear the internal H/W statistics counters. */ 8379 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 8380 8381 /* Reset the driver maintained statistics. */ 8382 sc->interrupts_rx = 8383 sc->interrupts_tx = 0; 8384 sc->tso_frames_requested = 8385 sc->tso_frames_completed = 8386 sc->tso_frames_failed = 0; 8387 sc->rx_empty_count = 8388 sc->tx_full_count = 0; 8389 sc->rx_low_watermark = USABLE_RX_BD_ALLOC; 8390 sc->tx_hi_watermark = 0; 8391 sc->l2fhdr_error_count = 8392 sc->l2fhdr_error_sim_count = 0; 8393 sc->mbuf_alloc_failed_count = 8394 sc->mbuf_alloc_failed_sim_count = 0; 8395 sc->dma_map_addr_rx_failed_count = 8396 sc->dma_map_addr_tx_failed_count = 0; 8397 sc->mbuf_frag_count = 0; 8398 sc->csum_offload_tcp_udp = 8399 sc->csum_offload_ip = 0; 8400 sc->vlan_tagged_frames_rcvd = 8401 sc->vlan_tagged_frames_stripped = 0; 8402 sc->split_header_frames_rcvd = 8403 sc->split_header_tcp_frames_rcvd = 0; 8404 8405 /* Clear firmware maintained statistics. */ 8406 REG_WR_IND(sc, 0x120084, 0); 8407 } 8408 8409 return error; 8410 } 8411 8412 8413 /****************************************************************************/ 8414 /* Allows the shared memory contents to be dumped through the sysctl . */ 8415 /* interface. */ 8416 /* */ 8417 /* Returns: */ 8418 /* 0 for success, positive value for failure. */ 8419 /****************************************************************************/ 8420 static int 8421 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS) 8422 { 8423 int error; 8424 int result; 8425 struct bce_softc *sc; 8426 8427 result = -1; 8428 error = sysctl_handle_int(oidp, &result, 0, req); 8429 8430 if (error || !req->newptr) 8431 return (error); 8432 8433 if (result == 1) { 8434 sc = (struct bce_softc *)arg1; 8435 bce_dump_shmem_state(sc); 8436 } 8437 8438 return error; 8439 } 8440 8441 8442 /****************************************************************************/ 8443 /* Allows the bootcode state to be dumped through the sysctl interface. */ 8444 /* */ 8445 /* Returns: */ 8446 /* 0 for success, positive value for failure. */ 8447 /****************************************************************************/ 8448 static int 8449 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 8450 { 8451 int error; 8452 int result; 8453 struct bce_softc *sc; 8454 8455 result = -1; 8456 error = sysctl_handle_int(oidp, &result, 0, req); 8457 8458 if (error || !req->newptr) 8459 return (error); 8460 8461 if (result == 1) { 8462 sc = (struct bce_softc *)arg1; 8463 bce_dump_bc_state(sc); 8464 } 8465 8466 return error; 8467 } 8468 8469 8470 /****************************************************************************/ 8471 /* Provides a sysctl interface to allow dumping the RX BD chain. */ 8472 /* */ 8473 /* Returns: */ 8474 /* 0 for success, positive value for failure. */ 8475 /****************************************************************************/ 8476 static int 8477 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS) 8478 { 8479 int error; 8480 int result; 8481 struct bce_softc *sc; 8482 8483 result = -1; 8484 error = sysctl_handle_int(oidp, &result, 0, req); 8485 8486 if (error || !req->newptr) 8487 return (error); 8488 8489 if (result == 1) { 8490 sc = (struct bce_softc *)arg1; 8491 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC); 8492 } 8493 8494 return error; 8495 } 8496 8497 8498 /****************************************************************************/ 8499 /* Provides a sysctl interface to allow dumping the RX MBUF chain. */ 8500 /* */ 8501 /* Returns: */ 8502 /* 0 for success, positive value for failure. */ 8503 /****************************************************************************/ 8504 static int 8505 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS) 8506 { 8507 int error; 8508 int result; 8509 struct bce_softc *sc; 8510 8511 result = -1; 8512 error = sysctl_handle_int(oidp, &result, 0, req); 8513 8514 if (error || !req->newptr) 8515 return (error); 8516 8517 if (result == 1) { 8518 sc = (struct bce_softc *)arg1; 8519 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 8520 } 8521 8522 return error; 8523 } 8524 8525 8526 /****************************************************************************/ 8527 /* Provides a sysctl interface to allow dumping the TX chain. */ 8528 /* */ 8529 /* Returns: */ 8530 /* 0 for success, positive value for failure. */ 8531 /****************************************************************************/ 8532 static int 8533 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 8534 { 8535 int error; 8536 int result; 8537 struct bce_softc *sc; 8538 8539 result = -1; 8540 error = sysctl_handle_int(oidp, &result, 0, req); 8541 8542 if (error || !req->newptr) 8543 return (error); 8544 8545 if (result == 1) { 8546 sc = (struct bce_softc *)arg1; 8547 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC); 8548 } 8549 8550 return error; 8551 } 8552 8553 8554 /****************************************************************************/ 8555 /* Provides a sysctl interface to allow dumping the page chain. */ 8556 /* */ 8557 /* Returns: */ 8558 /* 0 for success, positive value for failure. */ 8559 /****************************************************************************/ 8560 static int 8561 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS) 8562 { 8563 int error; 8564 int result; 8565 struct bce_softc *sc; 8566 8567 result = -1; 8568 error = sysctl_handle_int(oidp, &result, 0, req); 8569 8570 if (error || !req->newptr) 8571 return (error); 8572 8573 if (result == 1) { 8574 sc = (struct bce_softc *)arg1; 8575 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC); 8576 } 8577 8578 return error; 8579 } 8580 8581 /****************************************************************************/ 8582 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */ 8583 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8584 /* */ 8585 /* Returns: */ 8586 /* 0 for success, positive value for failure. */ 8587 /****************************************************************************/ 8588 static int 8589 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS) 8590 { 8591 struct bce_softc *sc = (struct bce_softc *)arg1; 8592 int error; 8593 u32 result; 8594 u32 val[1]; 8595 u8 *data = (u8 *) val; 8596 8597 result = -1; 8598 error = sysctl_handle_int(oidp, &result, 0, req); 8599 if (error || (req->newptr == NULL)) 8600 return (error); 8601 8602 error = bce_nvram_read(sc, result, data, 4); 8603 8604 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0])); 8605 8606 return (error); 8607 } 8608 8609 8610 /****************************************************************************/ 8611 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 8612 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8613 /* */ 8614 /* Returns: */ 8615 /* 0 for success, positive value for failure. */ 8616 /****************************************************************************/ 8617 static int 8618 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 8619 { 8620 struct bce_softc *sc = (struct bce_softc *)arg1; 8621 int error; 8622 u32 val, result; 8623 8624 result = -1; 8625 error = sysctl_handle_int(oidp, &result, 0, req); 8626 if (error || (req->newptr == NULL)) 8627 return (error); 8628 8629 /* Make sure the register is accessible. */ 8630 if (result < 0x8000) { 8631 val = REG_RD(sc, result); 8632 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8633 } else if (result < 0x0280000) { 8634 val = REG_RD_IND(sc, result); 8635 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 8636 } 8637 8638 return (error); 8639 } 8640 8641 8642 /****************************************************************************/ 8643 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 8644 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8645 /* */ 8646 /* Returns: */ 8647 /* 0 for success, positive value for failure. */ 8648 /****************************************************************************/ 8649 static int 8650 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 8651 { 8652 struct bce_softc *sc; 8653 device_t dev; 8654 int error, result; 8655 u16 val; 8656 8657 result = -1; 8658 error = sysctl_handle_int(oidp, &result, 0, req); 8659 if (error || (req->newptr == NULL)) 8660 return (error); 8661 8662 /* Make sure the register is accessible. */ 8663 if (result < 0x20) { 8664 sc = (struct bce_softc *)arg1; 8665 dev = sc->bce_dev; 8666 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 8667 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 8668 } 8669 return (error); 8670 } 8671 8672 8673 /****************************************************************************/ 8674 /* Provides a sysctl interface for dumping the nvram contents. */ 8675 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8676 /* */ 8677 /* Returns: */ 8678 /* 0 for success, positive errno for failure. */ 8679 /****************************************************************************/ 8680 static int 8681 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS) 8682 { 8683 struct bce_softc *sc = (struct bce_softc *)arg1; 8684 int error, i; 8685 8686 if (sc->nvram_buf == NULL) 8687 sc->nvram_buf = malloc(sc->bce_flash_size, 8688 M_TEMP, M_ZERO | M_WAITOK); 8689 8690 error = 0; 8691 if (req->oldlen == sc->bce_flash_size) { 8692 for (i = 0; i < sc->bce_flash_size && error == 0; i++) 8693 error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1); 8694 } 8695 8696 if (error == 0) 8697 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size); 8698 8699 return error; 8700 } 8701 8702 #ifdef BCE_NVRAM_WRITE_SUPPORT 8703 /****************************************************************************/ 8704 /* Provides a sysctl interface for writing to nvram. */ 8705 /* DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8706 /* */ 8707 /* Returns: */ 8708 /* 0 for success, positive errno for failure. */ 8709 /****************************************************************************/ 8710 static int 8711 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS) 8712 { 8713 struct bce_softc *sc = (struct bce_softc *)arg1; 8714 int error; 8715 8716 if (sc->nvram_buf == NULL) 8717 sc->nvram_buf = malloc(sc->bce_flash_size, 8718 M_TEMP, M_ZERO | M_WAITOK); 8719 else 8720 bzero(sc->nvram_buf, sc->bce_flash_size); 8721 8722 error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size); 8723 if (error == 0) 8724 return (error); 8725 8726 if (req->newlen == sc->bce_flash_size) 8727 error = bce_nvram_write(sc, 0, sc->nvram_buf, 8728 sc->bce_flash_size); 8729 8730 8731 return error; 8732 } 8733 #endif 8734 8735 8736 /****************************************************************************/ 8737 /* Provides a sysctl interface to allow reading a CID. */ 8738 /* */ 8739 /* Returns: */ 8740 /* 0 for success, positive value for failure. */ 8741 /****************************************************************************/ 8742 static int 8743 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS) 8744 { 8745 struct bce_softc *sc; 8746 int error, result; 8747 8748 result = -1; 8749 error = sysctl_handle_int(oidp, &result, 0, req); 8750 if (error || (req->newptr == NULL)) 8751 return (error); 8752 8753 /* Make sure the register is accessible. */ 8754 if (result <= TX_CID) { 8755 sc = (struct bce_softc *)arg1; 8756 bce_dump_ctx(sc, result); 8757 } 8758 8759 return (error); 8760 } 8761 8762 8763 /****************************************************************************/ 8764 /* Provides a sysctl interface to forcing the driver to dump state and */ 8765 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 8766 /* */ 8767 /* Returns: */ 8768 /* 0 for success, positive value for failure. */ 8769 /****************************************************************************/ 8770 static int 8771 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 8772 { 8773 int error; 8774 int result; 8775 struct bce_softc *sc; 8776 8777 result = -1; 8778 error = sysctl_handle_int(oidp, &result, 0, req); 8779 8780 if (error || !req->newptr) 8781 return (error); 8782 8783 if (result == 1) { 8784 sc = (struct bce_softc *)arg1; 8785 bce_breakpoint(sc); 8786 } 8787 8788 return error; 8789 } 8790 #endif 8791 8792 /****************************************************************************/ 8793 /* Adds any sysctl parameters for tuning or debugging purposes. */ 8794 /* */ 8795 /* Returns: */ 8796 /* 0 for success, positive value for failure. */ 8797 /****************************************************************************/ 8798 static void 8799 bce_add_sysctls(struct bce_softc *sc) 8800 { 8801 struct sysctl_ctx_list *ctx; 8802 struct sysctl_oid_list *children; 8803 8804 DBENTER(BCE_VERBOSE_MISC); 8805 8806 ctx = device_get_sysctl_ctx(sc->bce_dev); 8807 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 8808 8809 #ifdef BCE_DEBUG 8810 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8811 "l2fhdr_error_sim_control", 8812 CTLFLAG_RW, &l2fhdr_error_sim_control, 8813 0, "Debug control to force l2fhdr errors"); 8814 8815 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8816 "l2fhdr_error_sim_count", 8817 CTLFLAG_RD, &sc->l2fhdr_error_sim_count, 8818 0, "Number of simulated l2_fhdr errors"); 8819 #endif 8820 8821 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8822 "l2fhdr_error_count", 8823 CTLFLAG_RD, &sc->l2fhdr_error_count, 8824 0, "Number of l2_fhdr errors"); 8825 8826 #ifdef BCE_DEBUG 8827 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8828 "mbuf_alloc_failed_sim_control", 8829 CTLFLAG_RW, &mbuf_alloc_failed_sim_control, 8830 0, "Debug control to force mbuf allocation failures"); 8831 8832 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8833 "mbuf_alloc_failed_sim_count", 8834 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count, 8835 0, "Number of simulated mbuf cluster allocation failures"); 8836 #endif 8837 8838 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8839 "mbuf_alloc_failed_count", 8840 CTLFLAG_RD, &sc->mbuf_alloc_failed_count, 8841 0, "Number of mbuf allocation failures"); 8842 8843 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8844 "mbuf_frag_count", 8845 CTLFLAG_RD, &sc->mbuf_frag_count, 8846 0, "Number of fragmented mbufs"); 8847 8848 #ifdef BCE_DEBUG 8849 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8850 "dma_map_addr_failed_sim_control", 8851 CTLFLAG_RW, &dma_map_addr_failed_sim_control, 8852 0, "Debug control to force DMA mapping failures"); 8853 8854 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */ 8855 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8856 "dma_map_addr_failed_sim_count", 8857 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count, 8858 0, "Number of simulated DMA mapping failures"); 8859 8860 #endif 8861 8862 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8863 "dma_map_addr_rx_failed_count", 8864 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count, 8865 0, "Number of RX DMA mapping failures"); 8866 8867 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8868 "dma_map_addr_tx_failed_count", 8869 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count, 8870 0, "Number of TX DMA mapping failures"); 8871 8872 #ifdef BCE_DEBUG 8873 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8874 "unexpected_attention_sim_control", 8875 CTLFLAG_RW, &unexpected_attention_sim_control, 8876 0, "Debug control to simulate unexpected attentions"); 8877 8878 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8879 "unexpected_attention_sim_count", 8880 CTLFLAG_RW, &sc->unexpected_attention_sim_count, 8881 0, "Number of simulated unexpected attentions"); 8882 #endif 8883 8884 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 8885 "unexpected_attention_count", 8886 CTLFLAG_RW, &sc->unexpected_attention_count, 8887 0, "Number of unexpected attentions"); 8888 8889 #ifdef BCE_DEBUG 8890 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8891 "debug_bootcode_running_failure", 8892 CTLFLAG_RW, &bootcode_running_failure_sim_control, 8893 0, "Debug control to force bootcode running failures"); 8894 8895 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8896 "rx_low_watermark", 8897 CTLFLAG_RD, &sc->rx_low_watermark, 8898 0, "Lowest level of free rx_bd's"); 8899 8900 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8901 "rx_empty_count", 8902 CTLFLAG_RD, &sc->rx_empty_count, 8903 "Number of times the RX chain was empty"); 8904 8905 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 8906 "tx_hi_watermark", 8907 CTLFLAG_RD, &sc->tx_hi_watermark, 8908 0, "Highest level of used tx_bd's"); 8909 8910 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8911 "tx_full_count", 8912 CTLFLAG_RD, &sc->tx_full_count, 8913 "Number of times the TX chain was full"); 8914 8915 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8916 "tso_frames_requested", 8917 CTLFLAG_RD, &sc->tso_frames_requested, 8918 "Number of TSO frames requested"); 8919 8920 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8921 "tso_frames_completed", 8922 CTLFLAG_RD, &sc->tso_frames_completed, 8923 "Number of TSO frames completed"); 8924 8925 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8926 "tso_frames_failed", 8927 CTLFLAG_RD, &sc->tso_frames_failed, 8928 "Number of TSO frames failed"); 8929 8930 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8931 "csum_offload_ip", 8932 CTLFLAG_RD, &sc->csum_offload_ip, 8933 "Number of IP checksum offload frames"); 8934 8935 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8936 "csum_offload_tcp_udp", 8937 CTLFLAG_RD, &sc->csum_offload_tcp_udp, 8938 "Number of TCP/UDP checksum offload frames"); 8939 8940 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8941 "vlan_tagged_frames_rcvd", 8942 CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd, 8943 "Number of VLAN tagged frames received"); 8944 8945 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8946 "vlan_tagged_frames_stripped", 8947 CTLFLAG_RD, &sc->vlan_tagged_frames_stripped, 8948 "Number of VLAN tagged frames stripped"); 8949 8950 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8951 "interrupts_rx", 8952 CTLFLAG_RD, &sc->interrupts_rx, 8953 "Number of RX interrupts"); 8954 8955 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8956 "interrupts_tx", 8957 CTLFLAG_RD, &sc->interrupts_tx, 8958 "Number of TX interrupts"); 8959 8960 if (bce_hdr_split == TRUE) { 8961 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8962 "split_header_frames_rcvd", 8963 CTLFLAG_RD, &sc->split_header_frames_rcvd, 8964 "Number of split header frames received"); 8965 8966 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8967 "split_header_tcp_frames_rcvd", 8968 CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd, 8969 "Number of split header TCP frames received"); 8970 } 8971 8972 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8973 "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD, 8974 (void *)sc, 0, 8975 bce_sysctl_nvram_dump, "S", ""); 8976 8977 #ifdef BCE_NVRAM_WRITE_SUPPORT 8978 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 8979 "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR, 8980 (void *)sc, 0, 8981 bce_sysctl_nvram_write, "S", ""); 8982 #endif 8983 #endif /* BCE_DEBUG */ 8984 8985 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8986 "stat_IfHcInOctets", 8987 CTLFLAG_RD, &sc->stat_IfHCInOctets, 8988 "Bytes received"); 8989 8990 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8991 "stat_IfHCInBadOctets", 8992 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 8993 "Bad bytes received"); 8994 8995 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 8996 "stat_IfHCOutOctets", 8997 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 8998 "Bytes sent"); 8999 9000 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9001 "stat_IfHCOutBadOctets", 9002 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 9003 "Bad bytes sent"); 9004 9005 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9006 "stat_IfHCInUcastPkts", 9007 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 9008 "Unicast packets received"); 9009 9010 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9011 "stat_IfHCInMulticastPkts", 9012 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 9013 "Multicast packets received"); 9014 9015 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9016 "stat_IfHCInBroadcastPkts", 9017 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 9018 "Broadcast packets received"); 9019 9020 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9021 "stat_IfHCOutUcastPkts", 9022 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 9023 "Unicast packets sent"); 9024 9025 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9026 "stat_IfHCOutMulticastPkts", 9027 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 9028 "Multicast packets sent"); 9029 9030 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO, 9031 "stat_IfHCOutBroadcastPkts", 9032 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 9033 "Broadcast packets sent"); 9034 9035 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9036 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 9037 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 9038 0, "Internal MAC transmit errors"); 9039 9040 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9041 "stat_Dot3StatsCarrierSenseErrors", 9042 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 9043 0, "Carrier sense errors"); 9044 9045 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9046 "stat_Dot3StatsFCSErrors", 9047 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 9048 0, "Frame check sequence errors"); 9049 9050 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9051 "stat_Dot3StatsAlignmentErrors", 9052 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 9053 0, "Alignment errors"); 9054 9055 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9056 "stat_Dot3StatsSingleCollisionFrames", 9057 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 9058 0, "Single Collision Frames"); 9059 9060 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9061 "stat_Dot3StatsMultipleCollisionFrames", 9062 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 9063 0, "Multiple Collision Frames"); 9064 9065 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9066 "stat_Dot3StatsDeferredTransmissions", 9067 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 9068 0, "Deferred Transmissions"); 9069 9070 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9071 "stat_Dot3StatsExcessiveCollisions", 9072 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 9073 0, "Excessive Collisions"); 9074 9075 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9076 "stat_Dot3StatsLateCollisions", 9077 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 9078 0, "Late Collisions"); 9079 9080 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9081 "stat_EtherStatsCollisions", 9082 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 9083 0, "Collisions"); 9084 9085 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9086 "stat_EtherStatsFragments", 9087 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 9088 0, "Fragments"); 9089 9090 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9091 "stat_EtherStatsJabbers", 9092 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 9093 0, "Jabbers"); 9094 9095 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9096 "stat_EtherStatsUndersizePkts", 9097 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 9098 0, "Undersize packets"); 9099 9100 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9101 "stat_EtherStatsOversizePkts", 9102 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts, 9103 0, "stat_EtherStatsOversizePkts"); 9104 9105 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9106 "stat_EtherStatsPktsRx64Octets", 9107 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 9108 0, "Bytes received in 64 byte packets"); 9109 9110 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9111 "stat_EtherStatsPktsRx65Octetsto127Octets", 9112 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 9113 0, "Bytes received in 65 to 127 byte packets"); 9114 9115 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9116 "stat_EtherStatsPktsRx128Octetsto255Octets", 9117 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 9118 0, "Bytes received in 128 to 255 byte packets"); 9119 9120 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9121 "stat_EtherStatsPktsRx256Octetsto511Octets", 9122 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 9123 0, "Bytes received in 256 to 511 byte packets"); 9124 9125 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9126 "stat_EtherStatsPktsRx512Octetsto1023Octets", 9127 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 9128 0, "Bytes received in 512 to 1023 byte packets"); 9129 9130 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9131 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 9132 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 9133 0, "Bytes received in 1024 t0 1522 byte packets"); 9134 9135 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9136 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 9137 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 9138 0, "Bytes received in 1523 to 9022 byte packets"); 9139 9140 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9141 "stat_EtherStatsPktsTx64Octets", 9142 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 9143 0, "Bytes sent in 64 byte packets"); 9144 9145 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9146 "stat_EtherStatsPktsTx65Octetsto127Octets", 9147 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 9148 0, "Bytes sent in 65 to 127 byte packets"); 9149 9150 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9151 "stat_EtherStatsPktsTx128Octetsto255Octets", 9152 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 9153 0, "Bytes sent in 128 to 255 byte packets"); 9154 9155 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9156 "stat_EtherStatsPktsTx256Octetsto511Octets", 9157 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 9158 0, "Bytes sent in 256 to 511 byte packets"); 9159 9160 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9161 "stat_EtherStatsPktsTx512Octetsto1023Octets", 9162 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 9163 0, "Bytes sent in 512 to 1023 byte packets"); 9164 9165 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9166 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 9167 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 9168 0, "Bytes sent in 1024 to 1522 byte packets"); 9169 9170 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9171 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 9172 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 9173 0, "Bytes sent in 1523 to 9022 byte packets"); 9174 9175 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9176 "stat_XonPauseFramesReceived", 9177 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 9178 0, "XON pause frames receved"); 9179 9180 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9181 "stat_XoffPauseFramesReceived", 9182 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 9183 0, "XOFF pause frames received"); 9184 9185 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9186 "stat_OutXonSent", 9187 CTLFLAG_RD, &sc->stat_OutXonSent, 9188 0, "XON pause frames sent"); 9189 9190 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9191 "stat_OutXoffSent", 9192 CTLFLAG_RD, &sc->stat_OutXoffSent, 9193 0, "XOFF pause frames sent"); 9194 9195 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9196 "stat_FlowControlDone", 9197 CTLFLAG_RD, &sc->stat_FlowControlDone, 9198 0, "Flow control done"); 9199 9200 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9201 "stat_MacControlFramesReceived", 9202 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 9203 0, "MAC control frames received"); 9204 9205 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9206 "stat_XoffStateEntered", 9207 CTLFLAG_RD, &sc->stat_XoffStateEntered, 9208 0, "XOFF state entered"); 9209 9210 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9211 "stat_IfInFramesL2FilterDiscards", 9212 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 9213 0, "Received L2 packets discarded"); 9214 9215 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9216 "stat_IfInRuleCheckerDiscards", 9217 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 9218 0, "Received packets discarded by rule"); 9219 9220 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9221 "stat_IfInFTQDiscards", 9222 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 9223 0, "Received packet FTQ discards"); 9224 9225 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9226 "stat_IfInMBUFDiscards", 9227 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 9228 0, "Received packets discarded due to lack " 9229 "of controller buffer memory"); 9230 9231 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9232 "stat_IfInRuleCheckerP4Hit", 9233 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 9234 0, "Received packets rule checker hits"); 9235 9236 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9237 "stat_CatchupInRuleCheckerDiscards", 9238 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 9239 0, "Received packets discarded in Catchup path"); 9240 9241 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9242 "stat_CatchupInFTQDiscards", 9243 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 9244 0, "Received packets discarded in FTQ in Catchup path"); 9245 9246 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9247 "stat_CatchupInMBUFDiscards", 9248 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 9249 0, "Received packets discarded in controller " 9250 "buffer memory in Catchup path"); 9251 9252 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9253 "stat_CatchupInRuleCheckerP4Hit", 9254 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 9255 0, "Received packets rule checker hits in Catchup path"); 9256 9257 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 9258 "com_no_buffers", 9259 CTLFLAG_RD, &sc->com_no_buffers, 9260 0, "Valid packets received but no RX buffers available"); 9261 9262 #ifdef BCE_DEBUG 9263 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9264 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 9265 (void *)sc, 0, 9266 bce_sysctl_driver_state, "I", "Drive state information"); 9267 9268 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9269 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 9270 (void *)sc, 0, 9271 bce_sysctl_hw_state, "I", "Hardware state information"); 9272 9273 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9274 "status_block", CTLTYPE_INT | CTLFLAG_RW, 9275 (void *)sc, 0, 9276 bce_sysctl_status_block, "I", "Dump status block"); 9277 9278 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9279 "stats_block", CTLTYPE_INT | CTLFLAG_RW, 9280 (void *)sc, 0, 9281 bce_sysctl_stats_block, "I", "Dump statistics block"); 9282 9283 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9284 "stats_clear", CTLTYPE_INT | CTLFLAG_RW, 9285 (void *)sc, 0, 9286 bce_sysctl_stats_clear, "I", "Clear statistics block"); 9287 9288 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9289 "shmem_state", CTLTYPE_INT | CTLFLAG_RW, 9290 (void *)sc, 0, 9291 bce_sysctl_shmem_state, "I", "Shared memory state information"); 9292 9293 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9294 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 9295 (void *)sc, 0, 9296 bce_sysctl_bc_state, "I", "Bootcode state information"); 9297 9298 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9299 "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW, 9300 (void *)sc, 0, 9301 bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain"); 9302 9303 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9304 "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW, 9305 (void *)sc, 0, 9306 bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain"); 9307 9308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9309 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 9310 (void *)sc, 0, 9311 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 9312 9313 if (bce_hdr_split == TRUE) { 9314 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9315 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW, 9316 (void *)sc, 0, 9317 bce_sysctl_dump_pg_chain, "I", "Dump page chain"); 9318 } 9319 9320 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9321 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW, 9322 (void *)sc, 0, 9323 bce_sysctl_dump_ctx, "I", "Dump context memory"); 9324 9325 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9326 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 9327 (void *)sc, 0, 9328 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 9329 9330 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9331 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 9332 (void *)sc, 0, 9333 bce_sysctl_reg_read, "I", "Register read"); 9334 9335 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9336 "nvram_read", CTLTYPE_INT | CTLFLAG_RW, 9337 (void *)sc, 0, 9338 bce_sysctl_nvram_read, "I", "NVRAM read"); 9339 9340 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 9341 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 9342 (void *)sc, 0, 9343 bce_sysctl_phy_read, "I", "PHY register read"); 9344 9345 #endif 9346 9347 DBEXIT(BCE_VERBOSE_MISC); 9348 } 9349 9350 9351 /****************************************************************************/ 9352 /* BCE Debug Routines */ 9353 /****************************************************************************/ 9354 #ifdef BCE_DEBUG 9355 9356 /****************************************************************************/ 9357 /* Freezes the controller to allow for a cohesive state dump. */ 9358 /* */ 9359 /* Returns: */ 9360 /* Nothing. */ 9361 /****************************************************************************/ 9362 static __attribute__ ((noinline)) void 9363 bce_freeze_controller(struct bce_softc *sc) 9364 { 9365 u32 val; 9366 val = REG_RD(sc, BCE_MISC_COMMAND); 9367 val |= BCE_MISC_COMMAND_DISABLE_ALL; 9368 REG_WR(sc, BCE_MISC_COMMAND, val); 9369 } 9370 9371 9372 /****************************************************************************/ 9373 /* Unfreezes the controller after a freeze operation. This may not always */ 9374 /* work and the controller will require a reset! */ 9375 /* */ 9376 /* Returns: */ 9377 /* Nothing. */ 9378 /****************************************************************************/ 9379 static __attribute__ ((noinline)) void 9380 bce_unfreeze_controller(struct bce_softc *sc) 9381 { 9382 u32 val; 9383 val = REG_RD(sc, BCE_MISC_COMMAND); 9384 val |= BCE_MISC_COMMAND_ENABLE_ALL; 9385 REG_WR(sc, BCE_MISC_COMMAND, val); 9386 } 9387 9388 9389 /****************************************************************************/ 9390 /* Prints out Ethernet frame information from an mbuf. */ 9391 /* */ 9392 /* Partially decode an Ethernet frame to look at some important headers. */ 9393 /* */ 9394 /* Returns: */ 9395 /* Nothing. */ 9396 /****************************************************************************/ 9397 static __attribute__ ((noinline)) void 9398 bce_dump_enet(struct bce_softc *sc, struct mbuf *m) 9399 { 9400 struct ether_vlan_header *eh; 9401 u16 etype; 9402 int ehlen; 9403 struct ip *ip; 9404 struct tcphdr *th; 9405 struct udphdr *uh; 9406 struct arphdr *ah; 9407 9408 BCE_PRINTF( 9409 "-----------------------------" 9410 " Frame Decode " 9411 "-----------------------------\n"); 9412 9413 eh = mtod(m, struct ether_vlan_header *); 9414 9415 /* Handle VLAN encapsulation if present. */ 9416 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 9417 etype = ntohs(eh->evl_proto); 9418 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 9419 } else { 9420 etype = ntohs(eh->evl_encap_proto); 9421 ehlen = ETHER_HDR_LEN; 9422 } 9423 9424 /* ToDo: Add VLAN output. */ 9425 BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n", 9426 eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen); 9427 9428 switch (etype) { 9429 case ETHERTYPE_IP: 9430 ip = (struct ip *)(m->m_data + ehlen); 9431 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, " 9432 "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n", 9433 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr), 9434 ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum)); 9435 9436 switch (ip->ip_p) { 9437 case IPPROTO_TCP: 9438 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9439 BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = " 9440 "%d bytes, flags = 0x%b, csum = 0x%04X\n", 9441 ntohs(th->th_dport), ntohs(th->th_sport), 9442 (th->th_off << 2), th->th_flags, 9443 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST" 9444 "\02SYN\01FIN", ntohs(th->th_sum)); 9445 break; 9446 case IPPROTO_UDP: 9447 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 9448 BCE_PRINTF("-udp: dest = %d, src = %d, len = %d " 9449 "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport), 9450 ntohs(uh->uh_sport), ntohs(uh->uh_ulen), 9451 ntohs(uh->uh_sum)); 9452 break; 9453 case IPPROTO_ICMP: 9454 BCE_PRINTF("icmp:\n"); 9455 break; 9456 default: 9457 BCE_PRINTF("----: Other IP protocol.\n"); 9458 } 9459 break; 9460 case ETHERTYPE_IPV6: 9461 BCE_PRINTF("ipv6: No decode supported.\n"); 9462 break; 9463 case ETHERTYPE_ARP: 9464 BCE_PRINTF("-arp: "); 9465 ah = (struct arphdr *) (m->m_data + ehlen); 9466 switch (ntohs(ah->ar_op)) { 9467 case ARPOP_REVREQUEST: 9468 printf("reverse ARP request\n"); 9469 break; 9470 case ARPOP_REVREPLY: 9471 printf("reverse ARP reply\n"); 9472 break; 9473 case ARPOP_REQUEST: 9474 printf("ARP request\n"); 9475 break; 9476 case ARPOP_REPLY: 9477 printf("ARP reply\n"); 9478 break; 9479 default: 9480 printf("other ARP operation\n"); 9481 } 9482 break; 9483 default: 9484 BCE_PRINTF("----: Other protocol.\n"); 9485 } 9486 9487 BCE_PRINTF( 9488 "-----------------------------" 9489 "--------------" 9490 "-----------------------------\n"); 9491 } 9492 9493 9494 /****************************************************************************/ 9495 /* Prints out information about an mbuf. */ 9496 /* */ 9497 /* Returns: */ 9498 /* Nothing. */ 9499 /****************************************************************************/ 9500 static __attribute__ ((noinline)) void 9501 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 9502 { 9503 struct mbuf *mp = m; 9504 9505 if (m == NULL) { 9506 BCE_PRINTF("mbuf: null pointer\n"); 9507 return; 9508 } 9509 9510 while (mp) { 9511 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, " 9512 "m_data = %p\n", mp, mp->m_len, mp->m_flags, 9513 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data); 9514 9515 if (mp->m_flags & M_PKTHDR) { 9516 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, " 9517 "csum_flags = %b\n", mp->m_pkthdr.len, 9518 mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG" 9519 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 9520 "\22M_PROMISC\23M_NOFREE", 9521 mp->m_pkthdr.csum_flags, 9522 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 9523 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 9524 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 9525 "\14CSUM_PSEUDO_HDR"); 9526 } 9527 9528 if (mp->m_flags & M_EXT) { 9529 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ", 9530 mp->m_ext.ext_buf, mp->m_ext.ext_size); 9531 switch (mp->m_ext.ext_type) { 9532 case EXT_CLUSTER: 9533 printf("EXT_CLUSTER\n"); break; 9534 case EXT_SFBUF: 9535 printf("EXT_SFBUF\n"); break; 9536 case EXT_JUMBO9: 9537 printf("EXT_JUMBO9\n"); break; 9538 case EXT_JUMBO16: 9539 printf("EXT_JUMBO16\n"); break; 9540 case EXT_PACKET: 9541 printf("EXT_PACKET\n"); break; 9542 case EXT_MBUF: 9543 printf("EXT_MBUF\n"); break; 9544 case EXT_NET_DRV: 9545 printf("EXT_NET_DRV\n"); break; 9546 case EXT_MOD_TYPE: 9547 printf("EXT_MDD_TYPE\n"); break; 9548 case EXT_DISPOSABLE: 9549 printf("EXT_DISPOSABLE\n"); break; 9550 case EXT_EXTREF: 9551 printf("EXT_EXTREF\n"); break; 9552 default: 9553 printf("UNKNOWN\n"); 9554 } 9555 } 9556 9557 mp = mp->m_next; 9558 } 9559 } 9560 9561 9562 /****************************************************************************/ 9563 /* Prints out the mbufs in the TX mbuf chain. */ 9564 /* */ 9565 /* Returns: */ 9566 /* Nothing. */ 9567 /****************************************************************************/ 9568 static __attribute__ ((noinline)) void 9569 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9570 { 9571 struct mbuf *m; 9572 9573 BCE_PRINTF( 9574 "----------------------------" 9575 " tx mbuf data " 9576 "----------------------------\n"); 9577 9578 for (int i = 0; i < count; i++) { 9579 m = sc->tx_mbuf_ptr[chain_prod]; 9580 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod); 9581 bce_dump_mbuf(sc, m); 9582 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 9583 } 9584 9585 BCE_PRINTF( 9586 "----------------------------" 9587 "----------------" 9588 "----------------------------\n"); 9589 } 9590 9591 9592 /****************************************************************************/ 9593 /* Prints out the mbufs in the RX mbuf chain. */ 9594 /* */ 9595 /* Returns: */ 9596 /* Nothing. */ 9597 /****************************************************************************/ 9598 static __attribute__ ((noinline)) void 9599 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9600 { 9601 struct mbuf *m; 9602 9603 BCE_PRINTF( 9604 "----------------------------" 9605 " rx mbuf data " 9606 "----------------------------\n"); 9607 9608 for (int i = 0; i < count; i++) { 9609 m = sc->rx_mbuf_ptr[chain_prod]; 9610 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 9611 bce_dump_mbuf(sc, m); 9612 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 9613 } 9614 9615 9616 BCE_PRINTF( 9617 "----------------------------" 9618 "----------------" 9619 "----------------------------\n"); 9620 } 9621 9622 9623 /****************************************************************************/ 9624 /* Prints out the mbufs in the mbuf page chain. */ 9625 /* */ 9626 /* Returns: */ 9627 /* Nothing. */ 9628 /****************************************************************************/ 9629 static __attribute__ ((noinline)) void 9630 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count) 9631 { 9632 struct mbuf *m; 9633 9634 BCE_PRINTF( 9635 "----------------------------" 9636 " pg mbuf data " 9637 "----------------------------\n"); 9638 9639 for (int i = 0; i < count; i++) { 9640 m = sc->pg_mbuf_ptr[chain_prod]; 9641 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod); 9642 bce_dump_mbuf(sc, m); 9643 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod)); 9644 } 9645 9646 9647 BCE_PRINTF( 9648 "----------------------------" 9649 "----------------" 9650 "----------------------------\n"); 9651 } 9652 9653 9654 /****************************************************************************/ 9655 /* Prints out a tx_bd structure. */ 9656 /* */ 9657 /* Returns: */ 9658 /* Nothing. */ 9659 /****************************************************************************/ 9660 static __attribute__ ((noinline)) void 9661 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 9662 { 9663 int i = 0; 9664 9665 if (idx > MAX_TX_BD_ALLOC) 9666 /* Index out of range. */ 9667 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 9668 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 9669 /* TX Chain page pointer. */ 9670 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9671 "pointer\n", idx, txbd->tx_bd_haddr_hi, 9672 txbd->tx_bd_haddr_lo); 9673 else { 9674 /* Normal tx_bd entry. */ 9675 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, " 9676 "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = " 9677 "0x%04X (", idx, txbd->tx_bd_haddr_hi, 9678 txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, 9679 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); 9680 9681 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) { 9682 if (i>0) 9683 printf("|"); 9684 printf("CONN_FAULT"); 9685 i++; 9686 } 9687 9688 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) { 9689 if (i>0) 9690 printf("|"); 9691 printf("TCP_UDP_CKSUM"); 9692 i++; 9693 } 9694 9695 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) { 9696 if (i>0) 9697 printf("|"); 9698 printf("IP_CKSUM"); 9699 i++; 9700 } 9701 9702 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) { 9703 if (i>0) 9704 printf("|"); 9705 printf("VLAN"); 9706 i++; 9707 } 9708 9709 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) { 9710 if (i>0) 9711 printf("|"); 9712 printf("COAL_NOW"); 9713 i++; 9714 } 9715 9716 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) { 9717 if (i>0) 9718 printf("|"); 9719 printf("DONT_GEN_CRC"); 9720 i++; 9721 } 9722 9723 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) { 9724 if (i>0) 9725 printf("|"); 9726 printf("START"); 9727 i++; 9728 } 9729 9730 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) { 9731 if (i>0) 9732 printf("|"); 9733 printf("END"); 9734 i++; 9735 } 9736 9737 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) { 9738 if (i>0) 9739 printf("|"); 9740 printf("LSO"); 9741 i++; 9742 } 9743 9744 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) { 9745 if (i>0) 9746 printf("|"); 9747 printf("SW_OPTION=%d", ((txbd->tx_bd_flags & 9748 TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++; 9749 } 9750 9751 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) { 9752 if (i>0) 9753 printf("|"); 9754 printf("SW_FLAGS"); 9755 i++; 9756 } 9757 9758 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) { 9759 if (i>0) 9760 printf("|"); 9761 printf("SNAP)"); 9762 } else { 9763 printf(")\n"); 9764 } 9765 } 9766 } 9767 9768 9769 /****************************************************************************/ 9770 /* Prints out a rx_bd structure. */ 9771 /* */ 9772 /* Returns: */ 9773 /* Nothing. */ 9774 /****************************************************************************/ 9775 static __attribute__ ((noinline)) void 9776 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 9777 { 9778 if (idx > MAX_RX_BD_ALLOC) 9779 /* Index out of range. */ 9780 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 9781 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 9782 /* RX Chain page pointer. */ 9783 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page " 9784 "pointer\n", idx, rxbd->rx_bd_haddr_hi, 9785 rxbd->rx_bd_haddr_lo); 9786 else 9787 /* Normal rx_bd entry. */ 9788 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " 9789 "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, 9790 rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, 9791 rxbd->rx_bd_flags); 9792 } 9793 9794 9795 /****************************************************************************/ 9796 /* Prints out a rx_bd structure in the page chain. */ 9797 /* */ 9798 /* Returns: */ 9799 /* Nothing. */ 9800 /****************************************************************************/ 9801 static __attribute__ ((noinline)) void 9802 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd) 9803 { 9804 if (idx > MAX_PG_BD_ALLOC) 9805 /* Index out of range. */ 9806 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx); 9807 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE) 9808 /* Page Chain page pointer. */ 9809 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 9810 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo); 9811 else 9812 /* Normal rx_bd entry. */ 9813 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 9814 "flags = 0x%08X\n", idx, 9815 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo, 9816 pgbd->rx_bd_len, pgbd->rx_bd_flags); 9817 } 9818 9819 9820 /****************************************************************************/ 9821 /* Prints out a l2_fhdr structure. */ 9822 /* */ 9823 /* Returns: */ 9824 /* Nothing. */ 9825 /****************************************************************************/ 9826 static __attribute__ ((noinline)) void 9827 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 9828 { 9829 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, " 9830 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, " 9831 "tcp_udp_xsum = 0x%04X\n", idx, 9832 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB, 9833 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag, 9834 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum); 9835 } 9836 9837 9838 /****************************************************************************/ 9839 /* Prints out context memory info. (Only useful for CID 0 to 16.) */ 9840 /* */ 9841 /* Returns: */ 9842 /* Nothing. */ 9843 /****************************************************************************/ 9844 static __attribute__ ((noinline)) void 9845 bce_dump_ctx(struct bce_softc *sc, u16 cid) 9846 { 9847 if (cid > TX_CID) { 9848 BCE_PRINTF(" Unknown CID\n"); 9849 return; 9850 } 9851 9852 BCE_PRINTF( 9853 "----------------------------" 9854 " CTX Data " 9855 "----------------------------\n"); 9856 9857 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid); 9858 9859 if (cid == RX_CID) { 9860 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx " 9861 "producer index\n", 9862 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX)); 9863 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host " 9864 "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9865 BCE_L2CTX_RX_HOST_BSEQ)); 9866 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n", 9867 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ)); 9868 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer " 9869 "descriptor address\n", 9870 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI)); 9871 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer " 9872 "descriptor address\n", 9873 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO)); 9874 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer " 9875 "index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9876 BCE_L2CTX_RX_NX_BDIDX)); 9877 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page " 9878 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9879 BCE_L2CTX_RX_HOST_PG_BDIDX)); 9880 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page " 9881 "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid), 9882 BCE_L2CTX_RX_PG_BUF_SIZE)); 9883 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page " 9884 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9885 BCE_L2CTX_RX_NX_PG_BDHADDR_HI)); 9886 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page " 9887 "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid), 9888 BCE_L2CTX_RX_NX_PG_BDHADDR_LO)); 9889 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page " 9890 "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9891 BCE_L2CTX_RX_NX_PG_BDIDX)); 9892 } else if (cid == TX_CID) { 9893 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 9894 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n", 9895 CTX_RD(sc, GET_CID_ADDR(cid), 9896 BCE_L2CTX_TX_TYPE_XI)); 9897 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx " 9898 "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid), 9899 BCE_L2CTX_TX_CMD_TYPE_XI)); 9900 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) " 9901 "h/w buffer descriptor address\n", 9902 CTX_RD(sc, GET_CID_ADDR(cid), 9903 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI)); 9904 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) " 9905 "h/w buffer descriptor address\n", 9906 CTX_RD(sc, GET_CID_ADDR(cid), 9907 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI)); 9908 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) " 9909 "host producer index\n", 9910 CTX_RD(sc, GET_CID_ADDR(cid), 9911 BCE_L2CTX_TX_HOST_BIDX_XI)); 9912 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) " 9913 "host byte sequence\n", 9914 CTX_RD(sc, GET_CID_ADDR(cid), 9915 BCE_L2CTX_TX_HOST_BSEQ_XI)); 9916 } else { 9917 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n", 9918 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE)); 9919 BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n", 9920 CTX_RD(sc, GET_CID_ADDR(cid), 9921 BCE_L2CTX_TX_CMD_TYPE)); 9922 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) " 9923 "h/w buffer descriptor address\n", 9924 CTX_RD(sc, GET_CID_ADDR(cid), 9925 BCE_L2CTX_TX_TBDR_BHADDR_HI)); 9926 BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) " 9927 "h/w buffer descriptor address\n", 9928 CTX_RD(sc, GET_CID_ADDR(cid), 9929 BCE_L2CTX_TX_TBDR_BHADDR_LO)); 9930 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host " 9931 "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid), 9932 BCE_L2CTX_TX_HOST_BIDX)); 9933 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte " 9934 "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid), 9935 BCE_L2CTX_TX_HOST_BSEQ)); 9936 } 9937 } 9938 9939 BCE_PRINTF( 9940 "----------------------------" 9941 " Raw CTX " 9942 "----------------------------\n"); 9943 9944 for (int i = 0x0; i < 0x300; i += 0x10) { 9945 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i, 9946 CTX_RD(sc, GET_CID_ADDR(cid), i), 9947 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4), 9948 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8), 9949 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc)); 9950 } 9951 9952 9953 BCE_PRINTF( 9954 "----------------------------" 9955 "----------------" 9956 "----------------------------\n"); 9957 } 9958 9959 9960 /****************************************************************************/ 9961 /* Prints out the FTQ data. */ 9962 /* */ 9963 /* Returns: */ 9964 /* Nothing. */ 9965 /****************************************************************************/ 9966 static __attribute__ ((noinline)) void 9967 bce_dump_ftqs(struct bce_softc *sc) 9968 { 9969 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val; 9970 9971 BCE_PRINTF( 9972 "----------------------------" 9973 " FTQ Data " 9974 "----------------------------\n"); 9975 9976 BCE_PRINTF(" FTQ Command Control Depth_Now " 9977 "Max_Depth Valid_Cnt \n"); 9978 BCE_PRINTF(" ------- ---------- ---------- ---------- " 9979 "---------- ----------\n"); 9980 9981 /* Setup the generic statistic counters for the FTQ valid count. */ 9982 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) | 9983 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) | 9984 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) | 9985 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT); 9986 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 9987 9988 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) | 9989 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) | 9990 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) | 9991 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT); 9992 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val); 9993 9994 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) | 9995 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) | 9996 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) | 9997 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT); 9998 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val); 9999 10000 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) | 10001 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) | 10002 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) | 10003 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT); 10004 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val); 10005 10006 /* Input queue to the Receive Lookup state machine */ 10007 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD); 10008 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL); 10009 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22; 10010 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12; 10011 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10012 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10013 cmd, ctl, cur_depth, max_depth, valid_cnt); 10014 10015 /* Input queue to the Receive Processor */ 10016 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD); 10017 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL); 10018 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22; 10019 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12; 10020 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10021 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10022 cmd, ctl, cur_depth, max_depth, valid_cnt); 10023 10024 /* Input queue to the Recevie Processor */ 10025 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD); 10026 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL); 10027 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22; 10028 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12; 10029 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10030 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10031 cmd, ctl, cur_depth, max_depth, valid_cnt); 10032 10033 /* Input queue to the Receive Virtual to Physical state machine */ 10034 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD); 10035 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL); 10036 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22; 10037 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12; 10038 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10039 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10040 cmd, ctl, cur_depth, max_depth, valid_cnt); 10041 10042 /* Input queue to the Recevie Virtual to Physical state machine */ 10043 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD); 10044 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL); 10045 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22; 10046 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12; 10047 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4); 10048 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10049 cmd, ctl, cur_depth, max_depth, valid_cnt); 10050 10051 /* Input queue to the Receive Virtual to Physical state machine */ 10052 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD); 10053 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL); 10054 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22; 10055 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12; 10056 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5); 10057 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10058 cmd, ctl, cur_depth, max_depth, valid_cnt); 10059 10060 /* Input queue to the Receive DMA state machine */ 10061 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD); 10062 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL); 10063 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10064 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10065 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6); 10066 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10067 cmd, ctl, cur_depth, max_depth, valid_cnt); 10068 10069 /* Input queue to the Transmit Scheduler state machine */ 10070 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD); 10071 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL); 10072 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22; 10073 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12; 10074 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7); 10075 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10076 cmd, ctl, cur_depth, max_depth, valid_cnt); 10077 10078 /* Input queue to the Transmit Buffer Descriptor state machine */ 10079 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD); 10080 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL); 10081 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22; 10082 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12; 10083 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8); 10084 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10085 cmd, ctl, cur_depth, max_depth, valid_cnt); 10086 10087 /* Input queue to the Transmit Processor */ 10088 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD); 10089 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL); 10090 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22; 10091 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12; 10092 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9); 10093 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10094 cmd, ctl, cur_depth, max_depth, valid_cnt); 10095 10096 /* Input queue to the Transmit DMA state machine */ 10097 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD); 10098 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL); 10099 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22; 10100 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12; 10101 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10); 10102 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10103 cmd, ctl, cur_depth, max_depth, valid_cnt); 10104 10105 /* Input queue to the Transmit Patch-Up Processor */ 10106 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD); 10107 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL); 10108 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22; 10109 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12; 10110 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11); 10111 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10112 cmd, ctl, cur_depth, max_depth, valid_cnt); 10113 10114 /* Input queue to the Transmit Assembler state machine */ 10115 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD); 10116 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL); 10117 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22; 10118 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12; 10119 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12); 10120 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10121 cmd, ctl, cur_depth, max_depth, valid_cnt); 10122 10123 /* Input queue to the Completion Processor */ 10124 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD); 10125 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL); 10126 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22; 10127 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12; 10128 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13); 10129 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10130 cmd, ctl, cur_depth, max_depth, valid_cnt); 10131 10132 /* Input queue to the Completion Processor */ 10133 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD); 10134 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL); 10135 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22; 10136 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12; 10137 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14); 10138 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10139 cmd, ctl, cur_depth, max_depth, valid_cnt); 10140 10141 /* Input queue to the Completion Processor */ 10142 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD); 10143 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL); 10144 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22; 10145 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12; 10146 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15); 10147 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10148 cmd, ctl, cur_depth, max_depth, valid_cnt); 10149 10150 /* Setup the generic statistic counters for the FTQ valid count. */ 10151 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) | 10152 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) | 10153 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT); 10154 10155 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) 10156 val = val | 10157 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 10158 24); 10159 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val); 10160 10161 /* Input queue to the Management Control Processor */ 10162 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD); 10163 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL); 10164 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10165 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10166 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0); 10167 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10168 cmd, ctl, cur_depth, max_depth, valid_cnt); 10169 10170 /* Input queue to the Command Processor */ 10171 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD); 10172 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL); 10173 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22; 10174 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12; 10175 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1); 10176 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10177 cmd, ctl, cur_depth, max_depth, valid_cnt); 10178 10179 /* Input queue to the Completion Scheduler state machine */ 10180 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD); 10181 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL); 10182 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22; 10183 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12; 10184 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2); 10185 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10186 cmd, ctl, cur_depth, max_depth, valid_cnt); 10187 10188 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) { 10189 /* Input queue to the RV2P Command Scheduler */ 10190 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD); 10191 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL); 10192 cur_depth = (ctl & 0xFFC00000) >> 22; 10193 max_depth = (ctl & 0x003FF000) >> 12; 10194 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3); 10195 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", 10196 cmd, ctl, cur_depth, max_depth, valid_cnt); 10197 } 10198 10199 BCE_PRINTF( 10200 "----------------------------" 10201 "----------------" 10202 "----------------------------\n"); 10203 } 10204 10205 10206 /****************************************************************************/ 10207 /* Prints out the TX chain. */ 10208 /* */ 10209 /* Returns: */ 10210 /* Nothing. */ 10211 /****************************************************************************/ 10212 static __attribute__ ((noinline)) void 10213 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count) 10214 { 10215 struct tx_bd *txbd; 10216 10217 /* First some info about the tx_bd chain structure. */ 10218 BCE_PRINTF( 10219 "----------------------------" 10220 " tx_bd chain " 10221 "----------------------------\n"); 10222 10223 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 10224 (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages); 10225 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 10226 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 10227 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC); 10228 10229 BCE_PRINTF( 10230 "----------------------------" 10231 " tx_bd data " 10232 "----------------------------\n"); 10233 10234 /* Now print out a decoded list of TX buffer descriptors. */ 10235 for (int i = 0; i < count; i++) { 10236 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 10237 bce_dump_txbd(sc, tx_prod, txbd); 10238 tx_prod++; 10239 } 10240 10241 BCE_PRINTF( 10242 "----------------------------" 10243 "----------------" 10244 "----------------------------\n"); 10245 } 10246 10247 10248 /****************************************************************************/ 10249 /* Prints out the RX chain. */ 10250 /* */ 10251 /* Returns: */ 10252 /* Nothing. */ 10253 /****************************************************************************/ 10254 static __attribute__ ((noinline)) void 10255 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count) 10256 { 10257 struct rx_bd *rxbd; 10258 10259 /* First some info about the rx_bd chain structure. */ 10260 BCE_PRINTF( 10261 "----------------------------" 10262 " rx_bd chain " 10263 "----------------------------\n"); 10264 10265 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 10266 (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages); 10267 10268 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10269 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 10270 10271 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC); 10272 10273 BCE_PRINTF( 10274 "----------------------------" 10275 " rx_bd data " 10276 "----------------------------\n"); 10277 10278 /* Now print out the rx_bd's themselves. */ 10279 for (int i = 0; i < count; i++) { 10280 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 10281 bce_dump_rxbd(sc, rx_prod, rxbd); 10282 rx_prod = RX_CHAIN_IDX(rx_prod + 1); 10283 } 10284 10285 BCE_PRINTF( 10286 "----------------------------" 10287 "----------------" 10288 "----------------------------\n"); 10289 } 10290 10291 10292 /****************************************************************************/ 10293 /* Prints out the page chain. */ 10294 /* */ 10295 /* Returns: */ 10296 /* Nothing. */ 10297 /****************************************************************************/ 10298 static __attribute__ ((noinline)) void 10299 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count) 10300 { 10301 struct rx_bd *pgbd; 10302 10303 /* First some info about the page chain structure. */ 10304 BCE_PRINTF( 10305 "----------------------------" 10306 " page chain " 10307 "----------------------------\n"); 10308 10309 BCE_PRINTF("page size = 0x%08X, pg chain pages = 0x%08X\n", 10310 (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages); 10311 10312 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 10313 (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE); 10314 10315 BCE_PRINTF("total pg_bd = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC); 10316 10317 BCE_PRINTF( 10318 "----------------------------" 10319 " page data " 10320 "----------------------------\n"); 10321 10322 /* Now print out the rx_bd's themselves. */ 10323 for (int i = 0; i < count; i++) { 10324 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)]; 10325 bce_dump_pgbd(sc, pg_prod, pgbd); 10326 pg_prod = PG_CHAIN_IDX(pg_prod + 1); 10327 } 10328 10329 BCE_PRINTF( 10330 "----------------------------" 10331 "----------------" 10332 "----------------------------\n"); 10333 } 10334 10335 10336 #define BCE_PRINT_RX_CONS(arg) \ 10337 if (sblk->status_rx_quick_consumer_index##arg) \ 10338 BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n", \ 10339 sblk->status_rx_quick_consumer_index##arg, (u16) \ 10340 RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg), \ 10341 arg); 10342 10343 10344 #define BCE_PRINT_TX_CONS(arg) \ 10345 if (sblk->status_tx_quick_consumer_index##arg) \ 10346 BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n", \ 10347 sblk->status_tx_quick_consumer_index##arg, (u16) \ 10348 TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg), \ 10349 arg); 10350 10351 /****************************************************************************/ 10352 /* Prints out the status block from host memory. */ 10353 /* */ 10354 /* Returns: */ 10355 /* Nothing. */ 10356 /****************************************************************************/ 10357 static __attribute__ ((noinline)) void 10358 bce_dump_status_block(struct bce_softc *sc) 10359 { 10360 struct status_block *sblk; 10361 10362 sblk = sc->status_block; 10363 10364 BCE_PRINTF( 10365 "----------------------------" 10366 " Status Block " 10367 "----------------------------\n"); 10368 10369 /* Theses indices are used for normal L2 drivers. */ 10370 BCE_PRINTF(" 0x%08X - attn_bits\n", 10371 sblk->status_attn_bits); 10372 10373 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 10374 sblk->status_attn_bits_ack); 10375 10376 BCE_PRINT_RX_CONS(0); 10377 BCE_PRINT_TX_CONS(0) 10378 10379 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 10380 10381 /* Theses indices are not used for normal L2 drivers. */ 10382 BCE_PRINT_RX_CONS(1); BCE_PRINT_RX_CONS(2); BCE_PRINT_RX_CONS(3); 10383 BCE_PRINT_RX_CONS(4); BCE_PRINT_RX_CONS(5); BCE_PRINT_RX_CONS(6); 10384 BCE_PRINT_RX_CONS(7); BCE_PRINT_RX_CONS(8); BCE_PRINT_RX_CONS(9); 10385 BCE_PRINT_RX_CONS(10); BCE_PRINT_RX_CONS(11); BCE_PRINT_RX_CONS(12); 10386 BCE_PRINT_RX_CONS(13); BCE_PRINT_RX_CONS(14); BCE_PRINT_RX_CONS(15); 10387 10388 BCE_PRINT_TX_CONS(1); BCE_PRINT_TX_CONS(2); BCE_PRINT_TX_CONS(3); 10389 10390 if (sblk->status_completion_producer_index || 10391 sblk->status_cmd_consumer_index) 10392 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 10393 sblk->status_completion_producer_index, 10394 sblk->status_cmd_consumer_index); 10395 10396 BCE_PRINTF( 10397 "----------------------------" 10398 "----------------" 10399 "----------------------------\n"); 10400 } 10401 10402 10403 #define BCE_PRINT_64BIT_STAT(arg) \ 10404 if (sblk->arg##_lo || sblk->arg##_hi) \ 10405 BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi, \ 10406 sblk->arg##_lo, #arg); 10407 10408 #define BCE_PRINT_32BIT_STAT(arg) \ 10409 if (sblk->arg) \ 10410 BCE_PRINTF(" 0x%08X : %s\n", \ 10411 sblk->arg, #arg); 10412 10413 /****************************************************************************/ 10414 /* Prints out the statistics block from host memory. */ 10415 /* */ 10416 /* Returns: */ 10417 /* Nothing. */ 10418 /****************************************************************************/ 10419 static __attribute__ ((noinline)) void 10420 bce_dump_stats_block(struct bce_softc *sc) 10421 { 10422 struct statistics_block *sblk; 10423 10424 sblk = sc->stats_block; 10425 10426 BCE_PRINTF( 10427 "---------------" 10428 " Stats Block (All Stats Not Shown Are 0) " 10429 "---------------\n"); 10430 10431 BCE_PRINT_64BIT_STAT(stat_IfHCInOctets); 10432 BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets); 10433 BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets); 10434 BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets); 10435 BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts); 10436 BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts); 10437 BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts); 10438 BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts); 10439 BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts); 10440 BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts); 10441 BCE_PRINT_32BIT_STAT( 10442 stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 10443 BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors); 10444 BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors); 10445 BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors); 10446 BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames); 10447 BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames); 10448 BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions); 10449 BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions); 10450 BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions); 10451 BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions); 10452 BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments); 10453 BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers); 10454 BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts); 10455 BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts); 10456 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets); 10457 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets); 10458 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets); 10459 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets); 10460 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets); 10461 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets); 10462 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets); 10463 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets); 10464 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets); 10465 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets); 10466 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets); 10467 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets); 10468 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets); 10469 BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets); 10470 BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived); 10471 BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived); 10472 BCE_PRINT_32BIT_STAT(stat_OutXonSent); 10473 BCE_PRINT_32BIT_STAT(stat_OutXoffSent); 10474 BCE_PRINT_32BIT_STAT(stat_FlowControlDone); 10475 BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived); 10476 BCE_PRINT_32BIT_STAT(stat_XoffStateEntered); 10477 BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards); 10478 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards); 10479 BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards); 10480 BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards); 10481 BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit); 10482 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards); 10483 BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards); 10484 BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards); 10485 BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit); 10486 10487 BCE_PRINTF( 10488 "----------------------------" 10489 "----------------" 10490 "----------------------------\n"); 10491 } 10492 10493 10494 /****************************************************************************/ 10495 /* Prints out a summary of the driver state. */ 10496 /* */ 10497 /* Returns: */ 10498 /* Nothing. */ 10499 /****************************************************************************/ 10500 static __attribute__ ((noinline)) void 10501 bce_dump_driver_state(struct bce_softc *sc) 10502 { 10503 u32 val_hi, val_lo; 10504 10505 BCE_PRINTF( 10506 "-----------------------------" 10507 " Driver State " 10508 "-----------------------------\n"); 10509 10510 val_hi = BCE_ADDR_HI(sc); 10511 val_lo = BCE_ADDR_LO(sc); 10512 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual " 10513 "address\n", val_hi, val_lo); 10514 10515 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 10516 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 10517 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual " 10518 "address\n", val_hi, val_lo); 10519 10520 val_hi = BCE_ADDR_HI(sc->status_block); 10521 val_lo = BCE_ADDR_LO(sc->status_block); 10522 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block " 10523 "virtual address\n", val_hi, val_lo); 10524 10525 val_hi = BCE_ADDR_HI(sc->stats_block); 10526 val_lo = BCE_ADDR_LO(sc->stats_block); 10527 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block " 10528 "virtual address\n", val_hi, val_lo); 10529 10530 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 10531 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 10532 BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain " 10533 "virtual adddress\n", val_hi, val_lo); 10534 10535 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 10536 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 10537 BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain " 10538 "virtual address\n", val_hi, val_lo); 10539 10540 if (bce_hdr_split == TRUE) { 10541 val_hi = BCE_ADDR_HI(sc->pg_bd_chain); 10542 val_lo = BCE_ADDR_LO(sc->pg_bd_chain); 10543 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain " 10544 "virtual address\n", val_hi, val_lo); 10545 } 10546 10547 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 10548 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 10549 BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain " 10550 "virtual address\n", val_hi, val_lo); 10551 10552 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 10553 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 10554 BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain " 10555 "virtual address\n", val_hi, val_lo); 10556 10557 if (bce_hdr_split == TRUE) { 10558 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr); 10559 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr); 10560 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain " 10561 "virtual address\n", val_hi, val_lo); 10562 } 10563 10564 BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) " 10565 "h/w intrs\n", 10566 (long long unsigned int) sc->interrupts_generated); 10567 10568 BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) " 10569 "rx interrupts handled\n", 10570 (long long unsigned int) sc->interrupts_rx); 10571 10572 BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) " 10573 "tx interrupts handled\n", 10574 (long long unsigned int) sc->interrupts_tx); 10575 10576 BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) " 10577 "phy interrupts handled\n", 10578 (long long unsigned int) sc->phy_interrupts); 10579 10580 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) " 10581 "status block index\n", sc->last_status_idx); 10582 10583 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer " 10584 "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 10585 10586 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer " 10587 "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 10588 10589 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer " 10590 "byte seq index\n", sc->tx_prod_bseq); 10591 10592 BCE_PRINTF(" 0x%08X - (sc->debug_tx_mbuf_alloc) tx " 10593 "mbufs allocated\n", sc->debug_tx_mbuf_alloc); 10594 10595 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used " 10596 "tx_bd's\n", sc->used_tx_bd); 10597 10598 BCE_PRINTF(" 0x%04X/0x%04X - (sc->tx_hi_watermark)/" 10599 "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd); 10600 10601 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer " 10602 "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 10603 10604 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer " 10605 "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 10606 10607 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer " 10608 "byte seq index\n", sc->rx_prod_bseq); 10609 10610 BCE_PRINTF(" 0x%04X/0x%04X - (sc->rx_low_watermark)/" 10611 "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd); 10612 10613 BCE_PRINTF(" 0x%08X - (sc->debug_rx_mbuf_alloc) rx " 10614 "mbufs allocated\n", sc->debug_rx_mbuf_alloc); 10615 10616 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free " 10617 "rx_bd's\n", sc->free_rx_bd); 10618 10619 if (bce_hdr_split == TRUE) { 10620 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_prod) page producer " 10621 "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod)); 10622 10623 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->pg_cons) page consumer " 10624 "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons)); 10625 10626 BCE_PRINTF(" 0x%08X - (sc->debug_pg_mbuf_alloc) page " 10627 "mbufs allocated\n", sc->debug_pg_mbuf_alloc); 10628 } 10629 10630 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page " 10631 "rx_bd's\n", sc->free_pg_bd); 10632 10633 BCE_PRINTF(" 0x%04X/0x%04X - (sc->pg_low_watermark)/" 10634 "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd); 10635 10636 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) " 10637 "mbuf alloc failures\n", sc->mbuf_alloc_failed_count); 10638 10639 BCE_PRINTF(" 0x%08X - (sc->bce_flags) " 10640 "bce mac flags\n", sc->bce_flags); 10641 10642 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) " 10643 "bce phy flags\n", sc->bce_phy_flags); 10644 10645 BCE_PRINTF( 10646 "----------------------------" 10647 "----------------" 10648 "----------------------------\n"); 10649 } 10650 10651 10652 /****************************************************************************/ 10653 /* Prints out the hardware state through a summary of important register, */ 10654 /* followed by a complete register dump. */ 10655 /* */ 10656 /* Returns: */ 10657 /* Nothing. */ 10658 /****************************************************************************/ 10659 static __attribute__ ((noinline)) void 10660 bce_dump_hw_state(struct bce_softc *sc) 10661 { 10662 u32 val; 10663 10664 BCE_PRINTF( 10665 "----------------------------" 10666 " Hardware State " 10667 "----------------------------\n"); 10668 10669 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10670 10671 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 10672 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 10673 val, BCE_MISC_ENABLE_STATUS_BITS); 10674 10675 val = REG_RD(sc, BCE_DMA_STATUS); 10676 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", 10677 val, BCE_DMA_STATUS); 10678 10679 val = REG_RD(sc, BCE_CTX_STATUS); 10680 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", 10681 val, BCE_CTX_STATUS); 10682 10683 val = REG_RD(sc, BCE_EMAC_STATUS); 10684 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", 10685 val, BCE_EMAC_STATUS); 10686 10687 val = REG_RD(sc, BCE_RPM_STATUS); 10688 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", 10689 val, BCE_RPM_STATUS); 10690 10691 /* ToDo: Create a #define for this constant. */ 10692 val = REG_RD(sc, 0x2004); 10693 BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n", 10694 val, 0x2004); 10695 10696 val = REG_RD(sc, BCE_RV2P_STATUS); 10697 BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n", 10698 val, BCE_RV2P_STATUS); 10699 10700 /* ToDo: Create a #define for this constant. */ 10701 val = REG_RD(sc, 0x2c04); 10702 BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n", 10703 val, 0x2c04); 10704 10705 val = REG_RD(sc, BCE_TBDR_STATUS); 10706 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", 10707 val, BCE_TBDR_STATUS); 10708 10709 val = REG_RD(sc, BCE_TDMA_STATUS); 10710 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", 10711 val, BCE_TDMA_STATUS); 10712 10713 val = REG_RD(sc, BCE_HC_STATUS); 10714 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", 10715 val, BCE_HC_STATUS); 10716 10717 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10718 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10719 val, BCE_TXP_CPU_STATE); 10720 10721 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 10722 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 10723 val, BCE_TPAT_CPU_STATE); 10724 10725 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10726 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10727 val, BCE_RXP_CPU_STATE); 10728 10729 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 10730 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 10731 val, BCE_COM_CPU_STATE); 10732 10733 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 10734 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", 10735 val, BCE_MCP_CPU_STATE); 10736 10737 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 10738 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 10739 val, BCE_CP_CPU_STATE); 10740 10741 BCE_PRINTF( 10742 "----------------------------" 10743 "----------------" 10744 "----------------------------\n"); 10745 10746 BCE_PRINTF( 10747 "----------------------------" 10748 " Register Dump " 10749 "----------------------------\n"); 10750 10751 for (int i = 0x400; i < 0x8000; i += 0x10) { 10752 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10753 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10754 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10755 } 10756 10757 BCE_PRINTF( 10758 "----------------------------" 10759 "----------------" 10760 "----------------------------\n"); 10761 } 10762 10763 10764 /****************************************************************************/ 10765 /* Prints out the contentst of shared memory which is used for host driver */ 10766 /* to bootcode firmware communication. */ 10767 /* */ 10768 /* Returns: */ 10769 /* Nothing. */ 10770 /****************************************************************************/ 10771 static __attribute__ ((noinline)) void 10772 bce_dump_shmem_state(struct bce_softc *sc) 10773 { 10774 BCE_PRINTF( 10775 "----------------------------" 10776 " Hardware State " 10777 "----------------------------\n"); 10778 10779 BCE_PRINTF("0x%08X - Shared memory base address\n", 10780 sc->bce_shmem_base); 10781 BCE_PRINTF("%s - bootcode version\n", 10782 sc->bce_bc_ver); 10783 10784 BCE_PRINTF( 10785 "----------------------------" 10786 " Shared Mem " 10787 "----------------------------\n"); 10788 10789 for (int i = 0x0; i < 0x200; i += 0x10) { 10790 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10791 i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4), 10792 bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC)); 10793 } 10794 10795 BCE_PRINTF( 10796 "----------------------------" 10797 "----------------" 10798 "----------------------------\n"); 10799 } 10800 10801 10802 /****************************************************************************/ 10803 /* Prints out the mailbox queue registers. */ 10804 /* */ 10805 /* Returns: */ 10806 /* Nothing. */ 10807 /****************************************************************************/ 10808 static __attribute__ ((noinline)) void 10809 bce_dump_mq_regs(struct bce_softc *sc) 10810 { 10811 BCE_PRINTF( 10812 "----------------------------" 10813 " MQ Regs " 10814 "----------------------------\n"); 10815 10816 BCE_PRINTF( 10817 "----------------------------" 10818 "----------------" 10819 "----------------------------\n"); 10820 10821 for (int i = 0x3c00; i < 0x4000; i += 0x10) { 10822 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 10823 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 10824 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 10825 } 10826 10827 BCE_PRINTF( 10828 "----------------------------" 10829 "----------------" 10830 "----------------------------\n"); 10831 } 10832 10833 10834 /****************************************************************************/ 10835 /* Prints out the bootcode state. */ 10836 /* */ 10837 /* Returns: */ 10838 /* Nothing. */ 10839 /****************************************************************************/ 10840 static __attribute__ ((noinline)) void 10841 bce_dump_bc_state(struct bce_softc *sc) 10842 { 10843 u32 val; 10844 10845 BCE_PRINTF( 10846 "----------------------------" 10847 " Bootcode State " 10848 "----------------------------\n"); 10849 10850 BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver); 10851 10852 val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE); 10853 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 10854 val, BCE_BC_RESET_TYPE); 10855 10856 val = bce_shmem_rd(sc, BCE_BC_STATE); 10857 BCE_PRINTF("0x%08X - (0x%06X) state\n", 10858 val, BCE_BC_STATE); 10859 10860 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION); 10861 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 10862 val, BCE_BC_STATE_CONDITION); 10863 10864 val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD); 10865 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 10866 val, BCE_BC_STATE_DEBUG_CMD); 10867 10868 BCE_PRINTF( 10869 "----------------------------" 10870 "----------------" 10871 "----------------------------\n"); 10872 } 10873 10874 10875 /****************************************************************************/ 10876 /* Prints out the TXP processor state. */ 10877 /* */ 10878 /* Returns: */ 10879 /* Nothing. */ 10880 /****************************************************************************/ 10881 static __attribute__ ((noinline)) void 10882 bce_dump_txp_state(struct bce_softc *sc, int regs) 10883 { 10884 u32 val; 10885 u32 fw_version[3]; 10886 10887 BCE_PRINTF( 10888 "----------------------------" 10889 " TXP State " 10890 "----------------------------\n"); 10891 10892 for (int i = 0; i < 3; i++) 10893 fw_version[i] = htonl(REG_RD_IND(sc, 10894 (BCE_TXP_SCRATCH + 0x10 + i * 4))); 10895 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10896 10897 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 10898 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", 10899 val, BCE_TXP_CPU_MODE); 10900 10901 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 10902 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", 10903 val, BCE_TXP_CPU_STATE); 10904 10905 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 10906 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", 10907 val, BCE_TXP_CPU_EVENT_MASK); 10908 10909 if (regs) { 10910 BCE_PRINTF( 10911 "----------------------------" 10912 " Register Dump " 10913 "----------------------------\n"); 10914 10915 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 10916 /* Skip the big blank spaces */ 10917 if (i < 0x454000 && i > 0x5ffff) 10918 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10919 "0x%08X 0x%08X\n", i, 10920 REG_RD_IND(sc, i), 10921 REG_RD_IND(sc, i + 0x4), 10922 REG_RD_IND(sc, i + 0x8), 10923 REG_RD_IND(sc, i + 0xC)); 10924 } 10925 } 10926 10927 BCE_PRINTF( 10928 "----------------------------" 10929 "----------------" 10930 "----------------------------\n"); 10931 } 10932 10933 10934 /****************************************************************************/ 10935 /* Prints out the RXP processor state. */ 10936 /* */ 10937 /* Returns: */ 10938 /* Nothing. */ 10939 /****************************************************************************/ 10940 static __attribute__ ((noinline)) void 10941 bce_dump_rxp_state(struct bce_softc *sc, int regs) 10942 { 10943 u32 val; 10944 u32 fw_version[3]; 10945 10946 BCE_PRINTF( 10947 "----------------------------" 10948 " RXP State " 10949 "----------------------------\n"); 10950 10951 for (int i = 0; i < 3; i++) 10952 fw_version[i] = htonl(REG_RD_IND(sc, 10953 (BCE_RXP_SCRATCH + 0x10 + i * 4))); 10954 10955 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 10956 10957 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 10958 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", 10959 val, BCE_RXP_CPU_MODE); 10960 10961 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 10962 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", 10963 val, BCE_RXP_CPU_STATE); 10964 10965 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 10966 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", 10967 val, BCE_RXP_CPU_EVENT_MASK); 10968 10969 if (regs) { 10970 BCE_PRINTF( 10971 "----------------------------" 10972 " Register Dump " 10973 "----------------------------\n"); 10974 10975 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 10976 /* Skip the big blank sapces */ 10977 if (i < 0xc5400 && i > 0xdffff) 10978 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 10979 "0x%08X 0x%08X\n", i, 10980 REG_RD_IND(sc, i), 10981 REG_RD_IND(sc, i + 0x4), 10982 REG_RD_IND(sc, i + 0x8), 10983 REG_RD_IND(sc, i + 0xC)); 10984 } 10985 } 10986 10987 BCE_PRINTF( 10988 "----------------------------" 10989 "----------------" 10990 "----------------------------\n"); 10991 } 10992 10993 10994 /****************************************************************************/ 10995 /* Prints out the TPAT processor state. */ 10996 /* */ 10997 /* Returns: */ 10998 /* Nothing. */ 10999 /****************************************************************************/ 11000 static __attribute__ ((noinline)) void 11001 bce_dump_tpat_state(struct bce_softc *sc, int regs) 11002 { 11003 u32 val; 11004 u32 fw_version[3]; 11005 11006 BCE_PRINTF( 11007 "----------------------------" 11008 " TPAT State " 11009 "----------------------------\n"); 11010 11011 for (int i = 0; i < 3; i++) 11012 fw_version[i] = htonl(REG_RD_IND(sc, 11013 (BCE_TPAT_SCRATCH + 0x410 + i * 4))); 11014 11015 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11016 11017 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 11018 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", 11019 val, BCE_TPAT_CPU_MODE); 11020 11021 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 11022 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", 11023 val, BCE_TPAT_CPU_STATE); 11024 11025 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 11026 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", 11027 val, BCE_TPAT_CPU_EVENT_MASK); 11028 11029 if (regs) { 11030 BCE_PRINTF( 11031 "----------------------------" 11032 " Register Dump " 11033 "----------------------------\n"); 11034 11035 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 11036 /* Skip the big blank spaces */ 11037 if (i < 0x854000 && i > 0x9ffff) 11038 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11039 "0x%08X 0x%08X\n", i, 11040 REG_RD_IND(sc, i), 11041 REG_RD_IND(sc, i + 0x4), 11042 REG_RD_IND(sc, i + 0x8), 11043 REG_RD_IND(sc, i + 0xC)); 11044 } 11045 } 11046 11047 BCE_PRINTF( 11048 "----------------------------" 11049 "----------------" 11050 "----------------------------\n"); 11051 } 11052 11053 11054 /****************************************************************************/ 11055 /* Prints out the Command Procesor (CP) state. */ 11056 /* */ 11057 /* Returns: */ 11058 /* Nothing. */ 11059 /****************************************************************************/ 11060 static __attribute__ ((noinline)) void 11061 bce_dump_cp_state(struct bce_softc *sc, int regs) 11062 { 11063 u32 val; 11064 u32 fw_version[3]; 11065 11066 BCE_PRINTF( 11067 "----------------------------" 11068 " CP State " 11069 "----------------------------\n"); 11070 11071 for (int i = 0; i < 3; i++) 11072 fw_version[i] = htonl(REG_RD_IND(sc, 11073 (BCE_CP_SCRATCH + 0x10 + i * 4))); 11074 11075 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11076 11077 val = REG_RD_IND(sc, BCE_CP_CPU_MODE); 11078 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", 11079 val, BCE_CP_CPU_MODE); 11080 11081 val = REG_RD_IND(sc, BCE_CP_CPU_STATE); 11082 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", 11083 val, BCE_CP_CPU_STATE); 11084 11085 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK); 11086 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val, 11087 BCE_CP_CPU_EVENT_MASK); 11088 11089 if (regs) { 11090 BCE_PRINTF( 11091 "----------------------------" 11092 " Register Dump " 11093 "----------------------------\n"); 11094 11095 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) { 11096 /* Skip the big blank spaces */ 11097 if (i < 0x185400 && i > 0x19ffff) 11098 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11099 "0x%08X 0x%08X\n", i, 11100 REG_RD_IND(sc, i), 11101 REG_RD_IND(sc, i + 0x4), 11102 REG_RD_IND(sc, i + 0x8), 11103 REG_RD_IND(sc, i + 0xC)); 11104 } 11105 } 11106 11107 BCE_PRINTF( 11108 "----------------------------" 11109 "----------------" 11110 "----------------------------\n"); 11111 } 11112 11113 11114 /****************************************************************************/ 11115 /* Prints out the Completion Procesor (COM) state. */ 11116 /* */ 11117 /* Returns: */ 11118 /* Nothing. */ 11119 /****************************************************************************/ 11120 static __attribute__ ((noinline)) void 11121 bce_dump_com_state(struct bce_softc *sc, int regs) 11122 { 11123 u32 val; 11124 u32 fw_version[4]; 11125 11126 BCE_PRINTF( 11127 "----------------------------" 11128 " COM State " 11129 "----------------------------\n"); 11130 11131 for (int i = 0; i < 3; i++) 11132 fw_version[i] = htonl(REG_RD_IND(sc, 11133 (BCE_COM_SCRATCH + 0x10 + i * 4))); 11134 11135 BCE_PRINTF("Firmware version - %s\n", (char *) fw_version); 11136 11137 val = REG_RD_IND(sc, BCE_COM_CPU_MODE); 11138 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", 11139 val, BCE_COM_CPU_MODE); 11140 11141 val = REG_RD_IND(sc, BCE_COM_CPU_STATE); 11142 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", 11143 val, BCE_COM_CPU_STATE); 11144 11145 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK); 11146 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val, 11147 BCE_COM_CPU_EVENT_MASK); 11148 11149 if (regs) { 11150 BCE_PRINTF( 11151 "----------------------------" 11152 " Register Dump " 11153 "----------------------------\n"); 11154 11155 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) { 11156 BCE_PRINTF("0x%04X: 0x%08X 0x%08X " 11157 "0x%08X 0x%08X\n", i, 11158 REG_RD_IND(sc, i), 11159 REG_RD_IND(sc, i + 0x4), 11160 REG_RD_IND(sc, i + 0x8), 11161 REG_RD_IND(sc, i + 0xC)); 11162 } 11163 } 11164 11165 BCE_PRINTF( 11166 "----------------------------" 11167 "----------------" 11168 "----------------------------\n"); 11169 } 11170 11171 11172 /****************************************************************************/ 11173 /* Prints out the Receive Virtual 2 Physical (RV2P) state. */ 11174 /* */ 11175 /* Returns: */ 11176 /* Nothing. */ 11177 /****************************************************************************/ 11178 static __attribute__ ((noinline)) void 11179 bce_dump_rv2p_state(struct bce_softc *sc) 11180 { 11181 u32 val, pc1, pc2, fw_ver_high, fw_ver_low; 11182 11183 BCE_PRINTF( 11184 "----------------------------" 11185 " RV2P State " 11186 "----------------------------\n"); 11187 11188 /* Stall the RV2P processors. */ 11189 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11190 val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2; 11191 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11192 11193 /* Read the firmware version. */ 11194 val = 0x00000001; 11195 REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 11196 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11197 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11198 BCE_RV2P_INSTR_HIGH_HIGH; 11199 BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n", 11200 fw_ver_high, fw_ver_low); 11201 11202 val = 0x00000001; 11203 REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 11204 fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW); 11205 fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) & 11206 BCE_RV2P_INSTR_HIGH_HIGH; 11207 BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n", 11208 fw_ver_high, fw_ver_low); 11209 11210 /* Resume the RV2P processors. */ 11211 val = REG_RD_IND(sc, BCE_RV2P_CONFIG); 11212 val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2); 11213 REG_WR_IND(sc, BCE_RV2P_CONFIG, val); 11214 11215 /* Fetch the program counter value. */ 11216 val = 0x68007800; 11217 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11218 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11219 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11220 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11221 BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1); 11222 BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2); 11223 11224 /* Fetch the program counter value again to see if it is advancing. */ 11225 val = 0x68007800; 11226 REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val); 11227 val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK); 11228 pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE); 11229 pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16; 11230 BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1); 11231 BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2); 11232 11233 BCE_PRINTF( 11234 "----------------------------" 11235 "----------------" 11236 "----------------------------\n"); 11237 } 11238 11239 11240 /****************************************************************************/ 11241 /* Prints out the driver state and then enters the debugger. */ 11242 /* */ 11243 /* Returns: */ 11244 /* Nothing. */ 11245 /****************************************************************************/ 11246 static __attribute__ ((noinline)) void 11247 bce_breakpoint(struct bce_softc *sc) 11248 { 11249 11250 /* 11251 * Unreachable code to silence compiler warnings 11252 * about unused functions. 11253 */ 11254 if (0) { 11255 bce_freeze_controller(sc); 11256 bce_unfreeze_controller(sc); 11257 bce_dump_enet(sc, NULL); 11258 bce_dump_txbd(sc, 0, NULL); 11259 bce_dump_rxbd(sc, 0, NULL); 11260 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC); 11261 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC); 11262 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC); 11263 bce_dump_l2fhdr(sc, 0, NULL); 11264 bce_dump_ctx(sc, RX_CID); 11265 bce_dump_ftqs(sc); 11266 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC); 11267 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC); 11268 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC); 11269 bce_dump_status_block(sc); 11270 bce_dump_stats_block(sc); 11271 bce_dump_driver_state(sc); 11272 bce_dump_hw_state(sc); 11273 bce_dump_bc_state(sc); 11274 bce_dump_txp_state(sc, 0); 11275 bce_dump_rxp_state(sc, 0); 11276 bce_dump_tpat_state(sc, 0); 11277 bce_dump_cp_state(sc, 0); 11278 bce_dump_com_state(sc, 0); 11279 bce_dump_rv2p_state(sc); 11280 bce_dump_pgbd(sc, 0, NULL); 11281 } 11282 11283 bce_dump_status_block(sc); 11284 bce_dump_driver_state(sc); 11285 11286 /* Call the debugger. */ 11287 breakpoint(); 11288 11289 return; 11290 } 11291 #endif 11292 11293