1 /*- 2 * Copyright (c) 2006-2007 Broadcom Corporation 3 * David Christensen <davidch@broadcom.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written consent. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * The following controllers are supported by this driver: 36 * BCM5706C A2, A3 37 * BCM5708C B1, B2 38 * 39 * The following controllers are not supported by this driver: 40 * BCM5706C A0, A1 41 * BCM5706S A0, A1, A2, A3 42 * BCM5708C A0, B0 43 * BCM5708S A0, B0, B1, B2 44 */ 45 46 #include "opt_bce.h" 47 48 #include <dev/bce/if_bcereg.h> 49 #include <dev/bce/if_bcefw.h> 50 51 /****************************************************************************/ 52 /* BCE Debug Options */ 53 /****************************************************************************/ 54 #ifdef BCE_DEBUG 55 u32 bce_debug = BCE_WARN; 56 57 /* 0 = Never */ 58 /* 1 = 1 in 2,147,483,648 */ 59 /* 256 = 1 in 8,388,608 */ 60 /* 2048 = 1 in 1,048,576 */ 61 /* 65536 = 1 in 32,768 */ 62 /* 1048576 = 1 in 2,048 */ 63 /* 268435456 = 1 in 8 */ 64 /* 536870912 = 1 in 4 */ 65 /* 1073741824 = 1 in 2 */ 66 67 /* Controls how often the l2_fhdr frame error check will fail. */ 68 int bce_debug_l2fhdr_status_check = 0; 69 70 /* Controls how often the unexpected attention check will fail. */ 71 int bce_debug_unexpected_attention = 0; 72 73 /* Controls how often to simulate an mbuf allocation failure. */ 74 int bce_debug_mbuf_allocation_failure = 0; 75 76 /* Controls how often to simulate a DMA mapping failure. */ 77 int bce_debug_dma_map_addr_failure = 0; 78 79 /* Controls how often to simulate a bootcode failure. */ 80 int bce_debug_bootcode_running_failure = 0; 81 #endif 82 83 84 /****************************************************************************/ 85 /* PCI Device ID Table */ 86 /* */ 87 /* Used by bce_probe() to identify the devices supported by this driver. */ 88 /****************************************************************************/ 89 #define BCE_DEVDESC_MAX 64 90 91 static struct bce_type bce_devs[] = { 92 /* BCM5706C Controllers and OEM boards. */ 93 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101, 94 "HP NC370T Multifunction Gigabit Server Adapter" }, 95 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106, 96 "HP NC370i Multifunction Gigabit Server Adapter" }, 97 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID, 98 "Broadcom NetXtreme II BCM5706 1000Base-T" }, 99 100 /* BCM5706S controllers and OEM boards. */ 101 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102, 102 "HP NC370F Multifunction Gigabit Server Adapter" }, 103 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID, 104 "Broadcom NetXtreme II BCM5706 1000Base-SX" }, 105 106 /* BCM5708C controllers and OEM boards. */ 107 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID, 108 "Broadcom NetXtreme II BCM5708 1000Base-T" }, 109 110 /* BCM5708S controllers and OEM boards. */ 111 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID, 112 "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 113 { 0, 0, 0, 0, NULL } 114 }; 115 116 117 /****************************************************************************/ 118 /* Supported Flash NVRAM device data. */ 119 /****************************************************************************/ 120 static struct flash_spec flash_table[] = 121 { 122 /* Slow EEPROM */ 123 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400, 124 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 125 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 126 "EEPROM - slow"}, 127 /* Expansion entry 0001 */ 128 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406, 129 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 130 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 131 "Entry 0001"}, 132 /* Saifun SA25F010 (non-buffered flash) */ 133 /* strap, cfg1, & write1 need updates */ 134 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406, 135 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 136 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, 137 "Non-buffered flash (128kB)"}, 138 /* Saifun SA25F020 (non-buffered flash) */ 139 /* strap, cfg1, & write1 need updates */ 140 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406, 141 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 142 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, 143 "Non-buffered flash (256kB)"}, 144 /* Expansion entry 0100 */ 145 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406, 146 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 147 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 148 "Entry 0100"}, 149 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */ 150 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406, 151 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 152 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2, 153 "Entry 0101: ST M45PE10 (128kB non-bufferred)"}, 154 /* Entry 0110: ST M45PE20 (non-buffered flash)*/ 155 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406, 156 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE, 157 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4, 158 "Entry 0110: ST M45PE20 (256kB non-bufferred)"}, 159 /* Saifun SA25F005 (non-buffered flash) */ 160 /* strap, cfg1, & write1 need updates */ 161 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406, 162 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 163 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, 164 "Non-buffered flash (64kB)"}, 165 /* Fast EEPROM */ 166 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400, 167 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, 168 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, 169 "EEPROM - fast"}, 170 /* Expansion entry 1001 */ 171 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406, 172 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 173 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 174 "Entry 1001"}, 175 /* Expansion entry 1010 */ 176 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406, 177 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 179 "Entry 1010"}, 180 /* ATMEL AT45DB011B (buffered flash) */ 181 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400, 182 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 183 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, 184 "Buffered flash (128kB)"}, 185 /* Expansion entry 1100 */ 186 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406, 187 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 188 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 189 "Entry 1100"}, 190 /* Expansion entry 1101 */ 191 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406, 192 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, 193 SAIFUN_FLASH_BYTE_ADDR_MASK, 0, 194 "Entry 1101"}, 195 /* Ateml Expansion entry 1110 */ 196 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400, 197 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 198 BUFFERED_FLASH_BYTE_ADDR_MASK, 0, 199 "Entry 1110 (Atmel)"}, 200 /* ATMEL AT45DB021B (buffered flash) */ 201 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400, 202 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, 203 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2, 204 "Buffered flash (256kB)"}, 205 }; 206 207 208 /****************************************************************************/ 209 /* FreeBSD device entry points. */ 210 /****************************************************************************/ 211 static int bce_probe (device_t); 212 static int bce_attach (device_t); 213 static int bce_detach (device_t); 214 static void bce_shutdown (device_t); 215 216 217 /****************************************************************************/ 218 /* BCE Debug Data Structure Dump Routines */ 219 /****************************************************************************/ 220 #ifdef BCE_DEBUG 221 static void bce_dump_mbuf (struct bce_softc *, struct mbuf *); 222 static void bce_dump_tx_mbuf_chain (struct bce_softc *, int, int); 223 static void bce_dump_rx_mbuf_chain (struct bce_softc *, int, int); 224 static void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *); 225 static void bce_dump_rxbd (struct bce_softc *, int, struct rx_bd *); 226 static void bce_dump_l2fhdr (struct bce_softc *, int, struct l2_fhdr *); 227 static void bce_dump_tx_chain (struct bce_softc *, int, int); 228 static void bce_dump_rx_chain (struct bce_softc *, int, int); 229 static void bce_dump_status_block (struct bce_softc *); 230 static void bce_dump_stats_block (struct bce_softc *); 231 static void bce_dump_driver_state (struct bce_softc *); 232 static void bce_dump_hw_state (struct bce_softc *); 233 static void bce_dump_bc_state (struct bce_softc *); 234 static void bce_breakpoint (struct bce_softc *); 235 #endif 236 237 238 /****************************************************************************/ 239 /* BCE Register/Memory Access Routines */ 240 /****************************************************************************/ 241 static u32 bce_reg_rd_ind (struct bce_softc *, u32); 242 static void bce_reg_wr_ind (struct bce_softc *, u32, u32); 243 static void bce_ctx_wr (struct bce_softc *, u32, u32, u32); 244 static int bce_miibus_read_reg (device_t, int, int); 245 static int bce_miibus_write_reg (device_t, int, int, int); 246 static void bce_miibus_statchg (device_t); 247 248 249 /****************************************************************************/ 250 /* BCE NVRAM Access Routines */ 251 /****************************************************************************/ 252 static int bce_acquire_nvram_lock (struct bce_softc *); 253 static int bce_release_nvram_lock (struct bce_softc *); 254 static void bce_enable_nvram_access (struct bce_softc *); 255 static void bce_disable_nvram_access(struct bce_softc *); 256 static int bce_nvram_read_dword (struct bce_softc *, u32, u8 *, u32); 257 static int bce_init_nvram (struct bce_softc *); 258 static int bce_nvram_read (struct bce_softc *, u32, u8 *, int); 259 static int bce_nvram_test (struct bce_softc *); 260 #ifdef BCE_NVRAM_WRITE_SUPPORT 261 static int bce_enable_nvram_write (struct bce_softc *); 262 static void bce_disable_nvram_write (struct bce_softc *); 263 static int bce_nvram_erase_page (struct bce_softc *, u32); 264 static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32); 265 static int bce_nvram_write (struct bce_softc *, u32, u8 *, int); 266 #endif 267 268 /****************************************************************************/ 269 /* */ 270 /****************************************************************************/ 271 static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int); 272 static int bce_dma_alloc (device_t); 273 static void bce_dma_free (struct bce_softc *); 274 static void bce_release_resources (struct bce_softc *); 275 276 /****************************************************************************/ 277 /* BCE Firmware Synchronization and Load */ 278 /****************************************************************************/ 279 static int bce_fw_sync (struct bce_softc *, u32); 280 static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32); 281 static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *); 282 static void bce_init_cpus (struct bce_softc *); 283 284 static void bce_stop (struct bce_softc *); 285 static int bce_reset (struct bce_softc *, u32); 286 static int bce_chipinit (struct bce_softc *); 287 static int bce_blockinit (struct bce_softc *); 288 static int bce_get_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *); 289 290 static int bce_init_tx_chain (struct bce_softc *); 291 static int bce_init_rx_chain (struct bce_softc *); 292 static void bce_free_rx_chain (struct bce_softc *); 293 static void bce_free_tx_chain (struct bce_softc *); 294 295 static int bce_tx_encap (struct bce_softc *, struct mbuf **); 296 static void bce_start_locked (struct ifnet *); 297 static void bce_start (struct ifnet *); 298 static int bce_ioctl (struct ifnet *, u_long, caddr_t); 299 static void bce_watchdog (struct bce_softc *); 300 static int bce_ifmedia_upd (struct ifnet *); 301 static void bce_ifmedia_upd_locked (struct ifnet *); 302 static void bce_ifmedia_sts (struct ifnet *, struct ifmediareq *); 303 static void bce_init_locked (struct bce_softc *); 304 static void bce_init (void *); 305 static void bce_mgmt_init_locked(struct bce_softc *sc); 306 307 static void bce_init_context (struct bce_softc *); 308 static void bce_get_mac_addr (struct bce_softc *); 309 static void bce_set_mac_addr (struct bce_softc *); 310 static void bce_phy_intr (struct bce_softc *); 311 static void bce_rx_intr (struct bce_softc *); 312 static void bce_tx_intr (struct bce_softc *); 313 static void bce_disable_intr (struct bce_softc *); 314 static void bce_enable_intr (struct bce_softc *); 315 316 #ifdef DEVICE_POLLING 317 static void bce_poll_locked (struct ifnet *, enum poll_cmd, int); 318 static void bce_poll (struct ifnet *, enum poll_cmd, int); 319 #endif 320 static void bce_intr (void *); 321 static void bce_set_rx_mode (struct bce_softc *); 322 static void bce_stats_update (struct bce_softc *); 323 static void bce_tick (void *); 324 static void bce_pulse (void *); 325 static void bce_add_sysctls (struct bce_softc *); 326 327 328 /****************************************************************************/ 329 /* FreeBSD device dispatch table. */ 330 /****************************************************************************/ 331 static device_method_t bce_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, bce_probe), 334 DEVMETHOD(device_attach, bce_attach), 335 DEVMETHOD(device_detach, bce_detach), 336 DEVMETHOD(device_shutdown, bce_shutdown), 337 338 /* bus interface */ 339 DEVMETHOD(bus_print_child, bus_generic_print_child), 340 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 341 342 /* MII interface */ 343 DEVMETHOD(miibus_readreg, bce_miibus_read_reg), 344 DEVMETHOD(miibus_writereg, bce_miibus_write_reg), 345 DEVMETHOD(miibus_statchg, bce_miibus_statchg), 346 347 { 0, 0 } 348 }; 349 350 static driver_t bce_driver = { 351 "bce", 352 bce_methods, 353 sizeof(struct bce_softc) 354 }; 355 356 static devclass_t bce_devclass; 357 358 MODULE_DEPEND(bce, pci, 1, 1, 1); 359 MODULE_DEPEND(bce, ether, 1, 1, 1); 360 MODULE_DEPEND(bce, miibus, 1, 1, 1); 361 362 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0); 363 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0); 364 365 366 /****************************************************************************/ 367 /* Tunable device values */ 368 /****************************************************************************/ 369 static int bce_tso_enable = TRUE; 370 static int bce_msi_enable = 1; 371 372 /* Allowable values are TRUE or FALSE */ 373 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable); 374 /* Allowable values are 0 (IRQ only) and 1 (IRQ or MSI) */ 375 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable); 376 377 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters"); 378 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0, 379 "TSO Enable/Disable"); 380 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0, 381 "MSI | INTx selector"); 382 383 /****************************************************************************/ 384 /* Device probe function. */ 385 /* */ 386 /* Compares the device to the driver's list of supported devices and */ 387 /* reports back to the OS whether this is the right driver for the device. */ 388 /* */ 389 /* Returns: */ 390 /* BUS_PROBE_DEFAULT on success, positive value on failure. */ 391 /****************************************************************************/ 392 static int 393 bce_probe(device_t dev) 394 { 395 struct bce_type *t; 396 struct bce_softc *sc; 397 char *descbuf; 398 u16 vid = 0, did = 0, svid = 0, sdid = 0; 399 400 t = bce_devs; 401 402 sc = device_get_softc(dev); 403 bzero(sc, sizeof(struct bce_softc)); 404 sc->bce_unit = device_get_unit(dev); 405 sc->bce_dev = dev; 406 407 /* Get the data for the device to be probed. */ 408 vid = pci_get_vendor(dev); 409 did = pci_get_device(dev); 410 svid = pci_get_subvendor(dev); 411 sdid = pci_get_subdevice(dev); 412 413 DBPRINT(sc, BCE_VERBOSE_LOAD, 414 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 415 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 416 417 /* Look through the list of known devices for a match. */ 418 while(t->bce_name != NULL) { 419 420 if ((vid == t->bce_vid) && (did == t->bce_did) && 421 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) && 422 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) { 423 424 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 425 426 if (descbuf == NULL) 427 return(ENOMEM); 428 429 /* Print out the device identity. */ 430 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)", 431 t->bce_name, 432 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 433 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 434 435 device_set_desc_copy(dev, descbuf); 436 free(descbuf, M_TEMP); 437 return(BUS_PROBE_DEFAULT); 438 } 439 t++; 440 } 441 442 return(ENXIO); 443 } 444 445 446 /****************************************************************************/ 447 /* Device attach function. */ 448 /* */ 449 /* Allocates device resources, performs secondary chip identification, */ 450 /* resets and initializes the hardware, and initializes driver instance */ 451 /* variables. */ 452 /* */ 453 /* Returns: */ 454 /* 0 on success, positive value on failure. */ 455 /****************************************************************************/ 456 static int 457 bce_attach(device_t dev) 458 { 459 struct bce_softc *sc; 460 struct ifnet *ifp; 461 u32 val; 462 int count, mbuf, rid, rc = 0; 463 464 sc = device_get_softc(dev); 465 sc->bce_dev = dev; 466 467 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 468 469 mbuf = device_get_unit(dev); 470 471 /* Set initial device and PHY flags */ 472 sc->bce_flags = 0; 473 sc->bce_phy_flags = 0; 474 475 sc->bce_unit = mbuf; 476 477 pci_enable_busmaster(dev); 478 479 /* Allocate PCI memory resources. */ 480 rid = PCIR_BAR(0); 481 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 482 &rid, RF_ACTIVE | PCI_RF_DENSE); 483 484 if (sc->bce_res_mem == NULL) { 485 BCE_PRINTF("%s(%d): PCI memory allocation failed\n", 486 __FILE__, __LINE__); 487 rc = ENXIO; 488 goto bce_attach_fail; 489 } 490 491 /* Get various resource handles. */ 492 sc->bce_btag = rman_get_bustag(sc->bce_res_mem); 493 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem); 494 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem); 495 496 /* If MSI is enabled in the driver, get the vector count. */ 497 count = bce_msi_enable ? pci_msi_count(dev) : 0; 498 499 /* Allocate PCI IRQ resources. */ 500 if (count == 1 && pci_alloc_msi(dev, &count) == 0 && count == 1) { 501 rid = 1; 502 sc->bce_flags |= BCE_USING_MSI_FLAG; 503 DBPRINT(sc, BCE_VERBOSE_LOAD, 504 "Allocating %d MSI interrupt(s)\n", count); 505 } else { 506 rid = 0; 507 DBPRINT(sc, BCE_VERBOSE_LOAD, "Allocating IRQ interrupt\n"); 508 } 509 510 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 511 RF_SHAREABLE | RF_ACTIVE); 512 513 if (sc->bce_res_irq == NULL) { 514 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n", 515 __FILE__, __LINE__); 516 rc = ENXIO; 517 goto bce_attach_fail; 518 } 519 520 /* Initialize mutex for the current device instance. */ 521 BCE_LOCK_INIT(sc, device_get_nameunit(dev)); 522 523 /* 524 * Configure byte swap and enable indirect register access. 525 * Rely on CPU to do target byte swapping on big endian systems. 526 * Access to registers outside of PCI configurtion space are not 527 * valid until this is done. 528 */ 529 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG, 530 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 531 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4); 532 533 /* Save ASIC revsion info. */ 534 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID); 535 536 /* Weed out any non-production controller revisions. */ 537 switch(BCE_CHIP_ID(sc)) { 538 case BCE_CHIP_ID_5706_A0: 539 case BCE_CHIP_ID_5706_A1: 540 case BCE_CHIP_ID_5708_A0: 541 case BCE_CHIP_ID_5708_B0: 542 BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n", 543 __FILE__, __LINE__, 544 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'), 545 (pci_read_config(dev, PCIR_REVID, 4) & 0xf)); 546 rc = ENODEV; 547 goto bce_attach_fail; 548 } 549 550 /* 551 * The embedded PCIe to PCI-X bridge (EPB) 552 * in the 5708 cannot address memory above 553 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 554 */ 555 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708) 556 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR; 557 else 558 sc->max_bus_addr = BUS_SPACE_MAXADDR; 559 560 /* 561 * Find the base address for shared memory access. 562 * Newer versions of bootcode use a signature and offset 563 * while older versions use a fixed address. 564 */ 565 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE); 566 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG) 567 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0); 568 else 569 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE; 570 571 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n", 572 __FUNCTION__, sc->bce_shmem_base); 573 574 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base + 575 BCE_DEV_INFO_BC_REV); 576 DBPRINT(sc, BCE_INFO_FIRMWARE, "%s(): bce_fw_ver = 0x%08X\n", 577 __FUNCTION__, sc->bce_fw_ver); 578 579 /* Check if any management firmware is running. */ 580 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE); 581 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED)) { 582 sc->bce_flags |= BCE_MFW_ENABLE_FLAG; 583 DBPRINT(sc, BCE_INFO_LOAD, "%s(): BCE_MFW_ENABLE_FLAG\n", 584 __FUNCTION__); 585 } 586 587 /* Get PCI bus information (speed and type). */ 588 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS); 589 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) { 590 u32 clkreg; 591 592 sc->bce_flags |= BCE_PCIX_FLAG; 593 594 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS); 595 596 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; 597 switch (clkreg) { 598 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: 599 sc->bus_speed_mhz = 133; 600 break; 601 602 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: 603 sc->bus_speed_mhz = 100; 604 break; 605 606 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: 607 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: 608 sc->bus_speed_mhz = 66; 609 break; 610 611 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: 612 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: 613 sc->bus_speed_mhz = 50; 614 break; 615 616 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: 617 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: 618 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: 619 sc->bus_speed_mhz = 33; 620 break; 621 } 622 } else { 623 if (val & BCE_PCICFG_MISC_STATUS_M66EN) 624 sc->bus_speed_mhz = 66; 625 else 626 sc->bus_speed_mhz = 33; 627 } 628 629 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET) 630 sc->bce_flags |= BCE_PCI_32BIT_FLAG; 631 632 /* Reset the controller and announce to bootcde that driver is present. */ 633 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 634 BCE_PRINTF("%s(%d): Controller reset failed!\n", 635 __FILE__, __LINE__); 636 rc = ENXIO; 637 goto bce_attach_fail; 638 } 639 640 /* Initialize the controller. */ 641 if (bce_chipinit(sc)) { 642 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 643 __FILE__, __LINE__); 644 rc = ENXIO; 645 goto bce_attach_fail; 646 } 647 648 /* Perform NVRAM test. */ 649 if (bce_nvram_test(sc)) { 650 BCE_PRINTF("%s(%d): NVRAM test failed!\n", 651 __FILE__, __LINE__); 652 rc = ENXIO; 653 goto bce_attach_fail; 654 } 655 656 /* Fetch the permanent Ethernet MAC address. */ 657 bce_get_mac_addr(sc); 658 659 /* 660 * Trip points control how many BDs 661 * should be ready before generating an 662 * interrupt while ticks control how long 663 * a BD can sit in the chain before 664 * generating an interrupt. Set the default 665 * values for the RX and TX chains. 666 */ 667 668 #ifdef BCE_DEBUG 669 /* Force more frequent interrupts. */ 670 sc->bce_tx_quick_cons_trip_int = 1; 671 sc->bce_tx_quick_cons_trip = 1; 672 sc->bce_tx_ticks_int = 0; 673 sc->bce_tx_ticks = 0; 674 675 sc->bce_rx_quick_cons_trip_int = 1; 676 sc->bce_rx_quick_cons_trip = 1; 677 sc->bce_rx_ticks_int = 0; 678 sc->bce_rx_ticks = 0; 679 #else 680 /* Improve throughput at the expense of increased latency. */ 681 sc->bce_tx_quick_cons_trip_int = 20; 682 sc->bce_tx_quick_cons_trip = 20; 683 sc->bce_tx_ticks_int = 80; 684 sc->bce_tx_ticks = 80; 685 686 sc->bce_rx_quick_cons_trip_int = 6; 687 sc->bce_rx_quick_cons_trip = 6; 688 sc->bce_rx_ticks_int = 18; 689 sc->bce_rx_ticks = 18; 690 #endif 691 692 /* Update statistics once every second. */ 693 sc->bce_stats_ticks = 1000000 & 0xffff00; 694 695 /* 696 * The SerDes based NetXtreme II controllers 697 * that support 2.5Gb operation (currently 698 * 5708S) use a PHY at address 2, otherwise 699 * the PHY is present at address 1. 700 */ 701 sc->bce_phy_addr = 1; 702 703 if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) { 704 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG; 705 sc->bce_flags |= BCE_NO_WOL_FLAG; 706 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 707 sc->bce_phy_addr = 2; 708 val = REG_RD_IND(sc, sc->bce_shmem_base + 709 BCE_SHARED_HW_CFG_CONFIG); 710 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) { 711 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG; 712 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb capable adapter\n"); 713 } 714 } 715 } 716 717 /* Store data needed by PHY driver for backplane applications */ 718 sc->bce_shared_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 719 BCE_SHARED_HW_CFG_CONFIG); 720 sc->bce_port_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base + 721 BCE_SHARED_HW_CFG_CONFIG); 722 723 /* Allocate DMA memory resources. */ 724 if (bce_dma_alloc(dev)) { 725 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n", 726 __FILE__, __LINE__); 727 rc = ENXIO; 728 goto bce_attach_fail; 729 } 730 731 /* Allocate an ifnet structure. */ 732 ifp = sc->bce_ifp = if_alloc(IFT_ETHER); 733 if (ifp == NULL) { 734 BCE_PRINTF("%s(%d): Interface allocation failed!\n", 735 __FILE__, __LINE__); 736 rc = ENXIO; 737 goto bce_attach_fail; 738 } 739 740 /* Initialize the ifnet interface. */ 741 ifp->if_softc = sc; 742 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 743 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 744 ifp->if_ioctl = bce_ioctl; 745 ifp->if_start = bce_start; 746 ifp->if_init = bce_init; 747 ifp->if_mtu = ETHERMTU; 748 749 if (bce_tso_enable) { 750 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO; 751 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4; 752 } else { 753 ifp->if_hwassist = BCE_IF_HWASSIST; 754 ifp->if_capabilities = BCE_IF_CAPABILITIES; 755 } 756 757 ifp->if_capenable = ifp->if_capabilities; 758 759 /* Assume a standard 1500 byte MTU size for mbuf allocations. */ 760 sc->mbuf_alloc_size = MCLBYTES; 761 #ifdef DEVICE_POLLING 762 ifp->if_capabilities |= IFCAP_POLLING; 763 #endif 764 765 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD; 766 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 767 IFQ_SET_READY(&ifp->if_snd); 768 769 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 770 ifp->if_baudrate = IF_Mbps(2500ULL); 771 else 772 ifp->if_baudrate = IF_Mbps(1000); 773 774 /* Check for an MII child bus by probing the PHY. */ 775 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd, 776 bce_ifmedia_sts)) { 777 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n", 778 __FILE__, __LINE__); 779 rc = ENXIO; 780 goto bce_attach_fail; 781 } 782 783 /* Attach to the Ethernet interface list. */ 784 ether_ifattach(ifp, sc->eaddr); 785 786 #if __FreeBSD_version < 500000 787 callout_init(&sc->bce_tick_callout); 788 callout_init(&sc->bce_pulse_callout); 789 #else 790 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0); 791 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0); 792 #endif 793 794 /* Hookup IRQ last. */ 795 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, NULL, 796 bce_intr, sc, &sc->bce_intrhand); 797 798 if (rc) { 799 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n", 800 __FILE__, __LINE__); 801 bce_detach(dev); 802 goto bce_attach_exit; 803 } 804 805 /* 806 * At this point we've acquired all the resources 807 * we need to run so there's no turning back, we're 808 * cleared for launch. 809 */ 810 811 /* Print some important debugging info. */ 812 DBRUN(BCE_INFO, bce_dump_driver_state(sc)); 813 814 /* Add the supported sysctls to the kernel. */ 815 bce_add_sysctls(sc); 816 817 BCE_LOCK(sc); 818 /* 819 * The chip reset earlier notified the bootcode that 820 * a driver is present. We now need to start our pulse 821 * routine so that the bootcode is reminded that we're 822 * still running. 823 */ 824 bce_pulse(sc); 825 826 bce_mgmt_init_locked(sc); 827 BCE_UNLOCK(sc); 828 829 /* Finally, print some useful adapter info */ 830 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid); 831 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A', 832 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4)); 833 printf("Bus (PCI%s, %s, %dMHz); ", 834 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""), 835 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), 836 sc->bus_speed_mhz); 837 printf("F/W (0x%08X); Flags( ", sc->bce_fw_ver); 838 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 839 printf("MFW "); 840 if (sc->bce_flags & BCE_USING_MSI_FLAG) 841 printf("MSI "); 842 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) 843 printf("2.5G "); 844 printf(")\n"); 845 846 goto bce_attach_exit; 847 848 bce_attach_fail: 849 bce_release_resources(sc); 850 851 bce_attach_exit: 852 853 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 854 855 return(rc); 856 } 857 858 859 /****************************************************************************/ 860 /* Device detach function. */ 861 /* */ 862 /* Stops the controller, resets the controller, and releases resources. */ 863 /* */ 864 /* Returns: */ 865 /* 0 on success, positive value on failure. */ 866 /****************************************************************************/ 867 static int 868 bce_detach(device_t dev) 869 { 870 struct bce_softc *sc = device_get_softc(dev); 871 struct ifnet *ifp; 872 u32 msg; 873 874 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 875 876 ifp = sc->bce_ifp; 877 878 #ifdef DEVICE_POLLING 879 if (ifp->if_capenable & IFCAP_POLLING) 880 ether_poll_deregister(ifp); 881 #endif 882 883 /* Stop the pulse so the bootcode can go to driver absent state. */ 884 callout_stop(&sc->bce_pulse_callout); 885 886 /* Stop and reset the controller. */ 887 BCE_LOCK(sc); 888 bce_stop(sc); 889 if (sc->bce_flags & BCE_NO_WOL_FLAG) 890 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 891 else 892 msg = BCE_DRV_MSG_CODE_UNLOAD; 893 bce_reset(sc, msg); 894 BCE_UNLOCK(sc); 895 896 ether_ifdetach(ifp); 897 898 /* If we have a child device on the MII bus remove it too. */ 899 bus_generic_detach(dev); 900 device_delete_child(dev, sc->bce_miibus); 901 902 /* Release all remaining resources. */ 903 bce_release_resources(sc); 904 905 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 906 907 return(0); 908 } 909 910 911 /****************************************************************************/ 912 /* Device shutdown function. */ 913 /* */ 914 /* Stops and resets the controller. */ 915 /* */ 916 /* Returns: */ 917 /* Nothing */ 918 /****************************************************************************/ 919 static void 920 bce_shutdown(device_t dev) 921 { 922 struct bce_softc *sc = device_get_softc(dev); 923 u32 msg; 924 925 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Entering %s()\n", __FUNCTION__); 926 927 BCE_LOCK(sc); 928 bce_stop(sc); 929 if (sc->bce_flags & BCE_NO_WOL_FLAG) 930 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN; 931 else 932 msg = BCE_DRV_MSG_CODE_UNLOAD; 933 bce_reset(sc, msg); 934 BCE_UNLOCK(sc); 935 936 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Exiting %s()\n", __FUNCTION__); 937 } 938 939 940 /****************************************************************************/ 941 /* Indirect register read. */ 942 /* */ 943 /* Reads NetXtreme II registers using an index/data register pair in PCI */ 944 /* configuration space. Using this mechanism avoids issues with posted */ 945 /* reads but is much slower than memory-mapped I/O. */ 946 /* */ 947 /* Returns: */ 948 /* The value of the register. */ 949 /****************************************************************************/ 950 static u32 951 bce_reg_rd_ind(struct bce_softc *sc, u32 offset) 952 { 953 device_t dev; 954 dev = sc->bce_dev; 955 956 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 957 #ifdef BCE_DEBUG 958 { 959 u32 val; 960 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 961 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 962 __FUNCTION__, offset, val); 963 return val; 964 } 965 #else 966 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4); 967 #endif 968 } 969 970 971 /****************************************************************************/ 972 /* Indirect register write. */ 973 /* */ 974 /* Writes NetXtreme II registers using an index/data register pair in PCI */ 975 /* configuration space. Using this mechanism avoids issues with posted */ 976 /* writes but is muchh slower than memory-mapped I/O. */ 977 /* */ 978 /* Returns: */ 979 /* Nothing. */ 980 /****************************************************************************/ 981 static void 982 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val) 983 { 984 device_t dev; 985 dev = sc->bce_dev; 986 987 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n", 988 __FUNCTION__, offset, val); 989 990 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4); 991 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4); 992 } 993 994 995 /****************************************************************************/ 996 /* Context memory write. */ 997 /* */ 998 /* The NetXtreme II controller uses context memory to track connection */ 999 /* information for L2 and higher network protocols. */ 1000 /* */ 1001 /* Returns: */ 1002 /* Nothing. */ 1003 /****************************************************************************/ 1004 static void 1005 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 offset, u32 val) 1006 { 1007 1008 DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, " 1009 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val); 1010 1011 offset += cid_addr; 1012 REG_WR(sc, BCE_CTX_DATA_ADR, offset); 1013 REG_WR(sc, BCE_CTX_DATA, val); 1014 } 1015 1016 1017 /****************************************************************************/ 1018 /* PHY register read. */ 1019 /* */ 1020 /* Implements register reads on the MII bus. */ 1021 /* */ 1022 /* Returns: */ 1023 /* The value of the register. */ 1024 /****************************************************************************/ 1025 static int 1026 bce_miibus_read_reg(device_t dev, int phy, int reg) 1027 { 1028 struct bce_softc *sc; 1029 u32 val; 1030 int i; 1031 1032 sc = device_get_softc(dev); 1033 1034 /* Make sure we are accessing the correct PHY address. */ 1035 if (phy != sc->bce_phy_addr) { 1036 DBPRINT(sc, BCE_EXCESSIVE_PHY, "Invalid PHY address %d for PHY read!\n", phy); 1037 return(0); 1038 } 1039 1040 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1041 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1042 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1043 1044 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1045 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1046 1047 DELAY(40); 1048 } 1049 1050 val = BCE_MIPHY(phy) | BCE_MIREG(reg) | 1051 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT | 1052 BCE_EMAC_MDIO_COMM_START_BUSY; 1053 REG_WR(sc, BCE_EMAC_MDIO_COMM, val); 1054 1055 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1056 DELAY(10); 1057 1058 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1059 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1060 DELAY(5); 1061 1062 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1063 val &= BCE_EMAC_MDIO_COMM_DATA; 1064 1065 break; 1066 } 1067 } 1068 1069 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) { 1070 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n", 1071 __FILE__, __LINE__, phy, reg); 1072 val = 0x0; 1073 } else { 1074 val = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1075 } 1076 1077 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1078 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1079 1080 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1081 val = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1082 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1083 1084 REG_WR(sc, BCE_EMAC_MDIO_MODE, val); 1085 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1086 1087 DELAY(40); 1088 } 1089 1090 return (val & 0xffff); 1091 1092 } 1093 1094 1095 /****************************************************************************/ 1096 /* PHY register write. */ 1097 /* */ 1098 /* Implements register writes on the MII bus. */ 1099 /* */ 1100 /* Returns: */ 1101 /* The value of the register. */ 1102 /****************************************************************************/ 1103 static int 1104 bce_miibus_write_reg(device_t dev, int phy, int reg, int val) 1105 { 1106 struct bce_softc *sc; 1107 u32 val1; 1108 int i; 1109 1110 sc = device_get_softc(dev); 1111 1112 /* Make sure we are accessing the correct PHY address. */ 1113 if (phy != sc->bce_phy_addr) { 1114 DBPRINT(sc, BCE_EXCESSIVE_PHY, "Invalid PHY address %d for PHY write!\n", phy); 1115 return(0); 1116 } 1117 1118 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", 1119 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); 1120 1121 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1122 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1123 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL; 1124 1125 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1126 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1127 1128 DELAY(40); 1129 } 1130 1131 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val | 1132 BCE_EMAC_MDIO_COMM_COMMAND_WRITE | 1133 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT; 1134 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1); 1135 1136 for (i = 0; i < BCE_PHY_TIMEOUT; i++) { 1137 DELAY(10); 1138 1139 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM); 1140 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) { 1141 DELAY(5); 1142 break; 1143 } 1144 } 1145 1146 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY) 1147 BCE_PRINTF("%s(%d): PHY write timeout!\n", 1148 __FILE__, __LINE__); 1149 1150 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) { 1151 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE); 1152 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL; 1153 1154 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1); 1155 REG_RD(sc, BCE_EMAC_MDIO_MODE); 1156 1157 DELAY(40); 1158 } 1159 1160 return 0; 1161 } 1162 1163 1164 /****************************************************************************/ 1165 /* MII bus status change. */ 1166 /* */ 1167 /* Called by the MII bus driver when the PHY establishes link to set the */ 1168 /* MAC interface registers. */ 1169 /* */ 1170 /* Returns: */ 1171 /* Nothing. */ 1172 /****************************************************************************/ 1173 static void 1174 bce_miibus_statchg(device_t dev) 1175 { 1176 struct bce_softc *sc; 1177 struct mii_data *mii; 1178 int val; 1179 1180 sc = device_get_softc(dev); 1181 1182 mii = device_get_softc(sc->bce_miibus); 1183 1184 val = REG_RD(sc, BCE_EMAC_MODE); 1185 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX | 1186 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK | 1187 BCE_EMAC_MODE_25G); 1188 1189 /* Set MII or GMII interface based on the speed negotiated by the PHY. */ 1190 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1191 case IFM_10_T: 1192 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) { 1193 DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n"); 1194 val |= BCE_EMAC_MODE_PORT_MII_10; 1195 break; 1196 } 1197 /* fall-through */ 1198 case IFM_100_TX: 1199 DBPRINT(sc, BCE_INFO, "Enabling MII interface.\n"); 1200 val |= BCE_EMAC_MODE_PORT_MII; 1201 break; 1202 case IFM_2500_SX: 1203 DBPRINT(sc, BCE_INFO, "Enabling 2.5G MAC mode.\n"); 1204 val |= BCE_EMAC_MODE_25G; 1205 /* fall-through */ 1206 case IFM_1000_T: 1207 case IFM_1000_SX: 1208 DBPRINT(sc, BCE_INFO, "Enabling GMII interface.\n"); 1209 val |= BCE_EMAC_MODE_PORT_GMII; 1210 break; 1211 default: 1212 DBPRINT(sc, BCE_INFO, "Enabling default GMII interface.\n"); 1213 val |= BCE_EMAC_MODE_PORT_GMII; 1214 } 1215 1216 /* Set half or full duplex based on the duplicity negotiated by the PHY. */ 1217 if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) { 1218 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n"); 1219 val |= BCE_EMAC_MODE_HALF_DUPLEX; 1220 } else 1221 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n"); 1222 1223 REG_WR(sc, BCE_EMAC_MODE, val); 1224 1225 #if 0 1226 /* Todo: Enable flow control support in brgphy and bge. */ 1227 /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */ 1228 if (mii->mii_media_active & IFM_FLAG0) 1229 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN); 1230 if (mii->mii_media_active & IFM_FLAG1) 1231 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN); 1232 #endif 1233 1234 } 1235 1236 1237 /****************************************************************************/ 1238 /* Acquire NVRAM lock. */ 1239 /* */ 1240 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */ 1241 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1242 /* for use by the driver. */ 1243 /* */ 1244 /* Returns: */ 1245 /* 0 on success, positive value on failure. */ 1246 /****************************************************************************/ 1247 static int 1248 bce_acquire_nvram_lock(struct bce_softc *sc) 1249 { 1250 u32 val; 1251 int j; 1252 1253 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Acquiring NVRAM lock.\n"); 1254 1255 /* Request access to the flash interface. */ 1256 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2); 1257 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1258 val = REG_RD(sc, BCE_NVM_SW_ARB); 1259 if (val & BCE_NVM_SW_ARB_ARB_ARB2) 1260 break; 1261 1262 DELAY(5); 1263 } 1264 1265 if (j >= NVRAM_TIMEOUT_COUNT) { 1266 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n"); 1267 return EBUSY; 1268 } 1269 1270 return 0; 1271 } 1272 1273 1274 /****************************************************************************/ 1275 /* Release NVRAM lock. */ 1276 /* */ 1277 /* When the caller is finished accessing NVRAM the lock must be released. */ 1278 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */ 1279 /* for use by the driver. */ 1280 /* */ 1281 /* Returns: */ 1282 /* 0 on success, positive value on failure. */ 1283 /****************************************************************************/ 1284 static int 1285 bce_release_nvram_lock(struct bce_softc *sc) 1286 { 1287 int j; 1288 u32 val; 1289 1290 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Releasing NVRAM lock.\n"); 1291 1292 /* 1293 * Relinquish nvram interface. 1294 */ 1295 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2); 1296 1297 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1298 val = REG_RD(sc, BCE_NVM_SW_ARB); 1299 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2)) 1300 break; 1301 1302 DELAY(5); 1303 } 1304 1305 if (j >= NVRAM_TIMEOUT_COUNT) { 1306 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n"); 1307 return EBUSY; 1308 } 1309 1310 return 0; 1311 } 1312 1313 1314 #ifdef BCE_NVRAM_WRITE_SUPPORT 1315 /****************************************************************************/ 1316 /* Enable NVRAM write access. */ 1317 /* */ 1318 /* Before writing to NVRAM the caller must enable NVRAM writes. */ 1319 /* */ 1320 /* Returns: */ 1321 /* 0 on success, positive value on failure. */ 1322 /****************************************************************************/ 1323 static int 1324 bce_enable_nvram_write(struct bce_softc *sc) 1325 { 1326 u32 val; 1327 1328 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Enabling NVRAM write.\n"); 1329 1330 val = REG_RD(sc, BCE_MISC_CFG); 1331 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI); 1332 1333 if (!sc->bce_flash_info->buffered) { 1334 int j; 1335 1336 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1337 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT); 1338 1339 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1340 DELAY(5); 1341 1342 val = REG_RD(sc, BCE_NVM_COMMAND); 1343 if (val & BCE_NVM_COMMAND_DONE) 1344 break; 1345 } 1346 1347 if (j >= NVRAM_TIMEOUT_COUNT) { 1348 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n"); 1349 return EBUSY; 1350 } 1351 } 1352 return 0; 1353 } 1354 1355 1356 /****************************************************************************/ 1357 /* Disable NVRAM write access. */ 1358 /* */ 1359 /* When the caller is finished writing to NVRAM write access must be */ 1360 /* disabled. */ 1361 /* */ 1362 /* Returns: */ 1363 /* Nothing. */ 1364 /****************************************************************************/ 1365 static void 1366 bce_disable_nvram_write(struct bce_softc *sc) 1367 { 1368 u32 val; 1369 1370 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Disabling NVRAM write.\n"); 1371 1372 val = REG_RD(sc, BCE_MISC_CFG); 1373 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN); 1374 } 1375 #endif 1376 1377 1378 /****************************************************************************/ 1379 /* Enable NVRAM access. */ 1380 /* */ 1381 /* Before accessing NVRAM for read or write operations the caller must */ 1382 /* enabled NVRAM access. */ 1383 /* */ 1384 /* Returns: */ 1385 /* Nothing. */ 1386 /****************************************************************************/ 1387 static void 1388 bce_enable_nvram_access(struct bce_softc *sc) 1389 { 1390 u32 val; 1391 1392 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Enabling NVRAM access.\n"); 1393 1394 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1395 /* Enable both bits, even on read. */ 1396 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1397 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN); 1398 } 1399 1400 1401 /****************************************************************************/ 1402 /* Disable NVRAM access. */ 1403 /* */ 1404 /* When the caller is finished accessing NVRAM access must be disabled. */ 1405 /* */ 1406 /* Returns: */ 1407 /* Nothing. */ 1408 /****************************************************************************/ 1409 static void 1410 bce_disable_nvram_access(struct bce_softc *sc) 1411 { 1412 u32 val; 1413 1414 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Disabling NVRAM access.\n"); 1415 1416 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE); 1417 1418 /* Disable both bits, even after read. */ 1419 REG_WR(sc, BCE_NVM_ACCESS_ENABLE, 1420 val & ~(BCE_NVM_ACCESS_ENABLE_EN | 1421 BCE_NVM_ACCESS_ENABLE_WR_EN)); 1422 } 1423 1424 1425 #ifdef BCE_NVRAM_WRITE_SUPPORT 1426 /****************************************************************************/ 1427 /* Erase NVRAM page before writing. */ 1428 /* */ 1429 /* Non-buffered flash parts require that a page be erased before it is */ 1430 /* written. */ 1431 /* */ 1432 /* Returns: */ 1433 /* 0 on success, positive value on failure. */ 1434 /****************************************************************************/ 1435 static int 1436 bce_nvram_erase_page(struct bce_softc *sc, u32 offset) 1437 { 1438 u32 cmd; 1439 int j; 1440 1441 /* Buffered flash doesn't require an erase. */ 1442 if (sc->bce_flash_info->buffered) 1443 return 0; 1444 1445 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Erasing NVRAM page.\n"); 1446 1447 /* Build an erase command. */ 1448 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR | 1449 BCE_NVM_COMMAND_DOIT; 1450 1451 /* 1452 * Clear the DONE bit separately, set the NVRAM adress to erase, 1453 * and issue the erase command. 1454 */ 1455 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1456 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1457 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1458 1459 /* Wait for completion. */ 1460 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1461 u32 val; 1462 1463 DELAY(5); 1464 1465 val = REG_RD(sc, BCE_NVM_COMMAND); 1466 if (val & BCE_NVM_COMMAND_DONE) 1467 break; 1468 } 1469 1470 if (j >= NVRAM_TIMEOUT_COUNT) { 1471 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n"); 1472 return EBUSY; 1473 } 1474 1475 return 0; 1476 } 1477 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1478 1479 1480 /****************************************************************************/ 1481 /* Read a dword (32 bits) from NVRAM. */ 1482 /* */ 1483 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */ 1484 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */ 1485 /* */ 1486 /* Returns: */ 1487 /* 0 on success and the 32 bit value read, positive value on failure. */ 1488 /****************************************************************************/ 1489 static int 1490 bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val, 1491 u32 cmd_flags) 1492 { 1493 u32 cmd; 1494 int i, rc = 0; 1495 1496 /* Build the command word. */ 1497 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags; 1498 1499 /* Calculate the offset for buffered flash. */ 1500 if (sc->bce_flash_info->buffered) { 1501 offset = ((offset / sc->bce_flash_info->page_size) << 1502 sc->bce_flash_info->page_bits) + 1503 (offset % sc->bce_flash_info->page_size); 1504 } 1505 1506 /* 1507 * Clear the DONE bit separately, set the address to read, 1508 * and issue the read. 1509 */ 1510 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1511 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1512 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1513 1514 /* Wait for completion. */ 1515 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) { 1516 u32 val; 1517 1518 DELAY(5); 1519 1520 val = REG_RD(sc, BCE_NVM_COMMAND); 1521 if (val & BCE_NVM_COMMAND_DONE) { 1522 val = REG_RD(sc, BCE_NVM_READ); 1523 1524 val = bce_be32toh(val); 1525 memcpy(ret_val, &val, 4); 1526 break; 1527 } 1528 } 1529 1530 /* Check for errors. */ 1531 if (i >= NVRAM_TIMEOUT_COUNT) { 1532 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n", 1533 __FILE__, __LINE__, offset); 1534 rc = EBUSY; 1535 } 1536 1537 return(rc); 1538 } 1539 1540 1541 #ifdef BCE_NVRAM_WRITE_SUPPORT 1542 /****************************************************************************/ 1543 /* Write a dword (32 bits) to NVRAM. */ 1544 /* */ 1545 /* Write a 32 bit word to NVRAM. The caller is assumed to have already */ 1546 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and */ 1547 /* enabled NVRAM write access. */ 1548 /* */ 1549 /* Returns: */ 1550 /* 0 on success, positive value on failure. */ 1551 /****************************************************************************/ 1552 static int 1553 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val, 1554 u32 cmd_flags) 1555 { 1556 u32 cmd, val32; 1557 int j; 1558 1559 /* Build the command word. */ 1560 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags; 1561 1562 /* Calculate the offset for buffered flash. */ 1563 if (sc->bce_flash_info->buffered) { 1564 offset = ((offset / sc->bce_flash_info->page_size) << 1565 sc->bce_flash_info->page_bits) + 1566 (offset % sc->bce_flash_info->page_size); 1567 } 1568 1569 /* 1570 * Clear the DONE bit separately, convert NVRAM data to big-endian, 1571 * set the NVRAM address to write, and issue the write command 1572 */ 1573 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE); 1574 memcpy(&val32, val, 4); 1575 val32 = htobe32(val32); 1576 REG_WR(sc, BCE_NVM_WRITE, val32); 1577 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE); 1578 REG_WR(sc, BCE_NVM_COMMAND, cmd); 1579 1580 /* Wait for completion. */ 1581 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { 1582 DELAY(5); 1583 1584 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE) 1585 break; 1586 } 1587 if (j >= NVRAM_TIMEOUT_COUNT) { 1588 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n", 1589 __FILE__, __LINE__, offset); 1590 return EBUSY; 1591 } 1592 1593 return 0; 1594 } 1595 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 1596 1597 1598 /****************************************************************************/ 1599 /* Initialize NVRAM access. */ 1600 /* */ 1601 /* Identify the NVRAM device in use and prepare the NVRAM interface to */ 1602 /* access that device. */ 1603 /* */ 1604 /* Returns: */ 1605 /* 0 on success, positive value on failure. */ 1606 /****************************************************************************/ 1607 static int 1608 bce_init_nvram(struct bce_softc *sc) 1609 { 1610 u32 val; 1611 int j, entry_count, rc; 1612 struct flash_spec *flash; 1613 1614 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Entering %s()\n", __FUNCTION__); 1615 1616 /* Determine the selected interface. */ 1617 val = REG_RD(sc, BCE_NVM_CFG1); 1618 1619 entry_count = sizeof(flash_table) / sizeof(struct flash_spec); 1620 1621 rc = 0; 1622 1623 /* 1624 * Flash reconfiguration is required to support additional 1625 * NVRAM devices not directly supported in hardware. 1626 * Check if the flash interface was reconfigured 1627 * by the bootcode. 1628 */ 1629 1630 if (val & 0x40000000) { 1631 /* Flash interface reconfigured by bootcode. */ 1632 1633 DBPRINT(sc,BCE_INFO_LOAD, 1634 "bce_init_nvram(): Flash WAS reconfigured.\n"); 1635 1636 for (j = 0, flash = &flash_table[0]; j < entry_count; 1637 j++, flash++) { 1638 if ((val & FLASH_BACKUP_STRAP_MASK) == 1639 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) { 1640 sc->bce_flash_info = flash; 1641 break; 1642 } 1643 } 1644 } else { 1645 /* Flash interface not yet reconfigured. */ 1646 u32 mask; 1647 1648 DBPRINT(sc,BCE_INFO_LOAD, 1649 "bce_init_nvram(): Flash was NOT reconfigured.\n"); 1650 1651 if (val & (1 << 23)) 1652 mask = FLASH_BACKUP_STRAP_MASK; 1653 else 1654 mask = FLASH_STRAP_MASK; 1655 1656 /* Look for the matching NVRAM device configuration data. */ 1657 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) { 1658 1659 /* Check if the device matches any of the known devices. */ 1660 if ((val & mask) == (flash->strapping & mask)) { 1661 /* Found a device match. */ 1662 sc->bce_flash_info = flash; 1663 1664 /* Request access to the flash interface. */ 1665 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1666 return rc; 1667 1668 /* Reconfigure the flash interface. */ 1669 bce_enable_nvram_access(sc); 1670 REG_WR(sc, BCE_NVM_CFG1, flash->config1); 1671 REG_WR(sc, BCE_NVM_CFG2, flash->config2); 1672 REG_WR(sc, BCE_NVM_CFG3, flash->config3); 1673 REG_WR(sc, BCE_NVM_WRITE1, flash->write1); 1674 bce_disable_nvram_access(sc); 1675 bce_release_nvram_lock(sc); 1676 1677 break; 1678 } 1679 } 1680 } 1681 1682 /* Check if a matching device was found. */ 1683 if (j == entry_count) { 1684 sc->bce_flash_info = NULL; 1685 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n", 1686 __FILE__, __LINE__); 1687 rc = ENODEV; 1688 } 1689 1690 /* Write the flash config data to the shared memory interface. */ 1691 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2); 1692 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK; 1693 if (val) 1694 sc->bce_flash_size = val; 1695 else 1696 sc->bce_flash_size = sc->bce_flash_info->total_size; 1697 1698 DBPRINT(sc, BCE_INFO_LOAD, "bce_init_nvram() flash->total_size = 0x%08X\n", 1699 sc->bce_flash_info->total_size); 1700 1701 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Exiting %s()\n", __FUNCTION__); 1702 1703 return rc; 1704 } 1705 1706 1707 /****************************************************************************/ 1708 /* Read an arbitrary range of data from NVRAM. */ 1709 /* */ 1710 /* Prepares the NVRAM interface for access and reads the requested data */ 1711 /* into the supplied buffer. */ 1712 /* */ 1713 /* Returns: */ 1714 /* 0 on success and the data read, positive value on failure. */ 1715 /****************************************************************************/ 1716 static int 1717 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf, 1718 int buf_size) 1719 { 1720 int rc = 0; 1721 u32 cmd_flags, offset32, len32, extra; 1722 1723 if (buf_size == 0) 1724 return 0; 1725 1726 /* Request access to the flash interface. */ 1727 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1728 return rc; 1729 1730 /* Enable access to flash interface */ 1731 bce_enable_nvram_access(sc); 1732 1733 len32 = buf_size; 1734 offset32 = offset; 1735 extra = 0; 1736 1737 cmd_flags = 0; 1738 1739 if (offset32 & 3) { 1740 u8 buf[4]; 1741 u32 pre_len; 1742 1743 offset32 &= ~3; 1744 pre_len = 4 - (offset & 3); 1745 1746 if (pre_len >= len32) { 1747 pre_len = len32; 1748 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST; 1749 } 1750 else { 1751 cmd_flags = BCE_NVM_COMMAND_FIRST; 1752 } 1753 1754 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1755 1756 if (rc) 1757 return rc; 1758 1759 memcpy(ret_buf, buf + (offset & 3), pre_len); 1760 1761 offset32 += 4; 1762 ret_buf += pre_len; 1763 len32 -= pre_len; 1764 } 1765 1766 if (len32 & 3) { 1767 extra = 4 - (len32 & 3); 1768 len32 = (len32 + 4) & ~3; 1769 } 1770 1771 if (len32 == 4) { 1772 u8 buf[4]; 1773 1774 if (cmd_flags) 1775 cmd_flags = BCE_NVM_COMMAND_LAST; 1776 else 1777 cmd_flags = BCE_NVM_COMMAND_FIRST | 1778 BCE_NVM_COMMAND_LAST; 1779 1780 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1781 1782 memcpy(ret_buf, buf, 4 - extra); 1783 } 1784 else if (len32 > 0) { 1785 u8 buf[4]; 1786 1787 /* Read the first word. */ 1788 if (cmd_flags) 1789 cmd_flags = 0; 1790 else 1791 cmd_flags = BCE_NVM_COMMAND_FIRST; 1792 1793 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags); 1794 1795 /* Advance to the next dword. */ 1796 offset32 += 4; 1797 ret_buf += 4; 1798 len32 -= 4; 1799 1800 while (len32 > 4 && rc == 0) { 1801 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0); 1802 1803 /* Advance to the next dword. */ 1804 offset32 += 4; 1805 ret_buf += 4; 1806 len32 -= 4; 1807 } 1808 1809 if (rc) 1810 return rc; 1811 1812 cmd_flags = BCE_NVM_COMMAND_LAST; 1813 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags); 1814 1815 memcpy(ret_buf, buf, 4 - extra); 1816 } 1817 1818 /* Disable access to flash interface and release the lock. */ 1819 bce_disable_nvram_access(sc); 1820 bce_release_nvram_lock(sc); 1821 1822 return rc; 1823 } 1824 1825 1826 #ifdef BCE_NVRAM_WRITE_SUPPORT 1827 /****************************************************************************/ 1828 /* Write an arbitrary range of data from NVRAM. */ 1829 /* */ 1830 /* Prepares the NVRAM interface for write access and writes the requested */ 1831 /* data from the supplied buffer. The caller is responsible for */ 1832 /* calculating any appropriate CRCs. */ 1833 /* */ 1834 /* Returns: */ 1835 /* 0 on success, positive value on failure. */ 1836 /****************************************************************************/ 1837 static int 1838 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf, 1839 int buf_size) 1840 { 1841 u32 written, offset32, len32; 1842 u8 *buf, start[4], end[4]; 1843 int rc = 0; 1844 int align_start, align_end; 1845 1846 buf = data_buf; 1847 offset32 = offset; 1848 len32 = buf_size; 1849 align_start = align_end = 0; 1850 1851 if ((align_start = (offset32 & 3))) { 1852 offset32 &= ~3; 1853 len32 += align_start; 1854 if ((rc = bce_nvram_read(sc, offset32, start, 4))) 1855 return rc; 1856 } 1857 1858 if (len32 & 3) { 1859 if ((len32 > 4) || !align_start) { 1860 align_end = 4 - (len32 & 3); 1861 len32 += align_end; 1862 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4, 1863 end, 4))) { 1864 return rc; 1865 } 1866 } 1867 } 1868 1869 if (align_start || align_end) { 1870 buf = malloc(len32, M_DEVBUF, M_NOWAIT); 1871 if (buf == 0) 1872 return ENOMEM; 1873 if (align_start) { 1874 memcpy(buf, start, 4); 1875 } 1876 if (align_end) { 1877 memcpy(buf + len32 - 4, end, 4); 1878 } 1879 memcpy(buf + align_start, data_buf, buf_size); 1880 } 1881 1882 written = 0; 1883 while ((written < len32) && (rc == 0)) { 1884 u32 page_start, page_end, data_start, data_end; 1885 u32 addr, cmd_flags; 1886 int i; 1887 u8 flash_buffer[264]; 1888 1889 /* Find the page_start addr */ 1890 page_start = offset32 + written; 1891 page_start -= (page_start % sc->bce_flash_info->page_size); 1892 /* Find the page_end addr */ 1893 page_end = page_start + sc->bce_flash_info->page_size; 1894 /* Find the data_start addr */ 1895 data_start = (written == 0) ? offset32 : page_start; 1896 /* Find the data_end addr */ 1897 data_end = (page_end > offset32 + len32) ? 1898 (offset32 + len32) : page_end; 1899 1900 /* Request access to the flash interface. */ 1901 if ((rc = bce_acquire_nvram_lock(sc)) != 0) 1902 goto nvram_write_end; 1903 1904 /* Enable access to flash interface */ 1905 bce_enable_nvram_access(sc); 1906 1907 cmd_flags = BCE_NVM_COMMAND_FIRST; 1908 if (sc->bce_flash_info->buffered == 0) { 1909 int j; 1910 1911 /* Read the whole page into the buffer 1912 * (non-buffer flash only) */ 1913 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) { 1914 if (j == (sc->bce_flash_info->page_size - 4)) { 1915 cmd_flags |= BCE_NVM_COMMAND_LAST; 1916 } 1917 rc = bce_nvram_read_dword(sc, 1918 page_start + j, 1919 &flash_buffer[j], 1920 cmd_flags); 1921 1922 if (rc) 1923 goto nvram_write_end; 1924 1925 cmd_flags = 0; 1926 } 1927 } 1928 1929 /* Enable writes to flash interface (unlock write-protect) */ 1930 if ((rc = bce_enable_nvram_write(sc)) != 0) 1931 goto nvram_write_end; 1932 1933 /* Erase the page */ 1934 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0) 1935 goto nvram_write_end; 1936 1937 /* Re-enable the write again for the actual write */ 1938 bce_enable_nvram_write(sc); 1939 1940 /* Loop to write back the buffer data from page_start to 1941 * data_start */ 1942 i = 0; 1943 if (sc->bce_flash_info->buffered == 0) { 1944 for (addr = page_start; addr < data_start; 1945 addr += 4, i += 4) { 1946 1947 rc = bce_nvram_write_dword(sc, addr, 1948 &flash_buffer[i], cmd_flags); 1949 1950 if (rc != 0) 1951 goto nvram_write_end; 1952 1953 cmd_flags = 0; 1954 } 1955 } 1956 1957 /* Loop to write the new data from data_start to data_end */ 1958 for (addr = data_start; addr < data_end; addr += 4, i++) { 1959 if ((addr == page_end - 4) || 1960 ((sc->bce_flash_info->buffered) && 1961 (addr == data_end - 4))) { 1962 1963 cmd_flags |= BCE_NVM_COMMAND_LAST; 1964 } 1965 rc = bce_nvram_write_dword(sc, addr, buf, 1966 cmd_flags); 1967 1968 if (rc != 0) 1969 goto nvram_write_end; 1970 1971 cmd_flags = 0; 1972 buf += 4; 1973 } 1974 1975 /* Loop to write back the buffer data from data_end 1976 * to page_end */ 1977 if (sc->bce_flash_info->buffered == 0) { 1978 for (addr = data_end; addr < page_end; 1979 addr += 4, i += 4) { 1980 1981 if (addr == page_end-4) { 1982 cmd_flags = BCE_NVM_COMMAND_LAST; 1983 } 1984 rc = bce_nvram_write_dword(sc, addr, 1985 &flash_buffer[i], cmd_flags); 1986 1987 if (rc != 0) 1988 goto nvram_write_end; 1989 1990 cmd_flags = 0; 1991 } 1992 } 1993 1994 /* Disable writes to flash interface (lock write-protect) */ 1995 bce_disable_nvram_write(sc); 1996 1997 /* Disable access to flash interface */ 1998 bce_disable_nvram_access(sc); 1999 bce_release_nvram_lock(sc); 2000 2001 /* Increment written */ 2002 written += data_end - data_start; 2003 } 2004 2005 nvram_write_end: 2006 if (align_start || align_end) 2007 free(buf, M_DEVBUF); 2008 2009 return rc; 2010 } 2011 #endif /* BCE_NVRAM_WRITE_SUPPORT */ 2012 2013 2014 /****************************************************************************/ 2015 /* Verifies that NVRAM is accessible and contains valid data. */ 2016 /* */ 2017 /* Reads the configuration data from NVRAM and verifies that the CRC is */ 2018 /* correct. */ 2019 /* */ 2020 /* Returns: */ 2021 /* 0 on success, positive value on failure. */ 2022 /****************************************************************************/ 2023 static int 2024 bce_nvram_test(struct bce_softc *sc) 2025 { 2026 u32 buf[BCE_NVRAM_SIZE / 4]; 2027 u8 *data = (u8 *) buf; 2028 int rc = 0; 2029 u32 magic, csum; 2030 2031 2032 /* 2033 * Check that the device NVRAM is valid by reading 2034 * the magic value at offset 0. 2035 */ 2036 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) 2037 goto bce_nvram_test_done; 2038 2039 2040 magic = bce_be32toh(buf[0]); 2041 if (magic != BCE_NVRAM_MAGIC) { 2042 rc = ENODEV; 2043 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, " 2044 "Found: 0x%08X\n", 2045 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic); 2046 goto bce_nvram_test_done; 2047 } 2048 2049 /* 2050 * Verify that the device NVRAM includes valid 2051 * configuration data. 2052 */ 2053 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) 2054 goto bce_nvram_test_done; 2055 2056 csum = ether_crc32_le(data, 0x100); 2057 if (csum != BCE_CRC32_RESIDUAL) { 2058 rc = ENODEV; 2059 BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! " 2060 "Expected: 0x%08X, Found: 0x%08X\n", 2061 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2062 goto bce_nvram_test_done; 2063 } 2064 2065 csum = ether_crc32_le(data + 0x100, 0x100); 2066 if (csum != BCE_CRC32_RESIDUAL) { 2067 BCE_PRINTF("%s(%d): Invalid Feature Configuration Information " 2068 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n", 2069 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum); 2070 rc = ENODEV; 2071 } 2072 2073 bce_nvram_test_done: 2074 return rc; 2075 } 2076 2077 2078 /****************************************************************************/ 2079 /* Free any DMA memory owned by the driver. */ 2080 /* */ 2081 /* Scans through each data structre that requires DMA memory and frees */ 2082 /* the memory if allocated. */ 2083 /* */ 2084 /* Returns: */ 2085 /* Nothing. */ 2086 /****************************************************************************/ 2087 static void 2088 bce_dma_free(struct bce_softc *sc) 2089 { 2090 int i; 2091 2092 DBPRINT(sc,BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2093 2094 /* Destroy the status block. */ 2095 if (sc->status_block != NULL) 2096 bus_dmamem_free( 2097 sc->status_tag, 2098 sc->status_block, 2099 sc->status_map); 2100 2101 if (sc->status_map != NULL) { 2102 bus_dmamap_unload( 2103 sc->status_tag, 2104 sc->status_map); 2105 bus_dmamap_destroy(sc->status_tag, 2106 sc->status_map); 2107 } 2108 2109 if (sc->status_tag != NULL) 2110 bus_dma_tag_destroy(sc->status_tag); 2111 2112 2113 /* Destroy the statistics block. */ 2114 if (sc->stats_block != NULL) 2115 bus_dmamem_free( 2116 sc->stats_tag, 2117 sc->stats_block, 2118 sc->stats_map); 2119 2120 if (sc->stats_map != NULL) { 2121 bus_dmamap_unload( 2122 sc->stats_tag, 2123 sc->stats_map); 2124 bus_dmamap_destroy(sc->stats_tag, 2125 sc->stats_map); 2126 } 2127 2128 if (sc->stats_tag != NULL) 2129 bus_dma_tag_destroy(sc->stats_tag); 2130 2131 2132 /* Free, unmap and destroy all TX buffer descriptor chain pages. */ 2133 for (i = 0; i < TX_PAGES; i++ ) { 2134 if (sc->tx_bd_chain[i] != NULL) 2135 bus_dmamem_free( 2136 sc->tx_bd_chain_tag, 2137 sc->tx_bd_chain[i], 2138 sc->tx_bd_chain_map[i]); 2139 2140 if (sc->tx_bd_chain_map[i] != NULL) { 2141 bus_dmamap_unload( 2142 sc->tx_bd_chain_tag, 2143 sc->tx_bd_chain_map[i]); 2144 bus_dmamap_destroy( 2145 sc->tx_bd_chain_tag, 2146 sc->tx_bd_chain_map[i]); 2147 } 2148 2149 } 2150 2151 /* Destroy the TX buffer descriptor tag. */ 2152 if (sc->tx_bd_chain_tag != NULL) 2153 bus_dma_tag_destroy(sc->tx_bd_chain_tag); 2154 2155 2156 /* Free, unmap and destroy all RX buffer descriptor chain pages. */ 2157 for (i = 0; i < RX_PAGES; i++ ) { 2158 if (sc->rx_bd_chain[i] != NULL) 2159 bus_dmamem_free( 2160 sc->rx_bd_chain_tag, 2161 sc->rx_bd_chain[i], 2162 sc->rx_bd_chain_map[i]); 2163 2164 if (sc->rx_bd_chain_map[i] != NULL) { 2165 bus_dmamap_unload( 2166 sc->rx_bd_chain_tag, 2167 sc->rx_bd_chain_map[i]); 2168 bus_dmamap_destroy( 2169 sc->rx_bd_chain_tag, 2170 sc->rx_bd_chain_map[i]); 2171 } 2172 } 2173 2174 /* Destroy the RX buffer descriptor tag. */ 2175 if (sc->rx_bd_chain_tag != NULL) 2176 bus_dma_tag_destroy(sc->rx_bd_chain_tag); 2177 2178 2179 /* Unload and destroy the TX mbuf maps. */ 2180 for (i = 0; i < TOTAL_TX_BD; i++) { 2181 if (sc->tx_mbuf_map[i] != NULL) { 2182 bus_dmamap_unload(sc->tx_mbuf_tag, 2183 sc->tx_mbuf_map[i]); 2184 bus_dmamap_destroy(sc->tx_mbuf_tag, 2185 sc->tx_mbuf_map[i]); 2186 } 2187 } 2188 2189 /* Destroy the TX mbuf tag. */ 2190 if (sc->tx_mbuf_tag != NULL) 2191 bus_dma_tag_destroy(sc->tx_mbuf_tag); 2192 2193 2194 /* Unload and destroy the RX mbuf maps. */ 2195 for (i = 0; i < TOTAL_RX_BD; i++) { 2196 if (sc->rx_mbuf_map[i] != NULL) { 2197 bus_dmamap_unload(sc->rx_mbuf_tag, 2198 sc->rx_mbuf_map[i]); 2199 bus_dmamap_destroy(sc->rx_mbuf_tag, 2200 sc->rx_mbuf_map[i]); 2201 } 2202 } 2203 2204 /* Destroy the RX mbuf tag. */ 2205 if (sc->rx_mbuf_tag != NULL) 2206 bus_dma_tag_destroy(sc->rx_mbuf_tag); 2207 2208 2209 /* Destroy the parent tag */ 2210 if (sc->parent_tag != NULL) 2211 bus_dma_tag_destroy(sc->parent_tag); 2212 2213 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2214 2215 } 2216 2217 2218 /****************************************************************************/ 2219 /* Get DMA memory from the OS. */ 2220 /* */ 2221 /* Validates that the OS has provided DMA buffers in response to a */ 2222 /* bus_dmamap_load() call and saves the physical address of those buffers. */ 2223 /* When the callback is used the OS will return 0 for the mapping function */ 2224 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */ 2225 /* failures back to the caller. */ 2226 /* */ 2227 /* Returns: */ 2228 /* Nothing. */ 2229 /****************************************************************************/ 2230 static void 2231 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2232 { 2233 bus_addr_t *busaddr = arg; 2234 2235 /* Simulate a mapping failure. */ 2236 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure), 2237 printf("bce: %s(%d): Simulating DMA mapping error.\n", 2238 __FILE__, __LINE__); 2239 error = ENOMEM); 2240 2241 /* Check for an error and signal the caller that an error occurred. */ 2242 if (error) { 2243 printf("bce %s(%d): DMA mapping error! error = %d, " 2244 "nseg = %d\n", __FILE__, __LINE__, error, nseg); 2245 *busaddr = 0; 2246 return; 2247 } 2248 2249 *busaddr = segs->ds_addr; 2250 return; 2251 } 2252 2253 2254 /****************************************************************************/ 2255 /* Allocate any DMA memory needed by the driver. */ 2256 /* */ 2257 /* Allocates DMA memory needed for the various global structures needed by */ 2258 /* hardware. */ 2259 /* */ 2260 /* Returns: */ 2261 /* 0 for success, positive value for failure. */ 2262 /****************************************************************************/ 2263 static int 2264 bce_dma_alloc(device_t dev) 2265 { 2266 struct bce_softc *sc; 2267 int i, error, rc = 0; 2268 bus_addr_t busaddr; 2269 bus_size_t max_size, max_seg_size; 2270 int max_segments; 2271 2272 sc = device_get_softc(dev); 2273 2274 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2275 2276 /* 2277 * Allocate the parent bus DMA tag appropriate for PCI. 2278 */ 2279 if (bus_dma_tag_create(NULL, 2280 1, 2281 BCE_DMA_BOUNDARY, 2282 sc->max_bus_addr, 2283 BUS_SPACE_MAXADDR, 2284 NULL, NULL, 2285 MAXBSIZE, 2286 BUS_SPACE_UNRESTRICTED, 2287 BUS_SPACE_MAXSIZE_32BIT, 2288 0, 2289 NULL, NULL, 2290 &sc->parent_tag)) { 2291 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n", 2292 __FILE__, __LINE__); 2293 rc = ENOMEM; 2294 goto bce_dma_alloc_exit; 2295 } 2296 2297 /* 2298 * Create a DMA tag for the status block, allocate and clear the 2299 * memory, map the memory into DMA space, and fetch the physical 2300 * address of the block. 2301 */ 2302 if (bus_dma_tag_create(sc->parent_tag, 2303 BCE_DMA_ALIGN, 2304 BCE_DMA_BOUNDARY, 2305 sc->max_bus_addr, 2306 BUS_SPACE_MAXADDR, 2307 NULL, NULL, 2308 BCE_STATUS_BLK_SZ, 2309 1, 2310 BCE_STATUS_BLK_SZ, 2311 0, 2312 NULL, NULL, 2313 &sc->status_tag)) { 2314 BCE_PRINTF("%s(%d): Could not allocate status block DMA tag!\n", 2315 __FILE__, __LINE__); 2316 rc = ENOMEM; 2317 goto bce_dma_alloc_exit; 2318 } 2319 2320 if(bus_dmamem_alloc(sc->status_tag, 2321 (void **)&sc->status_block, 2322 BUS_DMA_NOWAIT, 2323 &sc->status_map)) { 2324 BCE_PRINTF("%s(%d): Could not allocate status block DMA memory!\n", 2325 __FILE__, __LINE__); 2326 rc = ENOMEM; 2327 goto bce_dma_alloc_exit; 2328 } 2329 2330 bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ); 2331 2332 error = bus_dmamap_load(sc->status_tag, 2333 sc->status_map, 2334 sc->status_block, 2335 BCE_STATUS_BLK_SZ, 2336 bce_dma_map_addr, 2337 &busaddr, 2338 BUS_DMA_NOWAIT); 2339 2340 if (error) { 2341 BCE_PRINTF("%s(%d): Could not map status block DMA memory!\n", 2342 __FILE__, __LINE__); 2343 rc = ENOMEM; 2344 goto bce_dma_alloc_exit; 2345 } 2346 2347 sc->status_block_paddr = busaddr; 2348 /* DRC - Fix for 64 bit addresses. */ 2349 DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n", 2350 (u32) sc->status_block_paddr); 2351 2352 /* 2353 * Create a DMA tag for the statistics block, allocate and clear the 2354 * memory, map the memory into DMA space, and fetch the physical 2355 * address of the block. 2356 */ 2357 if (bus_dma_tag_create(sc->parent_tag, 2358 BCE_DMA_ALIGN, 2359 BCE_DMA_BOUNDARY, 2360 sc->max_bus_addr, 2361 BUS_SPACE_MAXADDR, 2362 NULL, NULL, 2363 BCE_STATS_BLK_SZ, 2364 1, 2365 BCE_STATS_BLK_SZ, 2366 0, 2367 NULL, NULL, 2368 &sc->stats_tag)) { 2369 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA tag!\n", 2370 __FILE__, __LINE__); 2371 rc = ENOMEM; 2372 goto bce_dma_alloc_exit; 2373 } 2374 2375 if (bus_dmamem_alloc(sc->stats_tag, 2376 (void **)&sc->stats_block, 2377 BUS_DMA_NOWAIT, 2378 &sc->stats_map)) { 2379 BCE_PRINTF("%s(%d): Could not allocate statistics block DMA memory!\n", 2380 __FILE__, __LINE__); 2381 rc = ENOMEM; 2382 goto bce_dma_alloc_exit; 2383 } 2384 2385 bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ); 2386 2387 error = bus_dmamap_load(sc->stats_tag, 2388 sc->stats_map, 2389 sc->stats_block, 2390 BCE_STATS_BLK_SZ, 2391 bce_dma_map_addr, 2392 &busaddr, 2393 BUS_DMA_NOWAIT); 2394 2395 if(error) { 2396 BCE_PRINTF("%s(%d): Could not map statistics block DMA memory!\n", 2397 __FILE__, __LINE__); 2398 rc = ENOMEM; 2399 goto bce_dma_alloc_exit; 2400 } 2401 2402 sc->stats_block_paddr = busaddr; 2403 /* DRC - Fix for 64 bit address. */ 2404 DBPRINT(sc,BCE_INFO, "stats_block_paddr = 0x%08X\n", 2405 (u32) sc->stats_block_paddr); 2406 2407 /* 2408 * Create a DMA tag for the TX buffer descriptor chain, 2409 * allocate and clear the memory, and fetch the 2410 * physical address of the block. 2411 */ 2412 if(bus_dma_tag_create(sc->parent_tag, 2413 BCM_PAGE_SIZE, 2414 BCE_DMA_BOUNDARY, 2415 sc->max_bus_addr, 2416 BUS_SPACE_MAXADDR, 2417 NULL, NULL, 2418 BCE_TX_CHAIN_PAGE_SZ, 2419 1, 2420 BCE_TX_CHAIN_PAGE_SZ, 2421 0, 2422 NULL, NULL, 2423 &sc->tx_bd_chain_tag)) { 2424 BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain DMA tag!\n", 2425 __FILE__, __LINE__); 2426 rc = ENOMEM; 2427 goto bce_dma_alloc_exit; 2428 } 2429 2430 for (i = 0; i < TX_PAGES; i++) { 2431 2432 if(bus_dmamem_alloc(sc->tx_bd_chain_tag, 2433 (void **)&sc->tx_bd_chain[i], 2434 BUS_DMA_NOWAIT, 2435 &sc->tx_bd_chain_map[i])) { 2436 BCE_PRINTF("%s(%d): Could not allocate TX descriptor " 2437 "chain DMA memory!\n", __FILE__, __LINE__); 2438 rc = ENOMEM; 2439 goto bce_dma_alloc_exit; 2440 } 2441 2442 error = bus_dmamap_load(sc->tx_bd_chain_tag, 2443 sc->tx_bd_chain_map[i], 2444 sc->tx_bd_chain[i], 2445 BCE_TX_CHAIN_PAGE_SZ, 2446 bce_dma_map_addr, 2447 &busaddr, 2448 BUS_DMA_NOWAIT); 2449 2450 if (error) { 2451 BCE_PRINTF("%s(%d): Could not map TX descriptor chain DMA memory!\n", 2452 __FILE__, __LINE__); 2453 rc = ENOMEM; 2454 goto bce_dma_alloc_exit; 2455 } 2456 2457 sc->tx_bd_chain_paddr[i] = busaddr; 2458 /* DRC - Fix for 64 bit systems. */ 2459 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 2460 i, (u32) sc->tx_bd_chain_paddr[i]); 2461 } 2462 2463 /* Check the required size before mapping to conserve resources. */ 2464 if (bce_tso_enable) { 2465 max_size = BCE_TSO_MAX_SIZE; 2466 max_segments = BCE_MAX_SEGMENTS; 2467 max_seg_size = BCE_TSO_MAX_SEG_SIZE; 2468 } else { 2469 max_size = MCLBYTES * BCE_MAX_SEGMENTS; 2470 max_segments = BCE_MAX_SEGMENTS; 2471 max_seg_size = MCLBYTES; 2472 } 2473 2474 /* Create a DMA tag for TX mbufs. */ 2475 if (bus_dma_tag_create(sc->parent_tag, 2476 1, 2477 BCE_DMA_BOUNDARY, 2478 sc->max_bus_addr, 2479 BUS_SPACE_MAXADDR, 2480 NULL, NULL, 2481 max_size, 2482 max_segments, 2483 max_seg_size, 2484 0, 2485 NULL, NULL, 2486 &sc->tx_mbuf_tag)) { 2487 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n", 2488 __FILE__, __LINE__); 2489 rc = ENOMEM; 2490 goto bce_dma_alloc_exit; 2491 } 2492 2493 /* Create DMA maps for the TX mbufs clusters. */ 2494 for (i = 0; i < TOTAL_TX_BD; i++) { 2495 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT, 2496 &sc->tx_mbuf_map[i])) { 2497 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA map!\n", 2498 __FILE__, __LINE__); 2499 rc = ENOMEM; 2500 goto bce_dma_alloc_exit; 2501 } 2502 } 2503 2504 /* 2505 * Create a DMA tag for the RX buffer descriptor chain, 2506 * allocate and clear the memory, and fetch the physical 2507 * address of the blocks. 2508 */ 2509 if (bus_dma_tag_create(sc->parent_tag, 2510 BCM_PAGE_SIZE, 2511 BCE_DMA_BOUNDARY, 2512 BUS_SPACE_MAXADDR, 2513 sc->max_bus_addr, 2514 NULL, NULL, 2515 BCE_RX_CHAIN_PAGE_SZ, 2516 1, 2517 BCE_RX_CHAIN_PAGE_SZ, 2518 0, 2519 NULL, NULL, 2520 &sc->rx_bd_chain_tag)) { 2521 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain DMA tag!\n", 2522 __FILE__, __LINE__); 2523 rc = ENOMEM; 2524 goto bce_dma_alloc_exit; 2525 } 2526 2527 for (i = 0; i < RX_PAGES; i++) { 2528 2529 if (bus_dmamem_alloc(sc->rx_bd_chain_tag, 2530 (void **)&sc->rx_bd_chain[i], 2531 BUS_DMA_NOWAIT, 2532 &sc->rx_bd_chain_map[i])) { 2533 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain " 2534 "DMA memory!\n", __FILE__, __LINE__); 2535 rc = ENOMEM; 2536 goto bce_dma_alloc_exit; 2537 } 2538 2539 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 2540 2541 error = bus_dmamap_load(sc->rx_bd_chain_tag, 2542 sc->rx_bd_chain_map[i], 2543 sc->rx_bd_chain[i], 2544 BCE_RX_CHAIN_PAGE_SZ, 2545 bce_dma_map_addr, 2546 &busaddr, 2547 BUS_DMA_NOWAIT); 2548 2549 if (error) { 2550 BCE_PRINTF("%s(%d): Could not map RX descriptor chain DMA memory!\n", 2551 __FILE__, __LINE__); 2552 rc = ENOMEM; 2553 goto bce_dma_alloc_exit; 2554 } 2555 2556 sc->rx_bd_chain_paddr[i] = busaddr; 2557 /* DRC - Fix for 64 bit systems. */ 2558 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", 2559 i, (u32) sc->rx_bd_chain_paddr[i]); 2560 } 2561 2562 /* 2563 * Create a DMA tag for RX mbufs. 2564 */ 2565 if (bus_dma_tag_create(sc->parent_tag, 2566 1, 2567 BCE_DMA_BOUNDARY, 2568 sc->max_bus_addr, 2569 BUS_SPACE_MAXADDR, 2570 NULL, NULL, 2571 MJUM9BYTES, 2572 BCE_MAX_SEGMENTS, 2573 MJUM9BYTES, 2574 0, 2575 NULL, NULL, 2576 &sc->rx_mbuf_tag)) { 2577 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n", 2578 __FILE__, __LINE__); 2579 rc = ENOMEM; 2580 goto bce_dma_alloc_exit; 2581 } 2582 2583 /* Create DMA maps for the RX mbuf clusters. */ 2584 for (i = 0; i < TOTAL_RX_BD; i++) { 2585 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT, 2586 &sc->rx_mbuf_map[i])) { 2587 BCE_PRINTF("%s(%d): Unable to create RX mbuf DMA map!\n", 2588 __FILE__, __LINE__); 2589 rc = ENOMEM; 2590 goto bce_dma_alloc_exit; 2591 } 2592 } 2593 2594 bce_dma_alloc_exit: 2595 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2596 2597 return(rc); 2598 } 2599 2600 2601 /****************************************************************************/ 2602 /* Release all resources used by the driver. */ 2603 /* */ 2604 /* Releases all resources acquired by the driver including interrupts, */ 2605 /* interrupt handler, interfaces, mutexes, and DMA memory. */ 2606 /* */ 2607 /* Returns: */ 2608 /* Nothing. */ 2609 /****************************************************************************/ 2610 static void 2611 bce_release_resources(struct bce_softc *sc) 2612 { 2613 device_t dev; 2614 2615 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 2616 2617 dev = sc->bce_dev; 2618 2619 bce_dma_free(sc); 2620 2621 if (sc->bce_intrhand != NULL) { 2622 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n"); 2623 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand); 2624 } 2625 2626 if (sc->bce_res_irq != NULL) { 2627 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n"); 2628 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0, 2629 sc->bce_res_irq); 2630 } 2631 2632 if (sc->bce_flags & BCE_USING_MSI_FLAG) { 2633 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI vector.\n"); 2634 pci_release_msi(dev); 2635 } 2636 2637 if (sc->bce_res_mem != NULL) { 2638 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n"); 2639 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bce_res_mem); 2640 } 2641 2642 if (sc->bce_ifp != NULL) { 2643 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n"); 2644 if_free(sc->bce_ifp); 2645 } 2646 2647 if (mtx_initialized(&sc->bce_mtx)) 2648 BCE_LOCK_DESTROY(sc); 2649 2650 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 2651 2652 } 2653 2654 2655 /****************************************************************************/ 2656 /* Firmware synchronization. */ 2657 /* */ 2658 /* Before performing certain events such as a chip reset, synchronize with */ 2659 /* the firmware first. */ 2660 /* */ 2661 /* Returns: */ 2662 /* 0 for success, positive value for failure. */ 2663 /****************************************************************************/ 2664 static int 2665 bce_fw_sync(struct bce_softc *sc, u32 msg_data) 2666 { 2667 int i, rc = 0; 2668 u32 val; 2669 2670 /* Don't waste any time if we've timed out before. */ 2671 if (sc->bce_fw_timed_out) { 2672 rc = EBUSY; 2673 goto bce_fw_sync_exit; 2674 } 2675 2676 /* Increment the message sequence number. */ 2677 sc->bce_fw_wr_seq++; 2678 msg_data |= sc->bce_fw_wr_seq; 2679 2680 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data); 2681 2682 /* Send the message to the bootcode driver mailbox. */ 2683 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2684 2685 /* Wait for the bootcode to acknowledge the message. */ 2686 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) { 2687 /* Check for a response in the bootcode firmware mailbox. */ 2688 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB); 2689 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ)) 2690 break; 2691 DELAY(1000); 2692 } 2693 2694 /* If we've timed out, tell the bootcode that we've stopped waiting. */ 2695 if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) && 2696 ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) { 2697 2698 BCE_PRINTF("%s(%d): Firmware synchronization timeout! " 2699 "msg_data = 0x%08X\n", 2700 __FILE__, __LINE__, msg_data); 2701 2702 msg_data &= ~BCE_DRV_MSG_CODE; 2703 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT; 2704 2705 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data); 2706 2707 sc->bce_fw_timed_out = 1; 2708 rc = EBUSY; 2709 } 2710 2711 bce_fw_sync_exit: 2712 return (rc); 2713 } 2714 2715 2716 /****************************************************************************/ 2717 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */ 2718 /* */ 2719 /* Returns: */ 2720 /* Nothing. */ 2721 /****************************************************************************/ 2722 static void 2723 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code, 2724 u32 rv2p_code_len, u32 rv2p_proc) 2725 { 2726 int i; 2727 u32 val; 2728 2729 for (i = 0; i < rv2p_code_len; i += 8) { 2730 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code); 2731 rv2p_code++; 2732 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code); 2733 rv2p_code++; 2734 2735 if (rv2p_proc == RV2P_PROC1) { 2736 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR; 2737 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val); 2738 } 2739 else { 2740 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR; 2741 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val); 2742 } 2743 } 2744 2745 /* Reset the processor, un-stall is done later. */ 2746 if (rv2p_proc == RV2P_PROC1) { 2747 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET); 2748 } 2749 else { 2750 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET); 2751 } 2752 } 2753 2754 2755 /****************************************************************************/ 2756 /* Load RISC processor firmware. */ 2757 /* */ 2758 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */ 2759 /* associated with a particular processor. */ 2760 /* */ 2761 /* Returns: */ 2762 /* Nothing. */ 2763 /****************************************************************************/ 2764 static void 2765 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg, 2766 struct fw_info *fw) 2767 { 2768 u32 offset; 2769 u32 val; 2770 2771 /* Halt the CPU. */ 2772 val = REG_RD_IND(sc, cpu_reg->mode); 2773 val |= cpu_reg->mode_value_halt; 2774 REG_WR_IND(sc, cpu_reg->mode, val); 2775 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2776 2777 /* Load the Text area. */ 2778 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); 2779 if (fw->text) { 2780 int j; 2781 2782 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { 2783 REG_WR_IND(sc, offset, fw->text[j]); 2784 } 2785 } 2786 2787 /* Load the Data area. */ 2788 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); 2789 if (fw->data) { 2790 int j; 2791 2792 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { 2793 REG_WR_IND(sc, offset, fw->data[j]); 2794 } 2795 } 2796 2797 /* Load the SBSS area. */ 2798 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); 2799 if (fw->sbss) { 2800 int j; 2801 2802 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { 2803 REG_WR_IND(sc, offset, fw->sbss[j]); 2804 } 2805 } 2806 2807 /* Load the BSS area. */ 2808 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); 2809 if (fw->bss) { 2810 int j; 2811 2812 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { 2813 REG_WR_IND(sc, offset, fw->bss[j]); 2814 } 2815 } 2816 2817 /* Load the Read-Only area. */ 2818 offset = cpu_reg->spad_base + 2819 (fw->rodata_addr - cpu_reg->mips_view_base); 2820 if (fw->rodata) { 2821 int j; 2822 2823 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { 2824 REG_WR_IND(sc, offset, fw->rodata[j]); 2825 } 2826 } 2827 2828 /* Clear the pre-fetch instruction. */ 2829 REG_WR_IND(sc, cpu_reg->inst, 0); 2830 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr); 2831 2832 /* Start the CPU. */ 2833 val = REG_RD_IND(sc, cpu_reg->mode); 2834 val &= ~cpu_reg->mode_value_halt; 2835 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear); 2836 REG_WR_IND(sc, cpu_reg->mode, val); 2837 } 2838 2839 2840 /****************************************************************************/ 2841 /* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */ 2842 /* */ 2843 /* Loads the firmware for each CPU and starts the CPU. */ 2844 /* */ 2845 /* Returns: */ 2846 /* Nothing. */ 2847 /****************************************************************************/ 2848 static void 2849 bce_init_cpus(struct bce_softc *sc) 2850 { 2851 struct cpu_reg cpu_reg; 2852 struct fw_info fw; 2853 2854 /* Initialize the RV2P processor. */ 2855 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1); 2856 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2); 2857 2858 /* Initialize the RX Processor. */ 2859 cpu_reg.mode = BCE_RXP_CPU_MODE; 2860 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT; 2861 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA; 2862 cpu_reg.state = BCE_RXP_CPU_STATE; 2863 cpu_reg.state_value_clear = 0xffffff; 2864 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE; 2865 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK; 2866 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER; 2867 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION; 2868 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT; 2869 cpu_reg.spad_base = BCE_RXP_SCRATCH; 2870 cpu_reg.mips_view_base = 0x8000000; 2871 2872 fw.ver_major = bce_RXP_b06FwReleaseMajor; 2873 fw.ver_minor = bce_RXP_b06FwReleaseMinor; 2874 fw.ver_fix = bce_RXP_b06FwReleaseFix; 2875 fw.start_addr = bce_RXP_b06FwStartAddr; 2876 2877 fw.text_addr = bce_RXP_b06FwTextAddr; 2878 fw.text_len = bce_RXP_b06FwTextLen; 2879 fw.text_index = 0; 2880 fw.text = bce_RXP_b06FwText; 2881 2882 fw.data_addr = bce_RXP_b06FwDataAddr; 2883 fw.data_len = bce_RXP_b06FwDataLen; 2884 fw.data_index = 0; 2885 fw.data = bce_RXP_b06FwData; 2886 2887 fw.sbss_addr = bce_RXP_b06FwSbssAddr; 2888 fw.sbss_len = bce_RXP_b06FwSbssLen; 2889 fw.sbss_index = 0; 2890 fw.sbss = bce_RXP_b06FwSbss; 2891 2892 fw.bss_addr = bce_RXP_b06FwBssAddr; 2893 fw.bss_len = bce_RXP_b06FwBssLen; 2894 fw.bss_index = 0; 2895 fw.bss = bce_RXP_b06FwBss; 2896 2897 fw.rodata_addr = bce_RXP_b06FwRodataAddr; 2898 fw.rodata_len = bce_RXP_b06FwRodataLen; 2899 fw.rodata_index = 0; 2900 fw.rodata = bce_RXP_b06FwRodata; 2901 2902 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n"); 2903 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2904 2905 /* Initialize the TX Processor. */ 2906 cpu_reg.mode = BCE_TXP_CPU_MODE; 2907 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT; 2908 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA; 2909 cpu_reg.state = BCE_TXP_CPU_STATE; 2910 cpu_reg.state_value_clear = 0xffffff; 2911 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE; 2912 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK; 2913 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER; 2914 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION; 2915 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT; 2916 cpu_reg.spad_base = BCE_TXP_SCRATCH; 2917 cpu_reg.mips_view_base = 0x8000000; 2918 2919 fw.ver_major = bce_TXP_b06FwReleaseMajor; 2920 fw.ver_minor = bce_TXP_b06FwReleaseMinor; 2921 fw.ver_fix = bce_TXP_b06FwReleaseFix; 2922 fw.start_addr = bce_TXP_b06FwStartAddr; 2923 2924 fw.text_addr = bce_TXP_b06FwTextAddr; 2925 fw.text_len = bce_TXP_b06FwTextLen; 2926 fw.text_index = 0; 2927 fw.text = bce_TXP_b06FwText; 2928 2929 fw.data_addr = bce_TXP_b06FwDataAddr; 2930 fw.data_len = bce_TXP_b06FwDataLen; 2931 fw.data_index = 0; 2932 fw.data = bce_TXP_b06FwData; 2933 2934 fw.sbss_addr = bce_TXP_b06FwSbssAddr; 2935 fw.sbss_len = bce_TXP_b06FwSbssLen; 2936 fw.sbss_index = 0; 2937 fw.sbss = bce_TXP_b06FwSbss; 2938 2939 fw.bss_addr = bce_TXP_b06FwBssAddr; 2940 fw.bss_len = bce_TXP_b06FwBssLen; 2941 fw.bss_index = 0; 2942 fw.bss = bce_TXP_b06FwBss; 2943 2944 fw.rodata_addr = bce_TXP_b06FwRodataAddr; 2945 fw.rodata_len = bce_TXP_b06FwRodataLen; 2946 fw.rodata_index = 0; 2947 fw.rodata = bce_TXP_b06FwRodata; 2948 2949 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n"); 2950 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2951 2952 /* Initialize the TX Patch-up Processor. */ 2953 cpu_reg.mode = BCE_TPAT_CPU_MODE; 2954 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT; 2955 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA; 2956 cpu_reg.state = BCE_TPAT_CPU_STATE; 2957 cpu_reg.state_value_clear = 0xffffff; 2958 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE; 2959 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK; 2960 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER; 2961 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION; 2962 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT; 2963 cpu_reg.spad_base = BCE_TPAT_SCRATCH; 2964 cpu_reg.mips_view_base = 0x8000000; 2965 2966 fw.ver_major = bce_TPAT_b06FwReleaseMajor; 2967 fw.ver_minor = bce_TPAT_b06FwReleaseMinor; 2968 fw.ver_fix = bce_TPAT_b06FwReleaseFix; 2969 fw.start_addr = bce_TPAT_b06FwStartAddr; 2970 2971 fw.text_addr = bce_TPAT_b06FwTextAddr; 2972 fw.text_len = bce_TPAT_b06FwTextLen; 2973 fw.text_index = 0; 2974 fw.text = bce_TPAT_b06FwText; 2975 2976 fw.data_addr = bce_TPAT_b06FwDataAddr; 2977 fw.data_len = bce_TPAT_b06FwDataLen; 2978 fw.data_index = 0; 2979 fw.data = bce_TPAT_b06FwData; 2980 2981 fw.sbss_addr = bce_TPAT_b06FwSbssAddr; 2982 fw.sbss_len = bce_TPAT_b06FwSbssLen; 2983 fw.sbss_index = 0; 2984 fw.sbss = bce_TPAT_b06FwSbss; 2985 2986 fw.bss_addr = bce_TPAT_b06FwBssAddr; 2987 fw.bss_len = bce_TPAT_b06FwBssLen; 2988 fw.bss_index = 0; 2989 fw.bss = bce_TPAT_b06FwBss; 2990 2991 fw.rodata_addr = bce_TPAT_b06FwRodataAddr; 2992 fw.rodata_len = bce_TPAT_b06FwRodataLen; 2993 fw.rodata_index = 0; 2994 fw.rodata = bce_TPAT_b06FwRodata; 2995 2996 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n"); 2997 bce_load_cpu_fw(sc, &cpu_reg, &fw); 2998 2999 /* Initialize the Completion Processor. */ 3000 cpu_reg.mode = BCE_COM_CPU_MODE; 3001 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT; 3002 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA; 3003 cpu_reg.state = BCE_COM_CPU_STATE; 3004 cpu_reg.state_value_clear = 0xffffff; 3005 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE; 3006 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK; 3007 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER; 3008 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION; 3009 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT; 3010 cpu_reg.spad_base = BCE_COM_SCRATCH; 3011 cpu_reg.mips_view_base = 0x8000000; 3012 3013 fw.ver_major = bce_COM_b06FwReleaseMajor; 3014 fw.ver_minor = bce_COM_b06FwReleaseMinor; 3015 fw.ver_fix = bce_COM_b06FwReleaseFix; 3016 fw.start_addr = bce_COM_b06FwStartAddr; 3017 3018 fw.text_addr = bce_COM_b06FwTextAddr; 3019 fw.text_len = bce_COM_b06FwTextLen; 3020 fw.text_index = 0; 3021 fw.text = bce_COM_b06FwText; 3022 3023 fw.data_addr = bce_COM_b06FwDataAddr; 3024 fw.data_len = bce_COM_b06FwDataLen; 3025 fw.data_index = 0; 3026 fw.data = bce_COM_b06FwData; 3027 3028 fw.sbss_addr = bce_COM_b06FwSbssAddr; 3029 fw.sbss_len = bce_COM_b06FwSbssLen; 3030 fw.sbss_index = 0; 3031 fw.sbss = bce_COM_b06FwSbss; 3032 3033 fw.bss_addr = bce_COM_b06FwBssAddr; 3034 fw.bss_len = bce_COM_b06FwBssLen; 3035 fw.bss_index = 0; 3036 fw.bss = bce_COM_b06FwBss; 3037 3038 fw.rodata_addr = bce_COM_b06FwRodataAddr; 3039 fw.rodata_len = bce_COM_b06FwRodataLen; 3040 fw.rodata_index = 0; 3041 fw.rodata = bce_COM_b06FwRodata; 3042 3043 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n"); 3044 bce_load_cpu_fw(sc, &cpu_reg, &fw); 3045 } 3046 3047 3048 /****************************************************************************/ 3049 /* Initialize context memory. */ 3050 /* */ 3051 /* Clears the memory associated with each Context ID (CID). */ 3052 /* */ 3053 /* Returns: */ 3054 /* Nothing. */ 3055 /****************************************************************************/ 3056 static void 3057 bce_init_context(struct bce_softc *sc) 3058 { 3059 u32 vcid; 3060 3061 vcid = 96; 3062 while (vcid) { 3063 u32 vcid_addr, pcid_addr, offset; 3064 3065 vcid--; 3066 3067 vcid_addr = GET_CID_ADDR(vcid); 3068 pcid_addr = vcid_addr; 3069 3070 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0x00); 3071 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 3072 3073 /* Zero out the context. */ 3074 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { 3075 CTX_WR(sc, 0x00, offset, 0); 3076 } 3077 3078 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr); 3079 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr); 3080 } 3081 } 3082 3083 3084 /****************************************************************************/ 3085 /* Fetch the permanent MAC address of the controller. */ 3086 /* */ 3087 /* Returns: */ 3088 /* Nothing. */ 3089 /****************************************************************************/ 3090 static void 3091 bce_get_mac_addr(struct bce_softc *sc) 3092 { 3093 u32 mac_lo = 0, mac_hi = 0; 3094 3095 /* 3096 * The NetXtreme II bootcode populates various NIC 3097 * power-on and runtime configuration items in a 3098 * shared memory area. The factory configured MAC 3099 * address is available from both NVRAM and the 3100 * shared memory area so we'll read the value from 3101 * shared memory for speed. 3102 */ 3103 3104 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + 3105 BCE_PORT_HW_CFG_MAC_UPPER); 3106 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + 3107 BCE_PORT_HW_CFG_MAC_LOWER); 3108 3109 if ((mac_lo == 0) && (mac_hi == 0)) { 3110 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n", 3111 __FILE__, __LINE__); 3112 } else { 3113 sc->eaddr[0] = (u_char)(mac_hi >> 8); 3114 sc->eaddr[1] = (u_char)(mac_hi >> 0); 3115 sc->eaddr[2] = (u_char)(mac_lo >> 24); 3116 sc->eaddr[3] = (u_char)(mac_lo >> 16); 3117 sc->eaddr[4] = (u_char)(mac_lo >> 8); 3118 sc->eaddr[5] = (u_char)(mac_lo >> 0); 3119 } 3120 3121 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet address = %6D\n", sc->eaddr, ":"); 3122 } 3123 3124 3125 /****************************************************************************/ 3126 /* Program the MAC address. */ 3127 /* */ 3128 /* Returns: */ 3129 /* Nothing. */ 3130 /****************************************************************************/ 3131 static void 3132 bce_set_mac_addr(struct bce_softc *sc) 3133 { 3134 u32 val; 3135 u8 *mac_addr = sc->eaddr; 3136 3137 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = %6D\n", sc->eaddr, ":"); 3138 3139 val = (mac_addr[0] << 8) | mac_addr[1]; 3140 3141 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val); 3142 3143 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3144 (mac_addr[4] << 8) | mac_addr[5]; 3145 3146 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val); 3147 } 3148 3149 3150 /****************************************************************************/ 3151 /* Stop the controller. */ 3152 /* */ 3153 /* Returns: */ 3154 /* Nothing. */ 3155 /****************************************************************************/ 3156 static void 3157 bce_stop(struct bce_softc *sc) 3158 { 3159 struct ifnet *ifp; 3160 struct ifmedia_entry *ifm; 3161 struct mii_data *mii = NULL; 3162 int mtmp, itmp; 3163 3164 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3165 3166 BCE_LOCK_ASSERT(sc); 3167 3168 ifp = sc->bce_ifp; 3169 3170 mii = device_get_softc(sc->bce_miibus); 3171 3172 callout_stop(&sc->bce_tick_callout); 3173 3174 /* Disable the transmit/receive blocks. */ 3175 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff); 3176 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3177 DELAY(20); 3178 3179 bce_disable_intr(sc); 3180 3181 /* Free the RX lists. */ 3182 bce_free_rx_chain(sc); 3183 3184 /* Free TX buffers. */ 3185 bce_free_tx_chain(sc); 3186 3187 /* 3188 * Isolate/power down the PHY, but leave the media selection 3189 * unchanged so that things will be put back to normal when 3190 * we bring the interface back up. 3191 */ 3192 3193 itmp = ifp->if_flags; 3194 ifp->if_flags |= IFF_UP; 3195 3196 /* If we are called from bce_detach(), mii is already NULL. */ 3197 if (mii != NULL) { 3198 ifm = mii->mii_media.ifm_cur; 3199 mtmp = ifm->ifm_media; 3200 ifm->ifm_media = IFM_ETHER | IFM_NONE; 3201 mii_mediachg(mii); 3202 ifm->ifm_media = mtmp; 3203 } 3204 3205 ifp->if_flags = itmp; 3206 sc->watchdog_timer = 0; 3207 3208 sc->bce_link = 0; 3209 3210 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3211 3212 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3213 } 3214 3215 3216 static int 3217 bce_reset(struct bce_softc *sc, u32 reset_code) 3218 { 3219 u32 val; 3220 int i, rc = 0; 3221 3222 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n", 3223 __FUNCTION__, reset_code); 3224 3225 /* Wait for pending PCI transactions to complete. */ 3226 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 3227 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | 3228 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | 3229 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | 3230 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); 3231 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS); 3232 DELAY(5); 3233 3234 /* Assume bootcode is running. */ 3235 sc->bce_fw_timed_out = 0; 3236 3237 /* Give the firmware a chance to prepare for the reset. */ 3238 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code); 3239 if (rc) 3240 goto bce_reset_exit; 3241 3242 /* Set a firmware reminder that this is a soft reset. */ 3243 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE, 3244 BCE_DRV_RESET_SIGNATURE_MAGIC); 3245 3246 /* Dummy read to force the chip to complete all current transactions. */ 3247 val = REG_RD(sc, BCE_MISC_ID); 3248 3249 /* Chip reset. */ 3250 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3251 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | 3252 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; 3253 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val); 3254 3255 /* Allow up to 30us for reset to complete. */ 3256 for (i = 0; i < 10; i++) { 3257 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG); 3258 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3259 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { 3260 break; 3261 } 3262 DELAY(10); 3263 } 3264 3265 /* Check that reset completed successfully. */ 3266 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ | 3267 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { 3268 BCE_PRINTF("%s(%d): Reset failed!\n", 3269 __FILE__, __LINE__); 3270 rc = EBUSY; 3271 goto bce_reset_exit; 3272 } 3273 3274 /* Make sure byte swapping is properly configured. */ 3275 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0); 3276 if (val != 0x01020304) { 3277 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n", 3278 __FILE__, __LINE__); 3279 rc = ENODEV; 3280 goto bce_reset_exit; 3281 } 3282 3283 /* Just completed a reset, assume that firmware is running again. */ 3284 sc->bce_fw_timed_out = 0; 3285 3286 /* Wait for the firmware to finish its initialization. */ 3287 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code); 3288 if (rc) 3289 BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n", 3290 __FILE__, __LINE__); 3291 3292 bce_reset_exit: 3293 return (rc); 3294 } 3295 3296 3297 static int 3298 bce_chipinit(struct bce_softc *sc) 3299 { 3300 u32 val; 3301 int rc = 0; 3302 3303 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3304 3305 /* Make sure the interrupt is not active. */ 3306 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT); 3307 3308 /* 3309 * Initialize DMA byte/word swapping, configure the number of DMA 3310 * channels and PCI clock compensation delay. 3311 */ 3312 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP | 3313 BCE_DMA_CONFIG_DATA_WORD_SWAP | 3314 #if BYTE_ORDER == BIG_ENDIAN 3315 BCE_DMA_CONFIG_CNTL_BYTE_SWAP | 3316 #endif 3317 BCE_DMA_CONFIG_CNTL_WORD_SWAP | 3318 DMA_READ_CHANS << 12 | 3319 DMA_WRITE_CHANS << 16; 3320 3321 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY; 3322 3323 if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133)) 3324 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP; 3325 3326 /* 3327 * This setting resolves a problem observed on certain Intel PCI 3328 * chipsets that cannot handle multiple outstanding DMA operations. 3329 * See errata E9_5706A1_65. 3330 */ 3331 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 3332 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) && 3333 !(sc->bce_flags & BCE_PCIX_FLAG)) 3334 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA; 3335 3336 REG_WR(sc, BCE_DMA_CONFIG, val); 3337 3338 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */ 3339 if (sc->bce_flags & BCE_PCIX_FLAG) { 3340 u16 val; 3341 3342 val = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2); 3343 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, val & ~0x2, 2); 3344 } 3345 3346 /* Enable the RX_V2P and Context state machines before access. */ 3347 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 3348 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | 3349 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | 3350 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); 3351 3352 /* Initialize context mapping and zero out the quick contexts. */ 3353 bce_init_context(sc); 3354 3355 /* Initialize the on-boards CPUs */ 3356 bce_init_cpus(sc); 3357 3358 /* Prepare NVRAM for access. */ 3359 if (bce_init_nvram(sc)) { 3360 rc = ENODEV; 3361 goto bce_chipinit_exit; 3362 } 3363 3364 /* Set the kernel bypass block size */ 3365 val = REG_RD(sc, BCE_MQ_CONFIG); 3366 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE; 3367 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; 3368 REG_WR(sc, BCE_MQ_CONFIG, val); 3369 3370 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); 3371 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val); 3372 REG_WR(sc, BCE_MQ_KNL_WIND_END, val); 3373 3374 /* Set the page size and clear the RV2P processor stall bits. */ 3375 val = (BCM_PAGE_BITS - 8) << 24; 3376 REG_WR(sc, BCE_RV2P_CONFIG, val); 3377 3378 /* Configure page size. */ 3379 val = REG_RD(sc, BCE_TBDR_CONFIG); 3380 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE; 3381 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; 3382 REG_WR(sc, BCE_TBDR_CONFIG, val); 3383 3384 bce_chipinit_exit: 3385 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3386 3387 return(rc); 3388 } 3389 3390 3391 /****************************************************************************/ 3392 /* Initialize the controller in preparation to send/receive traffic. */ 3393 /* */ 3394 /* Returns: */ 3395 /* 0 for success, positive value for failure. */ 3396 /****************************************************************************/ 3397 static int 3398 bce_blockinit(struct bce_softc *sc) 3399 { 3400 u32 reg, val; 3401 int rc = 0; 3402 3403 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3404 3405 /* Load the hardware default MAC address. */ 3406 bce_set_mac_addr(sc); 3407 3408 /* Set the Ethernet backoff seed value */ 3409 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + 3410 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) + 3411 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16); 3412 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val); 3413 3414 sc->last_status_idx = 0; 3415 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE; 3416 3417 /* Set up link change interrupt generation. */ 3418 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK); 3419 3420 /* Program the physical address of the status block. */ 3421 REG_WR(sc, BCE_HC_STATUS_ADDR_L, 3422 BCE_ADDR_LO(sc->status_block_paddr)); 3423 REG_WR(sc, BCE_HC_STATUS_ADDR_H, 3424 BCE_ADDR_HI(sc->status_block_paddr)); 3425 3426 /* Program the physical address of the statistics block. */ 3427 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L, 3428 BCE_ADDR_LO(sc->stats_block_paddr)); 3429 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H, 3430 BCE_ADDR_HI(sc->stats_block_paddr)); 3431 3432 /* Program various host coalescing parameters. */ 3433 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 3434 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip); 3435 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 3436 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip); 3437 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 3438 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip); 3439 REG_WR(sc, BCE_HC_TX_TICKS, 3440 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks); 3441 REG_WR(sc, BCE_HC_RX_TICKS, 3442 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks); 3443 REG_WR(sc, BCE_HC_COM_TICKS, 3444 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks); 3445 REG_WR(sc, BCE_HC_CMD_TICKS, 3446 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks); 3447 REG_WR(sc, BCE_HC_STATS_TICKS, 3448 (sc->bce_stats_ticks & 0xffff00)); 3449 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 3450 0xbb8); /* 3ms */ 3451 REG_WR(sc, BCE_HC_CONFIG, 3452 (BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE | 3453 BCE_HC_CONFIG_COLLECT_STATS)); 3454 3455 /* Clear the internal statistics counters. */ 3456 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW); 3457 3458 /* Verify that bootcode is running. */ 3459 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE); 3460 3461 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure), 3462 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n", 3463 __FILE__, __LINE__); 3464 reg = 0); 3465 3466 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) != 3467 BCE_DEV_INFO_SIGNATURE_MAGIC) { 3468 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, " 3469 "Expected: 08%08X\n", __FILE__, __LINE__, 3470 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK), 3471 BCE_DEV_INFO_SIGNATURE_MAGIC); 3472 rc = ENODEV; 3473 goto bce_blockinit_exit; 3474 } 3475 3476 /* Allow bootcode to apply any additional fixes before enabling MAC. */ 3477 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET); 3478 3479 /* Enable link state change interrupt generation. */ 3480 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); 3481 3482 /* Enable all remaining blocks in the MAC. */ 3483 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff); 3484 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 3485 DELAY(20); 3486 3487 bce_blockinit_exit: 3488 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3489 3490 return (rc); 3491 } 3492 3493 3494 /****************************************************************************/ 3495 /* Encapsulate an mbuf cluster into the rx_bd chain. */ 3496 /* */ 3497 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */ 3498 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */ 3499 /* necessary. */ 3500 /* */ 3501 /* Returns: */ 3502 /* 0 for success, positive value for failure. */ 3503 /****************************************************************************/ 3504 static int 3505 bce_get_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod, u16 *chain_prod, 3506 u32 *prod_bseq) 3507 { 3508 bus_dmamap_t map; 3509 bus_dma_segment_t segs[4]; 3510 struct mbuf *m_new = NULL; 3511 struct rx_bd *rxbd; 3512 int i, nsegs, error, rc = 0; 3513 #ifdef BCE_DEBUG 3514 u16 debug_chain_prod = *chain_prod; 3515 #endif 3516 3517 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Entering %s()\n", 3518 __FUNCTION__); 3519 3520 /* Make sure the inputs are valid. */ 3521 DBRUNIF((*chain_prod > MAX_RX_BD), 3522 BCE_PRINTF("%s(%d): RX producer out of range: 0x%04X > 0x%04X\n", 3523 __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD)); 3524 3525 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, " 3526 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3527 3528 if (m == NULL) { 3529 3530 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure), 3531 BCE_PRINTF("%s(%d): Simulating mbuf allocation failure.\n", 3532 __FILE__, __LINE__); 3533 sc->mbuf_alloc_failed++; 3534 rc = ENOBUFS; 3535 goto bce_get_buf_exit); 3536 3537 /* This is a new mbuf allocation. */ 3538 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 3539 if (m_new == NULL) { 3540 3541 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf header allocation failed!\n", 3542 __FILE__, __LINE__); 3543 3544 DBRUNIF(1, sc->mbuf_alloc_failed++); 3545 3546 rc = ENOBUFS; 3547 goto bce_get_buf_exit; 3548 } 3549 3550 DBRUNIF(1, sc->rx_mbuf_alloc++); 3551 m_cljget(m_new, M_DONTWAIT, sc->mbuf_alloc_size); 3552 if (!(m_new->m_flags & M_EXT)) { 3553 3554 DBPRINT(sc, BCE_WARN, "%s(%d): RX mbuf chain allocation failed!\n", 3555 __FILE__, __LINE__); 3556 3557 m_freem(m_new); 3558 3559 DBRUNIF(1, sc->rx_mbuf_alloc--); 3560 DBRUNIF(1, sc->mbuf_alloc_failed++); 3561 3562 rc = ENOBUFS; 3563 goto bce_get_buf_exit; 3564 } 3565 3566 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3567 } else { 3568 m_new = m; 3569 m_new->m_len = m_new->m_pkthdr.len = sc->mbuf_alloc_size; 3570 m_new->m_data = m_new->m_ext.ext_buf; 3571 } 3572 3573 /* Map the mbuf cluster into device memory. */ 3574 map = sc->rx_mbuf_map[*chain_prod]; 3575 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new, 3576 segs, &nsegs, BUS_DMA_NOWAIT); 3577 3578 if (error) { 3579 BCE_PRINTF("%s(%d): Error mapping mbuf into RX chain!\n", 3580 __FILE__, __LINE__); 3581 3582 m_freem(m_new); 3583 3584 DBRUNIF(1, sc->rx_mbuf_alloc--); 3585 3586 rc = ENOBUFS; 3587 goto bce_get_buf_exit; 3588 } 3589 3590 /* Watch for overflow. */ 3591 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD), 3592 BCE_PRINTF("%s(%d): Too many free rx_bd (0x%04X > 0x%04X)!\n", 3593 __FILE__, __LINE__, sc->free_rx_bd, (u16) USABLE_RX_BD)); 3594 3595 /* Update some debug statistic counters */ 3596 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 3597 sc->rx_low_watermark = sc->free_rx_bd); 3598 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++); 3599 3600 /* Setup the rx_bd for the first segment. */ 3601 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3602 3603 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr)); 3604 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr)); 3605 rxbd->rx_bd_len = htole32(segs[0].ds_len); 3606 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START); 3607 *prod_bseq += segs[0].ds_len; 3608 3609 for (i = 1; i < nsegs; i++) { 3610 3611 *prod = NEXT_RX_BD(*prod); 3612 *chain_prod = RX_CHAIN_IDX(*prod); 3613 3614 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; 3615 3616 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 3617 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 3618 rxbd->rx_bd_len = htole32(segs[i].ds_len); 3619 rxbd->rx_bd_flags = 0; 3620 *prod_bseq += segs[i].ds_len; 3621 } 3622 3623 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END); 3624 3625 /* Save the mbuf and update our counter. */ 3626 sc->rx_mbuf_ptr[*chain_prod] = m_new; 3627 sc->free_rx_bd -= nsegs; 3628 3629 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 3630 nsegs)); 3631 3632 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, " 3633 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq); 3634 3635 bce_get_buf_exit: 3636 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Exiting %s()\n", 3637 __FUNCTION__); 3638 3639 return(rc); 3640 } 3641 3642 3643 /****************************************************************************/ 3644 /* Allocate memory and initialize the TX data structures. */ 3645 /* */ 3646 /* Returns: */ 3647 /* 0 for success, positive value for failure. */ 3648 /****************************************************************************/ 3649 static int 3650 bce_init_tx_chain(struct bce_softc *sc) 3651 { 3652 struct tx_bd *txbd; 3653 u32 val; 3654 int i, rc = 0; 3655 3656 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3657 3658 /* Set the initial TX producer/consumer indices. */ 3659 sc->tx_prod = 0; 3660 sc->tx_cons = 0; 3661 sc->tx_prod_bseq = 0; 3662 sc->used_tx_bd = 0; 3663 sc->max_tx_bd = USABLE_TX_BD; 3664 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD); 3665 DBRUNIF(1, sc->tx_full_count = 0); 3666 3667 /* 3668 * The NetXtreme II supports a linked-list structre called 3669 * a Buffer Descriptor Chain (or BD chain). A BD chain 3670 * consists of a series of 1 or more chain pages, each of which 3671 * consists of a fixed number of BD entries. 3672 * The last BD entry on each page is a pointer to the next page 3673 * in the chain, and the last pointer in the BD chain 3674 * points back to the beginning of the chain. 3675 */ 3676 3677 /* Set the TX next pointer chain entries. */ 3678 for (i = 0; i < TX_PAGES; i++) { 3679 int j; 3680 3681 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE]; 3682 3683 /* Check if we've reached the last page. */ 3684 if (i == (TX_PAGES - 1)) 3685 j = 0; 3686 else 3687 j = i + 1; 3688 3689 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j])); 3690 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j])); 3691 } 3692 3693 /* Initialize the context ID for an L2 TX chain. */ 3694 val = BCE_L2CTX_TYPE_TYPE_L2; 3695 val |= BCE_L2CTX_TYPE_SIZE_L2; 3696 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val); 3697 3698 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16); 3699 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val); 3700 3701 /* Point the hardware to the first page in the chain. */ 3702 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]); 3703 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val); 3704 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]); 3705 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val); 3706 3707 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD)); 3708 3709 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3710 3711 return(rc); 3712 } 3713 3714 3715 /****************************************************************************/ 3716 /* Free memory and clear the TX data structures. */ 3717 /* */ 3718 /* Returns: */ 3719 /* Nothing. */ 3720 /****************************************************************************/ 3721 static void 3722 bce_free_tx_chain(struct bce_softc *sc) 3723 { 3724 int i; 3725 3726 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3727 3728 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */ 3729 for (i = 0; i < TOTAL_TX_BD; i++) { 3730 if (sc->tx_mbuf_ptr[i] != NULL) { 3731 if (sc->tx_mbuf_map != NULL) 3732 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i], 3733 BUS_DMASYNC_POSTWRITE); 3734 m_freem(sc->tx_mbuf_ptr[i]); 3735 sc->tx_mbuf_ptr[i] = NULL; 3736 DBRUNIF(1, sc->tx_mbuf_alloc--); 3737 } 3738 } 3739 3740 /* Clear each TX chain page. */ 3741 for (i = 0; i < TX_PAGES; i++) 3742 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ); 3743 3744 /* Check if we lost any mbufs in the process. */ 3745 DBRUNIF((sc->tx_mbuf_alloc), 3746 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs " 3747 "from tx chain!\n", 3748 __FILE__, __LINE__, sc->tx_mbuf_alloc)); 3749 3750 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3751 } 3752 3753 3754 /****************************************************************************/ 3755 /* Allocate memory and initialize the RX data structures. */ 3756 /* */ 3757 /* Returns: */ 3758 /* 0 for success, positive value for failure. */ 3759 /****************************************************************************/ 3760 static int 3761 bce_init_rx_chain(struct bce_softc *sc) 3762 { 3763 struct rx_bd *rxbd; 3764 int i, rc = 0; 3765 u16 prod, chain_prod; 3766 u32 prod_bseq, val; 3767 3768 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3769 3770 /* Initialize the RX producer and consumer indices. */ 3771 sc->rx_prod = 0; 3772 sc->rx_cons = 0; 3773 sc->rx_prod_bseq = 0; 3774 sc->free_rx_bd = USABLE_RX_BD; 3775 sc->max_rx_bd = USABLE_RX_BD; 3776 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD); 3777 DBRUNIF(1, sc->rx_empty_count = 0); 3778 3779 /* Initialize the RX next pointer chain entries. */ 3780 for (i = 0; i < RX_PAGES; i++) { 3781 int j; 3782 3783 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE]; 3784 3785 /* Check if we've reached the last page. */ 3786 if (i == (RX_PAGES - 1)) 3787 j = 0; 3788 else 3789 j = i + 1; 3790 3791 /* Setup the chain page pointers. */ 3792 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j])); 3793 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j])); 3794 } 3795 3796 /* Initialize the context ID for an L2 RX chain. */ 3797 val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; 3798 val |= BCE_L2CTX_CTX_TYPE_SIZE_L2; 3799 val |= 0x02 << 8; 3800 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val); 3801 3802 /* Point the hardware to the first page in the chain. */ 3803 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]); 3804 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val); 3805 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]); 3806 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val); 3807 3808 /* Allocate mbuf clusters for the rx_bd chain. */ 3809 prod = prod_bseq = 0; 3810 while (prod < TOTAL_RX_BD) { 3811 chain_prod = RX_CHAIN_IDX(prod); 3812 if (bce_get_buf(sc, NULL, &prod, &chain_prod, &prod_bseq)) { 3813 BCE_PRINTF("%s(%d): Error filling RX chain: rx_bd[0x%04X]!\n", 3814 __FILE__, __LINE__, chain_prod); 3815 rc = ENOBUFS; 3816 break; 3817 } 3818 prod = NEXT_RX_BD(prod); 3819 } 3820 3821 /* Save the RX chain producer index. */ 3822 sc->rx_prod = prod; 3823 sc->rx_prod_bseq = prod_bseq; 3824 3825 for (i = 0; i < RX_PAGES; i++) { 3826 bus_dmamap_sync( 3827 sc->rx_bd_chain_tag, 3828 sc->rx_bd_chain_map[i], 3829 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3830 } 3831 3832 /* Tell the chip about the waiting rx_bd's. */ 3833 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); 3834 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 3835 3836 DBRUN(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD)); 3837 3838 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3839 3840 return(rc); 3841 } 3842 3843 3844 /****************************************************************************/ 3845 /* Free memory and clear the RX data structures. */ 3846 /* */ 3847 /* Returns: */ 3848 /* Nothing. */ 3849 /****************************************************************************/ 3850 static void 3851 bce_free_rx_chain(struct bce_softc *sc) 3852 { 3853 int i; 3854 3855 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 3856 3857 /* Free any mbufs still in the RX mbuf chain. */ 3858 for (i = 0; i < TOTAL_RX_BD; i++) { 3859 if (sc->rx_mbuf_ptr[i] != NULL) { 3860 if (sc->rx_mbuf_map[i] != NULL) 3861 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i], 3862 BUS_DMASYNC_POSTREAD); 3863 m_freem(sc->rx_mbuf_ptr[i]); 3864 sc->rx_mbuf_ptr[i] = NULL; 3865 DBRUNIF(1, sc->rx_mbuf_alloc--); 3866 } 3867 } 3868 3869 /* Clear each RX chain page. */ 3870 for (i = 0; i < RX_PAGES; i++) 3871 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ); 3872 3873 /* Check if we lost any mbufs in the process. */ 3874 DBRUNIF((sc->rx_mbuf_alloc), 3875 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs from rx chain!\n", 3876 __FILE__, __LINE__, sc->rx_mbuf_alloc)); 3877 3878 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 3879 } 3880 3881 3882 /****************************************************************************/ 3883 /* Set media options. */ 3884 /* */ 3885 /* Returns: */ 3886 /* 0 for success, positive value for failure. */ 3887 /****************************************************************************/ 3888 static int 3889 bce_ifmedia_upd(struct ifnet *ifp) 3890 { 3891 struct bce_softc *sc; 3892 3893 sc = ifp->if_softc; 3894 BCE_LOCK(sc); 3895 bce_ifmedia_upd_locked(ifp); 3896 BCE_UNLOCK(sc); 3897 return (0); 3898 } 3899 3900 3901 /****************************************************************************/ 3902 /* Set media options. */ 3903 /* */ 3904 /* Returns: */ 3905 /* Nothing. */ 3906 /****************************************************************************/ 3907 static void 3908 bce_ifmedia_upd_locked(struct ifnet *ifp) 3909 { 3910 struct bce_softc *sc; 3911 struct mii_data *mii; 3912 struct ifmedia *ifm; 3913 3914 sc = ifp->if_softc; 3915 ifm = &sc->bce_ifmedia; 3916 BCE_LOCK_ASSERT(sc); 3917 3918 mii = device_get_softc(sc->bce_miibus); 3919 3920 /* Make sure the MII bus has been enumerated. */ 3921 if (mii) { 3922 sc->bce_link = 0; 3923 if (mii->mii_instance) { 3924 struct mii_softc *miisc; 3925 3926 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3927 mii_phy_reset(miisc); 3928 } 3929 mii_mediachg(mii); 3930 } 3931 } 3932 3933 3934 /****************************************************************************/ 3935 /* Reports current media status. */ 3936 /* */ 3937 /* Returns: */ 3938 /* Nothing. */ 3939 /****************************************************************************/ 3940 static void 3941 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3942 { 3943 struct bce_softc *sc; 3944 struct mii_data *mii; 3945 3946 sc = ifp->if_softc; 3947 3948 BCE_LOCK(sc); 3949 3950 mii = device_get_softc(sc->bce_miibus); 3951 3952 mii_pollstat(mii); 3953 ifmr->ifm_active = mii->mii_media_active; 3954 ifmr->ifm_status = mii->mii_media_status; 3955 3956 BCE_UNLOCK(sc); 3957 } 3958 3959 3960 /****************************************************************************/ 3961 /* Handles PHY generated interrupt events. */ 3962 /* */ 3963 /* Returns: */ 3964 /* Nothing. */ 3965 /****************************************************************************/ 3966 static void 3967 bce_phy_intr(struct bce_softc *sc) 3968 { 3969 u32 new_link_state, old_link_state; 3970 3971 new_link_state = sc->status_block->status_attn_bits & 3972 STATUS_ATTN_BITS_LINK_STATE; 3973 old_link_state = sc->status_block->status_attn_bits_ack & 3974 STATUS_ATTN_BITS_LINK_STATE; 3975 3976 /* Handle any changes if the link state has changed. */ 3977 if (new_link_state != old_link_state) { 3978 3979 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc)); 3980 3981 sc->bce_link = 0; 3982 callout_stop(&sc->bce_tick_callout); 3983 bce_tick(sc); 3984 3985 /* Update the status_attn_bits_ack field in the status block. */ 3986 if (new_link_state) { 3987 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD, 3988 STATUS_ATTN_BITS_LINK_STATE); 3989 DBPRINT(sc, BCE_INFO_MISC, "Link is now UP.\n"); 3990 } 3991 else { 3992 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD, 3993 STATUS_ATTN_BITS_LINK_STATE); 3994 DBPRINT(sc, BCE_INFO_MISC, "Link is now DOWN.\n"); 3995 } 3996 3997 } 3998 3999 /* Acknowledge the link change interrupt. */ 4000 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE); 4001 } 4002 4003 4004 /****************************************************************************/ 4005 /* Handles received frame interrupt events. */ 4006 /* */ 4007 /* Returns: */ 4008 /* Nothing. */ 4009 /****************************************************************************/ 4010 static void 4011 bce_rx_intr(struct bce_softc *sc) 4012 { 4013 struct status_block *sblk = sc->status_block; 4014 struct ifnet *ifp = sc->bce_ifp; 4015 u16 hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod; 4016 u32 sw_prod_bseq; 4017 struct l2_fhdr *l2fhdr; 4018 4019 DBRUNIF(1, sc->rx_interrupts++); 4020 4021 /* Prepare the RX chain pages to be accessed by the host CPU. */ 4022 for (int i = 0; i < RX_PAGES; i++) 4023 bus_dmamap_sync(sc->rx_bd_chain_tag, 4024 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE); 4025 4026 /* Get the hardware's view of the RX consumer index. */ 4027 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4028 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4029 hw_cons++; 4030 4031 /* Get working copies of the driver's view of the RX indices. */ 4032 sw_cons = sc->rx_cons; 4033 sw_prod = sc->rx_prod; 4034 sw_prod_bseq = sc->rx_prod_bseq; 4035 4036 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, " 4037 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n", 4038 __FUNCTION__, sw_prod, sw_cons, 4039 sw_prod_bseq); 4040 4041 /* Prevent speculative reads from getting ahead of the status block. */ 4042 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4043 BUS_SPACE_BARRIER_READ); 4044 4045 /* Update some debug statistics counters */ 4046 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark), 4047 sc->rx_low_watermark = sc->free_rx_bd); 4048 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++); 4049 4050 /* Scan through the receive chain as long as there is work to do */ 4051 while (sw_cons != hw_cons) { 4052 struct mbuf *m; 4053 struct rx_bd *rxbd; 4054 unsigned int len; 4055 u32 status; 4056 4057 /* Clear the mbuf pointer. */ 4058 m = NULL; 4059 4060 /* Convert the producer/consumer indices to an actual rx_bd index. */ 4061 sw_chain_cons = RX_CHAIN_IDX(sw_cons); 4062 sw_chain_prod = RX_CHAIN_IDX(sw_prod); 4063 4064 /* Get the used rx_bd. */ 4065 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; 4066 sc->free_rx_bd++; 4067 4068 DBRUN(BCE_VERBOSE_RECV, 4069 BCE_PRINTF("%s(): ", __FUNCTION__); 4070 bce_dump_rxbd(sc, sw_chain_cons, rxbd)); 4071 4072 #ifdef DEVICE_POLLING 4073 if (ifp->if_capenable & IFCAP_POLLING) { 4074 if (sc->bce_rxcycles <= 0) 4075 break; 4076 sc->bce_rxcycles--; 4077 } 4078 #endif 4079 4080 /* The mbuf is stored with the last rx_bd entry of a packet. */ 4081 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) { 4082 4083 /* Validate that this is the last rx_bd. */ 4084 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)), 4085 BCE_PRINTF("%s(%d): Unexpected mbuf found in rx_bd[0x%04X]!\n", 4086 __FILE__, __LINE__, sw_chain_cons); 4087 bce_breakpoint(sc)); 4088 4089 /* 4090 * ToDo: If the received packet is small enough 4091 * to fit into a single, non-M_EXT mbuf, 4092 * allocate a new mbuf here, copy the data to 4093 * that mbuf, and recycle the mapped jumbo frame. 4094 */ 4095 4096 /* Unmap the mbuf from DMA space. */ 4097 bus_dmamap_sync(sc->rx_mbuf_tag, 4098 sc->rx_mbuf_map[sw_chain_cons], 4099 BUS_DMASYNC_POSTREAD); 4100 bus_dmamap_unload(sc->rx_mbuf_tag, 4101 sc->rx_mbuf_map[sw_chain_cons]); 4102 4103 /* Remove the mbuf from the driver's chain. */ 4104 m = sc->rx_mbuf_ptr[sw_chain_cons]; 4105 sc->rx_mbuf_ptr[sw_chain_cons] = NULL; 4106 4107 /* 4108 * Frames received on the NetXteme II are prepended 4109 * with an l2_fhdr structure which provides status 4110 * information about the received frame (including 4111 * VLAN tags and checksum info). The frames are also 4112 * automatically adjusted to align the IP header 4113 * (i.e. two null bytes are inserted before the 4114 * Ethernet header). 4115 */ 4116 l2fhdr = mtod(m, struct l2_fhdr *); 4117 4118 len = l2fhdr->l2_fhdr_pkt_len; 4119 status = l2fhdr->l2_fhdr_status; 4120 4121 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check), 4122 BCE_PRINTF("Simulating l2_fhdr status error.\n"); 4123 status = status | L2_FHDR_ERRORS_PHY_DECODE); 4124 4125 /* Watch for unusual sized frames. */ 4126 DBRUNIF(((len < BCE_MIN_MTU) || (len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)), 4127 BCE_PRINTF("%s(%d): Unusual frame size found. " 4128 "Min(%d), Actual(%d), Max(%d)\n", 4129 __FILE__, __LINE__, (int) BCE_MIN_MTU, 4130 len, (int) BCE_MAX_JUMBO_ETHER_MTU_VLAN); 4131 bce_dump_mbuf(sc, m); 4132 bce_breakpoint(sc)); 4133 4134 len -= ETHER_CRC_LEN; 4135 4136 /* Check the received frame for errors. */ 4137 if (status & (L2_FHDR_ERRORS_BAD_CRC | 4138 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT | 4139 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { 4140 4141 ifp->if_ierrors++; 4142 DBRUNIF(1, sc->l2fhdr_status_errors++); 4143 4144 /* Reuse the mbuf for a new frame. */ 4145 if (bce_get_buf(sc, m, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4146 4147 DBRUNIF(1, bce_breakpoint(sc)); 4148 panic("bce%d: Can't reuse RX mbuf!\n", sc->bce_unit); 4149 4150 } 4151 goto bce_rx_int_next_rx; 4152 } 4153 4154 /* 4155 * Get a new mbuf for the rx_bd. If no new 4156 * mbufs are available then reuse the current mbuf, 4157 * log an ierror on the interface, and generate 4158 * an error in the system log. 4159 */ 4160 if (bce_get_buf(sc, NULL, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4161 4162 DBRUN(BCE_WARN, 4163 BCE_PRINTF("%s(%d): Failed to allocate " 4164 "new mbuf, incoming frame dropped!\n", 4165 __FILE__, __LINE__)); 4166 4167 ifp->if_ierrors++; 4168 4169 /* Try and reuse the exisitng mbuf. */ 4170 if (bce_get_buf(sc, m, &sw_prod, &sw_chain_prod, &sw_prod_bseq)) { 4171 4172 DBRUNIF(1, bce_breakpoint(sc)); 4173 panic("bce%d: Double mbuf allocation failure!", sc->bce_unit); 4174 4175 } 4176 goto bce_rx_int_next_rx; 4177 } 4178 4179 /* Skip over the l2_fhdr when passing the data up the stack. */ 4180 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN); 4181 4182 /* Adjust the packet length to match the received data. */ 4183 m->m_pkthdr.len = m->m_len = len; 4184 4185 /* Send the packet to the appropriate interface. */ 4186 m->m_pkthdr.rcvif = ifp; 4187 4188 DBRUN(BCE_VERBOSE_RECV, 4189 struct ether_header *eh; 4190 eh = mtod(m, struct ether_header *); 4191 BCE_PRINTF("%s(): to: %6D, from: %6D, type: 0x%04X\n", 4192 __FUNCTION__, eh->ether_dhost, ":", 4193 eh->ether_shost, ":", htons(eh->ether_type))); 4194 4195 /* Validate the checksum if offload enabled. */ 4196 if (ifp->if_capenable & IFCAP_RXCSUM) { 4197 4198 /* Check for an IP datagram. */ 4199 if (status & L2_FHDR_STATUS_IP_DATAGRAM) { 4200 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4201 4202 /* Check if the IP checksum is valid. */ 4203 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0) 4204 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4205 else 4206 DBPRINT(sc, BCE_WARN_SEND, 4207 "%s(): Invalid IP checksum = 0x%04X!\n", 4208 __FUNCTION__, l2fhdr->l2_fhdr_ip_xsum); 4209 } 4210 4211 /* Check for a valid TCP/UDP frame. */ 4212 if (status & (L2_FHDR_STATUS_TCP_SEGMENT | 4213 L2_FHDR_STATUS_UDP_DATAGRAM)) { 4214 4215 /* Check for a good TCP/UDP checksum. */ 4216 if ((status & (L2_FHDR_ERRORS_TCP_XSUM | 4217 L2_FHDR_ERRORS_UDP_XSUM)) == 0) { 4218 m->m_pkthdr.csum_data = 4219 l2fhdr->l2_fhdr_tcp_udp_xsum; 4220 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID 4221 | CSUM_PSEUDO_HDR); 4222 } else 4223 DBPRINT(sc, BCE_WARN_SEND, 4224 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n", 4225 __FUNCTION__, l2fhdr->l2_fhdr_tcp_udp_xsum); 4226 } 4227 } 4228 4229 4230 /* 4231 * If we received a packet with a vlan tag, 4232 * attach that information to the packet. 4233 */ 4234 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) { 4235 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): VLAN tag = 0x%04X\n", 4236 __FUNCTION__, l2fhdr->l2_fhdr_vlan_tag); 4237 #if __FreeBSD_version < 700000 4238 VLAN_INPUT_TAG(ifp, m, l2fhdr->l2_fhdr_vlan_tag, continue); 4239 #else 4240 m->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag; 4241 m->m_flags |= M_VLANTAG; 4242 #endif 4243 } 4244 4245 /* Pass the mbuf off to the upper layers. */ 4246 ifp->if_ipackets++; 4247 4248 bce_rx_int_next_rx: 4249 sw_prod = NEXT_RX_BD(sw_prod); 4250 } 4251 4252 sw_cons = NEXT_RX_BD(sw_cons); 4253 4254 /* If we have a packet, pass it up the stack */ 4255 if (m) { 4256 /* Make sure we don't lose our place when we release the lock. */ 4257 sc->rx_cons = sw_cons; 4258 sc->rx_prod = sw_prod; 4259 sc->rx_prod_bseq = sw_prod_bseq; 4260 4261 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(): Passing received frame up.\n", 4262 __FUNCTION__); 4263 BCE_UNLOCK(sc); 4264 (*ifp->if_input)(ifp, m); 4265 DBRUNIF(1, sc->rx_mbuf_alloc--); 4266 BCE_LOCK(sc); 4267 4268 /* Recover our place. */ 4269 sw_cons = sc->rx_cons; 4270 sw_prod = sc->rx_prod; 4271 sw_prod_bseq = sc->rx_prod_bseq; 4272 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4273 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4274 hw_cons++; 4275 } 4276 4277 /* Refresh hw_cons to see if there's new work */ 4278 if (sw_cons == hw_cons) { 4279 hw_cons = sc->hw_rx_cons = sblk->status_rx_quick_consumer_index0; 4280 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 4281 hw_cons++; 4282 } 4283 4284 /* Prevent speculative reads from getting ahead of the status block. */ 4285 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4286 BUS_SPACE_BARRIER_READ); 4287 } 4288 4289 for (int i = 0; i < RX_PAGES; i++) 4290 bus_dmamap_sync(sc->rx_bd_chain_tag, 4291 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE); 4292 4293 sc->rx_cons = sw_cons; 4294 sc->rx_prod = sw_prod; 4295 sc->rx_prod_bseq = sw_prod_bseq; 4296 4297 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod); 4298 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq); 4299 4300 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, " 4301 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n", 4302 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq); 4303 } 4304 4305 4306 /****************************************************************************/ 4307 /* Handles transmit completion interrupt events. */ 4308 /* */ 4309 /* Returns: */ 4310 /* Nothing. */ 4311 /****************************************************************************/ 4312 static void 4313 bce_tx_intr(struct bce_softc *sc) 4314 { 4315 struct status_block *sblk = sc->status_block; 4316 struct ifnet *ifp = sc->bce_ifp; 4317 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons; 4318 4319 BCE_LOCK_ASSERT(sc); 4320 4321 DBRUNIF(1, sc->tx_interrupts++); 4322 4323 /* Get the hardware's view of the TX consumer index. */ 4324 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4325 4326 /* Skip to the next entry if this is a chain page pointer. */ 4327 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4328 hw_tx_cons++; 4329 4330 sw_tx_cons = sc->tx_cons; 4331 4332 /* Prevent speculative reads from getting ahead of the status block. */ 4333 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4334 BUS_SPACE_BARRIER_READ); 4335 4336 /* Cycle through any completed TX chain page entries. */ 4337 while (sw_tx_cons != hw_tx_cons) { 4338 #ifdef BCE_DEBUG 4339 struct tx_bd *txbd = NULL; 4340 #endif 4341 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons); 4342 4343 DBPRINT(sc, BCE_INFO_SEND, 4344 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, " 4345 "sw_tx_chain_cons = 0x%04X\n", 4346 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons); 4347 4348 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD), 4349 BCE_PRINTF("%s(%d): TX chain consumer out of range! " 4350 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons, 4351 (int) MAX_TX_BD); 4352 bce_breakpoint(sc)); 4353 4354 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)] 4355 [TX_IDX(sw_tx_chain_cons)]); 4356 4357 DBRUNIF((txbd == NULL), 4358 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n", 4359 __FILE__, __LINE__, sw_tx_chain_cons); 4360 bce_breakpoint(sc)); 4361 4362 DBRUN(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__); 4363 bce_dump_txbd(sc, sw_tx_chain_cons, txbd)); 4364 4365 /* 4366 * Free the associated mbuf. Remember 4367 * that only the last tx_bd of a packet 4368 * has an mbuf pointer and DMA map. 4369 */ 4370 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) { 4371 4372 /* Validate that this is the last tx_bd. */ 4373 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)), 4374 BCE_PRINTF("%s(%d): tx_bd END flag not set but " 4375 "txmbuf == NULL!\n", __FILE__, __LINE__); 4376 bce_breakpoint(sc)); 4377 4378 DBRUN(BCE_INFO_SEND, 4379 BCE_PRINTF("%s(): Unloading map/freeing mbuf " 4380 "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons)); 4381 4382 /* Unmap the mbuf. */ 4383 bus_dmamap_unload(sc->tx_mbuf_tag, 4384 sc->tx_mbuf_map[sw_tx_chain_cons]); 4385 4386 /* Free the mbuf. */ 4387 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); 4388 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; 4389 DBRUNIF(1, sc->tx_mbuf_alloc--); 4390 4391 ifp->if_opackets++; 4392 } 4393 4394 sc->used_tx_bd--; 4395 sw_tx_cons = NEXT_TX_BD(sw_tx_cons); 4396 4397 /* Refresh hw_cons to see if there's new work. */ 4398 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0; 4399 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 4400 hw_tx_cons++; 4401 4402 /* Prevent speculative reads from getting ahead of the status block. */ 4403 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 4404 BUS_SPACE_BARRIER_READ); 4405 } 4406 4407 /* Clear the TX timeout timer. */ 4408 sc->watchdog_timer = 0; 4409 4410 /* Clear the tx hardware queue full flag. */ 4411 if (sc->used_tx_bd < sc->max_tx_bd) { 4412 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE), 4413 DBPRINT(sc, BCE_INFO_SEND, 4414 "%s(): Open TX chain! %d/%d (used/total)\n", 4415 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd)); 4416 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4417 } 4418 4419 sc->tx_cons = sw_tx_cons; 4420 } 4421 4422 4423 /****************************************************************************/ 4424 /* Disables interrupt generation. */ 4425 /* */ 4426 /* Returns: */ 4427 /* Nothing. */ 4428 /****************************************************************************/ 4429 static void 4430 bce_disable_intr(struct bce_softc *sc) 4431 { 4432 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4433 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 4434 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD); 4435 } 4436 4437 4438 /****************************************************************************/ 4439 /* Enables interrupt generation. */ 4440 /* */ 4441 /* Returns: */ 4442 /* Nothing. */ 4443 /****************************************************************************/ 4444 static void 4445 bce_enable_intr(struct bce_softc *sc) 4446 { 4447 u32 val; 4448 4449 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4450 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | 4451 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); 4452 4453 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 4454 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 4455 4456 val = REG_RD(sc, BCE_HC_COMMAND); 4457 REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW); 4458 } 4459 4460 4461 /****************************************************************************/ 4462 /* Handles controller initialization. */ 4463 /* */ 4464 /* Returns: */ 4465 /* Nothing. */ 4466 /****************************************************************************/ 4467 static void 4468 bce_init_locked(struct bce_softc *sc) 4469 { 4470 struct ifnet *ifp; 4471 u32 ether_mtu; 4472 4473 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4474 4475 BCE_LOCK_ASSERT(sc); 4476 4477 ifp = sc->bce_ifp; 4478 4479 /* Check if the driver is still running and bail out if it is. */ 4480 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4481 goto bce_init_locked_exit; 4482 4483 bce_stop(sc); 4484 4485 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) { 4486 BCE_PRINTF("%s(%d): Controller reset failed!\n", 4487 __FILE__, __LINE__); 4488 goto bce_init_locked_exit; 4489 } 4490 4491 if (bce_chipinit(sc)) { 4492 BCE_PRINTF("%s(%d): Controller initialization failed!\n", 4493 __FILE__, __LINE__); 4494 goto bce_init_locked_exit; 4495 } 4496 4497 if (bce_blockinit(sc)) { 4498 BCE_PRINTF("%s(%d): Block initialization failed!\n", 4499 __FILE__, __LINE__); 4500 goto bce_init_locked_exit; 4501 } 4502 4503 /* Load our MAC address. */ 4504 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN); 4505 bce_set_mac_addr(sc); 4506 4507 /* Calculate and program the Ethernet MTU size. */ 4508 ether_mtu = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ifp->if_mtu + 4509 ETHER_CRC_LEN; 4510 4511 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting mtu = %d\n",__FUNCTION__, ether_mtu); 4512 4513 /* 4514 * Program the mtu, enabling jumbo frame 4515 * support if necessary. Also set the mbuf 4516 * allocation count for RX frames. 4517 */ 4518 if (ether_mtu > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 4519 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) | 4520 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA); 4521 sc->mbuf_alloc_size = MJUM9BYTES; 4522 } else { 4523 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu); 4524 sc->mbuf_alloc_size = MCLBYTES; 4525 } 4526 4527 /* Calculate the RX Ethernet frame size for rx_bd's. */ 4528 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8; 4529 4530 DBPRINT(sc, BCE_INFO_RECV, 4531 "%s(): mclbytes = %d, mbuf_alloc_size = %d, " 4532 "max_frame_size = %d\n", 4533 __FUNCTION__, (int) MCLBYTES, sc->mbuf_alloc_size, sc->max_frame_size); 4534 4535 /* Program appropriate promiscuous/multicast filtering. */ 4536 bce_set_rx_mode(sc); 4537 4538 /* Init RX buffer descriptor chain. */ 4539 bce_init_rx_chain(sc); 4540 4541 /* Init TX buffer descriptor chain. */ 4542 bce_init_tx_chain(sc); 4543 4544 #ifdef DEVICE_POLLING 4545 /* Disable interrupts if we are polling. */ 4546 if (ifp->if_capenable & IFCAP_POLLING) { 4547 bce_disable_intr(sc); 4548 4549 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 4550 (1 << 16) | sc->bce_rx_quick_cons_trip); 4551 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 4552 (1 << 16) | sc->bce_tx_quick_cons_trip); 4553 } else 4554 #endif 4555 /* Enable host interrupts. */ 4556 bce_enable_intr(sc); 4557 4558 bce_ifmedia_upd_locked(ifp); 4559 4560 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4561 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4562 4563 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 4564 4565 bce_init_locked_exit: 4566 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4567 4568 return; 4569 } 4570 4571 4572 /****************************************************************************/ 4573 /* Initialize the controller just enough so that any management firmware */ 4574 /* running on the device will continue to operate correctly. */ 4575 /* */ 4576 /* Returns: */ 4577 /* Nothing. */ 4578 /****************************************************************************/ 4579 static void 4580 bce_mgmt_init_locked(struct bce_softc *sc) 4581 { 4582 struct ifnet *ifp; 4583 4584 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__); 4585 4586 BCE_LOCK_ASSERT(sc); 4587 4588 /* Bail out if management firmware is not running. */ 4589 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) { 4590 DBPRINT(sc, BCE_VERBOSE_SPECIAL, 4591 "No management firmware running...\n"); 4592 goto bce_mgmt_init_locked_exit; 4593 } 4594 4595 ifp = sc->bce_ifp; 4596 4597 /* Enable all critical blocks in the MAC. */ 4598 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff); 4599 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS); 4600 DELAY(20); 4601 4602 bce_ifmedia_upd_locked(ifp); 4603 bce_mgmt_init_locked_exit: 4604 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__); 4605 4606 return; 4607 } 4608 4609 4610 /****************************************************************************/ 4611 /* Handles controller initialization when called from an unlocked routine. */ 4612 /* */ 4613 /* Returns: */ 4614 /* Nothing. */ 4615 /****************************************************************************/ 4616 static void 4617 bce_init(void *xsc) 4618 { 4619 struct bce_softc *sc = xsc; 4620 4621 BCE_LOCK(sc); 4622 bce_init_locked(sc); 4623 BCE_UNLOCK(sc); 4624 } 4625 4626 4627 /****************************************************************************/ 4628 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */ 4629 /* memory visible to the controller. */ 4630 /* */ 4631 /* Returns: */ 4632 /* 0 for success, positive value for failure. */ 4633 /****************************************************************************/ 4634 static int 4635 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head) 4636 { 4637 bus_dma_segment_t segs[BCE_MAX_SEGMENTS]; 4638 bus_dmamap_t map; 4639 struct tx_bd *txbd = NULL; 4640 struct mbuf *m0; 4641 struct ether_vlan_header *eh; 4642 struct ip *ip; 4643 struct tcphdr *th; 4644 u16 prod, chain_prod, etype, mss = 0, vlan_tag = 0, flags = 0; 4645 u32 prod_bseq; 4646 int hdr_len = 0, e_hlen = 0, ip_hlen = 0, tcp_hlen = 0, ip_len = 0; 4647 4648 4649 #ifdef BCE_DEBUG 4650 u16 debug_prod; 4651 #endif 4652 int i, error, nsegs, rc = 0; 4653 4654 /* Transfer any checksum offload flags to the bd. */ 4655 m0 = *m_head; 4656 if (m0->m_pkthdr.csum_flags) { 4657 if (m0->m_pkthdr.csum_flags & CSUM_IP) 4658 flags |= TX_BD_FLAGS_IP_CKSUM; 4659 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 4660 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; 4661 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 4662 /* For TSO the controller needs two pieces of info, */ 4663 /* the MSS and the IP+TCP options length. */ 4664 mss = htole16(m0->m_pkthdr.tso_segsz); 4665 4666 /* Map the header and find the Ethernet type & header length */ 4667 eh = mtod(m0, struct ether_vlan_header *); 4668 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 4669 etype = ntohs(eh->evl_proto); 4670 e_hlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4671 } else { 4672 etype = ntohs(eh->evl_encap_proto); 4673 e_hlen = ETHER_HDR_LEN; 4674 } 4675 4676 /* Check for supported TSO Ethernet types (only IPv4 for now) */ 4677 switch (etype) { 4678 case ETHERTYPE_IP: 4679 ip = (struct ip *)(m0->m_data + e_hlen); 4680 4681 /* TSO only supported for TCP protocol */ 4682 if (ip->ip_p != IPPROTO_TCP) { 4683 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n", 4684 __FILE__, __LINE__); 4685 goto bce_tx_encap_skip_tso; 4686 } 4687 4688 /* Get IP header length in bytes (min 20) */ 4689 ip_hlen = ip->ip_hl << 2; 4690 4691 /* Get the TCP header length in bytes (min 20) */ 4692 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 4693 tcp_hlen = (th->th_off << 2); 4694 4695 /* IP header length and checksum will be calc'd by hardware */ 4696 ip_len = ip->ip_len; 4697 ip->ip_len = 0; 4698 ip->ip_sum = 0; 4699 break; 4700 case ETHERTYPE_IPV6: 4701 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n", 4702 __FILE__, __LINE__); 4703 goto bce_tx_encap_skip_tso; 4704 default: 4705 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n", 4706 __FILE__, __LINE__); 4707 goto bce_tx_encap_skip_tso; 4708 } 4709 4710 hdr_len = e_hlen + ip_hlen + tcp_hlen; 4711 4712 DBPRINT(sc, BCE_EXCESSIVE_SEND, 4713 "%s(): hdr_len = %d, e_hlen = %d, ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n", 4714 __FUNCTION__, hdr_len, e_hlen, ip_hlen, tcp_hlen, ip_len); 4715 4716 /* Set the LSO flag in the TX BD */ 4717 flags |= TX_BD_FLAGS_SW_LSO; 4718 /* Set the length of IP + TCP options (in 32 bit words) */ 4719 flags |= (((ip_hlen + tcp_hlen - 40) >> 2) << 8); 4720 4721 bce_tx_encap_skip_tso: 4722 DBRUNIF(1, sc->requested_tso_frames++); 4723 } 4724 } 4725 4726 /* Transfer any VLAN tags to the bd. */ 4727 if (m0->m_flags & M_VLANTAG) { 4728 flags |= TX_BD_FLAGS_VLAN_TAG; 4729 vlan_tag = m0->m_pkthdr.ether_vtag; 4730 } 4731 4732 /* Map the mbuf into DMAable memory. */ 4733 prod = sc->tx_prod; 4734 chain_prod = TX_CHAIN_IDX(prod); 4735 map = sc->tx_mbuf_map[chain_prod]; 4736 4737 /* Map the mbuf into our DMA address space. */ 4738 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4739 segs, &nsegs, BUS_DMA_NOWAIT); 4740 4741 /* Check if the DMA mapping was successful */ 4742 if (error == EFBIG) { 4743 4744 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n", 4745 __FUNCTION__, nsegs); 4746 DBRUNIF(1, bce_dump_mbuf(sc, m0);); 4747 4748 /* Try to defrag the mbuf if there are too many segments. */ 4749 m0 = m_defrag(*m_head, M_DONTWAIT); 4750 if (m0 == NULL) { 4751 /* Defrag was unsuccessful */ 4752 m_freem(*m_head); 4753 *m_head = NULL; 4754 return (ENOBUFS); 4755 } 4756 4757 /* Defrag was successful, try mapping again */ 4758 *m_head = m0; 4759 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0, 4760 segs, &nsegs, BUS_DMA_NOWAIT); 4761 4762 /* Still getting an error after a defrag. */ 4763 if (error == ENOMEM) { 4764 return (error); 4765 } else if (error != 0) { 4766 BCE_PRINTF( 4767 "%s(%d): Unknown error mapping mbuf into TX chain!\n", 4768 __FILE__, __LINE__); 4769 m_freem(m0); 4770 *m_head = NULL; 4771 return (ENOBUFS); 4772 } 4773 } else if (error == ENOMEM) { 4774 return (error); 4775 } else if (error != 0) { 4776 m_freem(m0); 4777 *m_head = NULL; 4778 return (error); 4779 } 4780 4781 /* Make sure there's room in the chain */ 4782 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) { 4783 bus_dmamap_unload(sc->tx_mbuf_tag, map); 4784 return (ENOBUFS); 4785 } 4786 4787 /* prod points to an empty tx_bd at this point. */ 4788 prod_bseq = sc->tx_prod_bseq; 4789 4790 #ifdef BCE_DEBUG 4791 debug_prod = chain_prod; 4792 #endif 4793 4794 DBPRINT(sc, BCE_INFO_SEND, 4795 "%s(): Start: prod = 0x%04X, chain_prod = %04X, " 4796 "prod_bseq = 0x%08X\n", 4797 __FUNCTION__, prod, chain_prod, prod_bseq); 4798 4799 /* 4800 * Cycle through each mbuf segment that makes up 4801 * the outgoing frame, gathering the mapping info 4802 * for that segment and creating a tx_bd to for 4803 * the mbuf. 4804 */ 4805 for (i = 0; i < nsegs ; i++) { 4806 4807 chain_prod = TX_CHAIN_IDX(prod); 4808 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)]; 4809 4810 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr)); 4811 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr)); 4812 txbd->tx_bd_mss_nbytes = htole32(mss << 16) | htole16(segs[i].ds_len); 4813 txbd->tx_bd_vlan_tag = htole16(vlan_tag); 4814 txbd->tx_bd_flags = htole16(flags); 4815 prod_bseq += segs[i].ds_len; 4816 if (i == 0) 4817 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START); 4818 prod = NEXT_TX_BD(prod); 4819 } 4820 4821 /* Set the END flag on the last TX buffer descriptor. */ 4822 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END); 4823 4824 DBRUN(BCE_EXCESSIVE_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs)); 4825 4826 DBPRINT(sc, BCE_INFO_SEND, 4827 "%s(): End: prod = 0x%04X, chain_prod = %04X, " 4828 "prod_bseq = 0x%08X\n", 4829 __FUNCTION__, prod, chain_prod, prod_bseq); 4830 4831 /* 4832 * Ensure that the mbuf pointer for this transmission 4833 * is placed at the array index of the last 4834 * descriptor in this chain. This is done 4835 * because a single map is used for all 4836 * segments of the mbuf and we don't want to 4837 * unload the map before all of the segments 4838 * have been freed. 4839 */ 4840 sc->tx_mbuf_ptr[chain_prod] = m0; 4841 sc->used_tx_bd += nsegs; 4842 4843 /* Update some debug statistic counters */ 4844 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark), 4845 sc->tx_hi_watermark = sc->used_tx_bd); 4846 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++); 4847 DBRUNIF(1, sc->tx_mbuf_alloc++); 4848 4849 DBRUN(BCE_VERBOSE_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs)); 4850 4851 /* prod points to the next free tx_bd at this point. */ 4852 sc->tx_prod = prod; 4853 sc->tx_prod_bseq = prod_bseq; 4854 4855 return(rc); 4856 } 4857 4858 4859 /****************************************************************************/ 4860 /* Main transmit routine when called from another routine with a lock. */ 4861 /* */ 4862 /* Returns: */ 4863 /* Nothing. */ 4864 /****************************************************************************/ 4865 static void 4866 bce_start_locked(struct ifnet *ifp) 4867 { 4868 struct bce_softc *sc = ifp->if_softc; 4869 struct mbuf *m_head = NULL; 4870 int count = 0; 4871 u16 tx_prod, tx_chain_prod; 4872 4873 /* If there's no link or the transmit queue is empty then just exit. */ 4874 if (!sc->bce_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 4875 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link or transmit queue empty.\n", 4876 __FUNCTION__); 4877 goto bce_start_locked_exit; 4878 } 4879 4880 /* prod points to the next free tx_bd. */ 4881 tx_prod = sc->tx_prod; 4882 tx_chain_prod = TX_CHAIN_IDX(tx_prod); 4883 4884 DBPRINT(sc, BCE_INFO_SEND, 4885 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, " 4886 "tx_prod_bseq = 0x%08X\n", 4887 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4888 4889 /* 4890 * Keep adding entries while there is space in the ring. 4891 */ 4892 while (sc->used_tx_bd < sc->max_tx_bd) { 4893 4894 /* Check for any frames to send. */ 4895 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4896 if (m_head == NULL) 4897 break; 4898 4899 /* 4900 * Pack the data into the transmit ring. If we 4901 * don't have room, place the mbuf back at the 4902 * head of the queue and set the OACTIVE flag 4903 * to wait for the NIC to drain the chain. 4904 */ 4905 if (bce_tx_encap(sc, &m_head)) { 4906 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4907 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4908 DBPRINT(sc, BCE_INFO_SEND, 4909 "TX chain is closed for business! Total tx_bd used = %d\n", 4910 sc->used_tx_bd); 4911 break; 4912 } 4913 4914 count++; 4915 4916 /* Send a copy of the frame to any BPF listeners. */ 4917 ETHER_BPF_MTAP(ifp, m_head); 4918 } 4919 4920 if (count == 0) { 4921 /* no packets were dequeued */ 4922 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n", 4923 __FUNCTION__); 4924 goto bce_start_locked_exit; 4925 } 4926 4927 /* Update the driver's counters. */ 4928 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod); 4929 4930 DBPRINT(sc, BCE_INFO_SEND, 4931 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, " 4932 "tx_prod_bseq = 0x%08X\n", 4933 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq); 4934 4935 /* Start the transmit. */ 4936 REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod); 4937 REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq); 4938 4939 /* Set the tx timeout. */ 4940 sc->watchdog_timer = BCE_TX_TIMEOUT; 4941 4942 bce_start_locked_exit: 4943 return; 4944 } 4945 4946 4947 /****************************************************************************/ 4948 /* Main transmit routine when called from another routine without a lock. */ 4949 /* */ 4950 /* Returns: */ 4951 /* Nothing. */ 4952 /****************************************************************************/ 4953 static void 4954 bce_start(struct ifnet *ifp) 4955 { 4956 struct bce_softc *sc = ifp->if_softc; 4957 4958 BCE_LOCK(sc); 4959 bce_start_locked(ifp); 4960 BCE_UNLOCK(sc); 4961 } 4962 4963 4964 /****************************************************************************/ 4965 /* Handles any IOCTL calls from the operating system. */ 4966 /* */ 4967 /* Returns: */ 4968 /* 0 for success, positive value for failure. */ 4969 /****************************************************************************/ 4970 static int 4971 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4972 { 4973 struct bce_softc *sc = ifp->if_softc; 4974 struct ifreq *ifr = (struct ifreq *) data; 4975 struct mii_data *mii; 4976 int mask, error = 0; 4977 4978 switch(command) { 4979 4980 /* Set the interface MTU. */ 4981 case SIOCSIFMTU: 4982 /* Check that the MTU setting is supported. */ 4983 if ((ifr->ifr_mtu < BCE_MIN_MTU) || 4984 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) { 4985 error = EINVAL; 4986 break; 4987 } 4988 4989 DBPRINT(sc, BCE_INFO_MISC, 4990 "SIOCSIFMTU: Changing MTU from %d to %d\n", 4991 (int) ifp->if_mtu, (int) ifr->ifr_mtu); 4992 4993 BCE_LOCK(sc); 4994 ifp->if_mtu = ifr->ifr_mtu; 4995 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4996 bce_init_locked(sc); 4997 BCE_UNLOCK(sc); 4998 break; 4999 5000 /* Set interface flags. */ 5001 case SIOCSIFFLAGS: 5002 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n"); 5003 5004 BCE_LOCK(sc); 5005 5006 /* Check if the interface is up. */ 5007 if (ifp->if_flags & IFF_UP) { 5008 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5009 /* Change promiscuous/multicast flags as necessary. */ 5010 bce_set_rx_mode(sc); 5011 } else { 5012 /* Start the HW */ 5013 bce_init_locked(sc); 5014 } 5015 } else { 5016 /* The interface is down, check if driver is running. */ 5017 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5018 bce_stop(sc); 5019 5020 /* If MFW is running, restart the controller a bit. */ 5021 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) { 5022 bce_reset(sc, BCE_DRV_MSG_CODE_RESET); 5023 bce_chipinit(sc); 5024 bce_mgmt_init_locked(sc); 5025 } 5026 } 5027 } 5028 5029 BCE_UNLOCK(sc); 5030 error = 0; 5031 5032 break; 5033 5034 /* Add/Delete multicast address */ 5035 case SIOCADDMULTI: 5036 case SIOCDELMULTI: 5037 DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCADDMULTI/SIOCDELMULTI\n"); 5038 5039 BCE_LOCK(sc); 5040 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5041 bce_set_rx_mode(sc); 5042 error = 0; 5043 } 5044 BCE_UNLOCK(sc); 5045 5046 break; 5047 5048 /* Set/Get Interface media */ 5049 case SIOCSIFMEDIA: 5050 case SIOCGIFMEDIA: 5051 DBPRINT(sc, BCE_VERBOSE_MISC, "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n"); 5052 5053 mii = device_get_softc(sc->bce_miibus); 5054 error = ifmedia_ioctl(ifp, ifr, 5055 &mii->mii_media, command); 5056 break; 5057 5058 /* Set interface capability */ 5059 case SIOCSIFCAP: 5060 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5061 DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask); 5062 5063 #ifdef DEVICE_POLLING 5064 if (mask & IFCAP_POLLING) { 5065 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5066 5067 /* Setup the poll routine to call. */ 5068 error = ether_poll_register(bce_poll, ifp); 5069 if (error) { 5070 BCE_PRINTF("%s(%d): Error registering poll function!\n", 5071 __FILE__, __LINE__); 5072 goto bce_ioctl_exit; 5073 } 5074 5075 /* Clear the interrupt. */ 5076 BCE_LOCK(sc); 5077 bce_disable_intr(sc); 5078 5079 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5080 (1 << 16) | sc->bce_rx_quick_cons_trip); 5081 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5082 (1 << 16) | sc->bce_tx_quick_cons_trip); 5083 5084 ifp->if_capenable |= IFCAP_POLLING; 5085 BCE_UNLOCK(sc); 5086 } else { 5087 /* Clear the poll routine. */ 5088 error = ether_poll_deregister(ifp); 5089 5090 /* Enable interrupt even in error case */ 5091 BCE_LOCK(sc); 5092 bce_enable_intr(sc); 5093 5094 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP, 5095 (sc->bce_tx_quick_cons_trip_int << 16) | 5096 sc->bce_tx_quick_cons_trip); 5097 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP, 5098 (sc->bce_rx_quick_cons_trip_int << 16) | 5099 sc->bce_rx_quick_cons_trip); 5100 5101 ifp->if_capenable &= ~IFCAP_POLLING; 5102 BCE_UNLOCK(sc); 5103 } 5104 } 5105 #endif /*DEVICE_POLLING */ 5106 5107 /* Toggle the TX checksum capabilites enable flag. */ 5108 if (mask & IFCAP_TXCSUM) { 5109 ifp->if_capenable ^= IFCAP_TXCSUM; 5110 if (IFCAP_TXCSUM & ifp->if_capenable) 5111 ifp->if_hwassist = BCE_IF_HWASSIST; 5112 else 5113 ifp->if_hwassist = 0; 5114 } 5115 5116 /* Toggle the RX checksum capabilities enable flag. */ 5117 if (mask & IFCAP_RXCSUM) { 5118 ifp->if_capenable ^= IFCAP_RXCSUM; 5119 if (IFCAP_RXCSUM & ifp->if_capenable) 5120 ifp->if_hwassist = BCE_IF_HWASSIST; 5121 else 5122 ifp->if_hwassist = 0; 5123 } 5124 5125 /* Toggle the TSO capabilities enable flag. */ 5126 if (bce_tso_enable && (mask & IFCAP_TSO4)) { 5127 ifp->if_capenable ^= IFCAP_TSO4; 5128 if (IFCAP_RXCSUM & ifp->if_capenable) 5129 ifp->if_hwassist = BCE_IF_HWASSIST; 5130 else 5131 ifp->if_hwassist = 0; 5132 } 5133 5134 /* Toggle VLAN_MTU capabilities enable flag. */ 5135 if (mask & IFCAP_VLAN_MTU) { 5136 BCE_PRINTF("%s(%d): Changing VLAN_MTU not supported.\n", 5137 __FILE__, __LINE__); 5138 } 5139 5140 /* Toggle VLANHWTAG capabilities enabled flag. */ 5141 if (mask & IFCAP_VLAN_HWTAGGING) { 5142 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) 5143 BCE_PRINTF("%s(%d): Cannot change VLAN_HWTAGGING while " 5144 "management firmware (ASF/IPMI/UMP) is running!\n", 5145 __FILE__, __LINE__); 5146 else 5147 BCE_PRINTF("%s(%d): Changing VLAN_HWTAGGING not supported!\n", 5148 __FILE__, __LINE__); 5149 } 5150 5151 break; 5152 default: 5153 /* We don't know how to handle the IOCTL, pass it on. */ 5154 error = ether_ioctl(ifp, command, data); 5155 break; 5156 } 5157 5158 #ifdef DEVICE_POLLING 5159 bce_ioctl_exit: 5160 #endif 5161 return(error); 5162 } 5163 5164 5165 /****************************************************************************/ 5166 /* Transmit timeout handler. */ 5167 /* */ 5168 /* Returns: */ 5169 /* Nothing. */ 5170 /****************************************************************************/ 5171 static void 5172 bce_watchdog(struct bce_softc *sc) 5173 { 5174 5175 BCE_LOCK_ASSERT(sc); 5176 5177 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 5178 return; 5179 5180 /* 5181 * If we are in this routine because of pause frames, then 5182 * don't reset the hardware. 5183 */ 5184 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED) 5185 return; 5186 5187 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n", 5188 __FILE__, __LINE__); 5189 5190 DBRUN(BCE_VERBOSE_SEND, 5191 bce_dump_driver_state(sc); 5192 bce_dump_status_block(sc)); 5193 5194 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */ 5195 5196 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5197 5198 bce_init_locked(sc); 5199 sc->bce_ifp->if_oerrors++; 5200 5201 } 5202 5203 5204 #ifdef DEVICE_POLLING 5205 static void 5206 bce_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 5207 { 5208 struct bce_softc *sc = ifp->if_softc; 5209 5210 BCE_LOCK_ASSERT(sc); 5211 5212 sc->bce_rxcycles = count; 5213 5214 bus_dmamap_sync(sc->status_tag, sc->status_map, 5215 BUS_DMASYNC_POSTWRITE); 5216 5217 /* Check for any completed RX frames. */ 5218 if (sc->status_block->status_rx_quick_consumer_index0 != 5219 sc->hw_rx_cons) 5220 bce_rx_intr(sc); 5221 5222 /* Check for any completed TX frames. */ 5223 if (sc->status_block->status_tx_quick_consumer_index0 != 5224 sc->hw_tx_cons) 5225 bce_tx_intr(sc); 5226 5227 /* Check for new frames to transmit. */ 5228 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5229 bce_start_locked(ifp); 5230 5231 } 5232 5233 5234 static void 5235 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 5236 { 5237 struct bce_softc *sc = ifp->if_softc; 5238 5239 BCE_LOCK(sc); 5240 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5241 bce_poll_locked(ifp, cmd, count); 5242 BCE_UNLOCK(sc); 5243 } 5244 #endif /* DEVICE_POLLING */ 5245 5246 5247 #if 0 5248 static inline int 5249 bce_has_work(struct bce_softc *sc) 5250 { 5251 struct status_block *stat = sc->status_block; 5252 5253 if ((stat->status_rx_quick_consumer_index0 != sc->hw_rx_cons) || 5254 (stat->status_tx_quick_consumer_index0 != sc->hw_tx_cons)) 5255 return 1; 5256 5257 if (((stat->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) != 5258 bp->link_up) 5259 return 1; 5260 5261 return 0; 5262 } 5263 #endif 5264 5265 5266 /* 5267 * Interrupt handler. 5268 */ 5269 /****************************************************************************/ 5270 /* Main interrupt entry point. Verifies that the controller generated the */ 5271 /* interrupt and then calls a separate routine for handle the various */ 5272 /* interrupt causes (PHY, TX, RX). */ 5273 /* */ 5274 /* Returns: */ 5275 /* 0 for success, positive value for failure. */ 5276 /****************************************************************************/ 5277 static void 5278 bce_intr(void *xsc) 5279 { 5280 struct bce_softc *sc; 5281 struct ifnet *ifp; 5282 u32 status_attn_bits; 5283 5284 sc = xsc; 5285 ifp = sc->bce_ifp; 5286 5287 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 5288 BCE_LOCK(sc); 5289 5290 DBRUNIF(1, sc->interrupts_generated++); 5291 5292 #ifdef DEVICE_POLLING 5293 if (ifp->if_capenable & IFCAP_POLLING) { 5294 DBPRINT(sc, BCE_INFO_MISC, "Polling enabled!\n"); 5295 goto bce_intr_exit; 5296 } 5297 #endif 5298 5299 bus_dmamap_sync(sc->status_tag, sc->status_map, 5300 BUS_DMASYNC_POSTWRITE); 5301 5302 /* 5303 * If the hardware status block index 5304 * matches the last value read by the 5305 * driver and we haven't asserted our 5306 * interrupt then there's nothing to do. 5307 */ 5308 if ((sc->status_block->status_idx == sc->last_status_idx) && 5309 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) 5310 goto bce_intr_exit; 5311 5312 /* Ack the interrupt and stop others from occuring. */ 5313 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5314 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | 5315 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5316 5317 /* Keep processing data as long as there is work to do. */ 5318 for (;;) { 5319 5320 status_attn_bits = sc->status_block->status_attn_bits; 5321 5322 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention), 5323 BCE_PRINTF("Simulating unexpected status attention bit set."); 5324 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR); 5325 5326 /* Was it a link change interrupt? */ 5327 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 5328 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) 5329 bce_phy_intr(sc); 5330 5331 /* If any other attention is asserted then the chip is toast. */ 5332 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != 5333 (sc->status_block->status_attn_bits_ack & 5334 ~STATUS_ATTN_BITS_LINK_STATE))) { 5335 5336 DBRUN(1, sc->unexpected_attentions++); 5337 5338 BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n", 5339 __FILE__, __LINE__, sc->status_block->status_attn_bits); 5340 5341 DBRUN(BCE_FATAL, 5342 if (bce_debug_unexpected_attention == 0) 5343 bce_breakpoint(sc)); 5344 5345 bce_init_locked(sc); 5346 goto bce_intr_exit; 5347 } 5348 5349 /* Check for any completed RX frames. */ 5350 if (sc->status_block->status_rx_quick_consumer_index0 != sc->hw_rx_cons) 5351 bce_rx_intr(sc); 5352 5353 /* Check for any completed TX frames. */ 5354 if (sc->status_block->status_tx_quick_consumer_index0 != sc->hw_tx_cons) 5355 bce_tx_intr(sc); 5356 5357 /* Save the status block index value for use during the next interrupt. */ 5358 sc->last_status_idx = sc->status_block->status_idx; 5359 5360 /* Prevent speculative reads from getting ahead of the status block. */ 5361 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0, 5362 BUS_SPACE_BARRIER_READ); 5363 5364 /* If there's no work left then exit the interrupt service routine. */ 5365 if ((sc->status_block->status_rx_quick_consumer_index0 == sc->hw_rx_cons) && 5366 (sc->status_block->status_tx_quick_consumer_index0 == sc->hw_tx_cons)) 5367 break; 5368 5369 } 5370 5371 bus_dmamap_sync(sc->status_tag, sc->status_map, 5372 BUS_DMASYNC_PREWRITE); 5373 5374 /* Re-enable interrupts. */ 5375 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5376 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx | 5377 BCE_PCICFG_INT_ACK_CMD_MASK_INT); 5378 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, 5379 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); 5380 5381 /* Handle any frames that arrived while handling the interrupt. */ 5382 if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5383 bce_start_locked(ifp); 5384 5385 bce_intr_exit: 5386 BCE_UNLOCK(sc); 5387 } 5388 5389 5390 /****************************************************************************/ 5391 /* Programs the various packet receive modes (broadcast and multicast). */ 5392 /* */ 5393 /* Returns: */ 5394 /* Nothing. */ 5395 /****************************************************************************/ 5396 static void 5397 bce_set_rx_mode(struct bce_softc *sc) 5398 { 5399 struct ifnet *ifp; 5400 struct ifmultiaddr *ifma; 5401 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 5402 u32 rx_mode, sort_mode; 5403 int h, i; 5404 5405 BCE_LOCK_ASSERT(sc); 5406 5407 ifp = sc->bce_ifp; 5408 5409 /* Initialize receive mode default settings. */ 5410 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS | 5411 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG); 5412 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN; 5413 5414 /* 5415 * ASF/IPMI/UMP firmware requires that VLAN tag stripping 5416 * be enbled. 5417 */ 5418 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) && 5419 (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))) 5420 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG; 5421 5422 /* 5423 * Check for promiscuous, all multicast, or selected 5424 * multicast address filtering. 5425 */ 5426 if (ifp->if_flags & IFF_PROMISC) { 5427 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n"); 5428 5429 /* Enable promiscuous mode. */ 5430 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS; 5431 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN; 5432 } else if (ifp->if_flags & IFF_ALLMULTI) { 5433 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n"); 5434 5435 /* Enable all multicast addresses. */ 5436 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { 5437 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff); 5438 } 5439 sort_mode |= BCE_RPM_SORT_USER0_MC_EN; 5440 } else { 5441 /* Accept one or more multicast(s). */ 5442 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n"); 5443 5444 IF_ADDR_LOCK(ifp); 5445 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 5446 if (ifma->ifma_addr->sa_family != AF_LINK) 5447 continue; 5448 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 5449 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 5450 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F); 5451 } 5452 IF_ADDR_UNLOCK(ifp); 5453 5454 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) 5455 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]); 5456 5457 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN; 5458 } 5459 5460 /* Only make changes if the recive mode has actually changed. */ 5461 if (rx_mode != sc->rx_mode) { 5462 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: 0x%08X\n", 5463 rx_mode); 5464 5465 sc->rx_mode = rx_mode; 5466 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode); 5467 } 5468 5469 /* Disable and clear the exisitng sort before enabling a new sort. */ 5470 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0); 5471 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode); 5472 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA); 5473 } 5474 5475 5476 /****************************************************************************/ 5477 /* Called periodically to updates statistics from the controllers */ 5478 /* statistics block. */ 5479 /* */ 5480 /* Returns: */ 5481 /* Nothing. */ 5482 /****************************************************************************/ 5483 static void 5484 bce_stats_update(struct bce_softc *sc) 5485 { 5486 struct ifnet *ifp; 5487 struct statistics_block *stats; 5488 5489 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__); 5490 5491 ifp = sc->bce_ifp; 5492 5493 stats = (struct statistics_block *) sc->stats_block; 5494 5495 /* 5496 * Update the interface statistics from the 5497 * hardware statistics. 5498 */ 5499 ifp->if_collisions = (u_long) stats->stat_EtherStatsCollisions; 5500 5501 ifp->if_ierrors = (u_long) stats->stat_EtherStatsUndersizePkts + 5502 (u_long) stats->stat_EtherStatsOverrsizePkts + 5503 (u_long) stats->stat_IfInMBUFDiscards + 5504 (u_long) stats->stat_Dot3StatsAlignmentErrors + 5505 (u_long) stats->stat_Dot3StatsFCSErrors; 5506 5507 ifp->if_oerrors = (u_long) stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors + 5508 (u_long) stats->stat_Dot3StatsExcessiveCollisions + 5509 (u_long) stats->stat_Dot3StatsLateCollisions; 5510 5511 /* 5512 * Certain controllers don't report 5513 * carrier sense errors correctly. 5514 * See errata E11_5708CA0_1165. 5515 */ 5516 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) && 5517 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) 5518 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors; 5519 5520 /* 5521 * Update the sysctl statistics from the 5522 * hardware statistics. 5523 */ 5524 sc->stat_IfHCInOctets = 5525 ((u64) stats->stat_IfHCInOctets_hi << 32) + 5526 (u64) stats->stat_IfHCInOctets_lo; 5527 5528 sc->stat_IfHCInBadOctets = 5529 ((u64) stats->stat_IfHCInBadOctets_hi << 32) + 5530 (u64) stats->stat_IfHCInBadOctets_lo; 5531 5532 sc->stat_IfHCOutOctets = 5533 ((u64) stats->stat_IfHCOutOctets_hi << 32) + 5534 (u64) stats->stat_IfHCOutOctets_lo; 5535 5536 sc->stat_IfHCOutBadOctets = 5537 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) + 5538 (u64) stats->stat_IfHCOutBadOctets_lo; 5539 5540 sc->stat_IfHCInUcastPkts = 5541 ((u64) stats->stat_IfHCInUcastPkts_hi << 32) + 5542 (u64) stats->stat_IfHCInUcastPkts_lo; 5543 5544 sc->stat_IfHCInMulticastPkts = 5545 ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) + 5546 (u64) stats->stat_IfHCInMulticastPkts_lo; 5547 5548 sc->stat_IfHCInBroadcastPkts = 5549 ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) + 5550 (u64) stats->stat_IfHCInBroadcastPkts_lo; 5551 5552 sc->stat_IfHCOutUcastPkts = 5553 ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) + 5554 (u64) stats->stat_IfHCOutUcastPkts_lo; 5555 5556 sc->stat_IfHCOutMulticastPkts = 5557 ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) + 5558 (u64) stats->stat_IfHCOutMulticastPkts_lo; 5559 5560 sc->stat_IfHCOutBroadcastPkts = 5561 ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) + 5562 (u64) stats->stat_IfHCOutBroadcastPkts_lo; 5563 5564 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors = 5565 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 5566 5567 sc->stat_Dot3StatsCarrierSenseErrors = 5568 stats->stat_Dot3StatsCarrierSenseErrors; 5569 5570 sc->stat_Dot3StatsFCSErrors = 5571 stats->stat_Dot3StatsFCSErrors; 5572 5573 sc->stat_Dot3StatsAlignmentErrors = 5574 stats->stat_Dot3StatsAlignmentErrors; 5575 5576 sc->stat_Dot3StatsSingleCollisionFrames = 5577 stats->stat_Dot3StatsSingleCollisionFrames; 5578 5579 sc->stat_Dot3StatsMultipleCollisionFrames = 5580 stats->stat_Dot3StatsMultipleCollisionFrames; 5581 5582 sc->stat_Dot3StatsDeferredTransmissions = 5583 stats->stat_Dot3StatsDeferredTransmissions; 5584 5585 sc->stat_Dot3StatsExcessiveCollisions = 5586 stats->stat_Dot3StatsExcessiveCollisions; 5587 5588 sc->stat_Dot3StatsLateCollisions = 5589 stats->stat_Dot3StatsLateCollisions; 5590 5591 sc->stat_EtherStatsCollisions = 5592 stats->stat_EtherStatsCollisions; 5593 5594 sc->stat_EtherStatsFragments = 5595 stats->stat_EtherStatsFragments; 5596 5597 sc->stat_EtherStatsJabbers = 5598 stats->stat_EtherStatsJabbers; 5599 5600 sc->stat_EtherStatsUndersizePkts = 5601 stats->stat_EtherStatsUndersizePkts; 5602 5603 sc->stat_EtherStatsOverrsizePkts = 5604 stats->stat_EtherStatsOverrsizePkts; 5605 5606 sc->stat_EtherStatsPktsRx64Octets = 5607 stats->stat_EtherStatsPktsRx64Octets; 5608 5609 sc->stat_EtherStatsPktsRx65Octetsto127Octets = 5610 stats->stat_EtherStatsPktsRx65Octetsto127Octets; 5611 5612 sc->stat_EtherStatsPktsRx128Octetsto255Octets = 5613 stats->stat_EtherStatsPktsRx128Octetsto255Octets; 5614 5615 sc->stat_EtherStatsPktsRx256Octetsto511Octets = 5616 stats->stat_EtherStatsPktsRx256Octetsto511Octets; 5617 5618 sc->stat_EtherStatsPktsRx512Octetsto1023Octets = 5619 stats->stat_EtherStatsPktsRx512Octetsto1023Octets; 5620 5621 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets = 5622 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets; 5623 5624 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets = 5625 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets; 5626 5627 sc->stat_EtherStatsPktsTx64Octets = 5628 stats->stat_EtherStatsPktsTx64Octets; 5629 5630 sc->stat_EtherStatsPktsTx65Octetsto127Octets = 5631 stats->stat_EtherStatsPktsTx65Octetsto127Octets; 5632 5633 sc->stat_EtherStatsPktsTx128Octetsto255Octets = 5634 stats->stat_EtherStatsPktsTx128Octetsto255Octets; 5635 5636 sc->stat_EtherStatsPktsTx256Octetsto511Octets = 5637 stats->stat_EtherStatsPktsTx256Octetsto511Octets; 5638 5639 sc->stat_EtherStatsPktsTx512Octetsto1023Octets = 5640 stats->stat_EtherStatsPktsTx512Octetsto1023Octets; 5641 5642 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets = 5643 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets; 5644 5645 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets = 5646 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets; 5647 5648 sc->stat_XonPauseFramesReceived = 5649 stats->stat_XonPauseFramesReceived; 5650 5651 sc->stat_XoffPauseFramesReceived = 5652 stats->stat_XoffPauseFramesReceived; 5653 5654 sc->stat_OutXonSent = 5655 stats->stat_OutXonSent; 5656 5657 sc->stat_OutXoffSent = 5658 stats->stat_OutXoffSent; 5659 5660 sc->stat_FlowControlDone = 5661 stats->stat_FlowControlDone; 5662 5663 sc->stat_MacControlFramesReceived = 5664 stats->stat_MacControlFramesReceived; 5665 5666 sc->stat_XoffStateEntered = 5667 stats->stat_XoffStateEntered; 5668 5669 sc->stat_IfInFramesL2FilterDiscards = 5670 stats->stat_IfInFramesL2FilterDiscards; 5671 5672 sc->stat_IfInRuleCheckerDiscards = 5673 stats->stat_IfInRuleCheckerDiscards; 5674 5675 sc->stat_IfInFTQDiscards = 5676 stats->stat_IfInFTQDiscards; 5677 5678 sc->stat_IfInMBUFDiscards = 5679 stats->stat_IfInMBUFDiscards; 5680 5681 sc->stat_IfInRuleCheckerP4Hit = 5682 stats->stat_IfInRuleCheckerP4Hit; 5683 5684 sc->stat_CatchupInRuleCheckerDiscards = 5685 stats->stat_CatchupInRuleCheckerDiscards; 5686 5687 sc->stat_CatchupInFTQDiscards = 5688 stats->stat_CatchupInFTQDiscards; 5689 5690 sc->stat_CatchupInMBUFDiscards = 5691 stats->stat_CatchupInMBUFDiscards; 5692 5693 sc->stat_CatchupInRuleCheckerP4Hit = 5694 stats->stat_CatchupInRuleCheckerP4Hit; 5695 5696 sc->com_no_buffers = REG_RD_IND(sc, 0x120084); 5697 5698 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __FUNCTION__); 5699 } 5700 5701 5702 /****************************************************************************/ 5703 /* Periodic function to notify the bootcode that the driver is still */ 5704 /* present. */ 5705 /* */ 5706 /* Returns: */ 5707 /* Nothing. */ 5708 /****************************************************************************/ 5709 static void 5710 bce_pulse(void *xsc) 5711 { 5712 struct bce_softc *sc = xsc; 5713 u32 msg; 5714 5715 DBPRINT(sc, BCE_EXCESSIVE_MISC, "pulse\n"); 5716 5717 BCE_LOCK_ASSERT(sc); 5718 5719 /* Tell the firmware that the driver is still running. */ 5720 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq; 5721 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg); 5722 5723 /* Schedule the next pulse. */ 5724 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc); 5725 5726 return; 5727 } 5728 5729 5730 /****************************************************************************/ 5731 /* Periodic function to perform maintenance tasks. */ 5732 /* */ 5733 /* Returns: */ 5734 /* Nothing. */ 5735 /****************************************************************************/ 5736 static void 5737 bce_tick(void *xsc) 5738 { 5739 struct bce_softc *sc = xsc; 5740 struct mii_data *mii; 5741 struct ifnet *ifp; 5742 5743 ifp = sc->bce_ifp; 5744 5745 BCE_LOCK_ASSERT(sc); 5746 5747 /* Update the statistics from the hardware statistics block. */ 5748 bce_stats_update(sc); 5749 5750 /* Check that chip hasn't hung. */ 5751 bce_watchdog(sc); 5752 5753 /* Schedule the next tick. */ 5754 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc); 5755 5756 /* If link is up already up then we're done. */ 5757 if (sc->bce_link) 5758 goto bce_tick_locked_exit; 5759 5760 mii = device_get_softc(sc->bce_miibus); 5761 mii_tick(mii); 5762 5763 /* Check if the link has come up. */ 5764 if (!sc->bce_link && mii->mii_media_status & IFM_ACTIVE && 5765 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5766 sc->bce_link++; 5767 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 5768 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) && 5769 bootverbose) 5770 BCE_PRINTF("Gigabit link up\n"); 5771 /* Now that link is up, handle any outstanding TX traffic. */ 5772 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 5773 bce_start_locked(ifp); 5774 } 5775 5776 bce_tick_locked_exit: 5777 return; 5778 } 5779 5780 5781 #ifdef BCE_DEBUG 5782 /****************************************************************************/ 5783 /* Allows the driver state to be dumped through the sysctl interface. */ 5784 /* */ 5785 /* Returns: */ 5786 /* 0 for success, positive value for failure. */ 5787 /****************************************************************************/ 5788 static int 5789 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS) 5790 { 5791 int error; 5792 int result; 5793 struct bce_softc *sc; 5794 5795 result = -1; 5796 error = sysctl_handle_int(oidp, &result, 0, req); 5797 5798 if (error || !req->newptr) 5799 return (error); 5800 5801 if (result == 1) { 5802 sc = (struct bce_softc *)arg1; 5803 bce_dump_driver_state(sc); 5804 } 5805 5806 return error; 5807 } 5808 5809 5810 /****************************************************************************/ 5811 /* Allows the hardware state to be dumped through the sysctl interface. */ 5812 /* */ 5813 /* Returns: */ 5814 /* 0 for success, positive value for failure. */ 5815 /****************************************************************************/ 5816 static int 5817 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS) 5818 { 5819 int error; 5820 int result; 5821 struct bce_softc *sc; 5822 5823 result = -1; 5824 error = sysctl_handle_int(oidp, &result, 0, req); 5825 5826 if (error || !req->newptr) 5827 return (error); 5828 5829 if (result == 1) { 5830 sc = (struct bce_softc *)arg1; 5831 bce_dump_hw_state(sc); 5832 } 5833 5834 return error; 5835 } 5836 5837 5838 /****************************************************************************/ 5839 /* Allows the bootcode state to be dumped through the sysctl interface. */ 5840 /* */ 5841 /* Returns: */ 5842 /* 0 for success, positive value for failure. */ 5843 /****************************************************************************/ 5844 static int 5845 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS) 5846 { 5847 int error; 5848 int result; 5849 struct bce_softc *sc; 5850 5851 result = -1; 5852 error = sysctl_handle_int(oidp, &result, 0, req); 5853 5854 if (error || !req->newptr) 5855 return (error); 5856 5857 if (result == 1) { 5858 sc = (struct bce_softc *)arg1; 5859 bce_dump_bc_state(sc); 5860 } 5861 5862 return error; 5863 } 5864 5865 5866 /****************************************************************************/ 5867 /* Provides a sysctl interface to allow dumping the RX chain. */ 5868 /* */ 5869 /* Returns: */ 5870 /* 0 for success, positive value for failure. */ 5871 /****************************************************************************/ 5872 static int 5873 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS) 5874 { 5875 int error; 5876 int result; 5877 struct bce_softc *sc; 5878 5879 result = -1; 5880 error = sysctl_handle_int(oidp, &result, 0, req); 5881 5882 if (error || !req->newptr) 5883 return (error); 5884 5885 if (result == 1) { 5886 sc = (struct bce_softc *)arg1; 5887 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 5888 } 5889 5890 return error; 5891 } 5892 5893 5894 /****************************************************************************/ 5895 /* Provides a sysctl interface to allow dumping the TX chain. */ 5896 /* */ 5897 /* Returns: */ 5898 /* 0 for success, positive value for failure. */ 5899 /****************************************************************************/ 5900 static int 5901 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS) 5902 { 5903 int error; 5904 int result; 5905 struct bce_softc *sc; 5906 5907 result = -1; 5908 error = sysctl_handle_int(oidp, &result, 0, req); 5909 5910 if (error || !req->newptr) 5911 return (error); 5912 5913 if (result == 1) { 5914 sc = (struct bce_softc *)arg1; 5915 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 5916 } 5917 5918 return error; 5919 } 5920 5921 5922 /****************************************************************************/ 5923 /* Provides a sysctl interface to allow reading arbitrary registers in the */ 5924 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 5925 /* */ 5926 /* Returns: */ 5927 /* 0 for success, positive value for failure. */ 5928 /****************************************************************************/ 5929 static int 5930 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5931 { 5932 struct bce_softc *sc; 5933 int error; 5934 u32 val, result; 5935 5936 result = -1; 5937 error = sysctl_handle_int(oidp, &result, 0, req); 5938 if (error || (req->newptr == NULL)) 5939 return (error); 5940 5941 /* Make sure the register is accessible. */ 5942 if (result < 0x8000) { 5943 sc = (struct bce_softc *)arg1; 5944 val = REG_RD(sc, result); 5945 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 5946 } else if (result < 0x0280000) { 5947 sc = (struct bce_softc *)arg1; 5948 val = REG_RD_IND(sc, result); 5949 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val); 5950 } 5951 5952 return (error); 5953 } 5954 5955 5956 /****************************************************************************/ 5957 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */ 5958 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 5959 /* */ 5960 /* Returns: */ 5961 /* 0 for success, positive value for failure. */ 5962 /****************************************************************************/ 5963 static int 5964 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS) 5965 { 5966 struct bce_softc *sc; 5967 device_t dev; 5968 int error, result; 5969 u16 val; 5970 5971 result = -1; 5972 error = sysctl_handle_int(oidp, &result, 0, req); 5973 if (error || (req->newptr == NULL)) 5974 return (error); 5975 5976 /* Make sure the register is accessible. */ 5977 if (result < 0x20) { 5978 sc = (struct bce_softc *)arg1; 5979 dev = sc->bce_dev; 5980 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result); 5981 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val); 5982 } 5983 return (error); 5984 } 5985 5986 5987 /****************************************************************************/ 5988 /* Provides a sysctl interface to forcing the driver to dump state and */ 5989 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */ 5990 /* */ 5991 /* Returns: */ 5992 /* 0 for success, positive value for failure. */ 5993 /****************************************************************************/ 5994 static int 5995 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS) 5996 { 5997 int error; 5998 int result; 5999 struct bce_softc *sc; 6000 6001 result = -1; 6002 error = sysctl_handle_int(oidp, &result, 0, req); 6003 6004 if (error || !req->newptr) 6005 return (error); 6006 6007 if (result == 1) { 6008 sc = (struct bce_softc *)arg1; 6009 bce_breakpoint(sc); 6010 } 6011 6012 return error; 6013 } 6014 #endif 6015 6016 6017 /****************************************************************************/ 6018 /* Adds any sysctl parameters for tuning or debugging purposes. */ 6019 /* */ 6020 /* Returns: */ 6021 /* 0 for success, positive value for failure. */ 6022 /****************************************************************************/ 6023 static void 6024 bce_add_sysctls(struct bce_softc *sc) 6025 { 6026 struct sysctl_ctx_list *ctx; 6027 struct sysctl_oid_list *children; 6028 6029 ctx = device_get_sysctl_ctx(sc->bce_dev); 6030 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev)); 6031 6032 #ifdef BCE_DEBUG 6033 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6034 "rx_low_watermark", 6035 CTLFLAG_RD, &sc->rx_low_watermark, 6036 0, "Lowest level of free rx_bd's"); 6037 6038 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6039 "rx_empty_count", 6040 CTLFLAG_RD, &sc->rx_empty_count, 6041 0, "Number of times the RX chain was empty"); 6042 6043 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6044 "tx_hi_watermark", 6045 CTLFLAG_RD, &sc->tx_hi_watermark, 6046 0, "Highest level of used tx_bd's"); 6047 6048 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6049 "tx_full_count", 6050 CTLFLAG_RD, &sc->tx_full_count, 6051 0, "Number of times the TX chain was full"); 6052 6053 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6054 "l2fhdr_status_errors", 6055 CTLFLAG_RD, &sc->l2fhdr_status_errors, 6056 0, "l2_fhdr status errors"); 6057 6058 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6059 "unexpected_attentions", 6060 CTLFLAG_RD, &sc->unexpected_attentions, 6061 0, "unexpected attentions"); 6062 6063 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6064 "lost_status_block_updates", 6065 CTLFLAG_RD, &sc->lost_status_block_updates, 6066 0, "lost status block updates"); 6067 6068 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6069 "mbuf_alloc_failed", 6070 CTLFLAG_RD, &sc->mbuf_alloc_failed, 6071 0, "mbuf cluster allocation failures"); 6072 6073 SYSCTL_ADD_INT(ctx, children, OID_AUTO, 6074 "requested_tso_frames", 6075 CTLFLAG_RD, &sc->requested_tso_frames, 6076 0, "The number of TSO frames received"); 6077 #endif 6078 6079 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6080 "stat_IfHcInOctets", 6081 CTLFLAG_RD, &sc->stat_IfHCInOctets, 6082 "Bytes received"); 6083 6084 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6085 "stat_IfHCInBadOctets", 6086 CTLFLAG_RD, &sc->stat_IfHCInBadOctets, 6087 "Bad bytes received"); 6088 6089 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6090 "stat_IfHCOutOctets", 6091 CTLFLAG_RD, &sc->stat_IfHCOutOctets, 6092 "Bytes sent"); 6093 6094 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6095 "stat_IfHCOutBadOctets", 6096 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets, 6097 "Bad bytes sent"); 6098 6099 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6100 "stat_IfHCInUcastPkts", 6101 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts, 6102 "Unicast packets received"); 6103 6104 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6105 "stat_IfHCInMulticastPkts", 6106 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts, 6107 "Multicast packets received"); 6108 6109 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6110 "stat_IfHCInBroadcastPkts", 6111 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts, 6112 "Broadcast packets received"); 6113 6114 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6115 "stat_IfHCOutUcastPkts", 6116 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts, 6117 "Unicast packets sent"); 6118 6119 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6120 "stat_IfHCOutMulticastPkts", 6121 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts, 6122 "Multicast packets sent"); 6123 6124 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, 6125 "stat_IfHCOutBroadcastPkts", 6126 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts, 6127 "Broadcast packets sent"); 6128 6129 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6130 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors", 6131 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors, 6132 0, "Internal MAC transmit errors"); 6133 6134 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6135 "stat_Dot3StatsCarrierSenseErrors", 6136 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors, 6137 0, "Carrier sense errors"); 6138 6139 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6140 "stat_Dot3StatsFCSErrors", 6141 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors, 6142 0, "Frame check sequence errors"); 6143 6144 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6145 "stat_Dot3StatsAlignmentErrors", 6146 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors, 6147 0, "Alignment errors"); 6148 6149 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6150 "stat_Dot3StatsSingleCollisionFrames", 6151 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames, 6152 0, "Single Collision Frames"); 6153 6154 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6155 "stat_Dot3StatsMultipleCollisionFrames", 6156 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames, 6157 0, "Multiple Collision Frames"); 6158 6159 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6160 "stat_Dot3StatsDeferredTransmissions", 6161 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions, 6162 0, "Deferred Transmissions"); 6163 6164 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6165 "stat_Dot3StatsExcessiveCollisions", 6166 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions, 6167 0, "Excessive Collisions"); 6168 6169 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6170 "stat_Dot3StatsLateCollisions", 6171 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions, 6172 0, "Late Collisions"); 6173 6174 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6175 "stat_EtherStatsCollisions", 6176 CTLFLAG_RD, &sc->stat_EtherStatsCollisions, 6177 0, "Collisions"); 6178 6179 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6180 "stat_EtherStatsFragments", 6181 CTLFLAG_RD, &sc->stat_EtherStatsFragments, 6182 0, "Fragments"); 6183 6184 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6185 "stat_EtherStatsJabbers", 6186 CTLFLAG_RD, &sc->stat_EtherStatsJabbers, 6187 0, "Jabbers"); 6188 6189 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6190 "stat_EtherStatsUndersizePkts", 6191 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts, 6192 0, "Undersize packets"); 6193 6194 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6195 "stat_EtherStatsOverrsizePkts", 6196 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts, 6197 0, "stat_EtherStatsOverrsizePkts"); 6198 6199 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6200 "stat_EtherStatsPktsRx64Octets", 6201 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets, 6202 0, "Bytes received in 64 byte packets"); 6203 6204 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6205 "stat_EtherStatsPktsRx65Octetsto127Octets", 6206 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets, 6207 0, "Bytes received in 65 to 127 byte packets"); 6208 6209 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6210 "stat_EtherStatsPktsRx128Octetsto255Octets", 6211 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets, 6212 0, "Bytes received in 128 to 255 byte packets"); 6213 6214 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6215 "stat_EtherStatsPktsRx256Octetsto511Octets", 6216 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets, 6217 0, "Bytes received in 256 to 511 byte packets"); 6218 6219 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6220 "stat_EtherStatsPktsRx512Octetsto1023Octets", 6221 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets, 6222 0, "Bytes received in 512 to 1023 byte packets"); 6223 6224 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6225 "stat_EtherStatsPktsRx1024Octetsto1522Octets", 6226 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets, 6227 0, "Bytes received in 1024 t0 1522 byte packets"); 6228 6229 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6230 "stat_EtherStatsPktsRx1523Octetsto9022Octets", 6231 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets, 6232 0, "Bytes received in 1523 to 9022 byte packets"); 6233 6234 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6235 "stat_EtherStatsPktsTx64Octets", 6236 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets, 6237 0, "Bytes sent in 64 byte packets"); 6238 6239 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6240 "stat_EtherStatsPktsTx65Octetsto127Octets", 6241 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets, 6242 0, "Bytes sent in 65 to 127 byte packets"); 6243 6244 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6245 "stat_EtherStatsPktsTx128Octetsto255Octets", 6246 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets, 6247 0, "Bytes sent in 128 to 255 byte packets"); 6248 6249 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6250 "stat_EtherStatsPktsTx256Octetsto511Octets", 6251 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets, 6252 0, "Bytes sent in 256 to 511 byte packets"); 6253 6254 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6255 "stat_EtherStatsPktsTx512Octetsto1023Octets", 6256 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets, 6257 0, "Bytes sent in 512 to 1023 byte packets"); 6258 6259 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6260 "stat_EtherStatsPktsTx1024Octetsto1522Octets", 6261 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets, 6262 0, "Bytes sent in 1024 to 1522 byte packets"); 6263 6264 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6265 "stat_EtherStatsPktsTx1523Octetsto9022Octets", 6266 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets, 6267 0, "Bytes sent in 1523 to 9022 byte packets"); 6268 6269 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6270 "stat_XonPauseFramesReceived", 6271 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived, 6272 0, "XON pause frames receved"); 6273 6274 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6275 "stat_XoffPauseFramesReceived", 6276 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived, 6277 0, "XOFF pause frames received"); 6278 6279 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6280 "stat_OutXonSent", 6281 CTLFLAG_RD, &sc->stat_OutXonSent, 6282 0, "XON pause frames sent"); 6283 6284 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6285 "stat_OutXoffSent", 6286 CTLFLAG_RD, &sc->stat_OutXoffSent, 6287 0, "XOFF pause frames sent"); 6288 6289 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6290 "stat_FlowControlDone", 6291 CTLFLAG_RD, &sc->stat_FlowControlDone, 6292 0, "Flow control done"); 6293 6294 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6295 "stat_MacControlFramesReceived", 6296 CTLFLAG_RD, &sc->stat_MacControlFramesReceived, 6297 0, "MAC control frames received"); 6298 6299 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6300 "stat_XoffStateEntered", 6301 CTLFLAG_RD, &sc->stat_XoffStateEntered, 6302 0, "XOFF state entered"); 6303 6304 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6305 "stat_IfInFramesL2FilterDiscards", 6306 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards, 6307 0, "Received L2 packets discarded"); 6308 6309 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6310 "stat_IfInRuleCheckerDiscards", 6311 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards, 6312 0, "Received packets discarded by rule"); 6313 6314 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6315 "stat_IfInFTQDiscards", 6316 CTLFLAG_RD, &sc->stat_IfInFTQDiscards, 6317 0, "Received packet FTQ discards"); 6318 6319 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6320 "stat_IfInMBUFDiscards", 6321 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards, 6322 0, "Received packets discarded due to lack of controller buffer memory"); 6323 6324 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6325 "stat_IfInRuleCheckerP4Hit", 6326 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit, 6327 0, "Received packets rule checker hits"); 6328 6329 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6330 "stat_CatchupInRuleCheckerDiscards", 6331 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards, 6332 0, "Received packets discarded in Catchup path"); 6333 6334 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6335 "stat_CatchupInFTQDiscards", 6336 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards, 6337 0, "Received packets discarded in FTQ in Catchup path"); 6338 6339 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6340 "stat_CatchupInMBUFDiscards", 6341 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards, 6342 0, "Received packets discarded in controller buffer memory in Catchup path"); 6343 6344 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6345 "stat_CatchupInRuleCheckerP4Hit", 6346 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit, 6347 0, "Received packets rule checker hits in Catchup path"); 6348 6349 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, 6350 "com_no_buffers", 6351 CTLFLAG_RD, &sc->com_no_buffers, 6352 0, "Valid packets received but no RX buffers available"); 6353 6354 #ifdef BCE_DEBUG 6355 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6356 "driver_state", CTLTYPE_INT | CTLFLAG_RW, 6357 (void *)sc, 0, 6358 bce_sysctl_driver_state, "I", "Drive state information"); 6359 6360 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6361 "hw_state", CTLTYPE_INT | CTLFLAG_RW, 6362 (void *)sc, 0, 6363 bce_sysctl_hw_state, "I", "Hardware state information"); 6364 6365 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6366 "bc_state", CTLTYPE_INT | CTLFLAG_RW, 6367 (void *)sc, 0, 6368 bce_sysctl_bc_state, "I", "Bootcode state information"); 6369 6370 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6371 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW, 6372 (void *)sc, 0, 6373 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain"); 6374 6375 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6376 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW, 6377 (void *)sc, 0, 6378 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain"); 6379 6380 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6381 "breakpoint", CTLTYPE_INT | CTLFLAG_RW, 6382 (void *)sc, 0, 6383 bce_sysctl_breakpoint, "I", "Driver breakpoint"); 6384 6385 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6386 "reg_read", CTLTYPE_INT | CTLFLAG_RW, 6387 (void *)sc, 0, 6388 bce_sysctl_reg_read, "I", "Register read"); 6389 6390 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 6391 "phy_read", CTLTYPE_INT | CTLFLAG_RW, 6392 (void *)sc, 0, 6393 bce_sysctl_phy_read, "I", "PHY register read"); 6394 6395 #endif 6396 6397 } 6398 6399 6400 /****************************************************************************/ 6401 /* BCE Debug Routines */ 6402 /****************************************************************************/ 6403 #ifdef BCE_DEBUG 6404 6405 /****************************************************************************/ 6406 /* Freezes the controller to allow for a cohesive state dump. */ 6407 /* */ 6408 /* Returns: */ 6409 /* Nothing. */ 6410 /****************************************************************************/ 6411 static void 6412 bce_freeze_controller(struct bce_softc *sc) 6413 { 6414 u32 val; 6415 val = REG_RD(sc, BCE_MISC_COMMAND); 6416 val |= BCE_MISC_COMMAND_DISABLE_ALL; 6417 REG_WR(sc, BCE_MISC_COMMAND, val); 6418 6419 } 6420 6421 6422 /****************************************************************************/ 6423 /* Unfreezes the controller after a freeze operation. This may not always */ 6424 /* work and the controller will require a reset! */ 6425 /* */ 6426 /* Returns: */ 6427 /* Nothing. */ 6428 /****************************************************************************/ 6429 static void 6430 bce_unfreeze_controller(struct bce_softc *sc) 6431 { 6432 u32 val; 6433 val = REG_RD(sc, BCE_MISC_COMMAND); 6434 val |= BCE_MISC_COMMAND_ENABLE_ALL; 6435 REG_WR(sc, BCE_MISC_COMMAND, val); 6436 6437 } 6438 6439 /****************************************************************************/ 6440 /* Prints out information about an mbuf. */ 6441 /* */ 6442 /* Returns: */ 6443 /* Nothing. */ 6444 /****************************************************************************/ 6445 static void 6446 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m) 6447 { 6448 u32 val_hi, val_lo; 6449 struct mbuf *mp = m; 6450 6451 if (m == NULL) { 6452 BCE_PRINTF("mbuf: null pointer\n"); 6453 return; 6454 } 6455 6456 while (mp) { 6457 val_hi = BCE_ADDR_HI(mp); 6458 val_lo = BCE_ADDR_LO(mp); 6459 BCE_PRINTF("mbuf: vaddr = 0x%08X:%08X, m_len = %d, m_flags = ( ", 6460 val_hi, val_lo, mp->m_len); 6461 6462 if (mp->m_flags & M_EXT) 6463 printf("M_EXT "); 6464 if (mp->m_flags & M_PKTHDR) 6465 printf("M_PKTHDR "); 6466 if (mp->m_flags & M_EOR) 6467 printf("M_EOR "); 6468 if (mp->m_flags & M_RDONLY) 6469 printf("M_RDONLY "); 6470 6471 val_hi = BCE_ADDR_HI(mp->m_data); 6472 val_lo = BCE_ADDR_LO(mp->m_data); 6473 printf(") m_data = 0x%08X:%08X\n", 6474 val_hi, val_lo); 6475 6476 if (mp->m_flags & M_PKTHDR) { 6477 BCE_PRINTF("- m_pkthdr: flags = ( "); 6478 if (mp->m_flags & M_BCAST) 6479 printf("M_BCAST "); 6480 if (mp->m_flags & M_MCAST) 6481 printf("M_MCAST "); 6482 if (mp->m_flags & M_FRAG) 6483 printf("M_FRAG "); 6484 if (mp->m_flags & M_FIRSTFRAG) 6485 printf("M_FIRSTFRAG "); 6486 if (mp->m_flags & M_LASTFRAG) 6487 printf("M_LASTFRAG "); 6488 if (mp->m_flags & M_VLANTAG) 6489 printf("M_VLANTAG "); 6490 if (mp->m_flags & M_PROMISC) 6491 printf("M_PROMISC "); 6492 printf(") csum_flags = ( "); 6493 if (mp->m_pkthdr.csum_flags & CSUM_IP) 6494 printf("CSUM_IP "); 6495 if (mp->m_pkthdr.csum_flags & CSUM_TCP) 6496 printf("CSUM_TCP "); 6497 if (mp->m_pkthdr.csum_flags & CSUM_UDP) 6498 printf("CSUM_UDP "); 6499 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS) 6500 printf("CSUM_IP_FRAGS "); 6501 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT) 6502 printf("CSUM_FRAGMENT "); 6503 if (mp->m_pkthdr.csum_flags & CSUM_TSO) 6504 printf("CSUM_TSO "); 6505 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED) 6506 printf("CSUM_IP_CHECKED "); 6507 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID) 6508 printf("CSUM_IP_VALID "); 6509 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID) 6510 printf("CSUM_DATA_VALID "); 6511 printf(")\n"); 6512 } 6513 6514 if (mp->m_flags & M_EXT) { 6515 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf); 6516 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf); 6517 BCE_PRINTF("- m_ext: vaddr = 0x%08X:%08X, ext_size = %d, type = ", 6518 val_hi, val_lo, mp->m_ext.ext_size); 6519 switch (mp->m_ext.ext_type) { 6520 case EXT_CLUSTER: printf("EXT_CLUSTER\n"); break; 6521 case EXT_SFBUF: printf("EXT_SFBUF\n"); break; 6522 case EXT_JUMBO9: printf("EXT_JUMBO9\n"); break; 6523 case EXT_JUMBO16: printf("EXT_JUMBO16\n"); break; 6524 case EXT_PACKET: printf("EXT_PACKET\n"); break; 6525 case EXT_MBUF: printf("EXT_MBUF\n"); break; 6526 case EXT_NET_DRV: printf("EXT_NET_DRV\n"); break; 6527 case EXT_MOD_TYPE: printf("EXT_MDD_TYPE\n"); break; 6528 case EXT_DISPOSABLE: printf("EXT_DISPOSABLE\n"); break; 6529 case EXT_EXTREF: printf("EXT_EXTREF\n"); break; 6530 default: printf("UNKNOWN\n"); 6531 } 6532 } 6533 6534 mp = mp->m_next; 6535 } 6536 } 6537 6538 6539 /****************************************************************************/ 6540 /* Prints out the mbufs in the TX mbuf chain. */ 6541 /* */ 6542 /* Returns: */ 6543 /* Nothing. */ 6544 /****************************************************************************/ 6545 static void 6546 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6547 { 6548 struct mbuf *m; 6549 6550 BCE_PRINTF( 6551 "----------------------------" 6552 " tx mbuf data " 6553 "----------------------------\n"); 6554 6555 for (int i = 0; i < count; i++) { 6556 m = sc->tx_mbuf_ptr[chain_prod]; 6557 BCE_PRINTF("txmbuf[%d]\n", chain_prod); 6558 bce_dump_mbuf(sc, m); 6559 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod)); 6560 } 6561 6562 BCE_PRINTF( 6563 "----------------------------" 6564 "----------------" 6565 "----------------------------\n"); 6566 } 6567 6568 6569 /****************************************************************************/ 6570 /* Prints out the mbufs in the RX mbuf chain. */ 6571 /* */ 6572 /* Returns: */ 6573 /* Nothing. */ 6574 /****************************************************************************/ 6575 static void 6576 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count) 6577 { 6578 struct mbuf *m; 6579 6580 BCE_PRINTF( 6581 "----------------------------" 6582 " rx mbuf data " 6583 "----------------------------\n"); 6584 6585 for (int i = 0; i < count; i++) { 6586 m = sc->rx_mbuf_ptr[chain_prod]; 6587 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod); 6588 bce_dump_mbuf(sc, m); 6589 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod)); 6590 } 6591 6592 6593 BCE_PRINTF( 6594 "----------------------------" 6595 "----------------" 6596 "----------------------------\n"); 6597 } 6598 6599 6600 /****************************************************************************/ 6601 /* Prints out a tx_bd structure. */ 6602 /* */ 6603 /* Returns: */ 6604 /* Nothing. */ 6605 /****************************************************************************/ 6606 static void 6607 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd) 6608 { 6609 if (idx > MAX_TX_BD) 6610 /* Index out of range. */ 6611 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx); 6612 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) 6613 /* TX Chain page pointer. */ 6614 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6615 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo); 6616 else { 6617 /* Normal tx_bd entry. */ 6618 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6619 "vlan tag= 0x%04X, flags = 0x%04X (", idx, 6620 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, 6621 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, 6622 txbd->tx_bd_flags); 6623 6624 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) 6625 printf(" CONN_FAULT"); 6626 6627 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) 6628 printf(" TCP_UDP_CKSUM"); 6629 6630 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) 6631 printf(" IP_CKSUM"); 6632 6633 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) 6634 printf(" VLAN"); 6635 6636 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) 6637 printf(" COAL_NOW"); 6638 6639 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) 6640 printf(" DONT_GEN_CRC"); 6641 6642 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) 6643 printf(" START"); 6644 6645 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) 6646 printf(" END"); 6647 6648 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) 6649 printf(" LSO"); 6650 6651 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) 6652 printf(" OPTION_WORD"); 6653 6654 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) 6655 printf(" FLAGS"); 6656 6657 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) 6658 printf(" SNAP"); 6659 6660 printf(" )\n"); 6661 } 6662 6663 } 6664 6665 6666 /****************************************************************************/ 6667 /* Prints out a rx_bd structure. */ 6668 /* */ 6669 /* Returns: */ 6670 /* Nothing. */ 6671 /****************************************************************************/ 6672 static void 6673 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd) 6674 { 6675 if (idx > MAX_RX_BD) 6676 /* Index out of range. */ 6677 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx); 6678 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) 6679 /* TX Chain page pointer. */ 6680 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n", 6681 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo); 6682 else 6683 /* Normal tx_bd entry. */ 6684 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, " 6685 "flags = 0x%08X\n", idx, 6686 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, 6687 rxbd->rx_bd_len, rxbd->rx_bd_flags); 6688 } 6689 6690 6691 /****************************************************************************/ 6692 /* Prints out a l2_fhdr structure. */ 6693 /* */ 6694 /* Returns: */ 6695 /* Nothing. */ 6696 /****************************************************************************/ 6697 static void 6698 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr) 6699 { 6700 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%08X, " 6701 "pkt_len = 0x%04X, vlan = 0x%04x, ip_xsum = 0x%04X, " 6702 "tcp_udp_xsum = 0x%04X\n", idx, 6703 l2fhdr->l2_fhdr_status, l2fhdr->l2_fhdr_pkt_len, 6704 l2fhdr->l2_fhdr_vlan_tag, l2fhdr->l2_fhdr_ip_xsum, 6705 l2fhdr->l2_fhdr_tcp_udp_xsum); 6706 } 6707 6708 6709 /****************************************************************************/ 6710 /* Prints out the TX chain. */ 6711 /* */ 6712 /* Returns: */ 6713 /* Nothing. */ 6714 /****************************************************************************/ 6715 static void 6716 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count) 6717 { 6718 struct tx_bd *txbd; 6719 6720 /* First some info about the tx_bd chain structure. */ 6721 BCE_PRINTF( 6722 "----------------------------" 6723 " tx_bd chain " 6724 "----------------------------\n"); 6725 6726 BCE_PRINTF("page size = 0x%08X, tx chain pages = 0x%08X\n", 6727 (u32) BCM_PAGE_SIZE, (u32) TX_PAGES); 6728 6729 BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n", 6730 (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE); 6731 6732 BCE_PRINTF("total tx_bd = 0x%08X\n", (u32) TOTAL_TX_BD); 6733 6734 BCE_PRINTF( 6735 "----------------------------" 6736 " tx_bd data " 6737 "----------------------------\n"); 6738 6739 /* Now print out the tx_bd's themselves. */ 6740 for (int i = 0; i < count; i++) { 6741 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)]; 6742 bce_dump_txbd(sc, tx_prod, txbd); 6743 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod)); 6744 } 6745 6746 BCE_PRINTF( 6747 "----------------------------" 6748 "----------------" 6749 "----------------------------\n"); 6750 } 6751 6752 6753 /****************************************************************************/ 6754 /* Prints out the RX chain. */ 6755 /* */ 6756 /* Returns: */ 6757 /* Nothing. */ 6758 /****************************************************************************/ 6759 static void 6760 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count) 6761 { 6762 struct rx_bd *rxbd; 6763 6764 /* First some info about the tx_bd chain structure. */ 6765 BCE_PRINTF( 6766 "----------------------------" 6767 " rx_bd chain " 6768 "----------------------------\n"); 6769 6770 BCE_PRINTF("page size = 0x%08X, rx chain pages = 0x%08X\n", 6771 (u32) BCM_PAGE_SIZE, (u32) RX_PAGES); 6772 6773 BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n", 6774 (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE); 6775 6776 BCE_PRINTF("total rx_bd = 0x%08X\n", (u32) TOTAL_RX_BD); 6777 6778 BCE_PRINTF( 6779 "----------------------------" 6780 " rx_bd data " 6781 "----------------------------\n"); 6782 6783 /* Now print out the rx_bd's themselves. */ 6784 for (int i = 0; i < count; i++) { 6785 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)]; 6786 bce_dump_rxbd(sc, rx_prod, rxbd); 6787 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod)); 6788 } 6789 6790 BCE_PRINTF( 6791 "----------------------------" 6792 "----------------" 6793 "----------------------------\n"); 6794 } 6795 6796 6797 /****************************************************************************/ 6798 /* Prints out the status block from host memory. */ 6799 /* */ 6800 /* Returns: */ 6801 /* Nothing. */ 6802 /****************************************************************************/ 6803 static void 6804 bce_dump_status_block(struct bce_softc *sc) 6805 { 6806 struct status_block *sblk; 6807 6808 sblk = sc->status_block; 6809 6810 BCE_PRINTF( 6811 "----------------------------" 6812 " Status Block " 6813 "----------------------------\n"); 6814 6815 BCE_PRINTF(" 0x%08X - attn_bits\n", 6816 sblk->status_attn_bits); 6817 6818 BCE_PRINTF(" 0x%08X - attn_bits_ack\n", 6819 sblk->status_attn_bits_ack); 6820 6821 BCE_PRINTF("0x%04X(0x%04X) - rx_cons0\n", 6822 sblk->status_rx_quick_consumer_index0, 6823 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0)); 6824 6825 BCE_PRINTF("0x%04X(0x%04X) - tx_cons0\n", 6826 sblk->status_tx_quick_consumer_index0, 6827 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0)); 6828 6829 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx); 6830 6831 /* Theses indices are not used for normal L2 drivers. */ 6832 if (sblk->status_rx_quick_consumer_index1) 6833 BCE_PRINTF("0x%04X(0x%04X) - rx_cons1\n", 6834 sblk->status_rx_quick_consumer_index1, 6835 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1)); 6836 6837 if (sblk->status_tx_quick_consumer_index1) 6838 BCE_PRINTF("0x%04X(0x%04X) - tx_cons1\n", 6839 sblk->status_tx_quick_consumer_index1, 6840 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1)); 6841 6842 if (sblk->status_rx_quick_consumer_index2) 6843 BCE_PRINTF("0x%04X(0x%04X)- rx_cons2\n", 6844 sblk->status_rx_quick_consumer_index2, 6845 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2)); 6846 6847 if (sblk->status_tx_quick_consumer_index2) 6848 BCE_PRINTF("0x%04X(0x%04X) - tx_cons2\n", 6849 sblk->status_tx_quick_consumer_index2, 6850 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2)); 6851 6852 if (sblk->status_rx_quick_consumer_index3) 6853 BCE_PRINTF("0x%04X(0x%04X) - rx_cons3\n", 6854 sblk->status_rx_quick_consumer_index3, 6855 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3)); 6856 6857 if (sblk->status_tx_quick_consumer_index3) 6858 BCE_PRINTF("0x%04X(0x%04X) - tx_cons3\n", 6859 sblk->status_tx_quick_consumer_index3, 6860 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3)); 6861 6862 if (sblk->status_rx_quick_consumer_index4 || 6863 sblk->status_rx_quick_consumer_index5) 6864 BCE_PRINTF("rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", 6865 sblk->status_rx_quick_consumer_index4, 6866 sblk->status_rx_quick_consumer_index5); 6867 6868 if (sblk->status_rx_quick_consumer_index6 || 6869 sblk->status_rx_quick_consumer_index7) 6870 BCE_PRINTF("rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", 6871 sblk->status_rx_quick_consumer_index6, 6872 sblk->status_rx_quick_consumer_index7); 6873 6874 if (sblk->status_rx_quick_consumer_index8 || 6875 sblk->status_rx_quick_consumer_index9) 6876 BCE_PRINTF("rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", 6877 sblk->status_rx_quick_consumer_index8, 6878 sblk->status_rx_quick_consumer_index9); 6879 6880 if (sblk->status_rx_quick_consumer_index10 || 6881 sblk->status_rx_quick_consumer_index11) 6882 BCE_PRINTF("rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", 6883 sblk->status_rx_quick_consumer_index10, 6884 sblk->status_rx_quick_consumer_index11); 6885 6886 if (sblk->status_rx_quick_consumer_index12 || 6887 sblk->status_rx_quick_consumer_index13) 6888 BCE_PRINTF("rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", 6889 sblk->status_rx_quick_consumer_index12, 6890 sblk->status_rx_quick_consumer_index13); 6891 6892 if (sblk->status_rx_quick_consumer_index14 || 6893 sblk->status_rx_quick_consumer_index15) 6894 BCE_PRINTF("rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", 6895 sblk->status_rx_quick_consumer_index14, 6896 sblk->status_rx_quick_consumer_index15); 6897 6898 if (sblk->status_completion_producer_index || 6899 sblk->status_cmd_consumer_index) 6900 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n", 6901 sblk->status_completion_producer_index, 6902 sblk->status_cmd_consumer_index); 6903 6904 BCE_PRINTF( 6905 "----------------------------" 6906 "----------------" 6907 "----------------------------\n"); 6908 } 6909 6910 6911 /****************************************************************************/ 6912 /* Prints out the statistics block from host memory. */ 6913 /* */ 6914 /* Returns: */ 6915 /* Nothing. */ 6916 /****************************************************************************/ 6917 static void 6918 bce_dump_stats_block(struct bce_softc *sc) 6919 { 6920 struct statistics_block *sblk; 6921 6922 sblk = sc->stats_block; 6923 6924 BCE_PRINTF( 6925 "---------------" 6926 " Stats Block (All Stats Not Shown Are 0) " 6927 "---------------\n"); 6928 6929 if (sblk->stat_IfHCInOctets_hi 6930 || sblk->stat_IfHCInOctets_lo) 6931 BCE_PRINTF("0x%08X:%08X : " 6932 "IfHcInOctets\n", 6933 sblk->stat_IfHCInOctets_hi, 6934 sblk->stat_IfHCInOctets_lo); 6935 6936 if (sblk->stat_IfHCInBadOctets_hi 6937 || sblk->stat_IfHCInBadOctets_lo) 6938 BCE_PRINTF("0x%08X:%08X : " 6939 "IfHcInBadOctets\n", 6940 sblk->stat_IfHCInBadOctets_hi, 6941 sblk->stat_IfHCInBadOctets_lo); 6942 6943 if (sblk->stat_IfHCOutOctets_hi 6944 || sblk->stat_IfHCOutOctets_lo) 6945 BCE_PRINTF("0x%08X:%08X : " 6946 "IfHcOutOctets\n", 6947 sblk->stat_IfHCOutOctets_hi, 6948 sblk->stat_IfHCOutOctets_lo); 6949 6950 if (sblk->stat_IfHCOutBadOctets_hi 6951 || sblk->stat_IfHCOutBadOctets_lo) 6952 BCE_PRINTF("0x%08X:%08X : " 6953 "IfHcOutBadOctets\n", 6954 sblk->stat_IfHCOutBadOctets_hi, 6955 sblk->stat_IfHCOutBadOctets_lo); 6956 6957 if (sblk->stat_IfHCInUcastPkts_hi 6958 || sblk->stat_IfHCInUcastPkts_lo) 6959 BCE_PRINTF("0x%08X:%08X : " 6960 "IfHcInUcastPkts\n", 6961 sblk->stat_IfHCInUcastPkts_hi, 6962 sblk->stat_IfHCInUcastPkts_lo); 6963 6964 if (sblk->stat_IfHCInBroadcastPkts_hi 6965 || sblk->stat_IfHCInBroadcastPkts_lo) 6966 BCE_PRINTF("0x%08X:%08X : " 6967 "IfHcInBroadcastPkts\n", 6968 sblk->stat_IfHCInBroadcastPkts_hi, 6969 sblk->stat_IfHCInBroadcastPkts_lo); 6970 6971 if (sblk->stat_IfHCInMulticastPkts_hi 6972 || sblk->stat_IfHCInMulticastPkts_lo) 6973 BCE_PRINTF("0x%08X:%08X : " 6974 "IfHcInMulticastPkts\n", 6975 sblk->stat_IfHCInMulticastPkts_hi, 6976 sblk->stat_IfHCInMulticastPkts_lo); 6977 6978 if (sblk->stat_IfHCOutUcastPkts_hi 6979 || sblk->stat_IfHCOutUcastPkts_lo) 6980 BCE_PRINTF("0x%08X:%08X : " 6981 "IfHcOutUcastPkts\n", 6982 sblk->stat_IfHCOutUcastPkts_hi, 6983 sblk->stat_IfHCOutUcastPkts_lo); 6984 6985 if (sblk->stat_IfHCOutBroadcastPkts_hi 6986 || sblk->stat_IfHCOutBroadcastPkts_lo) 6987 BCE_PRINTF("0x%08X:%08X : " 6988 "IfHcOutBroadcastPkts\n", 6989 sblk->stat_IfHCOutBroadcastPkts_hi, 6990 sblk->stat_IfHCOutBroadcastPkts_lo); 6991 6992 if (sblk->stat_IfHCOutMulticastPkts_hi 6993 || sblk->stat_IfHCOutMulticastPkts_lo) 6994 BCE_PRINTF("0x%08X:%08X : " 6995 "IfHcOutMulticastPkts\n", 6996 sblk->stat_IfHCOutMulticastPkts_hi, 6997 sblk->stat_IfHCOutMulticastPkts_lo); 6998 6999 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) 7000 BCE_PRINTF(" 0x%08X : " 7001 "emac_tx_stat_dot3statsinternalmactransmiterrors\n", 7002 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); 7003 7004 if (sblk->stat_Dot3StatsCarrierSenseErrors) 7005 BCE_PRINTF(" 0x%08X : Dot3StatsCarrierSenseErrors\n", 7006 sblk->stat_Dot3StatsCarrierSenseErrors); 7007 7008 if (sblk->stat_Dot3StatsFCSErrors) 7009 BCE_PRINTF(" 0x%08X : Dot3StatsFCSErrors\n", 7010 sblk->stat_Dot3StatsFCSErrors); 7011 7012 if (sblk->stat_Dot3StatsAlignmentErrors) 7013 BCE_PRINTF(" 0x%08X : Dot3StatsAlignmentErrors\n", 7014 sblk->stat_Dot3StatsAlignmentErrors); 7015 7016 if (sblk->stat_Dot3StatsSingleCollisionFrames) 7017 BCE_PRINTF(" 0x%08X : Dot3StatsSingleCollisionFrames\n", 7018 sblk->stat_Dot3StatsSingleCollisionFrames); 7019 7020 if (sblk->stat_Dot3StatsMultipleCollisionFrames) 7021 BCE_PRINTF(" 0x%08X : Dot3StatsMultipleCollisionFrames\n", 7022 sblk->stat_Dot3StatsMultipleCollisionFrames); 7023 7024 if (sblk->stat_Dot3StatsDeferredTransmissions) 7025 BCE_PRINTF(" 0x%08X : Dot3StatsDeferredTransmissions\n", 7026 sblk->stat_Dot3StatsDeferredTransmissions); 7027 7028 if (sblk->stat_Dot3StatsExcessiveCollisions) 7029 BCE_PRINTF(" 0x%08X : Dot3StatsExcessiveCollisions\n", 7030 sblk->stat_Dot3StatsExcessiveCollisions); 7031 7032 if (sblk->stat_Dot3StatsLateCollisions) 7033 BCE_PRINTF(" 0x%08X : Dot3StatsLateCollisions\n", 7034 sblk->stat_Dot3StatsLateCollisions); 7035 7036 if (sblk->stat_EtherStatsCollisions) 7037 BCE_PRINTF(" 0x%08X : EtherStatsCollisions\n", 7038 sblk->stat_EtherStatsCollisions); 7039 7040 if (sblk->stat_EtherStatsFragments) 7041 BCE_PRINTF(" 0x%08X : EtherStatsFragments\n", 7042 sblk->stat_EtherStatsFragments); 7043 7044 if (sblk->stat_EtherStatsJabbers) 7045 BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n", 7046 sblk->stat_EtherStatsJabbers); 7047 7048 if (sblk->stat_EtherStatsUndersizePkts) 7049 BCE_PRINTF(" 0x%08X : EtherStatsUndersizePkts\n", 7050 sblk->stat_EtherStatsUndersizePkts); 7051 7052 if (sblk->stat_EtherStatsOverrsizePkts) 7053 BCE_PRINTF(" 0x%08X : EtherStatsOverrsizePkts\n", 7054 sblk->stat_EtherStatsOverrsizePkts); 7055 7056 if (sblk->stat_EtherStatsPktsRx64Octets) 7057 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx64Octets\n", 7058 sblk->stat_EtherStatsPktsRx64Octets); 7059 7060 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) 7061 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx65Octetsto127Octets\n", 7062 sblk->stat_EtherStatsPktsRx65Octetsto127Octets); 7063 7064 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) 7065 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx128Octetsto255Octets\n", 7066 sblk->stat_EtherStatsPktsRx128Octetsto255Octets); 7067 7068 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) 7069 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx256Octetsto511Octets\n", 7070 sblk->stat_EtherStatsPktsRx256Octetsto511Octets); 7071 7072 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) 7073 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx512Octetsto1023Octets\n", 7074 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets); 7075 7076 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) 7077 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1024Octetsto1522Octets\n", 7078 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets); 7079 7080 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) 7081 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx1523Octetsto9022Octets\n", 7082 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets); 7083 7084 if (sblk->stat_EtherStatsPktsTx64Octets) 7085 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx64Octets\n", 7086 sblk->stat_EtherStatsPktsTx64Octets); 7087 7088 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) 7089 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx65Octetsto127Octets\n", 7090 sblk->stat_EtherStatsPktsTx65Octetsto127Octets); 7091 7092 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) 7093 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx128Octetsto255Octets\n", 7094 sblk->stat_EtherStatsPktsTx128Octetsto255Octets); 7095 7096 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) 7097 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx256Octetsto511Octets\n", 7098 sblk->stat_EtherStatsPktsTx256Octetsto511Octets); 7099 7100 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) 7101 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx512Octetsto1023Octets\n", 7102 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets); 7103 7104 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) 7105 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1024Octetsto1522Octets\n", 7106 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets); 7107 7108 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) 7109 BCE_PRINTF(" 0x%08X : EtherStatsPktsTx1523Octetsto9022Octets\n", 7110 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets); 7111 7112 if (sblk->stat_XonPauseFramesReceived) 7113 BCE_PRINTF(" 0x%08X : XonPauseFramesReceived\n", 7114 sblk->stat_XonPauseFramesReceived); 7115 7116 if (sblk->stat_XoffPauseFramesReceived) 7117 BCE_PRINTF(" 0x%08X : XoffPauseFramesReceived\n", 7118 sblk->stat_XoffPauseFramesReceived); 7119 7120 if (sblk->stat_OutXonSent) 7121 BCE_PRINTF(" 0x%08X : OutXonSent\n", 7122 sblk->stat_OutXonSent); 7123 7124 if (sblk->stat_OutXoffSent) 7125 BCE_PRINTF(" 0x%08X : OutXoffSent\n", 7126 sblk->stat_OutXoffSent); 7127 7128 if (sblk->stat_FlowControlDone) 7129 BCE_PRINTF(" 0x%08X : FlowControlDone\n", 7130 sblk->stat_FlowControlDone); 7131 7132 if (sblk->stat_MacControlFramesReceived) 7133 BCE_PRINTF(" 0x%08X : MacControlFramesReceived\n", 7134 sblk->stat_MacControlFramesReceived); 7135 7136 if (sblk->stat_XoffStateEntered) 7137 BCE_PRINTF(" 0x%08X : XoffStateEntered\n", 7138 sblk->stat_XoffStateEntered); 7139 7140 if (sblk->stat_IfInFramesL2FilterDiscards) 7141 BCE_PRINTF(" 0x%08X : IfInFramesL2FilterDiscards\n", 7142 sblk->stat_IfInFramesL2FilterDiscards); 7143 7144 if (sblk->stat_IfInRuleCheckerDiscards) 7145 BCE_PRINTF(" 0x%08X : IfInRuleCheckerDiscards\n", 7146 sblk->stat_IfInRuleCheckerDiscards); 7147 7148 if (sblk->stat_IfInFTQDiscards) 7149 BCE_PRINTF(" 0x%08X : IfInFTQDiscards\n", 7150 sblk->stat_IfInFTQDiscards); 7151 7152 if (sblk->stat_IfInMBUFDiscards) 7153 BCE_PRINTF(" 0x%08X : IfInMBUFDiscards\n", 7154 sblk->stat_IfInMBUFDiscards); 7155 7156 if (sblk->stat_IfInRuleCheckerP4Hit) 7157 BCE_PRINTF(" 0x%08X : IfInRuleCheckerP4Hit\n", 7158 sblk->stat_IfInRuleCheckerP4Hit); 7159 7160 if (sblk->stat_CatchupInRuleCheckerDiscards) 7161 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerDiscards\n", 7162 sblk->stat_CatchupInRuleCheckerDiscards); 7163 7164 if (sblk->stat_CatchupInFTQDiscards) 7165 BCE_PRINTF(" 0x%08X : CatchupInFTQDiscards\n", 7166 sblk->stat_CatchupInFTQDiscards); 7167 7168 if (sblk->stat_CatchupInMBUFDiscards) 7169 BCE_PRINTF(" 0x%08X : CatchupInMBUFDiscards\n", 7170 sblk->stat_CatchupInMBUFDiscards); 7171 7172 if (sblk->stat_CatchupInRuleCheckerP4Hit) 7173 BCE_PRINTF(" 0x%08X : CatchupInRuleCheckerP4Hit\n", 7174 sblk->stat_CatchupInRuleCheckerP4Hit); 7175 7176 BCE_PRINTF( 7177 "----------------------------" 7178 "----------------" 7179 "----------------------------\n"); 7180 } 7181 7182 7183 /****************************************************************************/ 7184 /* Prints out a summary of the driver state. */ 7185 /* */ 7186 /* Returns: */ 7187 /* Nothing. */ 7188 /****************************************************************************/ 7189 static void 7190 bce_dump_driver_state(struct bce_softc *sc) 7191 { 7192 u32 val_hi, val_lo; 7193 7194 BCE_PRINTF( 7195 "-----------------------------" 7196 " Driver State " 7197 "-----------------------------\n"); 7198 7199 val_hi = BCE_ADDR_HI(sc); 7200 val_lo = BCE_ADDR_LO(sc); 7201 BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual address\n", 7202 val_hi, val_lo); 7203 7204 val_hi = BCE_ADDR_HI(sc->bce_vhandle); 7205 val_lo = BCE_ADDR_LO(sc->bce_vhandle); 7206 BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual address\n", 7207 val_hi, val_lo); 7208 7209 val_hi = BCE_ADDR_HI(sc->status_block); 7210 val_lo = BCE_ADDR_LO(sc->status_block); 7211 BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block virtual address\n", 7212 val_hi, val_lo); 7213 7214 val_hi = BCE_ADDR_HI(sc->stats_block); 7215 val_lo = BCE_ADDR_LO(sc->stats_block); 7216 BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block virtual address\n", 7217 val_hi, val_lo); 7218 7219 val_hi = BCE_ADDR_HI(sc->tx_bd_chain); 7220 val_lo = BCE_ADDR_LO(sc->tx_bd_chain); 7221 BCE_PRINTF( 7222 "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain virtual adddress\n", 7223 val_hi, val_lo); 7224 7225 val_hi = BCE_ADDR_HI(sc->rx_bd_chain); 7226 val_lo = BCE_ADDR_LO(sc->rx_bd_chain); 7227 BCE_PRINTF( 7228 "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain virtual address\n", 7229 val_hi, val_lo); 7230 7231 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr); 7232 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr); 7233 BCE_PRINTF( 7234 "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n", 7235 val_hi, val_lo); 7236 7237 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr); 7238 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr); 7239 BCE_PRINTF( 7240 "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n", 7241 val_hi, val_lo); 7242 7243 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) h/w intrs\n", 7244 sc->interrupts_generated); 7245 7246 BCE_PRINTF(" 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", 7247 sc->rx_interrupts); 7248 7249 BCE_PRINTF(" 0x%08X - (sc->tx_interrupts) tx interrupts handled\n", 7250 sc->tx_interrupts); 7251 7252 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) status block index\n", 7253 sc->last_status_idx); 7254 7255 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_prod) tx producer index\n", 7256 sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod)); 7257 7258 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->tx_cons) tx consumer index\n", 7259 sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons)); 7260 7261 BCE_PRINTF(" 0x%08X - (sc->tx_prod_bseq) tx producer bseq index\n", 7262 sc->tx_prod_bseq); 7263 7264 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_prod) rx producer index\n", 7265 sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod)); 7266 7267 BCE_PRINTF(" 0x%04X(0x%04X) - (sc->rx_cons) rx consumer index\n", 7268 sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons)); 7269 7270 BCE_PRINTF(" 0x%08X - (sc->rx_prod_bseq) rx producer bseq index\n", 7271 sc->rx_prod_bseq); 7272 7273 BCE_PRINTF(" 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 7274 sc->rx_mbuf_alloc); 7275 7276 BCE_PRINTF(" 0x%08X - (sc->free_rx_bd) free rx_bd's\n", 7277 sc->free_rx_bd); 7278 7279 BCE_PRINTF("0x%08X/%08X - (sc->rx_low_watermark) rx low watermark\n", 7280 sc->rx_low_watermark, sc->max_rx_bd); 7281 7282 BCE_PRINTF(" 0x%08X - (sc->txmbuf_alloc) tx mbufs allocated\n", 7283 sc->tx_mbuf_alloc); 7284 7285 BCE_PRINTF(" 0x%08X - (sc->rx_mbuf_alloc) rx mbufs allocated\n", 7286 sc->rx_mbuf_alloc); 7287 7288 BCE_PRINTF(" 0x%08X - (sc->used_tx_bd) used tx_bd's\n", 7289 sc->used_tx_bd); 7290 7291 BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n", 7292 sc->tx_hi_watermark, sc->max_tx_bd); 7293 7294 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed) failed mbuf alloc\n", 7295 sc->mbuf_alloc_failed); 7296 7297 BCE_PRINTF( 7298 "----------------------------" 7299 "----------------" 7300 "----------------------------\n"); 7301 } 7302 7303 7304 /****************************************************************************/ 7305 /* Prints out the hardware state through a summary of important register, */ 7306 /* followed by a complete register dump. */ 7307 /* */ 7308 /* Returns: */ 7309 /* Nothing. */ 7310 /****************************************************************************/ 7311 static void 7312 bce_dump_hw_state(struct bce_softc *sc) 7313 { 7314 u32 val1; 7315 7316 BCE_PRINTF( 7317 "----------------------------" 7318 " Hardware State " 7319 "----------------------------\n"); 7320 7321 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver); 7322 7323 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS); 7324 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n", 7325 val1, BCE_MISC_ENABLE_STATUS_BITS); 7326 7327 val1 = REG_RD(sc, BCE_DMA_STATUS); 7328 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", val1, BCE_DMA_STATUS); 7329 7330 val1 = REG_RD(sc, BCE_CTX_STATUS); 7331 BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n", val1, BCE_CTX_STATUS); 7332 7333 val1 = REG_RD(sc, BCE_EMAC_STATUS); 7334 BCE_PRINTF("0x%08X - (0x%06X) emac_status\n", val1, BCE_EMAC_STATUS); 7335 7336 val1 = REG_RD(sc, BCE_RPM_STATUS); 7337 BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n", val1, BCE_RPM_STATUS); 7338 7339 val1 = REG_RD(sc, BCE_TBDR_STATUS); 7340 BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n", val1, BCE_TBDR_STATUS); 7341 7342 val1 = REG_RD(sc, BCE_TDMA_STATUS); 7343 BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n", val1, BCE_TDMA_STATUS); 7344 7345 val1 = REG_RD(sc, BCE_HC_STATUS); 7346 BCE_PRINTF("0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS); 7347 7348 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 7349 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val1, BCE_TXP_CPU_STATE); 7350 7351 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 7352 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val1, BCE_TPAT_CPU_STATE); 7353 7354 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 7355 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val1, BCE_RXP_CPU_STATE); 7356 7357 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE); 7358 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val1, BCE_COM_CPU_STATE); 7359 7360 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE); 7361 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", val1, BCE_MCP_CPU_STATE); 7362 7363 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE); 7364 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val1, BCE_CP_CPU_STATE); 7365 7366 BCE_PRINTF( 7367 "----------------------------" 7368 "----------------" 7369 "----------------------------\n"); 7370 7371 BCE_PRINTF( 7372 "----------------------------" 7373 " Register Dump " 7374 "----------------------------\n"); 7375 7376 for (int i = 0x400; i < 0x8000; i += 0x10) 7377 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7378 i, REG_RD(sc, i), REG_RD(sc, i + 0x4), 7379 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); 7380 7381 BCE_PRINTF( 7382 "----------------------------" 7383 "----------------" 7384 "----------------------------\n"); 7385 } 7386 7387 7388 /****************************************************************************/ 7389 /* Prints out the bootcode state. */ 7390 /* */ 7391 /* Returns: */ 7392 /* Nothing. */ 7393 /****************************************************************************/ 7394 static void 7395 bce_dump_bc_state(struct bce_softc *sc) 7396 { 7397 u32 val; 7398 7399 BCE_PRINTF( 7400 "----------------------------" 7401 " Bootcode State " 7402 "----------------------------\n"); 7403 7404 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver); 7405 7406 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_RESET_TYPE); 7407 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n", 7408 val, BCE_BC_RESET_TYPE); 7409 7410 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE); 7411 BCE_PRINTF("0x%08X - (0x%06X) state\n", 7412 val, BCE_BC_STATE); 7413 7414 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_CONDITION); 7415 BCE_PRINTF("0x%08X - (0x%06X) condition\n", 7416 val, BCE_BC_CONDITION); 7417 7418 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE_DEBUG_CMD); 7419 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n", 7420 val, BCE_BC_STATE_DEBUG_CMD); 7421 7422 BCE_PRINTF( 7423 "----------------------------" 7424 "----------------" 7425 "----------------------------\n"); 7426 } 7427 7428 7429 /****************************************************************************/ 7430 /* Prints out the TXP state. */ 7431 /* */ 7432 /* Returns: */ 7433 /* Nothing. */ 7434 /****************************************************************************/ 7435 static void 7436 bce_dump_txp_state(struct bce_softc *sc) 7437 { 7438 u32 val1; 7439 7440 BCE_PRINTF( 7441 "----------------------------" 7442 " TXP State " 7443 "----------------------------\n"); 7444 7445 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE); 7446 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", val1, BCE_TXP_CPU_MODE); 7447 7448 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE); 7449 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val1, BCE_TXP_CPU_STATE); 7450 7451 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK); 7452 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", val1, BCE_TXP_CPU_EVENT_MASK); 7453 7454 BCE_PRINTF( 7455 "----------------------------" 7456 " Register Dump " 7457 "----------------------------\n"); 7458 7459 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) { 7460 /* Skip the big blank spaces */ 7461 if (i < 0x454000 && i > 0x5ffff) 7462 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7463 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 7464 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 7465 } 7466 7467 BCE_PRINTF( 7468 "----------------------------" 7469 "----------------" 7470 "----------------------------\n"); 7471 } 7472 7473 7474 /****************************************************************************/ 7475 /* Prints out the RXP state. */ 7476 /* */ 7477 /* Returns: */ 7478 /* Nothing. */ 7479 /****************************************************************************/ 7480 static void 7481 bce_dump_rxp_state(struct bce_softc *sc) 7482 { 7483 u32 val1; 7484 7485 BCE_PRINTF( 7486 "----------------------------" 7487 " RXP State " 7488 "----------------------------\n"); 7489 7490 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE); 7491 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", val1, BCE_RXP_CPU_MODE); 7492 7493 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE); 7494 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val1, BCE_RXP_CPU_STATE); 7495 7496 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK); 7497 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", val1, BCE_RXP_CPU_EVENT_MASK); 7498 7499 BCE_PRINTF( 7500 "----------------------------" 7501 " Register Dump " 7502 "----------------------------\n"); 7503 7504 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) { 7505 /* Skip the big blank sapces */ 7506 if (i < 0xc5400 && i > 0xdffff) 7507 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7508 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 7509 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 7510 } 7511 7512 BCE_PRINTF( 7513 "----------------------------" 7514 "----------------" 7515 "----------------------------\n"); 7516 } 7517 7518 7519 /****************************************************************************/ 7520 /* Prints out the TPAT state. */ 7521 /* */ 7522 /* Returns: */ 7523 /* Nothing. */ 7524 /****************************************************************************/ 7525 static void 7526 bce_dump_tpat_state(struct bce_softc *sc) 7527 { 7528 u32 val1; 7529 7530 BCE_PRINTF( 7531 "----------------------------" 7532 " TPAT State " 7533 "----------------------------\n"); 7534 7535 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE); 7536 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", val1, BCE_TPAT_CPU_MODE); 7537 7538 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE); 7539 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val1, BCE_TPAT_CPU_STATE); 7540 7541 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK); 7542 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", val1, BCE_TPAT_CPU_EVENT_MASK); 7543 7544 BCE_PRINTF( 7545 "----------------------------" 7546 " Register Dump " 7547 "----------------------------\n"); 7548 7549 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) { 7550 /* Skip the big blank spaces */ 7551 if (i < 0x854000 && i > 0x9ffff) 7552 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", 7553 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4), 7554 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC)); 7555 } 7556 7557 BCE_PRINTF( 7558 "----------------------------" 7559 "----------------" 7560 "----------------------------\n"); 7561 } 7562 7563 7564 /****************************************************************************/ 7565 /* Prints out the driver state and then enters the debugger. */ 7566 /* */ 7567 /* Returns: */ 7568 /* Nothing. */ 7569 /****************************************************************************/ 7570 static void 7571 bce_breakpoint(struct bce_softc *sc) 7572 { 7573 7574 /* Unreachable code to shut the compiler up about unused functions. */ 7575 if (0) { 7576 bce_freeze_controller(sc); 7577 bce_unfreeze_controller(sc); 7578 bce_dump_txbd(sc, 0, NULL); 7579 bce_dump_rxbd(sc, 0, NULL); 7580 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD); 7581 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD); 7582 bce_dump_l2fhdr(sc, 0, NULL); 7583 bce_dump_tx_chain(sc, 0, USABLE_TX_BD); 7584 bce_dump_rx_chain(sc, 0, USABLE_RX_BD); 7585 bce_dump_status_block(sc); 7586 bce_dump_stats_block(sc); 7587 bce_dump_driver_state(sc); 7588 bce_dump_hw_state(sc); 7589 bce_dump_bc_state(sc); 7590 bce_dump_txp_state(sc); 7591 bce_dump_rxp_state(sc); 7592 bce_dump_tpat_state(sc); 7593 } 7594 7595 /* bce_freeze_controller(sc); */ 7596 bce_dump_driver_state(sc); 7597 bce_dump_status_block(sc); 7598 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD); 7599 bce_dump_hw_state(sc); 7600 bce_dump_txp_state(sc); 7601 /* bce_unfreeze_controller(sc); */ 7602 7603 /* Call the debugger. */ 7604 breakpoint(); 7605 7606 return; 7607 } 7608 #endif 7609 7610