1 /*- 2 * Copyright (c) 2016,2017 SoftIron Inc. 3 * All rights reserved. 4 * 5 * This software was developed by Andrew Turner under 6 * the sponsorship of SoftIron Inc. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _XGBE_OSDEP_H_ 33 #define _XGBE_OSDEP_H_ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/endian.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mbuf.h> 41 #include <sys/mutex.h> 42 #include <sys/socket.h> 43 #include <sys/sx.h> 44 #include <sys/taskqueue.h> 45 46 #include <machine/bus.h> 47 48 #include <net/ethernet.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 52 typedef uint8_t u8; 53 typedef uint16_t u16; 54 typedef uint32_t __le32; 55 typedef uint32_t u32; 56 typedef uint64_t u64; 57 58 typedef struct { 59 struct mtx lock; 60 } spinlock_t; 61 62 static inline void 63 spin_lock_init(spinlock_t *spinlock) 64 { 65 66 mtx_init(&spinlock->lock, "axgbe_spin", NULL, MTX_DEF); 67 } 68 69 #define spin_lock_irqsave(spinlock, flags) \ 70 do { \ 71 (flags) = intr_disable(); \ 72 mtx_lock(&(spinlock)->lock); \ 73 } while (0) 74 75 #define spin_unlock_irqrestore(spinlock, flags) \ 76 do { \ 77 mtx_unlock(&(spinlock)->lock); \ 78 intr_restore(flags); \ 79 } while (0) 80 81 #define BIT(pos) (1ul << pos) 82 83 static inline void 84 clear_bit(int pos, unsigned long *p) 85 { 86 87 atomic_clear_long(p, 1ul << pos); 88 } 89 90 static inline int 91 test_bit(int pos, unsigned long *p) 92 { 93 unsigned long val; 94 95 val = *p; 96 return ((val & 1ul << pos) != 0); 97 } 98 99 static inline void 100 set_bit(int pos, unsigned long *p) 101 { 102 103 atomic_set_long(p, 1ul << pos); 104 } 105 106 #define lower_32_bits(x) ((x) & 0xffffffffu) 107 #define upper_32_bits(x) (((x) >> 32) & 0xffffffffu) 108 #define cpu_to_le32(x) le32toh(x) 109 #define le32_to_cpu(x) htole32(x) 110 111 MALLOC_DECLARE(M_AXGBE); 112 113 #define ADVERTISED_Pause 0x01 114 #define ADVERTISED_Asym_Pause 0x02 115 #define ADVERTISED_Autoneg 0x04 116 #define ADVERTISED_Backplane 0x08 117 #define ADVERTISED_10000baseKR_Full 0x10 118 #define ADVERTISED_2500baseX_Full 0x20 119 #define ADVERTISED_1000baseKX_Full 0x40 120 121 #define AUTONEG_DISABLE 0 122 #define AUTONEG_ENABLE 1 123 124 #define DUPLEX_UNKNOWN 1 125 #define DUPLEX_FULL 2 126 127 #define SPEED_UNKNOWN 1 128 #define SPEED_10000 2 129 #define SPEED_2500 3 130 #define SPEED_1000 4 131 132 #define SUPPORTED_Autoneg 0x01 133 #define SUPPORTED_Pause 0x02 134 #define SUPPORTED_Asym_Pause 0x04 135 #define SUPPORTED_Backplane 0x08 136 #define SUPPORTED_10000baseKR_Full 0x10 137 #define SUPPORTED_1000baseKX_Full 0x20 138 #define SUPPORTED_2500baseX_Full 0x40 139 #define SUPPORTED_10000baseR_FEC 0x80 140 141 #define BMCR_SPEED100 0x2000 142 143 #define MDIO_MMD_PMAPMD 1 144 #define MDIO_MMD_PCS 3 145 #define MDIO_MMD_AN 7 146 #define MDIO_PMA_10GBR_FECABLE 170 147 #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 148 #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 149 #define MII_ADDR_C45 (1<<30) 150 151 #define MDIO_CTRL1 0x00 /* MII_BMCR */ 152 #define MDIO_CTRL1_RESET 0x8000 /* BMCR_RESET */ 153 #define MDIO_CTRL1_SPEEDSELEXT 0x2040 /* BMCR_SPEED1000|BMCR_SPEED100*/ 154 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x3c) 155 #define MDIO_AN_CTRL1_ENABLE 0x1000 /* BMCR_AUTOEN */ 156 #define MDIO_CTRL1_LPOWER 0x0800 /* BMCR_PDOWN */ 157 #define MDIO_AN_CTRL1_RESTART 0x0200 /* BMCR_STARTNEG */ 158 159 #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) 160 161 #define MDIO_STAT1 1 /* MII_BMSR */ 162 #define MDIO_STAT1_LSTATUS 0x0004 /* BMSR_LINK */ 163 164 #define MDIO_CTRL2 0x07 165 #define MDIO_PCS_CTRL2_10GBR 0x0000 166 #define MDIO_PCS_CTRL2_10GBX 0x0001 167 #define MDIO_PCS_CTRL2_TYPE 0x0003 168 169 #define MDIO_AN_ADVERTISE 16 170 171 #define MDIO_AN_LPA 19 172 173 #define ETH_ALEN ETHER_ADDR_LEN 174 #define ETH_HLEN ETHER_HDR_LEN 175 #define ETH_FCS_LEN 4 176 #define VLAN_HLEN ETHER_VLAN_ENCAP_LEN 177 178 #define ARRAY_SIZE(x) nitems(x) 179 180 #define BITS_PER_LONG (sizeof(long) * CHAR_BIT) 181 #define BITS_TO_LONGS(n) howmany((n), BITS_PER_LONG) 182 183 #define NSEC_PER_SEC 1000000000ul 184 185 #define min_t(t, a, b) MIN((t)(a), (t)(b)) 186 #define max_t(t, a, b) MAX((t)(a), (t)(b)) 187 188 #endif /* _XGBE_OSDEP_H_ */ 189