1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016,2017 SoftIron Inc. 5 * Copyright (c) 2020 Advanced Micro Devices, Inc. 6 * 7 * This software was developed by Andrew Turner under 8 * the sponsorship of SoftIron Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #ifndef _XGBE_OSDEP_H_ 33 #define _XGBE_OSDEP_H_ 34 35 #include <sys/endian.h> 36 #include <sys/socket.h> 37 38 #include <net/ethernet.h> 39 #include <net/if.h> 40 #include <net/if_var.h> 41 #include <net/iflib.h> 42 43 MALLOC_DECLARE(M_AXGBE); 44 45 typedef uint16_t __le16; 46 typedef uint16_t __be16; 47 typedef uint32_t __le32; 48 49 #define BIT(pos) (1ul << pos) 50 51 #define cpu_to_be16(x) be16toh(x) 52 #define be16_to_cpu(x) htobe16(x) 53 #define lower_32_bits(x) ((x) & 0xffffffffu) 54 #define upper_32_bits(x) (((x) >> 32) & 0xffffffffu) 55 #define cpu_to_le32(x) le32toh(x) 56 #define le32_to_cpu(x) htole32(x) 57 #define cpu_to_le16(x) htole16(x) 58 59 typedef struct mtx spinlock_t; 60 61 static inline void 62 spin_lock_init(spinlock_t *spinlock) 63 { 64 mtx_init(spinlock, "axgbe_spin", NULL, MTX_SPIN); 65 } 66 67 #define spin_lock_irqsave(spinlock, flags) \ 68 do { \ 69 (flags) = intr_disable(); \ 70 mtx_lock_spin(spinlock); \ 71 } while (0) 72 73 #define spin_unlock_irqrestore(spinlock, flags) \ 74 do { \ 75 mtx_unlock_spin(spinlock); \ 76 intr_restore(flags); \ 77 } while (0) 78 79 #define ADVERTISED_Pause (1 << 0) 80 #define ADVERTISED_Asym_Pause (1 << 1) 81 #define ADVERTISED_Autoneg (1 << 2) 82 #define ADVERTISED_Backplane (1 << 3) 83 #define ADVERTISED_10000baseKR_Full (1 << 4) 84 #define ADVERTISED_2500baseX_Full (1 << 5) 85 #define ADVERTISED_1000baseKX_Full (1 << 6) 86 #define ADVERTISED_100baseT_Full (1 << 7) 87 #define ADVERTISED_10000baseR_FEC (1 << 8) 88 #define ADVERTISED_10000baseT_Full (1 << 9) 89 #define ADVERTISED_2500baseT_Full (1 << 10) 90 #define ADVERTISED_1000baseT_Full (1 << 11) 91 #define ADVERTISED_TP (1 << 12) 92 #define ADVERTISED_FIBRE (1 << 13) 93 #define ADVERTISED_1000baseX_Full (1 << 14) 94 #define ADVERTISED_10000baseSR_Full (1 << 15) 95 #define ADVERTISED_10000baseLR_Full (1 << 16) 96 #define ADVERTISED_10000baseLRM_Full (1 << 17) 97 #define ADVERTISED_10000baseER_Full (1 << 18) 98 #define ADVERTISED_10000baseCR_Full (1 << 19) 99 #define ADVERTISED_100baseT_Half (1 << 20) 100 #define ADVERTISED_1000baseT_Half (1 << 21) 101 102 #define SUPPORTED_Pause (1 << 0) 103 #define SUPPORTED_Asym_Pause (1 << 1) 104 #define SUPPORTED_Autoneg (1 << 2) 105 #define SUPPORTED_Backplane (1 << 3) 106 #define SUPPORTED_10000baseKR_Full (1 << 4) 107 #define SUPPORTED_2500baseX_Full (1 << 5) 108 #define SUPPORTED_1000baseKX_Full (1 << 6) 109 #define SUPPORTED_100baseT_Full (1 << 7) 110 #define SUPPORTED_10000baseR_FEC (1 << 8) 111 #define SUPPORTED_10000baseT_Full (1 << 9) 112 #define SUPPORTED_2500baseT_Full (1 << 10) 113 #define SUPPORTED_1000baseT_Full (1 << 11) 114 #define SUPPORTED_TP (1 << 12) 115 #define SUPPORTED_FIBRE (1 << 13) 116 #define SUPPORTED_1000baseX_Full (1 << 14) 117 #define SUPPORTED_10000baseSR_Full (1 << 15) 118 #define SUPPORTED_10000baseLR_Full (1 << 16) 119 #define SUPPORTED_10000baseLRM_Full (1 << 17) 120 #define SUPPORTED_10000baseER_Full (1 << 18) 121 #define SUPPORTED_10000baseCR_Full (1 << 19) 122 #define SUPPORTED_100baseT_Half (1 << 20) 123 #define SUPPORTED_1000baseT_Half (1 << 21) 124 125 #define LPA_PAUSE_ASYM 0x0800 126 127 #define AUTONEG_DISABLE 0 128 #define AUTONEG_ENABLE 1 129 130 #define DUPLEX_UNKNOWN 1 131 #define DUPLEX_FULL 2 132 #define DUPLEX_HALF 3 133 134 #define SPEED_UNKNOWN 1 135 #define SPEED_10000 2 136 #define SPEED_2500 3 137 #define SPEED_1000 4 138 #define SPEED_100 5 139 #define SPEED_10 6 140 141 #define BMCR_SPEED100 0x2000 142 143 #define MDIO_MMD_PMAPMD 1 144 #define MDIO_MMD_PCS 3 145 #define MDIO_MMD_AN 7 146 #define MDIO_MMD_VEND1 30 /* Vendor specific 1 */ 147 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ 148 149 #define MDIO_PMA_10GBR_FECABLE 170 150 #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 151 #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 152 #define MII_ADDR_C45 (1<<30) 153 154 #define MDIO_CTRL1 0x00 /* MII_BMCR */ 155 #define MDIO_CTRL1_RESET 0x8000 /* BMCR_RESET */ 156 #define MDIO_CTRL1_SPEEDSELEXT 0x2040 /* BMCR_SPEED1000|BMCR_SPEED100*/ 157 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x3c) 158 #define MDIO_AN_CTRL1_ENABLE 0x1000 /* BMCR_AUTOEN */ 159 #define MDIO_CTRL1_LPOWER 0x0800 /* BMCR_PDOWN */ 160 #define MDIO_AN_CTRL1_RESTART 0x0200 /* BMCR_STARTNEG */ 161 162 #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) 163 164 #define MDIO_STAT1 1 /* MII_BMSR */ 165 #define MDIO_STAT1_LSTATUS 0x0004 /* BMSR_LINK */ 166 167 #define MDIO_DEVID1 2 /* MII_PHYSID1 */ 168 #define MDIO_DEVID2 3 /* MII_PHYSID2 */ 169 #define MDIO_SPEED 4 170 #define MDIO_DEVS1 5 171 #define MDIO_DEVS2 6 172 #define MDIO_CTRL2 0x07 173 #define MDIO_PCS_CTRL2_10GBR 0x0000 174 #define MDIO_PCS_CTRL2_10GBX 0x0001 175 #define MDIO_PCS_CTRL2_TYPE 0x0003 176 177 #define MDIO_AN_ADVERTISE 16 178 179 #define MDIO_AN_LPA 19 180 181 #define ETH_ALEN ETHER_ADDR_LEN 182 #define ETH_HLEN ETHER_HDR_LEN 183 #define ETH_FCS_LEN 4 184 #define VLAN_HLEN ETHER_VLAN_ENCAP_LEN 185 #define VLAN_NVID 4096 186 #define VLAN_VID_MASK 0x0FFF 187 188 #define CRC32_POLY_LE 0xedb88320 189 190 #define ARRAY_SIZE(x) nitems(x) 191 192 #define BITS_PER_LONG (sizeof(long) * CHAR_BIT) 193 #define BITS_TO_LONGS(n) howmany((n), BITS_PER_LONG) 194 195 #define BITMAP_LAST_WORD_MASK(n) (~0UL >> (BITS_PER_LONG - (n))) 196 197 #define min_t(t, a, b) MIN((t)(a), (t)(b)) 198 #define max_t(t, a, b) MAX((t)(a), (t)(b)) 199 200 static inline void 201 clear_bit(int pos, unsigned long *p) 202 { 203 204 atomic_clear_long(p, 1ul << pos); 205 } 206 207 static inline int 208 test_bit(int pos, unsigned long *p) 209 { 210 unsigned long val; 211 212 val = *p; 213 return ((val & 1ul << pos) != 0); 214 } 215 216 static inline void 217 set_bit(int pos, unsigned long *p) 218 { 219 220 atomic_set_long(p, 1ul << pos); 221 } 222 223 static inline int 224 __ffsl(long mask) 225 { 226 227 return (ffsl(mask) - 1); 228 } 229 230 static inline int 231 get_bitmask_order(unsigned int count) 232 { 233 int order; 234 235 order = fls(count); 236 return (order); /* We could be slightly more clever with -1 here... */ 237 } 238 239 #endif /* _XGBE_OSDEP_H_ */ 240