1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc. 5 * 6 * This file is available to you under your choice of the following two 7 * licenses: 8 * 9 * License 1: GPLv2 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Redistribution and use in source and binary forms, with or without 60 * modification, are permitted provided that the following conditions are met: 61 * * Redistributions of source code must retain the above copyright 62 * notice, this list of conditions and the following disclaimer. 63 * * Redistributions in binary form must reproduce the above copyright 64 * notice, this list of conditions and the following disclaimer in the 65 * documentation and/or other materials provided with the distribution. 66 * * Neither the name of Advanced Micro Devices, Inc. nor the 67 * names of its contributors may be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 80 * 81 * This file incorporates work covered by the following copyright and 82 * permission notice: 83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 85 * Inc. unless otherwise expressly agreed to in writing between Synopsys 86 * and you. 87 * 88 * The Software IS NOT an item of Licensed Software or Licensed Product 89 * under any End User Software License Agreement or Agreement for Licensed 90 * Product with Synopsys or any supplement thereto. Permission is hereby 91 * granted, free of charge, to any person obtaining a copy of this software 92 * annotated with this license and the Software, to deal in the Software 93 * without restriction, including without limitation the rights to use, 94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 95 * of the Software, and to permit persons to whom the Software is furnished 96 * to do so, subject to the following conditions: 97 * 98 * The above copyright notice and this permission notice shall be included 99 * in all copies or substantial portions of the Software. 100 * 101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 111 * THE POSSIBILITY OF SUCH DAMAGE. 112 * 113 * $FreeBSD$ 114 */ 115 116 #ifndef __XGBE_H__ 117 #define __XGBE_H__ 118 119 #include <sys/param.h> 120 #if __FreeBSD_version < 1300000 121 #include <sys/kernel.h> 122 #endif 123 #include <sys/bus.h> 124 #include <sys/socket.h> 125 #include <sys/bitstring.h> 126 127 #include <net/if.h> 128 #include <net/if_media.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 133 #include "xgbe_osdep.h" 134 135 /* From linux/dcbnl.h */ 136 #define IEEE_8021QAZ_MAX_TCS 8 137 138 #define XGBE_DRV_NAME "amd-xgbe" 139 #define XGBE_DRV_VERSION "1.0.3" 140 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver" 141 142 /* Descriptor related defines */ 143 #define XGBE_TX_DESC_CNT 512 144 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3) 145 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1) 146 #define XGBE_RX_DESC_CNT 512 147 148 #define XGBE_TX_DESC_CNT_MIN 64 149 #define XGBE_TX_DESC_CNT_MAX 4096 150 #define XGBE_RX_DESC_CNT_MIN 64 151 #define XGBE_RX_DESC_CNT_MAX 4096 152 #define XGBE_TX_DESC_CNT_DEFAULT 512 153 #define XGBE_RX_DESC_CNT_DEFAULT 512 154 155 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) 156 157 /* Descriptors required for maximum contiguous TSO/GSO packet */ 158 #define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1) 159 160 /* Maximum possible descriptors needed for an SKB: 161 * - Maximum number of SKB frags 162 * - Maximum descriptors for contiguous TSO/GSO packet 163 * - Possible context descriptor 164 * - Possible TSO header descriptor 165 */ 166 #define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2) 167 168 #define XGBE_RX_MIN_BUF_SIZE 1522 169 #define XGBE_RX_BUF_ALIGN 64 170 #define XGBE_SKB_ALLOC_SIZE 256 171 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZ */ 172 173 #define XGBE_MAX_DMA_CHANNELS 16 174 #define XGBE_MAX_QUEUES 16 175 #define XGBE_PRIORITY_QUEUES 8 176 #define XGBE_DMA_STOP_TIMEOUT 5 177 178 /* DMA cache settings - Outer sharable, write-back, write-allocate */ 179 #define XGBE_DMA_OS_ARCR 0x002b2b2b 180 #define XGBE_DMA_OS_AWCR 0x2f2f2f2f 181 182 /* DMA cache settings - System, no caches used */ 183 #define XGBE_DMA_SYS_ARCR 0x00303030 184 #define XGBE_DMA_SYS_AWCR 0x30303030 185 186 /* DMA cache settings - PCI device */ 187 #define XGBE_DMA_PCI_ARCR 0x00000003 188 #define XGBE_DMA_PCI_AWCR 0x13131313 189 #define XGBE_DMA_PCI_AWARCR 0x00000313 190 191 /* DMA channel interrupt modes */ 192 #define XGBE_IRQ_MODE_EDGE 0 193 #define XGBE_IRQ_MODE_LEVEL 1 194 195 #define XGMAC_MIN_PACKET 60 196 #define XGMAC_STD_PACKET_MTU 1500 197 #define XGMAC_MAX_STD_PACKET 1518 198 #define XGMAC_JUMBO_PACKET_MTU 9000 199 #define XGMAC_MAX_JUMBO_PACKET 9018 200 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 201 202 #define XGMAC_PFC_DATA_LEN 46 203 #define XGMAC_PFC_DELAYS 14000 204 205 #define XGMAC_PRIO_QUEUES(_cnt) \ 206 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, (_cnt)) 207 208 /* Common property names */ 209 #define XGBE_MAC_ADDR_PROPERTY "mac-address" 210 #define XGBE_PHY_MODE_PROPERTY "phy-mode" 211 #define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt" 212 #define XGBE_SPEEDSET_PROPERTY "amd,speed-set" 213 #define XGBE_BLWC_PROPERTY "amd,serdes-blwc" 214 #define XGBE_CDR_RATE_PROPERTY "amd,serdes-cdr-rate" 215 #define XGBE_PQ_SKEW_PROPERTY "amd,serdes-pq-skew" 216 #define XGBE_TX_AMP_PROPERTY "amd,serdes-tx-amp" 217 #define XGBE_DFE_CFG_PROPERTY "amd,serdes-dfe-tap-config" 218 #define XGBE_DFE_ENA_PROPERTY "amd,serdes-dfe-tap-enable" 219 220 /* Device-tree clock names */ 221 #define XGBE_DMA_CLOCK "dma_clk" 222 #define XGBE_PTP_CLOCK "ptp_clk" 223 224 /* ACPI property names */ 225 #define XGBE_ACPI_DMA_FREQ "amd,dma-freq" 226 #define XGBE_ACPI_PTP_FREQ "amd,ptp-freq" 227 228 /* PCI BAR mapping */ 229 #define XGBE_XGMAC_BAR 0 230 #define XGBE_XPCS_BAR 1 231 #define XGBE_MAC_PROP_OFFSET 0x1d000 232 #define XGBE_I2C_CTRL_OFFSET 0x1e000 233 234 /* PCI MSI/MSIx support */ 235 #define XGBE_MSI_BASE_COUNT 4 236 #define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1) 237 238 /* PCI clock frequencies */ 239 #define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */ 240 #define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */ 241 242 /* Timestamp support - values based on 50MHz PTP clock 243 * 50MHz => 20 nsec 244 */ 245 #define XGBE_TSTAMP_SSINC 20 246 #define XGBE_TSTAMP_SNSINC 0 247 248 /* Driver PMT macros */ 249 #define XGMAC_DRIVER_CONTEXT 1 250 #define XGMAC_IOCTL_CONTEXT 2 251 252 #define XGMAC_FIFO_MIN_ALLOC 2048 253 #define XGMAC_FIFO_UNIT 256 254 #define XGMAC_FIFO_ALIGN(_x) \ 255 (((_x) + XGMAC_FIFO_UNIT - 1) & ~(XGMAC_FIFO_UNIT - 1)) 256 #define XGMAC_FIFO_FC_OFF 2048 257 #define XGMAC_FIFO_FC_MIN 4096 258 #define XGBE_FIFO_MAX 81920 259 260 #define XGBE_TC_MIN_QUANTUM 10 261 262 /* Helper macro for descriptor handling 263 * Always use XGBE_GET_DESC_DATA to access the descriptor data 264 * since the index is free-running and needs to be and-ed 265 * with the descriptor count value of the ring to index to 266 * the proper descriptor data. 267 */ 268 #define XGBE_GET_DESC_DATA(_ring, _idx) \ 269 ((_ring)->rdata + \ 270 ((_idx) & ((_ring)->rdesc_count - 1))) 271 272 /* Default coalescing parameters */ 273 #define XGMAC_INIT_DMA_TX_USECS 1000 274 #define XGMAC_INIT_DMA_TX_FRAMES 25 275 276 #define XGMAC_MAX_DMA_RIWT 0xff 277 #define XGMAC_INIT_DMA_RX_USECS 30 278 #define XGMAC_INIT_DMA_RX_FRAMES 25 279 280 /* Flow control queue count */ 281 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8 282 283 /* Flow control threshold units */ 284 #define XGMAC_FLOW_CONTROL_UNIT 512 285 #define XGMAC_FLOW_CONTROL_ALIGN(_x) \ 286 (((_x) + XGMAC_FLOW_CONTROL_UNIT - 1) & ~(XGMAC_FLOW_CONTROL_UNIT - 1)) 287 #define XGMAC_FLOW_CONTROL_VALUE(_x) \ 288 (((_x) < 1024) ? 0 : ((_x) / XGMAC_FLOW_CONTROL_UNIT) - 2) 289 #define XGMAC_FLOW_CONTROL_MAX 33280 290 291 /* Maximum MAC address hash table size (256 bits = 8 bytes) */ 292 #define XGBE_MAC_HASH_TABLE_SIZE 8 293 294 /* Receive Side Scaling */ 295 #define XGBE_RSS_HASH_KEY_SIZE 40 296 #define XGBE_RSS_MAX_TABLE_SIZE 256 297 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0 298 #define XGBE_RSS_HASH_KEY_TYPE 1 299 300 /* Auto-negotiation */ 301 #define XGBE_AN_MS_TIMEOUT 500 302 #define XGBE_LINK_TIMEOUT 10 303 304 #define XGBE_SGMII_AN_LINK_STATUS BIT(1) 305 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 306 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 307 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 308 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 309 310 /* ECC correctable error notification window (seconds) */ 311 #define XGBE_ECC_LIMIT 60 312 313 #define XGBE_AN_INT_CMPLT 0x01 314 #define XGBE_AN_INC_LINK 0x02 315 #define XGBE_AN_PG_RCV 0x04 316 #define XGBE_AN_INT_MASK 0x07 317 318 #define XGBE_SGMII_AN_LINK_STATUS BIT(1) 319 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 320 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 321 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 322 #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 323 324 /* Rate-change complete wait/retry count */ 325 #define XGBE_RATECHANGE_COUNT 500 326 327 /* Default SerDes settings */ 328 #define XGBE_SPEED_10000_BLWC 0 329 #define XGBE_SPEED_10000_CDR 0x7 330 #define XGBE_SPEED_10000_PLL 0x1 331 #define XGBE_SPEED_10000_PQ 0x12 332 #define XGBE_SPEED_10000_RATE 0x0 333 #define XGBE_SPEED_10000_TXAMP 0xa 334 #define XGBE_SPEED_10000_WORD 0x7 335 #define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1 336 #define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f 337 338 #define XGBE_SPEED_2500_BLWC 1 339 #define XGBE_SPEED_2500_CDR 0x2 340 #define XGBE_SPEED_2500_PLL 0x0 341 #define XGBE_SPEED_2500_PQ 0xa 342 #define XGBE_SPEED_2500_RATE 0x1 343 #define XGBE_SPEED_2500_TXAMP 0xf 344 #define XGBE_SPEED_2500_WORD 0x1 345 #define XGBE_SPEED_2500_DFE_TAP_CONFIG 0x3 346 #define XGBE_SPEED_2500_DFE_TAP_ENABLE 0x0 347 348 #define XGBE_SPEED_1000_BLWC 1 349 #define XGBE_SPEED_1000_CDR 0x2 350 #define XGBE_SPEED_1000_PLL 0x0 351 #define XGBE_SPEED_1000_PQ 0xa 352 #define XGBE_SPEED_1000_RATE 0x3 353 #define XGBE_SPEED_1000_TXAMP 0xf 354 #define XGBE_SPEED_1000_WORD 0x1 355 #define XGBE_SPEED_1000_DFE_TAP_CONFIG 0x3 356 #define XGBE_SPEED_1000_DFE_TAP_ENABLE 0x0 357 358 /* TSO related macros */ 359 #define XGBE_TSO_MAX_SIZE UINT16_MAX 360 361 /* MDIO port types */ 362 #define XGMAC_MAX_C22_PORT 3 363 364 /* Link mode bit operations */ 365 #define XGBE_ZERO_SUP(_phy) \ 366 ((_phy)->supported = 0) 367 368 #define XGBE_SET_SUP(_phy, _mode) \ 369 ((_phy)->supported |= SUPPORTED_##_mode) 370 371 #define XGBE_CLR_SUP(_phy, _mode) \ 372 ((_phy)->supported &= ~SUPPORTED_##_mode) 373 374 #define XGBE_IS_SUP(_phy, _mode) \ 375 ((_phy)->supported & SUPPORTED_##_mode) 376 377 #define XGBE_ZERO_ADV(_phy) \ 378 ((_phy)->advertising = 0) 379 380 #define XGBE_SET_ADV(_phy, _mode) \ 381 ((_phy)->advertising |= ADVERTISED_##_mode) 382 383 #define XGBE_CLR_ADV(_phy, _mode) \ 384 ((_phy)->advertising &= ~ADVERTISED_##_mode) 385 386 #define XGBE_ADV(_phy, _mode) \ 387 ((_phy)->advertising & ADVERTISED_##_mode) 388 389 #define XGBE_ZERO_LP_ADV(_phy) \ 390 ((_phy)->lp_advertising = 0) 391 392 #define XGBE_SET_LP_ADV(_phy, _mode) \ 393 ((_phy)->lp_advertising |= ADVERTISED_##_mode) 394 395 #define XGBE_CLR_LP_ADV(_phy, _mode) \ 396 ((_phy)->lp_advertising &= ~ADVERTISED_##_mode) 397 398 #define XGBE_LP_ADV(_phy, _mode) \ 399 ((_phy)->lp_advertising & ADVERTISED_##_mode) 400 401 #define XGBE_LM_COPY(_dphy, _dname, _sphy, _sname) \ 402 ((_dphy)->_dname = (_sphy)->_sname) 403 404 struct xgbe_prv_data; 405 406 struct xgbe_packet_data { 407 struct mbuf *m; 408 409 unsigned int attributes; 410 411 unsigned int errors; 412 413 unsigned int rdesc_count; 414 unsigned int length; 415 416 unsigned int header_len; 417 unsigned int tcp_header_len; 418 unsigned int tcp_payload_len; 419 unsigned short mss; 420 421 unsigned short vlan_ctag; 422 423 uint64_t rx_tstamp; 424 425 unsigned int tx_packets; 426 unsigned int tx_bytes; 427 428 uint32_t rss_hash; 429 uint32_t rss_hash_type; 430 }; 431 432 /* Common Rx and Tx descriptor mapping */ 433 struct xgbe_ring_desc { 434 __le32 desc0; 435 __le32 desc1; 436 __le32 desc2; 437 __le32 desc3; 438 }; 439 440 /* Tx-related ring data */ 441 struct xgbe_tx_ring_data { 442 unsigned int packets; /* BQL packet count */ 443 unsigned int bytes; /* BQL byte count */ 444 }; 445 446 /* Rx-related ring data */ 447 struct xgbe_rx_ring_data { 448 unsigned short hdr_len; /* Length of received header */ 449 unsigned short len; /* Length of received packet */ 450 }; 451 452 /* Structure used to hold information related to the descriptor 453 * and the packet associated with the descriptor (always use 454 * use the XGBE_GET_DESC_DATA macro to access this data from the ring) 455 */ 456 struct xgbe_ring_data { 457 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */ 458 bus_addr_t rdata_paddr; 459 460 struct xgbe_tx_ring_data tx; /* Tx-related data */ 461 struct xgbe_rx_ring_data rx; /* Rx-related data */ 462 463 464 /* Incomplete receive save location. If the budget is exhausted 465 * or the last descriptor (last normal descriptor or a following 466 * context descriptor) has not been DMA'd yet the current state 467 * of the receive processing needs to be saved. 468 */ 469 unsigned int state_saved; 470 struct { 471 struct mbuf *m; 472 unsigned int len; 473 unsigned int error; 474 } state; 475 476 }; 477 478 struct xgbe_ring { 479 /* Ring lock - used just for TX rings at the moment */ 480 spinlock_t lock; 481 482 /* Per packet related information */ 483 struct xgbe_packet_data packet_data; 484 485 /* Virtual/DMA addresses and count of allocated descriptor memory */ 486 struct xgbe_ring_desc *rdesc; 487 bus_addr_t rdesc_paddr; 488 unsigned int rdesc_count; 489 490 /* Array of descriptor data corresponding the descriptor memory 491 * (always use the XGBE_GET_DESC_DATA macro to access this data) 492 */ 493 struct xgbe_ring_data *rdata; 494 495 /* Ring index values 496 * cur - Tx: index of descriptor to be used for current transfer 497 * Rx: index of descriptor to check for packet availability 498 * dirty - Tx: index of descriptor to check for transfer complete 499 * Rx: index of descriptor to check for buffer reallocation 500 */ 501 unsigned int cur; 502 unsigned int dirty; 503 504 /* Coalesce frame count used for interrupt bit setting */ 505 unsigned int coalesce_count; 506 507 union { 508 struct { 509 unsigned int queue_stopped; 510 unsigned int xmit_more; 511 unsigned short cur_mss; 512 unsigned short cur_vlan_ctag; 513 } tx; 514 }; 515 516 uint16_t prev_pidx; 517 uint8_t prev_count; 518 519 } __aligned(CACHE_LINE_SIZE); 520 521 /* Structure used to describe the descriptor rings associated with 522 * a DMA channel. 523 */ 524 struct xgbe_channel { 525 char name[16]; 526 527 /* Address of private data area for device */ 528 struct xgbe_prv_data *pdata; 529 530 /* Queue index and base address of queue's DMA registers */ 531 unsigned int queue_index; 532 bus_space_tag_t dma_tag; 533 bus_space_handle_t dma_handle; 534 int dma_irq_rid; 535 536 /* Per channel interrupt irq number */ 537 struct resource *dma_irq_res; 538 void *dma_irq_tag; 539 540 /* Per channel interrupt enablement tracker */ 541 unsigned int curr_ier; 542 unsigned int saved_ier; 543 544 struct xgbe_ring *tx_ring; 545 struct xgbe_ring *rx_ring; 546 } __aligned(CACHE_LINE_SIZE); 547 548 enum xgbe_state { 549 XGBE_DOWN, 550 XGBE_LINK_INIT, 551 XGBE_LINK_ERR, 552 XGBE_STOPPED, 553 }; 554 555 enum xgbe_int { 556 XGMAC_INT_DMA_CH_SR_TI, 557 XGMAC_INT_DMA_CH_SR_TPS, 558 XGMAC_INT_DMA_CH_SR_TBU, 559 XGMAC_INT_DMA_CH_SR_RI, 560 XGMAC_INT_DMA_CH_SR_RBU, 561 XGMAC_INT_DMA_CH_SR_RPS, 562 XGMAC_INT_DMA_CH_SR_TI_RI, 563 XGMAC_INT_DMA_CH_SR_FBE, 564 XGMAC_INT_DMA_ALL, 565 }; 566 567 enum xgbe_int_state { 568 XGMAC_INT_STATE_SAVE, 569 XGMAC_INT_STATE_RESTORE, 570 }; 571 572 enum xgbe_ecc_sec { 573 XGBE_ECC_SEC_TX, 574 XGBE_ECC_SEC_RX, 575 XGBE_ECC_SEC_DESC, 576 }; 577 578 enum xgbe_speed { 579 XGBE_SPEED_1000 = 0, 580 XGBE_SPEED_2500, 581 XGBE_SPEED_10000, 582 XGBE_SPEEDS, 583 }; 584 585 enum xgbe_xpcs_access { 586 XGBE_XPCS_ACCESS_V1 = 0, 587 XGBE_XPCS_ACCESS_V2, 588 }; 589 590 enum xgbe_an_mode { 591 XGBE_AN_MODE_CL73 = 0, 592 XGBE_AN_MODE_CL73_REDRV, 593 XGBE_AN_MODE_CL37, 594 XGBE_AN_MODE_CL37_SGMII, 595 XGBE_AN_MODE_NONE, 596 }; 597 598 enum xgbe_an { 599 XGBE_AN_READY = 0, 600 XGBE_AN_PAGE_RECEIVED, 601 XGBE_AN_INCOMPAT_LINK, 602 XGBE_AN_COMPLETE, 603 XGBE_AN_NO_LINK, 604 XGBE_AN_ERROR, 605 }; 606 607 enum xgbe_rx { 608 XGBE_RX_BPA = 0, 609 XGBE_RX_XNP, 610 XGBE_RX_COMPLETE, 611 XGBE_RX_ERROR, 612 }; 613 614 enum xgbe_mode { 615 XGBE_MODE_KR = 0, 616 XGBE_MODE_KX, 617 XGBE_MODE_KX_1000, 618 XGBE_MODE_KX_2500, 619 XGBE_MODE_X, 620 XGBE_MODE_SGMII_100, 621 XGBE_MODE_SGMII_1000, 622 XGBE_MODE_SFI, 623 XGBE_MODE_UNKNOWN, 624 }; 625 626 enum xgbe_speedset { 627 XGBE_SPEEDSET_1000_10000 = 0, 628 XGBE_SPEEDSET_2500_10000, 629 }; 630 631 enum xgbe_mdio_mode { 632 XGBE_MDIO_MODE_NONE = 0, 633 XGBE_MDIO_MODE_CL22, 634 XGBE_MDIO_MODE_CL45, 635 }; 636 637 struct xgbe_phy { 638 uint32_t supported; 639 uint32_t advertising; 640 uint32_t lp_advertising; 641 642 int address; 643 644 int autoneg; 645 int speed; 646 int duplex; 647 648 int link; 649 650 int pause_autoneg; 651 int tx_pause; 652 int rx_pause; 653 654 int pause; 655 int asym_pause; 656 }; 657 658 enum xgbe_i2c_cmd { 659 XGBE_I2C_CMD_READ = 0, 660 XGBE_I2C_CMD_WRITE, 661 }; 662 663 struct xgbe_i2c_op { 664 enum xgbe_i2c_cmd cmd; 665 666 unsigned int target; 667 668 void *buf; 669 unsigned int len; 670 }; 671 672 struct xgbe_i2c_op_state { 673 struct xgbe_i2c_op *op; 674 675 unsigned int tx_len; 676 unsigned char *tx_buf; 677 678 unsigned int rx_len; 679 unsigned char *rx_buf; 680 681 unsigned int tx_abort_source; 682 683 int ret; 684 }; 685 686 struct xgbe_i2c { 687 unsigned int started; 688 unsigned int max_speed_mode; 689 unsigned int rx_fifo_size; 690 unsigned int tx_fifo_size; 691 692 struct xgbe_i2c_op_state op_state; 693 }; 694 695 struct xgbe_mmc_stats { 696 /* Tx Stats */ 697 uint64_t txoctetcount_gb; 698 uint64_t txframecount_gb; 699 uint64_t txbroadcastframes_g; 700 uint64_t txmulticastframes_g; 701 uint64_t tx64octets_gb; 702 uint64_t tx65to127octets_gb; 703 uint64_t tx128to255octets_gb; 704 uint64_t tx256to511octets_gb; 705 uint64_t tx512to1023octets_gb; 706 uint64_t tx1024tomaxoctets_gb; 707 uint64_t txunicastframes_gb; 708 uint64_t txmulticastframes_gb; 709 uint64_t txbroadcastframes_gb; 710 uint64_t txunderflowerror; 711 uint64_t txoctetcount_g; 712 uint64_t txframecount_g; 713 uint64_t txpauseframes; 714 uint64_t txvlanframes_g; 715 716 /* Rx Stats */ 717 uint64_t rxframecount_gb; 718 uint64_t rxoctetcount_gb; 719 uint64_t rxoctetcount_g; 720 uint64_t rxbroadcastframes_g; 721 uint64_t rxmulticastframes_g; 722 uint64_t rxcrcerror; 723 uint64_t rxrunterror; 724 uint64_t rxjabbererror; 725 uint64_t rxundersize_g; 726 uint64_t rxoversize_g; 727 uint64_t rx64octets_gb; 728 uint64_t rx65to127octets_gb; 729 uint64_t rx128to255octets_gb; 730 uint64_t rx256to511octets_gb; 731 uint64_t rx512to1023octets_gb; 732 uint64_t rx1024tomaxoctets_gb; 733 uint64_t rxunicastframes_g; 734 uint64_t rxlengtherror; 735 uint64_t rxoutofrangetype; 736 uint64_t rxpauseframes; 737 uint64_t rxfifooverflow; 738 uint64_t rxvlanframes_gb; 739 uint64_t rxwatchdogerror; 740 }; 741 742 struct xgbe_ext_stats { 743 uint64_t tx_tso_packets; 744 uint64_t rx_split_header_packets; 745 uint64_t rx_buffer_unavailable; 746 747 uint64_t txq_packets[XGBE_MAX_DMA_CHANNELS]; 748 uint64_t txq_bytes[XGBE_MAX_DMA_CHANNELS]; 749 uint64_t rxq_packets[XGBE_MAX_DMA_CHANNELS]; 750 uint64_t rxq_bytes[XGBE_MAX_DMA_CHANNELS]; 751 752 uint64_t tx_vxlan_packets; 753 uint64_t rx_vxlan_packets; 754 uint64_t rx_csum_errors; 755 uint64_t rx_vxlan_csum_errors; 756 }; 757 758 struct xgbe_hw_if { 759 int (*tx_complete)(struct xgbe_ring_desc *); 760 761 int (*set_mac_address)(struct xgbe_prv_data *, uint8_t *addr); 762 int (*config_rx_mode)(struct xgbe_prv_data *); 763 764 int (*enable_rx_csum)(struct xgbe_prv_data *); 765 int (*disable_rx_csum)(struct xgbe_prv_data *); 766 767 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *); 768 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *); 769 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *); 770 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *); 771 int (*update_vlan_hash_table)(struct xgbe_prv_data *); 772 773 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int); 774 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int); 775 int (*set_speed)(struct xgbe_prv_data *, int); 776 777 int (*set_ext_mii_mode)(struct xgbe_prv_data *, unsigned int, 778 enum xgbe_mdio_mode); 779 int (*read_ext_mii_regs)(struct xgbe_prv_data *, int, int); 780 int (*write_ext_mii_regs)(struct xgbe_prv_data *, int, int, uint16_t); 781 782 int (*set_gpio)(struct xgbe_prv_data *, unsigned int); 783 int (*clr_gpio)(struct xgbe_prv_data *, unsigned int); 784 785 void (*enable_tx)(struct xgbe_prv_data *); 786 void (*disable_tx)(struct xgbe_prv_data *); 787 void (*enable_rx)(struct xgbe_prv_data *); 788 void (*disable_rx)(struct xgbe_prv_data *); 789 790 void (*powerup_tx)(struct xgbe_prv_data *); 791 void (*powerdown_tx)(struct xgbe_prv_data *); 792 void (*powerup_rx)(struct xgbe_prv_data *); 793 void (*powerdown_rx)(struct xgbe_prv_data *); 794 795 int (*init)(struct xgbe_prv_data *); 796 int (*exit)(struct xgbe_prv_data *); 797 798 int (*enable_int)(struct xgbe_channel *, enum xgbe_int); 799 int (*disable_int)(struct xgbe_channel *, enum xgbe_int); 800 int (*dev_read)(struct xgbe_channel *); 801 void (*tx_desc_init)(struct xgbe_channel *); 802 void (*rx_desc_init)(struct xgbe_channel *); 803 void (*tx_desc_reset)(struct xgbe_ring_data *); 804 int (*is_last_desc)(struct xgbe_ring_desc *); 805 int (*is_context_desc)(struct xgbe_ring_desc *); 806 807 /* For FLOW ctrl */ 808 int (*config_tx_flow_control)(struct xgbe_prv_data *); 809 int (*config_rx_flow_control)(struct xgbe_prv_data *); 810 811 /* For RX coalescing */ 812 int (*config_rx_coalesce)(struct xgbe_prv_data *); 813 int (*config_tx_coalesce)(struct xgbe_prv_data *); 814 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int); 815 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int); 816 817 /* For RX and TX threshold config */ 818 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int); 819 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int); 820 821 /* For RX and TX Store and Forward Mode config */ 822 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int); 823 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int); 824 825 /* For TX DMA Operate on Second Frame config */ 826 int (*config_osp_mode)(struct xgbe_prv_data *); 827 828 /* For MMC statistics */ 829 void (*rx_mmc_int)(struct xgbe_prv_data *); 830 void (*tx_mmc_int)(struct xgbe_prv_data *); 831 void (*read_mmc_stats)(struct xgbe_prv_data *); 832 833 /* For Receive Side Scaling */ 834 int (*enable_rss)(struct xgbe_prv_data *); 835 int (*disable_rss)(struct xgbe_prv_data *); 836 int (*set_rss_hash_key)(struct xgbe_prv_data *, const uint8_t *); 837 int (*set_rss_lookup_table)(struct xgbe_prv_data *, const uint32_t *); 838 }; 839 840 /* This structure represents implementation specific routines for an 841 * implementation of a PHY. All routines are required unless noted below. 842 * Optional routines: 843 * an_pre, an_post 844 * kr_training_pre, kr_training_post 845 * module_info, module_eeprom 846 */ 847 struct xgbe_phy_impl_if { 848 /* Perform Setup/teardown actions */ 849 int (*init)(struct xgbe_prv_data *); 850 void (*exit)(struct xgbe_prv_data *); 851 852 /* Perform start/stop specific actions */ 853 int (*reset)(struct xgbe_prv_data *); 854 int (*start)(struct xgbe_prv_data *); 855 void (*stop)(struct xgbe_prv_data *); 856 857 /* Return the link status */ 858 int (*link_status)(struct xgbe_prv_data *, int *); 859 860 /* Indicate if a particular speed is valid */ 861 bool (*valid_speed)(struct xgbe_prv_data *, int); 862 863 /* Check if the specified mode can/should be used */ 864 bool (*use_mode)(struct xgbe_prv_data *, enum xgbe_mode); 865 /* Switch the PHY into various modes */ 866 void (*set_mode)(struct xgbe_prv_data *, enum xgbe_mode); 867 /* Retrieve mode needed for a specific speed */ 868 enum xgbe_mode (*get_mode)(struct xgbe_prv_data *, int); 869 /* Retrieve new/next mode when trying to auto-negotiate */ 870 enum xgbe_mode (*switch_mode)(struct xgbe_prv_data *); 871 /* Retrieve current mode */ 872 enum xgbe_mode (*cur_mode)(struct xgbe_prv_data *); 873 /* Retrieve interface sub-type */ 874 void (*get_type)(struct xgbe_prv_data *, struct ifmediareq *); 875 876 /* Retrieve current auto-negotiation mode */ 877 enum xgbe_an_mode (*an_mode)(struct xgbe_prv_data *); 878 879 /* Configure auto-negotiation settings */ 880 int (*an_config)(struct xgbe_prv_data *); 881 882 /* Set/override auto-negotiation advertisement settings */ 883 void (*an_advertising)(struct xgbe_prv_data *, 884 struct xgbe_phy *); 885 886 /* Process results of auto-negotiation */ 887 enum xgbe_mode (*an_outcome)(struct xgbe_prv_data *); 888 889 /* Pre/Post auto-negotiation support */ 890 void (*an_pre)(struct xgbe_prv_data *); 891 void (*an_post)(struct xgbe_prv_data *); 892 893 /* Pre/Post KR training enablement support */ 894 void (*kr_training_pre)(struct xgbe_prv_data *); 895 void (*kr_training_post)(struct xgbe_prv_data *); 896 897 /* SFP module related info */ 898 int (*module_info)(struct xgbe_prv_data *pdata); 899 int (*module_eeprom)(struct xgbe_prv_data *pdata); 900 }; 901 902 struct xgbe_phy_if { 903 /* For PHY setup/teardown */ 904 int (*phy_init)(struct xgbe_prv_data *); 905 void (*phy_exit)(struct xgbe_prv_data *); 906 907 /* For PHY support when setting device up/down */ 908 int (*phy_reset)(struct xgbe_prv_data *); 909 int (*phy_start)(struct xgbe_prv_data *); 910 void (*phy_stop)(struct xgbe_prv_data *); 911 912 /* For PHY support while device is up */ 913 void (*phy_status)(struct xgbe_prv_data *); 914 int (*phy_config_aneg)(struct xgbe_prv_data *); 915 916 /* For PHY settings validation */ 917 bool (*phy_valid_speed)(struct xgbe_prv_data *, int); 918 919 /* For single interrupt support */ 920 void (*an_isr)(struct xgbe_prv_data *); 921 922 /* PHY implementation specific services */ 923 struct xgbe_phy_impl_if phy_impl; 924 }; 925 926 struct xgbe_i2c_if { 927 /* For initial I2C setup */ 928 int (*i2c_init)(struct xgbe_prv_data *); 929 930 /* For I2C support when setting device up/down */ 931 int (*i2c_start)(struct xgbe_prv_data *); 932 void (*i2c_stop)(struct xgbe_prv_data *); 933 934 /* For performing I2C operations */ 935 int (*i2c_xfer)(struct xgbe_prv_data *, struct xgbe_i2c_op *); 936 937 /* For single interrupt support */ 938 void (*i2c_isr)(struct xgbe_prv_data *); 939 }; 940 941 struct xgbe_desc_if { 942 int (*alloc_ring_resources)(struct xgbe_prv_data *); 943 void (*free_ring_resources)(struct xgbe_prv_data *); 944 int (*map_tx_skb)(struct xgbe_channel *, struct mbuf *); 945 int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *, 946 struct xgbe_ring_data *); 947 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *); 948 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *); 949 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *); 950 }; 951 952 /* This structure contains flags that indicate what hardware features 953 * or configurations are present in the device. 954 */ 955 struct xgbe_hw_features { 956 /* HW Version */ 957 unsigned int version; 958 959 /* HW Feature Register0 */ 960 unsigned int gmii; /* 1000 Mbps support */ 961 unsigned int vlhash; /* VLAN Hash Filter */ 962 unsigned int sma; /* SMA(MDIO) Interface */ 963 unsigned int rwk; /* PMT remote wake-up packet */ 964 unsigned int mgk; /* PMT magic packet */ 965 unsigned int mmc; /* RMON module */ 966 unsigned int aoe; /* ARP Offload */ 967 unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ 968 unsigned int eee; /* Energy Efficient Ethernet */ 969 unsigned int tx_coe; /* Tx Checksum Offload */ 970 unsigned int rx_coe; /* Rx Checksum Offload */ 971 unsigned int addn_mac; /* Additional MAC Addresses */ 972 unsigned int ts_src; /* Timestamp Source */ 973 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ 974 unsigned int vxn; /* VXLAN/NVGRE */ 975 976 /* HW Feature Register1 */ 977 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ 978 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ 979 unsigned int adv_ts_hi; /* Advance Timestamping High Word */ 980 unsigned int dma_width; /* DMA width */ 981 unsigned int dcb; /* DCB Feature */ 982 unsigned int sph; /* Split Header Feature */ 983 unsigned int tso; /* TCP Segmentation Offload */ 984 unsigned int dma_debug; /* DMA Debug Registers */ 985 unsigned int rss; /* Receive Side Scaling */ 986 unsigned int tc_cnt; /* Number of Traffic Classes */ 987 unsigned int hash_table_size; /* Hash Table Size */ 988 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ 989 990 /* HW Feature Register2 */ 991 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ 992 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ 993 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ 994 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ 995 unsigned int pps_out_num; /* Number of PPS outputs */ 996 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ 997 }; 998 999 struct xgbe_version_data { 1000 void (*init_function_ptrs_phy_impl)(struct xgbe_phy_if *); 1001 enum xgbe_xpcs_access xpcs_access; 1002 unsigned int mmc_64bit; 1003 unsigned int tx_max_fifo_size; 1004 unsigned int rx_max_fifo_size; 1005 unsigned int tx_tstamp_workaround; 1006 unsigned int ecc_support; 1007 unsigned int i2c_support; 1008 unsigned int irq_reissue_support; 1009 unsigned int tx_desc_prefetch; 1010 unsigned int rx_desc_prefetch; 1011 unsigned int an_cdr_workaround; 1012 }; 1013 1014 struct xgbe_prv_data { 1015 struct ifnet *netdev; 1016 1017 struct platform_device *pdev; 1018 struct acpi_device *adev; 1019 device_t dev; 1020 1021 /* Version related data */ 1022 struct xgbe_version_data *vdata; 1023 1024 /* ACPI or DT flag */ 1025 unsigned int use_acpi; 1026 1027 /* XGMAC/XPCS related mmio registers */ 1028 struct resource *xgmac_res; /* XGMAC CSRs */ 1029 struct resource *xpcs_res; /* XPCS MMD registers */ 1030 struct resource *rxtx_res; /* SerDes Rx/Tx CSRs */ 1031 struct resource *sir0_res; /* SerDes integration registers (1/2) */ 1032 struct resource *sir1_res; /* SerDes integration registers (2/2) */ 1033 1034 /* Port property registers */ 1035 unsigned int pp0; 1036 unsigned int pp1; 1037 unsigned int pp2; 1038 unsigned int pp3; 1039 unsigned int pp4; 1040 1041 /* DMA tag */ 1042 bus_dma_tag_t dmat; 1043 1044 /* XPCS indirect addressing lock */ 1045 spinlock_t xpcs_lock; 1046 unsigned int xpcs_window_def_reg; 1047 unsigned int xpcs_window_sel_reg; 1048 unsigned int xpcs_window; 1049 unsigned int xpcs_window_size; 1050 unsigned int xpcs_window_mask; 1051 1052 /* RSS addressing mutex */ 1053 struct mtx rss_mutex; 1054 1055 /* Flags representing xgbe_state */ 1056 unsigned long dev_state; 1057 1058 /* ECC support */ 1059 unsigned long tx_sec_period; 1060 unsigned long tx_ded_period; 1061 unsigned long rx_sec_period; 1062 unsigned long rx_ded_period; 1063 unsigned long desc_sec_period; 1064 unsigned long desc_ded_period; 1065 1066 unsigned int tx_sec_count; 1067 unsigned int tx_ded_count; 1068 unsigned int rx_sec_count; 1069 unsigned int rx_ded_count; 1070 unsigned int desc_ded_count; 1071 unsigned int desc_sec_count; 1072 1073 struct if_irq dev_irq; 1074 1075 struct resource *dev_irq_res; 1076 struct resource *ecc_irq_res; 1077 struct resource *i2c_irq_res; 1078 struct resource *an_irq_res; 1079 1080 int ecc_rid; 1081 int i2c_rid; 1082 int an_rid; 1083 1084 void *dev_irq_tag; 1085 void *ecc_irq_tag; 1086 void *i2c_irq_tag; 1087 void *an_irq_tag; 1088 1089 struct resource *chan_irq_res[XGBE_MAX_DMA_CHANNELS]; 1090 1091 unsigned int per_channel_irq; 1092 unsigned int irq_count; 1093 unsigned int channel_irq_count; 1094 unsigned int channel_irq_mode; 1095 1096 char ecc_name[IFNAMSIZ + 32]; 1097 1098 unsigned int isr_as_tasklet; 1099 struct xgbe_hw_if hw_if; 1100 struct xgbe_phy_if phy_if; 1101 struct xgbe_desc_if desc_if; 1102 struct xgbe_i2c_if i2c_if; 1103 1104 /* AXI DMA settings */ 1105 unsigned int coherent; 1106 unsigned int arcr; 1107 unsigned int awcr; 1108 unsigned int awarcr; 1109 1110 /* Service routine support */ 1111 struct taskqueue *dev_workqueue; 1112 struct task service_work; 1113 struct callout service_timer; 1114 struct mtx timer_mutex; 1115 1116 /* Rings for Tx/Rx on a DMA channel */ 1117 struct xgbe_channel *channel[XGBE_MAX_DMA_CHANNELS]; 1118 unsigned int tx_max_channel_count; 1119 unsigned int rx_max_channel_count; 1120 unsigned int total_channel_count; 1121 unsigned int channel_count; 1122 unsigned int tx_ring_count; 1123 unsigned int tx_desc_count; 1124 unsigned int rx_ring_count; 1125 unsigned int rx_desc_count; 1126 1127 unsigned int new_tx_ring_count; 1128 unsigned int new_rx_ring_count; 1129 1130 unsigned int tx_max_q_count; 1131 unsigned int rx_max_q_count; 1132 unsigned int tx_q_count; 1133 unsigned int rx_q_count; 1134 1135 /* Tx/Rx common settings */ 1136 unsigned int blen; 1137 unsigned int pbl; 1138 unsigned int aal; 1139 unsigned int rd_osr_limit; 1140 unsigned int wr_osr_limit; 1141 1142 /* Tx settings */ 1143 unsigned int tx_sf_mode; 1144 unsigned int tx_threshold; 1145 unsigned int tx_osp_mode; 1146 unsigned int tx_max_fifo_size; 1147 1148 /* Rx settings */ 1149 unsigned int rx_sf_mode; 1150 unsigned int rx_threshold; 1151 unsigned int rx_max_fifo_size; 1152 1153 /* Tx coalescing settings */ 1154 unsigned int tx_usecs; 1155 unsigned int tx_frames; 1156 1157 /* Rx coalescing settings */ 1158 unsigned int rx_riwt; 1159 unsigned int rx_usecs; 1160 unsigned int rx_frames; 1161 1162 /* Current Rx buffer size */ 1163 unsigned int rx_buf_size; 1164 1165 /* Flow control settings */ 1166 unsigned int pause_autoneg; 1167 unsigned int tx_pause; 1168 unsigned int rx_pause; 1169 unsigned int rx_rfa[XGBE_MAX_QUEUES]; 1170 unsigned int rx_rfd[XGBE_MAX_QUEUES]; 1171 1172 /* Receive Side Scaling settings */ 1173 uint8_t rss_key[XGBE_RSS_HASH_KEY_SIZE]; 1174 uint32_t rss_table[XGBE_RSS_MAX_TABLE_SIZE]; 1175 uint32_t rss_options; 1176 unsigned int enable_rss; 1177 1178 /* VXLAN settings */ 1179 unsigned int vxlan_port_set; 1180 unsigned int vxlan_offloads_set; 1181 unsigned int vxlan_force_disable; 1182 unsigned int vxlan_port_count; 1183 uint16_t vxlan_port; 1184 uint64_t vxlan_features; 1185 1186 /* Netdev related settings */ 1187 unsigned char mac_addr[ETH_ALEN]; 1188 uint64_t netdev_features; 1189 struct xgbe_mmc_stats mmc_stats; 1190 struct xgbe_ext_stats ext_stats; 1191 1192 /* Filtering support */ 1193 bitstr_t *active_vlans; 1194 unsigned int num_active_vlans; 1195 1196 /* Device clocks */ 1197 struct clk *sysclk; 1198 unsigned long sysclk_rate; 1199 struct clk *ptpclk; 1200 unsigned long ptpclk_rate; 1201 1202 /* DCB support */ 1203 unsigned int q2tc_map[XGBE_MAX_QUEUES]; 1204 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS]; 1205 1206 /* Hardware features of the device */ 1207 struct xgbe_hw_features hw_feat; 1208 1209 /* Device work structure */ 1210 struct task restart_work; 1211 struct task stopdev_work; 1212 1213 /* Keeps track of power mode */ 1214 unsigned int power_down; 1215 1216 /* Network interface message level setting */ 1217 uint32_t msg_enable; 1218 1219 /* Current PHY settings */ 1220 int phy_link; 1221 int phy_speed; 1222 1223 /* MDIO/PHY related settings */ 1224 unsigned int phy_started; 1225 void *phy_data; 1226 struct xgbe_phy phy; 1227 int mdio_mmd; 1228 unsigned long link_check; 1229 struct mtx mdio_mutex; 1230 unsigned int mdio_addr; 1231 1232 unsigned int kr_redrv; 1233 1234 char an_name[IFNAMSIZ + 32]; 1235 struct taskqueue *an_workqueue; 1236 1237 struct task an_irq_work; 1238 1239 unsigned int speed_set; 1240 1241 /* SerDes UEFI configurable settings. 1242 * Switching between modes/speeds requires new values for some 1243 * SerDes settings. The values can be supplied as device 1244 * properties in array format. The first array entry is for 1245 * 1GbE, second for 2.5GbE and third for 10GbE 1246 */ 1247 uint32_t serdes_blwc[XGBE_SPEEDS]; 1248 uint32_t serdes_cdr_rate[XGBE_SPEEDS]; 1249 uint32_t serdes_pq_skew[XGBE_SPEEDS]; 1250 uint32_t serdes_tx_amp[XGBE_SPEEDS]; 1251 uint32_t serdes_dfe_tap_cfg[XGBE_SPEEDS]; 1252 uint32_t serdes_dfe_tap_ena[XGBE_SPEEDS]; 1253 1254 /* Auto-negotiation state machine support */ 1255 unsigned int an_int; 1256 unsigned int an_status; 1257 struct sx an_mutex; 1258 enum xgbe_an an_result; 1259 enum xgbe_an an_state; 1260 enum xgbe_rx kr_state; 1261 enum xgbe_rx kx_state; 1262 struct task an_work; 1263 unsigned int an_again; 1264 unsigned int an_supported; 1265 unsigned int parallel_detect; 1266 unsigned int fec_ability; 1267 unsigned long an_start; 1268 enum xgbe_an_mode an_mode; 1269 1270 /* I2C support */ 1271 struct xgbe_i2c i2c; 1272 struct mtx i2c_mutex; 1273 bool i2c_complete; 1274 1275 unsigned int lpm_ctrl; /* CTRL1 for resume */ 1276 unsigned int an_cdr_track_early; 1277 1278 uint64_t features; 1279 1280 device_t axgbe_miibus; 1281 unsigned int sysctl_xgmac_reg; 1282 unsigned int sysctl_xpcs_mmd; 1283 unsigned int sysctl_xpcs_reg; 1284 1285 unsigned int sysctl_xprop_reg; 1286 unsigned int sysctl_xi2c_reg; 1287 1288 bool sysctl_an_cdr_workaround; 1289 bool sysctl_an_cdr_track_early; 1290 1291 int pcie_bus; /* PCIe bus number */ 1292 int pcie_device; /* PCIe device/slot number */ 1293 int pcie_func; /* PCIe function number */ 1294 1295 void *sys_op; 1296 uint64_t use_adaptive_rx_coalesce; 1297 uint64_t use_adaptive_tx_coalesce; 1298 uint64_t rx_coalesce_usecs; 1299 1300 unsigned int debug_level; 1301 }; 1302 1303 struct axgbe_if_softc { 1304 struct xgbe_prv_data pdata; 1305 if_softc_ctx_t scctx; 1306 if_shared_ctx_t sctx; 1307 if_ctx_t ctx; 1308 struct ifnet *ifp; 1309 struct ifmedia *media; 1310 unsigned int link_status; 1311 }; 1312 1313 /* Function prototypes*/ 1314 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *); 1315 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *); 1316 void xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *); 1317 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *); 1318 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *); 1319 void xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *); 1320 void xgbe_get_all_hw_features(struct xgbe_prv_data *); 1321 void xgbe_init_rx_coalesce(struct xgbe_prv_data *); 1322 void xgbe_init_tx_coalesce(struct xgbe_prv_data *); 1323 1324 int xgbe_calc_rx_buf_size(struct ifnet *netdev, unsigned int mtu); 1325 1326 void axgbe_sysctl_init(struct xgbe_prv_data *pdata); 1327 void axgbe_sysctl_exit(struct xgbe_prv_data *pdata); 1328 1329 int xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, 1330 uint16_t val); 1331 int xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg); 1332 1333 void xgbe_dump_i2c_registers(struct xgbe_prv_data *); 1334 1335 uint32_t bitrev32(uint32_t); 1336 1337 /* For debug prints */ 1338 #ifdef YDEBUG 1339 #define DBGPR(x...) device_printf(pdata->dev, x) 1340 #else 1341 #define DBGPR(x...) do { } while (0) 1342 #endif 1343 1344 #ifdef YDEBUG_MDIO 1345 #define DBGPR_MDIO(x...) device_printf(pdata->dev, x) 1346 #else 1347 #define DBGPR_MDIO(x...) do { } while (0) 1348 #endif 1349 1350 #define axgbe_printf(lvl, ...) do { \ 1351 if (lvl <= pdata->debug_level) \ 1352 device_printf(pdata->dev, __VA_ARGS__); \ 1353 } while (0) 1354 1355 #define axgbe_error(...) do { \ 1356 device_printf(pdata->dev, __VA_ARGS__); \ 1357 } while (0) 1358 1359 #endif /* __XGBE_H__ */ 1360