1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * Copyright (c) 2020 Advanced Micro Devices, Inc. 5 * 6 * This file is available to you under your choice of the following two 7 * licenses: 8 * 9 * License 1: GPLv2 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Redistribution and use in source and binary forms, with or without 60 * modification, are permitted provided that the following conditions are met: 61 * * Redistributions of source code must retain the above copyright 62 * notice, this list of conditions and the following disclaimer. 63 * * Redistributions in binary form must reproduce the above copyright 64 * notice, this list of conditions and the following disclaimer in the 65 * documentation and/or other materials provided with the distribution. 66 * * Neither the name of Advanced Micro Devices, Inc. nor the 67 * names of its contributors may be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 80 * 81 * This file incorporates work covered by the following copyright and 82 * permission notice: 83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 85 * Inc. unless otherwise expressly agreed to in writing between Synopsys 86 * and you. 87 * 88 * The Software IS NOT an item of Licensed Software or Licensed Product 89 * under any End User Software License Agreement or Agreement for Licensed 90 * Product with Synopsys or any supplement thereto. Permission is hereby 91 * granted, free of charge, to any person obtaining a copy of this software 92 * annotated with this license and the Software, to deal in the Software 93 * without restriction, including without limitation the rights to use, 94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 95 * of the Software, and to permit persons to whom the Software is furnished 96 * to do so, subject to the following conditions: 97 * 98 * The above copyright notice and this permission notice shall be included 99 * in all copies or substantial portions of the Software. 100 * 101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 111 * THE POSSIBILITY OF SUCH DAMAGE. 112 */ 113 114 #include <sys/cdefs.h> 115 #include "xgbe.h" 116 #include "xgbe-common.h" 117 118 struct mtx xgbe_phy_comm_lock; 119 120 #define XGBE_PHY_PORT_SPEED_100 BIT(0) 121 #define XGBE_PHY_PORT_SPEED_1000 BIT(1) 122 #define XGBE_PHY_PORT_SPEED_2500 BIT(2) 123 #define XGBE_PHY_PORT_SPEED_10000 BIT(3) 124 125 #define XGBE_MUTEX_RELEASE 0x80000000 126 127 #define XGBE_SFP_DIRECT 7 128 #define GPIO_MASK_WIDTH 4 129 130 /* I2C target addresses */ 131 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 132 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 133 #define XGBE_SFP_PHY_ADDRESS 0x56 134 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 135 136 /* SFP sideband signal indicators */ 137 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 138 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 139 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 140 #define XGBE_GPIO_NO_RX_LOS BIT(3) 141 142 /* Rate-change complete wait/retry count */ 143 #define XGBE_RATECHANGE_COUNT 500 144 145 /* CDR delay values for KR support (in usec) */ 146 #define XGBE_CDR_DELAY_INIT 10000 147 #define XGBE_CDR_DELAY_INC 10000 148 #define XGBE_CDR_DELAY_MAX 100000 149 150 /* RRC frequency during link status check */ 151 #define XGBE_RRC_FREQUENCY 10 152 153 /* SFP port max PHY probe retries */ 154 #define XGBE_SFP_PHY_RETRY_MAX 5 155 156 enum xgbe_port_mode { 157 XGBE_PORT_MODE_RSVD = 0, 158 XGBE_PORT_MODE_BACKPLANE, 159 XGBE_PORT_MODE_BACKPLANE_2500, 160 XGBE_PORT_MODE_1000BASE_T, 161 XGBE_PORT_MODE_1000BASE_X, 162 XGBE_PORT_MODE_NBASE_T, 163 XGBE_PORT_MODE_10GBASE_T, 164 XGBE_PORT_MODE_10GBASE_R, 165 XGBE_PORT_MODE_SFP, 166 XGBE_PORT_MODE_MAX, 167 }; 168 169 enum xgbe_conn_type { 170 XGBE_CONN_TYPE_NONE = 0, 171 XGBE_CONN_TYPE_SFP, 172 XGBE_CONN_TYPE_MDIO, 173 XGBE_CONN_TYPE_RSVD1, 174 XGBE_CONN_TYPE_BACKPLANE, 175 XGBE_CONN_TYPE_MAX, 176 }; 177 178 /* SFP/SFP+ related definitions */ 179 enum xgbe_sfp_comm { 180 XGBE_SFP_COMM_DIRECT = 0, 181 XGBE_SFP_COMM_PCA9545, 182 }; 183 184 enum xgbe_sfp_cable { 185 XGBE_SFP_CABLE_UNKNOWN = 0, 186 XGBE_SFP_CABLE_ACTIVE, 187 XGBE_SFP_CABLE_PASSIVE, 188 }; 189 190 enum xgbe_sfp_base { 191 XGBE_SFP_BASE_UNKNOWN = 0, 192 XGBE_SFP_BASE_PX, 193 XGBE_SFP_BASE_BX10, 194 XGBE_SFP_BASE_100_FX, 195 XGBE_SFP_BASE_100_LX10, 196 XGBE_SFP_BASE_100_BX, 197 XGBE_SFP_BASE_1000_T, 198 XGBE_SFP_BASE_1000_SX, 199 XGBE_SFP_BASE_1000_LX, 200 XGBE_SFP_BASE_1000_CX, 201 XGBE_SFP_BASE_1000_BX, 202 XGBE_SFP_BASE_10000_SR, 203 XGBE_SFP_BASE_10000_LR, 204 XGBE_SFP_BASE_10000_LRM, 205 XGBE_SFP_BASE_10000_ER, 206 XGBE_SFP_BASE_10000_CR, 207 }; 208 209 enum xgbe_sfp_speed { 210 XGBE_SFP_SPEED_UNKNOWN = 0, 211 XGBE_SFP_SPEED_100, 212 XGBE_SFP_SPEED_100_1000, 213 XGBE_SFP_SPEED_1000, 214 XGBE_SFP_SPEED_10000, 215 XGBE_SFP_SPEED_25000, 216 }; 217 218 /* SFP Serial ID Base ID values relative to an offset of 0 */ 219 #define XGBE_SFP_BASE_ID 0 220 #define XGBE_SFP_ID_SFP 0x03 221 222 #define XGBE_SFP_BASE_EXT_ID 1 223 #define XGBE_SFP_EXT_ID_SFP 0x04 224 225 #define XGBE_SFP_BASE_CV 2 226 #define XGBE_SFP_BASE_CV_CP 0x21 227 228 #define XGBE_SFP_BASE_10GBE_CC 3 229 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 230 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 231 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 232 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 233 234 #define XGBE_SFP_BASE_1GBE_CC 6 235 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 236 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 237 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 238 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 239 #define XGBE_SFP_BASE_100M_CC_LX10 BIT(4) 240 #define XGBE_SFP_BASE_100M_CC_FX BIT(5) 241 #define XGBE_SFP_BASE_CC_BX10 BIT(6) 242 #define XGBE_SFP_BASE_CC_PX BIT(7) 243 244 #define XGBE_SFP_BASE_CABLE 8 245 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 246 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 247 248 #define XGBE_SFP_BASE_BR 12 249 #define XGBE_SFP_BASE_BR_100M_MIN 0x1 250 #define XGBE_SFP_BASE_BR_100M_MAX 0x2 251 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 252 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d 253 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 254 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68 255 #define XGBE_SFP_BASE_BR_25GBE 0xFF 256 257 /* Single mode, length of fiber in units of km */ 258 #define XGBE_SFP_BASE_SM_LEN_KM 14 259 #define XGBE_SFP_BASE_SM_LEN_KM_MIN 0x0A 260 261 /* Single mode, length of fiber in units of 100m */ 262 #define XGBE_SFP_BASE_SM_LEN_100M 15 263 #define XGBE_SFP_BASE_SM_LEN_100M_MIN 0x64 264 265 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 266 267 #define XGBE_SFP_BASE_VENDOR_NAME 20 268 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 269 #define XGBE_SFP_BASE_VENDOR_PN 40 270 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 271 #define XGBE_SFP_BASE_VENDOR_REV 56 272 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 273 274 /* 275 * Optical specification compliance - denotes wavelength 276 * for optical tranceivers 277 */ 278 #define XGBE_SFP_BASE_OSC 60 279 #define XGBE_SFP_BASE_OSC_LEN 2 280 #define XGBE_SFP_BASE_OSC_1310 0x051E 281 282 #define XGBE_SFP_BASE_CC 63 283 284 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 285 #define XGBE_SFP_BASE_VENDOR_SN 4 286 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 287 288 #define XGBE_SFP_EXTD_OPT1 1 289 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) 290 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) 291 292 #define XGBE_SFP_EXTD_DIAG 28 293 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 294 295 #define XGBE_SFP_EXTD_SFF_8472 30 296 297 #define XGBE_SFP_EXTD_CC 31 298 299 struct xgbe_sfp_eeprom { 300 uint8_t base[64]; 301 uint8_t extd[32]; 302 uint8_t vendor[32]; 303 }; 304 305 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \ 306 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \ 307 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 308 309 #define XGBE_SFP_EEPROM_BASE_LEN 256 310 #define XGBE_SFP_EEPROM_DIAG_LEN 256 311 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \ 312 XGBE_SFP_EEPROM_DIAG_LEN) 313 314 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 315 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 316 317 struct xgbe_sfp_ascii { 318 union { 319 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 320 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 321 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 322 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 323 } u; 324 }; 325 326 /* MDIO PHY reset types */ 327 enum xgbe_mdio_reset { 328 XGBE_MDIO_RESET_NONE = 0, 329 XGBE_MDIO_RESET_I2C_GPIO, 330 XGBE_MDIO_RESET_INT_GPIO, 331 XGBE_MDIO_RESET_MAX, 332 }; 333 334 /* Re-driver related definitions */ 335 enum xgbe_phy_redrv_if { 336 XGBE_PHY_REDRV_IF_MDIO = 0, 337 XGBE_PHY_REDRV_IF_I2C, 338 XGBE_PHY_REDRV_IF_MAX, 339 }; 340 341 enum xgbe_phy_redrv_model { 342 XGBE_PHY_REDRV_MODEL_4223 = 0, 343 XGBE_PHY_REDRV_MODEL_4227, 344 XGBE_PHY_REDRV_MODEL_MAX, 345 }; 346 347 enum xgbe_phy_redrv_mode { 348 XGBE_PHY_REDRV_MODE_CX = 5, 349 XGBE_PHY_REDRV_MODE_SR = 9, 350 }; 351 352 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 353 354 /* PHY related configuration information */ 355 struct xgbe_phy_data { 356 enum xgbe_port_mode port_mode; 357 358 unsigned int port_id; 359 360 unsigned int port_speeds; 361 362 enum xgbe_conn_type conn_type; 363 364 enum xgbe_mode cur_mode; 365 enum xgbe_mode start_mode; 366 367 unsigned int rrc_count; 368 369 unsigned int mdio_addr; 370 371 /* SFP Support */ 372 enum xgbe_sfp_comm sfp_comm; 373 unsigned int sfp_mux_address; 374 unsigned int sfp_mux_channel; 375 376 unsigned int sfp_gpio_address; 377 unsigned int sfp_gpio_mask; 378 unsigned int sfp_gpio_inputs; 379 unsigned int sfp_gpio_rx_los; 380 unsigned int sfp_gpio_tx_fault; 381 unsigned int sfp_gpio_mod_absent; 382 unsigned int sfp_gpio_rate_select; 383 384 unsigned int sfp_rx_los; 385 unsigned int sfp_tx_fault; 386 unsigned int sfp_mod_absent; 387 unsigned int sfp_changed; 388 unsigned int sfp_phy_avail; 389 unsigned int sfp_cable_len; 390 enum xgbe_sfp_base sfp_base; 391 enum xgbe_sfp_cable sfp_cable; 392 enum xgbe_sfp_speed sfp_speed; 393 struct xgbe_sfp_eeprom sfp_eeprom; 394 395 /* External PHY support */ 396 enum xgbe_mdio_mode phydev_mode; 397 uint32_t phy_id; 398 int phydev; 399 enum xgbe_mdio_reset mdio_reset; 400 unsigned int mdio_reset_addr; 401 unsigned int mdio_reset_gpio; 402 int sfp_phy_retries; 403 404 /* Re-driver support */ 405 unsigned int redrv; 406 unsigned int redrv_if; 407 unsigned int redrv_addr; 408 unsigned int redrv_lane; 409 unsigned int redrv_model; 410 411 /* KR AN support */ 412 unsigned int phy_cdr_notrack; 413 unsigned int phy_cdr_delay; 414 415 uint8_t port_sfp_inputs; 416 }; 417 418 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 419 static int xgbe_phy_reset(struct xgbe_prv_data *pdata); 420 static int axgbe_ifmedia_upd(struct ifnet *ifp); 421 static void axgbe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 422 423 static int 424 xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *i2c_op) 425 { 426 return (pdata->i2c_if.i2c_xfer(pdata, i2c_op)); 427 } 428 429 static int 430 xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 431 unsigned int val) 432 { 433 struct xgbe_phy_data *phy_data = pdata->phy_data; 434 struct xgbe_i2c_op i2c_op; 435 __be16 *redrv_val; 436 uint8_t redrv_data[5], csum; 437 unsigned int i, retry; 438 int ret; 439 440 /* High byte of register contains read/write indicator */ 441 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 442 redrv_data[1] = reg & 0xff; 443 redrv_val = (__be16 *)&redrv_data[2]; 444 *redrv_val = cpu_to_be16(val); 445 446 /* Calculate 1 byte checksum */ 447 csum = 0; 448 for (i = 0; i < 4; i++) { 449 csum += redrv_data[i]; 450 if (redrv_data[i] > csum) 451 csum++; 452 } 453 redrv_data[4] = ~csum; 454 455 retry = 1; 456 again1: 457 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 458 i2c_op.target = phy_data->redrv_addr; 459 i2c_op.len = sizeof(redrv_data); 460 i2c_op.buf = redrv_data; 461 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 462 if (ret) { 463 if ((ret == -EAGAIN) && retry--) 464 goto again1; 465 466 return (ret); 467 } 468 469 retry = 1; 470 again2: 471 i2c_op.cmd = XGBE_I2C_CMD_READ; 472 i2c_op.target = phy_data->redrv_addr; 473 i2c_op.len = 1; 474 i2c_op.buf = redrv_data; 475 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 476 if (ret) { 477 if ((ret == -EAGAIN) && retry--) 478 goto again2; 479 480 return (ret); 481 } 482 483 if (redrv_data[0] != 0xff) { 484 axgbe_error("Redriver write checksum error\n"); 485 ret = -EIO; 486 } 487 488 return (ret); 489 } 490 491 static int 492 xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, void *val, 493 unsigned int val_len) 494 { 495 struct xgbe_i2c_op i2c_op; 496 int retry, ret; 497 498 retry = 1; 499 again: 500 /* Write the specfied register */ 501 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 502 i2c_op.target = target; 503 i2c_op.len = val_len; 504 i2c_op.buf = val; 505 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 506 if ((ret == -EAGAIN) && retry--) 507 goto again; 508 509 return (ret); 510 } 511 512 static int 513 xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, void *reg, 514 unsigned int reg_len, void *val, unsigned int val_len) 515 { 516 struct xgbe_i2c_op i2c_op; 517 int retry, ret; 518 519 axgbe_printf(3, "%s: target 0x%x reg_len %d val_len %d\n", __func__, 520 target, reg_len, val_len); 521 retry = 1; 522 again1: 523 /* Set the specified register to read */ 524 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 525 i2c_op.target = target; 526 i2c_op.len = reg_len; 527 i2c_op.buf = reg; 528 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 529 axgbe_printf(3, "%s: ret1 %d retry %d\n", __func__, ret, retry); 530 if (ret) { 531 if ((ret == -EAGAIN) && retry--) 532 goto again1; 533 534 return (ret); 535 } 536 537 retry = 1; 538 again2: 539 /* Read the specfied register */ 540 i2c_op.cmd = XGBE_I2C_CMD_READ; 541 i2c_op.target = target; 542 i2c_op.len = val_len; 543 i2c_op.buf = val; 544 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 545 axgbe_printf(3, "%s: ret2 %d retry %d\n", __func__, ret, retry); 546 if ((ret == -EAGAIN) && retry--) 547 goto again2; 548 549 return (ret); 550 } 551 552 static int 553 xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 554 { 555 struct xgbe_phy_data *phy_data = pdata->phy_data; 556 struct xgbe_i2c_op i2c_op; 557 uint8_t mux_channel; 558 559 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 560 return (0); 561 562 /* Select no mux channels */ 563 mux_channel = 0; 564 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 565 i2c_op.target = phy_data->sfp_mux_address; 566 i2c_op.len = sizeof(mux_channel); 567 i2c_op.buf = &mux_channel; 568 569 return (xgbe_phy_i2c_xfer(pdata, &i2c_op)); 570 } 571 572 static int 573 xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 574 { 575 struct xgbe_phy_data *phy_data = pdata->phy_data; 576 struct xgbe_i2c_op i2c_op; 577 uint8_t mux_channel; 578 579 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 580 return (0); 581 582 /* Select desired mux channel */ 583 mux_channel = 1 << phy_data->sfp_mux_channel; 584 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 585 i2c_op.target = phy_data->sfp_mux_address; 586 i2c_op.len = sizeof(mux_channel); 587 i2c_op.buf = &mux_channel; 588 589 return (xgbe_phy_i2c_xfer(pdata, &i2c_op)); 590 } 591 592 static void 593 xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 594 { 595 mtx_unlock(&xgbe_phy_comm_lock); 596 } 597 598 static int 599 xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 600 { 601 struct xgbe_phy_data *phy_data = pdata->phy_data; 602 unsigned long timeout; 603 unsigned int mutex_id; 604 605 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 606 * the driver needs to take the software mutex and then the hardware 607 * mutexes before being able to use the busses. 608 */ 609 mtx_lock(&xgbe_phy_comm_lock); 610 611 /* Clear the mutexes */ 612 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 613 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 614 615 /* Mutex formats are the same for I2C and MDIO/GPIO */ 616 mutex_id = 0; 617 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 618 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 619 620 timeout = ticks + (5 * hz); 621 while (ticks < timeout) { 622 /* Must be all zeroes in order to obtain the mutex */ 623 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 624 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 625 DELAY(200); 626 continue; 627 } 628 629 /* Obtain the mutex */ 630 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 631 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 632 633 return (0); 634 } 635 636 mtx_unlock(&xgbe_phy_comm_lock); 637 638 axgbe_error("unable to obtain hardware mutexes\n"); 639 640 return (-ETIMEDOUT); 641 } 642 643 static int 644 xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, 645 uint16_t val) 646 { 647 struct xgbe_phy_data *phy_data = pdata->phy_data; 648 649 if (reg & MII_ADDR_C45) { 650 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 651 return (-ENOTSUP); 652 } else { 653 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 654 return (-ENOTSUP); 655 } 656 657 return (pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val)); 658 } 659 660 static int 661 xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, uint16_t val) 662 { 663 __be16 *mii_val; 664 uint8_t mii_data[3]; 665 int ret; 666 667 ret = xgbe_phy_sfp_get_mux(pdata); 668 if (ret) 669 return (ret); 670 671 mii_data[0] = reg & 0xff; 672 mii_val = (__be16 *)&mii_data[1]; 673 *mii_val = cpu_to_be16(val); 674 675 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 676 mii_data, sizeof(mii_data)); 677 678 xgbe_phy_sfp_put_mux(pdata); 679 680 return (ret); 681 } 682 683 int 684 xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, uint16_t val) 685 { 686 struct xgbe_phy_data *phy_data = pdata->phy_data; 687 int ret; 688 689 axgbe_printf(3, "%s: addr %d reg %d val %#x\n", __func__, addr, reg, val); 690 ret = xgbe_phy_get_comm_ownership(pdata); 691 if (ret) 692 return (ret); 693 694 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 695 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 696 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 697 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 698 else 699 ret = -ENOTSUP; 700 701 xgbe_phy_put_comm_ownership(pdata); 702 703 return (ret); 704 } 705 706 static int 707 xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, int reg) 708 { 709 struct xgbe_phy_data *phy_data = pdata->phy_data; 710 711 if (reg & MII_ADDR_C45) { 712 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 713 return (-ENOTSUP); 714 } else { 715 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 716 return (-ENOTSUP); 717 } 718 719 return (pdata->hw_if.read_ext_mii_regs(pdata, addr, reg)); 720 } 721 722 static int 723 xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 724 { 725 __be16 mii_val; 726 uint8_t mii_reg; 727 int ret; 728 729 ret = xgbe_phy_sfp_get_mux(pdata); 730 if (ret) 731 return (ret); 732 733 mii_reg = reg; 734 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 735 &mii_reg, sizeof(mii_reg), 736 &mii_val, sizeof(mii_val)); 737 if (!ret) 738 ret = be16_to_cpu(mii_val); 739 740 xgbe_phy_sfp_put_mux(pdata); 741 742 return (ret); 743 } 744 745 int 746 xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg) 747 { 748 struct xgbe_phy_data *phy_data = pdata->phy_data; 749 int ret; 750 751 axgbe_printf(3, "%s: addr %d reg %d\n", __func__, addr, reg); 752 ret = xgbe_phy_get_comm_ownership(pdata); 753 if (ret) 754 return (ret); 755 756 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 757 ret = xgbe_phy_i2c_mii_read(pdata, reg); 758 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 759 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 760 else 761 ret = -ENOTSUP; 762 763 xgbe_phy_put_comm_ownership(pdata); 764 765 return (ret); 766 } 767 768 static void 769 xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 770 { 771 struct xgbe_phy_data *phy_data = pdata->phy_data; 772 773 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 774 return; 775 776 XGBE_ZERO_SUP(&pdata->phy); 777 778 if (phy_data->sfp_mod_absent) { 779 pdata->phy.speed = SPEED_UNKNOWN; 780 pdata->phy.duplex = DUPLEX_UNKNOWN; 781 pdata->phy.autoneg = AUTONEG_ENABLE; 782 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 783 784 XGBE_SET_SUP(&pdata->phy, Autoneg); 785 XGBE_SET_SUP(&pdata->phy, Pause); 786 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 787 XGBE_SET_SUP(&pdata->phy, TP); 788 XGBE_SET_SUP(&pdata->phy, FIBRE); 789 790 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported); 791 792 return; 793 } 794 795 switch (phy_data->sfp_base) { 796 case XGBE_SFP_BASE_100_FX: 797 case XGBE_SFP_BASE_100_LX10: 798 case XGBE_SFP_BASE_100_BX: 799 pdata->phy.speed = SPEED_100; 800 pdata->phy.duplex = DUPLEX_FULL; 801 pdata->phy.autoneg = AUTONEG_DISABLE; 802 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 803 break; 804 case XGBE_SFP_BASE_1000_T: 805 case XGBE_SFP_BASE_1000_SX: 806 case XGBE_SFP_BASE_1000_LX: 807 case XGBE_SFP_BASE_1000_CX: 808 pdata->phy.speed = SPEED_UNKNOWN; 809 pdata->phy.duplex = DUPLEX_UNKNOWN; 810 pdata->phy.autoneg = AUTONEG_ENABLE; 811 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 812 XGBE_SET_SUP(&pdata->phy, Autoneg); 813 XGBE_SET_SUP(&pdata->phy, Pause); 814 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 815 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 816 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 817 XGBE_SET_SUP(&pdata->phy, 100baseT_Full); 818 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 819 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full); 820 } else { 821 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 822 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full); 823 } 824 break; 825 case XGBE_SFP_BASE_1000_BX: 826 case XGBE_SFP_BASE_PX: 827 pdata->phy.speed = SPEED_1000; 828 pdata->phy.duplex = DUPLEX_FULL; 829 pdata->phy.autoneg = AUTONEG_DISABLE; 830 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 831 break; 832 case XGBE_SFP_BASE_10000_SR: 833 case XGBE_SFP_BASE_10000_LR: 834 case XGBE_SFP_BASE_10000_LRM: 835 case XGBE_SFP_BASE_10000_ER: 836 case XGBE_SFP_BASE_10000_CR: 837 pdata->phy.speed = SPEED_10000; 838 pdata->phy.duplex = DUPLEX_FULL; 839 pdata->phy.autoneg = AUTONEG_DISABLE; 840 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 841 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 842 switch (phy_data->sfp_base) { 843 case XGBE_SFP_BASE_10000_SR: 844 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full); 845 break; 846 case XGBE_SFP_BASE_10000_LR: 847 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full); 848 break; 849 case XGBE_SFP_BASE_10000_LRM: 850 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full); 851 break; 852 case XGBE_SFP_BASE_10000_ER: 853 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full); 854 break; 855 case XGBE_SFP_BASE_10000_CR: 856 XGBE_SET_SUP(&pdata->phy, 10000baseCR_Full); 857 break; 858 default: 859 break; 860 } 861 } 862 break; 863 default: 864 pdata->phy.speed = SPEED_UNKNOWN; 865 pdata->phy.duplex = DUPLEX_UNKNOWN; 866 pdata->phy.autoneg = AUTONEG_DISABLE; 867 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 868 break; 869 } 870 871 switch (phy_data->sfp_base) { 872 case XGBE_SFP_BASE_1000_T: 873 case XGBE_SFP_BASE_1000_CX: 874 case XGBE_SFP_BASE_10000_CR: 875 XGBE_SET_SUP(&pdata->phy, TP); 876 break; 877 default: 878 XGBE_SET_SUP(&pdata->phy, FIBRE); 879 break; 880 } 881 882 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported); 883 884 axgbe_printf(1, "%s: link speed %d spf_base 0x%x pause_autoneg %d " 885 "advert 0x%x support 0x%x\n", __func__, pdata->phy.speed, 886 phy_data->sfp_base, pdata->phy.pause_autoneg, 887 pdata->phy.advertising, pdata->phy.supported); 888 } 889 890 static bool 891 xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 892 enum xgbe_sfp_speed sfp_speed) 893 { 894 uint8_t *sfp_base, min, max; 895 896 sfp_base = sfp_eeprom->base; 897 898 switch (sfp_speed) { 899 case XGBE_SFP_SPEED_100: 900 min = XGBE_SFP_BASE_BR_100M_MIN; 901 max = XGBE_SFP_BASE_BR_100M_MAX; 902 break; 903 case XGBE_SFP_SPEED_1000: 904 min = XGBE_SFP_BASE_BR_1GBE_MIN; 905 max = XGBE_SFP_BASE_BR_1GBE_MAX; 906 break; 907 case XGBE_SFP_SPEED_10000: 908 min = XGBE_SFP_BASE_BR_10GBE_MIN; 909 max = XGBE_SFP_BASE_BR_10GBE_MAX; 910 break; 911 case XGBE_SFP_SPEED_25000: 912 min = XGBE_SFP_BASE_BR_25GBE; 913 max = XGBE_SFP_BASE_BR_25GBE; 914 break; 915 default: 916 return (false); 917 } 918 919 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) && 920 (sfp_base[XGBE_SFP_BASE_BR] <= max)); 921 } 922 923 static void 924 xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 925 { 926 struct xgbe_phy_data *phy_data = pdata->phy_data; 927 928 if (phy_data->phydev) 929 phy_data->phydev = 0; 930 931 if (pdata->axgbe_miibus != NULL) { 932 device_delete_child(pdata->dev, pdata->axgbe_miibus); 933 pdata->axgbe_miibus = NULL; 934 } 935 } 936 937 static bool 938 xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 939 { 940 struct xgbe_phy_data *phy_data = pdata->phy_data; 941 unsigned int phy_id = phy_data->phy_id; 942 943 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 944 return (false); 945 946 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 947 return (false); 948 949 /* Enable Base-T AN */ 950 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0001); 951 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140); 952 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0000); 953 954 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 955 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1b, 0x9084); 956 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x09, 0x0e00); 957 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x8140); 958 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x04, 0x0d01); 959 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140); 960 961 axgbe_printf(3, "Finisar PHY quirk in place\n"); 962 963 return (true); 964 } 965 966 static bool 967 xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata) 968 { 969 struct xgbe_phy_data *phy_data = pdata->phy_data; 970 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 971 unsigned int phy_id = phy_data->phy_id; 972 int reg; 973 974 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 975 return (false); 976 977 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 978 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 979 return (false); 980 981 /* For Bel-Fuse, use the extra AN flag */ 982 pdata->an_again = 1; 983 984 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 985 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) 986 return (false); 987 988 if ((phy_id & 0xfffffff0) != 0x03625d10) 989 return (false); 990 991 /* Disable RGMII mode */ 992 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, 0x7007); 993 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18); 994 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080); 995 996 /* Enable fiber register bank */ 997 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00); 998 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c); 999 reg &= 0x03ff; 1000 reg &= ~0x0001; 1001 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 | 1002 reg | 0x0001); 1003 1004 /* Power down SerDes */ 1005 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00); 1006 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800); 1007 1008 /* Configure SGMII-to-Copper mode */ 1009 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00); 1010 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c); 1011 reg &= 0x03ff; 1012 reg &= ~0x0006; 1013 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 | 1014 reg | 0x0004); 1015 1016 /* Power up SerDes */ 1017 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00); 1018 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800); 1019 1020 /* Enable copper register bank */ 1021 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00); 1022 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c); 1023 reg &= 0x03ff; 1024 reg &= ~0x0001; 1025 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 | 1026 reg); 1027 1028 /* Power up SerDes */ 1029 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00); 1030 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800); 1031 1032 axgbe_printf(3, "BelFuse PHY quirk in place\n"); 1033 1034 return (true); 1035 } 1036 1037 static void 1038 xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 1039 { 1040 if (xgbe_phy_belfuse_phy_quirks(pdata)) 1041 return; 1042 1043 if (xgbe_phy_finisar_phy_quirks(pdata)) 1044 return; 1045 } 1046 1047 static int 1048 xgbe_get_phy_id(struct xgbe_prv_data *pdata) 1049 { 1050 struct xgbe_phy_data *phy_data = pdata->phy_data; 1051 uint32_t oui, model, phy_id1, phy_id2; 1052 int phy_reg; 1053 1054 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x02); 1055 if (phy_reg < 0) 1056 return (-EIO); 1057 1058 phy_id1 = (phy_reg & 0xffff); 1059 phy_data->phy_id = (phy_reg & 0xffff) << 16; 1060 1061 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x03); 1062 if (phy_reg < 0) 1063 return (-EIO); 1064 1065 phy_id2 = (phy_reg & 0xffff); 1066 phy_data->phy_id |= (phy_reg & 0xffff); 1067 1068 oui = MII_OUI(phy_id1, phy_id2); 1069 model = MII_MODEL(phy_id2); 1070 1071 axgbe_printf(2, "%s: phy_id1: 0x%x phy_id2: 0x%x oui: %#x model %#x\n", 1072 __func__, phy_id1, phy_id2, oui, model); 1073 1074 return (0); 1075 } 1076 1077 static int 1078 xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 1079 { 1080 struct xgbe_phy_data *phy_data = pdata->phy_data; 1081 int ret; 1082 1083 axgbe_printf(2, "%s: phydev %d phydev_mode %d sfp_phy_avail %d phy_id " 1084 "0x%08x\n", __func__, phy_data->phydev, phy_data->phydev_mode, 1085 phy_data->sfp_phy_avail, phy_data->phy_id); 1086 1087 /* If we already have a PHY, just return */ 1088 if (phy_data->phydev) { 1089 axgbe_printf(3, "%s: phy present already\n", __func__); 1090 return (0); 1091 } 1092 1093 /* Clear the extra AN flag */ 1094 pdata->an_again = 0; 1095 1096 /* Check for the use of an external PHY */ 1097 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) { 1098 axgbe_printf(3, "%s: phydev_mode %d\n", __func__, 1099 phy_data->phydev_mode); 1100 return (0); 1101 } 1102 1103 /* For SFP, only use an external PHY if available */ 1104 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1105 !phy_data->sfp_phy_avail) { 1106 axgbe_printf(3, "%s: port_mode %d avail %d\n", __func__, 1107 phy_data->port_mode, phy_data->sfp_phy_avail); 1108 return (0); 1109 } 1110 1111 /* Set the proper MDIO mode for the PHY */ 1112 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 1113 phy_data->phydev_mode); 1114 if (ret) { 1115 axgbe_error("mdio port/clause not compatible (%u/%u) ret %d\n", 1116 phy_data->mdio_addr, phy_data->phydev_mode, ret); 1117 return (ret); 1118 } 1119 1120 ret = xgbe_get_phy_id(pdata); 1121 if (ret) 1122 return (ret); 1123 axgbe_printf(2, "Get phy_id 0x%08x\n", phy_data->phy_id); 1124 1125 phy_data->phydev = 1; 1126 xgbe_phy_external_phy_quirks(pdata); 1127 1128 return (0); 1129 } 1130 1131 static void 1132 xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 1133 { 1134 struct xgbe_phy_data *phy_data = pdata->phy_data; 1135 int ret; 1136 1137 axgbe_printf(3, "%s: sfp_changed: 0x%x\n", __func__, 1138 phy_data->sfp_changed); 1139 if (!phy_data->sfp_phy_retries && !phy_data->sfp_changed) 1140 return; 1141 1142 phy_data->sfp_phy_avail = 0; 1143 1144 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 1145 return; 1146 1147 /* Check access to the PHY by reading CTRL1 */ 1148 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 1149 if (ret < 0) { 1150 phy_data->sfp_phy_retries++; 1151 if (phy_data->sfp_phy_retries >= XGBE_SFP_PHY_RETRY_MAX) 1152 phy_data->sfp_phy_retries = 0; 1153 axgbe_printf(1, "%s: ext phy fail %d. retrying.\n", __func__, ret); 1154 return; 1155 } 1156 1157 /* Successfully accessed the PHY */ 1158 phy_data->sfp_phy_avail = 1; 1159 axgbe_printf(3, "Successfully accessed External PHY\n"); 1160 1161 /* Attach external PHY to the miibus */ 1162 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev, 1163 (ifm_change_cb_t)axgbe_ifmedia_upd, 1164 (ifm_stat_cb_t)axgbe_ifmedia_sts, BMSR_DEFCAPMASK, 1165 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG); 1166 1167 if (ret) { 1168 axgbe_error("mii attach failed with err=(%d)\n", ret); 1169 } 1170 } 1171 1172 static bool 1173 xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) 1174 { 1175 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd; 1176 1177 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) 1178 return (false); 1179 1180 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) 1181 return (false); 1182 1183 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) 1184 return (true); 1185 1186 return (false); 1187 } 1188 1189 static bool 1190 xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) 1191 { 1192 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd; 1193 1194 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) 1195 return (false); 1196 1197 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) 1198 return (false); 1199 1200 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) 1201 return (true); 1202 1203 return (false); 1204 } 1205 1206 static bool 1207 xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) 1208 { 1209 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) 1210 return (false); 1211 1212 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) 1213 return (true); 1214 1215 return (false); 1216 } 1217 1218 static void 1219 xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1220 { 1221 struct xgbe_phy_data *phy_data = pdata->phy_data; 1222 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1223 uint8_t *sfp_base; 1224 uint16_t wavelen = 0; 1225 1226 sfp_base = sfp_eeprom->base; 1227 1228 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) { 1229 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_ID]); 1230 return; 1231 } 1232 1233 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) { 1234 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_EXT_ID]); 1235 return; 1236 } 1237 1238 /* Update transceiver signals (eeprom extd/options) */ 1239 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); 1240 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); 1241 1242 /* Assume ACTIVE cable unless told it is PASSIVE */ 1243 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1244 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1245 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1246 } else 1247 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1248 1249 wavelen = (sfp_base[XGBE_SFP_BASE_OSC] << 8) | sfp_base[XGBE_SFP_BASE_OSC + 1]; 1250 1251 /* 1252 * Determine the type of SFP. Certain 10G SFP+ modules read as 1253 * 1000BASE-CX. To prevent 10G DAC cables to be recognized as 1254 * 1G, we first check if it is a DAC and the bitrate is 10G. 1255 * If it's greater than 10G, we assume the DAC is capable 1256 * of multiple bitrates, set the MAC to 10G and hope for the best. 1257 */ 1258 if (((sfp_base[XGBE_SFP_BASE_CV] & XGBE_SFP_BASE_CV_CP) || 1259 (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE)) && 1260 (xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000) || 1261 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_25000))) 1262 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1263 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1264 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1265 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1266 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1267 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1268 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1269 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1270 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1271 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1272 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1273 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1274 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1275 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1276 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1277 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1278 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1279 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_100M_CC_LX10) 1280 phy_data->sfp_base = XGBE_SFP_BASE_100_LX10; 1281 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_100M_CC_FX) 1282 phy_data->sfp_base = XGBE_SFP_BASE_100_FX; 1283 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_CC_BX10) { 1284 /* BX10 can be either 100 or 1000 */ 1285 if (xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_100)) { 1286 phy_data->sfp_base = XGBE_SFP_BASE_100_BX; 1287 } else { 1288 /* default to 1000 */ 1289 phy_data->sfp_base = XGBE_SFP_BASE_1000_BX; 1290 } 1291 } else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_CC_PX) 1292 phy_data->sfp_base = XGBE_SFP_BASE_PX; 1293 else if (xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_1000) 1294 && (sfp_base[XGBE_SFP_BASE_SM_LEN_KM] >= XGBE_SFP_BASE_SM_LEN_KM_MIN 1295 || sfp_base[XGBE_SFP_BASE_SM_LEN_100M] >= XGBE_SFP_BASE_SM_LEN_100M_MIN) 1296 && wavelen >= XGBE_SFP_BASE_OSC_1310) 1297 phy_data->sfp_base = XGBE_SFP_BASE_1000_BX; 1298 else if (xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_100) 1299 && (sfp_base[XGBE_SFP_BASE_SM_LEN_KM] >= XGBE_SFP_BASE_SM_LEN_KM_MIN 1300 || sfp_base[XGBE_SFP_BASE_SM_LEN_100M] >= XGBE_SFP_BASE_SM_LEN_100M_MIN) 1301 && wavelen >= XGBE_SFP_BASE_OSC_1310) 1302 phy_data->sfp_base = XGBE_SFP_BASE_100_BX; 1303 1304 switch (phy_data->sfp_base) { 1305 case XGBE_SFP_BASE_100_FX: 1306 case XGBE_SFP_BASE_100_LX10: 1307 case XGBE_SFP_BASE_100_BX: 1308 phy_data->sfp_speed = XGBE_SFP_SPEED_100; 1309 case XGBE_SFP_BASE_1000_T: 1310 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1311 break; 1312 case XGBE_SFP_BASE_PX: 1313 case XGBE_SFP_BASE_1000_SX: 1314 case XGBE_SFP_BASE_1000_LX: 1315 case XGBE_SFP_BASE_1000_CX: 1316 case XGBE_SFP_BASE_1000_BX: 1317 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1318 break; 1319 case XGBE_SFP_BASE_10000_SR: 1320 case XGBE_SFP_BASE_10000_LR: 1321 case XGBE_SFP_BASE_10000_LRM: 1322 case XGBE_SFP_BASE_10000_ER: 1323 case XGBE_SFP_BASE_10000_CR: 1324 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1325 break; 1326 default: 1327 break; 1328 } 1329 axgbe_printf(3, "%s: sfp_base: 0x%x sfp_speed: 0x%x sfp_cable: 0x%x " 1330 "rx_los 0x%x tx_fault 0x%x\n", __func__, phy_data->sfp_base, 1331 phy_data->sfp_speed, phy_data->sfp_cable, phy_data->sfp_rx_los, 1332 phy_data->sfp_tx_fault); 1333 } 1334 1335 static void 1336 xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1337 struct xgbe_sfp_eeprom *sfp_eeprom) 1338 { 1339 struct xgbe_sfp_ascii sfp_ascii; 1340 char *sfp_data = (char *)&sfp_ascii; 1341 1342 axgbe_printf(0, "SFP detected:\n"); 1343 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1344 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1345 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1346 axgbe_printf(0, " vendor: %s\n", 1347 sfp_data); 1348 1349 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1350 XGBE_SFP_BASE_VENDOR_PN_LEN); 1351 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1352 axgbe_printf(0, " part number: %s\n", 1353 sfp_data); 1354 1355 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1356 XGBE_SFP_BASE_VENDOR_REV_LEN); 1357 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1358 axgbe_printf(0, " revision level: %s\n", 1359 sfp_data); 1360 1361 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1362 XGBE_SFP_BASE_VENDOR_SN_LEN); 1363 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1364 axgbe_printf(0, " serial number: %s\n", 1365 sfp_data); 1366 } 1367 1368 static bool 1369 xgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, unsigned int len) 1370 { 1371 uint8_t cc; 1372 1373 for (cc = 0; len; buf++, len--) 1374 cc += *buf; 1375 1376 return ((cc == cc_in) ? true : false); 1377 } 1378 1379 static void 1380 dump_sfp_eeprom(struct xgbe_prv_data *pdata, uint8_t *sfp_base) 1381 { 1382 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_ID] : 0x%04x\n", 1383 sfp_base[XGBE_SFP_BASE_ID]); 1384 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_EXT_ID] : 0x%04x\n", 1385 sfp_base[XGBE_SFP_BASE_EXT_ID]); 1386 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_CABLE] : 0x%04x\n", 1387 sfp_base[XGBE_SFP_BASE_CABLE]); 1388 } 1389 1390 static int 1391 xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1392 { 1393 struct xgbe_phy_data *phy_data = pdata->phy_data; 1394 struct xgbe_sfp_eeprom sfp_eeprom, *eeprom; 1395 uint8_t eeprom_addr, *base; 1396 int ret; 1397 1398 ret = xgbe_phy_sfp_get_mux(pdata); 1399 if (ret) { 1400 axgbe_error("I2C error setting SFP MUX\n"); 1401 return (ret); 1402 } 1403 1404 /* Read the SFP serial ID eeprom */ 1405 eeprom_addr = 0; 1406 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1407 &eeprom_addr, sizeof(eeprom_addr), 1408 &sfp_eeprom, sizeof(sfp_eeprom)); 1409 1410 if (ret) { 1411 axgbe_error("I2C error reading SFP EEPROM\n"); 1412 goto put; 1413 } 1414 1415 eeprom = &sfp_eeprom; 1416 base = eeprom->base; 1417 dump_sfp_eeprom(pdata, base); 1418 1419 /* Validate the contents read */ 1420 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1421 sfp_eeprom.base, sizeof(sfp_eeprom.base) - 1)) { 1422 axgbe_error("verify eeprom base failed\n"); 1423 ret = -EINVAL; 1424 goto put; 1425 } 1426 1427 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1428 sfp_eeprom.extd, sizeof(sfp_eeprom.extd) - 1)) { 1429 axgbe_error("verify eeprom extd failed\n"); 1430 ret = -EINVAL; 1431 goto put; 1432 } 1433 1434 /* Check for an added or changed SFP */ 1435 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1436 phy_data->sfp_changed = 1; 1437 1438 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1439 1440 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1441 1442 xgbe_phy_free_phy_device(pdata); 1443 } else 1444 phy_data->sfp_changed = 0; 1445 1446 put: 1447 xgbe_phy_sfp_put_mux(pdata); 1448 1449 return (ret); 1450 } 1451 1452 static void 1453 xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1454 { 1455 struct xgbe_phy_data *phy_data = pdata->phy_data; 1456 uint8_t gpio_reg, gpio_ports[2]; 1457 int ret, prev_sfp_inputs = phy_data->port_sfp_inputs; 1458 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id); 1459 1460 /* Read the input port registers */ 1461 axgbe_printf(3, "%s: befor sfp_mod:%d sfp_gpio_address:0x%x\n", 1462 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_address); 1463 1464 gpio_reg = 0; 1465 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, &gpio_reg, 1466 sizeof(gpio_reg), gpio_ports, sizeof(gpio_ports)); 1467 if (ret) { 1468 axgbe_error("%s: I2C error reading SFP GPIO addr:0x%x\n", 1469 __func__, phy_data->sfp_gpio_address); 1470 return; 1471 } 1472 1473 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; 1474 phy_data->port_sfp_inputs = (phy_data->sfp_gpio_inputs >> shift) & 0x0F; 1475 1476 if (prev_sfp_inputs != phy_data->port_sfp_inputs) 1477 axgbe_printf(0, "%s: port_sfp_inputs: 0x%0x\n", __func__, 1478 phy_data->port_sfp_inputs); 1479 1480 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); 1481 1482 axgbe_printf(3, "%s: after sfp_mod:%d sfp_gpio_inputs:0x%x\n", 1483 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_inputs); 1484 } 1485 1486 static void 1487 xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1488 { 1489 struct xgbe_phy_data *phy_data = pdata->phy_data; 1490 1491 xgbe_phy_free_phy_device(pdata); 1492 1493 phy_data->sfp_mod_absent = 1; 1494 phy_data->sfp_phy_avail = 0; 1495 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1496 } 1497 1498 static void 1499 xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1500 { 1501 phy_data->sfp_rx_los = 0; 1502 phy_data->sfp_tx_fault = 0; 1503 phy_data->sfp_mod_absent = 1; 1504 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1505 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1506 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1507 } 1508 1509 static void 1510 xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1511 { 1512 struct xgbe_phy_data *phy_data = pdata->phy_data; 1513 int ret, prev_sfp_state = phy_data->sfp_mod_absent; 1514 1515 /* Reset the SFP signals and info */ 1516 xgbe_phy_sfp_reset(phy_data); 1517 1518 ret = xgbe_phy_get_comm_ownership(pdata); 1519 if (ret) 1520 return; 1521 1522 /* Read the SFP signals and check for module presence */ 1523 xgbe_phy_sfp_signals(pdata); 1524 if (phy_data->sfp_mod_absent) { 1525 if (prev_sfp_state != phy_data->sfp_mod_absent) 1526 axgbe_error("%s: mod absent\n", __func__); 1527 xgbe_phy_sfp_mod_absent(pdata); 1528 goto put; 1529 } 1530 1531 ret = xgbe_phy_sfp_read_eeprom(pdata); 1532 if (ret) { 1533 /* Treat any error as if there isn't an SFP plugged in */ 1534 axgbe_error("%s: eeprom read failed\n", __func__); 1535 xgbe_phy_sfp_reset(phy_data); 1536 xgbe_phy_sfp_mod_absent(pdata); 1537 goto put; 1538 } 1539 1540 xgbe_phy_sfp_parse_eeprom(pdata); 1541 1542 xgbe_phy_sfp_external_phy(pdata); 1543 1544 put: 1545 xgbe_phy_sfp_phy_settings(pdata); 1546 1547 axgbe_printf(3, "%s: phy speed: 0x%x duplex: 0x%x autoneg: 0x%x " 1548 "pause_autoneg: 0x%x\n", __func__, pdata->phy.speed, 1549 pdata->phy.duplex, pdata->phy.autoneg, pdata->phy.pause_autoneg); 1550 1551 xgbe_phy_put_comm_ownership(pdata); 1552 } 1553 1554 static int 1555 xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata) 1556 { 1557 struct xgbe_phy_data *phy_data = pdata->phy_data; 1558 uint8_t eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX]; 1559 struct xgbe_sfp_eeprom *sfp_eeprom; 1560 int ret; 1561 1562 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 1563 ret = -ENXIO; 1564 goto done; 1565 } 1566 1567 if (phy_data->sfp_mod_absent) { 1568 ret = -EIO; 1569 goto done; 1570 } 1571 1572 ret = xgbe_phy_get_comm_ownership(pdata); 1573 if (ret) { 1574 ret = -EIO; 1575 goto done; 1576 } 1577 1578 ret = xgbe_phy_sfp_get_mux(pdata); 1579 if (ret) { 1580 axgbe_error("I2C error setting SFP MUX\n"); 1581 ret = -EIO; 1582 goto put_own; 1583 } 1584 1585 /* Read the SFP serial ID eeprom */ 1586 eeprom_addr = 0; 1587 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1588 &eeprom_addr, sizeof(eeprom_addr), 1589 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN); 1590 if (ret) { 1591 axgbe_error("I2C error reading SFP EEPROM\n"); 1592 ret = -EIO; 1593 goto put_mux; 1594 } 1595 1596 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data; 1597 1598 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) { 1599 /* Read the SFP diagnostic eeprom */ 1600 eeprom_addr = 0; 1601 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS, 1602 &eeprom_addr, sizeof(eeprom_addr), 1603 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN, 1604 XGBE_SFP_EEPROM_DIAG_LEN); 1605 if (ret) { 1606 axgbe_error("I2C error reading SFP DIAGS\n"); 1607 ret = -EIO; 1608 goto put_mux; 1609 } 1610 } 1611 1612 put_mux: 1613 xgbe_phy_sfp_put_mux(pdata); 1614 1615 put_own: 1616 xgbe_phy_put_comm_ownership(pdata); 1617 1618 done: 1619 return (ret); 1620 } 1621 1622 static int 1623 xgbe_phy_module_info(struct xgbe_prv_data *pdata) 1624 { 1625 struct xgbe_phy_data *phy_data = pdata->phy_data; 1626 1627 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 1628 return (-ENXIO); 1629 1630 if (phy_data->sfp_mod_absent) 1631 return (-EIO); 1632 1633 return (0); 1634 } 1635 1636 static void 1637 xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1638 { 1639 struct xgbe_phy_data *phy_data = pdata->phy_data; 1640 1641 pdata->phy.tx_pause = 0; 1642 pdata->phy.rx_pause = 0; 1643 1644 if (!phy_data->phydev) 1645 return; 1646 1647 if (pdata->phy.pause) 1648 XGBE_SET_LP_ADV(&pdata->phy, Pause); 1649 1650 if (pdata->phy.asym_pause) 1651 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause); 1652 1653 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, 1654 pdata->phy.tx_pause, pdata->phy.rx_pause); 1655 } 1656 1657 static enum xgbe_mode 1658 xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1659 { 1660 enum xgbe_mode mode; 1661 1662 XGBE_SET_LP_ADV(&pdata->phy, Autoneg); 1663 XGBE_SET_LP_ADV(&pdata->phy, TP); 1664 1665 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__, 1666 pdata->phy.pause_autoneg); 1667 1668 /* Use external PHY to determine flow control */ 1669 if (pdata->phy.pause_autoneg) 1670 xgbe_phy_phydev_flowctrl(pdata); 1671 1672 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1673 case XGBE_SGMII_AN_LINK_SPEED_100: 1674 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1675 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Full); 1676 mode = XGBE_MODE_SGMII_100; 1677 } else { 1678 /* Half-duplex not supported */ 1679 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Half); 1680 mode = XGBE_MODE_UNKNOWN; 1681 } 1682 break; 1683 case XGBE_SGMII_AN_LINK_SPEED_1000: 1684 default: 1685 /* Default to 1000 */ 1686 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1687 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Full); 1688 mode = XGBE_MODE_SGMII_1000; 1689 } else { 1690 /* Half-duplex not supported */ 1691 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Half); 1692 mode = XGBE_MODE_SGMII_1000; 1693 } 1694 break; 1695 } 1696 1697 return (mode); 1698 } 1699 1700 static enum xgbe_mode 1701 xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1702 { 1703 enum xgbe_mode mode; 1704 unsigned int ad_reg, lp_reg; 1705 1706 XGBE_SET_LP_ADV(&pdata->phy, Autoneg); 1707 XGBE_SET_LP_ADV(&pdata->phy, FIBRE); 1708 1709 /* Compare Advertisement and Link Partner register */ 1710 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1711 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1712 if (lp_reg & 0x100) 1713 XGBE_SET_LP_ADV(&pdata->phy, Pause); 1714 if (lp_reg & 0x80) 1715 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause); 1716 1717 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n", 1718 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg); 1719 1720 if (pdata->phy.pause_autoneg) { 1721 /* Set flow control based on auto-negotiation result */ 1722 pdata->phy.tx_pause = 0; 1723 pdata->phy.rx_pause = 0; 1724 1725 if (ad_reg & lp_reg & 0x100) { 1726 pdata->phy.tx_pause = 1; 1727 pdata->phy.rx_pause = 1; 1728 } else if (ad_reg & lp_reg & 0x80) { 1729 if (ad_reg & 0x100) 1730 pdata->phy.rx_pause = 1; 1731 else if (lp_reg & 0x100) 1732 pdata->phy.tx_pause = 1; 1733 } 1734 } 1735 1736 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause, 1737 pdata->phy.rx_pause); 1738 1739 if (lp_reg & 0x20) 1740 XGBE_SET_LP_ADV(&pdata->phy, 1000baseX_Full); 1741 1742 /* Half duplex is not supported */ 1743 ad_reg &= lp_reg; 1744 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1745 1746 return (mode); 1747 } 1748 1749 static enum xgbe_mode 1750 xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1751 { 1752 struct xgbe_phy_data *phy_data = pdata->phy_data; 1753 enum xgbe_mode mode; 1754 unsigned int ad_reg, lp_reg; 1755 1756 XGBE_SET_LP_ADV(&pdata->phy, Autoneg); 1757 XGBE_SET_LP_ADV(&pdata->phy, Backplane); 1758 1759 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__, 1760 pdata->phy.pause_autoneg); 1761 1762 /* Use external PHY to determine flow control */ 1763 if (pdata->phy.pause_autoneg) 1764 xgbe_phy_phydev_flowctrl(pdata); 1765 1766 /* Compare Advertisement and Link Partner register 2 */ 1767 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1768 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1769 if (lp_reg & 0x80) 1770 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full); 1771 if (lp_reg & 0x20) 1772 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full); 1773 1774 ad_reg &= lp_reg; 1775 if (ad_reg & 0x80) { 1776 switch (phy_data->port_mode) { 1777 case XGBE_PORT_MODE_BACKPLANE: 1778 mode = XGBE_MODE_KR; 1779 break; 1780 default: 1781 mode = XGBE_MODE_SFI; 1782 break; 1783 } 1784 } else if (ad_reg & 0x20) { 1785 switch (phy_data->port_mode) { 1786 case XGBE_PORT_MODE_BACKPLANE: 1787 mode = XGBE_MODE_KX_1000; 1788 break; 1789 case XGBE_PORT_MODE_1000BASE_X: 1790 mode = XGBE_MODE_X; 1791 break; 1792 case XGBE_PORT_MODE_SFP: 1793 switch (phy_data->sfp_base) { 1794 case XGBE_SFP_BASE_1000_T: 1795 if ((phy_data->phydev) && 1796 (pdata->phy.speed == SPEED_100)) 1797 mode = XGBE_MODE_SGMII_100; 1798 else 1799 mode = XGBE_MODE_SGMII_1000; 1800 break; 1801 case XGBE_SFP_BASE_1000_SX: 1802 case XGBE_SFP_BASE_1000_LX: 1803 case XGBE_SFP_BASE_1000_CX: 1804 default: 1805 mode = XGBE_MODE_X; 1806 break; 1807 } 1808 break; 1809 default: 1810 if ((phy_data->phydev) && 1811 (pdata->phy.speed == SPEED_100)) 1812 mode = XGBE_MODE_SGMII_100; 1813 else 1814 mode = XGBE_MODE_SGMII_1000; 1815 break; 1816 } 1817 } else { 1818 mode = XGBE_MODE_UNKNOWN; 1819 } 1820 1821 /* Compare Advertisement and Link Partner register 3 */ 1822 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1823 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1824 if (lp_reg & 0xc000) 1825 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC); 1826 1827 return (mode); 1828 } 1829 1830 static enum xgbe_mode 1831 xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1832 { 1833 enum xgbe_mode mode; 1834 unsigned int ad_reg, lp_reg; 1835 1836 XGBE_SET_LP_ADV(&pdata->phy, Autoneg); 1837 XGBE_SET_LP_ADV(&pdata->phy, Backplane); 1838 1839 /* Compare Advertisement and Link Partner register 1 */ 1840 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1841 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1842 if (lp_reg & 0x400) 1843 XGBE_SET_LP_ADV(&pdata->phy, Pause); 1844 if (lp_reg & 0x800) 1845 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause); 1846 1847 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n", 1848 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg); 1849 1850 if (pdata->phy.pause_autoneg) { 1851 /* Set flow control based on auto-negotiation result */ 1852 pdata->phy.tx_pause = 0; 1853 pdata->phy.rx_pause = 0; 1854 1855 if (ad_reg & lp_reg & 0x400) { 1856 pdata->phy.tx_pause = 1; 1857 pdata->phy.rx_pause = 1; 1858 } else if (ad_reg & lp_reg & 0x800) { 1859 if (ad_reg & 0x400) 1860 pdata->phy.rx_pause = 1; 1861 else if (lp_reg & 0x400) 1862 pdata->phy.tx_pause = 1; 1863 } 1864 } 1865 1866 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause, 1867 pdata->phy.rx_pause); 1868 1869 /* Compare Advertisement and Link Partner register 2 */ 1870 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1871 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1872 if (lp_reg & 0x80) 1873 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full); 1874 if (lp_reg & 0x20) 1875 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full); 1876 1877 ad_reg &= lp_reg; 1878 if (ad_reg & 0x80) 1879 mode = XGBE_MODE_KR; 1880 else if (ad_reg & 0x20) 1881 mode = XGBE_MODE_KX_1000; 1882 else 1883 mode = XGBE_MODE_UNKNOWN; 1884 1885 /* Compare Advertisement and Link Partner register 3 */ 1886 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1887 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1888 if (lp_reg & 0xc000) 1889 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC); 1890 1891 return (mode); 1892 } 1893 1894 static enum xgbe_mode 1895 xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1896 { 1897 switch (pdata->an_mode) { 1898 case XGBE_AN_MODE_CL73: 1899 return (xgbe_phy_an73_outcome(pdata)); 1900 case XGBE_AN_MODE_CL73_REDRV: 1901 return (xgbe_phy_an73_redrv_outcome(pdata)); 1902 case XGBE_AN_MODE_CL37: 1903 return (xgbe_phy_an37_outcome(pdata)); 1904 case XGBE_AN_MODE_CL37_SGMII: 1905 return (xgbe_phy_an37_sgmii_outcome(pdata)); 1906 default: 1907 return (XGBE_MODE_UNKNOWN); 1908 } 1909 } 1910 1911 static void 1912 xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy) 1913 { 1914 struct xgbe_phy_data *phy_data = pdata->phy_data; 1915 1916 XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising); 1917 1918 /* Without a re-driver, just return current advertising */ 1919 if (!phy_data->redrv) 1920 return; 1921 1922 /* With the KR re-driver we need to advertise a single speed */ 1923 XGBE_CLR_ADV(dphy, 1000baseKX_Full); 1924 XGBE_CLR_ADV(dphy, 10000baseKR_Full); 1925 1926 /* Advertise FEC support is present */ 1927 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 1928 XGBE_SET_ADV(dphy, 10000baseR_FEC); 1929 1930 switch (phy_data->port_mode) { 1931 case XGBE_PORT_MODE_BACKPLANE: 1932 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1933 break; 1934 case XGBE_PORT_MODE_BACKPLANE_2500: 1935 XGBE_SET_ADV(dphy, 1000baseKX_Full); 1936 break; 1937 case XGBE_PORT_MODE_1000BASE_T: 1938 case XGBE_PORT_MODE_1000BASE_X: 1939 case XGBE_PORT_MODE_NBASE_T: 1940 XGBE_SET_ADV(dphy, 1000baseKX_Full); 1941 break; 1942 case XGBE_PORT_MODE_10GBASE_T: 1943 if ((phy_data->phydev) && 1944 (pdata->phy.speed == SPEED_10000)) 1945 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1946 else 1947 XGBE_SET_ADV(dphy, 1000baseKX_Full); 1948 break; 1949 case XGBE_PORT_MODE_10GBASE_R: 1950 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1951 break; 1952 case XGBE_PORT_MODE_SFP: 1953 switch (phy_data->sfp_base) { 1954 case XGBE_SFP_BASE_1000_T: 1955 case XGBE_SFP_BASE_1000_SX: 1956 case XGBE_SFP_BASE_1000_LX: 1957 case XGBE_SFP_BASE_1000_CX: 1958 XGBE_SET_ADV(dphy, 1000baseKX_Full); 1959 break; 1960 default: 1961 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1962 break; 1963 } 1964 break; 1965 default: 1966 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1967 break; 1968 } 1969 } 1970 1971 static int 1972 xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1973 { 1974 struct xgbe_phy_data *phy_data = pdata->phy_data; 1975 int ret; 1976 1977 ret = xgbe_phy_find_phy_device(pdata); 1978 if (ret) 1979 return (ret); 1980 1981 axgbe_printf(2, "%s: find_phy_device return %s.\n", __func__, 1982 ret ? "Failure" : "Success"); 1983 1984 if (!phy_data->phydev) 1985 return (0); 1986 1987 return (ret); 1988 } 1989 1990 static enum xgbe_an_mode 1991 xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1992 { 1993 switch (phy_data->sfp_base) { 1994 case XGBE_SFP_BASE_1000_T: 1995 return (XGBE_AN_MODE_CL37_SGMII); 1996 case XGBE_SFP_BASE_1000_SX: 1997 case XGBE_SFP_BASE_1000_LX: 1998 case XGBE_SFP_BASE_1000_CX: 1999 return (XGBE_AN_MODE_CL37); 2000 default: 2001 return (XGBE_AN_MODE_NONE); 2002 } 2003 } 2004 2005 static enum xgbe_an_mode 2006 xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 2007 { 2008 struct xgbe_phy_data *phy_data = pdata->phy_data; 2009 2010 /* A KR re-driver will always require CL73 AN */ 2011 if (phy_data->redrv) 2012 return (XGBE_AN_MODE_CL73_REDRV); 2013 2014 switch (phy_data->port_mode) { 2015 case XGBE_PORT_MODE_BACKPLANE: 2016 return (XGBE_AN_MODE_CL73); 2017 case XGBE_PORT_MODE_BACKPLANE_2500: 2018 return (XGBE_AN_MODE_NONE); 2019 case XGBE_PORT_MODE_1000BASE_T: 2020 return (XGBE_AN_MODE_CL37_SGMII); 2021 case XGBE_PORT_MODE_1000BASE_X: 2022 return (XGBE_AN_MODE_CL37); 2023 case XGBE_PORT_MODE_NBASE_T: 2024 return (XGBE_AN_MODE_CL37_SGMII); 2025 case XGBE_PORT_MODE_10GBASE_T: 2026 return (XGBE_AN_MODE_CL73); 2027 case XGBE_PORT_MODE_10GBASE_R: 2028 return (XGBE_AN_MODE_NONE); 2029 case XGBE_PORT_MODE_SFP: 2030 return (xgbe_phy_an_sfp_mode(phy_data)); 2031 default: 2032 return (XGBE_AN_MODE_NONE); 2033 } 2034 } 2035 2036 static int 2037 xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 2038 enum xgbe_phy_redrv_mode mode) 2039 { 2040 struct xgbe_phy_data *phy_data = pdata->phy_data; 2041 uint16_t redrv_reg, redrv_val; 2042 2043 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 2044 redrv_val = (uint16_t)mode; 2045 2046 return (pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 2047 redrv_reg, redrv_val)); 2048 } 2049 2050 static int 2051 xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 2052 enum xgbe_phy_redrv_mode mode) 2053 { 2054 struct xgbe_phy_data *phy_data = pdata->phy_data; 2055 unsigned int redrv_reg; 2056 int ret; 2057 2058 /* Calculate the register to write */ 2059 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 2060 2061 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 2062 2063 return (ret); 2064 } 2065 2066 static void 2067 xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 2068 { 2069 struct xgbe_phy_data *phy_data = pdata->phy_data; 2070 enum xgbe_phy_redrv_mode mode; 2071 int ret; 2072 2073 if (!phy_data->redrv) 2074 return; 2075 2076 mode = XGBE_PHY_REDRV_MODE_CX; 2077 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 2078 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 2079 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 2080 mode = XGBE_PHY_REDRV_MODE_SR; 2081 2082 ret = xgbe_phy_get_comm_ownership(pdata); 2083 if (ret) 2084 return; 2085 2086 axgbe_printf(2, "%s: redrv_if set: %d\n", __func__, phy_data->redrv_if); 2087 if (phy_data->redrv_if) 2088 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 2089 else 2090 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 2091 2092 xgbe_phy_put_comm_ownership(pdata); 2093 } 2094 2095 static void 2096 xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable) 2097 { 2098 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 2099 XGBE_PMA_PLL_CTRL_MASK, 2100 enable ? XGBE_PMA_PLL_CTRL_ENABLE 2101 : XGBE_PMA_PLL_CTRL_DISABLE); 2102 DELAY(200); 2103 } 2104 2105 static void 2106 xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, unsigned int cmd, 2107 unsigned int sub_cmd) 2108 { 2109 unsigned int s0 = 0; 2110 unsigned int wait; 2111 2112 xgbe_phy_pll_ctrl(pdata, false); 2113 2114 /* Log if a previous command did not complete */ 2115 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 2116 axgbe_error("firmware mailbox not ready for command\n"); 2117 2118 /* Construct the command */ 2119 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 2120 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 2121 2122 /* Issue the command */ 2123 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 2124 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 2125 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 2126 2127 /* Wait for command to complete */ 2128 wait = XGBE_RATECHANGE_COUNT; 2129 while (wait--) { 2130 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 2131 axgbe_printf(3, "%s: Rate change done\n", __func__); 2132 goto reenable_pll; 2133 } 2134 2135 DELAY(2000); 2136 } 2137 2138 axgbe_printf(3, "firmware mailbox command did not complete\n"); 2139 2140 reenable_pll: 2141 xgbe_phy_pll_ctrl(pdata, true); 2142 } 2143 2144 static void 2145 xgbe_phy_rrc(struct xgbe_prv_data *pdata) 2146 { 2147 /* Receiver Reset Cycle */ 2148 xgbe_phy_perform_ratechange(pdata, 5, 0); 2149 2150 axgbe_printf(3, "receiver reset complete\n"); 2151 } 2152 2153 static void 2154 xgbe_phy_power_off(struct xgbe_prv_data *pdata) 2155 { 2156 struct xgbe_phy_data *phy_data = pdata->phy_data; 2157 2158 /* Power off */ 2159 xgbe_phy_perform_ratechange(pdata, 0, 0); 2160 2161 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2162 2163 axgbe_printf(3, "phy powered off\n"); 2164 } 2165 2166 static void 2167 xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 2168 { 2169 struct xgbe_phy_data *phy_data = pdata->phy_data; 2170 2171 xgbe_phy_set_redrv_mode(pdata); 2172 2173 /* 10G/SFI */ 2174 axgbe_printf(3, "%s: cable %d len %d\n", __func__, phy_data->sfp_cable, 2175 phy_data->sfp_cable_len); 2176 2177 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) 2178 xgbe_phy_perform_ratechange(pdata, 3, 0); 2179 else { 2180 if (phy_data->sfp_cable_len <= 1) 2181 xgbe_phy_perform_ratechange(pdata, 3, 1); 2182 else if (phy_data->sfp_cable_len <= 3) 2183 xgbe_phy_perform_ratechange(pdata, 3, 2); 2184 else 2185 xgbe_phy_perform_ratechange(pdata, 3, 3); 2186 } 2187 2188 phy_data->cur_mode = XGBE_MODE_SFI; 2189 2190 axgbe_printf(3, "10GbE SFI mode set\n"); 2191 } 2192 2193 static void 2194 xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 2195 { 2196 struct xgbe_phy_data *phy_data = pdata->phy_data; 2197 2198 xgbe_phy_set_redrv_mode(pdata); 2199 2200 /* 1G/X */ 2201 xgbe_phy_perform_ratechange(pdata, 1, 3); 2202 2203 phy_data->cur_mode = XGBE_MODE_X; 2204 2205 axgbe_printf(3, "1GbE X mode set\n"); 2206 } 2207 2208 static void 2209 xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 2210 { 2211 struct xgbe_phy_data *phy_data = pdata->phy_data; 2212 2213 xgbe_phy_set_redrv_mode(pdata); 2214 2215 /* 1G/SGMII */ 2216 xgbe_phy_perform_ratechange(pdata, 1, 2); 2217 2218 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 2219 2220 axgbe_printf(2, "1GbE SGMII mode set\n"); 2221 } 2222 2223 static void 2224 xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 2225 { 2226 struct xgbe_phy_data *phy_data = pdata->phy_data; 2227 2228 xgbe_phy_set_redrv_mode(pdata); 2229 2230 /* 100M/SGMII */ 2231 xgbe_phy_perform_ratechange(pdata, 1, 1); 2232 2233 phy_data->cur_mode = XGBE_MODE_SGMII_100; 2234 2235 axgbe_printf(3, "100MbE SGMII mode set\n"); 2236 } 2237 2238 static void 2239 xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 2240 { 2241 struct xgbe_phy_data *phy_data = pdata->phy_data; 2242 2243 xgbe_phy_set_redrv_mode(pdata); 2244 2245 /* 10G/KR */ 2246 xgbe_phy_perform_ratechange(pdata, 4, 0); 2247 2248 phy_data->cur_mode = XGBE_MODE_KR; 2249 2250 axgbe_printf(3, "10GbE KR mode set\n"); 2251 } 2252 2253 static void 2254 xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 2255 { 2256 struct xgbe_phy_data *phy_data = pdata->phy_data; 2257 2258 xgbe_phy_set_redrv_mode(pdata); 2259 2260 /* 2.5G/KX */ 2261 xgbe_phy_perform_ratechange(pdata, 2, 0); 2262 2263 phy_data->cur_mode = XGBE_MODE_KX_2500; 2264 2265 axgbe_printf(3, "2.5GbE KX mode set\n"); 2266 } 2267 2268 static void 2269 xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 2270 { 2271 struct xgbe_phy_data *phy_data = pdata->phy_data; 2272 2273 xgbe_phy_set_redrv_mode(pdata); 2274 2275 /* 1G/KX */ 2276 xgbe_phy_perform_ratechange(pdata, 1, 3); 2277 2278 phy_data->cur_mode = XGBE_MODE_KX_1000; 2279 2280 axgbe_printf(3, "1GbE KX mode set\n"); 2281 } 2282 2283 static enum xgbe_mode 2284 xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 2285 { 2286 struct xgbe_phy_data *phy_data = pdata->phy_data; 2287 2288 return (phy_data->cur_mode); 2289 } 2290 2291 static enum xgbe_mode 2292 xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 2293 { 2294 struct xgbe_phy_data *phy_data = pdata->phy_data; 2295 2296 /* No switching if not 10GBase-T */ 2297 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 2298 return (xgbe_phy_cur_mode(pdata)); 2299 2300 switch (xgbe_phy_cur_mode(pdata)) { 2301 case XGBE_MODE_SGMII_100: 2302 case XGBE_MODE_SGMII_1000: 2303 return (XGBE_MODE_KR); 2304 case XGBE_MODE_KR: 2305 default: 2306 return (XGBE_MODE_SGMII_1000); 2307 } 2308 } 2309 2310 static enum xgbe_mode 2311 xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 2312 { 2313 return (XGBE_MODE_KX_2500); 2314 } 2315 2316 static enum xgbe_mode 2317 xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 2318 { 2319 /* If we are in KR switch to KX, and vice-versa */ 2320 switch (xgbe_phy_cur_mode(pdata)) { 2321 case XGBE_MODE_KX_1000: 2322 return (XGBE_MODE_KR); 2323 case XGBE_MODE_KR: 2324 default: 2325 return (XGBE_MODE_KX_1000); 2326 } 2327 } 2328 2329 static enum xgbe_mode 2330 xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 2331 { 2332 struct xgbe_phy_data *phy_data = pdata->phy_data; 2333 2334 switch (phy_data->port_mode) { 2335 case XGBE_PORT_MODE_BACKPLANE: 2336 return (xgbe_phy_switch_bp_mode(pdata)); 2337 case XGBE_PORT_MODE_BACKPLANE_2500: 2338 return (xgbe_phy_switch_bp_2500_mode(pdata)); 2339 case XGBE_PORT_MODE_1000BASE_T: 2340 case XGBE_PORT_MODE_NBASE_T: 2341 case XGBE_PORT_MODE_10GBASE_T: 2342 return (xgbe_phy_switch_baset_mode(pdata)); 2343 case XGBE_PORT_MODE_1000BASE_X: 2344 case XGBE_PORT_MODE_10GBASE_R: 2345 case XGBE_PORT_MODE_SFP: 2346 /* No switching, so just return current mode */ 2347 return (xgbe_phy_cur_mode(pdata)); 2348 default: 2349 return (XGBE_MODE_UNKNOWN); 2350 } 2351 } 2352 2353 static enum xgbe_mode 2354 xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, int speed) 2355 { 2356 switch (speed) { 2357 case SPEED_1000: 2358 return (XGBE_MODE_X); 2359 case SPEED_10000: 2360 return (XGBE_MODE_KR); 2361 default: 2362 return (XGBE_MODE_UNKNOWN); 2363 } 2364 } 2365 2366 static enum xgbe_mode 2367 xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, int speed) 2368 { 2369 switch (speed) { 2370 case SPEED_100: 2371 return (XGBE_MODE_SGMII_100); 2372 case SPEED_1000: 2373 return (XGBE_MODE_SGMII_1000); 2374 case SPEED_2500: 2375 return (XGBE_MODE_KX_2500); 2376 case SPEED_10000: 2377 return (XGBE_MODE_KR); 2378 default: 2379 return (XGBE_MODE_UNKNOWN); 2380 } 2381 } 2382 2383 static enum xgbe_mode 2384 xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, int speed) 2385 { 2386 switch (speed) { 2387 case SPEED_100: 2388 return (XGBE_MODE_SGMII_100); 2389 case SPEED_1000: 2390 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2391 return (XGBE_MODE_SGMII_1000); 2392 else 2393 return (XGBE_MODE_X); 2394 case SPEED_10000: 2395 case SPEED_UNKNOWN: 2396 return (XGBE_MODE_SFI); 2397 default: 2398 return (XGBE_MODE_UNKNOWN); 2399 } 2400 } 2401 2402 static enum xgbe_mode 2403 xgbe_phy_get_bp_2500_mode(int speed) 2404 { 2405 switch (speed) { 2406 case SPEED_2500: 2407 return (XGBE_MODE_KX_2500); 2408 default: 2409 return (XGBE_MODE_UNKNOWN); 2410 } 2411 } 2412 2413 static enum xgbe_mode 2414 xgbe_phy_get_bp_mode(int speed) 2415 { 2416 switch (speed) { 2417 case SPEED_1000: 2418 return (XGBE_MODE_KX_1000); 2419 case SPEED_10000: 2420 return (XGBE_MODE_KR); 2421 default: 2422 return (XGBE_MODE_UNKNOWN); 2423 } 2424 } 2425 2426 static enum xgbe_mode 2427 xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed) 2428 { 2429 struct xgbe_phy_data *phy_data = pdata->phy_data; 2430 2431 switch (phy_data->port_mode) { 2432 case XGBE_PORT_MODE_BACKPLANE: 2433 return (xgbe_phy_get_bp_mode(speed)); 2434 case XGBE_PORT_MODE_BACKPLANE_2500: 2435 return (xgbe_phy_get_bp_2500_mode(speed)); 2436 case XGBE_PORT_MODE_1000BASE_T: 2437 case XGBE_PORT_MODE_NBASE_T: 2438 case XGBE_PORT_MODE_10GBASE_T: 2439 return (xgbe_phy_get_baset_mode(phy_data, speed)); 2440 case XGBE_PORT_MODE_1000BASE_X: 2441 case XGBE_PORT_MODE_10GBASE_R: 2442 return (xgbe_phy_get_basex_mode(phy_data, speed)); 2443 case XGBE_PORT_MODE_SFP: 2444 return (xgbe_phy_get_sfp_mode(phy_data, speed)); 2445 default: 2446 return (XGBE_MODE_UNKNOWN); 2447 } 2448 } 2449 2450 static void 2451 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2452 { 2453 switch (mode) { 2454 case XGBE_MODE_KX_1000: 2455 xgbe_phy_kx_1000_mode(pdata); 2456 break; 2457 case XGBE_MODE_KX_2500: 2458 xgbe_phy_kx_2500_mode(pdata); 2459 break; 2460 case XGBE_MODE_KR: 2461 xgbe_phy_kr_mode(pdata); 2462 break; 2463 case XGBE_MODE_SGMII_100: 2464 xgbe_phy_sgmii_100_mode(pdata); 2465 break; 2466 case XGBE_MODE_SGMII_1000: 2467 xgbe_phy_sgmii_1000_mode(pdata); 2468 break; 2469 case XGBE_MODE_X: 2470 xgbe_phy_x_mode(pdata); 2471 break; 2472 case XGBE_MODE_SFI: 2473 xgbe_phy_sfi_mode(pdata); 2474 break; 2475 default: 2476 break; 2477 } 2478 } 2479 2480 static void 2481 xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr) 2482 { 2483 struct xgbe_phy_data *phy_data = pdata->phy_data; 2484 2485 switch (pdata->phy.speed) { 2486 case SPEED_10000: 2487 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) 2488 ifmr->ifm_active |= IFM_10G_KR; 2489 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T) 2490 ifmr->ifm_active |= IFM_10G_T; 2491 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R) 2492 ifmr->ifm_active |= IFM_10G_KR; 2493 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP) 2494 ifmr->ifm_active |= IFM_10G_SFI; 2495 else 2496 ifmr->ifm_active |= IFM_OTHER; 2497 break; 2498 case SPEED_2500: 2499 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE_2500) 2500 ifmr->ifm_active |= IFM_2500_KX; 2501 else 2502 ifmr->ifm_active |= IFM_OTHER; 2503 break; 2504 case SPEED_1000: 2505 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) 2506 ifmr->ifm_active |= IFM_1000_KX; 2507 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_T) 2508 ifmr->ifm_active |= IFM_1000_T; 2509 #if 0 2510 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X) 2511 ifmr->ifm_active |= IFM_1000_SX; 2512 ifmr->ifm_active |= IFM_1000_LX; 2513 ifmr->ifm_active |= IFM_1000_CX; 2514 #endif 2515 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP) 2516 ifmr->ifm_active |= IFM_1000_SGMII; 2517 else 2518 ifmr->ifm_active |= IFM_OTHER; 2519 break; 2520 case SPEED_100: 2521 if(phy_data->port_mode == XGBE_PORT_MODE_NBASE_T) 2522 ifmr->ifm_active |= IFM_100_T; 2523 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP) 2524 ifmr->ifm_active |= IFM_100_SGMII; 2525 else 2526 ifmr->ifm_active |= IFM_OTHER; 2527 break; 2528 default: 2529 ifmr->ifm_active |= IFM_OTHER; 2530 axgbe_printf(1, "Unknown mode detected\n"); 2531 break; 2532 } 2533 } 2534 2535 static bool 2536 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode, 2537 bool advert) 2538 { 2539 2540 if (pdata->phy.autoneg == AUTONEG_ENABLE) 2541 return (advert); 2542 else { 2543 enum xgbe_mode cur_mode; 2544 2545 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2546 if (cur_mode == mode) 2547 return (true); 2548 } 2549 2550 return (false); 2551 } 2552 2553 static bool 2554 xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2555 { 2556 2557 switch (mode) { 2558 case XGBE_MODE_X: 2559 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2560 1000baseX_Full))); 2561 case XGBE_MODE_KR: 2562 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2563 10000baseKR_Full))); 2564 default: 2565 return (false); 2566 } 2567 } 2568 2569 static bool 2570 xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2571 { 2572 2573 axgbe_printf(3, "%s: check mode %d\n", __func__, mode); 2574 switch (mode) { 2575 case XGBE_MODE_SGMII_100: 2576 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2577 100baseT_Full))); 2578 case XGBE_MODE_SGMII_1000: 2579 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2580 1000baseT_Full))); 2581 case XGBE_MODE_KX_2500: 2582 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2583 2500baseT_Full))); 2584 case XGBE_MODE_KR: 2585 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2586 10000baseT_Full))); 2587 default: 2588 return (false); 2589 } 2590 } 2591 2592 static bool 2593 xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2594 { 2595 struct xgbe_phy_data *phy_data = pdata->phy_data; 2596 2597 switch (mode) { 2598 case XGBE_MODE_X: 2599 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2600 return (false); 2601 return (xgbe_phy_check_mode(pdata, mode, 2602 XGBE_ADV(&pdata->phy, 1000baseX_Full))); 2603 case XGBE_MODE_SGMII_100: 2604 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2605 return (false); 2606 return (xgbe_phy_check_mode(pdata, mode, 2607 XGBE_ADV(&pdata->phy, 100baseT_Full))); 2608 case XGBE_MODE_SGMII_1000: 2609 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2610 return (false); 2611 return (xgbe_phy_check_mode(pdata, mode, 2612 XGBE_ADV(&pdata->phy, 1000baseT_Full))); 2613 case XGBE_MODE_SFI: 2614 if (phy_data->sfp_mod_absent) 2615 return (true); 2616 return (xgbe_phy_check_mode(pdata, mode, 2617 XGBE_ADV(&pdata->phy, 10000baseSR_Full) || 2618 XGBE_ADV(&pdata->phy, 10000baseLR_Full) || 2619 XGBE_ADV(&pdata->phy, 10000baseLRM_Full) || 2620 XGBE_ADV(&pdata->phy, 10000baseER_Full) || 2621 XGBE_ADV(&pdata->phy, 10000baseCR_Full))); 2622 default: 2623 return (false); 2624 } 2625 } 2626 2627 static bool 2628 xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2629 { 2630 2631 switch (mode) { 2632 case XGBE_MODE_KX_2500: 2633 return (xgbe_phy_check_mode(pdata, mode, 2634 XGBE_ADV(&pdata->phy, 2500baseX_Full))); 2635 default: 2636 return (false); 2637 } 2638 } 2639 2640 static bool 2641 xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2642 { 2643 2644 switch (mode) { 2645 case XGBE_MODE_KX_1000: 2646 return (xgbe_phy_check_mode(pdata, mode, 2647 XGBE_ADV(&pdata->phy, 1000baseKX_Full))); 2648 case XGBE_MODE_KR: 2649 return (xgbe_phy_check_mode(pdata, mode, 2650 XGBE_ADV(&pdata->phy, 10000baseKR_Full))); 2651 default: 2652 return (false); 2653 } 2654 } 2655 2656 static bool 2657 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2658 { 2659 struct xgbe_phy_data *phy_data = pdata->phy_data; 2660 2661 switch (phy_data->port_mode) { 2662 case XGBE_PORT_MODE_BACKPLANE: 2663 return (xgbe_phy_use_bp_mode(pdata, mode)); 2664 case XGBE_PORT_MODE_BACKPLANE_2500: 2665 return (xgbe_phy_use_bp_2500_mode(pdata, mode)); 2666 case XGBE_PORT_MODE_1000BASE_T: 2667 axgbe_printf(3, "use_mode %s\n", 2668 xgbe_phy_use_baset_mode(pdata, mode) ? "found" : "Not found"); 2669 case XGBE_PORT_MODE_NBASE_T: 2670 case XGBE_PORT_MODE_10GBASE_T: 2671 return (xgbe_phy_use_baset_mode(pdata, mode)); 2672 case XGBE_PORT_MODE_1000BASE_X: 2673 case XGBE_PORT_MODE_10GBASE_R: 2674 return (xgbe_phy_use_basex_mode(pdata, mode)); 2675 case XGBE_PORT_MODE_SFP: 2676 return (xgbe_phy_use_sfp_mode(pdata, mode)); 2677 default: 2678 return (false); 2679 } 2680 } 2681 2682 static bool 2683 xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, int speed) 2684 { 2685 2686 switch (speed) { 2687 case SPEED_1000: 2688 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2689 case SPEED_10000: 2690 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2691 default: 2692 return (false); 2693 } 2694 } 2695 2696 static bool 2697 xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, int speed) 2698 { 2699 2700 switch (speed) { 2701 case SPEED_100: 2702 case SPEED_1000: 2703 return (true); 2704 case SPEED_2500: 2705 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T); 2706 case SPEED_10000: 2707 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2708 default: 2709 return (false); 2710 } 2711 } 2712 2713 static bool 2714 xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, int speed) 2715 { 2716 2717 switch (speed) { 2718 case SPEED_100: 2719 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100) || 2720 (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000)); 2721 case SPEED_1000: 2722 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2723 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2724 case SPEED_10000: 2725 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2726 default: 2727 return (false); 2728 } 2729 } 2730 2731 static bool 2732 xgbe_phy_valid_speed_bp_2500_mode(int speed) 2733 { 2734 2735 switch (speed) { 2736 case SPEED_2500: 2737 return (true); 2738 default: 2739 return (false); 2740 } 2741 } 2742 2743 static bool 2744 xgbe_phy_valid_speed_bp_mode(int speed) 2745 { 2746 2747 switch (speed) { 2748 case SPEED_1000: 2749 case SPEED_10000: 2750 return (true); 2751 default: 2752 return (false); 2753 } 2754 } 2755 2756 static bool 2757 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2758 { 2759 struct xgbe_phy_data *phy_data = pdata->phy_data; 2760 2761 switch (phy_data->port_mode) { 2762 case XGBE_PORT_MODE_BACKPLANE: 2763 return (xgbe_phy_valid_speed_bp_mode(speed)); 2764 case XGBE_PORT_MODE_BACKPLANE_2500: 2765 return (xgbe_phy_valid_speed_bp_2500_mode(speed)); 2766 case XGBE_PORT_MODE_1000BASE_T: 2767 case XGBE_PORT_MODE_NBASE_T: 2768 case XGBE_PORT_MODE_10GBASE_T: 2769 return (xgbe_phy_valid_speed_baset_mode(phy_data, speed)); 2770 case XGBE_PORT_MODE_1000BASE_X: 2771 case XGBE_PORT_MODE_10GBASE_R: 2772 return (xgbe_phy_valid_speed_basex_mode(phy_data, speed)); 2773 case XGBE_PORT_MODE_SFP: 2774 return (xgbe_phy_valid_speed_sfp_mode(phy_data, speed)); 2775 default: 2776 return (false); 2777 } 2778 } 2779 2780 static int 2781 xgbe_upd_link(struct xgbe_prv_data *pdata) 2782 { 2783 int reg; 2784 2785 axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link); 2786 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR); 2787 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR); 2788 if (reg < 0) 2789 return (reg); 2790 2791 if ((reg & BMSR_LINK) == 0) 2792 pdata->phy.link = 0; 2793 else 2794 pdata->phy.link = 1; 2795 2796 axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg); 2797 return (0); 2798 } 2799 2800 static int 2801 xgbe_phy_read_status(struct xgbe_prv_data *pdata) 2802 { 2803 int common_adv_gb = 0; 2804 int common_adv; 2805 int lpagb = 0; 2806 int adv, lpa; 2807 int ret; 2808 2809 ret = xgbe_upd_link(pdata); 2810 if (ret) { 2811 axgbe_printf(2, "Link Update return %d\n", ret); 2812 return (ret); 2813 } 2814 2815 if (AUTONEG_ENABLE == pdata->phy.autoneg) { 2816 if (pdata->phy.supported == SUPPORTED_1000baseT_Half || 2817 pdata->phy.supported == SUPPORTED_1000baseT_Full) { 2818 lpagb = xgbe_phy_mii_read(pdata, pdata->mdio_addr, 2819 MII_100T2SR); 2820 if (lpagb < 0) 2821 return (lpagb); 2822 2823 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, 2824 MII_100T2CR); 2825 if (adv < 0) 2826 return (adv); 2827 2828 if (lpagb & GTSR_MAN_MS_FLT) { 2829 if (adv & GTCR_MAN_MS) 2830 axgbe_printf(2, "Master/Slave Resolution " 2831 "failed, maybe conflicting manual settings\n"); 2832 else 2833 axgbe_printf(2, "Master/Slave Resolution failed\n"); 2834 return (-ENOLINK); 2835 } 2836 2837 if (pdata->phy.supported == SUPPORTED_1000baseT_Half) 2838 XGBE_SET_ADV(&pdata->phy, 1000baseT_Half); 2839 else if (pdata->phy.supported == SUPPORTED_1000baseT_Full) 2840 XGBE_SET_ADV(&pdata->phy, 1000baseT_Full); 2841 2842 common_adv_gb = lpagb & adv << 2; 2843 } 2844 2845 lpa = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANLPAR); 2846 if (lpa < 0) 2847 return (lpa); 2848 2849 if (pdata->phy.supported == SUPPORTED_Autoneg) 2850 XGBE_SET_ADV(&pdata->phy, Autoneg); 2851 2852 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANAR); 2853 if (adv < 0) 2854 return (adv); 2855 2856 common_adv = lpa & adv; 2857 2858 pdata->phy.speed = SPEED_10; 2859 pdata->phy.duplex = DUPLEX_HALF; 2860 pdata->phy.pause = 0; 2861 pdata->phy.asym_pause = 0; 2862 2863 axgbe_printf(2, "%s: lpa %#x adv %#x common_adv_gb %#x " 2864 "common_adv %#x\n", __func__, lpa, adv, common_adv_gb, 2865 common_adv); 2866 if (common_adv_gb & (GTSR_LP_1000TFDX | GTSR_LP_1000THDX)) { 2867 axgbe_printf(2, "%s: SPEED 1000\n", __func__); 2868 pdata->phy.speed = SPEED_1000; 2869 2870 if (common_adv_gb & GTSR_LP_1000TFDX) 2871 pdata->phy.duplex = DUPLEX_FULL; 2872 } else if (common_adv & (ANLPAR_TX_FD | ANLPAR_TX)) { 2873 axgbe_printf(2, "%s: SPEED 100\n", __func__); 2874 pdata->phy.speed = SPEED_100; 2875 2876 if (common_adv & ANLPAR_TX_FD) 2877 pdata->phy.duplex = DUPLEX_FULL; 2878 } else 2879 if (common_adv & ANLPAR_10_FD) 2880 pdata->phy.duplex = DUPLEX_FULL; 2881 2882 if (pdata->phy.duplex == DUPLEX_FULL) { 2883 pdata->phy.pause = lpa & ANLPAR_FC ? 1 : 0; 2884 pdata->phy.asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; 2885 } 2886 } else { 2887 int bmcr = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR); 2888 if (bmcr < 0) 2889 return (bmcr); 2890 2891 if (bmcr & BMCR_FDX) 2892 pdata->phy.duplex = DUPLEX_FULL; 2893 else 2894 pdata->phy.duplex = DUPLEX_HALF; 2895 2896 if (bmcr & BMCR_SPEED1) 2897 pdata->phy.speed = SPEED_1000; 2898 else if (bmcr & BMCR_SPEED100) 2899 pdata->phy.speed = SPEED_100; 2900 else 2901 pdata->phy.speed = SPEED_10; 2902 2903 pdata->phy.pause = 0; 2904 pdata->phy.asym_pause = 0; 2905 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x " 2906 "autoneg %#x\n", __func__, pdata->phy.speed, 2907 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg); 2908 } 2909 2910 return (0); 2911 } 2912 2913 static void 2914 xgbe_rrc(struct xgbe_prv_data *pdata) 2915 { 2916 struct xgbe_phy_data *phy_data = pdata->phy_data; 2917 int ret; 2918 2919 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { 2920 axgbe_printf(1, "ENTERED RRC: rrc_count: %d\n", 2921 phy_data->rrc_count); 2922 phy_data->rrc_count = 0; 2923 if (pdata->link_workaround) { 2924 ret = xgbe_phy_reset(pdata); 2925 if (ret) 2926 axgbe_error("Error resetting phy\n"); 2927 } else 2928 xgbe_phy_rrc(pdata); 2929 } 2930 } 2931 2932 static int 2933 xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2934 { 2935 struct xgbe_phy_data *phy_data = pdata->phy_data; 2936 struct mii_data *mii = NULL; 2937 unsigned int reg; 2938 int ret; 2939 2940 *an_restart = 0; 2941 2942 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2943 /* Check SFP signals */ 2944 axgbe_printf(3, "%s: calling phy detect\n", __func__); 2945 xgbe_phy_sfp_detect(pdata); 2946 2947 if (phy_data->sfp_changed) { 2948 axgbe_printf(1, "%s: SFP changed observed\n", __func__); 2949 *an_restart = 1; 2950 return (0); 2951 } 2952 2953 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) { 2954 axgbe_printf(1, "%s: SFP absent 0x%x & sfp_rx_los 0x%x\n", 2955 __func__, phy_data->sfp_mod_absent, 2956 phy_data->sfp_rx_los); 2957 2958 if (!phy_data->sfp_mod_absent) { 2959 xgbe_rrc(pdata); 2960 } 2961 2962 return (0); 2963 } 2964 } 2965 2966 if (phy_data->phydev || phy_data->port_mode != XGBE_PORT_MODE_SFP) { 2967 if (pdata->axgbe_miibus == NULL) { 2968 axgbe_printf(1, "%s: miibus not initialized", __func__); 2969 goto mdio_read; 2970 } 2971 2972 mii = device_get_softc(pdata->axgbe_miibus); 2973 mii_tick(mii); 2974 2975 ret = xgbe_phy_read_status(pdata); 2976 if (ret) { 2977 axgbe_error("Link: Read status returned %d\n", ret); 2978 return (0); 2979 } 2980 2981 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x " 2982 "autoneg %#x\n", __func__, pdata->phy.speed, 2983 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg); 2984 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR); 2985 ret = (ret < 0) ? ret : (ret & BMSR_ACOMP); 2986 axgbe_printf(2, "Link: BMCR returned %d\n", ret); 2987 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && !ret) 2988 return (0); 2989 2990 if (pdata->phy.link) 2991 return (1); 2992 2993 xgbe_rrc(pdata); 2994 } 2995 2996 mdio_read: 2997 2998 /* Link status is latched low, so read once to clear 2999 * and then read again to get current state 3000 */ 3001 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 3002 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 3003 axgbe_printf(1, "%s: link_status reg: 0x%x\n", __func__, reg); 3004 if (reg & MDIO_STAT1_LSTATUS) 3005 return (1); 3006 3007 /* No link, attempt a receiver reset cycle */ 3008 xgbe_rrc(pdata); 3009 3010 return (0); 3011 } 3012 3013 static void 3014 xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 3015 { 3016 struct xgbe_phy_data *phy_data = pdata->phy_data; 3017 3018 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 3019 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR); 3020 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3021 GPIO_MASK); 3022 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3023 GPIO_RX_LOS); 3024 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3025 GPIO_TX_FAULT); 3026 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3027 GPIO_MOD_ABS); 3028 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3029 GPIO_RATE_SELECT); 3030 3031 DBGPR("SFP: gpio_address=%#x\n", phy_data->sfp_gpio_address); 3032 DBGPR("SFP: gpio_mask=%#x\n", phy_data->sfp_gpio_mask); 3033 DBGPR("SFP: gpio_rx_los=%u\n", phy_data->sfp_gpio_rx_los); 3034 DBGPR("SFP: gpio_tx_fault=%u\n", phy_data->sfp_gpio_tx_fault); 3035 DBGPR("SFP: gpio_mod_absent=%u\n", 3036 phy_data->sfp_gpio_mod_absent); 3037 DBGPR("SFP: gpio_rate_select=%u\n", 3038 phy_data->sfp_gpio_rate_select); 3039 } 3040 3041 static void 3042 xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 3043 { 3044 struct xgbe_phy_data *phy_data = pdata->phy_data; 3045 unsigned int mux_addr_hi, mux_addr_lo; 3046 3047 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 3048 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 3049 if (mux_addr_lo == XGBE_SFP_DIRECT) 3050 return; 3051 3052 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 3053 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 3054 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, 3055 MUX_CHAN); 3056 3057 DBGPR("SFP: mux_address=%#x\n", phy_data->sfp_mux_address); 3058 DBGPR("SFP: mux_channel=%u\n", phy_data->sfp_mux_channel); 3059 } 3060 3061 static void 3062 xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 3063 { 3064 xgbe_phy_sfp_comm_setup(pdata); 3065 xgbe_phy_sfp_gpio_setup(pdata); 3066 } 3067 3068 static int 3069 xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 3070 { 3071 struct xgbe_phy_data *phy_data = pdata->phy_data; 3072 unsigned int ret; 3073 3074 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 3075 if (ret) 3076 return (ret); 3077 3078 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 3079 3080 return (ret); 3081 } 3082 3083 static int 3084 xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 3085 { 3086 struct xgbe_phy_data *phy_data = pdata->phy_data; 3087 uint8_t gpio_reg, gpio_ports[2], gpio_data[3]; 3088 int ret; 3089 3090 /* Read the output port registers */ 3091 gpio_reg = 2; 3092 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 3093 &gpio_reg, sizeof(gpio_reg), 3094 gpio_ports, sizeof(gpio_ports)); 3095 if (ret) 3096 return (ret); 3097 3098 /* Prepare to write the GPIO data */ 3099 gpio_data[0] = 2; 3100 gpio_data[1] = gpio_ports[0]; 3101 gpio_data[2] = gpio_ports[1]; 3102 3103 /* Set the GPIO pin */ 3104 if (phy_data->mdio_reset_gpio < 8) 3105 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 3106 else 3107 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 3108 3109 /* Write the output port registers */ 3110 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 3111 gpio_data, sizeof(gpio_data)); 3112 if (ret) 3113 return (ret); 3114 3115 /* Clear the GPIO pin */ 3116 if (phy_data->mdio_reset_gpio < 8) 3117 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 3118 else 3119 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 3120 3121 /* Write the output port registers */ 3122 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 3123 gpio_data, sizeof(gpio_data)); 3124 3125 return (ret); 3126 } 3127 3128 static int 3129 xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 3130 { 3131 struct xgbe_phy_data *phy_data = pdata->phy_data; 3132 int ret; 3133 3134 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 3135 return (0); 3136 3137 ret = xgbe_phy_get_comm_ownership(pdata); 3138 if (ret) 3139 return (ret); 3140 3141 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 3142 ret = xgbe_phy_i2c_mdio_reset(pdata); 3143 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 3144 ret = xgbe_phy_int_mdio_reset(pdata); 3145 3146 xgbe_phy_put_comm_ownership(pdata); 3147 3148 return (ret); 3149 } 3150 3151 static bool 3152 xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 3153 { 3154 if (!phy_data->redrv) 3155 return (false); 3156 3157 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 3158 return (true); 3159 3160 switch (phy_data->redrv_model) { 3161 case XGBE_PHY_REDRV_MODEL_4223: 3162 if (phy_data->redrv_lane > 3) 3163 return (true); 3164 break; 3165 case XGBE_PHY_REDRV_MODEL_4227: 3166 if (phy_data->redrv_lane > 1) 3167 return (true); 3168 break; 3169 default: 3170 return (true); 3171 } 3172 3173 return (false); 3174 } 3175 3176 static int 3177 xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 3178 { 3179 struct xgbe_phy_data *phy_data = pdata->phy_data; 3180 3181 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 3182 return (0); 3183 3184 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 3185 switch (phy_data->mdio_reset) { 3186 case XGBE_MDIO_RESET_NONE: 3187 case XGBE_MDIO_RESET_I2C_GPIO: 3188 case XGBE_MDIO_RESET_INT_GPIO: 3189 break; 3190 default: 3191 axgbe_error("unsupported MDIO reset (%#x)\n", 3192 phy_data->mdio_reset); 3193 return (-EINVAL); 3194 } 3195 3196 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 3197 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 3198 XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET_I2C_ADDR); 3199 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3200 MDIO_RESET_I2C_GPIO); 3201 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 3202 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3203 MDIO_RESET_INT_GPIO); 3204 3205 return (0); 3206 } 3207 3208 static bool 3209 xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 3210 { 3211 struct xgbe_phy_data *phy_data = pdata->phy_data; 3212 3213 switch (phy_data->port_mode) { 3214 case XGBE_PORT_MODE_BACKPLANE: 3215 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3216 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3217 return (false); 3218 break; 3219 case XGBE_PORT_MODE_BACKPLANE_2500: 3220 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 3221 return (false); 3222 break; 3223 case XGBE_PORT_MODE_1000BASE_T: 3224 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3225 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 3226 return (false); 3227 break; 3228 case XGBE_PORT_MODE_1000BASE_X: 3229 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3230 return (false); 3231 break; 3232 case XGBE_PORT_MODE_NBASE_T: 3233 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3234 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3235 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 3236 return (false); 3237 break; 3238 case XGBE_PORT_MODE_10GBASE_T: 3239 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3240 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3241 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3242 return (false); 3243 break; 3244 case XGBE_PORT_MODE_10GBASE_R: 3245 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3246 return (false); 3247 break; 3248 case XGBE_PORT_MODE_SFP: 3249 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3250 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3251 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3252 return (false); 3253 break; 3254 default: 3255 break; 3256 } 3257 3258 return (true); 3259 } 3260 3261 static bool 3262 xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 3263 { 3264 struct xgbe_phy_data *phy_data = pdata->phy_data; 3265 3266 switch (phy_data->port_mode) { 3267 case XGBE_PORT_MODE_BACKPLANE: 3268 case XGBE_PORT_MODE_BACKPLANE_2500: 3269 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 3270 return (false); 3271 break; 3272 case XGBE_PORT_MODE_1000BASE_T: 3273 case XGBE_PORT_MODE_1000BASE_X: 3274 case XGBE_PORT_MODE_NBASE_T: 3275 case XGBE_PORT_MODE_10GBASE_T: 3276 case XGBE_PORT_MODE_10GBASE_R: 3277 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 3278 return (false); 3279 break; 3280 case XGBE_PORT_MODE_SFP: 3281 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 3282 return (false); 3283 break; 3284 default: 3285 break; 3286 } 3287 3288 return (true); 3289 } 3290 3291 static bool 3292 xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 3293 { 3294 3295 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 3296 return (false); 3297 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 3298 return (false); 3299 3300 return (true); 3301 } 3302 3303 static void 3304 xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) 3305 { 3306 struct xgbe_phy_data *phy_data = pdata->phy_data; 3307 3308 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n", 3309 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack); 3310 3311 if (!pdata->sysctl_an_cdr_workaround) 3312 return; 3313 3314 if (!phy_data->phy_cdr_notrack) 3315 return; 3316 3317 DELAY(phy_data->phy_cdr_delay + 500); 3318 3319 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 3320 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_ON); 3321 3322 phy_data->phy_cdr_notrack = 0; 3323 3324 axgbe_printf(2, "CDR TRACK DONE\n"); 3325 } 3326 3327 static void 3328 xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) 3329 { 3330 struct xgbe_phy_data *phy_data = pdata->phy_data; 3331 3332 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n", 3333 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack); 3334 3335 if (!pdata->sysctl_an_cdr_workaround) 3336 return; 3337 3338 if (phy_data->phy_cdr_notrack) 3339 return; 3340 3341 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 3342 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_OFF); 3343 3344 xgbe_phy_rrc(pdata); 3345 3346 phy_data->phy_cdr_notrack = 1; 3347 } 3348 3349 static void 3350 xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) 3351 { 3352 if (!pdata->sysctl_an_cdr_track_early) 3353 xgbe_phy_cdr_track(pdata); 3354 } 3355 3356 static void 3357 xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) 3358 { 3359 if (pdata->sysctl_an_cdr_track_early) 3360 xgbe_phy_cdr_track(pdata); 3361 } 3362 3363 static void 3364 xgbe_phy_an_post(struct xgbe_prv_data *pdata) 3365 { 3366 struct xgbe_phy_data *phy_data = pdata->phy_data; 3367 3368 switch (pdata->an_mode) { 3369 case XGBE_AN_MODE_CL73: 3370 case XGBE_AN_MODE_CL73_REDRV: 3371 if (phy_data->cur_mode != XGBE_MODE_KR) 3372 break; 3373 3374 xgbe_phy_cdr_track(pdata); 3375 3376 switch (pdata->an_result) { 3377 case XGBE_AN_READY: 3378 case XGBE_AN_COMPLETE: 3379 break; 3380 default: 3381 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) 3382 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; 3383 else 3384 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3385 break; 3386 } 3387 break; 3388 default: 3389 break; 3390 } 3391 } 3392 3393 static void 3394 xgbe_phy_an_pre(struct xgbe_prv_data *pdata) 3395 { 3396 struct xgbe_phy_data *phy_data = pdata->phy_data; 3397 3398 switch (pdata->an_mode) { 3399 case XGBE_AN_MODE_CL73: 3400 case XGBE_AN_MODE_CL73_REDRV: 3401 if (phy_data->cur_mode != XGBE_MODE_KR) 3402 break; 3403 3404 xgbe_phy_cdr_notrack(pdata); 3405 break; 3406 default: 3407 break; 3408 } 3409 } 3410 3411 static void 3412 xgbe_phy_stop(struct xgbe_prv_data *pdata) 3413 { 3414 struct xgbe_phy_data *phy_data = pdata->phy_data; 3415 3416 /* If we have an external PHY, free it */ 3417 xgbe_phy_free_phy_device(pdata); 3418 3419 /* Reset SFP data */ 3420 xgbe_phy_sfp_reset(phy_data); 3421 xgbe_phy_sfp_mod_absent(pdata); 3422 3423 /* Reset CDR support */ 3424 xgbe_phy_cdr_track(pdata); 3425 3426 /* Power off the PHY */ 3427 xgbe_phy_power_off(pdata); 3428 3429 /* Stop the I2C controller */ 3430 pdata->i2c_if.i2c_stop(pdata); 3431 } 3432 3433 static int 3434 xgbe_phy_start(struct xgbe_prv_data *pdata) 3435 { 3436 struct xgbe_phy_data *phy_data = pdata->phy_data; 3437 int ret; 3438 3439 axgbe_printf(2, "%s: redrv %d redrv_if %d start_mode %d\n", __func__, 3440 phy_data->redrv, phy_data->redrv_if, phy_data->start_mode); 3441 3442 /* Start the I2C controller */ 3443 ret = pdata->i2c_if.i2c_start(pdata); 3444 if (ret) { 3445 axgbe_error("%s: impl i2c start ret %d\n", __func__, ret); 3446 return (ret); 3447 } 3448 3449 /* Set the proper MDIO mode for the re-driver */ 3450 if (phy_data->redrv && !phy_data->redrv_if) { 3451 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3452 XGBE_MDIO_MODE_CL22); 3453 if (ret) { 3454 axgbe_error("redriver mdio port not compatible (%u)\n", 3455 phy_data->redrv_addr); 3456 return (ret); 3457 } 3458 } 3459 3460 /* Start in highest supported mode */ 3461 xgbe_phy_set_mode(pdata, phy_data->start_mode); 3462 3463 /* Reset CDR support */ 3464 xgbe_phy_cdr_track(pdata); 3465 3466 /* After starting the I2C controller, we can check for an SFP */ 3467 switch (phy_data->port_mode) { 3468 case XGBE_PORT_MODE_SFP: 3469 axgbe_printf(3, "%s: calling phy detect\n", __func__); 3470 xgbe_phy_sfp_detect(pdata); 3471 break; 3472 default: 3473 break; 3474 } 3475 3476 /* If we have an external PHY, start it */ 3477 ret = xgbe_phy_find_phy_device(pdata); 3478 if (ret) { 3479 axgbe_error("%s: impl find phy dev ret %d\n", __func__, ret); 3480 goto err_i2c; 3481 } 3482 3483 axgbe_printf(3, "%s: impl return success\n", __func__); 3484 return (0); 3485 3486 err_i2c: 3487 pdata->i2c_if.i2c_stop(pdata); 3488 3489 return (ret); 3490 } 3491 3492 static int 3493 xgbe_phy_reset(struct xgbe_prv_data *pdata) 3494 { 3495 struct xgbe_phy_data *phy_data = pdata->phy_data; 3496 enum xgbe_mode cur_mode; 3497 int ret; 3498 3499 /* Reset by power cycling the PHY */ 3500 cur_mode = phy_data->cur_mode; 3501 xgbe_phy_power_off(pdata); 3502 xgbe_phy_set_mode(pdata, cur_mode); 3503 3504 axgbe_printf(3, "%s: mode %d\n", __func__, cur_mode); 3505 if (!phy_data->phydev) { 3506 axgbe_printf(1, "%s: no phydev\n", __func__); 3507 return (0); 3508 } 3509 3510 /* Reset the external PHY */ 3511 ret = xgbe_phy_mdio_reset(pdata); 3512 if (ret) { 3513 axgbe_error("%s: mdio reset %d\n", __func__, ret); 3514 return (ret); 3515 } 3516 3517 axgbe_printf(3, "%s: return success\n", __func__); 3518 3519 return (0); 3520 } 3521 3522 static void 3523 axgbe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 3524 { 3525 struct axgbe_if_softc *sc; 3526 struct xgbe_prv_data *pdata; 3527 struct mii_data *mii; 3528 3529 sc = if_getsoftc(ifp); 3530 pdata = &sc->pdata; 3531 3532 axgbe_printf(2, "%s: Invoked\n", __func__); 3533 mtx_lock_spin(&pdata->mdio_mutex); 3534 mii = device_get_softc(pdata->axgbe_miibus); 3535 axgbe_printf(2, "%s: media_active %#x media_status %#x\n", __func__, 3536 mii->mii_media_active, mii->mii_media_status); 3537 mii_pollstat(mii); 3538 ifmr->ifm_active = mii->mii_media_active; 3539 ifmr->ifm_status = mii->mii_media_status; 3540 mtx_unlock_spin(&pdata->mdio_mutex); 3541 } 3542 3543 static int 3544 axgbe_ifmedia_upd(if_t ifp) 3545 { 3546 struct xgbe_prv_data *pdata; 3547 struct axgbe_if_softc *sc; 3548 struct mii_data *mii; 3549 struct mii_softc *miisc; 3550 int ret; 3551 3552 sc = if_getsoftc(ifp); 3553 pdata = &sc->pdata; 3554 3555 axgbe_printf(2, "%s: Invoked\n", __func__); 3556 mtx_lock_spin(&pdata->mdio_mutex); 3557 mii = device_get_softc(pdata->axgbe_miibus); 3558 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3559 PHY_RESET(miisc); 3560 ret = mii_mediachg(mii); 3561 mtx_unlock_spin(&pdata->mdio_mutex); 3562 3563 return (ret); 3564 } 3565 3566 static void 3567 xgbe_phy_exit(struct xgbe_prv_data *pdata) 3568 { 3569 if (pdata->axgbe_miibus != NULL) 3570 device_delete_child(pdata->dev, pdata->axgbe_miibus); 3571 3572 /* free phy_data structure */ 3573 free(pdata->phy_data, M_AXGBE); 3574 } 3575 3576 static int 3577 xgbe_phy_init(struct xgbe_prv_data *pdata) 3578 { 3579 struct xgbe_phy_data *phy_data; 3580 int ret; 3581 3582 /* Initialize the global lock */ 3583 if (!mtx_initialized(&xgbe_phy_comm_lock)) 3584 mtx_init(&xgbe_phy_comm_lock, "xgbe phy common lock", NULL, MTX_DEF); 3585 3586 /* Check if enabled */ 3587 if (!xgbe_phy_port_enabled(pdata)) { 3588 axgbe_error("device is not enabled\n"); 3589 return (-ENODEV); 3590 } 3591 3592 /* Initialize the I2C controller */ 3593 ret = pdata->i2c_if.i2c_init(pdata); 3594 if (ret) 3595 return (ret); 3596 3597 phy_data = malloc(sizeof(*phy_data), M_AXGBE, M_WAITOK | M_ZERO); 3598 if (!phy_data) 3599 return (-ENOMEM); 3600 pdata->phy_data = phy_data; 3601 3602 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 3603 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 3604 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 3605 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 3606 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 3607 3608 pdata->mdio_addr = phy_data->mdio_addr; 3609 DBGPR("port mode=%u\n", phy_data->port_mode); 3610 DBGPR("port id=%u\n", phy_data->port_id); 3611 DBGPR("port speeds=%#x\n", phy_data->port_speeds); 3612 DBGPR("conn type=%u\n", phy_data->conn_type); 3613 DBGPR("mdio addr=%u\n", phy_data->mdio_addr); 3614 3615 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 3616 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 3617 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 3618 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 3619 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 3620 3621 if (phy_data->redrv) { 3622 DBGPR("redrv present\n"); 3623 DBGPR("redrv i/f=%u\n", phy_data->redrv_if); 3624 DBGPR("redrv addr=%#x\n", phy_data->redrv_addr); 3625 DBGPR("redrv lane=%u\n", phy_data->redrv_lane); 3626 DBGPR("redrv model=%u\n", phy_data->redrv_model); 3627 } 3628 3629 DBGPR("%s: redrv addr=%#x redrv i/f=%u\n", __func__, 3630 phy_data->redrv_addr, phy_data->redrv_if); 3631 /* Validate the connection requested */ 3632 if (xgbe_phy_conn_type_mismatch(pdata)) { 3633 axgbe_error("phy mode/connection mismatch " 3634 "(%#x/%#x)\n", phy_data->port_mode, phy_data->conn_type); 3635 return (-EINVAL); 3636 } 3637 3638 /* Validate the mode requested */ 3639 if (xgbe_phy_port_mode_mismatch(pdata)) { 3640 axgbe_error("phy mode/speed mismatch " 3641 "(%#x/%#x)\n", phy_data->port_mode, phy_data->port_speeds); 3642 return (-EINVAL); 3643 } 3644 3645 /* Check for and validate MDIO reset support */ 3646 ret = xgbe_phy_mdio_reset_setup(pdata); 3647 if (ret) { 3648 axgbe_error("%s, mdio_reset_setup ret %d\n", __func__, ret); 3649 return (ret); 3650 } 3651 3652 /* Validate the re-driver information */ 3653 if (xgbe_phy_redrv_error(phy_data)) { 3654 axgbe_error("phy re-driver settings error\n"); 3655 return (-EINVAL); 3656 } 3657 pdata->kr_redrv = phy_data->redrv; 3658 3659 /* Indicate current mode is unknown */ 3660 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 3661 3662 /* Initialize supported features. Current code does not support ethtool */ 3663 XGBE_ZERO_SUP(&pdata->phy); 3664 3665 DBGPR("%s: port mode %d\n", __func__, phy_data->port_mode); 3666 switch (phy_data->port_mode) { 3667 /* Backplane support */ 3668 case XGBE_PORT_MODE_BACKPLANE: 3669 XGBE_SET_SUP(&pdata->phy, Autoneg); 3670 XGBE_SET_SUP(&pdata->phy, Pause); 3671 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3672 XGBE_SET_SUP(&pdata->phy, Backplane); 3673 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3674 XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full); 3675 phy_data->start_mode = XGBE_MODE_KX_1000; 3676 } 3677 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3678 XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full); 3679 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3680 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC); 3681 phy_data->start_mode = XGBE_MODE_KR; 3682 } 3683 3684 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3685 break; 3686 case XGBE_PORT_MODE_BACKPLANE_2500: 3687 XGBE_SET_SUP(&pdata->phy, Pause); 3688 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3689 XGBE_SET_SUP(&pdata->phy, Backplane); 3690 XGBE_SET_SUP(&pdata->phy, 2500baseX_Full); 3691 phy_data->start_mode = XGBE_MODE_KX_2500; 3692 3693 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3694 break; 3695 3696 /* MDIO 1GBase-T support */ 3697 case XGBE_PORT_MODE_1000BASE_T: 3698 XGBE_SET_SUP(&pdata->phy, Autoneg); 3699 XGBE_SET_SUP(&pdata->phy, Pause); 3700 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3701 XGBE_SET_SUP(&pdata->phy, TP); 3702 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3703 XGBE_SET_SUP(&pdata->phy, 100baseT_Full); 3704 phy_data->start_mode = XGBE_MODE_SGMII_100; 3705 } 3706 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3707 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full); 3708 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3709 } 3710 3711 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3712 break; 3713 3714 /* MDIO Base-X support */ 3715 case XGBE_PORT_MODE_1000BASE_X: 3716 XGBE_SET_SUP(&pdata->phy, Autoneg); 3717 XGBE_SET_SUP(&pdata->phy, Pause); 3718 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3719 XGBE_SET_SUP(&pdata->phy, FIBRE); 3720 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full); 3721 phy_data->start_mode = XGBE_MODE_X; 3722 3723 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3724 break; 3725 3726 /* MDIO NBase-T support */ 3727 case XGBE_PORT_MODE_NBASE_T: 3728 XGBE_SET_SUP(&pdata->phy, Autoneg); 3729 XGBE_SET_SUP(&pdata->phy, Pause); 3730 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3731 XGBE_SET_SUP(&pdata->phy, TP); 3732 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3733 XGBE_SET_SUP(&pdata->phy, 100baseT_Full); 3734 phy_data->start_mode = XGBE_MODE_SGMII_100; 3735 } 3736 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3737 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full); 3738 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3739 } 3740 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3741 XGBE_SET_SUP(&pdata->phy, 2500baseT_Full); 3742 phy_data->start_mode = XGBE_MODE_KX_2500; 3743 } 3744 3745 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3746 break; 3747 3748 /* 10GBase-T support */ 3749 case XGBE_PORT_MODE_10GBASE_T: 3750 XGBE_SET_SUP(&pdata->phy, Autoneg); 3751 XGBE_SET_SUP(&pdata->phy, Pause); 3752 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3753 XGBE_SET_SUP(&pdata->phy, TP); 3754 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3755 XGBE_SET_SUP(&pdata->phy, 100baseT_Full); 3756 phy_data->start_mode = XGBE_MODE_SGMII_100; 3757 } 3758 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3759 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full); 3760 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3761 } 3762 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3763 XGBE_SET_SUP(&pdata->phy, 10000baseT_Full); 3764 phy_data->start_mode = XGBE_MODE_KR; 3765 } 3766 3767 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3768 break; 3769 3770 /* 10GBase-R support */ 3771 case XGBE_PORT_MODE_10GBASE_R: 3772 XGBE_SET_SUP(&pdata->phy, Autoneg); 3773 XGBE_SET_SUP(&pdata->phy, Pause); 3774 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3775 XGBE_SET_SUP(&pdata->phy, FIBRE); 3776 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full); 3777 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full); 3778 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full); 3779 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full); 3780 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3781 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC); 3782 phy_data->start_mode = XGBE_MODE_SFI; 3783 3784 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3785 break; 3786 3787 /* SFP support */ 3788 case XGBE_PORT_MODE_SFP: 3789 XGBE_SET_SUP(&pdata->phy, Autoneg); 3790 XGBE_SET_SUP(&pdata->phy, Pause); 3791 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3792 XGBE_SET_SUP(&pdata->phy, TP); 3793 XGBE_SET_SUP(&pdata->phy, FIBRE); 3794 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3795 phy_data->start_mode = XGBE_MODE_SGMII_100; 3796 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3797 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3798 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3799 phy_data->start_mode = XGBE_MODE_SFI; 3800 3801 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3802 3803 xgbe_phy_sfp_setup(pdata); 3804 DBGPR("%s: start %d mode %d adv 0x%x\n", __func__, 3805 phy_data->start_mode, phy_data->phydev_mode, 3806 pdata->phy.advertising); 3807 break; 3808 default: 3809 return (-EINVAL); 3810 } 3811 3812 axgbe_printf(2, "%s: start %d mode %d adv 0x%x\n", __func__, 3813 phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising); 3814 3815 DBGPR("%s: conn type %d mode %d\n", __func__, 3816 phy_data->conn_type, phy_data->phydev_mode); 3817 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3818 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3819 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3820 phy_data->phydev_mode); 3821 if (ret) { 3822 axgbe_error("mdio port/clause not compatible (%d/%u)\n", 3823 phy_data->mdio_addr, phy_data->phydev_mode); 3824 return (-EINVAL); 3825 } 3826 } 3827 3828 if (phy_data->redrv && !phy_data->redrv_if) { 3829 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3830 XGBE_MDIO_MODE_CL22); 3831 if (ret) { 3832 axgbe_error("redriver mdio port not compatible (%u)\n", 3833 phy_data->redrv_addr); 3834 return (-EINVAL); 3835 } 3836 } 3837 3838 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3839 3840 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 3841 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev, 3842 (ifm_change_cb_t)axgbe_ifmedia_upd, 3843 (ifm_stat_cb_t)axgbe_ifmedia_sts, BMSR_DEFCAPMASK, 3844 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG); 3845 3846 if (ret){ 3847 axgbe_printf(2, "mii attach failed with err=(%d)\n", ret); 3848 return (-EINVAL); 3849 } 3850 } 3851 3852 DBGPR("%s: return success\n", __func__); 3853 3854 return (0); 3855 } 3856 3857 void 3858 xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3859 { 3860 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3861 3862 phy_impl->init = xgbe_phy_init; 3863 phy_impl->exit = xgbe_phy_exit; 3864 3865 phy_impl->reset = xgbe_phy_reset; 3866 phy_impl->start = xgbe_phy_start; 3867 phy_impl->stop = xgbe_phy_stop; 3868 3869 phy_impl->link_status = xgbe_phy_link_status; 3870 3871 phy_impl->valid_speed = xgbe_phy_valid_speed; 3872 3873 phy_impl->use_mode = xgbe_phy_use_mode; 3874 phy_impl->set_mode = xgbe_phy_set_mode; 3875 phy_impl->get_mode = xgbe_phy_get_mode; 3876 phy_impl->switch_mode = xgbe_phy_switch_mode; 3877 phy_impl->cur_mode = xgbe_phy_cur_mode; 3878 phy_impl->get_type = xgbe_phy_get_type; 3879 3880 phy_impl->an_mode = xgbe_phy_an_mode; 3881 3882 phy_impl->an_config = xgbe_phy_an_config; 3883 3884 phy_impl->an_advertising = xgbe_phy_an_advertising; 3885 3886 phy_impl->an_outcome = xgbe_phy_an_outcome; 3887 3888 phy_impl->an_pre = xgbe_phy_an_pre; 3889 phy_impl->an_post = xgbe_phy_an_post; 3890 3891 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre; 3892 phy_impl->kr_training_post = xgbe_phy_kr_training_post; 3893 3894 phy_impl->module_info = xgbe_phy_module_info; 3895 phy_impl->module_eeprom = xgbe_phy_module_eeprom; 3896 } 3897