1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * Copyright (c) 2020 Advanced Micro Devices, Inc. 5 * 6 * This file is available to you under your choice of the following two 7 * licenses: 8 * 9 * License 1: GPLv2 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Redistribution and use in source and binary forms, with or without 60 * modification, are permitted provided that the following conditions are met: 61 * * Redistributions of source code must retain the above copyright 62 * notice, this list of conditions and the following disclaimer. 63 * * Redistributions in binary form must reproduce the above copyright 64 * notice, this list of conditions and the following disclaimer in the 65 * documentation and/or other materials provided with the distribution. 66 * * Neither the name of Advanced Micro Devices, Inc. nor the 67 * names of its contributors may be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 80 * 81 * This file incorporates work covered by the following copyright and 82 * permission notice: 83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 85 * Inc. unless otherwise expressly agreed to in writing between Synopsys 86 * and you. 87 * 88 * The Software IS NOT an item of Licensed Software or Licensed Product 89 * under any End User Software License Agreement or Agreement for Licensed 90 * Product with Synopsys or any supplement thereto. Permission is hereby 91 * granted, free of charge, to any person obtaining a copy of this software 92 * annotated with this license and the Software, to deal in the Software 93 * without restriction, including without limitation the rights to use, 94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 95 * of the Software, and to permit persons to whom the Software is furnished 96 * to do so, subject to the following conditions: 97 * 98 * The above copyright notice and this permission notice shall be included 99 * in all copies or substantial portions of the Software. 100 * 101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 111 * THE POSSIBILITY OF SUCH DAMAGE. 112 */ 113 114 #include <sys/cdefs.h> 115 __FBSDID("$FreeBSD$"); 116 117 #include "xgbe.h" 118 #include "xgbe-common.h" 119 120 struct mtx xgbe_phy_comm_lock; 121 122 #define XGBE_PHY_PORT_SPEED_100 BIT(0) 123 #define XGBE_PHY_PORT_SPEED_1000 BIT(1) 124 #define XGBE_PHY_PORT_SPEED_2500 BIT(2) 125 #define XGBE_PHY_PORT_SPEED_10000 BIT(3) 126 127 #define XGBE_MUTEX_RELEASE 0x80000000 128 129 #define XGBE_SFP_DIRECT 7 130 #define GPIO_MASK_WIDTH 4 131 132 /* I2C target addresses */ 133 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50 134 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51 135 #define XGBE_SFP_PHY_ADDRESS 0x56 136 #define XGBE_GPIO_ADDRESS_PCA9555 0x20 137 138 /* SFP sideband signal indicators */ 139 #define XGBE_GPIO_NO_TX_FAULT BIT(0) 140 #define XGBE_GPIO_NO_RATE_SELECT BIT(1) 141 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2) 142 #define XGBE_GPIO_NO_RX_LOS BIT(3) 143 144 /* Rate-change complete wait/retry count */ 145 #define XGBE_RATECHANGE_COUNT 500 146 147 /* CDR delay values for KR support (in usec) */ 148 #define XGBE_CDR_DELAY_INIT 10000 149 #define XGBE_CDR_DELAY_INC 10000 150 #define XGBE_CDR_DELAY_MAX 100000 151 152 /* RRC frequency during link status check */ 153 #define XGBE_RRC_FREQUENCY 10 154 155 enum xgbe_port_mode { 156 XGBE_PORT_MODE_RSVD = 0, 157 XGBE_PORT_MODE_BACKPLANE, 158 XGBE_PORT_MODE_BACKPLANE_2500, 159 XGBE_PORT_MODE_1000BASE_T, 160 XGBE_PORT_MODE_1000BASE_X, 161 XGBE_PORT_MODE_NBASE_T, 162 XGBE_PORT_MODE_10GBASE_T, 163 XGBE_PORT_MODE_10GBASE_R, 164 XGBE_PORT_MODE_SFP, 165 XGBE_PORT_MODE_MAX, 166 }; 167 168 enum xgbe_conn_type { 169 XGBE_CONN_TYPE_NONE = 0, 170 XGBE_CONN_TYPE_SFP, 171 XGBE_CONN_TYPE_MDIO, 172 XGBE_CONN_TYPE_RSVD1, 173 XGBE_CONN_TYPE_BACKPLANE, 174 XGBE_CONN_TYPE_MAX, 175 }; 176 177 /* SFP/SFP+ related definitions */ 178 enum xgbe_sfp_comm { 179 XGBE_SFP_COMM_DIRECT = 0, 180 XGBE_SFP_COMM_PCA9545, 181 }; 182 183 enum xgbe_sfp_cable { 184 XGBE_SFP_CABLE_UNKNOWN = 0, 185 XGBE_SFP_CABLE_ACTIVE, 186 XGBE_SFP_CABLE_PASSIVE, 187 }; 188 189 enum xgbe_sfp_base { 190 XGBE_SFP_BASE_UNKNOWN = 0, 191 XGBE_SFP_BASE_1000_T, 192 XGBE_SFP_BASE_1000_SX, 193 XGBE_SFP_BASE_1000_LX, 194 XGBE_SFP_BASE_1000_CX, 195 XGBE_SFP_BASE_10000_SR, 196 XGBE_SFP_BASE_10000_LR, 197 XGBE_SFP_BASE_10000_LRM, 198 XGBE_SFP_BASE_10000_ER, 199 XGBE_SFP_BASE_10000_CR, 200 }; 201 202 enum xgbe_sfp_speed { 203 XGBE_SFP_SPEED_UNKNOWN = 0, 204 XGBE_SFP_SPEED_100_1000, 205 XGBE_SFP_SPEED_1000, 206 XGBE_SFP_SPEED_10000, 207 }; 208 209 /* SFP Serial ID Base ID values relative to an offset of 0 */ 210 #define XGBE_SFP_BASE_ID 0 211 #define XGBE_SFP_ID_SFP 0x03 212 213 #define XGBE_SFP_BASE_EXT_ID 1 214 #define XGBE_SFP_EXT_ID_SFP 0x04 215 216 #define XGBE_SFP_BASE_CV 2 217 #define XGBE_SFP_BASE_CV_CP 0x21 218 219 #define XGBE_SFP_BASE_10GBE_CC 3 220 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4) 221 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5) 222 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 223 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7) 224 225 #define XGBE_SFP_BASE_1GBE_CC 6 226 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0) 227 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1) 228 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2) 229 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3) 230 231 #define XGBE_SFP_BASE_CABLE 8 232 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 233 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 234 235 #define XGBE_SFP_BASE_BR 12 236 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a 237 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d 238 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64 239 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68 240 241 #define XGBE_SFP_BASE_CU_CABLE_LEN 18 242 243 #define XGBE_SFP_BASE_VENDOR_NAME 20 244 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16 245 #define XGBE_SFP_BASE_VENDOR_PN 40 246 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16 247 #define XGBE_SFP_BASE_VENDOR_REV 56 248 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4 249 250 #define XGBE_SFP_BASE_CC 63 251 252 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 253 #define XGBE_SFP_BASE_VENDOR_SN 4 254 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 255 256 #define XGBE_SFP_EXTD_OPT1 1 257 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) 258 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) 259 260 #define XGBE_SFP_EXTD_DIAG 28 261 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 262 263 #define XGBE_SFP_EXTD_SFF_8472 30 264 265 #define XGBE_SFP_EXTD_CC 31 266 267 struct xgbe_sfp_eeprom { 268 uint8_t base[64]; 269 uint8_t extd[32]; 270 uint8_t vendor[32]; 271 }; 272 273 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \ 274 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \ 275 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 276 277 #define XGBE_SFP_EEPROM_BASE_LEN 256 278 #define XGBE_SFP_EEPROM_DIAG_LEN 256 279 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \ 280 XGBE_SFP_EEPROM_DIAG_LEN) 281 282 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE " 283 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 " 284 285 struct xgbe_sfp_ascii { 286 union { 287 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 288 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 289 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 290 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 291 } u; 292 }; 293 294 /* MDIO PHY reset types */ 295 enum xgbe_mdio_reset { 296 XGBE_MDIO_RESET_NONE = 0, 297 XGBE_MDIO_RESET_I2C_GPIO, 298 XGBE_MDIO_RESET_INT_GPIO, 299 XGBE_MDIO_RESET_MAX, 300 }; 301 302 /* Re-driver related definitions */ 303 enum xgbe_phy_redrv_if { 304 XGBE_PHY_REDRV_IF_MDIO = 0, 305 XGBE_PHY_REDRV_IF_I2C, 306 XGBE_PHY_REDRV_IF_MAX, 307 }; 308 309 enum xgbe_phy_redrv_model { 310 XGBE_PHY_REDRV_MODEL_4223 = 0, 311 XGBE_PHY_REDRV_MODEL_4227, 312 XGBE_PHY_REDRV_MODEL_MAX, 313 }; 314 315 enum xgbe_phy_redrv_mode { 316 XGBE_PHY_REDRV_MODE_CX = 5, 317 XGBE_PHY_REDRV_MODE_SR = 9, 318 }; 319 320 #define XGBE_PHY_REDRV_MODE_REG 0x12b0 321 322 /* PHY related configuration information */ 323 struct xgbe_phy_data { 324 enum xgbe_port_mode port_mode; 325 326 unsigned int port_id; 327 328 unsigned int port_speeds; 329 330 enum xgbe_conn_type conn_type; 331 332 enum xgbe_mode cur_mode; 333 enum xgbe_mode start_mode; 334 335 unsigned int rrc_count; 336 337 unsigned int mdio_addr; 338 339 /* SFP Support */ 340 enum xgbe_sfp_comm sfp_comm; 341 unsigned int sfp_mux_address; 342 unsigned int sfp_mux_channel; 343 344 unsigned int sfp_gpio_address; 345 unsigned int sfp_gpio_mask; 346 unsigned int sfp_gpio_inputs; 347 unsigned int sfp_gpio_rx_los; 348 unsigned int sfp_gpio_tx_fault; 349 unsigned int sfp_gpio_mod_absent; 350 unsigned int sfp_gpio_rate_select; 351 352 unsigned int sfp_rx_los; 353 unsigned int sfp_tx_fault; 354 unsigned int sfp_mod_absent; 355 unsigned int sfp_changed; 356 unsigned int sfp_phy_avail; 357 unsigned int sfp_cable_len; 358 enum xgbe_sfp_base sfp_base; 359 enum xgbe_sfp_cable sfp_cable; 360 enum xgbe_sfp_speed sfp_speed; 361 struct xgbe_sfp_eeprom sfp_eeprom; 362 363 /* External PHY support */ 364 enum xgbe_mdio_mode phydev_mode; 365 uint32_t phy_id; 366 int phydev; 367 enum xgbe_mdio_reset mdio_reset; 368 unsigned int mdio_reset_addr; 369 unsigned int mdio_reset_gpio; 370 371 /* Re-driver support */ 372 unsigned int redrv; 373 unsigned int redrv_if; 374 unsigned int redrv_addr; 375 unsigned int redrv_lane; 376 unsigned int redrv_model; 377 378 /* KR AN support */ 379 unsigned int phy_cdr_notrack; 380 unsigned int phy_cdr_delay; 381 382 uint8_t port_sfp_inputs; 383 }; 384 385 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata); 386 static int xgbe_phy_reset(struct xgbe_prv_data *pdata); 387 388 static int 389 xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *i2c_op) 390 { 391 return (pdata->i2c_if.i2c_xfer(pdata, i2c_op)); 392 } 393 394 static int 395 xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg, 396 unsigned int val) 397 { 398 struct xgbe_phy_data *phy_data = pdata->phy_data; 399 struct xgbe_i2c_op i2c_op; 400 __be16 *redrv_val; 401 uint8_t redrv_data[5], csum; 402 unsigned int i, retry; 403 int ret; 404 405 /* High byte of register contains read/write indicator */ 406 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 407 redrv_data[1] = reg & 0xff; 408 redrv_val = (__be16 *)&redrv_data[2]; 409 *redrv_val = cpu_to_be16(val); 410 411 /* Calculate 1 byte checksum */ 412 csum = 0; 413 for (i = 0; i < 4; i++) { 414 csum += redrv_data[i]; 415 if (redrv_data[i] > csum) 416 csum++; 417 } 418 redrv_data[4] = ~csum; 419 420 retry = 1; 421 again1: 422 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 423 i2c_op.target = phy_data->redrv_addr; 424 i2c_op.len = sizeof(redrv_data); 425 i2c_op.buf = redrv_data; 426 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 427 if (ret) { 428 if ((ret == -EAGAIN) && retry--) 429 goto again1; 430 431 return (ret); 432 } 433 434 retry = 1; 435 again2: 436 i2c_op.cmd = XGBE_I2C_CMD_READ; 437 i2c_op.target = phy_data->redrv_addr; 438 i2c_op.len = 1; 439 i2c_op.buf = redrv_data; 440 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 441 if (ret) { 442 if ((ret == -EAGAIN) && retry--) 443 goto again2; 444 445 return (ret); 446 } 447 448 if (redrv_data[0] != 0xff) { 449 axgbe_error("Redriver write checksum error\n"); 450 ret = -EIO; 451 } 452 453 return (ret); 454 } 455 456 static int 457 xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, void *val, 458 unsigned int val_len) 459 { 460 struct xgbe_i2c_op i2c_op; 461 int retry, ret; 462 463 retry = 1; 464 again: 465 /* Write the specfied register */ 466 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 467 i2c_op.target = target; 468 i2c_op.len = val_len; 469 i2c_op.buf = val; 470 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 471 if ((ret == -EAGAIN) && retry--) 472 goto again; 473 474 return (ret); 475 } 476 477 static int 478 xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, void *reg, 479 unsigned int reg_len, void *val, unsigned int val_len) 480 { 481 struct xgbe_i2c_op i2c_op; 482 int retry, ret; 483 484 axgbe_printf(3, "%s: target 0x%x reg_len %d val_len %d\n", __func__, 485 target, reg_len, val_len); 486 retry = 1; 487 again1: 488 /* Set the specified register to read */ 489 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 490 i2c_op.target = target; 491 i2c_op.len = reg_len; 492 i2c_op.buf = reg; 493 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 494 axgbe_printf(3, "%s: ret1 %d retry %d\n", __func__, ret, retry); 495 if (ret) { 496 if ((ret == -EAGAIN) && retry--) 497 goto again1; 498 499 return (ret); 500 } 501 502 retry = 1; 503 again2: 504 /* Read the specfied register */ 505 i2c_op.cmd = XGBE_I2C_CMD_READ; 506 i2c_op.target = target; 507 i2c_op.len = val_len; 508 i2c_op.buf = val; 509 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op); 510 axgbe_printf(3, "%s: ret2 %d retry %d\n", __func__, ret, retry); 511 if ((ret == -EAGAIN) && retry--) 512 goto again2; 513 514 return (ret); 515 } 516 517 static int 518 xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata) 519 { 520 struct xgbe_phy_data *phy_data = pdata->phy_data; 521 struct xgbe_i2c_op i2c_op; 522 uint8_t mux_channel; 523 524 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 525 return (0); 526 527 /* Select no mux channels */ 528 mux_channel = 0; 529 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 530 i2c_op.target = phy_data->sfp_mux_address; 531 i2c_op.len = sizeof(mux_channel); 532 i2c_op.buf = &mux_channel; 533 534 return (xgbe_phy_i2c_xfer(pdata, &i2c_op)); 535 } 536 537 static int 538 xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata) 539 { 540 struct xgbe_phy_data *phy_data = pdata->phy_data; 541 struct xgbe_i2c_op i2c_op; 542 uint8_t mux_channel; 543 544 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT) 545 return (0); 546 547 /* Select desired mux channel */ 548 mux_channel = 1 << phy_data->sfp_mux_channel; 549 i2c_op.cmd = XGBE_I2C_CMD_WRITE; 550 i2c_op.target = phy_data->sfp_mux_address; 551 i2c_op.len = sizeof(mux_channel); 552 i2c_op.buf = &mux_channel; 553 554 return (xgbe_phy_i2c_xfer(pdata, &i2c_op)); 555 } 556 557 static void 558 xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata) 559 { 560 mtx_unlock(&xgbe_phy_comm_lock); 561 } 562 563 static int 564 xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata) 565 { 566 struct xgbe_phy_data *phy_data = pdata->phy_data; 567 unsigned long timeout; 568 unsigned int mutex_id; 569 570 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 571 * the driver needs to take the software mutex and then the hardware 572 * mutexes before being able to use the busses. 573 */ 574 mtx_lock(&xgbe_phy_comm_lock); 575 576 /* Clear the mutexes */ 577 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE); 578 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE); 579 580 /* Mutex formats are the same for I2C and MDIO/GPIO */ 581 mutex_id = 0; 582 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 583 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 584 585 timeout = ticks + (5 * hz); 586 while (ticks < timeout) { 587 /* Must be all zeroes in order to obtain the mutex */ 588 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 589 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 590 DELAY(200); 591 continue; 592 } 593 594 /* Obtain the mutex */ 595 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 596 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 597 598 return (0); 599 } 600 601 mtx_unlock(&xgbe_phy_comm_lock); 602 603 axgbe_error("unable to obtain hardware mutexes\n"); 604 605 return (-ETIMEDOUT); 606 } 607 608 static int 609 xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, 610 uint16_t val) 611 { 612 struct xgbe_phy_data *phy_data = pdata->phy_data; 613 614 if (reg & MII_ADDR_C45) { 615 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 616 return (-ENOTSUP); 617 } else { 618 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 619 return (-ENOTSUP); 620 } 621 622 return (pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val)); 623 } 624 625 static int 626 xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, uint16_t val) 627 { 628 __be16 *mii_val; 629 uint8_t mii_data[3]; 630 int ret; 631 632 ret = xgbe_phy_sfp_get_mux(pdata); 633 if (ret) 634 return (ret); 635 636 mii_data[0] = reg & 0xff; 637 mii_val = (__be16 *)&mii_data[1]; 638 *mii_val = cpu_to_be16(val); 639 640 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS, 641 mii_data, sizeof(mii_data)); 642 643 xgbe_phy_sfp_put_mux(pdata); 644 645 return (ret); 646 } 647 648 int 649 xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, uint16_t val) 650 { 651 struct xgbe_phy_data *phy_data = pdata->phy_data; 652 int ret; 653 654 axgbe_printf(3, "%s: addr %d reg %d val %#x\n", __func__, addr, reg, val); 655 ret = xgbe_phy_get_comm_ownership(pdata); 656 if (ret) 657 return (ret); 658 659 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 660 ret = xgbe_phy_i2c_mii_write(pdata, reg, val); 661 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 662 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val); 663 else 664 ret = -ENOTSUP; 665 666 xgbe_phy_put_comm_ownership(pdata); 667 668 return (ret); 669 } 670 671 static int 672 xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, int reg) 673 { 674 struct xgbe_phy_data *phy_data = pdata->phy_data; 675 676 if (reg & MII_ADDR_C45) { 677 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45) 678 return (-ENOTSUP); 679 } else { 680 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22) 681 return (-ENOTSUP); 682 } 683 684 return (pdata->hw_if.read_ext_mii_regs(pdata, addr, reg)); 685 } 686 687 static int 688 xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg) 689 { 690 __be16 mii_val; 691 uint8_t mii_reg; 692 int ret; 693 694 ret = xgbe_phy_sfp_get_mux(pdata); 695 if (ret) 696 return (ret); 697 698 mii_reg = reg; 699 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS, 700 &mii_reg, sizeof(mii_reg), 701 &mii_val, sizeof(mii_val)); 702 if (!ret) 703 ret = be16_to_cpu(mii_val); 704 705 xgbe_phy_sfp_put_mux(pdata); 706 707 return (ret); 708 } 709 710 int 711 xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg) 712 { 713 struct xgbe_phy_data *phy_data = pdata->phy_data; 714 int ret; 715 716 axgbe_printf(3, "%s: addr %d reg %d\n", __func__, addr, reg); 717 ret = xgbe_phy_get_comm_ownership(pdata); 718 if (ret) 719 return (ret); 720 721 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 722 ret = xgbe_phy_i2c_mii_read(pdata, reg); 723 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO) 724 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg); 725 else 726 ret = -ENOTSUP; 727 728 xgbe_phy_put_comm_ownership(pdata); 729 730 return (ret); 731 } 732 733 static void 734 xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata) 735 { 736 struct xgbe_phy_data *phy_data = pdata->phy_data; 737 738 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed) 739 return; 740 741 XGBE_ZERO_SUP(&pdata->phy); 742 743 if (phy_data->sfp_mod_absent) { 744 pdata->phy.speed = SPEED_UNKNOWN; 745 pdata->phy.duplex = DUPLEX_UNKNOWN; 746 pdata->phy.autoneg = AUTONEG_ENABLE; 747 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 748 749 XGBE_SET_SUP(&pdata->phy, Autoneg); 750 XGBE_SET_SUP(&pdata->phy, Pause); 751 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 752 XGBE_SET_SUP(&pdata->phy, TP); 753 XGBE_SET_SUP(&pdata->phy, FIBRE); 754 755 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported); 756 757 return; 758 } 759 760 switch (phy_data->sfp_base) { 761 case XGBE_SFP_BASE_1000_T: 762 case XGBE_SFP_BASE_1000_SX: 763 case XGBE_SFP_BASE_1000_LX: 764 case XGBE_SFP_BASE_1000_CX: 765 pdata->phy.speed = SPEED_UNKNOWN; 766 pdata->phy.duplex = DUPLEX_UNKNOWN; 767 pdata->phy.autoneg = AUTONEG_ENABLE; 768 pdata->phy.pause_autoneg = AUTONEG_ENABLE; 769 XGBE_SET_SUP(&pdata->phy, Autoneg); 770 XGBE_SET_SUP(&pdata->phy, Pause); 771 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 772 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) { 773 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 774 XGBE_SET_SUP(&pdata->phy, 100baseT_Full); 775 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 776 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full); 777 } else { 778 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 779 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full); 780 } 781 break; 782 case XGBE_SFP_BASE_10000_SR: 783 case XGBE_SFP_BASE_10000_LR: 784 case XGBE_SFP_BASE_10000_LRM: 785 case XGBE_SFP_BASE_10000_ER: 786 case XGBE_SFP_BASE_10000_CR: 787 pdata->phy.speed = SPEED_10000; 788 pdata->phy.duplex = DUPLEX_FULL; 789 pdata->phy.autoneg = AUTONEG_DISABLE; 790 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 791 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 792 switch (phy_data->sfp_base) { 793 case XGBE_SFP_BASE_10000_SR: 794 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full); 795 break; 796 case XGBE_SFP_BASE_10000_LR: 797 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full); 798 break; 799 case XGBE_SFP_BASE_10000_LRM: 800 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full); 801 break; 802 case XGBE_SFP_BASE_10000_ER: 803 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full); 804 break; 805 case XGBE_SFP_BASE_10000_CR: 806 XGBE_SET_SUP(&pdata->phy, 10000baseCR_Full); 807 break; 808 default: 809 break; 810 } 811 } 812 break; 813 default: 814 pdata->phy.speed = SPEED_UNKNOWN; 815 pdata->phy.duplex = DUPLEX_UNKNOWN; 816 pdata->phy.autoneg = AUTONEG_DISABLE; 817 pdata->phy.pause_autoneg = AUTONEG_DISABLE; 818 break; 819 } 820 821 switch (phy_data->sfp_base) { 822 case XGBE_SFP_BASE_1000_T: 823 case XGBE_SFP_BASE_1000_CX: 824 case XGBE_SFP_BASE_10000_CR: 825 XGBE_SET_SUP(&pdata->phy, TP); 826 break; 827 default: 828 XGBE_SET_SUP(&pdata->phy, FIBRE); 829 break; 830 } 831 832 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported); 833 834 axgbe_printf(1, "%s: link speed %d spf_base 0x%x pause_autoneg %d " 835 "advert 0x%x support 0x%x\n", __func__, pdata->phy.speed, 836 phy_data->sfp_base, pdata->phy.pause_autoneg, 837 pdata->phy.advertising, pdata->phy.supported); 838 } 839 840 static bool 841 xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom, 842 enum xgbe_sfp_speed sfp_speed) 843 { 844 uint8_t *sfp_base, min, max; 845 846 sfp_base = sfp_eeprom->base; 847 848 switch (sfp_speed) { 849 case XGBE_SFP_SPEED_1000: 850 min = XGBE_SFP_BASE_BR_1GBE_MIN; 851 max = XGBE_SFP_BASE_BR_1GBE_MAX; 852 break; 853 case XGBE_SFP_SPEED_10000: 854 min = XGBE_SFP_BASE_BR_10GBE_MIN; 855 max = XGBE_SFP_BASE_BR_10GBE_MAX; 856 break; 857 default: 858 return (false); 859 } 860 861 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) && 862 (sfp_base[XGBE_SFP_BASE_BR] <= max)); 863 } 864 865 static void 866 xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata) 867 { 868 struct xgbe_phy_data *phy_data = pdata->phy_data; 869 870 if (phy_data->phydev) 871 phy_data->phydev = 0; 872 } 873 874 static bool 875 xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata) 876 { 877 struct xgbe_phy_data *phy_data = pdata->phy_data; 878 unsigned int phy_id = phy_data->phy_id; 879 880 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 881 return (false); 882 883 if ((phy_id & 0xfffffff0) != 0x01ff0cc0) 884 return (false); 885 886 /* Enable Base-T AN */ 887 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0001); 888 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140); 889 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0000); 890 891 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */ 892 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1b, 0x9084); 893 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x09, 0x0e00); 894 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x8140); 895 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x04, 0x0d01); 896 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140); 897 898 axgbe_printf(3, "Finisar PHY quirk in place\n"); 899 900 return (true); 901 } 902 903 static bool 904 xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata) 905 { 906 struct xgbe_phy_data *phy_data = pdata->phy_data; 907 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 908 unsigned int phy_id = phy_data->phy_id; 909 int reg; 910 911 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 912 return (false); 913 914 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 915 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN)) 916 return (false); 917 918 /* For Bel-Fuse, use the extra AN flag */ 919 pdata->an_again = 1; 920 921 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 922 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN)) 923 return (false); 924 925 if ((phy_id & 0xfffffff0) != 0x03625d10) 926 return (false); 927 928 /* Disable RGMII mode */ 929 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, 0x7007); 930 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18); 931 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080); 932 933 /* Enable fiber register bank */ 934 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00); 935 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c); 936 reg &= 0x03ff; 937 reg &= ~0x0001; 938 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 | 939 reg | 0x0001); 940 941 /* Power down SerDes */ 942 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00); 943 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800); 944 945 /* Configure SGMII-to-Copper mode */ 946 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00); 947 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c); 948 reg &= 0x03ff; 949 reg &= ~0x0006; 950 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 | 951 reg | 0x0004); 952 953 /* Power up SerDes */ 954 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00); 955 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800); 956 957 /* Enable copper register bank */ 958 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00); 959 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c); 960 reg &= 0x03ff; 961 reg &= ~0x0001; 962 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 | 963 reg); 964 965 /* Power up SerDes */ 966 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00); 967 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800); 968 969 axgbe_printf(3, "BelFuse PHY quirk in place\n"); 970 971 return (true); 972 } 973 974 static void 975 xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata) 976 { 977 if (xgbe_phy_belfuse_phy_quirks(pdata)) 978 return; 979 980 if (xgbe_phy_finisar_phy_quirks(pdata)) 981 return; 982 } 983 984 static int 985 xgbe_get_phy_id(struct xgbe_prv_data *pdata) 986 { 987 struct xgbe_phy_data *phy_data = pdata->phy_data; 988 uint32_t oui, model, phy_id1, phy_id2; 989 int phy_reg; 990 991 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x02); 992 if (phy_reg < 0) 993 return (-EIO); 994 995 phy_id1 = (phy_reg & 0xffff); 996 phy_data->phy_id = (phy_reg & 0xffff) << 16; 997 998 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x03); 999 if (phy_reg < 0) 1000 return (-EIO); 1001 1002 phy_id2 = (phy_reg & 0xffff); 1003 phy_data->phy_id |= (phy_reg & 0xffff); 1004 1005 oui = MII_OUI(phy_id1, phy_id2); 1006 model = MII_MODEL(phy_id2); 1007 1008 axgbe_printf(2, "%s: phy_id1: 0x%x phy_id2: 0x%x oui: %#x model %#x\n", 1009 __func__, phy_id1, phy_id2, oui, model); 1010 1011 return (0); 1012 } 1013 1014 static int 1015 xgbe_phy_start_aneg(struct xgbe_prv_data *pdata) 1016 { 1017 uint16_t ctl = 0; 1018 int changed = 0; 1019 int ret; 1020 1021 if (AUTONEG_ENABLE != pdata->phy.autoneg) { 1022 if (SPEED_1000 == pdata->phy.speed) 1023 ctl |= BMCR_SPEED1; 1024 else if (SPEED_100 == pdata->phy.speed) 1025 ctl |= BMCR_SPEED100; 1026 1027 if (DUPLEX_FULL == pdata->phy.duplex) 1028 ctl |= BMCR_FDX; 1029 1030 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR); 1031 if (ret) 1032 return (ret); 1033 1034 ret = xgbe_phy_mii_write(pdata, pdata->mdio_addr, MII_BMCR, 1035 (ret & ~(~(BMCR_LOOP | BMCR_ISO | BMCR_PDOWN))) | ctl); 1036 } 1037 1038 ctl = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR); 1039 if (ctl < 0) 1040 return (ctl); 1041 1042 if (!(ctl & BMCR_AUTOEN) || (ctl & BMCR_ISO)) 1043 changed = 1; 1044 1045 if (changed > 0) { 1046 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR); 1047 if (ret) 1048 return (ret); 1049 1050 ret = xgbe_phy_mii_write(pdata, pdata->mdio_addr, MII_BMCR, 1051 (ret & ~(BMCR_ISO)) | (BMCR_AUTOEN | BMCR_STARTNEG)); 1052 } 1053 1054 return (0); 1055 } 1056 1057 static int 1058 xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata) 1059 { 1060 struct xgbe_phy_data *phy_data = pdata->phy_data; 1061 int ret; 1062 1063 axgbe_printf(2, "%s: phydev %d phydev_mode %d sfp_phy_avail %d phy_id " 1064 "0x%08x\n", __func__, phy_data->phydev, phy_data->phydev_mode, 1065 phy_data->sfp_phy_avail, phy_data->phy_id); 1066 1067 /* If we already have a PHY, just return */ 1068 if (phy_data->phydev) { 1069 axgbe_printf(3, "%s: phy present already\n", __func__); 1070 return (0); 1071 } 1072 1073 /* Clear the extra AN flag */ 1074 pdata->an_again = 0; 1075 1076 /* Check for the use of an external PHY */ 1077 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) { 1078 axgbe_printf(3, "%s: phydev_mode %d\n", __func__, 1079 phy_data->phydev_mode); 1080 return (0); 1081 } 1082 1083 /* For SFP, only use an external PHY if available */ 1084 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 1085 !phy_data->sfp_phy_avail) { 1086 axgbe_printf(3, "%s: port_mode %d avail %d\n", __func__, 1087 phy_data->port_mode, phy_data->sfp_phy_avail); 1088 return (0); 1089 } 1090 1091 /* Set the proper MDIO mode for the PHY */ 1092 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 1093 phy_data->phydev_mode); 1094 if (ret) { 1095 axgbe_error("mdio port/clause not compatible (%u/%u) ret %d\n", 1096 phy_data->mdio_addr, phy_data->phydev_mode, ret); 1097 return (ret); 1098 } 1099 1100 ret = xgbe_get_phy_id(pdata); 1101 if (ret) 1102 return (ret); 1103 axgbe_printf(2, "Get phy_id 0x%08x\n", phy_data->phy_id); 1104 1105 phy_data->phydev = 1; 1106 xgbe_phy_external_phy_quirks(pdata); 1107 xgbe_phy_start_aneg(pdata); 1108 1109 return (0); 1110 } 1111 1112 static void 1113 xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) 1114 { 1115 struct xgbe_phy_data *phy_data = pdata->phy_data; 1116 int ret; 1117 1118 axgbe_printf(3, "%s: sfp_changed: 0x%x\n", __func__, 1119 phy_data->sfp_changed); 1120 if (!phy_data->sfp_changed) 1121 return; 1122 1123 phy_data->sfp_phy_avail = 0; 1124 1125 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 1126 return; 1127 1128 /* Check access to the PHY by reading CTRL1 */ 1129 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR); 1130 if (ret < 0) { 1131 axgbe_error("%s: ext phy fail %d\n", __func__, ret); 1132 return; 1133 } 1134 1135 /* Successfully accessed the PHY */ 1136 phy_data->sfp_phy_avail = 1; 1137 axgbe_printf(3, "Successfully accessed External PHY\n"); 1138 } 1139 1140 static bool 1141 xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) 1142 { 1143 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd; 1144 1145 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) 1146 return (false); 1147 1148 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) 1149 return (false); 1150 1151 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) 1152 return (true); 1153 1154 return (false); 1155 } 1156 1157 static bool 1158 xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) 1159 { 1160 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd; 1161 1162 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) 1163 return (false); 1164 1165 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) 1166 return (false); 1167 1168 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) 1169 return (true); 1170 1171 return (false); 1172 } 1173 1174 static bool 1175 xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) 1176 { 1177 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) 1178 return (false); 1179 1180 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) 1181 return (true); 1182 1183 return (false); 1184 } 1185 1186 static void 1187 xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) 1188 { 1189 struct xgbe_phy_data *phy_data = pdata->phy_data; 1190 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 1191 uint8_t *sfp_base; 1192 1193 sfp_base = sfp_eeprom->base; 1194 1195 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) { 1196 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_ID]); 1197 return; 1198 } 1199 1200 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) { 1201 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_EXT_ID]); 1202 return; 1203 } 1204 1205 /* Update transceiver signals (eeprom extd/options) */ 1206 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); 1207 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); 1208 1209 /* Assume ACTIVE cable unless told it is PASSIVE */ 1210 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) { 1211 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE; 1212 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN]; 1213 } else 1214 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE; 1215 1216 /* 1217 * Determine the type of SFP. Certain 10G SFP+ modules read as 1218 * 1000BASE-CX. To prevent 10G DAC cables to be recognized as 1219 * 1G, we first check if it is a DAC and the bitrate is 10G. 1220 */ 1221 if (((sfp_base[XGBE_SFP_BASE_CV] & XGBE_SFP_BASE_CV_CP) || 1222 (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE)) && 1223 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000)) 1224 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR; 1225 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR) 1226 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR; 1227 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR) 1228 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR; 1229 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM) 1230 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM; 1231 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER) 1232 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER; 1233 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX) 1234 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX; 1235 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX) 1236 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX; 1237 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX) 1238 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX; 1239 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T) 1240 phy_data->sfp_base = XGBE_SFP_BASE_1000_T; 1241 1242 switch (phy_data->sfp_base) { 1243 case XGBE_SFP_BASE_1000_T: 1244 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000; 1245 break; 1246 case XGBE_SFP_BASE_1000_SX: 1247 case XGBE_SFP_BASE_1000_LX: 1248 case XGBE_SFP_BASE_1000_CX: 1249 phy_data->sfp_speed = XGBE_SFP_SPEED_1000; 1250 break; 1251 case XGBE_SFP_BASE_10000_SR: 1252 case XGBE_SFP_BASE_10000_LR: 1253 case XGBE_SFP_BASE_10000_LRM: 1254 case XGBE_SFP_BASE_10000_ER: 1255 case XGBE_SFP_BASE_10000_CR: 1256 phy_data->sfp_speed = XGBE_SFP_SPEED_10000; 1257 break; 1258 default: 1259 break; 1260 } 1261 axgbe_printf(3, "%s: sfp_base: 0x%x sfp_speed: 0x%x sfp_cable: 0x%x " 1262 "rx_los 0x%x tx_fault 0x%x\n", __func__, phy_data->sfp_base, 1263 phy_data->sfp_speed, phy_data->sfp_cable, phy_data->sfp_rx_los, 1264 phy_data->sfp_tx_fault); 1265 } 1266 1267 static void 1268 xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata, 1269 struct xgbe_sfp_eeprom *sfp_eeprom) 1270 { 1271 struct xgbe_sfp_ascii sfp_ascii; 1272 char *sfp_data = (char *)&sfp_ascii; 1273 1274 axgbe_printf(3, "SFP detected:\n"); 1275 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME], 1276 XGBE_SFP_BASE_VENDOR_NAME_LEN); 1277 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0'; 1278 axgbe_printf(3, " vendor: %s\n", 1279 sfp_data); 1280 1281 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN], 1282 XGBE_SFP_BASE_VENDOR_PN_LEN); 1283 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0'; 1284 axgbe_printf(3, " part number: %s\n", 1285 sfp_data); 1286 1287 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV], 1288 XGBE_SFP_BASE_VENDOR_REV_LEN); 1289 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0'; 1290 axgbe_printf(3, " revision level: %s\n", 1291 sfp_data); 1292 1293 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN], 1294 XGBE_SFP_BASE_VENDOR_SN_LEN); 1295 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0'; 1296 axgbe_printf(3, " serial number: %s\n", 1297 sfp_data); 1298 } 1299 1300 static bool 1301 xgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, unsigned int len) 1302 { 1303 uint8_t cc; 1304 1305 for (cc = 0; len; buf++, len--) 1306 cc += *buf; 1307 1308 return ((cc == cc_in) ? true : false); 1309 } 1310 1311 static void 1312 dump_sfp_eeprom(struct xgbe_prv_data *pdata, uint8_t *sfp_base) 1313 { 1314 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_ID] : 0x%04x\n", 1315 sfp_base[XGBE_SFP_BASE_ID]); 1316 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_EXT_ID] : 0x%04x\n", 1317 sfp_base[XGBE_SFP_BASE_EXT_ID]); 1318 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_CABLE] : 0x%04x\n", 1319 sfp_base[XGBE_SFP_BASE_CABLE]); 1320 } 1321 1322 static int 1323 xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) 1324 { 1325 struct xgbe_phy_data *phy_data = pdata->phy_data; 1326 struct xgbe_sfp_eeprom sfp_eeprom, *eeprom; 1327 uint8_t eeprom_addr, *base; 1328 int ret; 1329 1330 ret = xgbe_phy_sfp_get_mux(pdata); 1331 if (ret) { 1332 axgbe_error("I2C error setting SFP MUX\n"); 1333 return (ret); 1334 } 1335 1336 /* Read the SFP serial ID eeprom */ 1337 eeprom_addr = 0; 1338 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1339 &eeprom_addr, sizeof(eeprom_addr), 1340 &sfp_eeprom, sizeof(sfp_eeprom)); 1341 1342 eeprom = &sfp_eeprom; 1343 base = eeprom->base; 1344 dump_sfp_eeprom(pdata, base); 1345 if (ret) { 1346 axgbe_error("I2C error reading SFP EEPROM\n"); 1347 goto put; 1348 } 1349 1350 /* Validate the contents read */ 1351 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC], 1352 sfp_eeprom.base, sizeof(sfp_eeprom.base) - 1)) { 1353 axgbe_error("verify eeprom base failed\n"); 1354 ret = -EINVAL; 1355 goto put; 1356 } 1357 1358 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC], 1359 sfp_eeprom.extd, sizeof(sfp_eeprom.extd) - 1)) { 1360 axgbe_error("verify eeprom extd failed\n"); 1361 ret = -EINVAL; 1362 goto put; 1363 } 1364 1365 /* Check for an added or changed SFP */ 1366 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 1367 phy_data->sfp_changed = 1; 1368 1369 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom); 1370 1371 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 1372 1373 xgbe_phy_free_phy_device(pdata); 1374 } else 1375 phy_data->sfp_changed = 0; 1376 1377 put: 1378 xgbe_phy_sfp_put_mux(pdata); 1379 1380 return (ret); 1381 } 1382 1383 static void 1384 xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) 1385 { 1386 struct xgbe_phy_data *phy_data = pdata->phy_data; 1387 uint8_t gpio_reg, gpio_ports[2]; 1388 int ret, prev_sfp_inputs = phy_data->port_sfp_inputs; 1389 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id); 1390 1391 /* Read the input port registers */ 1392 axgbe_printf(3, "%s: befor sfp_mod:%d sfp_gpio_address:0x%x\n", 1393 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_address); 1394 1395 gpio_reg = 0; 1396 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, &gpio_reg, 1397 sizeof(gpio_reg), gpio_ports, sizeof(gpio_ports)); 1398 if (ret) { 1399 axgbe_error("%s: I2C error reading SFP GPIO addr:0x%x\n", 1400 __func__, phy_data->sfp_gpio_address); 1401 return; 1402 } 1403 1404 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; 1405 phy_data->port_sfp_inputs = (phy_data->sfp_gpio_inputs >> shift) & 0x0F; 1406 1407 if (prev_sfp_inputs != phy_data->port_sfp_inputs) 1408 axgbe_printf(0, "%s: port_sfp_inputs: 0x%0x\n", __func__, 1409 phy_data->port_sfp_inputs); 1410 1411 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); 1412 1413 axgbe_printf(3, "%s: after sfp_mod:%d sfp_gpio_inputs:0x%x\n", 1414 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_inputs); 1415 } 1416 1417 static void 1418 xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) 1419 { 1420 struct xgbe_phy_data *phy_data = pdata->phy_data; 1421 1422 xgbe_phy_free_phy_device(pdata); 1423 1424 phy_data->sfp_mod_absent = 1; 1425 phy_data->sfp_phy_avail = 0; 1426 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 1427 } 1428 1429 static void 1430 xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data) 1431 { 1432 phy_data->sfp_rx_los = 0; 1433 phy_data->sfp_tx_fault = 0; 1434 phy_data->sfp_mod_absent = 1; 1435 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN; 1436 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN; 1437 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN; 1438 } 1439 1440 static void 1441 xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata) 1442 { 1443 struct xgbe_phy_data *phy_data = pdata->phy_data; 1444 int ret, prev_sfp_state = phy_data->sfp_mod_absent; 1445 1446 /* Reset the SFP signals and info */ 1447 xgbe_phy_sfp_reset(phy_data); 1448 1449 ret = xgbe_phy_get_comm_ownership(pdata); 1450 if (ret) 1451 return; 1452 1453 /* Read the SFP signals and check for module presence */ 1454 xgbe_phy_sfp_signals(pdata); 1455 if (phy_data->sfp_mod_absent) { 1456 if (prev_sfp_state != phy_data->sfp_mod_absent) 1457 axgbe_error("%s: mod absent\n", __func__); 1458 xgbe_phy_sfp_mod_absent(pdata); 1459 goto put; 1460 } 1461 1462 ret = xgbe_phy_sfp_read_eeprom(pdata); 1463 if (ret) { 1464 /* Treat any error as if there isn't an SFP plugged in */ 1465 axgbe_error("%s: eeprom read failed\n", __func__); 1466 xgbe_phy_sfp_reset(phy_data); 1467 xgbe_phy_sfp_mod_absent(pdata); 1468 goto put; 1469 } 1470 1471 xgbe_phy_sfp_parse_eeprom(pdata); 1472 1473 xgbe_phy_sfp_external_phy(pdata); 1474 1475 put: 1476 xgbe_phy_sfp_phy_settings(pdata); 1477 1478 axgbe_printf(3, "%s: phy speed: 0x%x duplex: 0x%x autoneg: 0x%x " 1479 "pause_autoneg: 0x%x\n", __func__, pdata->phy.speed, 1480 pdata->phy.duplex, pdata->phy.autoneg, pdata->phy.pause_autoneg); 1481 1482 xgbe_phy_put_comm_ownership(pdata); 1483 } 1484 1485 static int 1486 xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata) 1487 { 1488 struct xgbe_phy_data *phy_data = pdata->phy_data; 1489 uint8_t eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX]; 1490 struct xgbe_sfp_eeprom *sfp_eeprom; 1491 int ret; 1492 1493 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 1494 ret = -ENXIO; 1495 goto done; 1496 } 1497 1498 if (phy_data->sfp_mod_absent) { 1499 ret = -EIO; 1500 goto done; 1501 } 1502 1503 ret = xgbe_phy_get_comm_ownership(pdata); 1504 if (ret) { 1505 ret = -EIO; 1506 goto done; 1507 } 1508 1509 ret = xgbe_phy_sfp_get_mux(pdata); 1510 if (ret) { 1511 axgbe_error("I2C error setting SFP MUX\n"); 1512 ret = -EIO; 1513 goto put_own; 1514 } 1515 1516 /* Read the SFP serial ID eeprom */ 1517 eeprom_addr = 0; 1518 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS, 1519 &eeprom_addr, sizeof(eeprom_addr), 1520 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN); 1521 if (ret) { 1522 axgbe_error("I2C error reading SFP EEPROM\n"); 1523 ret = -EIO; 1524 goto put_mux; 1525 } 1526 1527 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data; 1528 1529 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) { 1530 /* Read the SFP diagnostic eeprom */ 1531 eeprom_addr = 0; 1532 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS, 1533 &eeprom_addr, sizeof(eeprom_addr), 1534 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN, 1535 XGBE_SFP_EEPROM_DIAG_LEN); 1536 if (ret) { 1537 axgbe_error("I2C error reading SFP DIAGS\n"); 1538 ret = -EIO; 1539 goto put_mux; 1540 } 1541 } 1542 1543 put_mux: 1544 xgbe_phy_sfp_put_mux(pdata); 1545 1546 put_own: 1547 xgbe_phy_put_comm_ownership(pdata); 1548 1549 done: 1550 return (ret); 1551 } 1552 1553 static int 1554 xgbe_phy_module_info(struct xgbe_prv_data *pdata) 1555 { 1556 struct xgbe_phy_data *phy_data = pdata->phy_data; 1557 1558 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) 1559 return (-ENXIO); 1560 1561 if (phy_data->sfp_mod_absent) 1562 return (-EIO); 1563 1564 return (0); 1565 } 1566 1567 static void 1568 xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata) 1569 { 1570 struct xgbe_phy_data *phy_data = pdata->phy_data; 1571 1572 pdata->phy.tx_pause = 0; 1573 pdata->phy.rx_pause = 0; 1574 1575 if (!phy_data->phydev) 1576 return; 1577 1578 if (pdata->phy.pause) 1579 XGBE_SET_LP_ADV(&pdata->phy, Pause); 1580 1581 if (pdata->phy.asym_pause) 1582 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause); 1583 1584 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, 1585 pdata->phy.tx_pause, pdata->phy.rx_pause); 1586 } 1587 1588 static enum xgbe_mode 1589 xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata) 1590 { 1591 enum xgbe_mode mode; 1592 1593 XGBE_SET_LP_ADV(&pdata->phy, Autoneg); 1594 XGBE_SET_LP_ADV(&pdata->phy, TP); 1595 1596 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__, 1597 pdata->phy.pause_autoneg); 1598 1599 /* Use external PHY to determine flow control */ 1600 if (pdata->phy.pause_autoneg) 1601 xgbe_phy_phydev_flowctrl(pdata); 1602 1603 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) { 1604 case XGBE_SGMII_AN_LINK_SPEED_100: 1605 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1606 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Full); 1607 mode = XGBE_MODE_SGMII_100; 1608 } else { 1609 /* Half-duplex not supported */ 1610 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Half); 1611 mode = XGBE_MODE_UNKNOWN; 1612 } 1613 break; 1614 case XGBE_SGMII_AN_LINK_SPEED_1000: 1615 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) { 1616 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Full); 1617 mode = XGBE_MODE_SGMII_1000; 1618 } else { 1619 /* Half-duplex not supported */ 1620 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Half); 1621 mode = XGBE_MODE_UNKNOWN; 1622 } 1623 break; 1624 default: 1625 mode = XGBE_MODE_UNKNOWN; 1626 } 1627 1628 return (mode); 1629 } 1630 1631 static enum xgbe_mode 1632 xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata) 1633 { 1634 enum xgbe_mode mode; 1635 unsigned int ad_reg, lp_reg; 1636 1637 XGBE_SET_LP_ADV(&pdata->phy, Autoneg); 1638 XGBE_SET_LP_ADV(&pdata->phy, FIBRE); 1639 1640 /* Compare Advertisement and Link Partner register */ 1641 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); 1642 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); 1643 if (lp_reg & 0x100) 1644 XGBE_SET_LP_ADV(&pdata->phy, Pause); 1645 if (lp_reg & 0x80) 1646 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause); 1647 1648 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n", 1649 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg); 1650 1651 if (pdata->phy.pause_autoneg) { 1652 /* Set flow control based on auto-negotiation result */ 1653 pdata->phy.tx_pause = 0; 1654 pdata->phy.rx_pause = 0; 1655 1656 if (ad_reg & lp_reg & 0x100) { 1657 pdata->phy.tx_pause = 1; 1658 pdata->phy.rx_pause = 1; 1659 } else if (ad_reg & lp_reg & 0x80) { 1660 if (ad_reg & 0x100) 1661 pdata->phy.rx_pause = 1; 1662 else if (lp_reg & 0x100) 1663 pdata->phy.tx_pause = 1; 1664 } 1665 } 1666 1667 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause, 1668 pdata->phy.rx_pause); 1669 1670 if (lp_reg & 0x20) 1671 XGBE_SET_LP_ADV(&pdata->phy, 1000baseX_Full); 1672 1673 /* Half duplex is not supported */ 1674 ad_reg &= lp_reg; 1675 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN; 1676 1677 return (mode); 1678 } 1679 1680 static enum xgbe_mode 1681 xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata) 1682 { 1683 struct xgbe_phy_data *phy_data = pdata->phy_data; 1684 enum xgbe_mode mode; 1685 unsigned int ad_reg, lp_reg; 1686 1687 XGBE_SET_LP_ADV(&pdata->phy, Autoneg); 1688 XGBE_SET_LP_ADV(&pdata->phy, Backplane); 1689 1690 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__, 1691 pdata->phy.pause_autoneg); 1692 1693 /* Use external PHY to determine flow control */ 1694 if (pdata->phy.pause_autoneg) 1695 xgbe_phy_phydev_flowctrl(pdata); 1696 1697 /* Compare Advertisement and Link Partner register 2 */ 1698 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1699 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1700 if (lp_reg & 0x80) 1701 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full); 1702 if (lp_reg & 0x20) 1703 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full); 1704 1705 ad_reg &= lp_reg; 1706 if (ad_reg & 0x80) { 1707 switch (phy_data->port_mode) { 1708 case XGBE_PORT_MODE_BACKPLANE: 1709 mode = XGBE_MODE_KR; 1710 break; 1711 default: 1712 mode = XGBE_MODE_SFI; 1713 break; 1714 } 1715 } else if (ad_reg & 0x20) { 1716 switch (phy_data->port_mode) { 1717 case XGBE_PORT_MODE_BACKPLANE: 1718 mode = XGBE_MODE_KX_1000; 1719 break; 1720 case XGBE_PORT_MODE_1000BASE_X: 1721 mode = XGBE_MODE_X; 1722 break; 1723 case XGBE_PORT_MODE_SFP: 1724 switch (phy_data->sfp_base) { 1725 case XGBE_SFP_BASE_1000_T: 1726 if ((phy_data->phydev) && 1727 (pdata->phy.speed == SPEED_100)) 1728 mode = XGBE_MODE_SGMII_100; 1729 else 1730 mode = XGBE_MODE_SGMII_1000; 1731 break; 1732 case XGBE_SFP_BASE_1000_SX: 1733 case XGBE_SFP_BASE_1000_LX: 1734 case XGBE_SFP_BASE_1000_CX: 1735 default: 1736 mode = XGBE_MODE_X; 1737 break; 1738 } 1739 break; 1740 default: 1741 if ((phy_data->phydev) && 1742 (pdata->phy.speed == SPEED_100)) 1743 mode = XGBE_MODE_SGMII_100; 1744 else 1745 mode = XGBE_MODE_SGMII_1000; 1746 break; 1747 } 1748 } else { 1749 mode = XGBE_MODE_UNKNOWN; 1750 } 1751 1752 /* Compare Advertisement and Link Partner register 3 */ 1753 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1754 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1755 if (lp_reg & 0xc000) 1756 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC); 1757 1758 return (mode); 1759 } 1760 1761 static enum xgbe_mode 1762 xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata) 1763 { 1764 enum xgbe_mode mode; 1765 unsigned int ad_reg, lp_reg; 1766 1767 XGBE_SET_LP_ADV(&pdata->phy, Autoneg); 1768 XGBE_SET_LP_ADV(&pdata->phy, Backplane); 1769 1770 /* Compare Advertisement and Link Partner register 1 */ 1771 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 1772 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 1773 if (lp_reg & 0x400) 1774 XGBE_SET_LP_ADV(&pdata->phy, Pause); 1775 if (lp_reg & 0x800) 1776 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause); 1777 1778 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n", 1779 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg); 1780 1781 if (pdata->phy.pause_autoneg) { 1782 /* Set flow control based on auto-negotiation result */ 1783 pdata->phy.tx_pause = 0; 1784 pdata->phy.rx_pause = 0; 1785 1786 if (ad_reg & lp_reg & 0x400) { 1787 pdata->phy.tx_pause = 1; 1788 pdata->phy.rx_pause = 1; 1789 } else if (ad_reg & lp_reg & 0x800) { 1790 if (ad_reg & 0x400) 1791 pdata->phy.rx_pause = 1; 1792 else if (lp_reg & 0x400) 1793 pdata->phy.tx_pause = 1; 1794 } 1795 } 1796 1797 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause, 1798 pdata->phy.rx_pause); 1799 1800 /* Compare Advertisement and Link Partner register 2 */ 1801 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 1802 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 1803 if (lp_reg & 0x80) 1804 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full); 1805 if (lp_reg & 0x20) 1806 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full); 1807 1808 ad_reg &= lp_reg; 1809 if (ad_reg & 0x80) 1810 mode = XGBE_MODE_KR; 1811 else if (ad_reg & 0x20) 1812 mode = XGBE_MODE_KX_1000; 1813 else 1814 mode = XGBE_MODE_UNKNOWN; 1815 1816 /* Compare Advertisement and Link Partner register 3 */ 1817 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 1818 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 1819 if (lp_reg & 0xc000) 1820 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC); 1821 1822 return (mode); 1823 } 1824 1825 static enum xgbe_mode 1826 xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) 1827 { 1828 switch (pdata->an_mode) { 1829 case XGBE_AN_MODE_CL73: 1830 return (xgbe_phy_an73_outcome(pdata)); 1831 case XGBE_AN_MODE_CL73_REDRV: 1832 return (xgbe_phy_an73_redrv_outcome(pdata)); 1833 case XGBE_AN_MODE_CL37: 1834 return (xgbe_phy_an37_outcome(pdata)); 1835 case XGBE_AN_MODE_CL37_SGMII: 1836 return (xgbe_phy_an37_sgmii_outcome(pdata)); 1837 default: 1838 return (XGBE_MODE_UNKNOWN); 1839 } 1840 } 1841 1842 static void 1843 xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy) 1844 { 1845 struct xgbe_phy_data *phy_data = pdata->phy_data; 1846 1847 XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising); 1848 1849 /* Without a re-driver, just return current advertising */ 1850 if (!phy_data->redrv) 1851 return; 1852 1853 /* With the KR re-driver we need to advertise a single speed */ 1854 XGBE_CLR_ADV(dphy, 1000baseKX_Full); 1855 XGBE_CLR_ADV(dphy, 10000baseKR_Full); 1856 1857 /* Advertise FEC support is present */ 1858 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 1859 XGBE_SET_ADV(dphy, 10000baseR_FEC); 1860 1861 switch (phy_data->port_mode) { 1862 case XGBE_PORT_MODE_BACKPLANE: 1863 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1864 break; 1865 case XGBE_PORT_MODE_BACKPLANE_2500: 1866 XGBE_SET_ADV(dphy, 1000baseKX_Full); 1867 break; 1868 case XGBE_PORT_MODE_1000BASE_T: 1869 case XGBE_PORT_MODE_1000BASE_X: 1870 case XGBE_PORT_MODE_NBASE_T: 1871 XGBE_SET_ADV(dphy, 1000baseKX_Full); 1872 break; 1873 case XGBE_PORT_MODE_10GBASE_T: 1874 if ((phy_data->phydev) && 1875 (pdata->phy.speed == SPEED_10000)) 1876 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1877 else 1878 XGBE_SET_ADV(dphy, 1000baseKX_Full); 1879 break; 1880 case XGBE_PORT_MODE_10GBASE_R: 1881 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1882 break; 1883 case XGBE_PORT_MODE_SFP: 1884 switch (phy_data->sfp_base) { 1885 case XGBE_SFP_BASE_1000_T: 1886 case XGBE_SFP_BASE_1000_SX: 1887 case XGBE_SFP_BASE_1000_LX: 1888 case XGBE_SFP_BASE_1000_CX: 1889 XGBE_SET_ADV(dphy, 1000baseKX_Full); 1890 break; 1891 default: 1892 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1893 break; 1894 } 1895 break; 1896 default: 1897 XGBE_SET_ADV(dphy, 10000baseKR_Full); 1898 break; 1899 } 1900 } 1901 1902 static int 1903 xgbe_phy_an_config(struct xgbe_prv_data *pdata) 1904 { 1905 struct xgbe_phy_data *phy_data = pdata->phy_data; 1906 int ret; 1907 1908 ret = xgbe_phy_find_phy_device(pdata); 1909 if (ret) 1910 return (ret); 1911 1912 axgbe_printf(2, "%s: find_phy_device return %s.\n", __func__, 1913 ret ? "Failure" : "Success"); 1914 1915 if (!phy_data->phydev) 1916 return (0); 1917 1918 ret = xgbe_phy_start_aneg(pdata); 1919 return (ret); 1920 } 1921 1922 static enum xgbe_an_mode 1923 xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data) 1924 { 1925 switch (phy_data->sfp_base) { 1926 case XGBE_SFP_BASE_1000_T: 1927 return (XGBE_AN_MODE_CL37_SGMII); 1928 case XGBE_SFP_BASE_1000_SX: 1929 case XGBE_SFP_BASE_1000_LX: 1930 case XGBE_SFP_BASE_1000_CX: 1931 return (XGBE_AN_MODE_CL37); 1932 default: 1933 return (XGBE_AN_MODE_NONE); 1934 } 1935 } 1936 1937 static enum xgbe_an_mode 1938 xgbe_phy_an_mode(struct xgbe_prv_data *pdata) 1939 { 1940 struct xgbe_phy_data *phy_data = pdata->phy_data; 1941 1942 /* A KR re-driver will always require CL73 AN */ 1943 if (phy_data->redrv) 1944 return (XGBE_AN_MODE_CL73_REDRV); 1945 1946 switch (phy_data->port_mode) { 1947 case XGBE_PORT_MODE_BACKPLANE: 1948 return (XGBE_AN_MODE_CL73); 1949 case XGBE_PORT_MODE_BACKPLANE_2500: 1950 return (XGBE_AN_MODE_NONE); 1951 case XGBE_PORT_MODE_1000BASE_T: 1952 return (XGBE_AN_MODE_CL37_SGMII); 1953 case XGBE_PORT_MODE_1000BASE_X: 1954 return (XGBE_AN_MODE_CL37); 1955 case XGBE_PORT_MODE_NBASE_T: 1956 return (XGBE_AN_MODE_CL37_SGMII); 1957 case XGBE_PORT_MODE_10GBASE_T: 1958 return (XGBE_AN_MODE_CL73); 1959 case XGBE_PORT_MODE_10GBASE_R: 1960 return (XGBE_AN_MODE_NONE); 1961 case XGBE_PORT_MODE_SFP: 1962 return (xgbe_phy_an_sfp_mode(phy_data)); 1963 default: 1964 return (XGBE_AN_MODE_NONE); 1965 } 1966 } 1967 1968 static int 1969 xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata, 1970 enum xgbe_phy_redrv_mode mode) 1971 { 1972 struct xgbe_phy_data *phy_data = pdata->phy_data; 1973 uint16_t redrv_reg, redrv_val; 1974 1975 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1976 redrv_val = (uint16_t)mode; 1977 1978 return (pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1979 redrv_reg, redrv_val)); 1980 } 1981 1982 static int 1983 xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata, 1984 enum xgbe_phy_redrv_mode mode) 1985 { 1986 struct xgbe_phy_data *phy_data = pdata->phy_data; 1987 unsigned int redrv_reg; 1988 int ret; 1989 1990 /* Calculate the register to write */ 1991 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1992 1993 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode); 1994 1995 return (ret); 1996 } 1997 1998 static void 1999 xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata) 2000 { 2001 struct xgbe_phy_data *phy_data = pdata->phy_data; 2002 enum xgbe_phy_redrv_mode mode; 2003 int ret; 2004 2005 if (!phy_data->redrv) 2006 return; 2007 2008 mode = XGBE_PHY_REDRV_MODE_CX; 2009 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) && 2010 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) && 2011 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR)) 2012 mode = XGBE_PHY_REDRV_MODE_SR; 2013 2014 ret = xgbe_phy_get_comm_ownership(pdata); 2015 if (ret) 2016 return; 2017 2018 axgbe_printf(2, "%s: redrv_if set: %d\n", __func__, phy_data->redrv_if); 2019 if (phy_data->redrv_if) 2020 xgbe_phy_set_redrv_mode_i2c(pdata, mode); 2021 else 2022 xgbe_phy_set_redrv_mode_mdio(pdata, mode); 2023 2024 xgbe_phy_put_comm_ownership(pdata); 2025 } 2026 2027 static void 2028 xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, unsigned int cmd, 2029 unsigned int sub_cmd) 2030 { 2031 unsigned int s0 = 0; 2032 unsigned int wait; 2033 2034 /* Log if a previous command did not complete */ 2035 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 2036 axgbe_error("firmware mailbox not ready for command\n"); 2037 2038 /* Construct the command */ 2039 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 2040 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 2041 2042 /* Issue the command */ 2043 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 2044 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 2045 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 2046 2047 /* Wait for command to complete */ 2048 wait = XGBE_RATECHANGE_COUNT; 2049 while (wait--) { 2050 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 2051 axgbe_printf(3, "%s: Rate change done\n", __func__); 2052 return; 2053 } 2054 2055 DELAY(2000); 2056 } 2057 2058 axgbe_printf(3, "firmware mailbox command did not complete\n"); 2059 } 2060 2061 static void 2062 xgbe_phy_rrc(struct xgbe_prv_data *pdata) 2063 { 2064 /* Receiver Reset Cycle */ 2065 xgbe_phy_perform_ratechange(pdata, 5, 0); 2066 2067 axgbe_printf(3, "receiver reset complete\n"); 2068 } 2069 2070 static void 2071 xgbe_phy_power_off(struct xgbe_prv_data *pdata) 2072 { 2073 struct xgbe_phy_data *phy_data = pdata->phy_data; 2074 2075 /* Power off */ 2076 xgbe_phy_perform_ratechange(pdata, 0, 0); 2077 2078 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 2079 2080 axgbe_printf(3, "phy powered off\n"); 2081 } 2082 2083 static void 2084 xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata) 2085 { 2086 struct xgbe_phy_data *phy_data = pdata->phy_data; 2087 2088 xgbe_phy_set_redrv_mode(pdata); 2089 2090 /* 10G/SFI */ 2091 axgbe_printf(3, "%s: cable %d len %d\n", __func__, phy_data->sfp_cable, 2092 phy_data->sfp_cable_len); 2093 2094 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) 2095 xgbe_phy_perform_ratechange(pdata, 3, 0); 2096 else { 2097 if (phy_data->sfp_cable_len <= 1) 2098 xgbe_phy_perform_ratechange(pdata, 3, 1); 2099 else if (phy_data->sfp_cable_len <= 3) 2100 xgbe_phy_perform_ratechange(pdata, 3, 2); 2101 else 2102 xgbe_phy_perform_ratechange(pdata, 3, 3); 2103 } 2104 2105 phy_data->cur_mode = XGBE_MODE_SFI; 2106 2107 axgbe_printf(3, "10GbE SFI mode set\n"); 2108 } 2109 2110 static void 2111 xgbe_phy_x_mode(struct xgbe_prv_data *pdata) 2112 { 2113 struct xgbe_phy_data *phy_data = pdata->phy_data; 2114 2115 xgbe_phy_set_redrv_mode(pdata); 2116 2117 /* 1G/X */ 2118 xgbe_phy_perform_ratechange(pdata, 1, 3); 2119 2120 phy_data->cur_mode = XGBE_MODE_X; 2121 2122 axgbe_printf(3, "1GbE X mode set\n"); 2123 } 2124 2125 static void 2126 xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata) 2127 { 2128 struct xgbe_phy_data *phy_data = pdata->phy_data; 2129 2130 xgbe_phy_set_redrv_mode(pdata); 2131 2132 /* 1G/SGMII */ 2133 xgbe_phy_perform_ratechange(pdata, 1, 2); 2134 2135 phy_data->cur_mode = XGBE_MODE_SGMII_1000; 2136 2137 axgbe_printf(2, "1GbE SGMII mode set\n"); 2138 } 2139 2140 static void 2141 xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata) 2142 { 2143 struct xgbe_phy_data *phy_data = pdata->phy_data; 2144 2145 xgbe_phy_set_redrv_mode(pdata); 2146 2147 /* 100M/SGMII */ 2148 xgbe_phy_perform_ratechange(pdata, 1, 1); 2149 2150 phy_data->cur_mode = XGBE_MODE_SGMII_100; 2151 2152 axgbe_printf(3, "100MbE SGMII mode set\n"); 2153 } 2154 2155 static void 2156 xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) 2157 { 2158 struct xgbe_phy_data *phy_data = pdata->phy_data; 2159 2160 xgbe_phy_set_redrv_mode(pdata); 2161 2162 /* 10G/KR */ 2163 xgbe_phy_perform_ratechange(pdata, 4, 0); 2164 2165 phy_data->cur_mode = XGBE_MODE_KR; 2166 2167 axgbe_printf(3, "10GbE KR mode set\n"); 2168 } 2169 2170 static void 2171 xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) 2172 { 2173 struct xgbe_phy_data *phy_data = pdata->phy_data; 2174 2175 xgbe_phy_set_redrv_mode(pdata); 2176 2177 /* 2.5G/KX */ 2178 xgbe_phy_perform_ratechange(pdata, 2, 0); 2179 2180 phy_data->cur_mode = XGBE_MODE_KX_2500; 2181 2182 axgbe_printf(3, "2.5GbE KX mode set\n"); 2183 } 2184 2185 static void 2186 xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) 2187 { 2188 struct xgbe_phy_data *phy_data = pdata->phy_data; 2189 2190 xgbe_phy_set_redrv_mode(pdata); 2191 2192 /* 1G/KX */ 2193 xgbe_phy_perform_ratechange(pdata, 1, 3); 2194 2195 phy_data->cur_mode = XGBE_MODE_KX_1000; 2196 2197 axgbe_printf(3, "1GbE KX mode set\n"); 2198 } 2199 2200 static enum xgbe_mode 2201 xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) 2202 { 2203 struct xgbe_phy_data *phy_data = pdata->phy_data; 2204 2205 return (phy_data->cur_mode); 2206 } 2207 2208 static enum xgbe_mode 2209 xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata) 2210 { 2211 struct xgbe_phy_data *phy_data = pdata->phy_data; 2212 2213 /* No switching if not 10GBase-T */ 2214 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T) 2215 return (xgbe_phy_cur_mode(pdata)); 2216 2217 switch (xgbe_phy_cur_mode(pdata)) { 2218 case XGBE_MODE_SGMII_100: 2219 case XGBE_MODE_SGMII_1000: 2220 return (XGBE_MODE_KR); 2221 case XGBE_MODE_KR: 2222 default: 2223 return (XGBE_MODE_SGMII_1000); 2224 } 2225 } 2226 2227 static enum xgbe_mode 2228 xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata) 2229 { 2230 return (XGBE_MODE_KX_2500); 2231 } 2232 2233 static enum xgbe_mode 2234 xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata) 2235 { 2236 /* If we are in KR switch to KX, and vice-versa */ 2237 switch (xgbe_phy_cur_mode(pdata)) { 2238 case XGBE_MODE_KX_1000: 2239 return (XGBE_MODE_KR); 2240 case XGBE_MODE_KR: 2241 default: 2242 return (XGBE_MODE_KX_1000); 2243 } 2244 } 2245 2246 static enum xgbe_mode 2247 xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) 2248 { 2249 struct xgbe_phy_data *phy_data = pdata->phy_data; 2250 2251 switch (phy_data->port_mode) { 2252 case XGBE_PORT_MODE_BACKPLANE: 2253 return (xgbe_phy_switch_bp_mode(pdata)); 2254 case XGBE_PORT_MODE_BACKPLANE_2500: 2255 return (xgbe_phy_switch_bp_2500_mode(pdata)); 2256 case XGBE_PORT_MODE_1000BASE_T: 2257 case XGBE_PORT_MODE_NBASE_T: 2258 case XGBE_PORT_MODE_10GBASE_T: 2259 return (xgbe_phy_switch_baset_mode(pdata)); 2260 case XGBE_PORT_MODE_1000BASE_X: 2261 case XGBE_PORT_MODE_10GBASE_R: 2262 case XGBE_PORT_MODE_SFP: 2263 /* No switching, so just return current mode */ 2264 return (xgbe_phy_cur_mode(pdata)); 2265 default: 2266 return (XGBE_MODE_UNKNOWN); 2267 } 2268 } 2269 2270 static enum xgbe_mode 2271 xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, int speed) 2272 { 2273 switch (speed) { 2274 case SPEED_1000: 2275 return (XGBE_MODE_X); 2276 case SPEED_10000: 2277 return (XGBE_MODE_KR); 2278 default: 2279 return (XGBE_MODE_UNKNOWN); 2280 } 2281 } 2282 2283 static enum xgbe_mode 2284 xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, int speed) 2285 { 2286 switch (speed) { 2287 case SPEED_100: 2288 return (XGBE_MODE_SGMII_100); 2289 case SPEED_1000: 2290 return (XGBE_MODE_SGMII_1000); 2291 case SPEED_2500: 2292 return (XGBE_MODE_KX_2500); 2293 case SPEED_10000: 2294 return (XGBE_MODE_KR); 2295 default: 2296 return (XGBE_MODE_UNKNOWN); 2297 } 2298 } 2299 2300 static enum xgbe_mode 2301 xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, int speed) 2302 { 2303 switch (speed) { 2304 case SPEED_100: 2305 return (XGBE_MODE_SGMII_100); 2306 case SPEED_1000: 2307 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2308 return (XGBE_MODE_SGMII_1000); 2309 else 2310 return (XGBE_MODE_X); 2311 case SPEED_10000: 2312 case SPEED_UNKNOWN: 2313 return (XGBE_MODE_SFI); 2314 default: 2315 return (XGBE_MODE_UNKNOWN); 2316 } 2317 } 2318 2319 static enum xgbe_mode 2320 xgbe_phy_get_bp_2500_mode(int speed) 2321 { 2322 switch (speed) { 2323 case SPEED_2500: 2324 return (XGBE_MODE_KX_2500); 2325 default: 2326 return (XGBE_MODE_UNKNOWN); 2327 } 2328 } 2329 2330 static enum xgbe_mode 2331 xgbe_phy_get_bp_mode(int speed) 2332 { 2333 switch (speed) { 2334 case SPEED_1000: 2335 return (XGBE_MODE_KX_1000); 2336 case SPEED_10000: 2337 return (XGBE_MODE_KR); 2338 default: 2339 return (XGBE_MODE_UNKNOWN); 2340 } 2341 } 2342 2343 static enum xgbe_mode 2344 xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed) 2345 { 2346 struct xgbe_phy_data *phy_data = pdata->phy_data; 2347 2348 switch (phy_data->port_mode) { 2349 case XGBE_PORT_MODE_BACKPLANE: 2350 return (xgbe_phy_get_bp_mode(speed)); 2351 case XGBE_PORT_MODE_BACKPLANE_2500: 2352 return (xgbe_phy_get_bp_2500_mode(speed)); 2353 case XGBE_PORT_MODE_1000BASE_T: 2354 case XGBE_PORT_MODE_NBASE_T: 2355 case XGBE_PORT_MODE_10GBASE_T: 2356 return (xgbe_phy_get_baset_mode(phy_data, speed)); 2357 case XGBE_PORT_MODE_1000BASE_X: 2358 case XGBE_PORT_MODE_10GBASE_R: 2359 return (xgbe_phy_get_basex_mode(phy_data, speed)); 2360 case XGBE_PORT_MODE_SFP: 2361 return (xgbe_phy_get_sfp_mode(phy_data, speed)); 2362 default: 2363 return (XGBE_MODE_UNKNOWN); 2364 } 2365 } 2366 2367 static void 2368 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2369 { 2370 switch (mode) { 2371 case XGBE_MODE_KX_1000: 2372 xgbe_phy_kx_1000_mode(pdata); 2373 break; 2374 case XGBE_MODE_KX_2500: 2375 xgbe_phy_kx_2500_mode(pdata); 2376 break; 2377 case XGBE_MODE_KR: 2378 xgbe_phy_kr_mode(pdata); 2379 break; 2380 case XGBE_MODE_SGMII_100: 2381 xgbe_phy_sgmii_100_mode(pdata); 2382 break; 2383 case XGBE_MODE_SGMII_1000: 2384 xgbe_phy_sgmii_1000_mode(pdata); 2385 break; 2386 case XGBE_MODE_X: 2387 xgbe_phy_x_mode(pdata); 2388 break; 2389 case XGBE_MODE_SFI: 2390 xgbe_phy_sfi_mode(pdata); 2391 break; 2392 default: 2393 break; 2394 } 2395 } 2396 2397 static void 2398 xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr) 2399 { 2400 struct xgbe_phy_data *phy_data = pdata->phy_data; 2401 2402 switch (pdata->phy.speed) { 2403 case SPEED_10000: 2404 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) 2405 ifmr->ifm_active |= IFM_10G_KR; 2406 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T) 2407 ifmr->ifm_active |= IFM_10G_T; 2408 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R) 2409 ifmr->ifm_active |= IFM_10G_KR; 2410 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP) 2411 ifmr->ifm_active |= IFM_10G_SFI; 2412 else 2413 ifmr->ifm_active |= IFM_OTHER; 2414 break; 2415 case SPEED_2500: 2416 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE_2500) 2417 ifmr->ifm_active |= IFM_2500_KX; 2418 else 2419 ifmr->ifm_active |= IFM_OTHER; 2420 break; 2421 case SPEED_1000: 2422 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) 2423 ifmr->ifm_active |= IFM_1000_KX; 2424 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_T) 2425 ifmr->ifm_active |= IFM_1000_T; 2426 #if 0 2427 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X) 2428 ifmr->ifm_active |= IFM_1000_SX; 2429 ifmr->ifm_active |= IFM_1000_LX; 2430 ifmr->ifm_active |= IFM_1000_CX; 2431 #endif 2432 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP) 2433 ifmr->ifm_active |= IFM_1000_SGMII; 2434 else 2435 ifmr->ifm_active |= IFM_OTHER; 2436 break; 2437 case SPEED_100: 2438 if(phy_data->port_mode == XGBE_PORT_MODE_NBASE_T) 2439 ifmr->ifm_active |= IFM_100_T; 2440 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP) 2441 ifmr->ifm_active |= IFM_1000_SGMII; 2442 else 2443 ifmr->ifm_active |= IFM_OTHER; 2444 break; 2445 default: 2446 ifmr->ifm_active |= IFM_OTHER; 2447 axgbe_printf(1, "Unknown mode detected\n"); 2448 break; 2449 } 2450 } 2451 2452 static bool 2453 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode, 2454 bool advert) 2455 { 2456 2457 if (pdata->phy.autoneg == AUTONEG_ENABLE) 2458 return (advert); 2459 else { 2460 enum xgbe_mode cur_mode; 2461 2462 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); 2463 if (cur_mode == mode) 2464 return (true); 2465 } 2466 2467 return (false); 2468 } 2469 2470 static bool 2471 xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2472 { 2473 2474 switch (mode) { 2475 case XGBE_MODE_X: 2476 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2477 1000baseX_Full))); 2478 case XGBE_MODE_KR: 2479 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2480 10000baseKR_Full))); 2481 default: 2482 return (false); 2483 } 2484 } 2485 2486 static bool 2487 xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2488 { 2489 2490 axgbe_printf(3, "%s: check mode %d\n", __func__, mode); 2491 switch (mode) { 2492 case XGBE_MODE_SGMII_100: 2493 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2494 100baseT_Full))); 2495 case XGBE_MODE_SGMII_1000: 2496 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2497 1000baseT_Full))); 2498 case XGBE_MODE_KX_2500: 2499 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2500 2500baseT_Full))); 2501 case XGBE_MODE_KR: 2502 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy, 2503 10000baseT_Full))); 2504 default: 2505 return (false); 2506 } 2507 } 2508 2509 static bool 2510 xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2511 { 2512 struct xgbe_phy_data *phy_data = pdata->phy_data; 2513 2514 switch (mode) { 2515 case XGBE_MODE_X: 2516 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) 2517 return (false); 2518 return (xgbe_phy_check_mode(pdata, mode, 2519 XGBE_ADV(&pdata->phy, 1000baseX_Full))); 2520 case XGBE_MODE_SGMII_100: 2521 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2522 return (false); 2523 return (xgbe_phy_check_mode(pdata, mode, 2524 XGBE_ADV(&pdata->phy, 100baseT_Full))); 2525 case XGBE_MODE_SGMII_1000: 2526 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T) 2527 return (false); 2528 return (xgbe_phy_check_mode(pdata, mode, 2529 XGBE_ADV(&pdata->phy, 1000baseT_Full))); 2530 case XGBE_MODE_SFI: 2531 if (phy_data->sfp_mod_absent) 2532 return (true); 2533 return (xgbe_phy_check_mode(pdata, mode, 2534 XGBE_ADV(&pdata->phy, 10000baseSR_Full) || 2535 XGBE_ADV(&pdata->phy, 10000baseLR_Full) || 2536 XGBE_ADV(&pdata->phy, 10000baseLRM_Full) || 2537 XGBE_ADV(&pdata->phy, 10000baseER_Full) || 2538 XGBE_ADV(&pdata->phy, 10000baseCR_Full))); 2539 default: 2540 return (false); 2541 } 2542 } 2543 2544 static bool 2545 xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2546 { 2547 2548 switch (mode) { 2549 case XGBE_MODE_KX_2500: 2550 return (xgbe_phy_check_mode(pdata, mode, 2551 XGBE_ADV(&pdata->phy, 2500baseX_Full))); 2552 default: 2553 return (false); 2554 } 2555 } 2556 2557 static bool 2558 xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2559 { 2560 2561 switch (mode) { 2562 case XGBE_MODE_KX_1000: 2563 return (xgbe_phy_check_mode(pdata, mode, 2564 XGBE_ADV(&pdata->phy, 1000baseKX_Full))); 2565 case XGBE_MODE_KR: 2566 return (xgbe_phy_check_mode(pdata, mode, 2567 XGBE_ADV(&pdata->phy, 10000baseKR_Full))); 2568 default: 2569 return (false); 2570 } 2571 } 2572 2573 static bool 2574 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) 2575 { 2576 struct xgbe_phy_data *phy_data = pdata->phy_data; 2577 2578 switch (phy_data->port_mode) { 2579 case XGBE_PORT_MODE_BACKPLANE: 2580 return (xgbe_phy_use_bp_mode(pdata, mode)); 2581 case XGBE_PORT_MODE_BACKPLANE_2500: 2582 return (xgbe_phy_use_bp_2500_mode(pdata, mode)); 2583 case XGBE_PORT_MODE_1000BASE_T: 2584 axgbe_printf(3, "use_mode %s\n", 2585 xgbe_phy_use_baset_mode(pdata, mode) ? "found" : "Not found"); 2586 case XGBE_PORT_MODE_NBASE_T: 2587 case XGBE_PORT_MODE_10GBASE_T: 2588 return (xgbe_phy_use_baset_mode(pdata, mode)); 2589 case XGBE_PORT_MODE_1000BASE_X: 2590 case XGBE_PORT_MODE_10GBASE_R: 2591 return (xgbe_phy_use_basex_mode(pdata, mode)); 2592 case XGBE_PORT_MODE_SFP: 2593 return (xgbe_phy_use_sfp_mode(pdata, mode)); 2594 default: 2595 return (false); 2596 } 2597 } 2598 2599 static bool 2600 xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, int speed) 2601 { 2602 2603 switch (speed) { 2604 case SPEED_1000: 2605 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X); 2606 case SPEED_10000: 2607 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R); 2608 default: 2609 return (false); 2610 } 2611 } 2612 2613 static bool 2614 xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, int speed) 2615 { 2616 2617 switch (speed) { 2618 case SPEED_100: 2619 case SPEED_1000: 2620 return (true); 2621 case SPEED_2500: 2622 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T); 2623 case SPEED_10000: 2624 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T); 2625 default: 2626 return (false); 2627 } 2628 } 2629 2630 static bool 2631 xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, int speed) 2632 { 2633 2634 switch (speed) { 2635 case SPEED_100: 2636 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000); 2637 case SPEED_1000: 2638 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) || 2639 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000)); 2640 case SPEED_10000: 2641 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000); 2642 default: 2643 return (false); 2644 } 2645 } 2646 2647 static bool 2648 xgbe_phy_valid_speed_bp_2500_mode(int speed) 2649 { 2650 2651 switch (speed) { 2652 case SPEED_2500: 2653 return (true); 2654 default: 2655 return (false); 2656 } 2657 } 2658 2659 static bool 2660 xgbe_phy_valid_speed_bp_mode(int speed) 2661 { 2662 2663 switch (speed) { 2664 case SPEED_1000: 2665 case SPEED_10000: 2666 return (true); 2667 default: 2668 return (false); 2669 } 2670 } 2671 2672 static bool 2673 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) 2674 { 2675 struct xgbe_phy_data *phy_data = pdata->phy_data; 2676 2677 switch (phy_data->port_mode) { 2678 case XGBE_PORT_MODE_BACKPLANE: 2679 return (xgbe_phy_valid_speed_bp_mode(speed)); 2680 case XGBE_PORT_MODE_BACKPLANE_2500: 2681 return (xgbe_phy_valid_speed_bp_2500_mode(speed)); 2682 case XGBE_PORT_MODE_1000BASE_T: 2683 case XGBE_PORT_MODE_NBASE_T: 2684 case XGBE_PORT_MODE_10GBASE_T: 2685 return (xgbe_phy_valid_speed_baset_mode(phy_data, speed)); 2686 case XGBE_PORT_MODE_1000BASE_X: 2687 case XGBE_PORT_MODE_10GBASE_R: 2688 return (xgbe_phy_valid_speed_basex_mode(phy_data, speed)); 2689 case XGBE_PORT_MODE_SFP: 2690 return (xgbe_phy_valid_speed_sfp_mode(phy_data, speed)); 2691 default: 2692 return (false); 2693 } 2694 } 2695 2696 static int 2697 xgbe_upd_link(struct xgbe_prv_data *pdata) 2698 { 2699 int reg; 2700 2701 axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link); 2702 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR); 2703 if (reg < 0) 2704 return (reg); 2705 2706 if ((reg & BMSR_LINK) == 0) 2707 pdata->phy.link = 0; 2708 else 2709 pdata->phy.link = 1; 2710 2711 axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg); 2712 return (0); 2713 } 2714 2715 static int 2716 xgbe_phy_read_status(struct xgbe_prv_data *pdata) 2717 { 2718 int common_adv_gb = 0; 2719 int common_adv; 2720 int lpagb = 0; 2721 int adv, lpa; 2722 int ret; 2723 2724 ret = xgbe_upd_link(pdata); 2725 if (ret) { 2726 axgbe_printf(2, "Link Update return %d\n", ret); 2727 return (ret); 2728 } 2729 2730 if (AUTONEG_ENABLE == pdata->phy.autoneg) { 2731 if (pdata->phy.supported == SUPPORTED_1000baseT_Half || 2732 pdata->phy.supported == SUPPORTED_1000baseT_Full) { 2733 lpagb = xgbe_phy_mii_read(pdata, pdata->mdio_addr, 2734 MII_100T2SR); 2735 if (lpagb < 0) 2736 return (lpagb); 2737 2738 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, 2739 MII_100T2CR); 2740 if (adv < 0) 2741 return (adv); 2742 2743 if (lpagb & GTSR_MAN_MS_FLT) { 2744 if (adv & GTCR_MAN_MS) 2745 axgbe_printf(2, "Master/Slave Resolution " 2746 "failed, maybe conflicting manual settings\n"); 2747 else 2748 axgbe_printf(2, "Master/Slave Resolution failed\n"); 2749 return (-ENOLINK); 2750 } 2751 2752 if (pdata->phy.supported == SUPPORTED_1000baseT_Half) 2753 XGBE_SET_ADV(&pdata->phy, 1000baseT_Half); 2754 else if (pdata->phy.supported == SUPPORTED_1000baseT_Full) 2755 XGBE_SET_ADV(&pdata->phy, 1000baseT_Full); 2756 2757 common_adv_gb = lpagb & adv << 2; 2758 } 2759 2760 lpa = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANLPAR); 2761 if (lpa < 0) 2762 return (lpa); 2763 2764 if (pdata->phy.supported == SUPPORTED_Autoneg) 2765 XGBE_SET_ADV(&pdata->phy, Autoneg); 2766 2767 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANAR); 2768 if (adv < 0) 2769 return (adv); 2770 2771 common_adv = lpa & adv; 2772 2773 pdata->phy.speed = SPEED_10; 2774 pdata->phy.duplex = DUPLEX_HALF; 2775 pdata->phy.pause = 0; 2776 pdata->phy.asym_pause = 0; 2777 2778 axgbe_printf(2, "%s: lpa %#x adv %#x common_adv_gb %#x " 2779 "common_adv %#x\n", __func__, lpa, adv, common_adv_gb, 2780 common_adv); 2781 if (common_adv_gb & (GTSR_LP_1000TFDX | GTSR_LP_1000THDX)) { 2782 axgbe_printf(2, "%s: SPEED 1000\n", __func__); 2783 pdata->phy.speed = SPEED_1000; 2784 2785 if (common_adv_gb & GTSR_LP_1000TFDX) 2786 pdata->phy.duplex = DUPLEX_FULL; 2787 } else if (common_adv & (ANLPAR_TX_FD | ANLPAR_TX)) { 2788 axgbe_printf(2, "%s: SPEED 100\n", __func__); 2789 pdata->phy.speed = SPEED_100; 2790 2791 if (common_adv & ANLPAR_TX_FD) 2792 pdata->phy.duplex = DUPLEX_FULL; 2793 } else 2794 if (common_adv & ANLPAR_10_FD) 2795 pdata->phy.duplex = DUPLEX_FULL; 2796 2797 if (pdata->phy.duplex == DUPLEX_FULL) { 2798 pdata->phy.pause = lpa & ANLPAR_FC ? 1 : 0; 2799 pdata->phy.asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; 2800 } 2801 } else { 2802 int bmcr = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR); 2803 if (bmcr < 0) 2804 return (bmcr); 2805 2806 if (bmcr & BMCR_FDX) 2807 pdata->phy.duplex = DUPLEX_FULL; 2808 else 2809 pdata->phy.duplex = DUPLEX_HALF; 2810 2811 if (bmcr & BMCR_SPEED1) 2812 pdata->phy.speed = SPEED_1000; 2813 else if (bmcr & BMCR_SPEED100) 2814 pdata->phy.speed = SPEED_100; 2815 else 2816 pdata->phy.speed = SPEED_10; 2817 2818 pdata->phy.pause = 0; 2819 pdata->phy.asym_pause = 0; 2820 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x " 2821 "autoneg %#x\n", __func__, pdata->phy.speed, 2822 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg); 2823 } 2824 2825 return (0); 2826 } 2827 2828 static int 2829 xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) 2830 { 2831 struct xgbe_phy_data *phy_data = pdata->phy_data; 2832 struct mii_data *mii = NULL; 2833 unsigned int reg; 2834 int ret; 2835 2836 *an_restart = 0; 2837 2838 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) { 2839 /* Check SFP signals */ 2840 axgbe_printf(3, "%s: calling phy detect\n", __func__); 2841 xgbe_phy_sfp_detect(pdata); 2842 2843 if (phy_data->sfp_changed) { 2844 axgbe_printf(1, "%s: SFP changed observed\n", __func__); 2845 *an_restart = 1; 2846 return (0); 2847 } 2848 2849 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) { 2850 axgbe_printf(1, "%s: SFP absent 0x%x & sfp_rx_los 0x%x\n", 2851 __func__, phy_data->sfp_mod_absent, 2852 phy_data->sfp_rx_los); 2853 return (0); 2854 } 2855 } else { 2856 mii = device_get_softc(pdata->axgbe_miibus); 2857 mii_tick(mii); 2858 2859 ret = xgbe_phy_read_status(pdata); 2860 if (ret) { 2861 axgbe_printf(2, "Link: Read status returned %d\n", ret); 2862 return (ret); 2863 } 2864 2865 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x " 2866 "autoneg %#x\n", __func__, pdata->phy.speed, 2867 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg); 2868 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR); 2869 ret = (ret < 0) ? ret : (ret & BMSR_ACOMP); 2870 axgbe_printf(2, "Link: BMCR returned %d\n", ret); 2871 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && !ret) 2872 return (0); 2873 2874 return (pdata->phy.link); 2875 } 2876 2877 /* Link status is latched low, so read once to clear 2878 * and then read again to get current state 2879 */ 2880 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2881 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 2882 axgbe_printf(1, "%s: link_status reg: 0x%x\n", __func__, reg); 2883 if (reg & MDIO_STAT1_LSTATUS) 2884 return (1); 2885 2886 /* No link, attempt a receiver reset cycle */ 2887 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { 2888 axgbe_printf(1, "ENTERED RRC: rrc_count: %d\n", 2889 phy_data->rrc_count); 2890 phy_data->rrc_count = 0; 2891 if (pdata->link_workaround) { 2892 ret = xgbe_phy_reset(pdata); 2893 if (ret) 2894 axgbe_error("Error resetting phy\n"); 2895 } else 2896 xgbe_phy_rrc(pdata); 2897 } 2898 2899 return (0); 2900 } 2901 2902 static void 2903 xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata) 2904 { 2905 struct xgbe_phy_data *phy_data = pdata->phy_data; 2906 2907 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 + 2908 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR); 2909 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2910 GPIO_MASK); 2911 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2912 GPIO_RX_LOS); 2913 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2914 GPIO_TX_FAULT); 2915 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2916 GPIO_MOD_ABS); 2917 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 2918 GPIO_RATE_SELECT); 2919 2920 DBGPR("SFP: gpio_address=%#x\n", phy_data->sfp_gpio_address); 2921 DBGPR("SFP: gpio_mask=%#x\n", phy_data->sfp_gpio_mask); 2922 DBGPR("SFP: gpio_rx_los=%u\n", phy_data->sfp_gpio_rx_los); 2923 DBGPR("SFP: gpio_tx_fault=%u\n", phy_data->sfp_gpio_tx_fault); 2924 DBGPR("SFP: gpio_mod_absent=%u\n", 2925 phy_data->sfp_gpio_mod_absent); 2926 DBGPR("SFP: gpio_rate_select=%u\n", 2927 phy_data->sfp_gpio_rate_select); 2928 } 2929 2930 static void 2931 xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata) 2932 { 2933 struct xgbe_phy_data *phy_data = pdata->phy_data; 2934 unsigned int mux_addr_hi, mux_addr_lo; 2935 2936 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 2937 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 2938 if (mux_addr_lo == XGBE_SFP_DIRECT) 2939 return; 2940 2941 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545; 2942 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 2943 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, 2944 MUX_CHAN); 2945 2946 DBGPR("SFP: mux_address=%#x\n", phy_data->sfp_mux_address); 2947 DBGPR("SFP: mux_channel=%u\n", phy_data->sfp_mux_channel); 2948 } 2949 2950 static void 2951 xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata) 2952 { 2953 xgbe_phy_sfp_comm_setup(pdata); 2954 xgbe_phy_sfp_gpio_setup(pdata); 2955 } 2956 2957 static int 2958 xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata) 2959 { 2960 struct xgbe_phy_data *phy_data = pdata->phy_data; 2961 unsigned int ret; 2962 2963 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio); 2964 if (ret) 2965 return (ret); 2966 2967 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio); 2968 2969 return (ret); 2970 } 2971 2972 static int 2973 xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata) 2974 { 2975 struct xgbe_phy_data *phy_data = pdata->phy_data; 2976 uint8_t gpio_reg, gpio_ports[2], gpio_data[3]; 2977 int ret; 2978 2979 /* Read the output port registers */ 2980 gpio_reg = 2; 2981 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr, 2982 &gpio_reg, sizeof(gpio_reg), 2983 gpio_ports, sizeof(gpio_ports)); 2984 if (ret) 2985 return (ret); 2986 2987 /* Prepare to write the GPIO data */ 2988 gpio_data[0] = 2; 2989 gpio_data[1] = gpio_ports[0]; 2990 gpio_data[2] = gpio_ports[1]; 2991 2992 /* Set the GPIO pin */ 2993 if (phy_data->mdio_reset_gpio < 8) 2994 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2995 else 2996 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8)); 2997 2998 /* Write the output port registers */ 2999 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 3000 gpio_data, sizeof(gpio_data)); 3001 if (ret) 3002 return (ret); 3003 3004 /* Clear the GPIO pin */ 3005 if (phy_data->mdio_reset_gpio < 8) 3006 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 3007 else 3008 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8)); 3009 3010 /* Write the output port registers */ 3011 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr, 3012 gpio_data, sizeof(gpio_data)); 3013 3014 return (ret); 3015 } 3016 3017 static int 3018 xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata) 3019 { 3020 struct xgbe_phy_data *phy_data = pdata->phy_data; 3021 int ret; 3022 3023 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 3024 return (0); 3025 3026 ret = xgbe_phy_get_comm_ownership(pdata); 3027 if (ret) 3028 return (ret); 3029 3030 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) 3031 ret = xgbe_phy_i2c_mdio_reset(pdata); 3032 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 3033 ret = xgbe_phy_int_mdio_reset(pdata); 3034 3035 xgbe_phy_put_comm_ownership(pdata); 3036 3037 return (ret); 3038 } 3039 3040 static bool 3041 xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data) 3042 { 3043 if (!phy_data->redrv) 3044 return (false); 3045 3046 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX) 3047 return (true); 3048 3049 switch (phy_data->redrv_model) { 3050 case XGBE_PHY_REDRV_MODEL_4223: 3051 if (phy_data->redrv_lane > 3) 3052 return (true); 3053 break; 3054 case XGBE_PHY_REDRV_MODEL_4227: 3055 if (phy_data->redrv_lane > 1) 3056 return (true); 3057 break; 3058 default: 3059 return (true); 3060 } 3061 3062 return (false); 3063 } 3064 3065 static int 3066 xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata) 3067 { 3068 struct xgbe_phy_data *phy_data = pdata->phy_data; 3069 3070 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO) 3071 return (0); 3072 3073 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 3074 switch (phy_data->mdio_reset) { 3075 case XGBE_MDIO_RESET_NONE: 3076 case XGBE_MDIO_RESET_I2C_GPIO: 3077 case XGBE_MDIO_RESET_INT_GPIO: 3078 break; 3079 default: 3080 axgbe_error("unsupported MDIO reset (%#x)\n", 3081 phy_data->mdio_reset); 3082 return (-EINVAL); 3083 } 3084 3085 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) { 3086 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 + 3087 XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET_I2C_ADDR); 3088 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3089 MDIO_RESET_I2C_GPIO); 3090 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) 3091 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 3092 MDIO_RESET_INT_GPIO); 3093 3094 return (0); 3095 } 3096 3097 static bool 3098 xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata) 3099 { 3100 struct xgbe_phy_data *phy_data = pdata->phy_data; 3101 3102 switch (phy_data->port_mode) { 3103 case XGBE_PORT_MODE_BACKPLANE: 3104 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3105 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3106 return (false); 3107 break; 3108 case XGBE_PORT_MODE_BACKPLANE_2500: 3109 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) 3110 return (false); 3111 break; 3112 case XGBE_PORT_MODE_1000BASE_T: 3113 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3114 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)) 3115 return (false); 3116 break; 3117 case XGBE_PORT_MODE_1000BASE_X: 3118 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3119 return (false); 3120 break; 3121 case XGBE_PORT_MODE_NBASE_T: 3122 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3123 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3124 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)) 3125 return (false); 3126 break; 3127 case XGBE_PORT_MODE_10GBASE_T: 3128 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3129 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3130 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3131 return (false); 3132 break; 3133 case XGBE_PORT_MODE_10GBASE_R: 3134 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3135 return (false); 3136 break; 3137 case XGBE_PORT_MODE_SFP: 3138 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) || 3139 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) || 3140 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)) 3141 return (false); 3142 break; 3143 default: 3144 break; 3145 } 3146 3147 return (true); 3148 } 3149 3150 static bool 3151 xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata) 3152 { 3153 struct xgbe_phy_data *phy_data = pdata->phy_data; 3154 3155 switch (phy_data->port_mode) { 3156 case XGBE_PORT_MODE_BACKPLANE: 3157 case XGBE_PORT_MODE_BACKPLANE_2500: 3158 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE) 3159 return (false); 3160 break; 3161 case XGBE_PORT_MODE_1000BASE_T: 3162 case XGBE_PORT_MODE_1000BASE_X: 3163 case XGBE_PORT_MODE_NBASE_T: 3164 case XGBE_PORT_MODE_10GBASE_T: 3165 case XGBE_PORT_MODE_10GBASE_R: 3166 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO) 3167 return (false); 3168 break; 3169 case XGBE_PORT_MODE_SFP: 3170 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP) 3171 return (false); 3172 break; 3173 default: 3174 break; 3175 } 3176 3177 return (true); 3178 } 3179 3180 static bool 3181 xgbe_phy_port_enabled(struct xgbe_prv_data *pdata) 3182 { 3183 3184 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 3185 return (false); 3186 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 3187 return (false); 3188 3189 return (true); 3190 } 3191 3192 static void 3193 xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) 3194 { 3195 struct xgbe_phy_data *phy_data = pdata->phy_data; 3196 3197 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n", 3198 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack); 3199 3200 if (!pdata->sysctl_an_cdr_workaround) 3201 return; 3202 3203 if (!phy_data->phy_cdr_notrack) 3204 return; 3205 3206 DELAY(phy_data->phy_cdr_delay + 500); 3207 3208 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 3209 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_ON); 3210 3211 phy_data->phy_cdr_notrack = 0; 3212 3213 axgbe_printf(2, "CDR TRACK DONE\n"); 3214 } 3215 3216 static void 3217 xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) 3218 { 3219 struct xgbe_phy_data *phy_data = pdata->phy_data; 3220 3221 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n", 3222 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack); 3223 3224 if (!pdata->sysctl_an_cdr_workaround) 3225 return; 3226 3227 if (phy_data->phy_cdr_notrack) 3228 return; 3229 3230 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 3231 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_OFF); 3232 3233 xgbe_phy_rrc(pdata); 3234 3235 phy_data->phy_cdr_notrack = 1; 3236 } 3237 3238 static void 3239 xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) 3240 { 3241 if (!pdata->sysctl_an_cdr_track_early) 3242 xgbe_phy_cdr_track(pdata); 3243 } 3244 3245 static void 3246 xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) 3247 { 3248 if (pdata->sysctl_an_cdr_track_early) 3249 xgbe_phy_cdr_track(pdata); 3250 } 3251 3252 static void 3253 xgbe_phy_an_post(struct xgbe_prv_data *pdata) 3254 { 3255 struct xgbe_phy_data *phy_data = pdata->phy_data; 3256 3257 switch (pdata->an_mode) { 3258 case XGBE_AN_MODE_CL73: 3259 case XGBE_AN_MODE_CL73_REDRV: 3260 if (phy_data->cur_mode != XGBE_MODE_KR) 3261 break; 3262 3263 xgbe_phy_cdr_track(pdata); 3264 3265 switch (pdata->an_result) { 3266 case XGBE_AN_READY: 3267 case XGBE_AN_COMPLETE: 3268 break; 3269 default: 3270 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) 3271 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; 3272 else 3273 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3274 break; 3275 } 3276 break; 3277 default: 3278 break; 3279 } 3280 } 3281 3282 static void 3283 xgbe_phy_an_pre(struct xgbe_prv_data *pdata) 3284 { 3285 struct xgbe_phy_data *phy_data = pdata->phy_data; 3286 3287 switch (pdata->an_mode) { 3288 case XGBE_AN_MODE_CL73: 3289 case XGBE_AN_MODE_CL73_REDRV: 3290 if (phy_data->cur_mode != XGBE_MODE_KR) 3291 break; 3292 3293 xgbe_phy_cdr_notrack(pdata); 3294 break; 3295 default: 3296 break; 3297 } 3298 } 3299 3300 static void 3301 xgbe_phy_stop(struct xgbe_prv_data *pdata) 3302 { 3303 struct xgbe_phy_data *phy_data = pdata->phy_data; 3304 3305 /* If we have an external PHY, free it */ 3306 xgbe_phy_free_phy_device(pdata); 3307 3308 /* Reset SFP data */ 3309 xgbe_phy_sfp_reset(phy_data); 3310 xgbe_phy_sfp_mod_absent(pdata); 3311 3312 /* Reset CDR support */ 3313 xgbe_phy_cdr_track(pdata); 3314 3315 /* Power off the PHY */ 3316 xgbe_phy_power_off(pdata); 3317 3318 /* Stop the I2C controller */ 3319 pdata->i2c_if.i2c_stop(pdata); 3320 } 3321 3322 static int 3323 xgbe_phy_start(struct xgbe_prv_data *pdata) 3324 { 3325 struct xgbe_phy_data *phy_data = pdata->phy_data; 3326 int ret; 3327 3328 axgbe_printf(2, "%s: redrv %d redrv_if %d start_mode %d\n", __func__, 3329 phy_data->redrv, phy_data->redrv_if, phy_data->start_mode); 3330 3331 /* Start the I2C controller */ 3332 ret = pdata->i2c_if.i2c_start(pdata); 3333 if (ret) { 3334 axgbe_error("%s: impl i2c start ret %d\n", __func__, ret); 3335 return (ret); 3336 } 3337 3338 /* Set the proper MDIO mode for the re-driver */ 3339 if (phy_data->redrv && !phy_data->redrv_if) { 3340 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3341 XGBE_MDIO_MODE_CL22); 3342 if (ret) { 3343 axgbe_error("redriver mdio port not compatible (%u)\n", 3344 phy_data->redrv_addr); 3345 return (ret); 3346 } 3347 } 3348 3349 /* Start in highest supported mode */ 3350 xgbe_phy_set_mode(pdata, phy_data->start_mode); 3351 3352 /* Reset CDR support */ 3353 xgbe_phy_cdr_track(pdata); 3354 3355 /* After starting the I2C controller, we can check for an SFP */ 3356 switch (phy_data->port_mode) { 3357 case XGBE_PORT_MODE_SFP: 3358 axgbe_printf(3, "%s: calling phy detect\n", __func__); 3359 xgbe_phy_sfp_detect(pdata); 3360 break; 3361 default: 3362 break; 3363 } 3364 3365 /* If we have an external PHY, start it */ 3366 ret = xgbe_phy_find_phy_device(pdata); 3367 if (ret) { 3368 axgbe_error("%s: impl find phy dev ret %d\n", __func__, ret); 3369 goto err_i2c; 3370 } 3371 3372 axgbe_printf(3, "%s: impl return success\n", __func__); 3373 return (0); 3374 3375 err_i2c: 3376 pdata->i2c_if.i2c_stop(pdata); 3377 3378 return (ret); 3379 } 3380 3381 static int 3382 xgbe_phy_reset(struct xgbe_prv_data *pdata) 3383 { 3384 struct xgbe_phy_data *phy_data = pdata->phy_data; 3385 enum xgbe_mode cur_mode; 3386 int ret; 3387 3388 /* Reset by power cycling the PHY */ 3389 cur_mode = phy_data->cur_mode; 3390 xgbe_phy_power_off(pdata); 3391 xgbe_phy_set_mode(pdata, cur_mode); 3392 3393 axgbe_printf(3, "%s: mode %d\n", __func__, cur_mode); 3394 if (!phy_data->phydev) { 3395 axgbe_printf(1, "%s: no phydev\n", __func__); 3396 return (0); 3397 } 3398 3399 /* Reset the external PHY */ 3400 ret = xgbe_phy_mdio_reset(pdata); 3401 if (ret) { 3402 axgbe_error("%s: mdio reset %d\n", __func__, ret); 3403 return (ret); 3404 } 3405 3406 axgbe_printf(3, "%s: return success\n", __func__); 3407 3408 return (0); 3409 } 3410 3411 static void 3412 axgbe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3413 { 3414 struct axgbe_if_softc *sc; 3415 struct xgbe_prv_data *pdata; 3416 struct mii_data *mii; 3417 3418 sc = ifp->if_softc; 3419 pdata = &sc->pdata; 3420 3421 axgbe_printf(2, "%s: Invoked\n", __func__); 3422 mtx_lock_spin(&pdata->mdio_mutex); 3423 mii = device_get_softc(pdata->axgbe_miibus); 3424 axgbe_printf(2, "%s: media_active %#x media_status %#x\n", __func__, 3425 mii->mii_media_active, mii->mii_media_status); 3426 mii_pollstat(mii); 3427 ifmr->ifm_active = mii->mii_media_active; 3428 ifmr->ifm_status = mii->mii_media_status; 3429 mtx_unlock_spin(&pdata->mdio_mutex); 3430 } 3431 3432 static int 3433 axgbe_ifmedia_upd(struct ifnet *ifp) 3434 { 3435 struct xgbe_prv_data *pdata; 3436 struct axgbe_if_softc *sc; 3437 struct mii_data *mii; 3438 struct mii_softc *miisc; 3439 int ret; 3440 3441 sc = ifp->if_softc; 3442 pdata = &sc->pdata; 3443 3444 axgbe_printf(2, "%s: Invoked\n", __func__); 3445 mtx_lock_spin(&pdata->mdio_mutex); 3446 mii = device_get_softc(pdata->axgbe_miibus); 3447 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3448 PHY_RESET(miisc); 3449 ret = mii_mediachg(mii); 3450 mtx_unlock_spin(&pdata->mdio_mutex); 3451 3452 return (ret); 3453 } 3454 3455 static void 3456 xgbe_phy_exit(struct xgbe_prv_data *pdata) 3457 { 3458 if (pdata->axgbe_miibus != NULL) 3459 device_delete_child(pdata->dev, pdata->axgbe_miibus); 3460 3461 /* free phy_data structure */ 3462 free(pdata->phy_data, M_AXGBE); 3463 } 3464 3465 static int 3466 xgbe_phy_init(struct xgbe_prv_data *pdata) 3467 { 3468 struct xgbe_phy_data *phy_data; 3469 int ret; 3470 3471 /* Initialize the global lock */ 3472 if (!mtx_initialized(&xgbe_phy_comm_lock)) 3473 mtx_init(&xgbe_phy_comm_lock, "xgbe phy common lock", NULL, MTX_DEF); 3474 3475 /* Check if enabled */ 3476 if (!xgbe_phy_port_enabled(pdata)) { 3477 axgbe_error("device is not enabled\n"); 3478 return (-ENODEV); 3479 } 3480 3481 /* Initialize the I2C controller */ 3482 ret = pdata->i2c_if.i2c_init(pdata); 3483 if (ret) 3484 return (ret); 3485 3486 phy_data = malloc(sizeof(*phy_data), M_AXGBE, M_WAITOK | M_ZERO); 3487 if (!phy_data) 3488 return (-ENOMEM); 3489 pdata->phy_data = phy_data; 3490 3491 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 3492 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 3493 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 3494 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 3495 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 3496 3497 pdata->mdio_addr = phy_data->mdio_addr; 3498 DBGPR("port mode=%u\n", phy_data->port_mode); 3499 DBGPR("port id=%u\n", phy_data->port_id); 3500 DBGPR("port speeds=%#x\n", phy_data->port_speeds); 3501 DBGPR("conn type=%u\n", phy_data->conn_type); 3502 DBGPR("mdio addr=%u\n", phy_data->mdio_addr); 3503 3504 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 3505 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 3506 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 3507 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 3508 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 3509 3510 if (phy_data->redrv) { 3511 DBGPR("redrv present\n"); 3512 DBGPR("redrv i/f=%u\n", phy_data->redrv_if); 3513 DBGPR("redrv addr=%#x\n", phy_data->redrv_addr); 3514 DBGPR("redrv lane=%u\n", phy_data->redrv_lane); 3515 DBGPR("redrv model=%u\n", phy_data->redrv_model); 3516 } 3517 3518 DBGPR("%s: redrv addr=%#x redrv i/f=%u\n", __func__, 3519 phy_data->redrv_addr, phy_data->redrv_if); 3520 /* Validate the connection requested */ 3521 if (xgbe_phy_conn_type_mismatch(pdata)) { 3522 axgbe_error("phy mode/connection mismatch " 3523 "(%#x/%#x)\n", phy_data->port_mode, phy_data->conn_type); 3524 return (-EINVAL); 3525 } 3526 3527 /* Validate the mode requested */ 3528 if (xgbe_phy_port_mode_mismatch(pdata)) { 3529 axgbe_error("phy mode/speed mismatch " 3530 "(%#x/%#x)\n", phy_data->port_mode, phy_data->port_speeds); 3531 return (-EINVAL); 3532 } 3533 3534 /* Check for and validate MDIO reset support */ 3535 ret = xgbe_phy_mdio_reset_setup(pdata); 3536 if (ret) { 3537 axgbe_error("%s, mdio_reset_setup ret %d\n", __func__, ret); 3538 return (ret); 3539 } 3540 3541 /* Validate the re-driver information */ 3542 if (xgbe_phy_redrv_error(phy_data)) { 3543 axgbe_error("phy re-driver settings error\n"); 3544 return (-EINVAL); 3545 } 3546 pdata->kr_redrv = phy_data->redrv; 3547 3548 /* Indicate current mode is unknown */ 3549 phy_data->cur_mode = XGBE_MODE_UNKNOWN; 3550 3551 /* Initialize supported features. Current code does not support ethtool */ 3552 XGBE_ZERO_SUP(&pdata->phy); 3553 3554 DBGPR("%s: port mode %d\n", __func__, phy_data->port_mode); 3555 switch (phy_data->port_mode) { 3556 /* Backplane support */ 3557 case XGBE_PORT_MODE_BACKPLANE: 3558 XGBE_SET_SUP(&pdata->phy, Autoneg); 3559 XGBE_SET_SUP(&pdata->phy, Pause); 3560 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3561 XGBE_SET_SUP(&pdata->phy, Backplane); 3562 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3563 XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full); 3564 phy_data->start_mode = XGBE_MODE_KX_1000; 3565 } 3566 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3567 XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full); 3568 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3569 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC); 3570 phy_data->start_mode = XGBE_MODE_KR; 3571 } 3572 3573 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3574 break; 3575 case XGBE_PORT_MODE_BACKPLANE_2500: 3576 XGBE_SET_SUP(&pdata->phy, Pause); 3577 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3578 XGBE_SET_SUP(&pdata->phy, Backplane); 3579 XGBE_SET_SUP(&pdata->phy, 2500baseX_Full); 3580 phy_data->start_mode = XGBE_MODE_KX_2500; 3581 3582 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3583 break; 3584 3585 /* MDIO 1GBase-T support */ 3586 case XGBE_PORT_MODE_1000BASE_T: 3587 XGBE_SET_SUP(&pdata->phy, Autoneg); 3588 XGBE_SET_SUP(&pdata->phy, Pause); 3589 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3590 XGBE_SET_SUP(&pdata->phy, TP); 3591 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3592 XGBE_SET_SUP(&pdata->phy, 100baseT_Full); 3593 phy_data->start_mode = XGBE_MODE_SGMII_100; 3594 } 3595 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3596 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full); 3597 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3598 } 3599 3600 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3601 break; 3602 3603 /* MDIO Base-X support */ 3604 case XGBE_PORT_MODE_1000BASE_X: 3605 XGBE_SET_SUP(&pdata->phy, Autoneg); 3606 XGBE_SET_SUP(&pdata->phy, Pause); 3607 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3608 XGBE_SET_SUP(&pdata->phy, FIBRE); 3609 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full); 3610 phy_data->start_mode = XGBE_MODE_X; 3611 3612 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3613 break; 3614 3615 /* MDIO NBase-T support */ 3616 case XGBE_PORT_MODE_NBASE_T: 3617 XGBE_SET_SUP(&pdata->phy, Autoneg); 3618 XGBE_SET_SUP(&pdata->phy, Pause); 3619 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3620 XGBE_SET_SUP(&pdata->phy, TP); 3621 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3622 XGBE_SET_SUP(&pdata->phy, 100baseT_Full); 3623 phy_data->start_mode = XGBE_MODE_SGMII_100; 3624 } 3625 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3626 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full); 3627 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3628 } 3629 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) { 3630 XGBE_SET_SUP(&pdata->phy, 2500baseT_Full); 3631 phy_data->start_mode = XGBE_MODE_KX_2500; 3632 } 3633 3634 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3635 break; 3636 3637 /* 10GBase-T support */ 3638 case XGBE_PORT_MODE_10GBASE_T: 3639 XGBE_SET_SUP(&pdata->phy, Autoneg); 3640 XGBE_SET_SUP(&pdata->phy, Pause); 3641 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3642 XGBE_SET_SUP(&pdata->phy, TP); 3643 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) { 3644 XGBE_SET_SUP(&pdata->phy, 100baseT_Full); 3645 phy_data->start_mode = XGBE_MODE_SGMII_100; 3646 } 3647 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) { 3648 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full); 3649 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3650 } 3651 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) { 3652 XGBE_SET_SUP(&pdata->phy, 10000baseT_Full); 3653 phy_data->start_mode = XGBE_MODE_KR; 3654 } 3655 3656 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45; 3657 break; 3658 3659 /* 10GBase-R support */ 3660 case XGBE_PORT_MODE_10GBASE_R: 3661 XGBE_SET_SUP(&pdata->phy, Autoneg); 3662 XGBE_SET_SUP(&pdata->phy, Pause); 3663 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3664 XGBE_SET_SUP(&pdata->phy, FIBRE); 3665 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full); 3666 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full); 3667 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full); 3668 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full); 3669 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 3670 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC); 3671 phy_data->start_mode = XGBE_MODE_SFI; 3672 3673 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE; 3674 break; 3675 3676 /* SFP support */ 3677 case XGBE_PORT_MODE_SFP: 3678 XGBE_SET_SUP(&pdata->phy, Autoneg); 3679 XGBE_SET_SUP(&pdata->phy, Pause); 3680 XGBE_SET_SUP(&pdata->phy, Asym_Pause); 3681 XGBE_SET_SUP(&pdata->phy, TP); 3682 XGBE_SET_SUP(&pdata->phy, FIBRE); 3683 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) 3684 phy_data->start_mode = XGBE_MODE_SGMII_100; 3685 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) 3686 phy_data->start_mode = XGBE_MODE_SGMII_1000; 3687 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) 3688 phy_data->start_mode = XGBE_MODE_SFI; 3689 3690 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22; 3691 3692 xgbe_phy_sfp_setup(pdata); 3693 DBGPR("%s: start %d mode %d adv 0x%x\n", __func__, 3694 phy_data->start_mode, phy_data->phydev_mode, 3695 pdata->phy.advertising); 3696 break; 3697 default: 3698 return (-EINVAL); 3699 } 3700 3701 axgbe_printf(2, "%s: start %d mode %d adv 0x%x\n", __func__, 3702 phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising); 3703 3704 DBGPR("%s: conn type %d mode %d\n", __func__, 3705 phy_data->conn_type, phy_data->phydev_mode); 3706 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) && 3707 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) { 3708 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 3709 phy_data->phydev_mode); 3710 if (ret) { 3711 axgbe_error("mdio port/clause not compatible (%d/%u)\n", 3712 phy_data->mdio_addr, phy_data->phydev_mode); 3713 return (-EINVAL); 3714 } 3715 } 3716 3717 if (phy_data->redrv && !phy_data->redrv_if) { 3718 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 3719 XGBE_MDIO_MODE_CL22); 3720 if (ret) { 3721 axgbe_error("redriver mdio port not compatible (%u)\n", 3722 phy_data->redrv_addr); 3723 return (-EINVAL); 3724 } 3725 } 3726 3727 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; 3728 3729 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) { 3730 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev, 3731 (ifm_change_cb_t)axgbe_ifmedia_upd, 3732 (ifm_stat_cb_t)axgbe_ifmedia_sts, BMSR_DEFCAPMASK, 3733 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG); 3734 3735 if (ret){ 3736 axgbe_printf(2, "mii attach failed with err=(%d)\n", ret); 3737 return (-EINVAL); 3738 } 3739 } 3740 3741 DBGPR("%s: return success\n", __func__); 3742 3743 return (0); 3744 } 3745 3746 void 3747 xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if) 3748 { 3749 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 3750 3751 phy_impl->init = xgbe_phy_init; 3752 phy_impl->exit = xgbe_phy_exit; 3753 3754 phy_impl->reset = xgbe_phy_reset; 3755 phy_impl->start = xgbe_phy_start; 3756 phy_impl->stop = xgbe_phy_stop; 3757 3758 phy_impl->link_status = xgbe_phy_link_status; 3759 3760 phy_impl->valid_speed = xgbe_phy_valid_speed; 3761 3762 phy_impl->use_mode = xgbe_phy_use_mode; 3763 phy_impl->set_mode = xgbe_phy_set_mode; 3764 phy_impl->get_mode = xgbe_phy_get_mode; 3765 phy_impl->switch_mode = xgbe_phy_switch_mode; 3766 phy_impl->cur_mode = xgbe_phy_cur_mode; 3767 phy_impl->get_type = xgbe_phy_get_type; 3768 3769 phy_impl->an_mode = xgbe_phy_an_mode; 3770 3771 phy_impl->an_config = xgbe_phy_an_config; 3772 3773 phy_impl->an_advertising = xgbe_phy_an_advertising; 3774 3775 phy_impl->an_outcome = xgbe_phy_an_outcome; 3776 3777 phy_impl->an_pre = xgbe_phy_an_pre; 3778 phy_impl->an_post = xgbe_phy_an_post; 3779 3780 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre; 3781 phy_impl->kr_training_post = xgbe_phy_kr_training_post; 3782 3783 phy_impl->module_info = xgbe_phy_module_info; 3784 phy_impl->module_eeprom = xgbe_phy_module_eeprom; 3785 } 3786