1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * Copyright (c) 2020 Advanced Micro Devices, Inc. 5 * 6 * This file is available to you under your choice of the following two 7 * licenses: 8 * 9 * License 1: GPLv2 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Redistribution and use in source and binary forms, with or without 60 * modification, are permitted provided that the following conditions are met: 61 * * Redistributions of source code must retain the above copyright 62 * notice, this list of conditions and the following disclaimer. 63 * * Redistributions in binary form must reproduce the above copyright 64 * notice, this list of conditions and the following disclaimer in the 65 * documentation and/or other materials provided with the distribution. 66 * * Neither the name of Advanced Micro Devices, Inc. nor the 67 * names of its contributors may be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 80 * 81 * This file incorporates work covered by the following copyright and 82 * permission notice: 83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 85 * Inc. unless otherwise expressly agreed to in writing between Synopsys 86 * and you. 87 * 88 * The Software IS NOT an item of Licensed Software or Licensed Product 89 * under any End User Software License Agreement or Agreement for Licensed 90 * Product with Synopsys or any supplement thereto. Permission is hereby 91 * granted, free of charge, to any person obtaining a copy of this software 92 * annotated with this license and the Software, to deal in the Software 93 * without restriction, including without limitation the rights to use, 94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 95 * of the Software, and to permit persons to whom the Software is furnished 96 * to do so, subject to the following conditions: 97 * 98 * The above copyright notice and this permission notice shall be included 99 * in all copies or substantial portions of the Software. 100 * 101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 111 * THE POSSIBILITY OF SUCH DAMAGE. 112 */ 113 114 #include <sys/cdefs.h> 115 __FBSDID("$FreeBSD$"); 116 117 #include "xgbe.h" 118 #include "xgbe-common.h" 119 120 #define XGBE_ABORT_COUNT 500 121 #define XGBE_DISABLE_COUNT 1000 122 123 #define XGBE_STD_SPEED 1 124 125 #define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX) 126 #define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX) 127 #define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX) 128 #define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX) 129 #define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL | \ 130 XGBE_INTR_TX_EMPTY | \ 131 XGBE_INTR_TX_ABRT | \ 132 XGBE_INTR_STOP_DET) 133 134 #define XGBE_I2C_READ BIT(8) 135 #define XGBE_I2C_STOP BIT(9) 136 137 static int 138 xgbe_i2c_abort(struct xgbe_prv_data *pdata) 139 { 140 unsigned int wait = XGBE_ABORT_COUNT; 141 142 /* Must be enabled to recognize the abort request */ 143 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1); 144 145 /* Issue the abort */ 146 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1); 147 148 while (wait--) { 149 if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT)) 150 return (0); 151 152 DELAY(500); 153 } 154 155 return (-EBUSY); 156 } 157 158 static int 159 xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable) 160 { 161 unsigned int wait = XGBE_DISABLE_COUNT; 162 unsigned int mode = enable ? 1 : 0; 163 164 while (wait--) { 165 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode); 166 if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode) 167 return (0); 168 169 DELAY(100); 170 } 171 172 return (-EBUSY); 173 } 174 175 static int 176 xgbe_i2c_disable(struct xgbe_prv_data *pdata) 177 { 178 unsigned int ret; 179 180 ret = xgbe_i2c_set_enable(pdata, false); 181 if (ret) { 182 /* Disable failed, try an abort */ 183 ret = xgbe_i2c_abort(pdata); 184 if (ret) { 185 axgbe_error("%s: i2c_abort %d\n", __func__, ret); 186 return (ret); 187 } 188 189 /* Abort succeeded, try to disable again */ 190 ret = xgbe_i2c_set_enable(pdata, false); 191 } 192 193 axgbe_printf(3, "%s: final i2c_disable %d\n", __func__, ret); 194 return (ret); 195 } 196 197 static int 198 xgbe_i2c_enable(struct xgbe_prv_data *pdata) 199 { 200 return (xgbe_i2c_set_enable(pdata, true)); 201 } 202 203 static void 204 xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata) 205 { 206 XI2C_IOREAD(pdata, IC_CLR_INTR); 207 } 208 209 static void 210 xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata) 211 { 212 XI2C_IOWRITE(pdata, IC_INTR_MASK, 0); 213 } 214 215 static void 216 xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata) 217 { 218 XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK); 219 } 220 221 static void 222 xgbe_i2c_write(struct xgbe_prv_data *pdata) 223 { 224 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 225 unsigned int tx_slots, cmd; 226 227 /* Configured to never receive Rx overflows, so fill up Tx fifo */ 228 tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR); 229 axgbe_printf(3, "%s: tx_slots %d tx_len %d\n", __func__, tx_slots, 230 state->tx_len); 231 232 while (tx_slots && state->tx_len) { 233 if (state->op->cmd == XGBE_I2C_CMD_READ) 234 cmd = XGBE_I2C_READ; 235 else 236 cmd = *state->tx_buf++; 237 238 axgbe_printf(3, "%s: cmd %d tx_len %d\n", __func__, cmd, 239 state->tx_len); 240 241 if (state->tx_len == 1) 242 XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1); 243 244 XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd); 245 246 tx_slots--; 247 state->tx_len--; 248 } 249 250 /* No more Tx operations, so ignore TX_EMPTY and return */ 251 if (!state->tx_len) 252 XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0); 253 } 254 255 static void 256 xgbe_i2c_read(struct xgbe_prv_data *pdata) 257 { 258 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 259 unsigned int rx_slots; 260 261 /* Anything to be read? */ 262 axgbe_printf(3, "%s: op cmd %d\n", __func__, state->op->cmd); 263 if (state->op->cmd != XGBE_I2C_CMD_READ) 264 return; 265 266 rx_slots = XI2C_IOREAD(pdata, IC_RXFLR); 267 axgbe_printf(3, "%s: rx_slots %d rx_len %d\n", __func__, rx_slots, 268 state->rx_len); 269 270 while (rx_slots && state->rx_len) { 271 *state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD); 272 state->rx_len--; 273 rx_slots--; 274 } 275 } 276 277 static void 278 xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata, unsigned int isr) 279 { 280 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 281 282 if (isr & XGBE_INTR_TX_ABRT) { 283 state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE); 284 XI2C_IOREAD(pdata, IC_CLR_TX_ABRT); 285 } 286 287 if (isr & XGBE_INTR_STOP_DET) 288 XI2C_IOREAD(pdata, IC_CLR_STOP_DET); 289 } 290 291 static void 292 xgbe_i2c_isr(void *data) 293 { 294 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 295 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 296 unsigned int isr; 297 298 isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT); 299 axgbe_printf(3, "%s: isr 0x%x\n", __func__, isr); 300 if (!isr) 301 goto reissue_check; 302 303 axgbe_printf(3, "%s: I2C interrupt status=%#010x\n", __func__, isr); 304 305 xgbe_i2c_clear_isr_interrupts(pdata, isr); 306 307 if (isr & XGBE_INTR_TX_ABRT) { 308 axgbe_printf(1, "%s: I2C TX_ABRT received (%#010x) for target " 309 "%#04x\n", __func__, state->tx_abort_source, 310 state->op->target); 311 312 xgbe_i2c_disable_interrupts(pdata); 313 314 state->ret = -EIO; 315 goto out; 316 } 317 318 /* Check for data in the Rx fifo */ 319 xgbe_i2c_read(pdata); 320 321 /* Fill up the Tx fifo next */ 322 xgbe_i2c_write(pdata); 323 324 out: 325 /* Complete on an error or STOP condition */ 326 axgbe_printf(3, "%s: ret %d stop %d\n", __func__, state->ret, 327 XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET)); 328 329 if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET)) 330 pdata->i2c_complete = true; 331 332 return; 333 334 reissue_check: 335 /* Reissue interrupt if status is not clear */ 336 if (pdata->vdata->irq_reissue_support) 337 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 2); 338 } 339 340 static void 341 xgbe_i2c_set_mode(struct xgbe_prv_data *pdata) 342 { 343 unsigned int reg; 344 345 reg = XI2C_IOREAD(pdata, IC_CON); 346 XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1); 347 XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1); 348 XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1); 349 XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED); 350 XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1); 351 XI2C_IOWRITE(pdata, IC_CON, reg); 352 } 353 354 static void 355 xgbe_i2c_get_features(struct xgbe_prv_data *pdata) 356 { 357 struct xgbe_i2c *i2c = &pdata->i2c; 358 unsigned int reg; 359 360 reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1); 361 i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 362 MAX_SPEED_MODE); 363 i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 364 RX_BUFFER_DEPTH); 365 i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 366 TX_BUFFER_DEPTH); 367 368 axgbe_printf(3, "%s: I2C features: %s=%u, %s=%u, %s=%u\n", __func__, 369 "MAX_SPEED_MODE", i2c->max_speed_mode, 370 "RX_BUFFER_DEPTH", i2c->rx_fifo_size, 371 "TX_BUFFER_DEPTH", i2c->tx_fifo_size); 372 } 373 374 static void 375 xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr) 376 { 377 XI2C_IOWRITE(pdata, IC_TAR, addr); 378 } 379 380 static void 381 xgbe_i2c_combined_isr(struct xgbe_prv_data *pdata) 382 { 383 xgbe_i2c_isr(pdata); 384 } 385 386 static int 387 xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op) 388 { 389 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 390 unsigned long timeout; 391 int ret; 392 393 mtx_lock(&pdata->i2c_mutex); 394 395 axgbe_printf(3, "i2c xfer started ---->>>\n"); 396 397 ret = xgbe_i2c_disable(pdata); 398 if (ret) { 399 axgbe_error("failed to disable i2c master\n"); 400 goto out; 401 } 402 403 xgbe_i2c_set_target(pdata, op->target); 404 405 memset(state, 0, sizeof(*state)); 406 state->op = op; 407 state->tx_len = op->len; 408 state->tx_buf = op->buf; 409 state->rx_len = op->len; 410 state->rx_buf = op->buf; 411 412 xgbe_i2c_clear_all_interrupts(pdata); 413 ret = xgbe_i2c_enable(pdata); 414 if (ret) { 415 axgbe_error("failed to enable i2c master\n"); 416 goto out; 417 } 418 419 /* Enabling the interrupts will cause the TX FIFO empty interrupt to 420 * fire and begin to process the command via the ISR. 421 */ 422 xgbe_i2c_enable_interrupts(pdata); 423 424 timeout = ticks + (20 * hz); 425 while (ticks < timeout) { 426 427 if (!pdata->i2c_complete) { 428 DELAY(200); 429 continue; 430 } 431 432 axgbe_printf(1, "%s: I2C OP complete\n", __func__); 433 break; 434 } 435 436 if ((ticks >= timeout) && !pdata->i2c_complete) { 437 axgbe_error("%s: operation timed out\n", __func__); 438 ret = -ETIMEDOUT; 439 goto disable; 440 } 441 442 ret = state->ret; 443 axgbe_printf(3, "%s: i2c xfer ret %d abrt_source 0x%x \n", __func__, 444 ret, state->tx_abort_source); 445 if (ret) { 446 447 axgbe_error("%s: i2c xfer ret %d abrt_source 0x%x \n", __func__, 448 ret, state->tx_abort_source); 449 if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK) 450 ret = -ENOTCONN; 451 else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST) 452 ret = -EAGAIN; 453 } 454 455 axgbe_printf(3, "i2c xfer finished ---->>>\n"); 456 457 disable: 458 pdata->i2c_complete = false; 459 xgbe_i2c_disable_interrupts(pdata); 460 xgbe_i2c_disable(pdata); 461 462 out: 463 mtx_unlock(&pdata->i2c_mutex); 464 return (ret); 465 } 466 467 static void 468 xgbe_i2c_stop(struct xgbe_prv_data *pdata) 469 { 470 if (!pdata->i2c.started) 471 return; 472 473 axgbe_printf(3, "stopping I2C\n"); 474 475 pdata->i2c.started = 0; 476 477 xgbe_i2c_disable_interrupts(pdata); 478 xgbe_i2c_disable(pdata); 479 xgbe_i2c_clear_all_interrupts(pdata); 480 } 481 482 static int 483 xgbe_i2c_start(struct xgbe_prv_data *pdata) 484 { 485 if (pdata->i2c.started) 486 return (0); 487 488 pdata->i2c.started = 1; 489 490 return (0); 491 } 492 493 static int 494 xgbe_i2c_init(struct xgbe_prv_data *pdata) 495 { 496 int ret; 497 498 /* initialize lock for i2c */ 499 mtx_init(&pdata->i2c_mutex, "xgbe i2c mutex lock", NULL, MTX_DEF); 500 pdata->i2c_complete = false; 501 502 xgbe_i2c_disable_interrupts(pdata); 503 504 ret = xgbe_i2c_disable(pdata); 505 if (ret) { 506 axgbe_error("failed to disable i2c master\n"); 507 return (ret); 508 } 509 510 xgbe_i2c_get_features(pdata); 511 512 xgbe_i2c_set_mode(pdata); 513 514 xgbe_i2c_clear_all_interrupts(pdata); 515 516 xgbe_dump_i2c_registers(pdata); 517 518 return (0); 519 } 520 521 void 522 xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if) 523 { 524 i2c_if->i2c_init = xgbe_i2c_init; 525 526 i2c_if->i2c_start = xgbe_i2c_start; 527 i2c_if->i2c_stop = xgbe_i2c_stop; 528 529 i2c_if->i2c_xfer = xgbe_i2c_xfer; 530 531 i2c_if->i2c_isr = xgbe_i2c_combined_isr; 532 } 533