1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * Copyright (c) 2020 Advanced Micro Devices, Inc. 5 * 6 * This file is available to you under your choice of the following two 7 * licenses: 8 * 9 * License 1: GPLv2 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Redistribution and use in source and binary forms, with or without 60 * modification, are permitted provided that the following conditions are met: 61 * * Redistributions of source code must retain the above copyright 62 * notice, this list of conditions and the following disclaimer. 63 * * Redistributions in binary form must reproduce the above copyright 64 * notice, this list of conditions and the following disclaimer in the 65 * documentation and/or other materials provided with the distribution. 66 * * Neither the name of Advanced Micro Devices, Inc. nor the 67 * names of its contributors may be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 80 * 81 * This file incorporates work covered by the following copyright and 82 * permission notice: 83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 85 * Inc. unless otherwise expressly agreed to in writing between Synopsys 86 * and you. 87 * 88 * The Software IS NOT an item of Licensed Software or Licensed Product 89 * under any End User Software License Agreement or Agreement for Licensed 90 * Product with Synopsys or any supplement thereto. Permission is hereby 91 * granted, free of charge, to any person obtaining a copy of this software 92 * annotated with this license and the Software, to deal in the Software 93 * without restriction, including without limitation the rights to use, 94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 95 * of the Software, and to permit persons to whom the Software is furnished 96 * to do so, subject to the following conditions: 97 * 98 * The above copyright notice and this permission notice shall be included 99 * in all copies or substantial portions of the Software. 100 * 101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 111 * THE POSSIBILITY OF SUCH DAMAGE. 112 */ 113 114 #include <sys/cdefs.h> 115 #include "xgbe.h" 116 #include "xgbe-common.h" 117 118 #define XGBE_ABORT_COUNT 500 119 #define XGBE_DISABLE_COUNT 1000 120 121 #define XGBE_STD_SPEED 1 122 123 #define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX) 124 #define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX) 125 #define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX) 126 #define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX) 127 #define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL | \ 128 XGBE_INTR_TX_EMPTY | \ 129 XGBE_INTR_TX_ABRT | \ 130 XGBE_INTR_STOP_DET) 131 132 #define XGBE_I2C_READ BIT(8) 133 #define XGBE_I2C_STOP BIT(9) 134 135 static int 136 xgbe_i2c_abort(struct xgbe_prv_data *pdata) 137 { 138 unsigned int wait = XGBE_ABORT_COUNT; 139 140 /* Must be enabled to recognize the abort request */ 141 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1); 142 143 /* Issue the abort */ 144 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1); 145 146 while (wait--) { 147 if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT)) 148 return (0); 149 150 DELAY(500); 151 } 152 153 return (-EBUSY); 154 } 155 156 static int 157 xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable) 158 { 159 unsigned int wait = XGBE_DISABLE_COUNT; 160 unsigned int mode = enable ? 1 : 0; 161 162 while (wait--) { 163 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode); 164 if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode) 165 return (0); 166 167 DELAY(100); 168 } 169 170 return (-EBUSY); 171 } 172 173 static int 174 xgbe_i2c_disable(struct xgbe_prv_data *pdata) 175 { 176 unsigned int ret; 177 178 ret = xgbe_i2c_set_enable(pdata, false); 179 if (ret) { 180 /* Disable failed, try an abort */ 181 ret = xgbe_i2c_abort(pdata); 182 if (ret) { 183 axgbe_error("%s: i2c_abort %d\n", __func__, ret); 184 return (ret); 185 } 186 187 /* Abort succeeded, try to disable again */ 188 ret = xgbe_i2c_set_enable(pdata, false); 189 } 190 191 axgbe_printf(3, "%s: final i2c_disable %d\n", __func__, ret); 192 return (ret); 193 } 194 195 static int 196 xgbe_i2c_enable(struct xgbe_prv_data *pdata) 197 { 198 return (xgbe_i2c_set_enable(pdata, true)); 199 } 200 201 static void 202 xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata) 203 { 204 XI2C_IOREAD(pdata, IC_CLR_INTR); 205 } 206 207 static void 208 xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata) 209 { 210 XI2C_IOWRITE(pdata, IC_INTR_MASK, 0); 211 } 212 213 static void 214 xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata) 215 { 216 XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK); 217 } 218 219 static void 220 xgbe_i2c_write(struct xgbe_prv_data *pdata) 221 { 222 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 223 unsigned int tx_slots, cmd; 224 225 /* Configured to never receive Rx overflows, so fill up Tx fifo */ 226 tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR); 227 axgbe_printf(3, "%s: tx_slots %d tx_len %d\n", __func__, tx_slots, 228 state->tx_len); 229 230 while (tx_slots && state->tx_len) { 231 if (state->op->cmd == XGBE_I2C_CMD_READ) 232 cmd = XGBE_I2C_READ; 233 else 234 cmd = *state->tx_buf++; 235 236 axgbe_printf(3, "%s: cmd %d tx_len %d\n", __func__, cmd, 237 state->tx_len); 238 239 if (state->tx_len == 1) 240 XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1); 241 242 XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd); 243 244 tx_slots--; 245 state->tx_len--; 246 } 247 248 /* No more Tx operations, so ignore TX_EMPTY and return */ 249 if (!state->tx_len) 250 XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0); 251 } 252 253 static void 254 xgbe_i2c_read(struct xgbe_prv_data *pdata) 255 { 256 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 257 unsigned int rx_slots; 258 259 /* Anything to be read? */ 260 axgbe_printf(3, "%s: op cmd %d\n", __func__, state->op->cmd); 261 if (state->op->cmd != XGBE_I2C_CMD_READ) 262 return; 263 264 rx_slots = XI2C_IOREAD(pdata, IC_RXFLR); 265 axgbe_printf(3, "%s: rx_slots %d rx_len %d\n", __func__, rx_slots, 266 state->rx_len); 267 268 while (rx_slots && state->rx_len) { 269 *state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD); 270 state->rx_len--; 271 rx_slots--; 272 } 273 } 274 275 static void 276 xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata, unsigned int isr) 277 { 278 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 279 280 if (isr & XGBE_INTR_TX_ABRT) { 281 state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE); 282 XI2C_IOREAD(pdata, IC_CLR_TX_ABRT); 283 } 284 285 if (isr & XGBE_INTR_STOP_DET) 286 XI2C_IOREAD(pdata, IC_CLR_STOP_DET); 287 } 288 289 static void 290 xgbe_i2c_isr(void *data) 291 { 292 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; 293 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 294 unsigned int isr; 295 296 isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT); 297 axgbe_printf(3, "%s: isr 0x%x\n", __func__, isr); 298 if (!isr) 299 goto reissue_check; 300 301 axgbe_printf(3, "%s: I2C interrupt status=%#010x\n", __func__, isr); 302 303 xgbe_i2c_clear_isr_interrupts(pdata, isr); 304 305 if (isr & XGBE_INTR_TX_ABRT) { 306 axgbe_printf(1, "%s: I2C TX_ABRT received (%#010x) for target " 307 "%#04x\n", __func__, state->tx_abort_source, 308 state->op->target); 309 310 xgbe_i2c_disable_interrupts(pdata); 311 312 state->ret = -EIO; 313 goto out; 314 } 315 316 /* Check for data in the Rx fifo */ 317 xgbe_i2c_read(pdata); 318 319 /* Fill up the Tx fifo next */ 320 xgbe_i2c_write(pdata); 321 322 out: 323 /* Complete on an error or STOP condition */ 324 axgbe_printf(3, "%s: ret %d stop %d\n", __func__, state->ret, 325 XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET)); 326 327 if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET)) 328 pdata->i2c_complete = true; 329 330 return; 331 332 reissue_check: 333 /* Reissue interrupt if status is not clear */ 334 if (pdata->vdata->irq_reissue_support) 335 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 2); 336 } 337 338 static void 339 xgbe_i2c_set_mode(struct xgbe_prv_data *pdata) 340 { 341 unsigned int reg; 342 343 reg = XI2C_IOREAD(pdata, IC_CON); 344 XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1); 345 XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1); 346 XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1); 347 XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED); 348 XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1); 349 XI2C_IOWRITE(pdata, IC_CON, reg); 350 } 351 352 static void 353 xgbe_i2c_get_features(struct xgbe_prv_data *pdata) 354 { 355 struct xgbe_i2c *i2c = &pdata->i2c; 356 unsigned int reg; 357 358 reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1); 359 i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 360 MAX_SPEED_MODE); 361 i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 362 RX_BUFFER_DEPTH); 363 i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1, 364 TX_BUFFER_DEPTH); 365 366 axgbe_printf(3, "%s: I2C features: %s=%u, %s=%u, %s=%u\n", __func__, 367 "MAX_SPEED_MODE", i2c->max_speed_mode, 368 "RX_BUFFER_DEPTH", i2c->rx_fifo_size, 369 "TX_BUFFER_DEPTH", i2c->tx_fifo_size); 370 } 371 372 static void 373 xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr) 374 { 375 XI2C_IOWRITE(pdata, IC_TAR, addr); 376 } 377 378 static void 379 xgbe_i2c_combined_isr(struct xgbe_prv_data *pdata) 380 { 381 xgbe_i2c_isr(pdata); 382 } 383 384 static int 385 xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op) 386 { 387 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state; 388 unsigned long timeout; 389 int ret; 390 391 mtx_lock(&pdata->i2c_mutex); 392 393 axgbe_printf(3, "i2c xfer started ---->>>\n"); 394 395 ret = xgbe_i2c_disable(pdata); 396 if (ret) { 397 axgbe_error("failed to disable i2c master\n"); 398 goto out; 399 } 400 401 xgbe_i2c_set_target(pdata, op->target); 402 403 memset(state, 0, sizeof(*state)); 404 state->op = op; 405 state->tx_len = op->len; 406 state->tx_buf = op->buf; 407 state->rx_len = op->len; 408 state->rx_buf = op->buf; 409 410 xgbe_i2c_clear_all_interrupts(pdata); 411 ret = xgbe_i2c_enable(pdata); 412 if (ret) { 413 axgbe_error("failed to enable i2c master\n"); 414 goto out; 415 } 416 417 /* Enabling the interrupts will cause the TX FIFO empty interrupt to 418 * fire and begin to process the command via the ISR. 419 */ 420 xgbe_i2c_enable_interrupts(pdata); 421 422 timeout = ticks + (20 * hz); 423 while (ticks < timeout) { 424 425 if (!pdata->i2c_complete) { 426 DELAY(200); 427 continue; 428 } 429 430 axgbe_printf(1, "%s: I2C OP complete\n", __func__); 431 break; 432 } 433 434 if ((ticks >= timeout) && !pdata->i2c_complete) { 435 axgbe_error("%s: operation timed out\n", __func__); 436 ret = -ETIMEDOUT; 437 goto disable; 438 } 439 440 ret = state->ret; 441 axgbe_printf(3, "%s: i2c xfer ret %d abrt_source 0x%x \n", __func__, 442 ret, state->tx_abort_source); 443 if (ret) { 444 445 axgbe_error("%s: i2c xfer ret %d abrt_source 0x%x \n", __func__, 446 ret, state->tx_abort_source); 447 if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK) 448 ret = -ENOTCONN; 449 else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST) 450 ret = -EAGAIN; 451 } 452 453 axgbe_printf(3, "i2c xfer finished ---->>>\n"); 454 455 disable: 456 pdata->i2c_complete = false; 457 xgbe_i2c_disable_interrupts(pdata); 458 xgbe_i2c_disable(pdata); 459 460 out: 461 mtx_unlock(&pdata->i2c_mutex); 462 return (ret); 463 } 464 465 static void 466 xgbe_i2c_stop(struct xgbe_prv_data *pdata) 467 { 468 if (!pdata->i2c.started) 469 return; 470 471 axgbe_printf(3, "stopping I2C\n"); 472 473 pdata->i2c.started = 0; 474 475 xgbe_i2c_disable_interrupts(pdata); 476 xgbe_i2c_disable(pdata); 477 xgbe_i2c_clear_all_interrupts(pdata); 478 } 479 480 static int 481 xgbe_i2c_start(struct xgbe_prv_data *pdata) 482 { 483 if (pdata->i2c.started) 484 return (0); 485 486 pdata->i2c.started = 1; 487 488 return (0); 489 } 490 491 static int 492 xgbe_i2c_init(struct xgbe_prv_data *pdata) 493 { 494 int ret; 495 496 /* initialize lock for i2c */ 497 mtx_init(&pdata->i2c_mutex, "xgbe i2c mutex lock", NULL, MTX_DEF); 498 pdata->i2c_complete = false; 499 500 xgbe_i2c_disable_interrupts(pdata); 501 502 ret = xgbe_i2c_disable(pdata); 503 if (ret) { 504 axgbe_error("failed to disable i2c master\n"); 505 return (ret); 506 } 507 508 xgbe_i2c_get_features(pdata); 509 510 xgbe_i2c_set_mode(pdata); 511 512 xgbe_i2c_clear_all_interrupts(pdata); 513 514 xgbe_dump_i2c_registers(pdata); 515 516 return (0); 517 } 518 519 void 520 xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if) 521 { 522 i2c_if->i2c_init = xgbe_i2c_init; 523 524 i2c_if->i2c_start = xgbe_i2c_start; 525 i2c_if->i2c_stop = xgbe_i2c_stop; 526 527 i2c_if->i2c_xfer = xgbe_i2c_xfer; 528 529 i2c_if->i2c_isr = xgbe_i2c_combined_isr; 530 } 531