1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117 #include <sys/cdefs.h> 118 __FBSDID("$FreeBSD$"); 119 120 #include <sys/param.h> 121 #include <sys/kernel.h> 122 123 #include "xgbe.h" 124 #include "xgbe-common.h" 125 126 #include <net/if_dl.h> 127 #include <net/if_var.h> 128 129 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, 130 unsigned int usec) 131 { 132 unsigned long rate; 133 unsigned int ret; 134 135 DBGPR("-->xgbe_usec_to_riwt\n"); 136 137 rate = pdata->sysclk_rate; 138 139 /* 140 * Convert the input usec value to the watchdog timer value. Each 141 * watchdog timer value is equivalent to 256 clock cycles. 142 * Calculate the required value as: 143 * ( usec * ( system_clock_mhz / 10^6 ) / 256 144 */ 145 ret = (usec * (rate / 1000000)) / 256; 146 147 DBGPR("<--xgbe_usec_to_riwt\n"); 148 149 return ret; 150 } 151 152 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, 153 unsigned int riwt) 154 { 155 unsigned long rate; 156 unsigned int ret; 157 158 DBGPR("-->xgbe_riwt_to_usec\n"); 159 160 rate = pdata->sysclk_rate; 161 162 /* 163 * Convert the input watchdog timer value to the usec value. Each 164 * watchdog timer value is equivalent to 256 clock cycles. 165 * Calculate the required value as: 166 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 ) 167 */ 168 ret = (riwt * 256) / (rate / 1000000); 169 170 DBGPR("<--xgbe_riwt_to_usec\n"); 171 172 return ret; 173 } 174 175 static int xgbe_config_pblx8(struct xgbe_prv_data *pdata) 176 { 177 struct xgbe_channel *channel; 178 unsigned int i; 179 180 channel = pdata->channel; 181 for (i = 0; i < pdata->channel_count; i++, channel++) 182 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8, 183 pdata->pblx8); 184 185 return 0; 186 } 187 188 static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata) 189 { 190 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL); 191 } 192 193 static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata) 194 { 195 struct xgbe_channel *channel; 196 unsigned int i; 197 198 channel = pdata->channel; 199 for (i = 0; i < pdata->channel_count; i++, channel++) { 200 if (!channel->tx_ring) 201 break; 202 203 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL, 204 pdata->tx_pbl); 205 } 206 207 return 0; 208 } 209 210 static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata) 211 { 212 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL); 213 } 214 215 static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata) 216 { 217 struct xgbe_channel *channel; 218 unsigned int i; 219 220 channel = pdata->channel; 221 for (i = 0; i < pdata->channel_count; i++, channel++) { 222 if (!channel->rx_ring) 223 break; 224 225 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL, 226 pdata->rx_pbl); 227 } 228 229 return 0; 230 } 231 232 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) 233 { 234 struct xgbe_channel *channel; 235 unsigned int i; 236 237 channel = pdata->channel; 238 for (i = 0; i < pdata->channel_count; i++, channel++) { 239 if (!channel->tx_ring) 240 break; 241 242 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP, 243 pdata->tx_osp_mode); 244 } 245 246 return 0; 247 } 248 249 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 250 { 251 unsigned int i; 252 253 for (i = 0; i < pdata->rx_q_count; i++) 254 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); 255 256 return 0; 257 } 258 259 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) 260 { 261 unsigned int i; 262 263 for (i = 0; i < pdata->tx_q_count; i++) 264 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); 265 266 return 0; 267 } 268 269 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, 270 unsigned int val) 271 { 272 unsigned int i; 273 274 for (i = 0; i < pdata->rx_q_count; i++) 275 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); 276 277 return 0; 278 } 279 280 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, 281 unsigned int val) 282 { 283 unsigned int i; 284 285 for (i = 0; i < pdata->tx_q_count; i++) 286 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); 287 288 return 0; 289 } 290 291 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) 292 { 293 struct xgbe_channel *channel; 294 unsigned int i; 295 296 channel = pdata->channel; 297 for (i = 0; i < pdata->channel_count; i++, channel++) { 298 if (!channel->rx_ring) 299 break; 300 301 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT, 302 pdata->rx_riwt); 303 } 304 305 return 0; 306 } 307 308 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) 309 { 310 return 0; 311 } 312 313 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) 314 { 315 struct xgbe_channel *channel; 316 unsigned int i; 317 318 channel = pdata->channel; 319 for (i = 0; i < pdata->channel_count; i++, channel++) { 320 if (!channel->rx_ring) 321 break; 322 323 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ, 324 pdata->rx_buf_size); 325 } 326 } 327 328 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) 329 { 330 struct xgbe_channel *channel; 331 unsigned int i; 332 333 channel = pdata->channel; 334 for (i = 0; i < pdata->channel_count; i++, channel++) { 335 if (!channel->tx_ring) 336 break; 337 338 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1); 339 } 340 } 341 342 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) 343 { 344 struct xgbe_channel *channel; 345 unsigned int i; 346 347 channel = pdata->channel; 348 for (i = 0; i < pdata->channel_count; i++, channel++) { 349 if (!channel->rx_ring) 350 break; 351 352 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1); 353 } 354 355 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); 356 } 357 358 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) 359 { 360 if (!pdata->hw_feat.rss) 361 return -EOPNOTSUPP; 362 363 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); 364 365 return 0; 366 } 367 368 static void xgbe_config_rss(struct xgbe_prv_data *pdata) 369 { 370 371 if (!pdata->hw_feat.rss) 372 return; 373 374 xgbe_disable_rss(pdata); 375 } 376 377 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 378 { 379 unsigned int max_q_count, q_count; 380 unsigned int reg, reg_val; 381 unsigned int i; 382 383 /* Clear MTL flow control */ 384 for (i = 0; i < pdata->rx_q_count; i++) 385 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); 386 387 /* Clear MAC flow control */ 388 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 389 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 390 reg = MAC_Q0TFCR; 391 for (i = 0; i < q_count; i++) { 392 reg_val = XGMAC_IOREAD(pdata, reg); 393 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0); 394 XGMAC_IOWRITE(pdata, reg, reg_val); 395 396 reg += MAC_QTFCR_INC; 397 } 398 399 return 0; 400 } 401 402 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 403 { 404 unsigned int max_q_count, q_count; 405 unsigned int reg, reg_val; 406 unsigned int i; 407 408 /* Set MTL flow control */ 409 for (i = 0; i < pdata->rx_q_count; i++) { 410 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1); 411 } 412 413 /* Set MAC flow control */ 414 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; 415 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); 416 reg = MAC_Q0TFCR; 417 for (i = 0; i < q_count; i++) { 418 reg_val = XGMAC_IOREAD(pdata, reg); 419 420 /* Enable transmit flow control */ 421 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1); 422 /* Set pause time */ 423 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff); 424 425 XGMAC_IOWRITE(pdata, reg, reg_val); 426 427 reg += MAC_QTFCR_INC; 428 } 429 430 return 0; 431 } 432 433 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) 434 { 435 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); 436 437 return 0; 438 } 439 440 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) 441 { 442 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); 443 444 return 0; 445 } 446 447 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) 448 { 449 450 if (pdata->tx_pause) 451 xgbe_enable_tx_flow_control(pdata); 452 else 453 xgbe_disable_tx_flow_control(pdata); 454 455 return 0; 456 } 457 458 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) 459 { 460 461 if (pdata->rx_pause) 462 xgbe_enable_rx_flow_control(pdata); 463 else 464 xgbe_disable_rx_flow_control(pdata); 465 466 return 0; 467 } 468 469 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) 470 { 471 472 xgbe_config_tx_flow_control(pdata); 473 xgbe_config_rx_flow_control(pdata); 474 475 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 476 } 477 478 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) 479 { 480 struct xgbe_channel *channel; 481 unsigned int dma_ch_isr, dma_ch_ier; 482 unsigned int i; 483 484 channel = pdata->channel; 485 for (i = 0; i < pdata->channel_count; i++, channel++) { 486 /* Clear all the interrupts which are set */ 487 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 488 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 489 490 /* Clear all interrupt enable bits */ 491 dma_ch_ier = 0; 492 493 /* Enable following interrupts 494 * NIE - Normal Interrupt Summary Enable 495 * AIE - Abnormal Interrupt Summary Enable 496 * FBEE - Fatal Bus Error Enable 497 */ 498 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1); 499 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1); 500 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); 501 502 if (channel->tx_ring) { 503 /* Enable the following Tx interrupts 504 * TIE - Transmit Interrupt Enable (unless using 505 * per channel interrupts) 506 */ 507 if (!pdata->per_channel_irq) 508 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 509 } 510 if (channel->rx_ring) { 511 /* Enable following Rx interrupts 512 * RBUE - Receive Buffer Unavailable Enable 513 * RIE - Receive Interrupt Enable (unless using 514 * per channel interrupts) 515 */ 516 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); 517 if (!pdata->per_channel_irq) 518 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 519 } 520 521 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 522 } 523 } 524 525 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) 526 { 527 unsigned int mtl_q_isr; 528 unsigned int q_count, i; 529 530 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); 531 for (i = 0; i < q_count; i++) { 532 /* Clear all the interrupts which are set */ 533 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); 534 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); 535 536 /* No MTL interrupts to be enabled */ 537 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); 538 } 539 } 540 541 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) 542 { 543 unsigned int mac_ier = 0; 544 545 /* Enable Timestamp interrupt */ 546 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1); 547 548 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); 549 550 /* Enable all counter interrupts */ 551 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); 552 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); 553 } 554 555 static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata) 556 { 557 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3) 558 return 0; 559 560 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3); 561 562 return 0; 563 } 564 565 static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata) 566 { 567 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2) 568 return 0; 569 570 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2); 571 572 return 0; 573 } 574 575 static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata) 576 { 577 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0) 578 return 0; 579 580 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0); 581 582 return 0; 583 } 584 585 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 586 { 587 /* Put the VLAN tag in the Rx descriptor */ 588 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); 589 590 /* Don't check the VLAN type */ 591 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); 592 593 /* Check only C-TAG (0x8100) packets */ 594 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); 595 596 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ 597 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); 598 599 /* Enable VLAN tag stripping */ 600 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); 601 602 return 0; 603 } 604 605 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) 606 { 607 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); 608 609 return 0; 610 } 611 612 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 613 { 614 /* Enable VLAN filtering */ 615 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); 616 617 /* Enable VLAN Hash Table filtering */ 618 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); 619 620 /* Disable VLAN tag inverse matching */ 621 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); 622 623 /* Only filter on the lower 12-bits of the VLAN tag */ 624 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); 625 626 /* In order for the VLAN Hash Table filtering to be effective, 627 * the VLAN tag identifier in the VLAN Tag Register must not 628 * be zero. Set the VLAN tag identifier to "1" to enable the 629 * VLAN Hash Table filtering. This implies that a VLAN tag of 630 * 1 will always pass filtering. 631 */ 632 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); 633 634 return 0; 635 } 636 637 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) 638 { 639 /* Disable VLAN filtering */ 640 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); 641 642 return 0; 643 } 644 645 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) 646 { 647 u16 vlan_hash_table = 0; 648 649 /* Set the VLAN Hash Table filtering register */ 650 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); 651 652 return 0; 653 } 654 655 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, 656 unsigned int enable) 657 { 658 unsigned int val = enable ? 1 : 0; 659 660 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) 661 return 0; 662 663 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); 664 665 /* Hardware will still perform VLAN filtering in promiscuous mode */ 666 xgbe_disable_rx_vlan_filtering(pdata); 667 668 return 0; 669 } 670 671 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, 672 unsigned int enable) 673 { 674 unsigned int val = enable ? 1 : 0; 675 676 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) 677 return 0; 678 679 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); 680 681 return 0; 682 } 683 684 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, 685 char *addr, unsigned int *mac_reg) 686 { 687 unsigned int mac_addr_hi, mac_addr_lo; 688 u8 *mac_addr; 689 690 mac_addr_lo = 0; 691 mac_addr_hi = 0; 692 693 if (addr) { 694 mac_addr = (u8 *)&mac_addr_lo; 695 mac_addr[0] = addr[0]; 696 mac_addr[1] = addr[1]; 697 mac_addr[2] = addr[2]; 698 mac_addr[3] = addr[3]; 699 mac_addr = (u8 *)&mac_addr_hi; 700 mac_addr[0] = addr[4]; 701 mac_addr[1] = addr[5]; 702 703 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1); 704 } 705 706 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); 707 *mac_reg += MAC_MACA_INC; 708 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); 709 *mac_reg += MAC_MACA_INC; 710 } 711 712 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) 713 { 714 unsigned int mac_reg; 715 unsigned int addn_macs; 716 717 mac_reg = MAC_MACA1HR; 718 addn_macs = pdata->hw_feat.addn_mac; 719 720 xgbe_set_mac_reg(pdata, pdata->mac_addr, &mac_reg); 721 addn_macs--; 722 723 /* Clear remaining additional MAC address entries */ 724 while (addn_macs--) 725 xgbe_set_mac_reg(pdata, NULL, &mac_reg); 726 } 727 728 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) 729 { 730 xgbe_set_mac_addn_addrs(pdata); 731 732 return 0; 733 } 734 735 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr) 736 { 737 unsigned int mac_addr_hi, mac_addr_lo; 738 739 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0); 740 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) | 741 (addr[1] << 8) | (addr[0] << 0); 742 743 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); 744 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); 745 746 return 0; 747 } 748 749 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) 750 { 751 unsigned int pr_mode, am_mode; 752 753 /* XXX */ 754 pr_mode = 0; 755 am_mode = 0; 756 757 xgbe_set_promiscuous_mode(pdata, pr_mode); 758 xgbe_set_all_multicast_mode(pdata, am_mode); 759 760 xgbe_add_mac_addresses(pdata); 761 762 return 0; 763 } 764 765 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 766 int mmd_reg) 767 { 768 unsigned long flags; 769 unsigned int mmd_address; 770 int mmd_data; 771 772 if (mmd_reg & MII_ADDR_C45) 773 mmd_address = mmd_reg & ~MII_ADDR_C45; 774 else 775 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 776 777 /* The PCS registers are accessed using mmio. The underlying APB3 778 * management interface uses indirect addressing to access the MMD 779 * register sets. This requires accessing of the PCS register in two 780 * phases, an address phase and a data phase. 781 * 782 * The mmio interface is based on 32-bit offsets and values. All 783 * register offsets must therefore be adjusted by left shifting the 784 * offset 2 bits and reading 32 bits of data. 785 */ 786 spin_lock_irqsave(&pdata->xpcs_lock, flags); 787 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); 788 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2); 789 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 790 791 return mmd_data; 792 } 793 794 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, 795 int mmd_reg, int mmd_data) 796 { 797 unsigned int mmd_address; 798 unsigned long flags; 799 800 if (mmd_reg & MII_ADDR_C45) 801 mmd_address = mmd_reg & ~MII_ADDR_C45; 802 else 803 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); 804 805 /* The PCS registers are accessed using mmio. The underlying APB3 806 * management interface uses indirect addressing to access the MMD 807 * register sets. This requires accessing of the PCS register in two 808 * phases, an address phase and a data phase. 809 * 810 * The mmio interface is based on 32-bit offsets and values. All 811 * register offsets must therefore be adjusted by left shifting the 812 * offset 2 bits and reading 32 bits of data. 813 */ 814 spin_lock_irqsave(&pdata->xpcs_lock, flags); 815 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8); 816 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); 817 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); 818 } 819 820 static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc) 821 { 822 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN); 823 } 824 825 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) 826 { 827 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); 828 829 return 0; 830 } 831 832 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) 833 { 834 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); 835 836 return 0; 837 } 838 839 static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata) 840 { 841 struct xgbe_ring_desc *rdesc = rdata->rdesc; 842 843 /* Reset the Tx descriptor 844 * Set buffer 1 (lo) address to zero 845 * Set buffer 1 (hi) address to zero 846 * Reset all other control bits (IC, TTSE, B2L & B1L) 847 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc) 848 */ 849 rdesc->desc0 = 0; 850 rdesc->desc1 = 0; 851 rdesc->desc2 = 0; 852 rdesc->desc3 = 0; 853 854 dsb(sy); 855 } 856 857 static void xgbe_tx_desc_init(struct xgbe_channel *channel) 858 { 859 struct xgbe_ring *ring = channel->tx_ring; 860 struct xgbe_ring_data *rdata; 861 int i; 862 int start_index = ring->cur; 863 864 DBGPR("-->tx_desc_init\n"); 865 866 /* Initialze all descriptors */ 867 for (i = 0; i < ring->rdesc_count; i++) { 868 rdata = XGBE_GET_DESC_DATA(ring, i); 869 870 /* Initialize Tx descriptor */ 871 xgbe_tx_desc_reset(rdata); 872 } 873 874 /* Update the total number of Tx descriptors */ 875 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1); 876 877 /* Update the starting address of descriptor ring */ 878 rdata = XGBE_GET_DESC_DATA(ring, start_index); 879 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI, 880 upper_32_bits(rdata->rdata_paddr)); 881 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO, 882 lower_32_bits(rdata->rdata_paddr)); 883 884 DBGPR("<--tx_desc_init\n"); 885 } 886 887 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, 888 struct xgbe_ring_data *rdata, unsigned int index) 889 { 890 struct xgbe_ring_desc *rdesc = rdata->rdesc; 891 unsigned int inte; 892 893 inte = 1; 894 895 /* Reset the Rx descriptor 896 * Set buffer 1 (lo) address to header dma address (lo) 897 * Set buffer 1 (hi) address to header dma address (hi) 898 * Set buffer 2 (lo) address to buffer dma address (lo) 899 * Set buffer 2 (hi) address to buffer dma address (hi) and 900 * set control bits OWN and INTE 901 */ 902 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->mbuf_hdr_paddr)); 903 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->mbuf_hdr_paddr)); 904 rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->mbuf_data_paddr)); 905 rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->mbuf_data_paddr)); 906 907 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE, inte); 908 909 dsb(sy); 910 911 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1); 912 913 dsb(sy); 914 } 915 916 static void xgbe_rx_desc_init(struct xgbe_channel *channel) 917 { 918 struct xgbe_prv_data *pdata = channel->pdata; 919 struct xgbe_ring *ring = channel->rx_ring; 920 struct xgbe_ring_data *rdata; 921 unsigned int start_index = ring->cur; 922 unsigned int i; 923 924 DBGPR("-->rx_desc_init\n"); 925 926 /* Initialize all descriptors */ 927 for (i = 0; i < ring->rdesc_count; i++) { 928 rdata = XGBE_GET_DESC_DATA(ring, i); 929 930 /* Initialize Rx descriptor */ 931 xgbe_rx_desc_reset(pdata, rdata, i); 932 } 933 934 bus_dmamap_sync(ring->rdesc_dmat, ring->rdesc_map, 935 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 936 937 /* Update the total number of Rx descriptors */ 938 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1); 939 940 /* Update the starting address of descriptor ring */ 941 rdata = XGBE_GET_DESC_DATA(ring, start_index); 942 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI, 943 upper_32_bits(rdata->rdata_paddr)); 944 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO, 945 lower_32_bits(rdata->rdata_paddr)); 946 947 /* Update the Rx Descriptor Tail Pointer */ 948 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1); 949 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 950 lower_32_bits(rdata->rdata_paddr)); 951 952 DBGPR("<--rx_desc_init\n"); 953 } 954 955 static void xgbe_tx_start_xmit(struct xgbe_channel *channel, 956 struct xgbe_ring *ring) 957 { 958 struct xgbe_ring_data *rdata; 959 960 /* Issue a poll command to Tx DMA by writing address 961 * of next immediate free descriptor */ 962 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 963 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO, 964 lower_32_bits(rdata->rdata_paddr)); 965 966 ring->tx.xmit_more = 0; 967 } 968 969 static void xgbe_dev_xmit(struct xgbe_channel *channel) 970 { 971 struct xgbe_prv_data *pdata = channel->pdata; 972 struct xgbe_ring *ring = channel->tx_ring; 973 struct xgbe_ring_data *rdata; 974 struct xgbe_ring_desc *rdesc; 975 struct xgbe_packet_data *packet = &ring->packet_data; 976 unsigned int tx_set_ic; 977 int start_index = ring->cur; 978 int cur_index = ring->cur; 979 int i; 980 981 DBGPR("-->xgbe_dev_xmit\n"); 982 983 /* Determine if an interrupt should be generated for this Tx: 984 * Interrupt: 985 * - Tx frame count exceeds the frame count setting 986 * - Addition of Tx frame count to the frame count since the 987 * last interrupt was set exceeds the frame count setting 988 * No interrupt: 989 * - No frame count setting specified (ethtool -C ethX tx-frames 0) 990 * - Addition of Tx frame count to the frame count since the 991 * last interrupt was set does not exceed the frame count setting 992 */ 993 ring->coalesce_count += packet->tx_packets; 994 if (!pdata->tx_frames) 995 tx_set_ic = 0; 996 else if (packet->tx_packets > pdata->tx_frames) 997 tx_set_ic = 1; 998 else if ((ring->coalesce_count % pdata->tx_frames) < 999 packet->tx_packets) 1000 tx_set_ic = 1; 1001 else 1002 tx_set_ic = 0; 1003 tx_set_ic = 1; 1004 1005 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1006 rdesc = rdata->rdesc; 1007 1008 /* Update buffer address (for TSO this is the header) */ 1009 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->mbuf_data_paddr)); 1010 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->mbuf_data_paddr)); 1011 1012 /* Update the buffer length */ 1013 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1014 rdata->mbuf_len); 1015 1016 /* Timestamp enablement check */ 1017 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1018 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1); 1019 1020 /* Mark it as First Descriptor */ 1021 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1); 1022 1023 /* Mark it as a NORMAL descriptor */ 1024 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1025 1026 /* Set OWN bit if not the first descriptor */ 1027 if (cur_index != start_index) 1028 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1029 1030 /* Enable CRC and Pad Insertion */ 1031 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0); 1032 1033 /* Set the total length to be transmitted */ 1034 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL, 1035 packet->length); 1036 1037 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) { 1038 cur_index++; 1039 rdata = XGBE_GET_DESC_DATA(ring, cur_index); 1040 rdesc = rdata->rdesc; 1041 1042 /* Update buffer address */ 1043 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->mbuf_data_paddr)); 1044 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->mbuf_data_paddr)); 1045 1046 /* Update the buffer length */ 1047 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L, 1048 rdata->mbuf_len); 1049 1050 /* Set OWN bit */ 1051 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1052 1053 /* Mark it as NORMAL descriptor */ 1054 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0); 1055 } 1056 1057 /* Set LAST bit for the last descriptor */ 1058 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1); 1059 1060 /* Set IC bit based on Tx coalescing settings */ 1061 if (tx_set_ic) 1062 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1); 1063 1064 /* Save the Tx info to report back during cleanup */ 1065 rdata->tx.packets = packet->tx_packets; 1066 rdata->tx.bytes = packet->tx_bytes; 1067 1068 /* Sync the DMA buffers */ 1069 bus_dmamap_sync(ring->rdesc_dmat, ring->rdesc_map, 1070 BUS_DMASYNC_PREWRITE); 1071 bus_dmamap_sync(ring->mbuf_dmat, ring->mbuf_map, 1072 BUS_DMASYNC_PREWRITE); 1073 1074 /* In case the Tx DMA engine is running, make sure everything 1075 * is written to the descriptor(s) before setting the OWN bit 1076 * for the first descriptor 1077 */ 1078 1079 /* Set OWN bit for the first descriptor */ 1080 rdata = XGBE_GET_DESC_DATA(ring, start_index); 1081 rdesc = rdata->rdesc; 1082 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1); 1083 1084 /* Sync to ensure the OWN bit was seen */ 1085 bus_dmamap_sync(ring->rdesc_dmat, ring->rdesc_map, 1086 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1087 1088 ring->cur = cur_index + 1; 1089 xgbe_tx_start_xmit(channel, ring); 1090 1091 DBGPR(" %s: descriptors %u to %u written\n", 1092 channel->name, start_index & (ring->rdesc_count - 1), 1093 (ring->cur - 1) & (ring->rdesc_count - 1)); 1094 1095 DBGPR("<--xgbe_dev_xmit\n"); 1096 } 1097 1098 static int xgbe_dev_read(struct xgbe_channel *channel) 1099 { 1100 struct xgbe_ring *ring = channel->rx_ring; 1101 struct xgbe_ring_data *rdata; 1102 struct xgbe_ring_desc *rdesc; 1103 struct xgbe_packet_data *packet = &ring->packet_data; 1104 unsigned int err, etlt; 1105 1106 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur); 1107 1108 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1109 rdesc = rdata->rdesc; 1110 1111 bus_dmamap_sync(ring->rdesc_dmat, ring->rdesc_map, 1112 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1113 1114 dsb(sy); 1115 1116 /* Check for data availability */ 1117 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN)) 1118 return 1; 1119 1120 dsb(sy); 1121 1122 /* Normal Descriptor, be sure Context Descriptor bit is off */ 1123 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0); 1124 1125 /* Indicate if a Context Descriptor is next */ 1126 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA)) 1127 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1128 CONTEXT_NEXT, 1); 1129 1130 /* Get the header length */ 1131 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD)) { 1132 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2, 1133 RX_NORMAL_DESC2, HL); 1134 } 1135 1136 /* Get the packet length */ 1137 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL); 1138 1139 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) { 1140 /* Not all the data has been transferred for this packet */ 1141 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1142 INCOMPLETE, 1); 1143 return 0; 1144 } 1145 1146 /* This is the last of the data for this packet */ 1147 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1148 INCOMPLETE, 0); 1149 1150 /* Check for errors (only valid in last descriptor) */ 1151 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES); 1152 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT); 1153 1154 if (err && etlt) { 1155 if ((etlt == 0x05) || (etlt == 0x06)) 1156 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, 1157 CSUM_DONE, 0); 1158 else 1159 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS, 1160 FRAME, 1); 1161 } 1162 1163 bus_dmamap_sync(ring->mbuf_dmat, rdata->mbuf_map, 1164 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1165 1166 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name, 1167 ring->cur & (ring->rdesc_count - 1), ring->cur); 1168 1169 return 0; 1170 } 1171 1172 static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc) 1173 { 1174 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */ 1175 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT); 1176 } 1177 1178 static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc) 1179 { 1180 /* Rx and Tx share LD bit, so check TDES3.LD bit */ 1181 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD); 1182 } 1183 1184 static int xgbe_enable_int(struct xgbe_channel *channel, 1185 enum xgbe_int int_id) 1186 { 1187 unsigned int dma_ch_ier; 1188 1189 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); 1190 1191 switch (int_id) { 1192 case XGMAC_INT_DMA_CH_SR_TI: 1193 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 1194 break; 1195 case XGMAC_INT_DMA_CH_SR_TPS: 1196 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1); 1197 break; 1198 case XGMAC_INT_DMA_CH_SR_TBU: 1199 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1); 1200 break; 1201 case XGMAC_INT_DMA_CH_SR_RI: 1202 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 1203 break; 1204 case XGMAC_INT_DMA_CH_SR_RBU: 1205 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1); 1206 break; 1207 case XGMAC_INT_DMA_CH_SR_RPS: 1208 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1); 1209 break; 1210 case XGMAC_INT_DMA_CH_SR_TI_RI: 1211 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1); 1212 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1); 1213 break; 1214 case XGMAC_INT_DMA_CH_SR_FBE: 1215 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1); 1216 break; 1217 case XGMAC_INT_DMA_ALL: 1218 dma_ch_ier |= channel->saved_ier; 1219 break; 1220 default: 1221 return -1; 1222 } 1223 1224 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 1225 1226 return 0; 1227 } 1228 1229 static int xgbe_disable_int(struct xgbe_channel *channel, 1230 enum xgbe_int int_id) 1231 { 1232 unsigned int dma_ch_ier; 1233 1234 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER); 1235 1236 switch (int_id) { 1237 case XGMAC_INT_DMA_CH_SR_TI: 1238 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); 1239 break; 1240 case XGMAC_INT_DMA_CH_SR_TPS: 1241 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0); 1242 break; 1243 case XGMAC_INT_DMA_CH_SR_TBU: 1244 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0); 1245 break; 1246 case XGMAC_INT_DMA_CH_SR_RI: 1247 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); 1248 break; 1249 case XGMAC_INT_DMA_CH_SR_RBU: 1250 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0); 1251 break; 1252 case XGMAC_INT_DMA_CH_SR_RPS: 1253 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0); 1254 break; 1255 case XGMAC_INT_DMA_CH_SR_TI_RI: 1256 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0); 1257 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0); 1258 break; 1259 case XGMAC_INT_DMA_CH_SR_FBE: 1260 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0); 1261 break; 1262 case XGMAC_INT_DMA_ALL: 1263 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK; 1264 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK; 1265 break; 1266 default: 1267 return -1; 1268 } 1269 1270 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier); 1271 1272 return 0; 1273 } 1274 1275 static int xgbe_exit(struct xgbe_prv_data *pdata) 1276 { 1277 unsigned int count = 2000; 1278 1279 DBGPR("-->xgbe_exit\n"); 1280 1281 /* Issue a software reset */ 1282 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); 1283 DELAY(10); 1284 1285 /* Poll Until Poll Condition */ 1286 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) 1287 DELAY(500); 1288 1289 if (!count) 1290 return -EBUSY; 1291 1292 DBGPR("<--xgbe_exit\n"); 1293 1294 return 0; 1295 } 1296 1297 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 1298 { 1299 unsigned int i, count; 1300 1301 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) 1302 return 0; 1303 1304 for (i = 0; i < pdata->tx_q_count; i++) 1305 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); 1306 1307 /* Poll Until Poll Condition */ 1308 for (i = 0; i < pdata->tx_q_count; i++) { 1309 count = 2000; 1310 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, 1311 MTL_Q_TQOMR, FTQ)) 1312 DELAY(500); 1313 1314 if (!count) 1315 return -EBUSY; 1316 } 1317 1318 return 0; 1319 } 1320 1321 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) 1322 { 1323 /* Set enhanced addressing mode */ 1324 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1); 1325 1326 /* Set the System Bus mode */ 1327 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1); 1328 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1); 1329 } 1330 1331 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) 1332 { 1333 unsigned int arcache, awcache; 1334 1335 arcache = 0; 1336 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache); 1337 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain); 1338 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache); 1339 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain); 1340 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache); 1341 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain); 1342 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache); 1343 1344 awcache = 0; 1345 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache); 1346 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain); 1347 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache); 1348 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain); 1349 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache); 1350 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain); 1351 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache); 1352 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain); 1353 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache); 1354 } 1355 1356 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 1357 { 1358 unsigned int i; 1359 1360 /* Set Tx to weighted round robin scheduling algorithm */ 1361 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); 1362 1363 /* Set Tx traffic classes to use WRR algorithm with equal weights */ 1364 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { 1365 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, 1366 MTL_TSA_ETS); 1367 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); 1368 } 1369 1370 /* Set Rx to strict priority algorithm */ 1371 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); 1372 } 1373 1374 static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size, 1375 unsigned int queue_count) 1376 { 1377 unsigned int q_fifo_size; 1378 unsigned int p_fifo; 1379 1380 /* Calculate the configured fifo size */ 1381 q_fifo_size = 1 << (fifo_size + 7); 1382 1383 /* The configured value may not be the actual amount of fifo RAM */ 1384 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size); 1385 1386 q_fifo_size = q_fifo_size / queue_count; 1387 1388 /* Each increment in the queue fifo size represents 256 bytes of 1389 * fifo, with 0 representing 256 bytes. Distribute the fifo equally 1390 * between the queues. 1391 */ 1392 p_fifo = q_fifo_size / 256; 1393 if (p_fifo) 1394 p_fifo--; 1395 1396 return p_fifo; 1397 } 1398 1399 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) 1400 { 1401 unsigned int fifo_size; 1402 unsigned int i; 1403 1404 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size, 1405 pdata->tx_q_count); 1406 1407 for (i = 0; i < pdata->tx_q_count; i++) 1408 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size); 1409 } 1410 1411 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) 1412 { 1413 unsigned int fifo_size; 1414 unsigned int i; 1415 1416 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size, 1417 pdata->rx_q_count); 1418 1419 for (i = 0; i < pdata->rx_q_count; i++) 1420 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size); 1421 } 1422 1423 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) 1424 { 1425 unsigned int qptc, qptc_extra, queue; 1426 unsigned int prio_queues; 1427 unsigned int ppq, ppq_extra, prio; 1428 unsigned int mask; 1429 unsigned int i, j, reg, reg_val; 1430 1431 /* Map the MTL Tx Queues to Traffic Classes 1432 * Note: Tx Queues >= Traffic Classes 1433 */ 1434 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; 1435 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; 1436 1437 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { 1438 for (j = 0; j < qptc; j++) { 1439 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 1440 Q2TCMAP, i); 1441 pdata->q2tc_map[queue++] = i; 1442 } 1443 1444 if (i < qptc_extra) { 1445 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, 1446 Q2TCMAP, i); 1447 pdata->q2tc_map[queue++] = i; 1448 } 1449 } 1450 1451 /* Map the 8 VLAN priority values to available MTL Rx queues */ 1452 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, 1453 pdata->rx_q_count); 1454 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 1455 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 1456 1457 reg = MAC_RQC2R; 1458 reg_val = 0; 1459 for (i = 0, prio = 0; i < prio_queues;) { 1460 mask = 0; 1461 for (j = 0; j < ppq; j++) { 1462 mask |= (1 << prio); 1463 pdata->prio2q_map[prio++] = i; 1464 } 1465 1466 if (i < ppq_extra) { 1467 mask |= (1 << prio); 1468 pdata->prio2q_map[prio++] = i; 1469 } 1470 1471 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 1472 1473 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues)) 1474 continue; 1475 1476 XGMAC_IOWRITE(pdata, reg, reg_val); 1477 reg += MAC_RQC2_INC; 1478 reg_val = 0; 1479 } 1480 1481 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */ 1482 reg = MTL_RQDCM0R; 1483 reg_val = 0; 1484 for (i = 0; i < pdata->rx_q_count;) { 1485 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3)); 1486 1487 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) 1488 continue; 1489 1490 XGMAC_IOWRITE(pdata, reg, reg_val); 1491 1492 reg += MTL_RQDCM_INC; 1493 reg_val = 0; 1494 } 1495 } 1496 1497 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) 1498 { 1499 unsigned int i; 1500 1501 for (i = 0; i < pdata->rx_q_count; i++) { 1502 /* Activate flow control when less than 4k left in fifo */ 1503 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2); 1504 1505 /* De-activate flow control when more than 6k left in fifo */ 1506 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4); 1507 } 1508 } 1509 1510 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) 1511 { 1512 1513 xgbe_set_mac_address(pdata, IF_LLADDR(pdata->netdev)); 1514 } 1515 1516 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) 1517 { 1518 unsigned int val; 1519 1520 val = (if_getmtu(pdata->netdev) > XGMAC_STD_PACKET_MTU) ? 1 : 0; 1521 1522 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1523 } 1524 1525 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) 1526 { 1527 switch (pdata->phy_speed) { 1528 case SPEED_10000: 1529 xgbe_set_xgmii_speed(pdata); 1530 break; 1531 1532 case SPEED_2500: 1533 xgbe_set_gmii_2500_speed(pdata); 1534 break; 1535 1536 case SPEED_1000: 1537 xgbe_set_gmii_speed(pdata); 1538 break; 1539 case SPEED_UNKNOWN: 1540 break; 1541 default: 1542 panic("TODO %s:%d\n", __FILE__, __LINE__); 1543 } 1544 } 1545 1546 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) 1547 { 1548 if ((if_getcapenable(pdata->netdev) & IFCAP_RXCSUM) != 0) 1549 xgbe_enable_rx_csum(pdata); 1550 else 1551 xgbe_disable_rx_csum(pdata); 1552 } 1553 1554 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) 1555 { 1556 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 1557 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 1558 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 1559 1560 /* Set the current VLAN Hash Table register value */ 1561 xgbe_update_vlan_hash_table(pdata); 1562 1563 xgbe_disable_rx_vlan_filtering(pdata); 1564 xgbe_disable_rx_vlan_stripping(pdata); 1565 } 1566 1567 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) 1568 { 1569 bool read_hi; 1570 u64 val; 1571 1572 switch (reg_lo) { 1573 /* These registers are always 64 bit */ 1574 case MMC_TXOCTETCOUNT_GB_LO: 1575 case MMC_TXOCTETCOUNT_G_LO: 1576 case MMC_RXOCTETCOUNT_GB_LO: 1577 case MMC_RXOCTETCOUNT_G_LO: 1578 read_hi = true; 1579 break; 1580 1581 default: 1582 read_hi = false; 1583 } 1584 1585 val = XGMAC_IOREAD(pdata, reg_lo); 1586 1587 if (read_hi) 1588 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); 1589 1590 return val; 1591 } 1592 1593 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) 1594 { 1595 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 1596 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); 1597 1598 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB)) 1599 stats->txoctetcount_gb += 1600 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 1601 1602 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB)) 1603 stats->txframecount_gb += 1604 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 1605 1606 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G)) 1607 stats->txbroadcastframes_g += 1608 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 1609 1610 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G)) 1611 stats->txmulticastframes_g += 1612 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 1613 1614 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB)) 1615 stats->tx64octets_gb += 1616 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 1617 1618 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB)) 1619 stats->tx65to127octets_gb += 1620 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 1621 1622 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB)) 1623 stats->tx128to255octets_gb += 1624 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 1625 1626 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB)) 1627 stats->tx256to511octets_gb += 1628 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 1629 1630 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB)) 1631 stats->tx512to1023octets_gb += 1632 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 1633 1634 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB)) 1635 stats->tx1024tomaxoctets_gb += 1636 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 1637 1638 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB)) 1639 stats->txunicastframes_gb += 1640 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 1641 1642 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB)) 1643 stats->txmulticastframes_gb += 1644 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 1645 1646 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB)) 1647 stats->txbroadcastframes_g += 1648 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 1649 1650 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR)) 1651 stats->txunderflowerror += 1652 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 1653 1654 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G)) 1655 stats->txoctetcount_g += 1656 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 1657 1658 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G)) 1659 stats->txframecount_g += 1660 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 1661 1662 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES)) 1663 stats->txpauseframes += 1664 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 1665 1666 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G)) 1667 stats->txvlanframes_g += 1668 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 1669 } 1670 1671 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) 1672 { 1673 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 1674 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); 1675 1676 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB)) 1677 stats->rxframecount_gb += 1678 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 1679 1680 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB)) 1681 stats->rxoctetcount_gb += 1682 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 1683 1684 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G)) 1685 stats->rxoctetcount_g += 1686 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 1687 1688 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G)) 1689 stats->rxbroadcastframes_g += 1690 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 1691 1692 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G)) 1693 stats->rxmulticastframes_g += 1694 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 1695 1696 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR)) 1697 stats->rxcrcerror += 1698 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 1699 1700 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR)) 1701 stats->rxrunterror += 1702 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 1703 1704 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR)) 1705 stats->rxjabbererror += 1706 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 1707 1708 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G)) 1709 stats->rxundersize_g += 1710 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 1711 1712 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G)) 1713 stats->rxoversize_g += 1714 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 1715 1716 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB)) 1717 stats->rx64octets_gb += 1718 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 1719 1720 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB)) 1721 stats->rx65to127octets_gb += 1722 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 1723 1724 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB)) 1725 stats->rx128to255octets_gb += 1726 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 1727 1728 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB)) 1729 stats->rx256to511octets_gb += 1730 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 1731 1732 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB)) 1733 stats->rx512to1023octets_gb += 1734 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 1735 1736 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB)) 1737 stats->rx1024tomaxoctets_gb += 1738 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 1739 1740 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G)) 1741 stats->rxunicastframes_g += 1742 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 1743 1744 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR)) 1745 stats->rxlengtherror += 1746 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 1747 1748 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE)) 1749 stats->rxoutofrangetype += 1750 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 1751 1752 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES)) 1753 stats->rxpauseframes += 1754 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 1755 1756 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW)) 1757 stats->rxfifooverflow += 1758 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 1759 1760 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB)) 1761 stats->rxvlanframes_gb += 1762 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 1763 1764 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR)) 1765 stats->rxwatchdogerror += 1766 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 1767 } 1768 1769 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) 1770 { 1771 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; 1772 1773 /* Freeze counters */ 1774 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 1775 1776 stats->txoctetcount_gb += 1777 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); 1778 1779 stats->txframecount_gb += 1780 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); 1781 1782 stats->txbroadcastframes_g += 1783 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); 1784 1785 stats->txmulticastframes_g += 1786 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); 1787 1788 stats->tx64octets_gb += 1789 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); 1790 1791 stats->tx65to127octets_gb += 1792 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); 1793 1794 stats->tx128to255octets_gb += 1795 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); 1796 1797 stats->tx256to511octets_gb += 1798 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); 1799 1800 stats->tx512to1023octets_gb += 1801 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); 1802 1803 stats->tx1024tomaxoctets_gb += 1804 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 1805 1806 stats->txunicastframes_gb += 1807 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); 1808 1809 stats->txmulticastframes_gb += 1810 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 1811 1812 stats->txbroadcastframes_g += 1813 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 1814 1815 stats->txunderflowerror += 1816 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); 1817 1818 stats->txoctetcount_g += 1819 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); 1820 1821 stats->txframecount_g += 1822 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); 1823 1824 stats->txpauseframes += 1825 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); 1826 1827 stats->txvlanframes_g += 1828 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); 1829 1830 stats->rxframecount_gb += 1831 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); 1832 1833 stats->rxoctetcount_gb += 1834 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); 1835 1836 stats->rxoctetcount_g += 1837 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); 1838 1839 stats->rxbroadcastframes_g += 1840 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); 1841 1842 stats->rxmulticastframes_g += 1843 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); 1844 1845 stats->rxcrcerror += 1846 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); 1847 1848 stats->rxrunterror += 1849 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); 1850 1851 stats->rxjabbererror += 1852 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); 1853 1854 stats->rxundersize_g += 1855 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); 1856 1857 stats->rxoversize_g += 1858 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); 1859 1860 stats->rx64octets_gb += 1861 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); 1862 1863 stats->rx65to127octets_gb += 1864 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); 1865 1866 stats->rx128to255octets_gb += 1867 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); 1868 1869 stats->rx256to511octets_gb += 1870 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); 1871 1872 stats->rx512to1023octets_gb += 1873 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); 1874 1875 stats->rx1024tomaxoctets_gb += 1876 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 1877 1878 stats->rxunicastframes_g += 1879 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); 1880 1881 stats->rxlengtherror += 1882 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); 1883 1884 stats->rxoutofrangetype += 1885 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); 1886 1887 stats->rxpauseframes += 1888 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); 1889 1890 stats->rxfifooverflow += 1891 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); 1892 1893 stats->rxvlanframes_gb += 1894 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); 1895 1896 stats->rxwatchdogerror += 1897 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); 1898 1899 /* Un-freeze counters */ 1900 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 1901 } 1902 1903 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) 1904 { 1905 /* Set counters to reset on read */ 1906 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); 1907 1908 /* Reset the counters */ 1909 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); 1910 } 1911 1912 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, 1913 struct xgbe_channel *channel) 1914 { 1915 unsigned int tx_dsr, tx_pos, tx_qidx; 1916 unsigned int tx_status; 1917 unsigned long tx_timeout; 1918 1919 /* Calculate the status register to read and the position within */ 1920 if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) { 1921 tx_dsr = DMA_DSR0; 1922 tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) + 1923 DMA_DSR0_TPS_START; 1924 } else { 1925 tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE; 1926 1927 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 1928 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 1929 DMA_DSRX_TPS_START; 1930 } 1931 1932 /* The Tx engine cannot be stopped if it is actively processing 1933 * descriptors. Wait for the Tx engine to enter the stopped or 1934 * suspended state. Don't wait forever though... 1935 */ 1936 tx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); 1937 while (ticks < tx_timeout) { 1938 tx_status = XGMAC_IOREAD(pdata, tx_dsr); 1939 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 1940 if ((tx_status == DMA_TPS_STOPPED) || 1941 (tx_status == DMA_TPS_SUSPENDED)) 1942 break; 1943 1944 DELAY(500); 1945 } 1946 } 1947 1948 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) 1949 { 1950 struct xgbe_channel *channel; 1951 unsigned int i; 1952 1953 /* Enable each Tx DMA channel */ 1954 channel = pdata->channel; 1955 for (i = 0; i < pdata->channel_count; i++, channel++) { 1956 if (!channel->tx_ring) 1957 break; 1958 1959 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); 1960 } 1961 1962 /* Enable each Tx queue */ 1963 for (i = 0; i < pdata->tx_q_count; i++) 1964 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 1965 MTL_Q_ENABLED); 1966 1967 /* Enable MAC Tx */ 1968 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 1969 } 1970 1971 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) 1972 { 1973 struct xgbe_channel *channel; 1974 unsigned int i; 1975 1976 /* Prepare for Tx DMA channel stop */ 1977 channel = pdata->channel; 1978 for (i = 0; i < pdata->channel_count; i++, channel++) { 1979 if (!channel->tx_ring) 1980 break; 1981 1982 xgbe_prepare_tx_stop(pdata, channel); 1983 } 1984 1985 /* Disable MAC Tx */ 1986 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 1987 1988 /* Disable each Tx queue */ 1989 for (i = 0; i < pdata->tx_q_count; i++) 1990 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); 1991 1992 /* Disable each Tx DMA channel */ 1993 channel = pdata->channel; 1994 for (i = 0; i < pdata->channel_count; i++, channel++) { 1995 if (!channel->tx_ring) 1996 break; 1997 1998 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); 1999 } 2000 } 2001 2002 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, 2003 unsigned int queue) 2004 { 2005 unsigned int rx_status; 2006 unsigned long rx_timeout; 2007 2008 /* The Rx engine cannot be stopped if it is actively processing 2009 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 2010 * wait forever though... 2011 */ 2012 rx_timeout = ticks + (XGBE_DMA_STOP_TIMEOUT * hz); 2013 while (ticks < rx_timeout) { 2014 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 2015 if ((XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 2016 (XGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 2017 break; 2018 2019 DELAY(500); 2020 } 2021 } 2022 2023 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) 2024 { 2025 struct xgbe_channel *channel; 2026 unsigned int reg_val, i; 2027 2028 /* Enable each Rx DMA channel */ 2029 channel = pdata->channel; 2030 for (i = 0; i < pdata->channel_count; i++, channel++) { 2031 if (!channel->rx_ring) 2032 break; 2033 2034 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); 2035 } 2036 2037 /* Enable each Rx queue */ 2038 reg_val = 0; 2039 for (i = 0; i < pdata->rx_q_count; i++) 2040 reg_val |= (0x02 << (i << 1)); 2041 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 2042 2043 /* Enable MAC Rx */ 2044 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 2045 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 2046 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 2047 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 2048 } 2049 2050 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) 2051 { 2052 struct xgbe_channel *channel; 2053 unsigned int i; 2054 2055 /* Disable MAC Rx */ 2056 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 2057 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 2058 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 2059 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 2060 2061 /* Prepare for Rx DMA channel stop */ 2062 for (i = 0; i < pdata->rx_q_count; i++) 2063 xgbe_prepare_rx_stop(pdata, i); 2064 2065 /* Disable each Rx queue */ 2066 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 2067 2068 /* Disable each Rx DMA channel */ 2069 channel = pdata->channel; 2070 for (i = 0; i < pdata->channel_count; i++, channel++) { 2071 if (!channel->rx_ring) 2072 break; 2073 2074 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); 2075 } 2076 } 2077 2078 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) 2079 { 2080 struct xgbe_channel *channel; 2081 unsigned int i; 2082 2083 /* Enable each Tx DMA channel */ 2084 channel = pdata->channel; 2085 for (i = 0; i < pdata->channel_count; i++, channel++) { 2086 if (!channel->tx_ring) 2087 break; 2088 2089 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1); 2090 } 2091 2092 /* Enable MAC Tx */ 2093 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 2094 } 2095 2096 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) 2097 { 2098 struct xgbe_channel *channel; 2099 unsigned int i; 2100 2101 /* Prepare for Tx DMA channel stop */ 2102 channel = pdata->channel; 2103 for (i = 0; i < pdata->channel_count; i++, channel++) { 2104 if (!channel->tx_ring) 2105 break; 2106 2107 xgbe_prepare_tx_stop(pdata, channel); 2108 } 2109 2110 /* Disable MAC Tx */ 2111 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 2112 2113 /* Disable each Tx DMA channel */ 2114 channel = pdata->channel; 2115 for (i = 0; i < pdata->channel_count; i++, channel++) { 2116 if (!channel->tx_ring) 2117 break; 2118 2119 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0); 2120 } 2121 } 2122 2123 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) 2124 { 2125 struct xgbe_channel *channel; 2126 unsigned int i; 2127 2128 /* Enable each Rx DMA channel */ 2129 channel = pdata->channel; 2130 for (i = 0; i < pdata->channel_count; i++, channel++) { 2131 if (!channel->rx_ring) 2132 break; 2133 2134 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1); 2135 } 2136 } 2137 2138 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) 2139 { 2140 struct xgbe_channel *channel; 2141 unsigned int i; 2142 2143 /* Disable each Rx DMA channel */ 2144 channel = pdata->channel; 2145 for (i = 0; i < pdata->channel_count; i++, channel++) { 2146 if (!channel->rx_ring) 2147 break; 2148 2149 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0); 2150 } 2151 } 2152 2153 static int xgbe_init(struct xgbe_prv_data *pdata) 2154 { 2155 struct xgbe_desc_if *desc_if = &pdata->desc_if; 2156 int ret; 2157 2158 DBGPR("-->xgbe_init\n"); 2159 2160 /* Flush Tx queues */ 2161 ret = xgbe_flush_tx_queues(pdata); 2162 if (ret) 2163 return ret; 2164 2165 /* 2166 * Initialize DMA related features 2167 */ 2168 xgbe_config_dma_bus(pdata); 2169 xgbe_config_dma_cache(pdata); 2170 xgbe_config_osp_mode(pdata); 2171 xgbe_config_pblx8(pdata); 2172 xgbe_config_tx_pbl_val(pdata); 2173 xgbe_config_rx_pbl_val(pdata); 2174 xgbe_config_rx_coalesce(pdata); 2175 xgbe_config_tx_coalesce(pdata); 2176 xgbe_config_rx_buffer_size(pdata); 2177 xgbe_config_tso_mode(pdata); 2178 xgbe_config_sph_mode(pdata); 2179 xgbe_config_rss(pdata); 2180 desc_if->wrapper_tx_desc_init(pdata); 2181 desc_if->wrapper_rx_desc_init(pdata); 2182 xgbe_enable_dma_interrupts(pdata); 2183 2184 /* 2185 * Initialize MTL related features 2186 */ 2187 xgbe_config_mtl_mode(pdata); 2188 xgbe_config_queue_mapping(pdata); 2189 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); 2190 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); 2191 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); 2192 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); 2193 xgbe_config_tx_fifo_size(pdata); 2194 xgbe_config_rx_fifo_size(pdata); 2195 xgbe_config_flow_control_threshold(pdata); 2196 /*TODO: Error Packet and undersized good Packet forwarding enable 2197 (FEP and FUP) 2198 */ 2199 xgbe_enable_mtl_interrupts(pdata); 2200 2201 /* 2202 * Initialize MAC related features 2203 */ 2204 xgbe_config_mac_address(pdata); 2205 xgbe_config_rx_mode(pdata); 2206 xgbe_config_jumbo_enable(pdata); 2207 xgbe_config_flow_control(pdata); 2208 xgbe_config_mac_speed(pdata); 2209 xgbe_config_checksum_offload(pdata); 2210 xgbe_config_vlan_support(pdata); 2211 xgbe_config_mmc(pdata); 2212 xgbe_enable_mac_interrupts(pdata); 2213 2214 DBGPR("<--xgbe_init\n"); 2215 2216 return 0; 2217 } 2218 2219 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if) 2220 { 2221 DBGPR("-->xgbe_init_function_ptrs\n"); 2222 2223 hw_if->tx_complete = xgbe_tx_complete; 2224 2225 hw_if->set_mac_address = xgbe_set_mac_address; 2226 hw_if->config_rx_mode = xgbe_config_rx_mode; 2227 2228 hw_if->enable_rx_csum = xgbe_enable_rx_csum; 2229 hw_if->disable_rx_csum = xgbe_disable_rx_csum; 2230 2231 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping; 2232 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping; 2233 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering; 2234 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering; 2235 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table; 2236 2237 hw_if->read_mmd_regs = xgbe_read_mmd_regs; 2238 hw_if->write_mmd_regs = xgbe_write_mmd_regs; 2239 2240 hw_if->set_gmii_speed = xgbe_set_gmii_speed; 2241 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed; 2242 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed; 2243 2244 hw_if->enable_tx = xgbe_enable_tx; 2245 hw_if->disable_tx = xgbe_disable_tx; 2246 hw_if->enable_rx = xgbe_enable_rx; 2247 hw_if->disable_rx = xgbe_disable_rx; 2248 2249 hw_if->powerup_tx = xgbe_powerup_tx; 2250 hw_if->powerdown_tx = xgbe_powerdown_tx; 2251 hw_if->powerup_rx = xgbe_powerup_rx; 2252 hw_if->powerdown_rx = xgbe_powerdown_rx; 2253 2254 hw_if->dev_xmit = xgbe_dev_xmit; 2255 hw_if->dev_read = xgbe_dev_read; 2256 hw_if->enable_int = xgbe_enable_int; 2257 hw_if->disable_int = xgbe_disable_int; 2258 hw_if->init = xgbe_init; 2259 hw_if->exit = xgbe_exit; 2260 2261 /* Descriptor related Sequences have to be initialized here */ 2262 hw_if->tx_desc_init = xgbe_tx_desc_init; 2263 hw_if->rx_desc_init = xgbe_rx_desc_init; 2264 hw_if->tx_desc_reset = xgbe_tx_desc_reset; 2265 hw_if->rx_desc_reset = xgbe_rx_desc_reset; 2266 hw_if->is_last_desc = xgbe_is_last_desc; 2267 hw_if->is_context_desc = xgbe_is_context_desc; 2268 hw_if->tx_start_xmit = xgbe_tx_start_xmit; 2269 2270 /* For FLOW ctrl */ 2271 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control; 2272 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control; 2273 2274 /* For RX coalescing */ 2275 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce; 2276 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce; 2277 hw_if->usec_to_riwt = xgbe_usec_to_riwt; 2278 hw_if->riwt_to_usec = xgbe_riwt_to_usec; 2279 2280 /* For RX and TX threshold config */ 2281 hw_if->config_rx_threshold = xgbe_config_rx_threshold; 2282 hw_if->config_tx_threshold = xgbe_config_tx_threshold; 2283 2284 /* For RX and TX Store and Forward Mode config */ 2285 hw_if->config_rsf_mode = xgbe_config_rsf_mode; 2286 hw_if->config_tsf_mode = xgbe_config_tsf_mode; 2287 2288 /* For TX DMA Operating on Second Frame config */ 2289 hw_if->config_osp_mode = xgbe_config_osp_mode; 2290 2291 /* For RX and TX PBL config */ 2292 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val; 2293 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val; 2294 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val; 2295 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val; 2296 hw_if->config_pblx8 = xgbe_config_pblx8; 2297 2298 /* For MMC statistics support */ 2299 hw_if->tx_mmc_int = xgbe_tx_mmc_int; 2300 hw_if->rx_mmc_int = xgbe_rx_mmc_int; 2301 hw_if->read_mmc_stats = xgbe_read_mmc_stats; 2302 2303 /* For Receive Side Scaling */ 2304 hw_if->disable_rss = xgbe_disable_rss; 2305 2306 DBGPR("<--xgbe_init_function_ptrs\n"); 2307 } 2308