1 /* 2 * AMD 10Gb Ethernet driver 3 * 4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc. 5 * 6 * This file is available to you under your choice of the following two 7 * licenses: 8 * 9 * License 1: GPLv2 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Redistribution and use in source and binary forms, with or without 60 * modification, are permitted provided that the following conditions are met: 61 * * Redistributions of source code must retain the above copyright 62 * notice, this list of conditions and the following disclaimer. 63 * * Redistributions in binary form must reproduce the above copyright 64 * notice, this list of conditions and the following disclaimer in the 65 * documentation and/or other materials provided with the distribution. 66 * * Neither the name of Advanced Micro Devices, Inc. nor the 67 * names of its contributors may be used to endorse or promote products 68 * derived from this software without specific prior written permission. 69 * 70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 80 * 81 * This file incorporates work covered by the following copyright and 82 * permission notice: 83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 85 * Inc. unless otherwise expressly agreed to in writing between Synopsys 86 * and you. 87 * 88 * The Software IS NOT an item of Licensed Software or Licensed Product 89 * under any End User Software License Agreement or Agreement for Licensed 90 * Product with Synopsys or any supplement thereto. Permission is hereby 91 * granted, free of charge, to any person obtaining a copy of this software 92 * annotated with this license and the Software, to deal in the Software 93 * without restriction, including without limitation the rights to use, 94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 95 * of the Software, and to permit persons to whom the Software is furnished 96 * to do so, subject to the following conditions: 97 * 98 * The above copyright notice and this permission notice shall be included 99 * in all copies or substantial portions of the Software. 100 * 101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 111 * THE POSSIBILITY OF SUCH DAMAGE. 112 */ 113 114 #ifndef __XGBE_COMMON_H__ 115 #define __XGBE_COMMON_H__ 116 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 /* DMA register offsets */ 121 #define DMA_MR 0x3000 122 #define DMA_SBMR 0x3004 123 #define DMA_ISR 0x3008 124 #define DMA_AXIARCR 0x3010 125 #define DMA_AXIAWCR 0x3018 126 #define DMA_AXIAWARCR 0x301c 127 #define DMA_DSR0 0x3020 128 #define DMA_DSR1 0x3024 129 #define DMA_DSR2 0x3028 130 #define DMA_DSR3 0x302C 131 #define DMA_DSR4 0x3030 132 #define DMA_TXEDMACR 0x3040 133 #define DMA_RXEDMACR 0x3044 134 135 /* DMA register entry bit positions and sizes */ 136 #define DMA_ISR_MACIS_INDEX 17 137 #define DMA_ISR_MACIS_WIDTH 1 138 #define DMA_ISR_MTLIS_INDEX 16 139 #define DMA_ISR_MTLIS_WIDTH 1 140 #define DMA_MR_INTM_INDEX 12 141 #define DMA_MR_INTM_WIDTH 2 142 #define DMA_MR_SWR_INDEX 0 143 #define DMA_MR_SWR_WIDTH 1 144 #define DMA_RXEDMACR_RDPS_INDEX 0 145 #define DMA_RXEDMACR_RDPS_WIDTH 3 146 #define DMA_SBMR_AAL_INDEX 12 147 #define DMA_SBMR_AAL_WIDTH 1 148 #define DMA_SBMR_EAME_INDEX 11 149 #define DMA_SBMR_EAME_WIDTH 1 150 #define DMA_SBMR_BLEN_INDEX 1 151 #define DMA_SBMR_BLEN_WIDTH 7 152 #define DMA_SBMR_RD_OSR_LMT_INDEX 16 153 #define DMA_SBMR_RD_OSR_LMT_WIDTH 6 154 #define DMA_SBMR_UNDEF_INDEX 0 155 #define DMA_SBMR_UNDEF_WIDTH 1 156 #define DMA_SBMR_WR_OSR_LMT_INDEX 24 157 #define DMA_SBMR_WR_OSR_LMT_WIDTH 6 158 #define DMA_TXEDMACR_TDPS_INDEX 0 159 #define DMA_TXEDMACR_TDPS_WIDTH 3 160 161 /* DMA register values */ 162 #define DMA_SBMR_BLEN_256 256 163 #define DMA_SBMR_BLEN_128 128 164 #define DMA_SBMR_BLEN_64 64 165 #define DMA_SBMR_BLEN_32 32 166 #define DMA_SBMR_BLEN_16 16 167 #define DMA_SBMR_BLEN_8 8 168 #define DMA_SBMR_BLEN_4 4 169 #define DMA_DSR_RPS_WIDTH 4 170 #define DMA_DSR_TPS_WIDTH 4 171 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH) 172 #define DMA_DSR0_RPS_START 8 173 #define DMA_DSR0_TPS_START 12 174 #define DMA_DSRX_FIRST_QUEUE 3 175 #define DMA_DSRX_INC 4 176 #define DMA_DSRX_QPR 4 177 #define DMA_DSRX_RPS_START 0 178 #define DMA_DSRX_TPS_START 4 179 #define DMA_TPS_STOPPED 0x00 180 #define DMA_TPS_SUSPENDED 0x06 181 182 /* DMA channel register offsets 183 * Multiple channels can be active. The first channel has registers 184 * that begin at 0x3100. Each subsequent channel has registers that 185 * are accessed using an offset of 0x80 from the previous channel. 186 */ 187 #define DMA_CH_BASE 0x3100 188 #define DMA_CH_INC 0x80 189 190 #define DMA_CH_CR 0x00 191 #define DMA_CH_TCR 0x04 192 #define DMA_CH_RCR 0x08 193 #define DMA_CH_TDLR_HI 0x10 194 #define DMA_CH_TDLR_LO 0x14 195 #define DMA_CH_RDLR_HI 0x18 196 #define DMA_CH_RDLR_LO 0x1c 197 #define DMA_CH_TDTR_LO 0x24 198 #define DMA_CH_RDTR_LO 0x2c 199 #define DMA_CH_TDRLR 0x30 200 #define DMA_CH_RDRLR 0x34 201 #define DMA_CH_IER 0x38 202 #define DMA_CH_RIWT 0x3c 203 #define DMA_CH_CATDR_LO 0x44 204 #define DMA_CH_CARDR_LO 0x4c 205 #define DMA_CH_CATBR_HI 0x50 206 #define DMA_CH_CATBR_LO 0x54 207 #define DMA_CH_CARBR_HI 0x58 208 #define DMA_CH_CARBR_LO 0x5c 209 #define DMA_CH_SR 0x60 210 #define DMA_CH_DSR 0x64 211 #define DMA_CH_DCFL 0x68 212 #define DMA_CH_MFC 0x6c 213 #define DMA_CH_TDTRO 0x70 214 #define DMA_CH_RDTRO 0x74 215 #define DMA_CH_TDWRO 0x78 216 #define DMA_CH_RDWRO 0x7C 217 218 /* DMA channel register entry bit positions and sizes */ 219 #define DMA_CH_CR_PBLX8_INDEX 16 220 #define DMA_CH_CR_PBLX8_WIDTH 1 221 #define DMA_CH_CR_SPH_INDEX 24 222 #define DMA_CH_CR_SPH_WIDTH 1 223 #define DMA_CH_IER_AIE20_INDEX 15 224 #define DMA_CH_IER_AIE20_WIDTH 1 225 #define DMA_CH_IER_AIE_INDEX 14 226 #define DMA_CH_IER_AIE_WIDTH 1 227 #define DMA_CH_IER_FBEE_INDEX 12 228 #define DMA_CH_IER_FBEE_WIDTH 1 229 #define DMA_CH_IER_NIE20_INDEX 16 230 #define DMA_CH_IER_NIE20_WIDTH 1 231 #define DMA_CH_IER_NIE_INDEX 15 232 #define DMA_CH_IER_NIE_WIDTH 1 233 #define DMA_CH_IER_RBUE_INDEX 7 234 #define DMA_CH_IER_RBUE_WIDTH 1 235 #define DMA_CH_IER_RIE_INDEX 6 236 #define DMA_CH_IER_RIE_WIDTH 1 237 #define DMA_CH_IER_RSE_INDEX 8 238 #define DMA_CH_IER_RSE_WIDTH 1 239 #define DMA_CH_IER_TBUE_INDEX 2 240 #define DMA_CH_IER_TBUE_WIDTH 1 241 #define DMA_CH_IER_TIE_INDEX 0 242 #define DMA_CH_IER_TIE_WIDTH 1 243 #define DMA_CH_IER_TXSE_INDEX 1 244 #define DMA_CH_IER_TXSE_WIDTH 1 245 #define DMA_CH_RCR_PBL_INDEX 16 246 #define DMA_CH_RCR_PBL_WIDTH 6 247 #define DMA_CH_RCR_RBSZ_INDEX 1 248 #define DMA_CH_RCR_RBSZ_WIDTH 14 249 #define DMA_CH_RCR_SR_INDEX 0 250 #define DMA_CH_RCR_SR_WIDTH 1 251 #define DMA_CH_RIWT_RWT_INDEX 0 252 #define DMA_CH_RIWT_RWT_WIDTH 8 253 #define DMA_CH_SR_FBE_INDEX 12 254 #define DMA_CH_SR_FBE_WIDTH 1 255 #define DMA_CH_SR_RBU_INDEX 7 256 #define DMA_CH_SR_RBU_WIDTH 1 257 #define DMA_CH_SR_RI_INDEX 6 258 #define DMA_CH_SR_RI_WIDTH 1 259 #define DMA_CH_SR_RPS_INDEX 8 260 #define DMA_CH_SR_RPS_WIDTH 1 261 #define DMA_CH_SR_TBU_INDEX 2 262 #define DMA_CH_SR_TBU_WIDTH 1 263 #define DMA_CH_SR_TI_INDEX 0 264 #define DMA_CH_SR_TI_WIDTH 1 265 #define DMA_CH_SR_TPS_INDEX 1 266 #define DMA_CH_SR_TPS_WIDTH 1 267 #define DMA_CH_TCR_OSP_INDEX 4 268 #define DMA_CH_TCR_OSP_WIDTH 1 269 #define DMA_CH_TCR_PBL_INDEX 16 270 #define DMA_CH_TCR_PBL_WIDTH 6 271 #define DMA_CH_TCR_ST_INDEX 0 272 #define DMA_CH_TCR_ST_WIDTH 1 273 #define DMA_CH_TCR_TSE_INDEX 12 274 #define DMA_CH_TCR_TSE_WIDTH 1 275 276 /* DMA channel register values */ 277 #define DMA_OSP_DISABLE 0x00 278 #define DMA_OSP_ENABLE 0x01 279 #define DMA_PBL_1 1 280 #define DMA_PBL_2 2 281 #define DMA_PBL_4 4 282 #define DMA_PBL_8 8 283 #define DMA_PBL_16 16 284 #define DMA_PBL_32 32 285 #define DMA_PBL_64 64 /* 8 x 8 */ 286 #define DMA_PBL_128 128 /* 8 x 16 */ 287 #define DMA_PBL_256 256 /* 8 x 32 */ 288 #define DMA_PBL_X8_DISABLE 0x00 289 #define DMA_PBL_X8_ENABLE 0x01 290 291 /* MAC register offsets */ 292 #define MAC_TCR 0x0000 293 #define MAC_RCR 0x0004 294 #define MAC_PFR 0x0008 295 #define MAC_WTR 0x000c 296 #define MAC_HTR0 0x0010 297 #define MAC_HTR1 0x0014 298 #define MAC_HTR2 0x0018 299 #define MAC_HTR3 0x001c 300 #define MAC_HTR4 0x0020 301 #define MAC_HTR5 0x0024 302 #define MAC_HTR6 0x0028 303 #define MAC_HTR7 0x002c 304 #define MAC_VLANTR 0x0050 305 #define MAC_VLANHTR 0x0058 306 #define MAC_VLANIR 0x0060 307 #define MAC_IVLANIR 0x0064 308 #define MAC_RETMR 0x006c 309 #define MAC_Q0TFCR 0x0070 310 #define MAC_Q1TFCR 0x0074 311 #define MAC_Q2TFCR 0x0078 312 #define MAC_Q3TFCR 0x007c 313 #define MAC_Q4TFCR 0x0080 314 #define MAC_Q5TFCR 0x0084 315 #define MAC_Q6TFCR 0x0088 316 #define MAC_Q7TFCR 0x008c 317 #define MAC_RFCR 0x0090 318 #define MAC_RQC0R 0x00a0 319 #define MAC_RQC1R 0x00a4 320 #define MAC_RQC2R 0x00a8 321 #define MAC_RQC3R 0x00ac 322 #define MAC_ISR 0x00b0 323 #define MAC_IER 0x00b4 324 #define MAC_RTSR 0x00b8 325 #define MAC_PMTCSR 0x00c0 326 #define MAC_RWKPFR 0x00c4 327 #define MAC_LPICSR 0x00d0 328 #define MAC_LPITCR 0x00d4 329 #define MAC_TIR 0x00e0 330 #define MAC_VR 0x0110 331 #define MAC_DR 0x0114 332 #define MAC_HWF0R 0x011c 333 #define MAC_HWF1R 0x0120 334 #define MAC_HWF2R 0x0124 335 #define MAC_MDIOSCAR 0x0200 336 #define MAC_MDIOSCCDR 0x0204 337 #define MAC_MDIOISR 0x0214 338 #define MAC_MDIOIER 0x0218 339 #define MAC_MDIOCL22R 0x0220 340 #define MAC_GPIOCR 0x0278 341 #define MAC_GPIOSR 0x027c 342 #define MAC_MACA0HR 0x0300 343 #define MAC_MACA0LR 0x0304 344 #define MAC_MACA1HR 0x0308 345 #define MAC_MACA1LR 0x030c 346 #define MAC_RSSCR 0x0c80 347 #define MAC_RSSAR 0x0c88 348 #define MAC_RSSDR 0x0c8c 349 #define MAC_TSCR 0x0d00 350 #define MAC_SSIR 0x0d04 351 #define MAC_STSR 0x0d08 352 #define MAC_STNR 0x0d0c 353 #define MAC_STSUR 0x0d10 354 #define MAC_STNUR 0x0d14 355 #define MAC_TSAR 0x0d18 356 #define MAC_TSSR 0x0d20 357 #define MAC_TXSNR 0x0d30 358 #define MAC_TXSSR 0x0d34 359 360 #define MAC_QTFCR_INC 4 361 #define MAC_MACA_INC 4 362 #define MAC_HTR_INC 4 363 364 #define MAC_RQC2_INC 4 365 #define MAC_RQC2_Q_PER_REG 4 366 367 /* MAC register entry bit positions and sizes */ 368 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18 369 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 370 #define MAC_HWF0R_ARPOFFSEL_INDEX 9 371 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1 372 #define MAC_HWF0R_EEESEL_INDEX 13 373 #define MAC_HWF0R_EEESEL_WIDTH 1 374 #define MAC_HWF0R_GMIISEL_INDEX 1 375 #define MAC_HWF0R_GMIISEL_WIDTH 1 376 #define MAC_HWF0R_MGKSEL_INDEX 7 377 #define MAC_HWF0R_MGKSEL_WIDTH 1 378 #define MAC_HWF0R_MMCSEL_INDEX 8 379 #define MAC_HWF0R_MMCSEL_WIDTH 1 380 #define MAC_HWF0R_RWKSEL_INDEX 6 381 #define MAC_HWF0R_RWKSEL_WIDTH 1 382 #define MAC_HWF0R_RXCOESEL_INDEX 16 383 #define MAC_HWF0R_RXCOESEL_WIDTH 1 384 #define MAC_HWF0R_SAVLANINS_INDEX 27 385 #define MAC_HWF0R_SAVLANINS_WIDTH 1 386 #define MAC_HWF0R_SMASEL_INDEX 5 387 #define MAC_HWF0R_SMASEL_WIDTH 1 388 #define MAC_HWF0R_TSSEL_INDEX 12 389 #define MAC_HWF0R_TSSEL_WIDTH 1 390 #define MAC_HWF0R_TSSTSSEL_INDEX 25 391 #define MAC_HWF0R_TSSTSSEL_WIDTH 2 392 #define MAC_HWF0R_TXCOESEL_INDEX 14 393 #define MAC_HWF0R_TXCOESEL_WIDTH 1 394 #define MAC_HWF0R_VLHASH_INDEX 4 395 #define MAC_HWF0R_VLHASH_WIDTH 1 396 #define MAC_HWF0R_VXN_INDEX 29 397 #define MAC_HWF0R_VXN_WIDTH 1 398 #define MAC_HWF1R_ADDR64_INDEX 14 399 #define MAC_HWF1R_ADDR64_WIDTH 2 400 #define MAC_HWF1R_ADVTHWORD_INDEX 13 401 #define MAC_HWF1R_ADVTHWORD_WIDTH 1 402 #define MAC_HWF1R_DBGMEMA_INDEX 19 403 #define MAC_HWF1R_DBGMEMA_WIDTH 1 404 #define MAC_HWF1R_DCBEN_INDEX 16 405 #define MAC_HWF1R_DCBEN_WIDTH 1 406 #define MAC_HWF1R_HASHTBLSZ_INDEX 24 407 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3 408 #define MAC_HWF1R_L3L4FNUM_INDEX 27 409 #define MAC_HWF1R_L3L4FNUM_WIDTH 4 410 #define MAC_HWF1R_NUMTC_INDEX 21 411 #define MAC_HWF1R_NUMTC_WIDTH 3 412 #define MAC_HWF1R_RSSEN_INDEX 20 413 #define MAC_HWF1R_RSSEN_WIDTH 1 414 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0 415 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5 416 #define MAC_HWF1R_SPHEN_INDEX 17 417 #define MAC_HWF1R_SPHEN_WIDTH 1 418 #define MAC_HWF1R_TSOEN_INDEX 18 419 #define MAC_HWF1R_TSOEN_WIDTH 1 420 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6 421 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5 422 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28 423 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3 424 #define MAC_HWF2R_PPSOUTNUM_INDEX 24 425 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3 426 #define MAC_HWF2R_RXCHCNT_INDEX 12 427 #define MAC_HWF2R_RXCHCNT_WIDTH 4 428 #define MAC_HWF2R_RXQCNT_INDEX 0 429 #define MAC_HWF2R_RXQCNT_WIDTH 4 430 #define MAC_HWF2R_TXCHCNT_INDEX 18 431 #define MAC_HWF2R_TXCHCNT_WIDTH 4 432 #define MAC_HWF2R_TXQCNT_INDEX 6 433 #define MAC_HWF2R_TXQCNT_WIDTH 4 434 #define MAC_IER_TSIE_INDEX 12 435 #define MAC_IER_TSIE_WIDTH 1 436 #define MAC_ISR_MMCRXIS_INDEX 9 437 #define MAC_ISR_MMCRXIS_WIDTH 1 438 #define MAC_ISR_MMCTXIS_INDEX 10 439 #define MAC_ISR_MMCTXIS_WIDTH 1 440 #define MAC_ISR_PMTIS_INDEX 4 441 #define MAC_ISR_PMTIS_WIDTH 1 442 #define MAC_ISR_SMI_INDEX 1 443 #define MAC_ISR_SMI_WIDTH 1 444 #define MAC_ISR_TSIS_INDEX 12 445 #define MAC_ISR_TSIS_WIDTH 1 446 #define MAC_MACA1HR_AE_INDEX 31 447 #define MAC_MACA1HR_AE_WIDTH 1 448 #define MAC_MDIOIER_SNGLCOMPIE_INDEX 12 449 #define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1 450 #define MAC_MDIOISR_SNGLCOMPINT_INDEX 12 451 #define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1 452 #define MAC_MDIOSCAR_DA_INDEX 21 453 #define MAC_MDIOSCAR_DA_WIDTH 5 454 #define MAC_MDIOSCAR_PA_INDEX 16 455 #define MAC_MDIOSCAR_PA_WIDTH 5 456 #define MAC_MDIOSCAR_RA_INDEX 0 457 #define MAC_MDIOSCAR_RA_WIDTH 16 458 #define MAC_MDIOSCCDR_BUSY_INDEX 22 459 #define MAC_MDIOSCCDR_BUSY_WIDTH 1 460 #define MAC_MDIOSCCDR_CMD_INDEX 16 461 #define MAC_MDIOSCCDR_CMD_WIDTH 2 462 #define MAC_MDIOSCCDR_CR_INDEX 19 463 #define MAC_MDIOSCCDR_CR_WIDTH 3 464 #define MAC_MDIOSCCDR_DATA_INDEX 0 465 #define MAC_MDIOSCCDR_DATA_WIDTH 16 466 #define MAC_MDIOSCCDR_SADDR_INDEX 18 467 #define MAC_MDIOSCCDR_SADDR_WIDTH 1 468 #define MAC_PFR_HMC_INDEX 2 469 #define MAC_PFR_HMC_WIDTH 1 470 #define MAC_PFR_HPF_INDEX 10 471 #define MAC_PFR_HPF_WIDTH 1 472 #define MAC_PFR_HUC_INDEX 1 473 #define MAC_PFR_HUC_WIDTH 1 474 #define MAC_PFR_PM_INDEX 4 475 #define MAC_PFR_PM_WIDTH 1 476 #define MAC_PFR_PR_INDEX 0 477 #define MAC_PFR_PR_WIDTH 1 478 #define MAC_PFR_VTFE_INDEX 16 479 #define MAC_PFR_VTFE_WIDTH 1 480 #define MAC_PFR_VUCC_INDEX 22 481 #define MAC_PFR_VUCC_WIDTH 1 482 #define MAC_PMTCSR_MGKPKTEN_INDEX 1 483 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1 484 #define MAC_PMTCSR_PWRDWN_INDEX 0 485 #define MAC_PMTCSR_PWRDWN_WIDTH 1 486 #define MAC_PMTCSR_RWKFILTRST_INDEX 31 487 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1 488 #define MAC_PMTCSR_RWKPKTEN_INDEX 2 489 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1 490 #define MAC_Q0TFCR_PT_INDEX 16 491 #define MAC_Q0TFCR_PT_WIDTH 16 492 #define MAC_Q0TFCR_TFE_INDEX 1 493 #define MAC_Q0TFCR_TFE_WIDTH 1 494 #define MAC_RCR_ACS_INDEX 1 495 #define MAC_RCR_ACS_WIDTH 1 496 #define MAC_RCR_CST_INDEX 2 497 #define MAC_RCR_CST_WIDTH 1 498 #define MAC_RCR_DCRCC_INDEX 3 499 #define MAC_RCR_DCRCC_WIDTH 1 500 #define MAC_RCR_HDSMS_INDEX 12 501 #define MAC_RCR_HDSMS_WIDTH 3 502 #define MAC_RCR_IPC_INDEX 9 503 #define MAC_RCR_IPC_WIDTH 1 504 #define MAC_RCR_JE_INDEX 8 505 #define MAC_RCR_JE_WIDTH 1 506 #define MAC_RCR_LM_INDEX 10 507 #define MAC_RCR_LM_WIDTH 1 508 #define MAC_RCR_RE_INDEX 0 509 #define MAC_RCR_RE_WIDTH 1 510 #define MAC_RCR_ARPEN_INDEX 31 511 #define MAC_RCR_ARPEN_WIDTH 1 512 #define MAC_RFCR_PFCE_INDEX 8 513 #define MAC_RFCR_PFCE_WIDTH 1 514 #define MAC_RFCR_RFE_INDEX 0 515 #define MAC_RFCR_RFE_WIDTH 1 516 #define MAC_RFCR_UP_INDEX 1 517 #define MAC_RFCR_UP_WIDTH 1 518 #define MAC_RQC0R_RXQ0EN_INDEX 0 519 #define MAC_RQC0R_RXQ0EN_WIDTH 2 520 #define MAC_RSSAR_ADDRT_INDEX 2 521 #define MAC_RSSAR_ADDRT_WIDTH 1 522 #define MAC_RSSAR_CT_INDEX 1 523 #define MAC_RSSAR_CT_WIDTH 1 524 #define MAC_RSSAR_OB_INDEX 0 525 #define MAC_RSSAR_OB_WIDTH 1 526 #define MAC_RSSAR_RSSIA_INDEX 8 527 #define MAC_RSSAR_RSSIA_WIDTH 8 528 #define MAC_RSSCR_IP2TE_INDEX 1 529 #define MAC_RSSCR_IP2TE_WIDTH 1 530 #define MAC_RSSCR_RSSE_INDEX 0 531 #define MAC_RSSCR_RSSE_WIDTH 1 532 #define MAC_RSSCR_TCP4TE_INDEX 2 533 #define MAC_RSSCR_TCP4TE_WIDTH 1 534 #define MAC_RSSCR_UDP4TE_INDEX 3 535 #define MAC_RSSCR_UDP4TE_WIDTH 1 536 #define MAC_RSSDR_DMCH_INDEX 0 537 #define MAC_RSSDR_DMCH_WIDTH 4 538 #define MAC_SSIR_SNSINC_INDEX 8 539 #define MAC_SSIR_SNSINC_WIDTH 8 540 #define MAC_SSIR_SSINC_INDEX 16 541 #define MAC_SSIR_SSINC_WIDTH 8 542 #define MAC_TCR_SS_INDEX 29 543 #define MAC_TCR_SS_WIDTH 2 544 #define MAC_TCR_TE_INDEX 0 545 #define MAC_TCR_TE_WIDTH 1 546 #define MAC_TCR_VNE_INDEX 24 547 #define MAC_TCR_VNE_WIDTH 1 548 #define MAC_TCR_VNM_INDEX 25 549 #define MAC_TCR_VNM_WIDTH 1 550 #define MAC_TIR_TNID_INDEX 0 551 #define MAC_TIR_TNID_WIDTH 16 552 #define MAC_TSCR_AV8021ASMEN_INDEX 28 553 #define MAC_TSCR_AV8021ASMEN_WIDTH 1 554 #define MAC_TSCR_SNAPTYPSEL_INDEX 16 555 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2 556 #define MAC_TSCR_TSADDREG_INDEX 5 557 #define MAC_TSCR_TSADDREG_WIDTH 1 558 #define MAC_TSCR_TSCFUPDT_INDEX 1 559 #define MAC_TSCR_TSCFUPDT_WIDTH 1 560 #define MAC_TSCR_TSCTRLSSR_INDEX 9 561 #define MAC_TSCR_TSCTRLSSR_WIDTH 1 562 #define MAC_TSCR_TSENA_INDEX 0 563 #define MAC_TSCR_TSENA_WIDTH 1 564 #define MAC_TSCR_TSENALL_INDEX 8 565 #define MAC_TSCR_TSENALL_WIDTH 1 566 #define MAC_TSCR_TSEVNTENA_INDEX 14 567 #define MAC_TSCR_TSEVNTENA_WIDTH 1 568 #define MAC_TSCR_TSINIT_INDEX 2 569 #define MAC_TSCR_TSINIT_WIDTH 1 570 #define MAC_TSCR_TSIPENA_INDEX 11 571 #define MAC_TSCR_TSIPENA_WIDTH 1 572 #define MAC_TSCR_TSIPV4ENA_INDEX 13 573 #define MAC_TSCR_TSIPV4ENA_WIDTH 1 574 #define MAC_TSCR_TSIPV6ENA_INDEX 12 575 #define MAC_TSCR_TSIPV6ENA_WIDTH 1 576 #define MAC_TSCR_TSMSTRENA_INDEX 15 577 #define MAC_TSCR_TSMSTRENA_WIDTH 1 578 #define MAC_TSCR_TSVER2ENA_INDEX 10 579 #define MAC_TSCR_TSVER2ENA_WIDTH 1 580 #define MAC_TSCR_TXTSSTSM_INDEX 24 581 #define MAC_TSCR_TXTSSTSM_WIDTH 1 582 #define MAC_TSSR_TXTSC_INDEX 15 583 #define MAC_TSSR_TXTSC_WIDTH 1 584 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31 585 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1 586 #define MAC_VLANHTR_VLHT_INDEX 0 587 #define MAC_VLANHTR_VLHT_WIDTH 16 588 #define MAC_VLANIR_VLTI_INDEX 20 589 #define MAC_VLANIR_VLTI_WIDTH 1 590 #define MAC_VLANIR_CSVL_INDEX 19 591 #define MAC_VLANIR_CSVL_WIDTH 1 592 #define MAC_VLANTR_DOVLTC_INDEX 20 593 #define MAC_VLANTR_DOVLTC_WIDTH 1 594 #define MAC_VLANTR_ERSVLM_INDEX 19 595 #define MAC_VLANTR_ERSVLM_WIDTH 1 596 #define MAC_VLANTR_ESVL_INDEX 18 597 #define MAC_VLANTR_ESVL_WIDTH 1 598 #define MAC_VLANTR_ETV_INDEX 16 599 #define MAC_VLANTR_ETV_WIDTH 1 600 #define MAC_VLANTR_EVLS_INDEX 21 601 #define MAC_VLANTR_EVLS_WIDTH 2 602 #define MAC_VLANTR_EVLRXS_INDEX 24 603 #define MAC_VLANTR_EVLRXS_WIDTH 1 604 #define MAC_VLANTR_VL_INDEX 0 605 #define MAC_VLANTR_VL_WIDTH 16 606 #define MAC_VLANTR_VTHM_INDEX 25 607 #define MAC_VLANTR_VTHM_WIDTH 1 608 #define MAC_VLANTR_VTIM_INDEX 17 609 #define MAC_VLANTR_VTIM_WIDTH 1 610 #define MAC_VR_DEVID_INDEX 8 611 #define MAC_VR_DEVID_WIDTH 8 612 #define MAC_VR_SNPSVER_INDEX 0 613 #define MAC_VR_SNPSVER_WIDTH 8 614 #define MAC_VR_USERVER_INDEX 16 615 #define MAC_VR_USERVER_WIDTH 8 616 617 /* MMC register offsets */ 618 #define MMC_CR 0x0800 619 #define MMC_RISR 0x0804 620 #define MMC_TISR 0x0808 621 #define MMC_RIER 0x080c 622 #define MMC_TIER 0x0810 623 #define MMC_TXOCTETCOUNT_GB_LO 0x0814 624 #define MMC_TXOCTETCOUNT_GB_HI 0x0818 625 #define MMC_TXFRAMECOUNT_GB_LO 0x081c 626 #define MMC_TXFRAMECOUNT_GB_HI 0x0820 627 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824 628 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828 629 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c 630 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830 631 #define MMC_TX64OCTETS_GB_LO 0x0834 632 #define MMC_TX64OCTETS_GB_HI 0x0838 633 #define MMC_TX65TO127OCTETS_GB_LO 0x083c 634 #define MMC_TX65TO127OCTETS_GB_HI 0x0840 635 #define MMC_TX128TO255OCTETS_GB_LO 0x0844 636 #define MMC_TX128TO255OCTETS_GB_HI 0x0848 637 #define MMC_TX256TO511OCTETS_GB_LO 0x084c 638 #define MMC_TX256TO511OCTETS_GB_HI 0x0850 639 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854 640 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858 641 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c 642 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860 643 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864 644 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868 645 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c 646 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870 647 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 648 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878 649 #define MMC_TXUNDERFLOWERROR_LO 0x087c 650 #define MMC_TXUNDERFLOWERROR_HI 0x0880 651 #define MMC_TXOCTETCOUNT_G_LO 0x0884 652 #define MMC_TXOCTETCOUNT_G_HI 0x0888 653 #define MMC_TXFRAMECOUNT_G_LO 0x088c 654 #define MMC_TXFRAMECOUNT_G_HI 0x0890 655 #define MMC_TXPAUSEFRAMES_LO 0x0894 656 #define MMC_TXPAUSEFRAMES_HI 0x0898 657 #define MMC_TXVLANFRAMES_G_LO 0x089c 658 #define MMC_TXVLANFRAMES_G_HI 0x08a0 659 #define MMC_RXFRAMECOUNT_GB_LO 0x0900 660 #define MMC_RXFRAMECOUNT_GB_HI 0x0904 661 #define MMC_RXOCTETCOUNT_GB_LO 0x0908 662 #define MMC_RXOCTETCOUNT_GB_HI 0x090c 663 #define MMC_RXOCTETCOUNT_G_LO 0x0910 664 #define MMC_RXOCTETCOUNT_G_HI 0x0914 665 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918 666 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c 667 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920 668 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924 669 #define MMC_RXCRCERROR_LO 0x0928 670 #define MMC_RXCRCERROR_HI 0x092c 671 #define MMC_RXRUNTERROR 0x0930 672 #define MMC_RXJABBERERROR 0x0934 673 #define MMC_RXUNDERSIZE_G 0x0938 674 #define MMC_RXOVERSIZE_G 0x093c 675 #define MMC_RX64OCTETS_GB_LO 0x0940 676 #define MMC_RX64OCTETS_GB_HI 0x0944 677 #define MMC_RX65TO127OCTETS_GB_LO 0x0948 678 #define MMC_RX65TO127OCTETS_GB_HI 0x094c 679 #define MMC_RX128TO255OCTETS_GB_LO 0x0950 680 #define MMC_RX128TO255OCTETS_GB_HI 0x0954 681 #define MMC_RX256TO511OCTETS_GB_LO 0x0958 682 #define MMC_RX256TO511OCTETS_GB_HI 0x095c 683 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960 684 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964 685 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 686 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c 687 #define MMC_RXUNICASTFRAMES_G_LO 0x0970 688 #define MMC_RXUNICASTFRAMES_G_HI 0x0974 689 #define MMC_RXLENGTHERROR_LO 0x0978 690 #define MMC_RXLENGTHERROR_HI 0x097c 691 #define MMC_RXOUTOFRANGETYPE_LO 0x0980 692 #define MMC_RXOUTOFRANGETYPE_HI 0x0984 693 #define MMC_RXPAUSEFRAMES_LO 0x0988 694 #define MMC_RXPAUSEFRAMES_HI 0x098c 695 #define MMC_RXFIFOOVERFLOW_LO 0x0990 696 #define MMC_RXFIFOOVERFLOW_HI 0x0994 697 #define MMC_RXVLANFRAMES_GB_LO 0x0998 698 #define MMC_RXVLANFRAMES_GB_HI 0x099c 699 #define MMC_RXWATCHDOGERROR 0x09a0 700 701 /* MMC register entry bit positions and sizes */ 702 #define MMC_CR_CR_INDEX 0 703 #define MMC_CR_CR_WIDTH 1 704 #define MMC_CR_CSR_INDEX 1 705 #define MMC_CR_CSR_WIDTH 1 706 #define MMC_CR_ROR_INDEX 2 707 #define MMC_CR_ROR_WIDTH 1 708 #define MMC_CR_MCF_INDEX 3 709 #define MMC_CR_MCF_WIDTH 1 710 #define MMC_CR_MCT_INDEX 4 711 #define MMC_CR_MCT_WIDTH 2 712 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0 713 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23 714 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0 715 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1 716 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1 717 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1 718 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2 719 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1 720 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3 721 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1 722 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4 723 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1 724 #define MMC_RISR_RXCRCERROR_INDEX 5 725 #define MMC_RISR_RXCRCERROR_WIDTH 1 726 #define MMC_RISR_RXRUNTERROR_INDEX 6 727 #define MMC_RISR_RXRUNTERROR_WIDTH 1 728 #define MMC_RISR_RXJABBERERROR_INDEX 7 729 #define MMC_RISR_RXJABBERERROR_WIDTH 1 730 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8 731 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1 732 #define MMC_RISR_RXOVERSIZE_G_INDEX 9 733 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1 734 #define MMC_RISR_RX64OCTETS_GB_INDEX 10 735 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1 736 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11 737 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1 738 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12 739 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1 740 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13 741 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1 742 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14 743 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1 744 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15 745 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1 746 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16 747 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1 748 #define MMC_RISR_RXLENGTHERROR_INDEX 17 749 #define MMC_RISR_RXLENGTHERROR_WIDTH 1 750 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18 751 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1 752 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19 753 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1 754 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20 755 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1 756 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21 757 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1 758 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22 759 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1 760 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0 761 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18 762 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0 763 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1 764 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1 765 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1 766 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2 767 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1 768 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3 769 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1 770 #define MMC_TISR_TX64OCTETS_GB_INDEX 4 771 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1 772 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5 773 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1 774 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6 775 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1 776 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7 777 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1 778 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8 779 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1 780 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9 781 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1 782 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10 783 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1 784 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11 785 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1 786 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12 787 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1 788 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13 789 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1 790 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14 791 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1 792 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15 793 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1 794 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16 795 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1 796 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17 797 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1 798 799 /* MTL register offsets */ 800 #define MTL_OMR 0x1000 801 #define MTL_FDCR 0x1008 802 #define MTL_FDSR 0x100c 803 #define MTL_FDDR 0x1010 804 #define MTL_ISR 0x1020 805 #define MTL_RQDCM0R 0x1030 806 #define MTL_RQDCM1R 0x1034 807 #define MTL_RQDCM2R 0x1038 808 #define MTL_TCPM0R 0x1040 809 #define MTL_TCPM1R 0x1044 810 811 #define MTL_RQDCM_INC 4 812 #define MTL_RQDCM_Q_PER_REG 4 813 #define MTL_TCPM_INC 4 814 #define MTL_TCPM_TC_PER_REG 4 815 816 /* MTL register entry bit positions and sizes */ 817 #define MTL_OMR_ETSALG_INDEX 5 818 #define MTL_OMR_ETSALG_WIDTH 2 819 #define MTL_OMR_RAA_INDEX 2 820 #define MTL_OMR_RAA_WIDTH 1 821 822 /* MTL queue register offsets 823 * Multiple queues can be active. The first queue has registers 824 * that begin at 0x1100. Each subsequent queue has registers that 825 * are accessed using an offset of 0x80 from the previous queue. 826 */ 827 #define MTL_Q_BASE 0x1100 828 #define MTL_Q_INC 0x80 829 830 #define MTL_Q_TQOMR 0x00 831 #define MTL_Q_TQUR 0x04 832 #define MTL_Q_TQDR 0x08 833 #define MTL_Q_TC0ETSCR 0x10 834 #define MTL_Q_TC0ETSSR 0x14 835 #define MTL_Q_TC0QWR 0x18 836 #define MTL_Q_RQOMR 0x40 837 #define MTL_Q_RQMPOCR 0x44 838 #define MTL_Q_RQDR 0x48 839 #define MTL_Q_RQCR 0x4c 840 #define MTL_Q_RQFCR 0x50 841 #define MTL_Q_IER 0x70 842 #define MTL_Q_ISR 0x74 843 844 /* MTL queue register entry bit positions and sizes */ 845 #define MTL_Q_RQDR_PRXQ_INDEX 16 846 #define MTL_Q_RQDR_PRXQ_WIDTH 14 847 #define MTL_Q_RQDR_RXQSTS_INDEX 4 848 #define MTL_Q_RQDR_RXQSTS_WIDTH 2 849 #define MTL_Q_RQFCR_RFA_INDEX 1 850 #define MTL_Q_RQFCR_RFA_WIDTH 6 851 #define MTL_Q_RQFCR_RFD_INDEX 17 852 #define MTL_Q_RQFCR_RFD_WIDTH 6 853 #define MTL_Q_RQOMR_EHFC_INDEX 7 854 #define MTL_Q_RQOMR_EHFC_WIDTH 1 855 #define MTL_Q_RQOMR_RQS_INDEX 16 856 #define MTL_Q_RQOMR_RQS_WIDTH 9 857 #define MTL_Q_RQOMR_RSF_INDEX 5 858 #define MTL_Q_RQOMR_RSF_WIDTH 1 859 #define MTL_Q_RQOMR_RTC_INDEX 0 860 #define MTL_Q_RQOMR_RTC_WIDTH 2 861 #define MTL_Q_TQDR_TRCSTS_INDEX 1 862 #define MTL_Q_TQDR_TRCSTS_WIDTH 2 863 #define MTL_Q_TQDR_TXQSTS_INDEX 4 864 #define MTL_Q_TQDR_TXQSTS_WIDTH 1 865 #define MTL_Q_TQOMR_FTQ_INDEX 0 866 #define MTL_Q_TQOMR_FTQ_WIDTH 1 867 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8 868 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3 869 #define MTL_Q_TQOMR_TQS_INDEX 16 870 #define MTL_Q_TQOMR_TQS_WIDTH 10 871 #define MTL_Q_TQOMR_TSF_INDEX 1 872 #define MTL_Q_TQOMR_TSF_WIDTH 1 873 #define MTL_Q_TQOMR_TTC_INDEX 4 874 #define MTL_Q_TQOMR_TTC_WIDTH 3 875 #define MTL_Q_TQOMR_TXQEN_INDEX 2 876 #define MTL_Q_TQOMR_TXQEN_WIDTH 2 877 878 /* MTL queue register value */ 879 #define MTL_RSF_DISABLE 0x00 880 #define MTL_RSF_ENABLE 0x01 881 #define MTL_TSF_DISABLE 0x00 882 #define MTL_TSF_ENABLE 0x01 883 884 #define MTL_RX_THRESHOLD_64 0x00 885 #define MTL_RX_THRESHOLD_96 0x02 886 #define MTL_RX_THRESHOLD_128 0x03 887 #define MTL_TX_THRESHOLD_32 0x01 888 #define MTL_TX_THRESHOLD_64 0x00 889 #define MTL_TX_THRESHOLD_96 0x02 890 #define MTL_TX_THRESHOLD_128 0x03 891 #define MTL_TX_THRESHOLD_192 0x04 892 #define MTL_TX_THRESHOLD_256 0x05 893 #define MTL_TX_THRESHOLD_384 0x06 894 #define MTL_TX_THRESHOLD_512 0x07 895 896 #define MTL_ETSALG_WRR 0x00 897 #define MTL_ETSALG_WFQ 0x01 898 #define MTL_ETSALG_DWRR 0x02 899 #define MTL_RAA_SP 0x00 900 #define MTL_RAA_WSP 0x01 901 902 #define MTL_Q_DISABLED 0x00 903 #define MTL_Q_ENABLED 0x02 904 905 /* MTL traffic class register offsets 906 * Multiple traffic classes can be active. The first class has registers 907 * that begin at 0x1100. Each subsequent queue has registers that 908 * are accessed using an offset of 0x80 from the previous queue. 909 */ 910 #define MTL_TC_BASE MTL_Q_BASE 911 #define MTL_TC_INC MTL_Q_INC 912 913 #define MTL_TC_ETSCR 0x10 914 #define MTL_TC_ETSSR 0x14 915 #define MTL_TC_QWR 0x18 916 917 /* MTL traffic class register entry bit positions and sizes */ 918 #define MTL_TC_ETSCR_TSA_INDEX 0 919 #define MTL_TC_ETSCR_TSA_WIDTH 2 920 #define MTL_TC_QWR_QW_INDEX 0 921 #define MTL_TC_QWR_QW_WIDTH 21 922 923 /* MTL traffic class register value */ 924 #define MTL_TSA_SP 0x00 925 #define MTL_TSA_ETS 0x02 926 927 /* PCS MMD select register offset 928 * The MMD select register is used for accessing PCS registers 929 * when the underlying APB3 interface is using indirect addressing. 930 * Indirect addressing requires accessing registers in two phases, 931 * an address phase and a data phase. The address phases requires 932 * writing an address selection value to the MMD select regiesters. 933 */ 934 #define PCS_V1_WINDOW_SELECT 0x03fc 935 #define PCS_V2_WINDOW_DEF 0x9060 936 #define PCS_V2_WINDOW_SELECT 0x9064 937 #define PCS_V2_RV_WINDOW_DEF 0x1060 938 #define PCS_V2_RV_WINDOW_SELECT 0x1064 939 940 /* PCS register entry bit positions and sizes */ 941 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6 942 #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14 943 #define PCS_V2_WINDOW_DEF_SIZE_INDEX 2 944 #define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4 945 946 /* SerDes integration register offsets */ 947 #define SIR0_KR_RT_1 0x002c 948 #define SIR0_STATUS 0x0040 949 #define SIR1_SPEED 0x0000 950 951 /* SerDes integration register entry bit positions and sizes */ 952 #define SIR0_KR_RT_1_RESET_INDEX 11 953 #define SIR0_KR_RT_1_RESET_WIDTH 1 954 #define SIR0_STATUS_RX_READY_INDEX 0 955 #define SIR0_STATUS_RX_READY_WIDTH 1 956 #define SIR0_STATUS_TX_READY_INDEX 8 957 #define SIR0_STATUS_TX_READY_WIDTH 1 958 #define SIR1_SPEED_CDR_RATE_INDEX 12 959 #define SIR1_SPEED_CDR_RATE_WIDTH 4 960 #define SIR1_SPEED_DATARATE_INDEX 4 961 #define SIR1_SPEED_DATARATE_WIDTH 2 962 #define SIR1_SPEED_PLLSEL_INDEX 3 963 #define SIR1_SPEED_PLLSEL_WIDTH 1 964 #define SIR1_SPEED_RATECHANGE_INDEX 6 965 #define SIR1_SPEED_RATECHANGE_WIDTH 1 966 #define SIR1_SPEED_TXAMP_INDEX 8 967 #define SIR1_SPEED_TXAMP_WIDTH 4 968 #define SIR1_SPEED_WORDMODE_INDEX 0 969 #define SIR1_SPEED_WORDMODE_WIDTH 3 970 971 /* SerDes RxTx register offsets */ 972 #define RXTX_REG6 0x0018 973 #define RXTX_REG20 0x0050 974 #define RXTX_REG22 0x0058 975 #define RXTX_REG114 0x01c8 976 #define RXTX_REG129 0x0204 977 978 /* SerDes RxTx register entry bit positions and sizes */ 979 #define RXTX_REG6_RESETB_RXD_INDEX 8 980 #define RXTX_REG6_RESETB_RXD_WIDTH 1 981 #define RXTX_REG20_BLWC_ENA_INDEX 2 982 #define RXTX_REG20_BLWC_ENA_WIDTH 1 983 #define RXTX_REG114_PQ_REG_INDEX 9 984 #define RXTX_REG114_PQ_REG_WIDTH 7 985 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14 986 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2 987 988 /* MAC Control register offsets */ 989 #define XP_PROP_0 0x0000 990 #define XP_PROP_1 0x0004 991 #define XP_PROP_2 0x0008 992 #define XP_PROP_3 0x000c 993 #define XP_PROP_4 0x0010 994 #define XP_PROP_5 0x0014 995 #define XP_MAC_ADDR_LO 0x0020 996 #define XP_MAC_ADDR_HI 0x0024 997 #define XP_ECC_ISR 0x0030 998 #define XP_ECC_IER 0x0034 999 #define XP_ECC_CNT0 0x003c 1000 #define XP_ECC_CNT1 0x0040 1001 #define XP_DRIVER_INT_REQ 0x0060 1002 #define XP_DRIVER_INT_RO 0x0064 1003 #define XP_DRIVER_SCRATCH_0 0x0068 1004 #define XP_DRIVER_SCRATCH_1 0x006c 1005 #define XP_INT_REISSUE_EN 0x0074 1006 #define XP_INT_EN 0x0078 1007 #define XP_I2C_MUTEX 0x0080 1008 #define XP_MDIO_MUTEX 0x0084 1009 1010 /* MAC Control register entry bit positions and sizes */ 1011 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0 1012 #define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1 1013 #define XP_DRIVER_INT_RO_STATUS_INDEX 0 1014 #define XP_DRIVER_INT_RO_STATUS_WIDTH 1 1015 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0 1016 #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8 1017 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8 1018 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8 1019 #define XP_ECC_CNT0_RX_DED_INDEX 24 1020 #define XP_ECC_CNT0_RX_DED_WIDTH 8 1021 #define XP_ECC_CNT0_RX_SEC_INDEX 16 1022 #define XP_ECC_CNT0_RX_SEC_WIDTH 8 1023 #define XP_ECC_CNT0_TX_DED_INDEX 8 1024 #define XP_ECC_CNT0_TX_DED_WIDTH 8 1025 #define XP_ECC_CNT0_TX_SEC_INDEX 0 1026 #define XP_ECC_CNT0_TX_SEC_WIDTH 8 1027 #define XP_ECC_CNT1_DESC_DED_INDEX 8 1028 #define XP_ECC_CNT1_DESC_DED_WIDTH 8 1029 #define XP_ECC_CNT1_DESC_SEC_INDEX 0 1030 #define XP_ECC_CNT1_DESC_SEC_WIDTH 8 1031 #define XP_ECC_IER_DESC_DED_INDEX 5 1032 #define XP_ECC_IER_DESC_DED_WIDTH 1 1033 #define XP_ECC_IER_DESC_SEC_INDEX 4 1034 #define XP_ECC_IER_DESC_SEC_WIDTH 1 1035 #define XP_ECC_IER_RX_DED_INDEX 3 1036 #define XP_ECC_IER_RX_DED_WIDTH 1 1037 #define XP_ECC_IER_RX_SEC_INDEX 2 1038 #define XP_ECC_IER_RX_SEC_WIDTH 1 1039 #define XP_ECC_IER_TX_DED_INDEX 1 1040 #define XP_ECC_IER_TX_DED_WIDTH 1 1041 #define XP_ECC_IER_TX_SEC_INDEX 0 1042 #define XP_ECC_IER_TX_SEC_WIDTH 1 1043 #define XP_ECC_ISR_DESC_DED_INDEX 5 1044 #define XP_ECC_ISR_DESC_DED_WIDTH 1 1045 #define XP_ECC_ISR_DESC_SEC_INDEX 4 1046 #define XP_ECC_ISR_DESC_SEC_WIDTH 1 1047 #define XP_ECC_ISR_RX_DED_INDEX 3 1048 #define XP_ECC_ISR_RX_DED_WIDTH 1 1049 #define XP_ECC_ISR_RX_SEC_INDEX 2 1050 #define XP_ECC_ISR_RX_SEC_WIDTH 1 1051 #define XP_ECC_ISR_TX_DED_INDEX 1 1052 #define XP_ECC_ISR_TX_DED_WIDTH 1 1053 #define XP_ECC_ISR_TX_SEC_INDEX 0 1054 #define XP_ECC_ISR_TX_SEC_WIDTH 1 1055 #define XP_I2C_MUTEX_BUSY_INDEX 31 1056 #define XP_I2C_MUTEX_BUSY_WIDTH 1 1057 #define XP_I2C_MUTEX_ID_INDEX 29 1058 #define XP_I2C_MUTEX_ID_WIDTH 2 1059 #define XP_I2C_MUTEX_ACTIVE_INDEX 0 1060 #define XP_I2C_MUTEX_ACTIVE_WIDTH 1 1061 #define XP_MAC_ADDR_HI_VALID_INDEX 31 1062 #define XP_MAC_ADDR_HI_VALID_WIDTH 1 1063 #define XP_PROP_0_CONN_TYPE_INDEX 28 1064 #define XP_PROP_0_CONN_TYPE_WIDTH 3 1065 #define XP_PROP_0_MDIO_ADDR_INDEX 16 1066 #define XP_PROP_0_MDIO_ADDR_WIDTH 5 1067 #define XP_PROP_0_PORT_ID_INDEX 0 1068 #define XP_PROP_0_PORT_ID_WIDTH 8 1069 #define XP_PROP_0_PORT_MODE_INDEX 8 1070 #define XP_PROP_0_PORT_MODE_WIDTH 4 1071 #define XP_PROP_0_PORT_SPEEDS_INDEX 23 1072 #define XP_PROP_0_PORT_SPEEDS_WIDTH 4 1073 #define XP_PROP_1_MAX_RX_DMA_INDEX 24 1074 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5 1075 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8 1076 #define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5 1077 #define XP_PROP_1_MAX_TX_DMA_INDEX 16 1078 #define XP_PROP_1_MAX_TX_DMA_WIDTH 5 1079 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0 1080 #define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5 1081 #define XP_PROP_2_RX_FIFO_SIZE_INDEX 16 1082 #define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16 1083 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0 1084 #define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16 1085 #define XP_PROP_3_GPIO_MASK_INDEX 28 1086 #define XP_PROP_3_GPIO_MASK_WIDTH 4 1087 #define XP_PROP_3_GPIO_MOD_ABS_INDEX 20 1088 #define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4 1089 #define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16 1090 #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4 1091 #define XP_PROP_3_GPIO_RX_LOS_INDEX 24 1092 #define XP_PROP_3_GPIO_RX_LOS_WIDTH 4 1093 #define XP_PROP_3_GPIO_TX_FAULT_INDEX 12 1094 #define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4 1095 #define XP_PROP_3_GPIO_ADDR_INDEX 8 1096 #define XP_PROP_3_GPIO_ADDR_WIDTH 3 1097 #define XP_PROP_3_MDIO_RESET_INDEX 0 1098 #define XP_PROP_3_MDIO_RESET_WIDTH 2 1099 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8 1100 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3 1101 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12 1102 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4 1103 #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4 1104 #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2 1105 #define XP_PROP_4_MUX_ADDR_HI_INDEX 8 1106 #define XP_PROP_4_MUX_ADDR_HI_WIDTH 5 1107 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0 1108 #define XP_PROP_4_MUX_ADDR_LO_WIDTH 3 1109 #define XP_PROP_4_MUX_CHAN_INDEX 4 1110 #define XP_PROP_4_MUX_CHAN_WIDTH 3 1111 #define XP_PROP_4_REDRV_ADDR_INDEX 16 1112 #define XP_PROP_4_REDRV_ADDR_WIDTH 7 1113 #define XP_PROP_4_REDRV_IF_INDEX 23 1114 #define XP_PROP_4_REDRV_IF_WIDTH 1 1115 #define XP_PROP_4_REDRV_LANE_INDEX 24 1116 #define XP_PROP_4_REDRV_LANE_WIDTH 3 1117 #define XP_PROP_4_REDRV_MODEL_INDEX 28 1118 #define XP_PROP_4_REDRV_MODEL_WIDTH 3 1119 #define XP_PROP_4_REDRV_PRESENT_INDEX 31 1120 #define XP_PROP_4_REDRV_PRESENT_WIDTH 1 1121 1122 /* I2C Control register offsets */ 1123 #define IC_CON 0x0000 1124 #define IC_TAR 0x0004 1125 #define IC_DATA_CMD 0x0010 1126 #define IC_INTR_STAT 0x002c 1127 #define IC_INTR_MASK 0x0030 1128 #define IC_RAW_INTR_STAT 0x0034 1129 #define IC_CLR_INTR 0x0040 1130 #define IC_CLR_TX_ABRT 0x0054 1131 #define IC_CLR_STOP_DET 0x0060 1132 #define IC_ENABLE 0x006c 1133 #define IC_TXFLR 0x0074 1134 #define IC_RXFLR 0x0078 1135 #define IC_TX_ABRT_SOURCE 0x0080 1136 #define IC_ENABLE_STATUS 0x009c 1137 #define IC_COMP_PARAM_1 0x00f4 1138 1139 /* I2C Control register entry bit positions and sizes */ 1140 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2 1141 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2 1142 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8 1143 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8 1144 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16 1145 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8 1146 #define IC_CON_MASTER_MODE_INDEX 0 1147 #define IC_CON_MASTER_MODE_WIDTH 1 1148 #define IC_CON_RESTART_EN_INDEX 5 1149 #define IC_CON_RESTART_EN_WIDTH 1 1150 #define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9 1151 #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1 1152 #define IC_CON_SLAVE_DISABLE_INDEX 6 1153 #define IC_CON_SLAVE_DISABLE_WIDTH 1 1154 #define IC_CON_SPEED_INDEX 1 1155 #define IC_CON_SPEED_WIDTH 2 1156 #define IC_DATA_CMD_CMD_INDEX 8 1157 #define IC_DATA_CMD_CMD_WIDTH 1 1158 #define IC_DATA_CMD_STOP_INDEX 9 1159 #define IC_DATA_CMD_STOP_WIDTH 1 1160 #define IC_ENABLE_ABORT_INDEX 1 1161 #define IC_ENABLE_ABORT_WIDTH 1 1162 #define IC_ENABLE_EN_INDEX 0 1163 #define IC_ENABLE_EN_WIDTH 1 1164 #define IC_ENABLE_STATUS_EN_INDEX 0 1165 #define IC_ENABLE_STATUS_EN_WIDTH 1 1166 #define IC_INTR_MASK_TX_EMPTY_INDEX 4 1167 #define IC_INTR_MASK_TX_EMPTY_WIDTH 1 1168 #define IC_RAW_INTR_STAT_RX_FULL_INDEX 2 1169 #define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1 1170 #define IC_RAW_INTR_STAT_STOP_DET_INDEX 9 1171 #define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1 1172 #define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6 1173 #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1 1174 #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4 1175 #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1 1176 1177 /* I2C Control register value */ 1178 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001 1179 #define IC_TX_ABRT_ARB_LOST 0x1000 1180 1181 /* Descriptor/Packet entry bit positions and sizes */ 1182 #define RX_PACKET_ERRORS_CRC_INDEX 2 1183 #define RX_PACKET_ERRORS_CRC_WIDTH 1 1184 #define RX_PACKET_ERRORS_FRAME_INDEX 3 1185 #define RX_PACKET_ERRORS_FRAME_WIDTH 1 1186 #define RX_PACKET_ERRORS_LENGTH_INDEX 0 1187 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1 1188 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1 1189 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1 1190 1191 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0 1192 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1 1193 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1 1194 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 1195 #define RX_PACKET_ATTRIBUTES_LAST_INDEX 2 1196 #define RX_PACKET_ATTRIBUTES_LAST_WIDTH 1 1197 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3 1198 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1 1199 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4 1200 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1 1201 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5 1202 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1 1203 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6 1204 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1 1205 #define RX_PACKET_ATTRIBUTES_FIRST_INDEX 7 1206 #define RX_PACKET_ATTRIBUTES_FIRST_WIDTH 1 1207 #define RX_PACKET_ATTRIBUTES_TNP_INDEX 8 1208 #define RX_PACKET_ATTRIBUTES_TNP_WIDTH 1 1209 #define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX 9 1210 #define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH 1 1211 1212 #define RX_NORMAL_DESC0_OVT_INDEX 0 1213 #define RX_NORMAL_DESC0_OVT_WIDTH 16 1214 #define RX_NORMAL_DESC2_HL_INDEX 0 1215 #define RX_NORMAL_DESC2_HL_WIDTH 10 1216 #define RX_NORMAL_DESC2_TNP_INDEX 11 1217 #define RX_NORMAL_DESC2_TNP_WIDTH 1 1218 #define RX_NORMAL_DESC2_RPNG_INDEX 14 1219 #define RX_NORMAL_DESC2_RPNG_WIDTH 1 1220 #define RX_NORMAL_DESC3_CDA_INDEX 27 1221 #define RX_NORMAL_DESC3_CDA_WIDTH 1 1222 #define RX_NORMAL_DESC3_CTXT_INDEX 30 1223 #define RX_NORMAL_DESC3_CTXT_WIDTH 1 1224 #define RX_NORMAL_DESC3_ES_INDEX 15 1225 #define RX_NORMAL_DESC3_ES_WIDTH 1 1226 #define RX_NORMAL_DESC3_ETLT_INDEX 16 1227 #define RX_NORMAL_DESC3_ETLT_WIDTH 4 1228 #define RX_NORMAL_DESC3_FD_INDEX 29 1229 #define RX_NORMAL_DESC3_FD_WIDTH 1 1230 #define RX_NORMAL_DESC3_INTE_INDEX 30 1231 #define RX_NORMAL_DESC3_INTE_WIDTH 1 1232 #define RX_NORMAL_DESC3_L34T_INDEX 20 1233 #define RX_NORMAL_DESC3_L34T_WIDTH 4 1234 #define RX_NORMAL_DESC3_LD_INDEX 28 1235 #define RX_NORMAL_DESC3_LD_WIDTH 1 1236 #define RX_NORMAL_DESC3_OWN_INDEX 31 1237 #define RX_NORMAL_DESC3_OWN_WIDTH 1 1238 #define RX_NORMAL_DESC3_PL_INDEX 0 1239 #define RX_NORMAL_DESC3_PL_WIDTH 14 1240 #define RX_NORMAL_DESC3_RSV_INDEX 26 1241 #define RX_NORMAL_DESC3_RSV_WIDTH 1 1242 1243 #define RX_DESC3_L34T_IPV4_TCP 1 1244 #define RX_DESC3_L34T_IPV4_UDP 2 1245 #define RX_DESC3_L34T_IPV4_ICMP 3 1246 #define RX_DESC3_L34T_IPV4_UNKNOWN 7 1247 #define RX_DESC3_L34T_IPV6_TCP 9 1248 #define RX_DESC3_L34T_IPV6_UDP 10 1249 #define RX_DESC3_L34T_IPV6_ICMP 11 1250 #define RX_DESC3_L34T_IPV6_UNKNOWN 15 1251 1252 #define RX_CONTEXT_DESC3_TSA_INDEX 4 1253 #define RX_CONTEXT_DESC3_TSA_WIDTH 1 1254 #define RX_CONTEXT_DESC3_TSD_INDEX 6 1255 #define RX_CONTEXT_DESC3_TSD_WIDTH 1 1256 1257 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0 1258 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1 1259 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1 1260 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1 1261 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2 1262 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1 1263 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3 1264 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1 1265 #define TX_PACKET_ATTRIBUTES_VXLAN_INDEX 4 1266 #define TX_PACKET_ATTRIBUTES_VXLAN_WIDTH 1 1267 1268 #define TX_CONTEXT_DESC2_MSS_INDEX 0 1269 #define TX_CONTEXT_DESC2_MSS_WIDTH 15 1270 #define TX_CONTEXT_DESC3_CTXT_INDEX 30 1271 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1 1272 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26 1273 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1 1274 #define TX_CONTEXT_DESC3_VLTV_INDEX 16 1275 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1 1276 #define TX_CONTEXT_DESC3_VT_INDEX 0 1277 #define TX_CONTEXT_DESC3_VT_WIDTH 16 1278 1279 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0 1280 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14 1281 #define TX_NORMAL_DESC2_IC_INDEX 31 1282 #define TX_NORMAL_DESC2_IC_WIDTH 1 1283 #define TX_NORMAL_DESC2_TTSE_INDEX 30 1284 #define TX_NORMAL_DESC2_TTSE_WIDTH 1 1285 #define TX_NORMAL_DESC2_VTIR_INDEX 14 1286 #define TX_NORMAL_DESC2_VTIR_WIDTH 2 1287 #define TX_NORMAL_DESC3_CIC_INDEX 16 1288 #define TX_NORMAL_DESC3_CIC_WIDTH 2 1289 #define TX_NORMAL_DESC3_CPC_INDEX 26 1290 #define TX_NORMAL_DESC3_CPC_WIDTH 2 1291 #define TX_NORMAL_DESC3_CTXT_INDEX 30 1292 #define TX_NORMAL_DESC3_CTXT_WIDTH 1 1293 #define TX_NORMAL_DESC3_FD_INDEX 29 1294 #define TX_NORMAL_DESC3_FD_WIDTH 1 1295 #define TX_NORMAL_DESC3_FL_INDEX 0 1296 #define TX_NORMAL_DESC3_FL_WIDTH 15 1297 #define TX_NORMAL_DESC3_LD_INDEX 28 1298 #define TX_NORMAL_DESC3_LD_WIDTH 1 1299 #define TX_NORMAL_DESC3_OWN_INDEX 31 1300 #define TX_NORMAL_DESC3_OWN_WIDTH 1 1301 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19 1302 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4 1303 #define TX_NORMAL_DESC3_TCPPL_INDEX 0 1304 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18 1305 #define TX_NORMAL_DESC3_TSE_INDEX 18 1306 #define TX_NORMAL_DESC3_TSE_WIDTH 1 1307 #define TX_NORMAL_DESC3_VNP_INDEX 23 1308 #define TX_NORMAL_DESC3_VNP_WIDTH 3 1309 1310 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2 1311 #define TX_NORMAL_DESC3_VXLAN_PACKET 0x3 1312 1313 /* MDIO undefined or vendor specific registers */ 1314 #ifndef MDIO_PMA_10GBR_PMD_CTRL 1315 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096 1316 #endif 1317 1318 #ifndef MDIO_PMA_10GBR_FECCTRL 1319 #define MDIO_PMA_10GBR_FECCTRL 0x00ab 1320 #endif 1321 1322 #ifndef MDIO_PCS_DIG_CTRL 1323 #define MDIO_PCS_DIG_CTRL 0x8000 1324 #endif 1325 1326 #ifndef MDIO_AN_XNP 1327 #define MDIO_AN_XNP 0x0016 1328 #endif 1329 1330 #ifndef MDIO_AN_LPX 1331 #define MDIO_AN_LPX 0x0019 1332 #endif 1333 1334 #ifndef MDIO_AN_COMP_STAT 1335 #define MDIO_AN_COMP_STAT 0x0030 1336 #endif 1337 1338 #ifndef MDIO_AN_INTMASK 1339 #define MDIO_AN_INTMASK 0x8001 1340 #endif 1341 1342 #ifndef MDIO_AN_INT 1343 #define MDIO_AN_INT 0x8002 1344 #endif 1345 1346 #ifndef MDIO_VEND2_AN_ADVERTISE 1347 #define MDIO_VEND2_AN_ADVERTISE 0x0004 1348 #endif 1349 1350 #ifndef MDIO_VEND2_AN_LP_ABILITY 1351 #define MDIO_VEND2_AN_LP_ABILITY 0x0005 1352 #endif 1353 1354 #ifndef MDIO_VEND2_AN_CTRL 1355 #define MDIO_VEND2_AN_CTRL 0x8001 1356 #endif 1357 1358 #ifndef MDIO_VEND2_AN_STAT 1359 #define MDIO_VEND2_AN_STAT 0x8002 1360 #endif 1361 1362 #ifndef MDIO_VEND2_PMA_CDR_CONTROL 1363 #define MDIO_VEND2_PMA_CDR_CONTROL 0x8056 1364 #endif 1365 1366 #ifndef MDIO_CTRL1_SPEED1G 1367 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) 1368 #endif 1369 1370 #ifndef MDIO_VEND2_CTRL1_AN_ENABLE 1371 #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12) 1372 #endif 1373 1374 #ifndef MDIO_VEND2_CTRL1_AN_RESTART 1375 #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9) 1376 #endif 1377 1378 #ifndef MDIO_VEND2_CTRL1_SS6 1379 #define MDIO_VEND2_CTRL1_SS6 BIT(6) 1380 #endif 1381 1382 #ifndef MDIO_VEND2_CTRL1_SS13 1383 #define MDIO_VEND2_CTRL1_SS13 BIT(13) 1384 #endif 1385 1386 /* MDIO mask values */ 1387 #define XGBE_AN_CL73_INT_CMPLT BIT(0) 1388 #define XGBE_AN_CL73_INC_LINK BIT(1) 1389 #define XGBE_AN_CL73_PG_RCV BIT(2) 1390 #define XGBE_AN_CL73_INT_MASK 0x07 1391 1392 #define XGBE_XNP_MCF_NULL_MESSAGE 0x001 1393 #define XGBE_XNP_ACK_PROCESSED BIT(12) 1394 #define XGBE_XNP_MP_FORMATTED BIT(13) 1395 #define XGBE_XNP_NP_EXCHANGE BIT(15) 1396 1397 #define XGBE_KR_TRAINING_START BIT(0) 1398 #define XGBE_KR_TRAINING_ENABLE BIT(1) 1399 1400 #define XGBE_PCS_CL37_BP BIT(12) 1401 1402 #define XGBE_AN_CL37_INT_CMPLT BIT(0) 1403 #define XGBE_AN_CL37_INT_MASK 0x01 1404 1405 #define XGBE_AN_CL37_HD_MASK 0x40 1406 #define XGBE_AN_CL37_FD_MASK 0x20 1407 1408 #define XGBE_AN_CL37_PCS_MODE_MASK 0x06 1409 #define XGBE_AN_CL37_PCS_MODE_BASEX 0x00 1410 #define XGBE_AN_CL37_PCS_MODE_SGMII 0x04 1411 #define XGBE_AN_CL37_TX_CONFIG_MASK 0x08 1412 #define XGBE_AN_CL37_MII_CTRL_8BIT 0x0100 1413 1414 #define XGBE_PMA_CDR_TRACK_EN_MASK 0x01 1415 #define XGBE_PMA_CDR_TRACK_EN_OFF 0x00 1416 #define XGBE_PMA_CDR_TRACK_EN_ON 0x01 1417 1418 /* Bit setting and getting macros 1419 * The get macro will extract the current bit field value from within 1420 * the variable 1421 * 1422 * The set macro will clear the current bit field value within the 1423 * variable and then set the bit field of the variable to the 1424 * specified value 1425 */ 1426 #define GET_BITS(_var, _index, _width) \ 1427 (((_var) >> (_index)) & ((0x1 << (_width)) - 1)) 1428 1429 #define SET_BITS(_var, _index, _width, _val) \ 1430 do { \ 1431 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \ 1432 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \ 1433 } while (0) 1434 1435 #define GET_BITS_LE(_var, _index, _width) \ 1436 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1)) 1437 1438 #define SET_BITS_LE(_var, _index, _width, _val) \ 1439 do { \ 1440 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \ 1441 (_var) |= cpu_to_le32((((_val) & \ 1442 ((0x1 << (_width)) - 1)) << (_index))); \ 1443 } while (0) 1444 1445 /* Bit setting and getting macros based on register fields 1446 * The get macro uses the bit field definitions formed using the input 1447 * names to extract the current bit field value from within the 1448 * variable 1449 * 1450 * The set macro uses the bit field definitions formed using the input 1451 * names to set the bit field of the variable to the specified value 1452 */ 1453 #define XGMAC_GET_BITS(_var, _prefix, _field) \ 1454 GET_BITS((_var), \ 1455 _prefix##_##_field##_INDEX, \ 1456 _prefix##_##_field##_WIDTH) 1457 1458 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \ 1459 SET_BITS((_var), \ 1460 _prefix##_##_field##_INDEX, \ 1461 _prefix##_##_field##_WIDTH, (_val)) 1462 1463 #define XGMAC_GET_BITS_LE(_var, _prefix, _field) \ 1464 GET_BITS_LE((_var), \ 1465 _prefix##_##_field##_INDEX, \ 1466 _prefix##_##_field##_WIDTH) 1467 1468 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \ 1469 SET_BITS_LE((_var), \ 1470 _prefix##_##_field##_INDEX, \ 1471 _prefix##_##_field##_WIDTH, (_val)) 1472 1473 /* Macros for reading or writing registers 1474 * The ioread macros will get bit fields or full values using the 1475 * register definitions formed using the input names 1476 * 1477 * The iowrite macros will set bit fields or full values using the 1478 * register definitions formed using the input names 1479 */ 1480 #define XGMAC_IOREAD(_pdata, _reg) \ 1481 bus_read_4((_pdata)->xgmac_res, _reg) 1482 1483 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \ 1484 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \ 1485 _reg##_##_field##_INDEX, \ 1486 _reg##_##_field##_WIDTH) 1487 1488 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ 1489 bus_write_4((_pdata)->xgmac_res, _reg, (_val)) 1490 1491 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1492 do { \ 1493 uint32_t reg_val = XGMAC_IOREAD((_pdata), _reg); \ 1494 SET_BITS(reg_val, \ 1495 _reg##_##_field##_INDEX, \ 1496 _reg##_##_field##_WIDTH, (_val)); \ 1497 XGMAC_IOWRITE((_pdata), _reg, reg_val); \ 1498 } while (0) 1499 1500 /* Macros for reading or writing MTL queue or traffic class registers 1501 * Similar to the standard read and write macros except that the 1502 * base register value is calculated by the queue or traffic class number 1503 */ 1504 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \ 1505 bus_read_4((_pdata)->xgmac_res, \ 1506 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg) 1507 1508 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \ 1509 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \ 1510 _reg##_##_field##_INDEX, \ 1511 _reg##_##_field##_WIDTH) 1512 1513 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \ 1514 bus_write_4((_pdata)->xgmac_res, \ 1515 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg, (_val)) 1516 1517 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \ 1518 do { \ 1519 uint32_t reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \ 1520 SET_BITS(reg_val, \ 1521 _reg##_##_field##_INDEX, \ 1522 _reg##_##_field##_WIDTH, (_val)); \ 1523 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \ 1524 } while (0) 1525 1526 /* Macros for reading or writing DMA channel registers 1527 * Similar to the standard read and write macros except that the 1528 * base register value is obtained from the ring 1529 */ 1530 #define XGMAC_DMA_IOREAD(_channel, _reg) \ 1531 bus_space_read_4((_channel)->dma_tag, (_channel)->dma_handle, _reg) 1532 1533 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \ 1534 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \ 1535 _reg##_##_field##_INDEX, \ 1536 _reg##_##_field##_WIDTH) 1537 1538 #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \ 1539 bus_space_write_4((_channel)->dma_tag, (_channel)->dma_handle, \ 1540 _reg, (_val)) 1541 1542 #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \ 1543 do { \ 1544 uint32_t reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \ 1545 SET_BITS(reg_val, \ 1546 _reg##_##_field##_INDEX, \ 1547 _reg##_##_field##_WIDTH, (_val)); \ 1548 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \ 1549 } while (0) 1550 1551 /* Macros for building, reading or writing register values or bits 1552 * within the register values of XPCS registers. 1553 */ 1554 #define XPCS_GET_BITS(_var, _prefix, _field) \ 1555 GET_BITS((_var), \ 1556 _prefix##_##_field##_INDEX, \ 1557 _prefix##_##_field##_WIDTH) 1558 1559 #define XPCS_SET_BITS(_var, _prefix, _field, _val) \ 1560 SET_BITS((_var), \ 1561 _prefix##_##_field##_INDEX, \ 1562 _prefix##_##_field##_WIDTH, (_val)) 1563 1564 #define XPCS32_IOWRITE(_pdata, _off, _val) \ 1565 bus_write_4((_pdata)->xpcs_res, (_off), _val) 1566 1567 #define XPCS32_IOREAD(_pdata, _off) \ 1568 bus_read_4((_pdata)->xpcs_res, (_off)) 1569 1570 #define XPCS16_IOWRITE(_pdata, _off, _val) \ 1571 bus_write_2((_pdata)->xpcs_res, (_off), _val) 1572 1573 #define XPCS16_IOREAD(_pdata, _off) \ 1574 bus_read_2((_pdata)->xpcs_res, (_off)) 1575 1576 /* Macros for building, reading or writing register values or bits 1577 * within the register values of SerDes integration registers. 1578 */ 1579 #define XSIR_GET_BITS(_var, _prefix, _field) \ 1580 GET_BITS((_var), \ 1581 _prefix##_##_field##_INDEX, \ 1582 _prefix##_##_field##_WIDTH) 1583 1584 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \ 1585 SET_BITS((_var), \ 1586 _prefix##_##_field##_INDEX, \ 1587 _prefix##_##_field##_WIDTH, (_val)) 1588 1589 #define XSIR0_IOREAD(_pdata, _reg) \ 1590 bus_read_2((_pdata)->sir0_res, _reg) 1591 1592 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \ 1593 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \ 1594 _reg##_##_field##_INDEX, \ 1595 _reg##_##_field##_WIDTH) 1596 1597 #define XSIR0_IOWRITE(_pdata, _reg, _val) \ 1598 bus_write_2((_pdata)->sir0_res, _reg, (_val)) 1599 1600 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1601 do { \ 1602 uint16_t reg_val = XSIR0_IOREAD((_pdata), _reg); \ 1603 SET_BITS(reg_val, \ 1604 _reg##_##_field##_INDEX, \ 1605 _reg##_##_field##_WIDTH, (_val)); \ 1606 XSIR0_IOWRITE((_pdata), _reg, reg_val); \ 1607 } while (0) 1608 1609 #define XSIR1_IOREAD(_pdata, _reg) \ 1610 bus_read_2((_pdata)->sir1_res, _reg) 1611 1612 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \ 1613 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \ 1614 _reg##_##_field##_INDEX, \ 1615 _reg##_##_field##_WIDTH) 1616 1617 #define XSIR1_IOWRITE(_pdata, _reg, _val) \ 1618 bus_write_2((_pdata)->sir1_res, _reg, (_val)) 1619 1620 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1621 do { \ 1622 uint16_t reg_val = XSIR1_IOREAD((_pdata), _reg); \ 1623 SET_BITS(reg_val, \ 1624 _reg##_##_field##_INDEX, \ 1625 _reg##_##_field##_WIDTH, (_val)); \ 1626 XSIR1_IOWRITE((_pdata), _reg, reg_val); \ 1627 } while (0) 1628 1629 /* Macros for building, reading or writing register values or bits 1630 * within the register values of SerDes RxTx registers. 1631 */ 1632 #define XRXTX_IOREAD(_pdata, _reg) \ 1633 bus_read_2((_pdata)->rxtx_res, _reg) 1634 1635 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \ 1636 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \ 1637 _reg##_##_field##_INDEX, \ 1638 _reg##_##_field##_WIDTH) 1639 1640 #define XRXTX_IOWRITE(_pdata, _reg, _val) \ 1641 bus_write_2((_pdata)->rxtx_res, _reg, (_val)) 1642 1643 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1644 do { \ 1645 uint16_t reg_val = XRXTX_IOREAD((_pdata), _reg); \ 1646 SET_BITS(reg_val, \ 1647 _reg##_##_field##_INDEX, \ 1648 _reg##_##_field##_WIDTH, (_val)); \ 1649 XRXTX_IOWRITE((_pdata), _reg, reg_val); \ 1650 } while (0) 1651 1652 /* Macros for building, reading or writing register values or bits 1653 * within the register values of MAC Control registers. 1654 */ 1655 #define XP_GET_BITS(_var, _prefix, _field) \ 1656 GET_BITS((_var), \ 1657 _prefix##_##_field##_INDEX, \ 1658 _prefix##_##_field##_WIDTH) 1659 1660 #define XP_SET_BITS(_var, _prefix, _field, _val) \ 1661 SET_BITS((_var), \ 1662 _prefix##_##_field##_INDEX, \ 1663 _prefix##_##_field##_WIDTH, (_val)) 1664 1665 #define XP_IOREAD(_pdata, _reg) \ 1666 bus_read_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET) 1667 1668 #define XP_IOREAD_BITS(_pdata, _reg, _field) \ 1669 GET_BITS(XP_IOREAD((_pdata), (_reg)), \ 1670 _reg##_##_field##_INDEX, \ 1671 _reg##_##_field##_WIDTH) 1672 1673 #define XP_IOWRITE(_pdata, _reg, _val) \ 1674 bus_write_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET, \ 1675 (_val)) 1676 1677 #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1678 do { \ 1679 uint32_t reg_val = XP_IOREAD((_pdata), (_reg)); \ 1680 SET_BITS(reg_val, \ 1681 _reg##_##_field##_INDEX, \ 1682 _reg##_##_field##_WIDTH, (_val)); \ 1683 XP_IOWRITE((_pdata), (_reg), reg_val); \ 1684 } while (0) 1685 1686 /* Macros for building, reading or writing register values or bits 1687 * within the register values of I2C Control registers. 1688 */ 1689 #define XI2C_GET_BITS(_var, _prefix, _field) \ 1690 GET_BITS((_var), \ 1691 _prefix##_##_field##_INDEX, \ 1692 _prefix##_##_field##_WIDTH) 1693 1694 #define XI2C_SET_BITS(_var, _prefix, _field, _val) \ 1695 SET_BITS((_var), \ 1696 _prefix##_##_field##_INDEX, \ 1697 _prefix##_##_field##_WIDTH, (_val)) 1698 1699 #define XI2C_IOREAD(_pdata, _reg) \ 1700 bus_read_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET) 1701 1702 #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \ 1703 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \ 1704 _reg##_##_field##_INDEX, \ 1705 _reg##_##_field##_WIDTH) 1706 1707 #define XI2C_IOWRITE(_pdata, _reg, _val) \ 1708 bus_write_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET, \ 1709 (_val)) 1710 1711 #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \ 1712 do { \ 1713 uint32_t reg_val = XI2C_IOREAD((_pdata), (_reg)); \ 1714 SET_BITS(reg_val, \ 1715 _reg##_##_field##_INDEX, \ 1716 _reg##_##_field##_WIDTH, (_val)); \ 1717 XI2C_IOWRITE((_pdata), (_reg), reg_val); \ 1718 } while (0) 1719 1720 /* Macros for building, reading or writing register values or bits 1721 * using MDIO. Different from above because of the use of standardized 1722 * Linux include values. No shifting is performed with the bit 1723 * operations, everything works on mask values. 1724 */ 1725 #define XMDIO_READ(_pdata, _mmd, _reg) \ 1726 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \ 1727 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff))) 1728 1729 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \ 1730 (XMDIO_READ((_pdata), _mmd, _reg) & _mask) 1731 1732 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \ 1733 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \ 1734 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val))) 1735 1736 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \ 1737 do { \ 1738 uint32_t mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \ 1739 mmd_val &= ~_mask; \ 1740 mmd_val |= (_val); \ 1741 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \ 1742 } while (0) 1743 1744 #endif 1745