1 /*- 2 * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 * $FreeBSD$ 37 */ 38 39 /* 40 * Defintions for the Atheros Wireless LAN controller driver. 41 */ 42 #ifndef _DEV_ATH_ATHVAR_H 43 #define _DEV_ATH_ATHVAR_H 44 45 #include <sys/taskqueue.h> 46 47 #include <contrib/dev/ath/ah.h> 48 #include <dev/ath/if_athioctl.h> 49 50 #define ATH_TIMEOUT 1000 51 52 #define ATH_RXBUF 40 /* number of RX buffers */ 53 #define ATH_TXBUF 60 /* number of TX buffers */ 54 #define ATH_TXDESC 8 /* number of descriptors per buffer */ 55 56 /* driver-specific node */ 57 struct ath_node { 58 struct ieee80211_node st_node; /* base class */ 59 u_int an_tx_ok; /* tx ok pkt */ 60 u_int an_tx_err; /* tx !ok pkt */ 61 u_int an_tx_retr; /* tx retry count */ 62 int an_tx_upper; /* tx upper rate req cnt */ 63 u_int an_tx_antenna; /* antenna for last good frame */ 64 }; 65 66 struct ath_buf { 67 TAILQ_ENTRY(ath_buf) bf_list; 68 int bf_nseg; 69 bus_dmamap_t bf_dmamap; /* DMA map of the buffer */ 70 struct ath_desc *bf_desc; /* virtual addr of desc */ 71 bus_addr_t bf_daddr; /* physical addr of desc */ 72 struct mbuf *bf_m; /* mbuf for buf */ 73 struct ieee80211_node *bf_node; /* pointer to the node */ 74 bus_size_t bf_mapsize; 75 #define ATH_MAX_SCATTER 64 76 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 77 }; 78 79 struct ath_softc { 80 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 81 int (*sc_newstate)(struct ieee80211com *, 82 enum ieee80211_state, int); 83 device_t sc_dev; 84 bus_space_tag_t sc_st; /* bus space tag */ 85 bus_space_handle_t sc_sh; /* bus space handle */ 86 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 87 struct mtx sc_mtx; /* master lock (recursive) */ 88 struct ath_hal *sc_ah; /* Atheros HAL */ 89 unsigned int sc_invalid : 1,/* disable hardware accesses */ 90 sc_have11g : 1,/* have 11g support */ 91 sc_doani : 1,/* dynamic noise immunity */ 92 sc_probing : 1;/* probing AP on beacon miss */ 93 /* rate tables */ 94 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 95 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 96 enum ieee80211_phymode sc_curmode; /* current phy mode */ 97 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 98 HAL_INT sc_imask; /* interrupt mask copy */ 99 100 struct ath_desc *sc_desc; /* TX/RX descriptors */ 101 bus_dma_segment_t sc_dseg; 102 bus_dmamap_t sc_ddmamap; /* DMA map for descriptors */ 103 bus_addr_t sc_desc_paddr; /* physical addr of sc_desc */ 104 bus_addr_t sc_desc_len; /* size of sc_desc */ 105 106 struct task sc_fataltask; /* fatal int processing */ 107 struct task sc_rxorntask; /* rxorn int processing */ 108 109 TAILQ_HEAD(, ath_buf) sc_rxbuf; /* receive buffer */ 110 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 111 struct task sc_rxtask; /* rx int processing */ 112 113 u_int sc_txhalq; /* HAL q for outgoing frames */ 114 u_int32_t *sc_txlink; /* link ptr in last TX desc */ 115 int sc_tx_timer; /* transmit timeout */ 116 TAILQ_HEAD(, ath_buf) sc_txbuf; /* transmit buffer */ 117 struct mtx sc_txbuflock; /* txbuf lock */ 118 TAILQ_HEAD(, ath_buf) sc_txq; /* transmitting queue */ 119 struct mtx sc_txqlock; /* lock on txq and txlink */ 120 struct task sc_txtask; /* tx int processing */ 121 122 u_int sc_bhalq; /* HAL q for outgoing beacons */ 123 struct ath_buf *sc_bcbuf; /* beacon buffer */ 124 struct ath_buf *sc_bufptr; /* allocated buffer ptr */ 125 struct task sc_swbatask; /* swba int processing */ 126 struct task sc_bmisstask; /* bmiss int processing */ 127 128 struct callout sc_cal_ch; /* callout handle for cals */ 129 struct callout sc_scan_ch; /* callout handle for scan */ 130 struct ath_stats sc_stats; /* interface statistics */ 131 }; 132 133 int ath_attach(u_int16_t, struct ath_softc *); 134 int ath_detach(struct ath_softc *); 135 void ath_resume(struct ath_softc *); 136 void ath_suspend(struct ath_softc *); 137 void ath_shutdown(struct ath_softc *); 138 void ath_intr(void *); 139 140 /* 141 * HAL definitions to comply with local coding convention. 142 */ 143 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 144 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 145 #define ath_hal_getratetable(_ah, _mode) \ 146 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 147 #define ath_hal_getregdomain(_ah) \ 148 ((*(_ah)->ah_getRegDomain)((_ah))) 149 #define ath_hal_getcountrycode(_ah) (_ah)->ah_countryCode 150 #define ath_hal_getmac(_ah, _mac) \ 151 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 152 #define ath_hal_detach(_ah) \ 153 ((*(_ah)->ah_detach)((_ah))) 154 #define ath_hal_intrset(_ah, _mask) \ 155 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 156 #define ath_hal_intrget(_ah) \ 157 ((*(_ah)->ah_getInterrupts)((_ah))) 158 #define ath_hal_intrpend(_ah) \ 159 ((*(_ah)->ah_isInterruptPending)((_ah))) 160 #define ath_hal_getisr(_ah, _pmask) \ 161 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 162 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 163 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 164 #define ath_hal_setpower(_ah, _mode, _sleepduration) \ 165 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration))) 166 #define ath_hal_keyreset(_ah, _ix) \ 167 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 168 #define ath_hal_keyset(_ah, _ix, _pk) \ 169 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE)) 170 #define ath_hal_keyisvalid(_ah, _ix) \ 171 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 172 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 173 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 174 #define ath_hal_getrxfilter(_ah) \ 175 ((*(_ah)->ah_getRxFilter)((_ah))) 176 #define ath_hal_setrxfilter(_ah, _filter) \ 177 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 178 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 179 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 180 #define ath_hal_waitforbeacon(_ah, _bf) \ 181 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 182 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 183 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 184 #define ath_hal_gettsf32(_ah) \ 185 ((*(_ah)->ah_getTsf32)((_ah))) 186 #define ath_hal_gettsf64(_ah) \ 187 ((*(_ah)->ah_getTsf64)((_ah))) 188 #define ath_hal_resettsf(_ah) \ 189 ((*(_ah)->ah_resetTsf)((_ah))) 190 #define ath_hal_rxena(_ah) \ 191 ((*(_ah)->ah_enableReceive)((_ah))) 192 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 193 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 194 #define ath_hal_gettxbuf(_ah, _q) \ 195 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 196 #define ath_hal_getrxbuf(_ah) \ 197 ((*(_ah)->ah_getRxDP)((_ah))) 198 #define ath_hal_txstart(_ah, _q) \ 199 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 200 #define ath_hal_setchannel(_ah, _chan) \ 201 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 202 #define ath_hal_calibrate(_ah, _chan) \ 203 ((*(_ah)->ah_perCalibration)((_ah), (_chan))) 204 #define ath_hal_setledstate(_ah, _state) \ 205 ((*(_ah)->ah_setLedState)((_ah), (_state))) 206 #define ath_hal_beaconinit(_ah, _opmode, _nextb, _bperiod) \ 207 ((*(_ah)->ah_beaconInit)((_ah), (_opmode), (_nextb), (_bperiod))) 208 #define ath_hal_beaconreset(_ah) \ 209 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 210 #define ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \ 211 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \ 212 (_dc), (_cc))) 213 #define ath_hal_setassocid(_ah, _bss, _associd) \ 214 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0)) 215 #define ath_hal_setopmode(_ah, _opmode) \ 216 ((*(_ah)->ah_setPCUConfig)((_ah), (_opmode))) 217 #define ath_hal_stoptxdma(_ah, _qnum) \ 218 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 219 #define ath_hal_stoppcurecv(_ah) \ 220 ((*(_ah)->ah_stopPcuReceive)((_ah))) 221 #define ath_hal_startpcurecv(_ah) \ 222 ((*(_ah)->ah_startPcuReceive)((_ah))) 223 #define ath_hal_stopdmarecv(_ah) \ 224 ((*(_ah)->ah_stopDmaReceive)((_ah))) 225 #define ath_hal_dumpstate(_ah) \ 226 ((*(_ah)->ah_dumpState)((_ah))) 227 #define ath_hal_dumpeeprom(_ah) \ 228 ((*(_ah)->ah_dumpEeprom)((_ah))) 229 #define ath_hal_dumprfgain(_ah) \ 230 ((*(_ah)->ah_dumpRfGain)((_ah))) 231 #define ath_hal_dumpani(_ah) \ 232 ((*(_ah)->ah_dumpAni)((_ah))) 233 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 234 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 235 #define ath_hal_resettxqueue(_ah, _q) \ 236 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 237 #define ath_hal_releasetxqueue(_ah, _q) \ 238 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 239 #define ath_hal_hasveol(_ah) \ 240 ((*(_ah)->ah_hasVEOL)((_ah))) 241 #define ath_hal_getrfgain(_ah) \ 242 ((*(_ah)->ah_getRfGain)((_ah))) 243 #define ath_hal_rxmonitor(_ah) \ 244 ((*(_ah)->ah_rxMonitor)((_ah))) 245 246 #define ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \ 247 _rate, _antmode) \ 248 ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 249 (_flen), (_hlen), (_rate), (_antmode))) 250 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 251 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 252 #define ath_hal_rxprocdesc(_ah, _ds) \ 253 ((*(_ah)->ah_procRxDesc)((_ah), (_ds))) 254 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 255 _txr0, _txtr0, _keyix, _ant, _flags, \ 256 _rtsrate, _rtsdura) \ 257 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 258 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 259 (_flags), (_rtsrate), (_rtsdura))) 260 #define ath_hal_setupxtxdesc(_ah, _ds, _short, \ 261 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 262 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \ 263 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 264 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \ 265 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last))) 266 #define ath_hal_txprocdesc(_ah, _ds) \ 267 ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) 268 269 #endif /* _DEV_ATH_ATHVAR_H */ 270