1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35 #ifndef _DEV_ATH_ATHVAR_H 36 #define _DEV_ATH_ATHVAR_H 37 38 #include <machine/atomic.h> 39 40 #include <dev/ath/ath_hal/ah.h> 41 #include <dev/ath/ath_hal/ah_desc.h> 42 #include <net80211/ieee80211_radiotap.h> 43 #include <dev/ath/if_athioctl.h> 44 #include <dev/ath/if_athrate.h> 45 #ifdef ATH_DEBUG_ALQ 46 #include <dev/ath/if_ath_alq.h> 47 #endif 48 49 #define ATH_TIMEOUT 1000 50 51 /* 52 * There is a separate TX ath_buf pool for management frames. 53 * This ensures that management frames such as probe responses 54 * and BAR frames can be transmitted during periods of high 55 * TX activity. 56 */ 57 #define ATH_MGMT_TXBUF 32 58 59 /* 60 * 802.11n requires more TX and RX buffers to do AMPDU. 61 */ 62 #ifdef ATH_ENABLE_11N 63 #define ATH_TXBUF 512 64 #define ATH_RXBUF 512 65 #endif 66 67 #ifndef ATH_RXBUF 68 #define ATH_RXBUF 40 /* number of RX buffers */ 69 #endif 70 #ifndef ATH_TXBUF 71 #define ATH_TXBUF 200 /* number of TX buffers */ 72 #endif 73 #define ATH_BCBUF 4 /* number of beacon buffers */ 74 75 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 76 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 77 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 78 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 79 80 #define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 81 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 82 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 83 84 /* 85 * The key cache is used for h/w cipher state and also for 86 * tracking station state such as the current tx antenna. 87 * We also setup a mapping table between key cache slot indices 88 * and station state to short-circuit node lookups on rx. 89 * Different parts have different size key caches. We handle 90 * up to ATH_KEYMAX entries (could dynamically allocate state). 91 */ 92 #define ATH_KEYMAX 128 /* max key cache size we handle */ 93 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 94 95 struct taskqueue; 96 struct kthread; 97 struct ath_buf; 98 99 #define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 100 101 /* 102 * Per-TID state 103 * 104 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 105 */ 106 struct ath_tid { 107 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 108 struct ath_node *an; /* pointer to parent */ 109 int tid; /* tid */ 110 int ac; /* which AC gets this trafic */ 111 int hwq_depth; /* how many buffers are on HW */ 112 u_int axq_depth; /* SW queue depth */ 113 114 struct { 115 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 116 u_int axq_depth; /* SW queue depth */ 117 } filtq; 118 119 /* 120 * Entry on the ath_txq; when there's traffic 121 * to send 122 */ 123 TAILQ_ENTRY(ath_tid) axq_qelem; 124 int sched; 125 int paused; /* >0 if the TID has been paused */ 126 127 /* 128 * These are flags - perhaps later collapse 129 * down to a single uint32_t ? 130 */ 131 int addba_tx_pending; /* TX ADDBA pending */ 132 int bar_wait; /* waiting for BAR */ 133 int bar_tx; /* BAR TXed */ 134 int isfiltered; /* is this node currently filtered */ 135 136 /* 137 * Is the TID being cleaned up after a transition 138 * from aggregation to non-aggregation? 139 * When this is set to 1, this TID will be paused 140 * and no further traffic will be queued until all 141 * the hardware packets pending for this TID have been 142 * TXed/completed; at which point (non-aggregation) 143 * traffic will resume being TXed. 144 */ 145 int cleanup_inprogress; 146 /* 147 * How many hardware-queued packets are 148 * waiting to be cleaned up. 149 * This is only valid if cleanup_inprogress is 1. 150 */ 151 int incomp; 152 153 /* 154 * The following implements a ring representing 155 * the frames in the current BAW. 156 * To avoid copying the array content each time 157 * the BAW is moved, the baw_head/baw_tail point 158 * to the current BAW begin/end; when the BAW is 159 * shifted the head/tail of the array are also 160 * appropriately shifted. 161 */ 162 /* active tx buffers, beginning at current BAW */ 163 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 164 /* where the baw head is in the array */ 165 int baw_head; 166 /* where the BAW tail is in the array */ 167 int baw_tail; 168 }; 169 170 /* driver-specific node state */ 171 struct ath_node { 172 struct ieee80211_node an_node; /* base class */ 173 u_int8_t an_mgmtrix; /* min h/w rate index */ 174 u_int8_t an_mcastrix; /* mcast h/w rate index */ 175 uint32_t an_is_powersave; /* node is sleeping */ 176 uint32_t an_stack_psq; /* net80211 psq isn't empty */ 177 uint32_t an_tim_set; /* TIM has been set */ 178 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 179 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 180 char an_name[32]; /* eg "wlan0_a1" */ 181 struct mtx an_mtx; /* protecting the rate control state */ 182 uint32_t an_swq_depth; /* how many SWQ packets for this 183 node */ 184 int clrdmask; /* has clrdmask been set */ 185 uint32_t an_leak_count; /* How many frames to leak during pause */ 186 /* variable-length rate control state follows */ 187 }; 188 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 189 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 190 191 #define ATH_RSSI_LPF_LEN 10 192 #define ATH_RSSI_DUMMY_MARKER 0x127 193 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 194 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 195 #define ATH_LPF_RSSI(x, y, len) \ 196 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 197 #define ATH_RSSI_LPF(x, y) do { \ 198 if ((y) >= -20) \ 199 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 200 } while (0) 201 #define ATH_EP_RND(x,mul) \ 202 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 203 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 204 205 typedef enum { 206 ATH_BUFTYPE_NORMAL = 0, 207 ATH_BUFTYPE_MGMT = 1, 208 } ath_buf_type_t; 209 210 struct ath_buf { 211 TAILQ_ENTRY(ath_buf) bf_list; 212 struct ath_buf * bf_next; /* next buffer in the aggregate */ 213 int bf_nseg; 214 HAL_STATUS bf_rxstatus; 215 uint16_t bf_flags; /* status flags (below) */ 216 uint16_t bf_descid; /* 16 bit descriptor ID */ 217 struct ath_desc *bf_desc; /* virtual addr of desc */ 218 struct ath_desc_status bf_status; /* tx/rx status */ 219 bus_addr_t bf_daddr; /* physical addr of desc */ 220 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 221 struct mbuf *bf_m; /* mbuf for buf */ 222 struct ieee80211_node *bf_node; /* pointer to the node */ 223 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 224 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 225 bus_size_t bf_mapsize; 226 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 227 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 228 229 /* Completion function to call on TX complete (fail or not) */ 230 /* 231 * "fail" here is set to 1 if the queue entries were removed 232 * through a call to ath_tx_draintxq(). 233 */ 234 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 235 236 /* This state is kept to support software retries and aggregation */ 237 struct { 238 uint16_t bfs_seqno; /* sequence number of this packet */ 239 uint16_t bfs_ndelim; /* number of delims for padding */ 240 241 uint8_t bfs_retries; /* retry count */ 242 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 243 uint8_t bfs_nframes; /* number of frames in aggregate */ 244 uint8_t bfs_pri; /* packet AC priority */ 245 uint8_t bfs_tx_queue; /* destination hardware TX queue */ 246 247 u_int32_t bfs_aggr:1, /* part of aggregate? */ 248 bfs_aggrburst:1, /* part of aggregate burst? */ 249 bfs_isretried:1, /* retried frame? */ 250 bfs_dobaw:1, /* actually check against BAW? */ 251 bfs_addedbaw:1, /* has been added to the BAW */ 252 bfs_shpream:1, /* use short preamble */ 253 bfs_istxfrag:1, /* is fragmented */ 254 bfs_ismrr:1, /* do multi-rate TX retry */ 255 bfs_doprot:1, /* do RTS/CTS based protection */ 256 bfs_doratelookup:1; /* do rate lookup before each TX */ 257 258 /* 259 * These fields are passed into the 260 * descriptor setup functions. 261 */ 262 263 /* Make this an 8 bit value? */ 264 HAL_PKT_TYPE bfs_atype; /* packet type */ 265 266 uint32_t bfs_pktlen; /* length of this packet */ 267 268 uint16_t bfs_hdrlen; /* length of this packet header */ 269 uint16_t bfs_al; /* length of aggregate */ 270 271 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 272 uint8_t bfs_txrate0; /* first TX rate */ 273 uint8_t bfs_try0; /* first try count */ 274 275 uint16_t bfs_txpower; /* tx power */ 276 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 277 uint8_t bfs_ctsrate; /* CTS rate */ 278 279 /* 16 bit? */ 280 int32_t bfs_keyix; /* crypto key index */ 281 int32_t bfs_txantenna; /* TX antenna config */ 282 283 /* Make this an 8 bit value? */ 284 enum ieee80211_protmode bfs_protmode; 285 286 /* 16 bit? */ 287 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 288 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 289 } bf_state; 290 }; 291 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 292 293 #define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 294 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 295 #define ATH_BUF_FIFOEND 0x00000004 296 #define ATH_BUF_FIFOPTR 0x00000008 297 298 #define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT) 299 300 /* 301 * DMA state for tx/rx descriptors. 302 */ 303 struct ath_descdma { 304 const char* dd_name; 305 struct ath_desc *dd_desc; /* descriptors */ 306 int dd_descsize; /* size of single descriptor */ 307 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 308 bus_size_t dd_desc_len; /* size of dd_desc */ 309 bus_dma_segment_t dd_dseg; 310 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 311 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 312 struct ath_buf *dd_bufptr; /* associated buffers */ 313 }; 314 315 /* 316 * Data transmit queue state. One of these exists for each 317 * hardware transmit queue. Packets sent to us from above 318 * are assigned to queues based on their priority. Not all 319 * devices support a complete set of hardware transmit queues. 320 * For those devices the array sc_ac2q will map multiple 321 * priorities to fewer hardware queues (typically all to one 322 * hardware queue). 323 */ 324 struct ath_txq { 325 struct ath_softc *axq_softc; /* Needed for scheduling */ 326 u_int axq_qnum; /* hardware q number */ 327 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 328 u_int axq_ac; /* WME AC */ 329 u_int axq_flags; 330 //#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 331 #define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */ 332 u_int axq_depth; /* queue depth (stat only) */ 333 u_int axq_aggr_depth; /* how many aggregates are queued */ 334 u_int axq_intrcnt; /* interrupt count */ 335 u_int32_t *axq_link; /* link ptr in last TX desc */ 336 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 337 struct mtx axq_lock; /* lock on q and link */ 338 339 /* 340 * This is the FIFO staging buffer when doing EDMA. 341 * 342 * For legacy chips, we just push the head pointer to 343 * the hardware and we ignore this list. 344 * 345 * For EDMA, the staging buffer is treated as normal; 346 * when it's time to push a list of frames to the hardware 347 * we move that list here and we stamp buffers with 348 * flags to identify the beginning/end of that particular 349 * FIFO entry. 350 */ 351 struct { 352 TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q; 353 u_int axq_depth; 354 } fifo; 355 u_int axq_fifo_depth; /* depth of FIFO frames */ 356 357 /* 358 * XXX the holdingbf field is protected by the TXBUF lock 359 * for now, NOT the TXQ lock. 360 * 361 * Architecturally, it would likely be better to move 362 * the holdingbf field to a separate array in ath_softc 363 * just to highlight that it's not protected by the normal 364 * TX path lock. 365 */ 366 struct ath_buf *axq_holdingbf; /* holding TX buffer */ 367 char axq_name[12]; /* e.g. "ath0_txq4" */ 368 369 /* Per-TID traffic queue for software -> hardware TX */ 370 /* 371 * This is protected by the general TX path lock, not (for now) 372 * by the TXQ lock. 373 */ 374 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 375 }; 376 377 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 378 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 379 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 380 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 381 } while (0) 382 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 383 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 384 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 385 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 386 #define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \ 387 MA_NOTOWNED) 388 389 390 #define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 391 #define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 392 #define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 393 #define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 394 MA_NOTOWNED) 395 396 /* 397 * These are for the hardware queue. 398 */ 399 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 400 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 401 (_tq)->axq_depth++; \ 402 } while (0) 403 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 404 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 405 (_tq)->axq_depth++; \ 406 } while (0) 407 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 408 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 409 (_tq)->axq_depth--; \ 410 } while (0) 411 #define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 412 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 413 414 /* 415 * These are for the TID software queue. 416 */ 417 #define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 418 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 419 (_tq)->axq_depth++; \ 420 (_tq)->an->an_swq_depth++; \ 421 } while (0) 422 #define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 423 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 424 (_tq)->axq_depth++; \ 425 (_tq)->an->an_swq_depth++; \ 426 } while (0) 427 #define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 428 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 429 (_tq)->axq_depth--; \ 430 (_tq)->an->an_swq_depth--; \ 431 } while (0) 432 #define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 433 #define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 434 435 /* 436 * These are for the TID filtered frame queue 437 */ 438 #define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 439 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 440 (_tq)->axq_depth++; \ 441 (_tq)->an->an_swq_depth++; \ 442 } while (0) 443 #define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 444 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 445 (_tq)->axq_depth++; \ 446 (_tq)->an->an_swq_depth++; \ 447 } while (0) 448 #define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 449 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 450 (_tq)->axq_depth--; \ 451 (_tq)->an->an_swq_depth--; \ 452 } while (0) 453 #define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 454 #define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 455 456 struct ath_vap { 457 struct ieee80211vap av_vap; /* base class */ 458 int av_bslot; /* beacon slot index */ 459 struct ath_buf *av_bcbuf; /* beacon buffer */ 460 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 461 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 462 463 void (*av_recv_mgmt)(struct ieee80211_node *, 464 struct mbuf *, int, int, int); 465 int (*av_newstate)(struct ieee80211vap *, 466 enum ieee80211_state, int); 467 void (*av_bmiss)(struct ieee80211vap *); 468 void (*av_node_ps)(struct ieee80211_node *, int); 469 int (*av_set_tim)(struct ieee80211_node *, int); 470 void (*av_recv_pspoll)(struct ieee80211_node *, 471 struct mbuf *); 472 }; 473 #define ATH_VAP(vap) ((struct ath_vap *)(vap)) 474 475 struct taskqueue; 476 struct ath_tx99; 477 478 /* 479 * Whether to reset the TX/RX queue with or without 480 * a queue flush. 481 */ 482 typedef enum { 483 ATH_RESET_DEFAULT = 0, 484 ATH_RESET_NOLOSS = 1, 485 ATH_RESET_FULL = 2, 486 } ATH_RESET_TYPE; 487 488 struct ath_rx_methods { 489 void (*recv_sched_queue)(struct ath_softc *sc, 490 HAL_RX_QUEUE q, int dosched); 491 void (*recv_sched)(struct ath_softc *sc, int dosched); 492 void (*recv_stop)(struct ath_softc *sc, int dodelay); 493 int (*recv_start)(struct ath_softc *sc); 494 void (*recv_flush)(struct ath_softc *sc); 495 void (*recv_tasklet)(void *arg, int npending); 496 int (*recv_rxbuf_init)(struct ath_softc *sc, 497 struct ath_buf *bf); 498 int (*recv_setup)(struct ath_softc *sc); 499 int (*recv_teardown)(struct ath_softc *sc); 500 }; 501 502 /* 503 * Represent the current state of the RX FIFO. 504 */ 505 struct ath_rx_edma { 506 struct ath_buf **m_fifo; 507 int m_fifolen; 508 int m_fifo_head; 509 int m_fifo_tail; 510 int m_fifo_depth; 511 struct mbuf *m_rxpending; 512 }; 513 514 struct ath_tx_edma_fifo { 515 struct ath_buf **m_fifo; 516 int m_fifolen; 517 int m_fifo_head; 518 int m_fifo_tail; 519 int m_fifo_depth; 520 }; 521 522 struct ath_tx_methods { 523 int (*xmit_setup)(struct ath_softc *sc); 524 int (*xmit_teardown)(struct ath_softc *sc); 525 void (*xmit_attach_comp_func)(struct ath_softc *sc); 526 527 void (*xmit_dma_restart)(struct ath_softc *sc, 528 struct ath_txq *txq); 529 void (*xmit_handoff)(struct ath_softc *sc, 530 struct ath_txq *txq, struct ath_buf *bf); 531 void (*xmit_drain)(struct ath_softc *sc, 532 ATH_RESET_TYPE reset_type); 533 }; 534 535 struct ath_softc { 536 struct ifnet *sc_ifp; /* interface common */ 537 struct ath_stats sc_stats; /* interface statistics */ 538 struct ath_tx_aggr_stats sc_aggr_stats; 539 struct ath_intr_stats sc_intr_stats; 540 uint64_t sc_debug; 541 uint64_t sc_ktrdebug; 542 int sc_nvaps; /* # vaps */ 543 int sc_nstavaps; /* # station vaps */ 544 int sc_nmeshvaps; /* # mbss vaps */ 545 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 546 u_int8_t sc_nbssid0; /* # vap's using base mac */ 547 uint32_t sc_bssidmask; /* bssid mask */ 548 549 struct ath_rx_methods sc_rx; 550 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 551 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */ 552 struct ath_tx_methods sc_tx; 553 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 554 555 /* 556 * This is (currently) protected by the TX queue lock; 557 * it should migrate to a separate lock later 558 * so as to minimise contention. 559 */ 560 ath_bufhead sc_txbuf_list; 561 562 int sc_rx_statuslen; 563 int sc_tx_desclen; 564 int sc_tx_statuslen; 565 int sc_tx_nmaps; /* Number of TX maps */ 566 int sc_edma_bufsize; 567 568 void (*sc_node_cleanup)(struct ieee80211_node *); 569 void (*sc_node_free)(struct ieee80211_node *); 570 device_t sc_dev; 571 HAL_BUS_TAG sc_st; /* bus space tag */ 572 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 573 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 574 struct mtx sc_mtx; /* master lock (recursive) */ 575 struct mtx sc_pcu_mtx; /* PCU access mutex */ 576 char sc_pcu_mtx_name[32]; 577 struct mtx sc_rx_mtx; /* RX access mutex */ 578 char sc_rx_mtx_name[32]; 579 struct mtx sc_tx_mtx; /* TX handling/comp mutex */ 580 char sc_tx_mtx_name[32]; 581 struct mtx sc_tx_ic_mtx; /* TX queue mutex */ 582 char sc_tx_ic_mtx_name[32]; 583 struct taskqueue *sc_tq; /* private task queue */ 584 struct ath_hal *sc_ah; /* Atheros HAL */ 585 struct ath_ratectrl *sc_rc; /* tx rate control support */ 586 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 587 void (*sc_setdefantenna)(struct ath_softc *, u_int); 588 589 /* 590 * First set of flags. 591 */ 592 uint32_t sc_invalid : 1,/* disable hardware accesses */ 593 sc_mrretry : 1,/* multi-rate retry support */ 594 sc_mrrprot : 1,/* MRR + protection support */ 595 sc_softled : 1,/* enable LED gpio status */ 596 sc_hardled : 1,/* enable MAC LED status */ 597 sc_splitmic : 1,/* split TKIP MIC keys */ 598 sc_needmib : 1,/* enable MIB stats intr */ 599 sc_diversity: 1,/* enable rx diversity */ 600 sc_hasveol : 1,/* tx VEOL support */ 601 sc_ledstate : 1,/* LED on/off state */ 602 sc_blinking : 1,/* LED blink operation active */ 603 sc_mcastkey : 1,/* mcast key cache search */ 604 sc_scanning : 1,/* scanning active */ 605 sc_syncbeacon:1,/* sync/resync beacon timers */ 606 sc_hasclrkey: 1,/* CLR key supported */ 607 sc_xchanmode: 1,/* extended channel mode */ 608 sc_outdoor : 1,/* outdoor operation */ 609 sc_dturbo : 1,/* dynamic turbo in use */ 610 sc_hasbmask : 1,/* bssid mask support */ 611 sc_hasbmatch: 1,/* bssid match disable support*/ 612 sc_hastsfadd: 1,/* tsf adjust support */ 613 sc_beacons : 1,/* beacons running */ 614 sc_swbmiss : 1,/* sta mode using sw bmiss */ 615 sc_stagbeacons:1,/* use staggered beacons */ 616 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 617 sc_resume_up: 1,/* on resume, start all vaps */ 618 sc_tdma : 1,/* TDMA in use */ 619 sc_setcca : 1,/* set/clr CCA with TDMA */ 620 sc_resetcal : 1,/* reset cal state next trip */ 621 sc_rxslink : 1,/* do self-linked final descriptor */ 622 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 623 sc_isedma : 1;/* supports EDMA */ 624 625 /* 626 * Second set of flags. 627 */ 628 u_int32_t sc_use_ent : 1, 629 sc_rx_stbc : 1, 630 sc_tx_stbc : 1; 631 632 633 int sc_cabq_enable; /* Enable cabq transmission */ 634 635 /* 636 * Enterprise mode configuration for AR9380 and later chipsets. 637 */ 638 uint32_t sc_ent_cfg; 639 640 uint32_t sc_eerd; /* regdomain from EEPROM */ 641 uint32_t sc_eecc; /* country code from EEPROM */ 642 /* rate tables */ 643 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 644 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 645 enum ieee80211_phymode sc_curmode; /* current phy mode */ 646 HAL_OPMODE sc_opmode; /* current operating mode */ 647 u_int16_t sc_curtxpow; /* current tx power limit */ 648 u_int16_t sc_curaid; /* current association id */ 649 struct ieee80211_channel *sc_curchan; /* current installed channel */ 650 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 651 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 652 struct { 653 u_int8_t ieeerate; /* IEEE rate */ 654 u_int8_t rxflags; /* radiotap rx flags */ 655 u_int8_t txflags; /* radiotap tx flags */ 656 u_int16_t ledon; /* softled on time */ 657 u_int16_t ledoff; /* softled off time */ 658 } sc_hwmap[32]; /* h/w rate ix mappings */ 659 u_int8_t sc_protrix; /* protection rate index */ 660 u_int8_t sc_lastdatarix; /* last data frame rate index */ 661 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 662 u_int sc_fftxqmin; /* min frames before staging */ 663 u_int sc_fftxqmax; /* max frames before drop */ 664 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 665 666 HAL_INT sc_imask; /* interrupt mask copy */ 667 668 /* 669 * These are modified in the interrupt handler as well as 670 * the task queues and other contexts. Thus these must be 671 * protected by a mutex, or they could clash. 672 * 673 * For now, access to these is behind the ATH_LOCK, 674 * just to save time. 675 */ 676 uint32_t sc_txq_active; /* bitmap of active TXQs */ 677 uint32_t sc_kickpcu; /* whether to kick the PCU */ 678 uint32_t sc_rxproc_cnt; /* In RX processing */ 679 uint32_t sc_txproc_cnt; /* In TX processing */ 680 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 681 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 682 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 683 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 684 685 u_int sc_keymax; /* size of key cache */ 686 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 687 688 /* 689 * Software based LED blinking 690 */ 691 u_int sc_ledpin; /* GPIO pin for driving LED */ 692 u_int sc_ledon; /* pin setting for LED on */ 693 u_int sc_ledidle; /* idle polling interval */ 694 int sc_ledevent; /* time of last LED event */ 695 u_int8_t sc_txrix; /* current tx rate for LED */ 696 u_int16_t sc_ledoff; /* off time for current blink */ 697 struct callout sc_ledtimer; /* led off timer */ 698 699 /* 700 * Hardware based LED blinking 701 */ 702 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 703 int sc_led_net_pin; /* MAC network LED GPIO pin */ 704 705 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 706 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 707 708 struct ath_descdma sc_rxdma; /* RX descriptors */ 709 ath_bufhead sc_rxbuf; /* receive buffer */ 710 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 711 struct task sc_rxtask; /* rx int processing */ 712 u_int8_t sc_defant; /* current default antenna */ 713 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 714 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 715 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 716 struct ath_rx_radiotap_header sc_rx_th; 717 int sc_rx_th_len; 718 u_int sc_monpass; /* frames to pass in mon.mode */ 719 720 struct ath_descdma sc_txdma; /* TX descriptors */ 721 uint16_t sc_txbuf_descid; 722 ath_bufhead sc_txbuf; /* transmit buffer */ 723 int sc_txbuf_cnt; /* how many buffers avail */ 724 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 725 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 726 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 727 struct mtx sc_txbuflock; /* txbuf lock */ 728 char sc_txname[12]; /* e.g. "ath0_buf" */ 729 u_int sc_txqsetup; /* h/w queues setup */ 730 u_int sc_txintrperiod;/* tx interrupt batching */ 731 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 732 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 733 struct task sc_txtask; /* tx int processing */ 734 struct task sc_txqtask; /* tx proc processing */ 735 struct task sc_txpkttask; /* tx frame processing */ 736 737 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 738 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 739 char sc_txcompname[12]; /* eg ath0_txcomp */ 740 741 int sc_wd_timer; /* count down for wd timer */ 742 struct callout sc_wd_ch; /* tx watchdog timer */ 743 struct ath_tx_radiotap_header sc_tx_th; 744 int sc_tx_th_len; 745 746 struct ath_descdma sc_bdma; /* beacon descriptors */ 747 ath_bufhead sc_bbuf; /* beacon buffers */ 748 u_int sc_bhalq; /* HAL q for outgoing beacons */ 749 u_int sc_bmisscount; /* missed beacon transmits */ 750 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 751 struct ath_txq *sc_cabq; /* tx q for cab frames */ 752 struct task sc_bmisstask; /* bmiss int processing */ 753 struct task sc_bstucktask; /* stuck beacon processing */ 754 struct task sc_resettask; /* interface reset task */ 755 struct task sc_fataltask; /* fatal task */ 756 enum { 757 OK, /* no change needed */ 758 UPDATE, /* update pending */ 759 COMMIT /* beacon sent, commit change */ 760 } sc_updateslot; /* slot time update fsm */ 761 int sc_slotupdate; /* slot to advance fsm */ 762 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 763 int sc_nbcnvaps; /* # vaps with beacons */ 764 765 struct callout sc_cal_ch; /* callout handle for cals */ 766 int sc_lastlongcal; /* last long cal completed */ 767 int sc_lastcalreset;/* last cal reset done */ 768 int sc_lastani; /* last ANI poll */ 769 int sc_lastshortcal; /* last short calibration */ 770 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 771 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 772 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 773 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 774 u_int sc_tdmaswba; /* TDMA SWBA counter */ 775 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 776 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 777 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 778 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 779 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 780 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 781 uint32_t sc_txchainmask; /* hardware TX chainmask */ 782 uint32_t sc_rxchainmask; /* hardware RX chainmask */ 783 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */ 784 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */ 785 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 786 int sc_aggr_limit; /* TX limit on all aggregates */ 787 int sc_delim_min_pad; /* Minimum delimiter count */ 788 789 /* Queue limits */ 790 791 /* 792 * To avoid queue starvation in congested conditions, 793 * these parameters tune the maximum number of frames 794 * queued to the data/mcastq before they're dropped. 795 * 796 * This is to prevent: 797 * + a single destination overwhelming everything, including 798 * management/multicast frames; 799 * + multicast frames overwhelming everything (when the 800 * air is sufficiently busy that cabq can't drain.) 801 * + A node in powersave shouldn't be allowed to exhaust 802 * all available mbufs; 803 * 804 * These implement: 805 * + data_minfree is the maximum number of free buffers 806 * overall to successfully allow a data frame. 807 * 808 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 809 */ 810 int sc_txq_node_maxdepth; 811 int sc_txq_data_minfree; 812 int sc_txq_mcastq_maxdepth; 813 int sc_txq_node_psq_maxdepth; 814 815 /* 816 * Aggregation twiddles 817 * 818 * hwq_limit: how busy to keep the hardware queue - don't schedule 819 * further packets to the hardware, regardless of the TID 820 * tid_hwq_lo: how low the per-TID hwq count has to be before the 821 * TID will be scheduled again 822 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 823 * stops being scheduled. 824 */ 825 int sc_hwq_limit; 826 int sc_tid_hwq_lo; 827 int sc_tid_hwq_hi; 828 829 /* DFS related state */ 830 void *sc_dfs; /* Used by an optional DFS module */ 831 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 832 struct task sc_dfstask; /* DFS processing task */ 833 834 /* Spectral related state */ 835 void *sc_spectral; 836 int sc_dospectral; 837 838 /* ALQ */ 839 #ifdef ATH_DEBUG_ALQ 840 struct if_ath_alq sc_alq; 841 #endif 842 843 /* TX AMPDU handling */ 844 int (*sc_addba_request)(struct ieee80211_node *, 845 struct ieee80211_tx_ampdu *, int, int, int); 846 int (*sc_addba_response)(struct ieee80211_node *, 847 struct ieee80211_tx_ampdu *, int, int, int); 848 void (*sc_addba_stop)(struct ieee80211_node *, 849 struct ieee80211_tx_ampdu *); 850 void (*sc_addba_response_timeout) 851 (struct ieee80211_node *, 852 struct ieee80211_tx_ampdu *); 853 void (*sc_bar_response)(struct ieee80211_node *ni, 854 struct ieee80211_tx_ampdu *tap, 855 int status); 856 }; 857 858 #define ATH_LOCK_INIT(_sc) \ 859 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 860 NULL, MTX_DEF | MTX_RECURSE) 861 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 862 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 863 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 864 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 865 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 866 867 /* 868 * The TX lock is non-reentrant and serialises the TX frame send 869 * and completion operations. 870 */ 871 #define ATH_TX_LOCK_INIT(_sc) do {\ 872 snprintf((_sc)->sc_tx_mtx_name, \ 873 sizeof((_sc)->sc_tx_mtx_name), \ 874 "%s TX lock", \ 875 device_get_nameunit((_sc)->sc_dev)); \ 876 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 877 NULL, MTX_DEF); \ 878 } while (0) 879 #define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx) 880 #define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) 881 #define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) 882 #define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 883 MA_OWNED) 884 #define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 885 MA_NOTOWNED) 886 #define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \ 887 mtx_trylock(&(_sc)->sc_tx_mtx)) 888 889 /* 890 * The IC TX lock is non-reentrant and serialises packet queuing from 891 * the upper layers. 892 */ 893 #define ATH_TX_IC_LOCK_INIT(_sc) do {\ 894 snprintf((_sc)->sc_tx_ic_mtx_name, \ 895 sizeof((_sc)->sc_tx_ic_mtx_name), \ 896 "%s IC TX lock", \ 897 device_get_nameunit((_sc)->sc_dev)); \ 898 mtx_init(&(_sc)->sc_tx_ic_mtx, (_sc)->sc_tx_ic_mtx_name, \ 899 NULL, MTX_DEF); \ 900 } while (0) 901 #define ATH_TX_IC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_ic_mtx) 902 #define ATH_TX_IC_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_ic_mtx) 903 #define ATH_TX_IC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_ic_mtx) 904 #define ATH_TX_IC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_ic_mtx, \ 905 MA_OWNED) 906 #define ATH_TX_IC_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_ic_mtx, \ 907 MA_NOTOWNED) 908 909 /* 910 * The PCU lock is non-recursive and should be treated as a spinlock. 911 * Although currently the interrupt code is run in netisr context and 912 * doesn't require this, this may change in the future. 913 * Please keep this in mind when protecting certain code paths 914 * with the PCU lock. 915 * 916 * The PCU lock is used to serialise access to the PCU so things such 917 * as TX, RX, state change (eg channel change), channel reset and updates 918 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 919 * 920 * Although the current single-thread taskqueue mechanism protects the 921 * majority of these situations by simply serialising them, there are 922 * a few others which occur at the same time. These include the TX path 923 * (which only acquires ATH_LOCK when recycling buffers to the free list), 924 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 925 */ 926 #define ATH_PCU_LOCK_INIT(_sc) do {\ 927 snprintf((_sc)->sc_pcu_mtx_name, \ 928 sizeof((_sc)->sc_pcu_mtx_name), \ 929 "%s PCU lock", \ 930 device_get_nameunit((_sc)->sc_dev)); \ 931 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 932 NULL, MTX_DEF); \ 933 } while (0) 934 #define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 935 #define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 936 #define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 937 #define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 938 MA_OWNED) 939 #define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 940 MA_NOTOWNED) 941 942 /* 943 * The RX lock is primarily a(nother) workaround to ensure that the 944 * RX FIFO/list isn't modified by various execution paths. 945 * Even though RX occurs in a single context (the ath taskqueue), the 946 * RX path can be executed via various reset/channel change paths. 947 */ 948 #define ATH_RX_LOCK_INIT(_sc) do {\ 949 snprintf((_sc)->sc_rx_mtx_name, \ 950 sizeof((_sc)->sc_rx_mtx_name), \ 951 "%s RX lock", \ 952 device_get_nameunit((_sc)->sc_dev)); \ 953 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 954 NULL, MTX_DEF); \ 955 } while (0) 956 #define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 957 #define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 958 #define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 959 #define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 960 MA_OWNED) 961 #define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 962 MA_NOTOWNED) 963 964 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 965 966 #define ATH_TXBUF_LOCK_INIT(_sc) do { \ 967 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 968 device_get_nameunit((_sc)->sc_dev)); \ 969 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 970 } while (0) 971 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 972 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 973 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 974 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 975 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 976 #define ATH_TXBUF_UNLOCK_ASSERT(_sc) \ 977 mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED) 978 979 #define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 980 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 981 "%s_buf", \ 982 device_get_nameunit((_sc)->sc_dev)); \ 983 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 984 MTX_DEF); \ 985 } while (0) 986 #define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 987 #define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 988 #define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 989 #define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 990 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 991 992 int ath_attach(u_int16_t, struct ath_softc *); 993 int ath_detach(struct ath_softc *); 994 void ath_resume(struct ath_softc *); 995 void ath_suspend(struct ath_softc *); 996 void ath_shutdown(struct ath_softc *); 997 void ath_intr(void *); 998 999 /* 1000 * HAL definitions to comply with local coding convention. 1001 */ 1002 #define ath_hal_detach(_ah) \ 1003 ((*(_ah)->ah_detach)((_ah))) 1004 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 1005 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 1006 #define ath_hal_macversion(_ah) \ 1007 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 1008 #define ath_hal_getratetable(_ah, _mode) \ 1009 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 1010 #define ath_hal_getmac(_ah, _mac) \ 1011 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 1012 #define ath_hal_setmac(_ah, _mac) \ 1013 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 1014 #define ath_hal_getbssidmask(_ah, _mask) \ 1015 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 1016 #define ath_hal_setbssidmask(_ah, _mask) \ 1017 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 1018 #define ath_hal_intrset(_ah, _mask) \ 1019 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 1020 #define ath_hal_intrget(_ah) \ 1021 ((*(_ah)->ah_getInterrupts)((_ah))) 1022 #define ath_hal_intrpend(_ah) \ 1023 ((*(_ah)->ah_isInterruptPending)((_ah))) 1024 #define ath_hal_getisr(_ah, _pmask) \ 1025 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1026 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 1027 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1028 #define ath_hal_setpower(_ah, _mode) \ 1029 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1030 #define ath_hal_keycachesize(_ah) \ 1031 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1032 #define ath_hal_keyreset(_ah, _ix) \ 1033 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1034 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 1035 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1036 #define ath_hal_keyisvalid(_ah, _ix) \ 1037 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1038 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 1039 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1040 #define ath_hal_getrxfilter(_ah) \ 1041 ((*(_ah)->ah_getRxFilter)((_ah))) 1042 #define ath_hal_setrxfilter(_ah, _filter) \ 1043 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1044 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 1045 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1046 #define ath_hal_waitforbeacon(_ah, _bf) \ 1047 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1048 #define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 1049 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 1050 /* NB: common across all chips */ 1051 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 1052 #define ath_hal_gettsf32(_ah) \ 1053 OS_REG_READ(_ah, AR_TSF_L32) 1054 #define ath_hal_gettsf64(_ah) \ 1055 ((*(_ah)->ah_getTsf64)((_ah))) 1056 #define ath_hal_settsf64(_ah, _val) \ 1057 ((*(_ah)->ah_setTsf64)((_ah), (_val))) 1058 #define ath_hal_resettsf(_ah) \ 1059 ((*(_ah)->ah_resetTsf)((_ah))) 1060 #define ath_hal_rxena(_ah) \ 1061 ((*(_ah)->ah_enableReceive)((_ah))) 1062 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 1063 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1064 #define ath_hal_gettxbuf(_ah, _q) \ 1065 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1066 #define ath_hal_numtxpending(_ah, _q) \ 1067 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 1068 #define ath_hal_getrxbuf(_ah, _rxq) \ 1069 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 1070 #define ath_hal_txstart(_ah, _q) \ 1071 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1072 #define ath_hal_setchannel(_ah, _chan) \ 1073 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1074 #define ath_hal_calibrate(_ah, _chan, _iqcal) \ 1075 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1076 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 1077 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 1078 #define ath_hal_calreset(_ah, _chan) \ 1079 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 1080 #define ath_hal_setledstate(_ah, _state) \ 1081 ((*(_ah)->ah_setLedState)((_ah), (_state))) 1082 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 1083 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1084 #define ath_hal_beaconreset(_ah) \ 1085 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1086 #define ath_hal_beaconsettimers(_ah, _bt) \ 1087 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 1088 #define ath_hal_beacontimers(_ah, _bs) \ 1089 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 1090 #define ath_hal_getnexttbtt(_ah) \ 1091 ((*(_ah)->ah_getNextTBTT)((_ah))) 1092 #define ath_hal_setassocid(_ah, _bss, _associd) \ 1093 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1094 #define ath_hal_phydisable(_ah) \ 1095 ((*(_ah)->ah_phyDisable)((_ah))) 1096 #define ath_hal_setopmode(_ah) \ 1097 ((*(_ah)->ah_setPCUConfig)((_ah))) 1098 #define ath_hal_stoptxdma(_ah, _qnum) \ 1099 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1100 #define ath_hal_stoppcurecv(_ah) \ 1101 ((*(_ah)->ah_stopPcuReceive)((_ah))) 1102 #define ath_hal_startpcurecv(_ah) \ 1103 ((*(_ah)->ah_startPcuReceive)((_ah))) 1104 #define ath_hal_stopdmarecv(_ah) \ 1105 ((*(_ah)->ah_stopDmaReceive)((_ah))) 1106 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1107 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1108 (_indata), (_insize), (_outdata), (_outsize))) 1109 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1110 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1111 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1112 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1113 #define ath_hal_resettxqueue(_ah, _q) \ 1114 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1115 #define ath_hal_releasetxqueue(_ah, _q) \ 1116 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1117 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1118 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1119 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1120 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1121 /* NB: common across all chips */ 1122 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1123 #define ath_hal_txqenabled(_ah, _qnum) \ 1124 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1125 #define ath_hal_getrfgain(_ah) \ 1126 ((*(_ah)->ah_getRfGain)((_ah))) 1127 #define ath_hal_getdefantenna(_ah) \ 1128 ((*(_ah)->ah_getDefAntenna)((_ah))) 1129 #define ath_hal_setdefantenna(_ah, _ant) \ 1130 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1131 #define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1132 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1133 #define ath_hal_ani_poll(_ah, _chan) \ 1134 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1135 #define ath_hal_mibevent(_ah, _stats) \ 1136 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1137 #define ath_hal_setslottime(_ah, _us) \ 1138 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1139 #define ath_hal_getslottime(_ah) \ 1140 ((*(_ah)->ah_getSlotTime)((_ah))) 1141 #define ath_hal_setacktimeout(_ah, _us) \ 1142 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1143 #define ath_hal_getacktimeout(_ah) \ 1144 ((*(_ah)->ah_getAckTimeout)((_ah))) 1145 #define ath_hal_setctstimeout(_ah, _us) \ 1146 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1147 #define ath_hal_getctstimeout(_ah) \ 1148 ((*(_ah)->ah_getCTSTimeout)((_ah))) 1149 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1150 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1151 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1152 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1153 #define ath_hal_ciphersupported(_ah, _cipher) \ 1154 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1155 #define ath_hal_getregdomain(_ah, _prd) \ 1156 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1157 #define ath_hal_setregdomain(_ah, _rd) \ 1158 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1159 #define ath_hal_getcountrycode(_ah, _pcc) \ 1160 (*(_pcc) = (_ah)->ah_countryCode) 1161 #define ath_hal_gettkipmic(_ah) \ 1162 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1163 #define ath_hal_settkipmic(_ah, _v) \ 1164 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1165 #define ath_hal_hastkipsplit(_ah) \ 1166 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1167 #define ath_hal_gettkipsplit(_ah) \ 1168 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1169 #define ath_hal_settkipsplit(_ah, _v) \ 1170 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1171 #define ath_hal_haswmetkipmic(_ah) \ 1172 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1173 #define ath_hal_hwphycounters(_ah) \ 1174 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1175 #define ath_hal_hasdiversity(_ah) \ 1176 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1177 #define ath_hal_getdiversity(_ah) \ 1178 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1179 #define ath_hal_setdiversity(_ah, _v) \ 1180 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1181 #define ath_hal_getantennaswitch(_ah) \ 1182 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1183 #define ath_hal_setantennaswitch(_ah, _v) \ 1184 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1185 #define ath_hal_getdiag(_ah, _pv) \ 1186 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1187 #define ath_hal_setdiag(_ah, _v) \ 1188 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1189 #define ath_hal_getnumtxqueues(_ah, _pv) \ 1190 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1191 #define ath_hal_hasveol(_ah) \ 1192 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1193 #define ath_hal_hastxpowlimit(_ah) \ 1194 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1195 #define ath_hal_settxpowlimit(_ah, _pow) \ 1196 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1197 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 1198 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1199 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 1200 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1201 #define ath_hal_gettpscale(_ah, _scale) \ 1202 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1203 #define ath_hal_settpscale(_ah, _v) \ 1204 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1205 #define ath_hal_hastpc(_ah) \ 1206 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1207 #define ath_hal_gettpc(_ah) \ 1208 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1209 #define ath_hal_settpc(_ah, _v) \ 1210 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1211 #define ath_hal_hasbursting(_ah) \ 1212 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1213 #define ath_hal_setmcastkeysearch(_ah, _v) \ 1214 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1215 #define ath_hal_hasmcastkeysearch(_ah) \ 1216 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1217 #define ath_hal_getmcastkeysearch(_ah) \ 1218 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1219 #define ath_hal_hasfastframes(_ah) \ 1220 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1221 #define ath_hal_hasbssidmask(_ah) \ 1222 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1223 #define ath_hal_hasbssidmatch(_ah) \ 1224 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1225 #define ath_hal_hastsfadjust(_ah) \ 1226 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1227 #define ath_hal_gettsfadjust(_ah) \ 1228 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1229 #define ath_hal_settsfadjust(_ah, _onoff) \ 1230 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1231 #define ath_hal_hasrfsilent(_ah) \ 1232 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1233 #define ath_hal_getrfkill(_ah) \ 1234 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1235 #define ath_hal_setrfkill(_ah, _onoff) \ 1236 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1237 #define ath_hal_getrfsilent(_ah, _prfsilent) \ 1238 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1239 #define ath_hal_setrfsilent(_ah, _rfsilent) \ 1240 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1241 #define ath_hal_gettpack(_ah, _ptpack) \ 1242 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1243 #define ath_hal_settpack(_ah, _tpack) \ 1244 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1245 #define ath_hal_gettpcts(_ah, _ptpcts) \ 1246 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1247 #define ath_hal_settpcts(_ah, _tpcts) \ 1248 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1249 #define ath_hal_hasintmit(_ah) \ 1250 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1251 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1252 #define ath_hal_getintmit(_ah) \ 1253 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1254 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1255 #define ath_hal_setintmit(_ah, _v) \ 1256 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1257 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1258 1259 /* EDMA definitions */ 1260 #define ath_hal_hasedma(_ah) \ 1261 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1262 0, NULL) == HAL_OK) 1263 #define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1264 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1265 == HAL_OK) 1266 #define ath_hal_getntxmaps(_ah, _req) \ 1267 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1268 == HAL_OK) 1269 #define ath_hal_gettxdesclen(_ah, _req) \ 1270 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1271 == HAL_OK) 1272 #define ath_hal_gettxstatuslen(_ah, _req) \ 1273 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1274 == HAL_OK) 1275 #define ath_hal_getrxstatuslen(_ah, _req) \ 1276 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1277 == HAL_OK) 1278 #define ath_hal_setrxbufsize(_ah, _req) \ 1279 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1280 == HAL_OK) 1281 1282 #define ath_hal_getchannoise(_ah, _c) \ 1283 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1284 1285 /* 802.11n HAL methods */ 1286 #define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1287 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1288 #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1289 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1290 #define ath_hal_setrxchainmask(_ah, _rx) \ 1291 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1292 #define ath_hal_settxchainmask(_ah, _tx) \ 1293 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1294 #define ath_hal_split4ktrans(_ah) \ 1295 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1296 0, NULL) == HAL_OK) 1297 #define ath_hal_self_linked_final_rxdesc(_ah) \ 1298 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1299 0, NULL) == HAL_OK) 1300 #define ath_hal_gtxto_supported(_ah) \ 1301 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1302 #define ath_hal_has_long_rxdesc_tsf(_ah) \ 1303 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1304 0, NULL) == HAL_OK) 1305 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1306 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1307 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1308 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1309 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1310 _txr0, _txtr0, _keyix, _ant, _flags, \ 1311 _rtsrate, _rtsdura) \ 1312 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1313 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1314 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1315 #define ath_hal_setupxtxdesc(_ah, _ds, \ 1316 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1317 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1318 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1319 #define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1320 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1321 (_first), (_last), (_ds0))) 1322 #define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1323 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1324 #define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1325 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1326 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1327 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1328 #define ath_hal_settxdesclink(_ah, _ds, _link) \ 1329 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1330 #define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1331 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1332 #define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1333 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1334 #define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1335 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1336 (_size))) 1337 #define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1338 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1339 1340 #define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1341 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1342 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1343 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1344 #define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1345 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1346 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1347 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1348 (_first), (_last), (_lastaggr))) 1349 #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1350 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1351 1352 #define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1353 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1354 (_series), (_ns), (_flags))) 1355 1356 #define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1357 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1358 #define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1359 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1360 #define ath_hal_set11n_aggr_last(_ah, _ds) \ 1361 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1362 1363 #define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1364 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1365 #define ath_hal_clr11n_aggr(_ah, _ds) \ 1366 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1367 #define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \ 1368 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v))) 1369 1370 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1371 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1372 #define ath_hal_gpioset(_ah, _gpio, _b) \ 1373 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1374 #define ath_hal_gpioget(_ah, _gpio) \ 1375 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1376 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1377 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1378 1379 /* 1380 * PCIe suspend/resume/poweron/poweroff related macros 1381 */ 1382 #define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1383 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1384 #define ath_hal_disablepcie(_ah) \ 1385 ((*(_ah)->ah_disablePCIE)((_ah))) 1386 1387 /* 1388 * This is badly-named; you need to set the correct parameters 1389 * to begin to receive useful radar events; and even then 1390 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1391 * more information. 1392 */ 1393 #define ath_hal_enabledfs(_ah, _param) \ 1394 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1395 #define ath_hal_getdfsthresh(_ah, _param) \ 1396 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1397 #define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1398 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1399 #define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1400 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1401 (_buf), (_event))) 1402 #define ath_hal_is_fast_clock_enabled(_ah) \ 1403 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1404 #define ath_hal_radar_wait(_ah, _chan) \ 1405 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1406 #define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1407 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1408 #define ath_hal_get_chan_ext_busy(_ah) \ 1409 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1410 #define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \ 1411 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask))) 1412 1413 #define ath_hal_spectral_supported(_ah) \ 1414 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK) 1415 #define ath_hal_spectral_get_config(_ah, _p) \ 1416 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1417 #define ath_hal_spectral_configure(_ah, _p) \ 1418 ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1419 #define ath_hal_spectral_start(_ah) \ 1420 ((*(_ah)->ah_spectralStart)((_ah))) 1421 #define ath_hal_spectral_stop(_ah) \ 1422 ((*(_ah)->ah_spectralStop)((_ah))) 1423 1424 #endif /* _DEV_ATH_ATHVAR_H */ 1425