1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35 #ifndef _DEV_ATH_ATHVAR_H 36 #define _DEV_ATH_ATHVAR_H 37 38 #include <dev/ath/ath_hal/ah.h> 39 #include <dev/ath/ath_hal/ah_desc.h> 40 #include <net80211/ieee80211_radiotap.h> 41 #include <dev/ath/if_athioctl.h> 42 #include <dev/ath/if_athrate.h> 43 44 #define ATH_TIMEOUT 1000 45 46 #ifndef ATH_RXBUF 47 #define ATH_RXBUF 40 /* number of RX buffers */ 48 #endif 49 #ifndef ATH_TXBUF 50 #define ATH_TXBUF 200 /* number of TX buffers */ 51 #endif 52 #define ATH_BCBUF 4 /* number of beacon buffers */ 53 54 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 55 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 56 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 57 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 58 59 #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 60 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 61 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 62 63 /* 64 * The key cache is used for h/w cipher state and also for 65 * tracking station state such as the current tx antenna. 66 * We also setup a mapping table between key cache slot indices 67 * and station state to short-circuit node lookups on rx. 68 * Different parts have different size key caches. We handle 69 * up to ATH_KEYMAX entries (could dynamically allocate state). 70 */ 71 #define ATH_KEYMAX 128 /* max key cache size we handle */ 72 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 73 74 #define ATH_FF_TXQMIN 2 /* min txq depth for staging */ 75 #define ATH_FF_TXQMAX 50 /* maximum # of queued frames allowed */ 76 #define ATH_FF_STAGEMAX 5 /* max waiting period for staged frame*/ 77 78 struct taskqueue; 79 struct kthread; 80 struct ath_buf; 81 82 /* driver-specific node state */ 83 struct ath_node { 84 struct ieee80211_node an_node; /* base class */ 85 u_int8_t an_mgmtrix; /* min h/w rate index */ 86 u_int8_t an_mcastrix; /* mcast h/w rate index */ 87 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 88 /* variable-length rate control state follows */ 89 }; 90 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 91 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 92 93 #define ATH_RSSI_LPF_LEN 10 94 #define ATH_RSSI_DUMMY_MARKER 0x127 95 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 96 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 97 #define ATH_LPF_RSSI(x, y, len) \ 98 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 99 #define ATH_RSSI_LPF(x, y) do { \ 100 if ((y) >= -20) \ 101 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 102 } while (0) 103 #define ATH_EP_RND(x,mul) \ 104 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 105 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 106 107 struct ath_buf { 108 STAILQ_ENTRY(ath_buf) bf_list; 109 TAILQ_ENTRY(ath_buf) bf_stagelist; /* stage queue list */ 110 u_int32_t bf_age; /* age when placed on stageq */ 111 int bf_nseg; 112 uint16_t bf_txflags; /* tx descriptor flags */ 113 uint16_t bf_flags; /* status flags (below) */ 114 struct ath_desc *bf_desc; /* virtual addr of desc */ 115 struct ath_desc_status bf_status; /* tx/rx status */ 116 bus_addr_t bf_daddr; /* physical addr of desc */ 117 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 118 struct mbuf *bf_m; /* mbuf for buf */ 119 struct ieee80211_node *bf_node; /* pointer to the node */ 120 bus_size_t bf_mapsize; 121 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 122 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 123 }; 124 typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 125 126 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 127 128 /* 129 * DMA state for tx/rx descriptors. 130 */ 131 struct ath_descdma { 132 const char* dd_name; 133 struct ath_desc *dd_desc; /* descriptors */ 134 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 135 bus_size_t dd_desc_len; /* size of dd_desc */ 136 bus_dma_segment_t dd_dseg; 137 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 138 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 139 struct ath_buf *dd_bufptr; /* associated buffers */ 140 }; 141 142 /* 143 * Data transmit queue state. One of these exists for each 144 * hardware transmit queue. Packets sent to us from above 145 * are assigned to queues based on their priority. Not all 146 * devices support a complete set of hardware transmit queues. 147 * For those devices the array sc_ac2q will map multiple 148 * priorities to fewer hardware queues (typically all to one 149 * hardware queue). 150 */ 151 struct ath_txq { 152 u_int axq_qnum; /* hardware q number */ 153 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 154 u_int axq_flags; 155 #define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 156 u_int axq_depth; /* queue depth (stat only) */ 157 u_int axq_intrcnt; /* interrupt count */ 158 u_int32_t *axq_link; /* link ptr in last TX desc */ 159 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 160 struct mtx axq_lock; /* lock on q and link */ 161 char axq_name[12]; /* e.g. "ath0_txq4" */ 162 /* 163 * Fast-frame state. The staging queue holds awaiting 164 * a fast-frame pairing. Buffers on this queue are 165 * assigned an ``age'' and flushed when they wait too long. 166 */ 167 TAILQ_HEAD(axq_headtype, ath_buf) axq_stageq; 168 u_int32_t axq_curage; /* queue age */ 169 }; 170 171 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 172 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 173 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 174 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 175 } while (0) 176 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 177 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 178 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 179 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 180 181 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 182 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 183 (_tq)->axq_depth++; \ 184 (_tq)->axq_curage++; \ 185 } while (0) 186 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 187 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 188 (_tq)->axq_depth--; \ 189 } while (0) 190 /* NB: this does not do the "head empty check" that STAILQ_LAST does */ 191 #define ATH_TXQ_LAST(_tq) \ 192 ((struct ath_buf *)(void *) \ 193 ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list))) 194 195 struct ath_vap { 196 struct ieee80211vap av_vap; /* base class */ 197 int av_bslot; /* beacon slot index */ 198 struct ath_buf *av_bcbuf; /* beacon buffer */ 199 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 200 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 201 202 void (*av_recv_mgmt)(struct ieee80211_node *, 203 struct mbuf *, int, int, int, u_int32_t); 204 int (*av_newstate)(struct ieee80211vap *, 205 enum ieee80211_state, int); 206 void (*av_bmiss)(struct ieee80211vap *); 207 }; 208 #define ATH_VAP(vap) ((struct ath_vap *)(vap)) 209 210 struct taskqueue; 211 struct ath_tx99; 212 213 struct ath_softc { 214 struct ifnet *sc_ifp; /* interface common */ 215 struct ath_stats sc_stats; /* interface statistics */ 216 int sc_debug; 217 int sc_nvaps; /* # vaps */ 218 int sc_nstavaps; /* # station vaps */ 219 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 220 u_int8_t sc_nbssid0; /* # vap's using base mac */ 221 uint32_t sc_bssidmask; /* bssid mask */ 222 223 void (*sc_node_free)(struct ieee80211_node *); 224 device_t sc_dev; 225 HAL_BUS_TAG sc_st; /* bus space tag */ 226 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 227 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 228 struct mtx sc_mtx; /* master lock (recursive) */ 229 struct taskqueue *sc_tq; /* private task queue */ 230 struct ath_hal *sc_ah; /* Atheros HAL */ 231 struct ath_ratectrl *sc_rc; /* tx rate control support */ 232 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 233 void (*sc_setdefantenna)(struct ath_softc *, u_int); 234 unsigned int sc_invalid : 1,/* disable hardware accesses */ 235 sc_mrretry : 1,/* multi-rate retry support */ 236 sc_softled : 1,/* enable LED gpio status */ 237 sc_splitmic : 1,/* split TKIP MIC keys */ 238 sc_needmib : 1,/* enable MIB stats intr */ 239 sc_diversity: 1,/* enable rx diversity */ 240 sc_hasveol : 1,/* tx VEOL support */ 241 sc_ledstate : 1,/* LED on/off state */ 242 sc_blinking : 1,/* LED blink operation active */ 243 sc_mcastkey : 1,/* mcast key cache search */ 244 sc_scanning : 1,/* scanning active */ 245 sc_syncbeacon:1,/* sync/resync beacon timers */ 246 sc_hasclrkey: 1,/* CLR key supported */ 247 sc_xchanmode: 1,/* extended channel mode */ 248 sc_outdoor : 1,/* outdoor operation */ 249 sc_dturbo : 1,/* dynamic turbo in use */ 250 sc_hasbmask : 1,/* bssid mask support */ 251 sc_hastsfadd: 1,/* tsf adjust support */ 252 sc_beacons : 1,/* beacons running */ 253 sc_swbmiss : 1,/* sta mode using sw bmiss */ 254 sc_stagbeacons:1,/* use staggered beacons */ 255 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 256 sc_resume_up: 1,/* on resume, start all vaps */ 257 sc_tdma : 1,/* TDMA in use */ 258 sc_setcca : 1,/* set/clr CCA with TDMA */ 259 sc_resetcal : 1;/* reset cal state next trip */ 260 uint32_t sc_eerd; /* regdomain from EEPROM */ 261 uint32_t sc_eecc; /* country code from EEPROM */ 262 /* rate tables */ 263 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 264 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 265 enum ieee80211_phymode sc_curmode; /* current phy mode */ 266 HAL_OPMODE sc_opmode; /* current operating mode */ 267 u_int16_t sc_curtxpow; /* current tx power limit */ 268 u_int16_t sc_curaid; /* current association id */ 269 struct ieee80211_channel *sc_curchan; /* current installed channel */ 270 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 271 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 272 struct { 273 u_int8_t ieeerate; /* IEEE rate */ 274 u_int8_t rxflags; /* radiotap rx flags */ 275 u_int8_t txflags; /* radiotap tx flags */ 276 u_int16_t ledon; /* softled on time */ 277 u_int16_t ledoff; /* softled off time */ 278 } sc_hwmap[32]; /* h/w rate ix mappings */ 279 u_int8_t sc_protrix; /* protection rate index */ 280 u_int8_t sc_lastdatarix; /* last data frame rate index */ 281 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 282 u_int sc_fftxqmin; /* min frames before staging */ 283 u_int sc_fftxqmax; /* max frames before drop */ 284 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 285 HAL_INT sc_imask; /* interrupt mask copy */ 286 u_int sc_keymax; /* size of key cache */ 287 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 288 289 u_int sc_ledpin; /* GPIO pin for driving LED */ 290 u_int sc_ledon; /* pin setting for LED on */ 291 u_int sc_ledidle; /* idle polling interval */ 292 int sc_ledevent; /* time of last LED event */ 293 u_int8_t sc_txrix; /* current tx rate for LED */ 294 u_int16_t sc_ledoff; /* off time for current blink */ 295 struct callout sc_ledtimer; /* led off timer */ 296 297 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 298 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 299 300 struct ath_tx_radiotap_header sc_tx_th; 301 int sc_tx_th_len; 302 struct ath_rx_radiotap_header sc_rx_th; 303 int sc_rx_th_len; 304 u_int sc_monpass; /* frames to pass in mon.mode */ 305 306 struct ath_descdma sc_rxdma; /* RX descriptors */ 307 ath_bufhead sc_rxbuf; /* receive buffer */ 308 struct mbuf *sc_rxpending; /* pending receive data */ 309 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 310 struct task sc_rxtask; /* rx int processing */ 311 u_int8_t sc_defant; /* current default antenna */ 312 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 313 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 314 315 struct ath_descdma sc_txdma; /* TX descriptors */ 316 ath_bufhead sc_txbuf; /* transmit buffer */ 317 struct mtx sc_txbuflock; /* txbuf lock */ 318 char sc_txname[12]; /* e.g. "ath0_buf" */ 319 u_int sc_txqsetup; /* h/w queues setup */ 320 u_int sc_txintrperiod;/* tx interrupt batching */ 321 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 322 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 323 struct task sc_txtask; /* tx int processing */ 324 325 struct ath_descdma sc_bdma; /* beacon descriptors */ 326 ath_bufhead sc_bbuf; /* beacon buffers */ 327 u_int sc_bhalq; /* HAL q for outgoing beacons */ 328 u_int sc_bmisscount; /* missed beacon transmits */ 329 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 330 struct ath_txq *sc_cabq; /* tx q for cab frames */ 331 struct task sc_bmisstask; /* bmiss int processing */ 332 struct task sc_bstucktask; /* stuck beacon processing */ 333 enum { 334 OK, /* no change needed */ 335 UPDATE, /* update pending */ 336 COMMIT /* beacon sent, commit change */ 337 } sc_updateslot; /* slot time update fsm */ 338 int sc_slotupdate; /* slot to advance fsm */ 339 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 340 int sc_nbcnvaps; /* # vaps with beacons */ 341 342 struct callout sc_cal_ch; /* callout handle for cals */ 343 int sc_lastlongcal; /* last long cal completed */ 344 int sc_lastcalreset;/* last cal reset done */ 345 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 346 #ifdef ATH_SUPPORT_TDMA 347 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 348 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 349 u_int sc_tdmaswba; /* TDMA SWBA counter */ 350 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 351 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 352 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 353 u_int sc_tdmabintcnt; /* TDMA beacon intvl (slots) */ 354 struct ath_rx_status *sc_tdmars; /* TDMA status of last rx */ 355 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 356 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 357 #endif 358 }; 359 360 #define ATH_LOCK_INIT(_sc) \ 361 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 362 NULL, MTX_DEF | MTX_RECURSE) 363 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 364 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 365 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 366 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 367 368 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 369 370 #define ATH_TXBUF_LOCK_INIT(_sc) do { \ 371 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 372 device_get_nameunit((_sc)->sc_dev)); \ 373 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 374 } while (0) 375 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 376 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 377 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 378 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 379 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 380 381 int ath_attach(u_int16_t, struct ath_softc *); 382 int ath_detach(struct ath_softc *); 383 void ath_resume(struct ath_softc *); 384 void ath_suspend(struct ath_softc *); 385 void ath_shutdown(struct ath_softc *); 386 void ath_intr(void *); 387 388 /* 389 * HAL definitions to comply with local coding convention. 390 */ 391 #define ath_hal_detach(_ah) \ 392 ((*(_ah)->ah_detach)((_ah))) 393 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 394 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 395 #define ath_hal_macversion(_ah) \ 396 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 397 #define ath_hal_getratetable(_ah, _mode) \ 398 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 399 #define ath_hal_getmac(_ah, _mac) \ 400 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 401 #define ath_hal_setmac(_ah, _mac) \ 402 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 403 #define ath_hal_getbssidmask(_ah, _mask) \ 404 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 405 #define ath_hal_setbssidmask(_ah, _mask) \ 406 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 407 #define ath_hal_intrset(_ah, _mask) \ 408 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 409 #define ath_hal_intrget(_ah) \ 410 ((*(_ah)->ah_getInterrupts)((_ah))) 411 #define ath_hal_intrpend(_ah) \ 412 ((*(_ah)->ah_isInterruptPending)((_ah))) 413 #define ath_hal_getisr(_ah, _pmask) \ 414 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 415 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 416 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 417 #define ath_hal_setpower(_ah, _mode) \ 418 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 419 #define ath_hal_keycachesize(_ah) \ 420 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 421 #define ath_hal_keyreset(_ah, _ix) \ 422 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 423 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 424 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 425 #define ath_hal_keyisvalid(_ah, _ix) \ 426 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 427 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 428 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 429 #define ath_hal_getrxfilter(_ah) \ 430 ((*(_ah)->ah_getRxFilter)((_ah))) 431 #define ath_hal_setrxfilter(_ah, _filter) \ 432 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 433 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 434 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 435 #define ath_hal_waitforbeacon(_ah, _bf) \ 436 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 437 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 438 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 439 /* NB: common across all chips */ 440 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 441 #define ath_hal_gettsf32(_ah) \ 442 OS_REG_READ(_ah, AR_TSF_L32) 443 #define ath_hal_gettsf64(_ah) \ 444 ((*(_ah)->ah_getTsf64)((_ah))) 445 #define ath_hal_resettsf(_ah) \ 446 ((*(_ah)->ah_resetTsf)((_ah))) 447 #define ath_hal_rxena(_ah) \ 448 ((*(_ah)->ah_enableReceive)((_ah))) 449 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 450 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 451 #define ath_hal_gettxbuf(_ah, _q) \ 452 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 453 #define ath_hal_numtxpending(_ah, _q) \ 454 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 455 #define ath_hal_getrxbuf(_ah) \ 456 ((*(_ah)->ah_getRxDP)((_ah))) 457 #define ath_hal_txstart(_ah, _q) \ 458 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 459 #define ath_hal_setchannel(_ah, _chan) \ 460 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 461 #define ath_hal_calibrate(_ah, _chan, _iqcal) \ 462 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 463 #if HAL_ABI_VERSION >= 0x08111000 464 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 465 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 466 #define ath_hal_calreset(_ah, _chan) \ 467 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 468 #else 469 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 470 ath_hal_calibrate(_ah, _chan, _isdone) 471 #define ath_hal_calreset(_ah, _chan) (0) 472 #endif 473 #define ath_hal_setledstate(_ah, _state) \ 474 ((*(_ah)->ah_setLedState)((_ah), (_state))) 475 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 476 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 477 #define ath_hal_beaconreset(_ah) \ 478 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 479 #define ath_hal_beaconsettimers(_ah, _bt) \ 480 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 481 #define ath_hal_beacontimers(_ah, _bs) \ 482 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 483 #define ath_hal_setassocid(_ah, _bss, _associd) \ 484 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 485 #define ath_hal_phydisable(_ah) \ 486 ((*(_ah)->ah_phyDisable)((_ah))) 487 #define ath_hal_setopmode(_ah) \ 488 ((*(_ah)->ah_setPCUConfig)((_ah))) 489 #define ath_hal_stoptxdma(_ah, _qnum) \ 490 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 491 #define ath_hal_stoppcurecv(_ah) \ 492 ((*(_ah)->ah_stopPcuReceive)((_ah))) 493 #define ath_hal_startpcurecv(_ah) \ 494 ((*(_ah)->ah_startPcuReceive)((_ah))) 495 #define ath_hal_stopdmarecv(_ah) \ 496 ((*(_ah)->ah_stopDmaReceive)((_ah))) 497 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 498 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 499 (_indata), (_insize), (_outdata), (_outsize))) 500 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 501 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 502 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 503 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 504 #define ath_hal_resettxqueue(_ah, _q) \ 505 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 506 #define ath_hal_releasetxqueue(_ah, _q) \ 507 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 508 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 509 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 510 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 511 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 512 /* NB: common across all chips */ 513 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 514 #define ath_hal_txqenabled(_ah, _qnum) \ 515 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 516 #define ath_hal_getrfgain(_ah) \ 517 ((*(_ah)->ah_getRfGain)((_ah))) 518 #define ath_hal_getdefantenna(_ah) \ 519 ((*(_ah)->ah_getDefAntenna)((_ah))) 520 #define ath_hal_setdefantenna(_ah, _ant) \ 521 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 522 #define ath_hal_rxmonitor(_ah, _arg, _chan) \ 523 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 524 #define ath_hal_mibevent(_ah, _stats) \ 525 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 526 #define ath_hal_setslottime(_ah, _us) \ 527 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 528 #define ath_hal_getslottime(_ah) \ 529 ((*(_ah)->ah_getSlotTime)((_ah))) 530 #define ath_hal_setacktimeout(_ah, _us) \ 531 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 532 #define ath_hal_getacktimeout(_ah) \ 533 ((*(_ah)->ah_getAckTimeout)((_ah))) 534 #define ath_hal_setctstimeout(_ah, _us) \ 535 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 536 #define ath_hal_getctstimeout(_ah) \ 537 ((*(_ah)->ah_getCTSTimeout)((_ah))) 538 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 539 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 540 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 541 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 542 #define ath_hal_ciphersupported(_ah, _cipher) \ 543 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 544 #define ath_hal_getregdomain(_ah, _prd) \ 545 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 546 #if HAL_ABI_VERSION < 0x08090100 547 /* XXX wrong for anything but amd64 and i386 */ 548 #if defined(__LP64__) 549 #define ath_hal_setregdomain(_ah, _rd) \ 550 (*(uint16_t *)(((uint8_t *)&(_ah)[1]) + 176) = (_rd)) 551 #else 552 #define ath_hal_setregdomain(_ah, _rd) \ 553 (*(uint16_t *)(((uint8_t *)&(_ah)[1]) + 128) = (_rd)) 554 #endif 555 #else 556 #define ath_hal_setregdomain(_ah, _rd) \ 557 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 558 #endif 559 #define ath_hal_getcountrycode(_ah, _pcc) \ 560 (*(_pcc) = (_ah)->ah_countryCode) 561 #define ath_hal_gettkipmic(_ah) \ 562 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 563 #define ath_hal_settkipmic(_ah, _v) \ 564 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 565 #define ath_hal_hastkipsplit(_ah) \ 566 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 567 #define ath_hal_gettkipsplit(_ah) \ 568 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 569 #define ath_hal_settkipsplit(_ah, _v) \ 570 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 571 #define ath_hal_haswmetkipmic(_ah) \ 572 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 573 #define ath_hal_hwphycounters(_ah) \ 574 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 575 #define ath_hal_hasdiversity(_ah) \ 576 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 577 #define ath_hal_getdiversity(_ah) \ 578 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 579 #define ath_hal_setdiversity(_ah, _v) \ 580 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 581 #define ath_hal_getantennaswitch(_ah) \ 582 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 583 #define ath_hal_setantennaswitch(_ah, _v) \ 584 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 585 #define ath_hal_getdiag(_ah, _pv) \ 586 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 587 #define ath_hal_setdiag(_ah, _v) \ 588 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 589 #define ath_hal_getnumtxqueues(_ah, _pv) \ 590 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 591 #define ath_hal_hasveol(_ah) \ 592 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 593 #define ath_hal_hastxpowlimit(_ah) \ 594 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 595 #define ath_hal_settxpowlimit(_ah, _pow) \ 596 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 597 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 598 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 599 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 600 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 601 #define ath_hal_gettpscale(_ah, _scale) \ 602 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 603 #define ath_hal_settpscale(_ah, _v) \ 604 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 605 #define ath_hal_hastpc(_ah) \ 606 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 607 #define ath_hal_gettpc(_ah) \ 608 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 609 #define ath_hal_settpc(_ah, _v) \ 610 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 611 #define ath_hal_hasbursting(_ah) \ 612 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 613 #ifdef notyet 614 #define ath_hal_hasmcastkeysearch(_ah) \ 615 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 616 #define ath_hal_getmcastkeysearch(_ah) \ 617 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 618 #else 619 #define ath_hal_getmcastkeysearch(_ah) 0 620 #endif 621 #define ath_hal_hasfastframes(_ah) \ 622 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 623 #define ath_hal_hasbssidmask(_ah) \ 624 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 625 #define ath_hal_hastsfadjust(_ah) \ 626 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 627 #define ath_hal_gettsfadjust(_ah) \ 628 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 629 #define ath_hal_settsfadjust(_ah, _onoff) \ 630 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 631 #define ath_hal_hasrfsilent(_ah) \ 632 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 633 #define ath_hal_getrfkill(_ah) \ 634 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 635 #define ath_hal_setrfkill(_ah, _onoff) \ 636 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 637 #define ath_hal_getrfsilent(_ah, _prfsilent) \ 638 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 639 #define ath_hal_setrfsilent(_ah, _rfsilent) \ 640 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 641 #define ath_hal_gettpack(_ah, _ptpack) \ 642 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 643 #define ath_hal_settpack(_ah, _tpack) \ 644 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 645 #define ath_hal_gettpcts(_ah, _ptpcts) \ 646 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 647 #define ath_hal_settpcts(_ah, _tpcts) \ 648 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 649 #define ath_hal_hasintmit(_ah) \ 650 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 0, NULL) == HAL_OK) 651 #define ath_hal_getintmit(_ah) \ 652 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 1, NULL) == HAL_OK) 653 #define ath_hal_setintmit(_ah, _v) \ 654 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, 1, _v, NULL) 655 #define ath_hal_getchannoise(_ah, _c) \ 656 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 657 #if HAL_ABI_VERSION < 0x05122200 658 #define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 659 #define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 660 #define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 661 #define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 662 #define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 663 #endif 664 #if HAL_ABI_VERSION < 0x06102501 665 #define ath_hal_ispublicsafetysku(ah) \ 666 (((ah)->ah_regdomain == 0 && (ah)->ah_countryCode == 842) || \ 667 (ah)->ah_regdomain == 0x12) 668 #endif 669 #if HAL_ABI_VERSION < 0x06122400 670 /* XXX yech, can't get to regdomain so just hack a compat shim */ 671 #define ath_hal_isgsmsku(ah) \ 672 ((ah)->ah_countryCode == 843) 673 #endif 674 #if HAL_ABI_VERSION < 0x07050400 675 /* compat shims so code compilers--it won't work though */ 676 #define CHANNEL_HT20 0x10000 677 #define CHANNEL_HT40PLUS 0x20000 678 #define CHANNEL_HT40MINUS 0x40000 679 #define HAL_MODE_11NG_HT20 0x008000 680 #define HAL_MODE_11NA_HT20 0x010000 681 #endif 682 683 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 684 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 685 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 686 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 687 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 688 _txr0, _txtr0, _keyix, _ant, _flags, \ 689 _rtsrate, _rtsdura) \ 690 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 691 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 692 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 693 #define ath_hal_setupxtxdesc(_ah, _ds, \ 694 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 695 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 696 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 697 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 698 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 699 #define ath_hal_txprocdesc(_ah, _ds, _ts) \ 700 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 701 #define ath_hal_gettxintrtxqs(_ah, _txqs) \ 702 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 703 704 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 705 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 706 #define ath_hal_gpioset(_ah, _gpio, _b) \ 707 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 708 #define ath_hal_gpioget(_ah, _gpio) \ 709 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 710 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 711 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 712 713 #define ath_hal_radar_wait(_ah, _chan) \ 714 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 715 716 #endif /* _DEV_ATH_ATHVAR_H */ 717