xref: /freebsd/sys/dev/ath/if_athvar.h (revision 7778ab7e0cc22f0824eb1d1047a7ef8b4785267a)
1 /*-
2  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification.
11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13  *    redistribution must be conditioned upon including a substantially
14  *    similar Disclaimer requirement for further binary redistribution.
15  *
16  * NO WARRANTY
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27  * THE POSSIBILITY OF SUCH DAMAGES.
28  *
29  * $FreeBSD$
30  */
31 
32 /*
33  * Defintions for the Atheros Wireless LAN controller driver.
34  */
35 #ifndef _DEV_ATH_ATHVAR_H
36 #define _DEV_ATH_ATHVAR_H
37 
38 #include <dev/ath/ath_hal/ah.h>
39 #include <dev/ath/ath_hal/ah_desc.h>
40 #include <net80211/ieee80211_radiotap.h>
41 #include <dev/ath/if_athioctl.h>
42 #include <dev/ath/if_athrate.h>
43 
44 #define	ATH_TIMEOUT		1000
45 
46 /*
47  * 802.11n requires more TX and RX buffers to do AMPDU.
48  */
49 #ifdef	ATH_ENABLE_11N
50 #define	ATH_TXBUF	512
51 #define	ATH_RXBUF	512
52 #endif
53 
54 #ifndef ATH_RXBUF
55 #define	ATH_RXBUF	40		/* number of RX buffers */
56 #endif
57 #ifndef ATH_TXBUF
58 #define	ATH_TXBUF	200		/* number of TX buffers */
59 #endif
60 #define	ATH_BCBUF	4		/* number of beacon buffers */
61 
62 #define	ATH_TXDESC	10		/* number of descriptors per buffer */
63 #define	ATH_TXMAXTRY	11		/* max number of transmit attempts */
64 #define	ATH_TXMGTTRY	4		/* xmit attempts for mgt/ctl frames */
65 #define	ATH_TXINTR_PERIOD 5		/* max number of batched tx descriptors */
66 
67 #define	ATH_BEACON_AIFS_DEFAULT	 1	/* default aifs for ap beacon q */
68 #define	ATH_BEACON_CWMIN_DEFAULT 0	/* default cwmin for ap beacon q */
69 #define	ATH_BEACON_CWMAX_DEFAULT 0	/* default cwmax for ap beacon q */
70 
71 /*
72  * The key cache is used for h/w cipher state and also for
73  * tracking station state such as the current tx antenna.
74  * We also setup a mapping table between key cache slot indices
75  * and station state to short-circuit node lookups on rx.
76  * Different parts have different size key caches.  We handle
77  * up to ATH_KEYMAX entries (could dynamically allocate state).
78  */
79 #define	ATH_KEYMAX	128		/* max key cache size we handle */
80 #define	ATH_KEYBYTES	(ATH_KEYMAX/NBBY)	/* storage space in bytes */
81 
82 struct taskqueue;
83 struct kthread;
84 struct ath_buf;
85 
86 /* driver-specific node state */
87 struct ath_node {
88 	struct ieee80211_node an_node;	/* base class */
89 	u_int8_t	an_mgmtrix;	/* min h/w rate index */
90 	u_int8_t	an_mcastrix;	/* mcast h/w rate index */
91 	struct ath_buf	*an_ff_buf[WME_NUM_AC]; /* ff staging area */
92 	/* variable-length rate control state follows */
93 };
94 #define	ATH_NODE(ni)	((struct ath_node *)(ni))
95 #define	ATH_NODE_CONST(ni)	((const struct ath_node *)(ni))
96 
97 #define ATH_RSSI_LPF_LEN	10
98 #define ATH_RSSI_DUMMY_MARKER	0x127
99 #define ATH_EP_MUL(x, mul)	((x) * (mul))
100 #define ATH_RSSI_IN(x)		(ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
101 #define ATH_LPF_RSSI(x, y, len) \
102     ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
103 #define ATH_RSSI_LPF(x, y) do {						\
104     if ((y) >= -20)							\
105     	x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN);	\
106 } while (0)
107 #define	ATH_EP_RND(x,mul) \
108 	((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
109 #define	ATH_RSSI(x)		ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER)
110 
111 struct ath_buf {
112 	STAILQ_ENTRY(ath_buf)	bf_list;
113 	int			bf_nseg;
114 	uint16_t		bf_txflags;	/* tx descriptor flags */
115 	uint16_t		bf_flags;	/* status flags (below) */
116 	struct ath_desc		*bf_desc;	/* virtual addr of desc */
117 	struct ath_desc_status	bf_status;	/* tx/rx status */
118 	bus_addr_t		bf_daddr;	/* physical addr of desc */
119 	bus_dmamap_t		bf_dmamap;	/* DMA map for mbuf chain */
120 	struct mbuf		*bf_m;		/* mbuf for buf */
121 	struct ieee80211_node	*bf_node;	/* pointer to the node */
122 	bus_size_t		bf_mapsize;
123 #define	ATH_MAX_SCATTER		ATH_TXDESC	/* max(tx,rx,beacon) desc's */
124 	bus_dma_segment_t	bf_segs[ATH_MAX_SCATTER];
125 };
126 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
127 
128 #define	ATH_BUF_BUSY	0x00000002	/* (tx) desc owned by h/w */
129 
130 /*
131  * DMA state for tx/rx descriptors.
132  */
133 struct ath_descdma {
134 	const char*		dd_name;
135 	struct ath_desc		*dd_desc;	/* descriptors */
136 	bus_addr_t		dd_desc_paddr;	/* physical addr of dd_desc */
137 	bus_size_t		dd_desc_len;	/* size of dd_desc */
138 	bus_dma_segment_t	dd_dseg;
139 	bus_dma_tag_t		dd_dmat;	/* bus DMA tag */
140 	bus_dmamap_t		dd_dmamap;	/* DMA map for descriptors */
141 	struct ath_buf		*dd_bufptr;	/* associated buffers */
142 };
143 
144 /*
145  * Data transmit queue state.  One of these exists for each
146  * hardware transmit queue.  Packets sent to us from above
147  * are assigned to queues based on their priority.  Not all
148  * devices support a complete set of hardware transmit queues.
149  * For those devices the array sc_ac2q will map multiple
150  * priorities to fewer hardware queues (typically all to one
151  * hardware queue).
152  */
153 struct ath_txq {
154 	u_int			axq_qnum;	/* hardware q number */
155 #define	ATH_TXQ_SWQ	(HAL_NUM_TX_QUEUES+1)	/* qnum for s/w only queue */
156 	u_int			axq_ac;		/* WME AC */
157 	u_int			axq_flags;
158 #define	ATH_TXQ_PUTPENDING	0x0001		/* ath_hal_puttxbuf pending */
159 	u_int			axq_depth;	/* queue depth (stat only) */
160 	u_int			axq_intrcnt;	/* interrupt count */
161 	u_int32_t		*axq_link;	/* link ptr in last TX desc */
162 	STAILQ_HEAD(, ath_buf)	axq_q;		/* transmit queue */
163 	struct mtx		axq_lock;	/* lock on q and link */
164 	char			axq_name[12];	/* e.g. "ath0_txq4" */
165 };
166 
167 #define	ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
168 	snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
169 		device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
170 	mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
171 } while (0)
172 #define	ATH_TXQ_LOCK_DESTROY(_tq)	mtx_destroy(&(_tq)->axq_lock)
173 #define	ATH_TXQ_LOCK(_tq)		mtx_lock(&(_tq)->axq_lock)
174 #define	ATH_TXQ_UNLOCK(_tq)		mtx_unlock(&(_tq)->axq_lock)
175 #define	ATH_TXQ_LOCK_ASSERT(_tq)	mtx_assert(&(_tq)->axq_lock, MA_OWNED)
176 
177 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
178 	STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
179 	(_tq)->axq_depth++; \
180 } while (0)
181 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
182 	STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
183 	(_tq)->axq_depth--; \
184 } while (0)
185 /* NB: this does not do the "head empty check" that STAILQ_LAST does */
186 #define	ATH_TXQ_LAST(_tq) \
187 	((struct ath_buf *)(void *) \
188 	 ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list)))
189 
190 struct ath_vap {
191 	struct ieee80211vap av_vap;	/* base class */
192 	int		av_bslot;	/* beacon slot index */
193 	struct ath_buf	*av_bcbuf;	/* beacon buffer */
194 	struct ieee80211_beacon_offsets av_boff;/* dynamic update state */
195 	struct ath_txq	av_mcastq;	/* buffered mcast s/w queue */
196 
197 	void		(*av_recv_mgmt)(struct ieee80211_node *,
198 				struct mbuf *, int, int, int);
199 	int		(*av_newstate)(struct ieee80211vap *,
200 				enum ieee80211_state, int);
201 	void		(*av_bmiss)(struct ieee80211vap *);
202 };
203 #define	ATH_VAP(vap)	((struct ath_vap *)(vap))
204 
205 struct taskqueue;
206 struct ath_tx99;
207 
208 struct ath_softc {
209 	struct ifnet		*sc_ifp;	/* interface common */
210 	struct ath_stats	sc_stats;	/* interface statistics */
211 	int			sc_debug;
212 	int			sc_nvaps;	/* # vaps */
213 	int			sc_nstavaps;	/* # station vaps */
214 	int			sc_nmeshvaps;	/* # mbss vaps */
215 	u_int8_t		sc_hwbssidmask[IEEE80211_ADDR_LEN];
216 	u_int8_t		sc_nbssid0;	/* # vap's using base mac */
217 	uint32_t		sc_bssidmask;	/* bssid mask */
218 
219 	void 			(*sc_node_free)(struct ieee80211_node *);
220 	device_t		sc_dev;
221 	HAL_BUS_TAG		sc_st;		/* bus space tag */
222 	HAL_BUS_HANDLE		sc_sh;		/* bus space handle */
223 	bus_dma_tag_t		sc_dmat;	/* bus DMA tag */
224 	struct mtx		sc_mtx;		/* master lock (recursive) */
225 	struct taskqueue	*sc_tq;		/* private task queue */
226 	struct ath_hal		*sc_ah;		/* Atheros HAL */
227 	struct ath_ratectrl	*sc_rc;		/* tx rate control support */
228 	struct ath_tx99		*sc_tx99;	/* tx99 adjunct state */
229 	void			(*sc_setdefantenna)(struct ath_softc *, u_int);
230 	unsigned int		sc_invalid  : 1,/* disable hardware accesses */
231 				sc_mrretry  : 1,/* multi-rate retry support */
232 				sc_softled  : 1,/* enable LED gpio status */
233 				sc_splitmic : 1,/* split TKIP MIC keys */
234 				sc_needmib  : 1,/* enable MIB stats intr */
235 				sc_diversity: 1,/* enable rx diversity */
236 				sc_hasveol  : 1,/* tx VEOL support */
237 				sc_ledstate : 1,/* LED on/off state */
238 				sc_blinking : 1,/* LED blink operation active */
239 				sc_mcastkey : 1,/* mcast key cache search */
240 				sc_scanning : 1,/* scanning active */
241 				sc_syncbeacon:1,/* sync/resync beacon timers */
242 				sc_hasclrkey: 1,/* CLR key supported */
243 				sc_xchanmode: 1,/* extended channel mode */
244 				sc_outdoor  : 1,/* outdoor operation */
245 				sc_dturbo   : 1,/* dynamic turbo in use */
246 				sc_hasbmask : 1,/* bssid mask support */
247 				sc_hasbmatch: 1,/* bssid match disable support*/
248 				sc_hastsfadd: 1,/* tsf adjust support */
249 				sc_beacons  : 1,/* beacons running */
250 				sc_swbmiss  : 1,/* sta mode using sw bmiss */
251 				sc_stagbeacons:1,/* use staggered beacons */
252 				sc_wmetkipmic:1,/* can do WME+TKIP MIC */
253 				sc_resume_up: 1,/* on resume, start all vaps */
254 				sc_tdma	    : 1,/* TDMA in use */
255 				sc_setcca   : 1,/* set/clr CCA with TDMA */
256 				sc_resetcal : 1,/* reset cal state next trip */
257 				sc_rxslink  : 1,/* do self-linked final descriptor */
258 				sc_kickpcu  : 1,/* kick PCU RX on next RX proc */
259 				sc_rxtsf32  : 1;/* RX dec TSF is 32 bits */
260 	uint32_t		sc_eerd;	/* regdomain from EEPROM */
261 	uint32_t		sc_eecc;	/* country code from EEPROM */
262 						/* rate tables */
263 	const HAL_RATE_TABLE	*sc_rates[IEEE80211_MODE_MAX];
264 	const HAL_RATE_TABLE	*sc_currates;	/* current rate table */
265 	enum ieee80211_phymode	sc_curmode;	/* current phy mode */
266 	HAL_OPMODE		sc_opmode;	/* current operating mode */
267 	u_int16_t		sc_curtxpow;	/* current tx power limit */
268 	u_int16_t		sc_curaid;	/* current association id */
269 	struct ieee80211_channel *sc_curchan;	/* current installed channel */
270 	u_int8_t		sc_curbssid[IEEE80211_ADDR_LEN];
271 	u_int8_t		sc_rixmap[256];	/* IEEE to h/w rate table ix */
272 	struct {
273 		u_int8_t	ieeerate;	/* IEEE rate */
274 		u_int8_t	rxflags;	/* radiotap rx flags */
275 		u_int8_t	txflags;	/* radiotap tx flags */
276 		u_int16_t	ledon;		/* softled on time */
277 		u_int16_t	ledoff;		/* softled off time */
278 	} sc_hwmap[32];				/* h/w rate ix mappings */
279 	u_int8_t		sc_protrix;	/* protection rate index */
280 	u_int8_t		sc_lastdatarix;	/* last data frame rate index */
281 	u_int			sc_mcastrate;	/* ieee rate for mcastrateix */
282 	u_int			sc_fftxqmin;	/* min frames before staging */
283 	u_int			sc_fftxqmax;	/* max frames before drop */
284 	u_int			sc_txantenna;	/* tx antenna (fixed or auto) */
285 	HAL_INT			sc_imask;	/* interrupt mask copy */
286 	u_int			sc_keymax;	/* size of key cache */
287 	u_int8_t		sc_keymap[ATH_KEYBYTES];/* key use bit map */
288 
289 	u_int			sc_ledpin;	/* GPIO pin for driving LED */
290 	u_int			sc_ledon;	/* pin setting for LED on */
291 	u_int			sc_ledidle;	/* idle polling interval */
292 	int			sc_ledevent;	/* time of last LED event */
293 	u_int8_t		sc_txrix;	/* current tx rate for LED */
294 	u_int16_t		sc_ledoff;	/* off time for current blink */
295 	struct callout		sc_ledtimer;	/* led off timer */
296 
297 	u_int			sc_rfsilentpin;	/* GPIO pin for rfkill int */
298 	u_int			sc_rfsilentpol;	/* pin setting for rfkill on */
299 
300 	struct ath_descdma	sc_rxdma;	/* RX descriptors */
301 	ath_bufhead		sc_rxbuf;	/* receive buffer */
302 	struct mbuf		*sc_rxpending;	/* pending receive data */
303 	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
304 	struct task		sc_rxtask;	/* rx int processing */
305 	u_int8_t		sc_defant;	/* current default antenna */
306 	u_int8_t		sc_rxotherant;	/* rx's on non-default antenna*/
307 	u_int64_t		sc_lastrx;	/* tsf at last rx'd frame */
308 	struct ath_rx_status	*sc_lastrs;	/* h/w status of last rx */
309 	struct ath_rx_radiotap_header sc_rx_th;
310 	int			sc_rx_th_len;
311 	u_int			sc_monpass;	/* frames to pass in mon.mode */
312 
313 	struct ath_descdma	sc_txdma;	/* TX descriptors */
314 	ath_bufhead		sc_txbuf;	/* transmit buffer */
315 	struct mtx		sc_txbuflock;	/* txbuf lock */
316 	char			sc_txname[12];	/* e.g. "ath0_buf" */
317 	u_int			sc_txqsetup;	/* h/w queues setup */
318 	u_int			sc_txintrperiod;/* tx interrupt batching */
319 	struct ath_txq		sc_txq[HAL_NUM_TX_QUEUES];
320 	struct ath_txq		*sc_ac2q[5];	/* WME AC -> h/w q map */
321 	struct task		sc_txtask;	/* tx int processing */
322 	int			sc_wd_timer;	/* count down for wd timer */
323 	struct callout		sc_wd_ch;	/* tx watchdog timer */
324 	struct ath_tx_radiotap_header sc_tx_th;
325 	int			sc_tx_th_len;
326 
327 	struct ath_descdma	sc_bdma;	/* beacon descriptors */
328 	ath_bufhead		sc_bbuf;	/* beacon buffers */
329 	u_int			sc_bhalq;	/* HAL q for outgoing beacons */
330 	u_int			sc_bmisscount;	/* missed beacon transmits */
331 	u_int32_t		sc_ant_tx[8];	/* recent tx frames/antenna */
332 	struct ath_txq		*sc_cabq;	/* tx q for cab frames */
333 	struct task		sc_bmisstask;	/* bmiss int processing */
334 	struct task		sc_bstucktask;	/* stuck beacon processing */
335 	enum {
336 		OK,				/* no change needed */
337 		UPDATE,				/* update pending */
338 		COMMIT				/* beacon sent, commit change */
339 	} sc_updateslot;			/* slot time update fsm */
340 	int			sc_slotupdate;	/* slot to advance fsm */
341 	struct ieee80211vap	*sc_bslot[ATH_BCBUF];
342 	int			sc_nbcnvaps;	/* # vaps with beacons */
343 
344 	struct callout		sc_cal_ch;	/* callout handle for cals */
345 	int			sc_lastlongcal;	/* last long cal completed */
346 	int			sc_lastcalreset;/* last cal reset done */
347 	int			sc_lastani;	/* last ANI poll */
348 	int			sc_lastshortcal;	/* last short calibration */
349 	HAL_BOOL		sc_doresetcal;	/* Yes, we're doing a reset cal atm */
350 	HAL_NODE_STATS		sc_halstats;	/* station-mode rssi stats */
351 	u_int			sc_tdmadbaprep;	/* TDMA DBA prep time */
352 	u_int			sc_tdmaswbaprep;/* TDMA SWBA prep time */
353 	u_int			sc_tdmaswba;	/* TDMA SWBA counter */
354 	u_int32_t		sc_tdmabintval;	/* TDMA beacon interval (TU) */
355 	u_int32_t		sc_tdmaguard;	/* TDMA guard time (usec) */
356 	u_int			sc_tdmaslotlen;	/* TDMA slot length (usec) */
357 	u_int32_t		sc_avgtsfdeltap;/* TDMA slot adjust (+) */
358 	u_int32_t		sc_avgtsfdeltam;/* TDMA slot adjust (-) */
359 	uint16_t		*sc_eepromdata;	/* Local eeprom data, if AR9100 */
360 	int			sc_txchainmask;	/* currently configured TX chainmask */
361 	int			sc_rxchainmask;	/* currently configured RX chainmask */
362 
363 	/* DFS related state */
364 	void			*sc_dfs;	/* Used by an optional DFS module */
365 	int			sc_dodfs;	/* Whether to enable DFS rx filter bits */
366 	struct task		sc_dfstask;	/* DFS processing task */
367 };
368 
369 #define	ATH_LOCK_INIT(_sc) \
370 	mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
371 		 NULL, MTX_DEF | MTX_RECURSE)
372 #define	ATH_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_mtx)
373 #define	ATH_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
374 #define	ATH_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
375 #define	ATH_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
376 
377 #define	ATH_TXQ_SETUP(sc, i)	((sc)->sc_txqsetup & (1<<i))
378 
379 #define	ATH_TXBUF_LOCK_INIT(_sc) do { \
380 	snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
381 		device_get_nameunit((_sc)->sc_dev)); \
382 	mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
383 } while (0)
384 #define	ATH_TXBUF_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_txbuflock)
385 #define	ATH_TXBUF_LOCK(_sc)		mtx_lock(&(_sc)->sc_txbuflock)
386 #define	ATH_TXBUF_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_txbuflock)
387 #define	ATH_TXBUF_LOCK_ASSERT(_sc) \
388 	mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
389 
390 int	ath_attach(u_int16_t, struct ath_softc *);
391 int	ath_detach(struct ath_softc *);
392 void	ath_resume(struct ath_softc *);
393 void	ath_suspend(struct ath_softc *);
394 void	ath_shutdown(struct ath_softc *);
395 void	ath_intr(void *);
396 
397 /*
398  * HAL definitions to comply with local coding convention.
399  */
400 #define	ath_hal_detach(_ah) \
401 	((*(_ah)->ah_detach)((_ah)))
402 #define	ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
403 	((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
404 #define	ath_hal_macversion(_ah) \
405 	(((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
406 #define	ath_hal_getratetable(_ah, _mode) \
407 	((*(_ah)->ah_getRateTable)((_ah), (_mode)))
408 #define	ath_hal_getmac(_ah, _mac) \
409 	((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
410 #define	ath_hal_setmac(_ah, _mac) \
411 	((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
412 #define	ath_hal_getbssidmask(_ah, _mask) \
413 	((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
414 #define	ath_hal_setbssidmask(_ah, _mask) \
415 	((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
416 #define	ath_hal_intrset(_ah, _mask) \
417 	((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
418 #define	ath_hal_intrget(_ah) \
419 	((*(_ah)->ah_getInterrupts)((_ah)))
420 #define	ath_hal_intrpend(_ah) \
421 	((*(_ah)->ah_isInterruptPending)((_ah)))
422 #define	ath_hal_getisr(_ah, _pmask) \
423 	((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
424 #define	ath_hal_updatetxtriglevel(_ah, _inc) \
425 	((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
426 #define	ath_hal_setpower(_ah, _mode) \
427 	((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
428 #define	ath_hal_keycachesize(_ah) \
429 	((*(_ah)->ah_getKeyCacheSize)((_ah)))
430 #define	ath_hal_keyreset(_ah, _ix) \
431 	((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
432 #define	ath_hal_keyset(_ah, _ix, _pk, _mac) \
433 	((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
434 #define	ath_hal_keyisvalid(_ah, _ix) \
435 	(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
436 #define	ath_hal_keysetmac(_ah, _ix, _mac) \
437 	((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
438 #define	ath_hal_getrxfilter(_ah) \
439 	((*(_ah)->ah_getRxFilter)((_ah)))
440 #define	ath_hal_setrxfilter(_ah, _filter) \
441 	((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
442 #define	ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
443 	((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
444 #define	ath_hal_waitforbeacon(_ah, _bf) \
445 	((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
446 #define	ath_hal_putrxbuf(_ah, _bufaddr) \
447 	((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
448 /* NB: common across all chips */
449 #define	AR_TSF_L32	0x804c	/* MAC local clock lower 32 bits */
450 #define	ath_hal_gettsf32(_ah) \
451 	OS_REG_READ(_ah, AR_TSF_L32)
452 #define	ath_hal_gettsf64(_ah) \
453 	((*(_ah)->ah_getTsf64)((_ah)))
454 #define	ath_hal_resettsf(_ah) \
455 	((*(_ah)->ah_resetTsf)((_ah)))
456 #define	ath_hal_rxena(_ah) \
457 	((*(_ah)->ah_enableReceive)((_ah)))
458 #define	ath_hal_puttxbuf(_ah, _q, _bufaddr) \
459 	((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
460 #define	ath_hal_gettxbuf(_ah, _q) \
461 	((*(_ah)->ah_getTxDP)((_ah), (_q)))
462 #define	ath_hal_numtxpending(_ah, _q) \
463 	((*(_ah)->ah_numTxPending)((_ah), (_q)))
464 #define	ath_hal_getrxbuf(_ah) \
465 	((*(_ah)->ah_getRxDP)((_ah)))
466 #define	ath_hal_txstart(_ah, _q) \
467 	((*(_ah)->ah_startTxDma)((_ah), (_q)))
468 #define	ath_hal_setchannel(_ah, _chan) \
469 	((*(_ah)->ah_setChannel)((_ah), (_chan)))
470 #define	ath_hal_calibrate(_ah, _chan, _iqcal) \
471 	((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
472 #define	ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \
473 	((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
474 #define	ath_hal_calreset(_ah, _chan) \
475 	((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
476 #define	ath_hal_setledstate(_ah, _state) \
477 	((*(_ah)->ah_setLedState)((_ah), (_state)))
478 #define	ath_hal_beaconinit(_ah, _nextb, _bperiod) \
479 	((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
480 #define	ath_hal_beaconreset(_ah) \
481 	((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
482 #define	ath_hal_beaconsettimers(_ah, _bt) \
483 	((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
484 #define	ath_hal_beacontimers(_ah, _bs) \
485 	((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
486 #define	ath_hal_getnexttbtt(_ah) \
487 	((*(_ah)->ah_getNextTBTT)((_ah)))
488 #define	ath_hal_setassocid(_ah, _bss, _associd) \
489 	((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
490 #define	ath_hal_phydisable(_ah) \
491 	((*(_ah)->ah_phyDisable)((_ah)))
492 #define	ath_hal_setopmode(_ah) \
493 	((*(_ah)->ah_setPCUConfig)((_ah)))
494 #define	ath_hal_stoptxdma(_ah, _qnum) \
495 	((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
496 #define	ath_hal_stoppcurecv(_ah) \
497 	((*(_ah)->ah_stopPcuReceive)((_ah)))
498 #define	ath_hal_startpcurecv(_ah) \
499 	((*(_ah)->ah_startPcuReceive)((_ah)))
500 #define	ath_hal_stopdmarecv(_ah) \
501 	((*(_ah)->ah_stopDmaReceive)((_ah)))
502 #define	ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
503 	((*(_ah)->ah_getDiagState)((_ah), (_id), \
504 		(_indata), (_insize), (_outdata), (_outsize)))
505 #define	ath_hal_getfatalstate(_ah, _outdata, _outsize) \
506 	ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
507 #define	ath_hal_setuptxqueue(_ah, _type, _irq) \
508 	((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
509 #define	ath_hal_resettxqueue(_ah, _q) \
510 	((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
511 #define	ath_hal_releasetxqueue(_ah, _q) \
512 	((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
513 #define	ath_hal_gettxqueueprops(_ah, _q, _qi) \
514 	((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
515 #define	ath_hal_settxqueueprops(_ah, _q, _qi) \
516 	((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
517 /* NB: common across all chips */
518 #define	AR_Q_TXE	0x0840	/* MAC Transmit Queue enable */
519 #define	ath_hal_txqenabled(_ah, _qnum) \
520 	(OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum)))
521 #define	ath_hal_getrfgain(_ah) \
522 	((*(_ah)->ah_getRfGain)((_ah)))
523 #define	ath_hal_getdefantenna(_ah) \
524 	((*(_ah)->ah_getDefAntenna)((_ah)))
525 #define	ath_hal_setdefantenna(_ah, _ant) \
526 	((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
527 #define	ath_hal_rxmonitor(_ah, _arg, _chan) \
528 	((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
529 #define	ath_hal_ani_poll(_ah, _chan) \
530 	((*(_ah)->ah_aniPoll)((_ah), (_chan)))
531 #define	ath_hal_mibevent(_ah, _stats) \
532 	((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
533 #define	ath_hal_setslottime(_ah, _us) \
534 	((*(_ah)->ah_setSlotTime)((_ah), (_us)))
535 #define	ath_hal_getslottime(_ah) \
536 	((*(_ah)->ah_getSlotTime)((_ah)))
537 #define	ath_hal_setacktimeout(_ah, _us) \
538 	((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
539 #define	ath_hal_getacktimeout(_ah) \
540 	((*(_ah)->ah_getAckTimeout)((_ah)))
541 #define	ath_hal_setctstimeout(_ah, _us) \
542 	((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
543 #define	ath_hal_getctstimeout(_ah) \
544 	((*(_ah)->ah_getCTSTimeout)((_ah)))
545 #define	ath_hal_getcapability(_ah, _cap, _param, _result) \
546 	((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
547 #define	ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
548 	((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
549 #define	ath_hal_ciphersupported(_ah, _cipher) \
550 	(ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
551 #define	ath_hal_getregdomain(_ah, _prd) \
552 	(ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
553 #define	ath_hal_setregdomain(_ah, _rd) \
554 	ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
555 #define	ath_hal_getcountrycode(_ah, _pcc) \
556 	(*(_pcc) = (_ah)->ah_countryCode)
557 #define	ath_hal_gettkipmic(_ah) \
558 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
559 #define	ath_hal_settkipmic(_ah, _v) \
560 	ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
561 #define	ath_hal_hastkipsplit(_ah) \
562 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
563 #define	ath_hal_gettkipsplit(_ah) \
564 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
565 #define	ath_hal_settkipsplit(_ah, _v) \
566 	ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
567 #define	ath_hal_haswmetkipmic(_ah) \
568 	(ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
569 #define	ath_hal_hwphycounters(_ah) \
570 	(ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
571 #define	ath_hal_hasdiversity(_ah) \
572 	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
573 #define	ath_hal_getdiversity(_ah) \
574 	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
575 #define	ath_hal_setdiversity(_ah, _v) \
576 	ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
577 #define	ath_hal_getantennaswitch(_ah) \
578 	((*(_ah)->ah_getAntennaSwitch)((_ah)))
579 #define	ath_hal_setantennaswitch(_ah, _v) \
580 	((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
581 #define	ath_hal_getdiag(_ah, _pv) \
582 	(ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
583 #define	ath_hal_setdiag(_ah, _v) \
584 	ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
585 #define	ath_hal_getnumtxqueues(_ah, _pv) \
586 	(ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
587 #define	ath_hal_hasveol(_ah) \
588 	(ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
589 #define	ath_hal_hastxpowlimit(_ah) \
590 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
591 #define	ath_hal_settxpowlimit(_ah, _pow) \
592 	((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
593 #define	ath_hal_gettxpowlimit(_ah, _ppow) \
594 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
595 #define	ath_hal_getmaxtxpow(_ah, _ppow) \
596 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
597 #define	ath_hal_gettpscale(_ah, _scale) \
598 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
599 #define	ath_hal_settpscale(_ah, _v) \
600 	ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
601 #define	ath_hal_hastpc(_ah) \
602 	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
603 #define	ath_hal_gettpc(_ah) \
604 	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
605 #define	ath_hal_settpc(_ah, _v) \
606 	ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
607 #define	ath_hal_hasbursting(_ah) \
608 	(ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
609 #define	ath_hal_setmcastkeysearch(_ah, _v) \
610 	ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL)
611 #define	ath_hal_hasmcastkeysearch(_ah) \
612 	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
613 #define	ath_hal_getmcastkeysearch(_ah) \
614 	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
615 #define	ath_hal_hasfastframes(_ah) \
616 	(ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
617 #define	ath_hal_hasbssidmask(_ah) \
618 	(ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
619 #define	ath_hal_hasbssidmatch(_ah) \
620 	(ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK)
621 #define	ath_hal_hastsfadjust(_ah) \
622 	(ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
623 #define	ath_hal_gettsfadjust(_ah) \
624 	(ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
625 #define	ath_hal_settsfadjust(_ah, _onoff) \
626 	ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
627 #define	ath_hal_hasrfsilent(_ah) \
628 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
629 #define	ath_hal_getrfkill(_ah) \
630 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
631 #define	ath_hal_setrfkill(_ah, _onoff) \
632 	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
633 #define	ath_hal_getrfsilent(_ah, _prfsilent) \
634 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
635 #define	ath_hal_setrfsilent(_ah, _rfsilent) \
636 	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
637 #define	ath_hal_gettpack(_ah, _ptpack) \
638 	(ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
639 #define	ath_hal_settpack(_ah, _tpack) \
640 	ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
641 #define	ath_hal_gettpcts(_ah, _ptpcts) \
642 	(ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
643 #define	ath_hal_settpcts(_ah, _tpcts) \
644 	ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
645 #define	ath_hal_hasintmit(_ah) \
646 	(ath_hal_getcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK)
647 #define	ath_hal_getintmit(_ah) \
648 	(ath_hal_getcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK)
649 #define	ath_hal_setintmit(_ah, _v) \
650 	ath_hal_setcapability(_ah, HAL_CAP_INTMIT, HAL_CAP_INTMIT_ENABLE, _v, NULL)
651 #define	ath_hal_getchannoise(_ah, _c) \
652 	((*(_ah)->ah_getChanNoise)((_ah), (_c)))
653 #define	ath_hal_getrxchainmask(_ah, _prxchainmask) \
654 	(ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask))
655 #define	ath_hal_gettxchainmask(_ah, _ptxchainmask) \
656 	(ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask))
657 #define	ath_hal_split4ktrans(_ah) \
658 	(ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, 0, NULL) == HAL_OK)
659 #define	ath_hal_self_linked_final_rxdesc(_ah) \
660 	(ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, 0, NULL) == HAL_OK)
661 #define	ath_hal_gtxto_supported(_ah) \
662 	(ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK)
663 #define	ath_hal_has_long_rxdesc_tsf(_ah) \
664 	(ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, 0, NULL) == HAL_OK)
665 
666 #define	ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
667 	((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
668 #define	ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
669 	((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
670 #define	ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
671 		_txr0, _txtr0, _keyix, _ant, _flags, \
672 		_rtsrate, _rtsdura) \
673 	((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
674 		(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
675 		(_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
676 #define	ath_hal_setupxtxdesc(_ah, _ds, \
677 		_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
678 	((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
679 		(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
680 #define	ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
681 	((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
682 #define	ath_hal_txprocdesc(_ah, _ds, _ts) \
683 	((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
684 #define	ath_hal_gettxintrtxqs(_ah, _txqs) \
685 	((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
686 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \
687 	((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries)))
688 
689 #define	ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \
690 	_cipher, _delims, _seglen, _first, _last) \
691 	((*(_ah)->ah_chainTxDesc((_ah), (_ds), (_pktlen), (_hdrlen), \
692 	(_type), (_keyix), (_cipher), (_delims), (_seglen), \
693 	(_first), (_last))))
694 #define	ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \
695 		_txr0, _txtr0, _antm, _rcr, _rcd) \
696 	((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \
697 	(_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd)))
698 #define	ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \
699 	((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0)))
700 #define	ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \
701 	((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \
702 	(_series), (_ns), (_flags)))
703 #define	ath_hal_set11naggrmiddle(_ah, _ds, _num) \
704 	((*(_ah)->ah_set11nAggrMiddle((_ah), (_ds), (_num))))
705 #define	ath_hal_set11nburstduration(_ah, _ds, _dur) \
706 	((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur)))
707 
708 /*
709  * This is badly-named; you need to set the correct parameters
710  * to begin to receive useful radar events; and even then
711  * it doesn't "enable" DFS. See the ath_dfs/null/ module for
712  * more information.
713  */
714 #define	ath_hal_enabledfs(_ah, _param) \
715 	((*(_ah)->ah_enableDfs)((_ah), (_param)))
716 #define	ath_hal_getdfsthresh(_ah, _param) \
717 	((*(_ah)->ah_getDfsThresh)((_ah), (_param)))
718 #define	ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \
719 	((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), (_buf), (_event)))
720 #define	ath_hal_is_fast_clock_enabled(_ah) \
721 	((*(_ah)->ah_isFastClockEnabled)((_ah)))
722 
723 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
724         ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
725 #define ath_hal_gpioset(_ah, _gpio, _b) \
726         ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
727 #define ath_hal_gpioget(_ah, _gpio) \
728         ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
729 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \
730         ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
731 
732 #define ath_hal_radar_wait(_ah, _chan) \
733 	((*(_ah)->ah_radarWait)((_ah), (_chan)))
734 
735 #endif /* _DEV_ATH_ATHVAR_H */
736