xref: /freebsd/sys/dev/ath/if_athvar.h (revision 7660b554bc59a07be0431c17e0e33815818baa69)
1 /*-
2  * Copyright (c) 2002, 2003 Sam Leffler, Errno Consulting
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification.
11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13  *    redistribution must be conditioned upon including a substantially
14  *    similar Disclaimer requirement for further binary redistribution.
15  * 3. Neither the names of the above-listed copyright holders nor the names
16  *    of any contributors may be used to endorse or promote products derived
17  *    from this software without specific prior written permission.
18  *
19  * Alternatively, this software may be distributed under the terms of the
20  * GNU General Public License ("GPL") version 2 as published by the Free
21  * Software Foundation.
22  *
23  * NO WARRANTY
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34  * THE POSSIBILITY OF SUCH DAMAGES.
35  *
36  * $FreeBSD$
37  */
38 
39 /*
40  * Defintions for the Atheros Wireless LAN controller driver.
41  */
42 #ifndef _DEV_ATH_ATHVAR_H
43 #define _DEV_ATH_ATHVAR_H
44 
45 #include <sys/taskqueue.h>
46 
47 #include <contrib/dev/ath/ah.h>
48 #include <net80211/ieee80211_radiotap.h>
49 #include <dev/ath/if_athioctl.h>
50 
51 #define	ATH_TIMEOUT		1000
52 
53 #define	ATH_RXBUF	40		/* number of RX buffers */
54 #define	ATH_TXBUF	60		/* number of TX buffers */
55 #define	ATH_TXDESC	8		/* number of descriptors per buffer */
56 
57 struct ath_recv_hist {
58 	int		arh_ticks;	/* sample time by system clock */
59 	u_int8_t	arh_rssi;	/* rssi */
60 	u_int8_t	arh_antenna;	/* antenna */
61 };
62 #define	ATH_RHIST_SIZE		16	/* number of samples */
63 #define	ATH_RHIST_NOTIME	(~0)
64 
65 /* driver-specific node */
66 struct ath_node {
67 	struct ieee80211_node an_node;	/* base class */
68 	u_int		an_tx_ok;	/* tx ok pkt */
69 	u_int		an_tx_err;	/* tx !ok pkt */
70 	u_int		an_tx_retr;	/* tx retry count */
71 	int		an_tx_upper;	/* tx upper rate req cnt */
72 	u_int		an_tx_antenna;	/* antenna for last good frame */
73 	u_int		an_rx_antenna;	/* antenna for last rcvd frame */
74 	struct ath_recv_hist an_rx_hist[ATH_RHIST_SIZE];
75 	u_int		an_rx_hist_next;/* index of next ``free entry'' */
76 };
77 #define	ATH_NODE(_n)	((struct ath_node *)(_n))
78 
79 struct ath_buf {
80 	TAILQ_ENTRY(ath_buf)	bf_list;
81 	int			bf_nseg;
82 	bus_dmamap_t		bf_dmamap;	/* DMA map of the buffer */
83 	struct ath_desc		*bf_desc;	/* virtual addr of desc */
84 	bus_addr_t		bf_daddr;	/* physical addr of desc */
85 	struct mbuf		*bf_m;		/* mbuf for buf */
86 	struct ieee80211_node	*bf_node;	/* pointer to the node */
87 	bus_size_t		bf_mapsize;
88 #define	ATH_MAX_SCATTER		64
89 	bus_dma_segment_t	bf_segs[ATH_MAX_SCATTER];
90 };
91 
92 struct ath_softc {
93 	struct ieee80211com	sc_ic;		/* IEEE 802.11 common */
94 	int			(*sc_newstate)(struct ieee80211com *,
95 					enum ieee80211_state, int);
96 	device_t		sc_dev;
97 	bus_space_tag_t		sc_st;		/* bus space tag */
98 	bus_space_handle_t	sc_sh;		/* bus space handle */
99 	bus_dma_tag_t		sc_dmat;	/* bus DMA tag */
100 	struct mtx		sc_mtx;		/* master lock (recursive) */
101 	struct ath_hal		*sc_ah;		/* Atheros HAL */
102 	unsigned int		sc_invalid  : 1,/* disable hardware accesses */
103 				sc_doani    : 1,/* dynamic noise immunity */
104 				sc_probing  : 1;/* probing AP on beacon miss */
105 						/* rate tables */
106 	const HAL_RATE_TABLE	*sc_rates[IEEE80211_MODE_MAX];
107 	const HAL_RATE_TABLE	*sc_currates;	/* current rate table */
108 	enum ieee80211_phymode	sc_curmode;	/* current phy mode */
109 	u_int8_t		sc_rixmap[256];	/* IEEE to h/w rate table ix */
110 	u_int8_t		sc_hwmap[32];	/* h/w rate ix to IEEE table */
111 	HAL_INT			sc_imask;	/* interrupt mask copy */
112 
113 	struct bpf_if		*sc_drvbpf;
114 	union {
115 		struct ath_tx_radiotap_header th;
116 		u_int8_t	pad[64];
117 	} u_tx_rt;
118 	union {
119 		struct ath_rx_radiotap_header th;
120 		u_int8_t	pad[64];
121 	} u_rx_rt;
122 
123 	struct ath_desc		*sc_desc;	/* TX/RX descriptors */
124 	bus_dma_segment_t	sc_dseg;
125 	bus_dmamap_t		sc_ddmamap;	/* DMA map for descriptors */
126 	bus_addr_t		sc_desc_paddr;	/* physical addr of sc_desc */
127 	bus_addr_t		sc_desc_len;	/* size of sc_desc */
128 
129 	struct task		sc_fataltask;	/* fatal int processing */
130 	struct task		sc_rxorntask;	/* rxorn int processing */
131 
132 	TAILQ_HEAD(, ath_buf)	sc_rxbuf;	/* receive buffer */
133 	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
134 	struct task		sc_rxtask;	/* rx int processing */
135 
136 	u_int			sc_txhalq;	/* HAL q for outgoing frames */
137 	u_int32_t		*sc_txlink;	/* link ptr in last TX desc */
138 	int			sc_tx_timer;	/* transmit timeout */
139 	TAILQ_HEAD(, ath_buf)	sc_txbuf;	/* transmit buffer */
140 	struct mtx		sc_txbuflock;	/* txbuf lock */
141 	TAILQ_HEAD(, ath_buf)	sc_txq;		/* transmitting queue */
142 	struct mtx		sc_txqlock;	/* lock on txq and txlink */
143 	struct task		sc_txtask;	/* tx int processing */
144 
145 	u_int			sc_bhalq;	/* HAL q for outgoing beacons */
146 	struct ath_buf		*sc_bcbuf;	/* beacon buffer */
147 	struct ath_buf		*sc_bufptr;	/* allocated buffer ptr */
148 	struct task		sc_swbatask;	/* swba int processing */
149 	struct task		sc_bmisstask;	/* bmiss int processing */
150 
151 	struct callout		sc_cal_ch;	/* callout handle for cals */
152 	struct callout		sc_scan_ch;	/* callout handle for scan */
153 	struct ath_stats	sc_stats;	/* interface statistics */
154 };
155 #define	sc_tx_th		u_tx_rt.th
156 #define	sc_rx_th		u_rx_rt.th
157 
158 int	ath_attach(u_int16_t, struct ath_softc *);
159 int	ath_detach(struct ath_softc *);
160 void	ath_resume(struct ath_softc *);
161 void	ath_suspend(struct ath_softc *);
162 void	ath_shutdown(struct ath_softc *);
163 void	ath_intr(void *);
164 
165 /*
166  * HAL definitions to comply with local coding convention.
167  */
168 #define	ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
169 	((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
170 #define	ath_hal_getratetable(_ah, _mode) \
171 	((*(_ah)->ah_getRateTable)((_ah), (_mode)))
172 #define	ath_hal_getregdomain(_ah) \
173 	((*(_ah)->ah_getRegDomain)((_ah)))
174 #define	ath_hal_getcountrycode(_ah)	(_ah)->ah_countryCode
175 #define	ath_hal_getmac(_ah, _mac) \
176 	((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
177 #define	ath_hal_detach(_ah) \
178 	((*(_ah)->ah_detach)((_ah)))
179 #define	ath_hal_intrset(_ah, _mask) \
180 	((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
181 #define	ath_hal_intrget(_ah) \
182 	((*(_ah)->ah_getInterrupts)((_ah)))
183 #define	ath_hal_intrpend(_ah) \
184 	((*(_ah)->ah_isInterruptPending)((_ah)))
185 #define	ath_hal_getisr(_ah, _pmask) \
186 	((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
187 #define	ath_hal_updatetxtriglevel(_ah, _inc) \
188 	((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
189 #define	ath_hal_setpower(_ah, _mode, _sleepduration) \
190 	((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration)))
191 #define	ath_hal_keyreset(_ah, _ix) \
192 	((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
193 #define	ath_hal_keyset(_ah, _ix, _pk) \
194 	((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), NULL, AH_FALSE))
195 #define	ath_hal_keyisvalid(_ah, _ix) \
196 	(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
197 #define	ath_hal_keysetmac(_ah, _ix, _mac) \
198 	((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
199 #define	ath_hal_getrxfilter(_ah) \
200 	((*(_ah)->ah_getRxFilter)((_ah)))
201 #define	ath_hal_setrxfilter(_ah, _filter) \
202 	((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
203 #define	ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
204 	((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
205 #define	ath_hal_waitforbeacon(_ah, _bf) \
206 	((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
207 #define	ath_hal_putrxbuf(_ah, _bufaddr) \
208 	((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
209 #define	ath_hal_gettsf32(_ah) \
210 	((*(_ah)->ah_getTsf32)((_ah)))
211 #define	ath_hal_gettsf64(_ah) \
212 	((*(_ah)->ah_getTsf64)((_ah)))
213 #define	ath_hal_resettsf(_ah) \
214 	((*(_ah)->ah_resetTsf)((_ah)))
215 #define	ath_hal_rxena(_ah) \
216 	((*(_ah)->ah_enableReceive)((_ah)))
217 #define	ath_hal_puttxbuf(_ah, _q, _bufaddr) \
218 	((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
219 #define	ath_hal_gettxbuf(_ah, _q) \
220 	((*(_ah)->ah_getTxDP)((_ah), (_q)))
221 #define	ath_hal_getrxbuf(_ah) \
222 	((*(_ah)->ah_getRxDP)((_ah)))
223 #define	ath_hal_txstart(_ah, _q) \
224 	((*(_ah)->ah_startTxDma)((_ah), (_q)))
225 #define	ath_hal_setchannel(_ah, _chan) \
226 	((*(_ah)->ah_setChannel)((_ah), (_chan)))
227 #define	ath_hal_calibrate(_ah, _chan) \
228 	((*(_ah)->ah_perCalibration)((_ah), (_chan)))
229 #define	ath_hal_setledstate(_ah, _state) \
230 	((*(_ah)->ah_setLedState)((_ah), (_state)))
231 #define	ath_hal_beaconinit(_ah, _opmode, _nextb, _bperiod) \
232 	((*(_ah)->ah_beaconInit)((_ah), (_opmode), (_nextb), (_bperiod)))
233 #define	ath_hal_beaconreset(_ah) \
234 	((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
235 #define	ath_hal_beacontimers(_ah, _bs, _tsf, _dc, _cc) \
236 	((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs), (_tsf), \
237 		(_dc), (_cc)))
238 #define	ath_hal_setassocid(_ah, _bss, _associd) \
239 	((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd), 0))
240 #define	ath_hal_setopmode(_ah, _opmode) \
241 	((*(_ah)->ah_setPCUConfig)((_ah), (_opmode)))
242 #define	ath_hal_stoptxdma(_ah, _qnum) \
243 	((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
244 #define	ath_hal_stoppcurecv(_ah) \
245 	((*(_ah)->ah_stopPcuReceive)((_ah)))
246 #define	ath_hal_startpcurecv(_ah) \
247 	((*(_ah)->ah_startPcuReceive)((_ah)))
248 #define	ath_hal_stopdmarecv(_ah) \
249 	((*(_ah)->ah_stopDmaReceive)((_ah)))
250 #define	ath_hal_dumpstate(_ah) \
251 	((*(_ah)->ah_dumpState)((_ah)))
252 #define	ath_hal_dumpeeprom(_ah) \
253 	((*(_ah)->ah_dumpEeprom)((_ah)))
254 #define	ath_hal_dumprfgain(_ah) \
255 	((*(_ah)->ah_dumpRfGain)((_ah)))
256 #define	ath_hal_dumpani(_ah) \
257 	((*(_ah)->ah_dumpAni)((_ah)))
258 #define	ath_hal_setuptxqueue(_ah, _type, _irq) \
259 	((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
260 #define	ath_hal_resettxqueue(_ah, _q) \
261 	((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
262 #define	ath_hal_releasetxqueue(_ah, _q) \
263 	((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
264 #define	ath_hal_hasveol(_ah) \
265 	((*(_ah)->ah_hasVEOL)((_ah)))
266 #define	ath_hal_getrfgain(_ah) \
267 	((*(_ah)->ah_getRfGain)((_ah)))
268 #define	ath_hal_rxmonitor(_ah) \
269 	((*(_ah)->ah_rxMonitor)((_ah)))
270 
271 #define	ath_hal_setupbeacondesc(_ah, _ds, _opmode, _flen, _hlen, \
272 		_rate, _antmode) \
273 	((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \
274 		(_flen), (_hlen), (_rate), (_antmode)))
275 #define	ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
276 	((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
277 #define	ath_hal_rxprocdesc(_ah, _ds) \
278 	((*(_ah)->ah_procRxDesc)((_ah), (_ds)))
279 #define	ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
280 		_txr0, _txtr0, _keyix, _ant, _flags, \
281 		_rtsrate, _rtsdura) \
282 	((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
283 		(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
284 		(_flags), (_rtsrate), (_rtsdura)))
285 #define	ath_hal_setupxtxdesc(_ah, _ds, _short, \
286 		_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
287 	((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), (_short), \
288 		(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
289 #define	ath_hal_filltxdesc(_ah, _ds, _l, _first, _last) \
290 	((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last)))
291 #define	ath_hal_txprocdesc(_ah, _ds) \
292 	((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
293 
294 #endif /* _DEV_ATH_ATHVAR_H */
295