1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35 #ifndef _DEV_ATH_ATHVAR_H 36 #define _DEV_ATH_ATHVAR_H 37 38 #include <machine/atomic.h> 39 40 #include <dev/ath/ath_hal/ah.h> 41 #include <dev/ath/ath_hal/ah_desc.h> 42 #include <net80211/ieee80211_radiotap.h> 43 #include <dev/ath/if_athioctl.h> 44 #include <dev/ath/if_athrate.h> 45 #ifdef ATH_DEBUG_ALQ 46 #include <dev/ath/if_ath_alq.h> 47 #endif 48 49 #define ATH_TIMEOUT 1000 50 51 /* 52 * There is a separate TX ath_buf pool for management frames. 53 * This ensures that management frames such as probe responses 54 * and BAR frames can be transmitted during periods of high 55 * TX activity. 56 */ 57 #define ATH_MGMT_TXBUF 32 58 59 /* 60 * 802.11n requires more TX and RX buffers to do AMPDU. 61 */ 62 #ifdef ATH_ENABLE_11N 63 #define ATH_TXBUF 512 64 #define ATH_RXBUF 512 65 #endif 66 67 #ifndef ATH_RXBUF 68 #define ATH_RXBUF 40 /* number of RX buffers */ 69 #endif 70 #ifndef ATH_TXBUF 71 #define ATH_TXBUF 200 /* number of TX buffers */ 72 #endif 73 #define ATH_BCBUF 4 /* number of beacon buffers */ 74 75 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 76 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 77 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 78 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 79 80 #define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 81 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 82 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 83 84 /* 85 * The key cache is used for h/w cipher state and also for 86 * tracking station state such as the current tx antenna. 87 * We also setup a mapping table between key cache slot indices 88 * and station state to short-circuit node lookups on rx. 89 * Different parts have different size key caches. We handle 90 * up to ATH_KEYMAX entries (could dynamically allocate state). 91 */ 92 #define ATH_KEYMAX 128 /* max key cache size we handle */ 93 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 94 95 struct taskqueue; 96 struct kthread; 97 struct ath_buf; 98 99 #define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 100 101 /* 102 * Per-TID state 103 * 104 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 105 */ 106 struct ath_tid { 107 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 108 struct ath_node *an; /* pointer to parent */ 109 int tid; /* tid */ 110 int ac; /* which AC gets this trafic */ 111 int hwq_depth; /* how many buffers are on HW */ 112 u_int axq_depth; /* SW queue depth */ 113 114 struct { 115 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 116 u_int axq_depth; /* SW queue depth */ 117 } filtq; 118 119 /* 120 * Entry on the ath_txq; when there's traffic 121 * to send 122 */ 123 TAILQ_ENTRY(ath_tid) axq_qelem; 124 int sched; 125 int paused; /* >0 if the TID has been paused */ 126 127 /* 128 * These are flags - perhaps later collapse 129 * down to a single uint32_t ? 130 */ 131 int addba_tx_pending; /* TX ADDBA pending */ 132 int bar_wait; /* waiting for BAR */ 133 int bar_tx; /* BAR TXed */ 134 int isfiltered; /* is this node currently filtered */ 135 136 /* 137 * Is the TID being cleaned up after a transition 138 * from aggregation to non-aggregation? 139 * When this is set to 1, this TID will be paused 140 * and no further traffic will be queued until all 141 * the hardware packets pending for this TID have been 142 * TXed/completed; at which point (non-aggregation) 143 * traffic will resume being TXed. 144 */ 145 int cleanup_inprogress; 146 /* 147 * How many hardware-queued packets are 148 * waiting to be cleaned up. 149 * This is only valid if cleanup_inprogress is 1. 150 */ 151 int incomp; 152 153 /* 154 * The following implements a ring representing 155 * the frames in the current BAW. 156 * To avoid copying the array content each time 157 * the BAW is moved, the baw_head/baw_tail point 158 * to the current BAW begin/end; when the BAW is 159 * shifted the head/tail of the array are also 160 * appropriately shifted. 161 */ 162 /* active tx buffers, beginning at current BAW */ 163 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 164 /* where the baw head is in the array */ 165 int baw_head; 166 /* where the BAW tail is in the array */ 167 int baw_tail; 168 }; 169 170 /* driver-specific node state */ 171 struct ath_node { 172 struct ieee80211_node an_node; /* base class */ 173 u_int8_t an_mgmtrix; /* min h/w rate index */ 174 u_int8_t an_mcastrix; /* mcast h/w rate index */ 175 uint32_t an_is_powersave; /* node is sleeping */ 176 uint32_t an_stack_psq; /* net80211 psq isn't empty */ 177 uint32_t an_tim_set; /* TIM has been set */ 178 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 179 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 180 char an_name[32]; /* eg "wlan0_a1" */ 181 struct mtx an_mtx; /* protecting the ath_node state */ 182 uint32_t an_swq_depth; /* how many SWQ packets for this 183 node */ 184 int clrdmask; /* has clrdmask been set */ 185 /* variable-length rate control state follows */ 186 }; 187 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 188 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 189 190 #define ATH_RSSI_LPF_LEN 10 191 #define ATH_RSSI_DUMMY_MARKER 0x127 192 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 193 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 194 #define ATH_LPF_RSSI(x, y, len) \ 195 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 196 #define ATH_RSSI_LPF(x, y) do { \ 197 if ((y) >= -20) \ 198 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 199 } while (0) 200 #define ATH_EP_RND(x,mul) \ 201 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 202 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 203 204 typedef enum { 205 ATH_BUFTYPE_NORMAL = 0, 206 ATH_BUFTYPE_MGMT = 1, 207 } ath_buf_type_t; 208 209 struct ath_buf { 210 TAILQ_ENTRY(ath_buf) bf_list; 211 struct ath_buf * bf_next; /* next buffer in the aggregate */ 212 int bf_nseg; 213 HAL_STATUS bf_rxstatus; 214 uint16_t bf_flags; /* status flags (below) */ 215 uint16_t bf_descid; /* 16 bit descriptor ID */ 216 struct ath_desc *bf_desc; /* virtual addr of desc */ 217 struct ath_desc_status bf_status; /* tx/rx status */ 218 bus_addr_t bf_daddr; /* physical addr of desc */ 219 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 220 struct mbuf *bf_m; /* mbuf for buf */ 221 struct ieee80211_node *bf_node; /* pointer to the node */ 222 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 223 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 224 bus_size_t bf_mapsize; 225 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 226 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 227 228 /* Completion function to call on TX complete (fail or not) */ 229 /* 230 * "fail" here is set to 1 if the queue entries were removed 231 * through a call to ath_tx_draintxq(). 232 */ 233 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 234 235 /* This state is kept to support software retries and aggregation */ 236 struct { 237 uint16_t bfs_seqno; /* sequence number of this packet */ 238 uint16_t bfs_ndelim; /* number of delims for padding */ 239 240 uint8_t bfs_retries; /* retry count */ 241 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 242 uint8_t bfs_nframes; /* number of frames in aggregate */ 243 uint8_t bfs_pri; /* packet AC priority */ 244 uint8_t bfs_tx_queue; /* destination hardware TX queue */ 245 246 u_int32_t bfs_aggr:1, /* part of aggregate? */ 247 bfs_aggrburst:1, /* part of aggregate burst? */ 248 bfs_isretried:1, /* retried frame? */ 249 bfs_dobaw:1, /* actually check against BAW? */ 250 bfs_addedbaw:1, /* has been added to the BAW */ 251 bfs_shpream:1, /* use short preamble */ 252 bfs_istxfrag:1, /* is fragmented */ 253 bfs_ismrr:1, /* do multi-rate TX retry */ 254 bfs_doprot:1, /* do RTS/CTS based protection */ 255 bfs_doratelookup:1; /* do rate lookup before each TX */ 256 257 /* 258 * These fields are passed into the 259 * descriptor setup functions. 260 */ 261 262 /* Make this an 8 bit value? */ 263 HAL_PKT_TYPE bfs_atype; /* packet type */ 264 265 uint32_t bfs_pktlen; /* length of this packet */ 266 267 uint16_t bfs_hdrlen; /* length of this packet header */ 268 uint16_t bfs_al; /* length of aggregate */ 269 270 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 271 uint8_t bfs_txrate0; /* first TX rate */ 272 uint8_t bfs_try0; /* first try count */ 273 274 uint16_t bfs_txpower; /* tx power */ 275 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 276 uint8_t bfs_ctsrate; /* CTS rate */ 277 278 /* 16 bit? */ 279 int32_t bfs_keyix; /* crypto key index */ 280 int32_t bfs_txantenna; /* TX antenna config */ 281 282 /* Make this an 8 bit value? */ 283 enum ieee80211_protmode bfs_protmode; 284 285 /* 16 bit? */ 286 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 287 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 288 } bf_state; 289 }; 290 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 291 292 #define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 293 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 294 295 /* 296 * DMA state for tx/rx descriptors. 297 */ 298 struct ath_descdma { 299 const char* dd_name; 300 struct ath_desc *dd_desc; /* descriptors */ 301 int dd_descsize; /* size of single descriptor */ 302 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 303 bus_size_t dd_desc_len; /* size of dd_desc */ 304 bus_dma_segment_t dd_dseg; 305 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 306 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 307 struct ath_buf *dd_bufptr; /* associated buffers */ 308 }; 309 310 /* 311 * Data transmit queue state. One of these exists for each 312 * hardware transmit queue. Packets sent to us from above 313 * are assigned to queues based on their priority. Not all 314 * devices support a complete set of hardware transmit queues. 315 * For those devices the array sc_ac2q will map multiple 316 * priorities to fewer hardware queues (typically all to one 317 * hardware queue). 318 */ 319 struct ath_txq { 320 struct ath_softc *axq_softc; /* Needed for scheduling */ 321 u_int axq_qnum; /* hardware q number */ 322 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 323 u_int axq_ac; /* WME AC */ 324 u_int axq_flags; 325 #define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 326 u_int axq_depth; /* queue depth (stat only) */ 327 u_int axq_aggr_depth; /* how many aggregates are queued */ 328 u_int axq_fifo_depth; /* depth of FIFO frames */ 329 u_int axq_intrcnt; /* interrupt count */ 330 u_int32_t *axq_link; /* link ptr in last TX desc */ 331 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 332 struct mtx axq_lock; /* lock on q and link */ 333 334 /* 335 * XXX the holdingbf field is protected by the TXBUF lock 336 * for now, NOT the TXQ lock. 337 * 338 * Architecturally, it would likely be better to move 339 * the holdingbf field to a separate array in ath_softc 340 * just to highlight that it's not protected by the normal 341 * TX path lock. 342 */ 343 struct ath_buf *axq_holdingbf; /* holding TX buffer */ 344 char axq_name[12]; /* e.g. "ath0_txq4" */ 345 346 /* Per-TID traffic queue for software -> hardware TX */ 347 /* 348 * This is protected by the general TX path lock, not (for now) 349 * by the TXQ lock. 350 */ 351 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 352 }; 353 354 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 355 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 356 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 357 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 358 } while (0) 359 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 360 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 361 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 362 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 363 364 365 #define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 366 #define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 367 #define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 368 #define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 369 MA_NOTOWNED) 370 371 /* 372 * These are for the hardware queue. 373 */ 374 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 375 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 376 (_tq)->axq_depth++; \ 377 } while (0) 378 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 379 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 380 (_tq)->axq_depth++; \ 381 } while (0) 382 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 383 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 384 (_tq)->axq_depth--; \ 385 } while (0) 386 #define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 387 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 388 389 /* 390 * These are for the TID software queue. 391 */ 392 #define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 393 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 394 (_tq)->axq_depth++; \ 395 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 396 } while (0) 397 #define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 398 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 399 (_tq)->axq_depth++; \ 400 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 401 } while (0) 402 #define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 403 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 404 (_tq)->axq_depth--; \ 405 atomic_subtract_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 406 } while (0) 407 #define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 408 #define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 409 410 /* 411 * These are for the TID filtered frame queue 412 */ 413 #define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 414 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 415 (_tq)->axq_depth++; \ 416 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 417 } while (0) 418 #define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 419 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 420 (_tq)->axq_depth++; \ 421 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 422 } while (0) 423 #define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 424 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 425 (_tq)->axq_depth--; \ 426 atomic_subtract_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 427 } while (0) 428 #define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 429 #define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 430 431 struct ath_vap { 432 struct ieee80211vap av_vap; /* base class */ 433 int av_bslot; /* beacon slot index */ 434 struct ath_buf *av_bcbuf; /* beacon buffer */ 435 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 436 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 437 438 void (*av_recv_mgmt)(struct ieee80211_node *, 439 struct mbuf *, int, int, int); 440 int (*av_newstate)(struct ieee80211vap *, 441 enum ieee80211_state, int); 442 void (*av_bmiss)(struct ieee80211vap *); 443 void (*av_node_ps)(struct ieee80211_node *, int); 444 int (*av_set_tim)(struct ieee80211_node *, int); 445 }; 446 #define ATH_VAP(vap) ((struct ath_vap *)(vap)) 447 448 struct taskqueue; 449 struct ath_tx99; 450 451 /* 452 * Whether to reset the TX/RX queue with or without 453 * a queue flush. 454 */ 455 typedef enum { 456 ATH_RESET_DEFAULT = 0, 457 ATH_RESET_NOLOSS = 1, 458 ATH_RESET_FULL = 2, 459 } ATH_RESET_TYPE; 460 461 struct ath_rx_methods { 462 void (*recv_sched_queue)(struct ath_softc *sc, 463 HAL_RX_QUEUE q, int dosched); 464 void (*recv_sched)(struct ath_softc *sc, int dosched); 465 void (*recv_stop)(struct ath_softc *sc, int dodelay); 466 int (*recv_start)(struct ath_softc *sc); 467 void (*recv_flush)(struct ath_softc *sc); 468 void (*recv_tasklet)(void *arg, int npending); 469 int (*recv_rxbuf_init)(struct ath_softc *sc, 470 struct ath_buf *bf); 471 int (*recv_setup)(struct ath_softc *sc); 472 int (*recv_teardown)(struct ath_softc *sc); 473 }; 474 475 /* 476 * Represent the current state of the RX FIFO. 477 */ 478 struct ath_rx_edma { 479 struct ath_buf **m_fifo; 480 int m_fifolen; 481 int m_fifo_head; 482 int m_fifo_tail; 483 int m_fifo_depth; 484 struct mbuf *m_rxpending; 485 }; 486 487 struct ath_tx_edma_fifo { 488 struct ath_buf **m_fifo; 489 int m_fifolen; 490 int m_fifo_head; 491 int m_fifo_tail; 492 int m_fifo_depth; 493 }; 494 495 struct ath_tx_methods { 496 int (*xmit_setup)(struct ath_softc *sc); 497 int (*xmit_teardown)(struct ath_softc *sc); 498 void (*xmit_attach_comp_func)(struct ath_softc *sc); 499 500 void (*xmit_dma_restart)(struct ath_softc *sc, 501 struct ath_txq *txq); 502 void (*xmit_handoff)(struct ath_softc *sc, 503 struct ath_txq *txq, struct ath_buf *bf); 504 void (*xmit_drain)(struct ath_softc *sc, 505 ATH_RESET_TYPE reset_type); 506 }; 507 508 struct ath_softc { 509 struct ifnet *sc_ifp; /* interface common */ 510 struct ath_stats sc_stats; /* interface statistics */ 511 struct ath_tx_aggr_stats sc_aggr_stats; 512 struct ath_intr_stats sc_intr_stats; 513 uint64_t sc_debug; 514 uint64_t sc_ktrdebug; 515 int sc_nvaps; /* # vaps */ 516 int sc_nstavaps; /* # station vaps */ 517 int sc_nmeshvaps; /* # mbss vaps */ 518 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 519 u_int8_t sc_nbssid0; /* # vap's using base mac */ 520 uint32_t sc_bssidmask; /* bssid mask */ 521 522 struct ath_rx_methods sc_rx; 523 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 524 struct ath_tx_methods sc_tx; 525 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 526 527 /* 528 * This is (currently) protected by the TX queue lock; 529 * it should migrate to a separate lock later 530 * so as to minimise contention. 531 */ 532 ath_bufhead sc_txbuf_list; 533 534 int sc_rx_statuslen; 535 int sc_tx_desclen; 536 int sc_tx_statuslen; 537 int sc_tx_nmaps; /* Number of TX maps */ 538 int sc_edma_bufsize; 539 540 void (*sc_node_cleanup)(struct ieee80211_node *); 541 void (*sc_node_free)(struct ieee80211_node *); 542 device_t sc_dev; 543 HAL_BUS_TAG sc_st; /* bus space tag */ 544 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 545 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 546 struct mtx sc_mtx; /* master lock (recursive) */ 547 struct mtx sc_pcu_mtx; /* PCU access mutex */ 548 char sc_pcu_mtx_name[32]; 549 struct mtx sc_rx_mtx; /* RX access mutex */ 550 char sc_rx_mtx_name[32]; 551 struct mtx sc_tx_mtx; /* TX handling/comp mutex */ 552 char sc_tx_mtx_name[32]; 553 struct mtx sc_tx_ic_mtx; /* TX queue mutex */ 554 char sc_tx_ic_mtx_name[32]; 555 struct taskqueue *sc_tq; /* private task queue */ 556 struct ath_hal *sc_ah; /* Atheros HAL */ 557 struct ath_ratectrl *sc_rc; /* tx rate control support */ 558 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 559 void (*sc_setdefantenna)(struct ath_softc *, u_int); 560 561 /* 562 * First set of flags. 563 */ 564 uint32_t sc_invalid : 1,/* disable hardware accesses */ 565 sc_mrretry : 1,/* multi-rate retry support */ 566 sc_mrrprot : 1,/* MRR + protection support */ 567 sc_softled : 1,/* enable LED gpio status */ 568 sc_hardled : 1,/* enable MAC LED status */ 569 sc_splitmic : 1,/* split TKIP MIC keys */ 570 sc_needmib : 1,/* enable MIB stats intr */ 571 sc_diversity: 1,/* enable rx diversity */ 572 sc_hasveol : 1,/* tx VEOL support */ 573 sc_ledstate : 1,/* LED on/off state */ 574 sc_blinking : 1,/* LED blink operation active */ 575 sc_mcastkey : 1,/* mcast key cache search */ 576 sc_scanning : 1,/* scanning active */ 577 sc_syncbeacon:1,/* sync/resync beacon timers */ 578 sc_hasclrkey: 1,/* CLR key supported */ 579 sc_xchanmode: 1,/* extended channel mode */ 580 sc_outdoor : 1,/* outdoor operation */ 581 sc_dturbo : 1,/* dynamic turbo in use */ 582 sc_hasbmask : 1,/* bssid mask support */ 583 sc_hasbmatch: 1,/* bssid match disable support*/ 584 sc_hastsfadd: 1,/* tsf adjust support */ 585 sc_beacons : 1,/* beacons running */ 586 sc_swbmiss : 1,/* sta mode using sw bmiss */ 587 sc_stagbeacons:1,/* use staggered beacons */ 588 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 589 sc_resume_up: 1,/* on resume, start all vaps */ 590 sc_tdma : 1,/* TDMA in use */ 591 sc_setcca : 1,/* set/clr CCA with TDMA */ 592 sc_resetcal : 1,/* reset cal state next trip */ 593 sc_rxslink : 1,/* do self-linked final descriptor */ 594 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 595 sc_isedma : 1;/* supports EDMA */ 596 597 /* 598 * Second set of flags. 599 */ 600 u_int32_t sc_use_ent : 1, 601 sc_rx_stbc : 1, 602 sc_tx_stbc : 1; 603 604 605 int sc_cabq_enable; /* Enable cabq transmission */ 606 607 /* 608 * Enterprise mode configuration for AR9380 and later chipsets. 609 */ 610 uint32_t sc_ent_cfg; 611 612 uint32_t sc_eerd; /* regdomain from EEPROM */ 613 uint32_t sc_eecc; /* country code from EEPROM */ 614 /* rate tables */ 615 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 616 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 617 enum ieee80211_phymode sc_curmode; /* current phy mode */ 618 HAL_OPMODE sc_opmode; /* current operating mode */ 619 u_int16_t sc_curtxpow; /* current tx power limit */ 620 u_int16_t sc_curaid; /* current association id */ 621 struct ieee80211_channel *sc_curchan; /* current installed channel */ 622 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 623 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 624 struct { 625 u_int8_t ieeerate; /* IEEE rate */ 626 u_int8_t rxflags; /* radiotap rx flags */ 627 u_int8_t txflags; /* radiotap tx flags */ 628 u_int16_t ledon; /* softled on time */ 629 u_int16_t ledoff; /* softled off time */ 630 } sc_hwmap[32]; /* h/w rate ix mappings */ 631 u_int8_t sc_protrix; /* protection rate index */ 632 u_int8_t sc_lastdatarix; /* last data frame rate index */ 633 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 634 u_int sc_fftxqmin; /* min frames before staging */ 635 u_int sc_fftxqmax; /* max frames before drop */ 636 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 637 638 HAL_INT sc_imask; /* interrupt mask copy */ 639 640 /* 641 * These are modified in the interrupt handler as well as 642 * the task queues and other contexts. Thus these must be 643 * protected by a mutex, or they could clash. 644 * 645 * For now, access to these is behind the ATH_LOCK, 646 * just to save time. 647 */ 648 uint32_t sc_txq_active; /* bitmap of active TXQs */ 649 uint32_t sc_kickpcu; /* whether to kick the PCU */ 650 uint32_t sc_rxproc_cnt; /* In RX processing */ 651 uint32_t sc_txproc_cnt; /* In TX processing */ 652 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 653 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 654 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 655 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 656 657 u_int sc_keymax; /* size of key cache */ 658 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 659 660 /* 661 * Software based LED blinking 662 */ 663 u_int sc_ledpin; /* GPIO pin for driving LED */ 664 u_int sc_ledon; /* pin setting for LED on */ 665 u_int sc_ledidle; /* idle polling interval */ 666 int sc_ledevent; /* time of last LED event */ 667 u_int8_t sc_txrix; /* current tx rate for LED */ 668 u_int16_t sc_ledoff; /* off time for current blink */ 669 struct callout sc_ledtimer; /* led off timer */ 670 671 /* 672 * Hardware based LED blinking 673 */ 674 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 675 int sc_led_net_pin; /* MAC network LED GPIO pin */ 676 677 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 678 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 679 680 struct ath_descdma sc_rxdma; /* RX descriptors */ 681 ath_bufhead sc_rxbuf; /* receive buffer */ 682 ath_bufhead sc_rx_rxlist; /* deferred RX completion */ 683 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 684 struct task sc_rxtask; /* rx int processing */ 685 u_int8_t sc_defant; /* current default antenna */ 686 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 687 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 688 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 689 struct ath_rx_radiotap_header sc_rx_th; 690 int sc_rx_th_len; 691 u_int sc_monpass; /* frames to pass in mon.mode */ 692 693 struct ath_descdma sc_txdma; /* TX descriptors */ 694 uint16_t sc_txbuf_descid; 695 ath_bufhead sc_txbuf; /* transmit buffer */ 696 int sc_txbuf_cnt; /* how many buffers avail */ 697 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 698 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 699 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 700 struct mtx sc_txbuflock; /* txbuf lock */ 701 char sc_txname[12]; /* e.g. "ath0_buf" */ 702 u_int sc_txqsetup; /* h/w queues setup */ 703 u_int sc_txintrperiod;/* tx interrupt batching */ 704 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 705 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 706 struct task sc_txtask; /* tx int processing */ 707 struct task sc_txqtask; /* tx proc processing */ 708 struct task sc_txpkttask; /* tx frame processing */ 709 710 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 711 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 712 char sc_txcompname[12]; /* eg ath0_txcomp */ 713 714 int sc_wd_timer; /* count down for wd timer */ 715 struct callout sc_wd_ch; /* tx watchdog timer */ 716 struct ath_tx_radiotap_header sc_tx_th; 717 int sc_tx_th_len; 718 719 struct ath_descdma sc_bdma; /* beacon descriptors */ 720 ath_bufhead sc_bbuf; /* beacon buffers */ 721 u_int sc_bhalq; /* HAL q for outgoing beacons */ 722 u_int sc_bmisscount; /* missed beacon transmits */ 723 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 724 struct ath_txq *sc_cabq; /* tx q for cab frames */ 725 struct task sc_bmisstask; /* bmiss int processing */ 726 struct task sc_bstucktask; /* stuck beacon processing */ 727 struct task sc_resettask; /* interface reset task */ 728 struct task sc_fataltask; /* fatal task */ 729 enum { 730 OK, /* no change needed */ 731 UPDATE, /* update pending */ 732 COMMIT /* beacon sent, commit change */ 733 } sc_updateslot; /* slot time update fsm */ 734 int sc_slotupdate; /* slot to advance fsm */ 735 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 736 int sc_nbcnvaps; /* # vaps with beacons */ 737 738 struct callout sc_cal_ch; /* callout handle for cals */ 739 int sc_lastlongcal; /* last long cal completed */ 740 int sc_lastcalreset;/* last cal reset done */ 741 int sc_lastani; /* last ANI poll */ 742 int sc_lastshortcal; /* last short calibration */ 743 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 744 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 745 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 746 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 747 u_int sc_tdmaswba; /* TDMA SWBA counter */ 748 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 749 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 750 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 751 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 752 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 753 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 754 int sc_txchainmask; /* hardware TX chainmask */ 755 int sc_rxchainmask; /* hardware RX chainmask */ 756 int sc_cur_txchainmask; /* currently configured TX chainmask */ 757 int sc_cur_rxchainmask; /* currently configured RX chainmask */ 758 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 759 int sc_aggr_limit; /* TX limit on all aggregates */ 760 int sc_delim_min_pad; /* Minimum delimiter count */ 761 762 /* Queue limits */ 763 764 /* 765 * To avoid queue starvation in congested conditions, 766 * these parameters tune the maximum number of frames 767 * queued to the data/mcastq before they're dropped. 768 * 769 * This is to prevent: 770 * + a single destination overwhelming everything, including 771 * management/multicast frames; 772 * + multicast frames overwhelming everything (when the 773 * air is sufficiently busy that cabq can't drain.) 774 * 775 * These implement: 776 * + data_minfree is the maximum number of free buffers 777 * overall to successfully allow a data frame. 778 * 779 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 780 */ 781 int sc_txq_data_minfree; 782 int sc_txq_mcastq_maxdepth; 783 784 /* 785 * Aggregation twiddles 786 * 787 * hwq_limit: how busy to keep the hardware queue - don't schedule 788 * further packets to the hardware, regardless of the TID 789 * tid_hwq_lo: how low the per-TID hwq count has to be before the 790 * TID will be scheduled again 791 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 792 * stops being scheduled. 793 */ 794 int sc_hwq_limit; 795 int sc_tid_hwq_lo; 796 int sc_tid_hwq_hi; 797 798 /* DFS related state */ 799 void *sc_dfs; /* Used by an optional DFS module */ 800 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 801 struct task sc_dfstask; /* DFS processing task */ 802 803 /* Spectral related state */ 804 void *sc_spectral; 805 int sc_dospectral; 806 807 /* ALQ */ 808 #ifdef ATH_DEBUG_ALQ 809 struct if_ath_alq sc_alq; 810 #endif 811 812 /* TX AMPDU handling */ 813 int (*sc_addba_request)(struct ieee80211_node *, 814 struct ieee80211_tx_ampdu *, int, int, int); 815 int (*sc_addba_response)(struct ieee80211_node *, 816 struct ieee80211_tx_ampdu *, int, int, int); 817 void (*sc_addba_stop)(struct ieee80211_node *, 818 struct ieee80211_tx_ampdu *); 819 void (*sc_addba_response_timeout) 820 (struct ieee80211_node *, 821 struct ieee80211_tx_ampdu *); 822 void (*sc_bar_response)(struct ieee80211_node *ni, 823 struct ieee80211_tx_ampdu *tap, 824 int status); 825 }; 826 827 #define ATH_LOCK_INIT(_sc) \ 828 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 829 NULL, MTX_DEF | MTX_RECURSE) 830 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 831 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 832 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 833 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 834 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 835 836 /* 837 * The TX lock is non-reentrant and serialises the TX frame send 838 * and completion operations. 839 */ 840 #define ATH_TX_LOCK_INIT(_sc) do {\ 841 snprintf((_sc)->sc_tx_mtx_name, \ 842 sizeof((_sc)->sc_tx_mtx_name), \ 843 "%s TX lock", \ 844 device_get_nameunit((_sc)->sc_dev)); \ 845 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \ 846 NULL, MTX_DEF); \ 847 } while (0) 848 #define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx) 849 #define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx) 850 #define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx) 851 #define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 852 MA_OWNED) 853 #define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \ 854 MA_NOTOWNED) 855 #define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \ 856 mtx_trylock(&(_sc)->sc_tx_mtx)) 857 858 /* 859 * The IC TX lock is non-reentrant and serialises packet queuing from 860 * the upper layers. 861 */ 862 #define ATH_TX_IC_LOCK_INIT(_sc) do {\ 863 snprintf((_sc)->sc_tx_ic_mtx_name, \ 864 sizeof((_sc)->sc_tx_ic_mtx_name), \ 865 "%s IC TX lock", \ 866 device_get_nameunit((_sc)->sc_dev)); \ 867 mtx_init(&(_sc)->sc_tx_ic_mtx, (_sc)->sc_tx_ic_mtx_name, \ 868 NULL, MTX_DEF); \ 869 } while (0) 870 #define ATH_TX_IC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_ic_mtx) 871 #define ATH_TX_IC_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_ic_mtx) 872 #define ATH_TX_IC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_ic_mtx) 873 #define ATH_TX_IC_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_ic_mtx, \ 874 MA_OWNED) 875 #define ATH_TX_IC_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_ic_mtx, \ 876 MA_NOTOWNED) 877 878 /* 879 * The PCU lock is non-recursive and should be treated as a spinlock. 880 * Although currently the interrupt code is run in netisr context and 881 * doesn't require this, this may change in the future. 882 * Please keep this in mind when protecting certain code paths 883 * with the PCU lock. 884 * 885 * The PCU lock is used to serialise access to the PCU so things such 886 * as TX, RX, state change (eg channel change), channel reset and updates 887 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 888 * 889 * Although the current single-thread taskqueue mechanism protects the 890 * majority of these situations by simply serialising them, there are 891 * a few others which occur at the same time. These include the TX path 892 * (which only acquires ATH_LOCK when recycling buffers to the free list), 893 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 894 */ 895 #define ATH_PCU_LOCK_INIT(_sc) do {\ 896 snprintf((_sc)->sc_pcu_mtx_name, \ 897 sizeof((_sc)->sc_pcu_mtx_name), \ 898 "%s PCU lock", \ 899 device_get_nameunit((_sc)->sc_dev)); \ 900 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 901 NULL, MTX_DEF); \ 902 } while (0) 903 #define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 904 #define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 905 #define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 906 #define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 907 MA_OWNED) 908 #define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 909 MA_NOTOWNED) 910 911 /* 912 * The RX lock is primarily a(nother) workaround to ensure that the 913 * RX FIFO/list isn't modified by various execution paths. 914 * Even though RX occurs in a single context (the ath taskqueue), the 915 * RX path can be executed via various reset/channel change paths. 916 */ 917 #define ATH_RX_LOCK_INIT(_sc) do {\ 918 snprintf((_sc)->sc_rx_mtx_name, \ 919 sizeof((_sc)->sc_rx_mtx_name), \ 920 "%s RX lock", \ 921 device_get_nameunit((_sc)->sc_dev)); \ 922 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 923 NULL, MTX_DEF); \ 924 } while (0) 925 #define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 926 #define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 927 #define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 928 #define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 929 MA_OWNED) 930 #define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 931 MA_NOTOWNED) 932 933 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 934 935 #define ATH_TXBUF_LOCK_INIT(_sc) do { \ 936 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 937 device_get_nameunit((_sc)->sc_dev)); \ 938 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 939 } while (0) 940 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 941 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 942 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 943 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 944 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 945 946 #define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 947 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 948 "%s_buf", \ 949 device_get_nameunit((_sc)->sc_dev)); \ 950 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 951 MTX_DEF); \ 952 } while (0) 953 #define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 954 #define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 955 #define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 956 #define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 957 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 958 959 int ath_attach(u_int16_t, struct ath_softc *); 960 int ath_detach(struct ath_softc *); 961 void ath_resume(struct ath_softc *); 962 void ath_suspend(struct ath_softc *); 963 void ath_shutdown(struct ath_softc *); 964 void ath_intr(void *); 965 966 /* 967 * HAL definitions to comply with local coding convention. 968 */ 969 #define ath_hal_detach(_ah) \ 970 ((*(_ah)->ah_detach)((_ah))) 971 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 972 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 973 #define ath_hal_macversion(_ah) \ 974 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 975 #define ath_hal_getratetable(_ah, _mode) \ 976 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 977 #define ath_hal_getmac(_ah, _mac) \ 978 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 979 #define ath_hal_setmac(_ah, _mac) \ 980 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 981 #define ath_hal_getbssidmask(_ah, _mask) \ 982 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 983 #define ath_hal_setbssidmask(_ah, _mask) \ 984 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 985 #define ath_hal_intrset(_ah, _mask) \ 986 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 987 #define ath_hal_intrget(_ah) \ 988 ((*(_ah)->ah_getInterrupts)((_ah))) 989 #define ath_hal_intrpend(_ah) \ 990 ((*(_ah)->ah_isInterruptPending)((_ah))) 991 #define ath_hal_getisr(_ah, _pmask) \ 992 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 993 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 994 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 995 #define ath_hal_setpower(_ah, _mode) \ 996 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 997 #define ath_hal_keycachesize(_ah) \ 998 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 999 #define ath_hal_keyreset(_ah, _ix) \ 1000 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1001 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 1002 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1003 #define ath_hal_keyisvalid(_ah, _ix) \ 1004 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1005 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 1006 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1007 #define ath_hal_getrxfilter(_ah) \ 1008 ((*(_ah)->ah_getRxFilter)((_ah))) 1009 #define ath_hal_setrxfilter(_ah, _filter) \ 1010 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1011 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 1012 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1013 #define ath_hal_waitforbeacon(_ah, _bf) \ 1014 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1015 #define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 1016 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 1017 /* NB: common across all chips */ 1018 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 1019 #define ath_hal_gettsf32(_ah) \ 1020 OS_REG_READ(_ah, AR_TSF_L32) 1021 #define ath_hal_gettsf64(_ah) \ 1022 ((*(_ah)->ah_getTsf64)((_ah))) 1023 #define ath_hal_settsf64(_ah, _val) \ 1024 ((*(_ah)->ah_setTsf64)((_ah), (_val))) 1025 #define ath_hal_resettsf(_ah) \ 1026 ((*(_ah)->ah_resetTsf)((_ah))) 1027 #define ath_hal_rxena(_ah) \ 1028 ((*(_ah)->ah_enableReceive)((_ah))) 1029 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 1030 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1031 #define ath_hal_gettxbuf(_ah, _q) \ 1032 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1033 #define ath_hal_numtxpending(_ah, _q) \ 1034 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 1035 #define ath_hal_getrxbuf(_ah, _rxq) \ 1036 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 1037 #define ath_hal_txstart(_ah, _q) \ 1038 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1039 #define ath_hal_setchannel(_ah, _chan) \ 1040 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1041 #define ath_hal_calibrate(_ah, _chan, _iqcal) \ 1042 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1043 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 1044 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 1045 #define ath_hal_calreset(_ah, _chan) \ 1046 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 1047 #define ath_hal_setledstate(_ah, _state) \ 1048 ((*(_ah)->ah_setLedState)((_ah), (_state))) 1049 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 1050 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1051 #define ath_hal_beaconreset(_ah) \ 1052 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1053 #define ath_hal_beaconsettimers(_ah, _bt) \ 1054 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 1055 #define ath_hal_beacontimers(_ah, _bs) \ 1056 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 1057 #define ath_hal_getnexttbtt(_ah) \ 1058 ((*(_ah)->ah_getNextTBTT)((_ah))) 1059 #define ath_hal_setassocid(_ah, _bss, _associd) \ 1060 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1061 #define ath_hal_phydisable(_ah) \ 1062 ((*(_ah)->ah_phyDisable)((_ah))) 1063 #define ath_hal_setopmode(_ah) \ 1064 ((*(_ah)->ah_setPCUConfig)((_ah))) 1065 #define ath_hal_stoptxdma(_ah, _qnum) \ 1066 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1067 #define ath_hal_stoppcurecv(_ah) \ 1068 ((*(_ah)->ah_stopPcuReceive)((_ah))) 1069 #define ath_hal_startpcurecv(_ah) \ 1070 ((*(_ah)->ah_startPcuReceive)((_ah))) 1071 #define ath_hal_stopdmarecv(_ah) \ 1072 ((*(_ah)->ah_stopDmaReceive)((_ah))) 1073 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 1074 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 1075 (_indata), (_insize), (_outdata), (_outsize))) 1076 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 1077 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 1078 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 1079 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1080 #define ath_hal_resettxqueue(_ah, _q) \ 1081 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1082 #define ath_hal_releasetxqueue(_ah, _q) \ 1083 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1084 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 1085 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1086 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 1087 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1088 /* NB: common across all chips */ 1089 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 1090 #define ath_hal_txqenabled(_ah, _qnum) \ 1091 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 1092 #define ath_hal_getrfgain(_ah) \ 1093 ((*(_ah)->ah_getRfGain)((_ah))) 1094 #define ath_hal_getdefantenna(_ah) \ 1095 ((*(_ah)->ah_getDefAntenna)((_ah))) 1096 #define ath_hal_setdefantenna(_ah, _ant) \ 1097 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 1098 #define ath_hal_rxmonitor(_ah, _arg, _chan) \ 1099 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1100 #define ath_hal_ani_poll(_ah, _chan) \ 1101 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1102 #define ath_hal_mibevent(_ah, _stats) \ 1103 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1104 #define ath_hal_setslottime(_ah, _us) \ 1105 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1106 #define ath_hal_getslottime(_ah) \ 1107 ((*(_ah)->ah_getSlotTime)((_ah))) 1108 #define ath_hal_setacktimeout(_ah, _us) \ 1109 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1110 #define ath_hal_getacktimeout(_ah) \ 1111 ((*(_ah)->ah_getAckTimeout)((_ah))) 1112 #define ath_hal_setctstimeout(_ah, _us) \ 1113 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1114 #define ath_hal_getctstimeout(_ah) \ 1115 ((*(_ah)->ah_getCTSTimeout)((_ah))) 1116 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1117 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1118 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1119 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1120 #define ath_hal_ciphersupported(_ah, _cipher) \ 1121 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1122 #define ath_hal_getregdomain(_ah, _prd) \ 1123 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1124 #define ath_hal_setregdomain(_ah, _rd) \ 1125 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1126 #define ath_hal_getcountrycode(_ah, _pcc) \ 1127 (*(_pcc) = (_ah)->ah_countryCode) 1128 #define ath_hal_gettkipmic(_ah) \ 1129 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1130 #define ath_hal_settkipmic(_ah, _v) \ 1131 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1132 #define ath_hal_hastkipsplit(_ah) \ 1133 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1134 #define ath_hal_gettkipsplit(_ah) \ 1135 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1136 #define ath_hal_settkipsplit(_ah, _v) \ 1137 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1138 #define ath_hal_haswmetkipmic(_ah) \ 1139 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1140 #define ath_hal_hwphycounters(_ah) \ 1141 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1142 #define ath_hal_hasdiversity(_ah) \ 1143 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1144 #define ath_hal_getdiversity(_ah) \ 1145 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1146 #define ath_hal_setdiversity(_ah, _v) \ 1147 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1148 #define ath_hal_getantennaswitch(_ah) \ 1149 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1150 #define ath_hal_setantennaswitch(_ah, _v) \ 1151 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1152 #define ath_hal_getdiag(_ah, _pv) \ 1153 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1154 #define ath_hal_setdiag(_ah, _v) \ 1155 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1156 #define ath_hal_getnumtxqueues(_ah, _pv) \ 1157 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1158 #define ath_hal_hasveol(_ah) \ 1159 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1160 #define ath_hal_hastxpowlimit(_ah) \ 1161 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1162 #define ath_hal_settxpowlimit(_ah, _pow) \ 1163 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1164 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 1165 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1166 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 1167 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1168 #define ath_hal_gettpscale(_ah, _scale) \ 1169 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1170 #define ath_hal_settpscale(_ah, _v) \ 1171 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1172 #define ath_hal_hastpc(_ah) \ 1173 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1174 #define ath_hal_gettpc(_ah) \ 1175 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1176 #define ath_hal_settpc(_ah, _v) \ 1177 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1178 #define ath_hal_hasbursting(_ah) \ 1179 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1180 #define ath_hal_setmcastkeysearch(_ah, _v) \ 1181 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1182 #define ath_hal_hasmcastkeysearch(_ah) \ 1183 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1184 #define ath_hal_getmcastkeysearch(_ah) \ 1185 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1186 #define ath_hal_hasfastframes(_ah) \ 1187 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1188 #define ath_hal_hasbssidmask(_ah) \ 1189 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1190 #define ath_hal_hasbssidmatch(_ah) \ 1191 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1192 #define ath_hal_hastsfadjust(_ah) \ 1193 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1194 #define ath_hal_gettsfadjust(_ah) \ 1195 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1196 #define ath_hal_settsfadjust(_ah, _onoff) \ 1197 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1198 #define ath_hal_hasrfsilent(_ah) \ 1199 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1200 #define ath_hal_getrfkill(_ah) \ 1201 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1202 #define ath_hal_setrfkill(_ah, _onoff) \ 1203 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1204 #define ath_hal_getrfsilent(_ah, _prfsilent) \ 1205 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1206 #define ath_hal_setrfsilent(_ah, _rfsilent) \ 1207 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1208 #define ath_hal_gettpack(_ah, _ptpack) \ 1209 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1210 #define ath_hal_settpack(_ah, _tpack) \ 1211 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1212 #define ath_hal_gettpcts(_ah, _ptpcts) \ 1213 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1214 #define ath_hal_settpcts(_ah, _tpcts) \ 1215 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1216 #define ath_hal_hasintmit(_ah) \ 1217 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1218 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1219 #define ath_hal_getintmit(_ah) \ 1220 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1221 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1222 #define ath_hal_setintmit(_ah, _v) \ 1223 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1224 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1225 1226 /* EDMA definitions */ 1227 #define ath_hal_hasedma(_ah) \ 1228 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1229 0, NULL) == HAL_OK) 1230 #define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1231 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1232 == HAL_OK) 1233 #define ath_hal_getntxmaps(_ah, _req) \ 1234 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1235 == HAL_OK) 1236 #define ath_hal_gettxdesclen(_ah, _req) \ 1237 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1238 == HAL_OK) 1239 #define ath_hal_gettxstatuslen(_ah, _req) \ 1240 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1241 == HAL_OK) 1242 #define ath_hal_getrxstatuslen(_ah, _req) \ 1243 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1244 == HAL_OK) 1245 #define ath_hal_setrxbufsize(_ah, _req) \ 1246 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1247 == HAL_OK) 1248 1249 #define ath_hal_getchannoise(_ah, _c) \ 1250 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1251 1252 /* 802.11n HAL methods */ 1253 #define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1254 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1255 #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1256 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1257 #define ath_hal_setrxchainmask(_ah, _rx) \ 1258 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1259 #define ath_hal_settxchainmask(_ah, _tx) \ 1260 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1261 #define ath_hal_split4ktrans(_ah) \ 1262 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1263 0, NULL) == HAL_OK) 1264 #define ath_hal_self_linked_final_rxdesc(_ah) \ 1265 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1266 0, NULL) == HAL_OK) 1267 #define ath_hal_gtxto_supported(_ah) \ 1268 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1269 #define ath_hal_has_long_rxdesc_tsf(_ah) \ 1270 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1271 0, NULL) == HAL_OK) 1272 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1273 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1274 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1275 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1276 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1277 _txr0, _txtr0, _keyix, _ant, _flags, \ 1278 _rtsrate, _rtsdura) \ 1279 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1280 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1281 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1282 #define ath_hal_setupxtxdesc(_ah, _ds, \ 1283 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1284 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1285 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1286 #define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1287 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1288 (_first), (_last), (_ds0))) 1289 #define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1290 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1291 #define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1292 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1293 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1294 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1295 #define ath_hal_settxdesclink(_ah, _ds, _link) \ 1296 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1297 #define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1298 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1299 #define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1300 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1301 #define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1302 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1303 (_size))) 1304 #define ath_hal_gettxrawtxdesc(_ah, _txstatus) \ 1305 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus))) 1306 1307 #define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1308 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1309 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1310 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1311 #define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1312 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1313 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1314 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1315 (_first), (_last), (_lastaggr))) 1316 #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1317 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1318 1319 #define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1320 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1321 (_series), (_ns), (_flags))) 1322 1323 #define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1324 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1325 #define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \ 1326 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1327 #define ath_hal_set11n_aggr_last(_ah, _ds) \ 1328 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1329 1330 #define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1331 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1332 #define ath_hal_clr11n_aggr(_ah, _ds) \ 1333 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1334 #define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \ 1335 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v))) 1336 1337 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1338 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1339 #define ath_hal_gpioset(_ah, _gpio, _b) \ 1340 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1341 #define ath_hal_gpioget(_ah, _gpio) \ 1342 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1343 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1344 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1345 1346 /* 1347 * PCIe suspend/resume/poweron/poweroff related macros 1348 */ 1349 #define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1350 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1351 #define ath_hal_disablepcie(_ah) \ 1352 ((*(_ah)->ah_disablePCIE)((_ah))) 1353 1354 /* 1355 * This is badly-named; you need to set the correct parameters 1356 * to begin to receive useful radar events; and even then 1357 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1358 * more information. 1359 */ 1360 #define ath_hal_enabledfs(_ah, _param) \ 1361 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1362 #define ath_hal_getdfsthresh(_ah, _param) \ 1363 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1364 #define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1365 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1366 #define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1367 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1368 (_buf), (_event))) 1369 #define ath_hal_is_fast_clock_enabled(_ah) \ 1370 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1371 #define ath_hal_radar_wait(_ah, _chan) \ 1372 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1373 #define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1374 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1375 #define ath_hal_get_chan_ext_busy(_ah) \ 1376 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1377 #define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \ 1378 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask))) 1379 1380 #define ath_hal_spectral_supported(_ah) \ 1381 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK) 1382 #define ath_hal_spectral_get_config(_ah, _p) \ 1383 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p))) 1384 #define ath_hal_spectral_configure(_ah, _p) \ 1385 ((*(_ah)->ah_spectralConfigure)((_ah), (_p))) 1386 #define ath_hal_spectral_start(_ah) \ 1387 ((*(_ah)->ah_spectralStart)((_ah))) 1388 #define ath_hal_spectral_stop(_ah) \ 1389 ((*(_ah)->ah_spectralStop)((_ah))) 1390 1391 #endif /* _DEV_ATH_ATHVAR_H */ 1392