1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35 #ifndef _DEV_ATH_ATHVAR_H 36 #define _DEV_ATH_ATHVAR_H 37 38 #include <dev/ath/ath_hal/ah.h> 39 #include <dev/ath/ath_hal/ah_desc.h> 40 #include <net80211/ieee80211_radiotap.h> 41 #include <dev/ath/if_athioctl.h> 42 #include <dev/ath/if_athrate.h> 43 44 #define ATH_TIMEOUT 1000 45 46 /* 47 * There is a separate TX ath_buf pool for management frames. 48 * This ensures that management frames such as probe responses 49 * and BAR frames can be transmitted during periods of high 50 * TX activity. 51 */ 52 #define ATH_MGMT_TXBUF 32 53 54 /* 55 * 802.11n requires more TX and RX buffers to do AMPDU. 56 */ 57 #ifdef ATH_ENABLE_11N 58 #define ATH_TXBUF 512 59 #define ATH_RXBUF 512 60 #endif 61 62 #ifndef ATH_RXBUF 63 #define ATH_RXBUF 40 /* number of RX buffers */ 64 #endif 65 #ifndef ATH_TXBUF 66 #define ATH_TXBUF 200 /* number of TX buffers */ 67 #endif 68 #define ATH_BCBUF 4 /* number of beacon buffers */ 69 70 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 71 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 72 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 73 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 74 75 #define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 76 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 77 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 78 79 /* 80 * The key cache is used for h/w cipher state and also for 81 * tracking station state such as the current tx antenna. 82 * We also setup a mapping table between key cache slot indices 83 * and station state to short-circuit node lookups on rx. 84 * Different parts have different size key caches. We handle 85 * up to ATH_KEYMAX entries (could dynamically allocate state). 86 */ 87 #define ATH_KEYMAX 128 /* max key cache size we handle */ 88 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 89 90 struct taskqueue; 91 struct kthread; 92 struct ath_buf; 93 94 #define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 95 96 /* 97 * Per-TID state 98 * 99 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 100 */ 101 struct ath_tid { 102 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 103 u_int axq_depth; /* SW queue depth */ 104 char axq_name[48]; /* lock name */ 105 struct ath_node *an; /* pointer to parent */ 106 int tid; /* tid */ 107 int ac; /* which AC gets this trafic */ 108 int hwq_depth; /* how many buffers are on HW */ 109 110 /* 111 * Entry on the ath_txq; when there's traffic 112 * to send 113 */ 114 TAILQ_ENTRY(ath_tid) axq_qelem; 115 int sched; 116 int paused; /* >0 if the TID has been paused */ 117 int addba_tx_pending; /* TX ADDBA pending */ 118 int bar_wait; /* waiting for BAR */ 119 int bar_tx; /* BAR TXed */ 120 121 /* 122 * Is the TID being cleaned up after a transition 123 * from aggregation to non-aggregation? 124 * When this is set to 1, this TID will be paused 125 * and no further traffic will be queued until all 126 * the hardware packets pending for this TID have been 127 * TXed/completed; at which point (non-aggregation) 128 * traffic will resume being TXed. 129 */ 130 int cleanup_inprogress; 131 /* 132 * How many hardware-queued packets are 133 * waiting to be cleaned up. 134 * This is only valid if cleanup_inprogress is 1. 135 */ 136 int incomp; 137 138 /* 139 * The following implements a ring representing 140 * the frames in the current BAW. 141 * To avoid copying the array content each time 142 * the BAW is moved, the baw_head/baw_tail point 143 * to the current BAW begin/end; when the BAW is 144 * shifted the head/tail of the array are also 145 * appropriately shifted. 146 */ 147 /* active tx buffers, beginning at current BAW */ 148 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 149 /* where the baw head is in the array */ 150 int baw_head; 151 /* where the BAW tail is in the array */ 152 int baw_tail; 153 }; 154 155 /* driver-specific node state */ 156 struct ath_node { 157 struct ieee80211_node an_node; /* base class */ 158 u_int8_t an_mgmtrix; /* min h/w rate index */ 159 u_int8_t an_mcastrix; /* mcast h/w rate index */ 160 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 161 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 162 char an_name[32]; /* eg "wlan0_a1" */ 163 struct mtx an_mtx; /* protecting the ath_node state */ 164 /* variable-length rate control state follows */ 165 }; 166 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 167 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 168 169 #define ATH_RSSI_LPF_LEN 10 170 #define ATH_RSSI_DUMMY_MARKER 0x127 171 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 172 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 173 #define ATH_LPF_RSSI(x, y, len) \ 174 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 175 #define ATH_RSSI_LPF(x, y) do { \ 176 if ((y) >= -20) \ 177 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 178 } while (0) 179 #define ATH_EP_RND(x,mul) \ 180 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 181 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 182 183 typedef enum { 184 ATH_BUFTYPE_NORMAL = 0, 185 ATH_BUFTYPE_MGMT = 1, 186 } ath_buf_type_t; 187 188 struct ath_buf { 189 TAILQ_ENTRY(ath_buf) bf_list; 190 struct ath_buf * bf_next; /* next buffer in the aggregate */ 191 int bf_nseg; 192 HAL_STATUS bf_rxstatus; 193 uint16_t bf_flags; /* status flags (below) */ 194 struct ath_desc *bf_desc; /* virtual addr of desc */ 195 struct ath_desc_status bf_status; /* tx/rx status */ 196 bus_addr_t bf_daddr; /* physical addr of desc */ 197 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 198 struct mbuf *bf_m; /* mbuf for buf */ 199 struct ieee80211_node *bf_node; /* pointer to the node */ 200 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 201 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 202 bus_size_t bf_mapsize; 203 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 204 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 205 206 /* Completion function to call on TX complete (fail or not) */ 207 /* 208 * "fail" here is set to 1 if the queue entries were removed 209 * through a call to ath_tx_draintxq(). 210 */ 211 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 212 213 /* This state is kept to support software retries and aggregation */ 214 struct { 215 uint16_t bfs_seqno; /* sequence number of this packet */ 216 uint16_t bfs_ndelim; /* number of delims for padding */ 217 218 uint8_t bfs_retries; /* retry count */ 219 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 220 uint8_t bfs_nframes; /* number of frames in aggregate */ 221 uint8_t bfs_pri; /* packet AC priority */ 222 223 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 224 225 u_int32_t bfs_aggr:1, /* part of aggregate? */ 226 bfs_aggrburst:1, /* part of aggregate burst? */ 227 bfs_isretried:1, /* retried frame? */ 228 bfs_dobaw:1, /* actually check against BAW? */ 229 bfs_addedbaw:1, /* has been added to the BAW */ 230 bfs_shpream:1, /* use short preamble */ 231 bfs_istxfrag:1, /* is fragmented */ 232 bfs_ismrr:1, /* do multi-rate TX retry */ 233 bfs_doprot:1, /* do RTS/CTS based protection */ 234 bfs_doratelookup:1; /* do rate lookup before each TX */ 235 236 /* 237 * These fields are passed into the 238 * descriptor setup functions. 239 */ 240 241 /* Make this an 8 bit value? */ 242 HAL_PKT_TYPE bfs_atype; /* packet type */ 243 244 uint32_t bfs_pktlen; /* length of this packet */ 245 246 uint16_t bfs_hdrlen; /* length of this packet header */ 247 uint16_t bfs_al; /* length of aggregate */ 248 249 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 250 uint8_t bfs_txrate0; /* first TX rate */ 251 uint8_t bfs_try0; /* first try count */ 252 253 uint16_t bfs_txpower; /* tx power */ 254 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 255 uint8_t bfs_ctsrate; /* CTS rate */ 256 257 /* 16 bit? */ 258 int32_t bfs_keyix; /* crypto key index */ 259 int32_t bfs_txantenna; /* TX antenna config */ 260 261 /* Make this an 8 bit value? */ 262 enum ieee80211_protmode bfs_protmode; 263 264 /* 16 bit? */ 265 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 266 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 267 } bf_state; 268 }; 269 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 270 271 #define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 272 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 273 274 /* 275 * DMA state for tx/rx descriptors. 276 */ 277 struct ath_descdma { 278 const char* dd_name; 279 struct ath_desc *dd_desc; /* descriptors */ 280 int dd_descsize; /* size of single descriptor */ 281 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 282 bus_size_t dd_desc_len; /* size of dd_desc */ 283 bus_dma_segment_t dd_dseg; 284 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 285 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 286 struct ath_buf *dd_bufptr; /* associated buffers */ 287 }; 288 289 /* 290 * Data transmit queue state. One of these exists for each 291 * hardware transmit queue. Packets sent to us from above 292 * are assigned to queues based on their priority. Not all 293 * devices support a complete set of hardware transmit queues. 294 * For those devices the array sc_ac2q will map multiple 295 * priorities to fewer hardware queues (typically all to one 296 * hardware queue). 297 */ 298 struct ath_txq { 299 struct ath_softc *axq_softc; /* Needed for scheduling */ 300 u_int axq_qnum; /* hardware q number */ 301 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 302 u_int axq_ac; /* WME AC */ 303 u_int axq_flags; 304 #define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 305 u_int axq_depth; /* queue depth (stat only) */ 306 u_int axq_aggr_depth; /* how many aggregates are queued */ 307 u_int axq_intrcnt; /* interrupt count */ 308 u_int32_t *axq_link; /* link ptr in last TX desc */ 309 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 310 struct mtx axq_lock; /* lock on q and link */ 311 char axq_name[12]; /* e.g. "ath0_txq4" */ 312 313 /* Per-TID traffic queue for software -> hardware TX */ 314 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 315 }; 316 317 #define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 318 #define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 319 #define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 320 321 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 322 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 323 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 324 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 325 } while (0) 326 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 327 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 328 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 329 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 330 #define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 331 332 #define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 333 ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 334 335 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 336 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 337 (_tq)->axq_depth++; \ 338 } while (0) 339 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 340 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 341 (_tq)->axq_depth++; \ 342 } while (0) 343 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 344 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 345 (_tq)->axq_depth--; \ 346 } while (0) 347 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 348 349 struct ath_vap { 350 struct ieee80211vap av_vap; /* base class */ 351 int av_bslot; /* beacon slot index */ 352 struct ath_buf *av_bcbuf; /* beacon buffer */ 353 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 354 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 355 356 void (*av_recv_mgmt)(struct ieee80211_node *, 357 struct mbuf *, int, int, int); 358 int (*av_newstate)(struct ieee80211vap *, 359 enum ieee80211_state, int); 360 void (*av_bmiss)(struct ieee80211vap *); 361 }; 362 #define ATH_VAP(vap) ((struct ath_vap *)(vap)) 363 364 struct taskqueue; 365 struct ath_tx99; 366 367 /* 368 * Whether to reset the TX/RX queue with or without 369 * a queue flush. 370 */ 371 typedef enum { 372 ATH_RESET_DEFAULT = 0, 373 ATH_RESET_NOLOSS = 1, 374 ATH_RESET_FULL = 2, 375 } ATH_RESET_TYPE; 376 377 struct ath_rx_methods { 378 void (*recv_stop)(struct ath_softc *sc, int dodelay); 379 int (*recv_start)(struct ath_softc *sc); 380 void (*recv_flush)(struct ath_softc *sc); 381 void (*recv_tasklet)(void *arg, int npending); 382 int (*recv_rxbuf_init)(struct ath_softc *sc, 383 struct ath_buf *bf); 384 int (*recv_setup)(struct ath_softc *sc); 385 int (*recv_teardown)(struct ath_softc *sc); 386 }; 387 388 /* 389 * Represent the current state of the RX FIFO. 390 */ 391 struct ath_rx_edma { 392 struct ath_buf **m_fifo; 393 int m_fifolen; 394 int m_fifo_head; 395 int m_fifo_tail; 396 int m_fifo_depth; 397 struct mbuf *m_rxpending; 398 }; 399 400 struct ath_tx_methods { 401 int (*xmit_setup)(struct ath_softc *sc); 402 int (*xmit_teardown)(struct ath_softc *sc); 403 }; 404 405 struct ath_softc { 406 struct ifnet *sc_ifp; /* interface common */ 407 struct ath_stats sc_stats; /* interface statistics */ 408 struct ath_tx_aggr_stats sc_aggr_stats; 409 struct ath_intr_stats sc_intr_stats; 410 uint64_t sc_debug; 411 int sc_nvaps; /* # vaps */ 412 int sc_nstavaps; /* # station vaps */ 413 int sc_nmeshvaps; /* # mbss vaps */ 414 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 415 u_int8_t sc_nbssid0; /* # vap's using base mac */ 416 uint32_t sc_bssidmask; /* bssid mask */ 417 418 struct ath_rx_methods sc_rx; 419 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 420 struct ath_tx_methods sc_tx; 421 422 int sc_rx_statuslen; 423 int sc_tx_desclen; 424 int sc_tx_statuslen; 425 int sc_tx_nmaps; /* Number of TX maps */ 426 int sc_edma_bufsize; 427 428 void (*sc_node_cleanup)(struct ieee80211_node *); 429 void (*sc_node_free)(struct ieee80211_node *); 430 device_t sc_dev; 431 HAL_BUS_TAG sc_st; /* bus space tag */ 432 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 433 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 434 struct mtx sc_mtx; /* master lock (recursive) */ 435 struct mtx sc_pcu_mtx; /* PCU access mutex */ 436 char sc_pcu_mtx_name[32]; 437 struct mtx sc_rx_mtx; /* RX access mutex */ 438 char sc_rx_mtx_name[32]; 439 struct taskqueue *sc_tq; /* private task queue */ 440 struct ath_hal *sc_ah; /* Atheros HAL */ 441 struct ath_ratectrl *sc_rc; /* tx rate control support */ 442 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 443 void (*sc_setdefantenna)(struct ath_softc *, u_int); 444 unsigned int sc_invalid : 1,/* disable hardware accesses */ 445 sc_mrretry : 1,/* multi-rate retry support */ 446 sc_softled : 1,/* enable LED gpio status */ 447 sc_hardled : 1,/* enable MAC LED status */ 448 sc_splitmic : 1,/* split TKIP MIC keys */ 449 sc_needmib : 1,/* enable MIB stats intr */ 450 sc_diversity: 1,/* enable rx diversity */ 451 sc_hasveol : 1,/* tx VEOL support */ 452 sc_ledstate : 1,/* LED on/off state */ 453 sc_blinking : 1,/* LED blink operation active */ 454 sc_mcastkey : 1,/* mcast key cache search */ 455 sc_scanning : 1,/* scanning active */ 456 sc_syncbeacon:1,/* sync/resync beacon timers */ 457 sc_hasclrkey: 1,/* CLR key supported */ 458 sc_xchanmode: 1,/* extended channel mode */ 459 sc_outdoor : 1,/* outdoor operation */ 460 sc_dturbo : 1,/* dynamic turbo in use */ 461 sc_hasbmask : 1,/* bssid mask support */ 462 sc_hasbmatch: 1,/* bssid match disable support*/ 463 sc_hastsfadd: 1,/* tsf adjust support */ 464 sc_beacons : 1,/* beacons running */ 465 sc_swbmiss : 1,/* sta mode using sw bmiss */ 466 sc_stagbeacons:1,/* use staggered beacons */ 467 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 468 sc_resume_up: 1,/* on resume, start all vaps */ 469 sc_tdma : 1,/* TDMA in use */ 470 sc_setcca : 1,/* set/clr CCA with TDMA */ 471 sc_resetcal : 1,/* reset cal state next trip */ 472 sc_rxslink : 1,/* do self-linked final descriptor */ 473 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 474 sc_isedma : 1;/* supports EDMA */ 475 uint32_t sc_eerd; /* regdomain from EEPROM */ 476 uint32_t sc_eecc; /* country code from EEPROM */ 477 /* rate tables */ 478 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 479 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 480 enum ieee80211_phymode sc_curmode; /* current phy mode */ 481 HAL_OPMODE sc_opmode; /* current operating mode */ 482 u_int16_t sc_curtxpow; /* current tx power limit */ 483 u_int16_t sc_curaid; /* current association id */ 484 struct ieee80211_channel *sc_curchan; /* current installed channel */ 485 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 486 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 487 struct { 488 u_int8_t ieeerate; /* IEEE rate */ 489 u_int8_t rxflags; /* radiotap rx flags */ 490 u_int8_t txflags; /* radiotap tx flags */ 491 u_int16_t ledon; /* softled on time */ 492 u_int16_t ledoff; /* softled off time */ 493 } sc_hwmap[32]; /* h/w rate ix mappings */ 494 u_int8_t sc_protrix; /* protection rate index */ 495 u_int8_t sc_lastdatarix; /* last data frame rate index */ 496 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 497 u_int sc_fftxqmin; /* min frames before staging */ 498 u_int sc_fftxqmax; /* max frames before drop */ 499 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 500 501 HAL_INT sc_imask; /* interrupt mask copy */ 502 503 /* 504 * These are modified in the interrupt handler as well as 505 * the task queues and other contexts. Thus these must be 506 * protected by a mutex, or they could clash. 507 * 508 * For now, access to these is behind the ATH_LOCK, 509 * just to save time. 510 */ 511 uint32_t sc_txq_active; /* bitmap of active TXQs */ 512 uint32_t sc_kickpcu; /* whether to kick the PCU */ 513 uint32_t sc_rxproc_cnt; /* In RX processing */ 514 uint32_t sc_txproc_cnt; /* In TX processing */ 515 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 516 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 517 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 518 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 519 520 u_int sc_keymax; /* size of key cache */ 521 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 522 523 /* 524 * Software based LED blinking 525 */ 526 u_int sc_ledpin; /* GPIO pin for driving LED */ 527 u_int sc_ledon; /* pin setting for LED on */ 528 u_int sc_ledidle; /* idle polling interval */ 529 int sc_ledevent; /* time of last LED event */ 530 u_int8_t sc_txrix; /* current tx rate for LED */ 531 u_int16_t sc_ledoff; /* off time for current blink */ 532 struct callout sc_ledtimer; /* led off timer */ 533 534 /* 535 * Hardware based LED blinking 536 */ 537 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 538 int sc_led_net_pin; /* MAC network LED GPIO pin */ 539 540 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 541 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 542 543 struct ath_descdma sc_rxdma; /* RX descriptors */ 544 ath_bufhead sc_rxbuf; /* receive buffer */ 545 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 546 struct task sc_rxtask; /* rx int processing */ 547 u_int8_t sc_defant; /* current default antenna */ 548 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 549 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 550 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 551 struct ath_rx_radiotap_header sc_rx_th; 552 int sc_rx_th_len; 553 u_int sc_monpass; /* frames to pass in mon.mode */ 554 555 struct ath_descdma sc_txdma; /* TX descriptors */ 556 ath_bufhead sc_txbuf; /* transmit buffer */ 557 int sc_txbuf_cnt; /* how many buffers avail */ 558 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 559 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 560 struct mtx sc_txbuflock; /* txbuf lock */ 561 char sc_txname[12]; /* e.g. "ath0_buf" */ 562 u_int sc_txqsetup; /* h/w queues setup */ 563 u_int sc_txintrperiod;/* tx interrupt batching */ 564 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 565 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 566 struct task sc_txtask; /* tx int processing */ 567 struct task sc_txqtask; /* tx proc processing */ 568 569 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 570 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 571 char sc_txcompname[12]; /* eg ath0_txcomp */ 572 573 int sc_wd_timer; /* count down for wd timer */ 574 struct callout sc_wd_ch; /* tx watchdog timer */ 575 struct ath_tx_radiotap_header sc_tx_th; 576 int sc_tx_th_len; 577 578 struct ath_descdma sc_bdma; /* beacon descriptors */ 579 ath_bufhead sc_bbuf; /* beacon buffers */ 580 u_int sc_bhalq; /* HAL q for outgoing beacons */ 581 u_int sc_bmisscount; /* missed beacon transmits */ 582 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 583 struct ath_txq *sc_cabq; /* tx q for cab frames */ 584 struct task sc_bmisstask; /* bmiss int processing */ 585 struct task sc_bstucktask; /* stuck beacon processing */ 586 struct task sc_resettask; /* interface reset task */ 587 struct task sc_fataltask; /* fatal task */ 588 enum { 589 OK, /* no change needed */ 590 UPDATE, /* update pending */ 591 COMMIT /* beacon sent, commit change */ 592 } sc_updateslot; /* slot time update fsm */ 593 int sc_slotupdate; /* slot to advance fsm */ 594 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 595 int sc_nbcnvaps; /* # vaps with beacons */ 596 597 struct callout sc_cal_ch; /* callout handle for cals */ 598 int sc_lastlongcal; /* last long cal completed */ 599 int sc_lastcalreset;/* last cal reset done */ 600 int sc_lastani; /* last ANI poll */ 601 int sc_lastshortcal; /* last short calibration */ 602 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 603 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 604 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 605 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 606 u_int sc_tdmaswba; /* TDMA SWBA counter */ 607 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 608 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 609 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 610 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 611 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 612 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 613 int sc_txchainmask; /* currently configured TX chainmask */ 614 int sc_rxchainmask; /* currently configured RX chainmask */ 615 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 616 617 /* Queue limits */ 618 619 /* 620 * To avoid queue starvation in congested conditions, 621 * these parameters tune the maximum number of frames 622 * queued to the data/mcastq before they're dropped. 623 * 624 * This is to prevent: 625 * + a single destination overwhelming everything, including 626 * management/multicast frames; 627 * + multicast frames overwhelming everything (when the 628 * air is sufficiently busy that cabq can't drain.) 629 * 630 * These implement: 631 * + data_minfree is the maximum number of free buffers 632 * overall to successfully allow a data frame. 633 * 634 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 635 */ 636 int sc_txq_data_minfree; 637 int sc_txq_mcastq_maxdepth; 638 639 /* 640 * Aggregation twiddles 641 * 642 * hwq_limit: how busy to keep the hardware queue - don't schedule 643 * further packets to the hardware, regardless of the TID 644 * tid_hwq_lo: how low the per-TID hwq count has to be before the 645 * TID will be scheduled again 646 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 647 * stops being scheduled. 648 */ 649 int sc_hwq_limit; 650 int sc_tid_hwq_lo; 651 int sc_tid_hwq_hi; 652 653 /* DFS related state */ 654 void *sc_dfs; /* Used by an optional DFS module */ 655 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 656 struct task sc_dfstask; /* DFS processing task */ 657 658 /* TX AMPDU handling */ 659 int (*sc_addba_request)(struct ieee80211_node *, 660 struct ieee80211_tx_ampdu *, int, int, int); 661 int (*sc_addba_response)(struct ieee80211_node *, 662 struct ieee80211_tx_ampdu *, int, int, int); 663 void (*sc_addba_stop)(struct ieee80211_node *, 664 struct ieee80211_tx_ampdu *); 665 void (*sc_addba_response_timeout) 666 (struct ieee80211_node *, 667 struct ieee80211_tx_ampdu *); 668 void (*sc_bar_response)(struct ieee80211_node *ni, 669 struct ieee80211_tx_ampdu *tap, 670 int status); 671 }; 672 673 #define ATH_LOCK_INIT(_sc) \ 674 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 675 NULL, MTX_DEF | MTX_RECURSE) 676 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 677 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 678 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 679 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 680 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 681 682 /* 683 * The PCU lock is non-recursive and should be treated as a spinlock. 684 * Although currently the interrupt code is run in netisr context and 685 * doesn't require this, this may change in the future. 686 * Please keep this in mind when protecting certain code paths 687 * with the PCU lock. 688 * 689 * The PCU lock is used to serialise access to the PCU so things such 690 * as TX, RX, state change (eg channel change), channel reset and updates 691 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 692 * 693 * Although the current single-thread taskqueue mechanism protects the 694 * majority of these situations by simply serialising them, there are 695 * a few others which occur at the same time. These include the TX path 696 * (which only acquires ATH_LOCK when recycling buffers to the free list), 697 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 698 */ 699 #define ATH_PCU_LOCK_INIT(_sc) do {\ 700 snprintf((_sc)->sc_pcu_mtx_name, \ 701 sizeof((_sc)->sc_pcu_mtx_name), \ 702 "%s PCU lock", \ 703 device_get_nameunit((_sc)->sc_dev)); \ 704 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 705 NULL, MTX_DEF); \ 706 } while (0) 707 #define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 708 #define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 709 #define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 710 #define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 711 MA_OWNED) 712 #define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 713 MA_NOTOWNED) 714 715 /* 716 * The RX lock is primarily a(nother) workaround to ensure that the 717 * RX FIFO/list isn't modified by various execution paths. 718 * Even though RX occurs in a single context (the ath taskqueue), the 719 * RX path can be executed via various reset/channel change paths. 720 */ 721 #define ATH_RX_LOCK_INIT(_sc) do {\ 722 snprintf((_sc)->sc_rx_mtx_name, \ 723 sizeof((_sc)->sc_rx_mtx_name), \ 724 "%s RX lock", \ 725 device_get_nameunit((_sc)->sc_dev)); \ 726 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 727 NULL, MTX_DEF); \ 728 } while (0) 729 #define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 730 #define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 731 #define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 732 #define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 733 MA_OWNED) 734 #define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 735 MA_NOTOWNED) 736 737 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 738 739 #define ATH_TXBUF_LOCK_INIT(_sc) do { \ 740 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 741 device_get_nameunit((_sc)->sc_dev)); \ 742 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 743 } while (0) 744 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 745 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 746 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 747 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 748 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 749 750 #define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 751 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 752 "%s_buf", \ 753 device_get_nameunit((_sc)->sc_dev)); \ 754 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 755 MTX_DEF); \ 756 } while (0) 757 #define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 758 #define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 759 #define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 760 #define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 761 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 762 763 int ath_attach(u_int16_t, struct ath_softc *); 764 int ath_detach(struct ath_softc *); 765 void ath_resume(struct ath_softc *); 766 void ath_suspend(struct ath_softc *); 767 void ath_shutdown(struct ath_softc *); 768 void ath_intr(void *); 769 770 /* 771 * HAL definitions to comply with local coding convention. 772 */ 773 #define ath_hal_detach(_ah) \ 774 ((*(_ah)->ah_detach)((_ah))) 775 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 776 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 777 #define ath_hal_macversion(_ah) \ 778 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 779 #define ath_hal_getratetable(_ah, _mode) \ 780 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 781 #define ath_hal_getmac(_ah, _mac) \ 782 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 783 #define ath_hal_setmac(_ah, _mac) \ 784 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 785 #define ath_hal_getbssidmask(_ah, _mask) \ 786 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 787 #define ath_hal_setbssidmask(_ah, _mask) \ 788 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 789 #define ath_hal_intrset(_ah, _mask) \ 790 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 791 #define ath_hal_intrget(_ah) \ 792 ((*(_ah)->ah_getInterrupts)((_ah))) 793 #define ath_hal_intrpend(_ah) \ 794 ((*(_ah)->ah_isInterruptPending)((_ah))) 795 #define ath_hal_getisr(_ah, _pmask) \ 796 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 797 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 798 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 799 #define ath_hal_setpower(_ah, _mode) \ 800 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 801 #define ath_hal_keycachesize(_ah) \ 802 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 803 #define ath_hal_keyreset(_ah, _ix) \ 804 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 805 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 806 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 807 #define ath_hal_keyisvalid(_ah, _ix) \ 808 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 809 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 810 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 811 #define ath_hal_getrxfilter(_ah) \ 812 ((*(_ah)->ah_getRxFilter)((_ah))) 813 #define ath_hal_setrxfilter(_ah, _filter) \ 814 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 815 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 816 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 817 #define ath_hal_waitforbeacon(_ah, _bf) \ 818 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 819 #define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 820 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 821 /* NB: common across all chips */ 822 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 823 #define ath_hal_gettsf32(_ah) \ 824 OS_REG_READ(_ah, AR_TSF_L32) 825 #define ath_hal_gettsf64(_ah) \ 826 ((*(_ah)->ah_getTsf64)((_ah))) 827 #define ath_hal_resettsf(_ah) \ 828 ((*(_ah)->ah_resetTsf)((_ah))) 829 #define ath_hal_rxena(_ah) \ 830 ((*(_ah)->ah_enableReceive)((_ah))) 831 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 832 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 833 #define ath_hal_gettxbuf(_ah, _q) \ 834 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 835 #define ath_hal_numtxpending(_ah, _q) \ 836 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 837 #define ath_hal_getrxbuf(_ah, _rxq) \ 838 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 839 #define ath_hal_txstart(_ah, _q) \ 840 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 841 #define ath_hal_setchannel(_ah, _chan) \ 842 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 843 #define ath_hal_calibrate(_ah, _chan, _iqcal) \ 844 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 845 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 846 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 847 #define ath_hal_calreset(_ah, _chan) \ 848 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 849 #define ath_hal_setledstate(_ah, _state) \ 850 ((*(_ah)->ah_setLedState)((_ah), (_state))) 851 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 852 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 853 #define ath_hal_beaconreset(_ah) \ 854 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 855 #define ath_hal_beaconsettimers(_ah, _bt) \ 856 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 857 #define ath_hal_beacontimers(_ah, _bs) \ 858 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 859 #define ath_hal_getnexttbtt(_ah) \ 860 ((*(_ah)->ah_getNextTBTT)((_ah))) 861 #define ath_hal_setassocid(_ah, _bss, _associd) \ 862 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 863 #define ath_hal_phydisable(_ah) \ 864 ((*(_ah)->ah_phyDisable)((_ah))) 865 #define ath_hal_setopmode(_ah) \ 866 ((*(_ah)->ah_setPCUConfig)((_ah))) 867 #define ath_hal_stoptxdma(_ah, _qnum) \ 868 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 869 #define ath_hal_stoppcurecv(_ah) \ 870 ((*(_ah)->ah_stopPcuReceive)((_ah))) 871 #define ath_hal_startpcurecv(_ah) \ 872 ((*(_ah)->ah_startPcuReceive)((_ah))) 873 #define ath_hal_stopdmarecv(_ah) \ 874 ((*(_ah)->ah_stopDmaReceive)((_ah))) 875 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 876 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 877 (_indata), (_insize), (_outdata), (_outsize))) 878 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 879 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 880 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 881 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 882 #define ath_hal_resettxqueue(_ah, _q) \ 883 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 884 #define ath_hal_releasetxqueue(_ah, _q) \ 885 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 886 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 887 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 888 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 889 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 890 /* NB: common across all chips */ 891 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 892 #define ath_hal_txqenabled(_ah, _qnum) \ 893 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 894 #define ath_hal_getrfgain(_ah) \ 895 ((*(_ah)->ah_getRfGain)((_ah))) 896 #define ath_hal_getdefantenna(_ah) \ 897 ((*(_ah)->ah_getDefAntenna)((_ah))) 898 #define ath_hal_setdefantenna(_ah, _ant) \ 899 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 900 #define ath_hal_rxmonitor(_ah, _arg, _chan) \ 901 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 902 #define ath_hal_ani_poll(_ah, _chan) \ 903 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 904 #define ath_hal_mibevent(_ah, _stats) \ 905 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 906 #define ath_hal_setslottime(_ah, _us) \ 907 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 908 #define ath_hal_getslottime(_ah) \ 909 ((*(_ah)->ah_getSlotTime)((_ah))) 910 #define ath_hal_setacktimeout(_ah, _us) \ 911 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 912 #define ath_hal_getacktimeout(_ah) \ 913 ((*(_ah)->ah_getAckTimeout)((_ah))) 914 #define ath_hal_setctstimeout(_ah, _us) \ 915 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 916 #define ath_hal_getctstimeout(_ah) \ 917 ((*(_ah)->ah_getCTSTimeout)((_ah))) 918 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 919 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 920 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 921 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 922 #define ath_hal_ciphersupported(_ah, _cipher) \ 923 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 924 #define ath_hal_getregdomain(_ah, _prd) \ 925 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 926 #define ath_hal_setregdomain(_ah, _rd) \ 927 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 928 #define ath_hal_getcountrycode(_ah, _pcc) \ 929 (*(_pcc) = (_ah)->ah_countryCode) 930 #define ath_hal_gettkipmic(_ah) \ 931 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 932 #define ath_hal_settkipmic(_ah, _v) \ 933 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 934 #define ath_hal_hastkipsplit(_ah) \ 935 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 936 #define ath_hal_gettkipsplit(_ah) \ 937 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 938 #define ath_hal_settkipsplit(_ah, _v) \ 939 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 940 #define ath_hal_haswmetkipmic(_ah) \ 941 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 942 #define ath_hal_hwphycounters(_ah) \ 943 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 944 #define ath_hal_hasdiversity(_ah) \ 945 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 946 #define ath_hal_getdiversity(_ah) \ 947 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 948 #define ath_hal_setdiversity(_ah, _v) \ 949 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 950 #define ath_hal_getantennaswitch(_ah) \ 951 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 952 #define ath_hal_setantennaswitch(_ah, _v) \ 953 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 954 #define ath_hal_getdiag(_ah, _pv) \ 955 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 956 #define ath_hal_setdiag(_ah, _v) \ 957 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 958 #define ath_hal_getnumtxqueues(_ah, _pv) \ 959 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 960 #define ath_hal_hasveol(_ah) \ 961 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 962 #define ath_hal_hastxpowlimit(_ah) \ 963 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 964 #define ath_hal_settxpowlimit(_ah, _pow) \ 965 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 966 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 967 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 968 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 969 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 970 #define ath_hal_gettpscale(_ah, _scale) \ 971 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 972 #define ath_hal_settpscale(_ah, _v) \ 973 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 974 #define ath_hal_hastpc(_ah) \ 975 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 976 #define ath_hal_gettpc(_ah) \ 977 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 978 #define ath_hal_settpc(_ah, _v) \ 979 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 980 #define ath_hal_hasbursting(_ah) \ 981 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 982 #define ath_hal_setmcastkeysearch(_ah, _v) \ 983 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 984 #define ath_hal_hasmcastkeysearch(_ah) \ 985 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 986 #define ath_hal_getmcastkeysearch(_ah) \ 987 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 988 #define ath_hal_hasfastframes(_ah) \ 989 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 990 #define ath_hal_hasbssidmask(_ah) \ 991 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 992 #define ath_hal_hasbssidmatch(_ah) \ 993 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 994 #define ath_hal_hastsfadjust(_ah) \ 995 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 996 #define ath_hal_gettsfadjust(_ah) \ 997 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 998 #define ath_hal_settsfadjust(_ah, _onoff) \ 999 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1000 #define ath_hal_hasrfsilent(_ah) \ 1001 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1002 #define ath_hal_getrfkill(_ah) \ 1003 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1004 #define ath_hal_setrfkill(_ah, _onoff) \ 1005 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1006 #define ath_hal_getrfsilent(_ah, _prfsilent) \ 1007 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1008 #define ath_hal_setrfsilent(_ah, _rfsilent) \ 1009 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1010 #define ath_hal_gettpack(_ah, _ptpack) \ 1011 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1012 #define ath_hal_settpack(_ah, _tpack) \ 1013 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1014 #define ath_hal_gettpcts(_ah, _ptpcts) \ 1015 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1016 #define ath_hal_settpcts(_ah, _tpcts) \ 1017 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1018 #define ath_hal_hasintmit(_ah) \ 1019 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1020 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1021 #define ath_hal_getintmit(_ah) \ 1022 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1023 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1024 #define ath_hal_setintmit(_ah, _v) \ 1025 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1026 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1027 1028 /* EDMA definitions */ 1029 #define ath_hal_hasedma(_ah) \ 1030 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1031 0, NULL) == HAL_OK) 1032 #define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1033 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1034 == HAL_OK) 1035 #define ath_hal_getntxmaps(_ah, _req) \ 1036 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1037 == HAL_OK) 1038 #define ath_hal_gettxdesclen(_ah, _req) \ 1039 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1040 == HAL_OK) 1041 #define ath_hal_gettxstatuslen(_ah, _req) \ 1042 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1043 == HAL_OK) 1044 #define ath_hal_getrxstatuslen(_ah, _req) \ 1045 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1046 == HAL_OK) 1047 #define ath_hal_setrxbufsize(_ah, _req) \ 1048 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1049 == HAL_OK) 1050 1051 #define ath_hal_getchannoise(_ah, _c) \ 1052 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1053 1054 /* 802.11n HAL methods */ 1055 #define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1056 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1057 #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1058 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1059 #define ath_hal_setrxchainmask(_ah, _rx) \ 1060 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1061 #define ath_hal_settxchainmask(_ah, _tx) \ 1062 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1063 #define ath_hal_split4ktrans(_ah) \ 1064 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1065 0, NULL) == HAL_OK) 1066 #define ath_hal_self_linked_final_rxdesc(_ah) \ 1067 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1068 0, NULL) == HAL_OK) 1069 #define ath_hal_gtxto_supported(_ah) \ 1070 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1071 #define ath_hal_has_long_rxdesc_tsf(_ah) \ 1072 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1073 0, NULL) == HAL_OK) 1074 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1075 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1076 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1077 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1078 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1079 _txr0, _txtr0, _keyix, _ant, _flags, \ 1080 _rtsrate, _rtsdura) \ 1081 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1082 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1083 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1084 #define ath_hal_setupxtxdesc(_ah, _ds, \ 1085 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1086 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1087 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1088 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 1089 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 1090 #define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1091 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1092 #define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1093 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1094 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1095 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1096 #define ath_hal_settxdesclink(_ah, _ds, _link) \ 1097 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1098 #define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1099 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1100 #define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1101 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1102 #define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1103 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1104 (_size))) 1105 1106 #define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1107 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1108 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1109 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1110 #define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 1111 _cipher, _delims, _seglen, _first, _last, _lastaggr) \ 1112 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \ 1113 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 1114 (_first), (_last), (_lastaggr))) 1115 #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1116 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1117 1118 #define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1119 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1120 (_series), (_ns), (_flags))) 1121 1122 #define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1123 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 1124 #define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1125 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1126 #define ath_hal_set11n_aggr_last(_ah, _ds) \ 1127 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1128 1129 #define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1130 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1131 #define ath_hal_clr11n_aggr(_ah, _ds) \ 1132 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1133 1134 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1135 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1136 #define ath_hal_gpioset(_ah, _gpio, _b) \ 1137 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1138 #define ath_hal_gpioget(_ah, _gpio) \ 1139 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1140 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1141 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1142 1143 /* 1144 * PCIe suspend/resume/poweron/poweroff related macros 1145 */ 1146 #define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1147 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1148 #define ath_hal_disablepcie(_ah) \ 1149 ((*(_ah)->ah_disablePCIE)((_ah))) 1150 1151 /* 1152 * This is badly-named; you need to set the correct parameters 1153 * to begin to receive useful radar events; and even then 1154 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1155 * more information. 1156 */ 1157 #define ath_hal_enabledfs(_ah, _param) \ 1158 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1159 #define ath_hal_getdfsthresh(_ah, _param) \ 1160 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1161 #define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1162 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1163 (_buf), (_event))) 1164 #define ath_hal_is_fast_clock_enabled(_ah) \ 1165 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1166 #define ath_hal_radar_wait(_ah, _chan) \ 1167 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1168 #define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1169 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1170 #define ath_hal_get_chan_ext_busy(_ah) \ 1171 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1172 1173 #endif /* _DEV_ATH_ATHVAR_H */ 1174