1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35 #ifndef _DEV_ATH_ATHVAR_H 36 #define _DEV_ATH_ATHVAR_H 37 38 #include <dev/ath/ath_hal/ah.h> 39 #include <dev/ath/ath_hal/ah_desc.h> 40 #include <net80211/ieee80211_radiotap.h> 41 #include <dev/ath/if_athioctl.h> 42 #include <dev/ath/if_athrate.h> 43 44 #define ATH_TIMEOUT 1000 45 46 /* 47 * 802.11n requires more TX and RX buffers to do AMPDU. 48 */ 49 #ifdef ATH_ENABLE_11N 50 #define ATH_TXBUF 512 51 #define ATH_RXBUF 512 52 #endif 53 54 #ifndef ATH_RXBUF 55 #define ATH_RXBUF 40 /* number of RX buffers */ 56 #endif 57 #ifndef ATH_TXBUF 58 #define ATH_TXBUF 200 /* number of TX buffers */ 59 #endif 60 #define ATH_BCBUF 4 /* number of beacon buffers */ 61 62 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 63 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 64 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 65 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 66 67 #define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 68 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 69 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 70 71 /* 72 * The key cache is used for h/w cipher state and also for 73 * tracking station state such as the current tx antenna. 74 * We also setup a mapping table between key cache slot indices 75 * and station state to short-circuit node lookups on rx. 76 * Different parts have different size key caches. We handle 77 * up to ATH_KEYMAX entries (could dynamically allocate state). 78 */ 79 #define ATH_KEYMAX 128 /* max key cache size we handle */ 80 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 81 82 struct taskqueue; 83 struct kthread; 84 struct ath_buf; 85 86 #define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 87 88 /* 89 * Per-TID state 90 * 91 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 92 */ 93 struct ath_tid { 94 TAILQ_HEAD(,ath_buf) axq_q; /* pending buffers */ 95 u_int axq_depth; /* SW queue depth */ 96 char axq_name[48]; /* lock name */ 97 struct ath_node *an; /* pointer to parent */ 98 int tid; /* tid */ 99 int ac; /* which AC gets this trafic */ 100 int hwq_depth; /* how many buffers are on HW */ 101 102 /* 103 * Entry on the ath_txq; when there's traffic 104 * to send 105 */ 106 TAILQ_ENTRY(ath_tid) axq_qelem; 107 int sched; 108 int paused; /* >0 if the TID has been paused */ 109 int bar_wait; /* waiting for BAR */ 110 int bar_tx; /* BAR TXed */ 111 112 /* 113 * Is the TID being cleaned up after a transition 114 * from aggregation to non-aggregation? 115 * When this is set to 1, this TID will be paused 116 * and no further traffic will be queued until all 117 * the hardware packets pending for this TID have been 118 * TXed/completed; at which point (non-aggregation) 119 * traffic will resume being TXed. 120 */ 121 int cleanup_inprogress; 122 /* 123 * How many hardware-queued packets are 124 * waiting to be cleaned up. 125 * This is only valid if cleanup_inprogress is 1. 126 */ 127 int incomp; 128 129 /* 130 * The following implements a ring representing 131 * the frames in the current BAW. 132 * To avoid copying the array content each time 133 * the BAW is moved, the baw_head/baw_tail point 134 * to the current BAW begin/end; when the BAW is 135 * shifted the head/tail of the array are also 136 * appropriately shifted. 137 */ 138 /* active tx buffers, beginning at current BAW */ 139 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 140 /* where the baw head is in the array */ 141 int baw_head; 142 /* where the BAW tail is in the array */ 143 int baw_tail; 144 }; 145 146 /* driver-specific node state */ 147 struct ath_node { 148 struct ieee80211_node an_node; /* base class */ 149 u_int8_t an_mgmtrix; /* min h/w rate index */ 150 u_int8_t an_mcastrix; /* mcast h/w rate index */ 151 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 152 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 153 char an_name[32]; /* eg "wlan0_a1" */ 154 struct mtx an_mtx; /* protecting the ath_node state */ 155 /* variable-length rate control state follows */ 156 }; 157 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 158 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 159 160 #define ATH_RSSI_LPF_LEN 10 161 #define ATH_RSSI_DUMMY_MARKER 0x127 162 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 163 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 164 #define ATH_LPF_RSSI(x, y, len) \ 165 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 166 #define ATH_RSSI_LPF(x, y) do { \ 167 if ((y) >= -20) \ 168 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 169 } while (0) 170 #define ATH_EP_RND(x,mul) \ 171 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 172 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 173 174 struct ath_buf { 175 TAILQ_ENTRY(ath_buf) bf_list; 176 struct ath_buf * bf_next; /* next buffer in the aggregate */ 177 int bf_nseg; 178 uint16_t bf_txflags; /* tx descriptor flags */ 179 uint16_t bf_flags; /* status flags (below) */ 180 struct ath_desc *bf_desc; /* virtual addr of desc */ 181 struct ath_desc_status bf_status; /* tx/rx status */ 182 bus_addr_t bf_daddr; /* physical addr of desc */ 183 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 184 struct mbuf *bf_m; /* mbuf for buf */ 185 struct ieee80211_node *bf_node; /* pointer to the node */ 186 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 187 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 188 bus_size_t bf_mapsize; 189 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 190 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 191 192 /* Completion function to call on TX complete (fail or not) */ 193 /* 194 * "fail" here is set to 1 if the queue entries were removed 195 * through a call to ath_tx_draintxq(). 196 */ 197 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 198 199 /* This state is kept to support software retries and aggregation */ 200 struct { 201 int bfs_seqno; /* sequence number of this packet */ 202 int bfs_retries; /* retry count */ 203 uint16_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 204 uint16_t bfs_pri; /* packet AC priority */ 205 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 206 uint16_t bfs_pktdur; /* packet duration (at current rate?) */ 207 uint16_t bfs_nframes; /* number of frames in aggregate */ 208 uint16_t bfs_ndelim; /* number of delims for padding */ 209 210 int bfs_aggr:1; /* part of aggregate? */ 211 int bfs_aggrburst:1; /* part of aggregate burst? */ 212 int bfs_isretried:1; /* retried frame? */ 213 int bfs_dobaw:1; /* actually check against BAW? */ 214 int bfs_addedbaw:1; /* has been added to the BAW */ 215 int bfs_shpream:1; /* use short preamble */ 216 int bfs_istxfrag:1; /* is fragmented */ 217 int bfs_ismrr:1; /* do multi-rate TX retry */ 218 int bfs_doprot:1; /* do RTS/CTS based protection */ 219 int bfs_doratelookup:1; /* do rate lookup before each TX */ 220 int bfs_need_seqno:1; /* need to assign a seqno for aggregation */ 221 int bfs_seqno_assigned:1; /* seqno has been assigned */ 222 int bfs_nfl; /* next fragment length */ 223 224 /* 225 * These fields are passed into the 226 * descriptor setup functions. 227 */ 228 HAL_PKT_TYPE bfs_atype; /* packet type */ 229 int bfs_pktlen; /* length of this packet */ 230 int bfs_hdrlen; /* length of this packet header */ 231 uint16_t bfs_al; /* length of aggregate */ 232 int bfs_flags; /* HAL descriptor flags */ 233 int bfs_txrate0; /* first TX rate */ 234 int bfs_try0; /* first try count */ 235 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 236 int bfs_keyix; /* crypto key index */ 237 int bfs_txpower; /* tx power */ 238 int bfs_txantenna; /* TX antenna config */ 239 enum ieee80211_protmode bfs_protmode; 240 HAL_11N_RATE_SERIES bfs_rc11n[ATH_RC_NUM]; /* 11n TX series */ 241 int bfs_ctsrate; /* CTS rate */ 242 int bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 243 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 244 } bf_state; 245 }; 246 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 247 248 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 249 250 /* 251 * DMA state for tx/rx descriptors. 252 */ 253 struct ath_descdma { 254 const char* dd_name; 255 struct ath_desc *dd_desc; /* descriptors */ 256 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 257 bus_size_t dd_desc_len; /* size of dd_desc */ 258 bus_dma_segment_t dd_dseg; 259 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 260 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 261 struct ath_buf *dd_bufptr; /* associated buffers */ 262 }; 263 264 /* 265 * Data transmit queue state. One of these exists for each 266 * hardware transmit queue. Packets sent to us from above 267 * are assigned to queues based on their priority. Not all 268 * devices support a complete set of hardware transmit queues. 269 * For those devices the array sc_ac2q will map multiple 270 * priorities to fewer hardware queues (typically all to one 271 * hardware queue). 272 */ 273 struct ath_txq { 274 struct ath_softc *axq_softc; /* Needed for scheduling */ 275 u_int axq_qnum; /* hardware q number */ 276 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 277 u_int axq_ac; /* WME AC */ 278 u_int axq_flags; 279 #define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 280 u_int axq_depth; /* queue depth (stat only) */ 281 u_int axq_aggr_depth; /* how many aggregates are queued */ 282 u_int axq_intrcnt; /* interrupt count */ 283 u_int32_t *axq_link; /* link ptr in last TX desc */ 284 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 285 struct mtx axq_lock; /* lock on q and link */ 286 char axq_name[12]; /* e.g. "ath0_txq4" */ 287 288 /* Per-TID traffic queue for software -> hardware TX */ 289 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 290 }; 291 292 #define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 293 #define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 294 #define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 295 296 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 297 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 298 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 299 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 300 } while (0) 301 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 302 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 303 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 304 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 305 #define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 306 307 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 308 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 309 (_tq)->axq_depth++; \ 310 } while (0) 311 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 312 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 313 (_tq)->axq_depth++; \ 314 } while (0) 315 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 316 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 317 (_tq)->axq_depth--; \ 318 } while (0) 319 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 320 321 struct ath_vap { 322 struct ieee80211vap av_vap; /* base class */ 323 int av_bslot; /* beacon slot index */ 324 struct ath_buf *av_bcbuf; /* beacon buffer */ 325 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 326 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 327 328 void (*av_recv_mgmt)(struct ieee80211_node *, 329 struct mbuf *, int, int, int); 330 int (*av_newstate)(struct ieee80211vap *, 331 enum ieee80211_state, int); 332 void (*av_bmiss)(struct ieee80211vap *); 333 }; 334 #define ATH_VAP(vap) ((struct ath_vap *)(vap)) 335 336 struct taskqueue; 337 struct ath_tx99; 338 339 /* 340 * Whether to reset the TX/RX queue with or without 341 * a queue flush. 342 */ 343 typedef enum { 344 ATH_RESET_DEFAULT = 0, 345 ATH_RESET_NOLOSS = 1, 346 ATH_RESET_FULL = 2, 347 } ATH_RESET_TYPE; 348 349 struct ath_softc { 350 struct ifnet *sc_ifp; /* interface common */ 351 struct ath_stats sc_stats; /* interface statistics */ 352 struct ath_tx_aggr_stats sc_aggr_stats; 353 int sc_debug; 354 int sc_nvaps; /* # vaps */ 355 int sc_nstavaps; /* # station vaps */ 356 int sc_nmeshvaps; /* # mbss vaps */ 357 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 358 u_int8_t sc_nbssid0; /* # vap's using base mac */ 359 uint32_t sc_bssidmask; /* bssid mask */ 360 361 void (*sc_node_cleanup)(struct ieee80211_node *); 362 void (*sc_node_free)(struct ieee80211_node *); 363 device_t sc_dev; 364 HAL_BUS_TAG sc_st; /* bus space tag */ 365 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 366 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 367 struct mtx sc_mtx; /* master lock (recursive) */ 368 struct mtx sc_pcu_mtx; /* PCU access mutex */ 369 char sc_pcu_mtx_name[32]; 370 struct taskqueue *sc_tq; /* private task queue */ 371 struct ath_hal *sc_ah; /* Atheros HAL */ 372 struct ath_ratectrl *sc_rc; /* tx rate control support */ 373 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 374 void (*sc_setdefantenna)(struct ath_softc *, u_int); 375 unsigned int sc_invalid : 1,/* disable hardware accesses */ 376 sc_mrretry : 1,/* multi-rate retry support */ 377 sc_softled : 1,/* enable LED gpio status */ 378 sc_hardled : 1,/* enable MAC LED status */ 379 sc_splitmic : 1,/* split TKIP MIC keys */ 380 sc_needmib : 1,/* enable MIB stats intr */ 381 sc_diversity: 1,/* enable rx diversity */ 382 sc_hasveol : 1,/* tx VEOL support */ 383 sc_ledstate : 1,/* LED on/off state */ 384 sc_blinking : 1,/* LED blink operation active */ 385 sc_mcastkey : 1,/* mcast key cache search */ 386 sc_scanning : 1,/* scanning active */ 387 sc_syncbeacon:1,/* sync/resync beacon timers */ 388 sc_hasclrkey: 1,/* CLR key supported */ 389 sc_xchanmode: 1,/* extended channel mode */ 390 sc_outdoor : 1,/* outdoor operation */ 391 sc_dturbo : 1,/* dynamic turbo in use */ 392 sc_hasbmask : 1,/* bssid mask support */ 393 sc_hasbmatch: 1,/* bssid match disable support*/ 394 sc_hastsfadd: 1,/* tsf adjust support */ 395 sc_beacons : 1,/* beacons running */ 396 sc_swbmiss : 1,/* sta mode using sw bmiss */ 397 sc_stagbeacons:1,/* use staggered beacons */ 398 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 399 sc_resume_up: 1,/* on resume, start all vaps */ 400 sc_tdma : 1,/* TDMA in use */ 401 sc_setcca : 1,/* set/clr CCA with TDMA */ 402 sc_resetcal : 1,/* reset cal state next trip */ 403 sc_rxslink : 1,/* do self-linked final descriptor */ 404 sc_rxtsf32 : 1;/* RX dec TSF is 32 bits */ 405 uint32_t sc_eerd; /* regdomain from EEPROM */ 406 uint32_t sc_eecc; /* country code from EEPROM */ 407 /* rate tables */ 408 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 409 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 410 enum ieee80211_phymode sc_curmode; /* current phy mode */ 411 HAL_OPMODE sc_opmode; /* current operating mode */ 412 u_int16_t sc_curtxpow; /* current tx power limit */ 413 u_int16_t sc_curaid; /* current association id */ 414 struct ieee80211_channel *sc_curchan; /* current installed channel */ 415 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 416 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 417 struct { 418 u_int8_t ieeerate; /* IEEE rate */ 419 u_int8_t rxflags; /* radiotap rx flags */ 420 u_int8_t txflags; /* radiotap tx flags */ 421 u_int16_t ledon; /* softled on time */ 422 u_int16_t ledoff; /* softled off time */ 423 } sc_hwmap[32]; /* h/w rate ix mappings */ 424 u_int8_t sc_protrix; /* protection rate index */ 425 u_int8_t sc_lastdatarix; /* last data frame rate index */ 426 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 427 u_int sc_fftxqmin; /* min frames before staging */ 428 u_int sc_fftxqmax; /* max frames before drop */ 429 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 430 431 HAL_INT sc_imask; /* interrupt mask copy */ 432 433 /* 434 * These are modified in the interrupt handler as well as 435 * the task queues and other contexts. Thus these must be 436 * protected by a mutex, or they could clash. 437 * 438 * For now, access to these is behind the ATH_LOCK, 439 * just to save time. 440 */ 441 uint32_t sc_txq_active; /* bitmap of active TXQs */ 442 uint32_t sc_kickpcu; /* whether to kick the PCU */ 443 uint32_t sc_rxproc_cnt; /* In RX processing */ 444 uint32_t sc_txproc_cnt; /* In TX processing */ 445 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 446 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 447 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 448 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 449 450 u_int sc_keymax; /* size of key cache */ 451 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 452 453 /* 454 * Software based LED blinking 455 */ 456 u_int sc_ledpin; /* GPIO pin for driving LED */ 457 u_int sc_ledon; /* pin setting for LED on */ 458 u_int sc_ledidle; /* idle polling interval */ 459 int sc_ledevent; /* time of last LED event */ 460 u_int8_t sc_txrix; /* current tx rate for LED */ 461 u_int16_t sc_ledoff; /* off time for current blink */ 462 struct callout sc_ledtimer; /* led off timer */ 463 464 /* 465 * Hardware based LED blinking 466 */ 467 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 468 int sc_led_net_pin; /* MAC network LED GPIO pin */ 469 470 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 471 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 472 473 struct ath_descdma sc_rxdma; /* RX descriptors */ 474 ath_bufhead sc_rxbuf; /* receive buffer */ 475 struct mbuf *sc_rxpending; /* pending receive data */ 476 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 477 struct task sc_rxtask; /* rx int processing */ 478 u_int8_t sc_defant; /* current default antenna */ 479 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 480 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 481 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 482 struct ath_rx_radiotap_header sc_rx_th; 483 int sc_rx_th_len; 484 u_int sc_monpass; /* frames to pass in mon.mode */ 485 486 struct ath_descdma sc_txdma; /* TX descriptors */ 487 ath_bufhead sc_txbuf; /* transmit buffer */ 488 struct mtx sc_txbuflock; /* txbuf lock */ 489 char sc_txname[12]; /* e.g. "ath0_buf" */ 490 u_int sc_txqsetup; /* h/w queues setup */ 491 u_int sc_txintrperiod;/* tx interrupt batching */ 492 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 493 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 494 struct task sc_txtask; /* tx int processing */ 495 struct task sc_txqtask; /* tx proc processing */ 496 int sc_wd_timer; /* count down for wd timer */ 497 struct callout sc_wd_ch; /* tx watchdog timer */ 498 struct ath_tx_radiotap_header sc_tx_th; 499 int sc_tx_th_len; 500 501 struct ath_descdma sc_bdma; /* beacon descriptors */ 502 ath_bufhead sc_bbuf; /* beacon buffers */ 503 u_int sc_bhalq; /* HAL q for outgoing beacons */ 504 u_int sc_bmisscount; /* missed beacon transmits */ 505 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 506 struct ath_txq *sc_cabq; /* tx q for cab frames */ 507 struct task sc_bmisstask; /* bmiss int processing */ 508 struct task sc_bstucktask; /* stuck beacon processing */ 509 struct task sc_resettask; /* interface reset task */ 510 enum { 511 OK, /* no change needed */ 512 UPDATE, /* update pending */ 513 COMMIT /* beacon sent, commit change */ 514 } sc_updateslot; /* slot time update fsm */ 515 int sc_slotupdate; /* slot to advance fsm */ 516 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 517 int sc_nbcnvaps; /* # vaps with beacons */ 518 519 struct callout sc_cal_ch; /* callout handle for cals */ 520 int sc_lastlongcal; /* last long cal completed */ 521 int sc_lastcalreset;/* last cal reset done */ 522 int sc_lastani; /* last ANI poll */ 523 int sc_lastshortcal; /* last short calibration */ 524 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 525 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 526 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 527 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 528 u_int sc_tdmaswba; /* TDMA SWBA counter */ 529 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 530 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 531 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 532 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 533 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 534 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 535 int sc_txchainmask; /* currently configured TX chainmask */ 536 int sc_rxchainmask; /* currently configured RX chainmask */ 537 538 /* Queue limits */ 539 540 /* 541 * To avoid queue starvation in congested conditions, 542 * these parameters tune the maximum number of frames 543 * queued to the data/mcastq before they're dropped. 544 * 545 * This is to prevent: 546 * + a single destination overwhelming everything, including 547 * management/multicast frames; 548 * + multicast frames overwhelming everything (when the 549 * air is sufficiently busy that cabq can't drain.) 550 * 551 * These implement: 552 * + data_minfree is the maximum number of free buffers 553 * overall to successfully allow a data frame. 554 * 555 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 556 */ 557 int sc_txq_data_minfree; 558 int sc_txq_mcastq_maxdepth; 559 560 /* 561 * Aggregation twiddles 562 * 563 * hwq_limit: how busy to keep the hardware queue - don't schedule 564 * further packets to the hardware, regardless of the TID 565 * tid_hwq_lo: how low the per-TID hwq count has to be before the 566 * TID will be scheduled again 567 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 568 * stops being scheduled. 569 */ 570 int sc_hwq_limit; 571 int sc_tid_hwq_lo; 572 int sc_tid_hwq_hi; 573 574 /* DFS related state */ 575 void *sc_dfs; /* Used by an optional DFS module */ 576 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 577 struct task sc_dfstask; /* DFS processing task */ 578 579 /* TX AMPDU handling */ 580 int (*sc_addba_request)(struct ieee80211_node *, 581 struct ieee80211_tx_ampdu *, int, int, int); 582 int (*sc_addba_response)(struct ieee80211_node *, 583 struct ieee80211_tx_ampdu *, int, int, int); 584 void (*sc_addba_stop)(struct ieee80211_node *, 585 struct ieee80211_tx_ampdu *); 586 void (*sc_addba_response_timeout) 587 (struct ieee80211_node *, 588 struct ieee80211_tx_ampdu *); 589 void (*sc_bar_response)(struct ieee80211_node *ni, 590 struct ieee80211_tx_ampdu *tap, 591 int status); 592 }; 593 594 #define ATH_LOCK_INIT(_sc) \ 595 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 596 NULL, MTX_DEF | MTX_RECURSE) 597 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 598 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 599 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 600 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 601 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 602 603 /* 604 * The PCU lock is non-recursive and should be treated as a spinlock. 605 * Although currently the interrupt code is run in netisr context and 606 * doesn't require this, this may change in the future. 607 * Please keep this in mind when protecting certain code paths 608 * with the PCU lock. 609 * 610 * The PCU lock is used to serialise access to the PCU so things such 611 * as TX, RX, state change (eg channel change), channel reset and updates 612 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 613 * 614 * Although the current single-thread taskqueue mechanism protects the 615 * majority of these situations by simply serialising them, there are 616 * a few others which occur at the same time. These include the TX path 617 * (which only acquires ATH_LOCK when recycling buffers to the free list), 618 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 619 */ 620 #define ATH_PCU_LOCK_INIT(_sc) do {\ 621 snprintf((_sc)->sc_pcu_mtx_name, \ 622 sizeof((_sc)->sc_pcu_mtx_name), \ 623 "%s PCU lock", \ 624 device_get_nameunit((_sc)->sc_dev)); \ 625 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 626 NULL, MTX_DEF); \ 627 } while (0) 628 #define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 629 #define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 630 #define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 631 #define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 632 MA_OWNED) 633 #define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 634 MA_NOTOWNED) 635 636 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 637 638 #define ATH_TXBUF_LOCK_INIT(_sc) do { \ 639 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 640 device_get_nameunit((_sc)->sc_dev)); \ 641 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 642 } while (0) 643 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 644 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 645 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 646 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 647 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 648 649 int ath_attach(u_int16_t, struct ath_softc *); 650 int ath_detach(struct ath_softc *); 651 void ath_resume(struct ath_softc *); 652 void ath_suspend(struct ath_softc *); 653 void ath_shutdown(struct ath_softc *); 654 void ath_intr(void *); 655 656 /* 657 * HAL definitions to comply with local coding convention. 658 */ 659 #define ath_hal_detach(_ah) \ 660 ((*(_ah)->ah_detach)((_ah))) 661 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 662 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 663 #define ath_hal_macversion(_ah) \ 664 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 665 #define ath_hal_getratetable(_ah, _mode) \ 666 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 667 #define ath_hal_getmac(_ah, _mac) \ 668 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 669 #define ath_hal_setmac(_ah, _mac) \ 670 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 671 #define ath_hal_getbssidmask(_ah, _mask) \ 672 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 673 #define ath_hal_setbssidmask(_ah, _mask) \ 674 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 675 #define ath_hal_intrset(_ah, _mask) \ 676 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 677 #define ath_hal_intrget(_ah) \ 678 ((*(_ah)->ah_getInterrupts)((_ah))) 679 #define ath_hal_intrpend(_ah) \ 680 ((*(_ah)->ah_isInterruptPending)((_ah))) 681 #define ath_hal_getisr(_ah, _pmask) \ 682 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 683 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 684 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 685 #define ath_hal_setpower(_ah, _mode) \ 686 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 687 #define ath_hal_keycachesize(_ah) \ 688 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 689 #define ath_hal_keyreset(_ah, _ix) \ 690 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 691 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 692 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 693 #define ath_hal_keyisvalid(_ah, _ix) \ 694 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 695 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 696 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 697 #define ath_hal_getrxfilter(_ah) \ 698 ((*(_ah)->ah_getRxFilter)((_ah))) 699 #define ath_hal_setrxfilter(_ah, _filter) \ 700 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 701 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 702 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 703 #define ath_hal_waitforbeacon(_ah, _bf) \ 704 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 705 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 706 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 707 /* NB: common across all chips */ 708 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 709 #define ath_hal_gettsf32(_ah) \ 710 OS_REG_READ(_ah, AR_TSF_L32) 711 #define ath_hal_gettsf64(_ah) \ 712 ((*(_ah)->ah_getTsf64)((_ah))) 713 #define ath_hal_resettsf(_ah) \ 714 ((*(_ah)->ah_resetTsf)((_ah))) 715 #define ath_hal_rxena(_ah) \ 716 ((*(_ah)->ah_enableReceive)((_ah))) 717 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 718 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 719 #define ath_hal_gettxbuf(_ah, _q) \ 720 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 721 #define ath_hal_numtxpending(_ah, _q) \ 722 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 723 #define ath_hal_getrxbuf(_ah) \ 724 ((*(_ah)->ah_getRxDP)((_ah))) 725 #define ath_hal_txstart(_ah, _q) \ 726 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 727 #define ath_hal_setchannel(_ah, _chan) \ 728 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 729 #define ath_hal_calibrate(_ah, _chan, _iqcal) \ 730 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 731 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 732 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 733 #define ath_hal_calreset(_ah, _chan) \ 734 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 735 #define ath_hal_setledstate(_ah, _state) \ 736 ((*(_ah)->ah_setLedState)((_ah), (_state))) 737 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 738 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 739 #define ath_hal_beaconreset(_ah) \ 740 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 741 #define ath_hal_beaconsettimers(_ah, _bt) \ 742 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 743 #define ath_hal_beacontimers(_ah, _bs) \ 744 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 745 #define ath_hal_getnexttbtt(_ah) \ 746 ((*(_ah)->ah_getNextTBTT)((_ah))) 747 #define ath_hal_setassocid(_ah, _bss, _associd) \ 748 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 749 #define ath_hal_phydisable(_ah) \ 750 ((*(_ah)->ah_phyDisable)((_ah))) 751 #define ath_hal_setopmode(_ah) \ 752 ((*(_ah)->ah_setPCUConfig)((_ah))) 753 #define ath_hal_stoptxdma(_ah, _qnum) \ 754 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 755 #define ath_hal_stoppcurecv(_ah) \ 756 ((*(_ah)->ah_stopPcuReceive)((_ah))) 757 #define ath_hal_startpcurecv(_ah) \ 758 ((*(_ah)->ah_startPcuReceive)((_ah))) 759 #define ath_hal_stopdmarecv(_ah) \ 760 ((*(_ah)->ah_stopDmaReceive)((_ah))) 761 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 762 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 763 (_indata), (_insize), (_outdata), (_outsize))) 764 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 765 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 766 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 767 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 768 #define ath_hal_resettxqueue(_ah, _q) \ 769 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 770 #define ath_hal_releasetxqueue(_ah, _q) \ 771 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 772 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 773 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 774 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 775 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 776 /* NB: common across all chips */ 777 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 778 #define ath_hal_txqenabled(_ah, _qnum) \ 779 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 780 #define ath_hal_getrfgain(_ah) \ 781 ((*(_ah)->ah_getRfGain)((_ah))) 782 #define ath_hal_getdefantenna(_ah) \ 783 ((*(_ah)->ah_getDefAntenna)((_ah))) 784 #define ath_hal_setdefantenna(_ah, _ant) \ 785 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 786 #define ath_hal_rxmonitor(_ah, _arg, _chan) \ 787 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 788 #define ath_hal_ani_poll(_ah, _chan) \ 789 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 790 #define ath_hal_mibevent(_ah, _stats) \ 791 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 792 #define ath_hal_setslottime(_ah, _us) \ 793 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 794 #define ath_hal_getslottime(_ah) \ 795 ((*(_ah)->ah_getSlotTime)((_ah))) 796 #define ath_hal_setacktimeout(_ah, _us) \ 797 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 798 #define ath_hal_getacktimeout(_ah) \ 799 ((*(_ah)->ah_getAckTimeout)((_ah))) 800 #define ath_hal_setctstimeout(_ah, _us) \ 801 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 802 #define ath_hal_getctstimeout(_ah) \ 803 ((*(_ah)->ah_getCTSTimeout)((_ah))) 804 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 805 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 806 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 807 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 808 #define ath_hal_ciphersupported(_ah, _cipher) \ 809 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 810 #define ath_hal_getregdomain(_ah, _prd) \ 811 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 812 #define ath_hal_setregdomain(_ah, _rd) \ 813 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 814 #define ath_hal_getcountrycode(_ah, _pcc) \ 815 (*(_pcc) = (_ah)->ah_countryCode) 816 #define ath_hal_gettkipmic(_ah) \ 817 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 818 #define ath_hal_settkipmic(_ah, _v) \ 819 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 820 #define ath_hal_hastkipsplit(_ah) \ 821 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 822 #define ath_hal_gettkipsplit(_ah) \ 823 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 824 #define ath_hal_settkipsplit(_ah, _v) \ 825 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 826 #define ath_hal_haswmetkipmic(_ah) \ 827 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 828 #define ath_hal_hwphycounters(_ah) \ 829 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 830 #define ath_hal_hasdiversity(_ah) \ 831 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 832 #define ath_hal_getdiversity(_ah) \ 833 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 834 #define ath_hal_setdiversity(_ah, _v) \ 835 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 836 #define ath_hal_getantennaswitch(_ah) \ 837 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 838 #define ath_hal_setantennaswitch(_ah, _v) \ 839 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 840 #define ath_hal_getdiag(_ah, _pv) \ 841 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 842 #define ath_hal_setdiag(_ah, _v) \ 843 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 844 #define ath_hal_getnumtxqueues(_ah, _pv) \ 845 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 846 #define ath_hal_hasveol(_ah) \ 847 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 848 #define ath_hal_hastxpowlimit(_ah) \ 849 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 850 #define ath_hal_settxpowlimit(_ah, _pow) \ 851 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 852 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 853 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 854 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 855 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 856 #define ath_hal_gettpscale(_ah, _scale) \ 857 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 858 #define ath_hal_settpscale(_ah, _v) \ 859 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 860 #define ath_hal_hastpc(_ah) \ 861 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 862 #define ath_hal_gettpc(_ah) \ 863 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 864 #define ath_hal_settpc(_ah, _v) \ 865 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 866 #define ath_hal_hasbursting(_ah) \ 867 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 868 #define ath_hal_setmcastkeysearch(_ah, _v) \ 869 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 870 #define ath_hal_hasmcastkeysearch(_ah) \ 871 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 872 #define ath_hal_getmcastkeysearch(_ah) \ 873 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 874 #define ath_hal_hasfastframes(_ah) \ 875 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 876 #define ath_hal_hasbssidmask(_ah) \ 877 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 878 #define ath_hal_hasbssidmatch(_ah) \ 879 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 880 #define ath_hal_hastsfadjust(_ah) \ 881 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 882 #define ath_hal_gettsfadjust(_ah) \ 883 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 884 #define ath_hal_settsfadjust(_ah, _onoff) \ 885 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 886 #define ath_hal_hasrfsilent(_ah) \ 887 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 888 #define ath_hal_getrfkill(_ah) \ 889 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 890 #define ath_hal_setrfkill(_ah, _onoff) \ 891 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 892 #define ath_hal_getrfsilent(_ah, _prfsilent) \ 893 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 894 #define ath_hal_setrfsilent(_ah, _rfsilent) \ 895 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 896 #define ath_hal_gettpack(_ah, _ptpack) \ 897 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 898 #define ath_hal_settpack(_ah, _tpack) \ 899 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 900 #define ath_hal_gettpcts(_ah, _ptpcts) \ 901 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 902 #define ath_hal_settpcts(_ah, _tpcts) \ 903 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 904 #define ath_hal_hasintmit(_ah) \ 905 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 906 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 907 #define ath_hal_getintmit(_ah) \ 908 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 909 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 910 #define ath_hal_setintmit(_ah, _v) \ 911 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 912 HAL_CAP_INTMIT_ENABLE, _v, NULL) 913 #define ath_hal_getchannoise(_ah, _c) \ 914 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 915 #define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 916 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 917 #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 918 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 919 #define ath_hal_setrxchainmask(_ah, _rx) \ 920 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 921 #define ath_hal_settxchainmask(_ah, _tx) \ 922 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 923 #define ath_hal_split4ktrans(_ah) \ 924 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 925 0, NULL) == HAL_OK) 926 #define ath_hal_self_linked_final_rxdesc(_ah) \ 927 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 928 0, NULL) == HAL_OK) 929 #define ath_hal_gtxto_supported(_ah) \ 930 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 931 #define ath_hal_has_long_rxdesc_tsf(_ah) \ 932 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 933 0, NULL) == HAL_OK) 934 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 935 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 936 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 937 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 938 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 939 _txr0, _txtr0, _keyix, _ant, _flags, \ 940 _rtsrate, _rtsdura) \ 941 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 942 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 943 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 944 #define ath_hal_setupxtxdesc(_ah, _ds, \ 945 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 946 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 947 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 948 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 949 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 950 #define ath_hal_txprocdesc(_ah, _ds, _ts) \ 951 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 952 #define ath_hal_gettxintrtxqs(_ah, _txqs) \ 953 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 954 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 955 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 956 957 #define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 958 _txr0, _txtr0, _antm, _rcr, _rcd) \ 959 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 960 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 961 #define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 962 _cipher, _delims, _seglen, _first, _last, _lastaggr) \ 963 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_pktlen), (_hdrlen), \ 964 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 965 (_first), (_last), (_lastaggr))) 966 #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 967 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 968 969 #define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 970 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 971 (_series), (_ns), (_flags))) 972 973 #define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 974 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num))) 975 #define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 976 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 977 #define ath_hal_set11n_aggr_last(_ah, _ds) \ 978 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 979 980 #define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 981 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 982 #define ath_hal_clr11n_aggr(_ah, _ds) \ 983 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 984 985 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 986 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 987 #define ath_hal_gpioset(_ah, _gpio, _b) \ 988 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 989 #define ath_hal_gpioget(_ah, _gpio) \ 990 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 991 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 992 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 993 994 /* 995 * This is badly-named; you need to set the correct parameters 996 * to begin to receive useful radar events; and even then 997 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 998 * more information. 999 */ 1000 #define ath_hal_enabledfs(_ah, _param) \ 1001 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1002 #define ath_hal_getdfsthresh(_ah, _param) \ 1003 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1004 #define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1005 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1006 (_buf), (_event))) 1007 #define ath_hal_is_fast_clock_enabled(_ah) \ 1008 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1009 #define ath_hal_radar_wait(_ah, _chan) \ 1010 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1011 #define ath_hal_get_chan_ext_busy(_ah) \ 1012 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1013 1014 #endif /* _DEV_ATH_ATHVAR_H */ 1015