xref: /freebsd/sys/dev/ath/if_athvar.h (revision 273c26a3c3bea87a241d6879abd4f991db180bf0)
1 /*-
2  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification.
11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13  *    redistribution must be conditioned upon including a substantially
14  *    similar Disclaimer requirement for further binary redistribution.
15  *
16  * NO WARRANTY
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27  * THE POSSIBILITY OF SUCH DAMAGES.
28  *
29  * $FreeBSD$
30  */
31 
32 /*
33  * Defintions for the Atheros Wireless LAN controller driver.
34  */
35 #ifndef _DEV_ATH_ATHVAR_H
36 #define _DEV_ATH_ATHVAR_H
37 
38 #include <machine/atomic.h>
39 
40 #include <dev/ath/ath_hal/ah.h>
41 #include <dev/ath/ath_hal/ah_desc.h>
42 #include <net80211/ieee80211_radiotap.h>
43 #include <dev/ath/if_athioctl.h>
44 #include <dev/ath/if_athrate.h>
45 #ifdef	ATH_DEBUG_ALQ
46 #include <dev/ath/if_ath_alq.h>
47 #endif
48 
49 #define	ATH_TIMEOUT		1000
50 
51 /*
52  * There is a separate TX ath_buf pool for management frames.
53  * This ensures that management frames such as probe responses
54  * and BAR frames can be transmitted during periods of high
55  * TX activity.
56  */
57 #define	ATH_MGMT_TXBUF		32
58 
59 /*
60  * 802.11n requires more TX and RX buffers to do AMPDU.
61  */
62 #ifdef	ATH_ENABLE_11N
63 #define	ATH_TXBUF	512
64 #define	ATH_RXBUF	512
65 #endif
66 
67 #ifndef ATH_RXBUF
68 #define	ATH_RXBUF	40		/* number of RX buffers */
69 #endif
70 #ifndef ATH_TXBUF
71 #define	ATH_TXBUF	200		/* number of TX buffers */
72 #endif
73 #define	ATH_BCBUF	4		/* number of beacon buffers */
74 
75 #define	ATH_TXDESC	10		/* number of descriptors per buffer */
76 #define	ATH_TXMAXTRY	11		/* max number of transmit attempts */
77 #define	ATH_TXMGTTRY	4		/* xmit attempts for mgt/ctl frames */
78 #define	ATH_TXINTR_PERIOD 5		/* max number of batched tx descriptors */
79 
80 #define	ATH_BEACON_AIFS_DEFAULT	 1	/* default aifs for ap beacon q */
81 #define	ATH_BEACON_CWMIN_DEFAULT 0	/* default cwmin for ap beacon q */
82 #define	ATH_BEACON_CWMAX_DEFAULT 0	/* default cwmax for ap beacon q */
83 
84 /*
85  * The following bits can be set during the PCI (and perhaps non-PCI
86  * later) device probe path.
87  *
88  * It controls some of the driver and HAL behaviour.
89  */
90 
91 #define	ATH_PCI_CUS198		0x0001
92 #define	ATH_PCI_CUS230		0x0002
93 #define	ATH_PCI_CUS217		0x0004
94 #define	ATH_PCI_CUS252		0x0008
95 #define	ATH_PCI_WOW		0x0010
96 #define	ATH_PCI_BT_ANT_DIV	0x0020
97 #define	ATH_PCI_D3_L1_WAR	0x0040
98 #define	ATH_PCI_AR9565_1ANT	0x0080
99 #define	ATH_PCI_AR9565_2ANT	0x0100
100 #define	ATH_PCI_NO_PLL_PWRSAVE	0x0200
101 #define	ATH_PCI_KILLER		0x0400
102 
103 /*
104  * The key cache is used for h/w cipher state and also for
105  * tracking station state such as the current tx antenna.
106  * We also setup a mapping table between key cache slot indices
107  * and station state to short-circuit node lookups on rx.
108  * Different parts have different size key caches.  We handle
109  * up to ATH_KEYMAX entries (could dynamically allocate state).
110  */
111 #define	ATH_KEYMAX	128		/* max key cache size we handle */
112 #define	ATH_KEYBYTES	(ATH_KEYMAX/NBBY)	/* storage space in bytes */
113 
114 struct taskqueue;
115 struct kthread;
116 struct ath_buf;
117 
118 #define	ATH_TID_MAX_BUFS	(2 * IEEE80211_AGGR_BAWMAX)
119 
120 /*
121  * Per-TID state
122  *
123  * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames.
124  */
125 struct ath_tid {
126 	TAILQ_HEAD(,ath_buf)	tid_q;		/* pending buffers */
127 	struct ath_node		*an;		/* pointer to parent */
128 	int			tid;		/* tid */
129 	int			ac;		/* which AC gets this traffic */
130 	int			hwq_depth;	/* how many buffers are on HW */
131 	u_int			axq_depth;	/* SW queue depth */
132 
133 	struct {
134 		TAILQ_HEAD(,ath_buf)	tid_q;		/* filtered queue */
135 		u_int			axq_depth;	/* SW queue depth */
136 	} filtq;
137 
138 	/*
139 	 * Entry on the ath_txq; when there's traffic
140 	 * to send
141 	 */
142 	TAILQ_ENTRY(ath_tid)	axq_qelem;
143 	int			sched;
144 	int			paused;	/* >0 if the TID has been paused */
145 
146 	/*
147 	 * These are flags - perhaps later collapse
148 	 * down to a single uint32_t ?
149 	 */
150 	int			addba_tx_pending;	/* TX ADDBA pending */
151 	int			bar_wait;	/* waiting for BAR */
152 	int			bar_tx;		/* BAR TXed */
153 	int			isfiltered;	/* is this node currently filtered */
154 
155 	/*
156 	 * Is the TID being cleaned up after a transition
157 	 * from aggregation to non-aggregation?
158 	 * When this is set to 1, this TID will be paused
159 	 * and no further traffic will be queued until all
160 	 * the hardware packets pending for this TID have been
161 	 * TXed/completed; at which point (non-aggregation)
162 	 * traffic will resume being TXed.
163 	 */
164 	int			cleanup_inprogress;
165 	/*
166 	 * How many hardware-queued packets are
167 	 * waiting to be cleaned up.
168 	 * This is only valid if cleanup_inprogress is 1.
169 	 */
170 	int			incomp;
171 
172 	/*
173 	 * The following implements a ring representing
174 	 * the frames in the current BAW.
175 	 * To avoid copying the array content each time
176 	 * the BAW is moved, the baw_head/baw_tail point
177 	 * to the current BAW begin/end; when the BAW is
178 	 * shifted the head/tail of the array are also
179 	 * appropriately shifted.
180 	 */
181 	/* active tx buffers, beginning at current BAW */
182 	struct ath_buf		*tx_buf[ATH_TID_MAX_BUFS];
183 	/* where the baw head is in the array */
184 	int			baw_head;
185 	/* where the BAW tail is in the array */
186 	int			baw_tail;
187 };
188 
189 /* driver-specific node state */
190 struct ath_node {
191 	struct ieee80211_node an_node;	/* base class */
192 	u_int8_t	an_mgmtrix;	/* min h/w rate index */
193 	u_int8_t	an_mcastrix;	/* mcast h/w rate index */
194 	uint32_t	an_is_powersave;	/* node is sleeping */
195 	uint32_t	an_stack_psq;		/* net80211 psq isn't empty */
196 	uint32_t	an_tim_set;		/* TIM has been set */
197 	struct ath_buf	*an_ff_buf[WME_NUM_AC]; /* ff staging area */
198 	struct ath_tid	an_tid[IEEE80211_TID_SIZE];	/* per-TID state */
199 	char		an_name[32];	/* eg "wlan0_a1" */
200 	struct mtx	an_mtx;		/* protecting the rate control state */
201 	uint32_t	an_swq_depth;	/* how many SWQ packets for this
202 					   node */
203 	int			clrdmask;	/* has clrdmask been set */
204 	uint32_t	an_leak_count;	/* How many frames to leak during pause */
205 	/* variable-length rate control state follows */
206 };
207 #define	ATH_NODE(ni)	((struct ath_node *)(ni))
208 #define	ATH_NODE_CONST(ni)	((const struct ath_node *)(ni))
209 
210 #define ATH_RSSI_LPF_LEN	10
211 #define ATH_RSSI_DUMMY_MARKER	0x127
212 #define ATH_EP_MUL(x, mul)	((x) * (mul))
213 #define ATH_RSSI_IN(x)		(ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
214 #define ATH_LPF_RSSI(x, y, len) \
215     ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
216 #define ATH_RSSI_LPF(x, y) do {						\
217     if ((y) >= -20)							\
218     	x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN);	\
219 } while (0)
220 #define	ATH_EP_RND(x,mul) \
221 	((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
222 #define	ATH_RSSI(x)		ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER)
223 
224 typedef enum {
225 	ATH_BUFTYPE_NORMAL	= 0,
226 	ATH_BUFTYPE_MGMT	= 1,
227 } ath_buf_type_t;
228 
229 struct ath_buf {
230 	TAILQ_ENTRY(ath_buf)	bf_list;
231 	struct ath_buf *	bf_next;	/* next buffer in the aggregate */
232 	int			bf_nseg;
233 	HAL_STATUS		bf_rxstatus;
234 	uint16_t		bf_flags;	/* status flags (below) */
235 	uint16_t		bf_descid;	/* 16 bit descriptor ID */
236 	struct ath_desc		*bf_desc;	/* virtual addr of desc */
237 	struct ath_desc_status	bf_status;	/* tx/rx status */
238 	bus_addr_t		bf_daddr;	/* physical addr of desc */
239 	bus_dmamap_t		bf_dmamap;	/* DMA map for mbuf chain */
240 	struct mbuf		*bf_m;		/* mbuf for buf */
241 	struct ieee80211_node	*bf_node;	/* pointer to the node */
242 	struct ath_desc		*bf_lastds;	/* last descriptor for comp status */
243 	struct ath_buf		*bf_last;	/* last buffer in aggregate, or self for non-aggregate */
244 	bus_size_t		bf_mapsize;
245 #define	ATH_MAX_SCATTER		ATH_TXDESC	/* max(tx,rx,beacon) desc's */
246 	bus_dma_segment_t	bf_segs[ATH_MAX_SCATTER];
247 	uint32_t		bf_nextfraglen;	/* length of next fragment */
248 
249 	/* Completion function to call on TX complete (fail or not) */
250 	/*
251 	 * "fail" here is set to 1 if the queue entries were removed
252 	 * through a call to ath_tx_draintxq().
253 	 */
254 	void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail);
255 
256 	/* This state is kept to support software retries and aggregation */
257 	struct {
258 		uint16_t bfs_seqno;	/* sequence number of this packet */
259 		uint16_t bfs_ndelim;	/* number of delims for padding */
260 
261 		uint8_t bfs_retries;	/* retry count */
262 		uint8_t bfs_tid;	/* packet TID (or TID_MAX for no QoS) */
263 		uint8_t bfs_nframes;	/* number of frames in aggregate */
264 		uint8_t bfs_pri;	/* packet AC priority */
265 		uint8_t bfs_tx_queue;	/* destination hardware TX queue */
266 
267 		u_int32_t bfs_aggr:1,		/* part of aggregate? */
268 		    bfs_aggrburst:1,	/* part of aggregate burst? */
269 		    bfs_isretried:1,	/* retried frame? */
270 		    bfs_dobaw:1,	/* actually check against BAW? */
271 		    bfs_addedbaw:1,	/* has been added to the BAW */
272 		    bfs_shpream:1,	/* use short preamble */
273 		    bfs_istxfrag:1,	/* is fragmented */
274 		    bfs_ismrr:1,	/* do multi-rate TX retry */
275 		    bfs_doprot:1,	/* do RTS/CTS based protection */
276 		    bfs_doratelookup:1;	/* do rate lookup before each TX */
277 
278 		/*
279 		 * These fields are passed into the
280 		 * descriptor setup functions.
281 		 */
282 
283 		/* Make this an 8 bit value? */
284 		HAL_PKT_TYPE bfs_atype;	/* packet type */
285 
286 		uint32_t bfs_pktlen;	/* length of this packet */
287 
288 		uint16_t bfs_hdrlen;	/* length of this packet header */
289 		uint16_t bfs_al;	/* length of aggregate */
290 
291 		uint16_t bfs_txflags;	/* HAL (tx) descriptor flags */
292 		uint8_t bfs_txrate0;	/* first TX rate */
293 		uint8_t bfs_try0;		/* first try count */
294 
295 		uint16_t bfs_txpower;	/* tx power */
296 		uint8_t bfs_ctsrate0;	/* Non-zero - use this as ctsrate */
297 		uint8_t bfs_ctsrate;	/* CTS rate */
298 
299 		/* 16 bit? */
300 		int32_t bfs_keyix;		/* crypto key index */
301 		int32_t bfs_txantenna;	/* TX antenna config */
302 
303 		/* Make this an 8 bit value? */
304 		enum ieee80211_protmode bfs_protmode;
305 
306 		/* 16 bit? */
307 		uint32_t bfs_ctsduration;	/* CTS duration (pre-11n NICs) */
308 		struct ath_rc_series bfs_rc[ATH_RC_NUM];	/* non-11n TX series */
309 	} bf_state;
310 };
311 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead;
312 
313 #define	ATH_BUF_MGMT	0x00000001	/* (tx) desc is a mgmt desc */
314 #define	ATH_BUF_BUSY	0x00000002	/* (tx) desc owned by h/w */
315 #define	ATH_BUF_FIFOEND	0x00000004
316 #define	ATH_BUF_FIFOPTR	0x00000008
317 #define	ATH_BUF_TOA_PROBE	0x00000010	/* ToD/ToA exchange probe */
318 
319 #define	ATH_BUF_FLAGS_CLONE	(ATH_BUF_MGMT | ATH_BUF_TOA_PROBE)
320 
321 /*
322  * DMA state for tx/rx descriptors.
323  */
324 struct ath_descdma {
325 	const char*		dd_name;
326 	struct ath_desc		*dd_desc;	/* descriptors */
327 	int			dd_descsize;	/* size of single descriptor */
328 	bus_addr_t		dd_desc_paddr;	/* physical addr of dd_desc */
329 	bus_size_t		dd_desc_len;	/* size of dd_desc */
330 	bus_dma_segment_t	dd_dseg;
331 	bus_dma_tag_t		dd_dmat;	/* bus DMA tag */
332 	bus_dmamap_t		dd_dmamap;	/* DMA map for descriptors */
333 	struct ath_buf		*dd_bufptr;	/* associated buffers */
334 };
335 
336 /*
337  * Data transmit queue state.  One of these exists for each
338  * hardware transmit queue.  Packets sent to us from above
339  * are assigned to queues based on their priority.  Not all
340  * devices support a complete set of hardware transmit queues.
341  * For those devices the array sc_ac2q will map multiple
342  * priorities to fewer hardware queues (typically all to one
343  * hardware queue).
344  */
345 struct ath_txq {
346 	struct ath_softc	*axq_softc;	/* Needed for scheduling */
347 	u_int			axq_qnum;	/* hardware q number */
348 #define	ATH_TXQ_SWQ	(HAL_NUM_TX_QUEUES+1)	/* qnum for s/w only queue */
349 	u_int			axq_ac;		/* WME AC */
350 	u_int			axq_flags;
351 //#define	ATH_TXQ_PUTPENDING	0x0001		/* ath_hal_puttxbuf pending */
352 #define	ATH_TXQ_PUTRUNNING	0x0002		/* ath_hal_puttxbuf has been called */
353 	u_int			axq_depth;	/* queue depth (stat only) */
354 	u_int			axq_aggr_depth;	/* how many aggregates are queued */
355 	u_int			axq_intrcnt;	/* interrupt count */
356 	u_int32_t		*axq_link;	/* link ptr in last TX desc */
357 	TAILQ_HEAD(axq_q_s, ath_buf)	axq_q;		/* transmit queue */
358 	struct mtx		axq_lock;	/* lock on q and link */
359 
360 	/*
361 	 * This is the FIFO staging buffer when doing EDMA.
362 	 *
363 	 * For legacy chips, we just push the head pointer to
364 	 * the hardware and we ignore this list.
365 	 *
366 	 * For EDMA, the staging buffer is treated as normal;
367 	 * when it's time to push a list of frames to the hardware
368 	 * we move that list here and we stamp buffers with
369 	 * flags to identify the beginning/end of that particular
370 	 * FIFO entry.
371 	 */
372 	struct {
373 		TAILQ_HEAD(axq_q_f_s, ath_buf)	axq_q;
374 		u_int				axq_depth;	/* how many frames (1 per legacy, 1 per A-MPDU list) are in the FIFO queue */
375 	} fifo;
376 	u_int			axq_fifo_depth;	/* how many FIFO slots are active */
377 
378 	/*
379 	 * XXX the holdingbf field is protected by the TXBUF lock
380 	 * for now, NOT the TXQ lock.
381 	 *
382 	 * Architecturally, it would likely be better to move
383 	 * the holdingbf field to a separate array in ath_softc
384 	 * just to highlight that it's not protected by the normal
385 	 * TX path lock.
386 	 */
387 	struct ath_buf		*axq_holdingbf;	/* holding TX buffer */
388 	char			axq_name[12];	/* e.g. "ath0_txq4" */
389 
390 	/* Per-TID traffic queue for software -> hardware TX */
391 	/*
392 	 * This is protected by the general TX path lock, not (for now)
393 	 * by the TXQ lock.
394 	 */
395 	TAILQ_HEAD(axq_t_s,ath_tid)	axq_tidq;
396 };
397 
398 #define	ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
399 	    snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
400 	      device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
401 	    mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
402 	} while (0)
403 #define	ATH_TXQ_LOCK_DESTROY(_tq)	mtx_destroy(&(_tq)->axq_lock)
404 #define	ATH_TXQ_LOCK(_tq)		mtx_lock(&(_tq)->axq_lock)
405 #define	ATH_TXQ_UNLOCK(_tq)		mtx_unlock(&(_tq)->axq_lock)
406 #define	ATH_TXQ_LOCK_ASSERT(_tq)	mtx_assert(&(_tq)->axq_lock, MA_OWNED)
407 #define	ATH_TXQ_UNLOCK_ASSERT(_tq)	mtx_assert(&(_tq)->axq_lock,	\
408 					    MA_NOTOWNED)
409 
410 
411 #define	ATH_NODE_LOCK(_an)		mtx_lock(&(_an)->an_mtx)
412 #define	ATH_NODE_UNLOCK(_an)		mtx_unlock(&(_an)->an_mtx)
413 #define	ATH_NODE_LOCK_ASSERT(_an)	mtx_assert(&(_an)->an_mtx, MA_OWNED)
414 #define	ATH_NODE_UNLOCK_ASSERT(_an)	mtx_assert(&(_an)->an_mtx,	\
415 					    MA_NOTOWNED)
416 
417 /*
418  * These are for the hardware queue.
419  */
420 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \
421 	TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \
422 	(_tq)->axq_depth++; \
423 } while (0)
424 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
425 	TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
426 	(_tq)->axq_depth++; \
427 } while (0)
428 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \
429 	TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \
430 	(_tq)->axq_depth--; \
431 } while (0)
432 #define	ATH_TXQ_FIRST(_tq)		TAILQ_FIRST(&(_tq)->axq_q)
433 #define	ATH_TXQ_LAST(_tq, _field)	TAILQ_LAST(&(_tq)->axq_q, _field)
434 
435 /*
436  * These are for the TID software queue.
437  */
438 #define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \
439 	TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \
440 	(_tq)->axq_depth++; \
441 	(_tq)->an->an_swq_depth++; \
442 } while (0)
443 #define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \
444 	TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \
445 	(_tq)->axq_depth++; \
446 	(_tq)->an->an_swq_depth++; \
447 } while (0)
448 #define ATH_TID_REMOVE(_tq, _elm, _field) do { \
449 	TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \
450 	(_tq)->axq_depth--; \
451 	(_tq)->an->an_swq_depth--; \
452 } while (0)
453 #define	ATH_TID_FIRST(_tq)		TAILQ_FIRST(&(_tq)->tid_q)
454 #define	ATH_TID_LAST(_tq, _field)	TAILQ_LAST(&(_tq)->tid_q, _field)
455 
456 /*
457  * These are for the TID filtered frame queue
458  */
459 #define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \
460 	TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \
461 	(_tq)->axq_depth++; \
462 	(_tq)->an->an_swq_depth++; \
463 } while (0)
464 #define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \
465 	TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \
466 	(_tq)->axq_depth++; \
467 	(_tq)->an->an_swq_depth++; \
468 } while (0)
469 #define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \
470 	TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \
471 	(_tq)->axq_depth--; \
472 	(_tq)->an->an_swq_depth--; \
473 } while (0)
474 #define	ATH_TID_FILT_FIRST(_tq)		TAILQ_FIRST(&(_tq)->filtq.tid_q)
475 #define	ATH_TID_FILT_LAST(_tq, _field)	TAILQ_LAST(&(_tq)->filtq.tid_q,_field)
476 
477 struct ath_vap {
478 	struct ieee80211vap av_vap;	/* base class */
479 	int		av_bslot;	/* beacon slot index */
480 	struct ath_buf	*av_bcbuf;	/* beacon buffer */
481 	struct ath_txq	av_mcastq;	/* buffered mcast s/w queue */
482 
483 	void		(*av_recv_mgmt)(struct ieee80211_node *,
484 				struct mbuf *, int,
485 				const struct ieee80211_rx_stats *, int, int);
486 	int		(*av_newstate)(struct ieee80211vap *,
487 				enum ieee80211_state, int);
488 	void		(*av_bmiss)(struct ieee80211vap *);
489 	void		(*av_node_ps)(struct ieee80211_node *, int);
490 	int		(*av_set_tim)(struct ieee80211_node *, int);
491 	void		(*av_recv_pspoll)(struct ieee80211_node *,
492 				struct mbuf *);
493 };
494 #define	ATH_VAP(vap)	((struct ath_vap *)(vap))
495 
496 struct taskqueue;
497 struct ath_tx99;
498 
499 /*
500  * Whether to reset the TX/RX queue with or without
501  * a queue flush.
502  */
503 typedef enum {
504 	ATH_RESET_DEFAULT = 0,
505 	ATH_RESET_NOLOSS = 1,
506 	ATH_RESET_FULL = 2,
507 } ATH_RESET_TYPE;
508 
509 struct ath_rx_methods {
510 	void		(*recv_sched_queue)(struct ath_softc *sc,
511 			    HAL_RX_QUEUE q, int dosched);
512 	void		(*recv_sched)(struct ath_softc *sc, int dosched);
513 	void		(*recv_stop)(struct ath_softc *sc, int dodelay);
514 	int		(*recv_start)(struct ath_softc *sc);
515 	void		(*recv_flush)(struct ath_softc *sc);
516 	void		(*recv_tasklet)(void *arg, int npending);
517 	int		(*recv_rxbuf_init)(struct ath_softc *sc,
518 			    struct ath_buf *bf);
519 	int		(*recv_setup)(struct ath_softc *sc);
520 	int		(*recv_teardown)(struct ath_softc *sc);
521 };
522 
523 /*
524  * Represent the current state of the RX FIFO.
525  */
526 struct ath_rx_edma {
527 	struct ath_buf	**m_fifo;
528 	int		m_fifolen;
529 	int		m_fifo_head;
530 	int		m_fifo_tail;
531 	int		m_fifo_depth;
532 	struct mbuf	*m_rxpending;
533 	struct ath_buf	*m_holdbf;
534 };
535 
536 struct ath_tx_edma_fifo {
537 	struct ath_buf	**m_fifo;
538 	int		m_fifolen;
539 	int		m_fifo_head;
540 	int		m_fifo_tail;
541 	int		m_fifo_depth;
542 };
543 
544 struct ath_tx_methods {
545 	int		(*xmit_setup)(struct ath_softc *sc);
546 	int		(*xmit_teardown)(struct ath_softc *sc);
547 	void		(*xmit_attach_comp_func)(struct ath_softc *sc);
548 
549 	void		(*xmit_dma_restart)(struct ath_softc *sc,
550 			    struct ath_txq *txq);
551 	void		(*xmit_handoff)(struct ath_softc *sc,
552 			    struct ath_txq *txq, struct ath_buf *bf);
553 	void		(*xmit_drain)(struct ath_softc *sc,
554 			    ATH_RESET_TYPE reset_type);
555 };
556 
557 struct ath_softc {
558 	struct ieee80211com	sc_ic;
559 	struct ath_stats	sc_stats;	/* device statistics */
560 	struct ath_tx_aggr_stats	sc_aggr_stats;
561 	struct ath_intr_stats	sc_intr_stats;
562 	uint64_t		sc_debug;
563 	uint64_t		sc_ktrdebug;
564 	int			sc_nvaps;	/* # vaps */
565 	int			sc_nstavaps;	/* # station vaps */
566 	int			sc_nmeshvaps;	/* # mbss vaps */
567 	u_int8_t		sc_hwbssidmask[IEEE80211_ADDR_LEN];
568 	u_int8_t		sc_nbssid0;	/* # vap's using base mac */
569 	uint32_t		sc_bssidmask;	/* bssid mask */
570 
571 	struct ath_rx_methods	sc_rx;
572 	struct ath_rx_edma	sc_rxedma[HAL_NUM_RX_QUEUES];	/* HP/LP queues */
573 	ath_bufhead		sc_rx_rxlist[HAL_NUM_RX_QUEUES];	/* deferred RX completion */
574 	struct ath_tx_methods	sc_tx;
575 	struct ath_tx_edma_fifo	sc_txedma[HAL_NUM_TX_QUEUES];
576 
577 	/*
578 	 * This is (currently) protected by the TX queue lock;
579 	 * it should migrate to a separate lock later
580 	 * so as to minimise contention.
581 	 */
582 	ath_bufhead		sc_txbuf_list;
583 
584 	int			sc_rx_statuslen;
585 	int			sc_tx_desclen;
586 	int			sc_tx_statuslen;
587 	int			sc_tx_nmaps;	/* Number of TX maps */
588 	int			sc_edma_bufsize;
589 	int			sc_rx_stopped;	/* XXX only for EDMA */
590 	int			sc_rx_resetted;	/* XXX only for EDMA */
591 
592 	void 			(*sc_node_cleanup)(struct ieee80211_node *);
593 	void 			(*sc_node_free)(struct ieee80211_node *);
594 	device_t		sc_dev;
595 	HAL_BUS_TAG		sc_st;		/* bus space tag */
596 	HAL_BUS_HANDLE		sc_sh;		/* bus space handle */
597 	bus_dma_tag_t		sc_dmat;	/* bus DMA tag */
598 	struct mtx		sc_mtx;		/* master lock (recursive) */
599 	struct mtx		sc_pcu_mtx;	/* PCU access mutex */
600 	char			sc_pcu_mtx_name[32];
601 	struct mtx		sc_rx_mtx;	/* RX access mutex */
602 	char			sc_rx_mtx_name[32];
603 	struct mtx		sc_tx_mtx;	/* TX handling/comp mutex */
604 	char			sc_tx_mtx_name[32];
605 	struct mtx		sc_tx_ic_mtx;	/* TX queue mutex */
606 	char			sc_tx_ic_mtx_name[32];
607 	struct taskqueue	*sc_tq;		/* private task queue */
608 	struct ath_hal		*sc_ah;		/* Atheros HAL */
609 	struct ath_ratectrl	*sc_rc;		/* tx rate control support */
610 	struct ath_tx99		*sc_tx99;	/* tx99 adjunct state */
611 	void			(*sc_setdefantenna)(struct ath_softc *, u_int);
612 
613 	/*
614 	 * First set of flags.
615 	 */
616 	uint32_t		sc_invalid  : 1,/* disable hardware accesses */
617 				sc_mrretry  : 1,/* multi-rate retry support */
618 				sc_mrrprot  : 1,/* MRR + protection support */
619 				sc_softled  : 1,/* enable LED gpio status */
620 				sc_hardled  : 1,/* enable MAC LED status */
621 				sc_splitmic : 1,/* split TKIP MIC keys */
622 				sc_needmib  : 1,/* enable MIB stats intr */
623 				sc_diversity: 1,/* enable rx diversity */
624 				sc_hasveol  : 1,/* tx VEOL support */
625 				sc_ledstate : 1,/* LED on/off state */
626 				sc_blinking : 1,/* LED blink operation active */
627 				sc_mcastkey : 1,/* mcast key cache search */
628 				sc_scanning : 1,/* scanning active */
629 				sc_syncbeacon:1,/* sync/resync beacon timers */
630 				sc_hasclrkey: 1,/* CLR key supported */
631 				sc_xchanmode: 1,/* extended channel mode */
632 				sc_outdoor  : 1,/* outdoor operation */
633 				sc_dturbo   : 1,/* dynamic turbo in use */
634 				sc_hasbmask : 1,/* bssid mask support */
635 				sc_hasbmatch: 1,/* bssid match disable support*/
636 				sc_hastsfadd: 1,/* tsf adjust support */
637 				sc_beacons  : 1,/* beacons running */
638 				sc_swbmiss  : 1,/* sta mode using sw bmiss */
639 				sc_stagbeacons:1,/* use staggered beacons */
640 				sc_wmetkipmic:1,/* can do WME+TKIP MIC */
641 				sc_resume_up: 1,/* on resume, start all vaps */
642 				sc_tdma	    : 1,/* TDMA in use */
643 				sc_setcca   : 1,/* set/clr CCA with TDMA */
644 				sc_resetcal : 1,/* reset cal state next trip */
645 				sc_rxslink  : 1,/* do self-linked final descriptor */
646 				sc_rxtsf32  : 1,/* RX dec TSF is 32 bits */
647 				sc_isedma   : 1,/* supports EDMA */
648 				sc_do_mybeacon : 1; /* supports mybeacon */
649 
650 	/*
651 	 * Second set of flags.
652 	 */
653 	u_int32_t		sc_running  : 1,	/* initialized */
654 				sc_use_ent  : 1,
655 				sc_rx_stbc  : 1,
656 				sc_tx_stbc  : 1,
657 				sc_has_ldpc : 1,
658 				sc_hasenforcetxop : 1, /* support enforce TxOP */
659 				sc_hasdivcomb : 1,     /* RX diversity combining */
660 				sc_rx_lnamixer : 1,    /* RX using LNA mixing */
661 				sc_btcoex_mci : 1;     /* MCI bluetooth coex */
662 
663 	int			sc_cabq_enable;	/* Enable cabq transmission */
664 
665 	/*
666 	 * Enterprise mode configuration for AR9380 and later chipsets.
667 	 */
668 	uint32_t		sc_ent_cfg;
669 
670 	uint32_t		sc_eerd;	/* regdomain from EEPROM */
671 	uint32_t		sc_eecc;	/* country code from EEPROM */
672 						/* rate tables */
673 	const HAL_RATE_TABLE	*sc_rates[IEEE80211_MODE_MAX];
674 	const HAL_RATE_TABLE	*sc_currates;	/* current rate table */
675 	enum ieee80211_phymode	sc_curmode;	/* current phy mode */
676 	HAL_OPMODE		sc_opmode;	/* current operating mode */
677 	u_int16_t		sc_curtxpow;	/* current tx power limit */
678 	u_int16_t		sc_curaid;	/* current association id */
679 	struct ieee80211_channel *sc_curchan;	/* current installed channel */
680 	u_int8_t		sc_curbssid[IEEE80211_ADDR_LEN];
681 	u_int8_t		sc_rixmap[256];	/* IEEE to h/w rate table ix */
682 	struct {
683 		u_int8_t	ieeerate;	/* IEEE rate */
684 		u_int8_t	rxflags;	/* radiotap rx flags */
685 		u_int8_t	txflags;	/* radiotap tx flags */
686 		u_int16_t	ledon;		/* softled on time */
687 		u_int16_t	ledoff;		/* softled off time */
688 	} sc_hwmap[32];				/* h/w rate ix mappings */
689 	u_int8_t		sc_protrix;	/* protection rate index */
690 	u_int8_t		sc_lastdatarix;	/* last data frame rate index */
691 	u_int			sc_mcastrate;	/* ieee rate for mcastrateix */
692 	u_int			sc_fftxqmin;	/* min frames before staging */
693 	u_int			sc_fftxqmax;	/* max frames before drop */
694 	u_int			sc_txantenna;	/* tx antenna (fixed or auto) */
695 
696 	HAL_INT			sc_imask;	/* interrupt mask copy */
697 
698 	/*
699 	 * These are modified in the interrupt handler as well as
700 	 * the task queues and other contexts. Thus these must be
701 	 * protected by a mutex, or they could clash.
702 	 *
703 	 * For now, access to these is behind the ATH_LOCK,
704 	 * just to save time.
705 	 */
706 	uint32_t		sc_txq_active;	/* bitmap of active TXQs */
707 	uint32_t		sc_kickpcu;	/* whether to kick the PCU */
708 	uint32_t		sc_rxproc_cnt;	/* In RX processing */
709 	uint32_t		sc_txproc_cnt;	/* In TX processing */
710 	uint32_t		sc_txstart_cnt;	/* In TX output (raw/start) */
711 	uint32_t		sc_inreset_cnt;	/* In active reset/chanchange */
712 	uint32_t		sc_txrx_cnt;	/* refcount on stop/start'ing TX */
713 	uint32_t		sc_intr_cnt;	/* refcount on interrupt handling */
714 
715 	u_int			sc_keymax;	/* size of key cache */
716 	u_int8_t		sc_keymap[ATH_KEYBYTES];/* key use bit map */
717 
718 	/*
719 	 * Software based LED blinking
720 	 */
721 	u_int			sc_ledpin;	/* GPIO pin for driving LED */
722 	u_int			sc_ledon;	/* pin setting for LED on */
723 	u_int			sc_ledidle;	/* idle polling interval */
724 	int			sc_ledevent;	/* time of last LED event */
725 	u_int8_t		sc_txrix;	/* current tx rate for LED */
726 	u_int16_t		sc_ledoff;	/* off time for current blink */
727 	struct callout		sc_ledtimer;	/* led off timer */
728 
729 	/*
730 	 * Hardware based LED blinking
731 	 */
732 	int			sc_led_pwr_pin;	/* MAC power LED GPIO pin */
733 	int			sc_led_net_pin;	/* MAC network LED GPIO pin */
734 
735 	u_int			sc_rfsilentpin;	/* GPIO pin for rfkill int */
736 	u_int			sc_rfsilentpol;	/* pin setting for rfkill on */
737 
738 	struct ath_descdma	sc_rxdma;	/* RX descriptors */
739 	ath_bufhead		sc_rxbuf;	/* receive buffer */
740 	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
741 	struct task		sc_rxtask;	/* rx int processing */
742 	u_int8_t		sc_defant;	/* current default antenna */
743 	u_int8_t		sc_rxotherant;	/* rx's on non-default antenna*/
744 	u_int64_t		sc_lastrx;	/* tsf at last rx'd frame */
745 	struct ath_rx_status	*sc_lastrs;	/* h/w status of last rx */
746 	struct ath_rx_radiotap_header sc_rx_th;
747 	int			sc_rx_th_len;
748 	u_int			sc_monpass;	/* frames to pass in mon.mode */
749 
750 	struct ath_descdma	sc_txdma;	/* TX descriptors */
751 	uint16_t		sc_txbuf_descid;
752 	ath_bufhead		sc_txbuf;	/* transmit buffer */
753 	int			sc_txbuf_cnt;	/* how many buffers avail */
754 	struct ath_descdma	sc_txdma_mgmt;	/* mgmt TX descriptors */
755 	ath_bufhead		sc_txbuf_mgmt;	/* mgmt transmit buffer */
756 	struct ath_descdma	sc_txsdma;	/* EDMA TX status desc's */
757 	struct mtx		sc_txbuflock;	/* txbuf lock */
758 	char			sc_txname[12];	/* e.g. "ath0_buf" */
759 	u_int			sc_txqsetup;	/* h/w queues setup */
760 	u_int			sc_txintrperiod;/* tx interrupt batching */
761 	struct ath_txq		sc_txq[HAL_NUM_TX_QUEUES];
762 	struct ath_txq		*sc_ac2q[5];	/* WME AC -> h/w q map */
763 	struct task		sc_txtask;	/* tx int processing */
764 	struct task		sc_txqtask;	/* tx proc processing */
765 
766 	struct ath_descdma	sc_txcompdma;	/* TX EDMA completion */
767 	struct mtx		sc_txcomplock;	/* TX EDMA completion lock */
768 	char			sc_txcompname[12];	/* eg ath0_txcomp */
769 
770 	int			sc_wd_timer;	/* count down for wd timer */
771 	struct callout		sc_wd_ch;	/* tx watchdog timer */
772 	struct ath_tx_radiotap_header sc_tx_th;
773 	int			sc_tx_th_len;
774 
775 	struct ath_descdma	sc_bdma;	/* beacon descriptors */
776 	ath_bufhead		sc_bbuf;	/* beacon buffers */
777 	u_int			sc_bhalq;	/* HAL q for outgoing beacons */
778 	u_int			sc_bmisscount;	/* missed beacon transmits */
779 	u_int32_t		sc_ant_tx[8];	/* recent tx frames/antenna */
780 	struct ath_txq		*sc_cabq;	/* tx q for cab frames */
781 	struct task		sc_bmisstask;	/* bmiss int processing */
782 	struct task		sc_bstucktask;	/* stuck beacon processing */
783 	struct task		sc_resettask;	/* interface reset task */
784 	struct task		sc_fataltask;	/* fatal task */
785 	enum {
786 		OK,				/* no change needed */
787 		UPDATE,				/* update pending */
788 		COMMIT				/* beacon sent, commit change */
789 	} sc_updateslot;			/* slot time update fsm */
790 	int			sc_slotupdate;	/* slot to advance fsm */
791 	struct ieee80211vap	*sc_bslot[ATH_BCBUF];
792 	int			sc_nbcnvaps;	/* # vaps with beacons */
793 
794 	struct callout		sc_cal_ch;	/* callout handle for cals */
795 	int			sc_lastlongcal;	/* last long cal completed */
796 	int			sc_lastcalreset;/* last cal reset done */
797 	int			sc_lastani;	/* last ANI poll */
798 	int			sc_lastshortcal;	/* last short calibration */
799 	HAL_BOOL		sc_doresetcal;	/* Yes, we're doing a reset cal atm */
800 	HAL_NODE_STATS		sc_halstats;	/* station-mode rssi stats */
801 	u_int			sc_tdmadbaprep;	/* TDMA DBA prep time */
802 	u_int			sc_tdmaswbaprep;/* TDMA SWBA prep time */
803 	u_int			sc_tdmaswba;	/* TDMA SWBA counter */
804 	u_int32_t		sc_tdmabintval;	/* TDMA beacon interval (TU) */
805 	u_int32_t		sc_tdmaguard;	/* TDMA guard time (usec) */
806 	u_int			sc_tdmaslotlen;	/* TDMA slot length (usec) */
807 	u_int32_t		sc_avgtsfdeltap;/* TDMA slot adjust (+) */
808 	u_int32_t		sc_avgtsfdeltam;/* TDMA slot adjust (-) */
809 	uint16_t		*sc_eepromdata;	/* Local eeprom data, if AR9100 */
810 	uint32_t		sc_txchainmask;	/* hardware TX chainmask */
811 	uint32_t		sc_rxchainmask;	/* hardware RX chainmask */
812 	uint32_t		sc_cur_txchainmask;	/* currently configured TX chainmask */
813 	uint32_t		sc_cur_rxchainmask;	/* currently configured RX chainmask */
814 	uint32_t		sc_rts_aggr_limit;	/* TX limit on RTS aggregates */
815 	int			sc_aggr_limit;	/* TX limit on all aggregates */
816 	int			sc_delim_min_pad;	/* Minimum delimiter count */
817 
818 	/* Queue limits */
819 
820 	/*
821 	 * To avoid queue starvation in congested conditions,
822 	 * these parameters tune the maximum number of frames
823 	 * queued to the data/mcastq before they're dropped.
824 	 *
825 	 * This is to prevent:
826 	 * + a single destination overwhelming everything, including
827 	 *   management/multicast frames;
828 	 * + multicast frames overwhelming everything (when the
829 	 *   air is sufficiently busy that cabq can't drain.)
830 	 * + A node in powersave shouldn't be allowed to exhaust
831 	 *   all available mbufs;
832 	 *
833 	 * These implement:
834 	 * + data_minfree is the maximum number of free buffers
835 	 *   overall to successfully allow a data frame.
836 	 *
837 	 * + mcastq_maxdepth is the maximum depth allowed of the cabq.
838 	 */
839 	int			sc_txq_node_maxdepth;
840 	int			sc_txq_data_minfree;
841 	int			sc_txq_mcastq_maxdepth;
842 	int			sc_txq_node_psq_maxdepth;
843 
844 	/*
845 	 * Software queue twiddles
846 	 *
847 	 * hwq_limit_nonaggr:
848 	 *		when to begin limiting non-aggregate frames to the
849 	 *		hardware queue, regardless of the TID.
850 	 * hwq_limit_aggr:
851 	 *		when to begin limiting A-MPDU frames to the
852 	 *		hardware queue, regardless of the TID.
853 	 * tid_hwq_lo:	how low the per-TID hwq count has to be before the
854 	 *		TID will be scheduled again
855 	 * tid_hwq_hi:	how many frames to queue to the HWQ before the TID
856 	 *		stops being scheduled.
857 	 */
858 	int			sc_hwq_limit_nonaggr;
859 	int			sc_hwq_limit_aggr;
860 	int			sc_tid_hwq_lo;
861 	int			sc_tid_hwq_hi;
862 
863 	/* DFS related state */
864 	void			*sc_dfs;	/* Used by an optional DFS module */
865 	int			sc_dodfs;	/* Whether to enable DFS rx filter bits */
866 	struct task		sc_dfstask;	/* DFS processing task */
867 
868 	/* Spectral related state */
869 	void			*sc_spectral;
870 	int			sc_dospectral;
871 
872 	/* LNA diversity related state */
873 	void			*sc_lna_div;
874 	int			sc_dolnadiv;
875 
876 	/* ALQ */
877 #ifdef	ATH_DEBUG_ALQ
878 	struct if_ath_alq sc_alq;
879 #endif
880 
881 	/* TX AMPDU handling */
882 	int			(*sc_addba_request)(struct ieee80211_node *,
883 				    struct ieee80211_tx_ampdu *, int, int, int);
884 	int			(*sc_addba_response)(struct ieee80211_node *,
885 				    struct ieee80211_tx_ampdu *, int, int, int);
886 	void			(*sc_addba_stop)(struct ieee80211_node *,
887 				    struct ieee80211_tx_ampdu *);
888 	void			(*sc_addba_response_timeout)
889 				    (struct ieee80211_node *,
890 				    struct ieee80211_tx_ampdu *);
891 	void			(*sc_bar_response)(struct ieee80211_node *ni,
892 				    struct ieee80211_tx_ampdu *tap,
893 				    int status);
894 
895 	/*
896 	 * Powersave state tracking.
897 	 *
898 	 * target/cur powerstate is the chip power state.
899 	 * target selfgen state is the self-generated frames
900 	 *   state.  The chip can be awake but transmitted frames
901 	 *   can have the PWRMGT bit set to 1 so the destination
902 	 *   thinks the node is asleep.
903 	 */
904 	HAL_POWER_MODE		sc_target_powerstate;
905 	HAL_POWER_MODE		sc_target_selfgen_state;
906 
907 	HAL_POWER_MODE		sc_cur_powerstate;
908 
909 	int			sc_powersave_refcnt;
910 
911 	/* ATH_PCI_* flags */
912 	uint32_t		sc_pci_devinfo;
913 
914 	/* BT coex */
915 	struct {
916 		struct ath_descdma buf;
917 
918 		/* gpm/sched buffer, saved pointers */
919 		char *sched_buf;
920 		bus_addr_t sched_paddr;
921 		char *gpm_buf;
922 		bus_addr_t gpm_paddr;
923 
924 		uint32_t wlan_channels[4];
925 	} sc_btcoex;
926 };
927 
928 #define	ATH_LOCK_INIT(_sc) \
929 	mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
930 		 NULL, MTX_DEF | MTX_RECURSE)
931 #define	ATH_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_mtx)
932 #define	ATH_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
933 #define	ATH_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
934 #define	ATH_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
935 #define	ATH_UNLOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
936 
937 /*
938  * The TX lock is non-reentrant and serialises the TX frame send
939  * and completion operations.
940  */
941 #define	ATH_TX_LOCK_INIT(_sc) do {\
942 	snprintf((_sc)->sc_tx_mtx_name,				\
943 	    sizeof((_sc)->sc_tx_mtx_name),				\
944 	    "%s TX lock",						\
945 	    device_get_nameunit((_sc)->sc_dev));			\
946 	mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name,		\
947 		 NULL, MTX_DEF);					\
948 	} while (0)
949 #define	ATH_TX_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_tx_mtx)
950 #define	ATH_TX_LOCK(_sc)		mtx_lock(&(_sc)->sc_tx_mtx)
951 #define	ATH_TX_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_tx_mtx)
952 #define	ATH_TX_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_tx_mtx,	\
953 		MA_OWNED)
954 #define	ATH_TX_UNLOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_tx_mtx,	\
955 		MA_NOTOWNED)
956 #define	ATH_TX_TRYLOCK(_sc)	(mtx_owned(&(_sc)->sc_tx_mtx) != 0 &&	\
957 					mtx_trylock(&(_sc)->sc_tx_mtx))
958 
959 /*
960  * The PCU lock is non-recursive and should be treated as a spinlock.
961  * Although currently the interrupt code is run in netisr context and
962  * doesn't require this, this may change in the future.
963  * Please keep this in mind when protecting certain code paths
964  * with the PCU lock.
965  *
966  * The PCU lock is used to serialise access to the PCU so things such
967  * as TX, RX, state change (eg channel change), channel reset and updates
968  * from interrupt context (eg kickpcu, txqactive bits) do not clash.
969  *
970  * Although the current single-thread taskqueue mechanism protects the
971  * majority of these situations by simply serialising them, there are
972  * a few others which occur at the same time. These include the TX path
973  * (which only acquires ATH_LOCK when recycling buffers to the free list),
974  * ath_set_channel, the channel scanning API and perhaps quite a bit more.
975  */
976 #define	ATH_PCU_LOCK_INIT(_sc) do {\
977 	snprintf((_sc)->sc_pcu_mtx_name,				\
978 	    sizeof((_sc)->sc_pcu_mtx_name),				\
979 	    "%s PCU lock",						\
980 	    device_get_nameunit((_sc)->sc_dev));			\
981 	mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name,		\
982 		 NULL, MTX_DEF);					\
983 	} while (0)
984 #define	ATH_PCU_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_pcu_mtx)
985 #define	ATH_PCU_LOCK(_sc)		mtx_lock(&(_sc)->sc_pcu_mtx)
986 #define	ATH_PCU_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_pcu_mtx)
987 #define	ATH_PCU_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_pcu_mtx,	\
988 		MA_OWNED)
989 #define	ATH_PCU_UNLOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_pcu_mtx,	\
990 		MA_NOTOWNED)
991 
992 /*
993  * The RX lock is primarily a(nother) workaround to ensure that the
994  * RX FIFO/list isn't modified by various execution paths.
995  * Even though RX occurs in a single context (the ath taskqueue), the
996  * RX path can be executed via various reset/channel change paths.
997  */
998 #define	ATH_RX_LOCK_INIT(_sc) do {\
999 	snprintf((_sc)->sc_rx_mtx_name,					\
1000 	    sizeof((_sc)->sc_rx_mtx_name),				\
1001 	    "%s RX lock",						\
1002 	    device_get_nameunit((_sc)->sc_dev));			\
1003 	mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name,		\
1004 		 NULL, MTX_DEF);					\
1005 	} while (0)
1006 #define	ATH_RX_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_rx_mtx)
1007 #define	ATH_RX_LOCK(_sc)		mtx_lock(&(_sc)->sc_rx_mtx)
1008 #define	ATH_RX_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_rx_mtx)
1009 #define	ATH_RX_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_rx_mtx,	\
1010 		MA_OWNED)
1011 #define	ATH_RX_UNLOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_rx_mtx,	\
1012 		MA_NOTOWNED)
1013 
1014 #define	ATH_TXQ_SETUP(sc, i)	((sc)->sc_txqsetup & (1<<i))
1015 
1016 #define	ATH_TXBUF_LOCK_INIT(_sc) do { \
1017 	snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
1018 		device_get_nameunit((_sc)->sc_dev)); \
1019 	mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
1020 } while (0)
1021 #define	ATH_TXBUF_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_txbuflock)
1022 #define	ATH_TXBUF_LOCK(_sc)		mtx_lock(&(_sc)->sc_txbuflock)
1023 #define	ATH_TXBUF_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_txbuflock)
1024 #define	ATH_TXBUF_LOCK_ASSERT(_sc) \
1025 	mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
1026 #define	ATH_TXBUF_UNLOCK_ASSERT(_sc) \
1027 	mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED)
1028 
1029 #define	ATH_TXSTATUS_LOCK_INIT(_sc) do { \
1030 	snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \
1031 		"%s_buf", \
1032 		device_get_nameunit((_sc)->sc_dev)); \
1033 	mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \
1034 		MTX_DEF); \
1035 } while (0)
1036 #define	ATH_TXSTATUS_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_txcomplock)
1037 #define	ATH_TXSTATUS_LOCK(_sc)		mtx_lock(&(_sc)->sc_txcomplock)
1038 #define	ATH_TXSTATUS_UNLOCK(_sc)	mtx_unlock(&(_sc)->sc_txcomplock)
1039 #define	ATH_TXSTATUS_LOCK_ASSERT(_sc) \
1040 	mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED)
1041 
1042 int	ath_attach(u_int16_t, struct ath_softc *);
1043 int	ath_detach(struct ath_softc *);
1044 void	ath_resume(struct ath_softc *);
1045 void	ath_suspend(struct ath_softc *);
1046 void	ath_shutdown(struct ath_softc *);
1047 void	ath_intr(void *);
1048 
1049 /*
1050  * HAL definitions to comply with local coding convention.
1051  */
1052 #define	ath_hal_detach(_ah) \
1053 	((*(_ah)->ah_detach)((_ah)))
1054 #define	ath_hal_reset(_ah, _opmode, _chan, _fullreset, _resettype, _pstatus) \
1055 	((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_fullreset), \
1056 	    (_resettype), (_pstatus)))
1057 #define	ath_hal_macversion(_ah) \
1058 	(((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
1059 #define	ath_hal_getratetable(_ah, _mode) \
1060 	((*(_ah)->ah_getRateTable)((_ah), (_mode)))
1061 #define	ath_hal_getmac(_ah, _mac) \
1062 	((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
1063 #define	ath_hal_setmac(_ah, _mac) \
1064 	((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
1065 #define	ath_hal_getbssidmask(_ah, _mask) \
1066 	((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
1067 #define	ath_hal_setbssidmask(_ah, _mask) \
1068 	((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
1069 #define	ath_hal_intrset(_ah, _mask) \
1070 	((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
1071 #define	ath_hal_intrget(_ah) \
1072 	((*(_ah)->ah_getInterrupts)((_ah)))
1073 #define	ath_hal_intrpend(_ah) \
1074 	((*(_ah)->ah_isInterruptPending)((_ah)))
1075 #define	ath_hal_getisr(_ah, _pmask) \
1076 	((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
1077 #define	ath_hal_updatetxtriglevel(_ah, _inc) \
1078 	((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
1079 #define	ath_hal_setpower(_ah, _mode) \
1080 	((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
1081 #define	ath_hal_setselfgenpower(_ah, _mode) \
1082 	((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE))
1083 #define	ath_hal_keycachesize(_ah) \
1084 	((*(_ah)->ah_getKeyCacheSize)((_ah)))
1085 #define	ath_hal_keyreset(_ah, _ix) \
1086 	((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
1087 #define	ath_hal_keyset(_ah, _ix, _pk, _mac) \
1088 	((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
1089 #define	ath_hal_keyisvalid(_ah, _ix) \
1090 	(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
1091 #define	ath_hal_keysetmac(_ah, _ix, _mac) \
1092 	((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
1093 #define	ath_hal_getrxfilter(_ah) \
1094 	((*(_ah)->ah_getRxFilter)((_ah)))
1095 #define	ath_hal_setrxfilter(_ah, _filter) \
1096 	((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
1097 #define	ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
1098 	((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
1099 #define	ath_hal_waitforbeacon(_ah, _bf) \
1100 	((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
1101 #define	ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \
1102 	((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq)))
1103 /* NB: common across all chips */
1104 #define	AR_TSF_L32	0x804c	/* MAC local clock lower 32 bits */
1105 #define	ath_hal_gettsf32(_ah) \
1106 	OS_REG_READ(_ah, AR_TSF_L32)
1107 #define	ath_hal_gettsf64(_ah) \
1108 	((*(_ah)->ah_getTsf64)((_ah)))
1109 #define	ath_hal_settsf64(_ah, _val) \
1110 	((*(_ah)->ah_setTsf64)((_ah), (_val)))
1111 #define	ath_hal_resettsf(_ah) \
1112 	((*(_ah)->ah_resetTsf)((_ah)))
1113 #define	ath_hal_rxena(_ah) \
1114 	((*(_ah)->ah_enableReceive)((_ah)))
1115 #define	ath_hal_puttxbuf(_ah, _q, _bufaddr) \
1116 	((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
1117 #define	ath_hal_gettxbuf(_ah, _q) \
1118 	((*(_ah)->ah_getTxDP)((_ah), (_q)))
1119 #define	ath_hal_numtxpending(_ah, _q) \
1120 	((*(_ah)->ah_numTxPending)((_ah), (_q)))
1121 #define	ath_hal_getrxbuf(_ah, _rxq) \
1122 	((*(_ah)->ah_getRxDP)((_ah), (_rxq)))
1123 #define	ath_hal_txstart(_ah, _q) \
1124 	((*(_ah)->ah_startTxDma)((_ah), (_q)))
1125 #define	ath_hal_setchannel(_ah, _chan) \
1126 	((*(_ah)->ah_setChannel)((_ah), (_chan)))
1127 #define	ath_hal_calibrate(_ah, _chan, _iqcal) \
1128 	((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
1129 #define	ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \
1130 	((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
1131 #define	ath_hal_calreset(_ah, _chan) \
1132 	((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
1133 #define	ath_hal_setledstate(_ah, _state) \
1134 	((*(_ah)->ah_setLedState)((_ah), (_state)))
1135 #define	ath_hal_beaconinit(_ah, _nextb, _bperiod) \
1136 	((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
1137 #define	ath_hal_beaconreset(_ah) \
1138 	((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
1139 #define	ath_hal_beaconsettimers(_ah, _bt) \
1140 	((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
1141 #define	ath_hal_beacontimers(_ah, _bs) \
1142 	((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
1143 #define	ath_hal_getnexttbtt(_ah) \
1144 	((*(_ah)->ah_getNextTBTT)((_ah)))
1145 #define	ath_hal_setassocid(_ah, _bss, _associd) \
1146 	((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
1147 #define	ath_hal_phydisable(_ah) \
1148 	((*(_ah)->ah_phyDisable)((_ah)))
1149 #define	ath_hal_setopmode(_ah) \
1150 	((*(_ah)->ah_setPCUConfig)((_ah)))
1151 #define	ath_hal_stoptxdma(_ah, _qnum) \
1152 	((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
1153 #define	ath_hal_stoppcurecv(_ah) \
1154 	((*(_ah)->ah_stopPcuReceive)((_ah)))
1155 #define	ath_hal_startpcurecv(_ah) \
1156 	((*(_ah)->ah_startPcuReceive)((_ah)))
1157 #define	ath_hal_stopdmarecv(_ah) \
1158 	((*(_ah)->ah_stopDmaReceive)((_ah)))
1159 #define	ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
1160 	((*(_ah)->ah_getDiagState)((_ah), (_id), \
1161 		(_indata), (_insize), (_outdata), (_outsize)))
1162 #define	ath_hal_getfatalstate(_ah, _outdata, _outsize) \
1163 	ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
1164 #define	ath_hal_setuptxqueue(_ah, _type, _irq) \
1165 	((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
1166 #define	ath_hal_resettxqueue(_ah, _q) \
1167 	((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
1168 #define	ath_hal_releasetxqueue(_ah, _q) \
1169 	((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
1170 #define	ath_hal_gettxqueueprops(_ah, _q, _qi) \
1171 	((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
1172 #define	ath_hal_settxqueueprops(_ah, _q, _qi) \
1173 	((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
1174 /* NB: common across all chips */
1175 #define	AR_Q_TXE	0x0840	/* MAC Transmit Queue enable */
1176 #define	ath_hal_txqenabled(_ah, _qnum) \
1177 	(OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum)))
1178 #define	ath_hal_getrfgain(_ah) \
1179 	((*(_ah)->ah_getRfGain)((_ah)))
1180 #define	ath_hal_getdefantenna(_ah) \
1181 	((*(_ah)->ah_getDefAntenna)((_ah)))
1182 #define	ath_hal_setdefantenna(_ah, _ant) \
1183 	((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
1184 #define	ath_hal_rxmonitor(_ah, _arg, _chan) \
1185 	((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
1186 #define	ath_hal_ani_poll(_ah, _chan) \
1187 	((*(_ah)->ah_aniPoll)((_ah), (_chan)))
1188 #define	ath_hal_mibevent(_ah, _stats) \
1189 	((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
1190 #define	ath_hal_setslottime(_ah, _us) \
1191 	((*(_ah)->ah_setSlotTime)((_ah), (_us)))
1192 #define	ath_hal_getslottime(_ah) \
1193 	((*(_ah)->ah_getSlotTime)((_ah)))
1194 #define	ath_hal_setacktimeout(_ah, _us) \
1195 	((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
1196 #define	ath_hal_getacktimeout(_ah) \
1197 	((*(_ah)->ah_getAckTimeout)((_ah)))
1198 #define	ath_hal_setctstimeout(_ah, _us) \
1199 	((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
1200 #define	ath_hal_getctstimeout(_ah) \
1201 	((*(_ah)->ah_getCTSTimeout)((_ah)))
1202 #define	ath_hal_getcapability(_ah, _cap, _param, _result) \
1203 	((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
1204 #define	ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
1205 	((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
1206 #define	ath_hal_ciphersupported(_ah, _cipher) \
1207 	(ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
1208 #define	ath_hal_getregdomain(_ah, _prd) \
1209 	(ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
1210 #define	ath_hal_setregdomain(_ah, _rd) \
1211 	ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
1212 #define	ath_hal_getcountrycode(_ah, _pcc) \
1213 	(*(_pcc) = (_ah)->ah_countryCode)
1214 #define	ath_hal_gettkipmic(_ah) \
1215 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
1216 #define	ath_hal_settkipmic(_ah, _v) \
1217 	ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
1218 #define	ath_hal_hastkipsplit(_ah) \
1219 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
1220 #define	ath_hal_gettkipsplit(_ah) \
1221 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
1222 #define	ath_hal_settkipsplit(_ah, _v) \
1223 	ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
1224 #define	ath_hal_haswmetkipmic(_ah) \
1225 	(ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
1226 #define	ath_hal_hwphycounters(_ah) \
1227 	(ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
1228 #define	ath_hal_hasdiversity(_ah) \
1229 	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
1230 #define	ath_hal_getdiversity(_ah) \
1231 	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
1232 #define	ath_hal_setdiversity(_ah, _v) \
1233 	ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
1234 #define	ath_hal_getantennaswitch(_ah) \
1235 	((*(_ah)->ah_getAntennaSwitch)((_ah)))
1236 #define	ath_hal_setantennaswitch(_ah, _v) \
1237 	((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
1238 #define	ath_hal_getdiag(_ah, _pv) \
1239 	(ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
1240 #define	ath_hal_setdiag(_ah, _v) \
1241 	ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
1242 #define	ath_hal_getnumtxqueues(_ah, _pv) \
1243 	(ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
1244 #define	ath_hal_hasveol(_ah) \
1245 	(ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
1246 #define	ath_hal_hastxpowlimit(_ah) \
1247 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
1248 #define	ath_hal_settxpowlimit(_ah, _pow) \
1249 	((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
1250 #define	ath_hal_gettxpowlimit(_ah, _ppow) \
1251 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
1252 #define	ath_hal_getmaxtxpow(_ah, _ppow) \
1253 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
1254 #define	ath_hal_gettpscale(_ah, _scale) \
1255 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
1256 #define	ath_hal_settpscale(_ah, _v) \
1257 	ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
1258 #define	ath_hal_hastpc(_ah) \
1259 	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
1260 #define	ath_hal_gettpc(_ah) \
1261 	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
1262 #define	ath_hal_settpc(_ah, _v) \
1263 	ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
1264 #define	ath_hal_hasbursting(_ah) \
1265 	(ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
1266 #define	ath_hal_setmcastkeysearch(_ah, _v) \
1267 	ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL)
1268 #define	ath_hal_hasmcastkeysearch(_ah) \
1269 	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
1270 #define	ath_hal_getmcastkeysearch(_ah) \
1271 	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
1272 #define	ath_hal_hasfastframes(_ah) \
1273 	(ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
1274 #define	ath_hal_hasbssidmask(_ah) \
1275 	(ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
1276 #define	ath_hal_hasbssidmatch(_ah) \
1277 	(ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK)
1278 #define	ath_hal_hastsfadjust(_ah) \
1279 	(ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
1280 #define	ath_hal_gettsfadjust(_ah) \
1281 	(ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
1282 #define	ath_hal_settsfadjust(_ah, _onoff) \
1283 	ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
1284 #define	ath_hal_hasrfsilent(_ah) \
1285 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
1286 #define	ath_hal_getrfkill(_ah) \
1287 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
1288 #define	ath_hal_setrfkill(_ah, _onoff) \
1289 	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
1290 #define	ath_hal_getrfsilent(_ah, _prfsilent) \
1291 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
1292 #define	ath_hal_setrfsilent(_ah, _rfsilent) \
1293 	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
1294 #define	ath_hal_gettpack(_ah, _ptpack) \
1295 	(ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
1296 #define	ath_hal_settpack(_ah, _tpack) \
1297 	ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
1298 #define	ath_hal_gettpcts(_ah, _ptpcts) \
1299 	(ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
1300 #define	ath_hal_settpcts(_ah, _tpcts) \
1301 	ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
1302 #define	ath_hal_hasintmit(_ah) \
1303 	(ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1304 	HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK)
1305 #define	ath_hal_getintmit(_ah) \
1306 	(ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1307 	HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK)
1308 #define	ath_hal_setintmit(_ah, _v) \
1309 	ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \
1310 	HAL_CAP_INTMIT_ENABLE, _v, NULL)
1311 #define	ath_hal_hasmybeacon(_ah) \
1312 	(ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK)
1313 
1314 #define	ath_hal_hasenforcetxop(_ah) \
1315 	(ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK)
1316 #define	ath_hal_getenforcetxop(_ah) \
1317 	(ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK)
1318 #define	ath_hal_setenforcetxop(_ah, _v) \
1319 	ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL)
1320 
1321 #define	ath_hal_hasrxlnamixer(_ah) \
1322 	(ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK)
1323 
1324 #define	ath_hal_hasdivantcomb(_ah) \
1325 	(ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK)
1326 #define	ath_hal_hasldpc(_ah) \
1327 	(ath_hal_getcapability(_ah, HAL_CAP_LDPC, 0, NULL) == HAL_OK)
1328 #define	ath_hal_hasldpcwar(_ah) \
1329 	(ath_hal_getcapability(_ah, HAL_CAP_LDPCWAR, 0, NULL) == HAL_OK)
1330 
1331 /* EDMA definitions */
1332 #define	ath_hal_hasedma(_ah) \
1333 	(ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT,	\
1334 	0, NULL) == HAL_OK)
1335 #define	ath_hal_getrxfifodepth(_ah, _qtype, _req) \
1336 	(ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req)	\
1337 	== HAL_OK)
1338 #define	ath_hal_getntxmaps(_ah, _req) \
1339 	(ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req)	\
1340 	== HAL_OK)
1341 #define	ath_hal_gettxdesclen(_ah, _req) \
1342 	(ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req)		\
1343 	== HAL_OK)
1344 #define	ath_hal_gettxstatuslen(_ah, _req) \
1345 	(ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req)	\
1346 	== HAL_OK)
1347 #define	ath_hal_getrxstatuslen(_ah, _req) \
1348 	(ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req)	\
1349 	== HAL_OK)
1350 #define	ath_hal_setrxbufsize(_ah, _req) \
1351 	(ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL)	\
1352 	== HAL_OK)
1353 
1354 #define	ath_hal_getchannoise(_ah, _c) \
1355 	((*(_ah)->ah_getChanNoise)((_ah), (_c)))
1356 
1357 /* 802.11n HAL methods */
1358 #define	ath_hal_getrxchainmask(_ah, _prxchainmask) \
1359 	(ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask))
1360 #define	ath_hal_gettxchainmask(_ah, _ptxchainmask) \
1361 	(ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask))
1362 #define	ath_hal_setrxchainmask(_ah, _rx) \
1363 	(ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL))
1364 #define	ath_hal_settxchainmask(_ah, _tx) \
1365 	(ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL))
1366 #define	ath_hal_split4ktrans(_ah) \
1367 	(ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \
1368 	0, NULL) == HAL_OK)
1369 #define	ath_hal_self_linked_final_rxdesc(_ah) \
1370 	(ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \
1371 	0, NULL) == HAL_OK)
1372 #define	ath_hal_gtxto_supported(_ah) \
1373 	(ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK)
1374 #define	ath_hal_get_rx_tsf_prec(_ah, _pr) \
1375 	(ath_hal_getcapability((_ah), HAL_CAP_RXTSTAMP_PREC, 0, (_pr)) \
1376 	    == HAL_OK)
1377 #define	ath_hal_get_tx_tsf_prec(_ah, _pr) \
1378 	(ath_hal_getcapability((_ah), HAL_CAP_TXTSTAMP_PREC, 0, (_pr)) \
1379 	    == HAL_OK)
1380 #define	ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
1381 	((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
1382 #define	ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
1383 	((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
1384 #define	ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
1385 		_txr0, _txtr0, _keyix, _ant, _flags, \
1386 		_rtsrate, _rtsdura) \
1387 	((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
1388 		(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
1389 		(_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
1390 #define	ath_hal_setupxtxdesc(_ah, _ds, \
1391 		_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
1392 	((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
1393 		(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
1394 #define	ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \
1395 	((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \
1396 		(_first), (_last), (_ds0)))
1397 #define	ath_hal_txprocdesc(_ah, _ds, _ts) \
1398 	((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
1399 #define	ath_hal_gettxintrtxqs(_ah, _txqs) \
1400 	((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
1401 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \
1402 	((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries)))
1403 #define ath_hal_settxdesclink(_ah, _ds, _link) \
1404 	((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link)))
1405 #define ath_hal_gettxdesclink(_ah, _ds, _link) \
1406 	((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link)))
1407 #define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \
1408 	((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr)))
1409 #define	ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \
1410 	((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \
1411 		(_size)))
1412 #define	ath_hal_gettxrawtxdesc(_ah, _txstatus) \
1413 	((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus)))
1414 
1415 #define	ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \
1416 		_txr0, _txtr0, _antm, _rcr, _rcd) \
1417 	((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \
1418 	(_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd)))
1419 #define	ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \
1420 	_keyix, _cipher, _delims, _first, _last, _lastaggr) \
1421 	((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \
1422 	(_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \
1423 	(_first), (_last), (_lastaggr)))
1424 #define	ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \
1425 	((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0)))
1426 
1427 #define	ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \
1428 	((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \
1429 	(_series), (_ns), (_flags)))
1430 
1431 #define	ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \
1432 	((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num)))
1433 #define	ath_hal_set11n_aggr_middle(_ah, _ds, _num) \
1434 	((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num)))
1435 #define	ath_hal_set11n_aggr_last(_ah, _ds) \
1436 	((*(_ah)->ah_set11nAggrLast)((_ah), (_ds)))
1437 
1438 #define	ath_hal_set11nburstduration(_ah, _ds, _dur) \
1439 	((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur)))
1440 #define	ath_hal_clr11n_aggr(_ah, _ds) \
1441 	((*(_ah)->ah_clr11nAggr)((_ah), (_ds)))
1442 #define	ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \
1443 	((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v)))
1444 
1445 #define	ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
1446 	((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
1447 #define	ath_hal_gpioset(_ah, _gpio, _b) \
1448 	((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
1449 #define	ath_hal_gpioget(_ah, _gpio) \
1450 	((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
1451 #define	ath_hal_gpiosetintr(_ah, _gpio, _b) \
1452 	((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
1453 
1454 /*
1455  * PCIe suspend/resume/poweron/poweroff related macros
1456  */
1457 #define	ath_hal_enablepcie(_ah, _restore, _poweroff) \
1458 	((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff)))
1459 #define	ath_hal_disablepcie(_ah) \
1460 	((*(_ah)->ah_disablePCIE)((_ah)))
1461 
1462 /*
1463  * This is badly-named; you need to set the correct parameters
1464  * to begin to receive useful radar events; and even then
1465  * it doesn't "enable" DFS. See the ath_dfs/null/ module for
1466  * more information.
1467  */
1468 #define	ath_hal_enabledfs(_ah, _param) \
1469 	((*(_ah)->ah_enableDfs)((_ah), (_param)))
1470 #define	ath_hal_getdfsthresh(_ah, _param) \
1471 	((*(_ah)->ah_getDfsThresh)((_ah), (_param)))
1472 #define	ath_hal_getdfsdefaultthresh(_ah, _param) \
1473 	((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param)))
1474 #define	ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \
1475 	((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \
1476 	(_buf), (_event)))
1477 #define	ath_hal_is_fast_clock_enabled(_ah) \
1478 	((*(_ah)->ah_isFastClockEnabled)((_ah)))
1479 #define	ath_hal_radar_wait(_ah, _chan) \
1480 	((*(_ah)->ah_radarWait)((_ah), (_chan)))
1481 #define	ath_hal_get_mib_cycle_counts(_ah, _sample) \
1482 	((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample)))
1483 #define	ath_hal_get_chan_ext_busy(_ah) \
1484 	((*(_ah)->ah_get11nExtBusy)((_ah)))
1485 #define	ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \
1486 	((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask)))
1487 
1488 #define	ath_hal_spectral_supported(_ah) \
1489 	(ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK)
1490 #define	ath_hal_spectral_get_config(_ah, _p) \
1491 	((*(_ah)->ah_spectralGetConfig)((_ah), (_p)))
1492 #define	ath_hal_spectral_configure(_ah, _p) \
1493 	((*(_ah)->ah_spectralConfigure)((_ah), (_p)))
1494 #define	ath_hal_spectral_start(_ah) \
1495 	((*(_ah)->ah_spectralStart)((_ah)))
1496 #define	ath_hal_spectral_stop(_ah) \
1497 	((*(_ah)->ah_spectralStop)((_ah)))
1498 
1499 #define	ath_hal_btcoex_supported(_ah) \
1500 	(ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK)
1501 #define	ath_hal_btcoex_set_info(_ah, _info) \
1502 	((*(_ah)->ah_btCoexSetInfo)((_ah), (_info)))
1503 #define	ath_hal_btcoex_set_config(_ah, _cfg) \
1504 	((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg)))
1505 #define	ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \
1506 	((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid)))
1507 #define	ath_hal_btcoex_set_weights(_ah, _weight) \
1508 	((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight)))
1509 #define	ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \
1510 	((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr)))
1511 #define	ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \
1512 	((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val)))
1513 #define	ath_hal_btcoex_enable(_ah) \
1514 	((*(_ah)->ah_btCoexEnable)((_ah)))
1515 #define	ath_hal_btcoex_disable(_ah) \
1516 	((*(_ah)->ah_btCoexDisable)((_ah)))
1517 
1518 #define	ath_hal_btcoex_mci_setup(_ah, _gp, _gb, _gl, _sp) \
1519 	((*(_ah)->ah_btMciSetup)((_ah), (_gp), (_gb), (_gl), (_sp)))
1520 #define	ath_hal_btcoex_mci_send_message(_ah, _h, _f, _p, _l, _wd, _cbt) \
1521 	((*(_ah)->ah_btMciSendMessage)((_ah), (_h), (_f), (_p), (_l), (_wd), (_cbt)))
1522 #define	ath_hal_btcoex_mci_get_interrupt(_ah, _mi, _mm) \
1523 	((*(_ah)->ah_btMciGetInterrupt)((_ah), (_mi), (_mm)))
1524 #define	ath_hal_btcoex_mci_state(_ah, _st, _pd) \
1525 	((*(_ah)->ah_btMciState)((_ah), (_st), (_pd)))
1526 #define	ath_hal_btcoex_mci_detach(_ah) \
1527 	((*(_ah)->ah_btMciDetach)((_ah)))
1528 
1529 #define	ath_hal_div_comb_conf_get(_ah, _conf) \
1530 	((*(_ah)->ah_divLnaConfGet)((_ah), (_conf)))
1531 #define	ath_hal_div_comb_conf_set(_ah, _conf) \
1532 	((*(_ah)->ah_divLnaConfSet)((_ah), (_conf)))
1533 
1534 #endif /* _DEV_ATH_ATHVAR_H */
1535