1 /*- 2 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35 #ifndef _DEV_ATH_ATHVAR_H 36 #define _DEV_ATH_ATHVAR_H 37 38 #include <contrib/dev/ath/ah.h> 39 #include <contrib/dev/ath/ah_desc.h> 40 #include <net80211/ieee80211_radiotap.h> 41 #include <dev/ath/if_athioctl.h> 42 #include <dev/ath/if_athrate.h> 43 44 #define ATH_TIMEOUT 1000 45 46 #ifndef ATH_RXBUF 47 #define ATH_RXBUF 40 /* number of RX buffers */ 48 #endif 49 #ifndef ATH_TXBUF 50 #define ATH_TXBUF 200 /* number of TX buffers */ 51 #endif 52 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 53 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 54 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 55 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 56 57 #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */ 58 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 59 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 60 61 /* 62 * The key cache is used for h/w cipher state and also for 63 * tracking station state such as the current tx antenna. 64 * We also setup a mapping table between key cache slot indices 65 * and station state to short-circuit node lookups on rx. 66 * Different parts have different size key caches. We handle 67 * up to ATH_KEYMAX entries (could dynamically allocate state). 68 */ 69 #define ATH_KEYMAX 128 /* max key cache size we handle */ 70 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 71 72 #define ATH_FF_TXQMIN 2 /* min txq depth for staging */ 73 #define ATH_FF_TXQMAX 50 /* maximum # of queued frames allowed */ 74 #define ATH_FF_STAGEMAX 5 /* max waiting period for staged frame*/ 75 76 struct taskqueue; 77 struct kthread; 78 struct ath_buf; 79 80 /* driver-specific node state */ 81 struct ath_node { 82 struct ieee80211_node an_node; /* base class */ 83 u_int32_t an_avgrssi; /* average rssi over all rx frames */ 84 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 85 /* variable-length rate control state follows */ 86 }; 87 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 88 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 89 90 #define ATH_RSSI_LPF_LEN 10 91 #define ATH_RSSI_DUMMY_MARKER 0x127 92 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 93 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 94 #define ATH_LPF_RSSI(x, y, len) \ 95 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 96 #define ATH_RSSI_LPF(x, y) do { \ 97 if ((y) >= -20) \ 98 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 99 } while (0) 100 101 struct ath_buf { 102 STAILQ_ENTRY(ath_buf) bf_list; 103 TAILQ_ENTRY(ath_buf) bf_stagelist; /* stage queue list */ 104 u_int32_t bf_age; /* age when placed on stageq */ 105 int bf_nseg; 106 int bf_flags; /* tx descriptor flags */ 107 struct ath_desc *bf_desc; /* virtual addr of desc */ 108 struct ath_desc_status bf_status; /* tx/rx status */ 109 bus_addr_t bf_daddr; /* physical addr of desc */ 110 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 111 struct mbuf *bf_m; /* mbuf for buf */ 112 struct ieee80211_node *bf_node; /* pointer to the node */ 113 bus_size_t bf_mapsize; 114 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 115 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 116 }; 117 typedef STAILQ_HEAD(, ath_buf) ath_bufhead; 118 119 /* 120 * DMA state for tx/rx descriptors. 121 */ 122 struct ath_descdma { 123 const char* dd_name; 124 struct ath_desc *dd_desc; /* descriptors */ 125 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 126 bus_size_t dd_desc_len; /* size of dd_desc */ 127 bus_dma_segment_t dd_dseg; 128 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 129 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 130 struct ath_buf *dd_bufptr; /* associated buffers */ 131 }; 132 133 /* 134 * Data transmit queue state. One of these exists for each 135 * hardware transmit queue. Packets sent to us from above 136 * are assigned to queues based on their priority. Not all 137 * devices support a complete set of hardware transmit queues. 138 * For those devices the array sc_ac2q will map multiple 139 * priorities to fewer hardware queues (typically all to one 140 * hardware queue). 141 */ 142 struct ath_txq { 143 u_int axq_qnum; /* hardware q number */ 144 u_int axq_depth; /* queue depth (stat only) */ 145 u_int axq_intrcnt; /* interrupt count */ 146 u_int32_t *axq_link; /* link ptr in last TX desc */ 147 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */ 148 struct mtx axq_lock; /* lock on q and link */ 149 char axq_name[12]; /* e.g. "ath0_txq4" */ 150 /* 151 * Fast-frame state. The staging queue holds awaiting 152 * a fast-frame pairing. Buffers on this queue are 153 * assigned an ``age'' and flushed when they wait too long. 154 */ 155 TAILQ_HEAD(axq_headtype, ath_buf) axq_stageq; 156 u_int32_t axq_curage; /* queue age */ 157 }; 158 159 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 160 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 161 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 162 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 163 } while (0) 164 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 165 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 166 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 167 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED) 168 169 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 170 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 171 (_tq)->axq_depth++; \ 172 (_tq)->axq_curage++; \ 173 } while (0) 174 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \ 175 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \ 176 (_tq)->axq_depth--; \ 177 } while (0) 178 179 struct taskqueue; 180 struct ath_tx99; 181 182 struct ath_softc { 183 struct ifnet *sc_ifp; /* interface common */ 184 struct ath_stats sc_stats; /* interface statistics */ 185 struct ieee80211com sc_ic; /* IEEE 802.11 common */ 186 int sc_debug; 187 u_int32_t sc_countrycode; 188 u_int32_t sc_regdomain; 189 void (*sc_recv_mgmt)(struct ieee80211com *, 190 struct mbuf *, 191 struct ieee80211_node *, 192 int, int, int, u_int32_t); 193 int (*sc_newstate)(struct ieee80211com *, 194 enum ieee80211_state, int); 195 void (*sc_node_free)(struct ieee80211_node *); 196 device_t sc_dev; 197 HAL_BUS_TAG sc_st; /* bus space tag */ 198 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 199 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 200 struct mtx sc_mtx; /* master lock (recursive) */ 201 struct taskqueue *sc_tq; /* private task queue */ 202 struct ath_hal *sc_ah; /* Atheros HAL */ 203 struct ath_ratectrl *sc_rc; /* tx rate control support */ 204 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 205 void (*sc_setdefantenna)(struct ath_softc *, u_int); 206 unsigned int sc_invalid : 1, /* disable hardware accesses */ 207 sc_mrretry : 1, /* multi-rate retry support */ 208 sc_softled : 1, /* enable LED gpio status */ 209 sc_splitmic: 1, /* split TKIP MIC keys */ 210 sc_needmib : 1, /* enable MIB stats intr */ 211 sc_diversity : 1,/* enable rx diversity */ 212 sc_hasveol : 1, /* tx VEOL support */ 213 sc_ledstate: 1, /* LED on/off state */ 214 sc_blinking: 1, /* LED blink operation active */ 215 sc_mcastkey: 1, /* mcast key cache search */ 216 sc_scanning: 1, /* scanning active */ 217 sc_syncbeacon:1,/* sync/resync beacon timers */ 218 sc_hasclrkey:1, /* CLR key supported */ 219 sc_xchanmode: 1,/* extended channel mode */ 220 sc_outdoor : 1,/* outdoor operation */ 221 sc_dturbo : 1; /* dynamic turbo in use */ 222 /* rate tables */ 223 #define IEEE80211_MODE_HALF (IEEE80211_MODE_MAX+0) 224 #define IEEE80211_MODE_QUARTER (IEEE80211_MODE_MAX+1) 225 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX+2]; 226 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 227 enum ieee80211_phymode sc_curmode; /* current phy mode */ 228 HAL_OPMODE sc_opmode; /* current operating mode */ 229 u_int16_t sc_curtxpow; /* current tx power limit */ 230 u_int16_t sc_curaid; /* current association id */ 231 HAL_CHANNEL sc_curchan; /* current h/w channel */ 232 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 233 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 234 struct { 235 u_int8_t ieeerate; /* IEEE rate */ 236 u_int8_t rxflags; /* radiotap rx flags */ 237 u_int8_t txflags; /* radiotap tx flags */ 238 u_int16_t ledon; /* softled on time */ 239 u_int16_t ledoff; /* softled off time */ 240 } sc_hwmap[32]; /* h/w rate ix mappings */ 241 u_int8_t sc_minrateix; /* min h/w rate index */ 242 u_int8_t sc_mcastrix; /* mcast h/w rate index */ 243 u_int8_t sc_protrix; /* protection rate index */ 244 u_int8_t sc_lastdatarix; /* last data frame rate index */ 245 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 246 u_int sc_fftxqmin; /* min frames before staging */ 247 u_int sc_fftxqmax; /* max frames before drop */ 248 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 249 HAL_INT sc_imask; /* interrupt mask copy */ 250 u_int sc_keymax; /* size of key cache */ 251 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 252 253 u_int sc_ledpin; /* GPIO pin for driving LED */ 254 u_int sc_ledon; /* pin setting for LED on */ 255 u_int sc_ledidle; /* idle polling interval */ 256 int sc_ledevent; /* time of last LED event */ 257 u_int8_t sc_rxrate; /* current rx rate for LED */ 258 u_int8_t sc_txrate; /* current tx rate for LED */ 259 u_int16_t sc_ledoff; /* off time for current blink */ 260 struct callout sc_ledtimer; /* led off timer */ 261 262 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 263 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 264 265 struct bpf_if *sc_drvbpf; 266 union { 267 struct ath_tx_radiotap_header th; 268 u_int8_t pad[64]; 269 } u_tx_rt; 270 int sc_tx_th_len; 271 union { 272 struct ath_rx_radiotap_header th; 273 u_int8_t pad[64]; 274 } u_rx_rt; 275 int sc_rx_th_len; 276 u_int sc_monpass; /* frames to pass in mon.mode */ 277 278 struct ath_descdma sc_rxdma; /* RX descriptos */ 279 ath_bufhead sc_rxbuf; /* receive buffer */ 280 struct mbuf *sc_rxpending; /* pending receive data */ 281 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 282 struct task sc_rxtask; /* rx int processing */ 283 struct task sc_rxorntask; /* rxorn int processing */ 284 u_int8_t sc_defant; /* current default antenna */ 285 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 286 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 287 288 struct ath_descdma sc_txdma; /* TX descriptors */ 289 ath_bufhead sc_txbuf; /* transmit buffer */ 290 struct mtx sc_txbuflock; /* txbuf lock */ 291 char sc_txname[12]; /* e.g. "ath0_buf" */ 292 u_int sc_txqsetup; /* h/w queues setup */ 293 u_int sc_txintrperiod;/* tx interrupt batching */ 294 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 295 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 296 struct task sc_txtask; /* tx int processing */ 297 298 struct ath_descdma sc_bdma; /* beacon descriptors */ 299 ath_bufhead sc_bbuf; /* beacon buffers */ 300 u_int sc_bhalq; /* HAL q for outgoing beacons */ 301 u_int sc_bmisscount; /* missed beacon transmits */ 302 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 303 struct ath_txq *sc_cabq; /* tx q for cab frames */ 304 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */ 305 struct task sc_bmisstask; /* bmiss int processing */ 306 struct task sc_bstucktask; /* stuck beacon processing */ 307 enum { 308 OK, /* no change needed */ 309 UPDATE, /* update pending */ 310 COMMIT /* beacon sent, commit change */ 311 } sc_updateslot; /* slot time update fsm */ 312 struct ath_txq sc_mcastq; /* mcast xmits w/ ps sta's */ 313 314 struct callout sc_cal_ch; /* callout handle for cals */ 315 int sc_calinterval; /* current polling interval */ 316 int sc_caltries; /* cals at current interval */ 317 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 318 struct callout sc_dfs_ch; /* callout handle for dfs */ 319 }; 320 #define sc_tx_th u_tx_rt.th 321 #define sc_rx_th u_rx_rt.th 322 323 #define ATH_LOCK_INIT(_sc) \ 324 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 325 NULL, MTX_DEF | MTX_RECURSE) 326 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 327 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 328 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 329 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 330 331 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 332 333 #define ATH_TXBUF_LOCK_INIT(_sc) do { \ 334 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 335 device_get_nameunit((_sc)->sc_dev)); \ 336 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 337 } while (0) 338 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 339 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 340 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 341 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 342 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 343 344 int ath_attach(u_int16_t, struct ath_softc *); 345 int ath_detach(struct ath_softc *); 346 void ath_resume(struct ath_softc *); 347 void ath_suspend(struct ath_softc *); 348 void ath_shutdown(struct ath_softc *); 349 void ath_intr(void *); 350 351 /* 352 * HAL definitions to comply with local coding convention. 353 */ 354 #define ath_hal_detach(_ah) \ 355 ((*(_ah)->ah_detach)((_ah))) 356 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 357 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 358 #define ath_hal_getratetable(_ah, _mode) \ 359 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 360 #define ath_hal_getmac(_ah, _mac) \ 361 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 362 #define ath_hal_setmac(_ah, _mac) \ 363 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 364 #define ath_hal_intrset(_ah, _mask) \ 365 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 366 #define ath_hal_intrget(_ah) \ 367 ((*(_ah)->ah_getInterrupts)((_ah))) 368 #define ath_hal_intrpend(_ah) \ 369 ((*(_ah)->ah_isInterruptPending)((_ah))) 370 #define ath_hal_getisr(_ah, _pmask) \ 371 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 372 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 373 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 374 #define ath_hal_setpower(_ah, _mode) \ 375 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 376 #define ath_hal_keycachesize(_ah) \ 377 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 378 #define ath_hal_keyreset(_ah, _ix) \ 379 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 380 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 381 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 382 #define ath_hal_keyisvalid(_ah, _ix) \ 383 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 384 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 385 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 386 #define ath_hal_getrxfilter(_ah) \ 387 ((*(_ah)->ah_getRxFilter)((_ah))) 388 #define ath_hal_setrxfilter(_ah, _filter) \ 389 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 390 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 391 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 392 #define ath_hal_waitforbeacon(_ah, _bf) \ 393 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 394 #define ath_hal_putrxbuf(_ah, _bufaddr) \ 395 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 396 #define ath_hal_gettsf32(_ah) \ 397 ((*(_ah)->ah_getTsf32)((_ah))) 398 #define ath_hal_gettsf64(_ah) \ 399 ((*(_ah)->ah_getTsf64)((_ah))) 400 #define ath_hal_resettsf(_ah) \ 401 ((*(_ah)->ah_resetTsf)((_ah))) 402 #define ath_hal_rxena(_ah) \ 403 ((*(_ah)->ah_enableReceive)((_ah))) 404 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 405 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 406 #define ath_hal_gettxbuf(_ah, _q) \ 407 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 408 #define ath_hal_numtxpending(_ah, _q) \ 409 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 410 #define ath_hal_getrxbuf(_ah) \ 411 ((*(_ah)->ah_getRxDP)((_ah))) 412 #define ath_hal_txstart(_ah, _q) \ 413 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 414 #define ath_hal_setchannel(_ah, _chan) \ 415 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 416 #define ath_hal_calibrate(_ah, _chan, _iqcal) \ 417 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 418 #define ath_hal_setledstate(_ah, _state) \ 419 ((*(_ah)->ah_setLedState)((_ah), (_state))) 420 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 421 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 422 #define ath_hal_beaconreset(_ah) \ 423 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 424 #define ath_hal_beacontimers(_ah, _bs) \ 425 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 426 #define ath_hal_setassocid(_ah, _bss, _associd) \ 427 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 428 #define ath_hal_phydisable(_ah) \ 429 ((*(_ah)->ah_phyDisable)((_ah))) 430 #define ath_hal_setopmode(_ah) \ 431 ((*(_ah)->ah_setPCUConfig)((_ah))) 432 #define ath_hal_stoptxdma(_ah, _qnum) \ 433 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 434 #define ath_hal_stoppcurecv(_ah) \ 435 ((*(_ah)->ah_stopPcuReceive)((_ah))) 436 #define ath_hal_startpcurecv(_ah) \ 437 ((*(_ah)->ah_startPcuReceive)((_ah))) 438 #define ath_hal_stopdmarecv(_ah) \ 439 ((*(_ah)->ah_stopDmaReceive)((_ah))) 440 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 441 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 442 (_indata), (_insize), (_outdata), (_outsize))) 443 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 444 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 445 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 446 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 447 #define ath_hal_resettxqueue(_ah, _q) \ 448 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 449 #define ath_hal_releasetxqueue(_ah, _q) \ 450 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 451 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 452 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 453 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 454 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 455 #define ath_hal_getrfgain(_ah) \ 456 ((*(_ah)->ah_getRfGain)((_ah))) 457 #define ath_hal_getdefantenna(_ah) \ 458 ((*(_ah)->ah_getDefAntenna)((_ah))) 459 #define ath_hal_setdefantenna(_ah, _ant) \ 460 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 461 #define ath_hal_rxmonitor(_ah, _arg, _chan) \ 462 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 463 #define ath_hal_mibevent(_ah, _stats) \ 464 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 465 #define ath_hal_setslottime(_ah, _us) \ 466 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 467 #define ath_hal_getslottime(_ah) \ 468 ((*(_ah)->ah_getSlotTime)((_ah))) 469 #define ath_hal_setacktimeout(_ah, _us) \ 470 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 471 #define ath_hal_getacktimeout(_ah) \ 472 ((*(_ah)->ah_getAckTimeout)((_ah))) 473 #define ath_hal_setctstimeout(_ah, _us) \ 474 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 475 #define ath_hal_getctstimeout(_ah) \ 476 ((*(_ah)->ah_getCTSTimeout)((_ah))) 477 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 478 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 479 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 480 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 481 #define ath_hal_ciphersupported(_ah, _cipher) \ 482 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 483 #define ath_hal_getregdomain(_ah, _prd) \ 484 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 485 #define ath_hal_setregdomain(_ah, _rd) \ 486 ((*(_ah)->ah_setRegulatoryDomain)((_ah), (_rd), NULL)) 487 #define ath_hal_getcountrycode(_ah, _pcc) \ 488 (*(_pcc) = (_ah)->ah_countryCode) 489 #define ath_hal_hastkipsplit(_ah) \ 490 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 491 #define ath_hal_gettkipsplit(_ah) \ 492 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 493 #define ath_hal_settkipsplit(_ah, _v) \ 494 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 495 #define ath_hal_hwphycounters(_ah) \ 496 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 497 #define ath_hal_hasdiversity(_ah) \ 498 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 499 #define ath_hal_getdiversity(_ah) \ 500 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 501 #define ath_hal_setdiversity(_ah, _v) \ 502 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 503 #define ath_hal_getantennaswitch(_ah) \ 504 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 505 #define ath_hal_setantennaswitch(_ah, _v) \ 506 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 507 #define ath_hal_getdiag(_ah, _pv) \ 508 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 509 #define ath_hal_setdiag(_ah, _v) \ 510 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 511 #define ath_hal_getnumtxqueues(_ah, _pv) \ 512 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 513 #define ath_hal_hasveol(_ah) \ 514 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 515 #define ath_hal_hastxpowlimit(_ah) \ 516 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 517 #define ath_hal_settxpowlimit(_ah, _pow) \ 518 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 519 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 520 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 521 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 522 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 523 #define ath_hal_gettpscale(_ah, _scale) \ 524 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 525 #define ath_hal_settpscale(_ah, _v) \ 526 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 527 #define ath_hal_hastpc(_ah) \ 528 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 529 #define ath_hal_gettpc(_ah) \ 530 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 531 #define ath_hal_settpc(_ah, _v) \ 532 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 533 #define ath_hal_hasbursting(_ah) \ 534 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 535 #ifdef notyet 536 #define ath_hal_hasmcastkeysearch(_ah) \ 537 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 538 #define ath_hal_getmcastkeysearch(_ah) \ 539 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 540 #else 541 #define ath_hal_getmcastkeysearch(_ah) 0 542 #endif 543 #define ath_hal_hasfastframes(_ah) \ 544 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 545 #define ath_hal_hasrfsilent(_ah) \ 546 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 547 #define ath_hal_getrfkill(_ah) \ 548 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 549 #define ath_hal_setrfkill(_ah, _onoff) \ 550 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 551 #define ath_hal_getrfsilent(_ah, _prfsilent) \ 552 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 553 #define ath_hal_setrfsilent(_ah, _rfsilent) \ 554 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 555 #define ath_hal_gettpack(_ah, _ptpack) \ 556 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 557 #define ath_hal_settpack(_ah, _tpack) \ 558 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 559 #define ath_hal_gettpcts(_ah, _ptpcts) \ 560 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 561 #define ath_hal_settpcts(_ah, _tpcts) \ 562 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 563 #define ath_hal_getchannoise(_ah, _c) \ 564 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 565 #if HAL_ABI_VERSION < 0x05122200 566 #define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 567 #define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 568 #define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 569 #define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 570 #define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 571 #endif 572 #if HAL_ABI_VERSION < 0x06102501 573 #define ath_hal_ispublicsafetysku(ah) \ 574 (((ah)->ah_regdomain == 0 && (ah)->ah_countryCode == 842) || \ 575 (ah)->ah_regdomain == 0x12) 576 #endif 577 #if HAL_ABI_VERSION < 0x06122400 578 /* XXX yech, can't get to regdomain so just hack a compat shim */ 579 #define ath_hal_isgsmsku(ah) \ 580 ((ah)->ah_countryCode == 843) 581 #endif 582 #if HAL_ABI_VERSION < 0x07050400 583 /* compat shims so code compilers--it won't work though */ 584 #define CHANNEL_HT20 0x10000 585 #define CHANNEL_HT40PLUS 0x20000 586 #define CHANNEL_HT40MINUS 0x40000 587 #define HAL_MODE_11NG_HT20 0x008000 588 #define HAL_MODE_11NA_HT20 0x010000 589 #endif 590 591 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 592 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 593 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 594 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 595 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 596 _txr0, _txtr0, _keyix, _ant, _flags, \ 597 _rtsrate, _rtsdura) \ 598 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 599 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 600 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 601 #define ath_hal_setupxtxdesc(_ah, _ds, \ 602 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 603 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 604 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 605 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 606 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 607 #define ath_hal_txprocdesc(_ah, _ds, _ts) \ 608 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 609 #define ath_hal_gettxintrtxqs(_ah, _txqs) \ 610 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 611 612 #define ath_hal_gpioCfgOutput(_ah, _gpio) \ 613 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio))) 614 #define ath_hal_gpioset(_ah, _gpio, _b) \ 615 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 616 #define ath_hal_gpioget(_ah, _gpio) \ 617 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 618 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 619 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 620 621 #define ath_hal_radar_wait(_ah, _chan) \ 622 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 623 624 #endif /* _DEV_ATH_ATHVAR_H */ 625