xref: /freebsd/sys/dev/ath/if_athvar.h (revision 195ebc7e9e4b129de810833791a19dfb4349d6a9)
1 /*-
2  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification.
11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13  *    redistribution must be conditioned upon including a substantially
14  *    similar Disclaimer requirement for further binary redistribution.
15  *
16  * NO WARRANTY
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27  * THE POSSIBILITY OF SUCH DAMAGES.
28  *
29  * $FreeBSD$
30  */
31 
32 /*
33  * Defintions for the Atheros Wireless LAN controller driver.
34  */
35 #ifndef _DEV_ATH_ATHVAR_H
36 #define _DEV_ATH_ATHVAR_H
37 
38 #include <dev/ath/ath_hal/ah.h>
39 #include <dev/ath/ath_hal/ah_desc.h>
40 #include <net80211/ieee80211_radiotap.h>
41 #include <dev/ath/if_athioctl.h>
42 #include <dev/ath/if_athrate.h>
43 
44 #define	ATH_TIMEOUT		1000
45 
46 #ifndef ATH_RXBUF
47 #define	ATH_RXBUF	40		/* number of RX buffers */
48 #endif
49 #ifndef ATH_TXBUF
50 #define	ATH_TXBUF	200		/* number of TX buffers */
51 #endif
52 #define	ATH_BCBUF	4		/* number of beacon buffers */
53 
54 #define	ATH_TXDESC	10		/* number of descriptors per buffer */
55 #define	ATH_TXMAXTRY	11		/* max number of transmit attempts */
56 #define	ATH_TXMGTTRY	4		/* xmit attempts for mgt/ctl frames */
57 #define	ATH_TXINTR_PERIOD 5		/* max number of batched tx descriptors */
58 
59 #define	ATH_BEACON_AIFS_DEFAULT	 0	/* default aifs for ap beacon q */
60 #define	ATH_BEACON_CWMIN_DEFAULT 0	/* default cwmin for ap beacon q */
61 #define	ATH_BEACON_CWMAX_DEFAULT 0	/* default cwmax for ap beacon q */
62 
63 /*
64  * The key cache is used for h/w cipher state and also for
65  * tracking station state such as the current tx antenna.
66  * We also setup a mapping table between key cache slot indices
67  * and station state to short-circuit node lookups on rx.
68  * Different parts have different size key caches.  We handle
69  * up to ATH_KEYMAX entries (could dynamically allocate state).
70  */
71 #define	ATH_KEYMAX	128		/* max key cache size we handle */
72 #define	ATH_KEYBYTES	(ATH_KEYMAX/NBBY)	/* storage space in bytes */
73 
74 struct taskqueue;
75 struct kthread;
76 struct ath_buf;
77 
78 /* driver-specific node state */
79 struct ath_node {
80 	struct ieee80211_node an_node;	/* base class */
81 	u_int8_t	an_mgmtrix;	/* min h/w rate index */
82 	u_int8_t	an_mcastrix;	/* mcast h/w rate index */
83 	struct ath_buf	*an_ff_buf[WME_NUM_AC]; /* ff staging area */
84 	/* variable-length rate control state follows */
85 };
86 #define	ATH_NODE(ni)	((struct ath_node *)(ni))
87 #define	ATH_NODE_CONST(ni)	((const struct ath_node *)(ni))
88 
89 #define ATH_RSSI_LPF_LEN	10
90 #define ATH_RSSI_DUMMY_MARKER	0x127
91 #define ATH_EP_MUL(x, mul)	((x) * (mul))
92 #define ATH_RSSI_IN(x)		(ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
93 #define ATH_LPF_RSSI(x, y, len) \
94     ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
95 #define ATH_RSSI_LPF(x, y) do {						\
96     if ((y) >= -20)							\
97     	x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN);	\
98 } while (0)
99 #define	ATH_EP_RND(x,mul) \
100 	((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
101 #define	ATH_RSSI(x)		ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER)
102 
103 struct ath_buf {
104 	STAILQ_ENTRY(ath_buf)	bf_list;
105 	int			bf_nseg;
106 	uint16_t		bf_txflags;	/* tx descriptor flags */
107 	uint16_t		bf_flags;	/* status flags (below) */
108 	struct ath_desc		*bf_desc;	/* virtual addr of desc */
109 	struct ath_desc_status	bf_status;	/* tx/rx status */
110 	bus_addr_t		bf_daddr;	/* physical addr of desc */
111 	bus_dmamap_t		bf_dmamap;	/* DMA map for mbuf chain */
112 	struct mbuf		*bf_m;		/* mbuf for buf */
113 	struct ieee80211_node	*bf_node;	/* pointer to the node */
114 	bus_size_t		bf_mapsize;
115 #define	ATH_MAX_SCATTER		ATH_TXDESC	/* max(tx,rx,beacon) desc's */
116 	bus_dma_segment_t	bf_segs[ATH_MAX_SCATTER];
117 };
118 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
119 
120 #define	ATH_BUF_BUSY	0x00000002	/* (tx) desc owned by h/w */
121 
122 /*
123  * DMA state for tx/rx descriptors.
124  */
125 struct ath_descdma {
126 	const char*		dd_name;
127 	struct ath_desc		*dd_desc;	/* descriptors */
128 	bus_addr_t		dd_desc_paddr;	/* physical addr of dd_desc */
129 	bus_size_t		dd_desc_len;	/* size of dd_desc */
130 	bus_dma_segment_t	dd_dseg;
131 	bus_dma_tag_t		dd_dmat;	/* bus DMA tag */
132 	bus_dmamap_t		dd_dmamap;	/* DMA map for descriptors */
133 	struct ath_buf		*dd_bufptr;	/* associated buffers */
134 };
135 
136 /*
137  * Data transmit queue state.  One of these exists for each
138  * hardware transmit queue.  Packets sent to us from above
139  * are assigned to queues based on their priority.  Not all
140  * devices support a complete set of hardware transmit queues.
141  * For those devices the array sc_ac2q will map multiple
142  * priorities to fewer hardware queues (typically all to one
143  * hardware queue).
144  */
145 struct ath_txq {
146 	u_int			axq_qnum;	/* hardware q number */
147 #define	ATH_TXQ_SWQ	(HAL_NUM_TX_QUEUES+1)	/* qnum for s/w only queue */
148 	u_int			axq_ac;		/* WME AC */
149 	u_int			axq_flags;
150 #define	ATH_TXQ_PUTPENDING	0x0001		/* ath_hal_puttxbuf pending */
151 	u_int			axq_depth;	/* queue depth (stat only) */
152 	u_int			axq_intrcnt;	/* interrupt count */
153 	u_int32_t		*axq_link;	/* link ptr in last TX desc */
154 	STAILQ_HEAD(, ath_buf)	axq_q;		/* transmit queue */
155 	struct mtx		axq_lock;	/* lock on q and link */
156 	char			axq_name[12];	/* e.g. "ath0_txq4" */
157 };
158 
159 #define	ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
160 	snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
161 		device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
162 	mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
163 } while (0)
164 #define	ATH_TXQ_LOCK_DESTROY(_tq)	mtx_destroy(&(_tq)->axq_lock)
165 #define	ATH_TXQ_LOCK(_tq)		mtx_lock(&(_tq)->axq_lock)
166 #define	ATH_TXQ_UNLOCK(_tq)		mtx_unlock(&(_tq)->axq_lock)
167 #define	ATH_TXQ_LOCK_ASSERT(_tq)	mtx_assert(&(_tq)->axq_lock, MA_OWNED)
168 
169 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
170 	STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
171 	(_tq)->axq_depth++; \
172 } while (0)
173 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
174 	STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
175 	(_tq)->axq_depth--; \
176 } while (0)
177 /* NB: this does not do the "head empty check" that STAILQ_LAST does */
178 #define	ATH_TXQ_LAST(_tq) \
179 	((struct ath_buf *)(void *) \
180 	 ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list)))
181 
182 struct ath_vap {
183 	struct ieee80211vap av_vap;	/* base class */
184 	int		av_bslot;	/* beacon slot index */
185 	struct ath_buf	*av_bcbuf;	/* beacon buffer */
186 	struct ieee80211_beacon_offsets av_boff;/* dynamic update state */
187 	struct ath_txq	av_mcastq;	/* buffered mcast s/w queue */
188 
189 	void		(*av_recv_mgmt)(struct ieee80211_node *,
190 				struct mbuf *, int, int, int);
191 	int		(*av_newstate)(struct ieee80211vap *,
192 				enum ieee80211_state, int);
193 	void		(*av_bmiss)(struct ieee80211vap *);
194 };
195 #define	ATH_VAP(vap)	((struct ath_vap *)(vap))
196 
197 struct taskqueue;
198 struct ath_tx99;
199 
200 struct ath_softc {
201 	struct ifnet		*sc_ifp;	/* interface common */
202 	struct ath_stats	sc_stats;	/* interface statistics */
203 	int			sc_debug;
204 	int			sc_nvaps;	/* # vaps */
205 	int			sc_nstavaps;	/* # station vaps */
206 	u_int8_t		sc_hwbssidmask[IEEE80211_ADDR_LEN];
207 	u_int8_t		sc_nbssid0;	/* # vap's using base mac */
208 	uint32_t		sc_bssidmask;	/* bssid mask */
209 
210 	void 			(*sc_node_free)(struct ieee80211_node *);
211 	device_t		sc_dev;
212 	HAL_BUS_TAG		sc_st;		/* bus space tag */
213 	HAL_BUS_HANDLE		sc_sh;		/* bus space handle */
214 	bus_dma_tag_t		sc_dmat;	/* bus DMA tag */
215 	struct mtx		sc_mtx;		/* master lock (recursive) */
216 	struct taskqueue	*sc_tq;		/* private task queue */
217 	struct ath_hal		*sc_ah;		/* Atheros HAL */
218 	struct ath_ratectrl	*sc_rc;		/* tx rate control support */
219 	struct ath_tx99		*sc_tx99;	/* tx99 adjunct state */
220 	void			(*sc_setdefantenna)(struct ath_softc *, u_int);
221 	unsigned int		sc_invalid  : 1,/* disable hardware accesses */
222 				sc_mrretry  : 1,/* multi-rate retry support */
223 				sc_softled  : 1,/* enable LED gpio status */
224 				sc_splitmic : 1,/* split TKIP MIC keys */
225 				sc_needmib  : 1,/* enable MIB stats intr */
226 				sc_diversity: 1,/* enable rx diversity */
227 				sc_hasveol  : 1,/* tx VEOL support */
228 				sc_ledstate : 1,/* LED on/off state */
229 				sc_blinking : 1,/* LED blink operation active */
230 				sc_mcastkey : 1,/* mcast key cache search */
231 				sc_scanning : 1,/* scanning active */
232 				sc_syncbeacon:1,/* sync/resync beacon timers */
233 				sc_hasclrkey: 1,/* CLR key supported */
234 				sc_xchanmode: 1,/* extended channel mode */
235 				sc_outdoor  : 1,/* outdoor operation */
236 				sc_dturbo   : 1,/* dynamic turbo in use */
237 				sc_hasbmask : 1,/* bssid mask support */
238 				sc_hastsfadd: 1,/* tsf adjust support */
239 				sc_beacons  : 1,/* beacons running */
240 				sc_swbmiss  : 1,/* sta mode using sw bmiss */
241 				sc_stagbeacons:1,/* use staggered beacons */
242 				sc_wmetkipmic:1,/* can do WME+TKIP MIC */
243 				sc_resume_up: 1,/* on resume, start all vaps */
244 				sc_tdma	    : 1,/* TDMA in use */
245 				sc_setcca   : 1,/* set/clr CCA with TDMA */
246 				sc_resetcal : 1;/* reset cal state next trip */
247 	uint32_t		sc_eerd;	/* regdomain from EEPROM */
248 	uint32_t		sc_eecc;	/* country code from EEPROM */
249 						/* rate tables */
250 	const HAL_RATE_TABLE	*sc_rates[IEEE80211_MODE_MAX];
251 	const HAL_RATE_TABLE	*sc_currates;	/* current rate table */
252 	enum ieee80211_phymode	sc_curmode;	/* current phy mode */
253 	HAL_OPMODE		sc_opmode;	/* current operating mode */
254 	u_int16_t		sc_curtxpow;	/* current tx power limit */
255 	u_int16_t		sc_curaid;	/* current association id */
256 	struct ieee80211_channel *sc_curchan;	/* current installed channel */
257 	u_int8_t		sc_curbssid[IEEE80211_ADDR_LEN];
258 	u_int8_t		sc_rixmap[256];	/* IEEE to h/w rate table ix */
259 	struct {
260 		u_int8_t	ieeerate;	/* IEEE rate */
261 		u_int8_t	rxflags;	/* radiotap rx flags */
262 		u_int8_t	txflags;	/* radiotap tx flags */
263 		u_int16_t	ledon;		/* softled on time */
264 		u_int16_t	ledoff;		/* softled off time */
265 	} sc_hwmap[32];				/* h/w rate ix mappings */
266 	u_int8_t		sc_protrix;	/* protection rate index */
267 	u_int8_t		sc_lastdatarix;	/* last data frame rate index */
268 	u_int			sc_mcastrate;	/* ieee rate for mcastrateix */
269 	u_int			sc_fftxqmin;	/* min frames before staging */
270 	u_int			sc_fftxqmax;	/* max frames before drop */
271 	u_int			sc_txantenna;	/* tx antenna (fixed or auto) */
272 	HAL_INT			sc_imask;	/* interrupt mask copy */
273 	u_int			sc_keymax;	/* size of key cache */
274 	u_int8_t		sc_keymap[ATH_KEYBYTES];/* key use bit map */
275 
276 	u_int			sc_ledpin;	/* GPIO pin for driving LED */
277 	u_int			sc_ledon;	/* pin setting for LED on */
278 	u_int			sc_ledidle;	/* idle polling interval */
279 	int			sc_ledevent;	/* time of last LED event */
280 	u_int8_t		sc_txrix;	/* current tx rate for LED */
281 	u_int16_t		sc_ledoff;	/* off time for current blink */
282 	struct callout		sc_ledtimer;	/* led off timer */
283 
284 	u_int			sc_rfsilentpin;	/* GPIO pin for rfkill int */
285 	u_int			sc_rfsilentpol;	/* pin setting for rfkill on */
286 
287 	struct ath_descdma	sc_rxdma;	/* RX descriptors */
288 	ath_bufhead		sc_rxbuf;	/* receive buffer */
289 	struct mbuf		*sc_rxpending;	/* pending receive data */
290 	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
291 	struct task		sc_rxtask;	/* rx int processing */
292 	u_int8_t		sc_defant;	/* current default antenna */
293 	u_int8_t		sc_rxotherant;	/* rx's on non-default antenna*/
294 	u_int64_t		sc_lastrx;	/* tsf at last rx'd frame */
295 	struct ath_rx_status	*sc_lastrs;	/* h/w status of last rx */
296 	struct ath_rx_radiotap_header sc_rx_th;
297 	int			sc_rx_th_len;
298 	u_int			sc_monpass;	/* frames to pass in mon.mode */
299 
300 	struct ath_descdma	sc_txdma;	/* TX descriptors */
301 	ath_bufhead		sc_txbuf;	/* transmit buffer */
302 	struct mtx		sc_txbuflock;	/* txbuf lock */
303 	char			sc_txname[12];	/* e.g. "ath0_buf" */
304 	u_int			sc_txqsetup;	/* h/w queues setup */
305 	u_int			sc_txintrperiod;/* tx interrupt batching */
306 	struct ath_txq		sc_txq[HAL_NUM_TX_QUEUES];
307 	struct ath_txq		*sc_ac2q[5];	/* WME AC -> h/w q map */
308 	struct task		sc_txtask;	/* tx int processing */
309 	int			sc_wd_timer;	/* count down for wd timer */
310 	struct callout		sc_wd_ch;	/* tx watchdog timer */
311 	struct ath_tx_radiotap_header sc_tx_th;
312 	int			sc_tx_th_len;
313 
314 	struct ath_descdma	sc_bdma;	/* beacon descriptors */
315 	ath_bufhead		sc_bbuf;	/* beacon buffers */
316 	u_int			sc_bhalq;	/* HAL q for outgoing beacons */
317 	u_int			sc_bmisscount;	/* missed beacon transmits */
318 	u_int32_t		sc_ant_tx[8];	/* recent tx frames/antenna */
319 	struct ath_txq		*sc_cabq;	/* tx q for cab frames */
320 	struct task		sc_bmisstask;	/* bmiss int processing */
321 	struct task		sc_bstucktask;	/* stuck beacon processing */
322 	enum {
323 		OK,				/* no change needed */
324 		UPDATE,				/* update pending */
325 		COMMIT				/* beacon sent, commit change */
326 	} sc_updateslot;			/* slot time update fsm */
327 	int			sc_slotupdate;	/* slot to advance fsm */
328 	struct ieee80211vap	*sc_bslot[ATH_BCBUF];
329 	int			sc_nbcnvaps;	/* # vaps with beacons */
330 
331 	struct callout		sc_cal_ch;	/* callout handle for cals */
332 	int			sc_lastlongcal;	/* last long cal completed */
333 	int			sc_lastcalreset;/* last cal reset done */
334 	HAL_NODE_STATS		sc_halstats;	/* station-mode rssi stats */
335 	u_int			sc_tdmadbaprep;	/* TDMA DBA prep time */
336 	u_int			sc_tdmaswbaprep;/* TDMA SWBA prep time */
337 	u_int			sc_tdmaswba;	/* TDMA SWBA counter */
338 	u_int32_t		sc_tdmabintval;	/* TDMA beacon interval (TU) */
339 	u_int32_t		sc_tdmaguard;	/* TDMA guard time (usec) */
340 	u_int			sc_tdmaslotlen;	/* TDMA slot length (usec) */
341 	u_int32_t		sc_avgtsfdeltap;/* TDMA slot adjust (+) */
342 	u_int32_t		sc_avgtsfdeltam;/* TDMA slot adjust (-) */
343 };
344 
345 #define	ATH_LOCK_INIT(_sc) \
346 	mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
347 		 NULL, MTX_DEF | MTX_RECURSE)
348 #define	ATH_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_mtx)
349 #define	ATH_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
350 #define	ATH_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
351 #define	ATH_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
352 
353 #define	ATH_TXQ_SETUP(sc, i)	((sc)->sc_txqsetup & (1<<i))
354 
355 #define	ATH_TXBUF_LOCK_INIT(_sc) do { \
356 	snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
357 		device_get_nameunit((_sc)->sc_dev)); \
358 	mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
359 } while (0)
360 #define	ATH_TXBUF_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->sc_txbuflock)
361 #define	ATH_TXBUF_LOCK(_sc)		mtx_lock(&(_sc)->sc_txbuflock)
362 #define	ATH_TXBUF_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_txbuflock)
363 #define	ATH_TXBUF_LOCK_ASSERT(_sc) \
364 	mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
365 
366 int	ath_attach(u_int16_t, struct ath_softc *);
367 int	ath_detach(struct ath_softc *);
368 void	ath_resume(struct ath_softc *);
369 void	ath_suspend(struct ath_softc *);
370 void	ath_shutdown(struct ath_softc *);
371 void	ath_intr(void *);
372 
373 /*
374  * HAL definitions to comply with local coding convention.
375  */
376 #define	ath_hal_detach(_ah) \
377 	((*(_ah)->ah_detach)((_ah)))
378 #define	ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
379 	((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
380 #define	ath_hal_macversion(_ah) \
381 	(((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
382 #define	ath_hal_getratetable(_ah, _mode) \
383 	((*(_ah)->ah_getRateTable)((_ah), (_mode)))
384 #define	ath_hal_getmac(_ah, _mac) \
385 	((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
386 #define	ath_hal_setmac(_ah, _mac) \
387 	((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
388 #define	ath_hal_getbssidmask(_ah, _mask) \
389 	((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
390 #define	ath_hal_setbssidmask(_ah, _mask) \
391 	((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
392 #define	ath_hal_intrset(_ah, _mask) \
393 	((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
394 #define	ath_hal_intrget(_ah) \
395 	((*(_ah)->ah_getInterrupts)((_ah)))
396 #define	ath_hal_intrpend(_ah) \
397 	((*(_ah)->ah_isInterruptPending)((_ah)))
398 #define	ath_hal_getisr(_ah, _pmask) \
399 	((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
400 #define	ath_hal_updatetxtriglevel(_ah, _inc) \
401 	((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
402 #define	ath_hal_setpower(_ah, _mode) \
403 	((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
404 #define	ath_hal_keycachesize(_ah) \
405 	((*(_ah)->ah_getKeyCacheSize)((_ah)))
406 #define	ath_hal_keyreset(_ah, _ix) \
407 	((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
408 #define	ath_hal_keyset(_ah, _ix, _pk, _mac) \
409 	((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
410 #define	ath_hal_keyisvalid(_ah, _ix) \
411 	(((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
412 #define	ath_hal_keysetmac(_ah, _ix, _mac) \
413 	((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
414 #define	ath_hal_getrxfilter(_ah) \
415 	((*(_ah)->ah_getRxFilter)((_ah)))
416 #define	ath_hal_setrxfilter(_ah, _filter) \
417 	((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
418 #define	ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
419 	((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
420 #define	ath_hal_waitforbeacon(_ah, _bf) \
421 	((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
422 #define	ath_hal_putrxbuf(_ah, _bufaddr) \
423 	((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
424 /* NB: common across all chips */
425 #define	AR_TSF_L32	0x804c	/* MAC local clock lower 32 bits */
426 #define	ath_hal_gettsf32(_ah) \
427 	OS_REG_READ(_ah, AR_TSF_L32)
428 #define	ath_hal_gettsf64(_ah) \
429 	((*(_ah)->ah_getTsf64)((_ah)))
430 #define	ath_hal_resettsf(_ah) \
431 	((*(_ah)->ah_resetTsf)((_ah)))
432 #define	ath_hal_rxena(_ah) \
433 	((*(_ah)->ah_enableReceive)((_ah)))
434 #define	ath_hal_puttxbuf(_ah, _q, _bufaddr) \
435 	((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
436 #define	ath_hal_gettxbuf(_ah, _q) \
437 	((*(_ah)->ah_getTxDP)((_ah), (_q)))
438 #define	ath_hal_numtxpending(_ah, _q) \
439 	((*(_ah)->ah_numTxPending)((_ah), (_q)))
440 #define	ath_hal_getrxbuf(_ah) \
441 	((*(_ah)->ah_getRxDP)((_ah)))
442 #define	ath_hal_txstart(_ah, _q) \
443 	((*(_ah)->ah_startTxDma)((_ah), (_q)))
444 #define	ath_hal_setchannel(_ah, _chan) \
445 	((*(_ah)->ah_setChannel)((_ah), (_chan)))
446 #define	ath_hal_calibrate(_ah, _chan, _iqcal) \
447 	((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
448 #define	ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \
449 	((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
450 #define	ath_hal_calreset(_ah, _chan) \
451 	((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
452 #define	ath_hal_setledstate(_ah, _state) \
453 	((*(_ah)->ah_setLedState)((_ah), (_state)))
454 #define	ath_hal_beaconinit(_ah, _nextb, _bperiod) \
455 	((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
456 #define	ath_hal_beaconreset(_ah) \
457 	((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
458 #define	ath_hal_beaconsettimers(_ah, _bt) \
459 	((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
460 #define	ath_hal_beacontimers(_ah, _bs) \
461 	((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
462 #define	ath_hal_setassocid(_ah, _bss, _associd) \
463 	((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
464 #define	ath_hal_phydisable(_ah) \
465 	((*(_ah)->ah_phyDisable)((_ah)))
466 #define	ath_hal_setopmode(_ah) \
467 	((*(_ah)->ah_setPCUConfig)((_ah)))
468 #define	ath_hal_stoptxdma(_ah, _qnum) \
469 	((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
470 #define	ath_hal_stoppcurecv(_ah) \
471 	((*(_ah)->ah_stopPcuReceive)((_ah)))
472 #define	ath_hal_startpcurecv(_ah) \
473 	((*(_ah)->ah_startPcuReceive)((_ah)))
474 #define	ath_hal_stopdmarecv(_ah) \
475 	((*(_ah)->ah_stopDmaReceive)((_ah)))
476 #define	ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
477 	((*(_ah)->ah_getDiagState)((_ah), (_id), \
478 		(_indata), (_insize), (_outdata), (_outsize)))
479 #define	ath_hal_getfatalstate(_ah, _outdata, _outsize) \
480 	ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
481 #define	ath_hal_setuptxqueue(_ah, _type, _irq) \
482 	((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
483 #define	ath_hal_resettxqueue(_ah, _q) \
484 	((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
485 #define	ath_hal_releasetxqueue(_ah, _q) \
486 	((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
487 #define	ath_hal_gettxqueueprops(_ah, _q, _qi) \
488 	((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
489 #define	ath_hal_settxqueueprops(_ah, _q, _qi) \
490 	((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
491 /* NB: common across all chips */
492 #define	AR_Q_TXE	0x0840	/* MAC Transmit Queue enable */
493 #define	ath_hal_txqenabled(_ah, _qnum) \
494 	(OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum)))
495 #define	ath_hal_getrfgain(_ah) \
496 	((*(_ah)->ah_getRfGain)((_ah)))
497 #define	ath_hal_getdefantenna(_ah) \
498 	((*(_ah)->ah_getDefAntenna)((_ah)))
499 #define	ath_hal_setdefantenna(_ah, _ant) \
500 	((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
501 #define	ath_hal_rxmonitor(_ah, _arg, _chan) \
502 	((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
503 #define	ath_hal_mibevent(_ah, _stats) \
504 	((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
505 #define	ath_hal_setslottime(_ah, _us) \
506 	((*(_ah)->ah_setSlotTime)((_ah), (_us)))
507 #define	ath_hal_getslottime(_ah) \
508 	((*(_ah)->ah_getSlotTime)((_ah)))
509 #define	ath_hal_setacktimeout(_ah, _us) \
510 	((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
511 #define	ath_hal_getacktimeout(_ah) \
512 	((*(_ah)->ah_getAckTimeout)((_ah)))
513 #define	ath_hal_setctstimeout(_ah, _us) \
514 	((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
515 #define	ath_hal_getctstimeout(_ah) \
516 	((*(_ah)->ah_getCTSTimeout)((_ah)))
517 #define	ath_hal_getcapability(_ah, _cap, _param, _result) \
518 	((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
519 #define	ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
520 	((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
521 #define	ath_hal_ciphersupported(_ah, _cipher) \
522 	(ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
523 #define	ath_hal_getregdomain(_ah, _prd) \
524 	(ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
525 #define	ath_hal_setregdomain(_ah, _rd) \
526 	ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
527 #define	ath_hal_getcountrycode(_ah, _pcc) \
528 	(*(_pcc) = (_ah)->ah_countryCode)
529 #define	ath_hal_gettkipmic(_ah) \
530 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
531 #define	ath_hal_settkipmic(_ah, _v) \
532 	ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
533 #define	ath_hal_hastkipsplit(_ah) \
534 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
535 #define	ath_hal_gettkipsplit(_ah) \
536 	(ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
537 #define	ath_hal_settkipsplit(_ah, _v) \
538 	ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
539 #define	ath_hal_haswmetkipmic(_ah) \
540 	(ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
541 #define	ath_hal_hwphycounters(_ah) \
542 	(ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
543 #define	ath_hal_hasdiversity(_ah) \
544 	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
545 #define	ath_hal_getdiversity(_ah) \
546 	(ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
547 #define	ath_hal_setdiversity(_ah, _v) \
548 	ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
549 #define	ath_hal_getantennaswitch(_ah) \
550 	((*(_ah)->ah_getAntennaSwitch)((_ah)))
551 #define	ath_hal_setantennaswitch(_ah, _v) \
552 	((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
553 #define	ath_hal_getdiag(_ah, _pv) \
554 	(ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
555 #define	ath_hal_setdiag(_ah, _v) \
556 	ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
557 #define	ath_hal_getnumtxqueues(_ah, _pv) \
558 	(ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
559 #define	ath_hal_hasveol(_ah) \
560 	(ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
561 #define	ath_hal_hastxpowlimit(_ah) \
562 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
563 #define	ath_hal_settxpowlimit(_ah, _pow) \
564 	((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
565 #define	ath_hal_gettxpowlimit(_ah, _ppow) \
566 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
567 #define	ath_hal_getmaxtxpow(_ah, _ppow) \
568 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
569 #define	ath_hal_gettpscale(_ah, _scale) \
570 	(ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
571 #define	ath_hal_settpscale(_ah, _v) \
572 	ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
573 #define	ath_hal_hastpc(_ah) \
574 	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
575 #define	ath_hal_gettpc(_ah) \
576 	(ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
577 #define	ath_hal_settpc(_ah, _v) \
578 	ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
579 #define	ath_hal_hasbursting(_ah) \
580 	(ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
581 #ifdef notyet
582 #define	ath_hal_hasmcastkeysearch(_ah) \
583 	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
584 #define	ath_hal_getmcastkeysearch(_ah) \
585 	(ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
586 #else
587 #define	ath_hal_getmcastkeysearch(_ah)	0
588 #endif
589 #define	ath_hal_hasfastframes(_ah) \
590 	(ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
591 #define	ath_hal_hasbssidmask(_ah) \
592 	(ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
593 #define	ath_hal_hastsfadjust(_ah) \
594 	(ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
595 #define	ath_hal_gettsfadjust(_ah) \
596 	(ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
597 #define	ath_hal_settsfadjust(_ah, _onoff) \
598 	ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
599 #define	ath_hal_hasrfsilent(_ah) \
600 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
601 #define	ath_hal_getrfkill(_ah) \
602 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
603 #define	ath_hal_setrfkill(_ah, _onoff) \
604 	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
605 #define	ath_hal_getrfsilent(_ah, _prfsilent) \
606 	(ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
607 #define	ath_hal_setrfsilent(_ah, _rfsilent) \
608 	ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
609 #define	ath_hal_gettpack(_ah, _ptpack) \
610 	(ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
611 #define	ath_hal_settpack(_ah, _tpack) \
612 	ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
613 #define	ath_hal_gettpcts(_ah, _ptpcts) \
614 	(ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
615 #define	ath_hal_settpcts(_ah, _tpcts) \
616 	ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
617 #define	ath_hal_hasintmit(_ah) \
618 	(ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 0, NULL) == HAL_OK)
619 #define	ath_hal_getintmit(_ah) \
620 	(ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 1, NULL) == HAL_OK)
621 #define	ath_hal_setintmit(_ah, _v) \
622 	ath_hal_setcapability(_ah, HAL_CAP_INTMIT, 1, _v, NULL)
623 #define	ath_hal_getchannoise(_ah, _c) \
624 	((*(_ah)->ah_getChanNoise)((_ah), (_c)))
625 
626 #define	ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
627 	((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
628 #define	ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
629 	((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
630 #define	ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
631 		_txr0, _txtr0, _keyix, _ant, _flags, \
632 		_rtsrate, _rtsdura) \
633 	((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
634 		(_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
635 		(_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
636 #define	ath_hal_setupxtxdesc(_ah, _ds, \
637 		_txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
638 	((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
639 		(_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
640 #define	ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
641 	((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
642 #define	ath_hal_txprocdesc(_ah, _ds, _ts) \
643 	((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
644 #define	ath_hal_gettxintrtxqs(_ah, _txqs) \
645 	((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
646 
647 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
648         ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
649 #define ath_hal_gpioset(_ah, _gpio, _b) \
650         ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
651 #define ath_hal_gpioget(_ah, _gpio) \
652         ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
653 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \
654         ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
655 
656 #define ath_hal_radar_wait(_ah, _chan) \
657 	((*(_ah)->ah_radarWait)((_ah), (_chan)))
658 
659 #endif /* _DEV_ATH_ATHVAR_H */
660