1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Defintions for the Atheros Wireless LAN controller driver. 34 */ 35 #ifndef _DEV_ATH_ATHVAR_H 36 #define _DEV_ATH_ATHVAR_H 37 38 #include <machine/atomic.h> 39 40 #include <dev/ath/ath_hal/ah.h> 41 #include <dev/ath/ath_hal/ah_desc.h> 42 #include <net80211/ieee80211_radiotap.h> 43 #include <dev/ath/if_athioctl.h> 44 #include <dev/ath/if_athrate.h> 45 46 #define ATH_TIMEOUT 1000 47 48 /* 49 * There is a separate TX ath_buf pool for management frames. 50 * This ensures that management frames such as probe responses 51 * and BAR frames can be transmitted during periods of high 52 * TX activity. 53 */ 54 #define ATH_MGMT_TXBUF 32 55 56 /* 57 * 802.11n requires more TX and RX buffers to do AMPDU. 58 */ 59 #ifdef ATH_ENABLE_11N 60 #define ATH_TXBUF 512 61 #define ATH_RXBUF 512 62 #endif 63 64 #ifndef ATH_RXBUF 65 #define ATH_RXBUF 40 /* number of RX buffers */ 66 #endif 67 #ifndef ATH_TXBUF 68 #define ATH_TXBUF 200 /* number of TX buffers */ 69 #endif 70 #define ATH_BCBUF 4 /* number of beacon buffers */ 71 72 #define ATH_TXDESC 10 /* number of descriptors per buffer */ 73 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */ 74 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */ 75 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */ 76 77 #define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */ 78 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */ 79 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */ 80 81 /* 82 * The key cache is used for h/w cipher state and also for 83 * tracking station state such as the current tx antenna. 84 * We also setup a mapping table between key cache slot indices 85 * and station state to short-circuit node lookups on rx. 86 * Different parts have different size key caches. We handle 87 * up to ATH_KEYMAX entries (could dynamically allocate state). 88 */ 89 #define ATH_KEYMAX 128 /* max key cache size we handle */ 90 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */ 91 92 struct taskqueue; 93 struct kthread; 94 struct ath_buf; 95 96 #define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX) 97 98 /* 99 * Per-TID state 100 * 101 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames. 102 */ 103 struct ath_tid { 104 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */ 105 u_int axq_depth; /* SW queue depth */ 106 char axq_name[48]; /* lock name */ 107 struct ath_node *an; /* pointer to parent */ 108 int tid; /* tid */ 109 int ac; /* which AC gets this trafic */ 110 int hwq_depth; /* how many buffers are on HW */ 111 112 struct { 113 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */ 114 u_int axq_depth; /* SW queue depth */ 115 char axq_name[48]; /* lock name */ 116 } filtq; 117 118 /* 119 * Entry on the ath_txq; when there's traffic 120 * to send 121 */ 122 TAILQ_ENTRY(ath_tid) axq_qelem; 123 int sched; 124 int paused; /* >0 if the TID has been paused */ 125 126 /* 127 * These are flags - perhaps later collapse 128 * down to a single uint32_t ? 129 */ 130 int addba_tx_pending; /* TX ADDBA pending */ 131 int bar_wait; /* waiting for BAR */ 132 int bar_tx; /* BAR TXed */ 133 int isfiltered; /* is this node currently filtered */ 134 int clrdmask; /* has clrdmask been set */ 135 136 /* 137 * Is the TID being cleaned up after a transition 138 * from aggregation to non-aggregation? 139 * When this is set to 1, this TID will be paused 140 * and no further traffic will be queued until all 141 * the hardware packets pending for this TID have been 142 * TXed/completed; at which point (non-aggregation) 143 * traffic will resume being TXed. 144 */ 145 int cleanup_inprogress; 146 /* 147 * How many hardware-queued packets are 148 * waiting to be cleaned up. 149 * This is only valid if cleanup_inprogress is 1. 150 */ 151 int incomp; 152 153 /* 154 * The following implements a ring representing 155 * the frames in the current BAW. 156 * To avoid copying the array content each time 157 * the BAW is moved, the baw_head/baw_tail point 158 * to the current BAW begin/end; when the BAW is 159 * shifted the head/tail of the array are also 160 * appropriately shifted. 161 */ 162 /* active tx buffers, beginning at current BAW */ 163 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; 164 /* where the baw head is in the array */ 165 int baw_head; 166 /* where the BAW tail is in the array */ 167 int baw_tail; 168 }; 169 170 /* driver-specific node state */ 171 struct ath_node { 172 struct ieee80211_node an_node; /* base class */ 173 u_int8_t an_mgmtrix; /* min h/w rate index */ 174 u_int8_t an_mcastrix; /* mcast h/w rate index */ 175 uint32_t an_is_powersave; /* node is sleeping */ 176 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */ 177 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */ 178 char an_name[32]; /* eg "wlan0_a1" */ 179 struct mtx an_mtx; /* protecting the ath_node state */ 180 uint32_t an_swq_depth; /* how many SWQ packets for this 181 node */ 182 /* variable-length rate control state follows */ 183 }; 184 #define ATH_NODE(ni) ((struct ath_node *)(ni)) 185 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni)) 186 187 #define ATH_RSSI_LPF_LEN 10 188 #define ATH_RSSI_DUMMY_MARKER 0x127 189 #define ATH_EP_MUL(x, mul) ((x) * (mul)) 190 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER)) 191 #define ATH_LPF_RSSI(x, y, len) \ 192 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y)) 193 #define ATH_RSSI_LPF(x, y) do { \ 194 if ((y) >= -20) \ 195 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \ 196 } while (0) 197 #define ATH_EP_RND(x,mul) \ 198 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 199 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER) 200 201 typedef enum { 202 ATH_BUFTYPE_NORMAL = 0, 203 ATH_BUFTYPE_MGMT = 1, 204 } ath_buf_type_t; 205 206 struct ath_buf { 207 TAILQ_ENTRY(ath_buf) bf_list; 208 struct ath_buf * bf_next; /* next buffer in the aggregate */ 209 int bf_nseg; 210 HAL_STATUS bf_rxstatus; 211 uint16_t bf_flags; /* status flags (below) */ 212 uint16_t bf_descid; /* 16 bit descriptor ID */ 213 struct ath_desc *bf_desc; /* virtual addr of desc */ 214 struct ath_desc_status bf_status; /* tx/rx status */ 215 bus_addr_t bf_daddr; /* physical addr of desc */ 216 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */ 217 struct mbuf *bf_m; /* mbuf for buf */ 218 struct ieee80211_node *bf_node; /* pointer to the node */ 219 struct ath_desc *bf_lastds; /* last descriptor for comp status */ 220 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */ 221 bus_size_t bf_mapsize; 222 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */ 223 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER]; 224 225 /* Completion function to call on TX complete (fail or not) */ 226 /* 227 * "fail" here is set to 1 if the queue entries were removed 228 * through a call to ath_tx_draintxq(). 229 */ 230 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail); 231 232 /* This state is kept to support software retries and aggregation */ 233 struct { 234 uint16_t bfs_seqno; /* sequence number of this packet */ 235 uint16_t bfs_ndelim; /* number of delims for padding */ 236 237 uint8_t bfs_retries; /* retry count */ 238 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */ 239 uint8_t bfs_nframes; /* number of frames in aggregate */ 240 uint8_t bfs_pri; /* packet AC priority */ 241 242 struct ath_txq *bfs_txq; /* eventual dest hardware TXQ */ 243 244 u_int32_t bfs_aggr:1, /* part of aggregate? */ 245 bfs_aggrburst:1, /* part of aggregate burst? */ 246 bfs_isretried:1, /* retried frame? */ 247 bfs_dobaw:1, /* actually check against BAW? */ 248 bfs_addedbaw:1, /* has been added to the BAW */ 249 bfs_shpream:1, /* use short preamble */ 250 bfs_istxfrag:1, /* is fragmented */ 251 bfs_ismrr:1, /* do multi-rate TX retry */ 252 bfs_doprot:1, /* do RTS/CTS based protection */ 253 bfs_doratelookup:1; /* do rate lookup before each TX */ 254 255 /* 256 * These fields are passed into the 257 * descriptor setup functions. 258 */ 259 260 /* Make this an 8 bit value? */ 261 HAL_PKT_TYPE bfs_atype; /* packet type */ 262 263 uint32_t bfs_pktlen; /* length of this packet */ 264 265 uint16_t bfs_hdrlen; /* length of this packet header */ 266 uint16_t bfs_al; /* length of aggregate */ 267 268 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */ 269 uint8_t bfs_txrate0; /* first TX rate */ 270 uint8_t bfs_try0; /* first try count */ 271 272 uint16_t bfs_txpower; /* tx power */ 273 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */ 274 uint8_t bfs_ctsrate; /* CTS rate */ 275 276 /* 16 bit? */ 277 int32_t bfs_keyix; /* crypto key index */ 278 int32_t bfs_txantenna; /* TX antenna config */ 279 280 /* Make this an 8 bit value? */ 281 enum ieee80211_protmode bfs_protmode; 282 283 /* 16 bit? */ 284 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */ 285 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */ 286 } bf_state; 287 }; 288 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead; 289 290 #define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */ 291 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */ 292 293 /* 294 * DMA state for tx/rx descriptors. 295 */ 296 struct ath_descdma { 297 const char* dd_name; 298 struct ath_desc *dd_desc; /* descriptors */ 299 int dd_descsize; /* size of single descriptor */ 300 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 301 bus_size_t dd_desc_len; /* size of dd_desc */ 302 bus_dma_segment_t dd_dseg; 303 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 304 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 305 struct ath_buf *dd_bufptr; /* associated buffers */ 306 }; 307 308 /* 309 * Data transmit queue state. One of these exists for each 310 * hardware transmit queue. Packets sent to us from above 311 * are assigned to queues based on their priority. Not all 312 * devices support a complete set of hardware transmit queues. 313 * For those devices the array sc_ac2q will map multiple 314 * priorities to fewer hardware queues (typically all to one 315 * hardware queue). 316 */ 317 struct ath_txq { 318 struct ath_softc *axq_softc; /* Needed for scheduling */ 319 u_int axq_qnum; /* hardware q number */ 320 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */ 321 u_int axq_ac; /* WME AC */ 322 u_int axq_flags; 323 #define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */ 324 u_int axq_depth; /* queue depth (stat only) */ 325 u_int axq_aggr_depth; /* how many aggregates are queued */ 326 u_int axq_fifo_depth; /* depth of FIFO frames */ 327 u_int axq_intrcnt; /* interrupt count */ 328 u_int32_t *axq_link; /* link ptr in last TX desc */ 329 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */ 330 struct mtx axq_lock; /* lock on q and link */ 331 char axq_name[12]; /* e.g. "ath0_txq4" */ 332 333 /* Per-TID traffic queue for software -> hardware TX */ 334 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq; 335 }; 336 337 #define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx) 338 #define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx) 339 #define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED) 340 #define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \ 341 MA_NOTOWNED) 342 343 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ 344 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \ 345 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \ 346 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \ 347 } while (0) 348 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock) 349 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock) 350 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock) 351 #define ATH_TXQ_LOCK_ASSERT(_tq) \ 352 mtx_assert(&(_tq)->axq_lock, MA_OWNED) 353 #define ATH_TXQ_UNLOCK_ASSERT(_tq) \ 354 mtx_assert(&(_tq)->axq_lock, MA_NOTOWNED) 355 #define ATH_TXQ_IS_LOCKED(_tq) mtx_owned(&(_tq)->axq_lock) 356 357 #define ATH_TID_LOCK_ASSERT(_sc, _tid) \ 358 ATH_TXQ_LOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 359 #define ATH_TID_UNLOCK_ASSERT(_sc, _tid) \ 360 ATH_TXQ_UNLOCK_ASSERT((_sc)->sc_ac2q[(_tid)->ac]) 361 362 /* 363 * These are for the hardware queue. 364 */ 365 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \ 366 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \ 367 (_tq)->axq_depth++; \ 368 } while (0) 369 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ 370 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \ 371 (_tq)->axq_depth++; \ 372 } while (0) 373 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \ 374 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \ 375 (_tq)->axq_depth--; \ 376 } while (0) 377 #define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q) 378 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field) 379 380 /* 381 * These are for the TID software queue. 382 */ 383 #define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \ 384 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \ 385 (_tq)->axq_depth++; \ 386 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 387 } while (0) 388 #define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \ 389 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \ 390 (_tq)->axq_depth++; \ 391 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 392 } while (0) 393 #define ATH_TID_REMOVE(_tq, _elm, _field) do { \ 394 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \ 395 (_tq)->axq_depth--; \ 396 atomic_subtract_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 397 } while (0) 398 #define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q) 399 #define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field) 400 401 /* 402 * These are for the TID filtered frame queue 403 */ 404 #define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \ 405 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \ 406 (_tq)->axq_depth++; \ 407 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 408 } while (0) 409 #define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \ 410 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \ 411 (_tq)->axq_depth++; \ 412 atomic_add_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 413 } while (0) 414 #define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \ 415 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \ 416 (_tq)->axq_depth--; \ 417 atomic_subtract_rel_32( &((_tq)->an)->an_swq_depth, 1); \ 418 } while (0) 419 #define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q) 420 #define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field) 421 422 struct ath_vap { 423 struct ieee80211vap av_vap; /* base class */ 424 int av_bslot; /* beacon slot index */ 425 struct ath_buf *av_bcbuf; /* beacon buffer */ 426 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */ 427 struct ath_txq av_mcastq; /* buffered mcast s/w queue */ 428 429 void (*av_recv_mgmt)(struct ieee80211_node *, 430 struct mbuf *, int, int, int); 431 int (*av_newstate)(struct ieee80211vap *, 432 enum ieee80211_state, int); 433 void (*av_bmiss)(struct ieee80211vap *); 434 void (*av_node_ps)(struct ieee80211_node *, int); 435 }; 436 #define ATH_VAP(vap) ((struct ath_vap *)(vap)) 437 438 struct taskqueue; 439 struct ath_tx99; 440 441 /* 442 * Whether to reset the TX/RX queue with or without 443 * a queue flush. 444 */ 445 typedef enum { 446 ATH_RESET_DEFAULT = 0, 447 ATH_RESET_NOLOSS = 1, 448 ATH_RESET_FULL = 2, 449 } ATH_RESET_TYPE; 450 451 struct ath_rx_methods { 452 void (*recv_stop)(struct ath_softc *sc, int dodelay); 453 int (*recv_start)(struct ath_softc *sc); 454 void (*recv_flush)(struct ath_softc *sc); 455 void (*recv_tasklet)(void *arg, int npending); 456 int (*recv_rxbuf_init)(struct ath_softc *sc, 457 struct ath_buf *bf); 458 int (*recv_setup)(struct ath_softc *sc); 459 int (*recv_teardown)(struct ath_softc *sc); 460 }; 461 462 /* 463 * Represent the current state of the RX FIFO. 464 */ 465 struct ath_rx_edma { 466 struct ath_buf **m_fifo; 467 int m_fifolen; 468 int m_fifo_head; 469 int m_fifo_tail; 470 int m_fifo_depth; 471 struct mbuf *m_rxpending; 472 }; 473 474 struct ath_tx_edma_fifo { 475 struct ath_buf **m_fifo; 476 int m_fifolen; 477 int m_fifo_head; 478 int m_fifo_tail; 479 int m_fifo_depth; 480 }; 481 482 struct ath_tx_methods { 483 int (*xmit_setup)(struct ath_softc *sc); 484 int (*xmit_teardown)(struct ath_softc *sc); 485 void (*xmit_attach_comp_func)(struct ath_softc *sc); 486 487 void (*xmit_dma_restart)(struct ath_softc *sc, 488 struct ath_txq *txq); 489 void (*xmit_handoff)(struct ath_softc *sc, 490 struct ath_txq *txq, struct ath_buf *bf); 491 void (*xmit_drain)(struct ath_softc *sc, 492 ATH_RESET_TYPE reset_type); 493 }; 494 495 struct ath_softc { 496 struct ifnet *sc_ifp; /* interface common */ 497 struct ath_stats sc_stats; /* interface statistics */ 498 struct ath_tx_aggr_stats sc_aggr_stats; 499 struct ath_intr_stats sc_intr_stats; 500 uint64_t sc_debug; 501 uint64_t sc_ktrdebug; 502 int sc_nvaps; /* # vaps */ 503 int sc_nstavaps; /* # station vaps */ 504 int sc_nmeshvaps; /* # mbss vaps */ 505 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN]; 506 u_int8_t sc_nbssid0; /* # vap's using base mac */ 507 uint32_t sc_bssidmask; /* bssid mask */ 508 509 struct ath_rx_methods sc_rx; 510 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */ 511 struct ath_tx_methods sc_tx; 512 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES]; 513 514 int sc_rx_statuslen; 515 int sc_tx_desclen; 516 int sc_tx_statuslen; 517 int sc_tx_nmaps; /* Number of TX maps */ 518 int sc_edma_bufsize; 519 520 void (*sc_node_cleanup)(struct ieee80211_node *); 521 void (*sc_node_free)(struct ieee80211_node *); 522 device_t sc_dev; 523 HAL_BUS_TAG sc_st; /* bus space tag */ 524 HAL_BUS_HANDLE sc_sh; /* bus space handle */ 525 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 526 struct mtx sc_mtx; /* master lock (recursive) */ 527 struct mtx sc_pcu_mtx; /* PCU access mutex */ 528 char sc_pcu_mtx_name[32]; 529 struct mtx sc_rx_mtx; /* RX access mutex */ 530 char sc_rx_mtx_name[32]; 531 struct taskqueue *sc_tq; /* private task queue */ 532 struct ath_hal *sc_ah; /* Atheros HAL */ 533 struct ath_ratectrl *sc_rc; /* tx rate control support */ 534 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */ 535 void (*sc_setdefantenna)(struct ath_softc *, u_int); 536 unsigned int sc_invalid : 1,/* disable hardware accesses */ 537 sc_mrretry : 1,/* multi-rate retry support */ 538 sc_mrrprot : 1,/* MRR + protection support */ 539 sc_softled : 1,/* enable LED gpio status */ 540 sc_hardled : 1,/* enable MAC LED status */ 541 sc_splitmic : 1,/* split TKIP MIC keys */ 542 sc_needmib : 1,/* enable MIB stats intr */ 543 sc_diversity: 1,/* enable rx diversity */ 544 sc_hasveol : 1,/* tx VEOL support */ 545 sc_ledstate : 1,/* LED on/off state */ 546 sc_blinking : 1,/* LED blink operation active */ 547 sc_mcastkey : 1,/* mcast key cache search */ 548 sc_scanning : 1,/* scanning active */ 549 sc_syncbeacon:1,/* sync/resync beacon timers */ 550 sc_hasclrkey: 1,/* CLR key supported */ 551 sc_xchanmode: 1,/* extended channel mode */ 552 sc_outdoor : 1,/* outdoor operation */ 553 sc_dturbo : 1,/* dynamic turbo in use */ 554 sc_hasbmask : 1,/* bssid mask support */ 555 sc_hasbmatch: 1,/* bssid match disable support*/ 556 sc_hastsfadd: 1,/* tsf adjust support */ 557 sc_beacons : 1,/* beacons running */ 558 sc_swbmiss : 1,/* sta mode using sw bmiss */ 559 sc_stagbeacons:1,/* use staggered beacons */ 560 sc_wmetkipmic:1,/* can do WME+TKIP MIC */ 561 sc_resume_up: 1,/* on resume, start all vaps */ 562 sc_tdma : 1,/* TDMA in use */ 563 sc_setcca : 1,/* set/clr CCA with TDMA */ 564 sc_resetcal : 1,/* reset cal state next trip */ 565 sc_rxslink : 1,/* do self-linked final descriptor */ 566 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */ 567 sc_isedma : 1;/* supports EDMA */ 568 uint32_t sc_eerd; /* regdomain from EEPROM */ 569 uint32_t sc_eecc; /* country code from EEPROM */ 570 /* rate tables */ 571 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 572 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 573 enum ieee80211_phymode sc_curmode; /* current phy mode */ 574 HAL_OPMODE sc_opmode; /* current operating mode */ 575 u_int16_t sc_curtxpow; /* current tx power limit */ 576 u_int16_t sc_curaid; /* current association id */ 577 struct ieee80211_channel *sc_curchan; /* current installed channel */ 578 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 579 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 580 struct { 581 u_int8_t ieeerate; /* IEEE rate */ 582 u_int8_t rxflags; /* radiotap rx flags */ 583 u_int8_t txflags; /* radiotap tx flags */ 584 u_int16_t ledon; /* softled on time */ 585 u_int16_t ledoff; /* softled off time */ 586 } sc_hwmap[32]; /* h/w rate ix mappings */ 587 u_int8_t sc_protrix; /* protection rate index */ 588 u_int8_t sc_lastdatarix; /* last data frame rate index */ 589 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 590 u_int sc_fftxqmin; /* min frames before staging */ 591 u_int sc_fftxqmax; /* max frames before drop */ 592 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 593 594 HAL_INT sc_imask; /* interrupt mask copy */ 595 596 /* 597 * These are modified in the interrupt handler as well as 598 * the task queues and other contexts. Thus these must be 599 * protected by a mutex, or they could clash. 600 * 601 * For now, access to these is behind the ATH_LOCK, 602 * just to save time. 603 */ 604 uint32_t sc_txq_active; /* bitmap of active TXQs */ 605 uint32_t sc_kickpcu; /* whether to kick the PCU */ 606 uint32_t sc_rxproc_cnt; /* In RX processing */ 607 uint32_t sc_txproc_cnt; /* In TX processing */ 608 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */ 609 uint32_t sc_inreset_cnt; /* In active reset/chanchange */ 610 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */ 611 uint32_t sc_intr_cnt; /* refcount on interrupt handling */ 612 613 u_int sc_keymax; /* size of key cache */ 614 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 615 616 /* 617 * Software based LED blinking 618 */ 619 u_int sc_ledpin; /* GPIO pin for driving LED */ 620 u_int sc_ledon; /* pin setting for LED on */ 621 u_int sc_ledidle; /* idle polling interval */ 622 int sc_ledevent; /* time of last LED event */ 623 u_int8_t sc_txrix; /* current tx rate for LED */ 624 u_int16_t sc_ledoff; /* off time for current blink */ 625 struct callout sc_ledtimer; /* led off timer */ 626 627 /* 628 * Hardware based LED blinking 629 */ 630 int sc_led_pwr_pin; /* MAC power LED GPIO pin */ 631 int sc_led_net_pin; /* MAC network LED GPIO pin */ 632 633 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 634 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 635 636 struct ath_descdma sc_rxdma; /* RX descriptors */ 637 ath_bufhead sc_rxbuf; /* receive buffer */ 638 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 639 struct task sc_rxtask; /* rx int processing */ 640 u_int8_t sc_defant; /* current default antenna */ 641 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 642 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 643 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 644 struct ath_rx_radiotap_header sc_rx_th; 645 int sc_rx_th_len; 646 u_int sc_monpass; /* frames to pass in mon.mode */ 647 648 struct ath_descdma sc_txdma; /* TX descriptors */ 649 uint16_t sc_txbuf_descid; 650 ath_bufhead sc_txbuf; /* transmit buffer */ 651 int sc_txbuf_cnt; /* how many buffers avail */ 652 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */ 653 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */ 654 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */ 655 struct mtx sc_txbuflock; /* txbuf lock */ 656 char sc_txname[12]; /* e.g. "ath0_buf" */ 657 u_int sc_txqsetup; /* h/w queues setup */ 658 u_int sc_txintrperiod;/* tx interrupt batching */ 659 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 660 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 661 struct task sc_txtask; /* tx int processing */ 662 struct task sc_txqtask; /* tx proc processing */ 663 struct task sc_txsndtask; /* tx send processing */ 664 665 struct ath_descdma sc_txcompdma; /* TX EDMA completion */ 666 struct mtx sc_txcomplock; /* TX EDMA completion lock */ 667 char sc_txcompname[12]; /* eg ath0_txcomp */ 668 669 int sc_wd_timer; /* count down for wd timer */ 670 struct callout sc_wd_ch; /* tx watchdog timer */ 671 struct ath_tx_radiotap_header sc_tx_th; 672 int sc_tx_th_len; 673 674 struct ath_descdma sc_bdma; /* beacon descriptors */ 675 ath_bufhead sc_bbuf; /* beacon buffers */ 676 u_int sc_bhalq; /* HAL q for outgoing beacons */ 677 u_int sc_bmisscount; /* missed beacon transmits */ 678 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 679 struct ath_txq *sc_cabq; /* tx q for cab frames */ 680 struct task sc_bmisstask; /* bmiss int processing */ 681 struct task sc_bstucktask; /* stuck beacon processing */ 682 struct task sc_resettask; /* interface reset task */ 683 struct task sc_fataltask; /* fatal task */ 684 enum { 685 OK, /* no change needed */ 686 UPDATE, /* update pending */ 687 COMMIT /* beacon sent, commit change */ 688 } sc_updateslot; /* slot time update fsm */ 689 int sc_slotupdate; /* slot to advance fsm */ 690 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 691 int sc_nbcnvaps; /* # vaps with beacons */ 692 693 struct callout sc_cal_ch; /* callout handle for cals */ 694 int sc_lastlongcal; /* last long cal completed */ 695 int sc_lastcalreset;/* last cal reset done */ 696 int sc_lastani; /* last ANI poll */ 697 int sc_lastshortcal; /* last short calibration */ 698 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 699 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 700 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 701 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 702 u_int sc_tdmaswba; /* TDMA SWBA counter */ 703 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 704 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 705 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 706 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 707 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 708 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 709 int sc_txchainmask; /* currently configured TX chainmask */ 710 int sc_rxchainmask; /* currently configured RX chainmask */ 711 int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ 712 713 /* Queue limits */ 714 715 /* 716 * To avoid queue starvation in congested conditions, 717 * these parameters tune the maximum number of frames 718 * queued to the data/mcastq before they're dropped. 719 * 720 * This is to prevent: 721 * + a single destination overwhelming everything, including 722 * management/multicast frames; 723 * + multicast frames overwhelming everything (when the 724 * air is sufficiently busy that cabq can't drain.) 725 * 726 * These implement: 727 * + data_minfree is the maximum number of free buffers 728 * overall to successfully allow a data frame. 729 * 730 * + mcastq_maxdepth is the maximum depth allowed of the cabq. 731 */ 732 int sc_txq_data_minfree; 733 int sc_txq_mcastq_maxdepth; 734 735 /* 736 * Aggregation twiddles 737 * 738 * hwq_limit: how busy to keep the hardware queue - don't schedule 739 * further packets to the hardware, regardless of the TID 740 * tid_hwq_lo: how low the per-TID hwq count has to be before the 741 * TID will be scheduled again 742 * tid_hwq_hi: how many frames to queue to the HWQ before the TID 743 * stops being scheduled. 744 */ 745 int sc_hwq_limit; 746 int sc_tid_hwq_lo; 747 int sc_tid_hwq_hi; 748 749 /* DFS related state */ 750 void *sc_dfs; /* Used by an optional DFS module */ 751 int sc_dodfs; /* Whether to enable DFS rx filter bits */ 752 struct task sc_dfstask; /* DFS processing task */ 753 754 /* TX AMPDU handling */ 755 int (*sc_addba_request)(struct ieee80211_node *, 756 struct ieee80211_tx_ampdu *, int, int, int); 757 int (*sc_addba_response)(struct ieee80211_node *, 758 struct ieee80211_tx_ampdu *, int, int, int); 759 void (*sc_addba_stop)(struct ieee80211_node *, 760 struct ieee80211_tx_ampdu *); 761 void (*sc_addba_response_timeout) 762 (struct ieee80211_node *, 763 struct ieee80211_tx_ampdu *); 764 void (*sc_bar_response)(struct ieee80211_node *ni, 765 struct ieee80211_tx_ampdu *tap, 766 int status); 767 }; 768 769 #define ATH_LOCK_INIT(_sc) \ 770 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 771 NULL, MTX_DEF | MTX_RECURSE) 772 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 773 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 774 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 775 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 776 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 777 778 /* 779 * The PCU lock is non-recursive and should be treated as a spinlock. 780 * Although currently the interrupt code is run in netisr context and 781 * doesn't require this, this may change in the future. 782 * Please keep this in mind when protecting certain code paths 783 * with the PCU lock. 784 * 785 * The PCU lock is used to serialise access to the PCU so things such 786 * as TX, RX, state change (eg channel change), channel reset and updates 787 * from interrupt context (eg kickpcu, txqactive bits) do not clash. 788 * 789 * Although the current single-thread taskqueue mechanism protects the 790 * majority of these situations by simply serialising them, there are 791 * a few others which occur at the same time. These include the TX path 792 * (which only acquires ATH_LOCK when recycling buffers to the free list), 793 * ath_set_channel, the channel scanning API and perhaps quite a bit more. 794 */ 795 #define ATH_PCU_LOCK_INIT(_sc) do {\ 796 snprintf((_sc)->sc_pcu_mtx_name, \ 797 sizeof((_sc)->sc_pcu_mtx_name), \ 798 "%s PCU lock", \ 799 device_get_nameunit((_sc)->sc_dev)); \ 800 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \ 801 NULL, MTX_DEF); \ 802 } while (0) 803 #define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx) 804 #define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx) 805 #define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx) 806 #define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 807 MA_OWNED) 808 #define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \ 809 MA_NOTOWNED) 810 811 /* 812 * The RX lock is primarily a(nother) workaround to ensure that the 813 * RX FIFO/list isn't modified by various execution paths. 814 * Even though RX occurs in a single context (the ath taskqueue), the 815 * RX path can be executed via various reset/channel change paths. 816 */ 817 #define ATH_RX_LOCK_INIT(_sc) do {\ 818 snprintf((_sc)->sc_rx_mtx_name, \ 819 sizeof((_sc)->sc_rx_mtx_name), \ 820 "%s RX lock", \ 821 device_get_nameunit((_sc)->sc_dev)); \ 822 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \ 823 NULL, MTX_DEF); \ 824 } while (0) 825 #define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx) 826 #define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx) 827 #define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx) 828 #define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 829 MA_OWNED) 830 #define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \ 831 MA_NOTOWNED) 832 833 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 834 835 #define ATH_TXBUF_LOCK_INIT(_sc) do { \ 836 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 837 device_get_nameunit((_sc)->sc_dev)); \ 838 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 839 } while (0) 840 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 841 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 842 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 843 #define ATH_TXBUF_LOCK_ASSERT(_sc) \ 844 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 845 846 #define ATH_TXSTATUS_LOCK_INIT(_sc) do { \ 847 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \ 848 "%s_buf", \ 849 device_get_nameunit((_sc)->sc_dev)); \ 850 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \ 851 MTX_DEF); \ 852 } while (0) 853 #define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock) 854 #define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock) 855 #define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock) 856 #define ATH_TXSTATUS_LOCK_ASSERT(_sc) \ 857 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED) 858 859 int ath_attach(u_int16_t, struct ath_softc *); 860 int ath_detach(struct ath_softc *); 861 void ath_resume(struct ath_softc *); 862 void ath_suspend(struct ath_softc *); 863 void ath_shutdown(struct ath_softc *); 864 void ath_intr(void *); 865 866 /* 867 * HAL definitions to comply with local coding convention. 868 */ 869 #define ath_hal_detach(_ah) \ 870 ((*(_ah)->ah_detach)((_ah))) 871 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 872 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 873 #define ath_hal_macversion(_ah) \ 874 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 875 #define ath_hal_getratetable(_ah, _mode) \ 876 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 877 #define ath_hal_getmac(_ah, _mac) \ 878 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 879 #define ath_hal_setmac(_ah, _mac) \ 880 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 881 #define ath_hal_getbssidmask(_ah, _mask) \ 882 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 883 #define ath_hal_setbssidmask(_ah, _mask) \ 884 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 885 #define ath_hal_intrset(_ah, _mask) \ 886 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 887 #define ath_hal_intrget(_ah) \ 888 ((*(_ah)->ah_getInterrupts)((_ah))) 889 #define ath_hal_intrpend(_ah) \ 890 ((*(_ah)->ah_isInterruptPending)((_ah))) 891 #define ath_hal_getisr(_ah, _pmask) \ 892 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 893 #define ath_hal_updatetxtriglevel(_ah, _inc) \ 894 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 895 #define ath_hal_setpower(_ah, _mode) \ 896 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 897 #define ath_hal_keycachesize(_ah) \ 898 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 899 #define ath_hal_keyreset(_ah, _ix) \ 900 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 901 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 902 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 903 #define ath_hal_keyisvalid(_ah, _ix) \ 904 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 905 #define ath_hal_keysetmac(_ah, _ix, _mac) \ 906 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 907 #define ath_hal_getrxfilter(_ah) \ 908 ((*(_ah)->ah_getRxFilter)((_ah))) 909 #define ath_hal_setrxfilter(_ah, _filter) \ 910 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 911 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 912 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 913 #define ath_hal_waitforbeacon(_ah, _bf) \ 914 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 915 #define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \ 916 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq))) 917 /* NB: common across all chips */ 918 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 919 #define ath_hal_gettsf32(_ah) \ 920 OS_REG_READ(_ah, AR_TSF_L32) 921 #define ath_hal_gettsf64(_ah) \ 922 ((*(_ah)->ah_getTsf64)((_ah))) 923 #define ath_hal_resettsf(_ah) \ 924 ((*(_ah)->ah_resetTsf)((_ah))) 925 #define ath_hal_rxena(_ah) \ 926 ((*(_ah)->ah_enableReceive)((_ah))) 927 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 928 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 929 #define ath_hal_gettxbuf(_ah, _q) \ 930 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 931 #define ath_hal_numtxpending(_ah, _q) \ 932 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 933 #define ath_hal_getrxbuf(_ah, _rxq) \ 934 ((*(_ah)->ah_getRxDP)((_ah), (_rxq))) 935 #define ath_hal_txstart(_ah, _q) \ 936 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 937 #define ath_hal_setchannel(_ah, _chan) \ 938 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 939 #define ath_hal_calibrate(_ah, _chan, _iqcal) \ 940 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 941 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 942 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 943 #define ath_hal_calreset(_ah, _chan) \ 944 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 945 #define ath_hal_setledstate(_ah, _state) \ 946 ((*(_ah)->ah_setLedState)((_ah), (_state))) 947 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 948 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 949 #define ath_hal_beaconreset(_ah) \ 950 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 951 #define ath_hal_beaconsettimers(_ah, _bt) \ 952 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 953 #define ath_hal_beacontimers(_ah, _bs) \ 954 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 955 #define ath_hal_getnexttbtt(_ah) \ 956 ((*(_ah)->ah_getNextTBTT)((_ah))) 957 #define ath_hal_setassocid(_ah, _bss, _associd) \ 958 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 959 #define ath_hal_phydisable(_ah) \ 960 ((*(_ah)->ah_phyDisable)((_ah))) 961 #define ath_hal_setopmode(_ah) \ 962 ((*(_ah)->ah_setPCUConfig)((_ah))) 963 #define ath_hal_stoptxdma(_ah, _qnum) \ 964 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 965 #define ath_hal_stoppcurecv(_ah) \ 966 ((*(_ah)->ah_stopPcuReceive)((_ah))) 967 #define ath_hal_startpcurecv(_ah) \ 968 ((*(_ah)->ah_startPcuReceive)((_ah))) 969 #define ath_hal_stopdmarecv(_ah) \ 970 ((*(_ah)->ah_stopDmaReceive)((_ah))) 971 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 972 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 973 (_indata), (_insize), (_outdata), (_outsize))) 974 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 975 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 976 #define ath_hal_setuptxqueue(_ah, _type, _irq) \ 977 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 978 #define ath_hal_resettxqueue(_ah, _q) \ 979 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 980 #define ath_hal_releasetxqueue(_ah, _q) \ 981 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 982 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 983 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 984 #define ath_hal_settxqueueprops(_ah, _q, _qi) \ 985 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 986 /* NB: common across all chips */ 987 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 988 #define ath_hal_txqenabled(_ah, _qnum) \ 989 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 990 #define ath_hal_getrfgain(_ah) \ 991 ((*(_ah)->ah_getRfGain)((_ah))) 992 #define ath_hal_getdefantenna(_ah) \ 993 ((*(_ah)->ah_getDefAntenna)((_ah))) 994 #define ath_hal_setdefantenna(_ah, _ant) \ 995 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 996 #define ath_hal_rxmonitor(_ah, _arg, _chan) \ 997 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 998 #define ath_hal_ani_poll(_ah, _chan) \ 999 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 1000 #define ath_hal_mibevent(_ah, _stats) \ 1001 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 1002 #define ath_hal_setslottime(_ah, _us) \ 1003 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1004 #define ath_hal_getslottime(_ah) \ 1005 ((*(_ah)->ah_getSlotTime)((_ah))) 1006 #define ath_hal_setacktimeout(_ah, _us) \ 1007 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 1008 #define ath_hal_getacktimeout(_ah) \ 1009 ((*(_ah)->ah_getAckTimeout)((_ah))) 1010 #define ath_hal_setctstimeout(_ah, _us) \ 1011 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 1012 #define ath_hal_getctstimeout(_ah) \ 1013 ((*(_ah)->ah_getCTSTimeout)((_ah))) 1014 #define ath_hal_getcapability(_ah, _cap, _param, _result) \ 1015 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1016 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 1017 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 1018 #define ath_hal_ciphersupported(_ah, _cipher) \ 1019 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1020 #define ath_hal_getregdomain(_ah, _prd) \ 1021 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 1022 #define ath_hal_setregdomain(_ah, _rd) \ 1023 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 1024 #define ath_hal_getcountrycode(_ah, _pcc) \ 1025 (*(_pcc) = (_ah)->ah_countryCode) 1026 #define ath_hal_gettkipmic(_ah) \ 1027 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 1028 #define ath_hal_settkipmic(_ah, _v) \ 1029 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 1030 #define ath_hal_hastkipsplit(_ah) \ 1031 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1032 #define ath_hal_gettkipsplit(_ah) \ 1033 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1034 #define ath_hal_settkipsplit(_ah, _v) \ 1035 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 1036 #define ath_hal_haswmetkipmic(_ah) \ 1037 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 1038 #define ath_hal_hwphycounters(_ah) \ 1039 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 1040 #define ath_hal_hasdiversity(_ah) \ 1041 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 1042 #define ath_hal_getdiversity(_ah) \ 1043 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 1044 #define ath_hal_setdiversity(_ah, _v) \ 1045 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 1046 #define ath_hal_getantennaswitch(_ah) \ 1047 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 1048 #define ath_hal_setantennaswitch(_ah, _v) \ 1049 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 1050 #define ath_hal_getdiag(_ah, _pv) \ 1051 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 1052 #define ath_hal_setdiag(_ah, _v) \ 1053 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 1054 #define ath_hal_getnumtxqueues(_ah, _pv) \ 1055 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 1056 #define ath_hal_hasveol(_ah) \ 1057 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1058 #define ath_hal_hastxpowlimit(_ah) \ 1059 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 1060 #define ath_hal_settxpowlimit(_ah, _pow) \ 1061 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 1062 #define ath_hal_gettxpowlimit(_ah, _ppow) \ 1063 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 1064 #define ath_hal_getmaxtxpow(_ah, _ppow) \ 1065 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 1066 #define ath_hal_gettpscale(_ah, _scale) \ 1067 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 1068 #define ath_hal_settpscale(_ah, _v) \ 1069 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 1070 #define ath_hal_hastpc(_ah) \ 1071 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 1072 #define ath_hal_gettpc(_ah) \ 1073 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 1074 #define ath_hal_settpc(_ah, _v) \ 1075 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 1076 #define ath_hal_hasbursting(_ah) \ 1077 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 1078 #define ath_hal_setmcastkeysearch(_ah, _v) \ 1079 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 1080 #define ath_hal_hasmcastkeysearch(_ah) \ 1081 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 1082 #define ath_hal_getmcastkeysearch(_ah) \ 1083 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 1084 #define ath_hal_hasfastframes(_ah) \ 1085 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 1086 #define ath_hal_hasbssidmask(_ah) \ 1087 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 1088 #define ath_hal_hasbssidmatch(_ah) \ 1089 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 1090 #define ath_hal_hastsfadjust(_ah) \ 1091 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 1092 #define ath_hal_gettsfadjust(_ah) \ 1093 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 1094 #define ath_hal_settsfadjust(_ah, _onoff) \ 1095 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 1096 #define ath_hal_hasrfsilent(_ah) \ 1097 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1098 #define ath_hal_getrfkill(_ah) \ 1099 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1100 #define ath_hal_setrfkill(_ah, _onoff) \ 1101 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 1102 #define ath_hal_getrfsilent(_ah, _prfsilent) \ 1103 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1104 #define ath_hal_setrfsilent(_ah, _rfsilent) \ 1105 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 1106 #define ath_hal_gettpack(_ah, _ptpack) \ 1107 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 1108 #define ath_hal_settpack(_ah, _tpack) \ 1109 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 1110 #define ath_hal_gettpcts(_ah, _ptpcts) \ 1111 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 1112 #define ath_hal_settpcts(_ah, _tpcts) \ 1113 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 1114 #define ath_hal_hasintmit(_ah) \ 1115 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1116 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK) 1117 #define ath_hal_getintmit(_ah) \ 1118 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \ 1119 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK) 1120 #define ath_hal_setintmit(_ah, _v) \ 1121 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ 1122 HAL_CAP_INTMIT_ENABLE, _v, NULL) 1123 1124 /* EDMA definitions */ 1125 #define ath_hal_hasedma(_ah) \ 1126 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 1127 0, NULL) == HAL_OK) 1128 #define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ 1129 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ 1130 == HAL_OK) 1131 #define ath_hal_getntxmaps(_ah, _req) \ 1132 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ 1133 == HAL_OK) 1134 #define ath_hal_gettxdesclen(_ah, _req) \ 1135 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ 1136 == HAL_OK) 1137 #define ath_hal_gettxstatuslen(_ah, _req) \ 1138 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ 1139 == HAL_OK) 1140 #define ath_hal_getrxstatuslen(_ah, _req) \ 1141 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ 1142 == HAL_OK) 1143 #define ath_hal_setrxbufsize(_ah, _req) \ 1144 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ 1145 == HAL_OK) 1146 1147 #define ath_hal_getchannoise(_ah, _c) \ 1148 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1149 1150 /* 802.11n HAL methods */ 1151 #define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 1152 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 1153 #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 1154 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 1155 #define ath_hal_setrxchainmask(_ah, _rx) \ 1156 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL)) 1157 #define ath_hal_settxchainmask(_ah, _tx) \ 1158 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL)) 1159 #define ath_hal_split4ktrans(_ah) \ 1160 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \ 1161 0, NULL) == HAL_OK) 1162 #define ath_hal_self_linked_final_rxdesc(_ah) \ 1163 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \ 1164 0, NULL) == HAL_OK) 1165 #define ath_hal_gtxto_supported(_ah) \ 1166 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK) 1167 #define ath_hal_has_long_rxdesc_tsf(_ah) \ 1168 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \ 1169 0, NULL) == HAL_OK) 1170 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 1171 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1172 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 1173 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1174 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1175 _txr0, _txtr0, _keyix, _ant, _flags, \ 1176 _rtsrate, _rtsdura) \ 1177 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1178 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1179 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1180 #define ath_hal_setupxtxdesc(_ah, _ds, \ 1181 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1182 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1183 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1184 #define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \ 1185 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \ 1186 (_first), (_last), (_ds0))) 1187 #define ath_hal_txprocdesc(_ah, _ds, _ts) \ 1188 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1189 #define ath_hal_gettxintrtxqs(_ah, _txqs) \ 1190 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 1191 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 1192 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 1193 #define ath_hal_settxdesclink(_ah, _ds, _link) \ 1194 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link))) 1195 #define ath_hal_gettxdesclink(_ah, _ds, _link) \ 1196 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link))) 1197 #define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \ 1198 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr))) 1199 #define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \ 1200 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \ 1201 (_size))) 1202 1203 #define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 1204 _txr0, _txtr0, _antm, _rcr, _rcd) \ 1205 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 1206 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 1207 #define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \ 1208 _keyix, _cipher, _delims, _first, _last, _lastaggr) \ 1209 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \ 1210 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \ 1211 (_first), (_last), (_lastaggr))) 1212 #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 1213 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 1214 1215 #define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 1216 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 1217 (_series), (_ns), (_flags))) 1218 1219 #define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \ 1220 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len))) 1221 #define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 1222 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num))) 1223 #define ath_hal_set11n_aggr_last(_ah, _ds) \ 1224 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds))) 1225 1226 #define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 1227 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 1228 #define ath_hal_clr11n_aggr(_ah, _ds) \ 1229 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds))) 1230 1231 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 1232 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 1233 #define ath_hal_gpioset(_ah, _gpio, _b) \ 1234 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 1235 #define ath_hal_gpioget(_ah, _gpio) \ 1236 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 1237 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 1238 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 1239 1240 /* 1241 * PCIe suspend/resume/poweron/poweroff related macros 1242 */ 1243 #define ath_hal_enablepcie(_ah, _restore, _poweroff) \ 1244 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff))) 1245 #define ath_hal_disablepcie(_ah) \ 1246 ((*(_ah)->ah_disablePCIE)((_ah))) 1247 1248 /* 1249 * This is badly-named; you need to set the correct parameters 1250 * to begin to receive useful radar events; and even then 1251 * it doesn't "enable" DFS. See the ath_dfs/null/ module for 1252 * more information. 1253 */ 1254 #define ath_hal_enabledfs(_ah, _param) \ 1255 ((*(_ah)->ah_enableDfs)((_ah), (_param))) 1256 #define ath_hal_getdfsthresh(_ah, _param) \ 1257 ((*(_ah)->ah_getDfsThresh)((_ah), (_param))) 1258 #define ath_hal_getdfsdefaultthresh(_ah, _param) \ 1259 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param))) 1260 #define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \ 1261 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \ 1262 (_buf), (_event))) 1263 #define ath_hal_is_fast_clock_enabled(_ah) \ 1264 ((*(_ah)->ah_isFastClockEnabled)((_ah))) 1265 #define ath_hal_radar_wait(_ah, _chan) \ 1266 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 1267 #define ath_hal_get_mib_cycle_counts(_ah, _sample) \ 1268 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample))) 1269 #define ath_hal_get_chan_ext_busy(_ah) \ 1270 ((*(_ah)->ah_get11nExtBusy)((_ah))) 1271 1272 #endif /* _DEV_ATH_ATHVAR_H */ 1273