1 /*- 2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_var.h> 77 #include <net/if_dl.h> 78 #include <net/if_media.h> 79 #include <net/if_types.h> 80 #include <net/if_arp.h> 81 #include <net/ethernet.h> 82 #include <net/if_llc.h> 83 84 #include <net80211/ieee80211_var.h> 85 #include <net80211/ieee80211_regdomain.h> 86 #ifdef IEEE80211_SUPPORT_SUPERG 87 #include <net80211/ieee80211_superg.h> 88 #endif 89 #ifdef IEEE80211_SUPPORT_TDMA 90 #include <net80211/ieee80211_tdma.h> 91 #endif 92 93 #include <net/bpf.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/if_ether.h> 98 #endif 99 100 #include <dev/ath/if_athvar.h> 101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 102 #include <dev/ath/ath_hal/ah_diagcodes.h> 103 104 #include <dev/ath/if_ath_debug.h> 105 #include <dev/ath/if_ath_misc.h> 106 #include <dev/ath/if_ath_tsf.h> 107 #include <dev/ath/if_ath_tx.h> 108 #include <dev/ath/if_ath_sysctl.h> 109 #include <dev/ath/if_ath_led.h> 110 #include <dev/ath/if_ath_keycache.h> 111 #include <dev/ath/if_ath_rx.h> 112 #include <dev/ath/if_ath_beacon.h> 113 #include <dev/ath/if_athdfs.h> 114 115 #ifdef ATH_TX99_DIAG 116 #include <dev/ath/ath_tx99/ath_tx99.h> 117 #endif 118 119 #include <dev/ath/if_ath_tx_edma.h> 120 121 #ifdef ATH_DEBUG_ALQ 122 #include <dev/ath/if_ath_alq.h> 123 #endif 124 125 /* 126 * some general macros 127 */ 128 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1) 129 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1) 130 131 /* 132 * XXX doesn't belong here, and should be tunable 133 */ 134 #define ATH_TXSTATUS_RING_SIZE 512 135 136 MALLOC_DECLARE(M_ATHDEV); 137 138 static void ath_edma_tx_processq(struct ath_softc *sc, int dosched); 139 140 /* 141 * Push some frames into the TX FIFO if we have space. 142 */ 143 static void 144 ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq) 145 { 146 struct ath_buf *bf, *bf_last; 147 int i = 0; 148 149 ATH_TXQ_LOCK_ASSERT(txq); 150 151 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d: called\n", 152 __func__, 153 txq->axq_qnum); 154 155 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) { 156 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) 157 break; 158 159 /* 160 * We have space in the FIFO - so let's push a frame 161 * into it. 162 */ 163 164 /* 165 * Remove it from the normal list 166 */ 167 ATH_TXQ_REMOVE(txq, bf, bf_list); 168 169 /* 170 * XXX for now, we only dequeue a frame at a time, so 171 * that's only one buffer. Later on when we just 172 * push this staging _list_ into the queue, we'll 173 * set bf_last to the end pointer in the list. 174 */ 175 bf_last = bf; 176 DPRINTF(sc, ATH_DEBUG_TX_PROC, 177 "%s: Q%d: depth=%d; pushing %p->%p\n", 178 __func__, 179 txq->axq_qnum, 180 txq->axq_fifo_depth, 181 bf, 182 bf_last); 183 184 /* 185 * Append it to the FIFO staging list 186 */ 187 ATH_TXQ_INSERT_TAIL(&txq->fifo, bf, bf_list); 188 189 /* 190 * Set fifo start / fifo end flags appropriately 191 * 192 */ 193 bf->bf_flags |= ATH_BUF_FIFOPTR; 194 bf_last->bf_flags |= ATH_BUF_FIFOEND; 195 196 /* 197 * Push _into_ the FIFO. 198 */ 199 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr); 200 #ifdef ATH_DEBUG 201 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 202 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0); 203 #endif/* ATH_DEBUG */ 204 #ifdef ATH_DEBUG_ALQ 205 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 206 ath_tx_alq_post(sc, bf); 207 #endif /* ATH_DEBUG_ALQ */ 208 txq->axq_fifo_depth++; 209 i++; 210 } 211 if (i > 0) 212 ath_hal_txstart(sc->sc_ah, txq->axq_qnum); 213 } 214 215 /* 216 * Re-initialise the DMA FIFO with the current contents of 217 * said TXQ. 218 * 219 * This should only be called as part of the chip reset path, as it 220 * assumes the FIFO is currently empty. 221 */ 222 static void 223 ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq) 224 { 225 struct ath_buf *bf; 226 int i = 0; 227 int fifostart = 1; 228 int old_fifo_depth; 229 230 DPRINTF(sc, ATH_DEBUG_RESET, "%s: Q%d: called\n", 231 __func__, 232 txq->axq_qnum); 233 234 ATH_TXQ_LOCK_ASSERT(txq); 235 236 /* 237 * Let's log if the tracked FIFO depth doesn't match 238 * what we actually push in. 239 */ 240 old_fifo_depth = txq->axq_fifo_depth; 241 txq->axq_fifo_depth = 0; 242 243 /* 244 * Walk the FIFO staging list, looking for "head" entries. 245 * Since we may have a partially completed list of frames, 246 * we push the first frame we see into the FIFO and re-mark 247 * it as the head entry. We then skip entries until we see 248 * FIFO end, at which point we get ready to push another 249 * entry into the FIFO. 250 */ 251 TAILQ_FOREACH(bf, &txq->fifo.axq_q, bf_list) { 252 /* 253 * If we're looking for FIFOEND and we haven't found 254 * it, skip. 255 * 256 * If we're looking for FIFOEND and we've found it, 257 * reset for another descriptor. 258 */ 259 #ifdef ATH_DEBUG 260 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 261 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0); 262 #endif/* ATH_DEBUG */ 263 #ifdef ATH_DEBUG_ALQ 264 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 265 ath_tx_alq_post(sc, bf); 266 #endif /* ATH_DEBUG_ALQ */ 267 268 if (fifostart == 0) { 269 if (bf->bf_flags & ATH_BUF_FIFOEND) 270 fifostart = 1; 271 continue; 272 } 273 274 /* Make sure we're not overflowing the FIFO! */ 275 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) { 276 device_printf(sc->sc_dev, 277 "%s: Q%d: more frames in the queue; FIFO depth=%d?!\n", 278 __func__, 279 txq->axq_qnum, 280 txq->axq_fifo_depth); 281 } 282 283 #if 0 284 DPRINTF(sc, ATH_DEBUG_RESET, 285 "%s: Q%d: depth=%d: pushing bf=%p; start=%d, end=%d\n", 286 __func__, 287 txq->axq_qnum, 288 txq->axq_fifo_depth, 289 bf, 290 !! (bf->bf_flags & ATH_BUF_FIFOPTR), 291 !! (bf->bf_flags & ATH_BUF_FIFOEND)); 292 #endif 293 294 /* 295 * Set this to be the first buffer in the FIFO 296 * list - even if it's also the last buffer in 297 * a FIFO list! 298 */ 299 bf->bf_flags |= ATH_BUF_FIFOPTR; 300 301 /* Push it into the FIFO and bump the FIFO count */ 302 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr); 303 txq->axq_fifo_depth++; 304 305 /* 306 * If this isn't the last entry either, let's 307 * clear fifostart so we continue looking for 308 * said last entry. 309 */ 310 if (! (bf->bf_flags & ATH_BUF_FIFOEND)) 311 fifostart = 0; 312 i++; 313 } 314 315 /* Only bother starting the queue if there's something in it */ 316 if (i > 0) 317 ath_hal_txstart(sc->sc_ah, txq->axq_qnum); 318 319 DPRINTF(sc, ATH_DEBUG_RESET, "%s: Q%d: FIFO depth was %d, is %d\n", 320 __func__, 321 txq->axq_qnum, 322 old_fifo_depth, 323 txq->axq_fifo_depth); 324 325 /* And now, let's check! */ 326 if (txq->axq_fifo_depth != old_fifo_depth) { 327 device_printf(sc->sc_dev, 328 "%s: Q%d: FIFO depth should be %d, is %d\n", 329 __func__, 330 txq->axq_qnum, 331 old_fifo_depth, 332 txq->axq_fifo_depth); 333 } 334 } 335 336 /* 337 * Hand off this frame to a hardware queue. 338 * 339 * Things are a bit hairy in the EDMA world. The TX FIFO is only 340 * 8 entries deep, so we need to keep track of exactly what we've 341 * pushed into the FIFO and what's just sitting in the TX queue, 342 * waiting to go out. 343 * 344 * So this is split into two halves - frames get appended to the 345 * TXQ; then a scheduler is called to push some frames into the 346 * actual TX FIFO. 347 */ 348 static void 349 ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 350 struct ath_buf *bf) 351 { 352 353 ATH_TXQ_LOCK(txq); 354 355 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 356 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 357 358 /* 359 * XXX TODO: write a hard-coded check to ensure that 360 * the queue id in the TX descriptor matches txq->axq_qnum. 361 */ 362 363 /* Update aggr stats */ 364 if (bf->bf_state.bfs_aggr) 365 txq->axq_aggr_depth++; 366 367 /* Push and update frame stats */ 368 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 369 370 /* For now, set the link pointer in the last descriptor 371 * to be NULL. 372 * 373 * Later on, when it comes time to handling multiple descriptors 374 * in one FIFO push, we can link descriptors together this way. 375 */ 376 377 /* 378 * Finally, call the FIFO schedule routine to schedule some 379 * frames to the FIFO. 380 */ 381 ath_edma_tx_fifo_fill(sc, txq); 382 ATH_TXQ_UNLOCK(txq); 383 } 384 385 /* 386 * Hand off this frame to a multicast software queue. 387 * 388 * The EDMA TX CABQ will get a list of chained frames, chained 389 * together using the next pointer. The single head of that 390 * particular queue is pushed to the hardware CABQ. 391 */ 392 static void 393 ath_edma_xmit_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 394 struct ath_buf *bf) 395 { 396 397 ATH_TX_LOCK_ASSERT(sc); 398 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 399 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 400 401 ATH_TXQ_LOCK(txq); 402 /* 403 * XXX this is mostly duplicated in ath_tx_handoff_mcast(). 404 */ 405 if (ATH_TXQ_LAST(txq, axq_q_s) != NULL) { 406 struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s); 407 struct ieee80211_frame *wh; 408 409 /* mark previous frame */ 410 wh = mtod(bf_last->bf_m, struct ieee80211_frame *); 411 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 412 413 /* re-sync buffer to memory */ 414 bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap, 415 BUS_DMASYNC_PREWRITE); 416 417 /* link descriptor */ 418 ath_hal_settxdesclink(sc->sc_ah, 419 bf_last->bf_lastds, 420 bf->bf_daddr); 421 } 422 #ifdef ATH_DEBUG_ALQ 423 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 424 ath_tx_alq_post(sc, bf); 425 #endif /* ATH_DEBUG_ALQ */ 426 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 427 ATH_TXQ_UNLOCK(txq); 428 } 429 430 /* 431 * Handoff this frame to the hardware. 432 * 433 * For the multicast queue, this will treat it as a software queue 434 * and append it to the list, after updating the MORE_DATA flag 435 * in the previous frame. The cabq processing code will ensure 436 * that the queue contents gets transferred over. 437 * 438 * For the hardware queues, this will queue a frame to the queue 439 * like before, then populate the FIFO from that. Since the 440 * EDMA hardware has 8 FIFO slots per TXQ, this ensures that 441 * frames such as management frames don't get prematurely dropped. 442 * 443 * This does imply that a similar flush-hwq-to-fifoq method will 444 * need to be called from the processq function, before the 445 * per-node software scheduler is called. 446 */ 447 static void 448 ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq, 449 struct ath_buf *bf) 450 { 451 452 DPRINTF(sc, ATH_DEBUG_XMIT_DESC, 453 "%s: called; bf=%p, txq=%p, qnum=%d\n", 454 __func__, 455 bf, 456 txq, 457 txq->axq_qnum); 458 459 if (txq->axq_qnum == ATH_TXQ_SWQ) 460 ath_edma_xmit_handoff_mcast(sc, txq, bf); 461 else 462 ath_edma_xmit_handoff_hw(sc, txq, bf); 463 } 464 465 static int 466 ath_edma_setup_txfifo(struct ath_softc *sc, int qnum) 467 { 468 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum]; 469 470 te->m_fifo = malloc(sizeof(struct ath_buf *) * HAL_TXFIFO_DEPTH, 471 M_ATHDEV, 472 M_NOWAIT | M_ZERO); 473 if (te->m_fifo == NULL) { 474 device_printf(sc->sc_dev, "%s: malloc failed\n", 475 __func__); 476 return (-ENOMEM); 477 } 478 479 /* 480 * Set initial "empty" state. 481 */ 482 te->m_fifo_head = te->m_fifo_tail = te->m_fifo_depth = 0; 483 484 return (0); 485 } 486 487 static int 488 ath_edma_free_txfifo(struct ath_softc *sc, int qnum) 489 { 490 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum]; 491 492 /* XXX TODO: actually deref the ath_buf entries? */ 493 free(te->m_fifo, M_ATHDEV); 494 return (0); 495 } 496 497 static int 498 ath_edma_dma_txsetup(struct ath_softc *sc) 499 { 500 int error; 501 int i; 502 503 error = ath_descdma_alloc_desc(sc, &sc->sc_txsdma, 504 NULL, "txcomp", sc->sc_tx_statuslen, ATH_TXSTATUS_RING_SIZE); 505 if (error != 0) 506 return (error); 507 508 ath_hal_setuptxstatusring(sc->sc_ah, 509 (void *) sc->sc_txsdma.dd_desc, 510 sc->sc_txsdma.dd_desc_paddr, 511 ATH_TXSTATUS_RING_SIZE); 512 513 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 514 ath_edma_setup_txfifo(sc, i); 515 } 516 517 return (0); 518 } 519 520 static int 521 ath_edma_dma_txteardown(struct ath_softc *sc) 522 { 523 int i; 524 525 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 526 ath_edma_free_txfifo(sc, i); 527 } 528 529 ath_descdma_cleanup(sc, &sc->sc_txsdma, NULL); 530 return (0); 531 } 532 533 /* 534 * Drain all TXQs, potentially after completing the existing completed 535 * frames. 536 */ 537 static void 538 ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 539 { 540 struct ifnet *ifp = sc->sc_ifp; 541 int i; 542 543 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 544 545 (void) ath_stoptxdma(sc); 546 547 /* 548 * If reset type is noloss, the TX FIFO needs to be serviced 549 * and those frames need to be handled. 550 * 551 * Otherwise, just toss everything in each TX queue. 552 */ 553 if (reset_type == ATH_RESET_NOLOSS) { 554 ath_edma_tx_processq(sc, 0); 555 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 556 if (ATH_TXQ_SETUP(sc, i)) { 557 ATH_TXQ_LOCK(&sc->sc_txq[i]); 558 /* 559 * Free the holding buffer; DMA is now 560 * stopped. 561 */ 562 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]); 563 /* 564 * Reset the link pointer to NULL; there's 565 * no frames to chain DMA to. 566 */ 567 sc->sc_txq[i].axq_link = NULL; 568 ATH_TXQ_UNLOCK(&sc->sc_txq[i]); 569 } 570 } 571 } else { 572 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 573 if (ATH_TXQ_SETUP(sc, i)) 574 ath_tx_draintxq(sc, &sc->sc_txq[i]); 575 } 576 } 577 578 /* XXX dump out the TX completion FIFO contents */ 579 580 /* XXX dump out the frames */ 581 582 IF_LOCK(&ifp->if_snd); 583 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 584 IF_UNLOCK(&ifp->if_snd); 585 sc->sc_wd_timer = 0; 586 } 587 588 /* 589 * TX completion tasklet. 590 */ 591 592 static void 593 ath_edma_tx_proc(void *arg, int npending) 594 { 595 struct ath_softc *sc = (struct ath_softc *) arg; 596 597 #if 0 598 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n", 599 __func__, npending); 600 #endif 601 ath_edma_tx_processq(sc, 1); 602 } 603 604 /* 605 * Process the TX status queue. 606 */ 607 static void 608 ath_edma_tx_processq(struct ath_softc *sc, int dosched) 609 { 610 struct ath_hal *ah = sc->sc_ah; 611 HAL_STATUS status; 612 struct ath_tx_status ts; 613 struct ath_txq *txq; 614 struct ath_buf *bf; 615 struct ieee80211_node *ni; 616 int nacked = 0; 617 int idx; 618 619 #ifdef ATH_DEBUG 620 /* XXX */ 621 uint32_t txstatus[32]; 622 #endif 623 624 for (idx = 0; ; idx++) { 625 bzero(&ts, sizeof(ts)); 626 627 ATH_TXSTATUS_LOCK(sc); 628 #ifdef ATH_DEBUG 629 ath_hal_gettxrawtxdesc(ah, txstatus); 630 #endif 631 status = ath_hal_txprocdesc(ah, NULL, (void *) &ts); 632 ATH_TXSTATUS_UNLOCK(sc); 633 634 if (status == HAL_EINPROGRESS) 635 break; 636 637 #ifdef ATH_DEBUG 638 if (sc->sc_debug & ATH_DEBUG_TX_PROC) 639 if (ts.ts_queue_id != sc->sc_bhalq) 640 ath_printtxstatbuf(sc, NULL, txstatus, ts.ts_queue_id, 641 idx, (status == HAL_OK)); 642 #endif 643 644 /* 645 * If there is an error with this descriptor, continue 646 * processing. 647 * 648 * XXX TBD: log some statistics? 649 */ 650 if (status == HAL_EIO) { 651 device_printf(sc->sc_dev, "%s: invalid TX status?\n", 652 __func__); 653 break; 654 } 655 656 #if defined(ATH_DEBUG_ALQ) && defined(ATH_DEBUG) 657 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS)) 658 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS, 659 sc->sc_tx_statuslen, 660 (char *) txstatus); 661 #endif /* ATH_DEBUG_ALQ */ 662 663 /* 664 * At this point we have a valid status descriptor. 665 * The QID and descriptor ID (which currently isn't set) 666 * is part of the status. 667 * 668 * We then assume that the descriptor in question is the 669 * -head- of the given QID. Eventually we should verify 670 * this by using the descriptor ID. 671 */ 672 673 /* 674 * The beacon queue is not currently a "real" queue. 675 * Frames aren't pushed onto it and the lock isn't setup. 676 * So skip it for now; the beacon handling code will 677 * free and alloc more beacon buffers as appropriate. 678 */ 679 if (ts.ts_queue_id == sc->sc_bhalq) 680 continue; 681 682 txq = &sc->sc_txq[ts.ts_queue_id]; 683 684 ATH_TXQ_LOCK(txq); 685 bf = ATH_TXQ_FIRST(&txq->fifo); 686 687 /* 688 * Work around the situation where I'm seeing notifications 689 * for Q1 when no frames are available. That needs to be 690 * debugged but not by crashing _here_. 691 */ 692 if (bf == NULL) { 693 device_printf(sc->sc_dev, "%s: Q%d: empty?\n", 694 __func__, 695 ts.ts_queue_id); 696 ATH_TXQ_UNLOCK(txq); 697 continue; 698 } 699 700 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d, bf=%p, start=%d, end=%d\n", 701 __func__, 702 ts.ts_queue_id, bf, 703 !! (bf->bf_flags & ATH_BUF_FIFOPTR), 704 !! (bf->bf_flags & ATH_BUF_FIFOEND)); 705 706 /* XXX TODO: actually output debugging info about this */ 707 708 #if 0 709 /* XXX assert the buffer/descriptor matches the status descid */ 710 if (ts.ts_desc_id != bf->bf_descid) { 711 device_printf(sc->sc_dev, 712 "%s: mismatched descid (qid=%d, tsdescid=%d, " 713 "bfdescid=%d\n", 714 __func__, 715 ts.ts_queue_id, 716 ts.ts_desc_id, 717 bf->bf_descid); 718 } 719 #endif 720 721 /* This removes the buffer and decrements the queue depth */ 722 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list); 723 if (bf->bf_state.bfs_aggr) 724 txq->axq_aggr_depth--; 725 726 /* 727 * If this was the end of a FIFO set, decrement FIFO depth 728 */ 729 if (bf->bf_flags & ATH_BUF_FIFOEND) 730 txq->axq_fifo_depth--; 731 732 /* 733 * If this isn't the final buffer in a FIFO set, mark 734 * the buffer as busy so it goes onto the holding queue. 735 */ 736 if (! (bf->bf_flags & ATH_BUF_FIFOEND)) 737 bf->bf_flags |= ATH_BUF_BUSY; 738 739 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d: FIFO depth is now %d (%d)\n", 740 __func__, 741 txq->axq_qnum, 742 txq->axq_fifo_depth, 743 txq->fifo.axq_depth); 744 745 /* XXX assert FIFO depth >= 0 */ 746 ATH_TXQ_UNLOCK(txq); 747 748 /* 749 * Outside of the TX lock - if the buffer is end 750 * end buffer in this FIFO, we don't need a holding 751 * buffer any longer. 752 */ 753 if (bf->bf_flags & ATH_BUF_FIFOEND) { 754 ATH_TXQ_LOCK(txq); 755 ath_txq_freeholdingbuf(sc, txq); 756 ATH_TXQ_UNLOCK(txq); 757 } 758 759 /* 760 * First we need to make sure ts_rate is valid. 761 * 762 * Pre-EDMA chips pass the whole TX descriptor to 763 * the proctxdesc function which will then fill out 764 * ts_rate based on the ts_finaltsi (final TX index) 765 * in the TX descriptor. However the TX completion 766 * FIFO doesn't have this information. So here we 767 * do a separate HAL call to populate that information. 768 * 769 * The same problem exists with ts_longretry. 770 * The FreeBSD HAL corrects ts_longretry in the HAL layer; 771 * the AR9380 HAL currently doesn't. So until the HAL 772 * is imported and this can be added, we correct for it 773 * here. 774 */ 775 /* XXX TODO */ 776 /* XXX faked for now. Ew. */ 777 if (ts.ts_finaltsi < 4) { 778 ts.ts_rate = 779 bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode; 780 switch (ts.ts_finaltsi) { 781 case 3: ts.ts_longretry += 782 bf->bf_state.bfs_rc[2].tries; 783 case 2: ts.ts_longretry += 784 bf->bf_state.bfs_rc[1].tries; 785 case 1: ts.ts_longretry += 786 bf->bf_state.bfs_rc[0].tries; 787 } 788 } else { 789 device_printf(sc->sc_dev, "%s: finaltsi=%d\n", 790 __func__, 791 ts.ts_finaltsi); 792 ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode; 793 } 794 795 /* 796 * XXX This is terrible. 797 * 798 * Right now, some code uses the TX status that is 799 * passed in here, but the completion handlers in the 800 * software TX path also use bf_status.ds_txstat. 801 * Ew. That should all go away. 802 * 803 * XXX It's also possible the rate control completion 804 * routine is called twice. 805 */ 806 memcpy(&bf->bf_status, &ts, sizeof(ts)); 807 808 ni = bf->bf_node; 809 810 /* Update RSSI */ 811 /* XXX duplicate from ath_tx_processq */ 812 if (ni != NULL && ts.ts_status == 0 && 813 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 814 nacked++; 815 sc->sc_stats.ast_tx_rssi = ts.ts_rssi; 816 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 817 ts.ts_rssi); 818 } 819 820 /* Handle frame completion and rate control update */ 821 ath_tx_process_buf_completion(sc, txq, &ts, bf); 822 823 /* bf is invalid at this point */ 824 825 /* 826 * Now that there's space in the FIFO, let's push some 827 * more frames into it. 828 */ 829 ATH_TXQ_LOCK(txq); 830 if (dosched) 831 ath_edma_tx_fifo_fill(sc, txq); 832 ATH_TXQ_UNLOCK(txq); 833 } 834 835 sc->sc_wd_timer = 0; 836 837 if (idx > 0) { 838 IF_LOCK(&sc->sc_ifp->if_snd); 839 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 840 IF_UNLOCK(&sc->sc_ifp->if_snd); 841 } 842 843 /* Kick software scheduler */ 844 /* 845 * XXX It's inefficient to do this if the FIFO queue is full, 846 * but there's no easy way right now to only populate 847 * the txq task for _one_ TXQ. This should be fixed. 848 */ 849 if (dosched) 850 ath_tx_swq_kick(sc); 851 } 852 853 static void 854 ath_edma_attach_comp_func(struct ath_softc *sc) 855 { 856 857 TASK_INIT(&sc->sc_txtask, 0, ath_edma_tx_proc, sc); 858 } 859 860 void 861 ath_xmit_setup_edma(struct ath_softc *sc) 862 { 863 864 /* Fetch EDMA field and buffer sizes */ 865 (void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen); 866 (void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen); 867 (void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps); 868 869 if (bootverbose) { 870 device_printf(sc->sc_dev, "TX descriptor length: %d\n", 871 sc->sc_tx_desclen); 872 device_printf(sc->sc_dev, "TX status length: %d\n", 873 sc->sc_tx_statuslen); 874 device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n", 875 sc->sc_tx_nmaps); 876 } 877 878 sc->sc_tx.xmit_setup = ath_edma_dma_txsetup; 879 sc->sc_tx.xmit_teardown = ath_edma_dma_txteardown; 880 sc->sc_tx.xmit_attach_comp_func = ath_edma_attach_comp_func; 881 882 sc->sc_tx.xmit_dma_restart = ath_edma_dma_restart; 883 sc->sc_tx.xmit_handoff = ath_edma_xmit_handoff; 884 sc->sc_tx.xmit_drain = ath_edma_tx_drain; 885 } 886