1 /*- 2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_regdomain.h> 85 #ifdef IEEE80211_SUPPORT_SUPERG 86 #include <net80211/ieee80211_superg.h> 87 #endif 88 #ifdef IEEE80211_SUPPORT_TDMA 89 #include <net80211/ieee80211_tdma.h> 90 #endif 91 92 #include <net/bpf.h> 93 94 #ifdef INET 95 #include <netinet/in.h> 96 #include <netinet/if_ether.h> 97 #endif 98 99 #include <dev/ath/if_athvar.h> 100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101 #include <dev/ath/ath_hal/ah_diagcodes.h> 102 103 #include <dev/ath/if_ath_debug.h> 104 #include <dev/ath/if_ath_misc.h> 105 #include <dev/ath/if_ath_tsf.h> 106 #include <dev/ath/if_ath_tx.h> 107 #include <dev/ath/if_ath_sysctl.h> 108 #include <dev/ath/if_ath_led.h> 109 #include <dev/ath/if_ath_keycache.h> 110 #include <dev/ath/if_ath_rx.h> 111 #include <dev/ath/if_ath_beacon.h> 112 #include <dev/ath/if_athdfs.h> 113 114 #ifdef ATH_TX99_DIAG 115 #include <dev/ath/ath_tx99/ath_tx99.h> 116 #endif 117 118 #include <dev/ath/if_ath_tx_edma.h> 119 120 /* 121 * some general macros 122 */ 123 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1) 124 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1) 125 126 /* 127 * XXX doesn't belong here, and should be tunable 128 */ 129 #define ATH_TXSTATUS_RING_SIZE 512 130 131 MALLOC_DECLARE(M_ATHDEV); 132 133 static void 134 ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq) 135 { 136 struct ath_buf *bf; 137 138 ATH_TXQ_LOCK_ASSERT(txq); 139 140 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called\n", __func__); 141 142 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) { 143 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) 144 break; 145 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr); 146 txq->axq_fifo_depth++; 147 } 148 ath_hal_txstart(sc->sc_ah, txq->axq_qnum); 149 } 150 151 /* 152 * Re-initialise the DMA FIFO with the current contents of 153 * said TXQ. 154 * 155 * This should only be called as part of the chip reset path, as it 156 * assumes the FIFO is currently empty. 157 * 158 * TODO: verify that a cold/warm reset does clear the TX FIFO, so 159 * writing in a partially-filled FIFO will not cause double-entries 160 * to appear. 161 */ 162 static void 163 ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq) 164 { 165 166 device_printf(sc->sc_dev, "%s: called: txq=%p, qnum=%d\n", 167 __func__, 168 txq, 169 txq->axq_qnum); 170 171 ATH_TXQ_LOCK_ASSERT(txq); 172 ath_edma_tx_fifo_fill(sc, txq); 173 174 } 175 176 /* 177 * Hand off this frame to a hardware queue. 178 * 179 * Things are a bit hairy in the EDMA world. The TX FIFO is only 180 * 8 entries deep, so we need to keep track of exactly what we've 181 * pushed into the FIFO and what's just sitting in the TX queue, 182 * waiting to go out. 183 * 184 * So this is split into two halves - frames get appended to the 185 * TXQ; then a scheduler is called to push some frames into the 186 * actual TX FIFO. 187 */ 188 static void 189 ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 190 struct ath_buf *bf) 191 { 192 struct ath_hal *ah = sc->sc_ah; 193 194 ATH_TXQ_LOCK_ASSERT(txq); 195 196 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 197 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 198 199 /* 200 * XXX TODO: write a hard-coded check to ensure that 201 * the queue id in the TX descriptor matches txq->axq_qnum. 202 */ 203 204 /* Update aggr stats */ 205 if (bf->bf_state.bfs_aggr) 206 txq->axq_aggr_depth++; 207 208 /* Push and update frame stats */ 209 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 210 211 #ifdef ATH_DEBUG 212 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 213 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 0); 214 #endif /* ATH_DEBUG */ 215 216 /* Only schedule to the FIFO if there's space */ 217 if (txq->axq_fifo_depth < HAL_TXFIFO_DEPTH) { 218 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 219 txq->axq_fifo_depth++; 220 ath_hal_txstart(ah, txq->axq_qnum); 221 } 222 } 223 224 /* 225 * Hand off this frame to a multicast software queue. 226 * 227 * Unlike legacy DMA, this doesn't chain together frames via the 228 * link pointer. Instead, they're just added to the queue. 229 * When it comes time to populate the CABQ, these frames should 230 * be individually pushed into the FIFO as appropriate. 231 * 232 * Yes, this does mean that I'll eventually have to flesh out some 233 * replacement code to handle populating the CABQ, rather than 234 * what's done in ath_beacon_generate(). It'll have to push each 235 * frame from the HW CABQ to the FIFO rather than just appending 236 * it to the existing TXQ and kicking off DMA. 237 */ 238 static void 239 ath_edma_xmit_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 240 struct ath_buf *bf) 241 { 242 243 ATH_TXQ_LOCK_ASSERT(txq); 244 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 245 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 246 247 /* 248 * XXX this is mostly duplicated in ath_tx_handoff_mcast(). 249 */ 250 if (ATH_TXQ_FIRST(txq) != NULL) { 251 struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s); 252 struct ieee80211_frame *wh; 253 254 /* mark previous frame */ 255 wh = mtod(bf_last->bf_m, struct ieee80211_frame *); 256 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 257 258 /* sync descriptor to memory */ 259 bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap, 260 BUS_DMASYNC_PREWRITE); 261 } 262 263 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 264 } 265 266 /* 267 * Handoff this frame to the hardware. 268 * 269 * For the multicast queue, this will treat it as a software queue 270 * and append it to the list, after updating the MORE_DATA flag 271 * in the previous frame. The cabq processing code will ensure 272 * that the queue contents gets transferred over. 273 * 274 * For the hardware queues, this will queue a frame to the queue 275 * like before, then populate the FIFO from that. Since the 276 * EDMA hardware has 8 FIFO slots per TXQ, this ensures that 277 * frames such as management frames don't get prematurely dropped. 278 * 279 * This does imply that a similar flush-hwq-to-fifoq method will 280 * need to be called from the processq function, before the 281 * per-node software scheduler is called. 282 */ 283 static void 284 ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq, 285 struct ath_buf *bf) 286 { 287 288 ATH_TXQ_LOCK_ASSERT(txq); 289 290 DPRINTF(sc, ATH_DEBUG_XMIT_DESC, 291 "%s: called; bf=%p, txq=%p, qnum=%d\n", 292 __func__, 293 bf, 294 txq, 295 txq->axq_qnum); 296 297 if (txq->axq_qnum == ATH_TXQ_SWQ) 298 ath_edma_xmit_handoff_mcast(sc, txq, bf); 299 else 300 ath_edma_xmit_handoff_hw(sc, txq, bf); 301 302 #if 0 303 /* 304 * XXX For now this is a placeholder; free the buffer 305 * and inform the stack that the TX failed. 306 */ 307 ath_tx_default_comp(sc, bf, 1); 308 #endif 309 } 310 311 static int 312 ath_edma_setup_txfifo(struct ath_softc *sc, int qnum) 313 { 314 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum]; 315 316 te->m_fifo = malloc(sizeof(struct ath_buf *) * HAL_TXFIFO_DEPTH, 317 M_ATHDEV, 318 M_NOWAIT | M_ZERO); 319 if (te->m_fifo == NULL) { 320 device_printf(sc->sc_dev, "%s: malloc failed\n", 321 __func__); 322 return (-ENOMEM); 323 } 324 325 /* 326 * Set initial "empty" state. 327 */ 328 te->m_fifo_head = te->m_fifo_tail = te->m_fifo_depth = 0; 329 330 return (0); 331 } 332 333 static int 334 ath_edma_free_txfifo(struct ath_softc *sc, int qnum) 335 { 336 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum]; 337 338 /* XXX TODO: actually deref the ath_buf entries? */ 339 free(te->m_fifo, M_ATHDEV); 340 return (0); 341 } 342 343 static int 344 ath_edma_dma_txsetup(struct ath_softc *sc) 345 { 346 int error; 347 int i; 348 349 error = ath_descdma_alloc_desc(sc, &sc->sc_txsdma, 350 NULL, "txcomp", sc->sc_tx_statuslen, ATH_TXSTATUS_RING_SIZE); 351 if (error != 0) 352 return (error); 353 354 ath_hal_setuptxstatusring(sc->sc_ah, 355 (void *) sc->sc_txsdma.dd_desc, 356 sc->sc_txsdma.dd_desc_paddr, 357 ATH_TXSTATUS_RING_SIZE); 358 359 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 360 ath_edma_setup_txfifo(sc, i); 361 } 362 363 364 return (0); 365 } 366 367 static int 368 ath_edma_dma_txteardown(struct ath_softc *sc) 369 { 370 int i; 371 372 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 373 ath_edma_free_txfifo(sc, i); 374 } 375 376 ath_descdma_cleanup(sc, &sc->sc_txsdma, NULL); 377 return (0); 378 } 379 380 /* 381 * Drain all TXQs, potentially after completing the existing completed 382 * frames. 383 */ 384 static void 385 ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 386 { 387 struct ifnet *ifp = sc->sc_ifp; 388 int i; 389 390 device_printf(sc->sc_dev, "%s: called\n", __func__); 391 392 (void) ath_stoptxdma(sc); 393 394 /* 395 * If reset type is noloss, the TX FIFO needs to be serviced 396 * and those frames need to be handled. 397 * 398 * Otherwise, just toss everything in each TX queue. 399 */ 400 401 /* XXX dump out the TX completion FIFO contents */ 402 403 /* XXX dump out the frames */ 404 405 /* XXX for now, just drain */ 406 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 407 if (ATH_TXQ_SETUP(sc, i)) 408 ath_tx_draintxq(sc, &sc->sc_txq[i]); 409 } 410 411 IF_LOCK(&ifp->if_snd); 412 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 413 IF_UNLOCK(&ifp->if_snd); 414 sc->sc_wd_timer = 0; 415 } 416 417 /* 418 * Process the TX status queue. 419 */ 420 static void 421 ath_edma_tx_proc(void *arg, int npending) 422 { 423 struct ath_softc *sc = (struct ath_softc *) arg; 424 struct ath_hal *ah = sc->sc_ah; 425 HAL_STATUS status; 426 struct ath_tx_status ts; 427 struct ath_txq *txq; 428 struct ath_buf *bf; 429 struct ieee80211_node *ni; 430 int nacked = 0; 431 432 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n", 433 __func__, npending); 434 435 for (;;) { 436 bzero(&ts, sizeof(ts)); 437 438 ATH_TXSTATUS_LOCK(sc); 439 status = ath_hal_txprocdesc(ah, NULL, (void *) &ts); 440 ATH_TXSTATUS_UNLOCK(sc); 441 442 if (status == HAL_EINPROGRESS) 443 break; 444 445 /* 446 * If there is an error with this descriptor, continue 447 * processing. 448 * 449 * XXX TBD: log some statistics? 450 */ 451 if (status == HAL_EIO) { 452 device_printf(sc->sc_dev, "%s: invalid TX status?\n", 453 __func__); 454 continue; 455 } 456 457 /* 458 * At this point we have a valid status descriptor. 459 * The QID and descriptor ID (which currently isn't set) 460 * is part of the status. 461 * 462 * We then assume that the descriptor in question is the 463 * -head- of the given QID. Eventually we should verify 464 * this by using the descriptor ID. 465 */ 466 467 /* 468 * The beacon queue is not currently a "real" queue. 469 * Frames aren't pushed onto it and the lock isn't setup. 470 * So skip it for now; the beacon handling code will 471 * free and alloc more beacon buffers as appropriate. 472 */ 473 if (ts.ts_queue_id == sc->sc_bhalq) 474 continue; 475 476 txq = &sc->sc_txq[ts.ts_queue_id]; 477 478 ATH_TXQ_LOCK(txq); 479 bf = TAILQ_FIRST(&txq->axq_q); 480 481 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: qcuid=%d, bf=%p\n", 482 __func__, 483 ts.ts_queue_id, bf); 484 485 #if 0 486 /* XXX assert the buffer/descriptor matches the status descid */ 487 if (ts.ts_desc_id != bf->bf_descid) { 488 device_printf(sc->sc_dev, 489 "%s: mismatched descid (qid=%d, tsdescid=%d, " 490 "bfdescid=%d\n", 491 __func__, 492 ts.ts_queue_id, 493 ts.ts_desc_id, 494 bf->bf_descid); 495 } 496 #endif 497 498 /* This removes the buffer and decrements the queue depth */ 499 ATH_TXQ_REMOVE(txq, bf, bf_list); 500 if (bf->bf_state.bfs_aggr) 501 txq->axq_aggr_depth--; 502 txq->axq_fifo_depth --; 503 /* XXX assert FIFO depth >= 0 */ 504 ATH_TXQ_UNLOCK(txq); 505 506 /* 507 * First we need to make sure ts_rate is valid. 508 * 509 * Pre-EDMA chips pass the whole TX descriptor to 510 * the proctxdesc function which will then fill out 511 * ts_rate based on the ts_finaltsi (final TX index) 512 * in the TX descriptor. However the TX completion 513 * FIFO doesn't have this information. So here we 514 * do a separate HAL call to populate that information. 515 */ 516 517 /* XXX TODO */ 518 /* XXX faked for now. Ew. */ 519 if (ts.ts_finaltsi < 4) { 520 ts.ts_rate = 521 bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode; 522 } else { 523 device_printf(sc->sc_dev, "%s: finaltsi=%d\n", 524 __func__, 525 ts.ts_finaltsi); 526 ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode; 527 } 528 529 /* 530 * XXX This is terrible. 531 * 532 * Right now, some code uses the TX status that is 533 * passed in here, but the completion handlers in the 534 * software TX path also use bf_status.ds_txstat. 535 * Ew. That should all go away. 536 * 537 * XXX It's also possible the rate control completion 538 * routine is called twice. 539 */ 540 memcpy(&bf->bf_status, &ts, sizeof(ts)); 541 542 ni = bf->bf_node; 543 544 /* Update RSSI */ 545 /* XXX duplicate from ath_tx_processq */ 546 if (ni != NULL && ts.ts_status == 0 && 547 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 548 nacked++; 549 sc->sc_stats.ast_tx_rssi = ts.ts_rssi; 550 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 551 ts.ts_rssi); 552 } 553 554 /* Handle frame completion and rate control update */ 555 ath_tx_process_buf_completion(sc, txq, &ts, bf); 556 557 /* bf is invalid at this point */ 558 559 /* 560 * Now that there's space in the FIFO, let's push some 561 * more frames into it. 562 * 563 * Unfortunately for now, the txq has FIFO and non-FIFO 564 * frames in the same linked list, so there's no way 565 * to quickly/easily populate frames without walking 566 * the queue and skipping 'axq_fifo_depth' frames. 567 * 568 * So for now, let's only repopulate the FIFO once it 569 * is empty. It's sucky for performance but it's enough 570 * to begin validating that things are somewhat 571 * working. 572 */ 573 ATH_TXQ_LOCK(txq); 574 if (txq->axq_fifo_depth == 0) { 575 ath_edma_tx_fifo_fill(sc, txq); 576 } 577 ATH_TXQ_UNLOCK(txq); 578 } 579 580 sc->sc_wd_timer = 0; 581 582 /* Kick software scheduler */ 583 /* 584 * XXX It's inefficient to do this if the FIFO queue is full, 585 * but there's no easy way right now to only populate 586 * the txq task for _one_ TXQ. This should be fixed. 587 */ 588 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 589 } 590 591 static void 592 ath_edma_attach_comp_func(struct ath_softc *sc) 593 { 594 595 TASK_INIT(&sc->sc_txtask, 0, ath_edma_tx_proc, sc); 596 } 597 598 void 599 ath_xmit_setup_edma(struct ath_softc *sc) 600 { 601 602 /* Fetch EDMA field and buffer sizes */ 603 (void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen); 604 (void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen); 605 (void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps); 606 607 device_printf(sc->sc_dev, "TX descriptor length: %d\n", 608 sc->sc_tx_desclen); 609 device_printf(sc->sc_dev, "TX status length: %d\n", 610 sc->sc_tx_statuslen); 611 device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n", 612 sc->sc_tx_nmaps); 613 614 sc->sc_tx.xmit_setup = ath_edma_dma_txsetup; 615 sc->sc_tx.xmit_teardown = ath_edma_dma_txteardown; 616 sc->sc_tx.xmit_attach_comp_func = ath_edma_attach_comp_func; 617 618 sc->sc_tx.xmit_dma_restart = ath_edma_dma_restart; 619 sc->sc_tx.xmit_handoff = ath_edma_xmit_handoff; 620 sc->sc_tx.xmit_drain = ath_edma_tx_drain; 621 } 622