xref: /freebsd/sys/dev/ath/if_ath_tx_edma.c (revision 39ee7a7a6bdd1557b1c3532abf60d139798ac88b)
1 /*-
2  * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification.
11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13  *    redistribution must be conditioned upon including a substantially
14  *    similar Disclaimer requirement for further binary redistribution.
15  *
16  * NO WARRANTY
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27  * THE POSSIBILITY OF SUCH DAMAGES.
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 /*
34  * Driver for the Atheros Wireless LAN controller.
35  *
36  * This software is derived from work of Atsushi Onoe; his contribution
37  * is greatly appreciated.
38  */
39 
40 #include "opt_inet.h"
41 #include "opt_ath.h"
42 /*
43  * This is needed for register operations which are performed
44  * by the driver - eg, calls to ath_hal_gettsf32().
45  *
46  * It's also required for any AH_DEBUG checks in here, eg the
47  * module dependencies.
48  */
49 #include "opt_ah.h"
50 #include "opt_wlan.h"
51 
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
55 #include <sys/mbuf.h>
56 #include <sys/malloc.h>
57 #include <sys/lock.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
64 #include <sys/bus.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
68 #include <sys/priv.h>
69 #include <sys/module.h>
70 #include <sys/ktr.h>
71 #include <sys/smp.h>	/* for mp_ncpus */
72 
73 #include <machine/bus.h>
74 
75 #include <net/if.h>
76 #include <net/if_var.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_llc.h>
83 
84 #include <net80211/ieee80211_var.h>
85 #include <net80211/ieee80211_regdomain.h>
86 #ifdef IEEE80211_SUPPORT_SUPERG
87 #include <net80211/ieee80211_superg.h>
88 #endif
89 #ifdef IEEE80211_SUPPORT_TDMA
90 #include <net80211/ieee80211_tdma.h>
91 #endif
92 
93 #include <net/bpf.h>
94 
95 #ifdef INET
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
98 #endif
99 
100 #include <dev/ath/if_athvar.h>
101 #include <dev/ath/ath_hal/ah_devid.h>		/* XXX for softled */
102 #include <dev/ath/ath_hal/ah_diagcodes.h>
103 
104 #include <dev/ath/if_ath_debug.h>
105 #include <dev/ath/if_ath_misc.h>
106 #include <dev/ath/if_ath_tsf.h>
107 #include <dev/ath/if_ath_tx.h>
108 #include <dev/ath/if_ath_sysctl.h>
109 #include <dev/ath/if_ath_led.h>
110 #include <dev/ath/if_ath_keycache.h>
111 #include <dev/ath/if_ath_rx.h>
112 #include <dev/ath/if_ath_beacon.h>
113 #include <dev/ath/if_athdfs.h>
114 
115 #ifdef ATH_TX99_DIAG
116 #include <dev/ath/ath_tx99/ath_tx99.h>
117 #endif
118 
119 #include <dev/ath/if_ath_tx_edma.h>
120 
121 #ifdef	ATH_DEBUG_ALQ
122 #include <dev/ath/if_ath_alq.h>
123 #endif
124 
125 /*
126  * some general macros
127  */
128 #define	INCR(_l, _sz)		(_l) ++; (_l) &= ((_sz) - 1)
129 #define	DECR(_l, _sz)		(_l) --; (_l) &= ((_sz) - 1)
130 
131 /*
132  * XXX doesn't belong here, and should be tunable
133  */
134 #define	ATH_TXSTATUS_RING_SIZE	512
135 
136 MALLOC_DECLARE(M_ATHDEV);
137 
138 static void ath_edma_tx_processq(struct ath_softc *sc, int dosched);
139 
140 /*
141  * Push some frames into the TX FIFO if we have space.
142  */
143 static void
144 ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq)
145 {
146 	struct ath_buf *bf, *bf_last;
147 	int i = 0;
148 
149 	ATH_TXQ_LOCK_ASSERT(txq);
150 
151 	DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d: called\n",
152 	    __func__,
153 	    txq->axq_qnum);
154 
155 	TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
156 		if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH)
157 			break;
158 
159 		/*
160 		 * We have space in the FIFO - so let's push a frame
161 		 * into it.
162 		 */
163 
164 		/*
165 		 * Remove it from the normal list
166 		 */
167 		ATH_TXQ_REMOVE(txq, bf, bf_list);
168 
169 		/*
170 		 * XXX for now, we only dequeue a frame at a time, so
171 		 * that's only one buffer.  Later on when we just
172 		 * push this staging _list_ into the queue, we'll
173 		 * set bf_last to the end pointer in the list.
174 		 */
175 		bf_last = bf;
176 		DPRINTF(sc, ATH_DEBUG_TX_PROC,
177 		    "%s: Q%d: depth=%d; pushing %p->%p\n",
178 		    __func__,
179 		    txq->axq_qnum,
180 		    txq->axq_fifo_depth,
181 		    bf,
182 		    bf_last);
183 
184 		/*
185 		 * Append it to the FIFO staging list
186 		 */
187 		ATH_TXQ_INSERT_TAIL(&txq->fifo, bf, bf_list);
188 
189 		/*
190 		 * Set fifo start / fifo end flags appropriately
191 		 *
192 		 */
193 		bf->bf_flags |= ATH_BUF_FIFOPTR;
194 		bf_last->bf_flags |= ATH_BUF_FIFOEND;
195 
196 		/*
197 		 * Push _into_ the FIFO.
198 		 */
199 		ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
200 #ifdef	ATH_DEBUG
201 		if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
202 			ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0);
203 #endif/* ATH_DEBUG */
204 #ifdef	ATH_DEBUG_ALQ
205 		if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
206 			ath_tx_alq_post(sc, bf);
207 #endif /* ATH_DEBUG_ALQ */
208 		txq->axq_fifo_depth++;
209 		i++;
210 	}
211 	if (i > 0)
212 		ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
213 }
214 
215 /*
216  * Re-initialise the DMA FIFO with the current contents of
217  * said TXQ.
218  *
219  * This should only be called as part of the chip reset path, as it
220  * assumes the FIFO is currently empty.
221  */
222 static void
223 ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq)
224 {
225 	struct ath_buf *bf;
226 	int i = 0;
227 	int fifostart = 1;
228 	int old_fifo_depth;
229 
230 	DPRINTF(sc, ATH_DEBUG_RESET, "%s: Q%d: called\n",
231 	    __func__,
232 	    txq->axq_qnum);
233 
234 	ATH_TXQ_LOCK_ASSERT(txq);
235 
236 	/*
237 	 * Let's log if the tracked FIFO depth doesn't match
238 	 * what we actually push in.
239 	 */
240 	old_fifo_depth = txq->axq_fifo_depth;
241 	txq->axq_fifo_depth = 0;
242 
243 	/*
244 	 * Walk the FIFO staging list, looking for "head" entries.
245 	 * Since we may have a partially completed list of frames,
246 	 * we push the first frame we see into the FIFO and re-mark
247 	 * it as the head entry.  We then skip entries until we see
248 	 * FIFO end, at which point we get ready to push another
249 	 * entry into the FIFO.
250 	 */
251 	TAILQ_FOREACH(bf, &txq->fifo.axq_q, bf_list) {
252 		/*
253 		 * If we're looking for FIFOEND and we haven't found
254 		 * it, skip.
255 		 *
256 		 * If we're looking for FIFOEND and we've found it,
257 		 * reset for another descriptor.
258 		 */
259 #ifdef	ATH_DEBUG
260 		if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
261 			ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0);
262 #endif/* ATH_DEBUG */
263 #ifdef	ATH_DEBUG_ALQ
264 		if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
265 			ath_tx_alq_post(sc, bf);
266 #endif /* ATH_DEBUG_ALQ */
267 
268 		if (fifostart == 0) {
269 			if (bf->bf_flags & ATH_BUF_FIFOEND)
270 				fifostart = 1;
271 			continue;
272 		}
273 
274 		/* Make sure we're not overflowing the FIFO! */
275 		if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) {
276 			device_printf(sc->sc_dev,
277 			    "%s: Q%d: more frames in the queue; FIFO depth=%d?!\n",
278 			    __func__,
279 			    txq->axq_qnum,
280 			    txq->axq_fifo_depth);
281 		}
282 
283 #if 0
284 		DPRINTF(sc, ATH_DEBUG_RESET,
285 		    "%s: Q%d: depth=%d: pushing bf=%p; start=%d, end=%d\n",
286 		    __func__,
287 		    txq->axq_qnum,
288 		    txq->axq_fifo_depth,
289 		    bf,
290 		    !! (bf->bf_flags & ATH_BUF_FIFOPTR),
291 		    !! (bf->bf_flags & ATH_BUF_FIFOEND));
292 #endif
293 
294 		/*
295 		 * Set this to be the first buffer in the FIFO
296 		 * list - even if it's also the last buffer in
297 		 * a FIFO list!
298 		 */
299 		bf->bf_flags |= ATH_BUF_FIFOPTR;
300 
301 		/* Push it into the FIFO and bump the FIFO count */
302 		ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
303 		txq->axq_fifo_depth++;
304 
305 		/*
306 		 * If this isn't the last entry either, let's
307 		 * clear fifostart so we continue looking for
308 		 * said last entry.
309 		 */
310 		if (! (bf->bf_flags & ATH_BUF_FIFOEND))
311 			fifostart = 0;
312 		i++;
313 	}
314 
315 	/* Only bother starting the queue if there's something in it */
316 	if (i > 0)
317 		ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
318 
319 	DPRINTF(sc, ATH_DEBUG_RESET, "%s: Q%d: FIFO depth was %d, is %d\n",
320 	    __func__,
321 	    txq->axq_qnum,
322 	    old_fifo_depth,
323 	    txq->axq_fifo_depth);
324 
325 	/* And now, let's check! */
326 	if (txq->axq_fifo_depth != old_fifo_depth) {
327 		device_printf(sc->sc_dev,
328 		    "%s: Q%d: FIFO depth should be %d, is %d\n",
329 		    __func__,
330 		    txq->axq_qnum,
331 		    old_fifo_depth,
332 		    txq->axq_fifo_depth);
333 	}
334 }
335 
336 /*
337  * Hand off this frame to a hardware queue.
338  *
339  * Things are a bit hairy in the EDMA world.  The TX FIFO is only
340  * 8 entries deep, so we need to keep track of exactly what we've
341  * pushed into the FIFO and what's just sitting in the TX queue,
342  * waiting to go out.
343  *
344  * So this is split into two halves - frames get appended to the
345  * TXQ; then a scheduler is called to push some frames into the
346  * actual TX FIFO.
347  */
348 static void
349 ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
350     struct ath_buf *bf)
351 {
352 
353 	ATH_TXQ_LOCK(txq);
354 
355 	KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
356 	    ("%s: busy status 0x%x", __func__, bf->bf_flags));
357 
358 	/*
359 	 * XXX TODO: write a hard-coded check to ensure that
360 	 * the queue id in the TX descriptor matches txq->axq_qnum.
361 	 */
362 
363 	/* Update aggr stats */
364 	if (bf->bf_state.bfs_aggr)
365 		txq->axq_aggr_depth++;
366 
367 	/* Push and update frame stats */
368 	ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
369 
370 	/* For now, set the link pointer in the last descriptor
371 	 * to be NULL.
372 	 *
373 	 * Later on, when it comes time to handling multiple descriptors
374 	 * in one FIFO push, we can link descriptors together this way.
375 	 */
376 
377 	/*
378 	 * Finally, call the FIFO schedule routine to schedule some
379 	 * frames to the FIFO.
380 	 */
381 	ath_edma_tx_fifo_fill(sc, txq);
382 	ATH_TXQ_UNLOCK(txq);
383 }
384 
385 /*
386  * Hand off this frame to a multicast software queue.
387  *
388  * The EDMA TX CABQ will get a list of chained frames, chained
389  * together using the next pointer.  The single head of that
390  * particular queue is pushed to the hardware CABQ.
391  */
392 static void
393 ath_edma_xmit_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
394     struct ath_buf *bf)
395 {
396 
397 	ATH_TX_LOCK_ASSERT(sc);
398 	KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
399 	    ("%s: busy status 0x%x", __func__, bf->bf_flags));
400 
401 	ATH_TXQ_LOCK(txq);
402 	/*
403 	 * XXX this is mostly duplicated in ath_tx_handoff_mcast().
404 	 */
405 	if (ATH_TXQ_LAST(txq, axq_q_s) != NULL) {
406 		struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s);
407 		struct ieee80211_frame *wh;
408 
409 		/* mark previous frame */
410 		wh = mtod(bf_last->bf_m, struct ieee80211_frame *);
411 		wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
412 
413 		/* re-sync buffer to memory */
414 		bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap,
415 		   BUS_DMASYNC_PREWRITE);
416 
417 		/* link descriptor */
418 		ath_hal_settxdesclink(sc->sc_ah,
419 		    bf_last->bf_lastds,
420 		    bf->bf_daddr);
421 	}
422 #ifdef	ATH_DEBUG_ALQ
423 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
424 		ath_tx_alq_post(sc, bf);
425 #endif	/* ATH_DEBUG_ALQ */
426 	ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
427 	ATH_TXQ_UNLOCK(txq);
428 }
429 
430 /*
431  * Handoff this frame to the hardware.
432  *
433  * For the multicast queue, this will treat it as a software queue
434  * and append it to the list, after updating the MORE_DATA flag
435  * in the previous frame.  The cabq processing code will ensure
436  * that the queue contents gets transferred over.
437  *
438  * For the hardware queues, this will queue a frame to the queue
439  * like before, then populate the FIFO from that.  Since the
440  * EDMA hardware has 8 FIFO slots per TXQ, this ensures that
441  * frames such as management frames don't get prematurely dropped.
442  *
443  * This does imply that a similar flush-hwq-to-fifoq method will
444  * need to be called from the processq function, before the
445  * per-node software scheduler is called.
446  */
447 static void
448 ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
449     struct ath_buf *bf)
450 {
451 
452 	DPRINTF(sc, ATH_DEBUG_XMIT_DESC,
453 	    "%s: called; bf=%p, txq=%p, qnum=%d\n",
454 	    __func__,
455 	    bf,
456 	    txq,
457 	    txq->axq_qnum);
458 
459 	if (txq->axq_qnum == ATH_TXQ_SWQ)
460 		ath_edma_xmit_handoff_mcast(sc, txq, bf);
461 	else
462 		ath_edma_xmit_handoff_hw(sc, txq, bf);
463 }
464 
465 static int
466 ath_edma_setup_txfifo(struct ath_softc *sc, int qnum)
467 {
468 	struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
469 
470 	te->m_fifo = malloc(sizeof(struct ath_buf *) * HAL_TXFIFO_DEPTH,
471 	    M_ATHDEV,
472 	    M_NOWAIT | M_ZERO);
473 	if (te->m_fifo == NULL) {
474 		device_printf(sc->sc_dev, "%s: malloc failed\n",
475 		    __func__);
476 		return (-ENOMEM);
477 	}
478 
479 	/*
480 	 * Set initial "empty" state.
481 	 */
482 	te->m_fifo_head = te->m_fifo_tail = te->m_fifo_depth = 0;
483 
484 	return (0);
485 }
486 
487 static int
488 ath_edma_free_txfifo(struct ath_softc *sc, int qnum)
489 {
490 	struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
491 
492 	/* XXX TODO: actually deref the ath_buf entries? */
493 	free(te->m_fifo, M_ATHDEV);
494 	return (0);
495 }
496 
497 static int
498 ath_edma_dma_txsetup(struct ath_softc *sc)
499 {
500 	int error;
501 	int i;
502 
503 	error = ath_descdma_alloc_desc(sc, &sc->sc_txsdma,
504 	    NULL, "txcomp", sc->sc_tx_statuslen, ATH_TXSTATUS_RING_SIZE);
505 	if (error != 0)
506 		return (error);
507 
508 	ath_hal_setuptxstatusring(sc->sc_ah,
509 	    (void *) sc->sc_txsdma.dd_desc,
510 	    sc->sc_txsdma.dd_desc_paddr,
511 	    ATH_TXSTATUS_RING_SIZE);
512 
513 	for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
514 		ath_edma_setup_txfifo(sc, i);
515 	}
516 
517 	return (0);
518 }
519 
520 static int
521 ath_edma_dma_txteardown(struct ath_softc *sc)
522 {
523 	int i;
524 
525 	for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
526 		ath_edma_free_txfifo(sc, i);
527 	}
528 
529 	ath_descdma_cleanup(sc, &sc->sc_txsdma, NULL);
530 	return (0);
531 }
532 
533 /*
534  * Drain all TXQs, potentially after completing the existing completed
535  * frames.
536  */
537 static void
538 ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
539 {
540 	int i;
541 
542 	DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
543 
544 	(void) ath_stoptxdma(sc);
545 
546 	/*
547 	 * If reset type is noloss, the TX FIFO needs to be serviced
548 	 * and those frames need to be handled.
549 	 *
550 	 * Otherwise, just toss everything in each TX queue.
551 	 */
552 	if (reset_type == ATH_RESET_NOLOSS) {
553 		ath_edma_tx_processq(sc, 0);
554 		for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
555 			if (ATH_TXQ_SETUP(sc, i)) {
556 				ATH_TXQ_LOCK(&sc->sc_txq[i]);
557 				/*
558 				 * Free the holding buffer; DMA is now
559 				 * stopped.
560 				 */
561 				ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
562 				/*
563 				 * Reset the link pointer to NULL; there's
564 				 * no frames to chain DMA to.
565 				 */
566 				sc->sc_txq[i].axq_link = NULL;
567 				ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
568 			}
569 		}
570 	} else {
571 		for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
572 			if (ATH_TXQ_SETUP(sc, i))
573 				ath_tx_draintxq(sc, &sc->sc_txq[i]);
574 		}
575 	}
576 
577 	/* XXX dump out the TX completion FIFO contents */
578 
579 	/* XXX dump out the frames */
580 
581 	sc->sc_wd_timer = 0;
582 }
583 
584 /*
585  * TX completion tasklet.
586  */
587 
588 static void
589 ath_edma_tx_proc(void *arg, int npending)
590 {
591 	struct ath_softc *sc = (struct ath_softc *) arg;
592 
593 #if 0
594 	DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n",
595 	    __func__, npending);
596 #endif
597 	ath_edma_tx_processq(sc, 1);
598 }
599 
600 /*
601  * Process the TX status queue.
602  */
603 static void
604 ath_edma_tx_processq(struct ath_softc *sc, int dosched)
605 {
606 	struct ath_hal *ah = sc->sc_ah;
607 	HAL_STATUS status;
608 	struct ath_tx_status ts;
609 	struct ath_txq *txq;
610 	struct ath_buf *bf;
611 	struct ieee80211_node *ni;
612 	int nacked = 0;
613 	int idx;
614 
615 #ifdef	ATH_DEBUG
616 	/* XXX */
617 	uint32_t txstatus[32];
618 #endif
619 
620 	for (idx = 0; ; idx++) {
621 		bzero(&ts, sizeof(ts));
622 
623 		ATH_TXSTATUS_LOCK(sc);
624 #ifdef	ATH_DEBUG
625 		ath_hal_gettxrawtxdesc(ah, txstatus);
626 #endif
627 		status = ath_hal_txprocdesc(ah, NULL, (void *) &ts);
628 		ATH_TXSTATUS_UNLOCK(sc);
629 
630 		if (status == HAL_EINPROGRESS)
631 			break;
632 
633 #ifdef	ATH_DEBUG
634 		if (sc->sc_debug & ATH_DEBUG_TX_PROC)
635 			if (ts.ts_queue_id != sc->sc_bhalq)
636 			ath_printtxstatbuf(sc, NULL, txstatus, ts.ts_queue_id,
637 			    idx, (status == HAL_OK));
638 #endif
639 
640 		/*
641 		 * If there is an error with this descriptor, continue
642 		 * processing.
643 		 *
644 		 * XXX TBD: log some statistics?
645 		 */
646 		if (status == HAL_EIO) {
647 			device_printf(sc->sc_dev, "%s: invalid TX status?\n",
648 			    __func__);
649 			break;
650 		}
651 
652 #if defined(ATH_DEBUG_ALQ) && defined(ATH_DEBUG)
653 		if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS))
654 			if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
655 			    sc->sc_tx_statuslen,
656 			    (char *) txstatus);
657 #endif /* ATH_DEBUG_ALQ */
658 
659 		/*
660 		 * At this point we have a valid status descriptor.
661 		 * The QID and descriptor ID (which currently isn't set)
662 		 * is part of the status.
663 		 *
664 		 * We then assume that the descriptor in question is the
665 		 * -head- of the given QID.  Eventually we should verify
666 		 * this by using the descriptor ID.
667 		 */
668 
669 		/*
670 		 * The beacon queue is not currently a "real" queue.
671 		 * Frames aren't pushed onto it and the lock isn't setup.
672 		 * So skip it for now; the beacon handling code will
673 		 * free and alloc more beacon buffers as appropriate.
674 		 */
675 		if (ts.ts_queue_id == sc->sc_bhalq)
676 			continue;
677 
678 		txq = &sc->sc_txq[ts.ts_queue_id];
679 
680 		ATH_TXQ_LOCK(txq);
681 		bf = ATH_TXQ_FIRST(&txq->fifo);
682 
683 		/*
684 		 * Work around the situation where I'm seeing notifications
685 		 * for Q1 when no frames are available.  That needs to be
686 		 * debugged but not by crashing _here_.
687 		 */
688 		if (bf == NULL) {
689 			device_printf(sc->sc_dev, "%s: Q%d: empty?\n",
690 			    __func__,
691 			    ts.ts_queue_id);
692 			ATH_TXQ_UNLOCK(txq);
693 			continue;
694 		}
695 
696 		DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d, bf=%p, start=%d, end=%d\n",
697 		    __func__,
698 		    ts.ts_queue_id, bf,
699 		    !! (bf->bf_flags & ATH_BUF_FIFOPTR),
700 		    !! (bf->bf_flags & ATH_BUF_FIFOEND));
701 
702 		/* XXX TODO: actually output debugging info about this */
703 
704 #if 0
705 		/* XXX assert the buffer/descriptor matches the status descid */
706 		if (ts.ts_desc_id != bf->bf_descid) {
707 			device_printf(sc->sc_dev,
708 			    "%s: mismatched descid (qid=%d, tsdescid=%d, "
709 			    "bfdescid=%d\n",
710 			    __func__,
711 			    ts.ts_queue_id,
712 			    ts.ts_desc_id,
713 			    bf->bf_descid);
714 		}
715 #endif
716 
717 		/* This removes the buffer and decrements the queue depth */
718 		ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
719 		if (bf->bf_state.bfs_aggr)
720 			txq->axq_aggr_depth--;
721 
722 		/*
723 		 * If this was the end of a FIFO set, decrement FIFO depth
724 		 */
725 		if (bf->bf_flags & ATH_BUF_FIFOEND)
726 			txq->axq_fifo_depth--;
727 
728 		/*
729 		 * If this isn't the final buffer in a FIFO set, mark
730 		 * the buffer as busy so it goes onto the holding queue.
731 		 */
732 		if (! (bf->bf_flags & ATH_BUF_FIFOEND))
733 			bf->bf_flags |= ATH_BUF_BUSY;
734 
735 		DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d: FIFO depth is now %d (%d)\n",
736 		    __func__,
737 		    txq->axq_qnum,
738 		    txq->axq_fifo_depth,
739 		    txq->fifo.axq_depth);
740 
741 		/* XXX assert FIFO depth >= 0 */
742 		ATH_TXQ_UNLOCK(txq);
743 
744 		/*
745 		 * Outside of the TX lock - if the buffer is end
746 		 * end buffer in this FIFO, we don't need a holding
747 		 * buffer any longer.
748 		 */
749 		if (bf->bf_flags & ATH_BUF_FIFOEND) {
750 			ATH_TXQ_LOCK(txq);
751 			ath_txq_freeholdingbuf(sc, txq);
752 			ATH_TXQ_UNLOCK(txq);
753 		}
754 
755 		/*
756 		 * First we need to make sure ts_rate is valid.
757 		 *
758 		 * Pre-EDMA chips pass the whole TX descriptor to
759 		 * the proctxdesc function which will then fill out
760 		 * ts_rate based on the ts_finaltsi (final TX index)
761 		 * in the TX descriptor.  However the TX completion
762 		 * FIFO doesn't have this information.  So here we
763 		 * do a separate HAL call to populate that information.
764 		 *
765 		 * The same problem exists with ts_longretry.
766 		 * The FreeBSD HAL corrects ts_longretry in the HAL layer;
767 		 * the AR9380 HAL currently doesn't.  So until the HAL
768 		 * is imported and this can be added, we correct for it
769 		 * here.
770 		 */
771 		/* XXX TODO */
772 		/* XXX faked for now. Ew. */
773 		if (ts.ts_finaltsi < 4) {
774 			ts.ts_rate =
775 			    bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode;
776 			switch (ts.ts_finaltsi) {
777 			case 3: ts.ts_longretry +=
778 			    bf->bf_state.bfs_rc[2].tries;
779 			case 2: ts.ts_longretry +=
780 			    bf->bf_state.bfs_rc[1].tries;
781 			case 1: ts.ts_longretry +=
782 			    bf->bf_state.bfs_rc[0].tries;
783 			}
784 		} else {
785 			device_printf(sc->sc_dev, "%s: finaltsi=%d\n",
786 			    __func__,
787 			    ts.ts_finaltsi);
788 			ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode;
789 		}
790 
791 		/*
792 		 * XXX This is terrible.
793 		 *
794 		 * Right now, some code uses the TX status that is
795 		 * passed in here, but the completion handlers in the
796 		 * software TX path also use bf_status.ds_txstat.
797 		 * Ew.  That should all go away.
798 		 *
799 		 * XXX It's also possible the rate control completion
800 		 * routine is called twice.
801 		 */
802 		memcpy(&bf->bf_status, &ts, sizeof(ts));
803 
804 		ni = bf->bf_node;
805 
806 		/* Update RSSI */
807 		/* XXX duplicate from ath_tx_processq */
808 		if (ni != NULL && ts.ts_status == 0 &&
809 		    ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
810 			nacked++;
811 			sc->sc_stats.ast_tx_rssi = ts.ts_rssi;
812 			ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
813 			    ts.ts_rssi);
814 		}
815 
816 		/* Handle frame completion and rate control update */
817 		ath_tx_process_buf_completion(sc, txq, &ts, bf);
818 
819 		/* bf is invalid at this point */
820 
821 		/*
822 		 * Now that there's space in the FIFO, let's push some
823 		 * more frames into it.
824 		 */
825 		ATH_TXQ_LOCK(txq);
826 		if (dosched)
827 			ath_edma_tx_fifo_fill(sc, txq);
828 		ATH_TXQ_UNLOCK(txq);
829 	}
830 
831 	sc->sc_wd_timer = 0;
832 
833 	/* Kick software scheduler */
834 	/*
835 	 * XXX It's inefficient to do this if the FIFO queue is full,
836 	 * but there's no easy way right now to only populate
837 	 * the txq task for _one_ TXQ.  This should be fixed.
838 	 */
839 	if (dosched)
840 		ath_tx_swq_kick(sc);
841 }
842 
843 static void
844 ath_edma_attach_comp_func(struct ath_softc *sc)
845 {
846 
847 	TASK_INIT(&sc->sc_txtask, 0, ath_edma_tx_proc, sc);
848 }
849 
850 void
851 ath_xmit_setup_edma(struct ath_softc *sc)
852 {
853 
854 	/* Fetch EDMA field and buffer sizes */
855 	(void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen);
856 	(void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen);
857 	(void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps);
858 
859 	if (bootverbose) {
860 		device_printf(sc->sc_dev, "TX descriptor length: %d\n",
861 		    sc->sc_tx_desclen);
862 		device_printf(sc->sc_dev, "TX status length: %d\n",
863 		    sc->sc_tx_statuslen);
864 		device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n",
865 		    sc->sc_tx_nmaps);
866 	}
867 
868 	sc->sc_tx.xmit_setup = ath_edma_dma_txsetup;
869 	sc->sc_tx.xmit_teardown = ath_edma_dma_txteardown;
870 	sc->sc_tx.xmit_attach_comp_func = ath_edma_attach_comp_func;
871 
872 	sc->sc_tx.xmit_dma_restart = ath_edma_dma_restart;
873 	sc->sc_tx.xmit_handoff = ath_edma_xmit_handoff;
874 	sc->sc_tx.xmit_drain = ath_edma_tx_drain;
875 }
876