1 /*- 2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_regdomain.h> 85 #ifdef IEEE80211_SUPPORT_SUPERG 86 #include <net80211/ieee80211_superg.h> 87 #endif 88 #ifdef IEEE80211_SUPPORT_TDMA 89 #include <net80211/ieee80211_tdma.h> 90 #endif 91 92 #include <net/bpf.h> 93 94 #ifdef INET 95 #include <netinet/in.h> 96 #include <netinet/if_ether.h> 97 #endif 98 99 #include <dev/ath/if_athvar.h> 100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101 #include <dev/ath/ath_hal/ah_diagcodes.h> 102 103 #include <dev/ath/if_ath_debug.h> 104 #include <dev/ath/if_ath_misc.h> 105 #include <dev/ath/if_ath_tsf.h> 106 #include <dev/ath/if_ath_tx.h> 107 #include <dev/ath/if_ath_sysctl.h> 108 #include <dev/ath/if_ath_led.h> 109 #include <dev/ath/if_ath_keycache.h> 110 #include <dev/ath/if_ath_rx.h> 111 #include <dev/ath/if_ath_beacon.h> 112 #include <dev/ath/if_athdfs.h> 113 114 #ifdef ATH_TX99_DIAG 115 #include <dev/ath/ath_tx99/ath_tx99.h> 116 #endif 117 118 #include <dev/ath/if_ath_tx_edma.h> 119 120 #ifdef ATH_DEBUG_ALQ 121 #include <dev/ath/if_ath_alq.h> 122 #endif 123 124 /* 125 * some general macros 126 */ 127 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1) 128 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1) 129 130 /* 131 * XXX doesn't belong here, and should be tunable 132 */ 133 #define ATH_TXSTATUS_RING_SIZE 512 134 135 MALLOC_DECLARE(M_ATHDEV); 136 137 static void ath_edma_tx_processq(struct ath_softc *sc, int dosched); 138 139 static void 140 ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq) 141 { 142 struct ath_buf *bf; 143 int i = 0; 144 145 ATH_TX_LOCK_ASSERT(sc); 146 147 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called\n", __func__); 148 149 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) { 150 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) 151 break; 152 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr); 153 #ifdef ATH_DEBUG 154 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 155 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0); 156 #endif/* ATH_DEBUG */ 157 #ifdef ATH_DEBUG_ALQ 158 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 159 ath_tx_alq_post(sc, bf); 160 #endif /* ATH_DEBUG_ALQ */ 161 txq->axq_fifo_depth++; 162 i++; 163 } 164 if (i > 0) 165 ath_hal_txstart(sc->sc_ah, txq->axq_qnum); 166 } 167 168 /* 169 * Re-initialise the DMA FIFO with the current contents of 170 * said TXQ. 171 * 172 * This should only be called as part of the chip reset path, as it 173 * assumes the FIFO is currently empty. 174 */ 175 static void 176 ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq) 177 { 178 179 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called: txq=%p, qnum=%d\n", 180 __func__, 181 txq, 182 txq->axq_qnum); 183 184 ATH_TX_LOCK_ASSERT(sc); 185 ath_edma_tx_fifo_fill(sc, txq); 186 187 } 188 189 /* 190 * Hand off this frame to a hardware queue. 191 * 192 * Things are a bit hairy in the EDMA world. The TX FIFO is only 193 * 8 entries deep, so we need to keep track of exactly what we've 194 * pushed into the FIFO and what's just sitting in the TX queue, 195 * waiting to go out. 196 * 197 * So this is split into two halves - frames get appended to the 198 * TXQ; then a scheduler is called to push some frames into the 199 * actual TX FIFO. 200 */ 201 static void 202 ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 203 struct ath_buf *bf) 204 { 205 struct ath_hal *ah = sc->sc_ah; 206 207 ATH_TX_LOCK_ASSERT(sc); 208 209 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 210 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 211 212 /* 213 * XXX TODO: write a hard-coded check to ensure that 214 * the queue id in the TX descriptor matches txq->axq_qnum. 215 */ 216 217 /* Update aggr stats */ 218 if (bf->bf_state.bfs_aggr) 219 txq->axq_aggr_depth++; 220 221 /* Push and update frame stats */ 222 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 223 224 /* Only schedule to the FIFO if there's space */ 225 if (txq->axq_fifo_depth < HAL_TXFIFO_DEPTH) { 226 #ifdef ATH_DEBUG 227 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 228 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 0); 229 #endif /* ATH_DEBUG */ 230 #ifdef ATH_DEBUG_ALQ 231 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 232 ath_tx_alq_post(sc, bf); 233 #endif /* ATH_DEBUG_ALQ */ 234 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 235 txq->axq_fifo_depth++; 236 ath_hal_txstart(ah, txq->axq_qnum); 237 } 238 } 239 240 /* 241 * Hand off this frame to a multicast software queue. 242 * 243 * The EDMA TX CABQ will get a list of chained frames, chained 244 * together using the next pointer. The single head of that 245 * particular queue is pushed to the hardware CABQ. 246 */ 247 static void 248 ath_edma_xmit_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 249 struct ath_buf *bf) 250 { 251 252 ATH_TX_LOCK_ASSERT(sc); 253 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 254 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 255 256 /* 257 * XXX this is mostly duplicated in ath_tx_handoff_mcast(). 258 */ 259 if (ATH_TXQ_FIRST(txq) != NULL) { 260 struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s); 261 struct ieee80211_frame *wh; 262 263 /* mark previous frame */ 264 wh = mtod(bf_last->bf_m, struct ieee80211_frame *); 265 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 266 267 /* sync descriptor to memory */ 268 bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap, 269 BUS_DMASYNC_PREWRITE); 270 } 271 272 #ifdef ATH_DEBUG_ALQ 273 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 274 ath_tx_alq_post(sc, bf); 275 #endif /* ATH_DEBUG_ALQ */ 276 277 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 278 ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link); 279 } 280 281 /* 282 * Handoff this frame to the hardware. 283 * 284 * For the multicast queue, this will treat it as a software queue 285 * and append it to the list, after updating the MORE_DATA flag 286 * in the previous frame. The cabq processing code will ensure 287 * that the queue contents gets transferred over. 288 * 289 * For the hardware queues, this will queue a frame to the queue 290 * like before, then populate the FIFO from that. Since the 291 * EDMA hardware has 8 FIFO slots per TXQ, this ensures that 292 * frames such as management frames don't get prematurely dropped. 293 * 294 * This does imply that a similar flush-hwq-to-fifoq method will 295 * need to be called from the processq function, before the 296 * per-node software scheduler is called. 297 */ 298 static void 299 ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq, 300 struct ath_buf *bf) 301 { 302 303 ATH_TX_LOCK_ASSERT(sc); 304 305 DPRINTF(sc, ATH_DEBUG_XMIT_DESC, 306 "%s: called; bf=%p, txq=%p, qnum=%d\n", 307 __func__, 308 bf, 309 txq, 310 txq->axq_qnum); 311 312 if (txq->axq_qnum == ATH_TXQ_SWQ) 313 ath_edma_xmit_handoff_mcast(sc, txq, bf); 314 else 315 ath_edma_xmit_handoff_hw(sc, txq, bf); 316 317 #if 0 318 /* 319 * XXX For now this is a placeholder; free the buffer 320 * and inform the stack that the TX failed. 321 */ 322 ath_tx_default_comp(sc, bf, 1); 323 #endif 324 } 325 326 static int 327 ath_edma_setup_txfifo(struct ath_softc *sc, int qnum) 328 { 329 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum]; 330 331 te->m_fifo = malloc(sizeof(struct ath_buf *) * HAL_TXFIFO_DEPTH, 332 M_ATHDEV, 333 M_NOWAIT | M_ZERO); 334 if (te->m_fifo == NULL) { 335 device_printf(sc->sc_dev, "%s: malloc failed\n", 336 __func__); 337 return (-ENOMEM); 338 } 339 340 /* 341 * Set initial "empty" state. 342 */ 343 te->m_fifo_head = te->m_fifo_tail = te->m_fifo_depth = 0; 344 345 return (0); 346 } 347 348 static int 349 ath_edma_free_txfifo(struct ath_softc *sc, int qnum) 350 { 351 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum]; 352 353 /* XXX TODO: actually deref the ath_buf entries? */ 354 free(te->m_fifo, M_ATHDEV); 355 return (0); 356 } 357 358 static int 359 ath_edma_dma_txsetup(struct ath_softc *sc) 360 { 361 int error; 362 int i; 363 364 error = ath_descdma_alloc_desc(sc, &sc->sc_txsdma, 365 NULL, "txcomp", sc->sc_tx_statuslen, ATH_TXSTATUS_RING_SIZE); 366 if (error != 0) 367 return (error); 368 369 ath_hal_setuptxstatusring(sc->sc_ah, 370 (void *) sc->sc_txsdma.dd_desc, 371 sc->sc_txsdma.dd_desc_paddr, 372 ATH_TXSTATUS_RING_SIZE); 373 374 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 375 ath_edma_setup_txfifo(sc, i); 376 } 377 378 return (0); 379 } 380 381 static int 382 ath_edma_dma_txteardown(struct ath_softc *sc) 383 { 384 int i; 385 386 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 387 ath_edma_free_txfifo(sc, i); 388 } 389 390 ath_descdma_cleanup(sc, &sc->sc_txsdma, NULL); 391 return (0); 392 } 393 394 /* 395 * Drain all TXQs, potentially after completing the existing completed 396 * frames. 397 */ 398 static void 399 ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 400 { 401 struct ifnet *ifp = sc->sc_ifp; 402 int i; 403 404 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 405 406 (void) ath_stoptxdma(sc); 407 408 /* 409 * If reset type is noloss, the TX FIFO needs to be serviced 410 * and those frames need to be handled. 411 * 412 * Otherwise, just toss everything in each TX queue. 413 */ 414 if (reset_type == ATH_RESET_NOLOSS) { 415 ath_edma_tx_processq(sc, 0); 416 } else { 417 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 418 if (ATH_TXQ_SETUP(sc, i)) 419 ath_tx_draintxq(sc, &sc->sc_txq[i]); 420 } 421 } 422 423 /* XXX dump out the TX completion FIFO contents */ 424 425 /* XXX dump out the frames */ 426 427 IF_LOCK(&ifp->if_snd); 428 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 429 IF_UNLOCK(&ifp->if_snd); 430 sc->sc_wd_timer = 0; 431 } 432 433 /* 434 * TX completion tasklet. 435 */ 436 437 static void 438 ath_edma_tx_proc(void *arg, int npending) 439 { 440 struct ath_softc *sc = (struct ath_softc *) arg; 441 442 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n", 443 __func__, npending); 444 ath_edma_tx_processq(sc, 1); 445 } 446 447 /* 448 * Process the TX status queue. 449 */ 450 static void 451 ath_edma_tx_processq(struct ath_softc *sc, int dosched) 452 { 453 struct ath_hal *ah = sc->sc_ah; 454 HAL_STATUS status; 455 struct ath_tx_status ts; 456 struct ath_txq *txq; 457 struct ath_buf *bf; 458 struct ieee80211_node *ni; 459 int nacked = 0; 460 int idx; 461 462 #ifdef ATH_DEBUG 463 /* XXX */ 464 uint32_t txstatus[32]; 465 #endif 466 467 for (idx = 0; ; idx++) { 468 bzero(&ts, sizeof(ts)); 469 470 ATH_TXSTATUS_LOCK(sc); 471 #ifdef ATH_DEBUG 472 ath_hal_gettxrawtxdesc(ah, txstatus); 473 #endif 474 status = ath_hal_txprocdesc(ah, NULL, (void *) &ts); 475 ATH_TXSTATUS_UNLOCK(sc); 476 477 #ifdef ATH_DEBUG 478 if (sc->sc_debug & ATH_DEBUG_TX_PROC) 479 ath_printtxstatbuf(sc, NULL, txstatus, ts.ts_queue_id, 480 idx, (status == HAL_OK)); 481 #endif 482 483 if (status == HAL_EINPROGRESS) 484 break; 485 486 /* 487 * If there is an error with this descriptor, continue 488 * processing. 489 * 490 * XXX TBD: log some statistics? 491 */ 492 if (status == HAL_EIO) { 493 device_printf(sc->sc_dev, "%s: invalid TX status?\n", 494 __func__); 495 continue; 496 } 497 498 #ifdef ATH_DEBUG_ALQ 499 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS)) 500 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS, 501 sc->sc_tx_statuslen, 502 (char *) txstatus); 503 #endif /* ATH_DEBUG_ALQ */ 504 505 /* 506 * At this point we have a valid status descriptor. 507 * The QID and descriptor ID (which currently isn't set) 508 * is part of the status. 509 * 510 * We then assume that the descriptor in question is the 511 * -head- of the given QID. Eventually we should verify 512 * this by using the descriptor ID. 513 */ 514 515 /* 516 * The beacon queue is not currently a "real" queue. 517 * Frames aren't pushed onto it and the lock isn't setup. 518 * So skip it for now; the beacon handling code will 519 * free and alloc more beacon buffers as appropriate. 520 */ 521 if (ts.ts_queue_id == sc->sc_bhalq) 522 continue; 523 524 txq = &sc->sc_txq[ts.ts_queue_id]; 525 526 ATH_TX_LOCK(sc); 527 bf = TAILQ_FIRST(&txq->axq_q); 528 529 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: qcuid=%d, bf=%p\n", 530 __func__, 531 ts.ts_queue_id, bf); 532 533 /* XXX TODO: actually output debugging info about this */ 534 535 #if 0 536 /* XXX assert the buffer/descriptor matches the status descid */ 537 if (ts.ts_desc_id != bf->bf_descid) { 538 device_printf(sc->sc_dev, 539 "%s: mismatched descid (qid=%d, tsdescid=%d, " 540 "bfdescid=%d\n", 541 __func__, 542 ts.ts_queue_id, 543 ts.ts_desc_id, 544 bf->bf_descid); 545 } 546 #endif 547 548 /* This removes the buffer and decrements the queue depth */ 549 ATH_TXQ_REMOVE(txq, bf, bf_list); 550 if (bf->bf_state.bfs_aggr) 551 txq->axq_aggr_depth--; 552 txq->axq_fifo_depth --; 553 /* XXX assert FIFO depth >= 0 */ 554 ATH_TX_UNLOCK(sc); 555 556 /* 557 * First we need to make sure ts_rate is valid. 558 * 559 * Pre-EDMA chips pass the whole TX descriptor to 560 * the proctxdesc function which will then fill out 561 * ts_rate based on the ts_finaltsi (final TX index) 562 * in the TX descriptor. However the TX completion 563 * FIFO doesn't have this information. So here we 564 * do a separate HAL call to populate that information. 565 * 566 * The same problem exists with ts_longretry. 567 * The FreeBSD HAL corrects ts_longretry in the HAL layer; 568 * the AR9380 HAL currently doesn't. So until the HAL 569 * is imported and this can be added, we correct for it 570 * here. 571 */ 572 /* XXX TODO */ 573 /* XXX faked for now. Ew. */ 574 if (ts.ts_finaltsi < 4) { 575 ts.ts_rate = 576 bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode; 577 switch (ts.ts_finaltsi) { 578 case 3: ts.ts_longretry += 579 bf->bf_state.bfs_rc[2].tries; 580 case 2: ts.ts_longretry += 581 bf->bf_state.bfs_rc[1].tries; 582 case 1: ts.ts_longretry += 583 bf->bf_state.bfs_rc[0].tries; 584 } 585 } else { 586 device_printf(sc->sc_dev, "%s: finaltsi=%d\n", 587 __func__, 588 ts.ts_finaltsi); 589 ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode; 590 } 591 592 /* 593 * XXX This is terrible. 594 * 595 * Right now, some code uses the TX status that is 596 * passed in here, but the completion handlers in the 597 * software TX path also use bf_status.ds_txstat. 598 * Ew. That should all go away. 599 * 600 * XXX It's also possible the rate control completion 601 * routine is called twice. 602 */ 603 memcpy(&bf->bf_status, &ts, sizeof(ts)); 604 605 ni = bf->bf_node; 606 607 /* Update RSSI */ 608 /* XXX duplicate from ath_tx_processq */ 609 if (ni != NULL && ts.ts_status == 0 && 610 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 611 nacked++; 612 sc->sc_stats.ast_tx_rssi = ts.ts_rssi; 613 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 614 ts.ts_rssi); 615 } 616 617 /* Handle frame completion and rate control update */ 618 ath_tx_process_buf_completion(sc, txq, &ts, bf); 619 620 /* bf is invalid at this point */ 621 622 /* 623 * Now that there's space in the FIFO, let's push some 624 * more frames into it. 625 * 626 * Unfortunately for now, the txq has FIFO and non-FIFO 627 * frames in the same linked list, so there's no way 628 * to quickly/easily populate frames without walking 629 * the queue and skipping 'axq_fifo_depth' frames. 630 * 631 * So for now, let's only repopulate the FIFO once it 632 * is empty. It's sucky for performance but it's enough 633 * to begin validating that things are somewhat 634 * working. 635 */ 636 ATH_TX_LOCK(sc); 637 if (dosched && txq->axq_fifo_depth == 0) { 638 ath_edma_tx_fifo_fill(sc, txq); 639 } 640 ATH_TX_UNLOCK(sc); 641 } 642 643 sc->sc_wd_timer = 0; 644 645 if (idx > 0) { 646 IF_LOCK(&sc->sc_ifp->if_snd); 647 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 648 IF_UNLOCK(&sc->sc_ifp->if_snd); 649 } 650 651 /* Kick software scheduler */ 652 /* 653 * XXX It's inefficient to do this if the FIFO queue is full, 654 * but there's no easy way right now to only populate 655 * the txq task for _one_ TXQ. This should be fixed. 656 */ 657 if (dosched) 658 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 659 } 660 661 static void 662 ath_edma_attach_comp_func(struct ath_softc *sc) 663 { 664 665 TASK_INIT(&sc->sc_txtask, 0, ath_edma_tx_proc, sc); 666 } 667 668 void 669 ath_xmit_setup_edma(struct ath_softc *sc) 670 { 671 672 /* Fetch EDMA field and buffer sizes */ 673 (void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen); 674 (void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen); 675 (void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps); 676 677 device_printf(sc->sc_dev, "TX descriptor length: %d\n", 678 sc->sc_tx_desclen); 679 device_printf(sc->sc_dev, "TX status length: %d\n", 680 sc->sc_tx_statuslen); 681 device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n", 682 sc->sc_tx_nmaps); 683 684 sc->sc_tx.xmit_setup = ath_edma_dma_txsetup; 685 sc->sc_tx.xmit_teardown = ath_edma_dma_txteardown; 686 sc->sc_tx.xmit_attach_comp_func = ath_edma_attach_comp_func; 687 688 sc->sc_tx.xmit_dma_restart = ath_edma_dma_restart; 689 sc->sc_tx.xmit_handoff = ath_edma_xmit_handoff; 690 sc->sc_tx.xmit_drain = ath_edma_tx_drain; 691 } 692