1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 #include "opt_wlan.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/sysctl.h> 47 #include <sys/mbuf.h> 48 #include <sys/malloc.h> 49 #include <sys/lock.h> 50 #include <sys/mutex.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/errno.h> 55 #include <sys/callout.h> 56 #include <sys/bus.h> 57 #include <sys/endian.h> 58 #include <sys/kthread.h> 59 #include <sys/taskqueue.h> 60 #include <sys/priv.h> 61 62 #include <machine/bus.h> 63 64 #include <net/if.h> 65 #include <net/if_dl.h> 66 #include <net/if_media.h> 67 #include <net/if_types.h> 68 #include <net/if_arp.h> 69 #include <net/ethernet.h> 70 #include <net/if_llc.h> 71 72 #include <net80211/ieee80211_var.h> 73 #include <net80211/ieee80211_regdomain.h> 74 #ifdef IEEE80211_SUPPORT_SUPERG 75 #include <net80211/ieee80211_superg.h> 76 #endif 77 #ifdef IEEE80211_SUPPORT_TDMA 78 #include <net80211/ieee80211_tdma.h> 79 #endif 80 #include <net80211/ieee80211_ht.h> 81 82 #include <net/bpf.h> 83 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/if_ether.h> 87 #endif 88 89 #include <dev/ath/if_athvar.h> 90 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 91 #include <dev/ath/ath_hal/ah_diagcodes.h> 92 93 #include <dev/ath/if_ath_debug.h> 94 95 #ifdef ATH_TX99_DIAG 96 #include <dev/ath/ath_tx99/ath_tx99.h> 97 #endif 98 99 #include <dev/ath/if_ath_misc.h> 100 #include <dev/ath/if_ath_tx.h> 101 #include <dev/ath/if_ath_tx_ht.h> 102 103 /* 104 * How many retries to perform in software 105 */ 106 #define SWMAX_RETRIES 10 107 108 static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, 109 int tid); 110 static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, 111 int tid); 112 static ieee80211_seq ath_tx_tid_seqno_assign(struct ath_softc *sc, 113 struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0); 114 static int ath_tx_action_frame_override_queue(struct ath_softc *sc, 115 struct ieee80211_node *ni, struct mbuf *m0, int *tid); 116 117 /* 118 * Whether to use the 11n rate scenario functions or not 119 */ 120 static inline int 121 ath_tx_is_11n(struct ath_softc *sc) 122 { 123 return ((sc->sc_ah->ah_magic == 0x20065416) || 124 (sc->sc_ah->ah_magic == 0x19741014)); 125 } 126 127 /* 128 * Obtain the current TID from the given frame. 129 * 130 * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.) 131 * This has implications for which AC/priority the packet is placed 132 * in. 133 */ 134 static int 135 ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0) 136 { 137 const struct ieee80211_frame *wh; 138 int pri = M_WME_GETAC(m0); 139 140 wh = mtod(m0, const struct ieee80211_frame *); 141 if (! IEEE80211_QOS_HAS_SEQ(wh)) 142 return IEEE80211_NONQOS_TID; 143 else 144 return WME_AC_TO_TID(pri); 145 } 146 147 /* 148 * Determine what the correct AC queue for the given frame 149 * should be. 150 * 151 * This code assumes that the TIDs map consistently to 152 * the underlying hardware (or software) ath_txq. 153 * Since the sender may try to set an AC which is 154 * arbitrary, non-QoS TIDs may end up being put on 155 * completely different ACs. There's no way to put a 156 * TID into multiple ath_txq's for scheduling, so 157 * for now we override the AC/TXQ selection and set 158 * non-QOS TID frames into the BE queue. 159 * 160 * This may be completely incorrect - specifically, 161 * some management frames may end up out of order 162 * compared to the QoS traffic they're controlling. 163 * I'll look into this later. 164 */ 165 static int 166 ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0) 167 { 168 const struct ieee80211_frame *wh; 169 int pri = M_WME_GETAC(m0); 170 wh = mtod(m0, const struct ieee80211_frame *); 171 if (IEEE80211_QOS_HAS_SEQ(wh)) 172 return pri; 173 174 return WME_AC_BE; 175 } 176 177 void 178 ath_txfrag_cleanup(struct ath_softc *sc, 179 ath_bufhead *frags, struct ieee80211_node *ni) 180 { 181 struct ath_buf *bf, *next; 182 183 ATH_TXBUF_LOCK_ASSERT(sc); 184 185 TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 186 /* NB: bf assumed clean */ 187 TAILQ_REMOVE(frags, bf, bf_list); 188 ath_returnbuf_head(sc, bf); 189 ieee80211_node_decref(ni); 190 } 191 } 192 193 /* 194 * Setup xmit of a fragmented frame. Allocate a buffer 195 * for each frag and bump the node reference count to 196 * reflect the held reference to be setup by ath_tx_start. 197 */ 198 int 199 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 200 struct mbuf *m0, struct ieee80211_node *ni) 201 { 202 struct mbuf *m; 203 struct ath_buf *bf; 204 205 ATH_TXBUF_LOCK(sc); 206 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 207 /* XXX non-management? */ 208 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 209 if (bf == NULL) { /* out of buffers, cleanup */ 210 device_printf(sc->sc_dev, "%s: no buffer?\n", 211 __func__); 212 ath_txfrag_cleanup(sc, frags, ni); 213 break; 214 } 215 ieee80211_node_incref(ni); 216 TAILQ_INSERT_TAIL(frags, bf, bf_list); 217 } 218 ATH_TXBUF_UNLOCK(sc); 219 220 return !TAILQ_EMPTY(frags); 221 } 222 223 /* 224 * Reclaim mbuf resources. For fragmented frames we 225 * need to claim each frag chained with m_nextpkt. 226 */ 227 void 228 ath_freetx(struct mbuf *m) 229 { 230 struct mbuf *next; 231 232 do { 233 next = m->m_nextpkt; 234 m->m_nextpkt = NULL; 235 m_freem(m); 236 } while ((m = next) != NULL); 237 } 238 239 static int 240 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 241 { 242 struct mbuf *m; 243 int error; 244 245 /* 246 * Load the DMA map so any coalescing is done. This 247 * also calculates the number of descriptors we need. 248 */ 249 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 250 bf->bf_segs, &bf->bf_nseg, 251 BUS_DMA_NOWAIT); 252 if (error == EFBIG) { 253 /* XXX packet requires too many descriptors */ 254 bf->bf_nseg = ATH_TXDESC+1; 255 } else if (error != 0) { 256 sc->sc_stats.ast_tx_busdma++; 257 ath_freetx(m0); 258 return error; 259 } 260 /* 261 * Discard null packets and check for packets that 262 * require too many TX descriptors. We try to convert 263 * the latter to a cluster. 264 */ 265 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 266 sc->sc_stats.ast_tx_linear++; 267 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); 268 if (m == NULL) { 269 ath_freetx(m0); 270 sc->sc_stats.ast_tx_nombuf++; 271 return ENOMEM; 272 } 273 m0 = m; 274 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 275 bf->bf_segs, &bf->bf_nseg, 276 BUS_DMA_NOWAIT); 277 if (error != 0) { 278 sc->sc_stats.ast_tx_busdma++; 279 ath_freetx(m0); 280 return error; 281 } 282 KASSERT(bf->bf_nseg <= ATH_TXDESC, 283 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 284 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 285 sc->sc_stats.ast_tx_nodata++; 286 ath_freetx(m0); 287 return EIO; 288 } 289 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 290 __func__, m0, m0->m_pkthdr.len); 291 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 292 bf->bf_m = m0; 293 294 return 0; 295 } 296 297 /* 298 * Chain together segments+descriptors for a non-11n frame. 299 */ 300 static void 301 ath_tx_chaindesclist(struct ath_softc *sc, struct ath_buf *bf) 302 { 303 struct ath_hal *ah = sc->sc_ah; 304 char *ds, *ds0; 305 int i, bp, dsp; 306 HAL_DMA_ADDR bufAddrList[4]; 307 uint32_t segLenList[4]; 308 int numTxMaps = 1; 309 int isFirstDesc = 1; 310 int qnum; 311 312 /* 313 * XXX There's txdma and txdma_mgmt; the descriptor 314 * sizes must match. 315 */ 316 struct ath_descdma *dd = &sc->sc_txdma; 317 318 /* 319 * Fillin the remainder of the descriptor info. 320 */ 321 322 /* 323 * For now the HAL doesn't implement halNumTxMaps for non-EDMA 324 * (ie it's 0.) So just work around it. 325 * 326 * XXX TODO: populate halNumTxMaps for each HAL chip and 327 * then undo this hack. 328 */ 329 if (sc->sc_ah->ah_magic == 0x19741014) 330 numTxMaps = 4; 331 332 /* 333 * For EDMA and later chips ensure the TX map is fully populated 334 * before advancing to the next descriptor. 335 */ 336 ds0 = ds = (char *) bf->bf_desc; 337 bp = dsp = 0; 338 bzero(bufAddrList, sizeof(bufAddrList)); 339 bzero(segLenList, sizeof(segLenList)); 340 for (i = 0; i < bf->bf_nseg; i++) { 341 bufAddrList[bp] = bf->bf_segs[i].ds_addr; 342 segLenList[bp] = bf->bf_segs[i].ds_len; 343 bp++; 344 345 /* 346 * Go to the next segment if this isn't the last segment 347 * and there's space in the current TX map. 348 */ 349 if ((i != bf->bf_nseg - 1) && (bp < numTxMaps)) 350 continue; 351 352 /* 353 * Last segment or we're out of buffer pointers. 354 */ 355 bp = 0; 356 357 if (i == bf->bf_nseg - 1) 358 ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 0); 359 else 360 ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 361 bf->bf_daddr + dd->dd_descsize * (dsp + 1)); 362 363 /* 364 * XXX this assumes that bfs_txq is the actual destination 365 * hardware queue at this point. It may not have been assigned, 366 * it may actually be pointing to the multicast software 367 * TXQ id. These must be fixed! 368 */ 369 qnum = bf->bf_state.bfs_txq->axq_qnum; 370 371 ath_hal_filltxdesc(ah, (struct ath_desc *) ds 372 , bufAddrList 373 , segLenList 374 , bf->bf_descid /* XXX desc id */ 375 , qnum 376 , isFirstDesc /* first segment */ 377 , i == bf->bf_nseg - 1 /* last segment */ 378 , (struct ath_desc *) ds0 /* first descriptor */ 379 ); 380 isFirstDesc = 0; 381 #ifdef ATH_DEBUG 382 if (sc->sc_debug & ATH_DEBUG_XMIT) 383 ath_printtxbuf(sc, bf, qnum, 0, 0); 384 #endif 385 bf->bf_lastds = (struct ath_desc *) ds; 386 387 /* 388 * Don't forget to skip to the next descriptor. 389 */ 390 ds += sc->sc_tx_desclen; 391 dsp++; 392 393 /* 394 * .. and don't forget to blank these out! 395 */ 396 bzero(bufAddrList, sizeof(bufAddrList)); 397 bzero(segLenList, sizeof(segLenList)); 398 } 399 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 400 } 401 402 /* 403 * Fill in the descriptor list for a aggregate subframe. 404 * 405 * The subframe is returned with the ds_link field in the last subframe 406 * pointing to 0. 407 */ 408 static void 409 ath_tx_chaindesclist_subframe(struct ath_softc *sc, struct ath_buf *bf) 410 { 411 struct ath_hal *ah = sc->sc_ah; 412 struct ath_desc *ds, *ds0; 413 int i; 414 HAL_DMA_ADDR bufAddrList[4]; 415 uint32_t segLenList[4]; 416 417 /* 418 * XXX There's txdma and txdma_mgmt; the descriptor 419 * sizes must match. 420 */ 421 struct ath_descdma *dd = &sc->sc_txdma; 422 423 ds0 = ds = bf->bf_desc; 424 425 /* 426 * There's no need to call ath_hal_setupfirsttxdesc here; 427 * That's only going to occur for the first frame in an aggregate. 428 */ 429 for (i = 0; i < bf->bf_nseg; i++, ds++) { 430 bzero(bufAddrList, sizeof(bufAddrList)); 431 bzero(segLenList, sizeof(segLenList)); 432 if (i == bf->bf_nseg - 1) 433 ath_hal_settxdesclink(ah, ds, 0); 434 else 435 ath_hal_settxdesclink(ah, ds, 436 bf->bf_daddr + dd->dd_descsize * (i + 1)); 437 438 bufAddrList[0] = bf->bf_segs[i].ds_addr; 439 segLenList[0] = bf->bf_segs[i].ds_len; 440 441 /* 442 * This performs the setup for an aggregate frame. 443 * This includes enabling the aggregate flags if needed. 444 */ 445 ath_hal_chaintxdesc(ah, ds, 446 bufAddrList, 447 segLenList, 448 bf->bf_state.bfs_pktlen, 449 bf->bf_state.bfs_hdrlen, 450 HAL_PKT_TYPE_AMPDU, /* forces aggregate bits to be set */ 451 bf->bf_state.bfs_keyix, 452 0, /* cipher, calculated from keyix */ 453 bf->bf_state.bfs_ndelim, 454 i == 0, /* first segment */ 455 i == bf->bf_nseg - 1, /* last segment */ 456 bf->bf_next == NULL /* last sub-frame in aggr */ 457 ); 458 459 DPRINTF(sc, ATH_DEBUG_XMIT, 460 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 461 __func__, i, ds->ds_link, ds->ds_data, 462 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 463 bf->bf_lastds = ds; 464 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 465 BUS_DMASYNC_PREWRITE); 466 } 467 } 468 469 /* 470 * Set the rate control fields in the given descriptor based on 471 * the bf_state fields and node state. 472 * 473 * The bfs fields should already be set with the relevant rate 474 * control information, including whether MRR is to be enabled. 475 * 476 * Since the FreeBSD HAL currently sets up the first TX rate 477 * in ath_hal_setuptxdesc(), this will setup the MRR 478 * conditionally for the pre-11n chips, and call ath_buf_set_rate 479 * unconditionally for 11n chips. These require the 11n rate 480 * scenario to be set if MCS rates are enabled, so it's easier 481 * to just always call it. The caller can then only set rates 2, 3 482 * and 4 if multi-rate retry is needed. 483 */ 484 static void 485 ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 486 struct ath_buf *bf) 487 { 488 struct ath_rc_series *rc = bf->bf_state.bfs_rc; 489 490 /* If mrr is disabled, blank tries 1, 2, 3 */ 491 if (! bf->bf_state.bfs_ismrr) 492 rc[1].tries = rc[2].tries = rc[3].tries = 0; 493 494 /* 495 * Always call - that way a retried descriptor will 496 * have the MRR fields overwritten. 497 * 498 * XXX TODO: see if this is really needed - setting up 499 * the first descriptor should set the MRR fields to 0 500 * for us anyway. 501 */ 502 if (ath_tx_is_11n(sc)) { 503 ath_buf_set_rate(sc, ni, bf); 504 } else { 505 ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc 506 , rc[1].ratecode, rc[1].tries 507 , rc[2].ratecode, rc[2].tries 508 , rc[3].ratecode, rc[3].tries 509 ); 510 } 511 } 512 513 /* 514 * Setup segments+descriptors for an 11n aggregate. 515 * bf_first is the first buffer in the aggregate. 516 * The descriptor list must already been linked together using 517 * bf->bf_next. 518 */ 519 static void 520 ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first) 521 { 522 struct ath_buf *bf, *bf_prev = NULL; 523 524 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n", 525 __func__, bf_first->bf_state.bfs_nframes, 526 bf_first->bf_state.bfs_al); 527 528 /* 529 * Setup all descriptors of all subframes. 530 */ 531 bf = bf_first; 532 while (bf != NULL) { 533 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 534 "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n", 535 __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen, 536 SEQNO(bf->bf_state.bfs_seqno)); 537 538 /* Sub-frame setup */ 539 ath_tx_chaindesclist_subframe(sc, bf); 540 541 /* 542 * Link the last descriptor of the previous frame 543 * to the beginning descriptor of this frame. 544 */ 545 if (bf_prev != NULL) 546 ath_hal_settxdesclink(sc->sc_ah, bf_prev->bf_lastds, 547 bf->bf_daddr); 548 549 /* Save a copy so we can link the next descriptor in */ 550 bf_prev = bf; 551 bf = bf->bf_next; 552 } 553 554 /* 555 * Setup first descriptor of first frame. 556 * chaintxdesc() overwrites the descriptor entries; 557 * setupfirsttxdesc() merges in things. 558 * Otherwise various fields aren't set correctly (eg flags). 559 */ 560 ath_hal_setupfirsttxdesc(sc->sc_ah, 561 bf_first->bf_desc, 562 bf_first->bf_state.bfs_al, 563 bf_first->bf_state.bfs_txflags | HAL_TXDESC_INTREQ, 564 bf_first->bf_state.bfs_txpower, 565 bf_first->bf_state.bfs_txrate0, 566 bf_first->bf_state.bfs_try0, 567 bf_first->bf_state.bfs_txantenna, 568 bf_first->bf_state.bfs_ctsrate, 569 bf_first->bf_state.bfs_ctsduration); 570 571 /* 572 * Set the first descriptor bf_lastds field to point to 573 * the last descriptor in the last subframe, that's where 574 * the status update will occur. 575 */ 576 bf_first->bf_lastds = bf_prev->bf_lastds; 577 578 /* 579 * And bf_last in the first descriptor points to the end of 580 * the aggregate list. 581 */ 582 bf_first->bf_last = bf_prev; 583 584 /* 585 * setup first desc with rate and aggr info 586 */ 587 ath_tx_set_ratectrl(sc, bf_first->bf_node, bf_first); 588 589 /* 590 * Setup the last descriptor in the list. 591 * 592 * bf_first->bf_lastds already points to it; the rate 593 * control information needs to be squirreled away here 594 * as well ans clearing the moreaggr/paddelim fields. 595 */ 596 ath_hal_setuplasttxdesc(sc->sc_ah, bf_first->bf_lastds, 597 bf_first->bf_desc); 598 599 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__); 600 } 601 602 /* 603 * Hand-off a frame to the multicast TX queue. 604 * 605 * This is a software TXQ which will be appended to the CAB queue 606 * during the beacon setup code. 607 * 608 * XXX TODO: since the AR9300 EDMA TX queue support wants the QCU ID 609 * as part of the TX descriptor, bf_state.bfs_txq must be updated 610 * with the actual hardware txq, or all of this will fall apart. 611 * 612 * XXX It may not be a bad idea to just stuff the QCU ID into bf_state 613 * and retire bfs_txq; then make sure the CABQ QCU ID is populated 614 * correctly. 615 */ 616 static void 617 ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 618 struct ath_buf *bf) 619 { 620 ATH_TXQ_LOCK_ASSERT(txq); 621 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 622 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 623 if (txq->axq_link != NULL) { 624 struct ath_buf *last = ATH_TXQ_LAST(txq, axq_q_s); 625 struct ieee80211_frame *wh; 626 627 /* mark previous frame */ 628 wh = mtod(last->bf_m, struct ieee80211_frame *); 629 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 630 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 631 BUS_DMASYNC_PREWRITE); 632 633 /* link descriptor */ 634 *txq->axq_link = bf->bf_daddr; 635 } 636 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 637 ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link); 638 } 639 640 /* 641 * Hand-off packet to a hardware queue. 642 */ 643 static void 644 ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 645 struct ath_buf *bf) 646 { 647 struct ath_hal *ah = sc->sc_ah; 648 649 /* 650 * Insert the frame on the outbound list and pass it on 651 * to the hardware. Multicast frames buffered for power 652 * save stations and transmit from the CAB queue are stored 653 * on a s/w only queue and loaded on to the CAB queue in 654 * the SWBA handler since frames only go out on DTIM and 655 * to avoid possible races. 656 */ 657 ATH_TXQ_LOCK_ASSERT(txq); 658 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 659 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 660 KASSERT(txq->axq_qnum != ATH_TXQ_SWQ, 661 ("ath_tx_handoff_hw called for mcast queue")); 662 663 #if 0 664 /* 665 * This causes a LOR. Find out where the PCU lock is being 666 * held whilst the TXQ lock is grabbed - that shouldn't 667 * be occuring. 668 */ 669 ATH_PCU_LOCK(sc); 670 if (sc->sc_inreset_cnt) { 671 ATH_PCU_UNLOCK(sc); 672 DPRINTF(sc, ATH_DEBUG_RESET, 673 "%s: called with sc_in_reset != 0\n", 674 __func__); 675 DPRINTF(sc, ATH_DEBUG_XMIT, 676 "%s: queued: TXDP[%u] = %p (%p) depth %d\n", 677 __func__, txq->axq_qnum, 678 (caddr_t)bf->bf_daddr, bf->bf_desc, 679 txq->axq_depth); 680 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 681 if (bf->bf_state.bfs_aggr) 682 txq->axq_aggr_depth++; 683 /* 684 * There's no need to update axq_link; the hardware 685 * is in reset and once the reset is complete, any 686 * non-empty queues will simply have DMA restarted. 687 */ 688 return; 689 } 690 ATH_PCU_UNLOCK(sc); 691 #endif 692 693 /* For now, so not to generate whitespace diffs */ 694 if (1) { 695 #ifdef IEEE80211_SUPPORT_TDMA 696 int qbusy; 697 698 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 699 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 700 if (txq->axq_link == NULL) { 701 /* 702 * Be careful writing the address to TXDP. If 703 * the tx q is enabled then this write will be 704 * ignored. Normally this is not an issue but 705 * when tdma is in use and the q is beacon gated 706 * this race can occur. If the q is busy then 707 * defer the work to later--either when another 708 * packet comes along or when we prepare a beacon 709 * frame at SWBA. 710 */ 711 if (!qbusy) { 712 ath_hal_puttxbuf(ah, txq->axq_qnum, 713 bf->bf_daddr); 714 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 715 DPRINTF(sc, ATH_DEBUG_XMIT, 716 "%s: TXDP[%u] = %p (%p) depth %d\n", 717 __func__, txq->axq_qnum, 718 (caddr_t)bf->bf_daddr, bf->bf_desc, 719 txq->axq_depth); 720 } else { 721 txq->axq_flags |= ATH_TXQ_PUTPENDING; 722 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 723 "%s: Q%u busy, defer enable\n", __func__, 724 txq->axq_qnum); 725 } 726 } else { 727 *txq->axq_link = bf->bf_daddr; 728 DPRINTF(sc, ATH_DEBUG_XMIT, 729 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 730 txq->axq_qnum, txq->axq_link, 731 (caddr_t)bf->bf_daddr, bf->bf_desc, 732 txq->axq_depth); 733 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) { 734 /* 735 * The q was busy when we previously tried 736 * to write the address of the first buffer 737 * in the chain. Since it's not busy now 738 * handle this chore. We are certain the 739 * buffer at the front is the right one since 740 * axq_link is NULL only when the buffer list 741 * is/was empty. 742 */ 743 ath_hal_puttxbuf(ah, txq->axq_qnum, 744 TAILQ_FIRST(&txq->axq_q)->bf_daddr); 745 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 746 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 747 "%s: Q%u restarted\n", __func__, 748 txq->axq_qnum); 749 } 750 } 751 #else 752 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 753 if (txq->axq_link == NULL) { 754 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 755 DPRINTF(sc, ATH_DEBUG_XMIT, 756 "%s: TXDP[%u] = %p (%p) depth %d\n", 757 __func__, txq->axq_qnum, 758 (caddr_t)bf->bf_daddr, bf->bf_desc, 759 txq->axq_depth); 760 } else { 761 *txq->axq_link = bf->bf_daddr; 762 DPRINTF(sc, ATH_DEBUG_XMIT, 763 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 764 txq->axq_qnum, txq->axq_link, 765 (caddr_t)bf->bf_daddr, bf->bf_desc, 766 txq->axq_depth); 767 } 768 #endif /* IEEE80211_SUPPORT_TDMA */ 769 if (bf->bf_state.bfs_aggr) 770 txq->axq_aggr_depth++; 771 ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link); 772 ath_hal_txstart(ah, txq->axq_qnum); 773 } 774 } 775 776 /* 777 * Restart TX DMA for the given TXQ. 778 * 779 * This must be called whether the queue is empty or not. 780 */ 781 static void 782 ath_legacy_tx_dma_restart(struct ath_softc *sc, struct ath_txq *txq) 783 { 784 struct ath_hal *ah = sc->sc_ah; 785 struct ath_buf *bf, *bf_last; 786 787 ATH_TXQ_LOCK_ASSERT(txq); 788 789 /* This is always going to be cleared, empty or not */ 790 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 791 792 /* XXX make this ATH_TXQ_FIRST */ 793 bf = TAILQ_FIRST(&txq->axq_q); 794 bf_last = ATH_TXQ_LAST(txq, axq_q_s); 795 796 if (bf == NULL) 797 return; 798 799 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 800 ath_hal_gettxdesclinkptr(ah, bf_last->bf_lastds, &txq->axq_link); 801 ath_hal_txstart(ah, txq->axq_qnum); 802 } 803 804 /* 805 * Hand off a packet to the hardware (or mcast queue.) 806 * 807 * The relevant hardware txq should be locked. 808 */ 809 static void 810 ath_legacy_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq, 811 struct ath_buf *bf) 812 { 813 ATH_TXQ_LOCK_ASSERT(txq); 814 815 if (txq->axq_qnum == ATH_TXQ_SWQ) 816 ath_tx_handoff_mcast(sc, txq, bf); 817 else 818 ath_tx_handoff_hw(sc, txq, bf); 819 } 820 821 static int 822 ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni, 823 struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen, 824 int *keyix) 825 { 826 DPRINTF(sc, ATH_DEBUG_XMIT, 827 "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n", 828 __func__, 829 *hdrlen, 830 *pktlen, 831 isfrag, 832 iswep, 833 m0); 834 835 if (iswep) { 836 const struct ieee80211_cipher *cip; 837 struct ieee80211_key *k; 838 839 /* 840 * Construct the 802.11 header+trailer for an encrypted 841 * frame. The only reason this can fail is because of an 842 * unknown or unsupported cipher/key type. 843 */ 844 k = ieee80211_crypto_encap(ni, m0); 845 if (k == NULL) { 846 /* 847 * This can happen when the key is yanked after the 848 * frame was queued. Just discard the frame; the 849 * 802.11 layer counts failures and provides 850 * debugging/diagnostics. 851 */ 852 return (0); 853 } 854 /* 855 * Adjust the packet + header lengths for the crypto 856 * additions and calculate the h/w key index. When 857 * a s/w mic is done the frame will have had any mic 858 * added to it prior to entry so m0->m_pkthdr.len will 859 * account for it. Otherwise we need to add it to the 860 * packet length. 861 */ 862 cip = k->wk_cipher; 863 (*hdrlen) += cip->ic_header; 864 (*pktlen) += cip->ic_header + cip->ic_trailer; 865 /* NB: frags always have any TKIP MIC done in s/w */ 866 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 867 (*pktlen) += cip->ic_miclen; 868 (*keyix) = k->wk_keyix; 869 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 870 /* 871 * Use station key cache slot, if assigned. 872 */ 873 (*keyix) = ni->ni_ucastkey.wk_keyix; 874 if ((*keyix) == IEEE80211_KEYIX_NONE) 875 (*keyix) = HAL_TXKEYIX_INVALID; 876 } else 877 (*keyix) = HAL_TXKEYIX_INVALID; 878 879 return (1); 880 } 881 882 /* 883 * Calculate whether interoperability protection is required for 884 * this frame. 885 * 886 * This requires the rate control information be filled in, 887 * as the protection requirement depends upon the current 888 * operating mode / PHY. 889 */ 890 static void 891 ath_tx_calc_protection(struct ath_softc *sc, struct ath_buf *bf) 892 { 893 struct ieee80211_frame *wh; 894 uint8_t rix; 895 uint16_t flags; 896 int shortPreamble; 897 const HAL_RATE_TABLE *rt = sc->sc_currates; 898 struct ifnet *ifp = sc->sc_ifp; 899 struct ieee80211com *ic = ifp->if_l2com; 900 901 flags = bf->bf_state.bfs_txflags; 902 rix = bf->bf_state.bfs_rc[0].rix; 903 shortPreamble = bf->bf_state.bfs_shpream; 904 wh = mtod(bf->bf_m, struct ieee80211_frame *); 905 906 /* 907 * If 802.11g protection is enabled, determine whether 908 * to use RTS/CTS or just CTS. Note that this is only 909 * done for OFDM unicast frames. 910 */ 911 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 912 rt->info[rix].phy == IEEE80211_T_OFDM && 913 (flags & HAL_TXDESC_NOACK) == 0) { 914 bf->bf_state.bfs_doprot = 1; 915 /* XXX fragments must use CCK rates w/ protection */ 916 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 917 flags |= HAL_TXDESC_RTSENA; 918 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 919 flags |= HAL_TXDESC_CTSENA; 920 } 921 /* 922 * For frags it would be desirable to use the 923 * highest CCK rate for RTS/CTS. But stations 924 * farther away may detect it at a lower CCK rate 925 * so use the configured protection rate instead 926 * (for now). 927 */ 928 sc->sc_stats.ast_tx_protect++; 929 } 930 931 /* 932 * If 11n protection is enabled and it's a HT frame, 933 * enable RTS. 934 * 935 * XXX ic_htprotmode or ic_curhtprotmode? 936 * XXX should it_htprotmode only matter if ic_curhtprotmode 937 * XXX indicates it's not a HT pure environment? 938 */ 939 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) && 940 rt->info[rix].phy == IEEE80211_T_HT && 941 (flags & HAL_TXDESC_NOACK) == 0) { 942 flags |= HAL_TXDESC_RTSENA; 943 sc->sc_stats.ast_tx_htprotect++; 944 } 945 bf->bf_state.bfs_txflags = flags; 946 } 947 948 /* 949 * Update the frame duration given the currently selected rate. 950 * 951 * This also updates the frame duration value, so it will require 952 * a DMA flush. 953 */ 954 static void 955 ath_tx_calc_duration(struct ath_softc *sc, struct ath_buf *bf) 956 { 957 struct ieee80211_frame *wh; 958 uint8_t rix; 959 uint16_t flags; 960 int shortPreamble; 961 struct ath_hal *ah = sc->sc_ah; 962 const HAL_RATE_TABLE *rt = sc->sc_currates; 963 int isfrag = bf->bf_m->m_flags & M_FRAG; 964 965 flags = bf->bf_state.bfs_txflags; 966 rix = bf->bf_state.bfs_rc[0].rix; 967 shortPreamble = bf->bf_state.bfs_shpream; 968 wh = mtod(bf->bf_m, struct ieee80211_frame *); 969 970 /* 971 * Calculate duration. This logically belongs in the 802.11 972 * layer but it lacks sufficient information to calculate it. 973 */ 974 if ((flags & HAL_TXDESC_NOACK) == 0 && 975 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 976 u_int16_t dur; 977 if (shortPreamble) 978 dur = rt->info[rix].spAckDuration; 979 else 980 dur = rt->info[rix].lpAckDuration; 981 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 982 dur += dur; /* additional SIFS+ACK */ 983 KASSERT(bf->bf_m->m_nextpkt != NULL, ("no fragment")); 984 /* 985 * Include the size of next fragment so NAV is 986 * updated properly. The last fragment uses only 987 * the ACK duration 988 */ 989 dur += ath_hal_computetxtime(ah, rt, 990 bf->bf_m->m_nextpkt->m_pkthdr.len, 991 rix, shortPreamble); 992 } 993 if (isfrag) { 994 /* 995 * Force hardware to use computed duration for next 996 * fragment by disabling multi-rate retry which updates 997 * duration based on the multi-rate duration table. 998 */ 999 bf->bf_state.bfs_ismrr = 0; 1000 bf->bf_state.bfs_try0 = ATH_TXMGTTRY; 1001 /* XXX update bfs_rc[0].try? */ 1002 } 1003 1004 /* Update the duration field itself */ 1005 *(u_int16_t *)wh->i_dur = htole16(dur); 1006 } 1007 } 1008 1009 static uint8_t 1010 ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt, 1011 int cix, int shortPreamble) 1012 { 1013 uint8_t ctsrate; 1014 1015 /* 1016 * CTS transmit rate is derived from the transmit rate 1017 * by looking in the h/w rate table. We must also factor 1018 * in whether or not a short preamble is to be used. 1019 */ 1020 /* NB: cix is set above where RTS/CTS is enabled */ 1021 KASSERT(cix != 0xff, ("cix not setup")); 1022 ctsrate = rt->info[cix].rateCode; 1023 1024 /* XXX this should only matter for legacy rates */ 1025 if (shortPreamble) 1026 ctsrate |= rt->info[cix].shortPreamble; 1027 1028 return (ctsrate); 1029 } 1030 1031 /* 1032 * Calculate the RTS/CTS duration for legacy frames. 1033 */ 1034 static int 1035 ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix, 1036 int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt, 1037 int flags) 1038 { 1039 int ctsduration = 0; 1040 1041 /* This mustn't be called for HT modes */ 1042 if (rt->info[cix].phy == IEEE80211_T_HT) { 1043 printf("%s: HT rate where it shouldn't be (0x%x)\n", 1044 __func__, rt->info[cix].rateCode); 1045 return (-1); 1046 } 1047 1048 /* 1049 * Compute the transmit duration based on the frame 1050 * size and the size of an ACK frame. We call into the 1051 * HAL to do the computation since it depends on the 1052 * characteristics of the actual PHY being used. 1053 * 1054 * NB: CTS is assumed the same size as an ACK so we can 1055 * use the precalculated ACK durations. 1056 */ 1057 if (shortPreamble) { 1058 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1059 ctsduration += rt->info[cix].spAckDuration; 1060 ctsduration += ath_hal_computetxtime(ah, 1061 rt, pktlen, rix, AH_TRUE); 1062 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1063 ctsduration += rt->info[rix].spAckDuration; 1064 } else { 1065 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1066 ctsduration += rt->info[cix].lpAckDuration; 1067 ctsduration += ath_hal_computetxtime(ah, 1068 rt, pktlen, rix, AH_FALSE); 1069 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1070 ctsduration += rt->info[rix].lpAckDuration; 1071 } 1072 1073 return (ctsduration); 1074 } 1075 1076 /* 1077 * Update the given ath_buf with updated rts/cts setup and duration 1078 * values. 1079 * 1080 * To support rate lookups for each software retry, the rts/cts rate 1081 * and cts duration must be re-calculated. 1082 * 1083 * This function assumes the RTS/CTS flags have been set as needed; 1084 * mrr has been disabled; and the rate control lookup has been done. 1085 * 1086 * XXX TODO: MRR need only be disabled for the pre-11n NICs. 1087 * XXX The 11n NICs support per-rate RTS/CTS configuration. 1088 */ 1089 static void 1090 ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf) 1091 { 1092 uint16_t ctsduration = 0; 1093 uint8_t ctsrate = 0; 1094 uint8_t rix = bf->bf_state.bfs_rc[0].rix; 1095 uint8_t cix = 0; 1096 const HAL_RATE_TABLE *rt = sc->sc_currates; 1097 1098 /* 1099 * No RTS/CTS enabled? Don't bother. 1100 */ 1101 if ((bf->bf_state.bfs_txflags & 1102 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) { 1103 /* XXX is this really needed? */ 1104 bf->bf_state.bfs_ctsrate = 0; 1105 bf->bf_state.bfs_ctsduration = 0; 1106 return; 1107 } 1108 1109 /* 1110 * If protection is enabled, use the protection rix control 1111 * rate. Otherwise use the rate0 control rate. 1112 */ 1113 if (bf->bf_state.bfs_doprot) 1114 rix = sc->sc_protrix; 1115 else 1116 rix = bf->bf_state.bfs_rc[0].rix; 1117 1118 /* 1119 * If the raw path has hard-coded ctsrate0 to something, 1120 * use it. 1121 */ 1122 if (bf->bf_state.bfs_ctsrate0 != 0) 1123 cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0); 1124 else 1125 /* Control rate from above */ 1126 cix = rt->info[rix].controlRate; 1127 1128 /* Calculate the rtscts rate for the given cix */ 1129 ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix, 1130 bf->bf_state.bfs_shpream); 1131 1132 /* The 11n chipsets do ctsduration calculations for you */ 1133 if (! ath_tx_is_11n(sc)) 1134 ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix, 1135 bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen, 1136 rt, bf->bf_state.bfs_txflags); 1137 1138 /* Squirrel away in ath_buf */ 1139 bf->bf_state.bfs_ctsrate = ctsrate; 1140 bf->bf_state.bfs_ctsduration = ctsduration; 1141 1142 /* 1143 * Must disable multi-rate retry when using RTS/CTS. 1144 */ 1145 if (!sc->sc_mrrprot) { 1146 bf->bf_state.bfs_ismrr = 0; 1147 bf->bf_state.bfs_try0 = 1148 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */ 1149 } 1150 } 1151 1152 /* 1153 * Setup the descriptor chain for a normal or fast-frame 1154 * frame. 1155 * 1156 * XXX TODO: extend to include the destination hardware QCU ID. 1157 * Make sure that is correct. Make sure that when being added 1158 * to the mcastq, the CABQ QCUID is set or things will get a bit 1159 * odd. 1160 */ 1161 static void 1162 ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf) 1163 { 1164 struct ath_desc *ds = bf->bf_desc; 1165 struct ath_hal *ah = sc->sc_ah; 1166 1167 ath_hal_setuptxdesc(ah, ds 1168 , bf->bf_state.bfs_pktlen /* packet length */ 1169 , bf->bf_state.bfs_hdrlen /* header length */ 1170 , bf->bf_state.bfs_atype /* Atheros packet type */ 1171 , bf->bf_state.bfs_txpower /* txpower */ 1172 , bf->bf_state.bfs_txrate0 1173 , bf->bf_state.bfs_try0 /* series 0 rate/tries */ 1174 , bf->bf_state.bfs_keyix /* key cache index */ 1175 , bf->bf_state.bfs_txantenna /* antenna mode */ 1176 , bf->bf_state.bfs_txflags /* flags */ 1177 , bf->bf_state.bfs_ctsrate /* rts/cts rate */ 1178 , bf->bf_state.bfs_ctsduration /* rts/cts duration */ 1179 ); 1180 1181 /* 1182 * This will be overriden when the descriptor chain is written. 1183 */ 1184 bf->bf_lastds = ds; 1185 bf->bf_last = bf; 1186 1187 /* Set rate control and descriptor chain for this frame */ 1188 ath_tx_set_ratectrl(sc, bf->bf_node, bf); 1189 ath_tx_chaindesclist(sc, bf); 1190 } 1191 1192 /* 1193 * Do a rate lookup. 1194 * 1195 * This performs a rate lookup for the given ath_buf only if it's required. 1196 * Non-data frames and raw frames don't require it. 1197 * 1198 * This populates the primary and MRR entries; MRR values are 1199 * then disabled later on if something requires it (eg RTS/CTS on 1200 * pre-11n chipsets. 1201 * 1202 * This needs to be done before the RTS/CTS fields are calculated 1203 * as they may depend upon the rate chosen. 1204 */ 1205 static void 1206 ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf) 1207 { 1208 uint8_t rate, rix; 1209 int try0; 1210 1211 if (! bf->bf_state.bfs_doratelookup) 1212 return; 1213 1214 /* Get rid of any previous state */ 1215 bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1216 1217 ATH_NODE_LOCK(ATH_NODE(bf->bf_node)); 1218 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream, 1219 bf->bf_state.bfs_pktlen, &rix, &try0, &rate); 1220 1221 /* In case MRR is disabled, make sure rc[0] is setup correctly */ 1222 bf->bf_state.bfs_rc[0].rix = rix; 1223 bf->bf_state.bfs_rc[0].ratecode = rate; 1224 bf->bf_state.bfs_rc[0].tries = try0; 1225 1226 if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY) 1227 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix, 1228 bf->bf_state.bfs_rc); 1229 ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node)); 1230 1231 sc->sc_txrix = rix; /* for LED blinking */ 1232 sc->sc_lastdatarix = rix; /* for fast frames */ 1233 bf->bf_state.bfs_try0 = try0; 1234 bf->bf_state.bfs_txrate0 = rate; 1235 } 1236 1237 /* 1238 * Transmit the given frame to the hardware. 1239 * 1240 * The frame must already be setup; rate control must already have 1241 * been done. 1242 * 1243 * XXX since the TXQ lock is being held here (and I dislike holding 1244 * it for this long when not doing software aggregation), later on 1245 * break this function into "setup_normal" and "xmit_normal". The 1246 * lock only needs to be held for the ath_tx_handoff call. 1247 */ 1248 static void 1249 ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq, 1250 struct ath_buf *bf) 1251 { 1252 1253 ATH_TXQ_LOCK_ASSERT(txq); 1254 1255 /* Setup the descriptor before handoff */ 1256 ath_tx_do_ratelookup(sc, bf); 1257 ath_tx_calc_duration(sc, bf); 1258 ath_tx_calc_protection(sc, bf); 1259 ath_tx_set_rtscts(sc, bf); 1260 ath_tx_rate_fill_rcflags(sc, bf); 1261 ath_tx_setds(sc, bf); 1262 1263 /* Hand off to hardware */ 1264 ath_tx_handoff(sc, txq, bf); 1265 } 1266 1267 1268 1269 static int 1270 ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni, 1271 struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq) 1272 { 1273 struct ieee80211vap *vap = ni->ni_vap; 1274 struct ath_hal *ah = sc->sc_ah; 1275 struct ifnet *ifp = sc->sc_ifp; 1276 struct ieee80211com *ic = ifp->if_l2com; 1277 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 1278 int error, iswep, ismcast, isfrag, ismrr; 1279 int keyix, hdrlen, pktlen, try0 = 0; 1280 u_int8_t rix = 0, txrate = 0; 1281 struct ath_desc *ds; 1282 struct ieee80211_frame *wh; 1283 u_int subtype, flags; 1284 HAL_PKT_TYPE atype; 1285 const HAL_RATE_TABLE *rt; 1286 HAL_BOOL shortPreamble; 1287 struct ath_node *an; 1288 u_int pri; 1289 1290 /* 1291 * To ensure that both sequence numbers and the CCMP PN handling 1292 * is "correct", make sure that the relevant TID queue is locked. 1293 * Otherwise the CCMP PN and seqno may appear out of order, causing 1294 * re-ordered frames to have out of order CCMP PN's, resulting 1295 * in many, many frame drops. 1296 */ 1297 ATH_TXQ_LOCK_ASSERT(txq); 1298 1299 wh = mtod(m0, struct ieee80211_frame *); 1300 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1301 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1302 isfrag = m0->m_flags & M_FRAG; 1303 hdrlen = ieee80211_anyhdrsize(wh); 1304 /* 1305 * Packet length must not include any 1306 * pad bytes; deduct them here. 1307 */ 1308 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 1309 1310 /* Handle encryption twiddling if needed */ 1311 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen, 1312 &pktlen, &keyix)) { 1313 ath_freetx(m0); 1314 return EIO; 1315 } 1316 1317 /* packet header may have moved, reset our local pointer */ 1318 wh = mtod(m0, struct ieee80211_frame *); 1319 1320 pktlen += IEEE80211_CRC_LEN; 1321 1322 /* 1323 * Load the DMA map so any coalescing is done. This 1324 * also calculates the number of descriptors we need. 1325 */ 1326 error = ath_tx_dmasetup(sc, bf, m0); 1327 if (error != 0) 1328 return error; 1329 bf->bf_node = ni; /* NB: held reference */ 1330 m0 = bf->bf_m; /* NB: may have changed */ 1331 wh = mtod(m0, struct ieee80211_frame *); 1332 1333 /* setup descriptors */ 1334 ds = bf->bf_desc; 1335 rt = sc->sc_currates; 1336 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1337 1338 /* 1339 * NB: the 802.11 layer marks whether or not we should 1340 * use short preamble based on the current mode and 1341 * negotiated parameters. 1342 */ 1343 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1344 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1345 shortPreamble = AH_TRUE; 1346 sc->sc_stats.ast_tx_shortpre++; 1347 } else { 1348 shortPreamble = AH_FALSE; 1349 } 1350 1351 an = ATH_NODE(ni); 1352 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1353 ismrr = 0; /* default no multi-rate retry*/ 1354 pri = M_WME_GETAC(m0); /* honor classification */ 1355 /* XXX use txparams instead of fixed values */ 1356 /* 1357 * Calculate Atheros packet type from IEEE80211 packet header, 1358 * setup for rate calculations, and select h/w transmit queue. 1359 */ 1360 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1361 case IEEE80211_FC0_TYPE_MGT: 1362 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1363 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1364 atype = HAL_PKT_TYPE_BEACON; 1365 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1366 atype = HAL_PKT_TYPE_PROBE_RESP; 1367 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1368 atype = HAL_PKT_TYPE_ATIM; 1369 else 1370 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 1371 rix = an->an_mgmtrix; 1372 txrate = rt->info[rix].rateCode; 1373 if (shortPreamble) 1374 txrate |= rt->info[rix].shortPreamble; 1375 try0 = ATH_TXMGTTRY; 1376 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1377 break; 1378 case IEEE80211_FC0_TYPE_CTL: 1379 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 1380 rix = an->an_mgmtrix; 1381 txrate = rt->info[rix].rateCode; 1382 if (shortPreamble) 1383 txrate |= rt->info[rix].shortPreamble; 1384 try0 = ATH_TXMGTTRY; 1385 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1386 break; 1387 case IEEE80211_FC0_TYPE_DATA: 1388 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1389 /* 1390 * Data frames: multicast frames go out at a fixed rate, 1391 * EAPOL frames use the mgmt frame rate; otherwise consult 1392 * the rate control module for the rate to use. 1393 */ 1394 if (ismcast) { 1395 rix = an->an_mcastrix; 1396 txrate = rt->info[rix].rateCode; 1397 if (shortPreamble) 1398 txrate |= rt->info[rix].shortPreamble; 1399 try0 = 1; 1400 } else if (m0->m_flags & M_EAPOL) { 1401 /* XXX? maybe always use long preamble? */ 1402 rix = an->an_mgmtrix; 1403 txrate = rt->info[rix].rateCode; 1404 if (shortPreamble) 1405 txrate |= rt->info[rix].shortPreamble; 1406 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 1407 } else { 1408 /* 1409 * Do rate lookup on each TX, rather than using 1410 * the hard-coded TX information decided here. 1411 */ 1412 ismrr = 1; 1413 bf->bf_state.bfs_doratelookup = 1; 1414 } 1415 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 1416 flags |= HAL_TXDESC_NOACK; 1417 break; 1418 default: 1419 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 1420 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1421 /* XXX statistic */ 1422 ath_freetx(m0); 1423 return EIO; 1424 } 1425 1426 /* 1427 * There are two known scenarios where the frame AC doesn't match 1428 * what the destination TXQ is. 1429 * 1430 * + non-QoS frames (eg management?) that the net80211 stack has 1431 * assigned a higher AC to, but since it's a non-QoS TID, it's 1432 * being thrown into TID 16. TID 16 gets the AC_BE queue. 1433 * It's quite possible that management frames should just be 1434 * direct dispatched to hardware rather than go via the software 1435 * queue; that should be investigated in the future. There are 1436 * some specific scenarios where this doesn't make sense, mostly 1437 * surrounding ADDBA request/response - hence why that is special 1438 * cased. 1439 * 1440 * + Multicast frames going into the VAP mcast queue. That shows up 1441 * as "TXQ 11". 1442 * 1443 * This driver should eventually support separate TID and TXQ locking, 1444 * allowing for arbitrary AC frames to appear on arbitrary software 1445 * queues, being queued to the "correct" hardware queue when needed. 1446 */ 1447 #if 0 1448 if (txq != sc->sc_ac2q[pri]) { 1449 device_printf(sc->sc_dev, 1450 "%s: txq=%p (%d), pri=%d, pri txq=%p (%d)\n", 1451 __func__, 1452 txq, 1453 txq->axq_qnum, 1454 pri, 1455 sc->sc_ac2q[pri], 1456 sc->sc_ac2q[pri]->axq_qnum); 1457 } 1458 #endif 1459 1460 /* 1461 * Calculate miscellaneous flags. 1462 */ 1463 if (ismcast) { 1464 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1465 } else if (pktlen > vap->iv_rtsthreshold && 1466 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 1467 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1468 sc->sc_stats.ast_tx_rts++; 1469 } 1470 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 1471 sc->sc_stats.ast_tx_noack++; 1472 #ifdef IEEE80211_SUPPORT_TDMA 1473 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 1474 DPRINTF(sc, ATH_DEBUG_TDMA, 1475 "%s: discard frame, ACK required w/ TDMA\n", __func__); 1476 sc->sc_stats.ast_tdma_ack++; 1477 ath_freetx(m0); 1478 return EIO; 1479 } 1480 #endif 1481 1482 /* 1483 * Determine if a tx interrupt should be generated for 1484 * this descriptor. We take a tx interrupt to reap 1485 * descriptors when the h/w hits an EOL condition or 1486 * when the descriptor is specifically marked to generate 1487 * an interrupt. We periodically mark descriptors in this 1488 * way to insure timely replenishing of the supply needed 1489 * for sending frames. Defering interrupts reduces system 1490 * load and potentially allows more concurrent work to be 1491 * done but if done to aggressively can cause senders to 1492 * backup. 1493 * 1494 * NB: use >= to deal with sc_txintrperiod changing 1495 * dynamically through sysctl. 1496 */ 1497 if (flags & HAL_TXDESC_INTREQ) { 1498 txq->axq_intrcnt = 0; 1499 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 1500 flags |= HAL_TXDESC_INTREQ; 1501 txq->axq_intrcnt = 0; 1502 } 1503 1504 /* This point forward is actual TX bits */ 1505 1506 /* 1507 * At this point we are committed to sending the frame 1508 * and we don't need to look at m_nextpkt; clear it in 1509 * case this frame is part of frag chain. 1510 */ 1511 m0->m_nextpkt = NULL; 1512 1513 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1514 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 1515 sc->sc_hwmap[rix].ieeerate, -1); 1516 1517 if (ieee80211_radiotap_active_vap(vap)) { 1518 u_int64_t tsf = ath_hal_gettsf64(ah); 1519 1520 sc->sc_tx_th.wt_tsf = htole64(tsf); 1521 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1522 if (iswep) 1523 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1524 if (isfrag) 1525 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1526 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1527 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1528 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1529 1530 ieee80211_radiotap_tx(vap, m0); 1531 } 1532 1533 /* Blank the legacy rate array */ 1534 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1535 1536 /* 1537 * ath_buf_set_rate needs at least one rate/try to setup 1538 * the rate scenario. 1539 */ 1540 bf->bf_state.bfs_rc[0].rix = rix; 1541 bf->bf_state.bfs_rc[0].tries = try0; 1542 bf->bf_state.bfs_rc[0].ratecode = txrate; 1543 1544 /* Store the decided rate index values away */ 1545 bf->bf_state.bfs_pktlen = pktlen; 1546 bf->bf_state.bfs_hdrlen = hdrlen; 1547 bf->bf_state.bfs_atype = atype; 1548 bf->bf_state.bfs_txpower = ni->ni_txpower; 1549 bf->bf_state.bfs_txrate0 = txrate; 1550 bf->bf_state.bfs_try0 = try0; 1551 bf->bf_state.bfs_keyix = keyix; 1552 bf->bf_state.bfs_txantenna = sc->sc_txantenna; 1553 bf->bf_state.bfs_txflags = flags; 1554 bf->bf_state.bfs_shpream = shortPreamble; 1555 1556 /* XXX this should be done in ath_tx_setrate() */ 1557 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */ 1558 bf->bf_state.bfs_ctsrate = 0; /* calculated later */ 1559 bf->bf_state.bfs_ctsduration = 0; 1560 bf->bf_state.bfs_ismrr = ismrr; 1561 1562 return 0; 1563 } 1564 1565 /* 1566 * Direct-dispatch the current frame to the hardware. 1567 * 1568 * This can be called by the net80211 code. 1569 * 1570 * XXX what about locking? Or, push the seqno assign into the 1571 * XXX aggregate scheduler so its serialised? 1572 */ 1573 int 1574 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, 1575 struct ath_buf *bf, struct mbuf *m0) 1576 { 1577 struct ieee80211vap *vap = ni->ni_vap; 1578 struct ath_vap *avp = ATH_VAP(vap); 1579 int r = 0; 1580 u_int pri; 1581 int tid; 1582 struct ath_txq *txq; 1583 int ismcast; 1584 const struct ieee80211_frame *wh; 1585 int is_ampdu, is_ampdu_tx, is_ampdu_pending; 1586 ieee80211_seq seqno; 1587 uint8_t type, subtype; 1588 1589 /* 1590 * Determine the target hardware queue. 1591 * 1592 * For multicast frames, the txq gets overridden appropriately 1593 * depending upon the state of PS. 1594 * 1595 * For any other frame, we do a TID/QoS lookup inside the frame 1596 * to see what the TID should be. If it's a non-QoS frame, the 1597 * AC and TID are overridden. The TID/TXQ code assumes the 1598 * TID is on a predictable hardware TXQ, so we don't support 1599 * having a node TID queued to multiple hardware TXQs. 1600 * This may change in the future but would require some locking 1601 * fudgery. 1602 */ 1603 pri = ath_tx_getac(sc, m0); 1604 tid = ath_tx_gettid(sc, m0); 1605 1606 txq = sc->sc_ac2q[pri]; 1607 wh = mtod(m0, struct ieee80211_frame *); 1608 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1609 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1610 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1611 1612 /* 1613 * Enforce how deep the multicast queue can grow. 1614 * 1615 * XXX duplicated in ath_raw_xmit(). 1616 */ 1617 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1618 ATH_TXQ_LOCK(sc->sc_cabq); 1619 1620 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 1621 sc->sc_stats.ast_tx_mcastq_overflow++; 1622 r = ENOBUFS; 1623 } 1624 1625 ATH_TXQ_UNLOCK(sc->sc_cabq); 1626 1627 if (r != 0) { 1628 m_freem(m0); 1629 return r; 1630 } 1631 } 1632 1633 /* A-MPDU TX */ 1634 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid); 1635 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid); 1636 is_ampdu = is_ampdu_tx | is_ampdu_pending; 1637 1638 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, ac=%d, is_ampdu=%d\n", 1639 __func__, tid, pri, is_ampdu); 1640 1641 /* Set local packet state, used to queue packets to hardware */ 1642 bf->bf_state.bfs_tid = tid; 1643 bf->bf_state.bfs_txq = txq; 1644 bf->bf_state.bfs_pri = pri; 1645 1646 /* 1647 * When servicing one or more stations in power-save mode 1648 * (or) if there is some mcast data waiting on the mcast 1649 * queue (to prevent out of order delivery) multicast frames 1650 * must be bufferd until after the beacon. 1651 * 1652 * TODO: we should lock the mcastq before we check the length. 1653 */ 1654 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) { 1655 txq = &avp->av_mcastq; 1656 /* 1657 * Mark the frame as eventually belonging on the CAB 1658 * queue, so the descriptor setup functions will 1659 * correctly initialise the descriptor 'qcuId' field. 1660 */ 1661 bf->bf_state.bfs_txq = sc->sc_cabq; 1662 } 1663 1664 /* Do the generic frame setup */ 1665 /* XXX should just bzero the bf_state? */ 1666 bf->bf_state.bfs_dobaw = 0; 1667 1668 /* 1669 * Acquire the TXQ lock early, so both the encap and seqno 1670 * are allocated together. 1671 * 1672 * XXX should TXQ for CABQ traffic be the multicast queue, 1673 * or the TXQ the given PRI would allocate from? (eg for 1674 * sequence number allocation locking.) 1675 */ 1676 ATH_TXQ_LOCK(txq); 1677 1678 /* A-MPDU TX? Manually set sequence number */ 1679 /* 1680 * Don't do it whilst pending; the net80211 layer still 1681 * assigns them. 1682 */ 1683 if (is_ampdu_tx) { 1684 /* 1685 * Always call; this function will 1686 * handle making sure that null data frames 1687 * don't get a sequence number from the current 1688 * TID and thus mess with the BAW. 1689 */ 1690 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0); 1691 1692 /* 1693 * Don't add QoS NULL frames to the BAW. 1694 */ 1695 if (IEEE80211_QOS_HAS_SEQ(wh) && 1696 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL) { 1697 bf->bf_state.bfs_dobaw = 1; 1698 } 1699 } 1700 1701 /* 1702 * If needed, the sequence number has been assigned. 1703 * Squirrel it away somewhere easy to get to. 1704 */ 1705 bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT; 1706 1707 /* Is ampdu pending? fetch the seqno and print it out */ 1708 if (is_ampdu_pending) 1709 DPRINTF(sc, ATH_DEBUG_SW_TX, 1710 "%s: tid %d: ampdu pending, seqno %d\n", 1711 __func__, tid, M_SEQNO_GET(m0)); 1712 1713 /* This also sets up the DMA map */ 1714 r = ath_tx_normal_setup(sc, ni, bf, m0, txq); 1715 1716 if (r != 0) 1717 goto done; 1718 1719 /* At this point m0 could have changed! */ 1720 m0 = bf->bf_m; 1721 1722 #if 1 1723 /* 1724 * If it's a multicast frame, do a direct-dispatch to the 1725 * destination hardware queue. Don't bother software 1726 * queuing it. 1727 */ 1728 /* 1729 * If it's a BAR frame, do a direct dispatch to the 1730 * destination hardware queue. Don't bother software 1731 * queuing it, as the TID will now be paused. 1732 * Sending a BAR frame can occur from the net80211 txa timer 1733 * (ie, retries) or from the ath txtask (completion call.) 1734 * It queues directly to hardware because the TID is paused 1735 * at this point (and won't be unpaused until the BAR has 1736 * either been TXed successfully or max retries has been 1737 * reached.) 1738 */ 1739 if (txq == &avp->av_mcastq) { 1740 DPRINTF(sc, ATH_DEBUG_SW_TX, 1741 "%s: bf=%p: mcastq: TX'ing\n", __func__, bf); 1742 ath_tx_xmit_normal(sc, txq, bf); 1743 } else if (type == IEEE80211_FC0_TYPE_CTL && 1744 subtype == IEEE80211_FC0_SUBTYPE_BAR) { 1745 DPRINTF(sc, ATH_DEBUG_SW_TX, 1746 "%s: BAR: TX'ing direct\n", __func__); 1747 ath_tx_xmit_normal(sc, txq, bf); 1748 } else { 1749 /* add to software queue */ 1750 DPRINTF(sc, ATH_DEBUG_SW_TX, 1751 "%s: bf=%p: swq: TX'ing\n", __func__, bf); 1752 ath_tx_swq(sc, ni, txq, bf); 1753 } 1754 #else 1755 /* 1756 * For now, since there's no software queue, 1757 * direct-dispatch to the hardware. 1758 */ 1759 ath_tx_xmit_normal(sc, txq, bf); 1760 #endif 1761 done: 1762 ATH_TXQ_UNLOCK(txq); 1763 1764 return 0; 1765 } 1766 1767 static int 1768 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 1769 struct ath_buf *bf, struct mbuf *m0, 1770 const struct ieee80211_bpf_params *params) 1771 { 1772 struct ifnet *ifp = sc->sc_ifp; 1773 struct ieee80211com *ic = ifp->if_l2com; 1774 struct ath_hal *ah = sc->sc_ah; 1775 struct ieee80211vap *vap = ni->ni_vap; 1776 int error, ismcast, ismrr; 1777 int keyix, hdrlen, pktlen, try0, txantenna; 1778 u_int8_t rix, txrate; 1779 struct ieee80211_frame *wh; 1780 u_int flags; 1781 HAL_PKT_TYPE atype; 1782 const HAL_RATE_TABLE *rt; 1783 struct ath_desc *ds; 1784 u_int pri; 1785 int o_tid = -1; 1786 int do_override; 1787 1788 wh = mtod(m0, struct ieee80211_frame *); 1789 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1790 hdrlen = ieee80211_anyhdrsize(wh); 1791 /* 1792 * Packet length must not include any 1793 * pad bytes; deduct them here. 1794 */ 1795 /* XXX honor IEEE80211_BPF_DATAPAD */ 1796 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 1797 1798 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n", 1799 __func__, ismcast); 1800 1801 pri = params->ibp_pri & 3; 1802 /* Override pri if the frame isn't a QoS one */ 1803 if (! IEEE80211_QOS_HAS_SEQ(wh)) 1804 pri = ath_tx_getac(sc, m0); 1805 1806 /* XXX If it's an ADDBA, override the correct queue */ 1807 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid); 1808 1809 /* Map ADDBA to the correct priority */ 1810 if (do_override) { 1811 #if 0 1812 device_printf(sc->sc_dev, 1813 "%s: overriding tid %d pri %d -> %d\n", 1814 __func__, o_tid, pri, TID_TO_WME_AC(o_tid)); 1815 #endif 1816 pri = TID_TO_WME_AC(o_tid); 1817 } 1818 1819 ATH_TXQ_LOCK(sc->sc_ac2q[pri]); 1820 1821 /* Handle encryption twiddling if needed */ 1822 if (! ath_tx_tag_crypto(sc, ni, 1823 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0, 1824 &hdrlen, &pktlen, &keyix)) { 1825 ath_freetx(m0); 1826 return EIO; 1827 } 1828 /* packet header may have moved, reset our local pointer */ 1829 wh = mtod(m0, struct ieee80211_frame *); 1830 1831 /* Do the generic frame setup */ 1832 /* XXX should just bzero the bf_state? */ 1833 bf->bf_state.bfs_dobaw = 0; 1834 1835 error = ath_tx_dmasetup(sc, bf, m0); 1836 if (error != 0) 1837 return error; 1838 m0 = bf->bf_m; /* NB: may have changed */ 1839 wh = mtod(m0, struct ieee80211_frame *); 1840 bf->bf_node = ni; /* NB: held reference */ 1841 1842 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1843 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1844 if (params->ibp_flags & IEEE80211_BPF_RTS) 1845 flags |= HAL_TXDESC_RTSENA; 1846 else if (params->ibp_flags & IEEE80211_BPF_CTS) { 1847 /* XXX assume 11g/11n protection? */ 1848 bf->bf_state.bfs_doprot = 1; 1849 flags |= HAL_TXDESC_CTSENA; 1850 } 1851 /* XXX leave ismcast to injector? */ 1852 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 1853 flags |= HAL_TXDESC_NOACK; 1854 1855 rt = sc->sc_currates; 1856 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1857 rix = ath_tx_findrix(sc, params->ibp_rate0); 1858 txrate = rt->info[rix].rateCode; 1859 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 1860 txrate |= rt->info[rix].shortPreamble; 1861 sc->sc_txrix = rix; 1862 try0 = params->ibp_try0; 1863 ismrr = (params->ibp_try1 != 0); 1864 txantenna = params->ibp_pri >> 2; 1865 if (txantenna == 0) /* XXX? */ 1866 txantenna = sc->sc_txantenna; 1867 1868 /* 1869 * Since ctsrate is fixed, store it away for later 1870 * use when the descriptor fields are being set. 1871 */ 1872 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) 1873 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate; 1874 1875 /* 1876 * NB: we mark all packets as type PSPOLL so the h/w won't 1877 * set the sequence number, duration, etc. 1878 */ 1879 atype = HAL_PKT_TYPE_PSPOLL; 1880 1881 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1882 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 1883 sc->sc_hwmap[rix].ieeerate, -1); 1884 1885 if (ieee80211_radiotap_active_vap(vap)) { 1886 u_int64_t tsf = ath_hal_gettsf64(ah); 1887 1888 sc->sc_tx_th.wt_tsf = htole64(tsf); 1889 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1890 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1891 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1892 if (m0->m_flags & M_FRAG) 1893 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1894 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1895 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1896 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1897 1898 ieee80211_radiotap_tx(vap, m0); 1899 } 1900 1901 /* 1902 * Formulate first tx descriptor with tx controls. 1903 */ 1904 ds = bf->bf_desc; 1905 /* XXX check return value? */ 1906 1907 /* Store the decided rate index values away */ 1908 bf->bf_state.bfs_pktlen = pktlen; 1909 bf->bf_state.bfs_hdrlen = hdrlen; 1910 bf->bf_state.bfs_atype = atype; 1911 bf->bf_state.bfs_txpower = params->ibp_power; 1912 bf->bf_state.bfs_txrate0 = txrate; 1913 bf->bf_state.bfs_try0 = try0; 1914 bf->bf_state.bfs_keyix = keyix; 1915 bf->bf_state.bfs_txantenna = txantenna; 1916 bf->bf_state.bfs_txflags = flags; 1917 bf->bf_state.bfs_shpream = 1918 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE); 1919 1920 /* Set local packet state, used to queue packets to hardware */ 1921 bf->bf_state.bfs_tid = WME_AC_TO_TID(pri); 1922 bf->bf_state.bfs_txq = sc->sc_ac2q[pri]; 1923 bf->bf_state.bfs_pri = pri; 1924 1925 /* XXX this should be done in ath_tx_setrate() */ 1926 bf->bf_state.bfs_ctsrate = 0; 1927 bf->bf_state.bfs_ctsduration = 0; 1928 bf->bf_state.bfs_ismrr = ismrr; 1929 1930 /* Blank the legacy rate array */ 1931 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1932 1933 bf->bf_state.bfs_rc[0].rix = 1934 ath_tx_findrix(sc, params->ibp_rate0); 1935 bf->bf_state.bfs_rc[0].tries = try0; 1936 bf->bf_state.bfs_rc[0].ratecode = txrate; 1937 1938 if (ismrr) { 1939 int rix; 1940 1941 rix = ath_tx_findrix(sc, params->ibp_rate1); 1942 bf->bf_state.bfs_rc[1].rix = rix; 1943 bf->bf_state.bfs_rc[1].tries = params->ibp_try1; 1944 1945 rix = ath_tx_findrix(sc, params->ibp_rate2); 1946 bf->bf_state.bfs_rc[2].rix = rix; 1947 bf->bf_state.bfs_rc[2].tries = params->ibp_try2; 1948 1949 rix = ath_tx_findrix(sc, params->ibp_rate3); 1950 bf->bf_state.bfs_rc[3].rix = rix; 1951 bf->bf_state.bfs_rc[3].tries = params->ibp_try3; 1952 } 1953 /* 1954 * All the required rate control decisions have been made; 1955 * fill in the rc flags. 1956 */ 1957 ath_tx_rate_fill_rcflags(sc, bf); 1958 1959 /* NB: no buffered multicast in power save support */ 1960 1961 /* 1962 * If we're overiding the ADDBA destination, dump directly 1963 * into the hardware queue, right after any pending 1964 * frames to that node are. 1965 */ 1966 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n", 1967 __func__, do_override); 1968 1969 if (do_override) { 1970 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf); 1971 } else { 1972 /* Queue to software queue */ 1973 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf); 1974 } 1975 ATH_TXQ_UNLOCK(sc->sc_ac2q[pri]); 1976 1977 return 0; 1978 } 1979 1980 /* 1981 * Send a raw frame. 1982 * 1983 * This can be called by net80211. 1984 */ 1985 int 1986 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1987 const struct ieee80211_bpf_params *params) 1988 { 1989 struct ieee80211com *ic = ni->ni_ic; 1990 struct ifnet *ifp = ic->ic_ifp; 1991 struct ath_softc *sc = ifp->if_softc; 1992 struct ath_buf *bf; 1993 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 1994 int error = 0; 1995 1996 ATH_PCU_LOCK(sc); 1997 if (sc->sc_inreset_cnt > 0) { 1998 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n", 1999 __func__); 2000 error = EIO; 2001 ATH_PCU_UNLOCK(sc); 2002 goto bad0; 2003 } 2004 sc->sc_txstart_cnt++; 2005 ATH_PCU_UNLOCK(sc); 2006 2007 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 2008 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 2009 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ? 2010 "!running" : "invalid"); 2011 m_freem(m); 2012 error = ENETDOWN; 2013 goto bad; 2014 } 2015 2016 /* 2017 * Enforce how deep the multicast queue can grow. 2018 * 2019 * XXX duplicated in ath_tx_start(). 2020 */ 2021 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2022 ATH_TXQ_LOCK(sc->sc_cabq); 2023 2024 if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 2025 sc->sc_stats.ast_tx_mcastq_overflow++; 2026 error = ENOBUFS; 2027 } 2028 2029 ATH_TXQ_UNLOCK(sc->sc_cabq); 2030 2031 if (error != 0) { 2032 m_freem(m); 2033 goto bad; 2034 } 2035 } 2036 2037 /* 2038 * Grab a TX buffer and associated resources. 2039 */ 2040 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT); 2041 if (bf == NULL) { 2042 sc->sc_stats.ast_tx_nobuf++; 2043 m_freem(m); 2044 error = ENOBUFS; 2045 goto bad; 2046 } 2047 2048 if (params == NULL) { 2049 /* 2050 * Legacy path; interpret frame contents to decide 2051 * precisely how to send the frame. 2052 */ 2053 if (ath_tx_start(sc, ni, bf, m)) { 2054 error = EIO; /* XXX */ 2055 goto bad2; 2056 } 2057 } else { 2058 /* 2059 * Caller supplied explicit parameters to use in 2060 * sending the frame. 2061 */ 2062 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 2063 error = EIO; /* XXX */ 2064 goto bad2; 2065 } 2066 } 2067 sc->sc_wd_timer = 5; 2068 ifp->if_opackets++; 2069 sc->sc_stats.ast_tx_raw++; 2070 2071 ATH_PCU_LOCK(sc); 2072 sc->sc_txstart_cnt--; 2073 ATH_PCU_UNLOCK(sc); 2074 2075 return 0; 2076 bad2: 2077 ATH_TXBUF_LOCK(sc); 2078 ath_returnbuf_head(sc, bf); 2079 ATH_TXBUF_UNLOCK(sc); 2080 bad: 2081 ATH_PCU_LOCK(sc); 2082 sc->sc_txstart_cnt--; 2083 ATH_PCU_UNLOCK(sc); 2084 bad0: 2085 ifp->if_oerrors++; 2086 sc->sc_stats.ast_tx_raw_fail++; 2087 ieee80211_free_node(ni); 2088 2089 return error; 2090 } 2091 2092 /* Some helper functions */ 2093 2094 /* 2095 * ADDBA (and potentially others) need to be placed in the same 2096 * hardware queue as the TID/node it's relating to. This is so 2097 * it goes out after any pending non-aggregate frames to the 2098 * same node/TID. 2099 * 2100 * If this isn't done, the ADDBA can go out before the frames 2101 * queued in hardware. Even though these frames have a sequence 2102 * number -earlier- than the ADDBA can be transmitted (but 2103 * no frames whose sequence numbers are after the ADDBA should 2104 * be!) they'll arrive after the ADDBA - and the receiving end 2105 * will simply drop them as being out of the BAW. 2106 * 2107 * The frames can't be appended to the TID software queue - it'll 2108 * never be sent out. So these frames have to be directly 2109 * dispatched to the hardware, rather than queued in software. 2110 * So if this function returns true, the TXQ has to be 2111 * overridden and it has to be directly dispatched. 2112 * 2113 * It's a dirty hack, but someone's gotta do it. 2114 */ 2115 2116 /* 2117 * XXX doesn't belong here! 2118 */ 2119 static int 2120 ieee80211_is_action(struct ieee80211_frame *wh) 2121 { 2122 /* Type: Management frame? */ 2123 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 2124 IEEE80211_FC0_TYPE_MGT) 2125 return 0; 2126 2127 /* Subtype: Action frame? */ 2128 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) != 2129 IEEE80211_FC0_SUBTYPE_ACTION) 2130 return 0; 2131 2132 return 1; 2133 } 2134 2135 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 2136 /* 2137 * Return an alternate TID for ADDBA request frames. 2138 * 2139 * Yes, this likely should be done in the net80211 layer. 2140 */ 2141 static int 2142 ath_tx_action_frame_override_queue(struct ath_softc *sc, 2143 struct ieee80211_node *ni, 2144 struct mbuf *m0, int *tid) 2145 { 2146 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 2147 struct ieee80211_action_ba_addbarequest *ia; 2148 uint8_t *frm; 2149 uint16_t baparamset; 2150 2151 /* Not action frame? Bail */ 2152 if (! ieee80211_is_action(wh)) 2153 return 0; 2154 2155 /* XXX Not needed for frames we send? */ 2156 #if 0 2157 /* Correct length? */ 2158 if (! ieee80211_parse_action(ni, m)) 2159 return 0; 2160 #endif 2161 2162 /* Extract out action frame */ 2163 frm = (u_int8_t *)&wh[1]; 2164 ia = (struct ieee80211_action_ba_addbarequest *) frm; 2165 2166 /* Not ADDBA? Bail */ 2167 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA) 2168 return 0; 2169 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST) 2170 return 0; 2171 2172 /* Extract TID, return it */ 2173 baparamset = le16toh(ia->rq_baparamset); 2174 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID); 2175 2176 return 1; 2177 } 2178 #undef MS 2179 2180 /* Per-node software queue operations */ 2181 2182 /* 2183 * Add the current packet to the given BAW. 2184 * It is assumed that the current packet 2185 * 2186 * + fits inside the BAW; 2187 * + already has had a sequence number allocated. 2188 * 2189 * Since the BAW status may be modified by both the ath task and 2190 * the net80211/ifnet contexts, the TID must be locked. 2191 */ 2192 void 2193 ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an, 2194 struct ath_tid *tid, struct ath_buf *bf) 2195 { 2196 int index, cindex; 2197 struct ieee80211_tx_ampdu *tap; 2198 2199 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2200 ATH_TID_LOCK_ASSERT(sc, tid); 2201 2202 if (bf->bf_state.bfs_isretried) 2203 return; 2204 2205 tap = ath_tx_get_tx_tid(an, tid->tid); 2206 2207 if (! bf->bf_state.bfs_dobaw) { 2208 device_printf(sc->sc_dev, 2209 "%s: dobaw=0, seqno=%d, window %d:%d\n", 2210 __func__, 2211 SEQNO(bf->bf_state.bfs_seqno), 2212 tap->txa_start, 2213 tap->txa_wnd); 2214 } 2215 2216 if (bf->bf_state.bfs_addedbaw) 2217 device_printf(sc->sc_dev, 2218 "%s: re-added? tid=%d, seqno %d; window %d:%d; " 2219 "baw head=%d tail=%d\n", 2220 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2221 tap->txa_start, tap->txa_wnd, tid->baw_head, 2222 tid->baw_tail); 2223 2224 /* 2225 * Verify that the given sequence number is not outside of the 2226 * BAW. Complain loudly if that's the case. 2227 */ 2228 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2229 SEQNO(bf->bf_state.bfs_seqno))) { 2230 device_printf(sc->sc_dev, 2231 "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; " 2232 "baw head=%d tail=%d\n", 2233 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2234 tap->txa_start, tap->txa_wnd, tid->baw_head, 2235 tid->baw_tail); 2236 } 2237 2238 /* 2239 * ni->ni_txseqs[] is the currently allocated seqno. 2240 * the txa state contains the current baw start. 2241 */ 2242 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno)); 2243 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2244 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2245 "%s: tid=%d, seqno %d; window %d:%d; index=%d cindex=%d " 2246 "baw head=%d tail=%d\n", 2247 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2248 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head, 2249 tid->baw_tail); 2250 2251 2252 #if 0 2253 assert(tid->tx_buf[cindex] == NULL); 2254 #endif 2255 if (tid->tx_buf[cindex] != NULL) { 2256 device_printf(sc->sc_dev, 2257 "%s: ba packet dup (index=%d, cindex=%d, " 2258 "head=%d, tail=%d)\n", 2259 __func__, index, cindex, tid->baw_head, tid->baw_tail); 2260 device_printf(sc->sc_dev, 2261 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n", 2262 __func__, 2263 tid->tx_buf[cindex], 2264 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno), 2265 bf, 2266 SEQNO(bf->bf_state.bfs_seqno) 2267 ); 2268 } 2269 tid->tx_buf[cindex] = bf; 2270 2271 if (index >= ((tid->baw_tail - tid->baw_head) & 2272 (ATH_TID_MAX_BUFS - 1))) { 2273 tid->baw_tail = cindex; 2274 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 2275 } 2276 } 2277 2278 /* 2279 * Flip the BAW buffer entry over from the existing one to the new one. 2280 * 2281 * When software retransmitting a (sub-)frame, it is entirely possible that 2282 * the frame ath_buf is marked as BUSY and can't be immediately reused. 2283 * In that instance the buffer is cloned and the new buffer is used for 2284 * retransmit. We thus need to update the ath_buf slot in the BAW buf 2285 * tracking array to maintain consistency. 2286 */ 2287 static void 2288 ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an, 2289 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf) 2290 { 2291 int index, cindex; 2292 struct ieee80211_tx_ampdu *tap; 2293 int seqno = SEQNO(old_bf->bf_state.bfs_seqno); 2294 2295 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2296 ATH_TID_LOCK_ASSERT(sc, tid); 2297 2298 tap = ath_tx_get_tx_tid(an, tid->tid); 2299 index = ATH_BA_INDEX(tap->txa_start, seqno); 2300 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2301 2302 /* 2303 * Just warn for now; if it happens then we should find out 2304 * about it. It's highly likely the aggregation session will 2305 * soon hang. 2306 */ 2307 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) { 2308 device_printf(sc->sc_dev, "%s: retransmitted buffer" 2309 " has mismatching seqno's, BA session may hang.\n", 2310 __func__); 2311 device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n", 2312 __func__, 2313 old_bf->bf_state.bfs_seqno, 2314 new_bf->bf_state.bfs_seqno); 2315 } 2316 2317 if (tid->tx_buf[cindex] != old_bf) { 2318 device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; " 2319 " has m BA session may hang.\n", 2320 __func__); 2321 device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n", 2322 __func__, 2323 old_bf, new_bf); 2324 } 2325 2326 tid->tx_buf[cindex] = new_bf; 2327 } 2328 2329 /* 2330 * seq_start - left edge of BAW 2331 * seq_next - current/next sequence number to allocate 2332 * 2333 * Since the BAW status may be modified by both the ath task and 2334 * the net80211/ifnet contexts, the TID must be locked. 2335 */ 2336 static void 2337 ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an, 2338 struct ath_tid *tid, const struct ath_buf *bf) 2339 { 2340 int index, cindex; 2341 struct ieee80211_tx_ampdu *tap; 2342 int seqno = SEQNO(bf->bf_state.bfs_seqno); 2343 2344 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2345 ATH_TID_LOCK_ASSERT(sc, tid); 2346 2347 tap = ath_tx_get_tx_tid(an, tid->tid); 2348 index = ATH_BA_INDEX(tap->txa_start, seqno); 2349 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2350 2351 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2352 "%s: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, " 2353 "baw head=%d, tail=%d\n", 2354 __func__, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index, 2355 cindex, tid->baw_head, tid->baw_tail); 2356 2357 /* 2358 * If this occurs then we have a big problem - something else 2359 * has slid tap->txa_start along without updating the BAW 2360 * tracking start/end pointers. Thus the TX BAW state is now 2361 * completely busted. 2362 * 2363 * But for now, since I haven't yet fixed TDMA and buffer cloning, 2364 * it's quite possible that a cloned buffer is making its way 2365 * here and causing it to fire off. Disable TDMA for now. 2366 */ 2367 if (tid->tx_buf[cindex] != bf) { 2368 device_printf(sc->sc_dev, 2369 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n", 2370 __func__, 2371 bf, SEQNO(bf->bf_state.bfs_seqno), 2372 tid->tx_buf[cindex], 2373 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno)); 2374 } 2375 2376 tid->tx_buf[cindex] = NULL; 2377 2378 while (tid->baw_head != tid->baw_tail && 2379 !tid->tx_buf[tid->baw_head]) { 2380 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 2381 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 2382 } 2383 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2384 "%s: baw is now %d:%d, baw head=%d\n", 2385 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head); 2386 } 2387 2388 /* 2389 * Mark the current node/TID as ready to TX. 2390 * 2391 * This is done to make it easy for the software scheduler to 2392 * find which nodes have data to send. 2393 * 2394 * The TXQ lock must be held. 2395 */ 2396 static void 2397 ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid) 2398 { 2399 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2400 2401 ATH_TXQ_LOCK_ASSERT(txq); 2402 2403 if (tid->paused) 2404 return; /* paused, can't schedule yet */ 2405 2406 if (tid->sched) 2407 return; /* already scheduled */ 2408 2409 tid->sched = 1; 2410 2411 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem); 2412 } 2413 2414 /* 2415 * Mark the current node as no longer needing to be polled for 2416 * TX packets. 2417 * 2418 * The TXQ lock must be held. 2419 */ 2420 static void 2421 ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid) 2422 { 2423 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2424 2425 ATH_TXQ_LOCK_ASSERT(txq); 2426 2427 if (tid->sched == 0) 2428 return; 2429 2430 tid->sched = 0; 2431 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem); 2432 } 2433 2434 /* 2435 * Assign a sequence number manually to the given frame. 2436 * 2437 * This should only be called for A-MPDU TX frames. 2438 */ 2439 static ieee80211_seq 2440 ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni, 2441 struct ath_buf *bf, struct mbuf *m0) 2442 { 2443 struct ieee80211_frame *wh; 2444 int tid, pri; 2445 ieee80211_seq seqno; 2446 uint8_t subtype; 2447 2448 /* TID lookup */ 2449 wh = mtod(m0, struct ieee80211_frame *); 2450 pri = M_WME_GETAC(m0); /* honor classification */ 2451 tid = WME_AC_TO_TID(pri); 2452 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pri=%d, tid=%d, qos has seq=%d\n", 2453 __func__, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2454 2455 /* XXX Is it a control frame? Ignore */ 2456 2457 /* Does the packet require a sequence number? */ 2458 if (! IEEE80211_QOS_HAS_SEQ(wh)) 2459 return -1; 2460 2461 ATH_TID_LOCK_ASSERT(sc, &(ATH_NODE(ni)->an_tid[tid])); 2462 2463 /* 2464 * Is it a QOS NULL Data frame? Give it a sequence number from 2465 * the default TID (IEEE80211_NONQOS_TID.) 2466 * 2467 * The RX path of everything I've looked at doesn't include the NULL 2468 * data frame sequence number in the aggregation state updates, so 2469 * assigning it a sequence number there will cause a BAW hole on the 2470 * RX side. 2471 */ 2472 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2473 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) { 2474 /* XXX no locking for this TID? This is a bit of a problem. */ 2475 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID]; 2476 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE); 2477 } else { 2478 /* Manually assign sequence number */ 2479 seqno = ni->ni_txseqs[tid]; 2480 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE); 2481 } 2482 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 2483 M_SEQNO_SET(m0, seqno); 2484 2485 /* Return so caller can do something with it if needed */ 2486 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: -> seqno=%d\n", __func__, seqno); 2487 return seqno; 2488 } 2489 2490 /* 2491 * Attempt to direct dispatch an aggregate frame to hardware. 2492 * If the frame is out of BAW, queue. 2493 * Otherwise, schedule it as a single frame. 2494 */ 2495 static void 2496 ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an, 2497 struct ath_txq *txq, struct ath_buf *bf) 2498 { 2499 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid]; 2500 // struct ath_txq *txq = bf->bf_state.bfs_txq; 2501 struct ieee80211_tx_ampdu *tap; 2502 2503 if (txq != bf->bf_state.bfs_txq) { 2504 device_printf(sc->sc_dev, "%s: txq %d != bfs_txq %d!\n", 2505 __func__, 2506 txq->axq_qnum, 2507 bf->bf_state.bfs_txq->axq_qnum); 2508 } 2509 2510 ATH_TXQ_LOCK_ASSERT(txq); 2511 ATH_TID_LOCK_ASSERT(sc, tid); 2512 2513 tap = ath_tx_get_tx_tid(an, tid->tid); 2514 2515 /* paused? queue */ 2516 if (tid->paused) { 2517 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 2518 /* XXX don't sched - we're paused! */ 2519 return; 2520 } 2521 2522 /* outside baw? queue */ 2523 if (bf->bf_state.bfs_dobaw && 2524 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2525 SEQNO(bf->bf_state.bfs_seqno)))) { 2526 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 2527 ath_tx_tid_sched(sc, tid); 2528 return; 2529 } 2530 2531 /* Direct dispatch to hardware */ 2532 ath_tx_do_ratelookup(sc, bf); 2533 ath_tx_calc_duration(sc, bf); 2534 ath_tx_calc_protection(sc, bf); 2535 ath_tx_set_rtscts(sc, bf); 2536 ath_tx_rate_fill_rcflags(sc, bf); 2537 ath_tx_setds(sc, bf); 2538 2539 /* Statistics */ 2540 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++; 2541 2542 /* Track per-TID hardware queue depth correctly */ 2543 tid->hwq_depth++; 2544 2545 /* Add to BAW */ 2546 if (bf->bf_state.bfs_dobaw) { 2547 ath_tx_addto_baw(sc, an, tid, bf); 2548 bf->bf_state.bfs_addedbaw = 1; 2549 } 2550 2551 /* Set completion handler, multi-frame aggregate or not */ 2552 bf->bf_comp = ath_tx_aggr_comp; 2553 2554 /* Hand off to hardware */ 2555 ath_tx_handoff(sc, txq, bf); 2556 } 2557 2558 /* 2559 * Attempt to send the packet. 2560 * If the queue isn't busy, direct-dispatch. 2561 * If the queue is busy enough, queue the given packet on the 2562 * relevant software queue. 2563 */ 2564 void 2565 ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq, 2566 struct ath_buf *bf) 2567 { 2568 struct ath_node *an = ATH_NODE(ni); 2569 struct ieee80211_frame *wh; 2570 struct ath_tid *atid; 2571 int pri, tid; 2572 struct mbuf *m0 = bf->bf_m; 2573 2574 ATH_TXQ_LOCK_ASSERT(txq); 2575 2576 /* Fetch the TID - non-QoS frames get assigned to TID 16 */ 2577 wh = mtod(m0, struct ieee80211_frame *); 2578 pri = ath_tx_getac(sc, m0); 2579 tid = ath_tx_gettid(sc, m0); 2580 atid = &an->an_tid[tid]; 2581 2582 ATH_TID_LOCK_ASSERT(sc, atid); 2583 2584 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d\n", 2585 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2586 2587 /* Set local packet state, used to queue packets to hardware */ 2588 /* XXX potentially duplicate info, re-check */ 2589 /* XXX remember, txq must be the hardware queue, not the av_mcastq */ 2590 bf->bf_state.bfs_tid = tid; 2591 bf->bf_state.bfs_txq = txq; 2592 bf->bf_state.bfs_pri = pri; 2593 2594 /* 2595 * If the hardware queue isn't busy, queue it directly. 2596 * If the hardware queue is busy, queue it. 2597 * If the TID is paused or the traffic it outside BAW, software 2598 * queue it. 2599 */ 2600 if (atid->paused) { 2601 /* TID is paused, queue */ 2602 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: paused\n", __func__); 2603 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2604 } else if (ath_tx_ampdu_pending(sc, an, tid)) { 2605 /* AMPDU pending; queue */ 2606 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pending\n", __func__); 2607 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2608 /* XXX sched? */ 2609 } else if (ath_tx_ampdu_running(sc, an, tid)) { 2610 /* AMPDU running, attempt direct dispatch if possible */ 2611 2612 /* 2613 * Always queue the frame to the tail of the list. 2614 */ 2615 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2616 2617 /* 2618 * If the hardware queue isn't busy, direct dispatch 2619 * the head frame in the list. Don't schedule the 2620 * TID - let it build some more frames first? 2621 * 2622 * Otherwise, schedule the TID. 2623 */ 2624 if (txq->axq_depth < sc->sc_hwq_limit) { 2625 bf = TAILQ_FIRST(&atid->axq_q); 2626 ATH_TXQ_REMOVE(atid, bf, bf_list); 2627 ath_tx_xmit_aggr(sc, an, txq, bf); 2628 DPRINTF(sc, ATH_DEBUG_SW_TX, 2629 "%s: xmit_aggr\n", 2630 __func__); 2631 } else { 2632 DPRINTF(sc, ATH_DEBUG_SW_TX, 2633 "%s: ampdu; swq'ing\n", 2634 __func__); 2635 ath_tx_tid_sched(sc, atid); 2636 } 2637 } else if (txq->axq_depth < sc->sc_hwq_limit) { 2638 /* AMPDU not running, attempt direct dispatch */ 2639 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: xmit_normal\n", __func__); 2640 ath_tx_xmit_normal(sc, txq, bf); 2641 } else { 2642 /* Busy; queue */ 2643 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: swq'ing\n", __func__); 2644 ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2645 ath_tx_tid_sched(sc, atid); 2646 } 2647 } 2648 2649 /* 2650 * Do the basic frame setup stuff that's required before the frame 2651 * is added to a software queue. 2652 * 2653 * All frames get mostly the same treatment and it's done once. 2654 * Retransmits fiddle with things like the rate control setup, 2655 * setting the retransmit bit in the packet; doing relevant DMA/bus 2656 * syncing and relinking it (back) into the hardware TX queue. 2657 * 2658 * Note that this may cause the mbuf to be reallocated, so 2659 * m0 may not be valid. 2660 */ 2661 2662 2663 /* 2664 * Configure the per-TID node state. 2665 * 2666 * This likely belongs in if_ath_node.c but I can't think of anywhere 2667 * else to put it just yet. 2668 * 2669 * This sets up the SLISTs and the mutex as appropriate. 2670 */ 2671 void 2672 ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an) 2673 { 2674 int i, j; 2675 struct ath_tid *atid; 2676 2677 for (i = 0; i < IEEE80211_TID_SIZE; i++) { 2678 atid = &an->an_tid[i]; 2679 TAILQ_INIT(&atid->axq_q); 2680 atid->tid = i; 2681 atid->an = an; 2682 for (j = 0; j < ATH_TID_MAX_BUFS; j++) 2683 atid->tx_buf[j] = NULL; 2684 atid->baw_head = atid->baw_tail = 0; 2685 atid->paused = 0; 2686 atid->sched = 0; 2687 atid->hwq_depth = 0; 2688 atid->cleanup_inprogress = 0; 2689 if (i == IEEE80211_NONQOS_TID) 2690 atid->ac = WME_AC_BE; 2691 else 2692 atid->ac = TID_TO_WME_AC(i); 2693 } 2694 } 2695 2696 /* 2697 * Pause the current TID. This stops packets from being transmitted 2698 * on it. 2699 * 2700 * Since this is also called from upper layers as well as the driver, 2701 * it will get the TID lock. 2702 */ 2703 static void 2704 ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid) 2705 { 2706 2707 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2708 tid->paused++; 2709 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n", 2710 __func__, tid->paused); 2711 } 2712 2713 /* 2714 * Unpause the current TID, and schedule it if needed. 2715 */ 2716 static void 2717 ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid) 2718 { 2719 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2720 2721 tid->paused--; 2722 2723 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n", 2724 __func__, tid->paused); 2725 2726 if (tid->paused || tid->axq_depth == 0) { 2727 return; 2728 } 2729 2730 ath_tx_tid_sched(sc, tid); 2731 /* Punt some frames to the hardware if needed */ 2732 //ath_txq_sched(sc, sc->sc_ac2q[tid->ac]); 2733 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 2734 } 2735 2736 /* 2737 * Suspend the queue because we need to TX a BAR. 2738 */ 2739 static void 2740 ath_tx_tid_bar_suspend(struct ath_softc *sc, struct ath_tid *tid) 2741 { 2742 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2743 2744 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2745 "%s: tid=%p, bar_wait=%d, bar_tx=%d, called\n", 2746 __func__, 2747 tid, 2748 tid->bar_wait, 2749 tid->bar_tx); 2750 2751 /* We shouldn't be called when bar_tx is 1 */ 2752 if (tid->bar_tx) { 2753 device_printf(sc->sc_dev, "%s: bar_tx is 1?!\n", 2754 __func__); 2755 } 2756 2757 /* If we've already been called, just be patient. */ 2758 if (tid->bar_wait) 2759 return; 2760 2761 /* Wait! */ 2762 tid->bar_wait = 1; 2763 2764 /* Only one pause, no matter how many frames fail */ 2765 ath_tx_tid_pause(sc, tid); 2766 } 2767 2768 /* 2769 * We've finished with BAR handling - either we succeeded or 2770 * failed. Either way, unsuspend TX. 2771 */ 2772 static void 2773 ath_tx_tid_bar_unsuspend(struct ath_softc *sc, struct ath_tid *tid) 2774 { 2775 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2776 2777 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2778 "%s: tid=%p, called\n", 2779 __func__, 2780 tid); 2781 2782 if (tid->bar_tx == 0 || tid->bar_wait == 0) { 2783 device_printf(sc->sc_dev, "%s: bar_tx=%d, bar_wait=%d: ?\n", 2784 __func__, tid->bar_tx, tid->bar_wait); 2785 } 2786 2787 tid->bar_tx = tid->bar_wait = 0; 2788 ath_tx_tid_resume(sc, tid); 2789 } 2790 2791 /* 2792 * Return whether we're ready to TX a BAR frame. 2793 * 2794 * Requires the TID lock be held. 2795 */ 2796 static int 2797 ath_tx_tid_bar_tx_ready(struct ath_softc *sc, struct ath_tid *tid) 2798 { 2799 2800 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2801 2802 if (tid->bar_wait == 0 || tid->hwq_depth > 0) 2803 return (0); 2804 2805 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, "%s: tid=%p (%d), bar ready\n", 2806 __func__, tid, tid->tid); 2807 2808 return (1); 2809 } 2810 2811 /* 2812 * Check whether the current TID is ready to have a BAR 2813 * TXed and if so, do the TX. 2814 * 2815 * Since the TID/TXQ lock can't be held during a call to 2816 * ieee80211_send_bar(), we have to do the dirty thing of unlocking it, 2817 * sending the BAR and locking it again. 2818 * 2819 * Eventually, the code to send the BAR should be broken out 2820 * from this routine so the lock doesn't have to be reacquired 2821 * just to be immediately dropped by the caller. 2822 */ 2823 static void 2824 ath_tx_tid_bar_tx(struct ath_softc *sc, struct ath_tid *tid) 2825 { 2826 struct ieee80211_tx_ampdu *tap; 2827 2828 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2829 2830 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2831 "%s: tid=%p, called\n", 2832 __func__, 2833 tid); 2834 2835 tap = ath_tx_get_tx_tid(tid->an, tid->tid); 2836 2837 /* 2838 * This is an error condition! 2839 */ 2840 if (tid->bar_wait == 0 || tid->bar_tx == 1) { 2841 device_printf(sc->sc_dev, 2842 "%s: tid=%p, bar_tx=%d, bar_wait=%d: ?\n", 2843 __func__, 2844 tid, 2845 tid->bar_tx, 2846 tid->bar_wait); 2847 return; 2848 } 2849 2850 /* Don't do anything if we still have pending frames */ 2851 if (tid->hwq_depth > 0) { 2852 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2853 "%s: tid=%p, hwq_depth=%d, waiting\n", 2854 __func__, 2855 tid, 2856 tid->hwq_depth); 2857 return; 2858 } 2859 2860 /* We're now about to TX */ 2861 tid->bar_tx = 1; 2862 2863 /* 2864 * Calculate new BAW left edge, now that all frames have either 2865 * succeeded or failed. 2866 * 2867 * XXX verify this is _actually_ the valid value to begin at! 2868 */ 2869 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2870 "%s: tid=%p, new BAW left edge=%d\n", 2871 __func__, 2872 tid, 2873 tap->txa_start); 2874 2875 /* Try sending the BAR frame */ 2876 /* We can't hold the lock here! */ 2877 2878 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 2879 if (ieee80211_send_bar(&tid->an->an_node, tap, tap->txa_start) == 0) { 2880 /* Success? Now we wait for notification that it's done */ 2881 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 2882 return; 2883 } 2884 2885 /* Failure? For now, warn loudly and continue */ 2886 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 2887 device_printf(sc->sc_dev, "%s: tid=%p, failed to TX BAR, continue!\n", 2888 __func__, tid); 2889 ath_tx_tid_bar_unsuspend(sc, tid); 2890 } 2891 2892 2893 /* 2894 * Free any packets currently pending in the software TX queue. 2895 * 2896 * This will be called when a node is being deleted. 2897 * 2898 * It can also be called on an active node during an interface 2899 * reset or state transition. 2900 * 2901 * (From Linux/reference): 2902 * 2903 * TODO: For frame(s) that are in the retry state, we will reuse the 2904 * sequence number(s) without setting the retry bit. The 2905 * alternative is to give up on these and BAR the receiver's window 2906 * forward. 2907 */ 2908 static void 2909 ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an, 2910 struct ath_tid *tid, ath_bufhead *bf_cq) 2911 { 2912 struct ath_buf *bf; 2913 struct ieee80211_tx_ampdu *tap; 2914 struct ieee80211_node *ni = &an->an_node; 2915 int t = 0; 2916 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2917 2918 tap = ath_tx_get_tx_tid(an, tid->tid); 2919 2920 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2921 2922 /* Walk the queue, free frames */ 2923 for (;;) { 2924 bf = TAILQ_FIRST(&tid->axq_q); 2925 if (bf == NULL) { 2926 break; 2927 } 2928 2929 if (t == 0) { 2930 device_printf(sc->sc_dev, 2931 "%s: node %p: bf=%p: addbaw=%d, dobaw=%d, " 2932 "seqno=%d, retry=%d\n", 2933 __func__, ni, bf, 2934 bf->bf_state.bfs_addedbaw, 2935 bf->bf_state.bfs_dobaw, 2936 SEQNO(bf->bf_state.bfs_seqno), 2937 bf->bf_state.bfs_retries); 2938 device_printf(sc->sc_dev, 2939 "%s: node %p: bf=%p: tid txq_depth=%d hwq_depth=%d, bar_wait=%d\n", 2940 __func__, ni, bf, 2941 tid->axq_depth, 2942 tid->hwq_depth, 2943 tid->bar_wait); 2944 device_printf(sc->sc_dev, 2945 "%s: node %p: tid %d: txq_depth=%d, " 2946 "txq_aggr_depth=%d, sched=%d, paused=%d, " 2947 "hwq_depth=%d, incomp=%d, baw_head=%d, " 2948 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n", 2949 __func__, ni, tid->tid, txq->axq_depth, 2950 txq->axq_aggr_depth, tid->sched, tid->paused, 2951 tid->hwq_depth, tid->incomp, tid->baw_head, 2952 tid->baw_tail, tap == NULL ? -1 : tap->txa_start, 2953 ni->ni_txseqs[tid->tid]); 2954 2955 /* XXX Dump the frame, see what it is? */ 2956 ieee80211_dump_pkt(ni->ni_ic, 2957 mtod(bf->bf_m, const uint8_t *), 2958 bf->bf_m->m_len, 0, -1); 2959 2960 t = 1; 2961 } 2962 2963 2964 /* 2965 * If the current TID is running AMPDU, update 2966 * the BAW. 2967 */ 2968 if (ath_tx_ampdu_running(sc, an, tid->tid) && 2969 bf->bf_state.bfs_dobaw) { 2970 /* 2971 * Only remove the frame from the BAW if it's 2972 * been transmitted at least once; this means 2973 * the frame was in the BAW to begin with. 2974 */ 2975 if (bf->bf_state.bfs_retries > 0) { 2976 ath_tx_update_baw(sc, an, tid, bf); 2977 bf->bf_state.bfs_dobaw = 0; 2978 } 2979 /* 2980 * This has become a non-fatal error now 2981 */ 2982 if (! bf->bf_state.bfs_addedbaw) 2983 device_printf(sc->sc_dev, 2984 "%s: wasn't added: seqno %d\n", 2985 __func__, SEQNO(bf->bf_state.bfs_seqno)); 2986 } 2987 ATH_TXQ_REMOVE(tid, bf, bf_list); 2988 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list); 2989 } 2990 2991 /* 2992 * Now that it's completed, grab the TID lock and update 2993 * the sequence number and BAW window. 2994 * Because sequence numbers have been assigned to frames 2995 * that haven't been sent yet, it's entirely possible 2996 * we'll be called with some pending frames that have not 2997 * been transmitted. 2998 * 2999 * The cleaner solution is to do the sequence number allocation 3000 * when the packet is first transmitted - and thus the "retries" 3001 * check above would be enough to update the BAW/seqno. 3002 */ 3003 3004 /* But don't do it for non-QoS TIDs */ 3005 if (tap) { 3006 #if 0 3007 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3008 "%s: node %p: TID %d: sliding BAW left edge to %d\n", 3009 __func__, an, tid->tid, tap->txa_start); 3010 #endif 3011 ni->ni_txseqs[tid->tid] = tap->txa_start; 3012 tid->baw_tail = tid->baw_head; 3013 } 3014 } 3015 3016 /* 3017 * Flush all software queued packets for the given node. 3018 * 3019 * This occurs when a completion handler frees the last buffer 3020 * for a node, and the node is thus freed. This causes the node 3021 * to be cleaned up, which ends up calling ath_tx_node_flush. 3022 */ 3023 void 3024 ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an) 3025 { 3026 int tid; 3027 ath_bufhead bf_cq; 3028 struct ath_buf *bf; 3029 3030 TAILQ_INIT(&bf_cq); 3031 3032 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 3033 struct ath_tid *atid = &an->an_tid[tid]; 3034 struct ath_txq *txq = sc->sc_ac2q[atid->ac]; 3035 3036 /* Remove this tid from the list of active tids */ 3037 ATH_TXQ_LOCK(txq); 3038 ath_tx_tid_unsched(sc, atid); 3039 3040 /* Free packets */ 3041 ath_tx_tid_drain(sc, an, atid, &bf_cq); 3042 ATH_TXQ_UNLOCK(txq); 3043 } 3044 3045 /* Handle completed frames */ 3046 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3047 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3048 ath_tx_default_comp(sc, bf, 0); 3049 } 3050 } 3051 3052 /* 3053 * Drain all the software TXQs currently with traffic queued. 3054 */ 3055 void 3056 ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq) 3057 { 3058 struct ath_tid *tid; 3059 ath_bufhead bf_cq; 3060 struct ath_buf *bf; 3061 3062 TAILQ_INIT(&bf_cq); 3063 ATH_TXQ_LOCK(txq); 3064 3065 /* 3066 * Iterate over all active tids for the given txq, 3067 * flushing and unsched'ing them 3068 */ 3069 while (! TAILQ_EMPTY(&txq->axq_tidq)) { 3070 tid = TAILQ_FIRST(&txq->axq_tidq); 3071 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq); 3072 ath_tx_tid_unsched(sc, tid); 3073 } 3074 3075 ATH_TXQ_UNLOCK(txq); 3076 3077 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3078 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3079 ath_tx_default_comp(sc, bf, 0); 3080 } 3081 } 3082 3083 /* 3084 * Handle completion of non-aggregate session frames. 3085 */ 3086 void 3087 ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3088 { 3089 struct ieee80211_node *ni = bf->bf_node; 3090 struct ath_node *an = ATH_NODE(ni); 3091 int tid = bf->bf_state.bfs_tid; 3092 struct ath_tid *atid = &an->an_tid[tid]; 3093 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3094 3095 /* The TID state is protected behind the TXQ lock */ 3096 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3097 3098 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n", 3099 __func__, bf, fail, atid->hwq_depth - 1); 3100 3101 atid->hwq_depth--; 3102 if (atid->hwq_depth < 0) 3103 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3104 __func__, atid->hwq_depth); 3105 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3106 3107 /* 3108 * punt to rate control if we're not being cleaned up 3109 * during a hw queue drain and the frame wanted an ACK. 3110 */ 3111 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 3112 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3113 ts, bf->bf_state.bfs_pktlen, 3114 1, (ts->ts_status == 0) ? 0 : 1); 3115 3116 ath_tx_default_comp(sc, bf, fail); 3117 } 3118 3119 /* 3120 * Handle cleanup of aggregate session packets that aren't 3121 * an A-MPDU. 3122 * 3123 * There's no need to update the BAW here - the session is being 3124 * torn down. 3125 */ 3126 static void 3127 ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3128 { 3129 struct ieee80211_node *ni = bf->bf_node; 3130 struct ath_node *an = ATH_NODE(ni); 3131 int tid = bf->bf_state.bfs_tid; 3132 struct ath_tid *atid = &an->an_tid[tid]; 3133 3134 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n", 3135 __func__, tid, atid->incomp); 3136 3137 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3138 atid->incomp--; 3139 if (atid->incomp == 0) { 3140 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3141 "%s: TID %d: cleaned up! resume!\n", 3142 __func__, tid); 3143 atid->cleanup_inprogress = 0; 3144 ath_tx_tid_resume(sc, atid); 3145 } 3146 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3147 3148 ath_tx_default_comp(sc, bf, 0); 3149 } 3150 3151 /* 3152 * Performs transmit side cleanup when TID changes from aggregated to 3153 * unaggregated. 3154 * 3155 * - Discard all retry frames from the s/w queue. 3156 * - Fix the tx completion function for all buffers in s/w queue. 3157 * - Count the number of unacked frames, and let transmit completion 3158 * handle it later. 3159 * 3160 * The caller is responsible for pausing the TID. 3161 */ 3162 static void 3163 ath_tx_tid_cleanup(struct ath_softc *sc, struct ath_node *an, int tid) 3164 { 3165 struct ath_tid *atid = &an->an_tid[tid]; 3166 struct ieee80211_tx_ampdu *tap; 3167 struct ath_buf *bf, *bf_next; 3168 ath_bufhead bf_cq; 3169 3170 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 3171 "%s: TID %d: called\n", __func__, tid); 3172 3173 TAILQ_INIT(&bf_cq); 3174 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3175 3176 /* 3177 * Update the frames in the software TX queue: 3178 * 3179 * + Discard retry frames in the queue 3180 * + Fix the completion function to be non-aggregate 3181 */ 3182 bf = TAILQ_FIRST(&atid->axq_q); 3183 while (bf) { 3184 if (bf->bf_state.bfs_isretried) { 3185 bf_next = TAILQ_NEXT(bf, bf_list); 3186 TAILQ_REMOVE(&atid->axq_q, bf, bf_list); 3187 atid->axq_depth--; 3188 if (bf->bf_state.bfs_dobaw) { 3189 ath_tx_update_baw(sc, an, atid, bf); 3190 if (! bf->bf_state.bfs_addedbaw) 3191 device_printf(sc->sc_dev, 3192 "%s: wasn't added: seqno %d\n", 3193 __func__, 3194 SEQNO(bf->bf_state.bfs_seqno)); 3195 } 3196 bf->bf_state.bfs_dobaw = 0; 3197 /* 3198 * Call the default completion handler with "fail" just 3199 * so upper levels are suitably notified about this. 3200 */ 3201 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3202 bf = bf_next; 3203 continue; 3204 } 3205 /* Give these the default completion handler */ 3206 bf->bf_comp = ath_tx_normal_comp; 3207 bf = TAILQ_NEXT(bf, bf_list); 3208 } 3209 3210 /* The caller is required to pause the TID */ 3211 #if 0 3212 /* Pause the TID */ 3213 ath_tx_tid_pause(sc, atid); 3214 #endif 3215 3216 /* 3217 * Calculate what hardware-queued frames exist based 3218 * on the current BAW size. Ie, what frames have been 3219 * added to the TX hardware queue for this TID but 3220 * not yet ACKed. 3221 */ 3222 tap = ath_tx_get_tx_tid(an, tid); 3223 /* Need the lock - fiddling with BAW */ 3224 while (atid->baw_head != atid->baw_tail) { 3225 if (atid->tx_buf[atid->baw_head]) { 3226 atid->incomp++; 3227 atid->cleanup_inprogress = 1; 3228 atid->tx_buf[atid->baw_head] = NULL; 3229 } 3230 INCR(atid->baw_head, ATH_TID_MAX_BUFS); 3231 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 3232 } 3233 3234 /* 3235 * If cleanup is required, defer TID scheduling 3236 * until all the HW queued packets have been 3237 * sent. 3238 */ 3239 if (! atid->cleanup_inprogress) 3240 ath_tx_tid_resume(sc, atid); 3241 3242 if (atid->cleanup_inprogress) 3243 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3244 "%s: TID %d: cleanup needed: %d packets\n", 3245 __func__, tid, atid->incomp); 3246 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3247 3248 /* Handle completing frames and fail them */ 3249 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3250 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3251 ath_tx_default_comp(sc, bf, 1); 3252 } 3253 } 3254 3255 static void 3256 ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) 3257 { 3258 struct ieee80211_frame *wh; 3259 3260 wh = mtod(bf->bf_m, struct ieee80211_frame *); 3261 /* Only update/resync if needed */ 3262 if (bf->bf_state.bfs_isretried == 0) { 3263 wh->i_fc[1] |= IEEE80211_FC1_RETRY; 3264 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3265 BUS_DMASYNC_PREWRITE); 3266 } 3267 sc->sc_stats.ast_tx_swretries++; 3268 bf->bf_state.bfs_isretried = 1; 3269 bf->bf_state.bfs_retries ++; 3270 } 3271 3272 static struct ath_buf * 3273 ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 3274 struct ath_tid *tid, struct ath_buf *bf) 3275 { 3276 struct ath_buf *nbf; 3277 int error; 3278 3279 nbf = ath_buf_clone(sc, bf); 3280 3281 #if 0 3282 device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n", 3283 __func__); 3284 #endif 3285 3286 if (nbf == NULL) { 3287 /* Failed to clone */ 3288 device_printf(sc->sc_dev, 3289 "%s: failed to clone a busy buffer\n", 3290 __func__); 3291 return NULL; 3292 } 3293 3294 /* Setup the dma for the new buffer */ 3295 error = ath_tx_dmasetup(sc, nbf, nbf->bf_m); 3296 if (error != 0) { 3297 device_printf(sc->sc_dev, 3298 "%s: failed to setup dma for clone\n", 3299 __func__); 3300 /* 3301 * Put this at the head of the list, not tail; 3302 * that way it doesn't interfere with the 3303 * busy buffer logic (which uses the tail of 3304 * the list.) 3305 */ 3306 ATH_TXBUF_LOCK(sc); 3307 ath_returnbuf_head(sc, nbf); 3308 ATH_TXBUF_UNLOCK(sc); 3309 return NULL; 3310 } 3311 3312 /* Update BAW if required, before we free the original buf */ 3313 if (bf->bf_state.bfs_dobaw) 3314 ath_tx_switch_baw_buf(sc, an, tid, bf, nbf); 3315 3316 /* Free current buffer; return the older buffer */ 3317 bf->bf_m = NULL; 3318 bf->bf_node = NULL; 3319 ath_freebuf(sc, bf); 3320 return nbf; 3321 } 3322 3323 /* 3324 * Handle retrying an unaggregate frame in an aggregate 3325 * session. 3326 * 3327 * If too many retries occur, pause the TID, wait for 3328 * any further retransmits (as there's no reason why 3329 * non-aggregate frames in an aggregate session are 3330 * transmitted in-order; they just have to be in-BAW) 3331 * and then queue a BAR. 3332 */ 3333 static void 3334 ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3335 { 3336 struct ieee80211_node *ni = bf->bf_node; 3337 struct ath_node *an = ATH_NODE(ni); 3338 int tid = bf->bf_state.bfs_tid; 3339 struct ath_tid *atid = &an->an_tid[tid]; 3340 struct ieee80211_tx_ampdu *tap; 3341 3342 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3343 3344 tap = ath_tx_get_tx_tid(an, tid); 3345 3346 /* 3347 * If the buffer is marked as busy, we can't directly 3348 * reuse it. Instead, try to clone the buffer. 3349 * If the clone is successful, recycle the old buffer. 3350 * If the clone is unsuccessful, set bfs_retries to max 3351 * to force the next bit of code to free the buffer 3352 * for us. 3353 */ 3354 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3355 (bf->bf_flags & ATH_BUF_BUSY)) { 3356 struct ath_buf *nbf; 3357 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3358 if (nbf) 3359 /* bf has been freed at this point */ 3360 bf = nbf; 3361 else 3362 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3363 } 3364 3365 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3366 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3367 "%s: exceeded retries; seqno %d\n", 3368 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3369 sc->sc_stats.ast_tx_swretrymax++; 3370 3371 /* Update BAW anyway */ 3372 if (bf->bf_state.bfs_dobaw) { 3373 ath_tx_update_baw(sc, an, atid, bf); 3374 if (! bf->bf_state.bfs_addedbaw) 3375 device_printf(sc->sc_dev, 3376 "%s: wasn't added: seqno %d\n", 3377 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3378 } 3379 bf->bf_state.bfs_dobaw = 0; 3380 3381 /* Suspend the TX queue and get ready to send the BAR */ 3382 ath_tx_tid_bar_suspend(sc, atid); 3383 3384 /* Send the BAR if there are no other frames waiting */ 3385 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3386 ath_tx_tid_bar_tx(sc, atid); 3387 3388 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3389 3390 /* Free buffer, bf is free after this call */ 3391 ath_tx_default_comp(sc, bf, 0); 3392 return; 3393 } 3394 3395 /* 3396 * This increments the retry counter as well as 3397 * sets the retry flag in the ath_buf and packet 3398 * body. 3399 */ 3400 ath_tx_set_retry(sc, bf); 3401 3402 /* 3403 * Insert this at the head of the queue, so it's 3404 * retried before any current/subsequent frames. 3405 */ 3406 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3407 ath_tx_tid_sched(sc, atid); 3408 /* Send the BAR if there are no other frames waiting */ 3409 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3410 ath_tx_tid_bar_tx(sc, atid); 3411 3412 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3413 } 3414 3415 /* 3416 * Common code for aggregate excessive retry/subframe retry. 3417 * If retrying, queues buffers to bf_q. If not, frees the 3418 * buffers. 3419 * 3420 * XXX should unify this with ath_tx_aggr_retry_unaggr() 3421 */ 3422 static int 3423 ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf, 3424 ath_bufhead *bf_q) 3425 { 3426 struct ieee80211_node *ni = bf->bf_node; 3427 struct ath_node *an = ATH_NODE(ni); 3428 int tid = bf->bf_state.bfs_tid; 3429 struct ath_tid *atid = &an->an_tid[tid]; 3430 3431 ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[atid->ac]); 3432 3433 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3434 ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0); 3435 /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */ 3436 3437 /* 3438 * If the buffer is marked as busy, we can't directly 3439 * reuse it. Instead, try to clone the buffer. 3440 * If the clone is successful, recycle the old buffer. 3441 * If the clone is unsuccessful, set bfs_retries to max 3442 * to force the next bit of code to free the buffer 3443 * for us. 3444 */ 3445 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3446 (bf->bf_flags & ATH_BUF_BUSY)) { 3447 struct ath_buf *nbf; 3448 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3449 if (nbf) 3450 /* bf has been freed at this point */ 3451 bf = nbf; 3452 else 3453 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3454 } 3455 3456 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3457 sc->sc_stats.ast_tx_swretrymax++; 3458 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3459 "%s: max retries: seqno %d\n", 3460 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3461 ath_tx_update_baw(sc, an, atid, bf); 3462 if (! bf->bf_state.bfs_addedbaw) 3463 device_printf(sc->sc_dev, 3464 "%s: wasn't added: seqno %d\n", 3465 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3466 bf->bf_state.bfs_dobaw = 0; 3467 return 1; 3468 } 3469 3470 ath_tx_set_retry(sc, bf); 3471 bf->bf_next = NULL; /* Just to make sure */ 3472 3473 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 3474 return 0; 3475 } 3476 3477 /* 3478 * error pkt completion for an aggregate destination 3479 */ 3480 static void 3481 ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first, 3482 struct ath_tid *tid) 3483 { 3484 struct ieee80211_node *ni = bf_first->bf_node; 3485 struct ath_node *an = ATH_NODE(ni); 3486 struct ath_buf *bf_next, *bf; 3487 ath_bufhead bf_q; 3488 int drops = 0; 3489 struct ieee80211_tx_ampdu *tap; 3490 ath_bufhead bf_cq; 3491 3492 TAILQ_INIT(&bf_q); 3493 TAILQ_INIT(&bf_cq); 3494 3495 /* 3496 * Update rate control - all frames have failed. 3497 * 3498 * XXX use the length in the first frame in the series; 3499 * XXX just so things are consistent for now. 3500 */ 3501 ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc, 3502 &bf_first->bf_status.ds_txstat, 3503 bf_first->bf_state.bfs_pktlen, 3504 bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes); 3505 3506 ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 3507 tap = ath_tx_get_tx_tid(an, tid->tid); 3508 sc->sc_stats.ast_tx_aggr_failall++; 3509 3510 /* Retry all subframes */ 3511 bf = bf_first; 3512 while (bf) { 3513 bf_next = bf->bf_next; 3514 bf->bf_next = NULL; /* Remove it from the aggr list */ 3515 sc->sc_stats.ast_tx_aggr_fail++; 3516 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 3517 drops++; 3518 bf->bf_next = NULL; 3519 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3520 } 3521 bf = bf_next; 3522 } 3523 3524 /* Prepend all frames to the beginning of the queue */ 3525 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 3526 TAILQ_REMOVE(&bf_q, bf, bf_list); 3527 ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 3528 } 3529 3530 /* 3531 * Schedule the TID to be re-tried. 3532 */ 3533 ath_tx_tid_sched(sc, tid); 3534 3535 /* 3536 * send bar if we dropped any frames 3537 * 3538 * Keep the txq lock held for now, as we need to ensure 3539 * that ni_txseqs[] is consistent (as it's being updated 3540 * in the ifnet TX context or raw TX context.) 3541 */ 3542 if (drops) { 3543 /* Suspend the TX queue and get ready to send the BAR */ 3544 ath_tx_tid_bar_suspend(sc, tid); 3545 } 3546 3547 /* 3548 * Send BAR if required 3549 */ 3550 if (ath_tx_tid_bar_tx_ready(sc, tid)) 3551 ath_tx_tid_bar_tx(sc, tid); 3552 ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 3553 3554 /* Complete frames which errored out */ 3555 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3556 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3557 ath_tx_default_comp(sc, bf, 0); 3558 } 3559 } 3560 3561 /* 3562 * Handle clean-up of packets from an aggregate list. 3563 * 3564 * There's no need to update the BAW here - the session is being 3565 * torn down. 3566 */ 3567 static void 3568 ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first) 3569 { 3570 struct ath_buf *bf, *bf_next; 3571 struct ieee80211_node *ni = bf_first->bf_node; 3572 struct ath_node *an = ATH_NODE(ni); 3573 int tid = bf_first->bf_state.bfs_tid; 3574 struct ath_tid *atid = &an->an_tid[tid]; 3575 3576 bf = bf_first; 3577 3578 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3579 3580 /* update incomp */ 3581 while (bf) { 3582 atid->incomp--; 3583 bf = bf->bf_next; 3584 } 3585 3586 if (atid->incomp == 0) { 3587 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3588 "%s: TID %d: cleaned up! resume!\n", 3589 __func__, tid); 3590 atid->cleanup_inprogress = 0; 3591 ath_tx_tid_resume(sc, atid); 3592 } 3593 3594 /* Send BAR if required */ 3595 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3596 ath_tx_tid_bar_tx(sc, atid); 3597 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3598 3599 /* Handle frame completion */ 3600 while (bf) { 3601 bf_next = bf->bf_next; 3602 ath_tx_default_comp(sc, bf, 1); 3603 bf = bf_next; 3604 } 3605 } 3606 3607 /* 3608 * Handle completion of an set of aggregate frames. 3609 * 3610 * XXX for now, simply complete each sub-frame. 3611 * 3612 * Note: the completion handler is the last descriptor in the aggregate, 3613 * not the last descriptor in the first frame. 3614 */ 3615 static void 3616 ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first, 3617 int fail) 3618 { 3619 //struct ath_desc *ds = bf->bf_lastds; 3620 struct ieee80211_node *ni = bf_first->bf_node; 3621 struct ath_node *an = ATH_NODE(ni); 3622 int tid = bf_first->bf_state.bfs_tid; 3623 struct ath_tid *atid = &an->an_tid[tid]; 3624 struct ath_tx_status ts; 3625 struct ieee80211_tx_ampdu *tap; 3626 ath_bufhead bf_q; 3627 ath_bufhead bf_cq; 3628 int seq_st, tx_ok; 3629 int hasba, isaggr; 3630 uint32_t ba[2]; 3631 struct ath_buf *bf, *bf_next; 3632 int ba_index; 3633 int drops = 0; 3634 int nframes = 0, nbad = 0, nf; 3635 int pktlen; 3636 /* XXX there's too much on the stack? */ 3637 struct ath_rc_series rc[ATH_RC_NUM]; 3638 int txseq; 3639 3640 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n", 3641 __func__, atid->hwq_depth); 3642 3643 /* The TID state is kept behind the TXQ lock */ 3644 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3645 3646 atid->hwq_depth--; 3647 if (atid->hwq_depth < 0) 3648 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3649 __func__, atid->hwq_depth); 3650 3651 /* 3652 * Punt cleanup to the relevant function, not our problem now 3653 */ 3654 if (atid->cleanup_inprogress) { 3655 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3656 ath_tx_comp_cleanup_aggr(sc, bf_first); 3657 return; 3658 } 3659 3660 /* 3661 * Take a copy; this may be needed -after- bf_first 3662 * has been completed and freed. 3663 */ 3664 ts = bf_first->bf_status.ds_txstat; 3665 /* 3666 * XXX for now, use the first frame in the aggregate for 3667 * XXX rate control completion; it's at least consistent. 3668 */ 3669 pktlen = bf_first->bf_state.bfs_pktlen; 3670 3671 /* 3672 * Handle errors first! 3673 * 3674 * Here, handle _any_ error as a "exceeded retries" error. 3675 * Later on (when filtered frames are to be specially handled) 3676 * it'll have to be expanded. 3677 */ 3678 #if 0 3679 if (ts.ts_status & HAL_TXERR_XRETRY) { 3680 #endif 3681 if (ts.ts_status != 0) { 3682 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3683 ath_tx_comp_aggr_error(sc, bf_first, atid); 3684 return; 3685 } 3686 3687 TAILQ_INIT(&bf_q); 3688 TAILQ_INIT(&bf_cq); 3689 tap = ath_tx_get_tx_tid(an, tid); 3690 3691 /* 3692 * extract starting sequence and block-ack bitmap 3693 */ 3694 /* XXX endian-ness of seq_st, ba? */ 3695 seq_st = ts.ts_seqnum; 3696 hasba = !! (ts.ts_flags & HAL_TX_BA); 3697 tx_ok = (ts.ts_status == 0); 3698 isaggr = bf_first->bf_state.bfs_aggr; 3699 ba[0] = ts.ts_ba_low; 3700 ba[1] = ts.ts_ba_high; 3701 3702 /* 3703 * Copy the TX completion status and the rate control 3704 * series from the first descriptor, as it may be freed 3705 * before the rate control code can get its grubby fingers 3706 * into things. 3707 */ 3708 memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc)); 3709 3710 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3711 "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, " 3712 "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n", 3713 __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags, 3714 isaggr, seq_st, hasba, ba[0], ba[1]); 3715 3716 /* Occasionally, the MAC sends a tx status for the wrong TID. */ 3717 if (tid != ts.ts_tid) { 3718 device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n", 3719 __func__, tid, ts.ts_tid); 3720 tx_ok = 0; 3721 } 3722 3723 /* AR5416 BA bug; this requires an interface reset */ 3724 if (isaggr && tx_ok && (! hasba)) { 3725 device_printf(sc->sc_dev, 3726 "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, " 3727 "seq_st=%d\n", 3728 __func__, hasba, tx_ok, isaggr, seq_st); 3729 /* XXX TODO: schedule an interface reset */ 3730 #ifdef ATH_DEBUG 3731 ath_printtxbuf(sc, bf_first, 3732 sc->sc_ac2q[atid->ac]->axq_qnum, 0, 0); 3733 #endif 3734 } 3735 3736 /* 3737 * Walk the list of frames, figure out which ones were correctly 3738 * sent and which weren't. 3739 */ 3740 bf = bf_first; 3741 nf = bf_first->bf_state.bfs_nframes; 3742 3743 /* bf_first is going to be invalid once this list is walked */ 3744 bf_first = NULL; 3745 3746 /* 3747 * Walk the list of completed frames and determine 3748 * which need to be completed and which need to be 3749 * retransmitted. 3750 * 3751 * For completed frames, the completion functions need 3752 * to be called at the end of this function as the last 3753 * node reference may free the node. 3754 * 3755 * Finally, since the TXQ lock can't be held during the 3756 * completion callback (to avoid lock recursion), 3757 * the completion calls have to be done outside of the 3758 * lock. 3759 */ 3760 while (bf) { 3761 nframes++; 3762 ba_index = ATH_BA_INDEX(seq_st, 3763 SEQNO(bf->bf_state.bfs_seqno)); 3764 bf_next = bf->bf_next; 3765 bf->bf_next = NULL; /* Remove it from the aggr list */ 3766 3767 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3768 "%s: checking bf=%p seqno=%d; ack=%d\n", 3769 __func__, bf, SEQNO(bf->bf_state.bfs_seqno), 3770 ATH_BA_ISSET(ba, ba_index)); 3771 3772 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) { 3773 sc->sc_stats.ast_tx_aggr_ok++; 3774 ath_tx_update_baw(sc, an, atid, bf); 3775 bf->bf_state.bfs_dobaw = 0; 3776 if (! bf->bf_state.bfs_addedbaw) 3777 device_printf(sc->sc_dev, 3778 "%s: wasn't added: seqno %d\n", 3779 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3780 bf->bf_next = NULL; 3781 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3782 } else { 3783 sc->sc_stats.ast_tx_aggr_fail++; 3784 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 3785 drops++; 3786 bf->bf_next = NULL; 3787 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3788 } 3789 nbad++; 3790 } 3791 bf = bf_next; 3792 } 3793 3794 /* 3795 * Now that the BAW updates have been done, unlock 3796 * 3797 * txseq is grabbed before the lock is released so we 3798 * have a consistent view of what -was- in the BAW. 3799 * Anything after this point will not yet have been 3800 * TXed. 3801 */ 3802 txseq = tap->txa_start; 3803 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3804 3805 if (nframes != nf) 3806 device_printf(sc->sc_dev, 3807 "%s: num frames seen=%d; bf nframes=%d\n", 3808 __func__, nframes, nf); 3809 3810 /* 3811 * Now we know how many frames were bad, call the rate 3812 * control code. 3813 */ 3814 if (fail == 0) 3815 ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes, 3816 nbad); 3817 3818 /* 3819 * send bar if we dropped any frames 3820 */ 3821 if (drops) { 3822 /* Suspend the TX queue and get ready to send the BAR */ 3823 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3824 ath_tx_tid_bar_suspend(sc, atid); 3825 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3826 } 3827 3828 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3829 "%s: txa_start now %d\n", __func__, tap->txa_start); 3830 3831 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3832 3833 /* Prepend all frames to the beginning of the queue */ 3834 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 3835 TAILQ_REMOVE(&bf_q, bf, bf_list); 3836 ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3837 } 3838 3839 /* 3840 * Reschedule to grab some further frames. 3841 */ 3842 ath_tx_tid_sched(sc, atid); 3843 3844 /* 3845 * Send BAR if required 3846 */ 3847 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3848 ath_tx_tid_bar_tx(sc, atid); 3849 3850 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3851 3852 /* Do deferred completion */ 3853 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3854 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3855 ath_tx_default_comp(sc, bf, 0); 3856 } 3857 } 3858 3859 /* 3860 * Handle completion of unaggregated frames in an ADDBA 3861 * session. 3862 * 3863 * Fail is set to 1 if the entry is being freed via a call to 3864 * ath_tx_draintxq(). 3865 */ 3866 static void 3867 ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail) 3868 { 3869 struct ieee80211_node *ni = bf->bf_node; 3870 struct ath_node *an = ATH_NODE(ni); 3871 int tid = bf->bf_state.bfs_tid; 3872 struct ath_tid *atid = &an->an_tid[tid]; 3873 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3874 3875 /* 3876 * Update rate control status here, before we possibly 3877 * punt to retry or cleanup. 3878 * 3879 * Do it outside of the TXQ lock. 3880 */ 3881 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 3882 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3883 &bf->bf_status.ds_txstat, 3884 bf->bf_state.bfs_pktlen, 3885 1, (ts->ts_status == 0) ? 0 : 1); 3886 3887 /* 3888 * This is called early so atid->hwq_depth can be tracked. 3889 * This unfortunately means that it's released and regrabbed 3890 * during retry and cleanup. That's rather inefficient. 3891 */ 3892 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3893 3894 if (tid == IEEE80211_NONQOS_TID) 3895 device_printf(sc->sc_dev, "%s: TID=16!\n", __func__); 3896 3897 DPRINTF(sc, ATH_DEBUG_SW_TX, 3898 "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n", 3899 __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth, 3900 SEQNO(bf->bf_state.bfs_seqno)); 3901 3902 atid->hwq_depth--; 3903 if (atid->hwq_depth < 0) 3904 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3905 __func__, atid->hwq_depth); 3906 3907 /* 3908 * If a cleanup is in progress, punt to comp_cleanup; 3909 * rather than handling it here. It's thus their 3910 * responsibility to clean up, call the completion 3911 * function in net80211, etc. 3912 */ 3913 if (atid->cleanup_inprogress) { 3914 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3915 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n", 3916 __func__); 3917 ath_tx_comp_cleanup_unaggr(sc, bf); 3918 return; 3919 } 3920 3921 /* 3922 * Don't bother with the retry check if all frames 3923 * are being failed (eg during queue deletion.) 3924 */ 3925 #if 0 3926 if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) { 3927 #endif 3928 if (fail == 0 && ts->ts_status != 0) { 3929 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3930 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n", 3931 __func__); 3932 ath_tx_aggr_retry_unaggr(sc, bf); 3933 return; 3934 } 3935 3936 /* Success? Complete */ 3937 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n", 3938 __func__, tid, SEQNO(bf->bf_state.bfs_seqno)); 3939 if (bf->bf_state.bfs_dobaw) { 3940 ath_tx_update_baw(sc, an, atid, bf); 3941 bf->bf_state.bfs_dobaw = 0; 3942 if (! bf->bf_state.bfs_addedbaw) 3943 device_printf(sc->sc_dev, 3944 "%s: wasn't added: seqno %d\n", 3945 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3946 } 3947 3948 /* 3949 * Send BAR if required 3950 */ 3951 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3952 ath_tx_tid_bar_tx(sc, atid); 3953 3954 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3955 3956 ath_tx_default_comp(sc, bf, fail); 3957 /* bf is freed at this point */ 3958 } 3959 3960 void 3961 ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3962 { 3963 if (bf->bf_state.bfs_aggr) 3964 ath_tx_aggr_comp_aggr(sc, bf, fail); 3965 else 3966 ath_tx_aggr_comp_unaggr(sc, bf, fail); 3967 } 3968 3969 /* 3970 * Schedule some packets from the given node/TID to the hardware. 3971 * 3972 * This is the aggregate version. 3973 */ 3974 void 3975 ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an, 3976 struct ath_tid *tid) 3977 { 3978 struct ath_buf *bf; 3979 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 3980 struct ieee80211_tx_ampdu *tap; 3981 ATH_AGGR_STATUS status; 3982 ath_bufhead bf_q; 3983 3984 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid); 3985 ATH_TXQ_LOCK_ASSERT(txq); 3986 3987 tap = ath_tx_get_tx_tid(an, tid->tid); 3988 3989 if (tid->tid == IEEE80211_NONQOS_TID) 3990 device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n", 3991 __func__); 3992 3993 for (;;) { 3994 status = ATH_AGGR_DONE; 3995 3996 /* 3997 * If the upper layer has paused the TID, don't 3998 * queue any further packets. 3999 * 4000 * This can also occur from the completion task because 4001 * of packet loss; but as its serialised with this code, 4002 * it won't "appear" half way through queuing packets. 4003 */ 4004 if (tid->paused) 4005 break; 4006 4007 bf = TAILQ_FIRST(&tid->axq_q); 4008 if (bf == NULL) { 4009 break; 4010 } 4011 4012 /* 4013 * If the packet doesn't fall within the BAW (eg a NULL 4014 * data frame), schedule it directly; continue. 4015 */ 4016 if (! bf->bf_state.bfs_dobaw) { 4017 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4018 "%s: non-baw packet\n", 4019 __func__); 4020 ATH_TXQ_REMOVE(tid, bf, bf_list); 4021 bf->bf_state.bfs_aggr = 0; 4022 ath_tx_do_ratelookup(sc, bf); 4023 ath_tx_calc_duration(sc, bf); 4024 ath_tx_calc_protection(sc, bf); 4025 ath_tx_set_rtscts(sc, bf); 4026 ath_tx_rate_fill_rcflags(sc, bf); 4027 ath_tx_setds(sc, bf); 4028 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4029 4030 sc->sc_aggr_stats.aggr_nonbaw_pkt++; 4031 4032 /* Queue the packet; continue */ 4033 goto queuepkt; 4034 } 4035 4036 TAILQ_INIT(&bf_q); 4037 4038 /* 4039 * Do a rate control lookup on the first frame in the 4040 * list. The rate control code needs that to occur 4041 * before it can determine whether to TX. 4042 * It's inaccurate because the rate control code doesn't 4043 * really "do" aggregate lookups, so it only considers 4044 * the size of the first frame. 4045 */ 4046 ath_tx_do_ratelookup(sc, bf); 4047 bf->bf_state.bfs_rc[3].rix = 0; 4048 bf->bf_state.bfs_rc[3].tries = 0; 4049 4050 ath_tx_calc_duration(sc, bf); 4051 ath_tx_calc_protection(sc, bf); 4052 4053 ath_tx_set_rtscts(sc, bf); 4054 ath_tx_rate_fill_rcflags(sc, bf); 4055 4056 status = ath_tx_form_aggr(sc, an, tid, &bf_q); 4057 4058 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4059 "%s: ath_tx_form_aggr() status=%d\n", __func__, status); 4060 4061 /* 4062 * No frames to be picked up - out of BAW 4063 */ 4064 if (TAILQ_EMPTY(&bf_q)) 4065 break; 4066 4067 /* 4068 * This assumes that the descriptor list in the ath_bufhead 4069 * are already linked together via bf_next pointers. 4070 */ 4071 bf = TAILQ_FIRST(&bf_q); 4072 4073 if (status == ATH_AGGR_8K_LIMITED) 4074 sc->sc_aggr_stats.aggr_rts_aggr_limited++; 4075 4076 /* 4077 * If it's the only frame send as non-aggregate 4078 * assume that ath_tx_form_aggr() has checked 4079 * whether it's in the BAW and added it appropriately. 4080 */ 4081 if (bf->bf_state.bfs_nframes == 1) { 4082 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4083 "%s: single-frame aggregate\n", __func__); 4084 bf->bf_state.bfs_aggr = 0; 4085 ath_tx_setds(sc, bf); 4086 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4087 if (status == ATH_AGGR_BAW_CLOSED) 4088 sc->sc_aggr_stats.aggr_baw_closed_single_pkt++; 4089 else 4090 sc->sc_aggr_stats.aggr_single_pkt++; 4091 } else { 4092 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4093 "%s: multi-frame aggregate: %d frames, " 4094 "length %d\n", 4095 __func__, bf->bf_state.bfs_nframes, 4096 bf->bf_state.bfs_al); 4097 bf->bf_state.bfs_aggr = 1; 4098 sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++; 4099 sc->sc_aggr_stats.aggr_aggr_pkt++; 4100 4101 /* 4102 * Calculate the duration/protection as required. 4103 */ 4104 ath_tx_calc_duration(sc, bf); 4105 ath_tx_calc_protection(sc, bf); 4106 4107 /* 4108 * Update the rate and rtscts information based on the 4109 * rate decision made by the rate control code; 4110 * the first frame in the aggregate needs it. 4111 */ 4112 ath_tx_set_rtscts(sc, bf); 4113 4114 /* 4115 * Setup the relevant descriptor fields 4116 * for aggregation. The first descriptor 4117 * already points to the rest in the chain. 4118 */ 4119 ath_tx_setds_11n(sc, bf); 4120 4121 } 4122 queuepkt: 4123 //txq = bf->bf_state.bfs_txq; 4124 4125 /* Set completion handler, multi-frame aggregate or not */ 4126 bf->bf_comp = ath_tx_aggr_comp; 4127 4128 if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID) 4129 device_printf(sc->sc_dev, "%s: TID=16?\n", __func__); 4130 4131 /* Punt to txq */ 4132 ath_tx_handoff(sc, txq, bf); 4133 4134 /* Track outstanding buffer count to hardware */ 4135 /* aggregates are "one" buffer */ 4136 tid->hwq_depth++; 4137 4138 /* 4139 * Break out if ath_tx_form_aggr() indicated 4140 * there can't be any further progress (eg BAW is full.) 4141 * Checking for an empty txq is done above. 4142 * 4143 * XXX locking on txq here? 4144 */ 4145 if (txq->axq_aggr_depth >= sc->sc_hwq_limit || 4146 status == ATH_AGGR_BAW_CLOSED) 4147 break; 4148 } 4149 } 4150 4151 /* 4152 * Schedule some packets from the given node/TID to the hardware. 4153 */ 4154 void 4155 ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an, 4156 struct ath_tid *tid) 4157 { 4158 struct ath_buf *bf; 4159 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 4160 4161 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n", 4162 __func__, an, tid->tid); 4163 4164 ATH_TXQ_LOCK_ASSERT(txq); 4165 4166 /* Check - is AMPDU pending or running? then print out something */ 4167 if (ath_tx_ampdu_pending(sc, an, tid->tid)) 4168 device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n", 4169 __func__, tid->tid); 4170 if (ath_tx_ampdu_running(sc, an, tid->tid)) 4171 device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n", 4172 __func__, tid->tid); 4173 4174 for (;;) { 4175 4176 /* 4177 * If the upper layers have paused the TID, don't 4178 * queue any further packets. 4179 */ 4180 if (tid->paused) 4181 break; 4182 4183 bf = TAILQ_FIRST(&tid->axq_q); 4184 if (bf == NULL) { 4185 break; 4186 } 4187 4188 ATH_TXQ_REMOVE(tid, bf, bf_list); 4189 4190 KASSERT(txq == bf->bf_state.bfs_txq, ("txqs not equal!\n")); 4191 4192 /* Sanity check! */ 4193 if (tid->tid != bf->bf_state.bfs_tid) { 4194 device_printf(sc->sc_dev, "%s: bfs_tid %d !=" 4195 " tid %d\n", 4196 __func__, bf->bf_state.bfs_tid, tid->tid); 4197 } 4198 /* Normal completion handler */ 4199 bf->bf_comp = ath_tx_normal_comp; 4200 4201 /* Program descriptors + rate control */ 4202 ath_tx_do_ratelookup(sc, bf); 4203 ath_tx_calc_duration(sc, bf); 4204 ath_tx_calc_protection(sc, bf); 4205 ath_tx_set_rtscts(sc, bf); 4206 ath_tx_rate_fill_rcflags(sc, bf); 4207 ath_tx_setds(sc, bf); 4208 4209 /* Track outstanding buffer count to hardware */ 4210 /* aggregates are "one" buffer */ 4211 tid->hwq_depth++; 4212 4213 /* Punt to hardware or software txq */ 4214 ath_tx_handoff(sc, txq, bf); 4215 } 4216 } 4217 4218 /* 4219 * Schedule some packets to the given hardware queue. 4220 * 4221 * This function walks the list of TIDs (ie, ath_node TIDs 4222 * with queued traffic) and attempts to schedule traffic 4223 * from them. 4224 * 4225 * TID scheduling is implemented as a FIFO, with TIDs being 4226 * added to the end of the queue after some frames have been 4227 * scheduled. 4228 */ 4229 void 4230 ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq) 4231 { 4232 struct ath_tid *tid, *next, *last; 4233 4234 ATH_TXQ_LOCK_ASSERT(txq); 4235 4236 /* 4237 * Don't schedule if the hardware queue is busy. 4238 * This (hopefully) gives some more time to aggregate 4239 * some packets in the aggregation queue. 4240 */ 4241 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 4242 sc->sc_aggr_stats.aggr_sched_nopkt++; 4243 return; 4244 } 4245 4246 last = TAILQ_LAST(&txq->axq_tidq, axq_t_s); 4247 4248 TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) { 4249 /* 4250 * Suspend paused queues here; they'll be resumed 4251 * once the addba completes or times out. 4252 */ 4253 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n", 4254 __func__, tid->tid, tid->paused); 4255 ath_tx_tid_unsched(sc, tid); 4256 if (tid->paused) { 4257 continue; 4258 } 4259 if (ath_tx_ampdu_running(sc, tid->an, tid->tid)) 4260 ath_tx_tid_hw_queue_aggr(sc, tid->an, tid); 4261 else 4262 ath_tx_tid_hw_queue_norm(sc, tid->an, tid); 4263 4264 /* Not empty? Re-schedule */ 4265 if (tid->axq_depth != 0) 4266 ath_tx_tid_sched(sc, tid); 4267 4268 /* Give the software queue time to aggregate more packets */ 4269 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 4270 break; 4271 } 4272 4273 /* 4274 * If this was the last entry on the original list, stop. 4275 * Otherwise nodes that have been rescheduled onto the end 4276 * of the TID FIFO list will just keep being rescheduled. 4277 */ 4278 if (tid == last) 4279 break; 4280 } 4281 } 4282 4283 /* 4284 * TX addba handling 4285 */ 4286 4287 /* 4288 * Return net80211 TID struct pointer, or NULL for none 4289 */ 4290 struct ieee80211_tx_ampdu * 4291 ath_tx_get_tx_tid(struct ath_node *an, int tid) 4292 { 4293 struct ieee80211_node *ni = &an->an_node; 4294 struct ieee80211_tx_ampdu *tap; 4295 4296 if (tid == IEEE80211_NONQOS_TID) 4297 return NULL; 4298 4299 tap = &ni->ni_tx_ampdu[tid]; 4300 return tap; 4301 } 4302 4303 /* 4304 * Is AMPDU-TX running? 4305 */ 4306 static int 4307 ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid) 4308 { 4309 struct ieee80211_tx_ampdu *tap; 4310 4311 if (tid == IEEE80211_NONQOS_TID) 4312 return 0; 4313 4314 tap = ath_tx_get_tx_tid(an, tid); 4315 if (tap == NULL) 4316 return 0; /* Not valid; default to not running */ 4317 4318 return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING); 4319 } 4320 4321 /* 4322 * Is AMPDU-TX negotiation pending? 4323 */ 4324 static int 4325 ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid) 4326 { 4327 struct ieee80211_tx_ampdu *tap; 4328 4329 if (tid == IEEE80211_NONQOS_TID) 4330 return 0; 4331 4332 tap = ath_tx_get_tx_tid(an, tid); 4333 if (tap == NULL) 4334 return 0; /* Not valid; default to not pending */ 4335 4336 return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND); 4337 } 4338 4339 /* 4340 * Is AMPDU-TX pending for the given TID? 4341 */ 4342 4343 4344 /* 4345 * Method to handle sending an ADDBA request. 4346 * 4347 * We tap this so the relevant flags can be set to pause the TID 4348 * whilst waiting for the response. 4349 * 4350 * XXX there's no timeout handler we can override? 4351 */ 4352 int 4353 ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4354 int dialogtoken, int baparamset, int batimeout) 4355 { 4356 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4357 int tid = tap->txa_tid; 4358 struct ath_node *an = ATH_NODE(ni); 4359 struct ath_tid *atid = &an->an_tid[tid]; 4360 4361 /* 4362 * XXX danger Will Robinson! 4363 * 4364 * Although the taskqueue may be running and scheduling some more 4365 * packets, these should all be _before_ the addba sequence number. 4366 * However, net80211 will keep self-assigning sequence numbers 4367 * until addba has been negotiated. 4368 * 4369 * In the past, these packets would be "paused" (which still works 4370 * fine, as they're being scheduled to the driver in the same 4371 * serialised method which is calling the addba request routine) 4372 * and when the aggregation session begins, they'll be dequeued 4373 * as aggregate packets and added to the BAW. However, now there's 4374 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these 4375 * packets. Thus they never get included in the BAW tracking and 4376 * this can cause the initial burst of packets after the addba 4377 * negotiation to "hang", as they quickly fall outside the BAW. 4378 * 4379 * The "eventual" solution should be to tag these packets with 4380 * dobaw. Although net80211 has given us a sequence number, 4381 * it'll be "after" the left edge of the BAW and thus it'll 4382 * fall within it. 4383 */ 4384 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4385 /* 4386 * This is a bit annoying. Until net80211 HT code inherits some 4387 * (any) locking, we may have this called in parallel BUT only 4388 * one response/timeout will be called. Grr. 4389 */ 4390 if (atid->addba_tx_pending == 0) { 4391 ath_tx_tid_pause(sc, atid); 4392 atid->addba_tx_pending = 1; 4393 } 4394 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4395 4396 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4397 "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n", 4398 __func__, dialogtoken, baparamset, batimeout); 4399 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4400 "%s: txa_start=%d, ni_txseqs=%d\n", 4401 __func__, tap->txa_start, ni->ni_txseqs[tid]); 4402 4403 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 4404 batimeout); 4405 } 4406 4407 /* 4408 * Handle an ADDBA response. 4409 * 4410 * We unpause the queue so TX'ing can resume. 4411 * 4412 * Any packets TX'ed from this point should be "aggregate" (whether 4413 * aggregate or not) so the BAW is updated. 4414 * 4415 * Note! net80211 keeps self-assigning sequence numbers until 4416 * ampdu is negotiated. This means the initially-negotiated BAW left 4417 * edge won't match the ni->ni_txseq. 4418 * 4419 * So, being very dirty, the BAW left edge is "slid" here to match 4420 * ni->ni_txseq. 4421 * 4422 * What likely SHOULD happen is that all packets subsequent to the 4423 * addba request should be tagged as aggregate and queued as non-aggregate 4424 * frames; thus updating the BAW. For now though, I'll just slide the 4425 * window. 4426 */ 4427 int 4428 ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4429 int status, int code, int batimeout) 4430 { 4431 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4432 int tid = tap->txa_tid; 4433 struct ath_node *an = ATH_NODE(ni); 4434 struct ath_tid *atid = &an->an_tid[tid]; 4435 int r; 4436 4437 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4438 "%s: called; status=%d, code=%d, batimeout=%d\n", __func__, 4439 status, code, batimeout); 4440 4441 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4442 "%s: txa_start=%d, ni_txseqs=%d\n", 4443 __func__, tap->txa_start, ni->ni_txseqs[tid]); 4444 4445 /* 4446 * Call this first, so the interface flags get updated 4447 * before the TID is unpaused. Otherwise a race condition 4448 * exists where the unpaused TID still doesn't yet have 4449 * IEEE80211_AGGR_RUNNING set. 4450 */ 4451 r = sc->sc_addba_response(ni, tap, status, code, batimeout); 4452 4453 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4454 atid->addba_tx_pending = 0; 4455 /* 4456 * XXX dirty! 4457 * Slide the BAW left edge to wherever net80211 left it for us. 4458 * Read above for more information. 4459 */ 4460 tap->txa_start = ni->ni_txseqs[tid]; 4461 ath_tx_tid_resume(sc, atid); 4462 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4463 return r; 4464 } 4465 4466 4467 /* 4468 * Stop ADDBA on a queue. 4469 * 4470 * This can be called whilst BAR TX is currently active on the queue, 4471 * so make sure this is unblocked before continuing. 4472 */ 4473 void 4474 ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 4475 { 4476 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4477 int tid = tap->txa_tid; 4478 struct ath_node *an = ATH_NODE(ni); 4479 struct ath_tid *atid = &an->an_tid[tid]; 4480 4481 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__); 4482 4483 /* 4484 * Pause TID traffic early, so there aren't any races 4485 * Unblock the pending BAR held traffic, if it's currently paused. 4486 */ 4487 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4488 ath_tx_tid_pause(sc, atid); 4489 if (atid->bar_wait) { 4490 /* 4491 * bar_unsuspend() expects bar_tx == 1, as it should be 4492 * called from the TX completion path. This quietens 4493 * the warning. It's cleared for us anyway. 4494 */ 4495 atid->bar_tx = 1; 4496 ath_tx_tid_bar_unsuspend(sc, atid); 4497 } 4498 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4499 4500 /* There's no need to hold the TXQ lock here */ 4501 sc->sc_addba_stop(ni, tap); 4502 4503 /* 4504 * ath_tx_tid_cleanup will resume the TID if possible, otherwise 4505 * it'll set the cleanup flag, and it'll be unpaused once 4506 * things have been cleaned up. 4507 */ 4508 ath_tx_tid_cleanup(sc, an, tid); 4509 } 4510 4511 /* 4512 * Note: net80211 bar_timeout() doesn't call this function on BAR failure; 4513 * it simply tears down the aggregation session. Ew. 4514 * 4515 * It however will call ieee80211_ampdu_stop() which will call 4516 * ic->ic_addba_stop(). 4517 * 4518 * XXX This uses a hard-coded max BAR count value; the whole 4519 * XXX BAR TX success or failure should be better handled! 4520 */ 4521 void 4522 ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4523 int status) 4524 { 4525 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4526 int tid = tap->txa_tid; 4527 struct ath_node *an = ATH_NODE(ni); 4528 struct ath_tid *atid = &an->an_tid[tid]; 4529 int attempts = tap->txa_attempts; 4530 4531 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 4532 "%s: called; tap=%p, atid=%p, txa_tid=%d, atid->tid=%d, status=%d, attempts=%d\n", 4533 __func__, 4534 tap, 4535 atid, 4536 tap->txa_tid, 4537 atid->tid, 4538 status, 4539 attempts); 4540 4541 /* Note: This may update the BAW details */ 4542 sc->sc_bar_response(ni, tap, status); 4543 4544 /* Unpause the TID */ 4545 /* 4546 * XXX if this is attempt=50, the TID will be downgraded 4547 * XXX to a non-aggregate session. So we must unpause the 4548 * XXX TID here or it'll never be done. 4549 */ 4550 if (status == 0 || attempts == 50) { 4551 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4552 ath_tx_tid_bar_unsuspend(sc, atid); 4553 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4554 } 4555 } 4556 4557 /* 4558 * This is called whenever the pending ADDBA request times out. 4559 * Unpause and reschedule the TID. 4560 */ 4561 void 4562 ath_addba_response_timeout(struct ieee80211_node *ni, 4563 struct ieee80211_tx_ampdu *tap) 4564 { 4565 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 4566 int tid = tap->txa_tid; 4567 struct ath_node *an = ATH_NODE(ni); 4568 struct ath_tid *atid = &an->an_tid[tid]; 4569 4570 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4571 "%s: called; resuming\n", __func__); 4572 4573 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4574 atid->addba_tx_pending = 0; 4575 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4576 4577 /* Note: This updates the aggregate state to (again) pending */ 4578 sc->sc_addba_response_timeout(ni, tap); 4579 4580 /* Unpause the TID; which reschedules it */ 4581 ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4582 ath_tx_tid_resume(sc, atid); 4583 ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4584 } 4585 4586 static int 4587 ath_legacy_dma_txsetup(struct ath_softc *sc) 4588 { 4589 4590 /* nothing new needed */ 4591 return (0); 4592 } 4593 4594 static int 4595 ath_legacy_dma_txteardown(struct ath_softc *sc) 4596 { 4597 4598 /* nothing new needed */ 4599 return (0); 4600 } 4601 4602 void 4603 ath_xmit_setup_legacy(struct ath_softc *sc) 4604 { 4605 /* 4606 * For now, just set the descriptor length to sizeof(ath_desc); 4607 * worry about extracting the real length out of the HAL later. 4608 */ 4609 sc->sc_tx_desclen = sizeof(struct ath_desc); 4610 sc->sc_tx_statuslen = 0; 4611 sc->sc_tx_nmaps = 1; /* only one buffer per TX desc */ 4612 4613 sc->sc_tx.xmit_setup = ath_legacy_dma_txsetup; 4614 sc->sc_tx.xmit_teardown = ath_legacy_dma_txteardown; 4615 sc->sc_tx.xmit_attach_comp_func = ath_legacy_attach_comp_func; 4616 4617 sc->sc_tx.xmit_dma_restart = ath_legacy_tx_dma_restart; 4618 sc->sc_tx.xmit_handoff = ath_legacy_xmit_handoff; 4619 4620 sc->sc_tx.xmit_drain = ath_legacy_tx_drain; 4621 } 4622