1 /*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2010-2012 Adrian Chadd, Xenion Pty Ltd 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * Driver for the Atheros Wireless LAN controller. 36 * 37 * This software is derived from work of Atsushi Onoe; his contribution 38 * is greatly appreciated. 39 */ 40 41 #include "opt_inet.h" 42 #include "opt_ath.h" 43 #include "opt_wlan.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/sysctl.h> 48 #include <sys/mbuf.h> 49 #include <sys/malloc.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/kernel.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/errno.h> 56 #include <sys/callout.h> 57 #include <sys/bus.h> 58 #include <sys/endian.h> 59 #include <sys/kthread.h> 60 #include <sys/taskqueue.h> 61 #include <sys/priv.h> 62 63 #include <machine/bus.h> 64 65 #include <net/if.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_types.h> 69 #include <net/if_arp.h> 70 #include <net/ethernet.h> 71 #include <net/if_llc.h> 72 73 #include <net80211/ieee80211_var.h> 74 #include <net80211/ieee80211_regdomain.h> 75 #ifdef IEEE80211_SUPPORT_SUPERG 76 #include <net80211/ieee80211_superg.h> 77 #endif 78 #ifdef IEEE80211_SUPPORT_TDMA 79 #include <net80211/ieee80211_tdma.h> 80 #endif 81 #include <net80211/ieee80211_ht.h> 82 83 #include <net/bpf.h> 84 85 #ifdef INET 86 #include <netinet/in.h> 87 #include <netinet/if_ether.h> 88 #endif 89 90 #include <dev/ath/if_athvar.h> 91 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 92 #include <dev/ath/ath_hal/ah_diagcodes.h> 93 94 #include <dev/ath/if_ath_debug.h> 95 96 #ifdef ATH_TX99_DIAG 97 #include <dev/ath/ath_tx99/ath_tx99.h> 98 #endif 99 100 #include <dev/ath/if_ath_misc.h> 101 #include <dev/ath/if_ath_tx.h> 102 #include <dev/ath/if_ath_tx_ht.h> 103 104 #ifdef ATH_DEBUG_ALQ 105 #include <dev/ath/if_ath_alq.h> 106 #endif 107 108 /* 109 * How many retries to perform in software 110 */ 111 #define SWMAX_RETRIES 10 112 113 /* 114 * What queue to throw the non-QoS TID traffic into 115 */ 116 #define ATH_NONQOS_TID_AC WME_AC_VO 117 118 #if 0 119 static int ath_tx_node_is_asleep(struct ath_softc *sc, struct ath_node *an); 120 #endif 121 static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, 122 int tid); 123 static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, 124 int tid); 125 static ieee80211_seq ath_tx_tid_seqno_assign(struct ath_softc *sc, 126 struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0); 127 static int ath_tx_action_frame_override_queue(struct ath_softc *sc, 128 struct ieee80211_node *ni, struct mbuf *m0, int *tid); 129 static struct ath_buf * 130 ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 131 struct ath_tid *tid, struct ath_buf *bf); 132 133 #ifdef ATH_DEBUG_ALQ 134 void 135 ath_tx_alq_post(struct ath_softc *sc, struct ath_buf *bf_first) 136 { 137 struct ath_buf *bf; 138 int i, n; 139 const char *ds; 140 141 /* XXX we should skip out early if debugging isn't enabled! */ 142 bf = bf_first; 143 144 while (bf != NULL) { 145 /* XXX should ensure bf_nseg > 0! */ 146 if (bf->bf_nseg == 0) 147 break; 148 n = ((bf->bf_nseg - 1) / sc->sc_tx_nmaps) + 1; 149 for (i = 0, ds = (const char *) bf->bf_desc; 150 i < n; 151 i++, ds += sc->sc_tx_desclen) { 152 if_ath_alq_post(&sc->sc_alq, 153 ATH_ALQ_EDMA_TXDESC, 154 sc->sc_tx_desclen, 155 ds); 156 } 157 bf = bf->bf_next; 158 } 159 } 160 #endif /* ATH_DEBUG_ALQ */ 161 162 /* 163 * Whether to use the 11n rate scenario functions or not 164 */ 165 static inline int 166 ath_tx_is_11n(struct ath_softc *sc) 167 { 168 return ((sc->sc_ah->ah_magic == 0x20065416) || 169 (sc->sc_ah->ah_magic == 0x19741014)); 170 } 171 172 /* 173 * Obtain the current TID from the given frame. 174 * 175 * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.) 176 * This has implications for which AC/priority the packet is placed 177 * in. 178 */ 179 static int 180 ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0) 181 { 182 const struct ieee80211_frame *wh; 183 int pri = M_WME_GETAC(m0); 184 185 wh = mtod(m0, const struct ieee80211_frame *); 186 if (! IEEE80211_QOS_HAS_SEQ(wh)) 187 return IEEE80211_NONQOS_TID; 188 else 189 return WME_AC_TO_TID(pri); 190 } 191 192 static void 193 ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) 194 { 195 struct ieee80211_frame *wh; 196 197 wh = mtod(bf->bf_m, struct ieee80211_frame *); 198 /* Only update/resync if needed */ 199 if (bf->bf_state.bfs_isretried == 0) { 200 wh->i_fc[1] |= IEEE80211_FC1_RETRY; 201 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 202 BUS_DMASYNC_PREWRITE); 203 } 204 bf->bf_state.bfs_isretried = 1; 205 bf->bf_state.bfs_retries ++; 206 } 207 208 /* 209 * Determine what the correct AC queue for the given frame 210 * should be. 211 * 212 * This code assumes that the TIDs map consistently to 213 * the underlying hardware (or software) ath_txq. 214 * Since the sender may try to set an AC which is 215 * arbitrary, non-QoS TIDs may end up being put on 216 * completely different ACs. There's no way to put a 217 * TID into multiple ath_txq's for scheduling, so 218 * for now we override the AC/TXQ selection and set 219 * non-QOS TID frames into the BE queue. 220 * 221 * This may be completely incorrect - specifically, 222 * some management frames may end up out of order 223 * compared to the QoS traffic they're controlling. 224 * I'll look into this later. 225 */ 226 static int 227 ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0) 228 { 229 const struct ieee80211_frame *wh; 230 int pri = M_WME_GETAC(m0); 231 wh = mtod(m0, const struct ieee80211_frame *); 232 if (IEEE80211_QOS_HAS_SEQ(wh)) 233 return pri; 234 235 return ATH_NONQOS_TID_AC; 236 } 237 238 void 239 ath_txfrag_cleanup(struct ath_softc *sc, 240 ath_bufhead *frags, struct ieee80211_node *ni) 241 { 242 struct ath_buf *bf, *next; 243 244 ATH_TXBUF_LOCK_ASSERT(sc); 245 246 TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 247 /* NB: bf assumed clean */ 248 TAILQ_REMOVE(frags, bf, bf_list); 249 ath_returnbuf_head(sc, bf); 250 ieee80211_node_decref(ni); 251 } 252 } 253 254 /* 255 * Setup xmit of a fragmented frame. Allocate a buffer 256 * for each frag and bump the node reference count to 257 * reflect the held reference to be setup by ath_tx_start. 258 */ 259 int 260 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 261 struct mbuf *m0, struct ieee80211_node *ni) 262 { 263 struct mbuf *m; 264 struct ath_buf *bf; 265 266 ATH_TXBUF_LOCK(sc); 267 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 268 /* XXX non-management? */ 269 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 270 if (bf == NULL) { /* out of buffers, cleanup */ 271 device_printf(sc->sc_dev, "%s: no buffer?\n", 272 __func__); 273 ath_txfrag_cleanup(sc, frags, ni); 274 break; 275 } 276 ieee80211_node_incref(ni); 277 TAILQ_INSERT_TAIL(frags, bf, bf_list); 278 } 279 ATH_TXBUF_UNLOCK(sc); 280 281 return !TAILQ_EMPTY(frags); 282 } 283 284 /* 285 * Reclaim mbuf resources. For fragmented frames we 286 * need to claim each frag chained with m_nextpkt. 287 */ 288 void 289 ath_freetx(struct mbuf *m) 290 { 291 struct mbuf *next; 292 293 do { 294 next = m->m_nextpkt; 295 m->m_nextpkt = NULL; 296 m_freem(m); 297 } while ((m = next) != NULL); 298 } 299 300 static int 301 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 302 { 303 struct mbuf *m; 304 int error; 305 306 /* 307 * Load the DMA map so any coalescing is done. This 308 * also calculates the number of descriptors we need. 309 */ 310 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 311 bf->bf_segs, &bf->bf_nseg, 312 BUS_DMA_NOWAIT); 313 if (error == EFBIG) { 314 /* XXX packet requires too many descriptors */ 315 bf->bf_nseg = ATH_MAX_SCATTER + 1; 316 } else if (error != 0) { 317 sc->sc_stats.ast_tx_busdma++; 318 ath_freetx(m0); 319 return error; 320 } 321 /* 322 * Discard null packets and check for packets that 323 * require too many TX descriptors. We try to convert 324 * the latter to a cluster. 325 */ 326 if (bf->bf_nseg > ATH_MAX_SCATTER) { /* too many desc's, linearize */ 327 sc->sc_stats.ast_tx_linear++; 328 m = m_collapse(m0, M_NOWAIT, ATH_MAX_SCATTER); 329 if (m == NULL) { 330 ath_freetx(m0); 331 sc->sc_stats.ast_tx_nombuf++; 332 return ENOMEM; 333 } 334 m0 = m; 335 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 336 bf->bf_segs, &bf->bf_nseg, 337 BUS_DMA_NOWAIT); 338 if (error != 0) { 339 sc->sc_stats.ast_tx_busdma++; 340 ath_freetx(m0); 341 return error; 342 } 343 KASSERT(bf->bf_nseg <= ATH_MAX_SCATTER, 344 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 345 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 346 sc->sc_stats.ast_tx_nodata++; 347 ath_freetx(m0); 348 return EIO; 349 } 350 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 351 __func__, m0, m0->m_pkthdr.len); 352 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 353 bf->bf_m = m0; 354 355 return 0; 356 } 357 358 /* 359 * Chain together segments+descriptors for a frame - 11n or otherwise. 360 * 361 * For aggregates, this is called on each frame in the aggregate. 362 */ 363 static void 364 ath_tx_chaindesclist(struct ath_softc *sc, struct ath_desc *ds0, 365 struct ath_buf *bf, int is_aggr, int is_first_subframe, 366 int is_last_subframe) 367 { 368 struct ath_hal *ah = sc->sc_ah; 369 char *ds; 370 int i, bp, dsp; 371 HAL_DMA_ADDR bufAddrList[4]; 372 uint32_t segLenList[4]; 373 int numTxMaps = 1; 374 int isFirstDesc = 1; 375 376 /* 377 * XXX There's txdma and txdma_mgmt; the descriptor 378 * sizes must match. 379 */ 380 struct ath_descdma *dd = &sc->sc_txdma; 381 382 /* 383 * Fillin the remainder of the descriptor info. 384 */ 385 386 /* 387 * We need the number of TX data pointers in each descriptor. 388 * EDMA and later chips support 4 TX buffers per descriptor; 389 * previous chips just support one. 390 */ 391 numTxMaps = sc->sc_tx_nmaps; 392 393 /* 394 * For EDMA and later chips ensure the TX map is fully populated 395 * before advancing to the next descriptor. 396 */ 397 ds = (char *) bf->bf_desc; 398 bp = dsp = 0; 399 bzero(bufAddrList, sizeof(bufAddrList)); 400 bzero(segLenList, sizeof(segLenList)); 401 for (i = 0; i < bf->bf_nseg; i++) { 402 bufAddrList[bp] = bf->bf_segs[i].ds_addr; 403 segLenList[bp] = bf->bf_segs[i].ds_len; 404 bp++; 405 406 /* 407 * Go to the next segment if this isn't the last segment 408 * and there's space in the current TX map. 409 */ 410 if ((i != bf->bf_nseg - 1) && (bp < numTxMaps)) 411 continue; 412 413 /* 414 * Last segment or we're out of buffer pointers. 415 */ 416 bp = 0; 417 418 if (i == bf->bf_nseg - 1) 419 ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 0); 420 else 421 ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 422 bf->bf_daddr + dd->dd_descsize * (dsp + 1)); 423 424 /* 425 * XXX This assumes that bfs_txq is the actual destination 426 * hardware queue at this point. It may not have been 427 * assigned, it may actually be pointing to the multicast 428 * software TXQ id. These must be fixed! 429 */ 430 ath_hal_filltxdesc(ah, (struct ath_desc *) ds 431 , bufAddrList 432 , segLenList 433 , bf->bf_descid /* XXX desc id */ 434 , bf->bf_state.bfs_tx_queue 435 , isFirstDesc /* first segment */ 436 , i == bf->bf_nseg - 1 /* last segment */ 437 , (struct ath_desc *) ds0 /* first descriptor */ 438 ); 439 440 /* 441 * Make sure the 11n aggregate fields are cleared. 442 * 443 * XXX TODO: this doesn't need to be called for 444 * aggregate frames; as it'll be called on all 445 * sub-frames. Since the descriptors are in 446 * non-cacheable memory, this leads to some 447 * rather slow writes on MIPS/ARM platforms. 448 */ 449 if (ath_tx_is_11n(sc)) 450 ath_hal_clr11n_aggr(sc->sc_ah, (struct ath_desc *) ds); 451 452 /* 453 * If 11n is enabled, set it up as if it's an aggregate 454 * frame. 455 */ 456 if (is_last_subframe) { 457 ath_hal_set11n_aggr_last(sc->sc_ah, 458 (struct ath_desc *) ds); 459 } else if (is_aggr) { 460 /* 461 * This clears the aggrlen field; so 462 * the caller needs to call set_aggr_first()! 463 * 464 * XXX TODO: don't call this for the first 465 * descriptor in the first frame in an 466 * aggregate! 467 */ 468 ath_hal_set11n_aggr_middle(sc->sc_ah, 469 (struct ath_desc *) ds, 470 bf->bf_state.bfs_ndelim); 471 } 472 isFirstDesc = 0; 473 bf->bf_lastds = (struct ath_desc *) ds; 474 475 /* 476 * Don't forget to skip to the next descriptor. 477 */ 478 ds += sc->sc_tx_desclen; 479 dsp++; 480 481 /* 482 * .. and don't forget to blank these out! 483 */ 484 bzero(bufAddrList, sizeof(bufAddrList)); 485 bzero(segLenList, sizeof(segLenList)); 486 } 487 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 488 } 489 490 /* 491 * Set the rate control fields in the given descriptor based on 492 * the bf_state fields and node state. 493 * 494 * The bfs fields should already be set with the relevant rate 495 * control information, including whether MRR is to be enabled. 496 * 497 * Since the FreeBSD HAL currently sets up the first TX rate 498 * in ath_hal_setuptxdesc(), this will setup the MRR 499 * conditionally for the pre-11n chips, and call ath_buf_set_rate 500 * unconditionally for 11n chips. These require the 11n rate 501 * scenario to be set if MCS rates are enabled, so it's easier 502 * to just always call it. The caller can then only set rates 2, 3 503 * and 4 if multi-rate retry is needed. 504 */ 505 static void 506 ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 507 struct ath_buf *bf) 508 { 509 struct ath_rc_series *rc = bf->bf_state.bfs_rc; 510 511 /* If mrr is disabled, blank tries 1, 2, 3 */ 512 if (! bf->bf_state.bfs_ismrr) 513 rc[1].tries = rc[2].tries = rc[3].tries = 0; 514 515 #if 0 516 /* 517 * If NOACK is set, just set ntries=1. 518 */ 519 else if (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) { 520 rc[1].tries = rc[2].tries = rc[3].tries = 0; 521 rc[0].tries = 1; 522 } 523 #endif 524 525 /* 526 * Always call - that way a retried descriptor will 527 * have the MRR fields overwritten. 528 * 529 * XXX TODO: see if this is really needed - setting up 530 * the first descriptor should set the MRR fields to 0 531 * for us anyway. 532 */ 533 if (ath_tx_is_11n(sc)) { 534 ath_buf_set_rate(sc, ni, bf); 535 } else { 536 ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc 537 , rc[1].ratecode, rc[1].tries 538 , rc[2].ratecode, rc[2].tries 539 , rc[3].ratecode, rc[3].tries 540 ); 541 } 542 } 543 544 /* 545 * Setup segments+descriptors for an 11n aggregate. 546 * bf_first is the first buffer in the aggregate. 547 * The descriptor list must already been linked together using 548 * bf->bf_next. 549 */ 550 static void 551 ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first) 552 { 553 struct ath_buf *bf, *bf_prev = NULL; 554 struct ath_desc *ds0 = bf_first->bf_desc; 555 556 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n", 557 __func__, bf_first->bf_state.bfs_nframes, 558 bf_first->bf_state.bfs_al); 559 560 bf = bf_first; 561 562 if (bf->bf_state.bfs_txrate0 == 0) 563 device_printf(sc->sc_dev, "%s: bf=%p, txrate0=%d\n", 564 __func__, bf, 0); 565 if (bf->bf_state.bfs_rc[0].ratecode == 0) 566 device_printf(sc->sc_dev, "%s: bf=%p, rix0=%d\n", 567 __func__, bf, 0); 568 569 /* 570 * Setup all descriptors of all subframes - this will 571 * call ath_hal_set11naggrmiddle() on every frame. 572 */ 573 while (bf != NULL) { 574 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 575 "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n", 576 __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen, 577 SEQNO(bf->bf_state.bfs_seqno)); 578 579 /* 580 * Setup the initial fields for the first descriptor - all 581 * the non-11n specific stuff. 582 */ 583 ath_hal_setuptxdesc(sc->sc_ah, bf->bf_desc 584 , bf->bf_state.bfs_pktlen /* packet length */ 585 , bf->bf_state.bfs_hdrlen /* header length */ 586 , bf->bf_state.bfs_atype /* Atheros packet type */ 587 , bf->bf_state.bfs_txpower /* txpower */ 588 , bf->bf_state.bfs_txrate0 589 , bf->bf_state.bfs_try0 /* series 0 rate/tries */ 590 , bf->bf_state.bfs_keyix /* key cache index */ 591 , bf->bf_state.bfs_txantenna /* antenna mode */ 592 , bf->bf_state.bfs_txflags | HAL_TXDESC_INTREQ /* flags */ 593 , bf->bf_state.bfs_ctsrate /* rts/cts rate */ 594 , bf->bf_state.bfs_ctsduration /* rts/cts duration */ 595 ); 596 597 /* 598 * First descriptor? Setup the rate control and initial 599 * aggregate header information. 600 */ 601 if (bf == bf_first) { 602 /* 603 * setup first desc with rate and aggr info 604 */ 605 ath_tx_set_ratectrl(sc, bf->bf_node, bf); 606 } 607 608 /* 609 * Setup the descriptors for a multi-descriptor frame. 610 * This is both aggregate and non-aggregate aware. 611 */ 612 ath_tx_chaindesclist(sc, ds0, bf, 613 1, /* is_aggr */ 614 !! (bf == bf_first), /* is_first_subframe */ 615 !! (bf->bf_next == NULL) /* is_last_subframe */ 616 ); 617 618 if (bf == bf_first) { 619 /* 620 * Initialise the first 11n aggregate with the 621 * aggregate length and aggregate enable bits. 622 */ 623 ath_hal_set11n_aggr_first(sc->sc_ah, 624 ds0, 625 bf->bf_state.bfs_al, 626 bf->bf_state.bfs_ndelim); 627 } 628 629 /* 630 * Link the last descriptor of the previous frame 631 * to the beginning descriptor of this frame. 632 */ 633 if (bf_prev != NULL) 634 ath_hal_settxdesclink(sc->sc_ah, bf_prev->bf_lastds, 635 bf->bf_daddr); 636 637 /* Save a copy so we can link the next descriptor in */ 638 bf_prev = bf; 639 bf = bf->bf_next; 640 } 641 642 /* 643 * Set the first descriptor bf_lastds field to point to 644 * the last descriptor in the last subframe, that's where 645 * the status update will occur. 646 */ 647 bf_first->bf_lastds = bf_prev->bf_lastds; 648 649 /* 650 * And bf_last in the first descriptor points to the end of 651 * the aggregate list. 652 */ 653 bf_first->bf_last = bf_prev; 654 655 /* 656 * For non-AR9300 NICs, which require the rate control 657 * in the final descriptor - let's set that up now. 658 * 659 * This is because the filltxdesc() HAL call doesn't 660 * populate the last segment with rate control information 661 * if firstSeg is also true. For non-aggregate frames 662 * that is fine, as the first frame already has rate control 663 * info. But if the last frame in an aggregate has one 664 * descriptor, both firstseg and lastseg will be true and 665 * the rate info isn't copied. 666 * 667 * This is inefficient on MIPS/ARM platforms that have 668 * non-cachable memory for TX descriptors, but we'll just 669 * make do for now. 670 * 671 * As to why the rate table is stashed in the last descriptor 672 * rather than the first descriptor? Because proctxdesc() 673 * is called on the final descriptor in an MPDU or A-MPDU - 674 * ie, the one that gets updated by the hardware upon 675 * completion. That way proctxdesc() doesn't need to know 676 * about the first _and_ last TX descriptor. 677 */ 678 ath_hal_setuplasttxdesc(sc->sc_ah, bf_prev->bf_lastds, ds0); 679 680 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__); 681 } 682 683 /* 684 * Hand-off a frame to the multicast TX queue. 685 * 686 * This is a software TXQ which will be appended to the CAB queue 687 * during the beacon setup code. 688 * 689 * XXX TODO: since the AR9300 EDMA TX queue support wants the QCU ID 690 * as part of the TX descriptor, bf_state.bfs_tx_queue must be updated 691 * with the actual hardware txq, or all of this will fall apart. 692 * 693 * XXX It may not be a bad idea to just stuff the QCU ID into bf_state 694 * and retire bfs_tx_queue; then make sure the CABQ QCU ID is populated 695 * correctly. 696 */ 697 static void 698 ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 699 struct ath_buf *bf) 700 { 701 ATH_TX_LOCK_ASSERT(sc); 702 703 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 704 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 705 706 ATH_TXQ_LOCK(txq); 707 if (ATH_TXQ_LAST(txq, axq_q_s) != NULL) { 708 struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s); 709 struct ieee80211_frame *wh; 710 711 /* mark previous frame */ 712 wh = mtod(bf_last->bf_m, struct ieee80211_frame *); 713 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 714 bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap, 715 BUS_DMASYNC_PREWRITE); 716 717 /* link descriptor */ 718 ath_hal_settxdesclink(sc->sc_ah, 719 bf_last->bf_lastds, 720 bf->bf_daddr); 721 } 722 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 723 ATH_TXQ_UNLOCK(txq); 724 } 725 726 /* 727 * Hand-off packet to a hardware queue. 728 */ 729 static void 730 ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 731 struct ath_buf *bf) 732 { 733 struct ath_hal *ah = sc->sc_ah; 734 735 /* 736 * Insert the frame on the outbound list and pass it on 737 * to the hardware. Multicast frames buffered for power 738 * save stations and transmit from the CAB queue are stored 739 * on a s/w only queue and loaded on to the CAB queue in 740 * the SWBA handler since frames only go out on DTIM and 741 * to avoid possible races. 742 */ 743 ATH_TX_LOCK_ASSERT(sc); 744 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 745 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 746 KASSERT(txq->axq_qnum != ATH_TXQ_SWQ, 747 ("ath_tx_handoff_hw called for mcast queue")); 748 749 #if 0 750 /* 751 * This causes a LOR. Find out where the PCU lock is being 752 * held whilst the TXQ lock is grabbed - that shouldn't 753 * be occuring. 754 */ 755 ATH_PCU_LOCK(sc); 756 if (sc->sc_inreset_cnt) { 757 ATH_PCU_UNLOCK(sc); 758 DPRINTF(sc, ATH_DEBUG_RESET, 759 "%s: called with sc_in_reset != 0\n", 760 __func__); 761 DPRINTF(sc, ATH_DEBUG_XMIT, 762 "%s: queued: TXDP[%u] = %p (%p) depth %d\n", 763 __func__, txq->axq_qnum, 764 (caddr_t)bf->bf_daddr, bf->bf_desc, 765 txq->axq_depth); 766 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 767 if (bf->bf_state.bfs_aggr) 768 txq->axq_aggr_depth++; 769 /* 770 * There's no need to update axq_link; the hardware 771 * is in reset and once the reset is complete, any 772 * non-empty queues will simply have DMA restarted. 773 */ 774 return; 775 } 776 ATH_PCU_UNLOCK(sc); 777 #endif 778 779 /* For now, so not to generate whitespace diffs */ 780 if (1) { 781 ATH_TXQ_LOCK(txq); 782 #ifdef IEEE80211_SUPPORT_TDMA 783 int qbusy; 784 785 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 786 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 787 788 ATH_KTR(sc, ATH_KTR_TX, 4, 789 "ath_tx_handoff: txq=%u, add bf=%p, qbusy=%d, depth=%d", 790 txq->axq_qnum, bf, qbusy, txq->axq_depth); 791 if (txq->axq_link == NULL) { 792 /* 793 * Be careful writing the address to TXDP. If 794 * the tx q is enabled then this write will be 795 * ignored. Normally this is not an issue but 796 * when tdma is in use and the q is beacon gated 797 * this race can occur. If the q is busy then 798 * defer the work to later--either when another 799 * packet comes along or when we prepare a beacon 800 * frame at SWBA. 801 */ 802 if (!qbusy) { 803 ath_hal_puttxbuf(ah, txq->axq_qnum, 804 bf->bf_daddr); 805 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 806 DPRINTF(sc, ATH_DEBUG_XMIT, 807 "%s: TXDP[%u] = %p (%p) lastds=%p depth %d\n", 808 __func__, txq->axq_qnum, 809 (caddr_t)bf->bf_daddr, bf->bf_desc, 810 bf->bf_lastds, 811 txq->axq_depth); 812 ATH_KTR(sc, ATH_KTR_TX, 5, 813 "ath_tx_handoff: TXDP[%u] = %p (%p) " 814 "lastds=%p depth %d", 815 txq->axq_qnum, 816 (caddr_t)bf->bf_daddr, bf->bf_desc, 817 bf->bf_lastds, 818 txq->axq_depth); 819 } else { 820 txq->axq_flags |= ATH_TXQ_PUTPENDING; 821 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 822 "%s: Q%u busy, defer enable\n", __func__, 823 txq->axq_qnum); 824 ATH_KTR(sc, ATH_KTR_TX, 0, "defer enable"); 825 } 826 } else { 827 *txq->axq_link = bf->bf_daddr; 828 DPRINTF(sc, ATH_DEBUG_XMIT, 829 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 830 txq->axq_qnum, txq->axq_link, 831 (caddr_t)bf->bf_daddr, bf->bf_desc, 832 txq->axq_depth); 833 ATH_KTR(sc, ATH_KTR_TX, 5, 834 "ath_tx_handoff: link[%u](%p)=%p (%p) lastds=%p", 835 txq->axq_qnum, txq->axq_link, 836 (caddr_t)bf->bf_daddr, bf->bf_desc, 837 bf->bf_lastds); 838 839 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) { 840 /* 841 * The q was busy when we previously tried 842 * to write the address of the first buffer 843 * in the chain. Since it's not busy now 844 * handle this chore. We are certain the 845 * buffer at the front is the right one since 846 * axq_link is NULL only when the buffer list 847 * is/was empty. 848 */ 849 ath_hal_puttxbuf(ah, txq->axq_qnum, 850 TAILQ_FIRST(&txq->axq_q)->bf_daddr); 851 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 852 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 853 "%s: Q%u restarted\n", __func__, 854 txq->axq_qnum); 855 ATH_KTR(sc, ATH_KTR_TX, 4, 856 "ath_tx_handoff: txq[%d] restarted, bf=%p " 857 "daddr=%p ds=%p", 858 txq->axq_qnum, 859 bf, 860 (caddr_t)bf->bf_daddr, 861 bf->bf_desc); 862 } 863 } 864 #else 865 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 866 ATH_KTR(sc, ATH_KTR_TX, 3, 867 "ath_tx_handoff: non-tdma: txq=%u, add bf=%p " 868 "depth=%d", 869 txq->axq_qnum, 870 bf, 871 txq->axq_depth); 872 if (txq->axq_link == NULL) { 873 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 874 DPRINTF(sc, ATH_DEBUG_XMIT, 875 "%s: TXDP[%u] = %p (%p) depth %d\n", 876 __func__, txq->axq_qnum, 877 (caddr_t)bf->bf_daddr, bf->bf_desc, 878 txq->axq_depth); 879 ATH_KTR(sc, ATH_KTR_TX, 5, 880 "ath_tx_handoff: non-tdma: TXDP[%u] = %p (%p) " 881 "lastds=%p depth %d", 882 txq->axq_qnum, 883 (caddr_t)bf->bf_daddr, bf->bf_desc, 884 bf->bf_lastds, 885 txq->axq_depth); 886 887 } else { 888 *txq->axq_link = bf->bf_daddr; 889 DPRINTF(sc, ATH_DEBUG_XMIT, 890 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 891 txq->axq_qnum, txq->axq_link, 892 (caddr_t)bf->bf_daddr, bf->bf_desc, 893 txq->axq_depth); 894 ATH_KTR(sc, ATH_KTR_TX, 5, 895 "ath_tx_handoff: non-tdma: link[%u](%p)=%p (%p) " 896 "lastds=%d", 897 txq->axq_qnum, txq->axq_link, 898 (caddr_t)bf->bf_daddr, bf->bf_desc, 899 bf->bf_lastds); 900 901 } 902 #endif /* IEEE80211_SUPPORT_TDMA */ 903 if (bf->bf_state.bfs_aggr) 904 txq->axq_aggr_depth++; 905 ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link); 906 ath_hal_txstart(ah, txq->axq_qnum); 907 ATH_TXQ_UNLOCK(txq); 908 ATH_KTR(sc, ATH_KTR_TX, 1, 909 "ath_tx_handoff: txq=%u, txstart", txq->axq_qnum); 910 } 911 } 912 913 /* 914 * Restart TX DMA for the given TXQ. 915 * 916 * This must be called whether the queue is empty or not. 917 */ 918 static void 919 ath_legacy_tx_dma_restart(struct ath_softc *sc, struct ath_txq *txq) 920 { 921 struct ath_hal *ah = sc->sc_ah; 922 struct ath_buf *bf, *bf_last; 923 924 ATH_TXQ_LOCK_ASSERT(txq); 925 /* This is always going to be cleared, empty or not */ 926 txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 927 928 /* XXX make this ATH_TXQ_FIRST */ 929 bf = TAILQ_FIRST(&txq->axq_q); 930 bf_last = ATH_TXQ_LAST(txq, axq_q_s); 931 932 if (bf == NULL) 933 return; 934 935 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 936 ath_hal_gettxdesclinkptr(ah, bf_last->bf_lastds, &txq->axq_link); 937 ath_hal_txstart(ah, txq->axq_qnum); 938 } 939 940 /* 941 * Hand off a packet to the hardware (or mcast queue.) 942 * 943 * The relevant hardware txq should be locked. 944 */ 945 static void 946 ath_legacy_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq, 947 struct ath_buf *bf) 948 { 949 ATH_TX_LOCK_ASSERT(sc); 950 951 #ifdef ATH_DEBUG_ALQ 952 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 953 ath_tx_alq_post(sc, bf); 954 #endif 955 956 if (txq->axq_qnum == ATH_TXQ_SWQ) 957 ath_tx_handoff_mcast(sc, txq, bf); 958 else 959 ath_tx_handoff_hw(sc, txq, bf); 960 } 961 962 static int 963 ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni, 964 struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen, 965 int *keyix) 966 { 967 DPRINTF(sc, ATH_DEBUG_XMIT, 968 "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n", 969 __func__, 970 *hdrlen, 971 *pktlen, 972 isfrag, 973 iswep, 974 m0); 975 976 if (iswep) { 977 const struct ieee80211_cipher *cip; 978 struct ieee80211_key *k; 979 980 /* 981 * Construct the 802.11 header+trailer for an encrypted 982 * frame. The only reason this can fail is because of an 983 * unknown or unsupported cipher/key type. 984 */ 985 k = ieee80211_crypto_encap(ni, m0); 986 if (k == NULL) { 987 /* 988 * This can happen when the key is yanked after the 989 * frame was queued. Just discard the frame; the 990 * 802.11 layer counts failures and provides 991 * debugging/diagnostics. 992 */ 993 return (0); 994 } 995 /* 996 * Adjust the packet + header lengths for the crypto 997 * additions and calculate the h/w key index. When 998 * a s/w mic is done the frame will have had any mic 999 * added to it prior to entry so m0->m_pkthdr.len will 1000 * account for it. Otherwise we need to add it to the 1001 * packet length. 1002 */ 1003 cip = k->wk_cipher; 1004 (*hdrlen) += cip->ic_header; 1005 (*pktlen) += cip->ic_header + cip->ic_trailer; 1006 /* NB: frags always have any TKIP MIC done in s/w */ 1007 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 1008 (*pktlen) += cip->ic_miclen; 1009 (*keyix) = k->wk_keyix; 1010 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 1011 /* 1012 * Use station key cache slot, if assigned. 1013 */ 1014 (*keyix) = ni->ni_ucastkey.wk_keyix; 1015 if ((*keyix) == IEEE80211_KEYIX_NONE) 1016 (*keyix) = HAL_TXKEYIX_INVALID; 1017 } else 1018 (*keyix) = HAL_TXKEYIX_INVALID; 1019 1020 return (1); 1021 } 1022 1023 /* 1024 * Calculate whether interoperability protection is required for 1025 * this frame. 1026 * 1027 * This requires the rate control information be filled in, 1028 * as the protection requirement depends upon the current 1029 * operating mode / PHY. 1030 */ 1031 static void 1032 ath_tx_calc_protection(struct ath_softc *sc, struct ath_buf *bf) 1033 { 1034 struct ieee80211_frame *wh; 1035 uint8_t rix; 1036 uint16_t flags; 1037 int shortPreamble; 1038 const HAL_RATE_TABLE *rt = sc->sc_currates; 1039 struct ifnet *ifp = sc->sc_ifp; 1040 struct ieee80211com *ic = ifp->if_l2com; 1041 1042 flags = bf->bf_state.bfs_txflags; 1043 rix = bf->bf_state.bfs_rc[0].rix; 1044 shortPreamble = bf->bf_state.bfs_shpream; 1045 wh = mtod(bf->bf_m, struct ieee80211_frame *); 1046 1047 /* 1048 * If 802.11g protection is enabled, determine whether 1049 * to use RTS/CTS or just CTS. Note that this is only 1050 * done for OFDM unicast frames. 1051 */ 1052 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1053 rt->info[rix].phy == IEEE80211_T_OFDM && 1054 (flags & HAL_TXDESC_NOACK) == 0) { 1055 bf->bf_state.bfs_doprot = 1; 1056 /* XXX fragments must use CCK rates w/ protection */ 1057 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1058 flags |= HAL_TXDESC_RTSENA; 1059 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1060 flags |= HAL_TXDESC_CTSENA; 1061 } 1062 /* 1063 * For frags it would be desirable to use the 1064 * highest CCK rate for RTS/CTS. But stations 1065 * farther away may detect it at a lower CCK rate 1066 * so use the configured protection rate instead 1067 * (for now). 1068 */ 1069 sc->sc_stats.ast_tx_protect++; 1070 } 1071 1072 /* 1073 * If 11n protection is enabled and it's a HT frame, 1074 * enable RTS. 1075 * 1076 * XXX ic_htprotmode or ic_curhtprotmode? 1077 * XXX should it_htprotmode only matter if ic_curhtprotmode 1078 * XXX indicates it's not a HT pure environment? 1079 */ 1080 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) && 1081 rt->info[rix].phy == IEEE80211_T_HT && 1082 (flags & HAL_TXDESC_NOACK) == 0) { 1083 flags |= HAL_TXDESC_RTSENA; 1084 sc->sc_stats.ast_tx_htprotect++; 1085 } 1086 bf->bf_state.bfs_txflags = flags; 1087 } 1088 1089 /* 1090 * Update the frame duration given the currently selected rate. 1091 * 1092 * This also updates the frame duration value, so it will require 1093 * a DMA flush. 1094 */ 1095 static void 1096 ath_tx_calc_duration(struct ath_softc *sc, struct ath_buf *bf) 1097 { 1098 struct ieee80211_frame *wh; 1099 uint8_t rix; 1100 uint16_t flags; 1101 int shortPreamble; 1102 struct ath_hal *ah = sc->sc_ah; 1103 const HAL_RATE_TABLE *rt = sc->sc_currates; 1104 int isfrag = bf->bf_m->m_flags & M_FRAG; 1105 1106 flags = bf->bf_state.bfs_txflags; 1107 rix = bf->bf_state.bfs_rc[0].rix; 1108 shortPreamble = bf->bf_state.bfs_shpream; 1109 wh = mtod(bf->bf_m, struct ieee80211_frame *); 1110 1111 /* 1112 * Calculate duration. This logically belongs in the 802.11 1113 * layer but it lacks sufficient information to calculate it. 1114 */ 1115 if ((flags & HAL_TXDESC_NOACK) == 0 && 1116 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 1117 u_int16_t dur; 1118 if (shortPreamble) 1119 dur = rt->info[rix].spAckDuration; 1120 else 1121 dur = rt->info[rix].lpAckDuration; 1122 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 1123 dur += dur; /* additional SIFS+ACK */ 1124 KASSERT(bf->bf_m->m_nextpkt != NULL, ("no fragment")); 1125 /* 1126 * Include the size of next fragment so NAV is 1127 * updated properly. The last fragment uses only 1128 * the ACK duration 1129 * 1130 * XXX TODO: ensure that the rate lookup for each 1131 * fragment is the same as the rate used by the 1132 * first fragment! 1133 */ 1134 dur += ath_hal_computetxtime(ah, rt, 1135 bf->bf_m->m_nextpkt->m_pkthdr.len, 1136 rix, shortPreamble); 1137 } 1138 if (isfrag) { 1139 /* 1140 * Force hardware to use computed duration for next 1141 * fragment by disabling multi-rate retry which updates 1142 * duration based on the multi-rate duration table. 1143 */ 1144 bf->bf_state.bfs_ismrr = 0; 1145 bf->bf_state.bfs_try0 = ATH_TXMGTTRY; 1146 /* XXX update bfs_rc[0].try? */ 1147 } 1148 1149 /* Update the duration field itself */ 1150 *(u_int16_t *)wh->i_dur = htole16(dur); 1151 } 1152 } 1153 1154 static uint8_t 1155 ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt, 1156 int cix, int shortPreamble) 1157 { 1158 uint8_t ctsrate; 1159 1160 /* 1161 * CTS transmit rate is derived from the transmit rate 1162 * by looking in the h/w rate table. We must also factor 1163 * in whether or not a short preamble is to be used. 1164 */ 1165 /* NB: cix is set above where RTS/CTS is enabled */ 1166 KASSERT(cix != 0xff, ("cix not setup")); 1167 ctsrate = rt->info[cix].rateCode; 1168 1169 /* XXX this should only matter for legacy rates */ 1170 if (shortPreamble) 1171 ctsrate |= rt->info[cix].shortPreamble; 1172 1173 return (ctsrate); 1174 } 1175 1176 /* 1177 * Calculate the RTS/CTS duration for legacy frames. 1178 */ 1179 static int 1180 ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix, 1181 int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt, 1182 int flags) 1183 { 1184 int ctsduration = 0; 1185 1186 /* This mustn't be called for HT modes */ 1187 if (rt->info[cix].phy == IEEE80211_T_HT) { 1188 printf("%s: HT rate where it shouldn't be (0x%x)\n", 1189 __func__, rt->info[cix].rateCode); 1190 return (-1); 1191 } 1192 1193 /* 1194 * Compute the transmit duration based on the frame 1195 * size and the size of an ACK frame. We call into the 1196 * HAL to do the computation since it depends on the 1197 * characteristics of the actual PHY being used. 1198 * 1199 * NB: CTS is assumed the same size as an ACK so we can 1200 * use the precalculated ACK durations. 1201 */ 1202 if (shortPreamble) { 1203 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1204 ctsduration += rt->info[cix].spAckDuration; 1205 ctsduration += ath_hal_computetxtime(ah, 1206 rt, pktlen, rix, AH_TRUE); 1207 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1208 ctsduration += rt->info[rix].spAckDuration; 1209 } else { 1210 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1211 ctsduration += rt->info[cix].lpAckDuration; 1212 ctsduration += ath_hal_computetxtime(ah, 1213 rt, pktlen, rix, AH_FALSE); 1214 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1215 ctsduration += rt->info[rix].lpAckDuration; 1216 } 1217 1218 return (ctsduration); 1219 } 1220 1221 /* 1222 * Update the given ath_buf with updated rts/cts setup and duration 1223 * values. 1224 * 1225 * To support rate lookups for each software retry, the rts/cts rate 1226 * and cts duration must be re-calculated. 1227 * 1228 * This function assumes the RTS/CTS flags have been set as needed; 1229 * mrr has been disabled; and the rate control lookup has been done. 1230 * 1231 * XXX TODO: MRR need only be disabled for the pre-11n NICs. 1232 * XXX The 11n NICs support per-rate RTS/CTS configuration. 1233 */ 1234 static void 1235 ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf) 1236 { 1237 uint16_t ctsduration = 0; 1238 uint8_t ctsrate = 0; 1239 uint8_t rix = bf->bf_state.bfs_rc[0].rix; 1240 uint8_t cix = 0; 1241 const HAL_RATE_TABLE *rt = sc->sc_currates; 1242 1243 /* 1244 * No RTS/CTS enabled? Don't bother. 1245 */ 1246 if ((bf->bf_state.bfs_txflags & 1247 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) { 1248 /* XXX is this really needed? */ 1249 bf->bf_state.bfs_ctsrate = 0; 1250 bf->bf_state.bfs_ctsduration = 0; 1251 return; 1252 } 1253 1254 /* 1255 * If protection is enabled, use the protection rix control 1256 * rate. Otherwise use the rate0 control rate. 1257 */ 1258 if (bf->bf_state.bfs_doprot) 1259 rix = sc->sc_protrix; 1260 else 1261 rix = bf->bf_state.bfs_rc[0].rix; 1262 1263 /* 1264 * If the raw path has hard-coded ctsrate0 to something, 1265 * use it. 1266 */ 1267 if (bf->bf_state.bfs_ctsrate0 != 0) 1268 cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0); 1269 else 1270 /* Control rate from above */ 1271 cix = rt->info[rix].controlRate; 1272 1273 /* Calculate the rtscts rate for the given cix */ 1274 ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix, 1275 bf->bf_state.bfs_shpream); 1276 1277 /* The 11n chipsets do ctsduration calculations for you */ 1278 if (! ath_tx_is_11n(sc)) 1279 ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix, 1280 bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen, 1281 rt, bf->bf_state.bfs_txflags); 1282 1283 /* Squirrel away in ath_buf */ 1284 bf->bf_state.bfs_ctsrate = ctsrate; 1285 bf->bf_state.bfs_ctsduration = ctsduration; 1286 1287 /* 1288 * Must disable multi-rate retry when using RTS/CTS. 1289 */ 1290 if (!sc->sc_mrrprot) { 1291 bf->bf_state.bfs_ismrr = 0; 1292 bf->bf_state.bfs_try0 = 1293 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */ 1294 } 1295 } 1296 1297 /* 1298 * Setup the descriptor chain for a normal or fast-frame 1299 * frame. 1300 * 1301 * XXX TODO: extend to include the destination hardware QCU ID. 1302 * Make sure that is correct. Make sure that when being added 1303 * to the mcastq, the CABQ QCUID is set or things will get a bit 1304 * odd. 1305 */ 1306 static void 1307 ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf) 1308 { 1309 struct ath_desc *ds = bf->bf_desc; 1310 struct ath_hal *ah = sc->sc_ah; 1311 1312 if (bf->bf_state.bfs_txrate0 == 0) 1313 device_printf(sc->sc_dev, "%s: bf=%p, txrate0=%d\n", 1314 __func__, bf, 0); 1315 1316 ath_hal_setuptxdesc(ah, ds 1317 , bf->bf_state.bfs_pktlen /* packet length */ 1318 , bf->bf_state.bfs_hdrlen /* header length */ 1319 , bf->bf_state.bfs_atype /* Atheros packet type */ 1320 , bf->bf_state.bfs_txpower /* txpower */ 1321 , bf->bf_state.bfs_txrate0 1322 , bf->bf_state.bfs_try0 /* series 0 rate/tries */ 1323 , bf->bf_state.bfs_keyix /* key cache index */ 1324 , bf->bf_state.bfs_txantenna /* antenna mode */ 1325 , bf->bf_state.bfs_txflags /* flags */ 1326 , bf->bf_state.bfs_ctsrate /* rts/cts rate */ 1327 , bf->bf_state.bfs_ctsduration /* rts/cts duration */ 1328 ); 1329 1330 /* 1331 * This will be overriden when the descriptor chain is written. 1332 */ 1333 bf->bf_lastds = ds; 1334 bf->bf_last = bf; 1335 1336 /* Set rate control and descriptor chain for this frame */ 1337 ath_tx_set_ratectrl(sc, bf->bf_node, bf); 1338 ath_tx_chaindesclist(sc, ds, bf, 0, 0, 0); 1339 } 1340 1341 /* 1342 * Do a rate lookup. 1343 * 1344 * This performs a rate lookup for the given ath_buf only if it's required. 1345 * Non-data frames and raw frames don't require it. 1346 * 1347 * This populates the primary and MRR entries; MRR values are 1348 * then disabled later on if something requires it (eg RTS/CTS on 1349 * pre-11n chipsets. 1350 * 1351 * This needs to be done before the RTS/CTS fields are calculated 1352 * as they may depend upon the rate chosen. 1353 */ 1354 static void 1355 ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf) 1356 { 1357 uint8_t rate, rix; 1358 int try0; 1359 1360 if (! bf->bf_state.bfs_doratelookup) 1361 return; 1362 1363 /* Get rid of any previous state */ 1364 bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1365 1366 ATH_NODE_LOCK(ATH_NODE(bf->bf_node)); 1367 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream, 1368 bf->bf_state.bfs_pktlen, &rix, &try0, &rate); 1369 1370 /* In case MRR is disabled, make sure rc[0] is setup correctly */ 1371 bf->bf_state.bfs_rc[0].rix = rix; 1372 bf->bf_state.bfs_rc[0].ratecode = rate; 1373 bf->bf_state.bfs_rc[0].tries = try0; 1374 1375 if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY) 1376 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix, 1377 bf->bf_state.bfs_rc); 1378 ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node)); 1379 1380 sc->sc_txrix = rix; /* for LED blinking */ 1381 sc->sc_lastdatarix = rix; /* for fast frames */ 1382 bf->bf_state.bfs_try0 = try0; 1383 bf->bf_state.bfs_txrate0 = rate; 1384 } 1385 1386 /* 1387 * Update the CLRDMASK bit in the ath_buf if it needs to be set. 1388 */ 1389 static void 1390 ath_tx_update_clrdmask(struct ath_softc *sc, struct ath_tid *tid, 1391 struct ath_buf *bf) 1392 { 1393 struct ath_node *an = ATH_NODE(bf->bf_node); 1394 1395 ATH_TX_LOCK_ASSERT(sc); 1396 1397 if (an->clrdmask == 1) { 1398 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1399 an->clrdmask = 0; 1400 } 1401 } 1402 1403 /* 1404 * Transmit the given frame to the hardware. 1405 * 1406 * The frame must already be setup; rate control must already have 1407 * been done. 1408 * 1409 * XXX since the TXQ lock is being held here (and I dislike holding 1410 * it for this long when not doing software aggregation), later on 1411 * break this function into "setup_normal" and "xmit_normal". The 1412 * lock only needs to be held for the ath_tx_handoff call. 1413 */ 1414 static void 1415 ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq, 1416 struct ath_buf *bf) 1417 { 1418 struct ath_node *an = ATH_NODE(bf->bf_node); 1419 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid]; 1420 1421 ATH_TX_LOCK_ASSERT(sc); 1422 1423 /* 1424 * For now, just enable CLRDMASK. ath_tx_xmit_normal() does 1425 * set a completion handler however it doesn't (yet) properly 1426 * handle the strict ordering requirements needed for normal, 1427 * non-aggregate session frames. 1428 * 1429 * Once this is implemented, only set CLRDMASK like this for 1430 * frames that must go out - eg management/raw frames. 1431 */ 1432 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1433 1434 /* Setup the descriptor before handoff */ 1435 ath_tx_do_ratelookup(sc, bf); 1436 ath_tx_calc_duration(sc, bf); 1437 ath_tx_calc_protection(sc, bf); 1438 ath_tx_set_rtscts(sc, bf); 1439 ath_tx_rate_fill_rcflags(sc, bf); 1440 ath_tx_setds(sc, bf); 1441 1442 /* Track per-TID hardware queue depth correctly */ 1443 tid->hwq_depth++; 1444 1445 /* Assign the completion handler */ 1446 bf->bf_comp = ath_tx_normal_comp; 1447 1448 /* Hand off to hardware */ 1449 ath_tx_handoff(sc, txq, bf); 1450 } 1451 1452 /* 1453 * Do the basic frame setup stuff that's required before the frame 1454 * is added to a software queue. 1455 * 1456 * All frames get mostly the same treatment and it's done once. 1457 * Retransmits fiddle with things like the rate control setup, 1458 * setting the retransmit bit in the packet; doing relevant DMA/bus 1459 * syncing and relinking it (back) into the hardware TX queue. 1460 * 1461 * Note that this may cause the mbuf to be reallocated, so 1462 * m0 may not be valid. 1463 */ 1464 static int 1465 ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni, 1466 struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq) 1467 { 1468 struct ieee80211vap *vap = ni->ni_vap; 1469 struct ath_hal *ah = sc->sc_ah; 1470 struct ifnet *ifp = sc->sc_ifp; 1471 struct ieee80211com *ic = ifp->if_l2com; 1472 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 1473 int error, iswep, ismcast, isfrag, ismrr; 1474 int keyix, hdrlen, pktlen, try0 = 0; 1475 u_int8_t rix = 0, txrate = 0; 1476 struct ath_desc *ds; 1477 struct ieee80211_frame *wh; 1478 u_int subtype, flags; 1479 HAL_PKT_TYPE atype; 1480 const HAL_RATE_TABLE *rt; 1481 HAL_BOOL shortPreamble; 1482 struct ath_node *an; 1483 u_int pri; 1484 1485 /* 1486 * To ensure that both sequence numbers and the CCMP PN handling 1487 * is "correct", make sure that the relevant TID queue is locked. 1488 * Otherwise the CCMP PN and seqno may appear out of order, causing 1489 * re-ordered frames to have out of order CCMP PN's, resulting 1490 * in many, many frame drops. 1491 */ 1492 ATH_TX_LOCK_ASSERT(sc); 1493 1494 wh = mtod(m0, struct ieee80211_frame *); 1495 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1496 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1497 isfrag = m0->m_flags & M_FRAG; 1498 hdrlen = ieee80211_anyhdrsize(wh); 1499 /* 1500 * Packet length must not include any 1501 * pad bytes; deduct them here. 1502 */ 1503 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 1504 1505 /* Handle encryption twiddling if needed */ 1506 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen, 1507 &pktlen, &keyix)) { 1508 ath_freetx(m0); 1509 return EIO; 1510 } 1511 1512 /* packet header may have moved, reset our local pointer */ 1513 wh = mtod(m0, struct ieee80211_frame *); 1514 1515 pktlen += IEEE80211_CRC_LEN; 1516 1517 /* 1518 * Load the DMA map so any coalescing is done. This 1519 * also calculates the number of descriptors we need. 1520 */ 1521 error = ath_tx_dmasetup(sc, bf, m0); 1522 if (error != 0) 1523 return error; 1524 bf->bf_node = ni; /* NB: held reference */ 1525 m0 = bf->bf_m; /* NB: may have changed */ 1526 wh = mtod(m0, struct ieee80211_frame *); 1527 1528 /* setup descriptors */ 1529 ds = bf->bf_desc; 1530 rt = sc->sc_currates; 1531 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1532 1533 /* 1534 * NB: the 802.11 layer marks whether or not we should 1535 * use short preamble based on the current mode and 1536 * negotiated parameters. 1537 */ 1538 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1539 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1540 shortPreamble = AH_TRUE; 1541 sc->sc_stats.ast_tx_shortpre++; 1542 } else { 1543 shortPreamble = AH_FALSE; 1544 } 1545 1546 an = ATH_NODE(ni); 1547 //flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1548 flags = 0; 1549 ismrr = 0; /* default no multi-rate retry*/ 1550 pri = M_WME_GETAC(m0); /* honor classification */ 1551 /* XXX use txparams instead of fixed values */ 1552 /* 1553 * Calculate Atheros packet type from IEEE80211 packet header, 1554 * setup for rate calculations, and select h/w transmit queue. 1555 */ 1556 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1557 case IEEE80211_FC0_TYPE_MGT: 1558 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1559 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1560 atype = HAL_PKT_TYPE_BEACON; 1561 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1562 atype = HAL_PKT_TYPE_PROBE_RESP; 1563 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1564 atype = HAL_PKT_TYPE_ATIM; 1565 else 1566 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 1567 rix = an->an_mgmtrix; 1568 txrate = rt->info[rix].rateCode; 1569 if (shortPreamble) 1570 txrate |= rt->info[rix].shortPreamble; 1571 try0 = ATH_TXMGTTRY; 1572 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1573 break; 1574 case IEEE80211_FC0_TYPE_CTL: 1575 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 1576 rix = an->an_mgmtrix; 1577 txrate = rt->info[rix].rateCode; 1578 if (shortPreamble) 1579 txrate |= rt->info[rix].shortPreamble; 1580 try0 = ATH_TXMGTTRY; 1581 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1582 break; 1583 case IEEE80211_FC0_TYPE_DATA: 1584 atype = HAL_PKT_TYPE_NORMAL; /* default */ 1585 /* 1586 * Data frames: multicast frames go out at a fixed rate, 1587 * EAPOL frames use the mgmt frame rate; otherwise consult 1588 * the rate control module for the rate to use. 1589 */ 1590 if (ismcast) { 1591 rix = an->an_mcastrix; 1592 txrate = rt->info[rix].rateCode; 1593 if (shortPreamble) 1594 txrate |= rt->info[rix].shortPreamble; 1595 try0 = 1; 1596 } else if (m0->m_flags & M_EAPOL) { 1597 /* XXX? maybe always use long preamble? */ 1598 rix = an->an_mgmtrix; 1599 txrate = rt->info[rix].rateCode; 1600 if (shortPreamble) 1601 txrate |= rt->info[rix].shortPreamble; 1602 try0 = ATH_TXMAXTRY; /* XXX?too many? */ 1603 } else { 1604 /* 1605 * Do rate lookup on each TX, rather than using 1606 * the hard-coded TX information decided here. 1607 */ 1608 ismrr = 1; 1609 bf->bf_state.bfs_doratelookup = 1; 1610 } 1611 if (cap->cap_wmeParams[pri].wmep_noackPolicy) 1612 flags |= HAL_TXDESC_NOACK; 1613 break; 1614 default: 1615 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 1616 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1617 /* XXX statistic */ 1618 /* XXX free tx dmamap */ 1619 ath_freetx(m0); 1620 return EIO; 1621 } 1622 1623 /* 1624 * There are two known scenarios where the frame AC doesn't match 1625 * what the destination TXQ is. 1626 * 1627 * + non-QoS frames (eg management?) that the net80211 stack has 1628 * assigned a higher AC to, but since it's a non-QoS TID, it's 1629 * being thrown into TID 16. TID 16 gets the AC_BE queue. 1630 * It's quite possible that management frames should just be 1631 * direct dispatched to hardware rather than go via the software 1632 * queue; that should be investigated in the future. There are 1633 * some specific scenarios where this doesn't make sense, mostly 1634 * surrounding ADDBA request/response - hence why that is special 1635 * cased. 1636 * 1637 * + Multicast frames going into the VAP mcast queue. That shows up 1638 * as "TXQ 11". 1639 * 1640 * This driver should eventually support separate TID and TXQ locking, 1641 * allowing for arbitrary AC frames to appear on arbitrary software 1642 * queues, being queued to the "correct" hardware queue when needed. 1643 */ 1644 #if 0 1645 if (txq != sc->sc_ac2q[pri]) { 1646 device_printf(sc->sc_dev, 1647 "%s: txq=%p (%d), pri=%d, pri txq=%p (%d)\n", 1648 __func__, 1649 txq, 1650 txq->axq_qnum, 1651 pri, 1652 sc->sc_ac2q[pri], 1653 sc->sc_ac2q[pri]->axq_qnum); 1654 } 1655 #endif 1656 1657 /* 1658 * Calculate miscellaneous flags. 1659 */ 1660 if (ismcast) { 1661 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1662 } else if (pktlen > vap->iv_rtsthreshold && 1663 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 1664 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1665 sc->sc_stats.ast_tx_rts++; 1666 } 1667 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 1668 sc->sc_stats.ast_tx_noack++; 1669 #ifdef IEEE80211_SUPPORT_TDMA 1670 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 1671 DPRINTF(sc, ATH_DEBUG_TDMA, 1672 "%s: discard frame, ACK required w/ TDMA\n", __func__); 1673 sc->sc_stats.ast_tdma_ack++; 1674 /* XXX free tx dmamap */ 1675 ath_freetx(m0); 1676 return EIO; 1677 } 1678 #endif 1679 1680 /* 1681 * Determine if a tx interrupt should be generated for 1682 * this descriptor. We take a tx interrupt to reap 1683 * descriptors when the h/w hits an EOL condition or 1684 * when the descriptor is specifically marked to generate 1685 * an interrupt. We periodically mark descriptors in this 1686 * way to insure timely replenishing of the supply needed 1687 * for sending frames. Defering interrupts reduces system 1688 * load and potentially allows more concurrent work to be 1689 * done but if done to aggressively can cause senders to 1690 * backup. 1691 * 1692 * NB: use >= to deal with sc_txintrperiod changing 1693 * dynamically through sysctl. 1694 */ 1695 if (flags & HAL_TXDESC_INTREQ) { 1696 txq->axq_intrcnt = 0; 1697 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 1698 flags |= HAL_TXDESC_INTREQ; 1699 txq->axq_intrcnt = 0; 1700 } 1701 1702 /* This point forward is actual TX bits */ 1703 1704 /* 1705 * At this point we are committed to sending the frame 1706 * and we don't need to look at m_nextpkt; clear it in 1707 * case this frame is part of frag chain. 1708 */ 1709 m0->m_nextpkt = NULL; 1710 1711 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1712 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 1713 sc->sc_hwmap[rix].ieeerate, -1); 1714 1715 if (ieee80211_radiotap_active_vap(vap)) { 1716 u_int64_t tsf = ath_hal_gettsf64(ah); 1717 1718 sc->sc_tx_th.wt_tsf = htole64(tsf); 1719 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1720 if (iswep) 1721 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1722 if (isfrag) 1723 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1724 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1725 sc->sc_tx_th.wt_txpower = ieee80211_get_node_txpower(ni); 1726 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1727 1728 ieee80211_radiotap_tx(vap, m0); 1729 } 1730 1731 /* Blank the legacy rate array */ 1732 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1733 1734 /* 1735 * ath_buf_set_rate needs at least one rate/try to setup 1736 * the rate scenario. 1737 */ 1738 bf->bf_state.bfs_rc[0].rix = rix; 1739 bf->bf_state.bfs_rc[0].tries = try0; 1740 bf->bf_state.bfs_rc[0].ratecode = txrate; 1741 1742 /* Store the decided rate index values away */ 1743 bf->bf_state.bfs_pktlen = pktlen; 1744 bf->bf_state.bfs_hdrlen = hdrlen; 1745 bf->bf_state.bfs_atype = atype; 1746 bf->bf_state.bfs_txpower = ieee80211_get_node_txpower(ni); 1747 bf->bf_state.bfs_txrate0 = txrate; 1748 bf->bf_state.bfs_try0 = try0; 1749 bf->bf_state.bfs_keyix = keyix; 1750 bf->bf_state.bfs_txantenna = sc->sc_txantenna; 1751 bf->bf_state.bfs_txflags = flags; 1752 bf->bf_state.bfs_shpream = shortPreamble; 1753 1754 /* XXX this should be done in ath_tx_setrate() */ 1755 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */ 1756 bf->bf_state.bfs_ctsrate = 0; /* calculated later */ 1757 bf->bf_state.bfs_ctsduration = 0; 1758 bf->bf_state.bfs_ismrr = ismrr; 1759 1760 return 0; 1761 } 1762 1763 /* 1764 * Queue a frame to the hardware or software queue. 1765 * 1766 * This can be called by the net80211 code. 1767 * 1768 * XXX what about locking? Or, push the seqno assign into the 1769 * XXX aggregate scheduler so its serialised? 1770 * 1771 * XXX When sending management frames via ath_raw_xmit(), 1772 * should CLRDMASK be set unconditionally? 1773 */ 1774 int 1775 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, 1776 struct ath_buf *bf, struct mbuf *m0) 1777 { 1778 struct ieee80211vap *vap = ni->ni_vap; 1779 struct ath_vap *avp = ATH_VAP(vap); 1780 int r = 0; 1781 u_int pri; 1782 int tid; 1783 struct ath_txq *txq; 1784 int ismcast; 1785 const struct ieee80211_frame *wh; 1786 int is_ampdu, is_ampdu_tx, is_ampdu_pending; 1787 ieee80211_seq seqno; 1788 uint8_t type, subtype; 1789 1790 ATH_TX_LOCK_ASSERT(sc); 1791 1792 /* 1793 * Determine the target hardware queue. 1794 * 1795 * For multicast frames, the txq gets overridden appropriately 1796 * depending upon the state of PS. 1797 * 1798 * For any other frame, we do a TID/QoS lookup inside the frame 1799 * to see what the TID should be. If it's a non-QoS frame, the 1800 * AC and TID are overridden. The TID/TXQ code assumes the 1801 * TID is on a predictable hardware TXQ, so we don't support 1802 * having a node TID queued to multiple hardware TXQs. 1803 * This may change in the future but would require some locking 1804 * fudgery. 1805 */ 1806 pri = ath_tx_getac(sc, m0); 1807 tid = ath_tx_gettid(sc, m0); 1808 1809 txq = sc->sc_ac2q[pri]; 1810 wh = mtod(m0, struct ieee80211_frame *); 1811 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1812 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1813 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1814 1815 /* 1816 * Enforce how deep the multicast queue can grow. 1817 * 1818 * XXX duplicated in ath_raw_xmit(). 1819 */ 1820 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1821 if (sc->sc_cabq->axq_depth + sc->sc_cabq->fifo.axq_depth 1822 > sc->sc_txq_mcastq_maxdepth) { 1823 sc->sc_stats.ast_tx_mcastq_overflow++; 1824 r = ENOBUFS; 1825 } 1826 if (r != 0) { 1827 m_freem(m0); 1828 return r; 1829 } 1830 } 1831 1832 /* A-MPDU TX */ 1833 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid); 1834 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid); 1835 is_ampdu = is_ampdu_tx | is_ampdu_pending; 1836 1837 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, ac=%d, is_ampdu=%d\n", 1838 __func__, tid, pri, is_ampdu); 1839 1840 /* Set local packet state, used to queue packets to hardware */ 1841 bf->bf_state.bfs_tid = tid; 1842 bf->bf_state.bfs_tx_queue = txq->axq_qnum; 1843 bf->bf_state.bfs_pri = pri; 1844 1845 #if 1 1846 /* 1847 * When servicing one or more stations in power-save mode 1848 * (or) if there is some mcast data waiting on the mcast 1849 * queue (to prevent out of order delivery) multicast frames 1850 * must be bufferd until after the beacon. 1851 * 1852 * TODO: we should lock the mcastq before we check the length. 1853 */ 1854 if (sc->sc_cabq_enable && ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) { 1855 txq = &avp->av_mcastq; 1856 /* 1857 * Mark the frame as eventually belonging on the CAB 1858 * queue, so the descriptor setup functions will 1859 * correctly initialise the descriptor 'qcuId' field. 1860 */ 1861 bf->bf_state.bfs_tx_queue = sc->sc_cabq->axq_qnum; 1862 } 1863 #endif 1864 1865 /* Do the generic frame setup */ 1866 /* XXX should just bzero the bf_state? */ 1867 bf->bf_state.bfs_dobaw = 0; 1868 1869 /* A-MPDU TX? Manually set sequence number */ 1870 /* 1871 * Don't do it whilst pending; the net80211 layer still 1872 * assigns them. 1873 */ 1874 if (is_ampdu_tx) { 1875 /* 1876 * Always call; this function will 1877 * handle making sure that null data frames 1878 * don't get a sequence number from the current 1879 * TID and thus mess with the BAW. 1880 */ 1881 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0); 1882 1883 /* 1884 * Don't add QoS NULL frames to the BAW. 1885 */ 1886 if (IEEE80211_QOS_HAS_SEQ(wh) && 1887 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL) { 1888 bf->bf_state.bfs_dobaw = 1; 1889 } 1890 } 1891 1892 /* 1893 * If needed, the sequence number has been assigned. 1894 * Squirrel it away somewhere easy to get to. 1895 */ 1896 bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT; 1897 1898 /* Is ampdu pending? fetch the seqno and print it out */ 1899 if (is_ampdu_pending) 1900 DPRINTF(sc, ATH_DEBUG_SW_TX, 1901 "%s: tid %d: ampdu pending, seqno %d\n", 1902 __func__, tid, M_SEQNO_GET(m0)); 1903 1904 /* This also sets up the DMA map */ 1905 r = ath_tx_normal_setup(sc, ni, bf, m0, txq); 1906 1907 if (r != 0) 1908 goto done; 1909 1910 /* At this point m0 could have changed! */ 1911 m0 = bf->bf_m; 1912 1913 #if 1 1914 /* 1915 * If it's a multicast frame, do a direct-dispatch to the 1916 * destination hardware queue. Don't bother software 1917 * queuing it. 1918 */ 1919 /* 1920 * If it's a BAR frame, do a direct dispatch to the 1921 * destination hardware queue. Don't bother software 1922 * queuing it, as the TID will now be paused. 1923 * Sending a BAR frame can occur from the net80211 txa timer 1924 * (ie, retries) or from the ath txtask (completion call.) 1925 * It queues directly to hardware because the TID is paused 1926 * at this point (and won't be unpaused until the BAR has 1927 * either been TXed successfully or max retries has been 1928 * reached.) 1929 */ 1930 if (txq == &avp->av_mcastq) { 1931 DPRINTF(sc, ATH_DEBUG_SW_TX, 1932 "%s: bf=%p: mcastq: TX'ing\n", __func__, bf); 1933 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1934 ath_tx_xmit_normal(sc, txq, bf); 1935 } else if (type == IEEE80211_FC0_TYPE_CTL && 1936 subtype == IEEE80211_FC0_SUBTYPE_BAR) { 1937 DPRINTF(sc, ATH_DEBUG_SW_TX, 1938 "%s: BAR: TX'ing direct\n", __func__); 1939 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1940 ath_tx_xmit_normal(sc, txq, bf); 1941 } else { 1942 /* add to software queue */ 1943 DPRINTF(sc, ATH_DEBUG_SW_TX, 1944 "%s: bf=%p: swq: TX'ing\n", __func__, bf); 1945 ath_tx_swq(sc, ni, txq, bf); 1946 } 1947 #else 1948 /* 1949 * For now, since there's no software queue, 1950 * direct-dispatch to the hardware. 1951 */ 1952 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 1953 ath_tx_xmit_normal(sc, txq, bf); 1954 #endif 1955 done: 1956 return 0; 1957 } 1958 1959 static int 1960 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 1961 struct ath_buf *bf, struct mbuf *m0, 1962 const struct ieee80211_bpf_params *params) 1963 { 1964 struct ifnet *ifp = sc->sc_ifp; 1965 struct ieee80211com *ic = ifp->if_l2com; 1966 struct ath_hal *ah = sc->sc_ah; 1967 struct ieee80211vap *vap = ni->ni_vap; 1968 int error, ismcast, ismrr; 1969 int keyix, hdrlen, pktlen, try0, txantenna; 1970 u_int8_t rix, txrate; 1971 struct ieee80211_frame *wh; 1972 u_int flags; 1973 HAL_PKT_TYPE atype; 1974 const HAL_RATE_TABLE *rt; 1975 struct ath_desc *ds; 1976 u_int pri; 1977 int o_tid = -1; 1978 int do_override; 1979 1980 ATH_TX_LOCK_ASSERT(sc); 1981 1982 wh = mtod(m0, struct ieee80211_frame *); 1983 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1984 hdrlen = ieee80211_anyhdrsize(wh); 1985 /* 1986 * Packet length must not include any 1987 * pad bytes; deduct them here. 1988 */ 1989 /* XXX honor IEEE80211_BPF_DATAPAD */ 1990 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 1991 1992 ATH_KTR(sc, ATH_KTR_TX, 2, 1993 "ath_tx_raw_start: ni=%p, bf=%p, raw", ni, bf); 1994 1995 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n", 1996 __func__, ismcast); 1997 1998 pri = params->ibp_pri & 3; 1999 /* Override pri if the frame isn't a QoS one */ 2000 if (! IEEE80211_QOS_HAS_SEQ(wh)) 2001 pri = ath_tx_getac(sc, m0); 2002 2003 /* XXX If it's an ADDBA, override the correct queue */ 2004 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid); 2005 2006 /* Map ADDBA to the correct priority */ 2007 if (do_override) { 2008 #if 0 2009 device_printf(sc->sc_dev, 2010 "%s: overriding tid %d pri %d -> %d\n", 2011 __func__, o_tid, pri, TID_TO_WME_AC(o_tid)); 2012 #endif 2013 pri = TID_TO_WME_AC(o_tid); 2014 } 2015 2016 /* Handle encryption twiddling if needed */ 2017 if (! ath_tx_tag_crypto(sc, ni, 2018 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0, 2019 &hdrlen, &pktlen, &keyix)) { 2020 ath_freetx(m0); 2021 return EIO; 2022 } 2023 /* packet header may have moved, reset our local pointer */ 2024 wh = mtod(m0, struct ieee80211_frame *); 2025 2026 /* Do the generic frame setup */ 2027 /* XXX should just bzero the bf_state? */ 2028 bf->bf_state.bfs_dobaw = 0; 2029 2030 error = ath_tx_dmasetup(sc, bf, m0); 2031 if (error != 0) 2032 return error; 2033 m0 = bf->bf_m; /* NB: may have changed */ 2034 wh = mtod(m0, struct ieee80211_frame *); 2035 bf->bf_node = ni; /* NB: held reference */ 2036 2037 /* Always enable CLRDMASK for raw frames for now.. */ 2038 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 2039 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 2040 if (params->ibp_flags & IEEE80211_BPF_RTS) 2041 flags |= HAL_TXDESC_RTSENA; 2042 else if (params->ibp_flags & IEEE80211_BPF_CTS) { 2043 /* XXX assume 11g/11n protection? */ 2044 bf->bf_state.bfs_doprot = 1; 2045 flags |= HAL_TXDESC_CTSENA; 2046 } 2047 /* XXX leave ismcast to injector? */ 2048 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 2049 flags |= HAL_TXDESC_NOACK; 2050 2051 rt = sc->sc_currates; 2052 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 2053 rix = ath_tx_findrix(sc, params->ibp_rate0); 2054 txrate = rt->info[rix].rateCode; 2055 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 2056 txrate |= rt->info[rix].shortPreamble; 2057 sc->sc_txrix = rix; 2058 try0 = params->ibp_try0; 2059 ismrr = (params->ibp_try1 != 0); 2060 txantenna = params->ibp_pri >> 2; 2061 if (txantenna == 0) /* XXX? */ 2062 txantenna = sc->sc_txantenna; 2063 2064 /* 2065 * Since ctsrate is fixed, store it away for later 2066 * use when the descriptor fields are being set. 2067 */ 2068 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) 2069 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate; 2070 2071 /* 2072 * NB: we mark all packets as type PSPOLL so the h/w won't 2073 * set the sequence number, duration, etc. 2074 */ 2075 atype = HAL_PKT_TYPE_PSPOLL; 2076 2077 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 2078 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 2079 sc->sc_hwmap[rix].ieeerate, -1); 2080 2081 if (ieee80211_radiotap_active_vap(vap)) { 2082 u_int64_t tsf = ath_hal_gettsf64(ah); 2083 2084 sc->sc_tx_th.wt_tsf = htole64(tsf); 2085 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 2086 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 2087 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2088 if (m0->m_flags & M_FRAG) 2089 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 2090 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 2091 sc->sc_tx_th.wt_txpower = MIN(params->ibp_power, 2092 ieee80211_get_node_txpower(ni)); 2093 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 2094 2095 ieee80211_radiotap_tx(vap, m0); 2096 } 2097 2098 /* 2099 * Formulate first tx descriptor with tx controls. 2100 */ 2101 ds = bf->bf_desc; 2102 /* XXX check return value? */ 2103 2104 /* Store the decided rate index values away */ 2105 bf->bf_state.bfs_pktlen = pktlen; 2106 bf->bf_state.bfs_hdrlen = hdrlen; 2107 bf->bf_state.bfs_atype = atype; 2108 bf->bf_state.bfs_txpower = MIN(params->ibp_power, 2109 ieee80211_get_node_txpower(ni)); 2110 bf->bf_state.bfs_txrate0 = txrate; 2111 bf->bf_state.bfs_try0 = try0; 2112 bf->bf_state.bfs_keyix = keyix; 2113 bf->bf_state.bfs_txantenna = txantenna; 2114 bf->bf_state.bfs_txflags = flags; 2115 bf->bf_state.bfs_shpream = 2116 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE); 2117 2118 /* Set local packet state, used to queue packets to hardware */ 2119 bf->bf_state.bfs_tid = WME_AC_TO_TID(pri); 2120 bf->bf_state.bfs_tx_queue = sc->sc_ac2q[pri]->axq_qnum; 2121 bf->bf_state.bfs_pri = pri; 2122 2123 /* XXX this should be done in ath_tx_setrate() */ 2124 bf->bf_state.bfs_ctsrate = 0; 2125 bf->bf_state.bfs_ctsduration = 0; 2126 bf->bf_state.bfs_ismrr = ismrr; 2127 2128 /* Blank the legacy rate array */ 2129 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 2130 2131 bf->bf_state.bfs_rc[0].rix = 2132 ath_tx_findrix(sc, params->ibp_rate0); 2133 bf->bf_state.bfs_rc[0].tries = try0; 2134 bf->bf_state.bfs_rc[0].ratecode = txrate; 2135 2136 if (ismrr) { 2137 int rix; 2138 2139 rix = ath_tx_findrix(sc, params->ibp_rate1); 2140 bf->bf_state.bfs_rc[1].rix = rix; 2141 bf->bf_state.bfs_rc[1].tries = params->ibp_try1; 2142 2143 rix = ath_tx_findrix(sc, params->ibp_rate2); 2144 bf->bf_state.bfs_rc[2].rix = rix; 2145 bf->bf_state.bfs_rc[2].tries = params->ibp_try2; 2146 2147 rix = ath_tx_findrix(sc, params->ibp_rate3); 2148 bf->bf_state.bfs_rc[3].rix = rix; 2149 bf->bf_state.bfs_rc[3].tries = params->ibp_try3; 2150 } 2151 /* 2152 * All the required rate control decisions have been made; 2153 * fill in the rc flags. 2154 */ 2155 ath_tx_rate_fill_rcflags(sc, bf); 2156 2157 /* NB: no buffered multicast in power save support */ 2158 2159 /* 2160 * If we're overiding the ADDBA destination, dump directly 2161 * into the hardware queue, right after any pending 2162 * frames to that node are. 2163 */ 2164 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n", 2165 __func__, do_override); 2166 2167 #if 1 2168 if (do_override) { 2169 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 2170 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf); 2171 } else { 2172 /* Queue to software queue */ 2173 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf); 2174 } 2175 #else 2176 /* Direct-dispatch to the hardware */ 2177 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 2178 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf); 2179 #endif 2180 return 0; 2181 } 2182 2183 /* 2184 * Send a raw frame. 2185 * 2186 * This can be called by net80211. 2187 */ 2188 int 2189 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2190 const struct ieee80211_bpf_params *params) 2191 { 2192 struct ieee80211com *ic = ni->ni_ic; 2193 struct ifnet *ifp = ic->ic_ifp; 2194 struct ath_softc *sc = ifp->if_softc; 2195 struct ath_buf *bf; 2196 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 2197 int error = 0; 2198 2199 ATH_PCU_LOCK(sc); 2200 if (sc->sc_inreset_cnt > 0) { 2201 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n", 2202 __func__); 2203 error = EIO; 2204 ATH_PCU_UNLOCK(sc); 2205 goto bad0; 2206 } 2207 sc->sc_txstart_cnt++; 2208 ATH_PCU_UNLOCK(sc); 2209 2210 ATH_TX_LOCK(sc); 2211 2212 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 2213 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 2214 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ? 2215 "!running" : "invalid"); 2216 m_freem(m); 2217 error = ENETDOWN; 2218 goto bad; 2219 } 2220 2221 /* 2222 * Enforce how deep the multicast queue can grow. 2223 * 2224 * XXX duplicated in ath_tx_start(). 2225 */ 2226 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 2227 if (sc->sc_cabq->axq_depth + sc->sc_cabq->fifo.axq_depth 2228 > sc->sc_txq_mcastq_maxdepth) { 2229 sc->sc_stats.ast_tx_mcastq_overflow++; 2230 error = ENOBUFS; 2231 } 2232 2233 if (error != 0) { 2234 m_freem(m); 2235 goto bad; 2236 } 2237 } 2238 2239 /* 2240 * Grab a TX buffer and associated resources. 2241 */ 2242 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT); 2243 if (bf == NULL) { 2244 sc->sc_stats.ast_tx_nobuf++; 2245 m_freem(m); 2246 error = ENOBUFS; 2247 goto bad; 2248 } 2249 ATH_KTR(sc, ATH_KTR_TX, 3, "ath_raw_xmit: m=%p, params=%p, bf=%p\n", 2250 m, params, bf); 2251 2252 if (params == NULL) { 2253 /* 2254 * Legacy path; interpret frame contents to decide 2255 * precisely how to send the frame. 2256 */ 2257 if (ath_tx_start(sc, ni, bf, m)) { 2258 error = EIO; /* XXX */ 2259 goto bad2; 2260 } 2261 } else { 2262 /* 2263 * Caller supplied explicit parameters to use in 2264 * sending the frame. 2265 */ 2266 if (ath_tx_raw_start(sc, ni, bf, m, params)) { 2267 error = EIO; /* XXX */ 2268 goto bad2; 2269 } 2270 } 2271 sc->sc_wd_timer = 5; 2272 ifp->if_opackets++; 2273 sc->sc_stats.ast_tx_raw++; 2274 2275 /* 2276 * Update the TIM - if there's anything queued to the 2277 * software queue and power save is enabled, we should 2278 * set the TIM. 2279 */ 2280 ath_tx_update_tim(sc, ni, 1); 2281 2282 ATH_TX_UNLOCK(sc); 2283 2284 ATH_PCU_LOCK(sc); 2285 sc->sc_txstart_cnt--; 2286 ATH_PCU_UNLOCK(sc); 2287 2288 return 0; 2289 bad2: 2290 ATH_KTR(sc, ATH_KTR_TX, 3, "ath_raw_xmit: bad2: m=%p, params=%p, " 2291 "bf=%p", 2292 m, 2293 params, 2294 bf); 2295 ATH_TXBUF_LOCK(sc); 2296 ath_returnbuf_head(sc, bf); 2297 ATH_TXBUF_UNLOCK(sc); 2298 bad: 2299 2300 ATH_TX_UNLOCK(sc); 2301 2302 ATH_PCU_LOCK(sc); 2303 sc->sc_txstart_cnt--; 2304 ATH_PCU_UNLOCK(sc); 2305 bad0: 2306 ATH_KTR(sc, ATH_KTR_TX, 2, "ath_raw_xmit: bad0: m=%p, params=%p", 2307 m, params); 2308 ifp->if_oerrors++; 2309 sc->sc_stats.ast_tx_raw_fail++; 2310 ieee80211_free_node(ni); 2311 2312 return error; 2313 } 2314 2315 /* Some helper functions */ 2316 2317 /* 2318 * ADDBA (and potentially others) need to be placed in the same 2319 * hardware queue as the TID/node it's relating to. This is so 2320 * it goes out after any pending non-aggregate frames to the 2321 * same node/TID. 2322 * 2323 * If this isn't done, the ADDBA can go out before the frames 2324 * queued in hardware. Even though these frames have a sequence 2325 * number -earlier- than the ADDBA can be transmitted (but 2326 * no frames whose sequence numbers are after the ADDBA should 2327 * be!) they'll arrive after the ADDBA - and the receiving end 2328 * will simply drop them as being out of the BAW. 2329 * 2330 * The frames can't be appended to the TID software queue - it'll 2331 * never be sent out. So these frames have to be directly 2332 * dispatched to the hardware, rather than queued in software. 2333 * So if this function returns true, the TXQ has to be 2334 * overridden and it has to be directly dispatched. 2335 * 2336 * It's a dirty hack, but someone's gotta do it. 2337 */ 2338 2339 /* 2340 * XXX doesn't belong here! 2341 */ 2342 static int 2343 ieee80211_is_action(struct ieee80211_frame *wh) 2344 { 2345 /* Type: Management frame? */ 2346 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 2347 IEEE80211_FC0_TYPE_MGT) 2348 return 0; 2349 2350 /* Subtype: Action frame? */ 2351 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) != 2352 IEEE80211_FC0_SUBTYPE_ACTION) 2353 return 0; 2354 2355 return 1; 2356 } 2357 2358 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 2359 /* 2360 * Return an alternate TID for ADDBA request frames. 2361 * 2362 * Yes, this likely should be done in the net80211 layer. 2363 */ 2364 static int 2365 ath_tx_action_frame_override_queue(struct ath_softc *sc, 2366 struct ieee80211_node *ni, 2367 struct mbuf *m0, int *tid) 2368 { 2369 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 2370 struct ieee80211_action_ba_addbarequest *ia; 2371 uint8_t *frm; 2372 uint16_t baparamset; 2373 2374 /* Not action frame? Bail */ 2375 if (! ieee80211_is_action(wh)) 2376 return 0; 2377 2378 /* XXX Not needed for frames we send? */ 2379 #if 0 2380 /* Correct length? */ 2381 if (! ieee80211_parse_action(ni, m)) 2382 return 0; 2383 #endif 2384 2385 /* Extract out action frame */ 2386 frm = (u_int8_t *)&wh[1]; 2387 ia = (struct ieee80211_action_ba_addbarequest *) frm; 2388 2389 /* Not ADDBA? Bail */ 2390 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA) 2391 return 0; 2392 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST) 2393 return 0; 2394 2395 /* Extract TID, return it */ 2396 baparamset = le16toh(ia->rq_baparamset); 2397 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID); 2398 2399 return 1; 2400 } 2401 #undef MS 2402 2403 /* Per-node software queue operations */ 2404 2405 /* 2406 * Add the current packet to the given BAW. 2407 * It is assumed that the current packet 2408 * 2409 * + fits inside the BAW; 2410 * + already has had a sequence number allocated. 2411 * 2412 * Since the BAW status may be modified by both the ath task and 2413 * the net80211/ifnet contexts, the TID must be locked. 2414 */ 2415 void 2416 ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an, 2417 struct ath_tid *tid, struct ath_buf *bf) 2418 { 2419 int index, cindex; 2420 struct ieee80211_tx_ampdu *tap; 2421 2422 ATH_TX_LOCK_ASSERT(sc); 2423 2424 if (bf->bf_state.bfs_isretried) 2425 return; 2426 2427 tap = ath_tx_get_tx_tid(an, tid->tid); 2428 2429 if (! bf->bf_state.bfs_dobaw) { 2430 device_printf(sc->sc_dev, 2431 "%s: dobaw=0, seqno=%d, window %d:%d\n", 2432 __func__, 2433 SEQNO(bf->bf_state.bfs_seqno), 2434 tap->txa_start, 2435 tap->txa_wnd); 2436 } 2437 2438 if (bf->bf_state.bfs_addedbaw) 2439 device_printf(sc->sc_dev, 2440 "%s: re-added? tid=%d, seqno %d; window %d:%d; " 2441 "baw head=%d tail=%d\n", 2442 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2443 tap->txa_start, tap->txa_wnd, tid->baw_head, 2444 tid->baw_tail); 2445 2446 /* 2447 * Verify that the given sequence number is not outside of the 2448 * BAW. Complain loudly if that's the case. 2449 */ 2450 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2451 SEQNO(bf->bf_state.bfs_seqno))) { 2452 device_printf(sc->sc_dev, 2453 "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; " 2454 "baw head=%d tail=%d\n", 2455 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2456 tap->txa_start, tap->txa_wnd, tid->baw_head, 2457 tid->baw_tail); 2458 } 2459 2460 /* 2461 * ni->ni_txseqs[] is the currently allocated seqno. 2462 * the txa state contains the current baw start. 2463 */ 2464 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno)); 2465 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2466 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2467 "%s: tid=%d, seqno %d; window %d:%d; index=%d cindex=%d " 2468 "baw head=%d tail=%d\n", 2469 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2470 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head, 2471 tid->baw_tail); 2472 2473 2474 #if 0 2475 assert(tid->tx_buf[cindex] == NULL); 2476 #endif 2477 if (tid->tx_buf[cindex] != NULL) { 2478 device_printf(sc->sc_dev, 2479 "%s: ba packet dup (index=%d, cindex=%d, " 2480 "head=%d, tail=%d)\n", 2481 __func__, index, cindex, tid->baw_head, tid->baw_tail); 2482 device_printf(sc->sc_dev, 2483 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n", 2484 __func__, 2485 tid->tx_buf[cindex], 2486 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno), 2487 bf, 2488 SEQNO(bf->bf_state.bfs_seqno) 2489 ); 2490 } 2491 tid->tx_buf[cindex] = bf; 2492 2493 if (index >= ((tid->baw_tail - tid->baw_head) & 2494 (ATH_TID_MAX_BUFS - 1))) { 2495 tid->baw_tail = cindex; 2496 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 2497 } 2498 } 2499 2500 /* 2501 * Flip the BAW buffer entry over from the existing one to the new one. 2502 * 2503 * When software retransmitting a (sub-)frame, it is entirely possible that 2504 * the frame ath_buf is marked as BUSY and can't be immediately reused. 2505 * In that instance the buffer is cloned and the new buffer is used for 2506 * retransmit. We thus need to update the ath_buf slot in the BAW buf 2507 * tracking array to maintain consistency. 2508 */ 2509 static void 2510 ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an, 2511 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf) 2512 { 2513 int index, cindex; 2514 struct ieee80211_tx_ampdu *tap; 2515 int seqno = SEQNO(old_bf->bf_state.bfs_seqno); 2516 2517 ATH_TX_LOCK_ASSERT(sc); 2518 2519 tap = ath_tx_get_tx_tid(an, tid->tid); 2520 index = ATH_BA_INDEX(tap->txa_start, seqno); 2521 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2522 2523 /* 2524 * Just warn for now; if it happens then we should find out 2525 * about it. It's highly likely the aggregation session will 2526 * soon hang. 2527 */ 2528 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) { 2529 device_printf(sc->sc_dev, "%s: retransmitted buffer" 2530 " has mismatching seqno's, BA session may hang.\n", 2531 __func__); 2532 device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n", 2533 __func__, 2534 old_bf->bf_state.bfs_seqno, 2535 new_bf->bf_state.bfs_seqno); 2536 } 2537 2538 if (tid->tx_buf[cindex] != old_bf) { 2539 device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; " 2540 " has m BA session may hang.\n", 2541 __func__); 2542 device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n", 2543 __func__, 2544 old_bf, new_bf); 2545 } 2546 2547 tid->tx_buf[cindex] = new_bf; 2548 } 2549 2550 /* 2551 * seq_start - left edge of BAW 2552 * seq_next - current/next sequence number to allocate 2553 * 2554 * Since the BAW status may be modified by both the ath task and 2555 * the net80211/ifnet contexts, the TID must be locked. 2556 */ 2557 static void 2558 ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an, 2559 struct ath_tid *tid, const struct ath_buf *bf) 2560 { 2561 int index, cindex; 2562 struct ieee80211_tx_ampdu *tap; 2563 int seqno = SEQNO(bf->bf_state.bfs_seqno); 2564 2565 ATH_TX_LOCK_ASSERT(sc); 2566 2567 tap = ath_tx_get_tx_tid(an, tid->tid); 2568 index = ATH_BA_INDEX(tap->txa_start, seqno); 2569 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2570 2571 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2572 "%s: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, " 2573 "baw head=%d, tail=%d\n", 2574 __func__, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index, 2575 cindex, tid->baw_head, tid->baw_tail); 2576 2577 /* 2578 * If this occurs then we have a big problem - something else 2579 * has slid tap->txa_start along without updating the BAW 2580 * tracking start/end pointers. Thus the TX BAW state is now 2581 * completely busted. 2582 * 2583 * But for now, since I haven't yet fixed TDMA and buffer cloning, 2584 * it's quite possible that a cloned buffer is making its way 2585 * here and causing it to fire off. Disable TDMA for now. 2586 */ 2587 if (tid->tx_buf[cindex] != bf) { 2588 device_printf(sc->sc_dev, 2589 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n", 2590 __func__, 2591 bf, SEQNO(bf->bf_state.bfs_seqno), 2592 tid->tx_buf[cindex], 2593 (tid->tx_buf[cindex] != NULL) ? 2594 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno) : -1); 2595 } 2596 2597 tid->tx_buf[cindex] = NULL; 2598 2599 while (tid->baw_head != tid->baw_tail && 2600 !tid->tx_buf[tid->baw_head]) { 2601 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 2602 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 2603 } 2604 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2605 "%s: baw is now %d:%d, baw head=%d\n", 2606 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head); 2607 } 2608 2609 /* 2610 * Mark the current node/TID as ready to TX. 2611 * 2612 * This is done to make it easy for the software scheduler to 2613 * find which nodes have data to send. 2614 * 2615 * The TXQ lock must be held. 2616 */ 2617 static void 2618 ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid) 2619 { 2620 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2621 2622 ATH_TX_LOCK_ASSERT(sc); 2623 2624 if (tid->paused) 2625 return; /* paused, can't schedule yet */ 2626 2627 if (tid->sched) 2628 return; /* already scheduled */ 2629 2630 tid->sched = 1; 2631 2632 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem); 2633 } 2634 2635 /* 2636 * Mark the current node as no longer needing to be polled for 2637 * TX packets. 2638 * 2639 * The TXQ lock must be held. 2640 */ 2641 static void 2642 ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid) 2643 { 2644 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2645 2646 ATH_TX_LOCK_ASSERT(sc); 2647 2648 if (tid->sched == 0) 2649 return; 2650 2651 tid->sched = 0; 2652 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem); 2653 } 2654 2655 /* 2656 * Assign a sequence number manually to the given frame. 2657 * 2658 * This should only be called for A-MPDU TX frames. 2659 */ 2660 static ieee80211_seq 2661 ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni, 2662 struct ath_buf *bf, struct mbuf *m0) 2663 { 2664 struct ieee80211_frame *wh; 2665 int tid, pri; 2666 ieee80211_seq seqno; 2667 uint8_t subtype; 2668 2669 /* TID lookup */ 2670 wh = mtod(m0, struct ieee80211_frame *); 2671 pri = M_WME_GETAC(m0); /* honor classification */ 2672 tid = WME_AC_TO_TID(pri); 2673 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pri=%d, tid=%d, qos has seq=%d\n", 2674 __func__, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2675 2676 /* XXX Is it a control frame? Ignore */ 2677 2678 /* Does the packet require a sequence number? */ 2679 if (! IEEE80211_QOS_HAS_SEQ(wh)) 2680 return -1; 2681 2682 ATH_TX_LOCK_ASSERT(sc); 2683 2684 /* 2685 * Is it a QOS NULL Data frame? Give it a sequence number from 2686 * the default TID (IEEE80211_NONQOS_TID.) 2687 * 2688 * The RX path of everything I've looked at doesn't include the NULL 2689 * data frame sequence number in the aggregation state updates, so 2690 * assigning it a sequence number there will cause a BAW hole on the 2691 * RX side. 2692 */ 2693 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2694 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) { 2695 /* XXX no locking for this TID? This is a bit of a problem. */ 2696 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID]; 2697 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE); 2698 } else { 2699 /* Manually assign sequence number */ 2700 seqno = ni->ni_txseqs[tid]; 2701 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE); 2702 } 2703 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 2704 M_SEQNO_SET(m0, seqno); 2705 2706 /* Return so caller can do something with it if needed */ 2707 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: -> seqno=%d\n", __func__, seqno); 2708 return seqno; 2709 } 2710 2711 /* 2712 * Attempt to direct dispatch an aggregate frame to hardware. 2713 * If the frame is out of BAW, queue. 2714 * Otherwise, schedule it as a single frame. 2715 */ 2716 static void 2717 ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an, 2718 struct ath_txq *txq, struct ath_buf *bf) 2719 { 2720 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid]; 2721 struct ieee80211_tx_ampdu *tap; 2722 2723 ATH_TX_LOCK_ASSERT(sc); 2724 2725 tap = ath_tx_get_tx_tid(an, tid->tid); 2726 2727 /* paused? queue */ 2728 if (tid->paused) { 2729 ATH_TID_INSERT_HEAD(tid, bf, bf_list); 2730 /* XXX don't sched - we're paused! */ 2731 return; 2732 } 2733 2734 /* outside baw? queue */ 2735 if (bf->bf_state.bfs_dobaw && 2736 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2737 SEQNO(bf->bf_state.bfs_seqno)))) { 2738 ATH_TID_INSERT_HEAD(tid, bf, bf_list); 2739 ath_tx_tid_sched(sc, tid); 2740 return; 2741 } 2742 2743 /* 2744 * This is a temporary check and should be removed once 2745 * all the relevant code paths have been fixed. 2746 * 2747 * During aggregate retries, it's possible that the head 2748 * frame will fail (which has the bfs_aggr and bfs_nframes 2749 * fields set for said aggregate) and will be retried as 2750 * a single frame. In this instance, the values should 2751 * be reset or the completion code will get upset with you. 2752 */ 2753 if (bf->bf_state.bfs_aggr != 0 || bf->bf_state.bfs_nframes > 1) { 2754 device_printf(sc->sc_dev, "%s: bfs_aggr=%d, bfs_nframes=%d\n", 2755 __func__, 2756 bf->bf_state.bfs_aggr, 2757 bf->bf_state.bfs_nframes); 2758 bf->bf_state.bfs_aggr = 0; 2759 bf->bf_state.bfs_nframes = 1; 2760 } 2761 2762 /* Update CLRDMASK just before this frame is queued */ 2763 ath_tx_update_clrdmask(sc, tid, bf); 2764 2765 /* Direct dispatch to hardware */ 2766 ath_tx_do_ratelookup(sc, bf); 2767 ath_tx_calc_duration(sc, bf); 2768 ath_tx_calc_protection(sc, bf); 2769 ath_tx_set_rtscts(sc, bf); 2770 ath_tx_rate_fill_rcflags(sc, bf); 2771 ath_tx_setds(sc, bf); 2772 2773 /* Statistics */ 2774 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++; 2775 2776 /* Track per-TID hardware queue depth correctly */ 2777 tid->hwq_depth++; 2778 2779 /* Add to BAW */ 2780 if (bf->bf_state.bfs_dobaw) { 2781 ath_tx_addto_baw(sc, an, tid, bf); 2782 bf->bf_state.bfs_addedbaw = 1; 2783 } 2784 2785 /* Set completion handler, multi-frame aggregate or not */ 2786 bf->bf_comp = ath_tx_aggr_comp; 2787 2788 /* Hand off to hardware */ 2789 ath_tx_handoff(sc, txq, bf); 2790 } 2791 2792 /* 2793 * Attempt to send the packet. 2794 * If the queue isn't busy, direct-dispatch. 2795 * If the queue is busy enough, queue the given packet on the 2796 * relevant software queue. 2797 */ 2798 void 2799 ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq, 2800 struct ath_buf *bf) 2801 { 2802 struct ath_node *an = ATH_NODE(ni); 2803 struct ieee80211_frame *wh; 2804 struct ath_tid *atid; 2805 int pri, tid; 2806 struct mbuf *m0 = bf->bf_m; 2807 2808 ATH_TX_LOCK_ASSERT(sc); 2809 2810 /* Fetch the TID - non-QoS frames get assigned to TID 16 */ 2811 wh = mtod(m0, struct ieee80211_frame *); 2812 pri = ath_tx_getac(sc, m0); 2813 tid = ath_tx_gettid(sc, m0); 2814 atid = &an->an_tid[tid]; 2815 2816 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d\n", 2817 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2818 2819 /* Set local packet state, used to queue packets to hardware */ 2820 /* XXX potentially duplicate info, re-check */ 2821 bf->bf_state.bfs_tid = tid; 2822 bf->bf_state.bfs_tx_queue = txq->axq_qnum; 2823 bf->bf_state.bfs_pri = pri; 2824 2825 /* 2826 * If the hardware queue isn't busy, queue it directly. 2827 * If the hardware queue is busy, queue it. 2828 * If the TID is paused or the traffic it outside BAW, software 2829 * queue it. 2830 */ 2831 if (atid->paused) { 2832 /* TID is paused, queue */ 2833 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: paused\n", __func__); 2834 ATH_TID_INSERT_TAIL(atid, bf, bf_list); 2835 } else if (ath_tx_ampdu_pending(sc, an, tid)) { 2836 /* AMPDU pending; queue */ 2837 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pending\n", __func__); 2838 ATH_TID_INSERT_TAIL(atid, bf, bf_list); 2839 /* XXX sched? */ 2840 } else if (ath_tx_ampdu_running(sc, an, tid)) { 2841 /* AMPDU running, attempt direct dispatch if possible */ 2842 2843 /* 2844 * Always queue the frame to the tail of the list. 2845 */ 2846 ATH_TID_INSERT_TAIL(atid, bf, bf_list); 2847 2848 /* 2849 * If the hardware queue isn't busy, direct dispatch 2850 * the head frame in the list. Don't schedule the 2851 * TID - let it build some more frames first? 2852 * 2853 * Otherwise, schedule the TID. 2854 */ 2855 if (txq->axq_depth + txq->fifo.axq_depth < sc->sc_hwq_limit) { 2856 bf = ATH_TID_FIRST(atid); 2857 ATH_TID_REMOVE(atid, bf, bf_list); 2858 2859 /* 2860 * Ensure it's definitely treated as a non-AMPDU 2861 * frame - this information may have been left 2862 * over from a previous attempt. 2863 */ 2864 bf->bf_state.bfs_aggr = 0; 2865 bf->bf_state.bfs_nframes = 1; 2866 2867 /* Queue to the hardware */ 2868 ath_tx_xmit_aggr(sc, an, txq, bf); 2869 DPRINTF(sc, ATH_DEBUG_SW_TX, 2870 "%s: xmit_aggr\n", 2871 __func__); 2872 } else { 2873 DPRINTF(sc, ATH_DEBUG_SW_TX, 2874 "%s: ampdu; swq'ing\n", 2875 __func__); 2876 2877 ath_tx_tid_sched(sc, atid); 2878 } 2879 } else if (txq->axq_depth + txq->fifo.axq_depth < sc->sc_hwq_limit) { 2880 /* AMPDU not running, attempt direct dispatch */ 2881 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: xmit_normal\n", __func__); 2882 /* See if clrdmask needs to be set */ 2883 ath_tx_update_clrdmask(sc, atid, bf); 2884 ath_tx_xmit_normal(sc, txq, bf); 2885 } else { 2886 /* Busy; queue */ 2887 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: swq'ing\n", __func__); 2888 ATH_TID_INSERT_TAIL(atid, bf, bf_list); 2889 ath_tx_tid_sched(sc, atid); 2890 } 2891 } 2892 2893 /* 2894 * Only set the clrdmask bit if none of the nodes are currently 2895 * filtered. 2896 * 2897 * XXX TODO: go through all the callers and check to see 2898 * which are being called in the context of looping over all 2899 * TIDs (eg, if all tids are being paused, resumed, etc.) 2900 * That'll avoid O(n^2) complexity here. 2901 */ 2902 static void 2903 ath_tx_set_clrdmask(struct ath_softc *sc, struct ath_node *an) 2904 { 2905 int i; 2906 2907 ATH_TX_LOCK_ASSERT(sc); 2908 2909 for (i = 0; i < IEEE80211_TID_SIZE; i++) { 2910 if (an->an_tid[i].isfiltered == 1) 2911 return; 2912 } 2913 an->clrdmask = 1; 2914 } 2915 2916 /* 2917 * Configure the per-TID node state. 2918 * 2919 * This likely belongs in if_ath_node.c but I can't think of anywhere 2920 * else to put it just yet. 2921 * 2922 * This sets up the SLISTs and the mutex as appropriate. 2923 */ 2924 void 2925 ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an) 2926 { 2927 int i, j; 2928 struct ath_tid *atid; 2929 2930 for (i = 0; i < IEEE80211_TID_SIZE; i++) { 2931 atid = &an->an_tid[i]; 2932 2933 /* XXX now with this bzer(), is the field 0'ing needed? */ 2934 bzero(atid, sizeof(*atid)); 2935 2936 TAILQ_INIT(&atid->tid_q); 2937 TAILQ_INIT(&atid->filtq.tid_q); 2938 atid->tid = i; 2939 atid->an = an; 2940 for (j = 0; j < ATH_TID_MAX_BUFS; j++) 2941 atid->tx_buf[j] = NULL; 2942 atid->baw_head = atid->baw_tail = 0; 2943 atid->paused = 0; 2944 atid->sched = 0; 2945 atid->hwq_depth = 0; 2946 atid->cleanup_inprogress = 0; 2947 if (i == IEEE80211_NONQOS_TID) 2948 atid->ac = ATH_NONQOS_TID_AC; 2949 else 2950 atid->ac = TID_TO_WME_AC(i); 2951 } 2952 an->clrdmask = 1; /* Always start by setting this bit */ 2953 } 2954 2955 /* 2956 * Pause the current TID. This stops packets from being transmitted 2957 * on it. 2958 * 2959 * Since this is also called from upper layers as well as the driver, 2960 * it will get the TID lock. 2961 */ 2962 static void 2963 ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid) 2964 { 2965 2966 ATH_TX_LOCK_ASSERT(sc); 2967 tid->paused++; 2968 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n", 2969 __func__, tid->paused); 2970 } 2971 2972 /* 2973 * Unpause the current TID, and schedule it if needed. 2974 */ 2975 static void 2976 ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid) 2977 { 2978 ATH_TX_LOCK_ASSERT(sc); 2979 2980 /* 2981 * There's some odd places where ath_tx_tid_resume() is called 2982 * when it shouldn't be; this works around that particular issue 2983 * until it's actually resolved. 2984 */ 2985 if (tid->paused == 0) { 2986 device_printf(sc->sc_dev, "%s: %6D: paused=0?\n", 2987 __func__, 2988 tid->an->an_node.ni_macaddr, 2989 ":"); 2990 } else { 2991 tid->paused--; 2992 } 2993 2994 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n", 2995 __func__, tid->paused); 2996 2997 if (tid->paused) 2998 return; 2999 3000 /* 3001 * Override the clrdmask configuration for the next frame 3002 * from this TID, just to get the ball rolling. 3003 */ 3004 ath_tx_set_clrdmask(sc, tid->an); 3005 3006 if (tid->axq_depth == 0) 3007 return; 3008 3009 /* XXX isfiltered shouldn't ever be 0 at this point */ 3010 if (tid->isfiltered == 1) { 3011 device_printf(sc->sc_dev, "%s: filtered?!\n", __func__); 3012 return; 3013 } 3014 3015 ath_tx_tid_sched(sc, tid); 3016 3017 /* 3018 * Queue the software TX scheduler. 3019 */ 3020 ath_tx_swq_kick(sc); 3021 } 3022 3023 /* 3024 * Add the given ath_buf to the TID filtered frame list. 3025 * This requires the TID be filtered. 3026 */ 3027 static void 3028 ath_tx_tid_filt_addbuf(struct ath_softc *sc, struct ath_tid *tid, 3029 struct ath_buf *bf) 3030 { 3031 3032 ATH_TX_LOCK_ASSERT(sc); 3033 3034 if (! tid->isfiltered) 3035 device_printf(sc->sc_dev, "%s: not filtered?!\n", __func__); 3036 3037 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: bf=%p\n", __func__, bf); 3038 3039 /* Set the retry bit and bump the retry counter */ 3040 ath_tx_set_retry(sc, bf); 3041 sc->sc_stats.ast_tx_swfiltered++; 3042 3043 ATH_TID_FILT_INSERT_TAIL(tid, bf, bf_list); 3044 } 3045 3046 /* 3047 * Handle a completed filtered frame from the given TID. 3048 * This just enables/pauses the filtered frame state if required 3049 * and appends the filtered frame to the filtered queue. 3050 */ 3051 static void 3052 ath_tx_tid_filt_comp_buf(struct ath_softc *sc, struct ath_tid *tid, 3053 struct ath_buf *bf) 3054 { 3055 3056 ATH_TX_LOCK_ASSERT(sc); 3057 3058 if (! tid->isfiltered) { 3059 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: filter transition\n", 3060 __func__); 3061 tid->isfiltered = 1; 3062 ath_tx_tid_pause(sc, tid); 3063 } 3064 3065 /* Add the frame to the filter queue */ 3066 ath_tx_tid_filt_addbuf(sc, tid, bf); 3067 } 3068 3069 /* 3070 * Complete the filtered frame TX completion. 3071 * 3072 * If there are no more frames in the hardware queue, unpause/unfilter 3073 * the TID if applicable. Otherwise we will wait for a node PS transition 3074 * to unfilter. 3075 */ 3076 static void 3077 ath_tx_tid_filt_comp_complete(struct ath_softc *sc, struct ath_tid *tid) 3078 { 3079 struct ath_buf *bf; 3080 3081 ATH_TX_LOCK_ASSERT(sc); 3082 3083 if (tid->hwq_depth != 0) 3084 return; 3085 3086 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: hwq=0, transition back\n", 3087 __func__); 3088 tid->isfiltered = 0; 3089 /* XXX ath_tx_tid_resume() also calls ath_tx_set_clrdmask()! */ 3090 ath_tx_set_clrdmask(sc, tid->an); 3091 3092 /* XXX this is really quite inefficient */ 3093 while ((bf = ATH_TID_FILT_LAST(tid, ath_bufhead_s)) != NULL) { 3094 ATH_TID_FILT_REMOVE(tid, bf, bf_list); 3095 ATH_TID_INSERT_HEAD(tid, bf, bf_list); 3096 } 3097 3098 ath_tx_tid_resume(sc, tid); 3099 } 3100 3101 /* 3102 * Called when a single (aggregate or otherwise) frame is completed. 3103 * 3104 * Returns 1 if the buffer could be added to the filtered list 3105 * (cloned or otherwise), 0 if the buffer couldn't be added to the 3106 * filtered list (failed clone; expired retry) and the caller should 3107 * free it and handle it like a failure (eg by sending a BAR.) 3108 */ 3109 static int 3110 ath_tx_tid_filt_comp_single(struct ath_softc *sc, struct ath_tid *tid, 3111 struct ath_buf *bf) 3112 { 3113 struct ath_buf *nbf; 3114 int retval; 3115 3116 ATH_TX_LOCK_ASSERT(sc); 3117 3118 /* 3119 * Don't allow a filtered frame to live forever. 3120 */ 3121 if (bf->bf_state.bfs_retries > SWMAX_RETRIES) { 3122 sc->sc_stats.ast_tx_swretrymax++; 3123 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3124 "%s: bf=%p, seqno=%d, exceeded retries\n", 3125 __func__, 3126 bf, 3127 bf->bf_state.bfs_seqno); 3128 return (0); 3129 } 3130 3131 /* 3132 * A busy buffer can't be added to the retry list. 3133 * It needs to be cloned. 3134 */ 3135 if (bf->bf_flags & ATH_BUF_BUSY) { 3136 nbf = ath_tx_retry_clone(sc, tid->an, tid, bf); 3137 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3138 "%s: busy buffer clone: %p -> %p\n", 3139 __func__, bf, nbf); 3140 } else { 3141 nbf = bf; 3142 } 3143 3144 if (nbf == NULL) { 3145 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3146 "%s: busy buffer couldn't be cloned (%p)!\n", 3147 __func__, bf); 3148 retval = 1; 3149 } else { 3150 ath_tx_tid_filt_comp_buf(sc, tid, nbf); 3151 retval = 0; 3152 } 3153 ath_tx_tid_filt_comp_complete(sc, tid); 3154 3155 return (retval); 3156 } 3157 3158 static void 3159 ath_tx_tid_filt_comp_aggr(struct ath_softc *sc, struct ath_tid *tid, 3160 struct ath_buf *bf_first, ath_bufhead *bf_q) 3161 { 3162 struct ath_buf *bf, *bf_next, *nbf; 3163 3164 ATH_TX_LOCK_ASSERT(sc); 3165 3166 bf = bf_first; 3167 while (bf) { 3168 bf_next = bf->bf_next; 3169 bf->bf_next = NULL; /* Remove it from the aggr list */ 3170 3171 /* 3172 * Don't allow a filtered frame to live forever. 3173 */ 3174 if (bf->bf_state.bfs_retries > SWMAX_RETRIES) { 3175 sc->sc_stats.ast_tx_swretrymax++; 3176 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3177 "%s: bf=%p, seqno=%d, exceeded retries\n", 3178 __func__, 3179 bf, 3180 bf->bf_state.bfs_seqno); 3181 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 3182 goto next; 3183 } 3184 3185 if (bf->bf_flags & ATH_BUF_BUSY) { 3186 nbf = ath_tx_retry_clone(sc, tid->an, tid, bf); 3187 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3188 "%s: busy buffer cloned: %p -> %p", 3189 __func__, bf, nbf); 3190 } else { 3191 nbf = bf; 3192 } 3193 3194 /* 3195 * If the buffer couldn't be cloned, add it to bf_q; 3196 * the caller will free the buffer(s) as required. 3197 */ 3198 if (nbf == NULL) { 3199 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, 3200 "%s: buffer couldn't be cloned! (%p)\n", 3201 __func__, bf); 3202 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 3203 } else { 3204 ath_tx_tid_filt_comp_buf(sc, tid, nbf); 3205 } 3206 next: 3207 bf = bf_next; 3208 } 3209 3210 ath_tx_tid_filt_comp_complete(sc, tid); 3211 } 3212 3213 /* 3214 * Suspend the queue because we need to TX a BAR. 3215 */ 3216 static void 3217 ath_tx_tid_bar_suspend(struct ath_softc *sc, struct ath_tid *tid) 3218 { 3219 3220 ATH_TX_LOCK_ASSERT(sc); 3221 3222 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3223 "%s: tid=%p, bar_wait=%d, bar_tx=%d, called\n", 3224 __func__, 3225 tid, 3226 tid->bar_wait, 3227 tid->bar_tx); 3228 3229 /* We shouldn't be called when bar_tx is 1 */ 3230 if (tid->bar_tx) { 3231 device_printf(sc->sc_dev, "%s: bar_tx is 1?!\n", 3232 __func__); 3233 } 3234 3235 /* If we've already been called, just be patient. */ 3236 if (tid->bar_wait) 3237 return; 3238 3239 /* Wait! */ 3240 tid->bar_wait = 1; 3241 3242 /* Only one pause, no matter how many frames fail */ 3243 ath_tx_tid_pause(sc, tid); 3244 } 3245 3246 /* 3247 * We've finished with BAR handling - either we succeeded or 3248 * failed. Either way, unsuspend TX. 3249 */ 3250 static void 3251 ath_tx_tid_bar_unsuspend(struct ath_softc *sc, struct ath_tid *tid) 3252 { 3253 3254 ATH_TX_LOCK_ASSERT(sc); 3255 3256 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3257 "%s: tid=%p, called\n", 3258 __func__, 3259 tid); 3260 3261 if (tid->bar_tx == 0 || tid->bar_wait == 0) { 3262 device_printf(sc->sc_dev, "%s: bar_tx=%d, bar_wait=%d: ?\n", 3263 __func__, tid->bar_tx, tid->bar_wait); 3264 } 3265 3266 tid->bar_tx = tid->bar_wait = 0; 3267 ath_tx_tid_resume(sc, tid); 3268 } 3269 3270 /* 3271 * Return whether we're ready to TX a BAR frame. 3272 * 3273 * Requires the TID lock be held. 3274 */ 3275 static int 3276 ath_tx_tid_bar_tx_ready(struct ath_softc *sc, struct ath_tid *tid) 3277 { 3278 3279 ATH_TX_LOCK_ASSERT(sc); 3280 3281 if (tid->bar_wait == 0 || tid->hwq_depth > 0) 3282 return (0); 3283 3284 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, "%s: tid=%p (%d), bar ready\n", 3285 __func__, tid, tid->tid); 3286 3287 return (1); 3288 } 3289 3290 /* 3291 * Check whether the current TID is ready to have a BAR 3292 * TXed and if so, do the TX. 3293 * 3294 * Since the TID/TXQ lock can't be held during a call to 3295 * ieee80211_send_bar(), we have to do the dirty thing of unlocking it, 3296 * sending the BAR and locking it again. 3297 * 3298 * Eventually, the code to send the BAR should be broken out 3299 * from this routine so the lock doesn't have to be reacquired 3300 * just to be immediately dropped by the caller. 3301 */ 3302 static void 3303 ath_tx_tid_bar_tx(struct ath_softc *sc, struct ath_tid *tid) 3304 { 3305 struct ieee80211_tx_ampdu *tap; 3306 3307 ATH_TX_LOCK_ASSERT(sc); 3308 3309 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3310 "%s: tid=%p, called\n", 3311 __func__, 3312 tid); 3313 3314 tap = ath_tx_get_tx_tid(tid->an, tid->tid); 3315 3316 /* 3317 * This is an error condition! 3318 */ 3319 if (tid->bar_wait == 0 || tid->bar_tx == 1) { 3320 device_printf(sc->sc_dev, 3321 "%s: tid=%p, bar_tx=%d, bar_wait=%d: ?\n", 3322 __func__, 3323 tid, 3324 tid->bar_tx, 3325 tid->bar_wait); 3326 return; 3327 } 3328 3329 /* Don't do anything if we still have pending frames */ 3330 if (tid->hwq_depth > 0) { 3331 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3332 "%s: tid=%p, hwq_depth=%d, waiting\n", 3333 __func__, 3334 tid, 3335 tid->hwq_depth); 3336 return; 3337 } 3338 3339 /* We're now about to TX */ 3340 tid->bar_tx = 1; 3341 3342 /* 3343 * Override the clrdmask configuration for the next frame, 3344 * just to get the ball rolling. 3345 */ 3346 ath_tx_set_clrdmask(sc, tid->an); 3347 3348 /* 3349 * Calculate new BAW left edge, now that all frames have either 3350 * succeeded or failed. 3351 * 3352 * XXX verify this is _actually_ the valid value to begin at! 3353 */ 3354 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 3355 "%s: tid=%p, new BAW left edge=%d\n", 3356 __func__, 3357 tid, 3358 tap->txa_start); 3359 3360 /* Try sending the BAR frame */ 3361 /* We can't hold the lock here! */ 3362 3363 ATH_TX_UNLOCK(sc); 3364 if (ieee80211_send_bar(&tid->an->an_node, tap, tap->txa_start) == 0) { 3365 /* Success? Now we wait for notification that it's done */ 3366 ATH_TX_LOCK(sc); 3367 return; 3368 } 3369 3370 /* Failure? For now, warn loudly and continue */ 3371 ATH_TX_LOCK(sc); 3372 device_printf(sc->sc_dev, "%s: tid=%p, failed to TX BAR, continue!\n", 3373 __func__, tid); 3374 ath_tx_tid_bar_unsuspend(sc, tid); 3375 } 3376 3377 static void 3378 ath_tx_tid_drain_pkt(struct ath_softc *sc, struct ath_node *an, 3379 struct ath_tid *tid, ath_bufhead *bf_cq, struct ath_buf *bf) 3380 { 3381 3382 ATH_TX_LOCK_ASSERT(sc); 3383 3384 /* 3385 * If the current TID is running AMPDU, update 3386 * the BAW. 3387 */ 3388 if (ath_tx_ampdu_running(sc, an, tid->tid) && 3389 bf->bf_state.bfs_dobaw) { 3390 /* 3391 * Only remove the frame from the BAW if it's 3392 * been transmitted at least once; this means 3393 * the frame was in the BAW to begin with. 3394 */ 3395 if (bf->bf_state.bfs_retries > 0) { 3396 ath_tx_update_baw(sc, an, tid, bf); 3397 bf->bf_state.bfs_dobaw = 0; 3398 } 3399 #if 0 3400 /* 3401 * This has become a non-fatal error now 3402 */ 3403 if (! bf->bf_state.bfs_addedbaw) 3404 device_printf(sc->sc_dev, 3405 "%s: wasn't added: seqno %d\n", 3406 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3407 #endif 3408 } 3409 3410 /* Strip it out of an aggregate list if it was in one */ 3411 bf->bf_next = NULL; 3412 3413 /* Insert on the free queue to be freed by the caller */ 3414 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list); 3415 } 3416 3417 static void 3418 ath_tx_tid_drain_print(struct ath_softc *sc, struct ath_node *an, 3419 const char *pfx, struct ath_tid *tid, struct ath_buf *bf) 3420 { 3421 struct ieee80211_node *ni = &an->an_node; 3422 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 3423 struct ieee80211_tx_ampdu *tap; 3424 3425 tap = ath_tx_get_tx_tid(an, tid->tid); 3426 3427 device_printf(sc->sc_dev, 3428 "%s: %s: node %p: bf=%p: addbaw=%d, dobaw=%d, " 3429 "seqno=%d, retry=%d\n", 3430 __func__, pfx, ni, bf, 3431 bf->bf_state.bfs_addedbaw, 3432 bf->bf_state.bfs_dobaw, 3433 SEQNO(bf->bf_state.bfs_seqno), 3434 bf->bf_state.bfs_retries); 3435 device_printf(sc->sc_dev, 3436 "%s: node %p: bf=%p: txq[%d] axq_depth=%d, axq_aggr_depth=%d\n", 3437 __func__, ni, bf, 3438 txq->axq_qnum, 3439 txq->axq_depth, 3440 txq->axq_aggr_depth); 3441 3442 device_printf(sc->sc_dev, 3443 "%s: node %p: bf=%p: tid txq_depth=%d hwq_depth=%d, bar_wait=%d, isfiltered=%d\n", 3444 __func__, ni, bf, 3445 tid->axq_depth, 3446 tid->hwq_depth, 3447 tid->bar_wait, 3448 tid->isfiltered); 3449 device_printf(sc->sc_dev, 3450 "%s: node %p: tid %d: " 3451 "sched=%d, paused=%d, " 3452 "incomp=%d, baw_head=%d, " 3453 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n", 3454 __func__, ni, tid->tid, 3455 tid->sched, tid->paused, 3456 tid->incomp, tid->baw_head, 3457 tid->baw_tail, tap == NULL ? -1 : tap->txa_start, 3458 ni->ni_txseqs[tid->tid]); 3459 3460 /* XXX Dump the frame, see what it is? */ 3461 ieee80211_dump_pkt(ni->ni_ic, 3462 mtod(bf->bf_m, const uint8_t *), 3463 bf->bf_m->m_len, 0, -1); 3464 } 3465 3466 /* 3467 * Free any packets currently pending in the software TX queue. 3468 * 3469 * This will be called when a node is being deleted. 3470 * 3471 * It can also be called on an active node during an interface 3472 * reset or state transition. 3473 * 3474 * (From Linux/reference): 3475 * 3476 * TODO: For frame(s) that are in the retry state, we will reuse the 3477 * sequence number(s) without setting the retry bit. The 3478 * alternative is to give up on these and BAR the receiver's window 3479 * forward. 3480 */ 3481 static void 3482 ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an, 3483 struct ath_tid *tid, ath_bufhead *bf_cq) 3484 { 3485 struct ath_buf *bf; 3486 struct ieee80211_tx_ampdu *tap; 3487 struct ieee80211_node *ni = &an->an_node; 3488 int t; 3489 3490 tap = ath_tx_get_tx_tid(an, tid->tid); 3491 3492 ATH_TX_LOCK_ASSERT(sc); 3493 3494 /* Walk the queue, free frames */ 3495 t = 0; 3496 for (;;) { 3497 bf = ATH_TID_FIRST(tid); 3498 if (bf == NULL) { 3499 break; 3500 } 3501 3502 if (t == 0) { 3503 ath_tx_tid_drain_print(sc, an, "norm", tid, bf); 3504 t = 1; 3505 } 3506 3507 ATH_TID_REMOVE(tid, bf, bf_list); 3508 ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf); 3509 } 3510 3511 /* And now, drain the filtered frame queue */ 3512 t = 0; 3513 for (;;) { 3514 bf = ATH_TID_FILT_FIRST(tid); 3515 if (bf == NULL) 3516 break; 3517 3518 if (t == 0) { 3519 ath_tx_tid_drain_print(sc, an, "filt", tid, bf); 3520 t = 1; 3521 } 3522 3523 ATH_TID_FILT_REMOVE(tid, bf, bf_list); 3524 ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf); 3525 } 3526 3527 /* 3528 * Override the clrdmask configuration for the next frame 3529 * in case there is some future transmission, just to get 3530 * the ball rolling. 3531 * 3532 * This won't hurt things if the TID is about to be freed. 3533 */ 3534 ath_tx_set_clrdmask(sc, tid->an); 3535 3536 /* 3537 * Now that it's completed, grab the TID lock and update 3538 * the sequence number and BAW window. 3539 * Because sequence numbers have been assigned to frames 3540 * that haven't been sent yet, it's entirely possible 3541 * we'll be called with some pending frames that have not 3542 * been transmitted. 3543 * 3544 * The cleaner solution is to do the sequence number allocation 3545 * when the packet is first transmitted - and thus the "retries" 3546 * check above would be enough to update the BAW/seqno. 3547 */ 3548 3549 /* But don't do it for non-QoS TIDs */ 3550 if (tap) { 3551 #if 0 3552 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3553 "%s: node %p: TID %d: sliding BAW left edge to %d\n", 3554 __func__, an, tid->tid, tap->txa_start); 3555 #endif 3556 ni->ni_txseqs[tid->tid] = tap->txa_start; 3557 tid->baw_tail = tid->baw_head; 3558 } 3559 } 3560 3561 /* 3562 * Flush all software queued packets for the given node. 3563 * 3564 * This occurs when a completion handler frees the last buffer 3565 * for a node, and the node is thus freed. This causes the node 3566 * to be cleaned up, which ends up calling ath_tx_node_flush. 3567 */ 3568 void 3569 ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an) 3570 { 3571 int tid; 3572 ath_bufhead bf_cq; 3573 struct ath_buf *bf; 3574 3575 TAILQ_INIT(&bf_cq); 3576 3577 ATH_KTR(sc, ATH_KTR_NODE, 1, "ath_tx_node_flush: flush node; ni=%p", 3578 &an->an_node); 3579 3580 ATH_TX_LOCK(sc); 3581 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 3582 struct ath_tid *atid = &an->an_tid[tid]; 3583 3584 /* Free packets */ 3585 ath_tx_tid_drain(sc, an, atid, &bf_cq); 3586 /* Remove this tid from the list of active tids */ 3587 ath_tx_tid_unsched(sc, atid); 3588 } 3589 ATH_TX_UNLOCK(sc); 3590 3591 /* Handle completed frames */ 3592 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3593 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3594 ath_tx_default_comp(sc, bf, 0); 3595 } 3596 } 3597 3598 /* 3599 * Drain all the software TXQs currently with traffic queued. 3600 */ 3601 void 3602 ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq) 3603 { 3604 struct ath_tid *tid; 3605 ath_bufhead bf_cq; 3606 struct ath_buf *bf; 3607 3608 TAILQ_INIT(&bf_cq); 3609 ATH_TX_LOCK(sc); 3610 3611 /* 3612 * Iterate over all active tids for the given txq, 3613 * flushing and unsched'ing them 3614 */ 3615 while (! TAILQ_EMPTY(&txq->axq_tidq)) { 3616 tid = TAILQ_FIRST(&txq->axq_tidq); 3617 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq); 3618 ath_tx_tid_unsched(sc, tid); 3619 } 3620 3621 ATH_TX_UNLOCK(sc); 3622 3623 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3624 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3625 ath_tx_default_comp(sc, bf, 0); 3626 } 3627 } 3628 3629 /* 3630 * Handle completion of non-aggregate session frames. 3631 * 3632 * This (currently) doesn't implement software retransmission of 3633 * non-aggregate frames! 3634 * 3635 * Software retransmission of non-aggregate frames needs to obey 3636 * the strict sequence number ordering, and drop any frames that 3637 * will fail this. 3638 * 3639 * For now, filtered frames and frame transmission will cause 3640 * all kinds of issues. So we don't support them. 3641 * 3642 * So anyone queuing frames via ath_tx_normal_xmit() or 3643 * ath_tx_hw_queue_norm() must override and set CLRDMASK. 3644 */ 3645 void 3646 ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3647 { 3648 struct ieee80211_node *ni = bf->bf_node; 3649 struct ath_node *an = ATH_NODE(ni); 3650 int tid = bf->bf_state.bfs_tid; 3651 struct ath_tid *atid = &an->an_tid[tid]; 3652 struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3653 3654 /* The TID state is protected behind the TXQ lock */ 3655 ATH_TX_LOCK(sc); 3656 3657 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n", 3658 __func__, bf, fail, atid->hwq_depth - 1); 3659 3660 atid->hwq_depth--; 3661 3662 #if 0 3663 /* 3664 * If the frame was filtered, stick it on the filter frame 3665 * queue and complain about it. It shouldn't happen! 3666 */ 3667 if ((ts->ts_status & HAL_TXERR_FILT) || 3668 (ts->ts_status != 0 && atid->isfiltered)) { 3669 device_printf(sc->sc_dev, 3670 "%s: isfiltered=%d, ts_status=%d: huh?\n", 3671 __func__, 3672 atid->isfiltered, 3673 ts->ts_status); 3674 ath_tx_tid_filt_comp_buf(sc, atid, bf); 3675 } 3676 #endif 3677 if (atid->isfiltered) 3678 device_printf(sc->sc_dev, "%s: filtered?!\n", __func__); 3679 if (atid->hwq_depth < 0) 3680 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3681 __func__, atid->hwq_depth); 3682 3683 /* 3684 * If the queue is filtered, potentially mark it as complete 3685 * and reschedule it as needed. 3686 * 3687 * This is required as there may be a subsequent TX descriptor 3688 * for this end-node that has CLRDMASK set, so it's quite possible 3689 * that a filtered frame will be followed by a non-filtered 3690 * (complete or otherwise) frame. 3691 * 3692 * XXX should we do this before we complete the frame? 3693 */ 3694 if (atid->isfiltered) 3695 ath_tx_tid_filt_comp_complete(sc, atid); 3696 ATH_TX_UNLOCK(sc); 3697 3698 /* 3699 * punt to rate control if we're not being cleaned up 3700 * during a hw queue drain and the frame wanted an ACK. 3701 */ 3702 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 3703 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3704 ts, bf->bf_state.bfs_pktlen, 3705 1, (ts->ts_status == 0) ? 0 : 1); 3706 3707 ath_tx_default_comp(sc, bf, fail); 3708 } 3709 3710 /* 3711 * Handle cleanup of aggregate session packets that aren't 3712 * an A-MPDU. 3713 * 3714 * There's no need to update the BAW here - the session is being 3715 * torn down. 3716 */ 3717 static void 3718 ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3719 { 3720 struct ieee80211_node *ni = bf->bf_node; 3721 struct ath_node *an = ATH_NODE(ni); 3722 int tid = bf->bf_state.bfs_tid; 3723 struct ath_tid *atid = &an->an_tid[tid]; 3724 3725 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n", 3726 __func__, tid, atid->incomp); 3727 3728 ATH_TX_LOCK(sc); 3729 atid->incomp--; 3730 if (atid->incomp == 0) { 3731 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3732 "%s: TID %d: cleaned up! resume!\n", 3733 __func__, tid); 3734 atid->cleanup_inprogress = 0; 3735 ath_tx_tid_resume(sc, atid); 3736 } 3737 ATH_TX_UNLOCK(sc); 3738 3739 ath_tx_default_comp(sc, bf, 0); 3740 } 3741 3742 /* 3743 * Performs transmit side cleanup when TID changes from aggregated to 3744 * unaggregated. 3745 * 3746 * - Discard all retry frames from the s/w queue. 3747 * - Fix the tx completion function for all buffers in s/w queue. 3748 * - Count the number of unacked frames, and let transmit completion 3749 * handle it later. 3750 * 3751 * The caller is responsible for pausing the TID. 3752 */ 3753 static void 3754 ath_tx_tid_cleanup(struct ath_softc *sc, struct ath_node *an, int tid) 3755 { 3756 struct ath_tid *atid = &an->an_tid[tid]; 3757 struct ieee80211_tx_ampdu *tap; 3758 struct ath_buf *bf, *bf_next; 3759 ath_bufhead bf_cq; 3760 3761 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 3762 "%s: TID %d: called\n", __func__, tid); 3763 3764 TAILQ_INIT(&bf_cq); 3765 ATH_TX_LOCK(sc); 3766 3767 /* 3768 * Move the filtered frames to the TX queue, before 3769 * we run off and discard/process things. 3770 */ 3771 /* XXX this is really quite inefficient */ 3772 while ((bf = ATH_TID_FILT_LAST(atid, ath_bufhead_s)) != NULL) { 3773 ATH_TID_FILT_REMOVE(atid, bf, bf_list); 3774 ATH_TID_INSERT_HEAD(atid, bf, bf_list); 3775 } 3776 3777 /* 3778 * Update the frames in the software TX queue: 3779 * 3780 * + Discard retry frames in the queue 3781 * + Fix the completion function to be non-aggregate 3782 */ 3783 bf = ATH_TID_FIRST(atid); 3784 while (bf) { 3785 if (bf->bf_state.bfs_isretried) { 3786 bf_next = TAILQ_NEXT(bf, bf_list); 3787 ATH_TID_REMOVE(atid, bf, bf_list); 3788 if (bf->bf_state.bfs_dobaw) { 3789 ath_tx_update_baw(sc, an, atid, bf); 3790 if (! bf->bf_state.bfs_addedbaw) 3791 device_printf(sc->sc_dev, 3792 "%s: wasn't added: seqno %d\n", 3793 __func__, 3794 SEQNO(bf->bf_state.bfs_seqno)); 3795 } 3796 bf->bf_state.bfs_dobaw = 0; 3797 /* 3798 * Call the default completion handler with "fail" just 3799 * so upper levels are suitably notified about this. 3800 */ 3801 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3802 bf = bf_next; 3803 continue; 3804 } 3805 /* Give these the default completion handler */ 3806 bf->bf_comp = ath_tx_normal_comp; 3807 bf = TAILQ_NEXT(bf, bf_list); 3808 } 3809 3810 /* The caller is required to pause the TID */ 3811 #if 0 3812 /* Pause the TID */ 3813 ath_tx_tid_pause(sc, atid); 3814 #endif 3815 3816 /* 3817 * Calculate what hardware-queued frames exist based 3818 * on the current BAW size. Ie, what frames have been 3819 * added to the TX hardware queue for this TID but 3820 * not yet ACKed. 3821 */ 3822 tap = ath_tx_get_tx_tid(an, tid); 3823 /* Need the lock - fiddling with BAW */ 3824 while (atid->baw_head != atid->baw_tail) { 3825 if (atid->tx_buf[atid->baw_head]) { 3826 atid->incomp++; 3827 atid->cleanup_inprogress = 1; 3828 atid->tx_buf[atid->baw_head] = NULL; 3829 } 3830 INCR(atid->baw_head, ATH_TID_MAX_BUFS); 3831 INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 3832 } 3833 3834 /* 3835 * If cleanup is required, defer TID scheduling 3836 * until all the HW queued packets have been 3837 * sent. 3838 */ 3839 if (! atid->cleanup_inprogress) 3840 ath_tx_tid_resume(sc, atid); 3841 3842 if (atid->cleanup_inprogress) 3843 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3844 "%s: TID %d: cleanup needed: %d packets\n", 3845 __func__, tid, atid->incomp); 3846 ATH_TX_UNLOCK(sc); 3847 3848 /* Handle completing frames and fail them */ 3849 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3850 TAILQ_REMOVE(&bf_cq, bf, bf_list); 3851 ath_tx_default_comp(sc, bf, 1); 3852 } 3853 } 3854 3855 static struct ath_buf * 3856 ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 3857 struct ath_tid *tid, struct ath_buf *bf) 3858 { 3859 struct ath_buf *nbf; 3860 int error; 3861 3862 /* 3863 * Clone the buffer. This will handle the dma unmap and 3864 * copy the node reference to the new buffer. If this 3865 * works out, 'bf' will have no DMA mapping, no mbuf 3866 * pointer and no node reference. 3867 */ 3868 nbf = ath_buf_clone(sc, bf); 3869 3870 #if 0 3871 device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n", 3872 __func__); 3873 #endif 3874 3875 if (nbf == NULL) { 3876 /* Failed to clone */ 3877 device_printf(sc->sc_dev, 3878 "%s: failed to clone a busy buffer\n", 3879 __func__); 3880 return NULL; 3881 } 3882 3883 /* Setup the dma for the new buffer */ 3884 error = ath_tx_dmasetup(sc, nbf, nbf->bf_m); 3885 if (error != 0) { 3886 device_printf(sc->sc_dev, 3887 "%s: failed to setup dma for clone\n", 3888 __func__); 3889 /* 3890 * Put this at the head of the list, not tail; 3891 * that way it doesn't interfere with the 3892 * busy buffer logic (which uses the tail of 3893 * the list.) 3894 */ 3895 ATH_TXBUF_LOCK(sc); 3896 ath_returnbuf_head(sc, nbf); 3897 ATH_TXBUF_UNLOCK(sc); 3898 return NULL; 3899 } 3900 3901 /* Update BAW if required, before we free the original buf */ 3902 if (bf->bf_state.bfs_dobaw) 3903 ath_tx_switch_baw_buf(sc, an, tid, bf, nbf); 3904 3905 /* Free original buffer; return new buffer */ 3906 ath_freebuf(sc, bf); 3907 3908 return nbf; 3909 } 3910 3911 /* 3912 * Handle retrying an unaggregate frame in an aggregate 3913 * session. 3914 * 3915 * If too many retries occur, pause the TID, wait for 3916 * any further retransmits (as there's no reason why 3917 * non-aggregate frames in an aggregate session are 3918 * transmitted in-order; they just have to be in-BAW) 3919 * and then queue a BAR. 3920 */ 3921 static void 3922 ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3923 { 3924 struct ieee80211_node *ni = bf->bf_node; 3925 struct ath_node *an = ATH_NODE(ni); 3926 int tid = bf->bf_state.bfs_tid; 3927 struct ath_tid *atid = &an->an_tid[tid]; 3928 struct ieee80211_tx_ampdu *tap; 3929 3930 ATH_TX_LOCK(sc); 3931 3932 tap = ath_tx_get_tx_tid(an, tid); 3933 3934 /* 3935 * If the buffer is marked as busy, we can't directly 3936 * reuse it. Instead, try to clone the buffer. 3937 * If the clone is successful, recycle the old buffer. 3938 * If the clone is unsuccessful, set bfs_retries to max 3939 * to force the next bit of code to free the buffer 3940 * for us. 3941 */ 3942 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3943 (bf->bf_flags & ATH_BUF_BUSY)) { 3944 struct ath_buf *nbf; 3945 nbf = ath_tx_retry_clone(sc, an, atid, bf); 3946 if (nbf) 3947 /* bf has been freed at this point */ 3948 bf = nbf; 3949 else 3950 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3951 } 3952 3953 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3954 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3955 "%s: exceeded retries; seqno %d\n", 3956 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3957 sc->sc_stats.ast_tx_swretrymax++; 3958 3959 /* Update BAW anyway */ 3960 if (bf->bf_state.bfs_dobaw) { 3961 ath_tx_update_baw(sc, an, atid, bf); 3962 if (! bf->bf_state.bfs_addedbaw) 3963 device_printf(sc->sc_dev, 3964 "%s: wasn't added: seqno %d\n", 3965 __func__, SEQNO(bf->bf_state.bfs_seqno)); 3966 } 3967 bf->bf_state.bfs_dobaw = 0; 3968 3969 /* Suspend the TX queue and get ready to send the BAR */ 3970 ath_tx_tid_bar_suspend(sc, atid); 3971 3972 /* Send the BAR if there are no other frames waiting */ 3973 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3974 ath_tx_tid_bar_tx(sc, atid); 3975 3976 ATH_TX_UNLOCK(sc); 3977 3978 /* Free buffer, bf is free after this call */ 3979 ath_tx_default_comp(sc, bf, 0); 3980 return; 3981 } 3982 3983 /* 3984 * This increments the retry counter as well as 3985 * sets the retry flag in the ath_buf and packet 3986 * body. 3987 */ 3988 ath_tx_set_retry(sc, bf); 3989 sc->sc_stats.ast_tx_swretries++; 3990 3991 /* 3992 * Insert this at the head of the queue, so it's 3993 * retried before any current/subsequent frames. 3994 */ 3995 ATH_TID_INSERT_HEAD(atid, bf, bf_list); 3996 ath_tx_tid_sched(sc, atid); 3997 /* Send the BAR if there are no other frames waiting */ 3998 if (ath_tx_tid_bar_tx_ready(sc, atid)) 3999 ath_tx_tid_bar_tx(sc, atid); 4000 4001 ATH_TX_UNLOCK(sc); 4002 } 4003 4004 /* 4005 * Common code for aggregate excessive retry/subframe retry. 4006 * If retrying, queues buffers to bf_q. If not, frees the 4007 * buffers. 4008 * 4009 * XXX should unify this with ath_tx_aggr_retry_unaggr() 4010 */ 4011 static int 4012 ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf, 4013 ath_bufhead *bf_q) 4014 { 4015 struct ieee80211_node *ni = bf->bf_node; 4016 struct ath_node *an = ATH_NODE(ni); 4017 int tid = bf->bf_state.bfs_tid; 4018 struct ath_tid *atid = &an->an_tid[tid]; 4019 4020 ATH_TX_LOCK_ASSERT(sc); 4021 4022 /* XXX clr11naggr should be done for all subframes */ 4023 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4024 ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0); 4025 4026 /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */ 4027 4028 /* 4029 * If the buffer is marked as busy, we can't directly 4030 * reuse it. Instead, try to clone the buffer. 4031 * If the clone is successful, recycle the old buffer. 4032 * If the clone is unsuccessful, set bfs_retries to max 4033 * to force the next bit of code to free the buffer 4034 * for us. 4035 */ 4036 if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 4037 (bf->bf_flags & ATH_BUF_BUSY)) { 4038 struct ath_buf *nbf; 4039 nbf = ath_tx_retry_clone(sc, an, atid, bf); 4040 if (nbf) 4041 /* bf has been freed at this point */ 4042 bf = nbf; 4043 else 4044 bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 4045 } 4046 4047 if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 4048 sc->sc_stats.ast_tx_swretrymax++; 4049 DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 4050 "%s: max retries: seqno %d\n", 4051 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4052 ath_tx_update_baw(sc, an, atid, bf); 4053 if (! bf->bf_state.bfs_addedbaw) 4054 device_printf(sc->sc_dev, 4055 "%s: wasn't added: seqno %d\n", 4056 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4057 bf->bf_state.bfs_dobaw = 0; 4058 return 1; 4059 } 4060 4061 ath_tx_set_retry(sc, bf); 4062 sc->sc_stats.ast_tx_swretries++; 4063 bf->bf_next = NULL; /* Just to make sure */ 4064 4065 /* Clear the aggregate state */ 4066 bf->bf_state.bfs_aggr = 0; 4067 bf->bf_state.bfs_ndelim = 0; /* ??? needed? */ 4068 bf->bf_state.bfs_nframes = 1; 4069 4070 TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 4071 return 0; 4072 } 4073 4074 /* 4075 * error pkt completion for an aggregate destination 4076 */ 4077 static void 4078 ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first, 4079 struct ath_tid *tid) 4080 { 4081 struct ieee80211_node *ni = bf_first->bf_node; 4082 struct ath_node *an = ATH_NODE(ni); 4083 struct ath_buf *bf_next, *bf; 4084 ath_bufhead bf_q; 4085 int drops = 0; 4086 struct ieee80211_tx_ampdu *tap; 4087 ath_bufhead bf_cq; 4088 4089 TAILQ_INIT(&bf_q); 4090 TAILQ_INIT(&bf_cq); 4091 4092 /* 4093 * Update rate control - all frames have failed. 4094 * 4095 * XXX use the length in the first frame in the series; 4096 * XXX just so things are consistent for now. 4097 */ 4098 ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc, 4099 &bf_first->bf_status.ds_txstat, 4100 bf_first->bf_state.bfs_pktlen, 4101 bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes); 4102 4103 ATH_TX_LOCK(sc); 4104 tap = ath_tx_get_tx_tid(an, tid->tid); 4105 sc->sc_stats.ast_tx_aggr_failall++; 4106 4107 /* Retry all subframes */ 4108 bf = bf_first; 4109 while (bf) { 4110 bf_next = bf->bf_next; 4111 bf->bf_next = NULL; /* Remove it from the aggr list */ 4112 sc->sc_stats.ast_tx_aggr_fail++; 4113 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 4114 drops++; 4115 bf->bf_next = NULL; 4116 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 4117 } 4118 bf = bf_next; 4119 } 4120 4121 /* Prepend all frames to the beginning of the queue */ 4122 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 4123 TAILQ_REMOVE(&bf_q, bf, bf_list); 4124 ATH_TID_INSERT_HEAD(tid, bf, bf_list); 4125 } 4126 4127 /* 4128 * Schedule the TID to be re-tried. 4129 */ 4130 ath_tx_tid_sched(sc, tid); 4131 4132 /* 4133 * send bar if we dropped any frames 4134 * 4135 * Keep the txq lock held for now, as we need to ensure 4136 * that ni_txseqs[] is consistent (as it's being updated 4137 * in the ifnet TX context or raw TX context.) 4138 */ 4139 if (drops) { 4140 /* Suspend the TX queue and get ready to send the BAR */ 4141 ath_tx_tid_bar_suspend(sc, tid); 4142 } 4143 4144 /* 4145 * Send BAR if required 4146 */ 4147 if (ath_tx_tid_bar_tx_ready(sc, tid)) 4148 ath_tx_tid_bar_tx(sc, tid); 4149 4150 ATH_TX_UNLOCK(sc); 4151 4152 /* Complete frames which errored out */ 4153 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 4154 TAILQ_REMOVE(&bf_cq, bf, bf_list); 4155 ath_tx_default_comp(sc, bf, 0); 4156 } 4157 } 4158 4159 /* 4160 * Handle clean-up of packets from an aggregate list. 4161 * 4162 * There's no need to update the BAW here - the session is being 4163 * torn down. 4164 */ 4165 static void 4166 ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first) 4167 { 4168 struct ath_buf *bf, *bf_next; 4169 struct ieee80211_node *ni = bf_first->bf_node; 4170 struct ath_node *an = ATH_NODE(ni); 4171 int tid = bf_first->bf_state.bfs_tid; 4172 struct ath_tid *atid = &an->an_tid[tid]; 4173 4174 ATH_TX_LOCK(sc); 4175 4176 /* update incomp */ 4177 bf = bf_first; 4178 while (bf) { 4179 atid->incomp--; 4180 bf = bf->bf_next; 4181 } 4182 4183 if (atid->incomp == 0) { 4184 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4185 "%s: TID %d: cleaned up! resume!\n", 4186 __func__, tid); 4187 atid->cleanup_inprogress = 0; 4188 ath_tx_tid_resume(sc, atid); 4189 } 4190 4191 /* Send BAR if required */ 4192 /* XXX why would we send a BAR when transitioning to non-aggregation? */ 4193 /* 4194 * XXX TODO: we should likely just tear down the BAR state here, 4195 * rather than sending a BAR. 4196 */ 4197 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4198 ath_tx_tid_bar_tx(sc, atid); 4199 4200 ATH_TX_UNLOCK(sc); 4201 4202 /* Handle frame completion */ 4203 bf = bf_first; 4204 while (bf) { 4205 bf_next = bf->bf_next; 4206 ath_tx_default_comp(sc, bf, 1); 4207 bf = bf_next; 4208 } 4209 } 4210 4211 /* 4212 * Handle completion of an set of aggregate frames. 4213 * 4214 * Note: the completion handler is the last descriptor in the aggregate, 4215 * not the last descriptor in the first frame. 4216 */ 4217 static void 4218 ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first, 4219 int fail) 4220 { 4221 //struct ath_desc *ds = bf->bf_lastds; 4222 struct ieee80211_node *ni = bf_first->bf_node; 4223 struct ath_node *an = ATH_NODE(ni); 4224 int tid = bf_first->bf_state.bfs_tid; 4225 struct ath_tid *atid = &an->an_tid[tid]; 4226 struct ath_tx_status ts; 4227 struct ieee80211_tx_ampdu *tap; 4228 ath_bufhead bf_q; 4229 ath_bufhead bf_cq; 4230 int seq_st, tx_ok; 4231 int hasba, isaggr; 4232 uint32_t ba[2]; 4233 struct ath_buf *bf, *bf_next; 4234 int ba_index; 4235 int drops = 0; 4236 int nframes = 0, nbad = 0, nf; 4237 int pktlen; 4238 /* XXX there's too much on the stack? */ 4239 struct ath_rc_series rc[ATH_RC_NUM]; 4240 int txseq; 4241 4242 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n", 4243 __func__, atid->hwq_depth); 4244 4245 /* 4246 * Take a copy; this may be needed -after- bf_first 4247 * has been completed and freed. 4248 */ 4249 ts = bf_first->bf_status.ds_txstat; 4250 4251 TAILQ_INIT(&bf_q); 4252 TAILQ_INIT(&bf_cq); 4253 4254 /* The TID state is kept behind the TXQ lock */ 4255 ATH_TX_LOCK(sc); 4256 4257 atid->hwq_depth--; 4258 if (atid->hwq_depth < 0) 4259 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 4260 __func__, atid->hwq_depth); 4261 4262 /* 4263 * If the TID is filtered, handle completing the filter 4264 * transition before potentially kicking it to the cleanup 4265 * function. 4266 * 4267 * XXX this is duplicate work, ew. 4268 */ 4269 if (atid->isfiltered) 4270 ath_tx_tid_filt_comp_complete(sc, atid); 4271 4272 /* 4273 * Punt cleanup to the relevant function, not our problem now 4274 */ 4275 if (atid->cleanup_inprogress) { 4276 if (atid->isfiltered) 4277 device_printf(sc->sc_dev, 4278 "%s: isfiltered=1, normal_comp?\n", 4279 __func__); 4280 ATH_TX_UNLOCK(sc); 4281 ath_tx_comp_cleanup_aggr(sc, bf_first); 4282 return; 4283 } 4284 4285 /* 4286 * If the frame is filtered, transition to filtered frame 4287 * mode and add this to the filtered frame list. 4288 * 4289 * XXX TODO: figure out how this interoperates with 4290 * BAR, pause and cleanup states. 4291 */ 4292 if ((ts.ts_status & HAL_TXERR_FILT) || 4293 (ts.ts_status != 0 && atid->isfiltered)) { 4294 if (fail != 0) 4295 device_printf(sc->sc_dev, 4296 "%s: isfiltered=1, fail=%d\n", __func__, fail); 4297 ath_tx_tid_filt_comp_aggr(sc, atid, bf_first, &bf_cq); 4298 4299 /* Remove from BAW */ 4300 TAILQ_FOREACH_SAFE(bf, &bf_cq, bf_list, bf_next) { 4301 if (bf->bf_state.bfs_addedbaw) 4302 drops++; 4303 if (bf->bf_state.bfs_dobaw) { 4304 ath_tx_update_baw(sc, an, atid, bf); 4305 if (! bf->bf_state.bfs_addedbaw) 4306 device_printf(sc->sc_dev, 4307 "%s: wasn't added: seqno %d\n", 4308 __func__, 4309 SEQNO(bf->bf_state.bfs_seqno)); 4310 } 4311 bf->bf_state.bfs_dobaw = 0; 4312 } 4313 /* 4314 * If any intermediate frames in the BAW were dropped when 4315 * handling filtering things, send a BAR. 4316 */ 4317 if (drops) 4318 ath_tx_tid_bar_suspend(sc, atid); 4319 4320 /* 4321 * Finish up by sending a BAR if required and freeing 4322 * the frames outside of the TX lock. 4323 */ 4324 goto finish_send_bar; 4325 } 4326 4327 /* 4328 * XXX for now, use the first frame in the aggregate for 4329 * XXX rate control completion; it's at least consistent. 4330 */ 4331 pktlen = bf_first->bf_state.bfs_pktlen; 4332 4333 /* 4334 * Handle errors first! 4335 * 4336 * Here, handle _any_ error as a "exceeded retries" error. 4337 * Later on (when filtered frames are to be specially handled) 4338 * it'll have to be expanded. 4339 */ 4340 #if 0 4341 if (ts.ts_status & HAL_TXERR_XRETRY) { 4342 #endif 4343 if (ts.ts_status != 0) { 4344 ATH_TX_UNLOCK(sc); 4345 ath_tx_comp_aggr_error(sc, bf_first, atid); 4346 return; 4347 } 4348 4349 tap = ath_tx_get_tx_tid(an, tid); 4350 4351 /* 4352 * extract starting sequence and block-ack bitmap 4353 */ 4354 /* XXX endian-ness of seq_st, ba? */ 4355 seq_st = ts.ts_seqnum; 4356 hasba = !! (ts.ts_flags & HAL_TX_BA); 4357 tx_ok = (ts.ts_status == 0); 4358 isaggr = bf_first->bf_state.bfs_aggr; 4359 ba[0] = ts.ts_ba_low; 4360 ba[1] = ts.ts_ba_high; 4361 4362 /* 4363 * Copy the TX completion status and the rate control 4364 * series from the first descriptor, as it may be freed 4365 * before the rate control code can get its grubby fingers 4366 * into things. 4367 */ 4368 memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc)); 4369 4370 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4371 "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, " 4372 "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n", 4373 __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags, 4374 isaggr, seq_st, hasba, ba[0], ba[1]); 4375 4376 /* 4377 * The reference driver doesn't do this; it simply ignores 4378 * this check in its entirety. 4379 * 4380 * I've seen this occur when using iperf to send traffic 4381 * out tid 1 - the aggregate frames are all marked as TID 1, 4382 * but the TXSTATUS has TID=0. So, let's just ignore this 4383 * check. 4384 */ 4385 #if 0 4386 /* Occasionally, the MAC sends a tx status for the wrong TID. */ 4387 if (tid != ts.ts_tid) { 4388 device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n", 4389 __func__, tid, ts.ts_tid); 4390 tx_ok = 0; 4391 } 4392 #endif 4393 4394 /* AR5416 BA bug; this requires an interface reset */ 4395 if (isaggr && tx_ok && (! hasba)) { 4396 device_printf(sc->sc_dev, 4397 "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, " 4398 "seq_st=%d\n", 4399 __func__, hasba, tx_ok, isaggr, seq_st); 4400 /* XXX TODO: schedule an interface reset */ 4401 #ifdef ATH_DEBUG 4402 ath_printtxbuf(sc, bf_first, 4403 sc->sc_ac2q[atid->ac]->axq_qnum, 0, 0); 4404 #endif 4405 } 4406 4407 /* 4408 * Walk the list of frames, figure out which ones were correctly 4409 * sent and which weren't. 4410 */ 4411 bf = bf_first; 4412 nf = bf_first->bf_state.bfs_nframes; 4413 4414 /* bf_first is going to be invalid once this list is walked */ 4415 bf_first = NULL; 4416 4417 /* 4418 * Walk the list of completed frames and determine 4419 * which need to be completed and which need to be 4420 * retransmitted. 4421 * 4422 * For completed frames, the completion functions need 4423 * to be called at the end of this function as the last 4424 * node reference may free the node. 4425 * 4426 * Finally, since the TXQ lock can't be held during the 4427 * completion callback (to avoid lock recursion), 4428 * the completion calls have to be done outside of the 4429 * lock. 4430 */ 4431 while (bf) { 4432 nframes++; 4433 ba_index = ATH_BA_INDEX(seq_st, 4434 SEQNO(bf->bf_state.bfs_seqno)); 4435 bf_next = bf->bf_next; 4436 bf->bf_next = NULL; /* Remove it from the aggr list */ 4437 4438 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4439 "%s: checking bf=%p seqno=%d; ack=%d\n", 4440 __func__, bf, SEQNO(bf->bf_state.bfs_seqno), 4441 ATH_BA_ISSET(ba, ba_index)); 4442 4443 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) { 4444 sc->sc_stats.ast_tx_aggr_ok++; 4445 ath_tx_update_baw(sc, an, atid, bf); 4446 bf->bf_state.bfs_dobaw = 0; 4447 if (! bf->bf_state.bfs_addedbaw) 4448 device_printf(sc->sc_dev, 4449 "%s: wasn't added: seqno %d\n", 4450 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4451 bf->bf_next = NULL; 4452 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 4453 } else { 4454 sc->sc_stats.ast_tx_aggr_fail++; 4455 if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 4456 drops++; 4457 bf->bf_next = NULL; 4458 TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 4459 } 4460 nbad++; 4461 } 4462 bf = bf_next; 4463 } 4464 4465 /* 4466 * Now that the BAW updates have been done, unlock 4467 * 4468 * txseq is grabbed before the lock is released so we 4469 * have a consistent view of what -was- in the BAW. 4470 * Anything after this point will not yet have been 4471 * TXed. 4472 */ 4473 txseq = tap->txa_start; 4474 ATH_TX_UNLOCK(sc); 4475 4476 if (nframes != nf) 4477 device_printf(sc->sc_dev, 4478 "%s: num frames seen=%d; bf nframes=%d\n", 4479 __func__, nframes, nf); 4480 4481 /* 4482 * Now we know how many frames were bad, call the rate 4483 * control code. 4484 */ 4485 if (fail == 0) 4486 ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes, 4487 nbad); 4488 4489 /* 4490 * send bar if we dropped any frames 4491 */ 4492 if (drops) { 4493 /* Suspend the TX queue and get ready to send the BAR */ 4494 ATH_TX_LOCK(sc); 4495 ath_tx_tid_bar_suspend(sc, atid); 4496 ATH_TX_UNLOCK(sc); 4497 } 4498 4499 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4500 "%s: txa_start now %d\n", __func__, tap->txa_start); 4501 4502 ATH_TX_LOCK(sc); 4503 4504 /* Prepend all frames to the beginning of the queue */ 4505 while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 4506 TAILQ_REMOVE(&bf_q, bf, bf_list); 4507 ATH_TID_INSERT_HEAD(atid, bf, bf_list); 4508 } 4509 4510 /* 4511 * Reschedule to grab some further frames. 4512 */ 4513 ath_tx_tid_sched(sc, atid); 4514 4515 /* 4516 * If the queue is filtered, re-schedule as required. 4517 * 4518 * This is required as there may be a subsequent TX descriptor 4519 * for this end-node that has CLRDMASK set, so it's quite possible 4520 * that a filtered frame will be followed by a non-filtered 4521 * (complete or otherwise) frame. 4522 * 4523 * XXX should we do this before we complete the frame? 4524 */ 4525 if (atid->isfiltered) 4526 ath_tx_tid_filt_comp_complete(sc, atid); 4527 4528 finish_send_bar: 4529 4530 /* 4531 * Send BAR if required 4532 */ 4533 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4534 ath_tx_tid_bar_tx(sc, atid); 4535 4536 ATH_TX_UNLOCK(sc); 4537 4538 /* Do deferred completion */ 4539 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 4540 TAILQ_REMOVE(&bf_cq, bf, bf_list); 4541 ath_tx_default_comp(sc, bf, 0); 4542 } 4543 } 4544 4545 /* 4546 * Handle completion of unaggregated frames in an ADDBA 4547 * session. 4548 * 4549 * Fail is set to 1 if the entry is being freed via a call to 4550 * ath_tx_draintxq(). 4551 */ 4552 static void 4553 ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail) 4554 { 4555 struct ieee80211_node *ni = bf->bf_node; 4556 struct ath_node *an = ATH_NODE(ni); 4557 int tid = bf->bf_state.bfs_tid; 4558 struct ath_tid *atid = &an->an_tid[tid]; 4559 struct ath_tx_status ts; 4560 int drops = 0; 4561 4562 /* 4563 * Take a copy of this; filtering/cloning the frame may free the 4564 * bf pointer. 4565 */ 4566 ts = bf->bf_status.ds_txstat; 4567 4568 /* 4569 * Update rate control status here, before we possibly 4570 * punt to retry or cleanup. 4571 * 4572 * Do it outside of the TXQ lock. 4573 */ 4574 if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 4575 ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 4576 &bf->bf_status.ds_txstat, 4577 bf->bf_state.bfs_pktlen, 4578 1, (ts.ts_status == 0) ? 0 : 1); 4579 4580 /* 4581 * This is called early so atid->hwq_depth can be tracked. 4582 * This unfortunately means that it's released and regrabbed 4583 * during retry and cleanup. That's rather inefficient. 4584 */ 4585 ATH_TX_LOCK(sc); 4586 4587 if (tid == IEEE80211_NONQOS_TID) 4588 device_printf(sc->sc_dev, "%s: TID=16!\n", __func__); 4589 4590 DPRINTF(sc, ATH_DEBUG_SW_TX, 4591 "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n", 4592 __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth, 4593 SEQNO(bf->bf_state.bfs_seqno)); 4594 4595 atid->hwq_depth--; 4596 if (atid->hwq_depth < 0) 4597 device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 4598 __func__, atid->hwq_depth); 4599 4600 /* 4601 * If the TID is filtered, handle completing the filter 4602 * transition before potentially kicking it to the cleanup 4603 * function. 4604 */ 4605 if (atid->isfiltered) 4606 ath_tx_tid_filt_comp_complete(sc, atid); 4607 4608 /* 4609 * If a cleanup is in progress, punt to comp_cleanup; 4610 * rather than handling it here. It's thus their 4611 * responsibility to clean up, call the completion 4612 * function in net80211, etc. 4613 */ 4614 if (atid->cleanup_inprogress) { 4615 if (atid->isfiltered) 4616 device_printf(sc->sc_dev, 4617 "%s: isfiltered=1, normal_comp?\n", 4618 __func__); 4619 ATH_TX_UNLOCK(sc); 4620 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n", 4621 __func__); 4622 ath_tx_comp_cleanup_unaggr(sc, bf); 4623 return; 4624 } 4625 4626 /* 4627 * XXX TODO: how does cleanup, BAR and filtered frame handling 4628 * overlap? 4629 * 4630 * If the frame is filtered OR if it's any failure but 4631 * the TID is filtered, the frame must be added to the 4632 * filtered frame list. 4633 * 4634 * However - a busy buffer can't be added to the filtered 4635 * list as it will end up being recycled without having 4636 * been made available for the hardware. 4637 */ 4638 if ((ts.ts_status & HAL_TXERR_FILT) || 4639 (ts.ts_status != 0 && atid->isfiltered)) { 4640 int freeframe; 4641 4642 if (fail != 0) 4643 device_printf(sc->sc_dev, 4644 "%s: isfiltered=1, fail=%d\n", 4645 __func__, 4646 fail); 4647 freeframe = ath_tx_tid_filt_comp_single(sc, atid, bf); 4648 if (freeframe) { 4649 /* Remove from BAW */ 4650 if (bf->bf_state.bfs_addedbaw) 4651 drops++; 4652 if (bf->bf_state.bfs_dobaw) { 4653 ath_tx_update_baw(sc, an, atid, bf); 4654 if (! bf->bf_state.bfs_addedbaw) 4655 device_printf(sc->sc_dev, 4656 "%s: wasn't added: seqno %d\n", 4657 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4658 } 4659 bf->bf_state.bfs_dobaw = 0; 4660 } 4661 4662 /* 4663 * If the frame couldn't be filtered, treat it as a drop and 4664 * prepare to send a BAR. 4665 */ 4666 if (freeframe && drops) 4667 ath_tx_tid_bar_suspend(sc, atid); 4668 4669 /* 4670 * Send BAR if required 4671 */ 4672 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4673 ath_tx_tid_bar_tx(sc, atid); 4674 4675 ATH_TX_UNLOCK(sc); 4676 /* 4677 * If freeframe is set, then the frame couldn't be 4678 * cloned and bf is still valid. Just complete/free it. 4679 */ 4680 if (freeframe) 4681 ath_tx_default_comp(sc, bf, fail); 4682 4683 4684 return; 4685 } 4686 /* 4687 * Don't bother with the retry check if all frames 4688 * are being failed (eg during queue deletion.) 4689 */ 4690 #if 0 4691 if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) { 4692 #endif 4693 if (fail == 0 && ts.ts_status != 0) { 4694 ATH_TX_UNLOCK(sc); 4695 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n", 4696 __func__); 4697 ath_tx_aggr_retry_unaggr(sc, bf); 4698 return; 4699 } 4700 4701 /* Success? Complete */ 4702 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n", 4703 __func__, tid, SEQNO(bf->bf_state.bfs_seqno)); 4704 if (bf->bf_state.bfs_dobaw) { 4705 ath_tx_update_baw(sc, an, atid, bf); 4706 bf->bf_state.bfs_dobaw = 0; 4707 if (! bf->bf_state.bfs_addedbaw) 4708 device_printf(sc->sc_dev, 4709 "%s: wasn't added: seqno %d\n", 4710 __func__, SEQNO(bf->bf_state.bfs_seqno)); 4711 } 4712 4713 /* 4714 * If the queue is filtered, re-schedule as required. 4715 * 4716 * This is required as there may be a subsequent TX descriptor 4717 * for this end-node that has CLRDMASK set, so it's quite possible 4718 * that a filtered frame will be followed by a non-filtered 4719 * (complete or otherwise) frame. 4720 * 4721 * XXX should we do this before we complete the frame? 4722 */ 4723 if (atid->isfiltered) 4724 ath_tx_tid_filt_comp_complete(sc, atid); 4725 4726 /* 4727 * Send BAR if required 4728 */ 4729 if (ath_tx_tid_bar_tx_ready(sc, atid)) 4730 ath_tx_tid_bar_tx(sc, atid); 4731 4732 ATH_TX_UNLOCK(sc); 4733 4734 ath_tx_default_comp(sc, bf, fail); 4735 /* bf is freed at this point */ 4736 } 4737 4738 void 4739 ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 4740 { 4741 if (bf->bf_state.bfs_aggr) 4742 ath_tx_aggr_comp_aggr(sc, bf, fail); 4743 else 4744 ath_tx_aggr_comp_unaggr(sc, bf, fail); 4745 } 4746 4747 /* 4748 * Schedule some packets from the given node/TID to the hardware. 4749 * 4750 * This is the aggregate version. 4751 */ 4752 void 4753 ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an, 4754 struct ath_tid *tid) 4755 { 4756 struct ath_buf *bf; 4757 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 4758 struct ieee80211_tx_ampdu *tap; 4759 ATH_AGGR_STATUS status; 4760 ath_bufhead bf_q; 4761 4762 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid); 4763 ATH_TX_LOCK_ASSERT(sc); 4764 4765 tap = ath_tx_get_tx_tid(an, tid->tid); 4766 4767 if (tid->tid == IEEE80211_NONQOS_TID) 4768 device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n", 4769 __func__); 4770 4771 for (;;) { 4772 status = ATH_AGGR_DONE; 4773 4774 /* 4775 * If the upper layer has paused the TID, don't 4776 * queue any further packets. 4777 * 4778 * This can also occur from the completion task because 4779 * of packet loss; but as its serialised with this code, 4780 * it won't "appear" half way through queuing packets. 4781 */ 4782 if (tid->paused) 4783 break; 4784 4785 bf = ATH_TID_FIRST(tid); 4786 if (bf == NULL) { 4787 break; 4788 } 4789 4790 /* 4791 * If the packet doesn't fall within the BAW (eg a NULL 4792 * data frame), schedule it directly; continue. 4793 */ 4794 if (! bf->bf_state.bfs_dobaw) { 4795 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4796 "%s: non-baw packet\n", 4797 __func__); 4798 ATH_TID_REMOVE(tid, bf, bf_list); 4799 4800 if (bf->bf_state.bfs_nframes > 1) 4801 device_printf(sc->sc_dev, 4802 "%s: aggr=%d, nframes=%d\n", 4803 __func__, 4804 bf->bf_state.bfs_aggr, 4805 bf->bf_state.bfs_nframes); 4806 4807 /* 4808 * This shouldn't happen - such frames shouldn't 4809 * ever have been queued as an aggregate in the 4810 * first place. However, make sure the fields 4811 * are correctly setup just to be totally sure. 4812 */ 4813 bf->bf_state.bfs_aggr = 0; 4814 bf->bf_state.bfs_nframes = 1; 4815 4816 /* Update CLRDMASK just before this frame is queued */ 4817 ath_tx_update_clrdmask(sc, tid, bf); 4818 4819 ath_tx_do_ratelookup(sc, bf); 4820 ath_tx_calc_duration(sc, bf); 4821 ath_tx_calc_protection(sc, bf); 4822 ath_tx_set_rtscts(sc, bf); 4823 ath_tx_rate_fill_rcflags(sc, bf); 4824 ath_tx_setds(sc, bf); 4825 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4826 4827 sc->sc_aggr_stats.aggr_nonbaw_pkt++; 4828 4829 /* Queue the packet; continue */ 4830 goto queuepkt; 4831 } 4832 4833 TAILQ_INIT(&bf_q); 4834 4835 /* 4836 * Do a rate control lookup on the first frame in the 4837 * list. The rate control code needs that to occur 4838 * before it can determine whether to TX. 4839 * It's inaccurate because the rate control code doesn't 4840 * really "do" aggregate lookups, so it only considers 4841 * the size of the first frame. 4842 */ 4843 ath_tx_do_ratelookup(sc, bf); 4844 bf->bf_state.bfs_rc[3].rix = 0; 4845 bf->bf_state.bfs_rc[3].tries = 0; 4846 4847 ath_tx_calc_duration(sc, bf); 4848 ath_tx_calc_protection(sc, bf); 4849 4850 ath_tx_set_rtscts(sc, bf); 4851 ath_tx_rate_fill_rcflags(sc, bf); 4852 4853 status = ath_tx_form_aggr(sc, an, tid, &bf_q); 4854 4855 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4856 "%s: ath_tx_form_aggr() status=%d\n", __func__, status); 4857 4858 /* 4859 * No frames to be picked up - out of BAW 4860 */ 4861 if (TAILQ_EMPTY(&bf_q)) 4862 break; 4863 4864 /* 4865 * This assumes that the descriptor list in the ath_bufhead 4866 * are already linked together via bf_next pointers. 4867 */ 4868 bf = TAILQ_FIRST(&bf_q); 4869 4870 if (status == ATH_AGGR_8K_LIMITED) 4871 sc->sc_aggr_stats.aggr_rts_aggr_limited++; 4872 4873 /* 4874 * If it's the only frame send as non-aggregate 4875 * assume that ath_tx_form_aggr() has checked 4876 * whether it's in the BAW and added it appropriately. 4877 */ 4878 if (bf->bf_state.bfs_nframes == 1) { 4879 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4880 "%s: single-frame aggregate\n", __func__); 4881 4882 /* Update CLRDMASK just before this frame is queued */ 4883 ath_tx_update_clrdmask(sc, tid, bf); 4884 4885 bf->bf_state.bfs_aggr = 0; 4886 bf->bf_state.bfs_ndelim = 0; 4887 ath_tx_setds(sc, bf); 4888 ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4889 if (status == ATH_AGGR_BAW_CLOSED) 4890 sc->sc_aggr_stats.aggr_baw_closed_single_pkt++; 4891 else 4892 sc->sc_aggr_stats.aggr_single_pkt++; 4893 } else { 4894 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4895 "%s: multi-frame aggregate: %d frames, " 4896 "length %d\n", 4897 __func__, bf->bf_state.bfs_nframes, 4898 bf->bf_state.bfs_al); 4899 bf->bf_state.bfs_aggr = 1; 4900 sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++; 4901 sc->sc_aggr_stats.aggr_aggr_pkt++; 4902 4903 /* Update CLRDMASK just before this frame is queued */ 4904 ath_tx_update_clrdmask(sc, tid, bf); 4905 4906 /* 4907 * Calculate the duration/protection as required. 4908 */ 4909 ath_tx_calc_duration(sc, bf); 4910 ath_tx_calc_protection(sc, bf); 4911 4912 /* 4913 * Update the rate and rtscts information based on the 4914 * rate decision made by the rate control code; 4915 * the first frame in the aggregate needs it. 4916 */ 4917 ath_tx_set_rtscts(sc, bf); 4918 4919 /* 4920 * Setup the relevant descriptor fields 4921 * for aggregation. The first descriptor 4922 * already points to the rest in the chain. 4923 */ 4924 ath_tx_setds_11n(sc, bf); 4925 4926 } 4927 queuepkt: 4928 /* Set completion handler, multi-frame aggregate or not */ 4929 bf->bf_comp = ath_tx_aggr_comp; 4930 4931 if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID) 4932 device_printf(sc->sc_dev, "%s: TID=16?\n", __func__); 4933 4934 /* Punt to txq */ 4935 ath_tx_handoff(sc, txq, bf); 4936 4937 /* Track outstanding buffer count to hardware */ 4938 /* aggregates are "one" buffer */ 4939 tid->hwq_depth++; 4940 4941 /* 4942 * Break out if ath_tx_form_aggr() indicated 4943 * there can't be any further progress (eg BAW is full.) 4944 * Checking for an empty txq is done above. 4945 * 4946 * XXX locking on txq here? 4947 */ 4948 if (txq->axq_aggr_depth >= sc->sc_hwq_limit || 4949 status == ATH_AGGR_BAW_CLOSED) 4950 break; 4951 } 4952 } 4953 4954 /* 4955 * Schedule some packets from the given node/TID to the hardware. 4956 */ 4957 void 4958 ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an, 4959 struct ath_tid *tid) 4960 { 4961 struct ath_buf *bf; 4962 struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 4963 4964 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n", 4965 __func__, an, tid->tid); 4966 4967 ATH_TX_LOCK_ASSERT(sc); 4968 4969 /* Check - is AMPDU pending or running? then print out something */ 4970 if (ath_tx_ampdu_pending(sc, an, tid->tid)) 4971 device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n", 4972 __func__, tid->tid); 4973 if (ath_tx_ampdu_running(sc, an, tid->tid)) 4974 device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n", 4975 __func__, tid->tid); 4976 4977 for (;;) { 4978 4979 /* 4980 * If the upper layers have paused the TID, don't 4981 * queue any further packets. 4982 */ 4983 if (tid->paused) 4984 break; 4985 4986 bf = ATH_TID_FIRST(tid); 4987 if (bf == NULL) { 4988 break; 4989 } 4990 4991 ATH_TID_REMOVE(tid, bf, bf_list); 4992 4993 /* Sanity check! */ 4994 if (tid->tid != bf->bf_state.bfs_tid) { 4995 device_printf(sc->sc_dev, "%s: bfs_tid %d !=" 4996 " tid %d\n", 4997 __func__, bf->bf_state.bfs_tid, tid->tid); 4998 } 4999 /* Normal completion handler */ 5000 bf->bf_comp = ath_tx_normal_comp; 5001 5002 /* 5003 * Override this for now, until the non-aggregate 5004 * completion handler correctly handles software retransmits. 5005 */ 5006 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK; 5007 5008 /* Update CLRDMASK just before this frame is queued */ 5009 ath_tx_update_clrdmask(sc, tid, bf); 5010 5011 /* Program descriptors + rate control */ 5012 ath_tx_do_ratelookup(sc, bf); 5013 ath_tx_calc_duration(sc, bf); 5014 ath_tx_calc_protection(sc, bf); 5015 ath_tx_set_rtscts(sc, bf); 5016 ath_tx_rate_fill_rcflags(sc, bf); 5017 ath_tx_setds(sc, bf); 5018 5019 /* Track outstanding buffer count to hardware */ 5020 /* aggregates are "one" buffer */ 5021 tid->hwq_depth++; 5022 5023 /* Punt to hardware or software txq */ 5024 ath_tx_handoff(sc, txq, bf); 5025 } 5026 } 5027 5028 /* 5029 * Schedule some packets to the given hardware queue. 5030 * 5031 * This function walks the list of TIDs (ie, ath_node TIDs 5032 * with queued traffic) and attempts to schedule traffic 5033 * from them. 5034 * 5035 * TID scheduling is implemented as a FIFO, with TIDs being 5036 * added to the end of the queue after some frames have been 5037 * scheduled. 5038 */ 5039 void 5040 ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq) 5041 { 5042 struct ath_tid *tid, *next, *last; 5043 5044 ATH_TX_LOCK_ASSERT(sc); 5045 5046 /* 5047 * Don't schedule if the hardware queue is busy. 5048 * This (hopefully) gives some more time to aggregate 5049 * some packets in the aggregation queue. 5050 */ 5051 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 5052 sc->sc_aggr_stats.aggr_sched_nopkt++; 5053 return; 5054 } 5055 5056 last = TAILQ_LAST(&txq->axq_tidq, axq_t_s); 5057 5058 TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) { 5059 /* 5060 * Suspend paused queues here; they'll be resumed 5061 * once the addba completes or times out. 5062 */ 5063 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n", 5064 __func__, tid->tid, tid->paused); 5065 ath_tx_tid_unsched(sc, tid); 5066 if (tid->paused) { 5067 continue; 5068 } 5069 if (ath_tx_ampdu_running(sc, tid->an, tid->tid)) 5070 ath_tx_tid_hw_queue_aggr(sc, tid->an, tid); 5071 else 5072 ath_tx_tid_hw_queue_norm(sc, tid->an, tid); 5073 5074 /* Not empty? Re-schedule */ 5075 if (tid->axq_depth != 0) 5076 ath_tx_tid_sched(sc, tid); 5077 5078 /* Give the software queue time to aggregate more packets */ 5079 if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 5080 break; 5081 } 5082 5083 /* 5084 * If this was the last entry on the original list, stop. 5085 * Otherwise nodes that have been rescheduled onto the end 5086 * of the TID FIFO list will just keep being rescheduled. 5087 */ 5088 if (tid == last) 5089 break; 5090 } 5091 } 5092 5093 /* 5094 * TX addba handling 5095 */ 5096 5097 /* 5098 * Return net80211 TID struct pointer, or NULL for none 5099 */ 5100 struct ieee80211_tx_ampdu * 5101 ath_tx_get_tx_tid(struct ath_node *an, int tid) 5102 { 5103 struct ieee80211_node *ni = &an->an_node; 5104 struct ieee80211_tx_ampdu *tap; 5105 5106 if (tid == IEEE80211_NONQOS_TID) 5107 return NULL; 5108 5109 tap = &ni->ni_tx_ampdu[tid]; 5110 return tap; 5111 } 5112 5113 /* 5114 * Is AMPDU-TX running? 5115 */ 5116 static int 5117 ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid) 5118 { 5119 struct ieee80211_tx_ampdu *tap; 5120 5121 if (tid == IEEE80211_NONQOS_TID) 5122 return 0; 5123 5124 tap = ath_tx_get_tx_tid(an, tid); 5125 if (tap == NULL) 5126 return 0; /* Not valid; default to not running */ 5127 5128 return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING); 5129 } 5130 5131 /* 5132 * Is AMPDU-TX negotiation pending? 5133 */ 5134 static int 5135 ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid) 5136 { 5137 struct ieee80211_tx_ampdu *tap; 5138 5139 if (tid == IEEE80211_NONQOS_TID) 5140 return 0; 5141 5142 tap = ath_tx_get_tx_tid(an, tid); 5143 if (tap == NULL) 5144 return 0; /* Not valid; default to not pending */ 5145 5146 return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND); 5147 } 5148 5149 /* 5150 * Is AMPDU-TX pending for the given TID? 5151 */ 5152 5153 5154 /* 5155 * Method to handle sending an ADDBA request. 5156 * 5157 * We tap this so the relevant flags can be set to pause the TID 5158 * whilst waiting for the response. 5159 * 5160 * XXX there's no timeout handler we can override? 5161 */ 5162 int 5163 ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5164 int dialogtoken, int baparamset, int batimeout) 5165 { 5166 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5167 int tid = tap->txa_tid; 5168 struct ath_node *an = ATH_NODE(ni); 5169 struct ath_tid *atid = &an->an_tid[tid]; 5170 5171 /* 5172 * XXX danger Will Robinson! 5173 * 5174 * Although the taskqueue may be running and scheduling some more 5175 * packets, these should all be _before_ the addba sequence number. 5176 * However, net80211 will keep self-assigning sequence numbers 5177 * until addba has been negotiated. 5178 * 5179 * In the past, these packets would be "paused" (which still works 5180 * fine, as they're being scheduled to the driver in the same 5181 * serialised method which is calling the addba request routine) 5182 * and when the aggregation session begins, they'll be dequeued 5183 * as aggregate packets and added to the BAW. However, now there's 5184 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these 5185 * packets. Thus they never get included in the BAW tracking and 5186 * this can cause the initial burst of packets after the addba 5187 * negotiation to "hang", as they quickly fall outside the BAW. 5188 * 5189 * The "eventual" solution should be to tag these packets with 5190 * dobaw. Although net80211 has given us a sequence number, 5191 * it'll be "after" the left edge of the BAW and thus it'll 5192 * fall within it. 5193 */ 5194 ATH_TX_LOCK(sc); 5195 /* 5196 * This is a bit annoying. Until net80211 HT code inherits some 5197 * (any) locking, we may have this called in parallel BUT only 5198 * one response/timeout will be called. Grr. 5199 */ 5200 if (atid->addba_tx_pending == 0) { 5201 ath_tx_tid_pause(sc, atid); 5202 atid->addba_tx_pending = 1; 5203 } 5204 ATH_TX_UNLOCK(sc); 5205 5206 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5207 "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n", 5208 __func__, dialogtoken, baparamset, batimeout); 5209 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5210 "%s: txa_start=%d, ni_txseqs=%d\n", 5211 __func__, tap->txa_start, ni->ni_txseqs[tid]); 5212 5213 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 5214 batimeout); 5215 } 5216 5217 /* 5218 * Handle an ADDBA response. 5219 * 5220 * We unpause the queue so TX'ing can resume. 5221 * 5222 * Any packets TX'ed from this point should be "aggregate" (whether 5223 * aggregate or not) so the BAW is updated. 5224 * 5225 * Note! net80211 keeps self-assigning sequence numbers until 5226 * ampdu is negotiated. This means the initially-negotiated BAW left 5227 * edge won't match the ni->ni_txseq. 5228 * 5229 * So, being very dirty, the BAW left edge is "slid" here to match 5230 * ni->ni_txseq. 5231 * 5232 * What likely SHOULD happen is that all packets subsequent to the 5233 * addba request should be tagged as aggregate and queued as non-aggregate 5234 * frames; thus updating the BAW. For now though, I'll just slide the 5235 * window. 5236 */ 5237 int 5238 ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5239 int status, int code, int batimeout) 5240 { 5241 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5242 int tid = tap->txa_tid; 5243 struct ath_node *an = ATH_NODE(ni); 5244 struct ath_tid *atid = &an->an_tid[tid]; 5245 int r; 5246 5247 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5248 "%s: called; status=%d, code=%d, batimeout=%d\n", __func__, 5249 status, code, batimeout); 5250 5251 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5252 "%s: txa_start=%d, ni_txseqs=%d\n", 5253 __func__, tap->txa_start, ni->ni_txseqs[tid]); 5254 5255 /* 5256 * Call this first, so the interface flags get updated 5257 * before the TID is unpaused. Otherwise a race condition 5258 * exists where the unpaused TID still doesn't yet have 5259 * IEEE80211_AGGR_RUNNING set. 5260 */ 5261 r = sc->sc_addba_response(ni, tap, status, code, batimeout); 5262 5263 ATH_TX_LOCK(sc); 5264 atid->addba_tx_pending = 0; 5265 /* 5266 * XXX dirty! 5267 * Slide the BAW left edge to wherever net80211 left it for us. 5268 * Read above for more information. 5269 */ 5270 tap->txa_start = ni->ni_txseqs[tid]; 5271 ath_tx_tid_resume(sc, atid); 5272 ATH_TX_UNLOCK(sc); 5273 return r; 5274 } 5275 5276 5277 /* 5278 * Stop ADDBA on a queue. 5279 * 5280 * This can be called whilst BAR TX is currently active on the queue, 5281 * so make sure this is unblocked before continuing. 5282 */ 5283 void 5284 ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 5285 { 5286 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5287 int tid = tap->txa_tid; 5288 struct ath_node *an = ATH_NODE(ni); 5289 struct ath_tid *atid = &an->an_tid[tid]; 5290 5291 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__); 5292 5293 /* 5294 * Pause TID traffic early, so there aren't any races 5295 * Unblock the pending BAR held traffic, if it's currently paused. 5296 */ 5297 ATH_TX_LOCK(sc); 5298 ath_tx_tid_pause(sc, atid); 5299 if (atid->bar_wait) { 5300 /* 5301 * bar_unsuspend() expects bar_tx == 1, as it should be 5302 * called from the TX completion path. This quietens 5303 * the warning. It's cleared for us anyway. 5304 */ 5305 atid->bar_tx = 1; 5306 ath_tx_tid_bar_unsuspend(sc, atid); 5307 } 5308 ATH_TX_UNLOCK(sc); 5309 5310 /* There's no need to hold the TXQ lock here */ 5311 sc->sc_addba_stop(ni, tap); 5312 5313 /* 5314 * ath_tx_tid_cleanup will resume the TID if possible, otherwise 5315 * it'll set the cleanup flag, and it'll be unpaused once 5316 * things have been cleaned up. 5317 */ 5318 ath_tx_tid_cleanup(sc, an, tid); 5319 } 5320 5321 /* 5322 * Note: net80211 bar_timeout() doesn't call this function on BAR failure; 5323 * it simply tears down the aggregation session. Ew. 5324 * 5325 * It however will call ieee80211_ampdu_stop() which will call 5326 * ic->ic_addba_stop(). 5327 * 5328 * XXX This uses a hard-coded max BAR count value; the whole 5329 * XXX BAR TX success or failure should be better handled! 5330 */ 5331 void 5332 ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 5333 int status) 5334 { 5335 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5336 int tid = tap->txa_tid; 5337 struct ath_node *an = ATH_NODE(ni); 5338 struct ath_tid *atid = &an->an_tid[tid]; 5339 int attempts = tap->txa_attempts; 5340 5341 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 5342 "%s: called; tap=%p, atid=%p, txa_tid=%d, atid->tid=%d, status=%d, attempts=%d\n", 5343 __func__, 5344 tap, 5345 atid, 5346 tap->txa_tid, 5347 atid->tid, 5348 status, 5349 attempts); 5350 5351 /* Note: This may update the BAW details */ 5352 sc->sc_bar_response(ni, tap, status); 5353 5354 /* Unpause the TID */ 5355 /* 5356 * XXX if this is attempt=50, the TID will be downgraded 5357 * XXX to a non-aggregate session. So we must unpause the 5358 * XXX TID here or it'll never be done. 5359 * 5360 * Also, don't call it if bar_tx/bar_wait are 0; something 5361 * has beaten us to the punch? (XXX figure out what?) 5362 */ 5363 if (status == 0 || attempts == 50) { 5364 ATH_TX_LOCK(sc); 5365 if (atid->bar_tx == 0 || atid->bar_wait == 0) 5366 device_printf(sc->sc_dev, 5367 "%s: huh? bar_tx=%d, bar_wait=%d\n", 5368 __func__, 5369 atid->bar_tx, atid->bar_wait); 5370 else 5371 ath_tx_tid_bar_unsuspend(sc, atid); 5372 ATH_TX_UNLOCK(sc); 5373 } 5374 } 5375 5376 /* 5377 * This is called whenever the pending ADDBA request times out. 5378 * Unpause and reschedule the TID. 5379 */ 5380 void 5381 ath_addba_response_timeout(struct ieee80211_node *ni, 5382 struct ieee80211_tx_ampdu *tap) 5383 { 5384 struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 5385 int tid = tap->txa_tid; 5386 struct ath_node *an = ATH_NODE(ni); 5387 struct ath_tid *atid = &an->an_tid[tid]; 5388 5389 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 5390 "%s: called; resuming\n", __func__); 5391 5392 ATH_TX_LOCK(sc); 5393 atid->addba_tx_pending = 0; 5394 ATH_TX_UNLOCK(sc); 5395 5396 /* Note: This updates the aggregate state to (again) pending */ 5397 sc->sc_addba_response_timeout(ni, tap); 5398 5399 /* Unpause the TID; which reschedules it */ 5400 ATH_TX_LOCK(sc); 5401 ath_tx_tid_resume(sc, atid); 5402 ATH_TX_UNLOCK(sc); 5403 } 5404 5405 /* 5406 * Check if a node is asleep or not. 5407 */ 5408 int 5409 ath_tx_node_is_asleep(struct ath_softc *sc, struct ath_node *an) 5410 { 5411 5412 ATH_NODE_LOCK_ASSERT(an); 5413 5414 return (an->an_is_powersave); 5415 } 5416 5417 /* 5418 * Mark a node as currently "in powersaving." 5419 * This suspends all traffic on the node. 5420 * 5421 * This must be called with the node/tx locks free. 5422 * 5423 * XXX TODO: the locking silliness below is due to how the node 5424 * locking currently works. Right now, the node lock is grabbed 5425 * to do rate control lookups and these are done with the TX 5426 * queue lock held. This means the node lock can't be grabbed 5427 * first here or a LOR will occur. 5428 * 5429 * Eventually (hopefully!) the TX path code will only grab 5430 * the TXQ lock when transmitting and the ath_node lock when 5431 * doing node/TID operations. There are other complications - 5432 * the sched/unsched operations involve walking the per-txq 5433 * 'active tid' list and this requires both locks to be held. 5434 */ 5435 void 5436 ath_tx_node_sleep(struct ath_softc *sc, struct ath_node *an) 5437 { 5438 struct ath_tid *atid; 5439 struct ath_txq *txq; 5440 int tid; 5441 5442 ATH_NODE_UNLOCK_ASSERT(an); 5443 5444 /* 5445 * It's possible that a parallel call to ath_tx_node_wakeup() 5446 * will unpause these queues. 5447 * 5448 * The node lock can't just be grabbed here, as there's places 5449 * in the driver where the node lock is grabbed _within_ a 5450 * TXQ lock. 5451 * So, we do this delicately and unwind state if needed. 5452 * 5453 * + Pause all the queues 5454 * + Grab the node lock 5455 * + If the queue is already asleep, unpause and quit 5456 * + else just mark as asleep. 5457 * 5458 * A parallel sleep() call will just pause and then 5459 * find they're already paused, so undo it. 5460 * 5461 * A parallel wakeup() call will check if asleep is 1 5462 * and if it's not (ie, it's 0), it'll treat it as already 5463 * being awake. If it's 1, it'll mark it as 0 and then 5464 * unpause everything. 5465 * 5466 * (Talk about a delicate hack.) 5467 */ 5468 5469 /* Suspend all traffic on the node */ 5470 ATH_TX_LOCK(sc); 5471 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 5472 atid = &an->an_tid[tid]; 5473 txq = sc->sc_ac2q[atid->ac]; 5474 5475 ath_tx_tid_pause(sc, atid); 5476 } 5477 ATH_TX_UNLOCK(sc); 5478 5479 ATH_NODE_LOCK(an); 5480 5481 /* In case of concurrency races from net80211.. */ 5482 if (an->an_is_powersave == 1) { 5483 ATH_NODE_UNLOCK(an); 5484 device_printf(sc->sc_dev, 5485 "%s: an=%p: node was already asleep\n", 5486 __func__, an); 5487 ATH_TX_LOCK(sc); 5488 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 5489 atid = &an->an_tid[tid]; 5490 txq = sc->sc_ac2q[atid->ac]; 5491 5492 ath_tx_tid_resume(sc, atid); 5493 } 5494 ATH_TX_UNLOCK(sc); 5495 return; 5496 } 5497 5498 /* Mark node as in powersaving */ 5499 an->an_is_powersave = 1; 5500 5501 ATH_NODE_UNLOCK(an); 5502 } 5503 5504 /* 5505 * Mark a node as currently "awake." 5506 * This resumes all traffic to the node. 5507 */ 5508 void 5509 ath_tx_node_wakeup(struct ath_softc *sc, struct ath_node *an) 5510 { 5511 struct ath_tid *atid; 5512 struct ath_txq *txq; 5513 int tid; 5514 5515 ATH_NODE_UNLOCK_ASSERT(an); 5516 ATH_NODE_LOCK(an); 5517 5518 /* In case of concurrency races from net80211.. */ 5519 if (an->an_is_powersave == 0) { 5520 ATH_NODE_UNLOCK(an); 5521 device_printf(sc->sc_dev, 5522 "%s: an=%p: node was already awake\n", 5523 __func__, an); 5524 return; 5525 } 5526 5527 /* Mark node as awake */ 5528 an->an_is_powersave = 0; 5529 5530 ATH_NODE_UNLOCK(an); 5531 5532 ATH_TX_LOCK(sc); 5533 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 5534 atid = &an->an_tid[tid]; 5535 txq = sc->sc_ac2q[atid->ac]; 5536 5537 ath_tx_tid_resume(sc, atid); 5538 } 5539 ATH_TX_UNLOCK(sc); 5540 } 5541 5542 static int 5543 ath_legacy_dma_txsetup(struct ath_softc *sc) 5544 { 5545 5546 /* nothing new needed */ 5547 return (0); 5548 } 5549 5550 static int 5551 ath_legacy_dma_txteardown(struct ath_softc *sc) 5552 { 5553 5554 /* nothing new needed */ 5555 return (0); 5556 } 5557 5558 void 5559 ath_xmit_setup_legacy(struct ath_softc *sc) 5560 { 5561 /* 5562 * For now, just set the descriptor length to sizeof(ath_desc); 5563 * worry about extracting the real length out of the HAL later. 5564 */ 5565 sc->sc_tx_desclen = sizeof(struct ath_desc); 5566 sc->sc_tx_statuslen = sizeof(struct ath_desc); 5567 sc->sc_tx_nmaps = 1; /* only one buffer per TX desc */ 5568 5569 sc->sc_tx.xmit_setup = ath_legacy_dma_txsetup; 5570 sc->sc_tx.xmit_teardown = ath_legacy_dma_txteardown; 5571 sc->sc_tx.xmit_attach_comp_func = ath_legacy_attach_comp_func; 5572 5573 sc->sc_tx.xmit_dma_restart = ath_legacy_tx_dma_restart; 5574 sc->sc_tx.xmit_handoff = ath_legacy_xmit_handoff; 5575 5576 sc->sc_tx.xmit_drain = ath_legacy_tx_drain; 5577 } 5578