1b8e788a5SAdrian Chadd /*- 2b8e788a5SAdrian Chadd * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3b8e788a5SAdrian Chadd * All rights reserved. 4b8e788a5SAdrian Chadd * 5b8e788a5SAdrian Chadd * Redistribution and use in source and binary forms, with or without 6b8e788a5SAdrian Chadd * modification, are permitted provided that the following conditions 7b8e788a5SAdrian Chadd * are met: 8b8e788a5SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 9b8e788a5SAdrian Chadd * notice, this list of conditions and the following disclaimer, 10b8e788a5SAdrian Chadd * without modification. 11b8e788a5SAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12b8e788a5SAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13b8e788a5SAdrian Chadd * redistribution must be conditioned upon including a substantially 14b8e788a5SAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 15b8e788a5SAdrian Chadd * 16b8e788a5SAdrian Chadd * NO WARRANTY 17b8e788a5SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18b8e788a5SAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19b8e788a5SAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20b8e788a5SAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21b8e788a5SAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22b8e788a5SAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23b8e788a5SAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24b8e788a5SAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25b8e788a5SAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26b8e788a5SAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27b8e788a5SAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 28b8e788a5SAdrian Chadd */ 29b8e788a5SAdrian Chadd 30b8e788a5SAdrian Chadd #include <sys/cdefs.h> 31b8e788a5SAdrian Chadd __FBSDID("$FreeBSD$"); 32b8e788a5SAdrian Chadd 33b8e788a5SAdrian Chadd /* 34b8e788a5SAdrian Chadd * Driver for the Atheros Wireless LAN controller. 35b8e788a5SAdrian Chadd * 36b8e788a5SAdrian Chadd * This software is derived from work of Atsushi Onoe; his contribution 37b8e788a5SAdrian Chadd * is greatly appreciated. 38b8e788a5SAdrian Chadd */ 39b8e788a5SAdrian Chadd 40b8e788a5SAdrian Chadd #include "opt_inet.h" 41b8e788a5SAdrian Chadd #include "opt_ath.h" 42b8e788a5SAdrian Chadd #include "opt_wlan.h" 43b8e788a5SAdrian Chadd 44b8e788a5SAdrian Chadd #include <sys/param.h> 45b8e788a5SAdrian Chadd #include <sys/systm.h> 46b8e788a5SAdrian Chadd #include <sys/sysctl.h> 47b8e788a5SAdrian Chadd #include <sys/mbuf.h> 48b8e788a5SAdrian Chadd #include <sys/malloc.h> 49b8e788a5SAdrian Chadd #include <sys/lock.h> 50b8e788a5SAdrian Chadd #include <sys/mutex.h> 51b8e788a5SAdrian Chadd #include <sys/kernel.h> 52b8e788a5SAdrian Chadd #include <sys/socket.h> 53b8e788a5SAdrian Chadd #include <sys/sockio.h> 54b8e788a5SAdrian Chadd #include <sys/errno.h> 55b8e788a5SAdrian Chadd #include <sys/callout.h> 56b8e788a5SAdrian Chadd #include <sys/bus.h> 57b8e788a5SAdrian Chadd #include <sys/endian.h> 58b8e788a5SAdrian Chadd #include <sys/kthread.h> 59b8e788a5SAdrian Chadd #include <sys/taskqueue.h> 60b8e788a5SAdrian Chadd #include <sys/priv.h> 61b8e788a5SAdrian Chadd 62b8e788a5SAdrian Chadd #include <machine/bus.h> 63b8e788a5SAdrian Chadd 64b8e788a5SAdrian Chadd #include <net/if.h> 65b8e788a5SAdrian Chadd #include <net/if_dl.h> 66b8e788a5SAdrian Chadd #include <net/if_media.h> 67b8e788a5SAdrian Chadd #include <net/if_types.h> 68b8e788a5SAdrian Chadd #include <net/if_arp.h> 69b8e788a5SAdrian Chadd #include <net/ethernet.h> 70b8e788a5SAdrian Chadd #include <net/if_llc.h> 71b8e788a5SAdrian Chadd 72b8e788a5SAdrian Chadd #include <net80211/ieee80211_var.h> 73b8e788a5SAdrian Chadd #include <net80211/ieee80211_regdomain.h> 74b8e788a5SAdrian Chadd #ifdef IEEE80211_SUPPORT_SUPERG 75b8e788a5SAdrian Chadd #include <net80211/ieee80211_superg.h> 76b8e788a5SAdrian Chadd #endif 77b8e788a5SAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA 78b8e788a5SAdrian Chadd #include <net80211/ieee80211_tdma.h> 79b8e788a5SAdrian Chadd #endif 80eb6f0de0SAdrian Chadd #include <net80211/ieee80211_ht.h> 81b8e788a5SAdrian Chadd 82b8e788a5SAdrian Chadd #include <net/bpf.h> 83b8e788a5SAdrian Chadd 84b8e788a5SAdrian Chadd #ifdef INET 85b8e788a5SAdrian Chadd #include <netinet/in.h> 86b8e788a5SAdrian Chadd #include <netinet/if_ether.h> 87b8e788a5SAdrian Chadd #endif 88b8e788a5SAdrian Chadd 89b8e788a5SAdrian Chadd #include <dev/ath/if_athvar.h> 90b8e788a5SAdrian Chadd #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 91b8e788a5SAdrian Chadd #include <dev/ath/ath_hal/ah_diagcodes.h> 92b8e788a5SAdrian Chadd 93b8e788a5SAdrian Chadd #include <dev/ath/if_ath_debug.h> 94b8e788a5SAdrian Chadd 95b8e788a5SAdrian Chadd #ifdef ATH_TX99_DIAG 96b8e788a5SAdrian Chadd #include <dev/ath/ath_tx99/ath_tx99.h> 97b8e788a5SAdrian Chadd #endif 98b8e788a5SAdrian Chadd 99b8e788a5SAdrian Chadd #include <dev/ath/if_ath_misc.h> 100b8e788a5SAdrian Chadd #include <dev/ath/if_ath_tx.h> 101c1782ce0SAdrian Chadd #include <dev/ath/if_ath_tx_ht.h> 102b8e788a5SAdrian Chadd 10381a82688SAdrian Chadd /* 104eb6f0de0SAdrian Chadd * How many retries to perform in software 105eb6f0de0SAdrian Chadd */ 106eb6f0de0SAdrian Chadd #define SWMAX_RETRIES 10 107eb6f0de0SAdrian Chadd 108eb6f0de0SAdrian Chadd static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, 109eb6f0de0SAdrian Chadd int tid); 110eb6f0de0SAdrian Chadd static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, 111eb6f0de0SAdrian Chadd int tid); 112a108d2d6SAdrian Chadd static ieee80211_seq ath_tx_tid_seqno_assign(struct ath_softc *sc, 113a108d2d6SAdrian Chadd struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0); 114eb6f0de0SAdrian Chadd static int ath_tx_action_frame_override_queue(struct ath_softc *sc, 115eb6f0de0SAdrian Chadd struct ieee80211_node *ni, struct mbuf *m0, int *tid); 116eb6f0de0SAdrian Chadd 117eb6f0de0SAdrian Chadd /* 11881a82688SAdrian Chadd * Whether to use the 11n rate scenario functions or not 11981a82688SAdrian Chadd */ 12081a82688SAdrian Chadd static inline int 12181a82688SAdrian Chadd ath_tx_is_11n(struct ath_softc *sc) 12281a82688SAdrian Chadd { 12381a82688SAdrian Chadd return (sc->sc_ah->ah_magic == 0x20065416); 12481a82688SAdrian Chadd } 12581a82688SAdrian Chadd 126eb6f0de0SAdrian Chadd /* 127eb6f0de0SAdrian Chadd * Obtain the current TID from the given frame. 128eb6f0de0SAdrian Chadd * 129eb6f0de0SAdrian Chadd * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.) 130eb6f0de0SAdrian Chadd * This has implications for which AC/priority the packet is placed 131eb6f0de0SAdrian Chadd * in. 132eb6f0de0SAdrian Chadd */ 133eb6f0de0SAdrian Chadd static int 134eb6f0de0SAdrian Chadd ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0) 135eb6f0de0SAdrian Chadd { 136eb6f0de0SAdrian Chadd const struct ieee80211_frame *wh; 137eb6f0de0SAdrian Chadd int pri = M_WME_GETAC(m0); 138eb6f0de0SAdrian Chadd 139eb6f0de0SAdrian Chadd wh = mtod(m0, const struct ieee80211_frame *); 140eb6f0de0SAdrian Chadd if (! IEEE80211_QOS_HAS_SEQ(wh)) 141eb6f0de0SAdrian Chadd return IEEE80211_NONQOS_TID; 142eb6f0de0SAdrian Chadd else 143eb6f0de0SAdrian Chadd return WME_AC_TO_TID(pri); 144eb6f0de0SAdrian Chadd } 145eb6f0de0SAdrian Chadd 146eb6f0de0SAdrian Chadd /* 147eb6f0de0SAdrian Chadd * Determine what the correct AC queue for the given frame 148eb6f0de0SAdrian Chadd * should be. 149eb6f0de0SAdrian Chadd * 150eb6f0de0SAdrian Chadd * This code assumes that the TIDs map consistently to 151eb6f0de0SAdrian Chadd * the underlying hardware (or software) ath_txq. 152eb6f0de0SAdrian Chadd * Since the sender may try to set an AC which is 153eb6f0de0SAdrian Chadd * arbitrary, non-QoS TIDs may end up being put on 154eb6f0de0SAdrian Chadd * completely different ACs. There's no way to put a 155eb6f0de0SAdrian Chadd * TID into multiple ath_txq's for scheduling, so 156eb6f0de0SAdrian Chadd * for now we override the AC/TXQ selection and set 157eb6f0de0SAdrian Chadd * non-QOS TID frames into the BE queue. 158eb6f0de0SAdrian Chadd * 159eb6f0de0SAdrian Chadd * This may be completely incorrect - specifically, 160eb6f0de0SAdrian Chadd * some management frames may end up out of order 161eb6f0de0SAdrian Chadd * compared to the QoS traffic they're controlling. 162eb6f0de0SAdrian Chadd * I'll look into this later. 163eb6f0de0SAdrian Chadd */ 164eb6f0de0SAdrian Chadd static int 165eb6f0de0SAdrian Chadd ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0) 166eb6f0de0SAdrian Chadd { 167eb6f0de0SAdrian Chadd const struct ieee80211_frame *wh; 168eb6f0de0SAdrian Chadd int pri = M_WME_GETAC(m0); 169eb6f0de0SAdrian Chadd wh = mtod(m0, const struct ieee80211_frame *); 170eb6f0de0SAdrian Chadd if (IEEE80211_QOS_HAS_SEQ(wh)) 171eb6f0de0SAdrian Chadd return pri; 172eb6f0de0SAdrian Chadd 173eb6f0de0SAdrian Chadd return WME_AC_BE; 174eb6f0de0SAdrian Chadd } 175eb6f0de0SAdrian Chadd 176b8e788a5SAdrian Chadd void 177b8e788a5SAdrian Chadd ath_txfrag_cleanup(struct ath_softc *sc, 178b8e788a5SAdrian Chadd ath_bufhead *frags, struct ieee80211_node *ni) 179b8e788a5SAdrian Chadd { 180b8e788a5SAdrian Chadd struct ath_buf *bf, *next; 181b8e788a5SAdrian Chadd 182b8e788a5SAdrian Chadd ATH_TXBUF_LOCK_ASSERT(sc); 183b8e788a5SAdrian Chadd 1846b349e5aSAdrian Chadd TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) { 185b8e788a5SAdrian Chadd /* NB: bf assumed clean */ 1866b349e5aSAdrian Chadd TAILQ_REMOVE(frags, bf, bf_list); 187e1a50456SAdrian Chadd ath_returnbuf_head(sc, bf); 188b8e788a5SAdrian Chadd ieee80211_node_decref(ni); 189b8e788a5SAdrian Chadd } 190b8e788a5SAdrian Chadd } 191b8e788a5SAdrian Chadd 192b8e788a5SAdrian Chadd /* 193b8e788a5SAdrian Chadd * Setup xmit of a fragmented frame. Allocate a buffer 194b8e788a5SAdrian Chadd * for each frag and bump the node reference count to 195b8e788a5SAdrian Chadd * reflect the held reference to be setup by ath_tx_start. 196b8e788a5SAdrian Chadd */ 197b8e788a5SAdrian Chadd int 198b8e788a5SAdrian Chadd ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags, 199b8e788a5SAdrian Chadd struct mbuf *m0, struct ieee80211_node *ni) 200b8e788a5SAdrian Chadd { 201b8e788a5SAdrian Chadd struct mbuf *m; 202b8e788a5SAdrian Chadd struct ath_buf *bf; 203b8e788a5SAdrian Chadd 204b8e788a5SAdrian Chadd ATH_TXBUF_LOCK(sc); 205b8e788a5SAdrian Chadd for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 206af33d486SAdrian Chadd /* XXX non-management? */ 207af33d486SAdrian Chadd bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL); 208b8e788a5SAdrian Chadd if (bf == NULL) { /* out of buffers, cleanup */ 209b43facbfSAdrian Chadd device_printf(sc->sc_dev, "%s: no buffer?\n", 210b43facbfSAdrian Chadd __func__); 211b8e788a5SAdrian Chadd ath_txfrag_cleanup(sc, frags, ni); 212b8e788a5SAdrian Chadd break; 213b8e788a5SAdrian Chadd } 214b8e788a5SAdrian Chadd ieee80211_node_incref(ni); 2156b349e5aSAdrian Chadd TAILQ_INSERT_TAIL(frags, bf, bf_list); 216b8e788a5SAdrian Chadd } 217b8e788a5SAdrian Chadd ATH_TXBUF_UNLOCK(sc); 218b8e788a5SAdrian Chadd 2196b349e5aSAdrian Chadd return !TAILQ_EMPTY(frags); 220b8e788a5SAdrian Chadd } 221b8e788a5SAdrian Chadd 222b8e788a5SAdrian Chadd /* 223b8e788a5SAdrian Chadd * Reclaim mbuf resources. For fragmented frames we 224b8e788a5SAdrian Chadd * need to claim each frag chained with m_nextpkt. 225b8e788a5SAdrian Chadd */ 226b8e788a5SAdrian Chadd void 227b8e788a5SAdrian Chadd ath_freetx(struct mbuf *m) 228b8e788a5SAdrian Chadd { 229b8e788a5SAdrian Chadd struct mbuf *next; 230b8e788a5SAdrian Chadd 231b8e788a5SAdrian Chadd do { 232b8e788a5SAdrian Chadd next = m->m_nextpkt; 233b8e788a5SAdrian Chadd m->m_nextpkt = NULL; 234b8e788a5SAdrian Chadd m_freem(m); 235b8e788a5SAdrian Chadd } while ((m = next) != NULL); 236b8e788a5SAdrian Chadd } 237b8e788a5SAdrian Chadd 238b8e788a5SAdrian Chadd static int 239b8e788a5SAdrian Chadd ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0) 240b8e788a5SAdrian Chadd { 241b8e788a5SAdrian Chadd struct mbuf *m; 242b8e788a5SAdrian Chadd int error; 243b8e788a5SAdrian Chadd 244b8e788a5SAdrian Chadd /* 245b8e788a5SAdrian Chadd * Load the DMA map so any coalescing is done. This 246b8e788a5SAdrian Chadd * also calculates the number of descriptors we need. 247b8e788a5SAdrian Chadd */ 248b8e788a5SAdrian Chadd error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 249b8e788a5SAdrian Chadd bf->bf_segs, &bf->bf_nseg, 250b8e788a5SAdrian Chadd BUS_DMA_NOWAIT); 251b8e788a5SAdrian Chadd if (error == EFBIG) { 252b8e788a5SAdrian Chadd /* XXX packet requires too many descriptors */ 253b8e788a5SAdrian Chadd bf->bf_nseg = ATH_TXDESC+1; 254b8e788a5SAdrian Chadd } else if (error != 0) { 255b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_busdma++; 256b8e788a5SAdrian Chadd ath_freetx(m0); 257b8e788a5SAdrian Chadd return error; 258b8e788a5SAdrian Chadd } 259b8e788a5SAdrian Chadd /* 260b8e788a5SAdrian Chadd * Discard null packets and check for packets that 261b8e788a5SAdrian Chadd * require too many TX descriptors. We try to convert 262b8e788a5SAdrian Chadd * the latter to a cluster. 263b8e788a5SAdrian Chadd */ 264b8e788a5SAdrian Chadd if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 265b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_linear++; 266b8e788a5SAdrian Chadd m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC); 267b8e788a5SAdrian Chadd if (m == NULL) { 268b8e788a5SAdrian Chadd ath_freetx(m0); 269b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_nombuf++; 270b8e788a5SAdrian Chadd return ENOMEM; 271b8e788a5SAdrian Chadd } 272b8e788a5SAdrian Chadd m0 = m; 273b8e788a5SAdrian Chadd error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 274b8e788a5SAdrian Chadd bf->bf_segs, &bf->bf_nseg, 275b8e788a5SAdrian Chadd BUS_DMA_NOWAIT); 276b8e788a5SAdrian Chadd if (error != 0) { 277b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_busdma++; 278b8e788a5SAdrian Chadd ath_freetx(m0); 279b8e788a5SAdrian Chadd return error; 280b8e788a5SAdrian Chadd } 281b8e788a5SAdrian Chadd KASSERT(bf->bf_nseg <= ATH_TXDESC, 282b8e788a5SAdrian Chadd ("too many segments after defrag; nseg %u", bf->bf_nseg)); 283b8e788a5SAdrian Chadd } else if (bf->bf_nseg == 0) { /* null packet, discard */ 284b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_nodata++; 285b8e788a5SAdrian Chadd ath_freetx(m0); 286b8e788a5SAdrian Chadd return EIO; 287b8e788a5SAdrian Chadd } 288b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", 289b8e788a5SAdrian Chadd __func__, m0, m0->m_pkthdr.len); 290b8e788a5SAdrian Chadd bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 291b8e788a5SAdrian Chadd bf->bf_m = m0; 292b8e788a5SAdrian Chadd 293b8e788a5SAdrian Chadd return 0; 294b8e788a5SAdrian Chadd } 295b8e788a5SAdrian Chadd 2966edf1dc7SAdrian Chadd /* 2976edf1dc7SAdrian Chadd * Chain together segments+descriptors for a non-11n frame. 2986edf1dc7SAdrian Chadd */ 299b8e788a5SAdrian Chadd static void 300eb6f0de0SAdrian Chadd ath_tx_chaindesclist(struct ath_softc *sc, struct ath_buf *bf) 301b8e788a5SAdrian Chadd { 302b8e788a5SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 303b8e788a5SAdrian Chadd struct ath_desc *ds, *ds0; 304b8e788a5SAdrian Chadd int i; 305*46634305SAdrian Chadd HAL_DMA_ADDR bufAddrList[4]; 306*46634305SAdrian Chadd uint32_t segLenList[4]; 307*46634305SAdrian Chadd 3083d9b1596SAdrian Chadd /* 3093d9b1596SAdrian Chadd * XXX There's txdma and txdma_mgmt; the descriptor 3103d9b1596SAdrian Chadd * sizes must match. 3113d9b1596SAdrian Chadd */ 3123d9b1596SAdrian Chadd struct ath_descdma *dd = &sc->sc_txdma; 313b8e788a5SAdrian Chadd 314b8e788a5SAdrian Chadd /* 315b8e788a5SAdrian Chadd * Fillin the remainder of the descriptor info. 316b8e788a5SAdrian Chadd */ 317b8e788a5SAdrian Chadd ds0 = ds = bf->bf_desc; 318b8e788a5SAdrian Chadd for (i = 0; i < bf->bf_nseg; i++, ds++) { 319*46634305SAdrian Chadd bufAddrList[0] = bf->bf_segs[i].ds_addr; 320*46634305SAdrian Chadd segLenList[0] = bf->bf_segs[i].ds_len; 321*46634305SAdrian Chadd 322*46634305SAdrian Chadd /* Blank this out until multi-buf support is added for AR9300 */ 323*46634305SAdrian Chadd bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0; 324*46634305SAdrian Chadd segLenList[1] = segLenList[2] = segLenList[3] = 0; 325*46634305SAdrian Chadd 326b8e788a5SAdrian Chadd if (i == bf->bf_nseg - 1) 327bb069955SAdrian Chadd ath_hal_settxdesclink(ah, ds, 0); 328b8e788a5SAdrian Chadd else 329bb069955SAdrian Chadd ath_hal_settxdesclink(ah, ds, 3303d9b1596SAdrian Chadd bf->bf_daddr + dd->dd_descsize * (i + 1)); 331*46634305SAdrian Chadd 332*46634305SAdrian Chadd /* 333*46634305SAdrian Chadd * XXX this assumes that bfs_txq is the actual destination 334*46634305SAdrian Chadd * hardware queue at this point. It may not have been assigned, 335*46634305SAdrian Chadd * it may actually be pointing to the multicast software 336*46634305SAdrian Chadd * TXQ id. These must be fixed! 337*46634305SAdrian Chadd */ 338b8e788a5SAdrian Chadd ath_hal_filltxdesc(ah, ds 339*46634305SAdrian Chadd , bufAddrList 340*46634305SAdrian Chadd , segLenList 341*46634305SAdrian Chadd , 0 /* XXX desc id */ 342*46634305SAdrian Chadd , bf->bf_state.bfs_txq->axq_qnum /* XXX multicast? */ 343b8e788a5SAdrian Chadd , i == 0 /* first segment */ 344b8e788a5SAdrian Chadd , i == bf->bf_nseg - 1 /* last segment */ 345b8e788a5SAdrian Chadd , ds0 /* first descriptor */ 346b8e788a5SAdrian Chadd ); 347b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, 348b8e788a5SAdrian Chadd "%s: %d: %08x %08x %08x %08x %08x %08x\n", 349b8e788a5SAdrian Chadd __func__, i, ds->ds_link, ds->ds_data, 350b8e788a5SAdrian Chadd ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3516edf1dc7SAdrian Chadd bf->bf_lastds = ds; 352b8e788a5SAdrian Chadd } 3534d7f8837SAdrian Chadd bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 35481a82688SAdrian Chadd } 35581a82688SAdrian Chadd 356eb6f0de0SAdrian Chadd /* 357eb6f0de0SAdrian Chadd * Fill in the descriptor list for a aggregate subframe. 358eb6f0de0SAdrian Chadd * 359eb6f0de0SAdrian Chadd * The subframe is returned with the ds_link field in the last subframe 360eb6f0de0SAdrian Chadd * pointing to 0. 361eb6f0de0SAdrian Chadd */ 36281a82688SAdrian Chadd static void 363eb6f0de0SAdrian Chadd ath_tx_chaindesclist_subframe(struct ath_softc *sc, struct ath_buf *bf) 36481a82688SAdrian Chadd { 36581a82688SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 366eb6f0de0SAdrian Chadd struct ath_desc *ds, *ds0; 367eb6f0de0SAdrian Chadd int i; 3683d9b1596SAdrian Chadd /* 3693d9b1596SAdrian Chadd * XXX There's txdma and txdma_mgmt; the descriptor 3703d9b1596SAdrian Chadd * sizes must match. 3713d9b1596SAdrian Chadd */ 3723d9b1596SAdrian Chadd struct ath_descdma *dd = &sc->sc_txdma; 37381a82688SAdrian Chadd 374eb6f0de0SAdrian Chadd ds0 = ds = bf->bf_desc; 375eb6f0de0SAdrian Chadd 376eb6f0de0SAdrian Chadd /* 377eb6f0de0SAdrian Chadd * There's no need to call ath_hal_setupfirsttxdesc here; 378eb6f0de0SAdrian Chadd * That's only going to occur for the first frame in an aggregate. 379eb6f0de0SAdrian Chadd */ 380eb6f0de0SAdrian Chadd for (i = 0; i < bf->bf_nseg; i++, ds++) { 381eb6f0de0SAdrian Chadd ds->ds_data = bf->bf_segs[i].ds_addr; 382eb6f0de0SAdrian Chadd if (i == bf->bf_nseg - 1) 383bb069955SAdrian Chadd ath_hal_settxdesclink(ah, ds, 0); 384eb6f0de0SAdrian Chadd else 385bb069955SAdrian Chadd ath_hal_settxdesclink(ah, ds, 3863d9b1596SAdrian Chadd bf->bf_daddr + dd->dd_descsize * (i + 1)); 387eb6f0de0SAdrian Chadd 388eb6f0de0SAdrian Chadd /* 389eb6f0de0SAdrian Chadd * This performs the setup for an aggregate frame. 390eb6f0de0SAdrian Chadd * This includes enabling the aggregate flags if needed. 391eb6f0de0SAdrian Chadd */ 392eb6f0de0SAdrian Chadd ath_hal_chaintxdesc(ah, ds, 393eb6f0de0SAdrian Chadd bf->bf_state.bfs_pktlen, 394eb6f0de0SAdrian Chadd bf->bf_state.bfs_hdrlen, 395eb6f0de0SAdrian Chadd HAL_PKT_TYPE_AMPDU, /* forces aggregate bits to be set */ 396eb6f0de0SAdrian Chadd bf->bf_state.bfs_keyix, 397eb6f0de0SAdrian Chadd 0, /* cipher, calculated from keyix */ 398eb6f0de0SAdrian Chadd bf->bf_state.bfs_ndelim, 399eb6f0de0SAdrian Chadd bf->bf_segs[i].ds_len, /* segment length */ 400eb6f0de0SAdrian Chadd i == 0, /* first segment */ 40133d34032SAdrian Chadd i == bf->bf_nseg - 1, /* last segment */ 40233d34032SAdrian Chadd bf->bf_next == NULL /* last sub-frame in aggr */ 403eb6f0de0SAdrian Chadd ); 404eb6f0de0SAdrian Chadd 405eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, 406eb6f0de0SAdrian Chadd "%s: %d: %08x %08x %08x %08x %08x %08x\n", 407eb6f0de0SAdrian Chadd __func__, i, ds->ds_link, ds->ds_data, 408eb6f0de0SAdrian Chadd ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 409eb6f0de0SAdrian Chadd bf->bf_lastds = ds; 4104d7f8837SAdrian Chadd bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 4114d7f8837SAdrian Chadd BUS_DMASYNC_PREWRITE); 412eb6f0de0SAdrian Chadd } 413eb6f0de0SAdrian Chadd } 414eb6f0de0SAdrian Chadd 415eb6f0de0SAdrian Chadd /* 416d34a7347SAdrian Chadd * Set the rate control fields in the given descriptor based on 417d34a7347SAdrian Chadd * the bf_state fields and node state. 418d34a7347SAdrian Chadd * 419d34a7347SAdrian Chadd * The bfs fields should already be set with the relevant rate 420d34a7347SAdrian Chadd * control information, including whether MRR is to be enabled. 421d34a7347SAdrian Chadd * 422d34a7347SAdrian Chadd * Since the FreeBSD HAL currently sets up the first TX rate 423d34a7347SAdrian Chadd * in ath_hal_setuptxdesc(), this will setup the MRR 424d34a7347SAdrian Chadd * conditionally for the pre-11n chips, and call ath_buf_set_rate 425d34a7347SAdrian Chadd * unconditionally for 11n chips. These require the 11n rate 426d34a7347SAdrian Chadd * scenario to be set if MCS rates are enabled, so it's easier 427d34a7347SAdrian Chadd * to just always call it. The caller can then only set rates 2, 3 428d34a7347SAdrian Chadd * and 4 if multi-rate retry is needed. 429d34a7347SAdrian Chadd */ 430d34a7347SAdrian Chadd static void 431d34a7347SAdrian Chadd ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni, 432d34a7347SAdrian Chadd struct ath_buf *bf) 433d34a7347SAdrian Chadd { 434d34a7347SAdrian Chadd struct ath_rc_series *rc = bf->bf_state.bfs_rc; 435d34a7347SAdrian Chadd 436d34a7347SAdrian Chadd /* If mrr is disabled, blank tries 1, 2, 3 */ 437d34a7347SAdrian Chadd if (! bf->bf_state.bfs_ismrr) 438d34a7347SAdrian Chadd rc[1].tries = rc[2].tries = rc[3].tries = 0; 439d34a7347SAdrian Chadd 440d34a7347SAdrian Chadd /* 441d34a7347SAdrian Chadd * Always call - that way a retried descriptor will 442d34a7347SAdrian Chadd * have the MRR fields overwritten. 443d34a7347SAdrian Chadd * 444d34a7347SAdrian Chadd * XXX TODO: see if this is really needed - setting up 445d34a7347SAdrian Chadd * the first descriptor should set the MRR fields to 0 446d34a7347SAdrian Chadd * for us anyway. 447d34a7347SAdrian Chadd */ 448d34a7347SAdrian Chadd if (ath_tx_is_11n(sc)) { 449d34a7347SAdrian Chadd ath_buf_set_rate(sc, ni, bf); 450d34a7347SAdrian Chadd } else { 451d34a7347SAdrian Chadd ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc 452d34a7347SAdrian Chadd , rc[1].ratecode, rc[1].tries 453d34a7347SAdrian Chadd , rc[2].ratecode, rc[2].tries 454d34a7347SAdrian Chadd , rc[3].ratecode, rc[3].tries 455d34a7347SAdrian Chadd ); 456d34a7347SAdrian Chadd } 457d34a7347SAdrian Chadd } 458d34a7347SAdrian Chadd 459d34a7347SAdrian Chadd /* 460eb6f0de0SAdrian Chadd * Setup segments+descriptors for an 11n aggregate. 461eb6f0de0SAdrian Chadd * bf_first is the first buffer in the aggregate. 462eb6f0de0SAdrian Chadd * The descriptor list must already been linked together using 463eb6f0de0SAdrian Chadd * bf->bf_next. 464eb6f0de0SAdrian Chadd */ 465eb6f0de0SAdrian Chadd static void 466eb6f0de0SAdrian Chadd ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first) 467eb6f0de0SAdrian Chadd { 468eb6f0de0SAdrian Chadd struct ath_buf *bf, *bf_prev = NULL; 469eb6f0de0SAdrian Chadd 470eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n", 471eb6f0de0SAdrian Chadd __func__, bf_first->bf_state.bfs_nframes, 472eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_al); 473eb6f0de0SAdrian Chadd 474eb6f0de0SAdrian Chadd /* 475eb6f0de0SAdrian Chadd * Setup all descriptors of all subframes. 476eb6f0de0SAdrian Chadd */ 477eb6f0de0SAdrian Chadd bf = bf_first; 478eb6f0de0SAdrian Chadd while (bf != NULL) { 479eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 480eb6f0de0SAdrian Chadd "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n", 481eb6f0de0SAdrian Chadd __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen, 482eb6f0de0SAdrian Chadd SEQNO(bf->bf_state.bfs_seqno)); 483eb6f0de0SAdrian Chadd 484eb6f0de0SAdrian Chadd /* Sub-frame setup */ 485eb6f0de0SAdrian Chadd ath_tx_chaindesclist_subframe(sc, bf); 486eb6f0de0SAdrian Chadd 487eb6f0de0SAdrian Chadd /* 488eb6f0de0SAdrian Chadd * Link the last descriptor of the previous frame 489eb6f0de0SAdrian Chadd * to the beginning descriptor of this frame. 490eb6f0de0SAdrian Chadd */ 491eb6f0de0SAdrian Chadd if (bf_prev != NULL) 492bb069955SAdrian Chadd ath_hal_settxdesclink(sc->sc_ah, bf_prev->bf_lastds, 493bb069955SAdrian Chadd bf->bf_daddr); 494eb6f0de0SAdrian Chadd 495eb6f0de0SAdrian Chadd /* Save a copy so we can link the next descriptor in */ 496eb6f0de0SAdrian Chadd bf_prev = bf; 497eb6f0de0SAdrian Chadd bf = bf->bf_next; 498eb6f0de0SAdrian Chadd } 499eb6f0de0SAdrian Chadd 500eb6f0de0SAdrian Chadd /* 501eb6f0de0SAdrian Chadd * Setup first descriptor of first frame. 502eb6f0de0SAdrian Chadd * chaintxdesc() overwrites the descriptor entries; 503eb6f0de0SAdrian Chadd * setupfirsttxdesc() merges in things. 504eb6f0de0SAdrian Chadd * Otherwise various fields aren't set correctly (eg flags). 505eb6f0de0SAdrian Chadd */ 506eb6f0de0SAdrian Chadd ath_hal_setupfirsttxdesc(sc->sc_ah, 507eb6f0de0SAdrian Chadd bf_first->bf_desc, 508eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_al, 509875a9451SAdrian Chadd bf_first->bf_state.bfs_txflags | HAL_TXDESC_INTREQ, 510eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_txpower, 511eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_txrate0, 512eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_try0, 513eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_txantenna, 514eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_ctsrate, 515eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_ctsduration); 516eb6f0de0SAdrian Chadd 517eb6f0de0SAdrian Chadd /* 518eb6f0de0SAdrian Chadd * Set the first descriptor bf_lastds field to point to 519eb6f0de0SAdrian Chadd * the last descriptor in the last subframe, that's where 520eb6f0de0SAdrian Chadd * the status update will occur. 521eb6f0de0SAdrian Chadd */ 522eb6f0de0SAdrian Chadd bf_first->bf_lastds = bf_prev->bf_lastds; 523eb6f0de0SAdrian Chadd 524eb6f0de0SAdrian Chadd /* 525eb6f0de0SAdrian Chadd * And bf_last in the first descriptor points to the end of 526eb6f0de0SAdrian Chadd * the aggregate list. 527eb6f0de0SAdrian Chadd */ 528eb6f0de0SAdrian Chadd bf_first->bf_last = bf_prev; 529eb6f0de0SAdrian Chadd 530d34a7347SAdrian Chadd /* 531d34a7347SAdrian Chadd * setup first desc with rate and aggr info 532d34a7347SAdrian Chadd */ 533d34a7347SAdrian Chadd ath_tx_set_ratectrl(sc, bf_first->bf_node, bf_first); 534d34a7347SAdrian Chadd 5358c08c07aSAdrian Chadd /* 5368c08c07aSAdrian Chadd * Setup the last descriptor in the list. 537a6e82959SAdrian Chadd * 538a6e82959SAdrian Chadd * bf_first->bf_lastds already points to it; the rate 539a6e82959SAdrian Chadd * control information needs to be squirreled away here 540a6e82959SAdrian Chadd * as well ans clearing the moreaggr/paddelim fields. 5418c08c07aSAdrian Chadd */ 542a6e82959SAdrian Chadd ath_hal_setuplasttxdesc(sc->sc_ah, bf_first->bf_lastds, 5438c08c07aSAdrian Chadd bf_first->bf_desc); 5448c08c07aSAdrian Chadd 545eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__); 546eb6f0de0SAdrian Chadd } 547eb6f0de0SAdrian Chadd 548*46634305SAdrian Chadd /* 549*46634305SAdrian Chadd * Hand-off a frame to the multicast TX queue. 550*46634305SAdrian Chadd * 551*46634305SAdrian Chadd * This is a software TXQ which will be appended to the CAB queue 552*46634305SAdrian Chadd * during the beacon setup code. 553*46634305SAdrian Chadd * 554*46634305SAdrian Chadd * XXX TODO: since the AR9300 EDMA TX queue support wants the QCU ID 555*46634305SAdrian Chadd * as part of the TX descriptor, bf_state.bfs_txq must be updated 556*46634305SAdrian Chadd * with the actual hardware txq, or all of this will fall apart. 557*46634305SAdrian Chadd * 558*46634305SAdrian Chadd * XXX It may not be a bad idea to just stuff the QCU ID into bf_state 559*46634305SAdrian Chadd * and retire bfs_txq; then make sure the CABQ QCU ID is populated 560*46634305SAdrian Chadd * correctly. 561*46634305SAdrian Chadd */ 562eb6f0de0SAdrian Chadd static void 563eb6f0de0SAdrian Chadd ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 564eb6f0de0SAdrian Chadd struct ath_buf *bf) 565eb6f0de0SAdrian Chadd { 566eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 567eb6f0de0SAdrian Chadd KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 568eb6f0de0SAdrian Chadd ("%s: busy status 0x%x", __func__, bf->bf_flags)); 569eb6f0de0SAdrian Chadd if (txq->axq_link != NULL) { 570eb6f0de0SAdrian Chadd struct ath_buf *last = ATH_TXQ_LAST(txq, axq_q_s); 571eb6f0de0SAdrian Chadd struct ieee80211_frame *wh; 572eb6f0de0SAdrian Chadd 573eb6f0de0SAdrian Chadd /* mark previous frame */ 574eb6f0de0SAdrian Chadd wh = mtod(last->bf_m, struct ieee80211_frame *); 575eb6f0de0SAdrian Chadd wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 576eb6f0de0SAdrian Chadd bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap, 577eb6f0de0SAdrian Chadd BUS_DMASYNC_PREWRITE); 578eb6f0de0SAdrian Chadd 579eb6f0de0SAdrian Chadd /* link descriptor */ 580eb6f0de0SAdrian Chadd *txq->axq_link = bf->bf_daddr; 581eb6f0de0SAdrian Chadd } 582eb6f0de0SAdrian Chadd ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 583bb069955SAdrian Chadd ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link); 584eb6f0de0SAdrian Chadd } 585eb6f0de0SAdrian Chadd 586eb6f0de0SAdrian Chadd /* 587eb6f0de0SAdrian Chadd * Hand-off packet to a hardware queue. 588eb6f0de0SAdrian Chadd */ 589eb6f0de0SAdrian Chadd static void 590d4365d16SAdrian Chadd ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 591d4365d16SAdrian Chadd struct ath_buf *bf) 592eb6f0de0SAdrian Chadd { 593eb6f0de0SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 59481a82688SAdrian Chadd 595b8e788a5SAdrian Chadd /* 596b8e788a5SAdrian Chadd * Insert the frame on the outbound list and pass it on 597b8e788a5SAdrian Chadd * to the hardware. Multicast frames buffered for power 598b8e788a5SAdrian Chadd * save stations and transmit from the CAB queue are stored 599b8e788a5SAdrian Chadd * on a s/w only queue and loaded on to the CAB queue in 600b8e788a5SAdrian Chadd * the SWBA handler since frames only go out on DTIM and 601b8e788a5SAdrian Chadd * to avoid possible races. 602b8e788a5SAdrian Chadd */ 603eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 604b8e788a5SAdrian Chadd KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 605eb6f0de0SAdrian Chadd ("%s: busy status 0x%x", __func__, bf->bf_flags)); 606eb6f0de0SAdrian Chadd KASSERT(txq->axq_qnum != ATH_TXQ_SWQ, 607eb6f0de0SAdrian Chadd ("ath_tx_handoff_hw called for mcast queue")); 608eb6f0de0SAdrian Chadd 609ef27340cSAdrian Chadd #if 0 610ef27340cSAdrian Chadd /* 611ef27340cSAdrian Chadd * This causes a LOR. Find out where the PCU lock is being 612ef27340cSAdrian Chadd * held whilst the TXQ lock is grabbed - that shouldn't 613ef27340cSAdrian Chadd * be occuring. 614ef27340cSAdrian Chadd */ 615ef27340cSAdrian Chadd ATH_PCU_LOCK(sc); 616ef27340cSAdrian Chadd if (sc->sc_inreset_cnt) { 617ef27340cSAdrian Chadd ATH_PCU_UNLOCK(sc); 618ef27340cSAdrian Chadd DPRINTF(sc, ATH_DEBUG_RESET, 619ef27340cSAdrian Chadd "%s: called with sc_in_reset != 0\n", 620ef27340cSAdrian Chadd __func__); 621ef27340cSAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, 622ef27340cSAdrian Chadd "%s: queued: TXDP[%u] = %p (%p) depth %d\n", 623ef27340cSAdrian Chadd __func__, txq->axq_qnum, 624ef27340cSAdrian Chadd (caddr_t)bf->bf_daddr, bf->bf_desc, 625ef27340cSAdrian Chadd txq->axq_depth); 626ef27340cSAdrian Chadd ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 627ef27340cSAdrian Chadd if (bf->bf_state.bfs_aggr) 628ef27340cSAdrian Chadd txq->axq_aggr_depth++; 629ef27340cSAdrian Chadd /* 630ef27340cSAdrian Chadd * There's no need to update axq_link; the hardware 631ef27340cSAdrian Chadd * is in reset and once the reset is complete, any 632ef27340cSAdrian Chadd * non-empty queues will simply have DMA restarted. 633ef27340cSAdrian Chadd */ 634ef27340cSAdrian Chadd return; 635ef27340cSAdrian Chadd } 636ef27340cSAdrian Chadd ATH_PCU_UNLOCK(sc); 637ef27340cSAdrian Chadd #endif 638ef27340cSAdrian Chadd 639eb6f0de0SAdrian Chadd /* For now, so not to generate whitespace diffs */ 640eb6f0de0SAdrian Chadd if (1) { 641b8e788a5SAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA 642b8e788a5SAdrian Chadd int qbusy; 643b8e788a5SAdrian Chadd 644b8e788a5SAdrian Chadd ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 645b8e788a5SAdrian Chadd qbusy = ath_hal_txqenabled(ah, txq->axq_qnum); 646b8e788a5SAdrian Chadd if (txq->axq_link == NULL) { 647b8e788a5SAdrian Chadd /* 648b8e788a5SAdrian Chadd * Be careful writing the address to TXDP. If 649b8e788a5SAdrian Chadd * the tx q is enabled then this write will be 650b8e788a5SAdrian Chadd * ignored. Normally this is not an issue but 651b8e788a5SAdrian Chadd * when tdma is in use and the q is beacon gated 652b8e788a5SAdrian Chadd * this race can occur. If the q is busy then 653b8e788a5SAdrian Chadd * defer the work to later--either when another 654b8e788a5SAdrian Chadd * packet comes along or when we prepare a beacon 655b8e788a5SAdrian Chadd * frame at SWBA. 656b8e788a5SAdrian Chadd */ 657b8e788a5SAdrian Chadd if (!qbusy) { 658d4365d16SAdrian Chadd ath_hal_puttxbuf(ah, txq->axq_qnum, 659d4365d16SAdrian Chadd bf->bf_daddr); 660b8e788a5SAdrian Chadd txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 661b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, 662b8e788a5SAdrian Chadd "%s: TXDP[%u] = %p (%p) depth %d\n", 663b8e788a5SAdrian Chadd __func__, txq->axq_qnum, 664b8e788a5SAdrian Chadd (caddr_t)bf->bf_daddr, bf->bf_desc, 665b8e788a5SAdrian Chadd txq->axq_depth); 666b8e788a5SAdrian Chadd } else { 667b8e788a5SAdrian Chadd txq->axq_flags |= ATH_TXQ_PUTPENDING; 668b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 669b8e788a5SAdrian Chadd "%s: Q%u busy, defer enable\n", __func__, 670b8e788a5SAdrian Chadd txq->axq_qnum); 671b8e788a5SAdrian Chadd } 672b8e788a5SAdrian Chadd } else { 673b8e788a5SAdrian Chadd *txq->axq_link = bf->bf_daddr; 674b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, 675b8e788a5SAdrian Chadd "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 676b8e788a5SAdrian Chadd txq->axq_qnum, txq->axq_link, 677d4365d16SAdrian Chadd (caddr_t)bf->bf_daddr, bf->bf_desc, 678d4365d16SAdrian Chadd txq->axq_depth); 679b8e788a5SAdrian Chadd if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) { 680b8e788a5SAdrian Chadd /* 681b8e788a5SAdrian Chadd * The q was busy when we previously tried 682b8e788a5SAdrian Chadd * to write the address of the first buffer 683b8e788a5SAdrian Chadd * in the chain. Since it's not busy now 684b8e788a5SAdrian Chadd * handle this chore. We are certain the 685b8e788a5SAdrian Chadd * buffer at the front is the right one since 686b8e788a5SAdrian Chadd * axq_link is NULL only when the buffer list 687b8e788a5SAdrian Chadd * is/was empty. 688b8e788a5SAdrian Chadd */ 689b8e788a5SAdrian Chadd ath_hal_puttxbuf(ah, txq->axq_qnum, 6906b349e5aSAdrian Chadd TAILQ_FIRST(&txq->axq_q)->bf_daddr); 691b8e788a5SAdrian Chadd txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 692b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT, 693b8e788a5SAdrian Chadd "%s: Q%u restarted\n", __func__, 694b8e788a5SAdrian Chadd txq->axq_qnum); 695b8e788a5SAdrian Chadd } 696b8e788a5SAdrian Chadd } 697b8e788a5SAdrian Chadd #else 698b8e788a5SAdrian Chadd ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 699b8e788a5SAdrian Chadd if (txq->axq_link == NULL) { 700b8e788a5SAdrian Chadd ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 701b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, 702b8e788a5SAdrian Chadd "%s: TXDP[%u] = %p (%p) depth %d\n", 703b8e788a5SAdrian Chadd __func__, txq->axq_qnum, 704b8e788a5SAdrian Chadd (caddr_t)bf->bf_daddr, bf->bf_desc, 705b8e788a5SAdrian Chadd txq->axq_depth); 706b8e788a5SAdrian Chadd } else { 707b8e788a5SAdrian Chadd *txq->axq_link = bf->bf_daddr; 708b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, 709b8e788a5SAdrian Chadd "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 710b8e788a5SAdrian Chadd txq->axq_qnum, txq->axq_link, 711d4365d16SAdrian Chadd (caddr_t)bf->bf_daddr, bf->bf_desc, 712d4365d16SAdrian Chadd txq->axq_depth); 713b8e788a5SAdrian Chadd } 714b8e788a5SAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */ 7156edf1dc7SAdrian Chadd if (bf->bf_state.bfs_aggr) 7166edf1dc7SAdrian Chadd txq->axq_aggr_depth++; 717bb069955SAdrian Chadd ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link); 718b8e788a5SAdrian Chadd ath_hal_txstart(ah, txq->axq_qnum); 719b8e788a5SAdrian Chadd } 720b8e788a5SAdrian Chadd } 721eb6f0de0SAdrian Chadd 722eb6f0de0SAdrian Chadd /* 723eb6f0de0SAdrian Chadd * Restart TX DMA for the given TXQ. 724eb6f0de0SAdrian Chadd * 725eb6f0de0SAdrian Chadd * This must be called whether the queue is empty or not. 726eb6f0de0SAdrian Chadd */ 727746bab5bSAdrian Chadd static void 728746bab5bSAdrian Chadd ath_legacy_tx_dma_restart(struct ath_softc *sc, struct ath_txq *txq) 729eb6f0de0SAdrian Chadd { 730eb6f0de0SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 731b1f3262cSAdrian Chadd struct ath_buf *bf, *bf_last; 732eb6f0de0SAdrian Chadd 733eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 734eb6f0de0SAdrian Chadd 735eb6f0de0SAdrian Chadd /* This is always going to be cleared, empty or not */ 736eb6f0de0SAdrian Chadd txq->axq_flags &= ~ATH_TXQ_PUTPENDING; 737eb6f0de0SAdrian Chadd 738b1f3262cSAdrian Chadd /* XXX make this ATH_TXQ_FIRST */ 739eb6f0de0SAdrian Chadd bf = TAILQ_FIRST(&txq->axq_q); 740b1f3262cSAdrian Chadd bf_last = ATH_TXQ_LAST(txq, axq_q_s); 741b1f3262cSAdrian Chadd 742eb6f0de0SAdrian Chadd if (bf == NULL) 743eb6f0de0SAdrian Chadd return; 744eb6f0de0SAdrian Chadd 745eb6f0de0SAdrian Chadd ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 746bb069955SAdrian Chadd ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link); 747eb6f0de0SAdrian Chadd ath_hal_txstart(ah, txq->axq_qnum); 748eb6f0de0SAdrian Chadd } 749eb6f0de0SAdrian Chadd 750eb6f0de0SAdrian Chadd /* 751eb6f0de0SAdrian Chadd * Hand off a packet to the hardware (or mcast queue.) 752eb6f0de0SAdrian Chadd * 753eb6f0de0SAdrian Chadd * The relevant hardware txq should be locked. 754eb6f0de0SAdrian Chadd */ 755eb6f0de0SAdrian Chadd static void 756746bab5bSAdrian Chadd ath_legacy_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq, 757746bab5bSAdrian Chadd struct ath_buf *bf) 758eb6f0de0SAdrian Chadd { 759eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 760eb6f0de0SAdrian Chadd 761eb6f0de0SAdrian Chadd if (txq->axq_qnum == ATH_TXQ_SWQ) 762eb6f0de0SAdrian Chadd ath_tx_handoff_mcast(sc, txq, bf); 763eb6f0de0SAdrian Chadd else 764eb6f0de0SAdrian Chadd ath_tx_handoff_hw(sc, txq, bf); 765b8e788a5SAdrian Chadd } 766b8e788a5SAdrian Chadd 76781a82688SAdrian Chadd static int 76881a82688SAdrian Chadd ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni, 769d4365d16SAdrian Chadd struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen, 770d4365d16SAdrian Chadd int *keyix) 77181a82688SAdrian Chadd { 77212be5b9cSAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, 77312be5b9cSAdrian Chadd "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n", 77412be5b9cSAdrian Chadd __func__, 77512be5b9cSAdrian Chadd *hdrlen, 77612be5b9cSAdrian Chadd *pktlen, 77712be5b9cSAdrian Chadd isfrag, 77812be5b9cSAdrian Chadd iswep, 77912be5b9cSAdrian Chadd m0); 78012be5b9cSAdrian Chadd 78181a82688SAdrian Chadd if (iswep) { 78281a82688SAdrian Chadd const struct ieee80211_cipher *cip; 78381a82688SAdrian Chadd struct ieee80211_key *k; 78481a82688SAdrian Chadd 78581a82688SAdrian Chadd /* 78681a82688SAdrian Chadd * Construct the 802.11 header+trailer for an encrypted 78781a82688SAdrian Chadd * frame. The only reason this can fail is because of an 78881a82688SAdrian Chadd * unknown or unsupported cipher/key type. 78981a82688SAdrian Chadd */ 79081a82688SAdrian Chadd k = ieee80211_crypto_encap(ni, m0); 79181a82688SAdrian Chadd if (k == NULL) { 79281a82688SAdrian Chadd /* 79381a82688SAdrian Chadd * This can happen when the key is yanked after the 79481a82688SAdrian Chadd * frame was queued. Just discard the frame; the 79581a82688SAdrian Chadd * 802.11 layer counts failures and provides 79681a82688SAdrian Chadd * debugging/diagnostics. 79781a82688SAdrian Chadd */ 798d4365d16SAdrian Chadd return (0); 79981a82688SAdrian Chadd } 80081a82688SAdrian Chadd /* 80181a82688SAdrian Chadd * Adjust the packet + header lengths for the crypto 80281a82688SAdrian Chadd * additions and calculate the h/w key index. When 80381a82688SAdrian Chadd * a s/w mic is done the frame will have had any mic 80481a82688SAdrian Chadd * added to it prior to entry so m0->m_pkthdr.len will 80581a82688SAdrian Chadd * account for it. Otherwise we need to add it to the 80681a82688SAdrian Chadd * packet length. 80781a82688SAdrian Chadd */ 80881a82688SAdrian Chadd cip = k->wk_cipher; 80981a82688SAdrian Chadd (*hdrlen) += cip->ic_header; 81081a82688SAdrian Chadd (*pktlen) += cip->ic_header + cip->ic_trailer; 81181a82688SAdrian Chadd /* NB: frags always have any TKIP MIC done in s/w */ 81281a82688SAdrian Chadd if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag) 81381a82688SAdrian Chadd (*pktlen) += cip->ic_miclen; 81481a82688SAdrian Chadd (*keyix) = k->wk_keyix; 81581a82688SAdrian Chadd } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 81681a82688SAdrian Chadd /* 81781a82688SAdrian Chadd * Use station key cache slot, if assigned. 81881a82688SAdrian Chadd */ 81981a82688SAdrian Chadd (*keyix) = ni->ni_ucastkey.wk_keyix; 82081a82688SAdrian Chadd if ((*keyix) == IEEE80211_KEYIX_NONE) 82181a82688SAdrian Chadd (*keyix) = HAL_TXKEYIX_INVALID; 82281a82688SAdrian Chadd } else 82381a82688SAdrian Chadd (*keyix) = HAL_TXKEYIX_INVALID; 82481a82688SAdrian Chadd 825d4365d16SAdrian Chadd return (1); 82681a82688SAdrian Chadd } 82781a82688SAdrian Chadd 828e2e4a2c2SAdrian Chadd /* 829e2e4a2c2SAdrian Chadd * Calculate whether interoperability protection is required for 830e2e4a2c2SAdrian Chadd * this frame. 831e2e4a2c2SAdrian Chadd * 832e2e4a2c2SAdrian Chadd * This requires the rate control information be filled in, 833e2e4a2c2SAdrian Chadd * as the protection requirement depends upon the current 834e2e4a2c2SAdrian Chadd * operating mode / PHY. 835e2e4a2c2SAdrian Chadd */ 836e2e4a2c2SAdrian Chadd static void 837e2e4a2c2SAdrian Chadd ath_tx_calc_protection(struct ath_softc *sc, struct ath_buf *bf) 838e2e4a2c2SAdrian Chadd { 839e2e4a2c2SAdrian Chadd struct ieee80211_frame *wh; 840e2e4a2c2SAdrian Chadd uint8_t rix; 841e2e4a2c2SAdrian Chadd uint16_t flags; 842e2e4a2c2SAdrian Chadd int shortPreamble; 843e2e4a2c2SAdrian Chadd const HAL_RATE_TABLE *rt = sc->sc_currates; 844e2e4a2c2SAdrian Chadd struct ifnet *ifp = sc->sc_ifp; 845e2e4a2c2SAdrian Chadd struct ieee80211com *ic = ifp->if_l2com; 846e2e4a2c2SAdrian Chadd 847e2e4a2c2SAdrian Chadd flags = bf->bf_state.bfs_txflags; 848e2e4a2c2SAdrian Chadd rix = bf->bf_state.bfs_rc[0].rix; 849e2e4a2c2SAdrian Chadd shortPreamble = bf->bf_state.bfs_shpream; 850e2e4a2c2SAdrian Chadd wh = mtod(bf->bf_m, struct ieee80211_frame *); 851e2e4a2c2SAdrian Chadd 852e2e4a2c2SAdrian Chadd /* 853e2e4a2c2SAdrian Chadd * If 802.11g protection is enabled, determine whether 854e2e4a2c2SAdrian Chadd * to use RTS/CTS or just CTS. Note that this is only 855e2e4a2c2SAdrian Chadd * done for OFDM unicast frames. 856e2e4a2c2SAdrian Chadd */ 857e2e4a2c2SAdrian Chadd if ((ic->ic_flags & IEEE80211_F_USEPROT) && 858e2e4a2c2SAdrian Chadd rt->info[rix].phy == IEEE80211_T_OFDM && 859e2e4a2c2SAdrian Chadd (flags & HAL_TXDESC_NOACK) == 0) { 860e2e4a2c2SAdrian Chadd bf->bf_state.bfs_doprot = 1; 861e2e4a2c2SAdrian Chadd /* XXX fragments must use CCK rates w/ protection */ 862e2e4a2c2SAdrian Chadd if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 863e2e4a2c2SAdrian Chadd flags |= HAL_TXDESC_RTSENA; 864e2e4a2c2SAdrian Chadd } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 865e2e4a2c2SAdrian Chadd flags |= HAL_TXDESC_CTSENA; 866e2e4a2c2SAdrian Chadd } 867e2e4a2c2SAdrian Chadd /* 868e2e4a2c2SAdrian Chadd * For frags it would be desirable to use the 869e2e4a2c2SAdrian Chadd * highest CCK rate for RTS/CTS. But stations 870e2e4a2c2SAdrian Chadd * farther away may detect it at a lower CCK rate 871e2e4a2c2SAdrian Chadd * so use the configured protection rate instead 872e2e4a2c2SAdrian Chadd * (for now). 873e2e4a2c2SAdrian Chadd */ 874e2e4a2c2SAdrian Chadd sc->sc_stats.ast_tx_protect++; 875e2e4a2c2SAdrian Chadd } 876e2e4a2c2SAdrian Chadd 877e2e4a2c2SAdrian Chadd /* 878e2e4a2c2SAdrian Chadd * If 11n protection is enabled and it's a HT frame, 879e2e4a2c2SAdrian Chadd * enable RTS. 880e2e4a2c2SAdrian Chadd * 881e2e4a2c2SAdrian Chadd * XXX ic_htprotmode or ic_curhtprotmode? 882e2e4a2c2SAdrian Chadd * XXX should it_htprotmode only matter if ic_curhtprotmode 883e2e4a2c2SAdrian Chadd * XXX indicates it's not a HT pure environment? 884e2e4a2c2SAdrian Chadd */ 885e2e4a2c2SAdrian Chadd if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) && 886e2e4a2c2SAdrian Chadd rt->info[rix].phy == IEEE80211_T_HT && 887e2e4a2c2SAdrian Chadd (flags & HAL_TXDESC_NOACK) == 0) { 888e2e4a2c2SAdrian Chadd flags |= HAL_TXDESC_RTSENA; 889e2e4a2c2SAdrian Chadd sc->sc_stats.ast_tx_htprotect++; 890e2e4a2c2SAdrian Chadd } 891e2e4a2c2SAdrian Chadd bf->bf_state.bfs_txflags = flags; 892e2e4a2c2SAdrian Chadd } 893e2e4a2c2SAdrian Chadd 894e2e4a2c2SAdrian Chadd /* 895e2e4a2c2SAdrian Chadd * Update the frame duration given the currently selected rate. 896e2e4a2c2SAdrian Chadd * 897e2e4a2c2SAdrian Chadd * This also updates the frame duration value, so it will require 898e2e4a2c2SAdrian Chadd * a DMA flush. 899e2e4a2c2SAdrian Chadd */ 900e2e4a2c2SAdrian Chadd static void 901e2e4a2c2SAdrian Chadd ath_tx_calc_duration(struct ath_softc *sc, struct ath_buf *bf) 902e2e4a2c2SAdrian Chadd { 903e2e4a2c2SAdrian Chadd struct ieee80211_frame *wh; 904e2e4a2c2SAdrian Chadd uint8_t rix; 905e2e4a2c2SAdrian Chadd uint16_t flags; 906e2e4a2c2SAdrian Chadd int shortPreamble; 907e2e4a2c2SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 908e2e4a2c2SAdrian Chadd const HAL_RATE_TABLE *rt = sc->sc_currates; 909e2e4a2c2SAdrian Chadd int isfrag = bf->bf_m->m_flags & M_FRAG; 910e2e4a2c2SAdrian Chadd 911e2e4a2c2SAdrian Chadd flags = bf->bf_state.bfs_txflags; 912e2e4a2c2SAdrian Chadd rix = bf->bf_state.bfs_rc[0].rix; 913e2e4a2c2SAdrian Chadd shortPreamble = bf->bf_state.bfs_shpream; 914e2e4a2c2SAdrian Chadd wh = mtod(bf->bf_m, struct ieee80211_frame *); 915e2e4a2c2SAdrian Chadd 916e2e4a2c2SAdrian Chadd /* 917e2e4a2c2SAdrian Chadd * Calculate duration. This logically belongs in the 802.11 918e2e4a2c2SAdrian Chadd * layer but it lacks sufficient information to calculate it. 919e2e4a2c2SAdrian Chadd */ 920e2e4a2c2SAdrian Chadd if ((flags & HAL_TXDESC_NOACK) == 0 && 921e2e4a2c2SAdrian Chadd (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 922e2e4a2c2SAdrian Chadd u_int16_t dur; 923e2e4a2c2SAdrian Chadd if (shortPreamble) 924e2e4a2c2SAdrian Chadd dur = rt->info[rix].spAckDuration; 925e2e4a2c2SAdrian Chadd else 926e2e4a2c2SAdrian Chadd dur = rt->info[rix].lpAckDuration; 927e2e4a2c2SAdrian Chadd if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) { 928e2e4a2c2SAdrian Chadd dur += dur; /* additional SIFS+ACK */ 929e2e4a2c2SAdrian Chadd KASSERT(bf->bf_m->m_nextpkt != NULL, ("no fragment")); 930e2e4a2c2SAdrian Chadd /* 931e2e4a2c2SAdrian Chadd * Include the size of next fragment so NAV is 932e2e4a2c2SAdrian Chadd * updated properly. The last fragment uses only 933e2e4a2c2SAdrian Chadd * the ACK duration 934e2e4a2c2SAdrian Chadd */ 935e2e4a2c2SAdrian Chadd dur += ath_hal_computetxtime(ah, rt, 936e2e4a2c2SAdrian Chadd bf->bf_m->m_nextpkt->m_pkthdr.len, 937e2e4a2c2SAdrian Chadd rix, shortPreamble); 938e2e4a2c2SAdrian Chadd } 939e2e4a2c2SAdrian Chadd if (isfrag) { 940e2e4a2c2SAdrian Chadd /* 941e2e4a2c2SAdrian Chadd * Force hardware to use computed duration for next 942e2e4a2c2SAdrian Chadd * fragment by disabling multi-rate retry which updates 943e2e4a2c2SAdrian Chadd * duration based on the multi-rate duration table. 944e2e4a2c2SAdrian Chadd */ 945e2e4a2c2SAdrian Chadd bf->bf_state.bfs_ismrr = 0; 946e2e4a2c2SAdrian Chadd bf->bf_state.bfs_try0 = ATH_TXMGTTRY; 947e2e4a2c2SAdrian Chadd /* XXX update bfs_rc[0].try? */ 948e2e4a2c2SAdrian Chadd } 949e2e4a2c2SAdrian Chadd 950e2e4a2c2SAdrian Chadd /* Update the duration field itself */ 951e2e4a2c2SAdrian Chadd *(u_int16_t *)wh->i_dur = htole16(dur); 952e2e4a2c2SAdrian Chadd } 953e2e4a2c2SAdrian Chadd } 954e2e4a2c2SAdrian Chadd 955e42b5dbaSAdrian Chadd static uint8_t 956e42b5dbaSAdrian Chadd ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt, 957eb6f0de0SAdrian Chadd int cix, int shortPreamble) 95879f02dbfSAdrian Chadd { 959e42b5dbaSAdrian Chadd uint8_t ctsrate; 960e42b5dbaSAdrian Chadd 96179f02dbfSAdrian Chadd /* 96279f02dbfSAdrian Chadd * CTS transmit rate is derived from the transmit rate 96379f02dbfSAdrian Chadd * by looking in the h/w rate table. We must also factor 96479f02dbfSAdrian Chadd * in whether or not a short preamble is to be used. 96579f02dbfSAdrian Chadd */ 96679f02dbfSAdrian Chadd /* NB: cix is set above where RTS/CTS is enabled */ 96779f02dbfSAdrian Chadd KASSERT(cix != 0xff, ("cix not setup")); 968e42b5dbaSAdrian Chadd ctsrate = rt->info[cix].rateCode; 969e42b5dbaSAdrian Chadd 970e42b5dbaSAdrian Chadd /* XXX this should only matter for legacy rates */ 971e42b5dbaSAdrian Chadd if (shortPreamble) 972e42b5dbaSAdrian Chadd ctsrate |= rt->info[cix].shortPreamble; 973e42b5dbaSAdrian Chadd 974d4365d16SAdrian Chadd return (ctsrate); 975e42b5dbaSAdrian Chadd } 976e42b5dbaSAdrian Chadd 977e42b5dbaSAdrian Chadd /* 978e42b5dbaSAdrian Chadd * Calculate the RTS/CTS duration for legacy frames. 979e42b5dbaSAdrian Chadd */ 980e42b5dbaSAdrian Chadd static int 981e42b5dbaSAdrian Chadd ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix, 982e42b5dbaSAdrian Chadd int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt, 983e42b5dbaSAdrian Chadd int flags) 984e42b5dbaSAdrian Chadd { 985e42b5dbaSAdrian Chadd int ctsduration = 0; 986e42b5dbaSAdrian Chadd 987e42b5dbaSAdrian Chadd /* This mustn't be called for HT modes */ 988e42b5dbaSAdrian Chadd if (rt->info[cix].phy == IEEE80211_T_HT) { 989e42b5dbaSAdrian Chadd printf("%s: HT rate where it shouldn't be (0x%x)\n", 990e42b5dbaSAdrian Chadd __func__, rt->info[cix].rateCode); 991d4365d16SAdrian Chadd return (-1); 992e42b5dbaSAdrian Chadd } 993e42b5dbaSAdrian Chadd 99479f02dbfSAdrian Chadd /* 99579f02dbfSAdrian Chadd * Compute the transmit duration based on the frame 99679f02dbfSAdrian Chadd * size and the size of an ACK frame. We call into the 99779f02dbfSAdrian Chadd * HAL to do the computation since it depends on the 99879f02dbfSAdrian Chadd * characteristics of the actual PHY being used. 99979f02dbfSAdrian Chadd * 100079f02dbfSAdrian Chadd * NB: CTS is assumed the same size as an ACK so we can 100179f02dbfSAdrian Chadd * use the precalculated ACK durations. 100279f02dbfSAdrian Chadd */ 100379f02dbfSAdrian Chadd if (shortPreamble) { 100479f02dbfSAdrian Chadd if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1005e42b5dbaSAdrian Chadd ctsduration += rt->info[cix].spAckDuration; 1006e42b5dbaSAdrian Chadd ctsduration += ath_hal_computetxtime(ah, 100779f02dbfSAdrian Chadd rt, pktlen, rix, AH_TRUE); 100879f02dbfSAdrian Chadd if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1009e42b5dbaSAdrian Chadd ctsduration += rt->info[rix].spAckDuration; 101079f02dbfSAdrian Chadd } else { 101179f02dbfSAdrian Chadd if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 1012e42b5dbaSAdrian Chadd ctsduration += rt->info[cix].lpAckDuration; 1013e42b5dbaSAdrian Chadd ctsduration += ath_hal_computetxtime(ah, 101479f02dbfSAdrian Chadd rt, pktlen, rix, AH_FALSE); 101579f02dbfSAdrian Chadd if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 1016e42b5dbaSAdrian Chadd ctsduration += rt->info[rix].lpAckDuration; 101779f02dbfSAdrian Chadd } 1018e42b5dbaSAdrian Chadd 1019d4365d16SAdrian Chadd return (ctsduration); 102079f02dbfSAdrian Chadd } 102179f02dbfSAdrian Chadd 1022eb6f0de0SAdrian Chadd /* 1023eb6f0de0SAdrian Chadd * Update the given ath_buf with updated rts/cts setup and duration 1024eb6f0de0SAdrian Chadd * values. 1025eb6f0de0SAdrian Chadd * 1026eb6f0de0SAdrian Chadd * To support rate lookups for each software retry, the rts/cts rate 1027eb6f0de0SAdrian Chadd * and cts duration must be re-calculated. 1028eb6f0de0SAdrian Chadd * 1029eb6f0de0SAdrian Chadd * This function assumes the RTS/CTS flags have been set as needed; 1030eb6f0de0SAdrian Chadd * mrr has been disabled; and the rate control lookup has been done. 1031eb6f0de0SAdrian Chadd * 1032eb6f0de0SAdrian Chadd * XXX TODO: MRR need only be disabled for the pre-11n NICs. 1033eb6f0de0SAdrian Chadd * XXX The 11n NICs support per-rate RTS/CTS configuration. 1034eb6f0de0SAdrian Chadd */ 1035eb6f0de0SAdrian Chadd static void 1036eb6f0de0SAdrian Chadd ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf) 1037eb6f0de0SAdrian Chadd { 1038eb6f0de0SAdrian Chadd uint16_t ctsduration = 0; 1039eb6f0de0SAdrian Chadd uint8_t ctsrate = 0; 1040eb6f0de0SAdrian Chadd uint8_t rix = bf->bf_state.bfs_rc[0].rix; 1041eb6f0de0SAdrian Chadd uint8_t cix = 0; 1042eb6f0de0SAdrian Chadd const HAL_RATE_TABLE *rt = sc->sc_currates; 1043eb6f0de0SAdrian Chadd 1044eb6f0de0SAdrian Chadd /* 1045eb6f0de0SAdrian Chadd * No RTS/CTS enabled? Don't bother. 1046eb6f0de0SAdrian Chadd */ 1047875a9451SAdrian Chadd if ((bf->bf_state.bfs_txflags & 1048eb6f0de0SAdrian Chadd (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) { 1049eb6f0de0SAdrian Chadd /* XXX is this really needed? */ 1050eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsrate = 0; 1051eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsduration = 0; 1052eb6f0de0SAdrian Chadd return; 1053eb6f0de0SAdrian Chadd } 1054eb6f0de0SAdrian Chadd 1055eb6f0de0SAdrian Chadd /* 1056eb6f0de0SAdrian Chadd * If protection is enabled, use the protection rix control 1057eb6f0de0SAdrian Chadd * rate. Otherwise use the rate0 control rate. 1058eb6f0de0SAdrian Chadd */ 1059eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_doprot) 1060eb6f0de0SAdrian Chadd rix = sc->sc_protrix; 1061eb6f0de0SAdrian Chadd else 1062eb6f0de0SAdrian Chadd rix = bf->bf_state.bfs_rc[0].rix; 1063eb6f0de0SAdrian Chadd 1064eb6f0de0SAdrian Chadd /* 1065eb6f0de0SAdrian Chadd * If the raw path has hard-coded ctsrate0 to something, 1066eb6f0de0SAdrian Chadd * use it. 1067eb6f0de0SAdrian Chadd */ 1068eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_ctsrate0 != 0) 1069eb6f0de0SAdrian Chadd cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0); 1070eb6f0de0SAdrian Chadd else 1071eb6f0de0SAdrian Chadd /* Control rate from above */ 1072eb6f0de0SAdrian Chadd cix = rt->info[rix].controlRate; 1073eb6f0de0SAdrian Chadd 1074eb6f0de0SAdrian Chadd /* Calculate the rtscts rate for the given cix */ 1075eb6f0de0SAdrian Chadd ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix, 1076eb6f0de0SAdrian Chadd bf->bf_state.bfs_shpream); 1077eb6f0de0SAdrian Chadd 1078eb6f0de0SAdrian Chadd /* The 11n chipsets do ctsduration calculations for you */ 1079eb6f0de0SAdrian Chadd if (! ath_tx_is_11n(sc)) 1080eb6f0de0SAdrian Chadd ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix, 1081eb6f0de0SAdrian Chadd bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen, 1082875a9451SAdrian Chadd rt, bf->bf_state.bfs_txflags); 1083eb6f0de0SAdrian Chadd 1084eb6f0de0SAdrian Chadd /* Squirrel away in ath_buf */ 1085eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsrate = ctsrate; 1086eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsduration = ctsduration; 1087eb6f0de0SAdrian Chadd 1088eb6f0de0SAdrian Chadd /* 1089eb6f0de0SAdrian Chadd * Must disable multi-rate retry when using RTS/CTS. 1090eb6f0de0SAdrian Chadd */ 1091af017101SAdrian Chadd if (!sc->sc_mrrprot) { 1092eb6f0de0SAdrian Chadd bf->bf_state.bfs_ismrr = 0; 1093eb6f0de0SAdrian Chadd bf->bf_state.bfs_try0 = 1094eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */ 1095eb6f0de0SAdrian Chadd } 1096af017101SAdrian Chadd } 1097eb6f0de0SAdrian Chadd 1098eb6f0de0SAdrian Chadd /* 1099eb6f0de0SAdrian Chadd * Setup the descriptor chain for a normal or fast-frame 1100eb6f0de0SAdrian Chadd * frame. 1101*46634305SAdrian Chadd * 1102*46634305SAdrian Chadd * XXX TODO: extend to include the destination hardware QCU ID. 1103*46634305SAdrian Chadd * Make sure that is correct. Make sure that when being added 1104*46634305SAdrian Chadd * to the mcastq, the CABQ QCUID is set or things will get a bit 1105*46634305SAdrian Chadd * odd. 1106eb6f0de0SAdrian Chadd */ 1107eb6f0de0SAdrian Chadd static void 1108eb6f0de0SAdrian Chadd ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf) 1109eb6f0de0SAdrian Chadd { 1110eb6f0de0SAdrian Chadd struct ath_desc *ds = bf->bf_desc; 1111eb6f0de0SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 1112eb6f0de0SAdrian Chadd 1113eb6f0de0SAdrian Chadd ath_hal_setuptxdesc(ah, ds 1114eb6f0de0SAdrian Chadd , bf->bf_state.bfs_pktlen /* packet length */ 1115eb6f0de0SAdrian Chadd , bf->bf_state.bfs_hdrlen /* header length */ 1116eb6f0de0SAdrian Chadd , bf->bf_state.bfs_atype /* Atheros packet type */ 1117eb6f0de0SAdrian Chadd , bf->bf_state.bfs_txpower /* txpower */ 1118eb6f0de0SAdrian Chadd , bf->bf_state.bfs_txrate0 1119eb6f0de0SAdrian Chadd , bf->bf_state.bfs_try0 /* series 0 rate/tries */ 1120eb6f0de0SAdrian Chadd , bf->bf_state.bfs_keyix /* key cache index */ 1121eb6f0de0SAdrian Chadd , bf->bf_state.bfs_txantenna /* antenna mode */ 1122875a9451SAdrian Chadd , bf->bf_state.bfs_txflags /* flags */ 1123eb6f0de0SAdrian Chadd , bf->bf_state.bfs_ctsrate /* rts/cts rate */ 1124eb6f0de0SAdrian Chadd , bf->bf_state.bfs_ctsduration /* rts/cts duration */ 1125eb6f0de0SAdrian Chadd ); 1126eb6f0de0SAdrian Chadd 1127eb6f0de0SAdrian Chadd /* 1128eb6f0de0SAdrian Chadd * This will be overriden when the descriptor chain is written. 1129eb6f0de0SAdrian Chadd */ 1130eb6f0de0SAdrian Chadd bf->bf_lastds = ds; 1131eb6f0de0SAdrian Chadd bf->bf_last = bf; 1132eb6f0de0SAdrian Chadd 1133d34a7347SAdrian Chadd /* Set rate control and descriptor chain for this frame */ 1134d34a7347SAdrian Chadd ath_tx_set_ratectrl(sc, bf->bf_node, bf); 1135d34a7347SAdrian Chadd ath_tx_chaindesclist(sc, bf); 1136eb6f0de0SAdrian Chadd } 1137eb6f0de0SAdrian Chadd 1138eb6f0de0SAdrian Chadd /* 1139eb6f0de0SAdrian Chadd * Do a rate lookup. 1140eb6f0de0SAdrian Chadd * 1141eb6f0de0SAdrian Chadd * This performs a rate lookup for the given ath_buf only if it's required. 1142eb6f0de0SAdrian Chadd * Non-data frames and raw frames don't require it. 1143eb6f0de0SAdrian Chadd * 1144eb6f0de0SAdrian Chadd * This populates the primary and MRR entries; MRR values are 1145eb6f0de0SAdrian Chadd * then disabled later on if something requires it (eg RTS/CTS on 1146eb6f0de0SAdrian Chadd * pre-11n chipsets. 1147eb6f0de0SAdrian Chadd * 1148eb6f0de0SAdrian Chadd * This needs to be done before the RTS/CTS fields are calculated 1149eb6f0de0SAdrian Chadd * as they may depend upon the rate chosen. 1150eb6f0de0SAdrian Chadd */ 1151eb6f0de0SAdrian Chadd static void 1152eb6f0de0SAdrian Chadd ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf) 1153eb6f0de0SAdrian Chadd { 1154eb6f0de0SAdrian Chadd uint8_t rate, rix; 1155eb6f0de0SAdrian Chadd int try0; 1156eb6f0de0SAdrian Chadd 1157eb6f0de0SAdrian Chadd if (! bf->bf_state.bfs_doratelookup) 1158eb6f0de0SAdrian Chadd return; 1159eb6f0de0SAdrian Chadd 1160eb6f0de0SAdrian Chadd /* Get rid of any previous state */ 1161eb6f0de0SAdrian Chadd bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1162eb6f0de0SAdrian Chadd 1163eb6f0de0SAdrian Chadd ATH_NODE_LOCK(ATH_NODE(bf->bf_node)); 1164eb6f0de0SAdrian Chadd ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream, 1165eb6f0de0SAdrian Chadd bf->bf_state.bfs_pktlen, &rix, &try0, &rate); 1166eb6f0de0SAdrian Chadd 1167eb6f0de0SAdrian Chadd /* In case MRR is disabled, make sure rc[0] is setup correctly */ 1168eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].rix = rix; 1169eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].ratecode = rate; 1170eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].tries = try0; 1171eb6f0de0SAdrian Chadd 1172eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY) 1173eb6f0de0SAdrian Chadd ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix, 1174eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc); 1175eb6f0de0SAdrian Chadd ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node)); 1176eb6f0de0SAdrian Chadd 1177eb6f0de0SAdrian Chadd sc->sc_txrix = rix; /* for LED blinking */ 1178eb6f0de0SAdrian Chadd sc->sc_lastdatarix = rix; /* for fast frames */ 1179eb6f0de0SAdrian Chadd bf->bf_state.bfs_try0 = try0; 1180eb6f0de0SAdrian Chadd bf->bf_state.bfs_txrate0 = rate; 1181eb6f0de0SAdrian Chadd } 1182eb6f0de0SAdrian Chadd 1183eb6f0de0SAdrian Chadd /* 1184eb6f0de0SAdrian Chadd * Transmit the given frame to the hardware. 1185eb6f0de0SAdrian Chadd * 1186eb6f0de0SAdrian Chadd * The frame must already be setup; rate control must already have 1187eb6f0de0SAdrian Chadd * been done. 1188eb6f0de0SAdrian Chadd * 1189eb6f0de0SAdrian Chadd * XXX since the TXQ lock is being held here (and I dislike holding 1190eb6f0de0SAdrian Chadd * it for this long when not doing software aggregation), later on 1191eb6f0de0SAdrian Chadd * break this function into "setup_normal" and "xmit_normal". The 1192eb6f0de0SAdrian Chadd * lock only needs to be held for the ath_tx_handoff call. 1193eb6f0de0SAdrian Chadd */ 1194eb6f0de0SAdrian Chadd static void 1195eb6f0de0SAdrian Chadd ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq, 1196eb6f0de0SAdrian Chadd struct ath_buf *bf) 1197eb6f0de0SAdrian Chadd { 1198eb6f0de0SAdrian Chadd 1199eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 1200eb6f0de0SAdrian Chadd 1201eb6f0de0SAdrian Chadd /* Setup the descriptor before handoff */ 1202eb6f0de0SAdrian Chadd ath_tx_do_ratelookup(sc, bf); 1203e2e4a2c2SAdrian Chadd ath_tx_calc_duration(sc, bf); 1204e2e4a2c2SAdrian Chadd ath_tx_calc_protection(sc, bf); 1205eb6f0de0SAdrian Chadd ath_tx_set_rtscts(sc, bf); 1206e2e4a2c2SAdrian Chadd ath_tx_rate_fill_rcflags(sc, bf); 1207eb6f0de0SAdrian Chadd ath_tx_setds(sc, bf); 1208eb6f0de0SAdrian Chadd 1209eb6f0de0SAdrian Chadd /* Hand off to hardware */ 1210eb6f0de0SAdrian Chadd ath_tx_handoff(sc, txq, bf); 1211eb6f0de0SAdrian Chadd } 1212eb6f0de0SAdrian Chadd 1213eb6f0de0SAdrian Chadd 1214eb6f0de0SAdrian Chadd 1215eb6f0de0SAdrian Chadd static int 1216eb6f0de0SAdrian Chadd ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni, 1217b43facbfSAdrian Chadd struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq) 1218b8e788a5SAdrian Chadd { 1219b8e788a5SAdrian Chadd struct ieee80211vap *vap = ni->ni_vap; 1220b8e788a5SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 1221b8e788a5SAdrian Chadd struct ifnet *ifp = sc->sc_ifp; 1222b8e788a5SAdrian Chadd struct ieee80211com *ic = ifp->if_l2com; 1223b8e788a5SAdrian Chadd const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 1224b8e788a5SAdrian Chadd int error, iswep, ismcast, isfrag, ismrr; 1225eb6f0de0SAdrian Chadd int keyix, hdrlen, pktlen, try0 = 0; 1226eb6f0de0SAdrian Chadd u_int8_t rix = 0, txrate = 0; 1227b8e788a5SAdrian Chadd struct ath_desc *ds; 1228b8e788a5SAdrian Chadd struct ieee80211_frame *wh; 1229eb6f0de0SAdrian Chadd u_int subtype, flags; 1230b8e788a5SAdrian Chadd HAL_PKT_TYPE atype; 1231b8e788a5SAdrian Chadd const HAL_RATE_TABLE *rt; 1232b8e788a5SAdrian Chadd HAL_BOOL shortPreamble; 1233b8e788a5SAdrian Chadd struct ath_node *an; 1234b8e788a5SAdrian Chadd u_int pri; 1235b8e788a5SAdrian Chadd 12367561cb5cSAdrian Chadd /* 12377561cb5cSAdrian Chadd * To ensure that both sequence numbers and the CCMP PN handling 12387561cb5cSAdrian Chadd * is "correct", make sure that the relevant TID queue is locked. 12397561cb5cSAdrian Chadd * Otherwise the CCMP PN and seqno may appear out of order, causing 12407561cb5cSAdrian Chadd * re-ordered frames to have out of order CCMP PN's, resulting 12417561cb5cSAdrian Chadd * in many, many frame drops. 12427561cb5cSAdrian Chadd */ 12437561cb5cSAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 12447561cb5cSAdrian Chadd 1245b8e788a5SAdrian Chadd wh = mtod(m0, struct ieee80211_frame *); 1246b8e788a5SAdrian Chadd iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 1247b8e788a5SAdrian Chadd ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1248b8e788a5SAdrian Chadd isfrag = m0->m_flags & M_FRAG; 1249b8e788a5SAdrian Chadd hdrlen = ieee80211_anyhdrsize(wh); 1250b8e788a5SAdrian Chadd /* 1251b8e788a5SAdrian Chadd * Packet length must not include any 1252b8e788a5SAdrian Chadd * pad bytes; deduct them here. 1253b8e788a5SAdrian Chadd */ 1254b8e788a5SAdrian Chadd pktlen = m0->m_pkthdr.len - (hdrlen & 3); 1255b8e788a5SAdrian Chadd 125681a82688SAdrian Chadd /* Handle encryption twiddling if needed */ 1257eb6f0de0SAdrian Chadd if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen, 1258eb6f0de0SAdrian Chadd &pktlen, &keyix)) { 1259b8e788a5SAdrian Chadd ath_freetx(m0); 1260b8e788a5SAdrian Chadd return EIO; 1261b8e788a5SAdrian Chadd } 1262b8e788a5SAdrian Chadd 1263b8e788a5SAdrian Chadd /* packet header may have moved, reset our local pointer */ 1264b8e788a5SAdrian Chadd wh = mtod(m0, struct ieee80211_frame *); 1265b8e788a5SAdrian Chadd 1266b8e788a5SAdrian Chadd pktlen += IEEE80211_CRC_LEN; 1267b8e788a5SAdrian Chadd 1268b8e788a5SAdrian Chadd /* 1269b8e788a5SAdrian Chadd * Load the DMA map so any coalescing is done. This 1270b8e788a5SAdrian Chadd * also calculates the number of descriptors we need. 1271b8e788a5SAdrian Chadd */ 1272b8e788a5SAdrian Chadd error = ath_tx_dmasetup(sc, bf, m0); 1273b8e788a5SAdrian Chadd if (error != 0) 1274b8e788a5SAdrian Chadd return error; 1275b8e788a5SAdrian Chadd bf->bf_node = ni; /* NB: held reference */ 1276b8e788a5SAdrian Chadd m0 = bf->bf_m; /* NB: may have changed */ 1277b8e788a5SAdrian Chadd wh = mtod(m0, struct ieee80211_frame *); 1278b8e788a5SAdrian Chadd 1279b8e788a5SAdrian Chadd /* setup descriptors */ 1280b8e788a5SAdrian Chadd ds = bf->bf_desc; 1281b8e788a5SAdrian Chadd rt = sc->sc_currates; 1282b8e788a5SAdrian Chadd KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1283b8e788a5SAdrian Chadd 1284b8e788a5SAdrian Chadd /* 1285b8e788a5SAdrian Chadd * NB: the 802.11 layer marks whether or not we should 1286b8e788a5SAdrian Chadd * use short preamble based on the current mode and 1287b8e788a5SAdrian Chadd * negotiated parameters. 1288b8e788a5SAdrian Chadd */ 1289b8e788a5SAdrian Chadd if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1290b8e788a5SAdrian Chadd (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 1291b8e788a5SAdrian Chadd shortPreamble = AH_TRUE; 1292b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_shortpre++; 1293b8e788a5SAdrian Chadd } else { 1294b8e788a5SAdrian Chadd shortPreamble = AH_FALSE; 1295b8e788a5SAdrian Chadd } 1296b8e788a5SAdrian Chadd 1297b8e788a5SAdrian Chadd an = ATH_NODE(ni); 1298b8e788a5SAdrian Chadd flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1299b8e788a5SAdrian Chadd ismrr = 0; /* default no multi-rate retry*/ 1300b8e788a5SAdrian Chadd pri = M_WME_GETAC(m0); /* honor classification */ 1301b8e788a5SAdrian Chadd /* XXX use txparams instead of fixed values */ 1302b8e788a5SAdrian Chadd /* 1303b8e788a5SAdrian Chadd * Calculate Atheros packet type from IEEE80211 packet header, 1304b8e788a5SAdrian Chadd * setup for rate calculations, and select h/w transmit queue. 1305b8e788a5SAdrian Chadd */ 1306b8e788a5SAdrian Chadd switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1307b8e788a5SAdrian Chadd case IEEE80211_FC0_TYPE_MGT: 1308b8e788a5SAdrian Chadd subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1309b8e788a5SAdrian Chadd if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 1310b8e788a5SAdrian Chadd atype = HAL_PKT_TYPE_BEACON; 1311b8e788a5SAdrian Chadd else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1312b8e788a5SAdrian Chadd atype = HAL_PKT_TYPE_PROBE_RESP; 1313b8e788a5SAdrian Chadd else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 1314b8e788a5SAdrian Chadd atype = HAL_PKT_TYPE_ATIM; 1315b8e788a5SAdrian Chadd else 1316b8e788a5SAdrian Chadd atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 1317b8e788a5SAdrian Chadd rix = an->an_mgmtrix; 1318b8e788a5SAdrian Chadd txrate = rt->info[rix].rateCode; 1319b8e788a5SAdrian Chadd if (shortPreamble) 1320b8e788a5SAdrian Chadd txrate |= rt->info[rix].shortPreamble; 1321b8e788a5SAdrian Chadd try0 = ATH_TXMGTTRY; 1322b8e788a5SAdrian Chadd flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1323b8e788a5SAdrian Chadd break; 1324b8e788a5SAdrian Chadd case IEEE80211_FC0_TYPE_CTL: 1325b8e788a5SAdrian Chadd atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 1326b8e788a5SAdrian Chadd rix = an->an_mgmtrix; 1327b8e788a5SAdrian Chadd txrate = rt->info[rix].rateCode; 1328b8e788a5SAdrian Chadd if (shortPreamble) 1329b8e788a5SAdrian Chadd txrate |= rt->info[rix].shortPreamble; 1330b8e788a5SAdrian Chadd try0 = ATH_TXMGTTRY; 1331b8e788a5SAdrian Chadd flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1332b8e788a5SAdrian Chadd break; 1333b8e788a5SAdrian Chadd case IEEE80211_FC0_TYPE_DATA: 1334b8e788a5SAdrian Chadd atype = HAL_PKT_TYPE_NORMAL; /* default */ 1335b8e788a5SAdrian Chadd /* 1336b8e788a5SAdrian Chadd * Data frames: multicast frames go out at a fixed rate, 1337b8e788a5SAdrian Chadd * EAPOL frames use the mgmt frame rate; otherwise consult 1338b8e788a5SAdrian Chadd * the rate control module for the rate to use. 1339b8e788a5SAdrian Chadd */ 1340b8e788a5SAdrian Chadd if (ismcast) { 1341b8e788a5SAdrian Chadd rix = an->an_mcastrix; 1342b8e788a5SAdrian Chadd txrate = rt->info[rix].rateCode; 1343b8e788a5SAdrian Chadd if (shortPreamble) 1344b8e788a5SAdrian Chadd txrate |= rt->info[rix].shortPreamble; 1345b8e788a5SAdrian Chadd try0 = 1; 1346b8e788a5SAdrian Chadd } else if (m0->m_flags & M_EAPOL) { 1347b8e788a5SAdrian Chadd /* XXX? maybe always use long preamble? */ 1348b8e788a5SAdrian Chadd rix = an->an_mgmtrix; 1349b8e788a5SAdrian Chadd txrate = rt->info[rix].rateCode; 1350b8e788a5SAdrian Chadd if (shortPreamble) 1351b8e788a5SAdrian Chadd txrate |= rt->info[rix].shortPreamble; 1352b8e788a5SAdrian Chadd try0 = ATH_TXMAXTRY; /* XXX?too many? */ 1353b8e788a5SAdrian Chadd } else { 1354eb6f0de0SAdrian Chadd /* 1355eb6f0de0SAdrian Chadd * Do rate lookup on each TX, rather than using 1356eb6f0de0SAdrian Chadd * the hard-coded TX information decided here. 1357eb6f0de0SAdrian Chadd */ 1358b8e788a5SAdrian Chadd ismrr = 1; 1359eb6f0de0SAdrian Chadd bf->bf_state.bfs_doratelookup = 1; 1360b8e788a5SAdrian Chadd } 1361b8e788a5SAdrian Chadd if (cap->cap_wmeParams[pri].wmep_noackPolicy) 1362b8e788a5SAdrian Chadd flags |= HAL_TXDESC_NOACK; 1363b8e788a5SAdrian Chadd break; 1364b8e788a5SAdrian Chadd default: 1365b8e788a5SAdrian Chadd if_printf(ifp, "bogus frame type 0x%x (%s)\n", 1366b8e788a5SAdrian Chadd wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1367b8e788a5SAdrian Chadd /* XXX statistic */ 1368b8e788a5SAdrian Chadd ath_freetx(m0); 1369b8e788a5SAdrian Chadd return EIO; 1370b8e788a5SAdrian Chadd } 1371b8e788a5SAdrian Chadd 1372447fd44aSAdrian Chadd /* 1373447fd44aSAdrian Chadd * There are two known scenarios where the frame AC doesn't match 1374447fd44aSAdrian Chadd * what the destination TXQ is. 1375447fd44aSAdrian Chadd * 1376447fd44aSAdrian Chadd * + non-QoS frames (eg management?) that the net80211 stack has 1377447fd44aSAdrian Chadd * assigned a higher AC to, but since it's a non-QoS TID, it's 1378447fd44aSAdrian Chadd * being thrown into TID 16. TID 16 gets the AC_BE queue. 1379447fd44aSAdrian Chadd * It's quite possible that management frames should just be 1380447fd44aSAdrian Chadd * direct dispatched to hardware rather than go via the software 1381447fd44aSAdrian Chadd * queue; that should be investigated in the future. There are 1382447fd44aSAdrian Chadd * some specific scenarios where this doesn't make sense, mostly 1383447fd44aSAdrian Chadd * surrounding ADDBA request/response - hence why that is special 1384447fd44aSAdrian Chadd * cased. 1385447fd44aSAdrian Chadd * 1386447fd44aSAdrian Chadd * + Multicast frames going into the VAP mcast queue. That shows up 1387447fd44aSAdrian Chadd * as "TXQ 11". 1388447fd44aSAdrian Chadd * 1389447fd44aSAdrian Chadd * This driver should eventually support separate TID and TXQ locking, 1390447fd44aSAdrian Chadd * allowing for arbitrary AC frames to appear on arbitrary software 1391447fd44aSAdrian Chadd * queues, being queued to the "correct" hardware queue when needed. 1392447fd44aSAdrian Chadd */ 1393447fd44aSAdrian Chadd #if 0 13946deb7f32SAdrian Chadd if (txq != sc->sc_ac2q[pri]) { 13956deb7f32SAdrian Chadd device_printf(sc->sc_dev, 13966deb7f32SAdrian Chadd "%s: txq=%p (%d), pri=%d, pri txq=%p (%d)\n", 13976deb7f32SAdrian Chadd __func__, 13986deb7f32SAdrian Chadd txq, 13996deb7f32SAdrian Chadd txq->axq_qnum, 14006deb7f32SAdrian Chadd pri, 14016deb7f32SAdrian Chadd sc->sc_ac2q[pri], 14026deb7f32SAdrian Chadd sc->sc_ac2q[pri]->axq_qnum); 14036deb7f32SAdrian Chadd } 1404447fd44aSAdrian Chadd #endif 14056deb7f32SAdrian Chadd 1406b8e788a5SAdrian Chadd /* 1407b8e788a5SAdrian Chadd * Calculate miscellaneous flags. 1408b8e788a5SAdrian Chadd */ 1409b8e788a5SAdrian Chadd if (ismcast) { 1410b8e788a5SAdrian Chadd flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 1411b8e788a5SAdrian Chadd } else if (pktlen > vap->iv_rtsthreshold && 1412b8e788a5SAdrian Chadd (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) { 1413b8e788a5SAdrian Chadd flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 1414b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_rts++; 1415b8e788a5SAdrian Chadd } 1416b8e788a5SAdrian Chadd if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */ 1417b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_noack++; 1418b8e788a5SAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA 1419b8e788a5SAdrian Chadd if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) { 1420b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA, 1421b8e788a5SAdrian Chadd "%s: discard frame, ACK required w/ TDMA\n", __func__); 1422b8e788a5SAdrian Chadd sc->sc_stats.ast_tdma_ack++; 1423b8e788a5SAdrian Chadd ath_freetx(m0); 1424b8e788a5SAdrian Chadd return EIO; 1425b8e788a5SAdrian Chadd } 1426b8e788a5SAdrian Chadd #endif 1427b8e788a5SAdrian Chadd 1428b8e788a5SAdrian Chadd /* 1429eb6f0de0SAdrian Chadd * Determine if a tx interrupt should be generated for 1430eb6f0de0SAdrian Chadd * this descriptor. We take a tx interrupt to reap 1431eb6f0de0SAdrian Chadd * descriptors when the h/w hits an EOL condition or 1432eb6f0de0SAdrian Chadd * when the descriptor is specifically marked to generate 1433eb6f0de0SAdrian Chadd * an interrupt. We periodically mark descriptors in this 1434eb6f0de0SAdrian Chadd * way to insure timely replenishing of the supply needed 1435eb6f0de0SAdrian Chadd * for sending frames. Defering interrupts reduces system 1436eb6f0de0SAdrian Chadd * load and potentially allows more concurrent work to be 1437eb6f0de0SAdrian Chadd * done but if done to aggressively can cause senders to 1438eb6f0de0SAdrian Chadd * backup. 1439eb6f0de0SAdrian Chadd * 1440eb6f0de0SAdrian Chadd * NB: use >= to deal with sc_txintrperiod changing 1441eb6f0de0SAdrian Chadd * dynamically through sysctl. 1442b8e788a5SAdrian Chadd */ 1443eb6f0de0SAdrian Chadd if (flags & HAL_TXDESC_INTREQ) { 1444eb6f0de0SAdrian Chadd txq->axq_intrcnt = 0; 1445eb6f0de0SAdrian Chadd } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 1446eb6f0de0SAdrian Chadd flags |= HAL_TXDESC_INTREQ; 1447eb6f0de0SAdrian Chadd txq->axq_intrcnt = 0; 1448eb6f0de0SAdrian Chadd } 1449e42b5dbaSAdrian Chadd 1450eb6f0de0SAdrian Chadd /* This point forward is actual TX bits */ 1451b8e788a5SAdrian Chadd 1452b8e788a5SAdrian Chadd /* 1453b8e788a5SAdrian Chadd * At this point we are committed to sending the frame 1454b8e788a5SAdrian Chadd * and we don't need to look at m_nextpkt; clear it in 1455b8e788a5SAdrian Chadd * case this frame is part of frag chain. 1456b8e788a5SAdrian Chadd */ 1457b8e788a5SAdrian Chadd m0->m_nextpkt = NULL; 1458b8e788a5SAdrian Chadd 1459b8e788a5SAdrian Chadd if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1460b8e788a5SAdrian Chadd ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len, 1461b8e788a5SAdrian Chadd sc->sc_hwmap[rix].ieeerate, -1); 1462b8e788a5SAdrian Chadd 1463b8e788a5SAdrian Chadd if (ieee80211_radiotap_active_vap(vap)) { 1464b8e788a5SAdrian Chadd u_int64_t tsf = ath_hal_gettsf64(ah); 1465b8e788a5SAdrian Chadd 1466b8e788a5SAdrian Chadd sc->sc_tx_th.wt_tsf = htole64(tsf); 1467b8e788a5SAdrian Chadd sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1468b8e788a5SAdrian Chadd if (iswep) 1469b8e788a5SAdrian Chadd sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1470b8e788a5SAdrian Chadd if (isfrag) 1471b8e788a5SAdrian Chadd sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1472b8e788a5SAdrian Chadd sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1473b8e788a5SAdrian Chadd sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1474b8e788a5SAdrian Chadd sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1475b8e788a5SAdrian Chadd 1476b8e788a5SAdrian Chadd ieee80211_radiotap_tx(vap, m0); 1477b8e788a5SAdrian Chadd } 1478b8e788a5SAdrian Chadd 1479eb6f0de0SAdrian Chadd /* Blank the legacy rate array */ 1480eb6f0de0SAdrian Chadd bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1481c1782ce0SAdrian Chadd 1482b8e788a5SAdrian Chadd /* 1483eb6f0de0SAdrian Chadd * ath_buf_set_rate needs at least one rate/try to setup 1484eb6f0de0SAdrian Chadd * the rate scenario. 1485b8e788a5SAdrian Chadd */ 1486eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].rix = rix; 1487eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].tries = try0; 1488eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].ratecode = txrate; 1489eb6f0de0SAdrian Chadd 1490eb6f0de0SAdrian Chadd /* Store the decided rate index values away */ 1491eb6f0de0SAdrian Chadd bf->bf_state.bfs_pktlen = pktlen; 1492eb6f0de0SAdrian Chadd bf->bf_state.bfs_hdrlen = hdrlen; 1493eb6f0de0SAdrian Chadd bf->bf_state.bfs_atype = atype; 1494eb6f0de0SAdrian Chadd bf->bf_state.bfs_txpower = ni->ni_txpower; 1495eb6f0de0SAdrian Chadd bf->bf_state.bfs_txrate0 = txrate; 1496eb6f0de0SAdrian Chadd bf->bf_state.bfs_try0 = try0; 1497eb6f0de0SAdrian Chadd bf->bf_state.bfs_keyix = keyix; 1498eb6f0de0SAdrian Chadd bf->bf_state.bfs_txantenna = sc->sc_txantenna; 1499875a9451SAdrian Chadd bf->bf_state.bfs_txflags = flags; 1500eb6f0de0SAdrian Chadd bf->bf_state.bfs_shpream = shortPreamble; 1501eb6f0de0SAdrian Chadd 1502eb6f0de0SAdrian Chadd /* XXX this should be done in ath_tx_setrate() */ 1503eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */ 1504eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsrate = 0; /* calculated later */ 1505eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsduration = 0; 1506eb6f0de0SAdrian Chadd bf->bf_state.bfs_ismrr = ismrr; 1507eb6f0de0SAdrian Chadd 1508eb6f0de0SAdrian Chadd return 0; 1509eb6f0de0SAdrian Chadd } 1510eb6f0de0SAdrian Chadd 1511b8e788a5SAdrian Chadd /* 1512eb6f0de0SAdrian Chadd * Direct-dispatch the current frame to the hardware. 1513eb6f0de0SAdrian Chadd * 1514eb6f0de0SAdrian Chadd * This can be called by the net80211 code. 1515eb6f0de0SAdrian Chadd * 1516eb6f0de0SAdrian Chadd * XXX what about locking? Or, push the seqno assign into the 1517eb6f0de0SAdrian Chadd * XXX aggregate scheduler so its serialised? 1518b8e788a5SAdrian Chadd */ 1519eb6f0de0SAdrian Chadd int 1520eb6f0de0SAdrian Chadd ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, 1521eb6f0de0SAdrian Chadd struct ath_buf *bf, struct mbuf *m0) 1522eb6f0de0SAdrian Chadd { 1523eb6f0de0SAdrian Chadd struct ieee80211vap *vap = ni->ni_vap; 1524eb6f0de0SAdrian Chadd struct ath_vap *avp = ATH_VAP(vap); 15259c85ff91SAdrian Chadd int r = 0; 1526eb6f0de0SAdrian Chadd u_int pri; 1527eb6f0de0SAdrian Chadd int tid; 1528eb6f0de0SAdrian Chadd struct ath_txq *txq; 1529eb6f0de0SAdrian Chadd int ismcast; 1530eb6f0de0SAdrian Chadd const struct ieee80211_frame *wh; 1531eb6f0de0SAdrian Chadd int is_ampdu, is_ampdu_tx, is_ampdu_pending; 1532a108d2d6SAdrian Chadd ieee80211_seq seqno; 1533eb6f0de0SAdrian Chadd uint8_t type, subtype; 1534eb6f0de0SAdrian Chadd 1535eb6f0de0SAdrian Chadd /* 1536eb6f0de0SAdrian Chadd * Determine the target hardware queue. 1537eb6f0de0SAdrian Chadd * 1538b43facbfSAdrian Chadd * For multicast frames, the txq gets overridden appropriately 1539b43facbfSAdrian Chadd * depending upon the state of PS. 1540eb6f0de0SAdrian Chadd * 1541eb6f0de0SAdrian Chadd * For any other frame, we do a TID/QoS lookup inside the frame 1542eb6f0de0SAdrian Chadd * to see what the TID should be. If it's a non-QoS frame, the 1543eb6f0de0SAdrian Chadd * AC and TID are overridden. The TID/TXQ code assumes the 1544eb6f0de0SAdrian Chadd * TID is on a predictable hardware TXQ, so we don't support 1545eb6f0de0SAdrian Chadd * having a node TID queued to multiple hardware TXQs. 1546eb6f0de0SAdrian Chadd * This may change in the future but would require some locking 1547eb6f0de0SAdrian Chadd * fudgery. 1548eb6f0de0SAdrian Chadd */ 1549eb6f0de0SAdrian Chadd pri = ath_tx_getac(sc, m0); 1550eb6f0de0SAdrian Chadd tid = ath_tx_gettid(sc, m0); 1551eb6f0de0SAdrian Chadd 1552eb6f0de0SAdrian Chadd txq = sc->sc_ac2q[pri]; 1553eb6f0de0SAdrian Chadd wh = mtod(m0, struct ieee80211_frame *); 1554eb6f0de0SAdrian Chadd ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1555eb6f0de0SAdrian Chadd type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1556eb6f0de0SAdrian Chadd subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 1557eb6f0de0SAdrian Chadd 15589c85ff91SAdrian Chadd /* 15599c85ff91SAdrian Chadd * Enforce how deep the multicast queue can grow. 15609c85ff91SAdrian Chadd * 15619c85ff91SAdrian Chadd * XXX duplicated in ath_raw_xmit(). 15629c85ff91SAdrian Chadd */ 15639c85ff91SAdrian Chadd if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 15649c85ff91SAdrian Chadd ATH_TXQ_LOCK(sc->sc_cabq); 15659c85ff91SAdrian Chadd 1566b09e37a1SAdrian Chadd if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 15679c85ff91SAdrian Chadd sc->sc_stats.ast_tx_mcastq_overflow++; 15689c85ff91SAdrian Chadd r = ENOBUFS; 15699c85ff91SAdrian Chadd } 15709c85ff91SAdrian Chadd 15719c85ff91SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_cabq); 15729c85ff91SAdrian Chadd 15739c85ff91SAdrian Chadd if (r != 0) { 15749c85ff91SAdrian Chadd m_freem(m0); 15759c85ff91SAdrian Chadd return r; 15769c85ff91SAdrian Chadd } 15779c85ff91SAdrian Chadd } 15789c85ff91SAdrian Chadd 1579eb6f0de0SAdrian Chadd /* A-MPDU TX */ 1580eb6f0de0SAdrian Chadd is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid); 1581eb6f0de0SAdrian Chadd is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid); 1582eb6f0de0SAdrian Chadd is_ampdu = is_ampdu_tx | is_ampdu_pending; 1583eb6f0de0SAdrian Chadd 1584a108d2d6SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, ac=%d, is_ampdu=%d\n", 1585a108d2d6SAdrian Chadd __func__, tid, pri, is_ampdu); 1586eb6f0de0SAdrian Chadd 1587*46634305SAdrian Chadd /* Set local packet state, used to queue packets to hardware */ 1588*46634305SAdrian Chadd bf->bf_state.bfs_tid = tid; 1589*46634305SAdrian Chadd bf->bf_state.bfs_txq = txq; 1590*46634305SAdrian Chadd bf->bf_state.bfs_pri = pri; 1591*46634305SAdrian Chadd 1592c5940c30SAdrian Chadd /* 1593b43facbfSAdrian Chadd * When servicing one or more stations in power-save mode 1594b43facbfSAdrian Chadd * (or) if there is some mcast data waiting on the mcast 1595b43facbfSAdrian Chadd * queue (to prevent out of order delivery) multicast frames 1596b43facbfSAdrian Chadd * must be bufferd until after the beacon. 1597b43facbfSAdrian Chadd * 1598b43facbfSAdrian Chadd * TODO: we should lock the mcastq before we check the length. 1599c5940c30SAdrian Chadd */ 1600*46634305SAdrian Chadd if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) { 1601eb6f0de0SAdrian Chadd txq = &avp->av_mcastq; 1602*46634305SAdrian Chadd /* 1603*46634305SAdrian Chadd * Mark the frame as eventually belonging on the CAB 1604*46634305SAdrian Chadd * queue, so the descriptor setup functions will 1605*46634305SAdrian Chadd * correctly initialise the descriptor 'qcuId' field. 1606*46634305SAdrian Chadd */ 1607*46634305SAdrian Chadd bf->bf_state.bfs_txq = sc->sc_cabq; 1608*46634305SAdrian Chadd } 1609eb6f0de0SAdrian Chadd 1610eb6f0de0SAdrian Chadd /* Do the generic frame setup */ 1611eb6f0de0SAdrian Chadd /* XXX should just bzero the bf_state? */ 1612eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw = 0; 1613eb6f0de0SAdrian Chadd 16147561cb5cSAdrian Chadd /* 16157561cb5cSAdrian Chadd * Acquire the TXQ lock early, so both the encap and seqno 16167561cb5cSAdrian Chadd * are allocated together. 1617*46634305SAdrian Chadd * 1618*46634305SAdrian Chadd * XXX should TXQ for CABQ traffic be the multicast queue, 1619*46634305SAdrian Chadd * or the TXQ the given PRI would allocate from? (eg for 1620*46634305SAdrian Chadd * sequence number allocation locking.) 16217561cb5cSAdrian Chadd */ 1622eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(txq); 16237561cb5cSAdrian Chadd 16247561cb5cSAdrian Chadd /* A-MPDU TX? Manually set sequence number */ 16257561cb5cSAdrian Chadd /* 16267561cb5cSAdrian Chadd * Don't do it whilst pending; the net80211 layer still 16277561cb5cSAdrian Chadd * assigns them. 16287561cb5cSAdrian Chadd */ 16297561cb5cSAdrian Chadd if (is_ampdu_tx) { 1630eb6f0de0SAdrian Chadd /* 1631eb6f0de0SAdrian Chadd * Always call; this function will 1632eb6f0de0SAdrian Chadd * handle making sure that null data frames 1633eb6f0de0SAdrian Chadd * don't get a sequence number from the current 1634eb6f0de0SAdrian Chadd * TID and thus mess with the BAW. 1635eb6f0de0SAdrian Chadd */ 1636a108d2d6SAdrian Chadd seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0); 163742f4d061SAdrian Chadd 163842f4d061SAdrian Chadd /* 163942f4d061SAdrian Chadd * Don't add QoS NULL frames to the BAW. 164042f4d061SAdrian Chadd */ 1641a108d2d6SAdrian Chadd if (IEEE80211_QOS_HAS_SEQ(wh) && 1642a108d2d6SAdrian Chadd subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL) { 1643eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw = 1; 1644eb6f0de0SAdrian Chadd } 1645c1782ce0SAdrian Chadd } 1646c1782ce0SAdrian Chadd 1647eb6f0de0SAdrian Chadd /* 1648eb6f0de0SAdrian Chadd * If needed, the sequence number has been assigned. 1649eb6f0de0SAdrian Chadd * Squirrel it away somewhere easy to get to. 1650eb6f0de0SAdrian Chadd */ 1651a108d2d6SAdrian Chadd bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT; 1652b8e788a5SAdrian Chadd 1653eb6f0de0SAdrian Chadd /* Is ampdu pending? fetch the seqno and print it out */ 1654eb6f0de0SAdrian Chadd if (is_ampdu_pending) 1655eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, 1656eb6f0de0SAdrian Chadd "%s: tid %d: ampdu pending, seqno %d\n", 1657eb6f0de0SAdrian Chadd __func__, tid, M_SEQNO_GET(m0)); 1658eb6f0de0SAdrian Chadd 1659eb6f0de0SAdrian Chadd /* This also sets up the DMA map */ 1660b43facbfSAdrian Chadd r = ath_tx_normal_setup(sc, ni, bf, m0, txq); 1661eb6f0de0SAdrian Chadd 1662eb6f0de0SAdrian Chadd if (r != 0) 16637561cb5cSAdrian Chadd goto done; 1664eb6f0de0SAdrian Chadd 1665eb6f0de0SAdrian Chadd /* At this point m0 could have changed! */ 1666eb6f0de0SAdrian Chadd m0 = bf->bf_m; 1667eb6f0de0SAdrian Chadd 1668eb6f0de0SAdrian Chadd #if 1 1669eb6f0de0SAdrian Chadd /* 1670eb6f0de0SAdrian Chadd * If it's a multicast frame, do a direct-dispatch to the 1671eb6f0de0SAdrian Chadd * destination hardware queue. Don't bother software 1672eb6f0de0SAdrian Chadd * queuing it. 1673eb6f0de0SAdrian Chadd */ 1674eb6f0de0SAdrian Chadd /* 1675eb6f0de0SAdrian Chadd * If it's a BAR frame, do a direct dispatch to the 1676eb6f0de0SAdrian Chadd * destination hardware queue. Don't bother software 1677eb6f0de0SAdrian Chadd * queuing it, as the TID will now be paused. 1678eb6f0de0SAdrian Chadd * Sending a BAR frame can occur from the net80211 txa timer 1679eb6f0de0SAdrian Chadd * (ie, retries) or from the ath txtask (completion call.) 1680eb6f0de0SAdrian Chadd * It queues directly to hardware because the TID is paused 1681eb6f0de0SAdrian Chadd * at this point (and won't be unpaused until the BAR has 1682eb6f0de0SAdrian Chadd * either been TXed successfully or max retries has been 1683eb6f0de0SAdrian Chadd * reached.) 1684eb6f0de0SAdrian Chadd */ 1685eb6f0de0SAdrian Chadd if (txq == &avp->av_mcastq) { 1686d3a6425bSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, 16870b96ef63SAdrian Chadd "%s: bf=%p: mcastq: TX'ing\n", __func__, bf); 1688eb6f0de0SAdrian Chadd ath_tx_xmit_normal(sc, txq, bf); 1689eb6f0de0SAdrian Chadd } else if (type == IEEE80211_FC0_TYPE_CTL && 1690eb6f0de0SAdrian Chadd subtype == IEEE80211_FC0_SUBTYPE_BAR) { 1691d3a6425bSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, 1692eb6f0de0SAdrian Chadd "%s: BAR: TX'ing direct\n", __func__); 1693eb6f0de0SAdrian Chadd ath_tx_xmit_normal(sc, txq, bf); 1694eb6f0de0SAdrian Chadd } else { 1695eb6f0de0SAdrian Chadd /* add to software queue */ 1696d3a6425bSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, 16970b96ef63SAdrian Chadd "%s: bf=%p: swq: TX'ing\n", __func__, bf); 1698eb6f0de0SAdrian Chadd ath_tx_swq(sc, ni, txq, bf); 1699eb6f0de0SAdrian Chadd } 1700eb6f0de0SAdrian Chadd #else 1701eb6f0de0SAdrian Chadd /* 1702eb6f0de0SAdrian Chadd * For now, since there's no software queue, 1703eb6f0de0SAdrian Chadd * direct-dispatch to the hardware. 1704eb6f0de0SAdrian Chadd */ 1705eb6f0de0SAdrian Chadd ath_tx_xmit_normal(sc, txq, bf); 1706eb6f0de0SAdrian Chadd #endif 17077561cb5cSAdrian Chadd done: 17087561cb5cSAdrian Chadd ATH_TXQ_UNLOCK(txq); 1709eb6f0de0SAdrian Chadd 1710b8e788a5SAdrian Chadd return 0; 1711b8e788a5SAdrian Chadd } 1712b8e788a5SAdrian Chadd 1713b8e788a5SAdrian Chadd static int 1714b8e788a5SAdrian Chadd ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni, 1715b8e788a5SAdrian Chadd struct ath_buf *bf, struct mbuf *m0, 1716b8e788a5SAdrian Chadd const struct ieee80211_bpf_params *params) 1717b8e788a5SAdrian Chadd { 1718b8e788a5SAdrian Chadd struct ifnet *ifp = sc->sc_ifp; 1719b8e788a5SAdrian Chadd struct ieee80211com *ic = ifp->if_l2com; 1720b8e788a5SAdrian Chadd struct ath_hal *ah = sc->sc_ah; 1721b8e788a5SAdrian Chadd struct ieee80211vap *vap = ni->ni_vap; 1722b8e788a5SAdrian Chadd int error, ismcast, ismrr; 1723b8e788a5SAdrian Chadd int keyix, hdrlen, pktlen, try0, txantenna; 1724eb6f0de0SAdrian Chadd u_int8_t rix, txrate; 1725b8e788a5SAdrian Chadd struct ieee80211_frame *wh; 1726eb6f0de0SAdrian Chadd u_int flags; 1727b8e788a5SAdrian Chadd HAL_PKT_TYPE atype; 1728b8e788a5SAdrian Chadd const HAL_RATE_TABLE *rt; 1729b8e788a5SAdrian Chadd struct ath_desc *ds; 1730b8e788a5SAdrian Chadd u_int pri; 1731eb6f0de0SAdrian Chadd int o_tid = -1; 1732eb6f0de0SAdrian Chadd int do_override; 1733b8e788a5SAdrian Chadd 1734b8e788a5SAdrian Chadd wh = mtod(m0, struct ieee80211_frame *); 1735b8e788a5SAdrian Chadd ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1736b8e788a5SAdrian Chadd hdrlen = ieee80211_anyhdrsize(wh); 1737b8e788a5SAdrian Chadd /* 1738b8e788a5SAdrian Chadd * Packet length must not include any 1739b8e788a5SAdrian Chadd * pad bytes; deduct them here. 1740b8e788a5SAdrian Chadd */ 1741b8e788a5SAdrian Chadd /* XXX honor IEEE80211_BPF_DATAPAD */ 1742b8e788a5SAdrian Chadd pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN; 1743b8e788a5SAdrian Chadd 1744eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n", 1745eb6f0de0SAdrian Chadd __func__, ismcast); 1746eb6f0de0SAdrian Chadd 17477561cb5cSAdrian Chadd pri = params->ibp_pri & 3; 17487561cb5cSAdrian Chadd /* Override pri if the frame isn't a QoS one */ 17497561cb5cSAdrian Chadd if (! IEEE80211_QOS_HAS_SEQ(wh)) 17507561cb5cSAdrian Chadd pri = ath_tx_getac(sc, m0); 17517561cb5cSAdrian Chadd 17527561cb5cSAdrian Chadd /* XXX If it's an ADDBA, override the correct queue */ 17537561cb5cSAdrian Chadd do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid); 17547561cb5cSAdrian Chadd 17557561cb5cSAdrian Chadd /* Map ADDBA to the correct priority */ 17567561cb5cSAdrian Chadd if (do_override) { 17577561cb5cSAdrian Chadd #if 0 17587561cb5cSAdrian Chadd device_printf(sc->sc_dev, 17597561cb5cSAdrian Chadd "%s: overriding tid %d pri %d -> %d\n", 17607561cb5cSAdrian Chadd __func__, o_tid, pri, TID_TO_WME_AC(o_tid)); 17617561cb5cSAdrian Chadd #endif 17627561cb5cSAdrian Chadd pri = TID_TO_WME_AC(o_tid); 17637561cb5cSAdrian Chadd } 17647561cb5cSAdrian Chadd 17657561cb5cSAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[pri]); 17667561cb5cSAdrian Chadd 176781a82688SAdrian Chadd /* Handle encryption twiddling if needed */ 1768eb6f0de0SAdrian Chadd if (! ath_tx_tag_crypto(sc, ni, 1769eb6f0de0SAdrian Chadd m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0, 1770eb6f0de0SAdrian Chadd &hdrlen, &pktlen, &keyix)) { 1771b8e788a5SAdrian Chadd ath_freetx(m0); 1772b8e788a5SAdrian Chadd return EIO; 1773b8e788a5SAdrian Chadd } 1774b8e788a5SAdrian Chadd /* packet header may have moved, reset our local pointer */ 1775b8e788a5SAdrian Chadd wh = mtod(m0, struct ieee80211_frame *); 1776b8e788a5SAdrian Chadd 1777eb6f0de0SAdrian Chadd /* Do the generic frame setup */ 1778eb6f0de0SAdrian Chadd /* XXX should just bzero the bf_state? */ 1779eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw = 0; 1780eb6f0de0SAdrian Chadd 1781b8e788a5SAdrian Chadd error = ath_tx_dmasetup(sc, bf, m0); 1782b8e788a5SAdrian Chadd if (error != 0) 1783b8e788a5SAdrian Chadd return error; 1784b8e788a5SAdrian Chadd m0 = bf->bf_m; /* NB: may have changed */ 1785b8e788a5SAdrian Chadd wh = mtod(m0, struct ieee80211_frame *); 1786b8e788a5SAdrian Chadd bf->bf_node = ni; /* NB: held reference */ 1787b8e788a5SAdrian Chadd 1788b8e788a5SAdrian Chadd flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 1789b8e788a5SAdrian Chadd flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 1790b8e788a5SAdrian Chadd if (params->ibp_flags & IEEE80211_BPF_RTS) 1791b8e788a5SAdrian Chadd flags |= HAL_TXDESC_RTSENA; 1792eb6f0de0SAdrian Chadd else if (params->ibp_flags & IEEE80211_BPF_CTS) { 1793eb6f0de0SAdrian Chadd /* XXX assume 11g/11n protection? */ 1794eb6f0de0SAdrian Chadd bf->bf_state.bfs_doprot = 1; 1795b8e788a5SAdrian Chadd flags |= HAL_TXDESC_CTSENA; 1796eb6f0de0SAdrian Chadd } 1797b8e788a5SAdrian Chadd /* XXX leave ismcast to injector? */ 1798b8e788a5SAdrian Chadd if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast) 1799b8e788a5SAdrian Chadd flags |= HAL_TXDESC_NOACK; 1800b8e788a5SAdrian Chadd 1801b8e788a5SAdrian Chadd rt = sc->sc_currates; 1802b8e788a5SAdrian Chadd KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 1803b8e788a5SAdrian Chadd rix = ath_tx_findrix(sc, params->ibp_rate0); 1804b8e788a5SAdrian Chadd txrate = rt->info[rix].rateCode; 1805b8e788a5SAdrian Chadd if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 1806b8e788a5SAdrian Chadd txrate |= rt->info[rix].shortPreamble; 1807b8e788a5SAdrian Chadd sc->sc_txrix = rix; 1808b8e788a5SAdrian Chadd try0 = params->ibp_try0; 1809b8e788a5SAdrian Chadd ismrr = (params->ibp_try1 != 0); 1810b8e788a5SAdrian Chadd txantenna = params->ibp_pri >> 2; 1811b8e788a5SAdrian Chadd if (txantenna == 0) /* XXX? */ 1812b8e788a5SAdrian Chadd txantenna = sc->sc_txantenna; 181379f02dbfSAdrian Chadd 181479f02dbfSAdrian Chadd /* 1815eb6f0de0SAdrian Chadd * Since ctsrate is fixed, store it away for later 1816eb6f0de0SAdrian Chadd * use when the descriptor fields are being set. 181779f02dbfSAdrian Chadd */ 1818eb6f0de0SAdrian Chadd if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) 1819eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate; 182079f02dbfSAdrian Chadd 1821b8e788a5SAdrian Chadd /* 1822b8e788a5SAdrian Chadd * NB: we mark all packets as type PSPOLL so the h/w won't 1823b8e788a5SAdrian Chadd * set the sequence number, duration, etc. 1824b8e788a5SAdrian Chadd */ 1825b8e788a5SAdrian Chadd atype = HAL_PKT_TYPE_PSPOLL; 1826b8e788a5SAdrian Chadd 1827b8e788a5SAdrian Chadd if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 1828b8e788a5SAdrian Chadd ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len, 1829b8e788a5SAdrian Chadd sc->sc_hwmap[rix].ieeerate, -1); 1830b8e788a5SAdrian Chadd 1831b8e788a5SAdrian Chadd if (ieee80211_radiotap_active_vap(vap)) { 1832b8e788a5SAdrian Chadd u_int64_t tsf = ath_hal_gettsf64(ah); 1833b8e788a5SAdrian Chadd 1834b8e788a5SAdrian Chadd sc->sc_tx_th.wt_tsf = htole64(tsf); 1835b8e788a5SAdrian Chadd sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags; 1836b8e788a5SAdrian Chadd if (wh->i_fc[1] & IEEE80211_FC1_WEP) 1837b8e788a5SAdrian Chadd sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 1838b8e788a5SAdrian Chadd if (m0->m_flags & M_FRAG) 1839b8e788a5SAdrian Chadd sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1840b8e788a5SAdrian Chadd sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate; 1841b8e788a5SAdrian Chadd sc->sc_tx_th.wt_txpower = ni->ni_txpower; 1842b8e788a5SAdrian Chadd sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 1843b8e788a5SAdrian Chadd 1844b8e788a5SAdrian Chadd ieee80211_radiotap_tx(vap, m0); 1845b8e788a5SAdrian Chadd } 1846b8e788a5SAdrian Chadd 1847b8e788a5SAdrian Chadd /* 1848b8e788a5SAdrian Chadd * Formulate first tx descriptor with tx controls. 1849b8e788a5SAdrian Chadd */ 1850b8e788a5SAdrian Chadd ds = bf->bf_desc; 1851b8e788a5SAdrian Chadd /* XXX check return value? */ 1852eb6f0de0SAdrian Chadd 1853eb6f0de0SAdrian Chadd /* Store the decided rate index values away */ 1854eb6f0de0SAdrian Chadd bf->bf_state.bfs_pktlen = pktlen; 1855eb6f0de0SAdrian Chadd bf->bf_state.bfs_hdrlen = hdrlen; 1856eb6f0de0SAdrian Chadd bf->bf_state.bfs_atype = atype; 1857eb6f0de0SAdrian Chadd bf->bf_state.bfs_txpower = params->ibp_power; 1858eb6f0de0SAdrian Chadd bf->bf_state.bfs_txrate0 = txrate; 1859eb6f0de0SAdrian Chadd bf->bf_state.bfs_try0 = try0; 1860eb6f0de0SAdrian Chadd bf->bf_state.bfs_keyix = keyix; 1861eb6f0de0SAdrian Chadd bf->bf_state.bfs_txantenna = txantenna; 1862875a9451SAdrian Chadd bf->bf_state.bfs_txflags = flags; 1863eb6f0de0SAdrian Chadd bf->bf_state.bfs_shpream = 1864eb6f0de0SAdrian Chadd !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE); 1865b8e788a5SAdrian Chadd 1866*46634305SAdrian Chadd /* Set local packet state, used to queue packets to hardware */ 1867*46634305SAdrian Chadd bf->bf_state.bfs_tid = WME_AC_TO_TID(pri); 1868*46634305SAdrian Chadd bf->bf_state.bfs_txq = sc->sc_ac2q[pri]; 1869*46634305SAdrian Chadd bf->bf_state.bfs_pri = pri; 1870*46634305SAdrian Chadd 1871eb6f0de0SAdrian Chadd /* XXX this should be done in ath_tx_setrate() */ 1872eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsrate = 0; 1873eb6f0de0SAdrian Chadd bf->bf_state.bfs_ctsduration = 0; 1874eb6f0de0SAdrian Chadd bf->bf_state.bfs_ismrr = ismrr; 1875eb6f0de0SAdrian Chadd 1876eb6f0de0SAdrian Chadd /* Blank the legacy rate array */ 1877eb6f0de0SAdrian Chadd bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc)); 1878eb6f0de0SAdrian Chadd 1879eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].rix = 1880eb6f0de0SAdrian Chadd ath_tx_findrix(sc, params->ibp_rate0); 1881eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].tries = try0; 1882eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[0].ratecode = txrate; 1883c1782ce0SAdrian Chadd 1884c1782ce0SAdrian Chadd if (ismrr) { 1885eb6f0de0SAdrian Chadd int rix; 1886c1782ce0SAdrian Chadd 1887b8e788a5SAdrian Chadd rix = ath_tx_findrix(sc, params->ibp_rate1); 1888eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[1].rix = rix; 1889eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[1].tries = params->ibp_try1; 1890c1782ce0SAdrian Chadd 1891eb6f0de0SAdrian Chadd rix = ath_tx_findrix(sc, params->ibp_rate2); 1892eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[2].rix = rix; 1893eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[2].tries = params->ibp_try2; 1894eb6f0de0SAdrian Chadd 1895eb6f0de0SAdrian Chadd rix = ath_tx_findrix(sc, params->ibp_rate3); 1896eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[3].rix = rix; 1897eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[3].tries = params->ibp_try3; 1898c1782ce0SAdrian Chadd } 1899eb6f0de0SAdrian Chadd /* 1900eb6f0de0SAdrian Chadd * All the required rate control decisions have been made; 1901eb6f0de0SAdrian Chadd * fill in the rc flags. 1902eb6f0de0SAdrian Chadd */ 1903eb6f0de0SAdrian Chadd ath_tx_rate_fill_rcflags(sc, bf); 1904b8e788a5SAdrian Chadd 1905b8e788a5SAdrian Chadd /* NB: no buffered multicast in power save support */ 1906eb6f0de0SAdrian Chadd 1907eb6f0de0SAdrian Chadd /* 1908eb6f0de0SAdrian Chadd * If we're overiding the ADDBA destination, dump directly 1909eb6f0de0SAdrian Chadd * into the hardware queue, right after any pending 1910eb6f0de0SAdrian Chadd * frames to that node are. 1911eb6f0de0SAdrian Chadd */ 1912eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n", 1913eb6f0de0SAdrian Chadd __func__, do_override); 1914eb6f0de0SAdrian Chadd 1915eb6f0de0SAdrian Chadd if (do_override) { 1916eb6f0de0SAdrian Chadd ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf); 1917eb6f0de0SAdrian Chadd } else { 1918eb6f0de0SAdrian Chadd /* Queue to software queue */ 1919eb6f0de0SAdrian Chadd ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf); 1920eb6f0de0SAdrian Chadd } 19217561cb5cSAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[pri]); 1922eb6f0de0SAdrian Chadd 1923b8e788a5SAdrian Chadd return 0; 1924b8e788a5SAdrian Chadd } 1925b8e788a5SAdrian Chadd 1926eb6f0de0SAdrian Chadd /* 1927eb6f0de0SAdrian Chadd * Send a raw frame. 1928eb6f0de0SAdrian Chadd * 1929eb6f0de0SAdrian Chadd * This can be called by net80211. 1930eb6f0de0SAdrian Chadd */ 1931b8e788a5SAdrian Chadd int 1932b8e788a5SAdrian Chadd ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1933b8e788a5SAdrian Chadd const struct ieee80211_bpf_params *params) 1934b8e788a5SAdrian Chadd { 1935b8e788a5SAdrian Chadd struct ieee80211com *ic = ni->ni_ic; 1936b8e788a5SAdrian Chadd struct ifnet *ifp = ic->ic_ifp; 1937b8e788a5SAdrian Chadd struct ath_softc *sc = ifp->if_softc; 1938b8e788a5SAdrian Chadd struct ath_buf *bf; 19399c85ff91SAdrian Chadd struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *); 19409c85ff91SAdrian Chadd int error = 0; 1941b8e788a5SAdrian Chadd 1942ef27340cSAdrian Chadd ATH_PCU_LOCK(sc); 1943ef27340cSAdrian Chadd if (sc->sc_inreset_cnt > 0) { 1944ef27340cSAdrian Chadd device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n", 1945ef27340cSAdrian Chadd __func__); 1946ef27340cSAdrian Chadd error = EIO; 1947ef27340cSAdrian Chadd ATH_PCU_UNLOCK(sc); 1948ef27340cSAdrian Chadd goto bad0; 1949ef27340cSAdrian Chadd } 1950ef27340cSAdrian Chadd sc->sc_txstart_cnt++; 1951ef27340cSAdrian Chadd ATH_PCU_UNLOCK(sc); 1952ef27340cSAdrian Chadd 1953b8e788a5SAdrian Chadd if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) { 1954b8e788a5SAdrian Chadd DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__, 1955b8e788a5SAdrian Chadd (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ? 1956b8e788a5SAdrian Chadd "!running" : "invalid"); 1957b8e788a5SAdrian Chadd m_freem(m); 1958b8e788a5SAdrian Chadd error = ENETDOWN; 1959b8e788a5SAdrian Chadd goto bad; 1960b8e788a5SAdrian Chadd } 19619c85ff91SAdrian Chadd 19629c85ff91SAdrian Chadd /* 19639c85ff91SAdrian Chadd * Enforce how deep the multicast queue can grow. 19649c85ff91SAdrian Chadd * 19659c85ff91SAdrian Chadd * XXX duplicated in ath_tx_start(). 19669c85ff91SAdrian Chadd */ 19679c85ff91SAdrian Chadd if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 19689c85ff91SAdrian Chadd ATH_TXQ_LOCK(sc->sc_cabq); 19699c85ff91SAdrian Chadd 1970b09e37a1SAdrian Chadd if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) { 19719c85ff91SAdrian Chadd sc->sc_stats.ast_tx_mcastq_overflow++; 19729c85ff91SAdrian Chadd error = ENOBUFS; 19739c85ff91SAdrian Chadd } 19749c85ff91SAdrian Chadd 19759c85ff91SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_cabq); 19769c85ff91SAdrian Chadd 19779c85ff91SAdrian Chadd if (error != 0) { 19789c85ff91SAdrian Chadd m_freem(m); 19799c85ff91SAdrian Chadd goto bad; 19809c85ff91SAdrian Chadd } 19819c85ff91SAdrian Chadd } 19829c85ff91SAdrian Chadd 1983b8e788a5SAdrian Chadd /* 1984b8e788a5SAdrian Chadd * Grab a TX buffer and associated resources. 1985b8e788a5SAdrian Chadd */ 1986af33d486SAdrian Chadd bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT); 1987b8e788a5SAdrian Chadd if (bf == NULL) { 1988b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_nobuf++; 1989b8e788a5SAdrian Chadd m_freem(m); 1990b8e788a5SAdrian Chadd error = ENOBUFS; 1991b8e788a5SAdrian Chadd goto bad; 1992b8e788a5SAdrian Chadd } 1993b8e788a5SAdrian Chadd 1994b8e788a5SAdrian Chadd if (params == NULL) { 1995b8e788a5SAdrian Chadd /* 1996b8e788a5SAdrian Chadd * Legacy path; interpret frame contents to decide 1997b8e788a5SAdrian Chadd * precisely how to send the frame. 1998b8e788a5SAdrian Chadd */ 1999b8e788a5SAdrian Chadd if (ath_tx_start(sc, ni, bf, m)) { 2000b8e788a5SAdrian Chadd error = EIO; /* XXX */ 2001b8e788a5SAdrian Chadd goto bad2; 2002b8e788a5SAdrian Chadd } 2003b8e788a5SAdrian Chadd } else { 2004b8e788a5SAdrian Chadd /* 2005b8e788a5SAdrian Chadd * Caller supplied explicit parameters to use in 2006b8e788a5SAdrian Chadd * sending the frame. 2007b8e788a5SAdrian Chadd */ 2008b8e788a5SAdrian Chadd if (ath_tx_raw_start(sc, ni, bf, m, params)) { 2009b8e788a5SAdrian Chadd error = EIO; /* XXX */ 2010b8e788a5SAdrian Chadd goto bad2; 2011b8e788a5SAdrian Chadd } 2012b8e788a5SAdrian Chadd } 2013b8e788a5SAdrian Chadd sc->sc_wd_timer = 5; 2014b8e788a5SAdrian Chadd ifp->if_opackets++; 2015b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_raw++; 2016b8e788a5SAdrian Chadd 2017ef27340cSAdrian Chadd ATH_PCU_LOCK(sc); 2018ef27340cSAdrian Chadd sc->sc_txstart_cnt--; 2019ef27340cSAdrian Chadd ATH_PCU_UNLOCK(sc); 2020ef27340cSAdrian Chadd 2021b8e788a5SAdrian Chadd return 0; 2022b8e788a5SAdrian Chadd bad2: 2023b8e788a5SAdrian Chadd ATH_TXBUF_LOCK(sc); 2024e1a50456SAdrian Chadd ath_returnbuf_head(sc, bf); 2025b8e788a5SAdrian Chadd ATH_TXBUF_UNLOCK(sc); 2026b8e788a5SAdrian Chadd bad: 2027ef27340cSAdrian Chadd ATH_PCU_LOCK(sc); 2028ef27340cSAdrian Chadd sc->sc_txstart_cnt--; 2029ef27340cSAdrian Chadd ATH_PCU_UNLOCK(sc); 2030ef27340cSAdrian Chadd bad0: 2031b8e788a5SAdrian Chadd ifp->if_oerrors++; 2032b8e788a5SAdrian Chadd sc->sc_stats.ast_tx_raw_fail++; 2033b8e788a5SAdrian Chadd ieee80211_free_node(ni); 2034ef27340cSAdrian Chadd 2035b8e788a5SAdrian Chadd return error; 2036b8e788a5SAdrian Chadd } 2037eb6f0de0SAdrian Chadd 2038eb6f0de0SAdrian Chadd /* Some helper functions */ 2039eb6f0de0SAdrian Chadd 2040eb6f0de0SAdrian Chadd /* 2041eb6f0de0SAdrian Chadd * ADDBA (and potentially others) need to be placed in the same 2042eb6f0de0SAdrian Chadd * hardware queue as the TID/node it's relating to. This is so 2043eb6f0de0SAdrian Chadd * it goes out after any pending non-aggregate frames to the 2044eb6f0de0SAdrian Chadd * same node/TID. 2045eb6f0de0SAdrian Chadd * 2046eb6f0de0SAdrian Chadd * If this isn't done, the ADDBA can go out before the frames 2047eb6f0de0SAdrian Chadd * queued in hardware. Even though these frames have a sequence 2048eb6f0de0SAdrian Chadd * number -earlier- than the ADDBA can be transmitted (but 2049eb6f0de0SAdrian Chadd * no frames whose sequence numbers are after the ADDBA should 2050eb6f0de0SAdrian Chadd * be!) they'll arrive after the ADDBA - and the receiving end 2051eb6f0de0SAdrian Chadd * will simply drop them as being out of the BAW. 2052eb6f0de0SAdrian Chadd * 2053eb6f0de0SAdrian Chadd * The frames can't be appended to the TID software queue - it'll 2054eb6f0de0SAdrian Chadd * never be sent out. So these frames have to be directly 2055eb6f0de0SAdrian Chadd * dispatched to the hardware, rather than queued in software. 2056eb6f0de0SAdrian Chadd * So if this function returns true, the TXQ has to be 2057eb6f0de0SAdrian Chadd * overridden and it has to be directly dispatched. 2058eb6f0de0SAdrian Chadd * 2059eb6f0de0SAdrian Chadd * It's a dirty hack, but someone's gotta do it. 2060eb6f0de0SAdrian Chadd */ 2061eb6f0de0SAdrian Chadd 2062eb6f0de0SAdrian Chadd /* 2063eb6f0de0SAdrian Chadd * XXX doesn't belong here! 2064eb6f0de0SAdrian Chadd */ 2065eb6f0de0SAdrian Chadd static int 2066eb6f0de0SAdrian Chadd ieee80211_is_action(struct ieee80211_frame *wh) 2067eb6f0de0SAdrian Chadd { 2068eb6f0de0SAdrian Chadd /* Type: Management frame? */ 2069eb6f0de0SAdrian Chadd if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != 2070eb6f0de0SAdrian Chadd IEEE80211_FC0_TYPE_MGT) 2071eb6f0de0SAdrian Chadd return 0; 2072eb6f0de0SAdrian Chadd 2073eb6f0de0SAdrian Chadd /* Subtype: Action frame? */ 2074eb6f0de0SAdrian Chadd if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) != 2075eb6f0de0SAdrian Chadd IEEE80211_FC0_SUBTYPE_ACTION) 2076eb6f0de0SAdrian Chadd return 0; 2077eb6f0de0SAdrian Chadd 2078eb6f0de0SAdrian Chadd return 1; 2079eb6f0de0SAdrian Chadd } 2080eb6f0de0SAdrian Chadd 2081eb6f0de0SAdrian Chadd #define MS(_v, _f) (((_v) & _f) >> _f##_S) 2082eb6f0de0SAdrian Chadd /* 2083eb6f0de0SAdrian Chadd * Return an alternate TID for ADDBA request frames. 2084eb6f0de0SAdrian Chadd * 2085eb6f0de0SAdrian Chadd * Yes, this likely should be done in the net80211 layer. 2086eb6f0de0SAdrian Chadd */ 2087eb6f0de0SAdrian Chadd static int 2088eb6f0de0SAdrian Chadd ath_tx_action_frame_override_queue(struct ath_softc *sc, 2089eb6f0de0SAdrian Chadd struct ieee80211_node *ni, 2090eb6f0de0SAdrian Chadd struct mbuf *m0, int *tid) 2091eb6f0de0SAdrian Chadd { 2092eb6f0de0SAdrian Chadd struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 2093eb6f0de0SAdrian Chadd struct ieee80211_action_ba_addbarequest *ia; 2094eb6f0de0SAdrian Chadd uint8_t *frm; 2095eb6f0de0SAdrian Chadd uint16_t baparamset; 2096eb6f0de0SAdrian Chadd 2097eb6f0de0SAdrian Chadd /* Not action frame? Bail */ 2098eb6f0de0SAdrian Chadd if (! ieee80211_is_action(wh)) 2099eb6f0de0SAdrian Chadd return 0; 2100eb6f0de0SAdrian Chadd 2101eb6f0de0SAdrian Chadd /* XXX Not needed for frames we send? */ 2102eb6f0de0SAdrian Chadd #if 0 2103eb6f0de0SAdrian Chadd /* Correct length? */ 2104eb6f0de0SAdrian Chadd if (! ieee80211_parse_action(ni, m)) 2105eb6f0de0SAdrian Chadd return 0; 2106eb6f0de0SAdrian Chadd #endif 2107eb6f0de0SAdrian Chadd 2108eb6f0de0SAdrian Chadd /* Extract out action frame */ 2109eb6f0de0SAdrian Chadd frm = (u_int8_t *)&wh[1]; 2110eb6f0de0SAdrian Chadd ia = (struct ieee80211_action_ba_addbarequest *) frm; 2111eb6f0de0SAdrian Chadd 2112eb6f0de0SAdrian Chadd /* Not ADDBA? Bail */ 2113eb6f0de0SAdrian Chadd if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA) 2114eb6f0de0SAdrian Chadd return 0; 2115eb6f0de0SAdrian Chadd if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST) 2116eb6f0de0SAdrian Chadd return 0; 2117eb6f0de0SAdrian Chadd 2118eb6f0de0SAdrian Chadd /* Extract TID, return it */ 2119eb6f0de0SAdrian Chadd baparamset = le16toh(ia->rq_baparamset); 2120eb6f0de0SAdrian Chadd *tid = (int) MS(baparamset, IEEE80211_BAPS_TID); 2121eb6f0de0SAdrian Chadd 2122eb6f0de0SAdrian Chadd return 1; 2123eb6f0de0SAdrian Chadd } 2124eb6f0de0SAdrian Chadd #undef MS 2125eb6f0de0SAdrian Chadd 2126eb6f0de0SAdrian Chadd /* Per-node software queue operations */ 2127eb6f0de0SAdrian Chadd 2128eb6f0de0SAdrian Chadd /* 2129eb6f0de0SAdrian Chadd * Add the current packet to the given BAW. 2130eb6f0de0SAdrian Chadd * It is assumed that the current packet 2131eb6f0de0SAdrian Chadd * 2132eb6f0de0SAdrian Chadd * + fits inside the BAW; 2133eb6f0de0SAdrian Chadd * + already has had a sequence number allocated. 2134eb6f0de0SAdrian Chadd * 2135eb6f0de0SAdrian Chadd * Since the BAW status may be modified by both the ath task and 2136eb6f0de0SAdrian Chadd * the net80211/ifnet contexts, the TID must be locked. 2137eb6f0de0SAdrian Chadd */ 2138eb6f0de0SAdrian Chadd void 2139eb6f0de0SAdrian Chadd ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an, 2140eb6f0de0SAdrian Chadd struct ath_tid *tid, struct ath_buf *bf) 2141eb6f0de0SAdrian Chadd { 2142eb6f0de0SAdrian Chadd int index, cindex; 2143eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 2144eb6f0de0SAdrian Chadd 2145eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2146c2ac9655SAdrian Chadd ATH_TID_LOCK_ASSERT(sc, tid); 2147eb6f0de0SAdrian Chadd 2148eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_isretried) 2149eb6f0de0SAdrian Chadd return; 2150eb6f0de0SAdrian Chadd 2151c7c07341SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid->tid); 2152c7c07341SAdrian Chadd 21537561cb5cSAdrian Chadd if (! bf->bf_state.bfs_dobaw) { 21547561cb5cSAdrian Chadd device_printf(sc->sc_dev, 21557561cb5cSAdrian Chadd "%s: dobaw=0, seqno=%d, window %d:%d\n", 21567561cb5cSAdrian Chadd __func__, 21577561cb5cSAdrian Chadd SEQNO(bf->bf_state.bfs_seqno), 21587561cb5cSAdrian Chadd tap->txa_start, 21597561cb5cSAdrian Chadd tap->txa_wnd); 21607561cb5cSAdrian Chadd } 21617561cb5cSAdrian Chadd 2162eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_addedbaw) 2163eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 2164a108d2d6SAdrian Chadd "%s: re-added? tid=%d, seqno %d; window %d:%d; " 2165d4365d16SAdrian Chadd "baw head=%d tail=%d\n", 2166a108d2d6SAdrian Chadd __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2167d4365d16SAdrian Chadd tap->txa_start, tap->txa_wnd, tid->baw_head, 2168d4365d16SAdrian Chadd tid->baw_tail); 2169eb6f0de0SAdrian Chadd 2170eb6f0de0SAdrian Chadd /* 21717561cb5cSAdrian Chadd * Verify that the given sequence number is not outside of the 21727561cb5cSAdrian Chadd * BAW. Complain loudly if that's the case. 21737561cb5cSAdrian Chadd */ 21747561cb5cSAdrian Chadd if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 21757561cb5cSAdrian Chadd SEQNO(bf->bf_state.bfs_seqno))) { 21767561cb5cSAdrian Chadd device_printf(sc->sc_dev, 21777561cb5cSAdrian Chadd "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; " 21787561cb5cSAdrian Chadd "baw head=%d tail=%d\n", 21797561cb5cSAdrian Chadd __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 21807561cb5cSAdrian Chadd tap->txa_start, tap->txa_wnd, tid->baw_head, 21817561cb5cSAdrian Chadd tid->baw_tail); 21827561cb5cSAdrian Chadd } 21837561cb5cSAdrian Chadd 21847561cb5cSAdrian Chadd /* 2185eb6f0de0SAdrian Chadd * ni->ni_txseqs[] is the currently allocated seqno. 2186eb6f0de0SAdrian Chadd * the txa state contains the current baw start. 2187eb6f0de0SAdrian Chadd */ 2188eb6f0de0SAdrian Chadd index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno)); 2189eb6f0de0SAdrian Chadd cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2190eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2191a108d2d6SAdrian Chadd "%s: tid=%d, seqno %d; window %d:%d; index=%d cindex=%d " 2192d4365d16SAdrian Chadd "baw head=%d tail=%d\n", 2193a108d2d6SAdrian Chadd __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno), 2194d4365d16SAdrian Chadd tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head, 2195d4365d16SAdrian Chadd tid->baw_tail); 2196eb6f0de0SAdrian Chadd 2197eb6f0de0SAdrian Chadd 2198eb6f0de0SAdrian Chadd #if 0 2199eb6f0de0SAdrian Chadd assert(tid->tx_buf[cindex] == NULL); 2200eb6f0de0SAdrian Chadd #endif 2201eb6f0de0SAdrian Chadd if (tid->tx_buf[cindex] != NULL) { 2202eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 2203eb6f0de0SAdrian Chadd "%s: ba packet dup (index=%d, cindex=%d, " 2204eb6f0de0SAdrian Chadd "head=%d, tail=%d)\n", 2205eb6f0de0SAdrian Chadd __func__, index, cindex, tid->baw_head, tid->baw_tail); 2206eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 2207eb6f0de0SAdrian Chadd "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n", 2208eb6f0de0SAdrian Chadd __func__, 2209eb6f0de0SAdrian Chadd tid->tx_buf[cindex], 2210eb6f0de0SAdrian Chadd SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno), 2211eb6f0de0SAdrian Chadd bf, 2212eb6f0de0SAdrian Chadd SEQNO(bf->bf_state.bfs_seqno) 2213eb6f0de0SAdrian Chadd ); 2214eb6f0de0SAdrian Chadd } 2215eb6f0de0SAdrian Chadd tid->tx_buf[cindex] = bf; 2216eb6f0de0SAdrian Chadd 2217d4365d16SAdrian Chadd if (index >= ((tid->baw_tail - tid->baw_head) & 2218d4365d16SAdrian Chadd (ATH_TID_MAX_BUFS - 1))) { 2219eb6f0de0SAdrian Chadd tid->baw_tail = cindex; 2220eb6f0de0SAdrian Chadd INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 2221eb6f0de0SAdrian Chadd } 2222eb6f0de0SAdrian Chadd } 2223eb6f0de0SAdrian Chadd 2224eb6f0de0SAdrian Chadd /* 222538962489SAdrian Chadd * Flip the BAW buffer entry over from the existing one to the new one. 222638962489SAdrian Chadd * 222738962489SAdrian Chadd * When software retransmitting a (sub-)frame, it is entirely possible that 222838962489SAdrian Chadd * the frame ath_buf is marked as BUSY and can't be immediately reused. 222938962489SAdrian Chadd * In that instance the buffer is cloned and the new buffer is used for 223038962489SAdrian Chadd * retransmit. We thus need to update the ath_buf slot in the BAW buf 223138962489SAdrian Chadd * tracking array to maintain consistency. 223238962489SAdrian Chadd */ 223338962489SAdrian Chadd static void 223438962489SAdrian Chadd ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an, 223538962489SAdrian Chadd struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf) 223638962489SAdrian Chadd { 223738962489SAdrian Chadd int index, cindex; 223838962489SAdrian Chadd struct ieee80211_tx_ampdu *tap; 223938962489SAdrian Chadd int seqno = SEQNO(old_bf->bf_state.bfs_seqno); 224038962489SAdrian Chadd 224138962489SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2242c2ac9655SAdrian Chadd ATH_TID_LOCK_ASSERT(sc, tid); 224338962489SAdrian Chadd 224438962489SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid->tid); 224538962489SAdrian Chadd index = ATH_BA_INDEX(tap->txa_start, seqno); 224638962489SAdrian Chadd cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 224738962489SAdrian Chadd 224838962489SAdrian Chadd /* 224938962489SAdrian Chadd * Just warn for now; if it happens then we should find out 225038962489SAdrian Chadd * about it. It's highly likely the aggregation session will 225138962489SAdrian Chadd * soon hang. 225238962489SAdrian Chadd */ 225338962489SAdrian Chadd if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) { 225438962489SAdrian Chadd device_printf(sc->sc_dev, "%s: retransmitted buffer" 225538962489SAdrian Chadd " has mismatching seqno's, BA session may hang.\n", 225638962489SAdrian Chadd __func__); 225738962489SAdrian Chadd device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n", 225838962489SAdrian Chadd __func__, 225938962489SAdrian Chadd old_bf->bf_state.bfs_seqno, 226038962489SAdrian Chadd new_bf->bf_state.bfs_seqno); 226138962489SAdrian Chadd } 226238962489SAdrian Chadd 226338962489SAdrian Chadd if (tid->tx_buf[cindex] != old_bf) { 226438962489SAdrian Chadd device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; " 226538962489SAdrian Chadd " has m BA session may hang.\n", 226638962489SAdrian Chadd __func__); 226738962489SAdrian Chadd device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n", 226838962489SAdrian Chadd __func__, 226938962489SAdrian Chadd old_bf, new_bf); 227038962489SAdrian Chadd } 227138962489SAdrian Chadd 227238962489SAdrian Chadd tid->tx_buf[cindex] = new_bf; 227338962489SAdrian Chadd } 227438962489SAdrian Chadd 227538962489SAdrian Chadd /* 2276eb6f0de0SAdrian Chadd * seq_start - left edge of BAW 2277eb6f0de0SAdrian Chadd * seq_next - current/next sequence number to allocate 2278eb6f0de0SAdrian Chadd * 2279eb6f0de0SAdrian Chadd * Since the BAW status may be modified by both the ath task and 2280eb6f0de0SAdrian Chadd * the net80211/ifnet contexts, the TID must be locked. 2281eb6f0de0SAdrian Chadd */ 2282eb6f0de0SAdrian Chadd static void 2283eb6f0de0SAdrian Chadd ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an, 2284eb6f0de0SAdrian Chadd struct ath_tid *tid, const struct ath_buf *bf) 2285eb6f0de0SAdrian Chadd { 2286eb6f0de0SAdrian Chadd int index, cindex; 2287eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 2288eb6f0de0SAdrian Chadd int seqno = SEQNO(bf->bf_state.bfs_seqno); 2289eb6f0de0SAdrian Chadd 2290eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 22914b6db404SAdrian Chadd ATH_TID_LOCK_ASSERT(sc, tid); 2292eb6f0de0SAdrian Chadd 2293eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid->tid); 2294eb6f0de0SAdrian Chadd index = ATH_BA_INDEX(tap->txa_start, seqno); 2295eb6f0de0SAdrian Chadd cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 2296eb6f0de0SAdrian Chadd 2297eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2298a108d2d6SAdrian Chadd "%s: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, " 2299d4365d16SAdrian Chadd "baw head=%d, tail=%d\n", 2300a108d2d6SAdrian Chadd __func__, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index, 2301eb6f0de0SAdrian Chadd cindex, tid->baw_head, tid->baw_tail); 2302eb6f0de0SAdrian Chadd 2303eb6f0de0SAdrian Chadd /* 2304eb6f0de0SAdrian Chadd * If this occurs then we have a big problem - something else 2305eb6f0de0SAdrian Chadd * has slid tap->txa_start along without updating the BAW 2306eb6f0de0SAdrian Chadd * tracking start/end pointers. Thus the TX BAW state is now 2307eb6f0de0SAdrian Chadd * completely busted. 2308eb6f0de0SAdrian Chadd * 2309eb6f0de0SAdrian Chadd * But for now, since I haven't yet fixed TDMA and buffer cloning, 2310eb6f0de0SAdrian Chadd * it's quite possible that a cloned buffer is making its way 2311eb6f0de0SAdrian Chadd * here and causing it to fire off. Disable TDMA for now. 2312eb6f0de0SAdrian Chadd */ 2313eb6f0de0SAdrian Chadd if (tid->tx_buf[cindex] != bf) { 2314eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 2315eb6f0de0SAdrian Chadd "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n", 2316eb6f0de0SAdrian Chadd __func__, 2317eb6f0de0SAdrian Chadd bf, SEQNO(bf->bf_state.bfs_seqno), 2318eb6f0de0SAdrian Chadd tid->tx_buf[cindex], 2319eb6f0de0SAdrian Chadd SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno)); 2320eb6f0de0SAdrian Chadd } 2321eb6f0de0SAdrian Chadd 2322eb6f0de0SAdrian Chadd tid->tx_buf[cindex] = NULL; 2323eb6f0de0SAdrian Chadd 2324d4365d16SAdrian Chadd while (tid->baw_head != tid->baw_tail && 2325d4365d16SAdrian Chadd !tid->tx_buf[tid->baw_head]) { 2326eb6f0de0SAdrian Chadd INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 2327eb6f0de0SAdrian Chadd INCR(tid->baw_head, ATH_TID_MAX_BUFS); 2328eb6f0de0SAdrian Chadd } 2329d4365d16SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 2330d4365d16SAdrian Chadd "%s: baw is now %d:%d, baw head=%d\n", 2331eb6f0de0SAdrian Chadd __func__, tap->txa_start, tap->txa_wnd, tid->baw_head); 2332eb6f0de0SAdrian Chadd } 2333eb6f0de0SAdrian Chadd 2334eb6f0de0SAdrian Chadd /* 2335eb6f0de0SAdrian Chadd * Mark the current node/TID as ready to TX. 2336eb6f0de0SAdrian Chadd * 2337eb6f0de0SAdrian Chadd * This is done to make it easy for the software scheduler to 2338eb6f0de0SAdrian Chadd * find which nodes have data to send. 2339eb6f0de0SAdrian Chadd * 2340eb6f0de0SAdrian Chadd * The TXQ lock must be held. 2341eb6f0de0SAdrian Chadd */ 2342eb6f0de0SAdrian Chadd static void 2343eb6f0de0SAdrian Chadd ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid) 2344eb6f0de0SAdrian Chadd { 2345eb6f0de0SAdrian Chadd struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2346eb6f0de0SAdrian Chadd 2347eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 2348eb6f0de0SAdrian Chadd 2349eb6f0de0SAdrian Chadd if (tid->paused) 2350eb6f0de0SAdrian Chadd return; /* paused, can't schedule yet */ 2351eb6f0de0SAdrian Chadd 2352eb6f0de0SAdrian Chadd if (tid->sched) 2353eb6f0de0SAdrian Chadd return; /* already scheduled */ 2354eb6f0de0SAdrian Chadd 2355eb6f0de0SAdrian Chadd tid->sched = 1; 2356eb6f0de0SAdrian Chadd 2357eb6f0de0SAdrian Chadd TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem); 2358eb6f0de0SAdrian Chadd } 2359eb6f0de0SAdrian Chadd 2360eb6f0de0SAdrian Chadd /* 2361eb6f0de0SAdrian Chadd * Mark the current node as no longer needing to be polled for 2362eb6f0de0SAdrian Chadd * TX packets. 2363eb6f0de0SAdrian Chadd * 2364eb6f0de0SAdrian Chadd * The TXQ lock must be held. 2365eb6f0de0SAdrian Chadd */ 2366eb6f0de0SAdrian Chadd static void 2367eb6f0de0SAdrian Chadd ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid) 2368eb6f0de0SAdrian Chadd { 2369eb6f0de0SAdrian Chadd struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2370eb6f0de0SAdrian Chadd 2371eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 2372eb6f0de0SAdrian Chadd 2373eb6f0de0SAdrian Chadd if (tid->sched == 0) 2374eb6f0de0SAdrian Chadd return; 2375eb6f0de0SAdrian Chadd 2376eb6f0de0SAdrian Chadd tid->sched = 0; 2377eb6f0de0SAdrian Chadd TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem); 2378eb6f0de0SAdrian Chadd } 2379eb6f0de0SAdrian Chadd 2380eb6f0de0SAdrian Chadd /* 2381eb6f0de0SAdrian Chadd * Assign a sequence number manually to the given frame. 2382eb6f0de0SAdrian Chadd * 2383eb6f0de0SAdrian Chadd * This should only be called for A-MPDU TX frames. 2384eb6f0de0SAdrian Chadd */ 2385a108d2d6SAdrian Chadd static ieee80211_seq 2386eb6f0de0SAdrian Chadd ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni, 2387eb6f0de0SAdrian Chadd struct ath_buf *bf, struct mbuf *m0) 2388eb6f0de0SAdrian Chadd { 2389eb6f0de0SAdrian Chadd struct ieee80211_frame *wh; 2390eb6f0de0SAdrian Chadd int tid, pri; 2391eb6f0de0SAdrian Chadd ieee80211_seq seqno; 2392eb6f0de0SAdrian Chadd uint8_t subtype; 2393eb6f0de0SAdrian Chadd 2394eb6f0de0SAdrian Chadd /* TID lookup */ 2395eb6f0de0SAdrian Chadd wh = mtod(m0, struct ieee80211_frame *); 2396eb6f0de0SAdrian Chadd pri = M_WME_GETAC(m0); /* honor classification */ 2397eb6f0de0SAdrian Chadd tid = WME_AC_TO_TID(pri); 2398a108d2d6SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pri=%d, tid=%d, qos has seq=%d\n", 2399a108d2d6SAdrian Chadd __func__, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2400eb6f0de0SAdrian Chadd 2401eb6f0de0SAdrian Chadd /* XXX Is it a control frame? Ignore */ 2402eb6f0de0SAdrian Chadd 2403eb6f0de0SAdrian Chadd /* Does the packet require a sequence number? */ 2404eb6f0de0SAdrian Chadd if (! IEEE80211_QOS_HAS_SEQ(wh)) 2405eb6f0de0SAdrian Chadd return -1; 2406eb6f0de0SAdrian Chadd 24077561cb5cSAdrian Chadd ATH_TID_LOCK_ASSERT(sc, &(ATH_NODE(ni)->an_tid[tid])); 24087561cb5cSAdrian Chadd 2409eb6f0de0SAdrian Chadd /* 2410eb6f0de0SAdrian Chadd * Is it a QOS NULL Data frame? Give it a sequence number from 2411eb6f0de0SAdrian Chadd * the default TID (IEEE80211_NONQOS_TID.) 2412eb6f0de0SAdrian Chadd * 2413eb6f0de0SAdrian Chadd * The RX path of everything I've looked at doesn't include the NULL 2414eb6f0de0SAdrian Chadd * data frame sequence number in the aggregation state updates, so 2415eb6f0de0SAdrian Chadd * assigning it a sequence number there will cause a BAW hole on the 2416eb6f0de0SAdrian Chadd * RX side. 2417eb6f0de0SAdrian Chadd */ 2418eb6f0de0SAdrian Chadd subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 2419eb6f0de0SAdrian Chadd if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) { 24207561cb5cSAdrian Chadd /* XXX no locking for this TID? This is a bit of a problem. */ 2421eb6f0de0SAdrian Chadd seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID]; 2422eb6f0de0SAdrian Chadd INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE); 2423eb6f0de0SAdrian Chadd } else { 2424eb6f0de0SAdrian Chadd /* Manually assign sequence number */ 2425eb6f0de0SAdrian Chadd seqno = ni->ni_txseqs[tid]; 2426eb6f0de0SAdrian Chadd INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE); 2427eb6f0de0SAdrian Chadd } 2428eb6f0de0SAdrian Chadd *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 2429eb6f0de0SAdrian Chadd M_SEQNO_SET(m0, seqno); 2430eb6f0de0SAdrian Chadd 2431eb6f0de0SAdrian Chadd /* Return so caller can do something with it if needed */ 2432a108d2d6SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: -> seqno=%d\n", __func__, seqno); 2433eb6f0de0SAdrian Chadd return seqno; 2434eb6f0de0SAdrian Chadd } 2435eb6f0de0SAdrian Chadd 2436eb6f0de0SAdrian Chadd /* 2437eb6f0de0SAdrian Chadd * Attempt to direct dispatch an aggregate frame to hardware. 2438eb6f0de0SAdrian Chadd * If the frame is out of BAW, queue. 2439eb6f0de0SAdrian Chadd * Otherwise, schedule it as a single frame. 2440eb6f0de0SAdrian Chadd */ 2441eb6f0de0SAdrian Chadd static void 2442*46634305SAdrian Chadd ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an, 2443*46634305SAdrian Chadd struct ath_txq *txq, struct ath_buf *bf) 2444eb6f0de0SAdrian Chadd { 2445eb6f0de0SAdrian Chadd struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid]; 2446*46634305SAdrian Chadd // struct ath_txq *txq = bf->bf_state.bfs_txq; 2447eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 2448eb6f0de0SAdrian Chadd 2449*46634305SAdrian Chadd if (txq != bf->bf_state.bfs_txq) { 2450*46634305SAdrian Chadd device_printf(sc->sc_dev, "%s: txq %d != bfs_txq %d!\n", 2451*46634305SAdrian Chadd __func__, 2452*46634305SAdrian Chadd txq->axq_qnum, 2453*46634305SAdrian Chadd bf->bf_state.bfs_txq->axq_qnum); 2454*46634305SAdrian Chadd } 2455*46634305SAdrian Chadd 2456eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 2457c2ac9655SAdrian Chadd ATH_TID_LOCK_ASSERT(sc, tid); 2458eb6f0de0SAdrian Chadd 2459eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid->tid); 2460eb6f0de0SAdrian Chadd 2461eb6f0de0SAdrian Chadd /* paused? queue */ 2462eb6f0de0SAdrian Chadd if (tid->paused) { 24634547f047SAdrian Chadd ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 24640f04c5a2SAdrian Chadd /* XXX don't sched - we're paused! */ 2465eb6f0de0SAdrian Chadd return; 2466eb6f0de0SAdrian Chadd } 2467eb6f0de0SAdrian Chadd 2468eb6f0de0SAdrian Chadd /* outside baw? queue */ 2469eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_dobaw && 2470eb6f0de0SAdrian Chadd (! BAW_WITHIN(tap->txa_start, tap->txa_wnd, 2471eb6f0de0SAdrian Chadd SEQNO(bf->bf_state.bfs_seqno)))) { 2472ba0e58f4SAdrian Chadd ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 2473eb6f0de0SAdrian Chadd ath_tx_tid_sched(sc, tid); 2474eb6f0de0SAdrian Chadd return; 2475eb6f0de0SAdrian Chadd } 2476eb6f0de0SAdrian Chadd 2477eb6f0de0SAdrian Chadd /* Direct dispatch to hardware */ 2478eb6f0de0SAdrian Chadd ath_tx_do_ratelookup(sc, bf); 2479e2e4a2c2SAdrian Chadd ath_tx_calc_duration(sc, bf); 2480e2e4a2c2SAdrian Chadd ath_tx_calc_protection(sc, bf); 2481eb6f0de0SAdrian Chadd ath_tx_set_rtscts(sc, bf); 2482e2e4a2c2SAdrian Chadd ath_tx_rate_fill_rcflags(sc, bf); 2483eb6f0de0SAdrian Chadd ath_tx_setds(sc, bf); 2484eb6f0de0SAdrian Chadd 2485eb6f0de0SAdrian Chadd /* Statistics */ 2486eb6f0de0SAdrian Chadd sc->sc_aggr_stats.aggr_low_hwq_single_pkt++; 2487eb6f0de0SAdrian Chadd 2488eb6f0de0SAdrian Chadd /* Track per-TID hardware queue depth correctly */ 2489eb6f0de0SAdrian Chadd tid->hwq_depth++; 2490eb6f0de0SAdrian Chadd 2491eb6f0de0SAdrian Chadd /* Add to BAW */ 2492eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_dobaw) { 2493eb6f0de0SAdrian Chadd ath_tx_addto_baw(sc, an, tid, bf); 2494eb6f0de0SAdrian Chadd bf->bf_state.bfs_addedbaw = 1; 2495eb6f0de0SAdrian Chadd } 2496eb6f0de0SAdrian Chadd 2497eb6f0de0SAdrian Chadd /* Set completion handler, multi-frame aggregate or not */ 2498eb6f0de0SAdrian Chadd bf->bf_comp = ath_tx_aggr_comp; 2499eb6f0de0SAdrian Chadd 2500eb6f0de0SAdrian Chadd /* Hand off to hardware */ 2501eb6f0de0SAdrian Chadd ath_tx_handoff(sc, txq, bf); 2502eb6f0de0SAdrian Chadd } 2503eb6f0de0SAdrian Chadd 2504eb6f0de0SAdrian Chadd /* 2505eb6f0de0SAdrian Chadd * Attempt to send the packet. 2506eb6f0de0SAdrian Chadd * If the queue isn't busy, direct-dispatch. 2507eb6f0de0SAdrian Chadd * If the queue is busy enough, queue the given packet on the 2508eb6f0de0SAdrian Chadd * relevant software queue. 2509eb6f0de0SAdrian Chadd */ 2510eb6f0de0SAdrian Chadd void 2511eb6f0de0SAdrian Chadd ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq, 2512eb6f0de0SAdrian Chadd struct ath_buf *bf) 2513eb6f0de0SAdrian Chadd { 2514eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 2515eb6f0de0SAdrian Chadd struct ieee80211_frame *wh; 2516eb6f0de0SAdrian Chadd struct ath_tid *atid; 2517eb6f0de0SAdrian Chadd int pri, tid; 2518eb6f0de0SAdrian Chadd struct mbuf *m0 = bf->bf_m; 2519eb6f0de0SAdrian Chadd 25207561cb5cSAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 25217561cb5cSAdrian Chadd 2522eb6f0de0SAdrian Chadd /* Fetch the TID - non-QoS frames get assigned to TID 16 */ 2523eb6f0de0SAdrian Chadd wh = mtod(m0, struct ieee80211_frame *); 2524eb6f0de0SAdrian Chadd pri = ath_tx_getac(sc, m0); 2525eb6f0de0SAdrian Chadd tid = ath_tx_gettid(sc, m0); 2526eb6f0de0SAdrian Chadd atid = &an->an_tid[tid]; 2527eb6f0de0SAdrian Chadd 2528c2ac9655SAdrian Chadd ATH_TID_LOCK_ASSERT(sc, atid); 2529c2ac9655SAdrian Chadd 2530a108d2d6SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d\n", 2531a108d2d6SAdrian Chadd __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh)); 2532eb6f0de0SAdrian Chadd 2533eb6f0de0SAdrian Chadd /* Set local packet state, used to queue packets to hardware */ 2534*46634305SAdrian Chadd /* XXX potentially duplicate info, re-check */ 2535*46634305SAdrian Chadd /* XXX remember, txq must be the hardware queue, not the av_mcastq */ 2536eb6f0de0SAdrian Chadd bf->bf_state.bfs_tid = tid; 2537eb6f0de0SAdrian Chadd bf->bf_state.bfs_txq = txq; 2538eb6f0de0SAdrian Chadd bf->bf_state.bfs_pri = pri; 2539eb6f0de0SAdrian Chadd 2540eb6f0de0SAdrian Chadd /* 2541eb6f0de0SAdrian Chadd * If the hardware queue isn't busy, queue it directly. 2542eb6f0de0SAdrian Chadd * If the hardware queue is busy, queue it. 2543eb6f0de0SAdrian Chadd * If the TID is paused or the traffic it outside BAW, software 2544eb6f0de0SAdrian Chadd * queue it. 2545eb6f0de0SAdrian Chadd */ 2546eb6f0de0SAdrian Chadd if (atid->paused) { 2547eb6f0de0SAdrian Chadd /* TID is paused, queue */ 2548a108d2d6SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: paused\n", __func__); 2549eb6f0de0SAdrian Chadd ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2550eb6f0de0SAdrian Chadd } else if (ath_tx_ampdu_pending(sc, an, tid)) { 2551eb6f0de0SAdrian Chadd /* AMPDU pending; queue */ 2552a108d2d6SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pending\n", __func__); 2553eb6f0de0SAdrian Chadd ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2554eb6f0de0SAdrian Chadd /* XXX sched? */ 2555eb6f0de0SAdrian Chadd } else if (ath_tx_ampdu_running(sc, an, tid)) { 2556eb6f0de0SAdrian Chadd /* AMPDU running, attempt direct dispatch if possible */ 255739f24578SAdrian Chadd 255839f24578SAdrian Chadd /* 255939f24578SAdrian Chadd * Always queue the frame to the tail of the list. 256039f24578SAdrian Chadd */ 256139f24578SAdrian Chadd ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 256239f24578SAdrian Chadd 256339f24578SAdrian Chadd /* 256439f24578SAdrian Chadd * If the hardware queue isn't busy, direct dispatch 256539f24578SAdrian Chadd * the head frame in the list. Don't schedule the 256639f24578SAdrian Chadd * TID - let it build some more frames first? 256739f24578SAdrian Chadd * 256839f24578SAdrian Chadd * Otherwise, schedule the TID. 256939f24578SAdrian Chadd */ 2570d4365d16SAdrian Chadd if (txq->axq_depth < sc->sc_hwq_limit) { 257139f24578SAdrian Chadd bf = TAILQ_FIRST(&atid->axq_q); 257239f24578SAdrian Chadd ATH_TXQ_REMOVE(atid, bf, bf_list); 2573*46634305SAdrian Chadd ath_tx_xmit_aggr(sc, an, txq, bf); 2574a108d2d6SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, 2575a108d2d6SAdrian Chadd "%s: xmit_aggr\n", 2576a108d2d6SAdrian Chadd __func__); 2577d4365d16SAdrian Chadd } else { 2578d4365d16SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, 2579a108d2d6SAdrian Chadd "%s: ampdu; swq'ing\n", 2580a108d2d6SAdrian Chadd __func__); 2581eb6f0de0SAdrian Chadd ath_tx_tid_sched(sc, atid); 2582eb6f0de0SAdrian Chadd } 2583eb6f0de0SAdrian Chadd } else if (txq->axq_depth < sc->sc_hwq_limit) { 2584eb6f0de0SAdrian Chadd /* AMPDU not running, attempt direct dispatch */ 2585a108d2d6SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: xmit_normal\n", __func__); 2586eb6f0de0SAdrian Chadd ath_tx_xmit_normal(sc, txq, bf); 2587eb6f0de0SAdrian Chadd } else { 2588eb6f0de0SAdrian Chadd /* Busy; queue */ 2589a108d2d6SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: swq'ing\n", __func__); 2590eb6f0de0SAdrian Chadd ATH_TXQ_INSERT_TAIL(atid, bf, bf_list); 2591eb6f0de0SAdrian Chadd ath_tx_tid_sched(sc, atid); 2592eb6f0de0SAdrian Chadd } 2593eb6f0de0SAdrian Chadd } 2594eb6f0de0SAdrian Chadd 2595eb6f0de0SAdrian Chadd /* 2596eb6f0de0SAdrian Chadd * Do the basic frame setup stuff that's required before the frame 2597eb6f0de0SAdrian Chadd * is added to a software queue. 2598eb6f0de0SAdrian Chadd * 2599eb6f0de0SAdrian Chadd * All frames get mostly the same treatment and it's done once. 2600eb6f0de0SAdrian Chadd * Retransmits fiddle with things like the rate control setup, 2601eb6f0de0SAdrian Chadd * setting the retransmit bit in the packet; doing relevant DMA/bus 2602eb6f0de0SAdrian Chadd * syncing and relinking it (back) into the hardware TX queue. 2603eb6f0de0SAdrian Chadd * 2604eb6f0de0SAdrian Chadd * Note that this may cause the mbuf to be reallocated, so 2605eb6f0de0SAdrian Chadd * m0 may not be valid. 2606eb6f0de0SAdrian Chadd */ 2607eb6f0de0SAdrian Chadd 2608eb6f0de0SAdrian Chadd 2609eb6f0de0SAdrian Chadd /* 2610eb6f0de0SAdrian Chadd * Configure the per-TID node state. 2611eb6f0de0SAdrian Chadd * 2612eb6f0de0SAdrian Chadd * This likely belongs in if_ath_node.c but I can't think of anywhere 2613eb6f0de0SAdrian Chadd * else to put it just yet. 2614eb6f0de0SAdrian Chadd * 2615eb6f0de0SAdrian Chadd * This sets up the SLISTs and the mutex as appropriate. 2616eb6f0de0SAdrian Chadd */ 2617eb6f0de0SAdrian Chadd void 2618eb6f0de0SAdrian Chadd ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an) 2619eb6f0de0SAdrian Chadd { 2620eb6f0de0SAdrian Chadd int i, j; 2621eb6f0de0SAdrian Chadd struct ath_tid *atid; 2622eb6f0de0SAdrian Chadd 2623eb6f0de0SAdrian Chadd for (i = 0; i < IEEE80211_TID_SIZE; i++) { 2624eb6f0de0SAdrian Chadd atid = &an->an_tid[i]; 2625eb6f0de0SAdrian Chadd TAILQ_INIT(&atid->axq_q); 2626eb6f0de0SAdrian Chadd atid->tid = i; 2627eb6f0de0SAdrian Chadd atid->an = an; 2628eb6f0de0SAdrian Chadd for (j = 0; j < ATH_TID_MAX_BUFS; j++) 2629eb6f0de0SAdrian Chadd atid->tx_buf[j] = NULL; 2630eb6f0de0SAdrian Chadd atid->baw_head = atid->baw_tail = 0; 2631eb6f0de0SAdrian Chadd atid->paused = 0; 2632eb6f0de0SAdrian Chadd atid->sched = 0; 2633eb6f0de0SAdrian Chadd atid->hwq_depth = 0; 2634eb6f0de0SAdrian Chadd atid->cleanup_inprogress = 0; 2635eb6f0de0SAdrian Chadd if (i == IEEE80211_NONQOS_TID) 2636eb6f0de0SAdrian Chadd atid->ac = WME_AC_BE; 2637eb6f0de0SAdrian Chadd else 2638eb6f0de0SAdrian Chadd atid->ac = TID_TO_WME_AC(i); 2639eb6f0de0SAdrian Chadd } 2640eb6f0de0SAdrian Chadd } 2641eb6f0de0SAdrian Chadd 2642eb6f0de0SAdrian Chadd /* 2643eb6f0de0SAdrian Chadd * Pause the current TID. This stops packets from being transmitted 2644eb6f0de0SAdrian Chadd * on it. 2645eb6f0de0SAdrian Chadd * 2646eb6f0de0SAdrian Chadd * Since this is also called from upper layers as well as the driver, 2647eb6f0de0SAdrian Chadd * it will get the TID lock. 2648eb6f0de0SAdrian Chadd */ 2649eb6f0de0SAdrian Chadd static void 2650eb6f0de0SAdrian Chadd ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid) 2651eb6f0de0SAdrian Chadd { 265288b3d483SAdrian Chadd 265388b3d483SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2654eb6f0de0SAdrian Chadd tid->paused++; 2655eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n", 2656eb6f0de0SAdrian Chadd __func__, tid->paused); 2657eb6f0de0SAdrian Chadd } 2658eb6f0de0SAdrian Chadd 2659eb6f0de0SAdrian Chadd /* 2660eb6f0de0SAdrian Chadd * Unpause the current TID, and schedule it if needed. 2661eb6f0de0SAdrian Chadd */ 2662eb6f0de0SAdrian Chadd static void 2663eb6f0de0SAdrian Chadd ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid) 2664eb6f0de0SAdrian Chadd { 2665eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2666eb6f0de0SAdrian Chadd 2667eb6f0de0SAdrian Chadd tid->paused--; 2668eb6f0de0SAdrian Chadd 2669eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n", 2670eb6f0de0SAdrian Chadd __func__, tid->paused); 2671eb6f0de0SAdrian Chadd 2672eb6f0de0SAdrian Chadd if (tid->paused || tid->axq_depth == 0) { 2673eb6f0de0SAdrian Chadd return; 2674eb6f0de0SAdrian Chadd } 2675eb6f0de0SAdrian Chadd 2676eb6f0de0SAdrian Chadd ath_tx_tid_sched(sc, tid); 2677eb6f0de0SAdrian Chadd /* Punt some frames to the hardware if needed */ 267803e9308fSAdrian Chadd //ath_txq_sched(sc, sc->sc_ac2q[tid->ac]); 267903e9308fSAdrian Chadd taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask); 2680eb6f0de0SAdrian Chadd } 2681eb6f0de0SAdrian Chadd 2682eb6f0de0SAdrian Chadd /* 268388b3d483SAdrian Chadd * Suspend the queue because we need to TX a BAR. 268488b3d483SAdrian Chadd */ 268588b3d483SAdrian Chadd static void 268688b3d483SAdrian Chadd ath_tx_tid_bar_suspend(struct ath_softc *sc, struct ath_tid *tid) 268788b3d483SAdrian Chadd { 268888b3d483SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 268988b3d483SAdrian Chadd 26900e22ed0eSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 2691e60c4fc2SAdrian Chadd "%s: tid=%p, bar_wait=%d, bar_tx=%d, called\n", 269288b3d483SAdrian Chadd __func__, 2693e60c4fc2SAdrian Chadd tid, 2694e60c4fc2SAdrian Chadd tid->bar_wait, 2695e60c4fc2SAdrian Chadd tid->bar_tx); 269688b3d483SAdrian Chadd 269788b3d483SAdrian Chadd /* We shouldn't be called when bar_tx is 1 */ 269888b3d483SAdrian Chadd if (tid->bar_tx) { 269988b3d483SAdrian Chadd device_printf(sc->sc_dev, "%s: bar_tx is 1?!\n", 270088b3d483SAdrian Chadd __func__); 270188b3d483SAdrian Chadd } 270288b3d483SAdrian Chadd 270388b3d483SAdrian Chadd /* If we've already been called, just be patient. */ 270488b3d483SAdrian Chadd if (tid->bar_wait) 270588b3d483SAdrian Chadd return; 270688b3d483SAdrian Chadd 270788b3d483SAdrian Chadd /* Wait! */ 270888b3d483SAdrian Chadd tid->bar_wait = 1; 270988b3d483SAdrian Chadd 271088b3d483SAdrian Chadd /* Only one pause, no matter how many frames fail */ 271188b3d483SAdrian Chadd ath_tx_tid_pause(sc, tid); 271288b3d483SAdrian Chadd } 271388b3d483SAdrian Chadd 271488b3d483SAdrian Chadd /* 271588b3d483SAdrian Chadd * We've finished with BAR handling - either we succeeded or 271688b3d483SAdrian Chadd * failed. Either way, unsuspend TX. 271788b3d483SAdrian Chadd */ 271888b3d483SAdrian Chadd static void 271988b3d483SAdrian Chadd ath_tx_tid_bar_unsuspend(struct ath_softc *sc, struct ath_tid *tid) 272088b3d483SAdrian Chadd { 272188b3d483SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 272288b3d483SAdrian Chadd 27230e22ed0eSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 272488b3d483SAdrian Chadd "%s: tid=%p, called\n", 272588b3d483SAdrian Chadd __func__, 272688b3d483SAdrian Chadd tid); 272788b3d483SAdrian Chadd 272888b3d483SAdrian Chadd if (tid->bar_tx == 0 || tid->bar_wait == 0) { 272988b3d483SAdrian Chadd device_printf(sc->sc_dev, "%s: bar_tx=%d, bar_wait=%d: ?\n", 273088b3d483SAdrian Chadd __func__, tid->bar_tx, tid->bar_wait); 273188b3d483SAdrian Chadd } 273288b3d483SAdrian Chadd 273388b3d483SAdrian Chadd tid->bar_tx = tid->bar_wait = 0; 273488b3d483SAdrian Chadd ath_tx_tid_resume(sc, tid); 273588b3d483SAdrian Chadd } 273688b3d483SAdrian Chadd 273788b3d483SAdrian Chadd /* 273888b3d483SAdrian Chadd * Return whether we're ready to TX a BAR frame. 273988b3d483SAdrian Chadd * 274088b3d483SAdrian Chadd * Requires the TID lock be held. 274188b3d483SAdrian Chadd */ 274288b3d483SAdrian Chadd static int 274388b3d483SAdrian Chadd ath_tx_tid_bar_tx_ready(struct ath_softc *sc, struct ath_tid *tid) 274488b3d483SAdrian Chadd { 274588b3d483SAdrian Chadd 274688b3d483SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 274788b3d483SAdrian Chadd 274888b3d483SAdrian Chadd if (tid->bar_wait == 0 || tid->hwq_depth > 0) 274988b3d483SAdrian Chadd return (0); 275088b3d483SAdrian Chadd 27510e22ed0eSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, "%s: tid=%p (%d), bar ready\n", 27520e22ed0eSAdrian Chadd __func__, tid, tid->tid); 27530e22ed0eSAdrian Chadd 275488b3d483SAdrian Chadd return (1); 275588b3d483SAdrian Chadd } 275688b3d483SAdrian Chadd 275788b3d483SAdrian Chadd /* 275888b3d483SAdrian Chadd * Check whether the current TID is ready to have a BAR 275988b3d483SAdrian Chadd * TXed and if so, do the TX. 276088b3d483SAdrian Chadd * 276188b3d483SAdrian Chadd * Since the TID/TXQ lock can't be held during a call to 276288b3d483SAdrian Chadd * ieee80211_send_bar(), we have to do the dirty thing of unlocking it, 276388b3d483SAdrian Chadd * sending the BAR and locking it again. 276488b3d483SAdrian Chadd * 276588b3d483SAdrian Chadd * Eventually, the code to send the BAR should be broken out 276688b3d483SAdrian Chadd * from this routine so the lock doesn't have to be reacquired 276788b3d483SAdrian Chadd * just to be immediately dropped by the caller. 276888b3d483SAdrian Chadd */ 276988b3d483SAdrian Chadd static void 277088b3d483SAdrian Chadd ath_tx_tid_bar_tx(struct ath_softc *sc, struct ath_tid *tid) 277188b3d483SAdrian Chadd { 277288b3d483SAdrian Chadd struct ieee80211_tx_ampdu *tap; 277388b3d483SAdrian Chadd 277488b3d483SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 277588b3d483SAdrian Chadd 27760e22ed0eSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 277788b3d483SAdrian Chadd "%s: tid=%p, called\n", 277888b3d483SAdrian Chadd __func__, 277988b3d483SAdrian Chadd tid); 278088b3d483SAdrian Chadd 278188b3d483SAdrian Chadd tap = ath_tx_get_tx_tid(tid->an, tid->tid); 278288b3d483SAdrian Chadd 278388b3d483SAdrian Chadd /* 278488b3d483SAdrian Chadd * This is an error condition! 278588b3d483SAdrian Chadd */ 278688b3d483SAdrian Chadd if (tid->bar_wait == 0 || tid->bar_tx == 1) { 278788b3d483SAdrian Chadd device_printf(sc->sc_dev, 278888b3d483SAdrian Chadd "%s: tid=%p, bar_tx=%d, bar_wait=%d: ?\n", 278988b3d483SAdrian Chadd __func__, 279088b3d483SAdrian Chadd tid, 279188b3d483SAdrian Chadd tid->bar_tx, 279288b3d483SAdrian Chadd tid->bar_wait); 279388b3d483SAdrian Chadd return; 279488b3d483SAdrian Chadd } 279588b3d483SAdrian Chadd 279688b3d483SAdrian Chadd /* Don't do anything if we still have pending frames */ 279788b3d483SAdrian Chadd if (tid->hwq_depth > 0) { 27980e22ed0eSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 279988b3d483SAdrian Chadd "%s: tid=%p, hwq_depth=%d, waiting\n", 280088b3d483SAdrian Chadd __func__, 280188b3d483SAdrian Chadd tid, 280288b3d483SAdrian Chadd tid->hwq_depth); 280388b3d483SAdrian Chadd return; 280488b3d483SAdrian Chadd } 280588b3d483SAdrian Chadd 280688b3d483SAdrian Chadd /* We're now about to TX */ 280788b3d483SAdrian Chadd tid->bar_tx = 1; 280888b3d483SAdrian Chadd 280988b3d483SAdrian Chadd /* 281088b3d483SAdrian Chadd * Calculate new BAW left edge, now that all frames have either 281188b3d483SAdrian Chadd * succeeded or failed. 281288b3d483SAdrian Chadd * 281388b3d483SAdrian Chadd * XXX verify this is _actually_ the valid value to begin at! 281488b3d483SAdrian Chadd */ 28150e22ed0eSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 281688b3d483SAdrian Chadd "%s: tid=%p, new BAW left edge=%d\n", 281788b3d483SAdrian Chadd __func__, 281888b3d483SAdrian Chadd tid, 281988b3d483SAdrian Chadd tap->txa_start); 282088b3d483SAdrian Chadd 282188b3d483SAdrian Chadd /* Try sending the BAR frame */ 282288b3d483SAdrian Chadd /* We can't hold the lock here! */ 282388b3d483SAdrian Chadd 282488b3d483SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 282588b3d483SAdrian Chadd if (ieee80211_send_bar(&tid->an->an_node, tap, tap->txa_start) == 0) { 282688b3d483SAdrian Chadd /* Success? Now we wait for notification that it's done */ 282788b3d483SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 282888b3d483SAdrian Chadd return; 282988b3d483SAdrian Chadd } 283088b3d483SAdrian Chadd 283188b3d483SAdrian Chadd /* Failure? For now, warn loudly and continue */ 283288b3d483SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 283388b3d483SAdrian Chadd device_printf(sc->sc_dev, "%s: tid=%p, failed to TX BAR, continue!\n", 283488b3d483SAdrian Chadd __func__, tid); 283588b3d483SAdrian Chadd ath_tx_tid_bar_unsuspend(sc, tid); 283688b3d483SAdrian Chadd } 283788b3d483SAdrian Chadd 283888b3d483SAdrian Chadd 283988b3d483SAdrian Chadd /* 2840eb6f0de0SAdrian Chadd * Free any packets currently pending in the software TX queue. 2841eb6f0de0SAdrian Chadd * 2842eb6f0de0SAdrian Chadd * This will be called when a node is being deleted. 2843eb6f0de0SAdrian Chadd * 2844eb6f0de0SAdrian Chadd * It can also be called on an active node during an interface 2845eb6f0de0SAdrian Chadd * reset or state transition. 2846eb6f0de0SAdrian Chadd * 2847eb6f0de0SAdrian Chadd * (From Linux/reference): 2848eb6f0de0SAdrian Chadd * 2849eb6f0de0SAdrian Chadd * TODO: For frame(s) that are in the retry state, we will reuse the 2850eb6f0de0SAdrian Chadd * sequence number(s) without setting the retry bit. The 2851eb6f0de0SAdrian Chadd * alternative is to give up on these and BAR the receiver's window 2852eb6f0de0SAdrian Chadd * forward. 2853eb6f0de0SAdrian Chadd */ 2854eb6f0de0SAdrian Chadd static void 2855d4365d16SAdrian Chadd ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an, 2856d4365d16SAdrian Chadd struct ath_tid *tid, ath_bufhead *bf_cq) 2857eb6f0de0SAdrian Chadd { 2858eb6f0de0SAdrian Chadd struct ath_buf *bf; 2859eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 2860eb6f0de0SAdrian Chadd struct ieee80211_node *ni = &an->an_node; 2861eb6f0de0SAdrian Chadd int t = 0; 2862eb6f0de0SAdrian Chadd struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 2863eb6f0de0SAdrian Chadd 2864eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid->tid); 2865eb6f0de0SAdrian Chadd 2866eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[tid->ac]); 2867eb6f0de0SAdrian Chadd 2868eb6f0de0SAdrian Chadd /* Walk the queue, free frames */ 2869eb6f0de0SAdrian Chadd for (;;) { 2870eb6f0de0SAdrian Chadd bf = TAILQ_FIRST(&tid->axq_q); 2871eb6f0de0SAdrian Chadd if (bf == NULL) { 2872eb6f0de0SAdrian Chadd break; 2873eb6f0de0SAdrian Chadd } 2874eb6f0de0SAdrian Chadd 2875eb6f0de0SAdrian Chadd if (t == 0) { 2876eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 287712be5b9cSAdrian Chadd "%s: node %p: bf=%p: addbaw=%d, dobaw=%d, " 2878a108d2d6SAdrian Chadd "seqno=%d, retry=%d\n", 287912be5b9cSAdrian Chadd __func__, ni, bf, 288012be5b9cSAdrian Chadd bf->bf_state.bfs_addedbaw, 288112be5b9cSAdrian Chadd bf->bf_state.bfs_dobaw, 28820f04c5a2SAdrian Chadd SEQNO(bf->bf_state.bfs_seqno), 28830f04c5a2SAdrian Chadd bf->bf_state.bfs_retries); 28840f04c5a2SAdrian Chadd device_printf(sc->sc_dev, 28850e22ed0eSAdrian Chadd "%s: node %p: bf=%p: tid txq_depth=%d hwq_depth=%d, bar_wait=%d\n", 28860f04c5a2SAdrian Chadd __func__, ni, bf, 28870f04c5a2SAdrian Chadd tid->axq_depth, 28880e22ed0eSAdrian Chadd tid->hwq_depth, 28890e22ed0eSAdrian Chadd tid->bar_wait); 289012be5b9cSAdrian Chadd device_printf(sc->sc_dev, 2891a108d2d6SAdrian Chadd "%s: node %p: tid %d: txq_depth=%d, " 2892eb6f0de0SAdrian Chadd "txq_aggr_depth=%d, sched=%d, paused=%d, " 2893d4365d16SAdrian Chadd "hwq_depth=%d, incomp=%d, baw_head=%d, " 2894d4365d16SAdrian Chadd "baw_tail=%d txa_start=%d, ni_txseqs=%d\n", 2895a108d2d6SAdrian Chadd __func__, ni, tid->tid, txq->axq_depth, 2896eb6f0de0SAdrian Chadd txq->axq_aggr_depth, tid->sched, tid->paused, 2897eb6f0de0SAdrian Chadd tid->hwq_depth, tid->incomp, tid->baw_head, 2898eb6f0de0SAdrian Chadd tid->baw_tail, tap == NULL ? -1 : tap->txa_start, 2899eb6f0de0SAdrian Chadd ni->ni_txseqs[tid->tid]); 2900c0711b97SAdrian Chadd 2901c0711b97SAdrian Chadd /* XXX Dump the frame, see what it is? */ 2902c0711b97SAdrian Chadd ieee80211_dump_pkt(ni->ni_ic, 2903c0711b97SAdrian Chadd mtod(bf->bf_m, const uint8_t *), 2904c0711b97SAdrian Chadd bf->bf_m->m_len, 0, -1); 2905c0711b97SAdrian Chadd 2906d743debcSAdrian Chadd t = 1; 2907eb6f0de0SAdrian Chadd } 2908eb6f0de0SAdrian Chadd 2909eb6f0de0SAdrian Chadd 2910eb6f0de0SAdrian Chadd /* 2911eb6f0de0SAdrian Chadd * If the current TID is running AMPDU, update 2912eb6f0de0SAdrian Chadd * the BAW. 2913eb6f0de0SAdrian Chadd */ 2914eb6f0de0SAdrian Chadd if (ath_tx_ampdu_running(sc, an, tid->tid) && 2915eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw) { 2916eb6f0de0SAdrian Chadd /* 2917eb6f0de0SAdrian Chadd * Only remove the frame from the BAW if it's 2918eb6f0de0SAdrian Chadd * been transmitted at least once; this means 2919eb6f0de0SAdrian Chadd * the frame was in the BAW to begin with. 2920eb6f0de0SAdrian Chadd */ 2921eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_retries > 0) { 2922eb6f0de0SAdrian Chadd ath_tx_update_baw(sc, an, tid, bf); 2923eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw = 0; 2924eb6f0de0SAdrian Chadd } 2925eb6f0de0SAdrian Chadd /* 2926eb6f0de0SAdrian Chadd * This has become a non-fatal error now 2927eb6f0de0SAdrian Chadd */ 2928eb6f0de0SAdrian Chadd if (! bf->bf_state.bfs_addedbaw) 2929eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 2930eb6f0de0SAdrian Chadd "%s: wasn't added: seqno %d\n", 2931eb6f0de0SAdrian Chadd __func__, SEQNO(bf->bf_state.bfs_seqno)); 2932eb6f0de0SAdrian Chadd } 2933eb6f0de0SAdrian Chadd ATH_TXQ_REMOVE(tid, bf, bf_list); 2934eb6f0de0SAdrian Chadd TAILQ_INSERT_TAIL(bf_cq, bf, bf_list); 2935eb6f0de0SAdrian Chadd } 2936eb6f0de0SAdrian Chadd 2937eb6f0de0SAdrian Chadd /* 2938eb6f0de0SAdrian Chadd * Now that it's completed, grab the TID lock and update 2939eb6f0de0SAdrian Chadd * the sequence number and BAW window. 2940eb6f0de0SAdrian Chadd * Because sequence numbers have been assigned to frames 2941eb6f0de0SAdrian Chadd * that haven't been sent yet, it's entirely possible 2942eb6f0de0SAdrian Chadd * we'll be called with some pending frames that have not 2943eb6f0de0SAdrian Chadd * been transmitted. 2944eb6f0de0SAdrian Chadd * 2945eb6f0de0SAdrian Chadd * The cleaner solution is to do the sequence number allocation 2946eb6f0de0SAdrian Chadd * when the packet is first transmitted - and thus the "retries" 2947eb6f0de0SAdrian Chadd * check above would be enough to update the BAW/seqno. 2948eb6f0de0SAdrian Chadd */ 2949eb6f0de0SAdrian Chadd 2950eb6f0de0SAdrian Chadd /* But don't do it for non-QoS TIDs */ 2951eb6f0de0SAdrian Chadd if (tap) { 2952eb6f0de0SAdrian Chadd #if 0 2953eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 2954eb6f0de0SAdrian Chadd "%s: node %p: TID %d: sliding BAW left edge to %d\n", 2955eb6f0de0SAdrian Chadd __func__, an, tid->tid, tap->txa_start); 2956eb6f0de0SAdrian Chadd #endif 2957eb6f0de0SAdrian Chadd ni->ni_txseqs[tid->tid] = tap->txa_start; 2958eb6f0de0SAdrian Chadd tid->baw_tail = tid->baw_head; 2959eb6f0de0SAdrian Chadd } 2960eb6f0de0SAdrian Chadd } 2961eb6f0de0SAdrian Chadd 2962eb6f0de0SAdrian Chadd /* 2963eb6f0de0SAdrian Chadd * Flush all software queued packets for the given node. 2964eb6f0de0SAdrian Chadd * 2965eb6f0de0SAdrian Chadd * This occurs when a completion handler frees the last buffer 2966eb6f0de0SAdrian Chadd * for a node, and the node is thus freed. This causes the node 2967eb6f0de0SAdrian Chadd * to be cleaned up, which ends up calling ath_tx_node_flush. 2968eb6f0de0SAdrian Chadd */ 2969eb6f0de0SAdrian Chadd void 2970eb6f0de0SAdrian Chadd ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an) 2971eb6f0de0SAdrian Chadd { 2972eb6f0de0SAdrian Chadd int tid; 2973eb6f0de0SAdrian Chadd ath_bufhead bf_cq; 2974eb6f0de0SAdrian Chadd struct ath_buf *bf; 2975eb6f0de0SAdrian Chadd 2976eb6f0de0SAdrian Chadd TAILQ_INIT(&bf_cq); 2977eb6f0de0SAdrian Chadd 2978eb6f0de0SAdrian Chadd for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) { 2979eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 2980eb6f0de0SAdrian Chadd struct ath_txq *txq = sc->sc_ac2q[atid->ac]; 2981eb6f0de0SAdrian Chadd 2982eb6f0de0SAdrian Chadd /* Remove this tid from the list of active tids */ 2983eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(txq); 2984eb6f0de0SAdrian Chadd ath_tx_tid_unsched(sc, atid); 2985eb6f0de0SAdrian Chadd 2986eb6f0de0SAdrian Chadd /* Free packets */ 2987eb6f0de0SAdrian Chadd ath_tx_tid_drain(sc, an, atid, &bf_cq); 2988eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(txq); 2989eb6f0de0SAdrian Chadd } 2990eb6f0de0SAdrian Chadd 2991eb6f0de0SAdrian Chadd /* Handle completed frames */ 2992eb6f0de0SAdrian Chadd while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 2993eb6f0de0SAdrian Chadd TAILQ_REMOVE(&bf_cq, bf, bf_list); 2994eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, 0); 2995eb6f0de0SAdrian Chadd } 2996eb6f0de0SAdrian Chadd } 2997eb6f0de0SAdrian Chadd 2998eb6f0de0SAdrian Chadd /* 2999eb6f0de0SAdrian Chadd * Drain all the software TXQs currently with traffic queued. 3000eb6f0de0SAdrian Chadd */ 3001eb6f0de0SAdrian Chadd void 3002eb6f0de0SAdrian Chadd ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq) 3003eb6f0de0SAdrian Chadd { 3004eb6f0de0SAdrian Chadd struct ath_tid *tid; 3005eb6f0de0SAdrian Chadd ath_bufhead bf_cq; 3006eb6f0de0SAdrian Chadd struct ath_buf *bf; 3007eb6f0de0SAdrian Chadd 3008eb6f0de0SAdrian Chadd TAILQ_INIT(&bf_cq); 3009eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(txq); 3010eb6f0de0SAdrian Chadd 3011eb6f0de0SAdrian Chadd /* 3012eb6f0de0SAdrian Chadd * Iterate over all active tids for the given txq, 3013eb6f0de0SAdrian Chadd * flushing and unsched'ing them 3014eb6f0de0SAdrian Chadd */ 3015eb6f0de0SAdrian Chadd while (! TAILQ_EMPTY(&txq->axq_tidq)) { 3016eb6f0de0SAdrian Chadd tid = TAILQ_FIRST(&txq->axq_tidq); 3017eb6f0de0SAdrian Chadd ath_tx_tid_drain(sc, tid->an, tid, &bf_cq); 3018eb6f0de0SAdrian Chadd ath_tx_tid_unsched(sc, tid); 3019eb6f0de0SAdrian Chadd } 3020eb6f0de0SAdrian Chadd 3021eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(txq); 3022eb6f0de0SAdrian Chadd 3023eb6f0de0SAdrian Chadd while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3024eb6f0de0SAdrian Chadd TAILQ_REMOVE(&bf_cq, bf, bf_list); 3025eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, 0); 3026eb6f0de0SAdrian Chadd } 3027eb6f0de0SAdrian Chadd } 3028eb6f0de0SAdrian Chadd 3029eb6f0de0SAdrian Chadd /* 3030eb6f0de0SAdrian Chadd * Handle completion of non-aggregate session frames. 3031eb6f0de0SAdrian Chadd */ 3032eb6f0de0SAdrian Chadd void 3033eb6f0de0SAdrian Chadd ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3034eb6f0de0SAdrian Chadd { 3035eb6f0de0SAdrian Chadd struct ieee80211_node *ni = bf->bf_node; 3036eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 3037eb6f0de0SAdrian Chadd int tid = bf->bf_state.bfs_tid; 3038eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 3039eb6f0de0SAdrian Chadd struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3040eb6f0de0SAdrian Chadd 3041eb6f0de0SAdrian Chadd /* The TID state is protected behind the TXQ lock */ 3042eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3043eb6f0de0SAdrian Chadd 3044eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n", 3045eb6f0de0SAdrian Chadd __func__, bf, fail, atid->hwq_depth - 1); 3046eb6f0de0SAdrian Chadd 3047eb6f0de0SAdrian Chadd atid->hwq_depth--; 3048eb6f0de0SAdrian Chadd if (atid->hwq_depth < 0) 3049eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3050eb6f0de0SAdrian Chadd __func__, atid->hwq_depth); 3051eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3052eb6f0de0SAdrian Chadd 3053eb6f0de0SAdrian Chadd /* 3054eb6f0de0SAdrian Chadd * punt to rate control if we're not being cleaned up 3055eb6f0de0SAdrian Chadd * during a hw queue drain and the frame wanted an ACK. 3056eb6f0de0SAdrian Chadd */ 3057875a9451SAdrian Chadd if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 3058eb6f0de0SAdrian Chadd ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3059eb6f0de0SAdrian Chadd ts, bf->bf_state.bfs_pktlen, 3060eb6f0de0SAdrian Chadd 1, (ts->ts_status == 0) ? 0 : 1); 3061eb6f0de0SAdrian Chadd 3062eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, fail); 3063eb6f0de0SAdrian Chadd } 3064eb6f0de0SAdrian Chadd 3065eb6f0de0SAdrian Chadd /* 3066eb6f0de0SAdrian Chadd * Handle cleanup of aggregate session packets that aren't 3067eb6f0de0SAdrian Chadd * an A-MPDU. 3068eb6f0de0SAdrian Chadd * 3069eb6f0de0SAdrian Chadd * There's no need to update the BAW here - the session is being 3070eb6f0de0SAdrian Chadd * torn down. 3071eb6f0de0SAdrian Chadd */ 3072eb6f0de0SAdrian Chadd static void 3073eb6f0de0SAdrian Chadd ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3074eb6f0de0SAdrian Chadd { 3075eb6f0de0SAdrian Chadd struct ieee80211_node *ni = bf->bf_node; 3076eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 3077eb6f0de0SAdrian Chadd int tid = bf->bf_state.bfs_tid; 3078eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 3079eb6f0de0SAdrian Chadd 3080eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n", 3081eb6f0de0SAdrian Chadd __func__, tid, atid->incomp); 3082eb6f0de0SAdrian Chadd 3083eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3084eb6f0de0SAdrian Chadd atid->incomp--; 3085eb6f0de0SAdrian Chadd if (atid->incomp == 0) { 3086eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3087eb6f0de0SAdrian Chadd "%s: TID %d: cleaned up! resume!\n", 3088eb6f0de0SAdrian Chadd __func__, tid); 3089eb6f0de0SAdrian Chadd atid->cleanup_inprogress = 0; 3090eb6f0de0SAdrian Chadd ath_tx_tid_resume(sc, atid); 3091eb6f0de0SAdrian Chadd } 3092eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3093eb6f0de0SAdrian Chadd 3094eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, 0); 3095eb6f0de0SAdrian Chadd } 3096eb6f0de0SAdrian Chadd 3097eb6f0de0SAdrian Chadd /* 3098eb6f0de0SAdrian Chadd * Performs transmit side cleanup when TID changes from aggregated to 3099eb6f0de0SAdrian Chadd * unaggregated. 3100eb6f0de0SAdrian Chadd * 3101eb6f0de0SAdrian Chadd * - Discard all retry frames from the s/w queue. 3102eb6f0de0SAdrian Chadd * - Fix the tx completion function for all buffers in s/w queue. 3103eb6f0de0SAdrian Chadd * - Count the number of unacked frames, and let transmit completion 3104eb6f0de0SAdrian Chadd * handle it later. 3105eb6f0de0SAdrian Chadd * 3106eb6f0de0SAdrian Chadd * The caller is responsible for pausing the TID. 3107eb6f0de0SAdrian Chadd */ 3108eb6f0de0SAdrian Chadd static void 31094dfd4507SAdrian Chadd ath_tx_tid_cleanup(struct ath_softc *sc, struct ath_node *an, int tid) 3110eb6f0de0SAdrian Chadd { 3111eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 3112eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 3113eb6f0de0SAdrian Chadd struct ath_buf *bf, *bf_next; 3114eb6f0de0SAdrian Chadd ath_bufhead bf_cq; 3115eb6f0de0SAdrian Chadd 3116d3a6425bSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAW, 3117eb6f0de0SAdrian Chadd "%s: TID %d: called\n", __func__, tid); 3118eb6f0de0SAdrian Chadd 3119eb6f0de0SAdrian Chadd TAILQ_INIT(&bf_cq); 3120eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3121eb6f0de0SAdrian Chadd 3122eb6f0de0SAdrian Chadd /* 3123eb6f0de0SAdrian Chadd * Update the frames in the software TX queue: 3124eb6f0de0SAdrian Chadd * 3125eb6f0de0SAdrian Chadd * + Discard retry frames in the queue 3126eb6f0de0SAdrian Chadd * + Fix the completion function to be non-aggregate 3127eb6f0de0SAdrian Chadd */ 3128eb6f0de0SAdrian Chadd bf = TAILQ_FIRST(&atid->axq_q); 3129eb6f0de0SAdrian Chadd while (bf) { 3130eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_isretried) { 3131eb6f0de0SAdrian Chadd bf_next = TAILQ_NEXT(bf, bf_list); 3132eb6f0de0SAdrian Chadd TAILQ_REMOVE(&atid->axq_q, bf, bf_list); 3133eb6f0de0SAdrian Chadd atid->axq_depth--; 3134eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_dobaw) { 3135eb6f0de0SAdrian Chadd ath_tx_update_baw(sc, an, atid, bf); 3136eb6f0de0SAdrian Chadd if (! bf->bf_state.bfs_addedbaw) 3137eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 3138eb6f0de0SAdrian Chadd "%s: wasn't added: seqno %d\n", 3139d4365d16SAdrian Chadd __func__, 3140d4365d16SAdrian Chadd SEQNO(bf->bf_state.bfs_seqno)); 3141eb6f0de0SAdrian Chadd } 3142eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw = 0; 3143eb6f0de0SAdrian Chadd /* 3144eb6f0de0SAdrian Chadd * Call the default completion handler with "fail" just 3145eb6f0de0SAdrian Chadd * so upper levels are suitably notified about this. 3146eb6f0de0SAdrian Chadd */ 3147eb6f0de0SAdrian Chadd TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3148eb6f0de0SAdrian Chadd bf = bf_next; 3149eb6f0de0SAdrian Chadd continue; 3150eb6f0de0SAdrian Chadd } 3151eb6f0de0SAdrian Chadd /* Give these the default completion handler */ 3152eb6f0de0SAdrian Chadd bf->bf_comp = ath_tx_normal_comp; 3153eb6f0de0SAdrian Chadd bf = TAILQ_NEXT(bf, bf_list); 3154eb6f0de0SAdrian Chadd } 3155eb6f0de0SAdrian Chadd 3156eb6f0de0SAdrian Chadd /* The caller is required to pause the TID */ 3157eb6f0de0SAdrian Chadd #if 0 3158eb6f0de0SAdrian Chadd /* Pause the TID */ 3159eb6f0de0SAdrian Chadd ath_tx_tid_pause(sc, atid); 3160eb6f0de0SAdrian Chadd #endif 3161eb6f0de0SAdrian Chadd 3162eb6f0de0SAdrian Chadd /* 3163eb6f0de0SAdrian Chadd * Calculate what hardware-queued frames exist based 3164eb6f0de0SAdrian Chadd * on the current BAW size. Ie, what frames have been 3165eb6f0de0SAdrian Chadd * added to the TX hardware queue for this TID but 3166eb6f0de0SAdrian Chadd * not yet ACKed. 3167eb6f0de0SAdrian Chadd */ 3168eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid); 3169eb6f0de0SAdrian Chadd /* Need the lock - fiddling with BAW */ 3170eb6f0de0SAdrian Chadd while (atid->baw_head != atid->baw_tail) { 3171eb6f0de0SAdrian Chadd if (atid->tx_buf[atid->baw_head]) { 3172eb6f0de0SAdrian Chadd atid->incomp++; 3173eb6f0de0SAdrian Chadd atid->cleanup_inprogress = 1; 3174eb6f0de0SAdrian Chadd atid->tx_buf[atid->baw_head] = NULL; 3175eb6f0de0SAdrian Chadd } 3176eb6f0de0SAdrian Chadd INCR(atid->baw_head, ATH_TID_MAX_BUFS); 3177eb6f0de0SAdrian Chadd INCR(tap->txa_start, IEEE80211_SEQ_RANGE); 3178eb6f0de0SAdrian Chadd } 3179eb6f0de0SAdrian Chadd 3180eb6f0de0SAdrian Chadd /* 3181eb6f0de0SAdrian Chadd * If cleanup is required, defer TID scheduling 3182eb6f0de0SAdrian Chadd * until all the HW queued packets have been 3183eb6f0de0SAdrian Chadd * sent. 3184eb6f0de0SAdrian Chadd */ 3185eb6f0de0SAdrian Chadd if (! atid->cleanup_inprogress) 3186eb6f0de0SAdrian Chadd ath_tx_tid_resume(sc, atid); 3187eb6f0de0SAdrian Chadd 3188eb6f0de0SAdrian Chadd if (atid->cleanup_inprogress) 3189eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3190eb6f0de0SAdrian Chadd "%s: TID %d: cleanup needed: %d packets\n", 3191eb6f0de0SAdrian Chadd __func__, tid, atid->incomp); 3192eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3193eb6f0de0SAdrian Chadd 3194eb6f0de0SAdrian Chadd /* Handle completing frames and fail them */ 3195eb6f0de0SAdrian Chadd while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3196eb6f0de0SAdrian Chadd TAILQ_REMOVE(&bf_cq, bf, bf_list); 3197eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, 1); 3198eb6f0de0SAdrian Chadd } 3199eb6f0de0SAdrian Chadd } 3200eb6f0de0SAdrian Chadd 3201eb6f0de0SAdrian Chadd static void 3202eb6f0de0SAdrian Chadd ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) 3203eb6f0de0SAdrian Chadd { 3204eb6f0de0SAdrian Chadd struct ieee80211_frame *wh; 3205eb6f0de0SAdrian Chadd 3206eb6f0de0SAdrian Chadd wh = mtod(bf->bf_m, struct ieee80211_frame *); 3207eb6f0de0SAdrian Chadd /* Only update/resync if needed */ 3208eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_isretried == 0) { 3209eb6f0de0SAdrian Chadd wh->i_fc[1] |= IEEE80211_FC1_RETRY; 3210eb6f0de0SAdrian Chadd bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3211eb6f0de0SAdrian Chadd BUS_DMASYNC_PREWRITE); 3212eb6f0de0SAdrian Chadd } 3213eb6f0de0SAdrian Chadd sc->sc_stats.ast_tx_swretries++; 3214eb6f0de0SAdrian Chadd bf->bf_state.bfs_isretried = 1; 3215eb6f0de0SAdrian Chadd bf->bf_state.bfs_retries ++; 3216eb6f0de0SAdrian Chadd } 3217eb6f0de0SAdrian Chadd 3218eb6f0de0SAdrian Chadd static struct ath_buf * 321938962489SAdrian Chadd ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an, 322038962489SAdrian Chadd struct ath_tid *tid, struct ath_buf *bf) 3221eb6f0de0SAdrian Chadd { 3222eb6f0de0SAdrian Chadd struct ath_buf *nbf; 3223eb6f0de0SAdrian Chadd int error; 3224eb6f0de0SAdrian Chadd 3225eb6f0de0SAdrian Chadd nbf = ath_buf_clone(sc, bf); 3226eb6f0de0SAdrian Chadd 3227eb6f0de0SAdrian Chadd #if 0 3228eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n", 3229eb6f0de0SAdrian Chadd __func__); 3230eb6f0de0SAdrian Chadd #endif 3231eb6f0de0SAdrian Chadd 3232eb6f0de0SAdrian Chadd if (nbf == NULL) { 3233eb6f0de0SAdrian Chadd /* Failed to clone */ 3234eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 3235eb6f0de0SAdrian Chadd "%s: failed to clone a busy buffer\n", 3236eb6f0de0SAdrian Chadd __func__); 3237eb6f0de0SAdrian Chadd return NULL; 3238eb6f0de0SAdrian Chadd } 3239eb6f0de0SAdrian Chadd 3240eb6f0de0SAdrian Chadd /* Setup the dma for the new buffer */ 3241eb6f0de0SAdrian Chadd error = ath_tx_dmasetup(sc, nbf, nbf->bf_m); 3242eb6f0de0SAdrian Chadd if (error != 0) { 3243eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 3244eb6f0de0SAdrian Chadd "%s: failed to setup dma for clone\n", 3245eb6f0de0SAdrian Chadd __func__); 3246eb6f0de0SAdrian Chadd /* 3247eb6f0de0SAdrian Chadd * Put this at the head of the list, not tail; 3248eb6f0de0SAdrian Chadd * that way it doesn't interfere with the 3249eb6f0de0SAdrian Chadd * busy buffer logic (which uses the tail of 3250eb6f0de0SAdrian Chadd * the list.) 3251eb6f0de0SAdrian Chadd */ 3252eb6f0de0SAdrian Chadd ATH_TXBUF_LOCK(sc); 325332c387f7SAdrian Chadd ath_returnbuf_head(sc, nbf); 3254eb6f0de0SAdrian Chadd ATH_TXBUF_UNLOCK(sc); 3255eb6f0de0SAdrian Chadd return NULL; 3256eb6f0de0SAdrian Chadd } 3257eb6f0de0SAdrian Chadd 325838962489SAdrian Chadd /* Update BAW if required, before we free the original buf */ 325938962489SAdrian Chadd if (bf->bf_state.bfs_dobaw) 326038962489SAdrian Chadd ath_tx_switch_baw_buf(sc, an, tid, bf, nbf); 326138962489SAdrian Chadd 3262eb6f0de0SAdrian Chadd /* Free current buffer; return the older buffer */ 3263eb6f0de0SAdrian Chadd bf->bf_m = NULL; 3264eb6f0de0SAdrian Chadd bf->bf_node = NULL; 3265eb6f0de0SAdrian Chadd ath_freebuf(sc, bf); 3266eb6f0de0SAdrian Chadd return nbf; 3267eb6f0de0SAdrian Chadd } 3268eb6f0de0SAdrian Chadd 3269eb6f0de0SAdrian Chadd /* 3270eb6f0de0SAdrian Chadd * Handle retrying an unaggregate frame in an aggregate 3271eb6f0de0SAdrian Chadd * session. 3272eb6f0de0SAdrian Chadd * 3273eb6f0de0SAdrian Chadd * If too many retries occur, pause the TID, wait for 3274eb6f0de0SAdrian Chadd * any further retransmits (as there's no reason why 3275eb6f0de0SAdrian Chadd * non-aggregate frames in an aggregate session are 3276eb6f0de0SAdrian Chadd * transmitted in-order; they just have to be in-BAW) 3277eb6f0de0SAdrian Chadd * and then queue a BAR. 3278eb6f0de0SAdrian Chadd */ 3279eb6f0de0SAdrian Chadd static void 3280eb6f0de0SAdrian Chadd ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf) 3281eb6f0de0SAdrian Chadd { 3282eb6f0de0SAdrian Chadd struct ieee80211_node *ni = bf->bf_node; 3283eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 3284eb6f0de0SAdrian Chadd int tid = bf->bf_state.bfs_tid; 3285eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 3286eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 3287eb6f0de0SAdrian Chadd 3288eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3289eb6f0de0SAdrian Chadd 3290eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid); 3291eb6f0de0SAdrian Chadd 3292eb6f0de0SAdrian Chadd /* 3293eb6f0de0SAdrian Chadd * If the buffer is marked as busy, we can't directly 3294eb6f0de0SAdrian Chadd * reuse it. Instead, try to clone the buffer. 3295eb6f0de0SAdrian Chadd * If the clone is successful, recycle the old buffer. 3296eb6f0de0SAdrian Chadd * If the clone is unsuccessful, set bfs_retries to max 3297eb6f0de0SAdrian Chadd * to force the next bit of code to free the buffer 3298eb6f0de0SAdrian Chadd * for us. 3299eb6f0de0SAdrian Chadd */ 3300eb6f0de0SAdrian Chadd if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3301eb6f0de0SAdrian Chadd (bf->bf_flags & ATH_BUF_BUSY)) { 3302eb6f0de0SAdrian Chadd struct ath_buf *nbf; 330338962489SAdrian Chadd nbf = ath_tx_retry_clone(sc, an, atid, bf); 3304eb6f0de0SAdrian Chadd if (nbf) 3305eb6f0de0SAdrian Chadd /* bf has been freed at this point */ 3306eb6f0de0SAdrian Chadd bf = nbf; 3307eb6f0de0SAdrian Chadd else 3308eb6f0de0SAdrian Chadd bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3309eb6f0de0SAdrian Chadd } 3310eb6f0de0SAdrian Chadd 3311eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3312eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3313eb6f0de0SAdrian Chadd "%s: exceeded retries; seqno %d\n", 3314eb6f0de0SAdrian Chadd __func__, SEQNO(bf->bf_state.bfs_seqno)); 3315eb6f0de0SAdrian Chadd sc->sc_stats.ast_tx_swretrymax++; 3316eb6f0de0SAdrian Chadd 3317eb6f0de0SAdrian Chadd /* Update BAW anyway */ 3318eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_dobaw) { 3319eb6f0de0SAdrian Chadd ath_tx_update_baw(sc, an, atid, bf); 3320eb6f0de0SAdrian Chadd if (! bf->bf_state.bfs_addedbaw) 3321eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 3322eb6f0de0SAdrian Chadd "%s: wasn't added: seqno %d\n", 3323eb6f0de0SAdrian Chadd __func__, SEQNO(bf->bf_state.bfs_seqno)); 3324eb6f0de0SAdrian Chadd } 3325eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw = 0; 3326eb6f0de0SAdrian Chadd 332788b3d483SAdrian Chadd /* Suspend the TX queue and get ready to send the BAR */ 332888b3d483SAdrian Chadd ath_tx_tid_bar_suspend(sc, atid); 332988b3d483SAdrian Chadd 333088b3d483SAdrian Chadd /* Send the BAR if there are no other frames waiting */ 333188b3d483SAdrian Chadd if (ath_tx_tid_bar_tx_ready(sc, atid)) 333288b3d483SAdrian Chadd ath_tx_tid_bar_tx(sc, atid); 333388b3d483SAdrian Chadd 3334eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3335eb6f0de0SAdrian Chadd 3336eb6f0de0SAdrian Chadd /* Free buffer, bf is free after this call */ 3337eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, 0); 3338eb6f0de0SAdrian Chadd return; 3339eb6f0de0SAdrian Chadd } 3340eb6f0de0SAdrian Chadd 3341eb6f0de0SAdrian Chadd /* 3342eb6f0de0SAdrian Chadd * This increments the retry counter as well as 3343eb6f0de0SAdrian Chadd * sets the retry flag in the ath_buf and packet 3344eb6f0de0SAdrian Chadd * body. 3345eb6f0de0SAdrian Chadd */ 3346eb6f0de0SAdrian Chadd ath_tx_set_retry(sc, bf); 3347eb6f0de0SAdrian Chadd 3348eb6f0de0SAdrian Chadd /* 3349eb6f0de0SAdrian Chadd * Insert this at the head of the queue, so it's 3350eb6f0de0SAdrian Chadd * retried before any current/subsequent frames. 3351eb6f0de0SAdrian Chadd */ 3352eb6f0de0SAdrian Chadd ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3353eb6f0de0SAdrian Chadd ath_tx_tid_sched(sc, atid); 335488b3d483SAdrian Chadd /* Send the BAR if there are no other frames waiting */ 335588b3d483SAdrian Chadd if (ath_tx_tid_bar_tx_ready(sc, atid)) 335688b3d483SAdrian Chadd ath_tx_tid_bar_tx(sc, atid); 3357eb6f0de0SAdrian Chadd 3358eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3359eb6f0de0SAdrian Chadd } 3360eb6f0de0SAdrian Chadd 3361eb6f0de0SAdrian Chadd /* 3362eb6f0de0SAdrian Chadd * Common code for aggregate excessive retry/subframe retry. 3363eb6f0de0SAdrian Chadd * If retrying, queues buffers to bf_q. If not, frees the 3364eb6f0de0SAdrian Chadd * buffers. 3365eb6f0de0SAdrian Chadd * 3366eb6f0de0SAdrian Chadd * XXX should unify this with ath_tx_aggr_retry_unaggr() 3367eb6f0de0SAdrian Chadd */ 3368eb6f0de0SAdrian Chadd static int 3369eb6f0de0SAdrian Chadd ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf, 3370eb6f0de0SAdrian Chadd ath_bufhead *bf_q) 3371eb6f0de0SAdrian Chadd { 3372eb6f0de0SAdrian Chadd struct ieee80211_node *ni = bf->bf_node; 3373eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 3374eb6f0de0SAdrian Chadd int tid = bf->bf_state.bfs_tid; 3375eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 3376eb6f0de0SAdrian Chadd 3377eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(sc->sc_ac2q[atid->ac]); 3378eb6f0de0SAdrian Chadd 3379eb6f0de0SAdrian Chadd ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3380eb6f0de0SAdrian Chadd ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0); 3381eb6f0de0SAdrian Chadd /* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */ 3382eb6f0de0SAdrian Chadd 3383eb6f0de0SAdrian Chadd /* 3384eb6f0de0SAdrian Chadd * If the buffer is marked as busy, we can't directly 3385eb6f0de0SAdrian Chadd * reuse it. Instead, try to clone the buffer. 3386eb6f0de0SAdrian Chadd * If the clone is successful, recycle the old buffer. 3387eb6f0de0SAdrian Chadd * If the clone is unsuccessful, set bfs_retries to max 3388eb6f0de0SAdrian Chadd * to force the next bit of code to free the buffer 3389eb6f0de0SAdrian Chadd * for us. 3390eb6f0de0SAdrian Chadd */ 3391eb6f0de0SAdrian Chadd if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) && 3392eb6f0de0SAdrian Chadd (bf->bf_flags & ATH_BUF_BUSY)) { 3393eb6f0de0SAdrian Chadd struct ath_buf *nbf; 339438962489SAdrian Chadd nbf = ath_tx_retry_clone(sc, an, atid, bf); 3395eb6f0de0SAdrian Chadd if (nbf) 3396eb6f0de0SAdrian Chadd /* bf has been freed at this point */ 3397eb6f0de0SAdrian Chadd bf = nbf; 3398eb6f0de0SAdrian Chadd else 3399eb6f0de0SAdrian Chadd bf->bf_state.bfs_retries = SWMAX_RETRIES + 1; 3400eb6f0de0SAdrian Chadd } 3401eb6f0de0SAdrian Chadd 3402eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) { 3403eb6f0de0SAdrian Chadd sc->sc_stats.ast_tx_swretrymax++; 3404eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES, 3405eb6f0de0SAdrian Chadd "%s: max retries: seqno %d\n", 3406eb6f0de0SAdrian Chadd __func__, SEQNO(bf->bf_state.bfs_seqno)); 3407eb6f0de0SAdrian Chadd ath_tx_update_baw(sc, an, atid, bf); 3408eb6f0de0SAdrian Chadd if (! bf->bf_state.bfs_addedbaw) 3409eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 3410eb6f0de0SAdrian Chadd "%s: wasn't added: seqno %d\n", 3411eb6f0de0SAdrian Chadd __func__, SEQNO(bf->bf_state.bfs_seqno)); 3412eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw = 0; 3413eb6f0de0SAdrian Chadd return 1; 3414eb6f0de0SAdrian Chadd } 3415eb6f0de0SAdrian Chadd 3416eb6f0de0SAdrian Chadd ath_tx_set_retry(sc, bf); 3417eb6f0de0SAdrian Chadd bf->bf_next = NULL; /* Just to make sure */ 3418eb6f0de0SAdrian Chadd 3419eb6f0de0SAdrian Chadd TAILQ_INSERT_TAIL(bf_q, bf, bf_list); 3420eb6f0de0SAdrian Chadd return 0; 3421eb6f0de0SAdrian Chadd } 3422eb6f0de0SAdrian Chadd 3423eb6f0de0SAdrian Chadd /* 3424eb6f0de0SAdrian Chadd * error pkt completion for an aggregate destination 3425eb6f0de0SAdrian Chadd */ 3426eb6f0de0SAdrian Chadd static void 3427eb6f0de0SAdrian Chadd ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first, 3428eb6f0de0SAdrian Chadd struct ath_tid *tid) 3429eb6f0de0SAdrian Chadd { 3430eb6f0de0SAdrian Chadd struct ieee80211_node *ni = bf_first->bf_node; 3431eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 3432eb6f0de0SAdrian Chadd struct ath_buf *bf_next, *bf; 3433eb6f0de0SAdrian Chadd ath_bufhead bf_q; 3434eb6f0de0SAdrian Chadd int drops = 0; 3435eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 3436eb6f0de0SAdrian Chadd ath_bufhead bf_cq; 3437eb6f0de0SAdrian Chadd 3438eb6f0de0SAdrian Chadd TAILQ_INIT(&bf_q); 3439eb6f0de0SAdrian Chadd TAILQ_INIT(&bf_cq); 3440eb6f0de0SAdrian Chadd 3441eb6f0de0SAdrian Chadd /* 3442eb6f0de0SAdrian Chadd * Update rate control - all frames have failed. 3443eb6f0de0SAdrian Chadd * 3444eb6f0de0SAdrian Chadd * XXX use the length in the first frame in the series; 3445eb6f0de0SAdrian Chadd * XXX just so things are consistent for now. 3446eb6f0de0SAdrian Chadd */ 3447eb6f0de0SAdrian Chadd ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc, 3448eb6f0de0SAdrian Chadd &bf_first->bf_status.ds_txstat, 3449eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_pktlen, 3450eb6f0de0SAdrian Chadd bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes); 3451eb6f0de0SAdrian Chadd 3452eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[tid->ac]); 3453eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid->tid); 34542d3d4776SAdrian Chadd sc->sc_stats.ast_tx_aggr_failall++; 3455eb6f0de0SAdrian Chadd 3456eb6f0de0SAdrian Chadd /* Retry all subframes */ 3457eb6f0de0SAdrian Chadd bf = bf_first; 3458eb6f0de0SAdrian Chadd while (bf) { 3459eb6f0de0SAdrian Chadd bf_next = bf->bf_next; 3460eb6f0de0SAdrian Chadd bf->bf_next = NULL; /* Remove it from the aggr list */ 34612d3d4776SAdrian Chadd sc->sc_stats.ast_tx_aggr_fail++; 3462eb6f0de0SAdrian Chadd if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 3463eb6f0de0SAdrian Chadd drops++; 3464eb6f0de0SAdrian Chadd bf->bf_next = NULL; 3465eb6f0de0SAdrian Chadd TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3466eb6f0de0SAdrian Chadd } 3467eb6f0de0SAdrian Chadd bf = bf_next; 3468eb6f0de0SAdrian Chadd } 3469eb6f0de0SAdrian Chadd 3470eb6f0de0SAdrian Chadd /* Prepend all frames to the beginning of the queue */ 3471eb6f0de0SAdrian Chadd while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 3472eb6f0de0SAdrian Chadd TAILQ_REMOVE(&bf_q, bf, bf_list); 3473eb6f0de0SAdrian Chadd ATH_TXQ_INSERT_HEAD(tid, bf, bf_list); 3474eb6f0de0SAdrian Chadd } 3475eb6f0de0SAdrian Chadd 347639da9d42SAdrian Chadd /* 347739da9d42SAdrian Chadd * Schedule the TID to be re-tried. 347839da9d42SAdrian Chadd */ 3479eb6f0de0SAdrian Chadd ath_tx_tid_sched(sc, tid); 3480eb6f0de0SAdrian Chadd 3481eb6f0de0SAdrian Chadd /* 3482eb6f0de0SAdrian Chadd * send bar if we dropped any frames 3483eb6f0de0SAdrian Chadd * 3484eb6f0de0SAdrian Chadd * Keep the txq lock held for now, as we need to ensure 3485eb6f0de0SAdrian Chadd * that ni_txseqs[] is consistent (as it's being updated 3486eb6f0de0SAdrian Chadd * in the ifnet TX context or raw TX context.) 3487eb6f0de0SAdrian Chadd */ 3488eb6f0de0SAdrian Chadd if (drops) { 348988b3d483SAdrian Chadd /* Suspend the TX queue and get ready to send the BAR */ 349088b3d483SAdrian Chadd ath_tx_tid_bar_suspend(sc, tid); 3491eb6f0de0SAdrian Chadd } 3492eb6f0de0SAdrian Chadd 349388b3d483SAdrian Chadd /* 349488b3d483SAdrian Chadd * Send BAR if required 349588b3d483SAdrian Chadd */ 349688b3d483SAdrian Chadd if (ath_tx_tid_bar_tx_ready(sc, tid)) 349788b3d483SAdrian Chadd ath_tx_tid_bar_tx(sc, tid); 349888b3d483SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[tid->ac]); 349988b3d483SAdrian Chadd 3500eb6f0de0SAdrian Chadd /* Complete frames which errored out */ 3501eb6f0de0SAdrian Chadd while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3502eb6f0de0SAdrian Chadd TAILQ_REMOVE(&bf_cq, bf, bf_list); 3503eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, 0); 3504eb6f0de0SAdrian Chadd } 3505eb6f0de0SAdrian Chadd } 3506eb6f0de0SAdrian Chadd 3507eb6f0de0SAdrian Chadd /* 3508eb6f0de0SAdrian Chadd * Handle clean-up of packets from an aggregate list. 3509eb6f0de0SAdrian Chadd * 3510eb6f0de0SAdrian Chadd * There's no need to update the BAW here - the session is being 3511eb6f0de0SAdrian Chadd * torn down. 3512eb6f0de0SAdrian Chadd */ 3513eb6f0de0SAdrian Chadd static void 3514eb6f0de0SAdrian Chadd ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first) 3515eb6f0de0SAdrian Chadd { 3516eb6f0de0SAdrian Chadd struct ath_buf *bf, *bf_next; 3517eb6f0de0SAdrian Chadd struct ieee80211_node *ni = bf_first->bf_node; 3518eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 3519eb6f0de0SAdrian Chadd int tid = bf_first->bf_state.bfs_tid; 3520eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 3521eb6f0de0SAdrian Chadd 3522eb6f0de0SAdrian Chadd bf = bf_first; 3523eb6f0de0SAdrian Chadd 3524eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3525eb6f0de0SAdrian Chadd 3526eb6f0de0SAdrian Chadd /* update incomp */ 3527eb6f0de0SAdrian Chadd while (bf) { 3528eb6f0de0SAdrian Chadd atid->incomp--; 3529eb6f0de0SAdrian Chadd bf = bf->bf_next; 3530eb6f0de0SAdrian Chadd } 3531eb6f0de0SAdrian Chadd 3532eb6f0de0SAdrian Chadd if (atid->incomp == 0) { 3533eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 3534eb6f0de0SAdrian Chadd "%s: TID %d: cleaned up! resume!\n", 3535eb6f0de0SAdrian Chadd __func__, tid); 3536eb6f0de0SAdrian Chadd atid->cleanup_inprogress = 0; 3537eb6f0de0SAdrian Chadd ath_tx_tid_resume(sc, atid); 3538eb6f0de0SAdrian Chadd } 353988b3d483SAdrian Chadd 354088b3d483SAdrian Chadd /* Send BAR if required */ 354188b3d483SAdrian Chadd if (ath_tx_tid_bar_tx_ready(sc, atid)) 354288b3d483SAdrian Chadd ath_tx_tid_bar_tx(sc, atid); 3543eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3544eb6f0de0SAdrian Chadd 3545eb6f0de0SAdrian Chadd /* Handle frame completion */ 3546eb6f0de0SAdrian Chadd while (bf) { 3547eb6f0de0SAdrian Chadd bf_next = bf->bf_next; 3548eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, 1); 3549eb6f0de0SAdrian Chadd bf = bf_next; 3550eb6f0de0SAdrian Chadd } 3551eb6f0de0SAdrian Chadd } 3552eb6f0de0SAdrian Chadd 3553eb6f0de0SAdrian Chadd /* 3554eb6f0de0SAdrian Chadd * Handle completion of an set of aggregate frames. 3555eb6f0de0SAdrian Chadd * 3556eb6f0de0SAdrian Chadd * XXX for now, simply complete each sub-frame. 3557eb6f0de0SAdrian Chadd * 3558eb6f0de0SAdrian Chadd * Note: the completion handler is the last descriptor in the aggregate, 3559eb6f0de0SAdrian Chadd * not the last descriptor in the first frame. 3560eb6f0de0SAdrian Chadd */ 3561eb6f0de0SAdrian Chadd static void 3562d4365d16SAdrian Chadd ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first, 3563d4365d16SAdrian Chadd int fail) 3564eb6f0de0SAdrian Chadd { 3565eb6f0de0SAdrian Chadd //struct ath_desc *ds = bf->bf_lastds; 3566eb6f0de0SAdrian Chadd struct ieee80211_node *ni = bf_first->bf_node; 3567eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 3568eb6f0de0SAdrian Chadd int tid = bf_first->bf_state.bfs_tid; 3569eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 3570eb6f0de0SAdrian Chadd struct ath_tx_status ts; 3571eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 3572eb6f0de0SAdrian Chadd ath_bufhead bf_q; 3573eb6f0de0SAdrian Chadd ath_bufhead bf_cq; 3574eb6f0de0SAdrian Chadd int seq_st, tx_ok; 3575eb6f0de0SAdrian Chadd int hasba, isaggr; 3576eb6f0de0SAdrian Chadd uint32_t ba[2]; 3577eb6f0de0SAdrian Chadd struct ath_buf *bf, *bf_next; 3578eb6f0de0SAdrian Chadd int ba_index; 3579eb6f0de0SAdrian Chadd int drops = 0; 3580eb6f0de0SAdrian Chadd int nframes = 0, nbad = 0, nf; 3581eb6f0de0SAdrian Chadd int pktlen; 3582eb6f0de0SAdrian Chadd /* XXX there's too much on the stack? */ 3583b815538dSAdrian Chadd struct ath_rc_series rc[ATH_RC_NUM]; 3584eb6f0de0SAdrian Chadd int txseq; 3585eb6f0de0SAdrian Chadd 3586eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n", 3587eb6f0de0SAdrian Chadd __func__, atid->hwq_depth); 3588eb6f0de0SAdrian Chadd 3589eb6f0de0SAdrian Chadd /* The TID state is kept behind the TXQ lock */ 3590eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3591eb6f0de0SAdrian Chadd 3592eb6f0de0SAdrian Chadd atid->hwq_depth--; 3593eb6f0de0SAdrian Chadd if (atid->hwq_depth < 0) 3594eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3595eb6f0de0SAdrian Chadd __func__, atid->hwq_depth); 3596eb6f0de0SAdrian Chadd 3597eb6f0de0SAdrian Chadd /* 3598eb6f0de0SAdrian Chadd * Punt cleanup to the relevant function, not our problem now 3599eb6f0de0SAdrian Chadd */ 3600eb6f0de0SAdrian Chadd if (atid->cleanup_inprogress) { 3601eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3602eb6f0de0SAdrian Chadd ath_tx_comp_cleanup_aggr(sc, bf_first); 3603eb6f0de0SAdrian Chadd return; 3604eb6f0de0SAdrian Chadd } 3605eb6f0de0SAdrian Chadd 3606eb6f0de0SAdrian Chadd /* 3607eb6f0de0SAdrian Chadd * Take a copy; this may be needed -after- bf_first 3608eb6f0de0SAdrian Chadd * has been completed and freed. 3609eb6f0de0SAdrian Chadd */ 3610eb6f0de0SAdrian Chadd ts = bf_first->bf_status.ds_txstat; 3611eb6f0de0SAdrian Chadd /* 3612eb6f0de0SAdrian Chadd * XXX for now, use the first frame in the aggregate for 3613eb6f0de0SAdrian Chadd * XXX rate control completion; it's at least consistent. 3614eb6f0de0SAdrian Chadd */ 3615eb6f0de0SAdrian Chadd pktlen = bf_first->bf_state.bfs_pktlen; 3616eb6f0de0SAdrian Chadd 3617eb6f0de0SAdrian Chadd /* 3618e9a6408eSAdrian Chadd * Handle errors first! 3619e9a6408eSAdrian Chadd * 3620e9a6408eSAdrian Chadd * Here, handle _any_ error as a "exceeded retries" error. 3621e9a6408eSAdrian Chadd * Later on (when filtered frames are to be specially handled) 3622e9a6408eSAdrian Chadd * it'll have to be expanded. 3623eb6f0de0SAdrian Chadd */ 3624e9a6408eSAdrian Chadd #if 0 3625eb6f0de0SAdrian Chadd if (ts.ts_status & HAL_TXERR_XRETRY) { 3626e9a6408eSAdrian Chadd #endif 3627e9a6408eSAdrian Chadd if (ts.ts_status != 0) { 3628eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3629eb6f0de0SAdrian Chadd ath_tx_comp_aggr_error(sc, bf_first, atid); 3630eb6f0de0SAdrian Chadd return; 3631eb6f0de0SAdrian Chadd } 3632eb6f0de0SAdrian Chadd 3633eb6f0de0SAdrian Chadd TAILQ_INIT(&bf_q); 3634eb6f0de0SAdrian Chadd TAILQ_INIT(&bf_cq); 3635eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid); 3636eb6f0de0SAdrian Chadd 3637eb6f0de0SAdrian Chadd /* 3638eb6f0de0SAdrian Chadd * extract starting sequence and block-ack bitmap 3639eb6f0de0SAdrian Chadd */ 3640eb6f0de0SAdrian Chadd /* XXX endian-ness of seq_st, ba? */ 3641eb6f0de0SAdrian Chadd seq_st = ts.ts_seqnum; 3642eb6f0de0SAdrian Chadd hasba = !! (ts.ts_flags & HAL_TX_BA); 3643eb6f0de0SAdrian Chadd tx_ok = (ts.ts_status == 0); 3644eb6f0de0SAdrian Chadd isaggr = bf_first->bf_state.bfs_aggr; 3645eb6f0de0SAdrian Chadd ba[0] = ts.ts_ba_low; 3646eb6f0de0SAdrian Chadd ba[1] = ts.ts_ba_high; 3647eb6f0de0SAdrian Chadd 3648eb6f0de0SAdrian Chadd /* 3649eb6f0de0SAdrian Chadd * Copy the TX completion status and the rate control 3650eb6f0de0SAdrian Chadd * series from the first descriptor, as it may be freed 3651eb6f0de0SAdrian Chadd * before the rate control code can get its grubby fingers 3652eb6f0de0SAdrian Chadd * into things. 3653eb6f0de0SAdrian Chadd */ 3654eb6f0de0SAdrian Chadd memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc)); 3655eb6f0de0SAdrian Chadd 3656eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3657d4365d16SAdrian Chadd "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, " 3658d4365d16SAdrian Chadd "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n", 3659eb6f0de0SAdrian Chadd __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags, 3660eb6f0de0SAdrian Chadd isaggr, seq_st, hasba, ba[0], ba[1]); 3661eb6f0de0SAdrian Chadd 3662eb6f0de0SAdrian Chadd /* Occasionally, the MAC sends a tx status for the wrong TID. */ 3663eb6f0de0SAdrian Chadd if (tid != ts.ts_tid) { 3664eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n", 3665eb6f0de0SAdrian Chadd __func__, tid, ts.ts_tid); 3666eb6f0de0SAdrian Chadd tx_ok = 0; 3667eb6f0de0SAdrian Chadd } 3668eb6f0de0SAdrian Chadd 3669eb6f0de0SAdrian Chadd /* AR5416 BA bug; this requires an interface reset */ 3670eb6f0de0SAdrian Chadd if (isaggr && tx_ok && (! hasba)) { 3671eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 3672d4365d16SAdrian Chadd "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, " 3673d4365d16SAdrian Chadd "seq_st=%d\n", 3674eb6f0de0SAdrian Chadd __func__, hasba, tx_ok, isaggr, seq_st); 3675eb6f0de0SAdrian Chadd /* XXX TODO: schedule an interface reset */ 36760f078d63SJohn Baldwin #ifdef ATH_DEBUG 36776abbbae5SAdrian Chadd ath_printtxbuf(sc, bf_first, 36786abbbae5SAdrian Chadd sc->sc_ac2q[atid->ac]->axq_qnum, 0, 0); 36790f078d63SJohn Baldwin #endif 3680eb6f0de0SAdrian Chadd } 3681eb6f0de0SAdrian Chadd 3682eb6f0de0SAdrian Chadd /* 3683eb6f0de0SAdrian Chadd * Walk the list of frames, figure out which ones were correctly 3684eb6f0de0SAdrian Chadd * sent and which weren't. 3685eb6f0de0SAdrian Chadd */ 3686eb6f0de0SAdrian Chadd bf = bf_first; 3687eb6f0de0SAdrian Chadd nf = bf_first->bf_state.bfs_nframes; 3688eb6f0de0SAdrian Chadd 3689eb6f0de0SAdrian Chadd /* bf_first is going to be invalid once this list is walked */ 3690eb6f0de0SAdrian Chadd bf_first = NULL; 3691eb6f0de0SAdrian Chadd 3692eb6f0de0SAdrian Chadd /* 3693eb6f0de0SAdrian Chadd * Walk the list of completed frames and determine 3694eb6f0de0SAdrian Chadd * which need to be completed and which need to be 3695eb6f0de0SAdrian Chadd * retransmitted. 3696eb6f0de0SAdrian Chadd * 3697eb6f0de0SAdrian Chadd * For completed frames, the completion functions need 3698eb6f0de0SAdrian Chadd * to be called at the end of this function as the last 3699eb6f0de0SAdrian Chadd * node reference may free the node. 3700eb6f0de0SAdrian Chadd * 3701eb6f0de0SAdrian Chadd * Finally, since the TXQ lock can't be held during the 3702eb6f0de0SAdrian Chadd * completion callback (to avoid lock recursion), 3703eb6f0de0SAdrian Chadd * the completion calls have to be done outside of the 3704eb6f0de0SAdrian Chadd * lock. 3705eb6f0de0SAdrian Chadd */ 3706eb6f0de0SAdrian Chadd while (bf) { 3707eb6f0de0SAdrian Chadd nframes++; 3708d4365d16SAdrian Chadd ba_index = ATH_BA_INDEX(seq_st, 3709d4365d16SAdrian Chadd SEQNO(bf->bf_state.bfs_seqno)); 3710eb6f0de0SAdrian Chadd bf_next = bf->bf_next; 3711eb6f0de0SAdrian Chadd bf->bf_next = NULL; /* Remove it from the aggr list */ 3712eb6f0de0SAdrian Chadd 3713eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3714eb6f0de0SAdrian Chadd "%s: checking bf=%p seqno=%d; ack=%d\n", 3715eb6f0de0SAdrian Chadd __func__, bf, SEQNO(bf->bf_state.bfs_seqno), 3716eb6f0de0SAdrian Chadd ATH_BA_ISSET(ba, ba_index)); 3717eb6f0de0SAdrian Chadd 3718eb6f0de0SAdrian Chadd if (tx_ok && ATH_BA_ISSET(ba, ba_index)) { 37192d3d4776SAdrian Chadd sc->sc_stats.ast_tx_aggr_ok++; 3720eb6f0de0SAdrian Chadd ath_tx_update_baw(sc, an, atid, bf); 3721eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw = 0; 3722eb6f0de0SAdrian Chadd if (! bf->bf_state.bfs_addedbaw) 3723eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 3724eb6f0de0SAdrian Chadd "%s: wasn't added: seqno %d\n", 3725eb6f0de0SAdrian Chadd __func__, SEQNO(bf->bf_state.bfs_seqno)); 3726eb6f0de0SAdrian Chadd bf->bf_next = NULL; 3727eb6f0de0SAdrian Chadd TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3728eb6f0de0SAdrian Chadd } else { 37292d3d4776SAdrian Chadd sc->sc_stats.ast_tx_aggr_fail++; 3730eb6f0de0SAdrian Chadd if (ath_tx_retry_subframe(sc, bf, &bf_q)) { 3731eb6f0de0SAdrian Chadd drops++; 3732eb6f0de0SAdrian Chadd bf->bf_next = NULL; 3733eb6f0de0SAdrian Chadd TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list); 3734eb6f0de0SAdrian Chadd } 3735eb6f0de0SAdrian Chadd nbad++; 3736eb6f0de0SAdrian Chadd } 3737eb6f0de0SAdrian Chadd bf = bf_next; 3738eb6f0de0SAdrian Chadd } 3739eb6f0de0SAdrian Chadd 3740eb6f0de0SAdrian Chadd /* 3741eb6f0de0SAdrian Chadd * Now that the BAW updates have been done, unlock 3742eb6f0de0SAdrian Chadd * 3743eb6f0de0SAdrian Chadd * txseq is grabbed before the lock is released so we 3744eb6f0de0SAdrian Chadd * have a consistent view of what -was- in the BAW. 3745eb6f0de0SAdrian Chadd * Anything after this point will not yet have been 3746eb6f0de0SAdrian Chadd * TXed. 3747eb6f0de0SAdrian Chadd */ 3748eb6f0de0SAdrian Chadd txseq = tap->txa_start; 3749eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3750eb6f0de0SAdrian Chadd 3751eb6f0de0SAdrian Chadd if (nframes != nf) 3752eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 3753eb6f0de0SAdrian Chadd "%s: num frames seen=%d; bf nframes=%d\n", 3754eb6f0de0SAdrian Chadd __func__, nframes, nf); 3755eb6f0de0SAdrian Chadd 3756eb6f0de0SAdrian Chadd /* 3757eb6f0de0SAdrian Chadd * Now we know how many frames were bad, call the rate 3758eb6f0de0SAdrian Chadd * control code. 3759eb6f0de0SAdrian Chadd */ 3760eb6f0de0SAdrian Chadd if (fail == 0) 3761d4365d16SAdrian Chadd ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes, 3762d4365d16SAdrian Chadd nbad); 3763eb6f0de0SAdrian Chadd 3764eb6f0de0SAdrian Chadd /* 3765eb6f0de0SAdrian Chadd * send bar if we dropped any frames 3766eb6f0de0SAdrian Chadd */ 3767eb6f0de0SAdrian Chadd if (drops) { 376888b3d483SAdrian Chadd /* Suspend the TX queue and get ready to send the BAR */ 376988b3d483SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 377088b3d483SAdrian Chadd ath_tx_tid_bar_suspend(sc, atid); 377188b3d483SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3772eb6f0de0SAdrian Chadd } 3773eb6f0de0SAdrian Chadd 377439da9d42SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 377539da9d42SAdrian Chadd "%s: txa_start now %d\n", __func__, tap->txa_start); 377639da9d42SAdrian Chadd 3777eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 377839da9d42SAdrian Chadd 377939da9d42SAdrian Chadd /* Prepend all frames to the beginning of the queue */ 3780eb6f0de0SAdrian Chadd while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) { 3781eb6f0de0SAdrian Chadd TAILQ_REMOVE(&bf_q, bf, bf_list); 3782eb6f0de0SAdrian Chadd ATH_TXQ_INSERT_HEAD(atid, bf, bf_list); 3783eb6f0de0SAdrian Chadd } 3784eb6f0de0SAdrian Chadd 378539da9d42SAdrian Chadd /* 378639da9d42SAdrian Chadd * Reschedule to grab some further frames. 378739da9d42SAdrian Chadd */ 378839da9d42SAdrian Chadd ath_tx_tid_sched(sc, atid); 3789eb6f0de0SAdrian Chadd 379088b3d483SAdrian Chadd /* 379188b3d483SAdrian Chadd * Send BAR if required 379288b3d483SAdrian Chadd */ 379388b3d483SAdrian Chadd if (ath_tx_tid_bar_tx_ready(sc, atid)) 379488b3d483SAdrian Chadd ath_tx_tid_bar_tx(sc, atid); 379539da9d42SAdrian Chadd 379688b3d483SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 379788b3d483SAdrian Chadd 3798eb6f0de0SAdrian Chadd /* Do deferred completion */ 3799eb6f0de0SAdrian Chadd while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) { 3800eb6f0de0SAdrian Chadd TAILQ_REMOVE(&bf_cq, bf, bf_list); 3801eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, 0); 3802eb6f0de0SAdrian Chadd } 3803eb6f0de0SAdrian Chadd } 3804eb6f0de0SAdrian Chadd 3805eb6f0de0SAdrian Chadd /* 3806eb6f0de0SAdrian Chadd * Handle completion of unaggregated frames in an ADDBA 3807eb6f0de0SAdrian Chadd * session. 3808eb6f0de0SAdrian Chadd * 3809eb6f0de0SAdrian Chadd * Fail is set to 1 if the entry is being freed via a call to 3810eb6f0de0SAdrian Chadd * ath_tx_draintxq(). 3811eb6f0de0SAdrian Chadd */ 3812eb6f0de0SAdrian Chadd static void 3813eb6f0de0SAdrian Chadd ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail) 3814eb6f0de0SAdrian Chadd { 3815eb6f0de0SAdrian Chadd struct ieee80211_node *ni = bf->bf_node; 3816eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 3817eb6f0de0SAdrian Chadd int tid = bf->bf_state.bfs_tid; 3818eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 3819eb6f0de0SAdrian Chadd struct ath_tx_status *ts = &bf->bf_status.ds_txstat; 3820eb6f0de0SAdrian Chadd 3821eb6f0de0SAdrian Chadd /* 3822eb6f0de0SAdrian Chadd * Update rate control status here, before we possibly 3823eb6f0de0SAdrian Chadd * punt to retry or cleanup. 3824eb6f0de0SAdrian Chadd * 3825eb6f0de0SAdrian Chadd * Do it outside of the TXQ lock. 3826eb6f0de0SAdrian Chadd */ 3827875a9451SAdrian Chadd if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) 3828eb6f0de0SAdrian Chadd ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc, 3829eb6f0de0SAdrian Chadd &bf->bf_status.ds_txstat, 3830eb6f0de0SAdrian Chadd bf->bf_state.bfs_pktlen, 3831eb6f0de0SAdrian Chadd 1, (ts->ts_status == 0) ? 0 : 1); 3832eb6f0de0SAdrian Chadd 3833eb6f0de0SAdrian Chadd /* 3834eb6f0de0SAdrian Chadd * This is called early so atid->hwq_depth can be tracked. 3835eb6f0de0SAdrian Chadd * This unfortunately means that it's released and regrabbed 3836eb6f0de0SAdrian Chadd * during retry and cleanup. That's rather inefficient. 3837eb6f0de0SAdrian Chadd */ 3838eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 3839eb6f0de0SAdrian Chadd 3840eb6f0de0SAdrian Chadd if (tid == IEEE80211_NONQOS_TID) 3841eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: TID=16!\n", __func__); 3842eb6f0de0SAdrian Chadd 3843d4365d16SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, 3844d4365d16SAdrian Chadd "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n", 3845d4365d16SAdrian Chadd __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth, 3846d4365d16SAdrian Chadd SEQNO(bf->bf_state.bfs_seqno)); 3847eb6f0de0SAdrian Chadd 3848eb6f0de0SAdrian Chadd atid->hwq_depth--; 3849eb6f0de0SAdrian Chadd if (atid->hwq_depth < 0) 3850eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n", 3851eb6f0de0SAdrian Chadd __func__, atid->hwq_depth); 3852eb6f0de0SAdrian Chadd 3853eb6f0de0SAdrian Chadd /* 3854eb6f0de0SAdrian Chadd * If a cleanup is in progress, punt to comp_cleanup; 3855eb6f0de0SAdrian Chadd * rather than handling it here. It's thus their 3856eb6f0de0SAdrian Chadd * responsibility to clean up, call the completion 3857eb6f0de0SAdrian Chadd * function in net80211, etc. 3858eb6f0de0SAdrian Chadd */ 3859eb6f0de0SAdrian Chadd if (atid->cleanup_inprogress) { 3860eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3861d4365d16SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n", 3862d4365d16SAdrian Chadd __func__); 3863eb6f0de0SAdrian Chadd ath_tx_comp_cleanup_unaggr(sc, bf); 3864eb6f0de0SAdrian Chadd return; 3865eb6f0de0SAdrian Chadd } 3866eb6f0de0SAdrian Chadd 3867eb6f0de0SAdrian Chadd /* 3868eb6f0de0SAdrian Chadd * Don't bother with the retry check if all frames 3869eb6f0de0SAdrian Chadd * are being failed (eg during queue deletion.) 3870eb6f0de0SAdrian Chadd */ 3871e9a6408eSAdrian Chadd #if 0 3872eb6f0de0SAdrian Chadd if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) { 3873e9a6408eSAdrian Chadd #endif 3874e9a6408eSAdrian Chadd if (fail == 0 && ts->ts_status != 0) { 3875eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3876d4365d16SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n", 3877d4365d16SAdrian Chadd __func__); 3878eb6f0de0SAdrian Chadd ath_tx_aggr_retry_unaggr(sc, bf); 3879eb6f0de0SAdrian Chadd return; 3880eb6f0de0SAdrian Chadd } 3881eb6f0de0SAdrian Chadd 3882eb6f0de0SAdrian Chadd /* Success? Complete */ 3883eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n", 3884eb6f0de0SAdrian Chadd __func__, tid, SEQNO(bf->bf_state.bfs_seqno)); 3885eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_dobaw) { 3886eb6f0de0SAdrian Chadd ath_tx_update_baw(sc, an, atid, bf); 3887eb6f0de0SAdrian Chadd bf->bf_state.bfs_dobaw = 0; 3888eb6f0de0SAdrian Chadd if (! bf->bf_state.bfs_addedbaw) 3889eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, 3890eb6f0de0SAdrian Chadd "%s: wasn't added: seqno %d\n", 3891eb6f0de0SAdrian Chadd __func__, SEQNO(bf->bf_state.bfs_seqno)); 3892eb6f0de0SAdrian Chadd } 3893eb6f0de0SAdrian Chadd 389488b3d483SAdrian Chadd /* 389588b3d483SAdrian Chadd * Send BAR if required 389688b3d483SAdrian Chadd */ 389788b3d483SAdrian Chadd if (ath_tx_tid_bar_tx_ready(sc, atid)) 389888b3d483SAdrian Chadd ath_tx_tid_bar_tx(sc, atid); 389988b3d483SAdrian Chadd 3900eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 3901eb6f0de0SAdrian Chadd 3902eb6f0de0SAdrian Chadd ath_tx_default_comp(sc, bf, fail); 3903eb6f0de0SAdrian Chadd /* bf is freed at this point */ 3904eb6f0de0SAdrian Chadd } 3905eb6f0de0SAdrian Chadd 3906eb6f0de0SAdrian Chadd void 3907eb6f0de0SAdrian Chadd ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail) 3908eb6f0de0SAdrian Chadd { 3909eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_aggr) 3910eb6f0de0SAdrian Chadd ath_tx_aggr_comp_aggr(sc, bf, fail); 3911eb6f0de0SAdrian Chadd else 3912eb6f0de0SAdrian Chadd ath_tx_aggr_comp_unaggr(sc, bf, fail); 3913eb6f0de0SAdrian Chadd } 3914eb6f0de0SAdrian Chadd 3915eb6f0de0SAdrian Chadd /* 3916eb6f0de0SAdrian Chadd * Schedule some packets from the given node/TID to the hardware. 3917eb6f0de0SAdrian Chadd * 3918eb6f0de0SAdrian Chadd * This is the aggregate version. 3919eb6f0de0SAdrian Chadd */ 3920eb6f0de0SAdrian Chadd void 3921eb6f0de0SAdrian Chadd ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an, 3922eb6f0de0SAdrian Chadd struct ath_tid *tid) 3923eb6f0de0SAdrian Chadd { 3924eb6f0de0SAdrian Chadd struct ath_buf *bf; 3925eb6f0de0SAdrian Chadd struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 3926eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 3927eb6f0de0SAdrian Chadd ATH_AGGR_STATUS status; 3928eb6f0de0SAdrian Chadd ath_bufhead bf_q; 3929eb6f0de0SAdrian Chadd 3930eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid); 3931eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 3932eb6f0de0SAdrian Chadd 3933eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid->tid); 3934eb6f0de0SAdrian Chadd 3935eb6f0de0SAdrian Chadd if (tid->tid == IEEE80211_NONQOS_TID) 3936eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n", 3937eb6f0de0SAdrian Chadd __func__); 3938eb6f0de0SAdrian Chadd 3939eb6f0de0SAdrian Chadd for (;;) { 3940eb6f0de0SAdrian Chadd status = ATH_AGGR_DONE; 3941eb6f0de0SAdrian Chadd 3942eb6f0de0SAdrian Chadd /* 3943eb6f0de0SAdrian Chadd * If the upper layer has paused the TID, don't 3944eb6f0de0SAdrian Chadd * queue any further packets. 3945eb6f0de0SAdrian Chadd * 3946eb6f0de0SAdrian Chadd * This can also occur from the completion task because 3947eb6f0de0SAdrian Chadd * of packet loss; but as its serialised with this code, 3948eb6f0de0SAdrian Chadd * it won't "appear" half way through queuing packets. 3949eb6f0de0SAdrian Chadd */ 3950eb6f0de0SAdrian Chadd if (tid->paused) 3951eb6f0de0SAdrian Chadd break; 3952eb6f0de0SAdrian Chadd 3953eb6f0de0SAdrian Chadd bf = TAILQ_FIRST(&tid->axq_q); 3954eb6f0de0SAdrian Chadd if (bf == NULL) { 3955eb6f0de0SAdrian Chadd break; 3956eb6f0de0SAdrian Chadd } 3957eb6f0de0SAdrian Chadd 3958eb6f0de0SAdrian Chadd /* 3959eb6f0de0SAdrian Chadd * If the packet doesn't fall within the BAW (eg a NULL 3960eb6f0de0SAdrian Chadd * data frame), schedule it directly; continue. 3961eb6f0de0SAdrian Chadd */ 3962eb6f0de0SAdrian Chadd if (! bf->bf_state.bfs_dobaw) { 3963d4365d16SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 3964d4365d16SAdrian Chadd "%s: non-baw packet\n", 3965eb6f0de0SAdrian Chadd __func__); 3966eb6f0de0SAdrian Chadd ATH_TXQ_REMOVE(tid, bf, bf_list); 3967eb6f0de0SAdrian Chadd bf->bf_state.bfs_aggr = 0; 3968eb6f0de0SAdrian Chadd ath_tx_do_ratelookup(sc, bf); 3969e2e4a2c2SAdrian Chadd ath_tx_calc_duration(sc, bf); 3970e2e4a2c2SAdrian Chadd ath_tx_calc_protection(sc, bf); 3971eb6f0de0SAdrian Chadd ath_tx_set_rtscts(sc, bf); 3972e2e4a2c2SAdrian Chadd ath_tx_rate_fill_rcflags(sc, bf); 3973eb6f0de0SAdrian Chadd ath_tx_setds(sc, bf); 3974eb6f0de0SAdrian Chadd ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 3975eb6f0de0SAdrian Chadd 3976eb6f0de0SAdrian Chadd sc->sc_aggr_stats.aggr_nonbaw_pkt++; 3977eb6f0de0SAdrian Chadd 3978eb6f0de0SAdrian Chadd /* Queue the packet; continue */ 3979eb6f0de0SAdrian Chadd goto queuepkt; 3980eb6f0de0SAdrian Chadd } 3981eb6f0de0SAdrian Chadd 3982eb6f0de0SAdrian Chadd TAILQ_INIT(&bf_q); 3983eb6f0de0SAdrian Chadd 3984eb6f0de0SAdrian Chadd /* 3985eb6f0de0SAdrian Chadd * Do a rate control lookup on the first frame in the 3986eb6f0de0SAdrian Chadd * list. The rate control code needs that to occur 3987eb6f0de0SAdrian Chadd * before it can determine whether to TX. 3988eb6f0de0SAdrian Chadd * It's inaccurate because the rate control code doesn't 3989eb6f0de0SAdrian Chadd * really "do" aggregate lookups, so it only considers 3990eb6f0de0SAdrian Chadd * the size of the first frame. 3991eb6f0de0SAdrian Chadd */ 3992eb6f0de0SAdrian Chadd ath_tx_do_ratelookup(sc, bf); 3993eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[3].rix = 0; 3994eb6f0de0SAdrian Chadd bf->bf_state.bfs_rc[3].tries = 0; 3995e2e4a2c2SAdrian Chadd 3996e2e4a2c2SAdrian Chadd ath_tx_calc_duration(sc, bf); 3997e2e4a2c2SAdrian Chadd ath_tx_calc_protection(sc, bf); 3998e2e4a2c2SAdrian Chadd 3999e2e4a2c2SAdrian Chadd ath_tx_set_rtscts(sc, bf); 4000eb6f0de0SAdrian Chadd ath_tx_rate_fill_rcflags(sc, bf); 4001eb6f0de0SAdrian Chadd 4002eb6f0de0SAdrian Chadd status = ath_tx_form_aggr(sc, an, tid, &bf_q); 4003eb6f0de0SAdrian Chadd 4004eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4005eb6f0de0SAdrian Chadd "%s: ath_tx_form_aggr() status=%d\n", __func__, status); 4006eb6f0de0SAdrian Chadd 4007eb6f0de0SAdrian Chadd /* 4008eb6f0de0SAdrian Chadd * No frames to be picked up - out of BAW 4009eb6f0de0SAdrian Chadd */ 4010eb6f0de0SAdrian Chadd if (TAILQ_EMPTY(&bf_q)) 4011eb6f0de0SAdrian Chadd break; 4012eb6f0de0SAdrian Chadd 4013eb6f0de0SAdrian Chadd /* 4014eb6f0de0SAdrian Chadd * This assumes that the descriptor list in the ath_bufhead 4015eb6f0de0SAdrian Chadd * are already linked together via bf_next pointers. 4016eb6f0de0SAdrian Chadd */ 4017eb6f0de0SAdrian Chadd bf = TAILQ_FIRST(&bf_q); 4018eb6f0de0SAdrian Chadd 4019e2e4a2c2SAdrian Chadd if (status == ATH_AGGR_8K_LIMITED) 4020e2e4a2c2SAdrian Chadd sc->sc_aggr_stats.aggr_rts_aggr_limited++; 4021e2e4a2c2SAdrian Chadd 4022eb6f0de0SAdrian Chadd /* 4023eb6f0de0SAdrian Chadd * If it's the only frame send as non-aggregate 4024eb6f0de0SAdrian Chadd * assume that ath_tx_form_aggr() has checked 4025eb6f0de0SAdrian Chadd * whether it's in the BAW and added it appropriately. 4026eb6f0de0SAdrian Chadd */ 4027eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_nframes == 1) { 4028eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4029eb6f0de0SAdrian Chadd "%s: single-frame aggregate\n", __func__); 4030eb6f0de0SAdrian Chadd bf->bf_state.bfs_aggr = 0; 4031eb6f0de0SAdrian Chadd ath_tx_setds(sc, bf); 4032eb6f0de0SAdrian Chadd ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc); 4033eb6f0de0SAdrian Chadd if (status == ATH_AGGR_BAW_CLOSED) 4034eb6f0de0SAdrian Chadd sc->sc_aggr_stats.aggr_baw_closed_single_pkt++; 4035eb6f0de0SAdrian Chadd else 4036eb6f0de0SAdrian Chadd sc->sc_aggr_stats.aggr_single_pkt++; 4037eb6f0de0SAdrian Chadd } else { 4038eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, 4039d4365d16SAdrian Chadd "%s: multi-frame aggregate: %d frames, " 4040d4365d16SAdrian Chadd "length %d\n", 4041eb6f0de0SAdrian Chadd __func__, bf->bf_state.bfs_nframes, 4042eb6f0de0SAdrian Chadd bf->bf_state.bfs_al); 4043eb6f0de0SAdrian Chadd bf->bf_state.bfs_aggr = 1; 4044eb6f0de0SAdrian Chadd sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++; 4045eb6f0de0SAdrian Chadd sc->sc_aggr_stats.aggr_aggr_pkt++; 4046eb6f0de0SAdrian Chadd 4047eb6f0de0SAdrian Chadd /* 4048e2e4a2c2SAdrian Chadd * Calculate the duration/protection as required. 4049e2e4a2c2SAdrian Chadd */ 4050e2e4a2c2SAdrian Chadd ath_tx_calc_duration(sc, bf); 4051e2e4a2c2SAdrian Chadd ath_tx_calc_protection(sc, bf); 4052e2e4a2c2SAdrian Chadd 4053e2e4a2c2SAdrian Chadd /* 4054eb6f0de0SAdrian Chadd * Update the rate and rtscts information based on the 4055eb6f0de0SAdrian Chadd * rate decision made by the rate control code; 4056eb6f0de0SAdrian Chadd * the first frame in the aggregate needs it. 4057eb6f0de0SAdrian Chadd */ 4058eb6f0de0SAdrian Chadd ath_tx_set_rtscts(sc, bf); 4059eb6f0de0SAdrian Chadd 4060eb6f0de0SAdrian Chadd /* 4061eb6f0de0SAdrian Chadd * Setup the relevant descriptor fields 4062eb6f0de0SAdrian Chadd * for aggregation. The first descriptor 4063eb6f0de0SAdrian Chadd * already points to the rest in the chain. 4064eb6f0de0SAdrian Chadd */ 4065eb6f0de0SAdrian Chadd ath_tx_setds_11n(sc, bf); 4066eb6f0de0SAdrian Chadd 4067eb6f0de0SAdrian Chadd } 4068eb6f0de0SAdrian Chadd queuepkt: 4069eb6f0de0SAdrian Chadd //txq = bf->bf_state.bfs_txq; 4070eb6f0de0SAdrian Chadd 4071eb6f0de0SAdrian Chadd /* Set completion handler, multi-frame aggregate or not */ 4072eb6f0de0SAdrian Chadd bf->bf_comp = ath_tx_aggr_comp; 4073eb6f0de0SAdrian Chadd 4074eb6f0de0SAdrian Chadd if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID) 4075eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: TID=16?\n", __func__); 4076eb6f0de0SAdrian Chadd 4077eb6f0de0SAdrian Chadd /* Punt to txq */ 4078eb6f0de0SAdrian Chadd ath_tx_handoff(sc, txq, bf); 4079eb6f0de0SAdrian Chadd 4080eb6f0de0SAdrian Chadd /* Track outstanding buffer count to hardware */ 4081eb6f0de0SAdrian Chadd /* aggregates are "one" buffer */ 4082eb6f0de0SAdrian Chadd tid->hwq_depth++; 4083eb6f0de0SAdrian Chadd 4084eb6f0de0SAdrian Chadd /* 4085eb6f0de0SAdrian Chadd * Break out if ath_tx_form_aggr() indicated 4086eb6f0de0SAdrian Chadd * there can't be any further progress (eg BAW is full.) 4087eb6f0de0SAdrian Chadd * Checking for an empty txq is done above. 4088eb6f0de0SAdrian Chadd * 4089eb6f0de0SAdrian Chadd * XXX locking on txq here? 4090eb6f0de0SAdrian Chadd */ 4091eb6f0de0SAdrian Chadd if (txq->axq_aggr_depth >= sc->sc_hwq_limit || 4092eb6f0de0SAdrian Chadd status == ATH_AGGR_BAW_CLOSED) 4093eb6f0de0SAdrian Chadd break; 4094eb6f0de0SAdrian Chadd } 4095eb6f0de0SAdrian Chadd } 4096eb6f0de0SAdrian Chadd 4097eb6f0de0SAdrian Chadd /* 4098eb6f0de0SAdrian Chadd * Schedule some packets from the given node/TID to the hardware. 4099eb6f0de0SAdrian Chadd */ 4100eb6f0de0SAdrian Chadd void 4101eb6f0de0SAdrian Chadd ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an, 4102eb6f0de0SAdrian Chadd struct ath_tid *tid) 4103eb6f0de0SAdrian Chadd { 4104eb6f0de0SAdrian Chadd struct ath_buf *bf; 4105eb6f0de0SAdrian Chadd struct ath_txq *txq = sc->sc_ac2q[tid->ac]; 4106eb6f0de0SAdrian Chadd 4107eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n", 4108eb6f0de0SAdrian Chadd __func__, an, tid->tid); 4109eb6f0de0SAdrian Chadd 4110eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 4111eb6f0de0SAdrian Chadd 4112eb6f0de0SAdrian Chadd /* Check - is AMPDU pending or running? then print out something */ 4113eb6f0de0SAdrian Chadd if (ath_tx_ampdu_pending(sc, an, tid->tid)) 4114eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n", 4115eb6f0de0SAdrian Chadd __func__, tid->tid); 4116eb6f0de0SAdrian Chadd if (ath_tx_ampdu_running(sc, an, tid->tid)) 4117eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n", 4118eb6f0de0SAdrian Chadd __func__, tid->tid); 4119eb6f0de0SAdrian Chadd 4120eb6f0de0SAdrian Chadd for (;;) { 4121eb6f0de0SAdrian Chadd 4122eb6f0de0SAdrian Chadd /* 4123eb6f0de0SAdrian Chadd * If the upper layers have paused the TID, don't 4124eb6f0de0SAdrian Chadd * queue any further packets. 4125eb6f0de0SAdrian Chadd */ 4126eb6f0de0SAdrian Chadd if (tid->paused) 4127eb6f0de0SAdrian Chadd break; 4128eb6f0de0SAdrian Chadd 4129eb6f0de0SAdrian Chadd bf = TAILQ_FIRST(&tid->axq_q); 4130eb6f0de0SAdrian Chadd if (bf == NULL) { 4131eb6f0de0SAdrian Chadd break; 4132eb6f0de0SAdrian Chadd } 4133eb6f0de0SAdrian Chadd 4134eb6f0de0SAdrian Chadd ATH_TXQ_REMOVE(tid, bf, bf_list); 4135eb6f0de0SAdrian Chadd 4136eb6f0de0SAdrian Chadd KASSERT(txq == bf->bf_state.bfs_txq, ("txqs not equal!\n")); 4137eb6f0de0SAdrian Chadd 4138eb6f0de0SAdrian Chadd /* Sanity check! */ 4139eb6f0de0SAdrian Chadd if (tid->tid != bf->bf_state.bfs_tid) { 4140eb6f0de0SAdrian Chadd device_printf(sc->sc_dev, "%s: bfs_tid %d !=" 4141eb6f0de0SAdrian Chadd " tid %d\n", 4142eb6f0de0SAdrian Chadd __func__, bf->bf_state.bfs_tid, tid->tid); 4143eb6f0de0SAdrian Chadd } 4144eb6f0de0SAdrian Chadd /* Normal completion handler */ 4145eb6f0de0SAdrian Chadd bf->bf_comp = ath_tx_normal_comp; 4146eb6f0de0SAdrian Chadd 4147eb6f0de0SAdrian Chadd /* Program descriptors + rate control */ 4148eb6f0de0SAdrian Chadd ath_tx_do_ratelookup(sc, bf); 4149e2e4a2c2SAdrian Chadd ath_tx_calc_duration(sc, bf); 4150e2e4a2c2SAdrian Chadd ath_tx_calc_protection(sc, bf); 4151eb6f0de0SAdrian Chadd ath_tx_set_rtscts(sc, bf); 4152e2e4a2c2SAdrian Chadd ath_tx_rate_fill_rcflags(sc, bf); 4153eb6f0de0SAdrian Chadd ath_tx_setds(sc, bf); 4154eb6f0de0SAdrian Chadd 4155eb6f0de0SAdrian Chadd /* Track outstanding buffer count to hardware */ 4156eb6f0de0SAdrian Chadd /* aggregates are "one" buffer */ 4157eb6f0de0SAdrian Chadd tid->hwq_depth++; 4158eb6f0de0SAdrian Chadd 4159eb6f0de0SAdrian Chadd /* Punt to hardware or software txq */ 4160eb6f0de0SAdrian Chadd ath_tx_handoff(sc, txq, bf); 4161eb6f0de0SAdrian Chadd } 4162eb6f0de0SAdrian Chadd } 4163eb6f0de0SAdrian Chadd 4164eb6f0de0SAdrian Chadd /* 4165eb6f0de0SAdrian Chadd * Schedule some packets to the given hardware queue. 4166eb6f0de0SAdrian Chadd * 4167eb6f0de0SAdrian Chadd * This function walks the list of TIDs (ie, ath_node TIDs 4168eb6f0de0SAdrian Chadd * with queued traffic) and attempts to schedule traffic 4169eb6f0de0SAdrian Chadd * from them. 4170eb6f0de0SAdrian Chadd * 4171eb6f0de0SAdrian Chadd * TID scheduling is implemented as a FIFO, with TIDs being 4172eb6f0de0SAdrian Chadd * added to the end of the queue after some frames have been 4173eb6f0de0SAdrian Chadd * scheduled. 4174eb6f0de0SAdrian Chadd */ 4175eb6f0de0SAdrian Chadd void 4176eb6f0de0SAdrian Chadd ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq) 4177eb6f0de0SAdrian Chadd { 4178eb6f0de0SAdrian Chadd struct ath_tid *tid, *next, *last; 4179eb6f0de0SAdrian Chadd 4180eb6f0de0SAdrian Chadd ATH_TXQ_LOCK_ASSERT(txq); 4181eb6f0de0SAdrian Chadd 4182eb6f0de0SAdrian Chadd /* 4183eb6f0de0SAdrian Chadd * Don't schedule if the hardware queue is busy. 4184eb6f0de0SAdrian Chadd * This (hopefully) gives some more time to aggregate 4185eb6f0de0SAdrian Chadd * some packets in the aggregation queue. 4186eb6f0de0SAdrian Chadd */ 4187eb6f0de0SAdrian Chadd if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 4188eb6f0de0SAdrian Chadd sc->sc_aggr_stats.aggr_sched_nopkt++; 4189eb6f0de0SAdrian Chadd return; 4190eb6f0de0SAdrian Chadd } 4191eb6f0de0SAdrian Chadd 4192eb6f0de0SAdrian Chadd last = TAILQ_LAST(&txq->axq_tidq, axq_t_s); 4193eb6f0de0SAdrian Chadd 4194eb6f0de0SAdrian Chadd TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) { 4195eb6f0de0SAdrian Chadd /* 4196eb6f0de0SAdrian Chadd * Suspend paused queues here; they'll be resumed 4197eb6f0de0SAdrian Chadd * once the addba completes or times out. 4198eb6f0de0SAdrian Chadd */ 4199eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n", 4200eb6f0de0SAdrian Chadd __func__, tid->tid, tid->paused); 4201eb6f0de0SAdrian Chadd ath_tx_tid_unsched(sc, tid); 4202eb6f0de0SAdrian Chadd if (tid->paused) { 4203eb6f0de0SAdrian Chadd continue; 4204eb6f0de0SAdrian Chadd } 4205eb6f0de0SAdrian Chadd if (ath_tx_ampdu_running(sc, tid->an, tid->tid)) 4206eb6f0de0SAdrian Chadd ath_tx_tid_hw_queue_aggr(sc, tid->an, tid); 4207eb6f0de0SAdrian Chadd else 4208eb6f0de0SAdrian Chadd ath_tx_tid_hw_queue_norm(sc, tid->an, tid); 4209eb6f0de0SAdrian Chadd 4210eb6f0de0SAdrian Chadd /* Not empty? Re-schedule */ 4211eb6f0de0SAdrian Chadd if (tid->axq_depth != 0) 4212eb6f0de0SAdrian Chadd ath_tx_tid_sched(sc, tid); 4213eb6f0de0SAdrian Chadd 4214eb6f0de0SAdrian Chadd /* Give the software queue time to aggregate more packets */ 4215eb6f0de0SAdrian Chadd if (txq->axq_aggr_depth >= sc->sc_hwq_limit) { 4216eb6f0de0SAdrian Chadd break; 4217eb6f0de0SAdrian Chadd } 4218eb6f0de0SAdrian Chadd 4219eb6f0de0SAdrian Chadd /* 4220eb6f0de0SAdrian Chadd * If this was the last entry on the original list, stop. 4221eb6f0de0SAdrian Chadd * Otherwise nodes that have been rescheduled onto the end 4222eb6f0de0SAdrian Chadd * of the TID FIFO list will just keep being rescheduled. 4223eb6f0de0SAdrian Chadd */ 4224eb6f0de0SAdrian Chadd if (tid == last) 4225eb6f0de0SAdrian Chadd break; 4226eb6f0de0SAdrian Chadd } 4227eb6f0de0SAdrian Chadd } 4228eb6f0de0SAdrian Chadd 4229eb6f0de0SAdrian Chadd /* 4230eb6f0de0SAdrian Chadd * TX addba handling 4231eb6f0de0SAdrian Chadd */ 4232eb6f0de0SAdrian Chadd 4233eb6f0de0SAdrian Chadd /* 4234eb6f0de0SAdrian Chadd * Return net80211 TID struct pointer, or NULL for none 4235eb6f0de0SAdrian Chadd */ 4236eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu * 4237eb6f0de0SAdrian Chadd ath_tx_get_tx_tid(struct ath_node *an, int tid) 4238eb6f0de0SAdrian Chadd { 4239eb6f0de0SAdrian Chadd struct ieee80211_node *ni = &an->an_node; 4240eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 4241eb6f0de0SAdrian Chadd 4242eb6f0de0SAdrian Chadd if (tid == IEEE80211_NONQOS_TID) 4243eb6f0de0SAdrian Chadd return NULL; 4244eb6f0de0SAdrian Chadd 42452aa563dfSAdrian Chadd tap = &ni->ni_tx_ampdu[tid]; 4246eb6f0de0SAdrian Chadd return tap; 4247eb6f0de0SAdrian Chadd } 4248eb6f0de0SAdrian Chadd 4249eb6f0de0SAdrian Chadd /* 4250eb6f0de0SAdrian Chadd * Is AMPDU-TX running? 4251eb6f0de0SAdrian Chadd */ 4252eb6f0de0SAdrian Chadd static int 4253eb6f0de0SAdrian Chadd ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid) 4254eb6f0de0SAdrian Chadd { 4255eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 4256eb6f0de0SAdrian Chadd 4257eb6f0de0SAdrian Chadd if (tid == IEEE80211_NONQOS_TID) 4258eb6f0de0SAdrian Chadd return 0; 4259eb6f0de0SAdrian Chadd 4260eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid); 4261eb6f0de0SAdrian Chadd if (tap == NULL) 4262eb6f0de0SAdrian Chadd return 0; /* Not valid; default to not running */ 4263eb6f0de0SAdrian Chadd 4264eb6f0de0SAdrian Chadd return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING); 4265eb6f0de0SAdrian Chadd } 4266eb6f0de0SAdrian Chadd 4267eb6f0de0SAdrian Chadd /* 4268eb6f0de0SAdrian Chadd * Is AMPDU-TX negotiation pending? 4269eb6f0de0SAdrian Chadd */ 4270eb6f0de0SAdrian Chadd static int 4271eb6f0de0SAdrian Chadd ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid) 4272eb6f0de0SAdrian Chadd { 4273eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap; 4274eb6f0de0SAdrian Chadd 4275eb6f0de0SAdrian Chadd if (tid == IEEE80211_NONQOS_TID) 4276eb6f0de0SAdrian Chadd return 0; 4277eb6f0de0SAdrian Chadd 4278eb6f0de0SAdrian Chadd tap = ath_tx_get_tx_tid(an, tid); 4279eb6f0de0SAdrian Chadd if (tap == NULL) 4280eb6f0de0SAdrian Chadd return 0; /* Not valid; default to not pending */ 4281eb6f0de0SAdrian Chadd 4282eb6f0de0SAdrian Chadd return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND); 4283eb6f0de0SAdrian Chadd } 4284eb6f0de0SAdrian Chadd 4285eb6f0de0SAdrian Chadd /* 4286eb6f0de0SAdrian Chadd * Is AMPDU-TX pending for the given TID? 4287eb6f0de0SAdrian Chadd */ 4288eb6f0de0SAdrian Chadd 4289eb6f0de0SAdrian Chadd 4290eb6f0de0SAdrian Chadd /* 4291eb6f0de0SAdrian Chadd * Method to handle sending an ADDBA request. 4292eb6f0de0SAdrian Chadd * 4293eb6f0de0SAdrian Chadd * We tap this so the relevant flags can be set to pause the TID 4294eb6f0de0SAdrian Chadd * whilst waiting for the response. 4295eb6f0de0SAdrian Chadd * 4296eb6f0de0SAdrian Chadd * XXX there's no timeout handler we can override? 4297eb6f0de0SAdrian Chadd */ 4298eb6f0de0SAdrian Chadd int 4299eb6f0de0SAdrian Chadd ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4300eb6f0de0SAdrian Chadd int dialogtoken, int baparamset, int batimeout) 4301eb6f0de0SAdrian Chadd { 4302eb6f0de0SAdrian Chadd struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 43032aa563dfSAdrian Chadd int tid = tap->txa_tid; 4304eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 4305eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 4306eb6f0de0SAdrian Chadd 4307eb6f0de0SAdrian Chadd /* 4308eb6f0de0SAdrian Chadd * XXX danger Will Robinson! 4309eb6f0de0SAdrian Chadd * 4310eb6f0de0SAdrian Chadd * Although the taskqueue may be running and scheduling some more 4311eb6f0de0SAdrian Chadd * packets, these should all be _before_ the addba sequence number. 4312eb6f0de0SAdrian Chadd * However, net80211 will keep self-assigning sequence numbers 4313eb6f0de0SAdrian Chadd * until addba has been negotiated. 4314eb6f0de0SAdrian Chadd * 4315eb6f0de0SAdrian Chadd * In the past, these packets would be "paused" (which still works 4316eb6f0de0SAdrian Chadd * fine, as they're being scheduled to the driver in the same 4317eb6f0de0SAdrian Chadd * serialised method which is calling the addba request routine) 4318eb6f0de0SAdrian Chadd * and when the aggregation session begins, they'll be dequeued 4319eb6f0de0SAdrian Chadd * as aggregate packets and added to the BAW. However, now there's 4320eb6f0de0SAdrian Chadd * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these 4321eb6f0de0SAdrian Chadd * packets. Thus they never get included in the BAW tracking and 4322eb6f0de0SAdrian Chadd * this can cause the initial burst of packets after the addba 4323eb6f0de0SAdrian Chadd * negotiation to "hang", as they quickly fall outside the BAW. 4324eb6f0de0SAdrian Chadd * 4325eb6f0de0SAdrian Chadd * The "eventual" solution should be to tag these packets with 4326eb6f0de0SAdrian Chadd * dobaw. Although net80211 has given us a sequence number, 4327eb6f0de0SAdrian Chadd * it'll be "after" the left edge of the BAW and thus it'll 4328eb6f0de0SAdrian Chadd * fall within it. 4329eb6f0de0SAdrian Chadd */ 433096ff26ffSAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4331d3a6425bSAdrian Chadd /* 4332d3a6425bSAdrian Chadd * This is a bit annoying. Until net80211 HT code inherits some 4333d3a6425bSAdrian Chadd * (any) locking, we may have this called in parallel BUT only 4334d3a6425bSAdrian Chadd * one response/timeout will be called. Grr. 4335d3a6425bSAdrian Chadd */ 4336d3a6425bSAdrian Chadd if (atid->addba_tx_pending == 0) { 4337eb6f0de0SAdrian Chadd ath_tx_tid_pause(sc, atid); 4338d3a6425bSAdrian Chadd atid->addba_tx_pending = 1; 4339d3a6425bSAdrian Chadd } 434096ff26ffSAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4341eb6f0de0SAdrian Chadd 4342eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4343eb6f0de0SAdrian Chadd "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n", 4344eb6f0de0SAdrian Chadd __func__, dialogtoken, baparamset, batimeout); 4345eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4346eb6f0de0SAdrian Chadd "%s: txa_start=%d, ni_txseqs=%d\n", 4347eb6f0de0SAdrian Chadd __func__, tap->txa_start, ni->ni_txseqs[tid]); 4348eb6f0de0SAdrian Chadd 4349eb6f0de0SAdrian Chadd return sc->sc_addba_request(ni, tap, dialogtoken, baparamset, 4350eb6f0de0SAdrian Chadd batimeout); 4351eb6f0de0SAdrian Chadd } 4352eb6f0de0SAdrian Chadd 4353eb6f0de0SAdrian Chadd /* 4354eb6f0de0SAdrian Chadd * Handle an ADDBA response. 4355eb6f0de0SAdrian Chadd * 4356eb6f0de0SAdrian Chadd * We unpause the queue so TX'ing can resume. 4357eb6f0de0SAdrian Chadd * 4358eb6f0de0SAdrian Chadd * Any packets TX'ed from this point should be "aggregate" (whether 4359eb6f0de0SAdrian Chadd * aggregate or not) so the BAW is updated. 4360eb6f0de0SAdrian Chadd * 4361eb6f0de0SAdrian Chadd * Note! net80211 keeps self-assigning sequence numbers until 4362eb6f0de0SAdrian Chadd * ampdu is negotiated. This means the initially-negotiated BAW left 4363eb6f0de0SAdrian Chadd * edge won't match the ni->ni_txseq. 4364eb6f0de0SAdrian Chadd * 4365eb6f0de0SAdrian Chadd * So, being very dirty, the BAW left edge is "slid" here to match 4366eb6f0de0SAdrian Chadd * ni->ni_txseq. 4367eb6f0de0SAdrian Chadd * 4368eb6f0de0SAdrian Chadd * What likely SHOULD happen is that all packets subsequent to the 4369eb6f0de0SAdrian Chadd * addba request should be tagged as aggregate and queued as non-aggregate 4370eb6f0de0SAdrian Chadd * frames; thus updating the BAW. For now though, I'll just slide the 4371eb6f0de0SAdrian Chadd * window. 4372eb6f0de0SAdrian Chadd */ 4373eb6f0de0SAdrian Chadd int 4374eb6f0de0SAdrian Chadd ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4375eb6f0de0SAdrian Chadd int status, int code, int batimeout) 4376eb6f0de0SAdrian Chadd { 4377eb6f0de0SAdrian Chadd struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 43782aa563dfSAdrian Chadd int tid = tap->txa_tid; 4379eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 4380eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 4381eb6f0de0SAdrian Chadd int r; 4382eb6f0de0SAdrian Chadd 4383eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4384eb6f0de0SAdrian Chadd "%s: called; status=%d, code=%d, batimeout=%d\n", __func__, 4385eb6f0de0SAdrian Chadd status, code, batimeout); 4386eb6f0de0SAdrian Chadd 4387eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4388eb6f0de0SAdrian Chadd "%s: txa_start=%d, ni_txseqs=%d\n", 4389eb6f0de0SAdrian Chadd __func__, tap->txa_start, ni->ni_txseqs[tid]); 4390eb6f0de0SAdrian Chadd 4391eb6f0de0SAdrian Chadd /* 4392eb6f0de0SAdrian Chadd * Call this first, so the interface flags get updated 4393eb6f0de0SAdrian Chadd * before the TID is unpaused. Otherwise a race condition 4394eb6f0de0SAdrian Chadd * exists where the unpaused TID still doesn't yet have 4395eb6f0de0SAdrian Chadd * IEEE80211_AGGR_RUNNING set. 4396eb6f0de0SAdrian Chadd */ 4397eb6f0de0SAdrian Chadd r = sc->sc_addba_response(ni, tap, status, code, batimeout); 4398eb6f0de0SAdrian Chadd 4399eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4400d3a6425bSAdrian Chadd atid->addba_tx_pending = 0; 4401eb6f0de0SAdrian Chadd /* 4402eb6f0de0SAdrian Chadd * XXX dirty! 4403eb6f0de0SAdrian Chadd * Slide the BAW left edge to wherever net80211 left it for us. 4404eb6f0de0SAdrian Chadd * Read above for more information. 4405eb6f0de0SAdrian Chadd */ 4406eb6f0de0SAdrian Chadd tap->txa_start = ni->ni_txseqs[tid]; 4407eb6f0de0SAdrian Chadd ath_tx_tid_resume(sc, atid); 4408eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4409eb6f0de0SAdrian Chadd return r; 4410eb6f0de0SAdrian Chadd } 4411eb6f0de0SAdrian Chadd 4412eb6f0de0SAdrian Chadd 4413eb6f0de0SAdrian Chadd /* 4414eb6f0de0SAdrian Chadd * Stop ADDBA on a queue. 44158405fe86SAdrian Chadd * 44168405fe86SAdrian Chadd * This can be called whilst BAR TX is currently active on the queue, 44178405fe86SAdrian Chadd * so make sure this is unblocked before continuing. 4418eb6f0de0SAdrian Chadd */ 4419eb6f0de0SAdrian Chadd void 4420eb6f0de0SAdrian Chadd ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap) 4421eb6f0de0SAdrian Chadd { 4422eb6f0de0SAdrian Chadd struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 44232aa563dfSAdrian Chadd int tid = tap->txa_tid; 4424eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 4425eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 4426eb6f0de0SAdrian Chadd 4427eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__); 4428eb6f0de0SAdrian Chadd 44298405fe86SAdrian Chadd /* 44308405fe86SAdrian Chadd * Pause TID traffic early, so there aren't any races 44318405fe86SAdrian Chadd * Unblock the pending BAR held traffic, if it's currently paused. 44328405fe86SAdrian Chadd */ 443396ff26ffSAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4434eb6f0de0SAdrian Chadd ath_tx_tid_pause(sc, atid); 44358405fe86SAdrian Chadd if (atid->bar_wait) { 44368405fe86SAdrian Chadd /* 44378405fe86SAdrian Chadd * bar_unsuspend() expects bar_tx == 1, as it should be 44388405fe86SAdrian Chadd * called from the TX completion path. This quietens 44398405fe86SAdrian Chadd * the warning. It's cleared for us anyway. 44408405fe86SAdrian Chadd */ 44418405fe86SAdrian Chadd atid->bar_tx = 1; 44428405fe86SAdrian Chadd ath_tx_tid_bar_unsuspend(sc, atid); 44438405fe86SAdrian Chadd } 444496ff26ffSAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4445eb6f0de0SAdrian Chadd 4446eb6f0de0SAdrian Chadd /* There's no need to hold the TXQ lock here */ 4447eb6f0de0SAdrian Chadd sc->sc_addba_stop(ni, tap); 4448eb6f0de0SAdrian Chadd 4449eb6f0de0SAdrian Chadd /* 44504dfd4507SAdrian Chadd * ath_tx_tid_cleanup will resume the TID if possible, otherwise 4451eb6f0de0SAdrian Chadd * it'll set the cleanup flag, and it'll be unpaused once 4452eb6f0de0SAdrian Chadd * things have been cleaned up. 4453eb6f0de0SAdrian Chadd */ 44544dfd4507SAdrian Chadd ath_tx_tid_cleanup(sc, an, tid); 4455eb6f0de0SAdrian Chadd } 4456eb6f0de0SAdrian Chadd 4457eb6f0de0SAdrian Chadd /* 4458eb6f0de0SAdrian Chadd * Note: net80211 bar_timeout() doesn't call this function on BAR failure; 4459eb6f0de0SAdrian Chadd * it simply tears down the aggregation session. Ew. 4460eb6f0de0SAdrian Chadd * 4461eb6f0de0SAdrian Chadd * It however will call ieee80211_ampdu_stop() which will call 4462eb6f0de0SAdrian Chadd * ic->ic_addba_stop(). 4463eb6f0de0SAdrian Chadd * 4464eb6f0de0SAdrian Chadd * XXX This uses a hard-coded max BAR count value; the whole 4465eb6f0de0SAdrian Chadd * XXX BAR TX success or failure should be better handled! 4466eb6f0de0SAdrian Chadd */ 4467eb6f0de0SAdrian Chadd void 4468eb6f0de0SAdrian Chadd ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, 4469eb6f0de0SAdrian Chadd int status) 4470eb6f0de0SAdrian Chadd { 4471eb6f0de0SAdrian Chadd struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 44722aa563dfSAdrian Chadd int tid = tap->txa_tid; 4473eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 4474eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 4475eb6f0de0SAdrian Chadd int attempts = tap->txa_attempts; 4476eb6f0de0SAdrian Chadd 44770e22ed0eSAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, 4478e60c4fc2SAdrian Chadd "%s: called; tap=%p, atid=%p, txa_tid=%d, atid->tid=%d, status=%d, attempts=%d\n", 44790e22ed0eSAdrian Chadd __func__, 4480e60c4fc2SAdrian Chadd tap, 4481e60c4fc2SAdrian Chadd atid, 4482e60c4fc2SAdrian Chadd tap->txa_tid, 4483e60c4fc2SAdrian Chadd atid->tid, 44840e22ed0eSAdrian Chadd status, 44850e22ed0eSAdrian Chadd attempts); 4486eb6f0de0SAdrian Chadd 4487eb6f0de0SAdrian Chadd /* Note: This may update the BAW details */ 4488eb6f0de0SAdrian Chadd sc->sc_bar_response(ni, tap, status); 4489eb6f0de0SAdrian Chadd 4490eb6f0de0SAdrian Chadd /* Unpause the TID */ 4491eb6f0de0SAdrian Chadd /* 4492eb6f0de0SAdrian Chadd * XXX if this is attempt=50, the TID will be downgraded 4493eb6f0de0SAdrian Chadd * XXX to a non-aggregate session. So we must unpause the 4494eb6f0de0SAdrian Chadd * XXX TID here or it'll never be done. 4495eb6f0de0SAdrian Chadd */ 4496eb6f0de0SAdrian Chadd if (status == 0 || attempts == 50) { 4497eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 449888b3d483SAdrian Chadd ath_tx_tid_bar_unsuspend(sc, atid); 4499eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4500eb6f0de0SAdrian Chadd } 4501eb6f0de0SAdrian Chadd } 4502eb6f0de0SAdrian Chadd 4503eb6f0de0SAdrian Chadd /* 4504eb6f0de0SAdrian Chadd * This is called whenever the pending ADDBA request times out. 4505eb6f0de0SAdrian Chadd * Unpause and reschedule the TID. 4506eb6f0de0SAdrian Chadd */ 4507eb6f0de0SAdrian Chadd void 4508eb6f0de0SAdrian Chadd ath_addba_response_timeout(struct ieee80211_node *ni, 4509eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *tap) 4510eb6f0de0SAdrian Chadd { 4511eb6f0de0SAdrian Chadd struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc; 45122aa563dfSAdrian Chadd int tid = tap->txa_tid; 4513eb6f0de0SAdrian Chadd struct ath_node *an = ATH_NODE(ni); 4514eb6f0de0SAdrian Chadd struct ath_tid *atid = &an->an_tid[tid]; 4515eb6f0de0SAdrian Chadd 4516eb6f0de0SAdrian Chadd DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, 4517eb6f0de0SAdrian Chadd "%s: called; resuming\n", __func__); 4518eb6f0de0SAdrian Chadd 4519d3a6425bSAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4520d3a6425bSAdrian Chadd atid->addba_tx_pending = 0; 4521d3a6425bSAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4522d3a6425bSAdrian Chadd 4523eb6f0de0SAdrian Chadd /* Note: This updates the aggregate state to (again) pending */ 4524eb6f0de0SAdrian Chadd sc->sc_addba_response_timeout(ni, tap); 4525eb6f0de0SAdrian Chadd 4526eb6f0de0SAdrian Chadd /* Unpause the TID; which reschedules it */ 4527eb6f0de0SAdrian Chadd ATH_TXQ_LOCK(sc->sc_ac2q[atid->ac]); 4528eb6f0de0SAdrian Chadd ath_tx_tid_resume(sc, atid); 4529eb6f0de0SAdrian Chadd ATH_TXQ_UNLOCK(sc->sc_ac2q[atid->ac]); 4530eb6f0de0SAdrian Chadd } 45313fdfc330SAdrian Chadd 45323fdfc330SAdrian Chadd static int 45333fdfc330SAdrian Chadd ath_legacy_dma_txsetup(struct ath_softc *sc) 45343fdfc330SAdrian Chadd { 45353fdfc330SAdrian Chadd 45363fdfc330SAdrian Chadd /* nothing new needed */ 45373fdfc330SAdrian Chadd return (0); 45383fdfc330SAdrian Chadd } 45393fdfc330SAdrian Chadd 45403fdfc330SAdrian Chadd static int 45413fdfc330SAdrian Chadd ath_legacy_dma_txteardown(struct ath_softc *sc) 45423fdfc330SAdrian Chadd { 45433fdfc330SAdrian Chadd 45443fdfc330SAdrian Chadd /* nothing new needed */ 45453fdfc330SAdrian Chadd return (0); 45463fdfc330SAdrian Chadd } 45473fdfc330SAdrian Chadd 45483fdfc330SAdrian Chadd void 45493fdfc330SAdrian Chadd ath_xmit_setup_legacy(struct ath_softc *sc) 45503fdfc330SAdrian Chadd { 45511006fc0cSAdrian Chadd /* 45521006fc0cSAdrian Chadd * For now, just set the descriptor length to sizeof(ath_desc); 45531006fc0cSAdrian Chadd * worry about extracting the real length out of the HAL later. 45541006fc0cSAdrian Chadd */ 45551006fc0cSAdrian Chadd sc->sc_tx_desclen = sizeof(struct ath_desc); 45561006fc0cSAdrian Chadd sc->sc_tx_statuslen = 0; 45571006fc0cSAdrian Chadd sc->sc_tx_nmaps = 1; /* only one buffer per TX desc */ 45583fdfc330SAdrian Chadd 45593fdfc330SAdrian Chadd sc->sc_tx.xmit_setup = ath_legacy_dma_txsetup; 45603fdfc330SAdrian Chadd sc->sc_tx.xmit_teardown = ath_legacy_dma_txteardown; 4561f8418db5SAdrian Chadd sc->sc_tx.xmit_attach_comp_func = ath_legacy_attach_comp_func; 4562746bab5bSAdrian Chadd 4563746bab5bSAdrian Chadd sc->sc_tx.xmit_dma_restart = ath_legacy_tx_dma_restart; 4564746bab5bSAdrian Chadd sc->sc_tx.xmit_handoff = ath_legacy_xmit_handoff; 4565f8418db5SAdrian Chadd sc->sc_tx.xmit_processq = ath_legacy_tx_processq; 4566f8418db5SAdrian Chadd sc->sc_tx.xmit_drainq = ath_legacy_tx_draintxq; 45673fdfc330SAdrian Chadd } 4568