xref: /freebsd/sys/dev/ath/if_ath_tx.c (revision 0891354cd2170c30348149cb55d70e309869a12c)
1b8e788a5SAdrian Chadd /*-
2b8e788a5SAdrian Chadd  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3c6e9cee2SAdrian Chadd  * Copyright (c) 2010-2012 Adrian Chadd, Xenion Pty Ltd
4b8e788a5SAdrian Chadd  * All rights reserved.
5b8e788a5SAdrian Chadd  *
6b8e788a5SAdrian Chadd  * Redistribution and use in source and binary forms, with or without
7b8e788a5SAdrian Chadd  * modification, are permitted provided that the following conditions
8b8e788a5SAdrian Chadd  * are met:
9b8e788a5SAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
10b8e788a5SAdrian Chadd  *    notice, this list of conditions and the following disclaimer,
11b8e788a5SAdrian Chadd  *    without modification.
12b8e788a5SAdrian Chadd  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
13b8e788a5SAdrian Chadd  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
14b8e788a5SAdrian Chadd  *    redistribution must be conditioned upon including a substantially
15b8e788a5SAdrian Chadd  *    similar Disclaimer requirement for further binary redistribution.
16b8e788a5SAdrian Chadd  *
17b8e788a5SAdrian Chadd  * NO WARRANTY
18b8e788a5SAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19b8e788a5SAdrian Chadd  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20b8e788a5SAdrian Chadd  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
21b8e788a5SAdrian Chadd  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
22b8e788a5SAdrian Chadd  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
23b8e788a5SAdrian Chadd  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24b8e788a5SAdrian Chadd  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25b8e788a5SAdrian Chadd  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
26b8e788a5SAdrian Chadd  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27b8e788a5SAdrian Chadd  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28b8e788a5SAdrian Chadd  * THE POSSIBILITY OF SUCH DAMAGES.
29b8e788a5SAdrian Chadd  */
30b8e788a5SAdrian Chadd 
31b8e788a5SAdrian Chadd #include <sys/cdefs.h>
32b8e788a5SAdrian Chadd __FBSDID("$FreeBSD$");
33b8e788a5SAdrian Chadd 
34b8e788a5SAdrian Chadd /*
35b8e788a5SAdrian Chadd  * Driver for the Atheros Wireless LAN controller.
36b8e788a5SAdrian Chadd  *
37b8e788a5SAdrian Chadd  * This software is derived from work of Atsushi Onoe; his contribution
38b8e788a5SAdrian Chadd  * is greatly appreciated.
39b8e788a5SAdrian Chadd  */
40b8e788a5SAdrian Chadd 
41b8e788a5SAdrian Chadd #include "opt_inet.h"
42b8e788a5SAdrian Chadd #include "opt_ath.h"
43b8e788a5SAdrian Chadd #include "opt_wlan.h"
44b8e788a5SAdrian Chadd 
45b8e788a5SAdrian Chadd #include <sys/param.h>
46b8e788a5SAdrian Chadd #include <sys/systm.h>
47b8e788a5SAdrian Chadd #include <sys/sysctl.h>
48b8e788a5SAdrian Chadd #include <sys/mbuf.h>
49b8e788a5SAdrian Chadd #include <sys/malloc.h>
50b8e788a5SAdrian Chadd #include <sys/lock.h>
51b8e788a5SAdrian Chadd #include <sys/mutex.h>
52b8e788a5SAdrian Chadd #include <sys/kernel.h>
53b8e788a5SAdrian Chadd #include <sys/socket.h>
54b8e788a5SAdrian Chadd #include <sys/sockio.h>
55b8e788a5SAdrian Chadd #include <sys/errno.h>
56b8e788a5SAdrian Chadd #include <sys/callout.h>
57b8e788a5SAdrian Chadd #include <sys/bus.h>
58b8e788a5SAdrian Chadd #include <sys/endian.h>
59b8e788a5SAdrian Chadd #include <sys/kthread.h>
60b8e788a5SAdrian Chadd #include <sys/taskqueue.h>
61b8e788a5SAdrian Chadd #include <sys/priv.h>
62b8e788a5SAdrian Chadd 
63b8e788a5SAdrian Chadd #include <machine/bus.h>
64b8e788a5SAdrian Chadd 
65b8e788a5SAdrian Chadd #include <net/if.h>
66b8e788a5SAdrian Chadd #include <net/if_dl.h>
67b8e788a5SAdrian Chadd #include <net/if_media.h>
68b8e788a5SAdrian Chadd #include <net/if_types.h>
69b8e788a5SAdrian Chadd #include <net/if_arp.h>
70b8e788a5SAdrian Chadd #include <net/ethernet.h>
71b8e788a5SAdrian Chadd #include <net/if_llc.h>
72b8e788a5SAdrian Chadd 
73b8e788a5SAdrian Chadd #include <net80211/ieee80211_var.h>
74b8e788a5SAdrian Chadd #include <net80211/ieee80211_regdomain.h>
75b8e788a5SAdrian Chadd #ifdef IEEE80211_SUPPORT_SUPERG
76b8e788a5SAdrian Chadd #include <net80211/ieee80211_superg.h>
77b8e788a5SAdrian Chadd #endif
78b8e788a5SAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
79b8e788a5SAdrian Chadd #include <net80211/ieee80211_tdma.h>
80b8e788a5SAdrian Chadd #endif
81eb6f0de0SAdrian Chadd #include <net80211/ieee80211_ht.h>
82b8e788a5SAdrian Chadd 
83b8e788a5SAdrian Chadd #include <net/bpf.h>
84b8e788a5SAdrian Chadd 
85b8e788a5SAdrian Chadd #ifdef INET
86b8e788a5SAdrian Chadd #include <netinet/in.h>
87b8e788a5SAdrian Chadd #include <netinet/if_ether.h>
88b8e788a5SAdrian Chadd #endif
89b8e788a5SAdrian Chadd 
90b8e788a5SAdrian Chadd #include <dev/ath/if_athvar.h>
91b8e788a5SAdrian Chadd #include <dev/ath/ath_hal/ah_devid.h>		/* XXX for softled */
92b8e788a5SAdrian Chadd #include <dev/ath/ath_hal/ah_diagcodes.h>
93b8e788a5SAdrian Chadd 
94b8e788a5SAdrian Chadd #include <dev/ath/if_ath_debug.h>
95b8e788a5SAdrian Chadd 
96b8e788a5SAdrian Chadd #ifdef ATH_TX99_DIAG
97b8e788a5SAdrian Chadd #include <dev/ath/ath_tx99/ath_tx99.h>
98b8e788a5SAdrian Chadd #endif
99b8e788a5SAdrian Chadd 
100b8e788a5SAdrian Chadd #include <dev/ath/if_ath_misc.h>
101b8e788a5SAdrian Chadd #include <dev/ath/if_ath_tx.h>
102c1782ce0SAdrian Chadd #include <dev/ath/if_ath_tx_ht.h>
103b8e788a5SAdrian Chadd 
104b69b0dccSAdrian Chadd #ifdef	ATH_DEBUG_ALQ
105b69b0dccSAdrian Chadd #include <dev/ath/if_ath_alq.h>
106b69b0dccSAdrian Chadd #endif
107b69b0dccSAdrian Chadd 
10881a82688SAdrian Chadd /*
109eb6f0de0SAdrian Chadd  * How many retries to perform in software
110eb6f0de0SAdrian Chadd  */
111eb6f0de0SAdrian Chadd #define	SWMAX_RETRIES		10
112eb6f0de0SAdrian Chadd 
1137403d1b9SAdrian Chadd /*
1147403d1b9SAdrian Chadd  * What queue to throw the non-QoS TID traffic into
1157403d1b9SAdrian Chadd  */
1167403d1b9SAdrian Chadd #define	ATH_NONQOS_TID_AC	WME_AC_VO
1177403d1b9SAdrian Chadd 
1180eb81626SAdrian Chadd #if 0
1190eb81626SAdrian Chadd static int ath_tx_node_is_asleep(struct ath_softc *sc, struct ath_node *an);
1200eb81626SAdrian Chadd #endif
121eb6f0de0SAdrian Chadd static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an,
122eb6f0de0SAdrian Chadd     int tid);
123eb6f0de0SAdrian Chadd static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an,
124eb6f0de0SAdrian Chadd     int tid);
125a108d2d6SAdrian Chadd static ieee80211_seq ath_tx_tid_seqno_assign(struct ath_softc *sc,
126a108d2d6SAdrian Chadd     struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0);
127eb6f0de0SAdrian Chadd static int ath_tx_action_frame_override_queue(struct ath_softc *sc,
128eb6f0de0SAdrian Chadd     struct ieee80211_node *ni, struct mbuf *m0, int *tid);
129f1bc738eSAdrian Chadd static struct ath_buf *
130f1bc738eSAdrian Chadd ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an,
131f1bc738eSAdrian Chadd     struct ath_tid *tid, struct ath_buf *bf);
132eb6f0de0SAdrian Chadd 
133bb327d28SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
134bb327d28SAdrian Chadd void
135bb327d28SAdrian Chadd ath_tx_alq_post(struct ath_softc *sc, struct ath_buf *bf_first)
136bb327d28SAdrian Chadd {
137bb327d28SAdrian Chadd 	struct ath_buf *bf;
138bb327d28SAdrian Chadd 	int i, n;
139bb327d28SAdrian Chadd 	const char *ds;
140bb327d28SAdrian Chadd 
141bb327d28SAdrian Chadd 	/* XXX we should skip out early if debugging isn't enabled! */
142bb327d28SAdrian Chadd 	bf = bf_first;
143bb327d28SAdrian Chadd 
144bb327d28SAdrian Chadd 	while (bf != NULL) {
145bb327d28SAdrian Chadd 		/* XXX should ensure bf_nseg > 0! */
146bb327d28SAdrian Chadd 		if (bf->bf_nseg == 0)
147bb327d28SAdrian Chadd 			break;
148bb327d28SAdrian Chadd 		n = ((bf->bf_nseg - 1) / sc->sc_tx_nmaps) + 1;
149bb327d28SAdrian Chadd 		for (i = 0, ds = (const char *) bf->bf_desc;
150bb327d28SAdrian Chadd 		    i < n;
151bb327d28SAdrian Chadd 		    i++, ds += sc->sc_tx_desclen) {
152bb327d28SAdrian Chadd 			if_ath_alq_post(&sc->sc_alq,
153bb327d28SAdrian Chadd 			    ATH_ALQ_EDMA_TXDESC,
154bb327d28SAdrian Chadd 			    sc->sc_tx_desclen,
155bb327d28SAdrian Chadd 			    ds);
156bb327d28SAdrian Chadd 		}
157bb327d28SAdrian Chadd 		bf = bf->bf_next;
158bb327d28SAdrian Chadd 	}
159bb327d28SAdrian Chadd }
160bb327d28SAdrian Chadd #endif /* ATH_DEBUG_ALQ */
161bb327d28SAdrian Chadd 
162eb6f0de0SAdrian Chadd /*
16381a82688SAdrian Chadd  * Whether to use the 11n rate scenario functions or not
16481a82688SAdrian Chadd  */
16581a82688SAdrian Chadd static inline int
16681a82688SAdrian Chadd ath_tx_is_11n(struct ath_softc *sc)
16781a82688SAdrian Chadd {
1684ddf2cc3SAdrian Chadd 	return ((sc->sc_ah->ah_magic == 0x20065416) ||
1694ddf2cc3SAdrian Chadd 		    (sc->sc_ah->ah_magic == 0x19741014));
17081a82688SAdrian Chadd }
17181a82688SAdrian Chadd 
172eb6f0de0SAdrian Chadd /*
173eb6f0de0SAdrian Chadd  * Obtain the current TID from the given frame.
174eb6f0de0SAdrian Chadd  *
175eb6f0de0SAdrian Chadd  * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.)
176eb6f0de0SAdrian Chadd  * This has implications for which AC/priority the packet is placed
177eb6f0de0SAdrian Chadd  * in.
178eb6f0de0SAdrian Chadd  */
179eb6f0de0SAdrian Chadd static int
180eb6f0de0SAdrian Chadd ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0)
181eb6f0de0SAdrian Chadd {
182eb6f0de0SAdrian Chadd 	const struct ieee80211_frame *wh;
183eb6f0de0SAdrian Chadd 	int pri = M_WME_GETAC(m0);
184eb6f0de0SAdrian Chadd 
185eb6f0de0SAdrian Chadd 	wh = mtod(m0, const struct ieee80211_frame *);
186eb6f0de0SAdrian Chadd 	if (! IEEE80211_QOS_HAS_SEQ(wh))
187eb6f0de0SAdrian Chadd 		return IEEE80211_NONQOS_TID;
188eb6f0de0SAdrian Chadd 	else
189eb6f0de0SAdrian Chadd 		return WME_AC_TO_TID(pri);
190eb6f0de0SAdrian Chadd }
191eb6f0de0SAdrian Chadd 
192f1bc738eSAdrian Chadd static void
193f1bc738eSAdrian Chadd ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
194f1bc738eSAdrian Chadd {
195f1bc738eSAdrian Chadd 	struct ieee80211_frame *wh;
196f1bc738eSAdrian Chadd 
197f1bc738eSAdrian Chadd 	wh = mtod(bf->bf_m, struct ieee80211_frame *);
198f1bc738eSAdrian Chadd 	/* Only update/resync if needed */
199f1bc738eSAdrian Chadd 	if (bf->bf_state.bfs_isretried == 0) {
200f1bc738eSAdrian Chadd 		wh->i_fc[1] |= IEEE80211_FC1_RETRY;
201f1bc738eSAdrian Chadd 		bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
202f1bc738eSAdrian Chadd 		    BUS_DMASYNC_PREWRITE);
203f1bc738eSAdrian Chadd 	}
204f1bc738eSAdrian Chadd 	bf->bf_state.bfs_isretried = 1;
205f1bc738eSAdrian Chadd 	bf->bf_state.bfs_retries ++;
206f1bc738eSAdrian Chadd }
207f1bc738eSAdrian Chadd 
208eb6f0de0SAdrian Chadd /*
209eb6f0de0SAdrian Chadd  * Determine what the correct AC queue for the given frame
210eb6f0de0SAdrian Chadd  * should be.
211eb6f0de0SAdrian Chadd  *
212eb6f0de0SAdrian Chadd  * This code assumes that the TIDs map consistently to
213eb6f0de0SAdrian Chadd  * the underlying hardware (or software) ath_txq.
214eb6f0de0SAdrian Chadd  * Since the sender may try to set an AC which is
215eb6f0de0SAdrian Chadd  * arbitrary, non-QoS TIDs may end up being put on
216eb6f0de0SAdrian Chadd  * completely different ACs. There's no way to put a
217eb6f0de0SAdrian Chadd  * TID into multiple ath_txq's for scheduling, so
218eb6f0de0SAdrian Chadd  * for now we override the AC/TXQ selection and set
219eb6f0de0SAdrian Chadd  * non-QOS TID frames into the BE queue.
220eb6f0de0SAdrian Chadd  *
221eb6f0de0SAdrian Chadd  * This may be completely incorrect - specifically,
222eb6f0de0SAdrian Chadd  * some management frames may end up out of order
223eb6f0de0SAdrian Chadd  * compared to the QoS traffic they're controlling.
224eb6f0de0SAdrian Chadd  * I'll look into this later.
225eb6f0de0SAdrian Chadd  */
226eb6f0de0SAdrian Chadd static int
227eb6f0de0SAdrian Chadd ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0)
228eb6f0de0SAdrian Chadd {
229eb6f0de0SAdrian Chadd 	const struct ieee80211_frame *wh;
230eb6f0de0SAdrian Chadd 	int pri = M_WME_GETAC(m0);
231eb6f0de0SAdrian Chadd 	wh = mtod(m0, const struct ieee80211_frame *);
232eb6f0de0SAdrian Chadd 	if (IEEE80211_QOS_HAS_SEQ(wh))
233eb6f0de0SAdrian Chadd 		return pri;
234eb6f0de0SAdrian Chadd 
2357403d1b9SAdrian Chadd 	return ATH_NONQOS_TID_AC;
236eb6f0de0SAdrian Chadd }
237eb6f0de0SAdrian Chadd 
238b8e788a5SAdrian Chadd void
239b8e788a5SAdrian Chadd ath_txfrag_cleanup(struct ath_softc *sc,
240b8e788a5SAdrian Chadd 	ath_bufhead *frags, struct ieee80211_node *ni)
241b8e788a5SAdrian Chadd {
242b8e788a5SAdrian Chadd 	struct ath_buf *bf, *next;
243b8e788a5SAdrian Chadd 
244b8e788a5SAdrian Chadd 	ATH_TXBUF_LOCK_ASSERT(sc);
245b8e788a5SAdrian Chadd 
2466b349e5aSAdrian Chadd 	TAILQ_FOREACH_SAFE(bf, frags, bf_list, next) {
247b8e788a5SAdrian Chadd 		/* NB: bf assumed clean */
2486b349e5aSAdrian Chadd 		TAILQ_REMOVE(frags, bf, bf_list);
249e1a50456SAdrian Chadd 		ath_returnbuf_head(sc, bf);
250b8e788a5SAdrian Chadd 		ieee80211_node_decref(ni);
251b8e788a5SAdrian Chadd 	}
252b8e788a5SAdrian Chadd }
253b8e788a5SAdrian Chadd 
254b8e788a5SAdrian Chadd /*
255b8e788a5SAdrian Chadd  * Setup xmit of a fragmented frame.  Allocate a buffer
256b8e788a5SAdrian Chadd  * for each frag and bump the node reference count to
257b8e788a5SAdrian Chadd  * reflect the held reference to be setup by ath_tx_start.
258b8e788a5SAdrian Chadd  */
259b8e788a5SAdrian Chadd int
260b8e788a5SAdrian Chadd ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags,
261b8e788a5SAdrian Chadd 	struct mbuf *m0, struct ieee80211_node *ni)
262b8e788a5SAdrian Chadd {
263b8e788a5SAdrian Chadd 	struct mbuf *m;
264b8e788a5SAdrian Chadd 	struct ath_buf *bf;
265b8e788a5SAdrian Chadd 
266b8e788a5SAdrian Chadd 	ATH_TXBUF_LOCK(sc);
267b8e788a5SAdrian Chadd 	for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) {
268af33d486SAdrian Chadd 		/* XXX non-management? */
269af33d486SAdrian Chadd 		bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
270b8e788a5SAdrian Chadd 		if (bf == NULL) {	/* out of buffers, cleanup */
271b43facbfSAdrian Chadd 			device_printf(sc->sc_dev, "%s: no buffer?\n",
272b43facbfSAdrian Chadd 			    __func__);
273b8e788a5SAdrian Chadd 			ath_txfrag_cleanup(sc, frags, ni);
274b8e788a5SAdrian Chadd 			break;
275b8e788a5SAdrian Chadd 		}
276b8e788a5SAdrian Chadd 		ieee80211_node_incref(ni);
2776b349e5aSAdrian Chadd 		TAILQ_INSERT_TAIL(frags, bf, bf_list);
278b8e788a5SAdrian Chadd 	}
279b8e788a5SAdrian Chadd 	ATH_TXBUF_UNLOCK(sc);
280b8e788a5SAdrian Chadd 
2816b349e5aSAdrian Chadd 	return !TAILQ_EMPTY(frags);
282b8e788a5SAdrian Chadd }
283b8e788a5SAdrian Chadd 
284b8e788a5SAdrian Chadd /*
285b8e788a5SAdrian Chadd  * Reclaim mbuf resources.  For fragmented frames we
286b8e788a5SAdrian Chadd  * need to claim each frag chained with m_nextpkt.
287b8e788a5SAdrian Chadd  */
288b8e788a5SAdrian Chadd void
289b8e788a5SAdrian Chadd ath_freetx(struct mbuf *m)
290b8e788a5SAdrian Chadd {
291b8e788a5SAdrian Chadd 	struct mbuf *next;
292b8e788a5SAdrian Chadd 
293b8e788a5SAdrian Chadd 	do {
294b8e788a5SAdrian Chadd 		next = m->m_nextpkt;
295b8e788a5SAdrian Chadd 		m->m_nextpkt = NULL;
296b8e788a5SAdrian Chadd 		m_freem(m);
297b8e788a5SAdrian Chadd 	} while ((m = next) != NULL);
298b8e788a5SAdrian Chadd }
299b8e788a5SAdrian Chadd 
300b8e788a5SAdrian Chadd static int
301b8e788a5SAdrian Chadd ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0)
302b8e788a5SAdrian Chadd {
303b8e788a5SAdrian Chadd 	struct mbuf *m;
304b8e788a5SAdrian Chadd 	int error;
305b8e788a5SAdrian Chadd 
306b8e788a5SAdrian Chadd 	/*
307b8e788a5SAdrian Chadd 	 * Load the DMA map so any coalescing is done.  This
308b8e788a5SAdrian Chadd 	 * also calculates the number of descriptors we need.
309b8e788a5SAdrian Chadd 	 */
310b8e788a5SAdrian Chadd 	error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
311b8e788a5SAdrian Chadd 				     bf->bf_segs, &bf->bf_nseg,
312b8e788a5SAdrian Chadd 				     BUS_DMA_NOWAIT);
313b8e788a5SAdrian Chadd 	if (error == EFBIG) {
314b8e788a5SAdrian Chadd 		/* XXX packet requires too many descriptors */
315b8e788a5SAdrian Chadd 		bf->bf_nseg = ATH_TXDESC+1;
316b8e788a5SAdrian Chadd 	} else if (error != 0) {
317b8e788a5SAdrian Chadd 		sc->sc_stats.ast_tx_busdma++;
318b8e788a5SAdrian Chadd 		ath_freetx(m0);
319b8e788a5SAdrian Chadd 		return error;
320b8e788a5SAdrian Chadd 	}
321b8e788a5SAdrian Chadd 	/*
322b8e788a5SAdrian Chadd 	 * Discard null packets and check for packets that
323b8e788a5SAdrian Chadd 	 * require too many TX descriptors.  We try to convert
324b8e788a5SAdrian Chadd 	 * the latter to a cluster.
325b8e788a5SAdrian Chadd 	 */
326b8e788a5SAdrian Chadd 	if (bf->bf_nseg > ATH_TXDESC) {		/* too many desc's, linearize */
327b8e788a5SAdrian Chadd 		sc->sc_stats.ast_tx_linear++;
328c6499eccSGleb Smirnoff 		m = m_collapse(m0, M_NOWAIT, ATH_TXDESC);
329b8e788a5SAdrian Chadd 		if (m == NULL) {
330b8e788a5SAdrian Chadd 			ath_freetx(m0);
331b8e788a5SAdrian Chadd 			sc->sc_stats.ast_tx_nombuf++;
332b8e788a5SAdrian Chadd 			return ENOMEM;
333b8e788a5SAdrian Chadd 		}
334b8e788a5SAdrian Chadd 		m0 = m;
335b8e788a5SAdrian Chadd 		error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
336b8e788a5SAdrian Chadd 					     bf->bf_segs, &bf->bf_nseg,
337b8e788a5SAdrian Chadd 					     BUS_DMA_NOWAIT);
338b8e788a5SAdrian Chadd 		if (error != 0) {
339b8e788a5SAdrian Chadd 			sc->sc_stats.ast_tx_busdma++;
340b8e788a5SAdrian Chadd 			ath_freetx(m0);
341b8e788a5SAdrian Chadd 			return error;
342b8e788a5SAdrian Chadd 		}
343b8e788a5SAdrian Chadd 		KASSERT(bf->bf_nseg <= ATH_TXDESC,
344b8e788a5SAdrian Chadd 		    ("too many segments after defrag; nseg %u", bf->bf_nseg));
345b8e788a5SAdrian Chadd 	} else if (bf->bf_nseg == 0) {		/* null packet, discard */
346b8e788a5SAdrian Chadd 		sc->sc_stats.ast_tx_nodata++;
347b8e788a5SAdrian Chadd 		ath_freetx(m0);
348b8e788a5SAdrian Chadd 		return EIO;
349b8e788a5SAdrian Chadd 	}
350b8e788a5SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n",
351b8e788a5SAdrian Chadd 		__func__, m0, m0->m_pkthdr.len);
352b8e788a5SAdrian Chadd 	bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
353b8e788a5SAdrian Chadd 	bf->bf_m = m0;
354b8e788a5SAdrian Chadd 
355b8e788a5SAdrian Chadd 	return 0;
356b8e788a5SAdrian Chadd }
357b8e788a5SAdrian Chadd 
3586edf1dc7SAdrian Chadd /*
3596e84772fSAdrian Chadd  * Chain together segments+descriptors for a frame - 11n or otherwise.
3606e84772fSAdrian Chadd  *
3616e84772fSAdrian Chadd  * For aggregates, this is called on each frame in the aggregate.
3626edf1dc7SAdrian Chadd  */
363b8e788a5SAdrian Chadd static void
3646e84772fSAdrian Chadd ath_tx_chaindesclist(struct ath_softc *sc, struct ath_desc *ds0,
3656e84772fSAdrian Chadd     struct ath_buf *bf, int is_aggr, int is_first_subframe,
3666e84772fSAdrian Chadd     int is_last_subframe)
367b8e788a5SAdrian Chadd {
368b8e788a5SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
3696e84772fSAdrian Chadd 	char *ds;
3702b200bb4SAdrian Chadd 	int i, bp, dsp;
37146634305SAdrian Chadd 	HAL_DMA_ADDR bufAddrList[4];
37246634305SAdrian Chadd 	uint32_t segLenList[4];
3732b200bb4SAdrian Chadd 	int numTxMaps = 1;
374e2137b86SAdrian Chadd 	int isFirstDesc = 1;
37546634305SAdrian Chadd 
3763d9b1596SAdrian Chadd 	/*
3773d9b1596SAdrian Chadd 	 * XXX There's txdma and txdma_mgmt; the descriptor
3783d9b1596SAdrian Chadd 	 * sizes must match.
3793d9b1596SAdrian Chadd 	 */
3803d9b1596SAdrian Chadd 	struct ath_descdma *dd = &sc->sc_txdma;
381b8e788a5SAdrian Chadd 
382b8e788a5SAdrian Chadd 	/*
383b8e788a5SAdrian Chadd 	 * Fillin the remainder of the descriptor info.
384b8e788a5SAdrian Chadd 	 */
38546634305SAdrian Chadd 
3862b200bb4SAdrian Chadd 	/*
387378a752fSAdrian Chadd 	 * We need the number of TX data pointers in each descriptor.
388378a752fSAdrian Chadd 	 * EDMA and later chips support 4 TX buffers per descriptor;
389378a752fSAdrian Chadd 	 * previous chips just support one.
3902b200bb4SAdrian Chadd 	 */
391378a752fSAdrian Chadd 	numTxMaps = sc->sc_tx_nmaps;
3922b200bb4SAdrian Chadd 
3932b200bb4SAdrian Chadd 	/*
3942b200bb4SAdrian Chadd 	 * For EDMA and later chips ensure the TX map is fully populated
3952b200bb4SAdrian Chadd 	 * before advancing to the next descriptor.
3962b200bb4SAdrian Chadd 	 */
3976e84772fSAdrian Chadd 	ds = (char *) bf->bf_desc;
3982b200bb4SAdrian Chadd 	bp = dsp = 0;
3992b200bb4SAdrian Chadd 	bzero(bufAddrList, sizeof(bufAddrList));
4002b200bb4SAdrian Chadd 	bzero(segLenList, sizeof(segLenList));
4012b200bb4SAdrian Chadd 	for (i = 0; i < bf->bf_nseg; i++) {
4022b200bb4SAdrian Chadd 		bufAddrList[bp] = bf->bf_segs[i].ds_addr;
4032b200bb4SAdrian Chadd 		segLenList[bp] = bf->bf_segs[i].ds_len;
4042b200bb4SAdrian Chadd 		bp++;
4052b200bb4SAdrian Chadd 
4062b200bb4SAdrian Chadd 		/*
4072b200bb4SAdrian Chadd 		 * Go to the next segment if this isn't the last segment
4082b200bb4SAdrian Chadd 		 * and there's space in the current TX map.
4092b200bb4SAdrian Chadd 		 */
4102b200bb4SAdrian Chadd 		if ((i != bf->bf_nseg - 1) && (bp < numTxMaps))
4112b200bb4SAdrian Chadd 			continue;
4122b200bb4SAdrian Chadd 
4132b200bb4SAdrian Chadd 		/*
4142b200bb4SAdrian Chadd 		 * Last segment or we're out of buffer pointers.
4152b200bb4SAdrian Chadd 		 */
4162b200bb4SAdrian Chadd 		bp = 0;
41746634305SAdrian Chadd 
418b8e788a5SAdrian Chadd 		if (i == bf->bf_nseg - 1)
41942083b3dSAdrian Chadd 			ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 0);
420b8e788a5SAdrian Chadd 		else
42142083b3dSAdrian Chadd 			ath_hal_settxdesclink(ah, (struct ath_desc *) ds,
4222b200bb4SAdrian Chadd 			    bf->bf_daddr + dd->dd_descsize * (dsp + 1));
42346634305SAdrian Chadd 
42446634305SAdrian Chadd 		/*
425fc56c9c5SAdrian Chadd 		 * XXX This assumes that bfs_txq is the actual destination
426fc56c9c5SAdrian Chadd 		 * hardware queue at this point.  It may not have been
427fc56c9c5SAdrian Chadd 		 * assigned, it may actually be pointing to the multicast
428fc56c9c5SAdrian Chadd 		 * software TXQ id.  These must be fixed!
42946634305SAdrian Chadd 		 */
43042083b3dSAdrian Chadd 		ath_hal_filltxdesc(ah, (struct ath_desc *) ds
43146634305SAdrian Chadd 			, bufAddrList
43246634305SAdrian Chadd 			, segLenList
4332b200bb4SAdrian Chadd 			, bf->bf_descid		/* XXX desc id */
434fc56c9c5SAdrian Chadd 			, bf->bf_state.bfs_tx_queue
435e2137b86SAdrian Chadd 			, isFirstDesc		/* first segment */
436b8e788a5SAdrian Chadd 			, i == bf->bf_nseg - 1	/* last segment */
43742083b3dSAdrian Chadd 			, (struct ath_desc *) ds0	/* first descriptor */
438b8e788a5SAdrian Chadd 		);
43921840808SAdrian Chadd 
4406e84772fSAdrian Chadd 		/*
4416e84772fSAdrian Chadd 		 * Make sure the 11n aggregate fields are cleared.
4426e84772fSAdrian Chadd 		 *
4436e84772fSAdrian Chadd 		 * XXX TODO: this doesn't need to be called for
4446e84772fSAdrian Chadd 		 * aggregate frames; as it'll be called on all
4456e84772fSAdrian Chadd 		 * sub-frames.  Since the descriptors are in
4466e84772fSAdrian Chadd 		 * non-cacheable memory, this leads to some
4476e84772fSAdrian Chadd 		 * rather slow writes on MIPS/ARM platforms.
4486e84772fSAdrian Chadd 		 */
44921840808SAdrian Chadd 		if (ath_tx_is_11n(sc))
4505d9b19f7SAdrian Chadd 			ath_hal_clr11n_aggr(sc->sc_ah, (struct ath_desc *) ds);
45121840808SAdrian Chadd 
4526e84772fSAdrian Chadd 		/*
4536e84772fSAdrian Chadd 		 * If 11n is enabled, set it up as if it's an aggregate
4546e84772fSAdrian Chadd 		 * frame.
4556e84772fSAdrian Chadd 		 */
4566e84772fSAdrian Chadd 		if (is_last_subframe) {
4576e84772fSAdrian Chadd 			ath_hal_set11n_aggr_last(sc->sc_ah,
4586e84772fSAdrian Chadd 			    (struct ath_desc *) ds);
4596e84772fSAdrian Chadd 		} else if (is_aggr) {
4606e84772fSAdrian Chadd 			/*
4616e84772fSAdrian Chadd 			 * This clears the aggrlen field; so
4626e84772fSAdrian Chadd 			 * the caller needs to call set_aggr_first()!
4636e84772fSAdrian Chadd 			 *
4646e84772fSAdrian Chadd 			 * XXX TODO: don't call this for the first
4656e84772fSAdrian Chadd 			 * descriptor in the first frame in an
4666e84772fSAdrian Chadd 			 * aggregate!
4676e84772fSAdrian Chadd 			 */
4686e84772fSAdrian Chadd 			ath_hal_set11n_aggr_middle(sc->sc_ah,
4696e84772fSAdrian Chadd 			    (struct ath_desc *) ds,
4706e84772fSAdrian Chadd 			    bf->bf_state.bfs_ndelim);
4716e84772fSAdrian Chadd 		}
472e2137b86SAdrian Chadd 		isFirstDesc = 0;
47342083b3dSAdrian Chadd 		bf->bf_lastds = (struct ath_desc *) ds;
4742b200bb4SAdrian Chadd 
4752b200bb4SAdrian Chadd 		/*
4762b200bb4SAdrian Chadd 		 * Don't forget to skip to the next descriptor.
4772b200bb4SAdrian Chadd 		 */
47842083b3dSAdrian Chadd 		ds += sc->sc_tx_desclen;
4792b200bb4SAdrian Chadd 		dsp++;
4802b200bb4SAdrian Chadd 
4812b200bb4SAdrian Chadd 		/*
4822b200bb4SAdrian Chadd 		 * .. and don't forget to blank these out!
4832b200bb4SAdrian Chadd 		 */
4842b200bb4SAdrian Chadd 		bzero(bufAddrList, sizeof(bufAddrList));
4852b200bb4SAdrian Chadd 		bzero(segLenList, sizeof(segLenList));
486b8e788a5SAdrian Chadd 	}
4874d7f8837SAdrian Chadd 	bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
48881a82688SAdrian Chadd }
48981a82688SAdrian Chadd 
490eb6f0de0SAdrian Chadd /*
491d34a7347SAdrian Chadd  * Set the rate control fields in the given descriptor based on
492d34a7347SAdrian Chadd  * the bf_state fields and node state.
493d34a7347SAdrian Chadd  *
494d34a7347SAdrian Chadd  * The bfs fields should already be set with the relevant rate
495d34a7347SAdrian Chadd  * control information, including whether MRR is to be enabled.
496d34a7347SAdrian Chadd  *
497d34a7347SAdrian Chadd  * Since the FreeBSD HAL currently sets up the first TX rate
498d34a7347SAdrian Chadd  * in ath_hal_setuptxdesc(), this will setup the MRR
499d34a7347SAdrian Chadd  * conditionally for the pre-11n chips, and call ath_buf_set_rate
500d34a7347SAdrian Chadd  * unconditionally for 11n chips. These require the 11n rate
501d34a7347SAdrian Chadd  * scenario to be set if MCS rates are enabled, so it's easier
502d34a7347SAdrian Chadd  * to just always call it. The caller can then only set rates 2, 3
503d34a7347SAdrian Chadd  * and 4 if multi-rate retry is needed.
504d34a7347SAdrian Chadd  */
505d34a7347SAdrian Chadd static void
506d34a7347SAdrian Chadd ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
507d34a7347SAdrian Chadd     struct ath_buf *bf)
508d34a7347SAdrian Chadd {
509d34a7347SAdrian Chadd 	struct ath_rc_series *rc = bf->bf_state.bfs_rc;
510d34a7347SAdrian Chadd 
511d34a7347SAdrian Chadd 	/* If mrr is disabled, blank tries 1, 2, 3 */
512d34a7347SAdrian Chadd 	if (! bf->bf_state.bfs_ismrr)
513d34a7347SAdrian Chadd 		rc[1].tries = rc[2].tries = rc[3].tries = 0;
514d34a7347SAdrian Chadd 
515491e1248SAdrian Chadd #if 0
516491e1248SAdrian Chadd 	/*
517491e1248SAdrian Chadd 	 * If NOACK is set, just set ntries=1.
518491e1248SAdrian Chadd 	 */
519491e1248SAdrian Chadd 	else if (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) {
520491e1248SAdrian Chadd 		rc[1].tries = rc[2].tries = rc[3].tries = 0;
521491e1248SAdrian Chadd 		rc[0].tries = 1;
522491e1248SAdrian Chadd 	}
523491e1248SAdrian Chadd #endif
524491e1248SAdrian Chadd 
525d34a7347SAdrian Chadd 	/*
526d34a7347SAdrian Chadd 	 * Always call - that way a retried descriptor will
527d34a7347SAdrian Chadd 	 * have the MRR fields overwritten.
528d34a7347SAdrian Chadd 	 *
529d34a7347SAdrian Chadd 	 * XXX TODO: see if this is really needed - setting up
530d34a7347SAdrian Chadd 	 * the first descriptor should set the MRR fields to 0
531d34a7347SAdrian Chadd 	 * for us anyway.
532d34a7347SAdrian Chadd 	 */
533d34a7347SAdrian Chadd 	if (ath_tx_is_11n(sc)) {
534d34a7347SAdrian Chadd 		ath_buf_set_rate(sc, ni, bf);
535d34a7347SAdrian Chadd 	} else {
536d34a7347SAdrian Chadd 		ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc
537d34a7347SAdrian Chadd 			, rc[1].ratecode, rc[1].tries
538d34a7347SAdrian Chadd 			, rc[2].ratecode, rc[2].tries
539d34a7347SAdrian Chadd 			, rc[3].ratecode, rc[3].tries
540d34a7347SAdrian Chadd 		);
541d34a7347SAdrian Chadd 	}
542d34a7347SAdrian Chadd }
543d34a7347SAdrian Chadd 
544d34a7347SAdrian Chadd /*
545eb6f0de0SAdrian Chadd  * Setup segments+descriptors for an 11n aggregate.
546eb6f0de0SAdrian Chadd  * bf_first is the first buffer in the aggregate.
547eb6f0de0SAdrian Chadd  * The descriptor list must already been linked together using
548eb6f0de0SAdrian Chadd  * bf->bf_next.
549eb6f0de0SAdrian Chadd  */
550eb6f0de0SAdrian Chadd static void
551eb6f0de0SAdrian Chadd ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first)
552eb6f0de0SAdrian Chadd {
553eb6f0de0SAdrian Chadd 	struct ath_buf *bf, *bf_prev = NULL;
5546e84772fSAdrian Chadd 	struct ath_desc *ds0 = bf_first->bf_desc;
555eb6f0de0SAdrian Chadd 
556eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n",
557eb6f0de0SAdrian Chadd 	    __func__, bf_first->bf_state.bfs_nframes,
558eb6f0de0SAdrian Chadd 	    bf_first->bf_state.bfs_al);
559eb6f0de0SAdrian Chadd 
5607d9dd2acSAdrian Chadd 	bf = bf_first;
5617d9dd2acSAdrian Chadd 
5627d9dd2acSAdrian Chadd 	if (bf->bf_state.bfs_txrate0 == 0)
5637d9dd2acSAdrian Chadd 		device_printf(sc->sc_dev, "%s: bf=%p, txrate0=%d\n",
5647d9dd2acSAdrian Chadd 		    __func__, bf, 0);
5657d9dd2acSAdrian Chadd 	if (bf->bf_state.bfs_rc[0].ratecode == 0)
5667d9dd2acSAdrian Chadd 		device_printf(sc->sc_dev, "%s: bf=%p, rix0=%d\n",
5677d9dd2acSAdrian Chadd 		    __func__, bf, 0);
5687d9dd2acSAdrian Chadd 
569eb6f0de0SAdrian Chadd 	/*
5706e84772fSAdrian Chadd 	 * Setup all descriptors of all subframes - this will
5716e84772fSAdrian Chadd 	 * call ath_hal_set11naggrmiddle() on every frame.
572eb6f0de0SAdrian Chadd 	 */
573eb6f0de0SAdrian Chadd 	while (bf != NULL) {
574eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
575eb6f0de0SAdrian Chadd 		    "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n",
576eb6f0de0SAdrian Chadd 		    __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen,
577eb6f0de0SAdrian Chadd 		    SEQNO(bf->bf_state.bfs_seqno));
578eb6f0de0SAdrian Chadd 
5796e84772fSAdrian Chadd 		/*
5806e84772fSAdrian Chadd 		 * Setup the initial fields for the first descriptor - all
5816e84772fSAdrian Chadd 		 * the non-11n specific stuff.
5826e84772fSAdrian Chadd 		 */
5836e84772fSAdrian Chadd 		ath_hal_setuptxdesc(sc->sc_ah, bf->bf_desc
5846e84772fSAdrian Chadd 			, bf->bf_state.bfs_pktlen	/* packet length */
5856e84772fSAdrian Chadd 			, bf->bf_state.bfs_hdrlen	/* header length */
5866e84772fSAdrian Chadd 			, bf->bf_state.bfs_atype	/* Atheros packet type */
5876e84772fSAdrian Chadd 			, bf->bf_state.bfs_txpower	/* txpower */
5886e84772fSAdrian Chadd 			, bf->bf_state.bfs_txrate0
5896e84772fSAdrian Chadd 			, bf->bf_state.bfs_try0		/* series 0 rate/tries */
5906e84772fSAdrian Chadd 			, bf->bf_state.bfs_keyix	/* key cache index */
5916e84772fSAdrian Chadd 			, bf->bf_state.bfs_txantenna	/* antenna mode */
5926e84772fSAdrian Chadd 			, bf->bf_state.bfs_txflags | HAL_TXDESC_INTREQ	/* flags */
5936e84772fSAdrian Chadd 			, bf->bf_state.bfs_ctsrate	/* rts/cts rate */
5946e84772fSAdrian Chadd 			, bf->bf_state.bfs_ctsduration	/* rts/cts duration */
5956e84772fSAdrian Chadd 		);
5966e84772fSAdrian Chadd 
5976e84772fSAdrian Chadd 		/*
5986e84772fSAdrian Chadd 		 * First descriptor? Setup the rate control and initial
5996e84772fSAdrian Chadd 		 * aggregate header information.
6006e84772fSAdrian Chadd 		 */
6016e84772fSAdrian Chadd 		if (bf == bf_first) {
6026e84772fSAdrian Chadd 			/*
6036e84772fSAdrian Chadd 			 * setup first desc with rate and aggr info
6046e84772fSAdrian Chadd 			 */
6056e84772fSAdrian Chadd 			ath_tx_set_ratectrl(sc, bf->bf_node, bf);
6066e84772fSAdrian Chadd 		}
6076e84772fSAdrian Chadd 
6086e84772fSAdrian Chadd 		/*
6096e84772fSAdrian Chadd 		 * Setup the descriptors for a multi-descriptor frame.
6106e84772fSAdrian Chadd 		 * This is both aggregate and non-aggregate aware.
6116e84772fSAdrian Chadd 		 */
6126e84772fSAdrian Chadd 		ath_tx_chaindesclist(sc, ds0, bf,
6136e84772fSAdrian Chadd 		    1, /* is_aggr */
6146e84772fSAdrian Chadd 		    !! (bf == bf_first), /* is_first_subframe */
6156e84772fSAdrian Chadd 		    !! (bf->bf_next == NULL) /* is_last_subframe */
6166e84772fSAdrian Chadd 		    );
6176e84772fSAdrian Chadd 
6186e84772fSAdrian Chadd 		if (bf == bf_first) {
6196e84772fSAdrian Chadd 			/*
6206e84772fSAdrian Chadd 			 * Initialise the first 11n aggregate with the
6216e84772fSAdrian Chadd 			 * aggregate length and aggregate enable bits.
6226e84772fSAdrian Chadd 			 */
6236e84772fSAdrian Chadd 			ath_hal_set11n_aggr_first(sc->sc_ah,
6246e84772fSAdrian Chadd 			    ds0,
6256e84772fSAdrian Chadd 			    bf->bf_state.bfs_al,
6266e84772fSAdrian Chadd 			    bf->bf_state.bfs_ndelim);
6276e84772fSAdrian Chadd 		}
628eb6f0de0SAdrian Chadd 
629eb6f0de0SAdrian Chadd 		/*
630eb6f0de0SAdrian Chadd 		 * Link the last descriptor of the previous frame
631eb6f0de0SAdrian Chadd 		 * to the beginning descriptor of this frame.
632eb6f0de0SAdrian Chadd 		 */
633eb6f0de0SAdrian Chadd 		if (bf_prev != NULL)
634bb069955SAdrian Chadd 			ath_hal_settxdesclink(sc->sc_ah, bf_prev->bf_lastds,
635bb069955SAdrian Chadd 			    bf->bf_daddr);
636eb6f0de0SAdrian Chadd 
637eb6f0de0SAdrian Chadd 		/* Save a copy so we can link the next descriptor in */
638eb6f0de0SAdrian Chadd 		bf_prev = bf;
639eb6f0de0SAdrian Chadd 		bf = bf->bf_next;
640eb6f0de0SAdrian Chadd 	}
641eb6f0de0SAdrian Chadd 
642eb6f0de0SAdrian Chadd 	/*
643eb6f0de0SAdrian Chadd 	 * Set the first descriptor bf_lastds field to point to
644eb6f0de0SAdrian Chadd 	 * the last descriptor in the last subframe, that's where
645eb6f0de0SAdrian Chadd 	 * the status update will occur.
646eb6f0de0SAdrian Chadd 	 */
647eb6f0de0SAdrian Chadd 	bf_first->bf_lastds = bf_prev->bf_lastds;
648eb6f0de0SAdrian Chadd 
649eb6f0de0SAdrian Chadd 	/*
650eb6f0de0SAdrian Chadd 	 * And bf_last in the first descriptor points to the end of
651eb6f0de0SAdrian Chadd 	 * the aggregate list.
652eb6f0de0SAdrian Chadd 	 */
653eb6f0de0SAdrian Chadd 	bf_first->bf_last = bf_prev;
654eb6f0de0SAdrian Chadd 
655bbdf3df1SAdrian Chadd 	/*
656bbdf3df1SAdrian Chadd 	 * For non-AR9300 NICs, which require the rate control
657bbdf3df1SAdrian Chadd 	 * in the final descriptor - let's set that up now.
658bbdf3df1SAdrian Chadd 	 *
659bbdf3df1SAdrian Chadd 	 * This is because the filltxdesc() HAL call doesn't
660bbdf3df1SAdrian Chadd 	 * populate the last segment with rate control information
661bbdf3df1SAdrian Chadd 	 * if firstSeg is also true.  For non-aggregate frames
662bbdf3df1SAdrian Chadd 	 * that is fine, as the first frame already has rate control
663bbdf3df1SAdrian Chadd 	 * info.  But if the last frame in an aggregate has one
664bbdf3df1SAdrian Chadd 	 * descriptor, both firstseg and lastseg will be true and
665bbdf3df1SAdrian Chadd 	 * the rate info isn't copied.
666bbdf3df1SAdrian Chadd 	 *
667bbdf3df1SAdrian Chadd 	 * This is inefficient on MIPS/ARM platforms that have
668bbdf3df1SAdrian Chadd 	 * non-cachable memory for TX descriptors, but we'll just
669bbdf3df1SAdrian Chadd 	 * make do for now.
670bbdf3df1SAdrian Chadd 	 *
671bbdf3df1SAdrian Chadd 	 * As to why the rate table is stashed in the last descriptor
672bbdf3df1SAdrian Chadd 	 * rather than the first descriptor?  Because proctxdesc()
673bbdf3df1SAdrian Chadd 	 * is called on the final descriptor in an MPDU or A-MPDU -
674bbdf3df1SAdrian Chadd 	 * ie, the one that gets updated by the hardware upon
675bbdf3df1SAdrian Chadd 	 * completion.  That way proctxdesc() doesn't need to know
676bbdf3df1SAdrian Chadd 	 * about the first _and_ last TX descriptor.
677bbdf3df1SAdrian Chadd 	 */
678bbdf3df1SAdrian Chadd 	ath_hal_setuplasttxdesc(sc->sc_ah, bf_prev->bf_lastds, ds0);
679bbdf3df1SAdrian Chadd 
680eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__);
681eb6f0de0SAdrian Chadd }
682eb6f0de0SAdrian Chadd 
68346634305SAdrian Chadd /*
68446634305SAdrian Chadd  * Hand-off a frame to the multicast TX queue.
68546634305SAdrian Chadd  *
68646634305SAdrian Chadd  * This is a software TXQ which will be appended to the CAB queue
68746634305SAdrian Chadd  * during the beacon setup code.
68846634305SAdrian Chadd  *
68946634305SAdrian Chadd  * XXX TODO: since the AR9300 EDMA TX queue support wants the QCU ID
690fc56c9c5SAdrian Chadd  * as part of the TX descriptor, bf_state.bfs_tx_queue must be updated
69146634305SAdrian Chadd  * with the actual hardware txq, or all of this will fall apart.
69246634305SAdrian Chadd  *
69346634305SAdrian Chadd  * XXX It may not be a bad idea to just stuff the QCU ID into bf_state
694fc56c9c5SAdrian Chadd  * and retire bfs_tx_queue; then make sure the CABQ QCU ID is populated
69546634305SAdrian Chadd  * correctly.
69646634305SAdrian Chadd  */
697eb6f0de0SAdrian Chadd static void
698eb6f0de0SAdrian Chadd ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
699eb6f0de0SAdrian Chadd     struct ath_buf *bf)
700eb6f0de0SAdrian Chadd {
701375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
702375307d4SAdrian Chadd 
703eb6f0de0SAdrian Chadd 	KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
704eb6f0de0SAdrian Chadd 	     ("%s: busy status 0x%x", __func__, bf->bf_flags));
70556a85978SAdrian Chadd 
70656a85978SAdrian Chadd 	ATH_TXQ_LOCK(txq);
707*0891354cSAdrian Chadd 	if (ATH_TXQ_LAST(txq, axq_q_s) != NULL) {
708*0891354cSAdrian Chadd 		struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s);
709eb6f0de0SAdrian Chadd 		struct ieee80211_frame *wh;
710eb6f0de0SAdrian Chadd 
711eb6f0de0SAdrian Chadd 		/* mark previous frame */
712*0891354cSAdrian Chadd 		wh = mtod(bf_last->bf_m, struct ieee80211_frame *);
713eb6f0de0SAdrian Chadd 		wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
714*0891354cSAdrian Chadd 		bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap,
715eb6f0de0SAdrian Chadd 		    BUS_DMASYNC_PREWRITE);
716eb6f0de0SAdrian Chadd 
717eb6f0de0SAdrian Chadd 		/* link descriptor */
718*0891354cSAdrian Chadd 		ath_hal_settxdesclink(sc->sc_ah,
719*0891354cSAdrian Chadd 		    bf_last->bf_lastds,
720*0891354cSAdrian Chadd 		    bf->bf_daddr);
721eb6f0de0SAdrian Chadd 	}
722eb6f0de0SAdrian Chadd 	ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
723bb069955SAdrian Chadd 	ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link);
724b837332dSAdrian Chadd 	ATH_TXQ_UNLOCK(txq);
725eb6f0de0SAdrian Chadd }
726eb6f0de0SAdrian Chadd 
727eb6f0de0SAdrian Chadd /*
728eb6f0de0SAdrian Chadd  * Hand-off packet to a hardware queue.
729eb6f0de0SAdrian Chadd  */
730eb6f0de0SAdrian Chadd static void
731d4365d16SAdrian Chadd ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
732d4365d16SAdrian Chadd     struct ath_buf *bf)
733eb6f0de0SAdrian Chadd {
734eb6f0de0SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
73581a82688SAdrian Chadd 
736b8e788a5SAdrian Chadd 	/*
737b8e788a5SAdrian Chadd 	 * Insert the frame on the outbound list and pass it on
738b8e788a5SAdrian Chadd 	 * to the hardware.  Multicast frames buffered for power
739b8e788a5SAdrian Chadd 	 * save stations and transmit from the CAB queue are stored
740b8e788a5SAdrian Chadd 	 * on a s/w only queue and loaded on to the CAB queue in
741b8e788a5SAdrian Chadd 	 * the SWBA handler since frames only go out on DTIM and
742b8e788a5SAdrian Chadd 	 * to avoid possible races.
743b8e788a5SAdrian Chadd 	 */
744375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
745b8e788a5SAdrian Chadd 	KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
746eb6f0de0SAdrian Chadd 	     ("%s: busy status 0x%x", __func__, bf->bf_flags));
747eb6f0de0SAdrian Chadd 	KASSERT(txq->axq_qnum != ATH_TXQ_SWQ,
748eb6f0de0SAdrian Chadd 	     ("ath_tx_handoff_hw called for mcast queue"));
749eb6f0de0SAdrian Chadd 
750ef27340cSAdrian Chadd #if 0
751ef27340cSAdrian Chadd 	/*
752ef27340cSAdrian Chadd 	 * This causes a LOR. Find out where the PCU lock is being
753ef27340cSAdrian Chadd 	 * held whilst the TXQ lock is grabbed - that shouldn't
754ef27340cSAdrian Chadd 	 * be occuring.
755ef27340cSAdrian Chadd 	 */
756ef27340cSAdrian Chadd 	ATH_PCU_LOCK(sc);
757ef27340cSAdrian Chadd 	if (sc->sc_inreset_cnt) {
758ef27340cSAdrian Chadd 		ATH_PCU_UNLOCK(sc);
759ef27340cSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_RESET,
760ef27340cSAdrian Chadd 		    "%s: called with sc_in_reset != 0\n",
761ef27340cSAdrian Chadd 		    __func__);
762ef27340cSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_XMIT,
763ef27340cSAdrian Chadd 		    "%s: queued: TXDP[%u] = %p (%p) depth %d\n",
764ef27340cSAdrian Chadd 		    __func__, txq->axq_qnum,
765ef27340cSAdrian Chadd 		    (caddr_t)bf->bf_daddr, bf->bf_desc,
766ef27340cSAdrian Chadd 		    txq->axq_depth);
767ef27340cSAdrian Chadd 		ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
768ef27340cSAdrian Chadd 		if (bf->bf_state.bfs_aggr)
769ef27340cSAdrian Chadd 			txq->axq_aggr_depth++;
770ef27340cSAdrian Chadd 		/*
771ef27340cSAdrian Chadd 		 * There's no need to update axq_link; the hardware
772ef27340cSAdrian Chadd 		 * is in reset and once the reset is complete, any
773ef27340cSAdrian Chadd 		 * non-empty queues will simply have DMA restarted.
774ef27340cSAdrian Chadd 		 */
775ef27340cSAdrian Chadd 		return;
776ef27340cSAdrian Chadd 		}
777ef27340cSAdrian Chadd 	ATH_PCU_UNLOCK(sc);
778ef27340cSAdrian Chadd #endif
779ef27340cSAdrian Chadd 
780eb6f0de0SAdrian Chadd 	/* For now, so not to generate whitespace diffs */
781eb6f0de0SAdrian Chadd 	if (1) {
782b837332dSAdrian Chadd 		ATH_TXQ_LOCK(txq);
783b8e788a5SAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
784b8e788a5SAdrian Chadd 		int qbusy;
785b8e788a5SAdrian Chadd 
786b8e788a5SAdrian Chadd 		ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
787b8e788a5SAdrian Chadd 		qbusy = ath_hal_txqenabled(ah, txq->axq_qnum);
78803682514SAdrian Chadd 
78903682514SAdrian Chadd 		ATH_KTR(sc, ATH_KTR_TX, 4,
79003682514SAdrian Chadd 		    "ath_tx_handoff: txq=%u, add bf=%p, qbusy=%d, depth=%d",
79103682514SAdrian Chadd 		    txq->axq_qnum, bf, qbusy, txq->axq_depth);
792b8e788a5SAdrian Chadd 		if (txq->axq_link == NULL) {
793b8e788a5SAdrian Chadd 			/*
794b8e788a5SAdrian Chadd 			 * Be careful writing the address to TXDP.  If
795b8e788a5SAdrian Chadd 			 * the tx q is enabled then this write will be
796b8e788a5SAdrian Chadd 			 * ignored.  Normally this is not an issue but
797b8e788a5SAdrian Chadd 			 * when tdma is in use and the q is beacon gated
798b8e788a5SAdrian Chadd 			 * this race can occur.  If the q is busy then
799b8e788a5SAdrian Chadd 			 * defer the work to later--either when another
800b8e788a5SAdrian Chadd 			 * packet comes along or when we prepare a beacon
801b8e788a5SAdrian Chadd 			 * frame at SWBA.
802b8e788a5SAdrian Chadd 			 */
803b8e788a5SAdrian Chadd 			if (!qbusy) {
804d4365d16SAdrian Chadd 				ath_hal_puttxbuf(ah, txq->axq_qnum,
805d4365d16SAdrian Chadd 				    bf->bf_daddr);
806b8e788a5SAdrian Chadd 				txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
807b8e788a5SAdrian Chadd 				DPRINTF(sc, ATH_DEBUG_XMIT,
80803682514SAdrian Chadd 				    "%s: TXDP[%u] = %p (%p) lastds=%p depth %d\n",
809b8e788a5SAdrian Chadd 				    __func__, txq->axq_qnum,
810b8e788a5SAdrian Chadd 				    (caddr_t)bf->bf_daddr, bf->bf_desc,
81103682514SAdrian Chadd 				    bf->bf_lastds,
81203682514SAdrian Chadd 				    txq->axq_depth);
81303682514SAdrian Chadd 				ATH_KTR(sc, ATH_KTR_TX, 5,
81403682514SAdrian Chadd 				    "ath_tx_handoff: TXDP[%u] = %p (%p) "
81503682514SAdrian Chadd 				    "lastds=%p depth %d",
81603682514SAdrian Chadd 				    txq->axq_qnum,
81703682514SAdrian Chadd 				    (caddr_t)bf->bf_daddr, bf->bf_desc,
81803682514SAdrian Chadd 				    bf->bf_lastds,
819b8e788a5SAdrian Chadd 				    txq->axq_depth);
820b8e788a5SAdrian Chadd 			} else {
821b8e788a5SAdrian Chadd 				txq->axq_flags |= ATH_TXQ_PUTPENDING;
822b8e788a5SAdrian Chadd 				DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
823b8e788a5SAdrian Chadd 				    "%s: Q%u busy, defer enable\n", __func__,
824b8e788a5SAdrian Chadd 				    txq->axq_qnum);
82503682514SAdrian Chadd 				ATH_KTR(sc, ATH_KTR_TX, 0, "defer enable");
826b8e788a5SAdrian Chadd 			}
827b8e788a5SAdrian Chadd 		} else {
828b8e788a5SAdrian Chadd 			*txq->axq_link = bf->bf_daddr;
829b8e788a5SAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_XMIT,
830b8e788a5SAdrian Chadd 			    "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
831b8e788a5SAdrian Chadd 			    txq->axq_qnum, txq->axq_link,
832d4365d16SAdrian Chadd 			    (caddr_t)bf->bf_daddr, bf->bf_desc,
833d4365d16SAdrian Chadd 			    txq->axq_depth);
83403682514SAdrian Chadd 			ATH_KTR(sc, ATH_KTR_TX, 5,
83503682514SAdrian Chadd 			    "ath_tx_handoff: link[%u](%p)=%p (%p) lastds=%p",
83603682514SAdrian Chadd 			    txq->axq_qnum, txq->axq_link,
83703682514SAdrian Chadd 			    (caddr_t)bf->bf_daddr, bf->bf_desc,
83803682514SAdrian Chadd 			    bf->bf_lastds);
83903682514SAdrian Chadd 
840b8e788a5SAdrian Chadd 			if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) {
841b8e788a5SAdrian Chadd 				/*
842b8e788a5SAdrian Chadd 				 * The q was busy when we previously tried
843b8e788a5SAdrian Chadd 				 * to write the address of the first buffer
844b8e788a5SAdrian Chadd 				 * in the chain.  Since it's not busy now
845b8e788a5SAdrian Chadd 				 * handle this chore.  We are certain the
846b8e788a5SAdrian Chadd 				 * buffer at the front is the right one since
847b8e788a5SAdrian Chadd 				 * axq_link is NULL only when the buffer list
848b8e788a5SAdrian Chadd 				 * is/was empty.
849b8e788a5SAdrian Chadd 				 */
850b8e788a5SAdrian Chadd 				ath_hal_puttxbuf(ah, txq->axq_qnum,
8516b349e5aSAdrian Chadd 					TAILQ_FIRST(&txq->axq_q)->bf_daddr);
852b8e788a5SAdrian Chadd 				txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
853b8e788a5SAdrian Chadd 				DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
854b8e788a5SAdrian Chadd 				    "%s: Q%u restarted\n", __func__,
855b8e788a5SAdrian Chadd 				    txq->axq_qnum);
85603682514SAdrian Chadd 				ATH_KTR(sc, ATH_KTR_TX, 4,
85703682514SAdrian Chadd 				  "ath_tx_handoff: txq[%d] restarted, bf=%p "
85803682514SAdrian Chadd 				  "daddr=%p ds=%p",
85903682514SAdrian Chadd 				    txq->axq_qnum,
86003682514SAdrian Chadd 				    bf,
86103682514SAdrian Chadd 				    (caddr_t)bf->bf_daddr,
86203682514SAdrian Chadd 				    bf->bf_desc);
863b8e788a5SAdrian Chadd 			}
864b8e788a5SAdrian Chadd 		}
865b8e788a5SAdrian Chadd #else
866b8e788a5SAdrian Chadd 		ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
867b1dddc28SAdrian Chadd 		ATH_KTR(sc, ATH_KTR_TX, 3,
868b1dddc28SAdrian Chadd 		    "ath_tx_handoff: non-tdma: txq=%u, add bf=%p "
86903682514SAdrian Chadd 		    "depth=%d",
87003682514SAdrian Chadd 		    txq->axq_qnum,
87103682514SAdrian Chadd 		    bf,
87203682514SAdrian Chadd 		    txq->axq_depth);
873b8e788a5SAdrian Chadd 		if (txq->axq_link == NULL) {
874b8e788a5SAdrian Chadd 			ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
875b8e788a5SAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_XMIT,
876b8e788a5SAdrian Chadd 			    "%s: TXDP[%u] = %p (%p) depth %d\n",
877b8e788a5SAdrian Chadd 			    __func__, txq->axq_qnum,
878b8e788a5SAdrian Chadd 			    (caddr_t)bf->bf_daddr, bf->bf_desc,
879b8e788a5SAdrian Chadd 			    txq->axq_depth);
88003682514SAdrian Chadd 			ATH_KTR(sc, ATH_KTR_TX, 5,
88103682514SAdrian Chadd 			    "ath_tx_handoff: non-tdma: TXDP[%u] = %p (%p) "
88203682514SAdrian Chadd 			    "lastds=%p depth %d",
88303682514SAdrian Chadd 			    txq->axq_qnum,
88403682514SAdrian Chadd 			    (caddr_t)bf->bf_daddr, bf->bf_desc,
88503682514SAdrian Chadd 			    bf->bf_lastds,
88603682514SAdrian Chadd 			    txq->axq_depth);
88703682514SAdrian Chadd 
888b8e788a5SAdrian Chadd 		} else {
889b8e788a5SAdrian Chadd 			*txq->axq_link = bf->bf_daddr;
890b8e788a5SAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_XMIT,
891b8e788a5SAdrian Chadd 			    "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
892b8e788a5SAdrian Chadd 			    txq->axq_qnum, txq->axq_link,
893d4365d16SAdrian Chadd 			    (caddr_t)bf->bf_daddr, bf->bf_desc,
894d4365d16SAdrian Chadd 			    txq->axq_depth);
89503682514SAdrian Chadd 			ATH_KTR(sc, ATH_KTR_TX, 5,
89603682514SAdrian Chadd 			    "ath_tx_handoff: non-tdma: link[%u](%p)=%p (%p) "
89703682514SAdrian Chadd 			    "lastds=%d",
89803682514SAdrian Chadd 			    txq->axq_qnum, txq->axq_link,
89903682514SAdrian Chadd 			    (caddr_t)bf->bf_daddr, bf->bf_desc,
90003682514SAdrian Chadd 			    bf->bf_lastds);
90103682514SAdrian Chadd 
902b8e788a5SAdrian Chadd 		}
903b8e788a5SAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */
9046edf1dc7SAdrian Chadd 		if (bf->bf_state.bfs_aggr)
9056edf1dc7SAdrian Chadd 			txq->axq_aggr_depth++;
906bb069955SAdrian Chadd 		ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link);
907b8e788a5SAdrian Chadd 		ath_hal_txstart(ah, txq->axq_qnum);
908b837332dSAdrian Chadd 		ATH_TXQ_UNLOCK(txq);
90903682514SAdrian Chadd 		ATH_KTR(sc, ATH_KTR_TX, 1,
91003682514SAdrian Chadd 		    "ath_tx_handoff: txq=%u, txstart", txq->axq_qnum);
911b8e788a5SAdrian Chadd 	}
912b8e788a5SAdrian Chadd }
913eb6f0de0SAdrian Chadd 
914eb6f0de0SAdrian Chadd /*
915eb6f0de0SAdrian Chadd  * Restart TX DMA for the given TXQ.
916eb6f0de0SAdrian Chadd  *
917eb6f0de0SAdrian Chadd  * This must be called whether the queue is empty or not.
918eb6f0de0SAdrian Chadd  */
919746bab5bSAdrian Chadd static void
920746bab5bSAdrian Chadd ath_legacy_tx_dma_restart(struct ath_softc *sc, struct ath_txq *txq)
921eb6f0de0SAdrian Chadd {
922eb6f0de0SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
923b1f3262cSAdrian Chadd 	struct ath_buf *bf, *bf_last;
924eb6f0de0SAdrian Chadd 
925b837332dSAdrian Chadd 	ATH_TXQ_LOCK_ASSERT(txq);
926eb6f0de0SAdrian Chadd 	/* This is always going to be cleared, empty or not */
927eb6f0de0SAdrian Chadd 	txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
928eb6f0de0SAdrian Chadd 
929b1f3262cSAdrian Chadd 	/* XXX make this ATH_TXQ_FIRST */
930eb6f0de0SAdrian Chadd 	bf = TAILQ_FIRST(&txq->axq_q);
931b1f3262cSAdrian Chadd 	bf_last = ATH_TXQ_LAST(txq, axq_q_s);
932b1f3262cSAdrian Chadd 
933eb6f0de0SAdrian Chadd 	if (bf == NULL)
934eb6f0de0SAdrian Chadd 		return;
935eb6f0de0SAdrian Chadd 
936eb6f0de0SAdrian Chadd 	ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
937d2da5544SAdrian Chadd 	ath_hal_gettxdesclinkptr(ah, bf_last->bf_lastds, &txq->axq_link);
938eb6f0de0SAdrian Chadd 	ath_hal_txstart(ah, txq->axq_qnum);
939eb6f0de0SAdrian Chadd }
940eb6f0de0SAdrian Chadd 
941eb6f0de0SAdrian Chadd /*
942eb6f0de0SAdrian Chadd  * Hand off a packet to the hardware (or mcast queue.)
943eb6f0de0SAdrian Chadd  *
944eb6f0de0SAdrian Chadd  * The relevant hardware txq should be locked.
945eb6f0de0SAdrian Chadd  */
946eb6f0de0SAdrian Chadd static void
947746bab5bSAdrian Chadd ath_legacy_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
948746bab5bSAdrian Chadd     struct ath_buf *bf)
949eb6f0de0SAdrian Chadd {
950375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
951eb6f0de0SAdrian Chadd 
952bb327d28SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
953bb327d28SAdrian Chadd 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
954bb327d28SAdrian Chadd 		ath_tx_alq_post(sc, bf);
955bb327d28SAdrian Chadd #endif
956bb327d28SAdrian Chadd 
957eb6f0de0SAdrian Chadd 	if (txq->axq_qnum == ATH_TXQ_SWQ)
958eb6f0de0SAdrian Chadd 		ath_tx_handoff_mcast(sc, txq, bf);
959eb6f0de0SAdrian Chadd 	else
960eb6f0de0SAdrian Chadd 		ath_tx_handoff_hw(sc, txq, bf);
961b8e788a5SAdrian Chadd }
962b8e788a5SAdrian Chadd 
96381a82688SAdrian Chadd static int
96481a82688SAdrian Chadd ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni,
965d4365d16SAdrian Chadd     struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen,
966d4365d16SAdrian Chadd     int *keyix)
96781a82688SAdrian Chadd {
96812be5b9cSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_XMIT,
96912be5b9cSAdrian Chadd 	    "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n",
97012be5b9cSAdrian Chadd 	    __func__,
97112be5b9cSAdrian Chadd 	    *hdrlen,
97212be5b9cSAdrian Chadd 	    *pktlen,
97312be5b9cSAdrian Chadd 	    isfrag,
97412be5b9cSAdrian Chadd 	    iswep,
97512be5b9cSAdrian Chadd 	    m0);
97612be5b9cSAdrian Chadd 
97781a82688SAdrian Chadd 	if (iswep) {
97881a82688SAdrian Chadd 		const struct ieee80211_cipher *cip;
97981a82688SAdrian Chadd 		struct ieee80211_key *k;
98081a82688SAdrian Chadd 
98181a82688SAdrian Chadd 		/*
98281a82688SAdrian Chadd 		 * Construct the 802.11 header+trailer for an encrypted
98381a82688SAdrian Chadd 		 * frame. The only reason this can fail is because of an
98481a82688SAdrian Chadd 		 * unknown or unsupported cipher/key type.
98581a82688SAdrian Chadd 		 */
98681a82688SAdrian Chadd 		k = ieee80211_crypto_encap(ni, m0);
98781a82688SAdrian Chadd 		if (k == NULL) {
98881a82688SAdrian Chadd 			/*
98981a82688SAdrian Chadd 			 * This can happen when the key is yanked after the
99081a82688SAdrian Chadd 			 * frame was queued.  Just discard the frame; the
99181a82688SAdrian Chadd 			 * 802.11 layer counts failures and provides
99281a82688SAdrian Chadd 			 * debugging/diagnostics.
99381a82688SAdrian Chadd 			 */
994d4365d16SAdrian Chadd 			return (0);
99581a82688SAdrian Chadd 		}
99681a82688SAdrian Chadd 		/*
99781a82688SAdrian Chadd 		 * Adjust the packet + header lengths for the crypto
99881a82688SAdrian Chadd 		 * additions and calculate the h/w key index.  When
99981a82688SAdrian Chadd 		 * a s/w mic is done the frame will have had any mic
100081a82688SAdrian Chadd 		 * added to it prior to entry so m0->m_pkthdr.len will
100181a82688SAdrian Chadd 		 * account for it. Otherwise we need to add it to the
100281a82688SAdrian Chadd 		 * packet length.
100381a82688SAdrian Chadd 		 */
100481a82688SAdrian Chadd 		cip = k->wk_cipher;
100581a82688SAdrian Chadd 		(*hdrlen) += cip->ic_header;
100681a82688SAdrian Chadd 		(*pktlen) += cip->ic_header + cip->ic_trailer;
100781a82688SAdrian Chadd 		/* NB: frags always have any TKIP MIC done in s/w */
100881a82688SAdrian Chadd 		if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag)
100981a82688SAdrian Chadd 			(*pktlen) += cip->ic_miclen;
101081a82688SAdrian Chadd 		(*keyix) = k->wk_keyix;
101181a82688SAdrian Chadd 	} else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
101281a82688SAdrian Chadd 		/*
101381a82688SAdrian Chadd 		 * Use station key cache slot, if assigned.
101481a82688SAdrian Chadd 		 */
101581a82688SAdrian Chadd 		(*keyix) = ni->ni_ucastkey.wk_keyix;
101681a82688SAdrian Chadd 		if ((*keyix) == IEEE80211_KEYIX_NONE)
101781a82688SAdrian Chadd 			(*keyix) = HAL_TXKEYIX_INVALID;
101881a82688SAdrian Chadd 	} else
101981a82688SAdrian Chadd 		(*keyix) = HAL_TXKEYIX_INVALID;
102081a82688SAdrian Chadd 
1021d4365d16SAdrian Chadd 	return (1);
102281a82688SAdrian Chadd }
102381a82688SAdrian Chadd 
1024e2e4a2c2SAdrian Chadd /*
1025e2e4a2c2SAdrian Chadd  * Calculate whether interoperability protection is required for
1026e2e4a2c2SAdrian Chadd  * this frame.
1027e2e4a2c2SAdrian Chadd  *
1028e2e4a2c2SAdrian Chadd  * This requires the rate control information be filled in,
1029e2e4a2c2SAdrian Chadd  * as the protection requirement depends upon the current
1030e2e4a2c2SAdrian Chadd  * operating mode / PHY.
1031e2e4a2c2SAdrian Chadd  */
1032e2e4a2c2SAdrian Chadd static void
1033e2e4a2c2SAdrian Chadd ath_tx_calc_protection(struct ath_softc *sc, struct ath_buf *bf)
1034e2e4a2c2SAdrian Chadd {
1035e2e4a2c2SAdrian Chadd 	struct ieee80211_frame *wh;
1036e2e4a2c2SAdrian Chadd 	uint8_t rix;
1037e2e4a2c2SAdrian Chadd 	uint16_t flags;
1038e2e4a2c2SAdrian Chadd 	int shortPreamble;
1039e2e4a2c2SAdrian Chadd 	const HAL_RATE_TABLE *rt = sc->sc_currates;
1040e2e4a2c2SAdrian Chadd 	struct ifnet *ifp = sc->sc_ifp;
1041e2e4a2c2SAdrian Chadd 	struct ieee80211com *ic = ifp->if_l2com;
1042e2e4a2c2SAdrian Chadd 
1043e2e4a2c2SAdrian Chadd 	flags = bf->bf_state.bfs_txflags;
1044e2e4a2c2SAdrian Chadd 	rix = bf->bf_state.bfs_rc[0].rix;
1045e2e4a2c2SAdrian Chadd 	shortPreamble = bf->bf_state.bfs_shpream;
1046e2e4a2c2SAdrian Chadd 	wh = mtod(bf->bf_m, struct ieee80211_frame *);
1047e2e4a2c2SAdrian Chadd 
1048e2e4a2c2SAdrian Chadd 	/*
1049e2e4a2c2SAdrian Chadd 	 * If 802.11g protection is enabled, determine whether
1050e2e4a2c2SAdrian Chadd 	 * to use RTS/CTS or just CTS.  Note that this is only
1051e2e4a2c2SAdrian Chadd 	 * done for OFDM unicast frames.
1052e2e4a2c2SAdrian Chadd 	 */
1053e2e4a2c2SAdrian Chadd 	if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1054e2e4a2c2SAdrian Chadd 	    rt->info[rix].phy == IEEE80211_T_OFDM &&
1055e2e4a2c2SAdrian Chadd 	    (flags & HAL_TXDESC_NOACK) == 0) {
1056e2e4a2c2SAdrian Chadd 		bf->bf_state.bfs_doprot = 1;
1057e2e4a2c2SAdrian Chadd 		/* XXX fragments must use CCK rates w/ protection */
1058e2e4a2c2SAdrian Chadd 		if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1059e2e4a2c2SAdrian Chadd 			flags |= HAL_TXDESC_RTSENA;
1060e2e4a2c2SAdrian Chadd 		} else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1061e2e4a2c2SAdrian Chadd 			flags |= HAL_TXDESC_CTSENA;
1062e2e4a2c2SAdrian Chadd 		}
1063e2e4a2c2SAdrian Chadd 		/*
1064e2e4a2c2SAdrian Chadd 		 * For frags it would be desirable to use the
1065e2e4a2c2SAdrian Chadd 		 * highest CCK rate for RTS/CTS.  But stations
1066e2e4a2c2SAdrian Chadd 		 * farther away may detect it at a lower CCK rate
1067e2e4a2c2SAdrian Chadd 		 * so use the configured protection rate instead
1068e2e4a2c2SAdrian Chadd 		 * (for now).
1069e2e4a2c2SAdrian Chadd 		 */
1070e2e4a2c2SAdrian Chadd 		sc->sc_stats.ast_tx_protect++;
1071e2e4a2c2SAdrian Chadd 	}
1072e2e4a2c2SAdrian Chadd 
1073e2e4a2c2SAdrian Chadd 	/*
1074e2e4a2c2SAdrian Chadd 	 * If 11n protection is enabled and it's a HT frame,
1075e2e4a2c2SAdrian Chadd 	 * enable RTS.
1076e2e4a2c2SAdrian Chadd 	 *
1077e2e4a2c2SAdrian Chadd 	 * XXX ic_htprotmode or ic_curhtprotmode?
1078e2e4a2c2SAdrian Chadd 	 * XXX should it_htprotmode only matter if ic_curhtprotmode
1079e2e4a2c2SAdrian Chadd 	 * XXX indicates it's not a HT pure environment?
1080e2e4a2c2SAdrian Chadd 	 */
1081e2e4a2c2SAdrian Chadd 	if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) &&
1082e2e4a2c2SAdrian Chadd 	    rt->info[rix].phy == IEEE80211_T_HT &&
1083e2e4a2c2SAdrian Chadd 	    (flags & HAL_TXDESC_NOACK) == 0) {
1084e2e4a2c2SAdrian Chadd 		flags |= HAL_TXDESC_RTSENA;
1085e2e4a2c2SAdrian Chadd 		sc->sc_stats.ast_tx_htprotect++;
1086e2e4a2c2SAdrian Chadd 	}
1087e2e4a2c2SAdrian Chadd 	bf->bf_state.bfs_txflags = flags;
1088e2e4a2c2SAdrian Chadd }
1089e2e4a2c2SAdrian Chadd 
1090e2e4a2c2SAdrian Chadd /*
1091e2e4a2c2SAdrian Chadd  * Update the frame duration given the currently selected rate.
1092e2e4a2c2SAdrian Chadd  *
1093e2e4a2c2SAdrian Chadd  * This also updates the frame duration value, so it will require
1094e2e4a2c2SAdrian Chadd  * a DMA flush.
1095e2e4a2c2SAdrian Chadd  */
1096e2e4a2c2SAdrian Chadd static void
1097e2e4a2c2SAdrian Chadd ath_tx_calc_duration(struct ath_softc *sc, struct ath_buf *bf)
1098e2e4a2c2SAdrian Chadd {
1099e2e4a2c2SAdrian Chadd 	struct ieee80211_frame *wh;
1100e2e4a2c2SAdrian Chadd 	uint8_t rix;
1101e2e4a2c2SAdrian Chadd 	uint16_t flags;
1102e2e4a2c2SAdrian Chadd 	int shortPreamble;
1103e2e4a2c2SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
1104e2e4a2c2SAdrian Chadd 	const HAL_RATE_TABLE *rt = sc->sc_currates;
1105e2e4a2c2SAdrian Chadd 	int isfrag = bf->bf_m->m_flags & M_FRAG;
1106e2e4a2c2SAdrian Chadd 
1107e2e4a2c2SAdrian Chadd 	flags = bf->bf_state.bfs_txflags;
1108e2e4a2c2SAdrian Chadd 	rix = bf->bf_state.bfs_rc[0].rix;
1109e2e4a2c2SAdrian Chadd 	shortPreamble = bf->bf_state.bfs_shpream;
1110e2e4a2c2SAdrian Chadd 	wh = mtod(bf->bf_m, struct ieee80211_frame *);
1111e2e4a2c2SAdrian Chadd 
1112e2e4a2c2SAdrian Chadd 	/*
1113e2e4a2c2SAdrian Chadd 	 * Calculate duration.  This logically belongs in the 802.11
1114e2e4a2c2SAdrian Chadd 	 * layer but it lacks sufficient information to calculate it.
1115e2e4a2c2SAdrian Chadd 	 */
1116e2e4a2c2SAdrian Chadd 	if ((flags & HAL_TXDESC_NOACK) == 0 &&
1117e2e4a2c2SAdrian Chadd 	    (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
1118e2e4a2c2SAdrian Chadd 		u_int16_t dur;
1119e2e4a2c2SAdrian Chadd 		if (shortPreamble)
1120e2e4a2c2SAdrian Chadd 			dur = rt->info[rix].spAckDuration;
1121e2e4a2c2SAdrian Chadd 		else
1122e2e4a2c2SAdrian Chadd 			dur = rt->info[rix].lpAckDuration;
1123e2e4a2c2SAdrian Chadd 		if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) {
1124e2e4a2c2SAdrian Chadd 			dur += dur;		/* additional SIFS+ACK */
11251a85141aSAdrian Chadd 			KASSERT(bf->bf_m->m_nextpkt != NULL, ("no fragment"));
1126e2e4a2c2SAdrian Chadd 			/*
1127e2e4a2c2SAdrian Chadd 			 * Include the size of next fragment so NAV is
1128e2e4a2c2SAdrian Chadd 			 * updated properly.  The last fragment uses only
1129e2e4a2c2SAdrian Chadd 			 * the ACK duration
11309572684aSAdrian Chadd 			 *
11319572684aSAdrian Chadd 			 * XXX TODO: ensure that the rate lookup for each
11329572684aSAdrian Chadd 			 * fragment is the same as the rate used by the
11339572684aSAdrian Chadd 			 * first fragment!
1134e2e4a2c2SAdrian Chadd 			 */
1135e2e4a2c2SAdrian Chadd 			dur += ath_hal_computetxtime(ah, rt,
11361a85141aSAdrian Chadd 					bf->bf_m->m_nextpkt->m_pkthdr.len,
1137e2e4a2c2SAdrian Chadd 					rix, shortPreamble);
1138e2e4a2c2SAdrian Chadd 		}
1139e2e4a2c2SAdrian Chadd 		if (isfrag) {
1140e2e4a2c2SAdrian Chadd 			/*
1141e2e4a2c2SAdrian Chadd 			 * Force hardware to use computed duration for next
1142e2e4a2c2SAdrian Chadd 			 * fragment by disabling multi-rate retry which updates
1143e2e4a2c2SAdrian Chadd 			 * duration based on the multi-rate duration table.
1144e2e4a2c2SAdrian Chadd 			 */
1145e2e4a2c2SAdrian Chadd 			bf->bf_state.bfs_ismrr = 0;
1146e2e4a2c2SAdrian Chadd 			bf->bf_state.bfs_try0 = ATH_TXMGTTRY;
1147e2e4a2c2SAdrian Chadd 			/* XXX update bfs_rc[0].try? */
1148e2e4a2c2SAdrian Chadd 		}
1149e2e4a2c2SAdrian Chadd 
1150e2e4a2c2SAdrian Chadd 		/* Update the duration field itself */
1151e2e4a2c2SAdrian Chadd 		*(u_int16_t *)wh->i_dur = htole16(dur);
1152e2e4a2c2SAdrian Chadd 	}
1153e2e4a2c2SAdrian Chadd }
1154e2e4a2c2SAdrian Chadd 
1155e42b5dbaSAdrian Chadd static uint8_t
1156e42b5dbaSAdrian Chadd ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt,
1157eb6f0de0SAdrian Chadd     int cix, int shortPreamble)
115879f02dbfSAdrian Chadd {
1159e42b5dbaSAdrian Chadd 	uint8_t ctsrate;
1160e42b5dbaSAdrian Chadd 
116179f02dbfSAdrian Chadd 	/*
116279f02dbfSAdrian Chadd 	 * CTS transmit rate is derived from the transmit rate
116379f02dbfSAdrian Chadd 	 * by looking in the h/w rate table.  We must also factor
116479f02dbfSAdrian Chadd 	 * in whether or not a short preamble is to be used.
116579f02dbfSAdrian Chadd 	 */
116679f02dbfSAdrian Chadd 	/* NB: cix is set above where RTS/CTS is enabled */
116779f02dbfSAdrian Chadd 	KASSERT(cix != 0xff, ("cix not setup"));
1168e42b5dbaSAdrian Chadd 	ctsrate = rt->info[cix].rateCode;
1169e42b5dbaSAdrian Chadd 
1170e42b5dbaSAdrian Chadd 	/* XXX this should only matter for legacy rates */
1171e42b5dbaSAdrian Chadd 	if (shortPreamble)
1172e42b5dbaSAdrian Chadd 		ctsrate |= rt->info[cix].shortPreamble;
1173e42b5dbaSAdrian Chadd 
1174d4365d16SAdrian Chadd 	return (ctsrate);
1175e42b5dbaSAdrian Chadd }
1176e42b5dbaSAdrian Chadd 
1177e42b5dbaSAdrian Chadd /*
1178e42b5dbaSAdrian Chadd  * Calculate the RTS/CTS duration for legacy frames.
1179e42b5dbaSAdrian Chadd  */
1180e42b5dbaSAdrian Chadd static int
1181e42b5dbaSAdrian Chadd ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix,
1182e42b5dbaSAdrian Chadd     int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt,
1183e42b5dbaSAdrian Chadd     int flags)
1184e42b5dbaSAdrian Chadd {
1185e42b5dbaSAdrian Chadd 	int ctsduration = 0;
1186e42b5dbaSAdrian Chadd 
1187e42b5dbaSAdrian Chadd 	/* This mustn't be called for HT modes */
1188e42b5dbaSAdrian Chadd 	if (rt->info[cix].phy == IEEE80211_T_HT) {
1189e42b5dbaSAdrian Chadd 		printf("%s: HT rate where it shouldn't be (0x%x)\n",
1190e42b5dbaSAdrian Chadd 		    __func__, rt->info[cix].rateCode);
1191d4365d16SAdrian Chadd 		return (-1);
1192e42b5dbaSAdrian Chadd 	}
1193e42b5dbaSAdrian Chadd 
119479f02dbfSAdrian Chadd 	/*
119579f02dbfSAdrian Chadd 	 * Compute the transmit duration based on the frame
119679f02dbfSAdrian Chadd 	 * size and the size of an ACK frame.  We call into the
119779f02dbfSAdrian Chadd 	 * HAL to do the computation since it depends on the
119879f02dbfSAdrian Chadd 	 * characteristics of the actual PHY being used.
119979f02dbfSAdrian Chadd 	 *
120079f02dbfSAdrian Chadd 	 * NB: CTS is assumed the same size as an ACK so we can
120179f02dbfSAdrian Chadd 	 *     use the precalculated ACK durations.
120279f02dbfSAdrian Chadd 	 */
120379f02dbfSAdrian Chadd 	if (shortPreamble) {
120479f02dbfSAdrian Chadd 		if (flags & HAL_TXDESC_RTSENA)		/* SIFS + CTS */
1205e42b5dbaSAdrian Chadd 			ctsduration += rt->info[cix].spAckDuration;
1206e42b5dbaSAdrian Chadd 		ctsduration += ath_hal_computetxtime(ah,
120779f02dbfSAdrian Chadd 			rt, pktlen, rix, AH_TRUE);
120879f02dbfSAdrian Chadd 		if ((flags & HAL_TXDESC_NOACK) == 0)	/* SIFS + ACK */
1209e42b5dbaSAdrian Chadd 			ctsduration += rt->info[rix].spAckDuration;
121079f02dbfSAdrian Chadd 	} else {
121179f02dbfSAdrian Chadd 		if (flags & HAL_TXDESC_RTSENA)		/* SIFS + CTS */
1212e42b5dbaSAdrian Chadd 			ctsduration += rt->info[cix].lpAckDuration;
1213e42b5dbaSAdrian Chadd 		ctsduration += ath_hal_computetxtime(ah,
121479f02dbfSAdrian Chadd 			rt, pktlen, rix, AH_FALSE);
121579f02dbfSAdrian Chadd 		if ((flags & HAL_TXDESC_NOACK) == 0)	/* SIFS + ACK */
1216e42b5dbaSAdrian Chadd 			ctsduration += rt->info[rix].lpAckDuration;
121779f02dbfSAdrian Chadd 	}
1218e42b5dbaSAdrian Chadd 
1219d4365d16SAdrian Chadd 	return (ctsduration);
122079f02dbfSAdrian Chadd }
122179f02dbfSAdrian Chadd 
1222eb6f0de0SAdrian Chadd /*
1223eb6f0de0SAdrian Chadd  * Update the given ath_buf with updated rts/cts setup and duration
1224eb6f0de0SAdrian Chadd  * values.
1225eb6f0de0SAdrian Chadd  *
1226eb6f0de0SAdrian Chadd  * To support rate lookups for each software retry, the rts/cts rate
1227eb6f0de0SAdrian Chadd  * and cts duration must be re-calculated.
1228eb6f0de0SAdrian Chadd  *
1229eb6f0de0SAdrian Chadd  * This function assumes the RTS/CTS flags have been set as needed;
1230eb6f0de0SAdrian Chadd  * mrr has been disabled; and the rate control lookup has been done.
1231eb6f0de0SAdrian Chadd  *
1232eb6f0de0SAdrian Chadd  * XXX TODO: MRR need only be disabled for the pre-11n NICs.
1233eb6f0de0SAdrian Chadd  * XXX The 11n NICs support per-rate RTS/CTS configuration.
1234eb6f0de0SAdrian Chadd  */
1235eb6f0de0SAdrian Chadd static void
1236eb6f0de0SAdrian Chadd ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf)
1237eb6f0de0SAdrian Chadd {
1238eb6f0de0SAdrian Chadd 	uint16_t ctsduration = 0;
1239eb6f0de0SAdrian Chadd 	uint8_t ctsrate = 0;
1240eb6f0de0SAdrian Chadd 	uint8_t rix = bf->bf_state.bfs_rc[0].rix;
1241eb6f0de0SAdrian Chadd 	uint8_t cix = 0;
1242eb6f0de0SAdrian Chadd 	const HAL_RATE_TABLE *rt = sc->sc_currates;
1243eb6f0de0SAdrian Chadd 
1244eb6f0de0SAdrian Chadd 	/*
1245eb6f0de0SAdrian Chadd 	 * No RTS/CTS enabled? Don't bother.
1246eb6f0de0SAdrian Chadd 	 */
1247875a9451SAdrian Chadd 	if ((bf->bf_state.bfs_txflags &
1248eb6f0de0SAdrian Chadd 	    (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) {
1249eb6f0de0SAdrian Chadd 		/* XXX is this really needed? */
1250eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_ctsrate = 0;
1251eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_ctsduration = 0;
1252eb6f0de0SAdrian Chadd 		return;
1253eb6f0de0SAdrian Chadd 	}
1254eb6f0de0SAdrian Chadd 
1255eb6f0de0SAdrian Chadd 	/*
1256eb6f0de0SAdrian Chadd 	 * If protection is enabled, use the protection rix control
1257eb6f0de0SAdrian Chadd 	 * rate. Otherwise use the rate0 control rate.
1258eb6f0de0SAdrian Chadd 	 */
1259eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_doprot)
1260eb6f0de0SAdrian Chadd 		rix = sc->sc_protrix;
1261eb6f0de0SAdrian Chadd 	else
1262eb6f0de0SAdrian Chadd 		rix = bf->bf_state.bfs_rc[0].rix;
1263eb6f0de0SAdrian Chadd 
1264eb6f0de0SAdrian Chadd 	/*
1265eb6f0de0SAdrian Chadd 	 * If the raw path has hard-coded ctsrate0 to something,
1266eb6f0de0SAdrian Chadd 	 * use it.
1267eb6f0de0SAdrian Chadd 	 */
1268eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_ctsrate0 != 0)
1269eb6f0de0SAdrian Chadd 		cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0);
1270eb6f0de0SAdrian Chadd 	else
1271eb6f0de0SAdrian Chadd 		/* Control rate from above */
1272eb6f0de0SAdrian Chadd 		cix = rt->info[rix].controlRate;
1273eb6f0de0SAdrian Chadd 
1274eb6f0de0SAdrian Chadd 	/* Calculate the rtscts rate for the given cix */
1275eb6f0de0SAdrian Chadd 	ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix,
1276eb6f0de0SAdrian Chadd 	    bf->bf_state.bfs_shpream);
1277eb6f0de0SAdrian Chadd 
1278eb6f0de0SAdrian Chadd 	/* The 11n chipsets do ctsduration calculations for you */
1279eb6f0de0SAdrian Chadd 	if (! ath_tx_is_11n(sc))
1280eb6f0de0SAdrian Chadd 		ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix,
1281eb6f0de0SAdrian Chadd 		    bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen,
1282875a9451SAdrian Chadd 		    rt, bf->bf_state.bfs_txflags);
1283eb6f0de0SAdrian Chadd 
1284eb6f0de0SAdrian Chadd 	/* Squirrel away in ath_buf */
1285eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_ctsrate = ctsrate;
1286eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_ctsduration = ctsduration;
1287eb6f0de0SAdrian Chadd 
1288eb6f0de0SAdrian Chadd 	/*
1289eb6f0de0SAdrian Chadd 	 * Must disable multi-rate retry when using RTS/CTS.
1290eb6f0de0SAdrian Chadd 	 */
1291af017101SAdrian Chadd 	if (!sc->sc_mrrprot) {
1292eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_ismrr = 0;
1293eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_try0 =
1294eb6f0de0SAdrian Chadd 		    bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */
1295eb6f0de0SAdrian Chadd 	}
1296af017101SAdrian Chadd }
1297eb6f0de0SAdrian Chadd 
1298eb6f0de0SAdrian Chadd /*
1299eb6f0de0SAdrian Chadd  * Setup the descriptor chain for a normal or fast-frame
1300eb6f0de0SAdrian Chadd  * frame.
130146634305SAdrian Chadd  *
130246634305SAdrian Chadd  * XXX TODO: extend to include the destination hardware QCU ID.
130346634305SAdrian Chadd  * Make sure that is correct.  Make sure that when being added
130446634305SAdrian Chadd  * to the mcastq, the CABQ QCUID is set or things will get a bit
130546634305SAdrian Chadd  * odd.
1306eb6f0de0SAdrian Chadd  */
1307eb6f0de0SAdrian Chadd static void
1308eb6f0de0SAdrian Chadd ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf)
1309eb6f0de0SAdrian Chadd {
1310eb6f0de0SAdrian Chadd 	struct ath_desc *ds = bf->bf_desc;
1311eb6f0de0SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
1312eb6f0de0SAdrian Chadd 
13137d9dd2acSAdrian Chadd 	if (bf->bf_state.bfs_txrate0 == 0)
13147d9dd2acSAdrian Chadd 		device_printf(sc->sc_dev, "%s: bf=%p, txrate0=%d\n",
13157d9dd2acSAdrian Chadd 		    __func__, bf, 0);
13167d9dd2acSAdrian Chadd 
1317eb6f0de0SAdrian Chadd 	ath_hal_setuptxdesc(ah, ds
1318eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_pktlen	/* packet length */
1319eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_hdrlen	/* header length */
1320eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_atype	/* Atheros packet type */
1321eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_txpower	/* txpower */
1322eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_txrate0
1323eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_try0		/* series 0 rate/tries */
1324eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_keyix	/* key cache index */
1325eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_txantenna	/* antenna mode */
1326875a9451SAdrian Chadd 		, bf->bf_state.bfs_txflags	/* flags */
1327eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_ctsrate	/* rts/cts rate */
1328eb6f0de0SAdrian Chadd 		, bf->bf_state.bfs_ctsduration	/* rts/cts duration */
1329eb6f0de0SAdrian Chadd 	);
1330eb6f0de0SAdrian Chadd 
1331eb6f0de0SAdrian Chadd 	/*
1332eb6f0de0SAdrian Chadd 	 * This will be overriden when the descriptor chain is written.
1333eb6f0de0SAdrian Chadd 	 */
1334eb6f0de0SAdrian Chadd 	bf->bf_lastds = ds;
1335eb6f0de0SAdrian Chadd 	bf->bf_last = bf;
1336eb6f0de0SAdrian Chadd 
1337d34a7347SAdrian Chadd 	/* Set rate control and descriptor chain for this frame */
1338d34a7347SAdrian Chadd 	ath_tx_set_ratectrl(sc, bf->bf_node, bf);
13396e84772fSAdrian Chadd 	ath_tx_chaindesclist(sc, ds, bf, 0, 0, 0);
1340eb6f0de0SAdrian Chadd }
1341eb6f0de0SAdrian Chadd 
1342eb6f0de0SAdrian Chadd /*
1343eb6f0de0SAdrian Chadd  * Do a rate lookup.
1344eb6f0de0SAdrian Chadd  *
1345eb6f0de0SAdrian Chadd  * This performs a rate lookup for the given ath_buf only if it's required.
1346eb6f0de0SAdrian Chadd  * Non-data frames and raw frames don't require it.
1347eb6f0de0SAdrian Chadd  *
1348eb6f0de0SAdrian Chadd  * This populates the primary and MRR entries; MRR values are
1349eb6f0de0SAdrian Chadd  * then disabled later on if something requires it (eg RTS/CTS on
1350eb6f0de0SAdrian Chadd  * pre-11n chipsets.
1351eb6f0de0SAdrian Chadd  *
1352eb6f0de0SAdrian Chadd  * This needs to be done before the RTS/CTS fields are calculated
1353eb6f0de0SAdrian Chadd  * as they may depend upon the rate chosen.
1354eb6f0de0SAdrian Chadd  */
1355eb6f0de0SAdrian Chadd static void
1356eb6f0de0SAdrian Chadd ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf)
1357eb6f0de0SAdrian Chadd {
1358eb6f0de0SAdrian Chadd 	uint8_t rate, rix;
1359eb6f0de0SAdrian Chadd 	int try0;
1360eb6f0de0SAdrian Chadd 
1361eb6f0de0SAdrian Chadd 	if (! bf->bf_state.bfs_doratelookup)
1362eb6f0de0SAdrian Chadd 		return;
1363eb6f0de0SAdrian Chadd 
1364eb6f0de0SAdrian Chadd 	/* Get rid of any previous state */
1365eb6f0de0SAdrian Chadd 	bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1366eb6f0de0SAdrian Chadd 
1367eb6f0de0SAdrian Chadd 	ATH_NODE_LOCK(ATH_NODE(bf->bf_node));
1368eb6f0de0SAdrian Chadd 	ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream,
1369eb6f0de0SAdrian Chadd 	    bf->bf_state.bfs_pktlen, &rix, &try0, &rate);
1370eb6f0de0SAdrian Chadd 
1371eb6f0de0SAdrian Chadd 	/* In case MRR is disabled, make sure rc[0] is setup correctly */
1372eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_rc[0].rix = rix;
1373eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_rc[0].ratecode = rate;
1374eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_rc[0].tries = try0;
1375eb6f0de0SAdrian Chadd 
1376eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY)
1377eb6f0de0SAdrian Chadd 		ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix,
1378eb6f0de0SAdrian Chadd 		    bf->bf_state.bfs_rc);
1379eb6f0de0SAdrian Chadd 	ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node));
1380eb6f0de0SAdrian Chadd 
1381eb6f0de0SAdrian Chadd 	sc->sc_txrix = rix;	/* for LED blinking */
1382eb6f0de0SAdrian Chadd 	sc->sc_lastdatarix = rix;	/* for fast frames */
1383eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_try0 = try0;
1384eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_txrate0 = rate;
1385eb6f0de0SAdrian Chadd }
1386eb6f0de0SAdrian Chadd 
1387eb6f0de0SAdrian Chadd /*
13880c54de88SAdrian Chadd  * Update the CLRDMASK bit in the ath_buf if it needs to be set.
13890c54de88SAdrian Chadd  */
13900c54de88SAdrian Chadd static void
13910c54de88SAdrian Chadd ath_tx_update_clrdmask(struct ath_softc *sc, struct ath_tid *tid,
13920c54de88SAdrian Chadd     struct ath_buf *bf)
13930c54de88SAdrian Chadd {
13944f25ddbbSAdrian Chadd 	struct ath_node *an = ATH_NODE(bf->bf_node);
13950c54de88SAdrian Chadd 
1396375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
13970c54de88SAdrian Chadd 
13984f25ddbbSAdrian Chadd 	if (an->clrdmask == 1) {
13990c54de88SAdrian Chadd 		bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
14004f25ddbbSAdrian Chadd 		an->clrdmask = 0;
14010c54de88SAdrian Chadd 	}
14020c54de88SAdrian Chadd }
14030c54de88SAdrian Chadd 
14040c54de88SAdrian Chadd /*
1405eb6f0de0SAdrian Chadd  * Transmit the given frame to the hardware.
1406eb6f0de0SAdrian Chadd  *
1407eb6f0de0SAdrian Chadd  * The frame must already be setup; rate control must already have
1408eb6f0de0SAdrian Chadd  * been done.
1409eb6f0de0SAdrian Chadd  *
1410eb6f0de0SAdrian Chadd  * XXX since the TXQ lock is being held here (and I dislike holding
1411eb6f0de0SAdrian Chadd  * it for this long when not doing software aggregation), later on
1412eb6f0de0SAdrian Chadd  * break this function into "setup_normal" and "xmit_normal". The
1413eb6f0de0SAdrian Chadd  * lock only needs to be held for the ath_tx_handoff call.
1414eb6f0de0SAdrian Chadd  */
1415eb6f0de0SAdrian Chadd static void
1416eb6f0de0SAdrian Chadd ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq,
1417eb6f0de0SAdrian Chadd     struct ath_buf *bf)
1418eb6f0de0SAdrian Chadd {
14190c54de88SAdrian Chadd 	struct ath_node *an = ATH_NODE(bf->bf_node);
14200c54de88SAdrian Chadd 	struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid];
1421eb6f0de0SAdrian Chadd 
1422375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
1423eb6f0de0SAdrian Chadd 
14240c54de88SAdrian Chadd 	/*
14250c54de88SAdrian Chadd 	 * For now, just enable CLRDMASK. ath_tx_xmit_normal() does
14260c54de88SAdrian Chadd 	 * set a completion handler however it doesn't (yet) properly
14270c54de88SAdrian Chadd 	 * handle the strict ordering requirements needed for normal,
14280c54de88SAdrian Chadd 	 * non-aggregate session frames.
14290c54de88SAdrian Chadd 	 *
14300c54de88SAdrian Chadd 	 * Once this is implemented, only set CLRDMASK like this for
14310c54de88SAdrian Chadd 	 * frames that must go out - eg management/raw frames.
14320c54de88SAdrian Chadd 	 */
14330c54de88SAdrian Chadd 	bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
14340c54de88SAdrian Chadd 
1435eb6f0de0SAdrian Chadd 	/* Setup the descriptor before handoff */
1436eb6f0de0SAdrian Chadd 	ath_tx_do_ratelookup(sc, bf);
1437e2e4a2c2SAdrian Chadd 	ath_tx_calc_duration(sc, bf);
1438e2e4a2c2SAdrian Chadd 	ath_tx_calc_protection(sc, bf);
1439eb6f0de0SAdrian Chadd 	ath_tx_set_rtscts(sc, bf);
1440e2e4a2c2SAdrian Chadd 	ath_tx_rate_fill_rcflags(sc, bf);
1441eb6f0de0SAdrian Chadd 	ath_tx_setds(sc, bf);
1442eb6f0de0SAdrian Chadd 
14430c54de88SAdrian Chadd 	/* Track per-TID hardware queue depth correctly */
14440c54de88SAdrian Chadd 	tid->hwq_depth++;
14450c54de88SAdrian Chadd 
14460c54de88SAdrian Chadd 	/* Assign the completion handler */
14470c54de88SAdrian Chadd 	bf->bf_comp = ath_tx_normal_comp;
14484e81f27cSAdrian Chadd 
1449eb6f0de0SAdrian Chadd 	/* Hand off to hardware */
1450eb6f0de0SAdrian Chadd 	ath_tx_handoff(sc, txq, bf);
1451eb6f0de0SAdrian Chadd }
1452eb6f0de0SAdrian Chadd 
1453d05b576dSAdrian Chadd /*
1454d05b576dSAdrian Chadd  * Do the basic frame setup stuff that's required before the frame
1455d05b576dSAdrian Chadd  * is added to a software queue.
1456d05b576dSAdrian Chadd  *
1457d05b576dSAdrian Chadd  * All frames get mostly the same treatment and it's done once.
1458d05b576dSAdrian Chadd  * Retransmits fiddle with things like the rate control setup,
1459d05b576dSAdrian Chadd  * setting the retransmit bit in the packet; doing relevant DMA/bus
1460d05b576dSAdrian Chadd  * syncing and relinking it (back) into the hardware TX queue.
1461d05b576dSAdrian Chadd  *
1462d05b576dSAdrian Chadd  * Note that this may cause the mbuf to be reallocated, so
1463d05b576dSAdrian Chadd  * m0 may not be valid.
1464d05b576dSAdrian Chadd  */
1465eb6f0de0SAdrian Chadd static int
1466eb6f0de0SAdrian Chadd ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni,
1467b43facbfSAdrian Chadd     struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq)
1468b8e788a5SAdrian Chadd {
1469b8e788a5SAdrian Chadd 	struct ieee80211vap *vap = ni->ni_vap;
1470b8e788a5SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
1471b8e788a5SAdrian Chadd 	struct ifnet *ifp = sc->sc_ifp;
1472b8e788a5SAdrian Chadd 	struct ieee80211com *ic = ifp->if_l2com;
1473b8e788a5SAdrian Chadd 	const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
1474b8e788a5SAdrian Chadd 	int error, iswep, ismcast, isfrag, ismrr;
1475eb6f0de0SAdrian Chadd 	int keyix, hdrlen, pktlen, try0 = 0;
1476eb6f0de0SAdrian Chadd 	u_int8_t rix = 0, txrate = 0;
1477b8e788a5SAdrian Chadd 	struct ath_desc *ds;
1478b8e788a5SAdrian Chadd 	struct ieee80211_frame *wh;
1479eb6f0de0SAdrian Chadd 	u_int subtype, flags;
1480b8e788a5SAdrian Chadd 	HAL_PKT_TYPE atype;
1481b8e788a5SAdrian Chadd 	const HAL_RATE_TABLE *rt;
1482b8e788a5SAdrian Chadd 	HAL_BOOL shortPreamble;
1483b8e788a5SAdrian Chadd 	struct ath_node *an;
1484b8e788a5SAdrian Chadd 	u_int pri;
1485b8e788a5SAdrian Chadd 
14867561cb5cSAdrian Chadd 	/*
14877561cb5cSAdrian Chadd 	 * To ensure that both sequence numbers and the CCMP PN handling
14887561cb5cSAdrian Chadd 	 * is "correct", make sure that the relevant TID queue is locked.
14897561cb5cSAdrian Chadd 	 * Otherwise the CCMP PN and seqno may appear out of order, causing
14907561cb5cSAdrian Chadd 	 * re-ordered frames to have out of order CCMP PN's, resulting
14917561cb5cSAdrian Chadd 	 * in many, many frame drops.
14927561cb5cSAdrian Chadd 	 */
1493375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
14947561cb5cSAdrian Chadd 
1495b8e788a5SAdrian Chadd 	wh = mtod(m0, struct ieee80211_frame *);
1496b8e788a5SAdrian Chadd 	iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1497b8e788a5SAdrian Chadd 	ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1498b8e788a5SAdrian Chadd 	isfrag = m0->m_flags & M_FRAG;
1499b8e788a5SAdrian Chadd 	hdrlen = ieee80211_anyhdrsize(wh);
1500b8e788a5SAdrian Chadd 	/*
1501b8e788a5SAdrian Chadd 	 * Packet length must not include any
1502b8e788a5SAdrian Chadd 	 * pad bytes; deduct them here.
1503b8e788a5SAdrian Chadd 	 */
1504b8e788a5SAdrian Chadd 	pktlen = m0->m_pkthdr.len - (hdrlen & 3);
1505b8e788a5SAdrian Chadd 
150681a82688SAdrian Chadd 	/* Handle encryption twiddling if needed */
1507eb6f0de0SAdrian Chadd 	if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen,
1508eb6f0de0SAdrian Chadd 	    &pktlen, &keyix)) {
1509b8e788a5SAdrian Chadd 		ath_freetx(m0);
1510b8e788a5SAdrian Chadd 		return EIO;
1511b8e788a5SAdrian Chadd 	}
1512b8e788a5SAdrian Chadd 
1513b8e788a5SAdrian Chadd 	/* packet header may have moved, reset our local pointer */
1514b8e788a5SAdrian Chadd 	wh = mtod(m0, struct ieee80211_frame *);
1515b8e788a5SAdrian Chadd 
1516b8e788a5SAdrian Chadd 	pktlen += IEEE80211_CRC_LEN;
1517b8e788a5SAdrian Chadd 
1518b8e788a5SAdrian Chadd 	/*
1519b8e788a5SAdrian Chadd 	 * Load the DMA map so any coalescing is done.  This
1520b8e788a5SAdrian Chadd 	 * also calculates the number of descriptors we need.
1521b8e788a5SAdrian Chadd 	 */
1522b8e788a5SAdrian Chadd 	error = ath_tx_dmasetup(sc, bf, m0);
1523b8e788a5SAdrian Chadd 	if (error != 0)
1524b8e788a5SAdrian Chadd 		return error;
1525b8e788a5SAdrian Chadd 	bf->bf_node = ni;			/* NB: held reference */
1526b8e788a5SAdrian Chadd 	m0 = bf->bf_m;				/* NB: may have changed */
1527b8e788a5SAdrian Chadd 	wh = mtod(m0, struct ieee80211_frame *);
1528b8e788a5SAdrian Chadd 
1529b8e788a5SAdrian Chadd 	/* setup descriptors */
1530b8e788a5SAdrian Chadd 	ds = bf->bf_desc;
1531b8e788a5SAdrian Chadd 	rt = sc->sc_currates;
1532b8e788a5SAdrian Chadd 	KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
1533b8e788a5SAdrian Chadd 
1534b8e788a5SAdrian Chadd 	/*
1535b8e788a5SAdrian Chadd 	 * NB: the 802.11 layer marks whether or not we should
1536b8e788a5SAdrian Chadd 	 * use short preamble based on the current mode and
1537b8e788a5SAdrian Chadd 	 * negotiated parameters.
1538b8e788a5SAdrian Chadd 	 */
1539b8e788a5SAdrian Chadd 	if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1540b8e788a5SAdrian Chadd 	    (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
1541b8e788a5SAdrian Chadd 		shortPreamble = AH_TRUE;
1542b8e788a5SAdrian Chadd 		sc->sc_stats.ast_tx_shortpre++;
1543b8e788a5SAdrian Chadd 	} else {
1544b8e788a5SAdrian Chadd 		shortPreamble = AH_FALSE;
1545b8e788a5SAdrian Chadd 	}
1546b8e788a5SAdrian Chadd 
1547b8e788a5SAdrian Chadd 	an = ATH_NODE(ni);
15484e81f27cSAdrian Chadd 	//flags = HAL_TXDESC_CLRDMASK;		/* XXX needed for crypto errs */
15494e81f27cSAdrian Chadd 	flags = 0;
1550b8e788a5SAdrian Chadd 	ismrr = 0;				/* default no multi-rate retry*/
1551b8e788a5SAdrian Chadd 	pri = M_WME_GETAC(m0);			/* honor classification */
1552b8e788a5SAdrian Chadd 	/* XXX use txparams instead of fixed values */
1553b8e788a5SAdrian Chadd 	/*
1554b8e788a5SAdrian Chadd 	 * Calculate Atheros packet type from IEEE80211 packet header,
1555b8e788a5SAdrian Chadd 	 * setup for rate calculations, and select h/w transmit queue.
1556b8e788a5SAdrian Chadd 	 */
1557b8e788a5SAdrian Chadd 	switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1558b8e788a5SAdrian Chadd 	case IEEE80211_FC0_TYPE_MGT:
1559b8e788a5SAdrian Chadd 		subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1560b8e788a5SAdrian Chadd 		if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
1561b8e788a5SAdrian Chadd 			atype = HAL_PKT_TYPE_BEACON;
1562b8e788a5SAdrian Chadd 		else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1563b8e788a5SAdrian Chadd 			atype = HAL_PKT_TYPE_PROBE_RESP;
1564b8e788a5SAdrian Chadd 		else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1565b8e788a5SAdrian Chadd 			atype = HAL_PKT_TYPE_ATIM;
1566b8e788a5SAdrian Chadd 		else
1567b8e788a5SAdrian Chadd 			atype = HAL_PKT_TYPE_NORMAL;	/* XXX */
1568b8e788a5SAdrian Chadd 		rix = an->an_mgmtrix;
1569b8e788a5SAdrian Chadd 		txrate = rt->info[rix].rateCode;
1570b8e788a5SAdrian Chadd 		if (shortPreamble)
1571b8e788a5SAdrian Chadd 			txrate |= rt->info[rix].shortPreamble;
1572b8e788a5SAdrian Chadd 		try0 = ATH_TXMGTTRY;
1573b8e788a5SAdrian Chadd 		flags |= HAL_TXDESC_INTREQ;	/* force interrupt */
1574b8e788a5SAdrian Chadd 		break;
1575b8e788a5SAdrian Chadd 	case IEEE80211_FC0_TYPE_CTL:
1576b8e788a5SAdrian Chadd 		atype = HAL_PKT_TYPE_PSPOLL;	/* stop setting of duration */
1577b8e788a5SAdrian Chadd 		rix = an->an_mgmtrix;
1578b8e788a5SAdrian Chadd 		txrate = rt->info[rix].rateCode;
1579b8e788a5SAdrian Chadd 		if (shortPreamble)
1580b8e788a5SAdrian Chadd 			txrate |= rt->info[rix].shortPreamble;
1581b8e788a5SAdrian Chadd 		try0 = ATH_TXMGTTRY;
1582b8e788a5SAdrian Chadd 		flags |= HAL_TXDESC_INTREQ;	/* force interrupt */
1583b8e788a5SAdrian Chadd 		break;
1584b8e788a5SAdrian Chadd 	case IEEE80211_FC0_TYPE_DATA:
1585b8e788a5SAdrian Chadd 		atype = HAL_PKT_TYPE_NORMAL;		/* default */
1586b8e788a5SAdrian Chadd 		/*
1587b8e788a5SAdrian Chadd 		 * Data frames: multicast frames go out at a fixed rate,
1588b8e788a5SAdrian Chadd 		 * EAPOL frames use the mgmt frame rate; otherwise consult
1589b8e788a5SAdrian Chadd 		 * the rate control module for the rate to use.
1590b8e788a5SAdrian Chadd 		 */
1591b8e788a5SAdrian Chadd 		if (ismcast) {
1592b8e788a5SAdrian Chadd 			rix = an->an_mcastrix;
1593b8e788a5SAdrian Chadd 			txrate = rt->info[rix].rateCode;
1594b8e788a5SAdrian Chadd 			if (shortPreamble)
1595b8e788a5SAdrian Chadd 				txrate |= rt->info[rix].shortPreamble;
1596b8e788a5SAdrian Chadd 			try0 = 1;
1597b8e788a5SAdrian Chadd 		} else if (m0->m_flags & M_EAPOL) {
1598b8e788a5SAdrian Chadd 			/* XXX? maybe always use long preamble? */
1599b8e788a5SAdrian Chadd 			rix = an->an_mgmtrix;
1600b8e788a5SAdrian Chadd 			txrate = rt->info[rix].rateCode;
1601b8e788a5SAdrian Chadd 			if (shortPreamble)
1602b8e788a5SAdrian Chadd 				txrate |= rt->info[rix].shortPreamble;
1603b8e788a5SAdrian Chadd 			try0 = ATH_TXMAXTRY;	/* XXX?too many? */
1604b8e788a5SAdrian Chadd 		} else {
1605eb6f0de0SAdrian Chadd 			/*
1606eb6f0de0SAdrian Chadd 			 * Do rate lookup on each TX, rather than using
1607eb6f0de0SAdrian Chadd 			 * the hard-coded TX information decided here.
1608eb6f0de0SAdrian Chadd 			 */
1609b8e788a5SAdrian Chadd 			ismrr = 1;
1610eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_doratelookup = 1;
1611b8e788a5SAdrian Chadd 		}
1612b8e788a5SAdrian Chadd 		if (cap->cap_wmeParams[pri].wmep_noackPolicy)
1613b8e788a5SAdrian Chadd 			flags |= HAL_TXDESC_NOACK;
1614b8e788a5SAdrian Chadd 		break;
1615b8e788a5SAdrian Chadd 	default:
1616b8e788a5SAdrian Chadd 		if_printf(ifp, "bogus frame type 0x%x (%s)\n",
1617b8e788a5SAdrian Chadd 			wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
1618b8e788a5SAdrian Chadd 		/* XXX statistic */
1619b8e788a5SAdrian Chadd 		ath_freetx(m0);
1620b8e788a5SAdrian Chadd 		return EIO;
1621b8e788a5SAdrian Chadd 	}
1622b8e788a5SAdrian Chadd 
1623447fd44aSAdrian Chadd 	/*
1624447fd44aSAdrian Chadd 	 * There are two known scenarios where the frame AC doesn't match
1625447fd44aSAdrian Chadd 	 * what the destination TXQ is.
1626447fd44aSAdrian Chadd 	 *
1627447fd44aSAdrian Chadd 	 * + non-QoS frames (eg management?) that the net80211 stack has
1628447fd44aSAdrian Chadd 	 *   assigned a higher AC to, but since it's a non-QoS TID, it's
1629447fd44aSAdrian Chadd 	 *   being thrown into TID 16.  TID 16 gets the AC_BE queue.
1630447fd44aSAdrian Chadd 	 *   It's quite possible that management frames should just be
1631447fd44aSAdrian Chadd 	 *   direct dispatched to hardware rather than go via the software
1632447fd44aSAdrian Chadd 	 *   queue; that should be investigated in the future.  There are
1633447fd44aSAdrian Chadd 	 *   some specific scenarios where this doesn't make sense, mostly
1634447fd44aSAdrian Chadd 	 *   surrounding ADDBA request/response - hence why that is special
1635447fd44aSAdrian Chadd 	 *   cased.
1636447fd44aSAdrian Chadd 	 *
1637447fd44aSAdrian Chadd 	 * + Multicast frames going into the VAP mcast queue.  That shows up
1638447fd44aSAdrian Chadd 	 *   as "TXQ 11".
1639447fd44aSAdrian Chadd 	 *
1640447fd44aSAdrian Chadd 	 * This driver should eventually support separate TID and TXQ locking,
1641447fd44aSAdrian Chadd 	 * allowing for arbitrary AC frames to appear on arbitrary software
1642447fd44aSAdrian Chadd 	 * queues, being queued to the "correct" hardware queue when needed.
1643447fd44aSAdrian Chadd 	 */
1644447fd44aSAdrian Chadd #if 0
16456deb7f32SAdrian Chadd 	if (txq != sc->sc_ac2q[pri]) {
16466deb7f32SAdrian Chadd 		device_printf(sc->sc_dev,
16476deb7f32SAdrian Chadd 		    "%s: txq=%p (%d), pri=%d, pri txq=%p (%d)\n",
16486deb7f32SAdrian Chadd 		    __func__,
16496deb7f32SAdrian Chadd 		    txq,
16506deb7f32SAdrian Chadd 		    txq->axq_qnum,
16516deb7f32SAdrian Chadd 		    pri,
16526deb7f32SAdrian Chadd 		    sc->sc_ac2q[pri],
16536deb7f32SAdrian Chadd 		    sc->sc_ac2q[pri]->axq_qnum);
16546deb7f32SAdrian Chadd 	}
1655447fd44aSAdrian Chadd #endif
16566deb7f32SAdrian Chadd 
1657b8e788a5SAdrian Chadd 	/*
1658b8e788a5SAdrian Chadd 	 * Calculate miscellaneous flags.
1659b8e788a5SAdrian Chadd 	 */
1660b8e788a5SAdrian Chadd 	if (ismcast) {
1661b8e788a5SAdrian Chadd 		flags |= HAL_TXDESC_NOACK;	/* no ack on broad/multicast */
1662b8e788a5SAdrian Chadd 	} else if (pktlen > vap->iv_rtsthreshold &&
1663b8e788a5SAdrian Chadd 	    (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) {
1664b8e788a5SAdrian Chadd 		flags |= HAL_TXDESC_RTSENA;	/* RTS based on frame length */
1665b8e788a5SAdrian Chadd 		sc->sc_stats.ast_tx_rts++;
1666b8e788a5SAdrian Chadd 	}
1667b8e788a5SAdrian Chadd 	if (flags & HAL_TXDESC_NOACK)		/* NB: avoid double counting */
1668b8e788a5SAdrian Chadd 		sc->sc_stats.ast_tx_noack++;
1669b8e788a5SAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
1670b8e788a5SAdrian Chadd 	if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) {
1671b8e788a5SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_TDMA,
1672b8e788a5SAdrian Chadd 		    "%s: discard frame, ACK required w/ TDMA\n", __func__);
1673b8e788a5SAdrian Chadd 		sc->sc_stats.ast_tdma_ack++;
1674b8e788a5SAdrian Chadd 		ath_freetx(m0);
1675b8e788a5SAdrian Chadd 		return EIO;
1676b8e788a5SAdrian Chadd 	}
1677b8e788a5SAdrian Chadd #endif
1678b8e788a5SAdrian Chadd 
1679b8e788a5SAdrian Chadd 	/*
1680eb6f0de0SAdrian Chadd 	 * Determine if a tx interrupt should be generated for
1681eb6f0de0SAdrian Chadd 	 * this descriptor.  We take a tx interrupt to reap
1682eb6f0de0SAdrian Chadd 	 * descriptors when the h/w hits an EOL condition or
1683eb6f0de0SAdrian Chadd 	 * when the descriptor is specifically marked to generate
1684eb6f0de0SAdrian Chadd 	 * an interrupt.  We periodically mark descriptors in this
1685eb6f0de0SAdrian Chadd 	 * way to insure timely replenishing of the supply needed
1686eb6f0de0SAdrian Chadd 	 * for sending frames.  Defering interrupts reduces system
1687eb6f0de0SAdrian Chadd 	 * load and potentially allows more concurrent work to be
1688eb6f0de0SAdrian Chadd 	 * done but if done to aggressively can cause senders to
1689eb6f0de0SAdrian Chadd 	 * backup.
1690eb6f0de0SAdrian Chadd 	 *
1691eb6f0de0SAdrian Chadd 	 * NB: use >= to deal with sc_txintrperiod changing
1692eb6f0de0SAdrian Chadd 	 *     dynamically through sysctl.
1693b8e788a5SAdrian Chadd 	 */
1694eb6f0de0SAdrian Chadd 	if (flags & HAL_TXDESC_INTREQ) {
1695eb6f0de0SAdrian Chadd 		txq->axq_intrcnt = 0;
1696eb6f0de0SAdrian Chadd 	} else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
1697eb6f0de0SAdrian Chadd 		flags |= HAL_TXDESC_INTREQ;
1698eb6f0de0SAdrian Chadd 		txq->axq_intrcnt = 0;
1699eb6f0de0SAdrian Chadd 	}
1700e42b5dbaSAdrian Chadd 
1701eb6f0de0SAdrian Chadd 	/* This point forward is actual TX bits */
1702b8e788a5SAdrian Chadd 
1703b8e788a5SAdrian Chadd 	/*
1704b8e788a5SAdrian Chadd 	 * At this point we are committed to sending the frame
1705b8e788a5SAdrian Chadd 	 * and we don't need to look at m_nextpkt; clear it in
1706b8e788a5SAdrian Chadd 	 * case this frame is part of frag chain.
1707b8e788a5SAdrian Chadd 	 */
1708b8e788a5SAdrian Chadd 	m0->m_nextpkt = NULL;
1709b8e788a5SAdrian Chadd 
1710b8e788a5SAdrian Chadd 	if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
1711b8e788a5SAdrian Chadd 		ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len,
1712b8e788a5SAdrian Chadd 		    sc->sc_hwmap[rix].ieeerate, -1);
1713b8e788a5SAdrian Chadd 
1714b8e788a5SAdrian Chadd 	if (ieee80211_radiotap_active_vap(vap)) {
1715b8e788a5SAdrian Chadd 		u_int64_t tsf = ath_hal_gettsf64(ah);
1716b8e788a5SAdrian Chadd 
1717b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_tsf = htole64(tsf);
1718b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
1719b8e788a5SAdrian Chadd 		if (iswep)
1720b8e788a5SAdrian Chadd 			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
1721b8e788a5SAdrian Chadd 		if (isfrag)
1722b8e788a5SAdrian Chadd 			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
1723b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
1724b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_txpower = ni->ni_txpower;
1725b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
1726b8e788a5SAdrian Chadd 
1727b8e788a5SAdrian Chadd 		ieee80211_radiotap_tx(vap, m0);
1728b8e788a5SAdrian Chadd 	}
1729b8e788a5SAdrian Chadd 
1730eb6f0de0SAdrian Chadd 	/* Blank the legacy rate array */
1731eb6f0de0SAdrian Chadd 	bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1732c1782ce0SAdrian Chadd 
1733b8e788a5SAdrian Chadd 	/*
1734eb6f0de0SAdrian Chadd 	 * ath_buf_set_rate needs at least one rate/try to setup
1735eb6f0de0SAdrian Chadd 	 * the rate scenario.
1736b8e788a5SAdrian Chadd 	 */
1737eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_rc[0].rix = rix;
1738eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_rc[0].tries = try0;
1739eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_rc[0].ratecode = txrate;
1740eb6f0de0SAdrian Chadd 
1741eb6f0de0SAdrian Chadd 	/* Store the decided rate index values away */
1742eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_pktlen = pktlen;
1743eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_hdrlen = hdrlen;
1744eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_atype = atype;
1745eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_txpower = ni->ni_txpower;
1746eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_txrate0 = txrate;
1747eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_try0 = try0;
1748eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_keyix = keyix;
1749eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_txantenna = sc->sc_txantenna;
1750875a9451SAdrian Chadd 	bf->bf_state.bfs_txflags = flags;
1751eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_shpream = shortPreamble;
1752eb6f0de0SAdrian Chadd 
1753eb6f0de0SAdrian Chadd 	/* XXX this should be done in ath_tx_setrate() */
1754eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_ctsrate0 = 0;	/* ie, no hard-coded ctsrate */
1755eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_ctsrate = 0;	/* calculated later */
1756eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_ctsduration = 0;
1757eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_ismrr = ismrr;
1758eb6f0de0SAdrian Chadd 
1759eb6f0de0SAdrian Chadd 	return 0;
1760eb6f0de0SAdrian Chadd }
1761eb6f0de0SAdrian Chadd 
1762b8e788a5SAdrian Chadd /*
17634e81f27cSAdrian Chadd  * Queue a frame to the hardware or software queue.
1764eb6f0de0SAdrian Chadd  *
1765eb6f0de0SAdrian Chadd  * This can be called by the net80211 code.
1766eb6f0de0SAdrian Chadd  *
1767eb6f0de0SAdrian Chadd  * XXX what about locking? Or, push the seqno assign into the
1768eb6f0de0SAdrian Chadd  * XXX aggregate scheduler so its serialised?
17694e81f27cSAdrian Chadd  *
17704e81f27cSAdrian Chadd  * XXX When sending management frames via ath_raw_xmit(),
17714e81f27cSAdrian Chadd  *     should CLRDMASK be set unconditionally?
1772b8e788a5SAdrian Chadd  */
1773eb6f0de0SAdrian Chadd int
1774eb6f0de0SAdrian Chadd ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
1775eb6f0de0SAdrian Chadd     struct ath_buf *bf, struct mbuf *m0)
1776eb6f0de0SAdrian Chadd {
1777eb6f0de0SAdrian Chadd 	struct ieee80211vap *vap = ni->ni_vap;
1778eb6f0de0SAdrian Chadd 	struct ath_vap *avp = ATH_VAP(vap);
17799c85ff91SAdrian Chadd 	int r = 0;
1780eb6f0de0SAdrian Chadd 	u_int pri;
1781eb6f0de0SAdrian Chadd 	int tid;
1782eb6f0de0SAdrian Chadd 	struct ath_txq *txq;
1783eb6f0de0SAdrian Chadd 	int ismcast;
1784eb6f0de0SAdrian Chadd 	const struct ieee80211_frame *wh;
1785eb6f0de0SAdrian Chadd 	int is_ampdu, is_ampdu_tx, is_ampdu_pending;
1786a108d2d6SAdrian Chadd 	ieee80211_seq seqno;
1787eb6f0de0SAdrian Chadd 	uint8_t type, subtype;
1788eb6f0de0SAdrian Chadd 
1789375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
1790375307d4SAdrian Chadd 
1791eb6f0de0SAdrian Chadd 	/*
1792eb6f0de0SAdrian Chadd 	 * Determine the target hardware queue.
1793eb6f0de0SAdrian Chadd 	 *
1794b43facbfSAdrian Chadd 	 * For multicast frames, the txq gets overridden appropriately
1795b43facbfSAdrian Chadd 	 * depending upon the state of PS.
1796eb6f0de0SAdrian Chadd 	 *
1797eb6f0de0SAdrian Chadd 	 * For any other frame, we do a TID/QoS lookup inside the frame
1798eb6f0de0SAdrian Chadd 	 * to see what the TID should be. If it's a non-QoS frame, the
1799eb6f0de0SAdrian Chadd 	 * AC and TID are overridden. The TID/TXQ code assumes the
1800eb6f0de0SAdrian Chadd 	 * TID is on a predictable hardware TXQ, so we don't support
1801eb6f0de0SAdrian Chadd 	 * having a node TID queued to multiple hardware TXQs.
1802eb6f0de0SAdrian Chadd 	 * This may change in the future but would require some locking
1803eb6f0de0SAdrian Chadd 	 * fudgery.
1804eb6f0de0SAdrian Chadd 	 */
1805eb6f0de0SAdrian Chadd 	pri = ath_tx_getac(sc, m0);
1806eb6f0de0SAdrian Chadd 	tid = ath_tx_gettid(sc, m0);
1807eb6f0de0SAdrian Chadd 
1808eb6f0de0SAdrian Chadd 	txq = sc->sc_ac2q[pri];
1809eb6f0de0SAdrian Chadd 	wh = mtod(m0, struct ieee80211_frame *);
1810eb6f0de0SAdrian Chadd 	ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1811eb6f0de0SAdrian Chadd 	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1812eb6f0de0SAdrian Chadd 	subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1813eb6f0de0SAdrian Chadd 
18149c85ff91SAdrian Chadd 	/*
18159c85ff91SAdrian Chadd 	 * Enforce how deep the multicast queue can grow.
18169c85ff91SAdrian Chadd 	 *
18179c85ff91SAdrian Chadd 	 * XXX duplicated in ath_raw_xmit().
18189c85ff91SAdrian Chadd 	 */
18199c85ff91SAdrian Chadd 	if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1820b09e37a1SAdrian Chadd 		if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) {
18219c85ff91SAdrian Chadd 			sc->sc_stats.ast_tx_mcastq_overflow++;
18229c85ff91SAdrian Chadd 			r = ENOBUFS;
18239c85ff91SAdrian Chadd 		}
18249c85ff91SAdrian Chadd 		if (r != 0) {
18259c85ff91SAdrian Chadd 			m_freem(m0);
18269c85ff91SAdrian Chadd 			return r;
18279c85ff91SAdrian Chadd 		}
18289c85ff91SAdrian Chadd 	}
18299c85ff91SAdrian Chadd 
1830eb6f0de0SAdrian Chadd 	/* A-MPDU TX */
1831eb6f0de0SAdrian Chadd 	is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid);
1832eb6f0de0SAdrian Chadd 	is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid);
1833eb6f0de0SAdrian Chadd 	is_ampdu = is_ampdu_tx | is_ampdu_pending;
1834eb6f0de0SAdrian Chadd 
1835a108d2d6SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, ac=%d, is_ampdu=%d\n",
1836a108d2d6SAdrian Chadd 	    __func__, tid, pri, is_ampdu);
1837eb6f0de0SAdrian Chadd 
183846634305SAdrian Chadd 	/* Set local packet state, used to queue packets to hardware */
183946634305SAdrian Chadd 	bf->bf_state.bfs_tid = tid;
1840fc56c9c5SAdrian Chadd 	bf->bf_state.bfs_tx_queue = txq->axq_qnum;
184146634305SAdrian Chadd 	bf->bf_state.bfs_pri = pri;
184246634305SAdrian Chadd 
1843b837332dSAdrian Chadd #if 1
1844c5940c30SAdrian Chadd 	/*
1845b43facbfSAdrian Chadd 	 * When servicing one or more stations in power-save mode
1846b43facbfSAdrian Chadd 	 * (or) if there is some mcast data waiting on the mcast
1847b43facbfSAdrian Chadd 	 * queue (to prevent out of order delivery) multicast frames
1848b43facbfSAdrian Chadd 	 * must be bufferd until after the beacon.
1849b43facbfSAdrian Chadd 	 *
1850b43facbfSAdrian Chadd 	 * TODO: we should lock the mcastq before we check the length.
1851c5940c30SAdrian Chadd 	 */
1852b837332dSAdrian Chadd 	if (sc->sc_cabq_enable && ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) {
1853eb6f0de0SAdrian Chadd 		txq = &avp->av_mcastq;
185446634305SAdrian Chadd 		/*
185546634305SAdrian Chadd 		 * Mark the frame as eventually belonging on the CAB
185646634305SAdrian Chadd 		 * queue, so the descriptor setup functions will
185746634305SAdrian Chadd 		 * correctly initialise the descriptor 'qcuId' field.
185846634305SAdrian Chadd 		 */
1859fc56c9c5SAdrian Chadd 		bf->bf_state.bfs_tx_queue = sc->sc_cabq->axq_qnum;
186046634305SAdrian Chadd 	}
1861b837332dSAdrian Chadd #endif
1862eb6f0de0SAdrian Chadd 
1863eb6f0de0SAdrian Chadd 	/* Do the generic frame setup */
1864eb6f0de0SAdrian Chadd 	/* XXX should just bzero the bf_state? */
1865eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_dobaw = 0;
1866eb6f0de0SAdrian Chadd 
18677561cb5cSAdrian Chadd 	/* A-MPDU TX? Manually set sequence number */
18687561cb5cSAdrian Chadd 	/*
18697561cb5cSAdrian Chadd 	 * Don't do it whilst pending; the net80211 layer still
18707561cb5cSAdrian Chadd 	 * assigns them.
18717561cb5cSAdrian Chadd 	 */
18727561cb5cSAdrian Chadd 	if (is_ampdu_tx) {
1873eb6f0de0SAdrian Chadd 		/*
1874eb6f0de0SAdrian Chadd 		 * Always call; this function will
1875eb6f0de0SAdrian Chadd 		 * handle making sure that null data frames
1876eb6f0de0SAdrian Chadd 		 * don't get a sequence number from the current
1877eb6f0de0SAdrian Chadd 		 * TID and thus mess with the BAW.
1878eb6f0de0SAdrian Chadd 		 */
1879a108d2d6SAdrian Chadd 		seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0);
188042f4d061SAdrian Chadd 
188142f4d061SAdrian Chadd 		/*
188242f4d061SAdrian Chadd 		 * Don't add QoS NULL frames to the BAW.
188342f4d061SAdrian Chadd 		 */
1884a108d2d6SAdrian Chadd 		if (IEEE80211_QOS_HAS_SEQ(wh) &&
1885a108d2d6SAdrian Chadd 		    subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL) {
1886eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_dobaw = 1;
1887eb6f0de0SAdrian Chadd 		}
1888c1782ce0SAdrian Chadd 	}
1889c1782ce0SAdrian Chadd 
1890eb6f0de0SAdrian Chadd 	/*
1891eb6f0de0SAdrian Chadd 	 * If needed, the sequence number has been assigned.
1892eb6f0de0SAdrian Chadd 	 * Squirrel it away somewhere easy to get to.
1893eb6f0de0SAdrian Chadd 	 */
1894a108d2d6SAdrian Chadd 	bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT;
1895b8e788a5SAdrian Chadd 
1896eb6f0de0SAdrian Chadd 	/* Is ampdu pending? fetch the seqno and print it out */
1897eb6f0de0SAdrian Chadd 	if (is_ampdu_pending)
1898eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX,
1899eb6f0de0SAdrian Chadd 		    "%s: tid %d: ampdu pending, seqno %d\n",
1900eb6f0de0SAdrian Chadd 		    __func__, tid, M_SEQNO_GET(m0));
1901eb6f0de0SAdrian Chadd 
1902eb6f0de0SAdrian Chadd 	/* This also sets up the DMA map */
1903b43facbfSAdrian Chadd 	r = ath_tx_normal_setup(sc, ni, bf, m0, txq);
1904eb6f0de0SAdrian Chadd 
1905eb6f0de0SAdrian Chadd 	if (r != 0)
19067561cb5cSAdrian Chadd 		goto done;
1907eb6f0de0SAdrian Chadd 
1908eb6f0de0SAdrian Chadd 	/* At this point m0 could have changed! */
1909eb6f0de0SAdrian Chadd 	m0 = bf->bf_m;
1910eb6f0de0SAdrian Chadd 
1911eb6f0de0SAdrian Chadd #if 1
1912eb6f0de0SAdrian Chadd 	/*
1913eb6f0de0SAdrian Chadd 	 * If it's a multicast frame, do a direct-dispatch to the
1914eb6f0de0SAdrian Chadd 	 * destination hardware queue. Don't bother software
1915eb6f0de0SAdrian Chadd 	 * queuing it.
1916eb6f0de0SAdrian Chadd 	 */
1917eb6f0de0SAdrian Chadd 	/*
1918eb6f0de0SAdrian Chadd 	 * If it's a BAR frame, do a direct dispatch to the
1919eb6f0de0SAdrian Chadd 	 * destination hardware queue. Don't bother software
1920eb6f0de0SAdrian Chadd 	 * queuing it, as the TID will now be paused.
1921eb6f0de0SAdrian Chadd 	 * Sending a BAR frame can occur from the net80211 txa timer
1922eb6f0de0SAdrian Chadd 	 * (ie, retries) or from the ath txtask (completion call.)
1923eb6f0de0SAdrian Chadd 	 * It queues directly to hardware because the TID is paused
1924eb6f0de0SAdrian Chadd 	 * at this point (and won't be unpaused until the BAR has
1925eb6f0de0SAdrian Chadd 	 * either been TXed successfully or max retries has been
1926eb6f0de0SAdrian Chadd 	 * reached.)
1927eb6f0de0SAdrian Chadd 	 */
1928eb6f0de0SAdrian Chadd 	if (txq == &avp->av_mcastq) {
1929d3a6425bSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX,
19300b96ef63SAdrian Chadd 		    "%s: bf=%p: mcastq: TX'ing\n", __func__, bf);
19314e81f27cSAdrian Chadd 		bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
1932eb6f0de0SAdrian Chadd 		ath_tx_xmit_normal(sc, txq, bf);
1933eb6f0de0SAdrian Chadd 	} else if (type == IEEE80211_FC0_TYPE_CTL &&
1934eb6f0de0SAdrian Chadd 		    subtype == IEEE80211_FC0_SUBTYPE_BAR) {
1935d3a6425bSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX,
1936eb6f0de0SAdrian Chadd 		    "%s: BAR: TX'ing direct\n", __func__);
19374e81f27cSAdrian Chadd 		bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
1938eb6f0de0SAdrian Chadd 		ath_tx_xmit_normal(sc, txq, bf);
1939eb6f0de0SAdrian Chadd 	} else {
1940eb6f0de0SAdrian Chadd 		/* add to software queue */
1941d3a6425bSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX,
19420b96ef63SAdrian Chadd 		    "%s: bf=%p: swq: TX'ing\n", __func__, bf);
1943eb6f0de0SAdrian Chadd 		ath_tx_swq(sc, ni, txq, bf);
1944eb6f0de0SAdrian Chadd 	}
1945eb6f0de0SAdrian Chadd #else
1946eb6f0de0SAdrian Chadd 	/*
1947eb6f0de0SAdrian Chadd 	 * For now, since there's no software queue,
1948eb6f0de0SAdrian Chadd 	 * direct-dispatch to the hardware.
1949eb6f0de0SAdrian Chadd 	 */
19504e81f27cSAdrian Chadd 	bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
1951eb6f0de0SAdrian Chadd 	ath_tx_xmit_normal(sc, txq, bf);
1952eb6f0de0SAdrian Chadd #endif
19537561cb5cSAdrian Chadd done:
1954b8e788a5SAdrian Chadd 	return 0;
1955b8e788a5SAdrian Chadd }
1956b8e788a5SAdrian Chadd 
1957b8e788a5SAdrian Chadd static int
1958b8e788a5SAdrian Chadd ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
1959b8e788a5SAdrian Chadd 	struct ath_buf *bf, struct mbuf *m0,
1960b8e788a5SAdrian Chadd 	const struct ieee80211_bpf_params *params)
1961b8e788a5SAdrian Chadd {
1962b8e788a5SAdrian Chadd 	struct ifnet *ifp = sc->sc_ifp;
1963b8e788a5SAdrian Chadd 	struct ieee80211com *ic = ifp->if_l2com;
1964b8e788a5SAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
1965b8e788a5SAdrian Chadd 	struct ieee80211vap *vap = ni->ni_vap;
1966b8e788a5SAdrian Chadd 	int error, ismcast, ismrr;
1967b8e788a5SAdrian Chadd 	int keyix, hdrlen, pktlen, try0, txantenna;
1968eb6f0de0SAdrian Chadd 	u_int8_t rix, txrate;
1969b8e788a5SAdrian Chadd 	struct ieee80211_frame *wh;
1970eb6f0de0SAdrian Chadd 	u_int flags;
1971b8e788a5SAdrian Chadd 	HAL_PKT_TYPE atype;
1972b8e788a5SAdrian Chadd 	const HAL_RATE_TABLE *rt;
1973b8e788a5SAdrian Chadd 	struct ath_desc *ds;
1974b8e788a5SAdrian Chadd 	u_int pri;
1975eb6f0de0SAdrian Chadd 	int o_tid = -1;
1976eb6f0de0SAdrian Chadd 	int do_override;
1977b8e788a5SAdrian Chadd 
1978375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
1979375307d4SAdrian Chadd 
1980b8e788a5SAdrian Chadd 	wh = mtod(m0, struct ieee80211_frame *);
1981b8e788a5SAdrian Chadd 	ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1982b8e788a5SAdrian Chadd 	hdrlen = ieee80211_anyhdrsize(wh);
1983b8e788a5SAdrian Chadd 	/*
1984b8e788a5SAdrian Chadd 	 * Packet length must not include any
1985b8e788a5SAdrian Chadd 	 * pad bytes; deduct them here.
1986b8e788a5SAdrian Chadd 	 */
1987b8e788a5SAdrian Chadd 	/* XXX honor IEEE80211_BPF_DATAPAD */
1988b8e788a5SAdrian Chadd 	pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN;
1989b8e788a5SAdrian Chadd 
199003682514SAdrian Chadd 	ATH_KTR(sc, ATH_KTR_TX, 2,
199103682514SAdrian Chadd 	     "ath_tx_raw_start: ni=%p, bf=%p, raw", ni, bf);
199203682514SAdrian Chadd 
1993eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n",
1994eb6f0de0SAdrian Chadd 	    __func__, ismcast);
1995eb6f0de0SAdrian Chadd 
19967561cb5cSAdrian Chadd 	pri = params->ibp_pri & 3;
19977561cb5cSAdrian Chadd 	/* Override pri if the frame isn't a QoS one */
19987561cb5cSAdrian Chadd 	if (! IEEE80211_QOS_HAS_SEQ(wh))
19997561cb5cSAdrian Chadd 		pri = ath_tx_getac(sc, m0);
20007561cb5cSAdrian Chadd 
20017561cb5cSAdrian Chadd 	/* XXX If it's an ADDBA, override the correct queue */
20027561cb5cSAdrian Chadd 	do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid);
20037561cb5cSAdrian Chadd 
20047561cb5cSAdrian Chadd 	/* Map ADDBA to the correct priority */
20057561cb5cSAdrian Chadd 	if (do_override) {
20067561cb5cSAdrian Chadd #if 0
20077561cb5cSAdrian Chadd 		device_printf(sc->sc_dev,
20087561cb5cSAdrian Chadd 		    "%s: overriding tid %d pri %d -> %d\n",
20097561cb5cSAdrian Chadd 		    __func__, o_tid, pri, TID_TO_WME_AC(o_tid));
20107561cb5cSAdrian Chadd #endif
20117561cb5cSAdrian Chadd 		pri = TID_TO_WME_AC(o_tid);
20127561cb5cSAdrian Chadd 	}
20137561cb5cSAdrian Chadd 
201481a82688SAdrian Chadd 	/* Handle encryption twiddling if needed */
2015eb6f0de0SAdrian Chadd 	if (! ath_tx_tag_crypto(sc, ni,
2016eb6f0de0SAdrian Chadd 	    m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0,
2017eb6f0de0SAdrian Chadd 	    &hdrlen, &pktlen, &keyix)) {
2018b8e788a5SAdrian Chadd 		ath_freetx(m0);
2019b8e788a5SAdrian Chadd 		return EIO;
2020b8e788a5SAdrian Chadd 	}
2021b8e788a5SAdrian Chadd 	/* packet header may have moved, reset our local pointer */
2022b8e788a5SAdrian Chadd 	wh = mtod(m0, struct ieee80211_frame *);
2023b8e788a5SAdrian Chadd 
2024eb6f0de0SAdrian Chadd 	/* Do the generic frame setup */
2025eb6f0de0SAdrian Chadd 	/* XXX should just bzero the bf_state? */
2026eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_dobaw = 0;
2027eb6f0de0SAdrian Chadd 
2028b8e788a5SAdrian Chadd 	error = ath_tx_dmasetup(sc, bf, m0);
2029b8e788a5SAdrian Chadd 	if (error != 0)
2030b8e788a5SAdrian Chadd 		return error;
2031b8e788a5SAdrian Chadd 	m0 = bf->bf_m;				/* NB: may have changed */
2032b8e788a5SAdrian Chadd 	wh = mtod(m0, struct ieee80211_frame *);
2033b8e788a5SAdrian Chadd 	bf->bf_node = ni;			/* NB: held reference */
2034b8e788a5SAdrian Chadd 
20354e81f27cSAdrian Chadd 	/* Always enable CLRDMASK for raw frames for now.. */
2036b8e788a5SAdrian Chadd 	flags = HAL_TXDESC_CLRDMASK;		/* XXX needed for crypto errs */
2037b8e788a5SAdrian Chadd 	flags |= HAL_TXDESC_INTREQ;		/* force interrupt */
2038b8e788a5SAdrian Chadd 	if (params->ibp_flags & IEEE80211_BPF_RTS)
2039b8e788a5SAdrian Chadd 		flags |= HAL_TXDESC_RTSENA;
2040eb6f0de0SAdrian Chadd 	else if (params->ibp_flags & IEEE80211_BPF_CTS) {
2041eb6f0de0SAdrian Chadd 		/* XXX assume 11g/11n protection? */
2042eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_doprot = 1;
2043b8e788a5SAdrian Chadd 		flags |= HAL_TXDESC_CTSENA;
2044eb6f0de0SAdrian Chadd 	}
2045b8e788a5SAdrian Chadd 	/* XXX leave ismcast to injector? */
2046b8e788a5SAdrian Chadd 	if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast)
2047b8e788a5SAdrian Chadd 		flags |= HAL_TXDESC_NOACK;
2048b8e788a5SAdrian Chadd 
2049b8e788a5SAdrian Chadd 	rt = sc->sc_currates;
2050b8e788a5SAdrian Chadd 	KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
2051b8e788a5SAdrian Chadd 	rix = ath_tx_findrix(sc, params->ibp_rate0);
2052b8e788a5SAdrian Chadd 	txrate = rt->info[rix].rateCode;
2053b8e788a5SAdrian Chadd 	if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
2054b8e788a5SAdrian Chadd 		txrate |= rt->info[rix].shortPreamble;
2055b8e788a5SAdrian Chadd 	sc->sc_txrix = rix;
2056b8e788a5SAdrian Chadd 	try0 = params->ibp_try0;
2057b8e788a5SAdrian Chadd 	ismrr = (params->ibp_try1 != 0);
2058b8e788a5SAdrian Chadd 	txantenna = params->ibp_pri >> 2;
2059b8e788a5SAdrian Chadd 	if (txantenna == 0)			/* XXX? */
2060b8e788a5SAdrian Chadd 		txantenna = sc->sc_txantenna;
206179f02dbfSAdrian Chadd 
206279f02dbfSAdrian Chadd 	/*
2063eb6f0de0SAdrian Chadd 	 * Since ctsrate is fixed, store it away for later
2064eb6f0de0SAdrian Chadd 	 * use when the descriptor fields are being set.
206579f02dbfSAdrian Chadd 	 */
2066eb6f0de0SAdrian Chadd 	if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA))
2067eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate;
206879f02dbfSAdrian Chadd 
2069b8e788a5SAdrian Chadd 	/*
2070b8e788a5SAdrian Chadd 	 * NB: we mark all packets as type PSPOLL so the h/w won't
2071b8e788a5SAdrian Chadd 	 * set the sequence number, duration, etc.
2072b8e788a5SAdrian Chadd 	 */
2073b8e788a5SAdrian Chadd 	atype = HAL_PKT_TYPE_PSPOLL;
2074b8e788a5SAdrian Chadd 
2075b8e788a5SAdrian Chadd 	if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
2076b8e788a5SAdrian Chadd 		ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
2077b8e788a5SAdrian Chadd 		    sc->sc_hwmap[rix].ieeerate, -1);
2078b8e788a5SAdrian Chadd 
2079b8e788a5SAdrian Chadd 	if (ieee80211_radiotap_active_vap(vap)) {
2080b8e788a5SAdrian Chadd 		u_int64_t tsf = ath_hal_gettsf64(ah);
2081b8e788a5SAdrian Chadd 
2082b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_tsf = htole64(tsf);
2083b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
2084b8e788a5SAdrian Chadd 		if (wh->i_fc[1] & IEEE80211_FC1_WEP)
2085b8e788a5SAdrian Chadd 			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2086b8e788a5SAdrian Chadd 		if (m0->m_flags & M_FRAG)
2087b8e788a5SAdrian Chadd 			sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
2088b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
2089b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_txpower = ni->ni_txpower;
2090b8e788a5SAdrian Chadd 		sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
2091b8e788a5SAdrian Chadd 
2092b8e788a5SAdrian Chadd 		ieee80211_radiotap_tx(vap, m0);
2093b8e788a5SAdrian Chadd 	}
2094b8e788a5SAdrian Chadd 
2095b8e788a5SAdrian Chadd 	/*
2096b8e788a5SAdrian Chadd 	 * Formulate first tx descriptor with tx controls.
2097b8e788a5SAdrian Chadd 	 */
2098b8e788a5SAdrian Chadd 	ds = bf->bf_desc;
2099b8e788a5SAdrian Chadd 	/* XXX check return value? */
2100eb6f0de0SAdrian Chadd 
2101eb6f0de0SAdrian Chadd 	/* Store the decided rate index values away */
2102eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_pktlen = pktlen;
2103eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_hdrlen = hdrlen;
2104eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_atype = atype;
2105eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_txpower = params->ibp_power;
2106eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_txrate0 = txrate;
2107eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_try0 = try0;
2108eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_keyix = keyix;
2109eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_txantenna = txantenna;
2110875a9451SAdrian Chadd 	bf->bf_state.bfs_txflags = flags;
2111eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_shpream =
2112eb6f0de0SAdrian Chadd 	    !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE);
2113b8e788a5SAdrian Chadd 
211446634305SAdrian Chadd 	/* Set local packet state, used to queue packets to hardware */
211546634305SAdrian Chadd 	bf->bf_state.bfs_tid = WME_AC_TO_TID(pri);
2116fc56c9c5SAdrian Chadd 	bf->bf_state.bfs_tx_queue = sc->sc_ac2q[pri]->axq_qnum;
211746634305SAdrian Chadd 	bf->bf_state.bfs_pri = pri;
211846634305SAdrian Chadd 
2119eb6f0de0SAdrian Chadd 	/* XXX this should be done in ath_tx_setrate() */
2120eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_ctsrate = 0;
2121eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_ctsduration = 0;
2122eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_ismrr = ismrr;
2123eb6f0de0SAdrian Chadd 
2124eb6f0de0SAdrian Chadd 	/* Blank the legacy rate array */
2125eb6f0de0SAdrian Chadd 	bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
2126eb6f0de0SAdrian Chadd 
2127eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_rc[0].rix =
2128eb6f0de0SAdrian Chadd 	    ath_tx_findrix(sc, params->ibp_rate0);
2129eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_rc[0].tries = try0;
2130eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_rc[0].ratecode = txrate;
2131c1782ce0SAdrian Chadd 
2132c1782ce0SAdrian Chadd 	if (ismrr) {
2133eb6f0de0SAdrian Chadd 		int rix;
2134c1782ce0SAdrian Chadd 
2135b8e788a5SAdrian Chadd 		rix = ath_tx_findrix(sc, params->ibp_rate1);
2136eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_rc[1].rix = rix;
2137eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_rc[1].tries = params->ibp_try1;
2138c1782ce0SAdrian Chadd 
2139eb6f0de0SAdrian Chadd 		rix = ath_tx_findrix(sc, params->ibp_rate2);
2140eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_rc[2].rix = rix;
2141eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_rc[2].tries = params->ibp_try2;
2142eb6f0de0SAdrian Chadd 
2143eb6f0de0SAdrian Chadd 		rix = ath_tx_findrix(sc, params->ibp_rate3);
2144eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_rc[3].rix = rix;
2145eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_rc[3].tries = params->ibp_try3;
2146c1782ce0SAdrian Chadd 	}
2147eb6f0de0SAdrian Chadd 	/*
2148eb6f0de0SAdrian Chadd 	 * All the required rate control decisions have been made;
2149eb6f0de0SAdrian Chadd 	 * fill in the rc flags.
2150eb6f0de0SAdrian Chadd 	 */
2151eb6f0de0SAdrian Chadd 	ath_tx_rate_fill_rcflags(sc, bf);
2152b8e788a5SAdrian Chadd 
2153b8e788a5SAdrian Chadd 	/* NB: no buffered multicast in power save support */
2154eb6f0de0SAdrian Chadd 
2155eb6f0de0SAdrian Chadd 	/*
2156eb6f0de0SAdrian Chadd 	 * If we're overiding the ADDBA destination, dump directly
2157eb6f0de0SAdrian Chadd 	 * into the hardware queue, right after any pending
2158eb6f0de0SAdrian Chadd 	 * frames to that node are.
2159eb6f0de0SAdrian Chadd 	 */
2160eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n",
2161eb6f0de0SAdrian Chadd 	    __func__, do_override);
2162eb6f0de0SAdrian Chadd 
216394eefcf1SAdrian Chadd #if 1
2164eb6f0de0SAdrian Chadd 	if (do_override) {
21654e81f27cSAdrian Chadd 		bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
2166eb6f0de0SAdrian Chadd 		ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf);
2167eb6f0de0SAdrian Chadd 	} else {
2168eb6f0de0SAdrian Chadd 		/* Queue to software queue */
2169eb6f0de0SAdrian Chadd 		ath_tx_swq(sc, ni, sc->sc_ac2q[pri], bf);
2170eb6f0de0SAdrian Chadd 	}
217194eefcf1SAdrian Chadd #else
217294eefcf1SAdrian Chadd 	/* Direct-dispatch to the hardware */
217394eefcf1SAdrian Chadd 	bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
217494eefcf1SAdrian Chadd 	ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf);
217594eefcf1SAdrian Chadd #endif
2176b8e788a5SAdrian Chadd 	return 0;
2177b8e788a5SAdrian Chadd }
2178b8e788a5SAdrian Chadd 
2179eb6f0de0SAdrian Chadd /*
2180eb6f0de0SAdrian Chadd  * Send a raw frame.
2181eb6f0de0SAdrian Chadd  *
2182eb6f0de0SAdrian Chadd  * This can be called by net80211.
2183eb6f0de0SAdrian Chadd  */
2184b8e788a5SAdrian Chadd int
2185b8e788a5SAdrian Chadd ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
2186b8e788a5SAdrian Chadd 	const struct ieee80211_bpf_params *params)
2187b8e788a5SAdrian Chadd {
2188b8e788a5SAdrian Chadd 	struct ieee80211com *ic = ni->ni_ic;
2189b8e788a5SAdrian Chadd 	struct ifnet *ifp = ic->ic_ifp;
2190b8e788a5SAdrian Chadd 	struct ath_softc *sc = ifp->if_softc;
2191b8e788a5SAdrian Chadd 	struct ath_buf *bf;
21929c85ff91SAdrian Chadd 	struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *);
21939c85ff91SAdrian Chadd 	int error = 0;
2194b8e788a5SAdrian Chadd 
2195ef27340cSAdrian Chadd 	ATH_PCU_LOCK(sc);
2196ef27340cSAdrian Chadd 	if (sc->sc_inreset_cnt > 0) {
2197ef27340cSAdrian Chadd 		device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; bailing\n",
2198ef27340cSAdrian Chadd 		    __func__);
2199ef27340cSAdrian Chadd 		error = EIO;
2200ef27340cSAdrian Chadd 		ATH_PCU_UNLOCK(sc);
2201ef27340cSAdrian Chadd 		goto bad0;
2202ef27340cSAdrian Chadd 	}
2203ef27340cSAdrian Chadd 	sc->sc_txstart_cnt++;
2204ef27340cSAdrian Chadd 	ATH_PCU_UNLOCK(sc);
2205ef27340cSAdrian Chadd 
22061b5c5f5aSAdrian Chadd 	ATH_TX_LOCK(sc);
22071b5c5f5aSAdrian Chadd 
2208b8e788a5SAdrian Chadd 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) {
2209b8e788a5SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__,
2210b8e788a5SAdrian Chadd 		    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ?
2211b8e788a5SAdrian Chadd 			"!running" : "invalid");
2212b8e788a5SAdrian Chadd 		m_freem(m);
2213b8e788a5SAdrian Chadd 		error = ENETDOWN;
2214b8e788a5SAdrian Chadd 		goto bad;
2215b8e788a5SAdrian Chadd 	}
22169c85ff91SAdrian Chadd 
22179c85ff91SAdrian Chadd 	/*
22189c85ff91SAdrian Chadd 	 * Enforce how deep the multicast queue can grow.
22199c85ff91SAdrian Chadd 	 *
22209c85ff91SAdrian Chadd 	 * XXX duplicated in ath_tx_start().
22219c85ff91SAdrian Chadd 	 */
22229c85ff91SAdrian Chadd 	if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2223b09e37a1SAdrian Chadd 		if (sc->sc_cabq->axq_depth > sc->sc_txq_mcastq_maxdepth) {
22249c85ff91SAdrian Chadd 			sc->sc_stats.ast_tx_mcastq_overflow++;
22259c85ff91SAdrian Chadd 			error = ENOBUFS;
22269c85ff91SAdrian Chadd 		}
22279c85ff91SAdrian Chadd 
22289c85ff91SAdrian Chadd 		if (error != 0) {
22299c85ff91SAdrian Chadd 			m_freem(m);
22309c85ff91SAdrian Chadd 			goto bad;
22319c85ff91SAdrian Chadd 		}
22329c85ff91SAdrian Chadd 	}
22339c85ff91SAdrian Chadd 
2234b8e788a5SAdrian Chadd 	/*
2235b8e788a5SAdrian Chadd 	 * Grab a TX buffer and associated resources.
2236b8e788a5SAdrian Chadd 	 */
2237af33d486SAdrian Chadd 	bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
2238b8e788a5SAdrian Chadd 	if (bf == NULL) {
2239b8e788a5SAdrian Chadd 		sc->sc_stats.ast_tx_nobuf++;
2240b8e788a5SAdrian Chadd 		m_freem(m);
2241b8e788a5SAdrian Chadd 		error = ENOBUFS;
2242b8e788a5SAdrian Chadd 		goto bad;
2243b8e788a5SAdrian Chadd 	}
224403682514SAdrian Chadd 	ATH_KTR(sc, ATH_KTR_TX, 3, "ath_raw_xmit: m=%p, params=%p, bf=%p\n",
224503682514SAdrian Chadd 	    m, params,  bf);
2246b8e788a5SAdrian Chadd 
2247b8e788a5SAdrian Chadd 	if (params == NULL) {
2248b8e788a5SAdrian Chadd 		/*
2249b8e788a5SAdrian Chadd 		 * Legacy path; interpret frame contents to decide
2250b8e788a5SAdrian Chadd 		 * precisely how to send the frame.
2251b8e788a5SAdrian Chadd 		 */
2252b8e788a5SAdrian Chadd 		if (ath_tx_start(sc, ni, bf, m)) {
2253b8e788a5SAdrian Chadd 			error = EIO;		/* XXX */
2254b8e788a5SAdrian Chadd 			goto bad2;
2255b8e788a5SAdrian Chadd 		}
2256b8e788a5SAdrian Chadd 	} else {
2257b8e788a5SAdrian Chadd 		/*
2258b8e788a5SAdrian Chadd 		 * Caller supplied explicit parameters to use in
2259b8e788a5SAdrian Chadd 		 * sending the frame.
2260b8e788a5SAdrian Chadd 		 */
2261b8e788a5SAdrian Chadd 		if (ath_tx_raw_start(sc, ni, bf, m, params)) {
2262b8e788a5SAdrian Chadd 			error = EIO;		/* XXX */
2263b8e788a5SAdrian Chadd 			goto bad2;
2264b8e788a5SAdrian Chadd 		}
2265b8e788a5SAdrian Chadd 	}
2266b8e788a5SAdrian Chadd 	sc->sc_wd_timer = 5;
2267b8e788a5SAdrian Chadd 	ifp->if_opackets++;
2268b8e788a5SAdrian Chadd 	sc->sc_stats.ast_tx_raw++;
2269b8e788a5SAdrian Chadd 
2270548a605dSAdrian Chadd 	/*
2271548a605dSAdrian Chadd 	 * Update the TIM - if there's anything queued to the
2272548a605dSAdrian Chadd 	 * software queue and power save is enabled, we should
2273548a605dSAdrian Chadd 	 * set the TIM.
2274548a605dSAdrian Chadd 	 */
2275548a605dSAdrian Chadd 	ath_tx_update_tim(sc, ni, 1);
2276548a605dSAdrian Chadd 
2277974185bbSAdrian Chadd 	ATH_TX_UNLOCK(sc);
2278974185bbSAdrian Chadd 
2279ef27340cSAdrian Chadd 	ATH_PCU_LOCK(sc);
2280ef27340cSAdrian Chadd 	sc->sc_txstart_cnt--;
2281ef27340cSAdrian Chadd 	ATH_PCU_UNLOCK(sc);
2282ef27340cSAdrian Chadd 
2283b8e788a5SAdrian Chadd 	return 0;
2284b8e788a5SAdrian Chadd bad2:
228503682514SAdrian Chadd 	ATH_KTR(sc, ATH_KTR_TX, 3, "ath_raw_xmit: bad2: m=%p, params=%p, "
228603682514SAdrian Chadd 	    "bf=%p",
228703682514SAdrian Chadd 	    m,
228803682514SAdrian Chadd 	    params,
228903682514SAdrian Chadd 	    bf);
2290b8e788a5SAdrian Chadd 	ATH_TXBUF_LOCK(sc);
2291e1a50456SAdrian Chadd 	ath_returnbuf_head(sc, bf);
2292b8e788a5SAdrian Chadd 	ATH_TXBUF_UNLOCK(sc);
2293b8e788a5SAdrian Chadd bad:
22941b5c5f5aSAdrian Chadd 
22951b5c5f5aSAdrian Chadd 	ATH_TX_UNLOCK(sc);
22961b5c5f5aSAdrian Chadd 
2297ef27340cSAdrian Chadd 	ATH_PCU_LOCK(sc);
2298ef27340cSAdrian Chadd 	sc->sc_txstart_cnt--;
2299ef27340cSAdrian Chadd 	ATH_PCU_UNLOCK(sc);
2300ef27340cSAdrian Chadd bad0:
230103682514SAdrian Chadd 	ATH_KTR(sc, ATH_KTR_TX, 2, "ath_raw_xmit: bad0: m=%p, params=%p",
230203682514SAdrian Chadd 	    m, params);
2303b8e788a5SAdrian Chadd 	ifp->if_oerrors++;
2304b8e788a5SAdrian Chadd 	sc->sc_stats.ast_tx_raw_fail++;
2305b8e788a5SAdrian Chadd 	ieee80211_free_node(ni);
2306ef27340cSAdrian Chadd 
2307b8e788a5SAdrian Chadd 	return error;
2308b8e788a5SAdrian Chadd }
2309eb6f0de0SAdrian Chadd 
2310eb6f0de0SAdrian Chadd /* Some helper functions */
2311eb6f0de0SAdrian Chadd 
2312eb6f0de0SAdrian Chadd /*
2313eb6f0de0SAdrian Chadd  * ADDBA (and potentially others) need to be placed in the same
2314eb6f0de0SAdrian Chadd  * hardware queue as the TID/node it's relating to. This is so
2315eb6f0de0SAdrian Chadd  * it goes out after any pending non-aggregate frames to the
2316eb6f0de0SAdrian Chadd  * same node/TID.
2317eb6f0de0SAdrian Chadd  *
2318eb6f0de0SAdrian Chadd  * If this isn't done, the ADDBA can go out before the frames
2319eb6f0de0SAdrian Chadd  * queued in hardware. Even though these frames have a sequence
2320eb6f0de0SAdrian Chadd  * number -earlier- than the ADDBA can be transmitted (but
2321eb6f0de0SAdrian Chadd  * no frames whose sequence numbers are after the ADDBA should
2322eb6f0de0SAdrian Chadd  * be!) they'll arrive after the ADDBA - and the receiving end
2323eb6f0de0SAdrian Chadd  * will simply drop them as being out of the BAW.
2324eb6f0de0SAdrian Chadd  *
2325eb6f0de0SAdrian Chadd  * The frames can't be appended to the TID software queue - it'll
2326eb6f0de0SAdrian Chadd  * never be sent out. So these frames have to be directly
2327eb6f0de0SAdrian Chadd  * dispatched to the hardware, rather than queued in software.
2328eb6f0de0SAdrian Chadd  * So if this function returns true, the TXQ has to be
2329eb6f0de0SAdrian Chadd  * overridden and it has to be directly dispatched.
2330eb6f0de0SAdrian Chadd  *
2331eb6f0de0SAdrian Chadd  * It's a dirty hack, but someone's gotta do it.
2332eb6f0de0SAdrian Chadd  */
2333eb6f0de0SAdrian Chadd 
2334eb6f0de0SAdrian Chadd /*
2335eb6f0de0SAdrian Chadd  * XXX doesn't belong here!
2336eb6f0de0SAdrian Chadd  */
2337eb6f0de0SAdrian Chadd static int
2338eb6f0de0SAdrian Chadd ieee80211_is_action(struct ieee80211_frame *wh)
2339eb6f0de0SAdrian Chadd {
2340eb6f0de0SAdrian Chadd 	/* Type: Management frame? */
2341eb6f0de0SAdrian Chadd 	if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
2342eb6f0de0SAdrian Chadd 	    IEEE80211_FC0_TYPE_MGT)
2343eb6f0de0SAdrian Chadd 		return 0;
2344eb6f0de0SAdrian Chadd 
2345eb6f0de0SAdrian Chadd 	/* Subtype: Action frame? */
2346eb6f0de0SAdrian Chadd 	if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) !=
2347eb6f0de0SAdrian Chadd 	    IEEE80211_FC0_SUBTYPE_ACTION)
2348eb6f0de0SAdrian Chadd 		return 0;
2349eb6f0de0SAdrian Chadd 
2350eb6f0de0SAdrian Chadd 	return 1;
2351eb6f0de0SAdrian Chadd }
2352eb6f0de0SAdrian Chadd 
2353eb6f0de0SAdrian Chadd #define	MS(_v, _f)	(((_v) & _f) >> _f##_S)
2354eb6f0de0SAdrian Chadd /*
2355eb6f0de0SAdrian Chadd  * Return an alternate TID for ADDBA request frames.
2356eb6f0de0SAdrian Chadd  *
2357eb6f0de0SAdrian Chadd  * Yes, this likely should be done in the net80211 layer.
2358eb6f0de0SAdrian Chadd  */
2359eb6f0de0SAdrian Chadd static int
2360eb6f0de0SAdrian Chadd ath_tx_action_frame_override_queue(struct ath_softc *sc,
2361eb6f0de0SAdrian Chadd     struct ieee80211_node *ni,
2362eb6f0de0SAdrian Chadd     struct mbuf *m0, int *tid)
2363eb6f0de0SAdrian Chadd {
2364eb6f0de0SAdrian Chadd 	struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
2365eb6f0de0SAdrian Chadd 	struct ieee80211_action_ba_addbarequest *ia;
2366eb6f0de0SAdrian Chadd 	uint8_t *frm;
2367eb6f0de0SAdrian Chadd 	uint16_t baparamset;
2368eb6f0de0SAdrian Chadd 
2369eb6f0de0SAdrian Chadd 	/* Not action frame? Bail */
2370eb6f0de0SAdrian Chadd 	if (! ieee80211_is_action(wh))
2371eb6f0de0SAdrian Chadd 		return 0;
2372eb6f0de0SAdrian Chadd 
2373eb6f0de0SAdrian Chadd 	/* XXX Not needed for frames we send? */
2374eb6f0de0SAdrian Chadd #if 0
2375eb6f0de0SAdrian Chadd 	/* Correct length? */
2376eb6f0de0SAdrian Chadd 	if (! ieee80211_parse_action(ni, m))
2377eb6f0de0SAdrian Chadd 		return 0;
2378eb6f0de0SAdrian Chadd #endif
2379eb6f0de0SAdrian Chadd 
2380eb6f0de0SAdrian Chadd 	/* Extract out action frame */
2381eb6f0de0SAdrian Chadd 	frm = (u_int8_t *)&wh[1];
2382eb6f0de0SAdrian Chadd 	ia = (struct ieee80211_action_ba_addbarequest *) frm;
2383eb6f0de0SAdrian Chadd 
2384eb6f0de0SAdrian Chadd 	/* Not ADDBA? Bail */
2385eb6f0de0SAdrian Chadd 	if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA)
2386eb6f0de0SAdrian Chadd 		return 0;
2387eb6f0de0SAdrian Chadd 	if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST)
2388eb6f0de0SAdrian Chadd 		return 0;
2389eb6f0de0SAdrian Chadd 
2390eb6f0de0SAdrian Chadd 	/* Extract TID, return it */
2391eb6f0de0SAdrian Chadd 	baparamset = le16toh(ia->rq_baparamset);
2392eb6f0de0SAdrian Chadd 	*tid = (int) MS(baparamset, IEEE80211_BAPS_TID);
2393eb6f0de0SAdrian Chadd 
2394eb6f0de0SAdrian Chadd 	return 1;
2395eb6f0de0SAdrian Chadd }
2396eb6f0de0SAdrian Chadd #undef	MS
2397eb6f0de0SAdrian Chadd 
2398eb6f0de0SAdrian Chadd /* Per-node software queue operations */
2399eb6f0de0SAdrian Chadd 
2400eb6f0de0SAdrian Chadd /*
2401eb6f0de0SAdrian Chadd  * Add the current packet to the given BAW.
2402eb6f0de0SAdrian Chadd  * It is assumed that the current packet
2403eb6f0de0SAdrian Chadd  *
2404eb6f0de0SAdrian Chadd  * + fits inside the BAW;
2405eb6f0de0SAdrian Chadd  * + already has had a sequence number allocated.
2406eb6f0de0SAdrian Chadd  *
2407eb6f0de0SAdrian Chadd  * Since the BAW status may be modified by both the ath task and
2408eb6f0de0SAdrian Chadd  * the net80211/ifnet contexts, the TID must be locked.
2409eb6f0de0SAdrian Chadd  */
2410eb6f0de0SAdrian Chadd void
2411eb6f0de0SAdrian Chadd ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an,
2412eb6f0de0SAdrian Chadd     struct ath_tid *tid, struct ath_buf *bf)
2413eb6f0de0SAdrian Chadd {
2414eb6f0de0SAdrian Chadd 	int index, cindex;
2415eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
2416eb6f0de0SAdrian Chadd 
2417375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
2418eb6f0de0SAdrian Chadd 
2419eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_isretried)
2420eb6f0de0SAdrian Chadd 		return;
2421eb6f0de0SAdrian Chadd 
2422c7c07341SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid->tid);
2423c7c07341SAdrian Chadd 
24247561cb5cSAdrian Chadd 	if (! bf->bf_state.bfs_dobaw) {
24257561cb5cSAdrian Chadd 		device_printf(sc->sc_dev,
24267561cb5cSAdrian Chadd 		    "%s: dobaw=0, seqno=%d, window %d:%d\n",
24277561cb5cSAdrian Chadd 		    __func__,
24287561cb5cSAdrian Chadd 		    SEQNO(bf->bf_state.bfs_seqno),
24297561cb5cSAdrian Chadd 		    tap->txa_start,
24307561cb5cSAdrian Chadd 		    tap->txa_wnd);
24317561cb5cSAdrian Chadd 	}
24327561cb5cSAdrian Chadd 
2433eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_addedbaw)
2434eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev,
2435a108d2d6SAdrian Chadd 		    "%s: re-added? tid=%d, seqno %d; window %d:%d; "
2436d4365d16SAdrian Chadd 		    "baw head=%d tail=%d\n",
2437a108d2d6SAdrian Chadd 		    __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
2438d4365d16SAdrian Chadd 		    tap->txa_start, tap->txa_wnd, tid->baw_head,
2439d4365d16SAdrian Chadd 		    tid->baw_tail);
2440eb6f0de0SAdrian Chadd 
2441eb6f0de0SAdrian Chadd 	/*
24427561cb5cSAdrian Chadd 	 * Verify that the given sequence number is not outside of the
24437561cb5cSAdrian Chadd 	 * BAW.  Complain loudly if that's the case.
24447561cb5cSAdrian Chadd 	 */
24457561cb5cSAdrian Chadd 	if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
24467561cb5cSAdrian Chadd 	    SEQNO(bf->bf_state.bfs_seqno))) {
24477561cb5cSAdrian Chadd 		device_printf(sc->sc_dev,
24487561cb5cSAdrian Chadd 		    "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; "
24497561cb5cSAdrian Chadd 		    "baw head=%d tail=%d\n",
24507561cb5cSAdrian Chadd 		    __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
24517561cb5cSAdrian Chadd 		    tap->txa_start, tap->txa_wnd, tid->baw_head,
24527561cb5cSAdrian Chadd 		    tid->baw_tail);
24537561cb5cSAdrian Chadd 	}
24547561cb5cSAdrian Chadd 
24557561cb5cSAdrian Chadd 	/*
2456eb6f0de0SAdrian Chadd 	 * ni->ni_txseqs[] is the currently allocated seqno.
2457eb6f0de0SAdrian Chadd 	 * the txa state contains the current baw start.
2458eb6f0de0SAdrian Chadd 	 */
2459eb6f0de0SAdrian Chadd 	index  = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno));
2460eb6f0de0SAdrian Chadd 	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2461eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2462a108d2d6SAdrian Chadd 	    "%s: tid=%d, seqno %d; window %d:%d; index=%d cindex=%d "
2463d4365d16SAdrian Chadd 	    "baw head=%d tail=%d\n",
2464a108d2d6SAdrian Chadd 	    __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
2465d4365d16SAdrian Chadd 	    tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head,
2466d4365d16SAdrian Chadd 	    tid->baw_tail);
2467eb6f0de0SAdrian Chadd 
2468eb6f0de0SAdrian Chadd 
2469eb6f0de0SAdrian Chadd #if 0
2470eb6f0de0SAdrian Chadd 	assert(tid->tx_buf[cindex] == NULL);
2471eb6f0de0SAdrian Chadd #endif
2472eb6f0de0SAdrian Chadd 	if (tid->tx_buf[cindex] != NULL) {
2473eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev,
2474eb6f0de0SAdrian Chadd 		    "%s: ba packet dup (index=%d, cindex=%d, "
2475eb6f0de0SAdrian Chadd 		    "head=%d, tail=%d)\n",
2476eb6f0de0SAdrian Chadd 		    __func__, index, cindex, tid->baw_head, tid->baw_tail);
2477eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev,
2478eb6f0de0SAdrian Chadd 		    "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n",
2479eb6f0de0SAdrian Chadd 		    __func__,
2480eb6f0de0SAdrian Chadd 		    tid->tx_buf[cindex],
2481eb6f0de0SAdrian Chadd 		    SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno),
2482eb6f0de0SAdrian Chadd 		    bf,
2483eb6f0de0SAdrian Chadd 		    SEQNO(bf->bf_state.bfs_seqno)
2484eb6f0de0SAdrian Chadd 		);
2485eb6f0de0SAdrian Chadd 	}
2486eb6f0de0SAdrian Chadd 	tid->tx_buf[cindex] = bf;
2487eb6f0de0SAdrian Chadd 
2488d4365d16SAdrian Chadd 	if (index >= ((tid->baw_tail - tid->baw_head) &
2489d4365d16SAdrian Chadd 	    (ATH_TID_MAX_BUFS - 1))) {
2490eb6f0de0SAdrian Chadd 		tid->baw_tail = cindex;
2491eb6f0de0SAdrian Chadd 		INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
2492eb6f0de0SAdrian Chadd 	}
2493eb6f0de0SAdrian Chadd }
2494eb6f0de0SAdrian Chadd 
2495eb6f0de0SAdrian Chadd /*
249638962489SAdrian Chadd  * Flip the BAW buffer entry over from the existing one to the new one.
249738962489SAdrian Chadd  *
249838962489SAdrian Chadd  * When software retransmitting a (sub-)frame, it is entirely possible that
249938962489SAdrian Chadd  * the frame ath_buf is marked as BUSY and can't be immediately reused.
250038962489SAdrian Chadd  * In that instance the buffer is cloned and the new buffer is used for
250138962489SAdrian Chadd  * retransmit. We thus need to update the ath_buf slot in the BAW buf
250238962489SAdrian Chadd  * tracking array to maintain consistency.
250338962489SAdrian Chadd  */
250438962489SAdrian Chadd static void
250538962489SAdrian Chadd ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an,
250638962489SAdrian Chadd     struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf)
250738962489SAdrian Chadd {
250838962489SAdrian Chadd 	int index, cindex;
250938962489SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
251038962489SAdrian Chadd 	int seqno = SEQNO(old_bf->bf_state.bfs_seqno);
251138962489SAdrian Chadd 
2512375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
251338962489SAdrian Chadd 
251438962489SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid->tid);
251538962489SAdrian Chadd 	index  = ATH_BA_INDEX(tap->txa_start, seqno);
251638962489SAdrian Chadd 	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
251738962489SAdrian Chadd 
251838962489SAdrian Chadd 	/*
251938962489SAdrian Chadd 	 * Just warn for now; if it happens then we should find out
252038962489SAdrian Chadd 	 * about it. It's highly likely the aggregation session will
252138962489SAdrian Chadd 	 * soon hang.
252238962489SAdrian Chadd 	 */
252338962489SAdrian Chadd 	if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) {
252438962489SAdrian Chadd 		device_printf(sc->sc_dev, "%s: retransmitted buffer"
252538962489SAdrian Chadd 		    " has mismatching seqno's, BA session may hang.\n",
252638962489SAdrian Chadd 		    __func__);
252738962489SAdrian Chadd 		device_printf(sc->sc_dev, "%s: old seqno=%d, new_seqno=%d\n",
252838962489SAdrian Chadd 		    __func__,
252938962489SAdrian Chadd 		    old_bf->bf_state.bfs_seqno,
253038962489SAdrian Chadd 		    new_bf->bf_state.bfs_seqno);
253138962489SAdrian Chadd 	}
253238962489SAdrian Chadd 
253338962489SAdrian Chadd 	if (tid->tx_buf[cindex] != old_bf) {
253438962489SAdrian Chadd 		device_printf(sc->sc_dev, "%s: ath_buf pointer incorrect; "
253538962489SAdrian Chadd 		    " has m BA session may hang.\n",
253638962489SAdrian Chadd 		    __func__);
253738962489SAdrian Chadd 		device_printf(sc->sc_dev, "%s: old bf=%p, new bf=%p\n",
253838962489SAdrian Chadd 		    __func__,
253938962489SAdrian Chadd 		    old_bf, new_bf);
254038962489SAdrian Chadd 	}
254138962489SAdrian Chadd 
254238962489SAdrian Chadd 	tid->tx_buf[cindex] = new_bf;
254338962489SAdrian Chadd }
254438962489SAdrian Chadd 
254538962489SAdrian Chadd /*
2546eb6f0de0SAdrian Chadd  * seq_start - left edge of BAW
2547eb6f0de0SAdrian Chadd  * seq_next - current/next sequence number to allocate
2548eb6f0de0SAdrian Chadd  *
2549eb6f0de0SAdrian Chadd  * Since the BAW status may be modified by both the ath task and
2550eb6f0de0SAdrian Chadd  * the net80211/ifnet contexts, the TID must be locked.
2551eb6f0de0SAdrian Chadd  */
2552eb6f0de0SAdrian Chadd static void
2553eb6f0de0SAdrian Chadd ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an,
2554eb6f0de0SAdrian Chadd     struct ath_tid *tid, const struct ath_buf *bf)
2555eb6f0de0SAdrian Chadd {
2556eb6f0de0SAdrian Chadd 	int index, cindex;
2557eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
2558eb6f0de0SAdrian Chadd 	int seqno = SEQNO(bf->bf_state.bfs_seqno);
2559eb6f0de0SAdrian Chadd 
2560375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
2561eb6f0de0SAdrian Chadd 
2562eb6f0de0SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid->tid);
2563eb6f0de0SAdrian Chadd 	index  = ATH_BA_INDEX(tap->txa_start, seqno);
2564eb6f0de0SAdrian Chadd 	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2565eb6f0de0SAdrian Chadd 
2566eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2567a108d2d6SAdrian Chadd 	    "%s: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, "
2568d4365d16SAdrian Chadd 	    "baw head=%d, tail=%d\n",
2569a108d2d6SAdrian Chadd 	    __func__, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index,
2570eb6f0de0SAdrian Chadd 	    cindex, tid->baw_head, tid->baw_tail);
2571eb6f0de0SAdrian Chadd 
2572eb6f0de0SAdrian Chadd 	/*
2573eb6f0de0SAdrian Chadd 	 * If this occurs then we have a big problem - something else
2574eb6f0de0SAdrian Chadd 	 * has slid tap->txa_start along without updating the BAW
2575eb6f0de0SAdrian Chadd 	 * tracking start/end pointers. Thus the TX BAW state is now
2576eb6f0de0SAdrian Chadd 	 * completely busted.
2577eb6f0de0SAdrian Chadd 	 *
2578eb6f0de0SAdrian Chadd 	 * But for now, since I haven't yet fixed TDMA and buffer cloning,
2579eb6f0de0SAdrian Chadd 	 * it's quite possible that a cloned buffer is making its way
2580eb6f0de0SAdrian Chadd 	 * here and causing it to fire off. Disable TDMA for now.
2581eb6f0de0SAdrian Chadd 	 */
2582eb6f0de0SAdrian Chadd 	if (tid->tx_buf[cindex] != bf) {
2583eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev,
2584eb6f0de0SAdrian Chadd 		    "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n",
2585eb6f0de0SAdrian Chadd 		    __func__,
2586eb6f0de0SAdrian Chadd 		    bf, SEQNO(bf->bf_state.bfs_seqno),
2587eb6f0de0SAdrian Chadd 		    tid->tx_buf[cindex],
2588eb6f0de0SAdrian Chadd 		    SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno));
2589eb6f0de0SAdrian Chadd 	}
2590eb6f0de0SAdrian Chadd 
2591eb6f0de0SAdrian Chadd 	tid->tx_buf[cindex] = NULL;
2592eb6f0de0SAdrian Chadd 
2593d4365d16SAdrian Chadd 	while (tid->baw_head != tid->baw_tail &&
2594d4365d16SAdrian Chadd 	    !tid->tx_buf[tid->baw_head]) {
2595eb6f0de0SAdrian Chadd 		INCR(tap->txa_start, IEEE80211_SEQ_RANGE);
2596eb6f0de0SAdrian Chadd 		INCR(tid->baw_head, ATH_TID_MAX_BUFS);
2597eb6f0de0SAdrian Chadd 	}
2598d4365d16SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2599d4365d16SAdrian Chadd 	    "%s: baw is now %d:%d, baw head=%d\n",
2600eb6f0de0SAdrian Chadd 	    __func__, tap->txa_start, tap->txa_wnd, tid->baw_head);
2601eb6f0de0SAdrian Chadd }
2602eb6f0de0SAdrian Chadd 
2603eb6f0de0SAdrian Chadd /*
2604eb6f0de0SAdrian Chadd  * Mark the current node/TID as ready to TX.
2605eb6f0de0SAdrian Chadd  *
2606eb6f0de0SAdrian Chadd  * This is done to make it easy for the software scheduler to
2607eb6f0de0SAdrian Chadd  * find which nodes have data to send.
2608eb6f0de0SAdrian Chadd  *
2609eb6f0de0SAdrian Chadd  * The TXQ lock must be held.
2610eb6f0de0SAdrian Chadd  */
2611eb6f0de0SAdrian Chadd static void
2612eb6f0de0SAdrian Chadd ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid)
2613eb6f0de0SAdrian Chadd {
2614eb6f0de0SAdrian Chadd 	struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2615eb6f0de0SAdrian Chadd 
2616375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
2617eb6f0de0SAdrian Chadd 
2618eb6f0de0SAdrian Chadd 	if (tid->paused)
2619eb6f0de0SAdrian Chadd 		return;		/* paused, can't schedule yet */
2620eb6f0de0SAdrian Chadd 
2621eb6f0de0SAdrian Chadd 	if (tid->sched)
2622eb6f0de0SAdrian Chadd 		return;		/* already scheduled */
2623eb6f0de0SAdrian Chadd 
2624eb6f0de0SAdrian Chadd 	tid->sched = 1;
2625eb6f0de0SAdrian Chadd 
2626eb6f0de0SAdrian Chadd 	TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem);
2627eb6f0de0SAdrian Chadd }
2628eb6f0de0SAdrian Chadd 
2629eb6f0de0SAdrian Chadd /*
2630eb6f0de0SAdrian Chadd  * Mark the current node as no longer needing to be polled for
2631eb6f0de0SAdrian Chadd  * TX packets.
2632eb6f0de0SAdrian Chadd  *
2633eb6f0de0SAdrian Chadd  * The TXQ lock must be held.
2634eb6f0de0SAdrian Chadd  */
2635eb6f0de0SAdrian Chadd static void
2636eb6f0de0SAdrian Chadd ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid)
2637eb6f0de0SAdrian Chadd {
2638eb6f0de0SAdrian Chadd 	struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2639eb6f0de0SAdrian Chadd 
2640375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
2641eb6f0de0SAdrian Chadd 
2642eb6f0de0SAdrian Chadd 	if (tid->sched == 0)
2643eb6f0de0SAdrian Chadd 		return;
2644eb6f0de0SAdrian Chadd 
2645eb6f0de0SAdrian Chadd 	tid->sched = 0;
2646eb6f0de0SAdrian Chadd 	TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem);
2647eb6f0de0SAdrian Chadd }
2648eb6f0de0SAdrian Chadd 
2649eb6f0de0SAdrian Chadd /*
2650eb6f0de0SAdrian Chadd  * Assign a sequence number manually to the given frame.
2651eb6f0de0SAdrian Chadd  *
2652eb6f0de0SAdrian Chadd  * This should only be called for A-MPDU TX frames.
2653eb6f0de0SAdrian Chadd  */
2654a108d2d6SAdrian Chadd static ieee80211_seq
2655eb6f0de0SAdrian Chadd ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni,
2656eb6f0de0SAdrian Chadd     struct ath_buf *bf, struct mbuf *m0)
2657eb6f0de0SAdrian Chadd {
2658eb6f0de0SAdrian Chadd 	struct ieee80211_frame *wh;
2659eb6f0de0SAdrian Chadd 	int tid, pri;
2660eb6f0de0SAdrian Chadd 	ieee80211_seq seqno;
2661eb6f0de0SAdrian Chadd 	uint8_t subtype;
2662eb6f0de0SAdrian Chadd 
2663eb6f0de0SAdrian Chadd 	/* TID lookup */
2664eb6f0de0SAdrian Chadd 	wh = mtod(m0, struct ieee80211_frame *);
2665eb6f0de0SAdrian Chadd 	pri = M_WME_GETAC(m0);			/* honor classification */
2666eb6f0de0SAdrian Chadd 	tid = WME_AC_TO_TID(pri);
2667a108d2d6SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pri=%d, tid=%d, qos has seq=%d\n",
2668a108d2d6SAdrian Chadd 	    __func__, pri, tid, IEEE80211_QOS_HAS_SEQ(wh));
2669eb6f0de0SAdrian Chadd 
2670eb6f0de0SAdrian Chadd 	/* XXX Is it a control frame? Ignore */
2671eb6f0de0SAdrian Chadd 
2672eb6f0de0SAdrian Chadd 	/* Does the packet require a sequence number? */
2673eb6f0de0SAdrian Chadd 	if (! IEEE80211_QOS_HAS_SEQ(wh))
2674eb6f0de0SAdrian Chadd 		return -1;
2675eb6f0de0SAdrian Chadd 
2676375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
26777561cb5cSAdrian Chadd 
2678eb6f0de0SAdrian Chadd 	/*
2679eb6f0de0SAdrian Chadd 	 * Is it a QOS NULL Data frame? Give it a sequence number from
2680eb6f0de0SAdrian Chadd 	 * the default TID (IEEE80211_NONQOS_TID.)
2681eb6f0de0SAdrian Chadd 	 *
2682eb6f0de0SAdrian Chadd 	 * The RX path of everything I've looked at doesn't include the NULL
2683eb6f0de0SAdrian Chadd 	 * data frame sequence number in the aggregation state updates, so
2684eb6f0de0SAdrian Chadd 	 * assigning it a sequence number there will cause a BAW hole on the
2685eb6f0de0SAdrian Chadd 	 * RX side.
2686eb6f0de0SAdrian Chadd 	 */
2687eb6f0de0SAdrian Chadd 	subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
2688eb6f0de0SAdrian Chadd 	if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) {
26897561cb5cSAdrian Chadd 		/* XXX no locking for this TID? This is a bit of a problem. */
2690eb6f0de0SAdrian Chadd 		seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID];
2691eb6f0de0SAdrian Chadd 		INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE);
2692eb6f0de0SAdrian Chadd 	} else {
2693eb6f0de0SAdrian Chadd 		/* Manually assign sequence number */
2694eb6f0de0SAdrian Chadd 		seqno = ni->ni_txseqs[tid];
2695eb6f0de0SAdrian Chadd 		INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE);
2696eb6f0de0SAdrian Chadd 	}
2697eb6f0de0SAdrian Chadd 	*(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
2698eb6f0de0SAdrian Chadd 	M_SEQNO_SET(m0, seqno);
2699eb6f0de0SAdrian Chadd 
2700eb6f0de0SAdrian Chadd 	/* Return so caller can do something with it if needed */
2701a108d2d6SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s:  -> seqno=%d\n", __func__, seqno);
2702eb6f0de0SAdrian Chadd 	return seqno;
2703eb6f0de0SAdrian Chadd }
2704eb6f0de0SAdrian Chadd 
2705eb6f0de0SAdrian Chadd /*
2706eb6f0de0SAdrian Chadd  * Attempt to direct dispatch an aggregate frame to hardware.
2707eb6f0de0SAdrian Chadd  * If the frame is out of BAW, queue.
2708eb6f0de0SAdrian Chadd  * Otherwise, schedule it as a single frame.
2709eb6f0de0SAdrian Chadd  */
2710eb6f0de0SAdrian Chadd static void
271146634305SAdrian Chadd ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an,
271246634305SAdrian Chadd     struct ath_txq *txq, struct ath_buf *bf)
2713eb6f0de0SAdrian Chadd {
2714eb6f0de0SAdrian Chadd 	struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid];
2715eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
2716eb6f0de0SAdrian Chadd 
2717375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
2718eb6f0de0SAdrian Chadd 
2719eb6f0de0SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid->tid);
2720eb6f0de0SAdrian Chadd 
2721eb6f0de0SAdrian Chadd 	/* paused? queue */
2722eb6f0de0SAdrian Chadd 	if (tid->paused) {
27233e6cc97fSAdrian Chadd 		ATH_TID_INSERT_HEAD(tid, bf, bf_list);
27240f04c5a2SAdrian Chadd 		/* XXX don't sched - we're paused! */
2725eb6f0de0SAdrian Chadd 		return;
2726eb6f0de0SAdrian Chadd 	}
2727eb6f0de0SAdrian Chadd 
2728eb6f0de0SAdrian Chadd 	/* outside baw? queue */
2729eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_dobaw &&
2730eb6f0de0SAdrian Chadd 	    (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
2731eb6f0de0SAdrian Chadd 	    SEQNO(bf->bf_state.bfs_seqno)))) {
27323e6cc97fSAdrian Chadd 		ATH_TID_INSERT_HEAD(tid, bf, bf_list);
2733eb6f0de0SAdrian Chadd 		ath_tx_tid_sched(sc, tid);
2734eb6f0de0SAdrian Chadd 		return;
2735eb6f0de0SAdrian Chadd 	}
2736eb6f0de0SAdrian Chadd 
27372a9f83afSAdrian Chadd 	/*
27382a9f83afSAdrian Chadd 	 * This is a temporary check and should be removed once
27392a9f83afSAdrian Chadd 	 * all the relevant code paths have been fixed.
27402a9f83afSAdrian Chadd 	 *
27412a9f83afSAdrian Chadd 	 * During aggregate retries, it's possible that the head
27422a9f83afSAdrian Chadd 	 * frame will fail (which has the bfs_aggr and bfs_nframes
27432a9f83afSAdrian Chadd 	 * fields set for said aggregate) and will be retried as
27442a9f83afSAdrian Chadd 	 * a single frame.  In this instance, the values should
27452a9f83afSAdrian Chadd 	 * be reset or the completion code will get upset with you.
27462a9f83afSAdrian Chadd 	 */
27472a9f83afSAdrian Chadd 	if (bf->bf_state.bfs_aggr != 0 || bf->bf_state.bfs_nframes > 1) {
27482a9f83afSAdrian Chadd 		device_printf(sc->sc_dev, "%s: bfs_aggr=%d, bfs_nframes=%d\n",
27492a9f83afSAdrian Chadd 		    __func__,
27502a9f83afSAdrian Chadd 		    bf->bf_state.bfs_aggr,
27512a9f83afSAdrian Chadd 		    bf->bf_state.bfs_nframes);
27522a9f83afSAdrian Chadd 		bf->bf_state.bfs_aggr = 0;
27532a9f83afSAdrian Chadd 		bf->bf_state.bfs_nframes = 1;
27542a9f83afSAdrian Chadd 	}
27552a9f83afSAdrian Chadd 
27564e81f27cSAdrian Chadd 	/* Update CLRDMASK just before this frame is queued */
27574e81f27cSAdrian Chadd 	ath_tx_update_clrdmask(sc, tid, bf);
27584e81f27cSAdrian Chadd 
2759eb6f0de0SAdrian Chadd 	/* Direct dispatch to hardware */
2760eb6f0de0SAdrian Chadd 	ath_tx_do_ratelookup(sc, bf);
2761e2e4a2c2SAdrian Chadd 	ath_tx_calc_duration(sc, bf);
2762e2e4a2c2SAdrian Chadd 	ath_tx_calc_protection(sc, bf);
2763eb6f0de0SAdrian Chadd 	ath_tx_set_rtscts(sc, bf);
2764e2e4a2c2SAdrian Chadd 	ath_tx_rate_fill_rcflags(sc, bf);
2765eb6f0de0SAdrian Chadd 	ath_tx_setds(sc, bf);
2766eb6f0de0SAdrian Chadd 
2767eb6f0de0SAdrian Chadd 	/* Statistics */
2768eb6f0de0SAdrian Chadd 	sc->sc_aggr_stats.aggr_low_hwq_single_pkt++;
2769eb6f0de0SAdrian Chadd 
2770eb6f0de0SAdrian Chadd 	/* Track per-TID hardware queue depth correctly */
2771eb6f0de0SAdrian Chadd 	tid->hwq_depth++;
2772eb6f0de0SAdrian Chadd 
2773eb6f0de0SAdrian Chadd 	/* Add to BAW */
2774eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_dobaw) {
2775eb6f0de0SAdrian Chadd 		ath_tx_addto_baw(sc, an, tid, bf);
2776eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_addedbaw = 1;
2777eb6f0de0SAdrian Chadd 	}
2778eb6f0de0SAdrian Chadd 
2779eb6f0de0SAdrian Chadd 	/* Set completion handler, multi-frame aggregate or not */
2780eb6f0de0SAdrian Chadd 	bf->bf_comp = ath_tx_aggr_comp;
2781eb6f0de0SAdrian Chadd 
2782eb6f0de0SAdrian Chadd 	/* Hand off to hardware */
2783eb6f0de0SAdrian Chadd 	ath_tx_handoff(sc, txq, bf);
2784eb6f0de0SAdrian Chadd }
2785eb6f0de0SAdrian Chadd 
2786eb6f0de0SAdrian Chadd /*
2787eb6f0de0SAdrian Chadd  * Attempt to send the packet.
2788eb6f0de0SAdrian Chadd  * If the queue isn't busy, direct-dispatch.
2789eb6f0de0SAdrian Chadd  * If the queue is busy enough, queue the given packet on the
2790eb6f0de0SAdrian Chadd  *  relevant software queue.
2791eb6f0de0SAdrian Chadd  */
2792eb6f0de0SAdrian Chadd void
2793eb6f0de0SAdrian Chadd ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_txq *txq,
2794eb6f0de0SAdrian Chadd     struct ath_buf *bf)
2795eb6f0de0SAdrian Chadd {
2796eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
2797eb6f0de0SAdrian Chadd 	struct ieee80211_frame *wh;
2798eb6f0de0SAdrian Chadd 	struct ath_tid *atid;
2799eb6f0de0SAdrian Chadd 	int pri, tid;
2800eb6f0de0SAdrian Chadd 	struct mbuf *m0 = bf->bf_m;
2801eb6f0de0SAdrian Chadd 
2802375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
28037561cb5cSAdrian Chadd 
2804eb6f0de0SAdrian Chadd 	/* Fetch the TID - non-QoS frames get assigned to TID 16 */
2805eb6f0de0SAdrian Chadd 	wh = mtod(m0, struct ieee80211_frame *);
2806eb6f0de0SAdrian Chadd 	pri = ath_tx_getac(sc, m0);
2807eb6f0de0SAdrian Chadd 	tid = ath_tx_gettid(sc, m0);
2808eb6f0de0SAdrian Chadd 	atid = &an->an_tid[tid];
2809eb6f0de0SAdrian Chadd 
2810a108d2d6SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d\n",
2811a108d2d6SAdrian Chadd 	    __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh));
2812eb6f0de0SAdrian Chadd 
2813eb6f0de0SAdrian Chadd 	/* Set local packet state, used to queue packets to hardware */
281446634305SAdrian Chadd 	/* XXX potentially duplicate info, re-check */
2815eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_tid = tid;
2816fc56c9c5SAdrian Chadd 	bf->bf_state.bfs_tx_queue = txq->axq_qnum;
2817eb6f0de0SAdrian Chadd 	bf->bf_state.bfs_pri = pri;
2818eb6f0de0SAdrian Chadd 
2819eb6f0de0SAdrian Chadd 	/*
2820eb6f0de0SAdrian Chadd 	 * If the hardware queue isn't busy, queue it directly.
2821eb6f0de0SAdrian Chadd 	 * If the hardware queue is busy, queue it.
2822eb6f0de0SAdrian Chadd 	 * If the TID is paused or the traffic it outside BAW, software
2823eb6f0de0SAdrian Chadd 	 * queue it.
2824eb6f0de0SAdrian Chadd 	 */
2825eb6f0de0SAdrian Chadd 	if (atid->paused) {
2826eb6f0de0SAdrian Chadd 		/* TID is paused, queue */
2827a108d2d6SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: paused\n", __func__);
28283e6cc97fSAdrian Chadd 		ATH_TID_INSERT_TAIL(atid, bf, bf_list);
2829eb6f0de0SAdrian Chadd 	} else if (ath_tx_ampdu_pending(sc, an, tid)) {
2830eb6f0de0SAdrian Chadd 		/* AMPDU pending; queue */
2831a108d2d6SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pending\n", __func__);
28323e6cc97fSAdrian Chadd 		ATH_TID_INSERT_TAIL(atid, bf, bf_list);
2833eb6f0de0SAdrian Chadd 		/* XXX sched? */
2834eb6f0de0SAdrian Chadd 	} else if (ath_tx_ampdu_running(sc, an, tid)) {
2835eb6f0de0SAdrian Chadd 		/* AMPDU running, attempt direct dispatch if possible */
283639f24578SAdrian Chadd 
283739f24578SAdrian Chadd 		/*
283839f24578SAdrian Chadd 		 * Always queue the frame to the tail of the list.
283939f24578SAdrian Chadd 		 */
28403e6cc97fSAdrian Chadd 		ATH_TID_INSERT_TAIL(atid, bf, bf_list);
284139f24578SAdrian Chadd 
284239f24578SAdrian Chadd 		/*
284339f24578SAdrian Chadd 		 * If the hardware queue isn't busy, direct dispatch
284439f24578SAdrian Chadd 		 * the head frame in the list.  Don't schedule the
284539f24578SAdrian Chadd 		 * TID - let it build some more frames first?
284639f24578SAdrian Chadd 		 *
284739f24578SAdrian Chadd 		 * Otherwise, schedule the TID.
284839f24578SAdrian Chadd 		 */
2849d4365d16SAdrian Chadd 		if (txq->axq_depth < sc->sc_hwq_limit) {
28503e6cc97fSAdrian Chadd 			bf = ATH_TID_FIRST(atid);
28513e6cc97fSAdrian Chadd 			ATH_TID_REMOVE(atid, bf, bf_list);
28522a9f83afSAdrian Chadd 
28532a9f83afSAdrian Chadd 			/*
28542a9f83afSAdrian Chadd 			 * Ensure it's definitely treated as a non-AMPDU
28552a9f83afSAdrian Chadd 			 * frame - this information may have been left
28562a9f83afSAdrian Chadd 			 * over from a previous attempt.
28572a9f83afSAdrian Chadd 			 */
28582a9f83afSAdrian Chadd 			bf->bf_state.bfs_aggr = 0;
28592a9f83afSAdrian Chadd 			bf->bf_state.bfs_nframes = 1;
28602a9f83afSAdrian Chadd 
28612a9f83afSAdrian Chadd 			/* Queue to the hardware */
286246634305SAdrian Chadd 			ath_tx_xmit_aggr(sc, an, txq, bf);
2863a108d2d6SAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_SW_TX,
2864a108d2d6SAdrian Chadd 			    "%s: xmit_aggr\n",
2865a108d2d6SAdrian Chadd 			    __func__);
2866d4365d16SAdrian Chadd 		} else {
2867d4365d16SAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_SW_TX,
2868a108d2d6SAdrian Chadd 			    "%s: ampdu; swq'ing\n",
2869a108d2d6SAdrian Chadd 			    __func__);
287003682514SAdrian Chadd 
2871eb6f0de0SAdrian Chadd 			ath_tx_tid_sched(sc, atid);
2872eb6f0de0SAdrian Chadd 		}
2873eb6f0de0SAdrian Chadd 	} else if (txq->axq_depth < sc->sc_hwq_limit) {
2874eb6f0de0SAdrian Chadd 		/* AMPDU not running, attempt direct dispatch */
2875a108d2d6SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: xmit_normal\n", __func__);
28760a544719SAdrian Chadd 		/* See if clrdmask needs to be set */
28770a544719SAdrian Chadd 		ath_tx_update_clrdmask(sc, atid, bf);
2878eb6f0de0SAdrian Chadd 		ath_tx_xmit_normal(sc, txq, bf);
2879eb6f0de0SAdrian Chadd 	} else {
2880eb6f0de0SAdrian Chadd 		/* Busy; queue */
2881a108d2d6SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: swq'ing\n", __func__);
28823e6cc97fSAdrian Chadd 		ATH_TID_INSERT_TAIL(atid, bf, bf_list);
2883eb6f0de0SAdrian Chadd 		ath_tx_tid_sched(sc, atid);
2884eb6f0de0SAdrian Chadd 	}
2885eb6f0de0SAdrian Chadd }
2886eb6f0de0SAdrian Chadd 
2887eb6f0de0SAdrian Chadd /*
28884f25ddbbSAdrian Chadd  * Only set the clrdmask bit if none of the nodes are currently
28894f25ddbbSAdrian Chadd  * filtered.
28904f25ddbbSAdrian Chadd  *
28914f25ddbbSAdrian Chadd  * XXX TODO: go through all the callers and check to see
28924f25ddbbSAdrian Chadd  * which are being called in the context of looping over all
28934f25ddbbSAdrian Chadd  * TIDs (eg, if all tids are being paused, resumed, etc.)
28944f25ddbbSAdrian Chadd  * That'll avoid O(n^2) complexity here.
28954f25ddbbSAdrian Chadd  */
28964f25ddbbSAdrian Chadd static void
28974f25ddbbSAdrian Chadd ath_tx_set_clrdmask(struct ath_softc *sc, struct ath_node *an)
28984f25ddbbSAdrian Chadd {
28994f25ddbbSAdrian Chadd 	int i;
29004f25ddbbSAdrian Chadd 
29014f25ddbbSAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
29024f25ddbbSAdrian Chadd 
29034f25ddbbSAdrian Chadd 	for (i = 0; i < IEEE80211_TID_SIZE; i++) {
29044f25ddbbSAdrian Chadd 		if (an->an_tid[i].isfiltered == 1)
2905f74d878fSAdrian Chadd 			return;
29064f25ddbbSAdrian Chadd 	}
29074f25ddbbSAdrian Chadd 	an->clrdmask = 1;
29084f25ddbbSAdrian Chadd }
29094f25ddbbSAdrian Chadd 
29104f25ddbbSAdrian Chadd /*
2911eb6f0de0SAdrian Chadd  * Configure the per-TID node state.
2912eb6f0de0SAdrian Chadd  *
2913eb6f0de0SAdrian Chadd  * This likely belongs in if_ath_node.c but I can't think of anywhere
2914eb6f0de0SAdrian Chadd  * else to put it just yet.
2915eb6f0de0SAdrian Chadd  *
2916eb6f0de0SAdrian Chadd  * This sets up the SLISTs and the mutex as appropriate.
2917eb6f0de0SAdrian Chadd  */
2918eb6f0de0SAdrian Chadd void
2919eb6f0de0SAdrian Chadd ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an)
2920eb6f0de0SAdrian Chadd {
2921eb6f0de0SAdrian Chadd 	int i, j;
2922eb6f0de0SAdrian Chadd 	struct ath_tid *atid;
2923eb6f0de0SAdrian Chadd 
2924eb6f0de0SAdrian Chadd 	for (i = 0; i < IEEE80211_TID_SIZE; i++) {
2925eb6f0de0SAdrian Chadd 		atid = &an->an_tid[i];
2926f1bc738eSAdrian Chadd 
2927f1bc738eSAdrian Chadd 		/* XXX now with this bzer(), is the field 0'ing needed? */
2928f1bc738eSAdrian Chadd 		bzero(atid, sizeof(*atid));
2929f1bc738eSAdrian Chadd 
29303e6cc97fSAdrian Chadd 		TAILQ_INIT(&atid->tid_q);
29313e6cc97fSAdrian Chadd 		TAILQ_INIT(&atid->filtq.tid_q);
2932eb6f0de0SAdrian Chadd 		atid->tid = i;
2933eb6f0de0SAdrian Chadd 		atid->an = an;
2934eb6f0de0SAdrian Chadd 		for (j = 0; j < ATH_TID_MAX_BUFS; j++)
2935eb6f0de0SAdrian Chadd 			atid->tx_buf[j] = NULL;
2936eb6f0de0SAdrian Chadd 		atid->baw_head = atid->baw_tail = 0;
2937eb6f0de0SAdrian Chadd 		atid->paused = 0;
2938eb6f0de0SAdrian Chadd 		atid->sched = 0;
2939eb6f0de0SAdrian Chadd 		atid->hwq_depth = 0;
2940eb6f0de0SAdrian Chadd 		atid->cleanup_inprogress = 0;
2941eb6f0de0SAdrian Chadd 		if (i == IEEE80211_NONQOS_TID)
29427403d1b9SAdrian Chadd 			atid->ac = ATH_NONQOS_TID_AC;
2943eb6f0de0SAdrian Chadd 		else
2944eb6f0de0SAdrian Chadd 			atid->ac = TID_TO_WME_AC(i);
2945eb6f0de0SAdrian Chadd 	}
29464f25ddbbSAdrian Chadd 	an->clrdmask = 1;	/* Always start by setting this bit */
2947eb6f0de0SAdrian Chadd }
2948eb6f0de0SAdrian Chadd 
2949eb6f0de0SAdrian Chadd /*
2950eb6f0de0SAdrian Chadd  * Pause the current TID. This stops packets from being transmitted
2951eb6f0de0SAdrian Chadd  * on it.
2952eb6f0de0SAdrian Chadd  *
2953eb6f0de0SAdrian Chadd  * Since this is also called from upper layers as well as the driver,
2954eb6f0de0SAdrian Chadd  * it will get the TID lock.
2955eb6f0de0SAdrian Chadd  */
2956eb6f0de0SAdrian Chadd static void
2957eb6f0de0SAdrian Chadd ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid)
2958eb6f0de0SAdrian Chadd {
295988b3d483SAdrian Chadd 
2960375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
2961eb6f0de0SAdrian Chadd 	tid->paused++;
2962eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n",
2963eb6f0de0SAdrian Chadd 	    __func__, tid->paused);
2964eb6f0de0SAdrian Chadd }
2965eb6f0de0SAdrian Chadd 
2966eb6f0de0SAdrian Chadd /*
2967eb6f0de0SAdrian Chadd  * Unpause the current TID, and schedule it if needed.
2968eb6f0de0SAdrian Chadd  */
2969eb6f0de0SAdrian Chadd static void
2970eb6f0de0SAdrian Chadd ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid)
2971eb6f0de0SAdrian Chadd {
2972375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
2973eb6f0de0SAdrian Chadd 
2974eb6f0de0SAdrian Chadd 	tid->paused--;
2975eb6f0de0SAdrian Chadd 
2976eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n",
2977eb6f0de0SAdrian Chadd 	    __func__, tid->paused);
2978eb6f0de0SAdrian Chadd 
29790eb81626SAdrian Chadd 	if (tid->paused)
2980eb6f0de0SAdrian Chadd 		return;
29810eb81626SAdrian Chadd 
29820eb81626SAdrian Chadd 	/*
29830eb81626SAdrian Chadd 	 * Override the clrdmask configuration for the next frame
29840eb81626SAdrian Chadd 	 * from this TID, just to get the ball rolling.
29850eb81626SAdrian Chadd 	 */
29864f25ddbbSAdrian Chadd 	ath_tx_set_clrdmask(sc, tid->an);
29870eb81626SAdrian Chadd 
29880eb81626SAdrian Chadd 	if (tid->axq_depth == 0)
29890eb81626SAdrian Chadd 		return;
2990eb6f0de0SAdrian Chadd 
2991f1bc738eSAdrian Chadd 	/* XXX isfiltered shouldn't ever be 0 at this point */
2992f1bc738eSAdrian Chadd 	if (tid->isfiltered == 1) {
2993f1bc738eSAdrian Chadd 		device_printf(sc->sc_dev, "%s: filtered?!\n", __func__);
2994f1bc738eSAdrian Chadd 		return;
2995f1bc738eSAdrian Chadd 	}
2996f1bc738eSAdrian Chadd 
2997eb6f0de0SAdrian Chadd 	ath_tx_tid_sched(sc, tid);
299821bca442SAdrian Chadd 
299921bca442SAdrian Chadd 	/*
300021bca442SAdrian Chadd 	 * Queue the software TX scheduler.
300121bca442SAdrian Chadd 	 */
300221bca442SAdrian Chadd 	ath_tx_swq_kick(sc);
3003eb6f0de0SAdrian Chadd }
3004eb6f0de0SAdrian Chadd 
3005eb6f0de0SAdrian Chadd /*
3006f1bc738eSAdrian Chadd  * Add the given ath_buf to the TID filtered frame list.
3007f1bc738eSAdrian Chadd  * This requires the TID be filtered.
3008f1bc738eSAdrian Chadd  */
3009f1bc738eSAdrian Chadd static void
3010f1bc738eSAdrian Chadd ath_tx_tid_filt_addbuf(struct ath_softc *sc, struct ath_tid *tid,
3011f1bc738eSAdrian Chadd     struct ath_buf *bf)
3012f1bc738eSAdrian Chadd {
3013f1bc738eSAdrian Chadd 
3014375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
3015375307d4SAdrian Chadd 
3016f1bc738eSAdrian Chadd 	if (! tid->isfiltered)
3017f1bc738eSAdrian Chadd 		device_printf(sc->sc_dev, "%s: not filtered?!\n", __func__);
3018f1bc738eSAdrian Chadd 
3019f1bc738eSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: bf=%p\n", __func__, bf);
3020f1bc738eSAdrian Chadd 
3021f1bc738eSAdrian Chadd 	/* Set the retry bit and bump the retry counter */
3022f1bc738eSAdrian Chadd 	ath_tx_set_retry(sc, bf);
3023f1bc738eSAdrian Chadd 	sc->sc_stats.ast_tx_swfiltered++;
3024f1bc738eSAdrian Chadd 
302513aa9ee5SAdrian Chadd 	ATH_TID_FILT_INSERT_TAIL(tid, bf, bf_list);
3026f1bc738eSAdrian Chadd }
3027f1bc738eSAdrian Chadd 
3028f1bc738eSAdrian Chadd /*
3029f1bc738eSAdrian Chadd  * Handle a completed filtered frame from the given TID.
3030f1bc738eSAdrian Chadd  * This just enables/pauses the filtered frame state if required
3031f1bc738eSAdrian Chadd  * and appends the filtered frame to the filtered queue.
3032f1bc738eSAdrian Chadd  */
3033f1bc738eSAdrian Chadd static void
3034f1bc738eSAdrian Chadd ath_tx_tid_filt_comp_buf(struct ath_softc *sc, struct ath_tid *tid,
3035f1bc738eSAdrian Chadd     struct ath_buf *bf)
3036f1bc738eSAdrian Chadd {
3037f1bc738eSAdrian Chadd 
3038375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
3039f1bc738eSAdrian Chadd 
3040f1bc738eSAdrian Chadd 	if (! tid->isfiltered) {
3041f1bc738eSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: filter transition\n",
3042f1bc738eSAdrian Chadd 		    __func__);
3043f1bc738eSAdrian Chadd 		tid->isfiltered = 1;
3044f1bc738eSAdrian Chadd 		ath_tx_tid_pause(sc, tid);
3045f1bc738eSAdrian Chadd 	}
3046f1bc738eSAdrian Chadd 
3047f1bc738eSAdrian Chadd 	/* Add the frame to the filter queue */
3048f1bc738eSAdrian Chadd 	ath_tx_tid_filt_addbuf(sc, tid, bf);
3049f1bc738eSAdrian Chadd }
3050f1bc738eSAdrian Chadd 
3051f1bc738eSAdrian Chadd /*
3052f1bc738eSAdrian Chadd  * Complete the filtered frame TX completion.
3053f1bc738eSAdrian Chadd  *
3054f1bc738eSAdrian Chadd  * If there are no more frames in the hardware queue, unpause/unfilter
3055f1bc738eSAdrian Chadd  * the TID if applicable.  Otherwise we will wait for a node PS transition
3056f1bc738eSAdrian Chadd  * to unfilter.
3057f1bc738eSAdrian Chadd  */
3058f1bc738eSAdrian Chadd static void
3059f1bc738eSAdrian Chadd ath_tx_tid_filt_comp_complete(struct ath_softc *sc, struct ath_tid *tid)
3060f1bc738eSAdrian Chadd {
3061f1bc738eSAdrian Chadd 	struct ath_buf *bf;
3062f1bc738eSAdrian Chadd 
3063375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
3064f1bc738eSAdrian Chadd 
3065f1bc738eSAdrian Chadd 	if (tid->hwq_depth != 0)
3066f1bc738eSAdrian Chadd 		return;
3067f1bc738eSAdrian Chadd 
3068f1bc738eSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: hwq=0, transition back\n",
3069f1bc738eSAdrian Chadd 	    __func__);
3070f1bc738eSAdrian Chadd 	tid->isfiltered = 0;
30714f25ddbbSAdrian Chadd 	/* XXX ath_tx_tid_resume() also calls ath_tx_set_clrdmask()! */
30724f25ddbbSAdrian Chadd 	ath_tx_set_clrdmask(sc, tid->an);
3073f1bc738eSAdrian Chadd 
3074f1bc738eSAdrian Chadd 	/* XXX this is really quite inefficient */
307513aa9ee5SAdrian Chadd 	while ((bf = ATH_TID_FILT_LAST(tid, ath_bufhead_s)) != NULL) {
307613aa9ee5SAdrian Chadd 		ATH_TID_FILT_REMOVE(tid, bf, bf_list);
30773e6cc97fSAdrian Chadd 		ATH_TID_INSERT_HEAD(tid, bf, bf_list);
3078f1bc738eSAdrian Chadd 	}
3079f1bc738eSAdrian Chadd 
3080f1bc738eSAdrian Chadd 	ath_tx_tid_resume(sc, tid);
3081f1bc738eSAdrian Chadd }
3082f1bc738eSAdrian Chadd 
3083f1bc738eSAdrian Chadd /*
3084f1bc738eSAdrian Chadd  * Called when a single (aggregate or otherwise) frame is completed.
3085f1bc738eSAdrian Chadd  *
3086f1bc738eSAdrian Chadd  * Returns 1 if the buffer could be added to the filtered list
3087f1bc738eSAdrian Chadd  * (cloned or otherwise), 0 if the buffer couldn't be added to the
3088f1bc738eSAdrian Chadd  * filtered list (failed clone; expired retry) and the caller should
3089f1bc738eSAdrian Chadd  * free it and handle it like a failure (eg by sending a BAR.)
3090f1bc738eSAdrian Chadd  */
3091f1bc738eSAdrian Chadd static int
3092f1bc738eSAdrian Chadd ath_tx_tid_filt_comp_single(struct ath_softc *sc, struct ath_tid *tid,
3093f1bc738eSAdrian Chadd     struct ath_buf *bf)
3094f1bc738eSAdrian Chadd {
3095f1bc738eSAdrian Chadd 	struct ath_buf *nbf;
3096f1bc738eSAdrian Chadd 	int retval;
3097f1bc738eSAdrian Chadd 
3098375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
3099f1bc738eSAdrian Chadd 
3100f1bc738eSAdrian Chadd 	/*
3101f1bc738eSAdrian Chadd 	 * Don't allow a filtered frame to live forever.
3102f1bc738eSAdrian Chadd 	 */
3103f1bc738eSAdrian Chadd 	if (bf->bf_state.bfs_retries > SWMAX_RETRIES) {
31040eb81626SAdrian Chadd 		sc->sc_stats.ast_tx_swretrymax++;
3105f1bc738eSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3106f1bc738eSAdrian Chadd 		    "%s: bf=%p, seqno=%d, exceeded retries\n",
3107f1bc738eSAdrian Chadd 		    __func__,
3108f1bc738eSAdrian Chadd 		    bf,
3109f1bc738eSAdrian Chadd 		    bf->bf_state.bfs_seqno);
3110f1bc738eSAdrian Chadd 		return (0);
3111f1bc738eSAdrian Chadd 	}
3112f1bc738eSAdrian Chadd 
3113f1bc738eSAdrian Chadd 	/*
3114f1bc738eSAdrian Chadd 	 * A busy buffer can't be added to the retry list.
3115f1bc738eSAdrian Chadd 	 * It needs to be cloned.
3116f1bc738eSAdrian Chadd 	 */
3117f1bc738eSAdrian Chadd 	if (bf->bf_flags & ATH_BUF_BUSY) {
3118f1bc738eSAdrian Chadd 		nbf = ath_tx_retry_clone(sc, tid->an, tid, bf);
3119f1bc738eSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3120f1bc738eSAdrian Chadd 		    "%s: busy buffer clone: %p -> %p\n",
3121f1bc738eSAdrian Chadd 		    __func__, bf, nbf);
3122f1bc738eSAdrian Chadd 	} else {
3123f1bc738eSAdrian Chadd 		nbf = bf;
3124f1bc738eSAdrian Chadd 	}
3125f1bc738eSAdrian Chadd 
3126f1bc738eSAdrian Chadd 	if (nbf == NULL) {
3127f1bc738eSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3128f1bc738eSAdrian Chadd 		    "%s: busy buffer couldn't be cloned (%p)!\n",
3129f1bc738eSAdrian Chadd 		    __func__, bf);
3130f1bc738eSAdrian Chadd 		retval = 1;
3131f1bc738eSAdrian Chadd 	} else {
3132f1bc738eSAdrian Chadd 		ath_tx_tid_filt_comp_buf(sc, tid, nbf);
3133f1bc738eSAdrian Chadd 		retval = 0;
3134f1bc738eSAdrian Chadd 	}
3135f1bc738eSAdrian Chadd 	ath_tx_tid_filt_comp_complete(sc, tid);
3136f1bc738eSAdrian Chadd 
3137f1bc738eSAdrian Chadd 	return (retval);
3138f1bc738eSAdrian Chadd }
3139f1bc738eSAdrian Chadd 
3140f1bc738eSAdrian Chadd static void
3141f1bc738eSAdrian Chadd ath_tx_tid_filt_comp_aggr(struct ath_softc *sc, struct ath_tid *tid,
3142f1bc738eSAdrian Chadd     struct ath_buf *bf_first, ath_bufhead *bf_q)
3143f1bc738eSAdrian Chadd {
3144f1bc738eSAdrian Chadd 	struct ath_buf *bf, *bf_next, *nbf;
3145f1bc738eSAdrian Chadd 
3146375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
3147f1bc738eSAdrian Chadd 
3148f1bc738eSAdrian Chadd 	bf = bf_first;
3149f1bc738eSAdrian Chadd 	while (bf) {
3150f1bc738eSAdrian Chadd 		bf_next = bf->bf_next;
3151f1bc738eSAdrian Chadd 		bf->bf_next = NULL;	/* Remove it from the aggr list */
3152f1bc738eSAdrian Chadd 
3153f1bc738eSAdrian Chadd 		/*
3154f1bc738eSAdrian Chadd 		 * Don't allow a filtered frame to live forever.
3155f1bc738eSAdrian Chadd 		 */
3156f1bc738eSAdrian Chadd 		if (bf->bf_state.bfs_retries > SWMAX_RETRIES) {
31570eb81626SAdrian Chadd 			sc->sc_stats.ast_tx_swretrymax++;
3158f1bc738eSAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3159f1bc738eSAdrian Chadd 			    "%s: bf=%p, seqno=%d, exceeded retries\n",
3160f1bc738eSAdrian Chadd 			    __func__,
3161f1bc738eSAdrian Chadd 			    bf,
3162f1bc738eSAdrian Chadd 			    bf->bf_state.bfs_seqno);
3163f1bc738eSAdrian Chadd 			TAILQ_INSERT_TAIL(bf_q, bf, bf_list);
3164f1bc738eSAdrian Chadd 			goto next;
3165f1bc738eSAdrian Chadd 		}
3166f1bc738eSAdrian Chadd 
3167f1bc738eSAdrian Chadd 		if (bf->bf_flags & ATH_BUF_BUSY) {
3168f1bc738eSAdrian Chadd 			nbf = ath_tx_retry_clone(sc, tid->an, tid, bf);
3169f1bc738eSAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3170f1bc738eSAdrian Chadd 			    "%s: busy buffer cloned: %p -> %p",
3171f1bc738eSAdrian Chadd 			    __func__, bf, nbf);
3172f1bc738eSAdrian Chadd 		} else {
3173f1bc738eSAdrian Chadd 			nbf = bf;
3174f1bc738eSAdrian Chadd 		}
3175f1bc738eSAdrian Chadd 
3176f1bc738eSAdrian Chadd 		/*
3177f1bc738eSAdrian Chadd 		 * If the buffer couldn't be cloned, add it to bf_q;
3178f1bc738eSAdrian Chadd 		 * the caller will free the buffer(s) as required.
3179f1bc738eSAdrian Chadd 		 */
3180f1bc738eSAdrian Chadd 		if (nbf == NULL) {
3181f1bc738eSAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3182f1bc738eSAdrian Chadd 			    "%s: buffer couldn't be cloned! (%p)\n",
3183f1bc738eSAdrian Chadd 			    __func__, bf);
3184f1bc738eSAdrian Chadd 			TAILQ_INSERT_TAIL(bf_q, bf, bf_list);
3185f1bc738eSAdrian Chadd 		} else {
3186f1bc738eSAdrian Chadd 			ath_tx_tid_filt_comp_buf(sc, tid, nbf);
3187f1bc738eSAdrian Chadd 		}
3188f1bc738eSAdrian Chadd next:
3189f1bc738eSAdrian Chadd 		bf = bf_next;
3190f1bc738eSAdrian Chadd 	}
3191f1bc738eSAdrian Chadd 
3192f1bc738eSAdrian Chadd 	ath_tx_tid_filt_comp_complete(sc, tid);
3193f1bc738eSAdrian Chadd }
3194f1bc738eSAdrian Chadd 
3195f1bc738eSAdrian Chadd /*
319688b3d483SAdrian Chadd  * Suspend the queue because we need to TX a BAR.
319788b3d483SAdrian Chadd  */
319888b3d483SAdrian Chadd static void
319988b3d483SAdrian Chadd ath_tx_tid_bar_suspend(struct ath_softc *sc, struct ath_tid *tid)
320088b3d483SAdrian Chadd {
3201375307d4SAdrian Chadd 
3202375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
320388b3d483SAdrian Chadd 
32040e22ed0eSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3205e60c4fc2SAdrian Chadd 	    "%s: tid=%p, bar_wait=%d, bar_tx=%d, called\n",
320688b3d483SAdrian Chadd 	    __func__,
3207e60c4fc2SAdrian Chadd 	    tid,
3208e60c4fc2SAdrian Chadd 	    tid->bar_wait,
3209e60c4fc2SAdrian Chadd 	    tid->bar_tx);
321088b3d483SAdrian Chadd 
321188b3d483SAdrian Chadd 	/* We shouldn't be called when bar_tx is 1 */
321288b3d483SAdrian Chadd 	if (tid->bar_tx) {
321388b3d483SAdrian Chadd 		device_printf(sc->sc_dev, "%s: bar_tx is 1?!\n",
321488b3d483SAdrian Chadd 		    __func__);
321588b3d483SAdrian Chadd 	}
321688b3d483SAdrian Chadd 
321788b3d483SAdrian Chadd 	/* If we've already been called, just be patient. */
321888b3d483SAdrian Chadd 	if (tid->bar_wait)
321988b3d483SAdrian Chadd 		return;
322088b3d483SAdrian Chadd 
322188b3d483SAdrian Chadd 	/* Wait! */
322288b3d483SAdrian Chadd 	tid->bar_wait = 1;
322388b3d483SAdrian Chadd 
322488b3d483SAdrian Chadd 	/* Only one pause, no matter how many frames fail */
322588b3d483SAdrian Chadd 	ath_tx_tid_pause(sc, tid);
322688b3d483SAdrian Chadd }
322788b3d483SAdrian Chadd 
322888b3d483SAdrian Chadd /*
322988b3d483SAdrian Chadd  * We've finished with BAR handling - either we succeeded or
323088b3d483SAdrian Chadd  * failed. Either way, unsuspend TX.
323188b3d483SAdrian Chadd  */
323288b3d483SAdrian Chadd static void
323388b3d483SAdrian Chadd ath_tx_tid_bar_unsuspend(struct ath_softc *sc, struct ath_tid *tid)
323488b3d483SAdrian Chadd {
3235375307d4SAdrian Chadd 
3236375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
323788b3d483SAdrian Chadd 
32380e22ed0eSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
323988b3d483SAdrian Chadd 	    "%s: tid=%p, called\n",
324088b3d483SAdrian Chadd 	    __func__,
324188b3d483SAdrian Chadd 	    tid);
324288b3d483SAdrian Chadd 
324388b3d483SAdrian Chadd 	if (tid->bar_tx == 0 || tid->bar_wait == 0) {
324488b3d483SAdrian Chadd 		device_printf(sc->sc_dev, "%s: bar_tx=%d, bar_wait=%d: ?\n",
324588b3d483SAdrian Chadd 		    __func__, tid->bar_tx, tid->bar_wait);
324688b3d483SAdrian Chadd 	}
324788b3d483SAdrian Chadd 
324888b3d483SAdrian Chadd 	tid->bar_tx = tid->bar_wait = 0;
324988b3d483SAdrian Chadd 	ath_tx_tid_resume(sc, tid);
325088b3d483SAdrian Chadd }
325188b3d483SAdrian Chadd 
325288b3d483SAdrian Chadd /*
325388b3d483SAdrian Chadd  * Return whether we're ready to TX a BAR frame.
325488b3d483SAdrian Chadd  *
325588b3d483SAdrian Chadd  * Requires the TID lock be held.
325688b3d483SAdrian Chadd  */
325788b3d483SAdrian Chadd static int
325888b3d483SAdrian Chadd ath_tx_tid_bar_tx_ready(struct ath_softc *sc, struct ath_tid *tid)
325988b3d483SAdrian Chadd {
326088b3d483SAdrian Chadd 
3261375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
326288b3d483SAdrian Chadd 
326388b3d483SAdrian Chadd 	if (tid->bar_wait == 0 || tid->hwq_depth > 0)
326488b3d483SAdrian Chadd 		return (0);
326588b3d483SAdrian Chadd 
32660e22ed0eSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, "%s: tid=%p (%d), bar ready\n",
32670e22ed0eSAdrian Chadd 	    __func__, tid, tid->tid);
32680e22ed0eSAdrian Chadd 
326988b3d483SAdrian Chadd 	return (1);
327088b3d483SAdrian Chadd }
327188b3d483SAdrian Chadd 
327288b3d483SAdrian Chadd /*
327388b3d483SAdrian Chadd  * Check whether the current TID is ready to have a BAR
327488b3d483SAdrian Chadd  * TXed and if so, do the TX.
327588b3d483SAdrian Chadd  *
327688b3d483SAdrian Chadd  * Since the TID/TXQ lock can't be held during a call to
327788b3d483SAdrian Chadd  * ieee80211_send_bar(), we have to do the dirty thing of unlocking it,
327888b3d483SAdrian Chadd  * sending the BAR and locking it again.
327988b3d483SAdrian Chadd  *
328088b3d483SAdrian Chadd  * Eventually, the code to send the BAR should be broken out
328188b3d483SAdrian Chadd  * from this routine so the lock doesn't have to be reacquired
328288b3d483SAdrian Chadd  * just to be immediately dropped by the caller.
328388b3d483SAdrian Chadd  */
328488b3d483SAdrian Chadd static void
328588b3d483SAdrian Chadd ath_tx_tid_bar_tx(struct ath_softc *sc, struct ath_tid *tid)
328688b3d483SAdrian Chadd {
328788b3d483SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
328888b3d483SAdrian Chadd 
3289375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
329088b3d483SAdrian Chadd 
32910e22ed0eSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
329288b3d483SAdrian Chadd 	    "%s: tid=%p, called\n",
329388b3d483SAdrian Chadd 	    __func__,
329488b3d483SAdrian Chadd 	    tid);
329588b3d483SAdrian Chadd 
329688b3d483SAdrian Chadd 	tap = ath_tx_get_tx_tid(tid->an, tid->tid);
329788b3d483SAdrian Chadd 
329888b3d483SAdrian Chadd 	/*
329988b3d483SAdrian Chadd 	 * This is an error condition!
330088b3d483SAdrian Chadd 	 */
330188b3d483SAdrian Chadd 	if (tid->bar_wait == 0 || tid->bar_tx == 1) {
330288b3d483SAdrian Chadd 		device_printf(sc->sc_dev,
330388b3d483SAdrian Chadd 		    "%s: tid=%p, bar_tx=%d, bar_wait=%d: ?\n",
330488b3d483SAdrian Chadd 		    __func__,
330588b3d483SAdrian Chadd 		    tid,
330688b3d483SAdrian Chadd 		    tid->bar_tx,
330788b3d483SAdrian Chadd 		    tid->bar_wait);
330888b3d483SAdrian Chadd 		return;
330988b3d483SAdrian Chadd 	}
331088b3d483SAdrian Chadd 
331188b3d483SAdrian Chadd 	/* Don't do anything if we still have pending frames */
331288b3d483SAdrian Chadd 	if (tid->hwq_depth > 0) {
33130e22ed0eSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
331488b3d483SAdrian Chadd 		    "%s: tid=%p, hwq_depth=%d, waiting\n",
331588b3d483SAdrian Chadd 		    __func__,
331688b3d483SAdrian Chadd 		    tid,
331788b3d483SAdrian Chadd 		    tid->hwq_depth);
331888b3d483SAdrian Chadd 		return;
331988b3d483SAdrian Chadd 	}
332088b3d483SAdrian Chadd 
332188b3d483SAdrian Chadd 	/* We're now about to TX */
332288b3d483SAdrian Chadd 	tid->bar_tx = 1;
332388b3d483SAdrian Chadd 
332488b3d483SAdrian Chadd 	/*
33254e81f27cSAdrian Chadd 	 * Override the clrdmask configuration for the next frame,
33264e81f27cSAdrian Chadd 	 * just to get the ball rolling.
33274e81f27cSAdrian Chadd 	 */
33284f25ddbbSAdrian Chadd 	ath_tx_set_clrdmask(sc, tid->an);
33294e81f27cSAdrian Chadd 
33304e81f27cSAdrian Chadd 	/*
333188b3d483SAdrian Chadd 	 * Calculate new BAW left edge, now that all frames have either
333288b3d483SAdrian Chadd 	 * succeeded or failed.
333388b3d483SAdrian Chadd 	 *
333488b3d483SAdrian Chadd 	 * XXX verify this is _actually_ the valid value to begin at!
333588b3d483SAdrian Chadd 	 */
33360e22ed0eSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
333788b3d483SAdrian Chadd 	    "%s: tid=%p, new BAW left edge=%d\n",
333888b3d483SAdrian Chadd 	    __func__,
333988b3d483SAdrian Chadd 	    tid,
334088b3d483SAdrian Chadd 	    tap->txa_start);
334188b3d483SAdrian Chadd 
334288b3d483SAdrian Chadd 	/* Try sending the BAR frame */
334388b3d483SAdrian Chadd 	/* We can't hold the lock here! */
334488b3d483SAdrian Chadd 
3345375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
334688b3d483SAdrian Chadd 	if (ieee80211_send_bar(&tid->an->an_node, tap, tap->txa_start) == 0) {
334788b3d483SAdrian Chadd 		/* Success? Now we wait for notification that it's done */
3348375307d4SAdrian Chadd 		ATH_TX_LOCK(sc);
334988b3d483SAdrian Chadd 		return;
335088b3d483SAdrian Chadd 	}
335188b3d483SAdrian Chadd 
335288b3d483SAdrian Chadd 	/* Failure? For now, warn loudly and continue */
3353375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
335488b3d483SAdrian Chadd 	device_printf(sc->sc_dev, "%s: tid=%p, failed to TX BAR, continue!\n",
335588b3d483SAdrian Chadd 	    __func__, tid);
335688b3d483SAdrian Chadd 	ath_tx_tid_bar_unsuspend(sc, tid);
335788b3d483SAdrian Chadd }
335888b3d483SAdrian Chadd 
3359eb6f0de0SAdrian Chadd static void
3360f1bc738eSAdrian Chadd ath_tx_tid_drain_pkt(struct ath_softc *sc, struct ath_node *an,
3361f1bc738eSAdrian Chadd     struct ath_tid *tid, ath_bufhead *bf_cq, struct ath_buf *bf)
3362eb6f0de0SAdrian Chadd {
3363eb6f0de0SAdrian Chadd 
3364375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
3365eb6f0de0SAdrian Chadd 
3366eb6f0de0SAdrian Chadd 	/*
3367eb6f0de0SAdrian Chadd 	 * If the current TID is running AMPDU, update
3368eb6f0de0SAdrian Chadd 	 * the BAW.
3369eb6f0de0SAdrian Chadd 	 */
3370eb6f0de0SAdrian Chadd 	if (ath_tx_ampdu_running(sc, an, tid->tid) &&
3371eb6f0de0SAdrian Chadd 	    bf->bf_state.bfs_dobaw) {
3372eb6f0de0SAdrian Chadd 		/*
3373eb6f0de0SAdrian Chadd 		 * Only remove the frame from the BAW if it's
3374eb6f0de0SAdrian Chadd 		 * been transmitted at least once; this means
3375eb6f0de0SAdrian Chadd 		 * the frame was in the BAW to begin with.
3376eb6f0de0SAdrian Chadd 		 */
3377eb6f0de0SAdrian Chadd 		if (bf->bf_state.bfs_retries > 0) {
3378eb6f0de0SAdrian Chadd 			ath_tx_update_baw(sc, an, tid, bf);
3379eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_dobaw = 0;
3380eb6f0de0SAdrian Chadd 		}
3381ce597531SAdrian Chadd #if 0
3382eb6f0de0SAdrian Chadd 		/*
3383eb6f0de0SAdrian Chadd 		 * This has become a non-fatal error now
3384eb6f0de0SAdrian Chadd 		 */
3385eb6f0de0SAdrian Chadd 		if (! bf->bf_state.bfs_addedbaw)
3386eb6f0de0SAdrian Chadd 			device_printf(sc->sc_dev,
3387eb6f0de0SAdrian Chadd 			    "%s: wasn't added: seqno %d\n",
3388eb6f0de0SAdrian Chadd 			    __func__, SEQNO(bf->bf_state.bfs_seqno));
3389ce597531SAdrian Chadd #endif
3390eb6f0de0SAdrian Chadd 	}
3391b837332dSAdrian Chadd 
3392b837332dSAdrian Chadd 	/* Strip it out of an aggregate list if it was in one */
3393b837332dSAdrian Chadd 	bf->bf_next = NULL;
3394b837332dSAdrian Chadd 
3395b837332dSAdrian Chadd 	/* Insert on the free queue to be freed by the caller */
3396eb6f0de0SAdrian Chadd 	TAILQ_INSERT_TAIL(bf_cq, bf, bf_list);
3397eb6f0de0SAdrian Chadd }
3398eb6f0de0SAdrian Chadd 
3399f1bc738eSAdrian Chadd static void
3400f1bc738eSAdrian Chadd ath_tx_tid_drain_print(struct ath_softc *sc, struct ath_node *an,
340103682514SAdrian Chadd     const char *pfx, struct ath_tid *tid, struct ath_buf *bf)
3402f1bc738eSAdrian Chadd {
3403f1bc738eSAdrian Chadd 	struct ieee80211_node *ni = &an->an_node;
3404f1bc738eSAdrian Chadd 	struct ath_txq *txq = sc->sc_ac2q[tid->ac];
3405f1bc738eSAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
3406f1bc738eSAdrian Chadd 
3407f1bc738eSAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid->tid);
3408f1bc738eSAdrian Chadd 
3409f1bc738eSAdrian Chadd 	device_printf(sc->sc_dev,
341003682514SAdrian Chadd 	    "%s: %s: node %p: bf=%p: addbaw=%d, dobaw=%d, "
3411f1bc738eSAdrian Chadd 	    "seqno=%d, retry=%d\n",
341203682514SAdrian Chadd 	    __func__, pfx, ni, bf,
3413f1bc738eSAdrian Chadd 	    bf->bf_state.bfs_addedbaw,
3414f1bc738eSAdrian Chadd 	    bf->bf_state.bfs_dobaw,
3415f1bc738eSAdrian Chadd 	    SEQNO(bf->bf_state.bfs_seqno),
3416f1bc738eSAdrian Chadd 	    bf->bf_state.bfs_retries);
3417f1bc738eSAdrian Chadd 	device_printf(sc->sc_dev,
341803682514SAdrian Chadd 	    "%s: node %p: bf=%p: txq[%d] axq_depth=%d, axq_aggr_depth=%d\n",
34194e81f27cSAdrian Chadd 	        __func__, ni, bf,
342003682514SAdrian Chadd 	    txq->axq_qnum,
34214e81f27cSAdrian Chadd 	    txq->axq_depth,
34224e81f27cSAdrian Chadd 	    txq->axq_aggr_depth);
34234e81f27cSAdrian Chadd 
34244e81f27cSAdrian Chadd 	device_printf(sc->sc_dev,
3425f1bc738eSAdrian Chadd 	    "%s: node %p: bf=%p: tid txq_depth=%d hwq_depth=%d, bar_wait=%d, isfiltered=%d\n",
3426f1bc738eSAdrian Chadd 	    __func__, ni, bf,
3427f1bc738eSAdrian Chadd 	    tid->axq_depth,
3428f1bc738eSAdrian Chadd 	    tid->hwq_depth,
3429f1bc738eSAdrian Chadd 	    tid->bar_wait,
3430f1bc738eSAdrian Chadd 	    tid->isfiltered);
3431f1bc738eSAdrian Chadd 	device_printf(sc->sc_dev,
34324e81f27cSAdrian Chadd 	    "%s: node %p: tid %d: "
34334e81f27cSAdrian Chadd 	    "sched=%d, paused=%d, "
34344e81f27cSAdrian Chadd 	    "incomp=%d, baw_head=%d, "
3435f1bc738eSAdrian Chadd 	    "baw_tail=%d txa_start=%d, ni_txseqs=%d\n",
34364e81f27cSAdrian Chadd 	     __func__, ni, tid->tid,
34374e81f27cSAdrian Chadd 	     tid->sched, tid->paused,
34384e81f27cSAdrian Chadd 	     tid->incomp, tid->baw_head,
3439f1bc738eSAdrian Chadd 	     tid->baw_tail, tap == NULL ? -1 : tap->txa_start,
3440f1bc738eSAdrian Chadd 	     ni->ni_txseqs[tid->tid]);
3441f1bc738eSAdrian Chadd 
3442f1bc738eSAdrian Chadd 	/* XXX Dump the frame, see what it is? */
3443f1bc738eSAdrian Chadd 	ieee80211_dump_pkt(ni->ni_ic,
3444f1bc738eSAdrian Chadd 	    mtod(bf->bf_m, const uint8_t *),
3445f1bc738eSAdrian Chadd 	    bf->bf_m->m_len, 0, -1);
3446f1bc738eSAdrian Chadd }
3447f1bc738eSAdrian Chadd 
3448f1bc738eSAdrian Chadd /*
3449f1bc738eSAdrian Chadd  * Free any packets currently pending in the software TX queue.
3450f1bc738eSAdrian Chadd  *
3451f1bc738eSAdrian Chadd  * This will be called when a node is being deleted.
3452f1bc738eSAdrian Chadd  *
3453f1bc738eSAdrian Chadd  * It can also be called on an active node during an interface
3454f1bc738eSAdrian Chadd  * reset or state transition.
3455f1bc738eSAdrian Chadd  *
3456f1bc738eSAdrian Chadd  * (From Linux/reference):
3457f1bc738eSAdrian Chadd  *
3458f1bc738eSAdrian Chadd  * TODO: For frame(s) that are in the retry state, we will reuse the
3459f1bc738eSAdrian Chadd  * sequence number(s) without setting the retry bit. The
3460f1bc738eSAdrian Chadd  * alternative is to give up on these and BAR the receiver's window
3461f1bc738eSAdrian Chadd  * forward.
3462f1bc738eSAdrian Chadd  */
3463f1bc738eSAdrian Chadd static void
3464f1bc738eSAdrian Chadd ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an,
3465f1bc738eSAdrian Chadd     struct ath_tid *tid, ath_bufhead *bf_cq)
3466f1bc738eSAdrian Chadd {
3467f1bc738eSAdrian Chadd 	struct ath_buf *bf;
3468f1bc738eSAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
3469f1bc738eSAdrian Chadd 	struct ieee80211_node *ni = &an->an_node;
3470f1bc738eSAdrian Chadd 	int t;
3471f1bc738eSAdrian Chadd 
3472f1bc738eSAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid->tid);
3473f1bc738eSAdrian Chadd 
3474375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
3475f1bc738eSAdrian Chadd 
3476f1bc738eSAdrian Chadd 	/* Walk the queue, free frames */
3477f1bc738eSAdrian Chadd 	t = 0;
3478f1bc738eSAdrian Chadd 	for (;;) {
34793e6cc97fSAdrian Chadd 		bf = ATH_TID_FIRST(tid);
3480f1bc738eSAdrian Chadd 		if (bf == NULL) {
3481f1bc738eSAdrian Chadd 			break;
3482f1bc738eSAdrian Chadd 		}
3483f1bc738eSAdrian Chadd 
3484f1bc738eSAdrian Chadd 		if (t == 0) {
348503682514SAdrian Chadd 			ath_tx_tid_drain_print(sc, an, "norm", tid, bf);
3486f1bc738eSAdrian Chadd 			t = 1;
3487f1bc738eSAdrian Chadd 		}
3488f1bc738eSAdrian Chadd 
34893e6cc97fSAdrian Chadd 		ATH_TID_REMOVE(tid, bf, bf_list);
3490f1bc738eSAdrian Chadd 		ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf);
3491f1bc738eSAdrian Chadd 	}
3492f1bc738eSAdrian Chadd 
3493f1bc738eSAdrian Chadd 	/* And now, drain the filtered frame queue */
3494f1bc738eSAdrian Chadd 	t = 0;
3495f1bc738eSAdrian Chadd 	for (;;) {
349613aa9ee5SAdrian Chadd 		bf = ATH_TID_FILT_FIRST(tid);
3497f1bc738eSAdrian Chadd 		if (bf == NULL)
3498f1bc738eSAdrian Chadd 			break;
3499f1bc738eSAdrian Chadd 
3500f1bc738eSAdrian Chadd 		if (t == 0) {
350103682514SAdrian Chadd 			ath_tx_tid_drain_print(sc, an, "filt", tid, bf);
3502f1bc738eSAdrian Chadd 			t = 1;
3503f1bc738eSAdrian Chadd 		}
3504f1bc738eSAdrian Chadd 
350513aa9ee5SAdrian Chadd 		ATH_TID_FILT_REMOVE(tid, bf, bf_list);
3506f1bc738eSAdrian Chadd 		ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf);
3507f1bc738eSAdrian Chadd 	}
3508f1bc738eSAdrian Chadd 
3509eb6f0de0SAdrian Chadd 	/*
35104e81f27cSAdrian Chadd 	 * Override the clrdmask configuration for the next frame
35114e81f27cSAdrian Chadd 	 * in case there is some future transmission, just to get
35124e81f27cSAdrian Chadd 	 * the ball rolling.
35134e81f27cSAdrian Chadd 	 *
35144e81f27cSAdrian Chadd 	 * This won't hurt things if the TID is about to be freed.
35154e81f27cSAdrian Chadd 	 */
35164f25ddbbSAdrian Chadd 	ath_tx_set_clrdmask(sc, tid->an);
35174e81f27cSAdrian Chadd 
35184e81f27cSAdrian Chadd 	/*
3519eb6f0de0SAdrian Chadd 	 * Now that it's completed, grab the TID lock and update
3520eb6f0de0SAdrian Chadd 	 * the sequence number and BAW window.
3521eb6f0de0SAdrian Chadd 	 * Because sequence numbers have been assigned to frames
3522eb6f0de0SAdrian Chadd 	 * that haven't been sent yet, it's entirely possible
3523eb6f0de0SAdrian Chadd 	 * we'll be called with some pending frames that have not
3524eb6f0de0SAdrian Chadd 	 * been transmitted.
3525eb6f0de0SAdrian Chadd 	 *
3526eb6f0de0SAdrian Chadd 	 * The cleaner solution is to do the sequence number allocation
3527eb6f0de0SAdrian Chadd 	 * when the packet is first transmitted - and thus the "retries"
3528eb6f0de0SAdrian Chadd 	 * check above would be enough to update the BAW/seqno.
3529eb6f0de0SAdrian Chadd 	 */
3530eb6f0de0SAdrian Chadd 
3531eb6f0de0SAdrian Chadd 	/* But don't do it for non-QoS TIDs */
3532eb6f0de0SAdrian Chadd 	if (tap) {
3533eb6f0de0SAdrian Chadd #if 0
3534eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3535eb6f0de0SAdrian Chadd 		    "%s: node %p: TID %d: sliding BAW left edge to %d\n",
3536eb6f0de0SAdrian Chadd 		    __func__, an, tid->tid, tap->txa_start);
3537eb6f0de0SAdrian Chadd #endif
3538eb6f0de0SAdrian Chadd 		ni->ni_txseqs[tid->tid] = tap->txa_start;
3539eb6f0de0SAdrian Chadd 		tid->baw_tail = tid->baw_head;
3540eb6f0de0SAdrian Chadd 	}
3541eb6f0de0SAdrian Chadd }
3542eb6f0de0SAdrian Chadd 
3543eb6f0de0SAdrian Chadd /*
3544eb6f0de0SAdrian Chadd  * Flush all software queued packets for the given node.
3545eb6f0de0SAdrian Chadd  *
3546eb6f0de0SAdrian Chadd  * This occurs when a completion handler frees the last buffer
3547eb6f0de0SAdrian Chadd  * for a node, and the node is thus freed. This causes the node
3548eb6f0de0SAdrian Chadd  * to be cleaned up, which ends up calling ath_tx_node_flush.
3549eb6f0de0SAdrian Chadd  */
3550eb6f0de0SAdrian Chadd void
3551eb6f0de0SAdrian Chadd ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an)
3552eb6f0de0SAdrian Chadd {
3553eb6f0de0SAdrian Chadd 	int tid;
3554eb6f0de0SAdrian Chadd 	ath_bufhead bf_cq;
3555eb6f0de0SAdrian Chadd 	struct ath_buf *bf;
3556eb6f0de0SAdrian Chadd 
3557eb6f0de0SAdrian Chadd 	TAILQ_INIT(&bf_cq);
3558eb6f0de0SAdrian Chadd 
355903682514SAdrian Chadd 	ATH_KTR(sc, ATH_KTR_NODE, 1, "ath_tx_node_flush: flush node; ni=%p",
356003682514SAdrian Chadd 	    &an->an_node);
356103682514SAdrian Chadd 
3562375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
3563eb6f0de0SAdrian Chadd 	for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) {
3564eb6f0de0SAdrian Chadd 		struct ath_tid *atid = &an->an_tid[tid];
3565eb6f0de0SAdrian Chadd 
3566eb6f0de0SAdrian Chadd 		/* Free packets */
3567eb6f0de0SAdrian Chadd 		ath_tx_tid_drain(sc, an, atid, &bf_cq);
356823f44d2bSAdrian Chadd 		/* Remove this tid from the list of active tids */
356923f44d2bSAdrian Chadd 		ath_tx_tid_unsched(sc, atid);
3570eb6f0de0SAdrian Chadd 	}
3571375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
3572eb6f0de0SAdrian Chadd 
3573eb6f0de0SAdrian Chadd 	/* Handle completed frames */
3574eb6f0de0SAdrian Chadd 	while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3575eb6f0de0SAdrian Chadd 		TAILQ_REMOVE(&bf_cq, bf, bf_list);
3576eb6f0de0SAdrian Chadd 		ath_tx_default_comp(sc, bf, 0);
3577eb6f0de0SAdrian Chadd 	}
3578eb6f0de0SAdrian Chadd }
3579eb6f0de0SAdrian Chadd 
3580eb6f0de0SAdrian Chadd /*
3581eb6f0de0SAdrian Chadd  * Drain all the software TXQs currently with traffic queued.
3582eb6f0de0SAdrian Chadd  */
3583eb6f0de0SAdrian Chadd void
3584eb6f0de0SAdrian Chadd ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq)
3585eb6f0de0SAdrian Chadd {
3586eb6f0de0SAdrian Chadd 	struct ath_tid *tid;
3587eb6f0de0SAdrian Chadd 	ath_bufhead bf_cq;
3588eb6f0de0SAdrian Chadd 	struct ath_buf *bf;
3589eb6f0de0SAdrian Chadd 
3590eb6f0de0SAdrian Chadd 	TAILQ_INIT(&bf_cq);
3591375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
3592eb6f0de0SAdrian Chadd 
3593eb6f0de0SAdrian Chadd 	/*
3594eb6f0de0SAdrian Chadd 	 * Iterate over all active tids for the given txq,
3595eb6f0de0SAdrian Chadd 	 * flushing and unsched'ing them
3596eb6f0de0SAdrian Chadd 	 */
3597eb6f0de0SAdrian Chadd 	while (! TAILQ_EMPTY(&txq->axq_tidq)) {
3598eb6f0de0SAdrian Chadd 		tid = TAILQ_FIRST(&txq->axq_tidq);
3599eb6f0de0SAdrian Chadd 		ath_tx_tid_drain(sc, tid->an, tid, &bf_cq);
3600eb6f0de0SAdrian Chadd 		ath_tx_tid_unsched(sc, tid);
3601eb6f0de0SAdrian Chadd 	}
3602eb6f0de0SAdrian Chadd 
3603375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
3604eb6f0de0SAdrian Chadd 
3605eb6f0de0SAdrian Chadd 	while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3606eb6f0de0SAdrian Chadd 		TAILQ_REMOVE(&bf_cq, bf, bf_list);
3607eb6f0de0SAdrian Chadd 		ath_tx_default_comp(sc, bf, 0);
3608eb6f0de0SAdrian Chadd 	}
3609eb6f0de0SAdrian Chadd }
3610eb6f0de0SAdrian Chadd 
3611eb6f0de0SAdrian Chadd /*
3612eb6f0de0SAdrian Chadd  * Handle completion of non-aggregate session frames.
36130c54de88SAdrian Chadd  *
36140c54de88SAdrian Chadd  * This (currently) doesn't implement software retransmission of
36150c54de88SAdrian Chadd  * non-aggregate frames!
36160c54de88SAdrian Chadd  *
36170c54de88SAdrian Chadd  * Software retransmission of non-aggregate frames needs to obey
36180c54de88SAdrian Chadd  * the strict sequence number ordering, and drop any frames that
36190c54de88SAdrian Chadd  * will fail this.
36200c54de88SAdrian Chadd  *
36210c54de88SAdrian Chadd  * For now, filtered frames and frame transmission will cause
36220c54de88SAdrian Chadd  * all kinds of issues.  So we don't support them.
36230c54de88SAdrian Chadd  *
36240c54de88SAdrian Chadd  * So anyone queuing frames via ath_tx_normal_xmit() or
36250c54de88SAdrian Chadd  * ath_tx_hw_queue_norm() must override and set CLRDMASK.
3626eb6f0de0SAdrian Chadd  */
3627eb6f0de0SAdrian Chadd void
3628eb6f0de0SAdrian Chadd ath_tx_normal_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
3629eb6f0de0SAdrian Chadd {
3630eb6f0de0SAdrian Chadd 	struct ieee80211_node *ni = bf->bf_node;
3631eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
3632eb6f0de0SAdrian Chadd 	int tid = bf->bf_state.bfs_tid;
3633eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
3634eb6f0de0SAdrian Chadd 	struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
3635eb6f0de0SAdrian Chadd 
3636eb6f0de0SAdrian Chadd 	/* The TID state is protected behind the TXQ lock */
3637375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
3638eb6f0de0SAdrian Chadd 
3639eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p: fail=%d, hwq_depth now %d\n",
3640eb6f0de0SAdrian Chadd 	    __func__, bf, fail, atid->hwq_depth - 1);
3641eb6f0de0SAdrian Chadd 
3642eb6f0de0SAdrian Chadd 	atid->hwq_depth--;
3643f1bc738eSAdrian Chadd 
36440c54de88SAdrian Chadd #if 0
36450c54de88SAdrian Chadd 	/*
36460c54de88SAdrian Chadd 	 * If the frame was filtered, stick it on the filter frame
36470c54de88SAdrian Chadd 	 * queue and complain about it.  It shouldn't happen!
36480c54de88SAdrian Chadd 	 */
36490c54de88SAdrian Chadd 	if ((ts->ts_status & HAL_TXERR_FILT) ||
36500c54de88SAdrian Chadd 	    (ts->ts_status != 0 && atid->isfiltered)) {
36510c54de88SAdrian Chadd 		device_printf(sc->sc_dev,
36520c54de88SAdrian Chadd 		    "%s: isfiltered=%d, ts_status=%d: huh?\n",
36530c54de88SAdrian Chadd 		    __func__,
36540c54de88SAdrian Chadd 		    atid->isfiltered,
36550c54de88SAdrian Chadd 		    ts->ts_status);
36560c54de88SAdrian Chadd 		ath_tx_tid_filt_comp_buf(sc, atid, bf);
36570c54de88SAdrian Chadd 	}
36580c54de88SAdrian Chadd #endif
3659f1bc738eSAdrian Chadd 	if (atid->isfiltered)
36600c54de88SAdrian Chadd 		device_printf(sc->sc_dev, "%s: filtered?!\n", __func__);
3661eb6f0de0SAdrian Chadd 	if (atid->hwq_depth < 0)
3662eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
3663eb6f0de0SAdrian Chadd 		    __func__, atid->hwq_depth);
3664f1bc738eSAdrian Chadd 
3665f1bc738eSAdrian Chadd 	/*
3666f1bc738eSAdrian Chadd 	 * If the queue is filtered, potentially mark it as complete
3667f1bc738eSAdrian Chadd 	 * and reschedule it as needed.
3668f1bc738eSAdrian Chadd 	 *
3669f1bc738eSAdrian Chadd 	 * This is required as there may be a subsequent TX descriptor
3670f1bc738eSAdrian Chadd 	 * for this end-node that has CLRDMASK set, so it's quite possible
3671f1bc738eSAdrian Chadd 	 * that a filtered frame will be followed by a non-filtered
3672f1bc738eSAdrian Chadd 	 * (complete or otherwise) frame.
3673f1bc738eSAdrian Chadd 	 *
3674f1bc738eSAdrian Chadd 	 * XXX should we do this before we complete the frame?
3675f1bc738eSAdrian Chadd 	 */
3676f1bc738eSAdrian Chadd 	if (atid->isfiltered)
3677f1bc738eSAdrian Chadd 		ath_tx_tid_filt_comp_complete(sc, atid);
3678375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
3679eb6f0de0SAdrian Chadd 
3680eb6f0de0SAdrian Chadd 	/*
3681eb6f0de0SAdrian Chadd 	 * punt to rate control if we're not being cleaned up
3682eb6f0de0SAdrian Chadd 	 * during a hw queue drain and the frame wanted an ACK.
3683eb6f0de0SAdrian Chadd 	 */
3684875a9451SAdrian Chadd 	if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0))
3685eb6f0de0SAdrian Chadd 		ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc,
3686eb6f0de0SAdrian Chadd 		    ts, bf->bf_state.bfs_pktlen,
3687eb6f0de0SAdrian Chadd 		    1, (ts->ts_status == 0) ? 0 : 1);
3688eb6f0de0SAdrian Chadd 
3689eb6f0de0SAdrian Chadd 	ath_tx_default_comp(sc, bf, fail);
3690eb6f0de0SAdrian Chadd }
3691eb6f0de0SAdrian Chadd 
3692eb6f0de0SAdrian Chadd /*
3693eb6f0de0SAdrian Chadd  * Handle cleanup of aggregate session packets that aren't
3694eb6f0de0SAdrian Chadd  * an A-MPDU.
3695eb6f0de0SAdrian Chadd  *
3696eb6f0de0SAdrian Chadd  * There's no need to update the BAW here - the session is being
3697eb6f0de0SAdrian Chadd  * torn down.
3698eb6f0de0SAdrian Chadd  */
3699eb6f0de0SAdrian Chadd static void
3700eb6f0de0SAdrian Chadd ath_tx_comp_cleanup_unaggr(struct ath_softc *sc, struct ath_buf *bf)
3701eb6f0de0SAdrian Chadd {
3702eb6f0de0SAdrian Chadd 	struct ieee80211_node *ni = bf->bf_node;
3703eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
3704eb6f0de0SAdrian Chadd 	int tid = bf->bf_state.bfs_tid;
3705eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
3706eb6f0de0SAdrian Chadd 
3707eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: TID %d: incomp=%d\n",
3708eb6f0de0SAdrian Chadd 	    __func__, tid, atid->incomp);
3709eb6f0de0SAdrian Chadd 
3710375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
3711eb6f0de0SAdrian Chadd 	atid->incomp--;
3712eb6f0de0SAdrian Chadd 	if (atid->incomp == 0) {
3713eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3714eb6f0de0SAdrian Chadd 		    "%s: TID %d: cleaned up! resume!\n",
3715eb6f0de0SAdrian Chadd 		    __func__, tid);
3716eb6f0de0SAdrian Chadd 		atid->cleanup_inprogress = 0;
3717eb6f0de0SAdrian Chadd 		ath_tx_tid_resume(sc, atid);
3718eb6f0de0SAdrian Chadd 	}
3719375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
3720eb6f0de0SAdrian Chadd 
3721eb6f0de0SAdrian Chadd 	ath_tx_default_comp(sc, bf, 0);
3722eb6f0de0SAdrian Chadd }
3723eb6f0de0SAdrian Chadd 
3724eb6f0de0SAdrian Chadd /*
3725eb6f0de0SAdrian Chadd  * Performs transmit side cleanup when TID changes from aggregated to
3726eb6f0de0SAdrian Chadd  * unaggregated.
3727eb6f0de0SAdrian Chadd  *
3728eb6f0de0SAdrian Chadd  * - Discard all retry frames from the s/w queue.
3729eb6f0de0SAdrian Chadd  * - Fix the tx completion function for all buffers in s/w queue.
3730eb6f0de0SAdrian Chadd  * - Count the number of unacked frames, and let transmit completion
3731eb6f0de0SAdrian Chadd  *   handle it later.
3732eb6f0de0SAdrian Chadd  *
3733eb6f0de0SAdrian Chadd  * The caller is responsible for pausing the TID.
3734eb6f0de0SAdrian Chadd  */
3735eb6f0de0SAdrian Chadd static void
37364dfd4507SAdrian Chadd ath_tx_tid_cleanup(struct ath_softc *sc, struct ath_node *an, int tid)
3737eb6f0de0SAdrian Chadd {
3738eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
3739eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
3740eb6f0de0SAdrian Chadd 	struct ath_buf *bf, *bf_next;
3741eb6f0de0SAdrian Chadd 	ath_bufhead bf_cq;
3742eb6f0de0SAdrian Chadd 
3743d3a6425bSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
3744eb6f0de0SAdrian Chadd 	    "%s: TID %d: called\n", __func__, tid);
3745eb6f0de0SAdrian Chadd 
3746eb6f0de0SAdrian Chadd 	TAILQ_INIT(&bf_cq);
3747375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
3748eb6f0de0SAdrian Chadd 
3749eb6f0de0SAdrian Chadd 	/*
3750f1bc738eSAdrian Chadd 	 * Move the filtered frames to the TX queue, before
3751f1bc738eSAdrian Chadd 	 * we run off and discard/process things.
3752f1bc738eSAdrian Chadd 	 */
3753f1bc738eSAdrian Chadd 	/* XXX this is really quite inefficient */
375413aa9ee5SAdrian Chadd 	while ((bf = ATH_TID_FILT_LAST(atid, ath_bufhead_s)) != NULL) {
375513aa9ee5SAdrian Chadd 		ATH_TID_FILT_REMOVE(atid, bf, bf_list);
37563e6cc97fSAdrian Chadd 		ATH_TID_INSERT_HEAD(atid, bf, bf_list);
3757f1bc738eSAdrian Chadd 	}
3758f1bc738eSAdrian Chadd 
3759f1bc738eSAdrian Chadd 	/*
3760eb6f0de0SAdrian Chadd 	 * Update the frames in the software TX queue:
3761eb6f0de0SAdrian Chadd 	 *
3762eb6f0de0SAdrian Chadd 	 * + Discard retry frames in the queue
3763eb6f0de0SAdrian Chadd 	 * + Fix the completion function to be non-aggregate
3764eb6f0de0SAdrian Chadd 	 */
37653e6cc97fSAdrian Chadd 	bf = ATH_TID_FIRST(atid);
3766eb6f0de0SAdrian Chadd 	while (bf) {
3767eb6f0de0SAdrian Chadd 		if (bf->bf_state.bfs_isretried) {
3768eb6f0de0SAdrian Chadd 			bf_next = TAILQ_NEXT(bf, bf_list);
37693e6cc97fSAdrian Chadd 			ATH_TID_REMOVE(atid, bf, bf_list);
3770eb6f0de0SAdrian Chadd 			if (bf->bf_state.bfs_dobaw) {
3771eb6f0de0SAdrian Chadd 				ath_tx_update_baw(sc, an, atid, bf);
3772eb6f0de0SAdrian Chadd 				if (! bf->bf_state.bfs_addedbaw)
3773eb6f0de0SAdrian Chadd 					device_printf(sc->sc_dev,
3774eb6f0de0SAdrian Chadd 					    "%s: wasn't added: seqno %d\n",
3775d4365d16SAdrian Chadd 					    __func__,
3776d4365d16SAdrian Chadd 					    SEQNO(bf->bf_state.bfs_seqno));
3777eb6f0de0SAdrian Chadd 			}
3778eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_dobaw = 0;
3779eb6f0de0SAdrian Chadd 			/*
3780eb6f0de0SAdrian Chadd 			 * Call the default completion handler with "fail" just
3781eb6f0de0SAdrian Chadd 			 * so upper levels are suitably notified about this.
3782eb6f0de0SAdrian Chadd 			 */
3783eb6f0de0SAdrian Chadd 			TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
3784eb6f0de0SAdrian Chadd 			bf = bf_next;
3785eb6f0de0SAdrian Chadd 			continue;
3786eb6f0de0SAdrian Chadd 		}
3787eb6f0de0SAdrian Chadd 		/* Give these the default completion handler */
3788eb6f0de0SAdrian Chadd 		bf->bf_comp = ath_tx_normal_comp;
3789eb6f0de0SAdrian Chadd 		bf = TAILQ_NEXT(bf, bf_list);
3790eb6f0de0SAdrian Chadd 	}
3791eb6f0de0SAdrian Chadd 
3792eb6f0de0SAdrian Chadd 	/* The caller is required to pause the TID */
3793eb6f0de0SAdrian Chadd #if 0
3794eb6f0de0SAdrian Chadd 	/* Pause the TID */
3795eb6f0de0SAdrian Chadd 	ath_tx_tid_pause(sc, atid);
3796eb6f0de0SAdrian Chadd #endif
3797eb6f0de0SAdrian Chadd 
3798eb6f0de0SAdrian Chadd 	/*
3799eb6f0de0SAdrian Chadd 	 * Calculate what hardware-queued frames exist based
3800eb6f0de0SAdrian Chadd 	 * on the current BAW size. Ie, what frames have been
3801eb6f0de0SAdrian Chadd 	 * added to the TX hardware queue for this TID but
3802eb6f0de0SAdrian Chadd 	 * not yet ACKed.
3803eb6f0de0SAdrian Chadd 	 */
3804eb6f0de0SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid);
3805eb6f0de0SAdrian Chadd 	/* Need the lock - fiddling with BAW */
3806eb6f0de0SAdrian Chadd 	while (atid->baw_head != atid->baw_tail) {
3807eb6f0de0SAdrian Chadd 		if (atid->tx_buf[atid->baw_head]) {
3808eb6f0de0SAdrian Chadd 			atid->incomp++;
3809eb6f0de0SAdrian Chadd 			atid->cleanup_inprogress = 1;
3810eb6f0de0SAdrian Chadd 			atid->tx_buf[atid->baw_head] = NULL;
3811eb6f0de0SAdrian Chadd 		}
3812eb6f0de0SAdrian Chadd 		INCR(atid->baw_head, ATH_TID_MAX_BUFS);
3813eb6f0de0SAdrian Chadd 		INCR(tap->txa_start, IEEE80211_SEQ_RANGE);
3814eb6f0de0SAdrian Chadd 	}
3815eb6f0de0SAdrian Chadd 
3816eb6f0de0SAdrian Chadd 	/*
3817eb6f0de0SAdrian Chadd 	 * If cleanup is required, defer TID scheduling
3818eb6f0de0SAdrian Chadd 	 * until all the HW queued packets have been
3819eb6f0de0SAdrian Chadd 	 * sent.
3820eb6f0de0SAdrian Chadd 	 */
3821eb6f0de0SAdrian Chadd 	if (! atid->cleanup_inprogress)
3822eb6f0de0SAdrian Chadd 		ath_tx_tid_resume(sc, atid);
3823eb6f0de0SAdrian Chadd 
3824eb6f0de0SAdrian Chadd 	if (atid->cleanup_inprogress)
3825eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3826eb6f0de0SAdrian Chadd 		    "%s: TID %d: cleanup needed: %d packets\n",
3827eb6f0de0SAdrian Chadd 		    __func__, tid, atid->incomp);
3828375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
3829eb6f0de0SAdrian Chadd 
3830eb6f0de0SAdrian Chadd 	/* Handle completing frames and fail them */
3831eb6f0de0SAdrian Chadd 	while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
3832eb6f0de0SAdrian Chadd 		TAILQ_REMOVE(&bf_cq, bf, bf_list);
3833eb6f0de0SAdrian Chadd 		ath_tx_default_comp(sc, bf, 1);
3834eb6f0de0SAdrian Chadd 	}
3835eb6f0de0SAdrian Chadd }
3836eb6f0de0SAdrian Chadd 
3837eb6f0de0SAdrian Chadd static struct ath_buf *
383838962489SAdrian Chadd ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an,
383938962489SAdrian Chadd     struct ath_tid *tid, struct ath_buf *bf)
3840eb6f0de0SAdrian Chadd {
3841eb6f0de0SAdrian Chadd 	struct ath_buf *nbf;
3842eb6f0de0SAdrian Chadd 	int error;
3843eb6f0de0SAdrian Chadd 
3844eb6f0de0SAdrian Chadd 	nbf = ath_buf_clone(sc, bf);
3845eb6f0de0SAdrian Chadd 
3846eb6f0de0SAdrian Chadd #if 0
3847eb6f0de0SAdrian Chadd 	device_printf(sc->sc_dev, "%s: ATH_BUF_BUSY; cloning\n",
3848eb6f0de0SAdrian Chadd 	    __func__);
3849eb6f0de0SAdrian Chadd #endif
3850eb6f0de0SAdrian Chadd 
3851eb6f0de0SAdrian Chadd 	if (nbf == NULL) {
3852eb6f0de0SAdrian Chadd 		/* Failed to clone */
3853eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev,
3854eb6f0de0SAdrian Chadd 		    "%s: failed to clone a busy buffer\n",
3855eb6f0de0SAdrian Chadd 		    __func__);
3856eb6f0de0SAdrian Chadd 		return NULL;
3857eb6f0de0SAdrian Chadd 	}
3858eb6f0de0SAdrian Chadd 
3859eb6f0de0SAdrian Chadd 	/* Setup the dma for the new buffer */
3860eb6f0de0SAdrian Chadd 	error = ath_tx_dmasetup(sc, nbf, nbf->bf_m);
3861eb6f0de0SAdrian Chadd 	if (error != 0) {
3862eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev,
3863eb6f0de0SAdrian Chadd 		    "%s: failed to setup dma for clone\n",
3864eb6f0de0SAdrian Chadd 		    __func__);
3865eb6f0de0SAdrian Chadd 		/*
3866eb6f0de0SAdrian Chadd 		 * Put this at the head of the list, not tail;
3867eb6f0de0SAdrian Chadd 		 * that way it doesn't interfere with the
3868eb6f0de0SAdrian Chadd 		 * busy buffer logic (which uses the tail of
3869eb6f0de0SAdrian Chadd 		 * the list.)
3870eb6f0de0SAdrian Chadd 		 */
3871eb6f0de0SAdrian Chadd 		ATH_TXBUF_LOCK(sc);
387232c387f7SAdrian Chadd 		ath_returnbuf_head(sc, nbf);
3873eb6f0de0SAdrian Chadd 		ATH_TXBUF_UNLOCK(sc);
3874eb6f0de0SAdrian Chadd 		return NULL;
3875eb6f0de0SAdrian Chadd 	}
3876eb6f0de0SAdrian Chadd 
387738962489SAdrian Chadd 	/* Update BAW if required, before we free the original buf */
387838962489SAdrian Chadd 	if (bf->bf_state.bfs_dobaw)
387938962489SAdrian Chadd 		ath_tx_switch_baw_buf(sc, an, tid, bf, nbf);
388038962489SAdrian Chadd 
3881eb6f0de0SAdrian Chadd 	/* Free current buffer; return the older buffer */
3882eb6f0de0SAdrian Chadd 	bf->bf_m = NULL;
3883eb6f0de0SAdrian Chadd 	bf->bf_node = NULL;
3884eb6f0de0SAdrian Chadd 	ath_freebuf(sc, bf);
3885f1bc738eSAdrian Chadd 
3886eb6f0de0SAdrian Chadd 	return nbf;
3887eb6f0de0SAdrian Chadd }
3888eb6f0de0SAdrian Chadd 
3889eb6f0de0SAdrian Chadd /*
3890eb6f0de0SAdrian Chadd  * Handle retrying an unaggregate frame in an aggregate
3891eb6f0de0SAdrian Chadd  * session.
3892eb6f0de0SAdrian Chadd  *
3893eb6f0de0SAdrian Chadd  * If too many retries occur, pause the TID, wait for
3894eb6f0de0SAdrian Chadd  * any further retransmits (as there's no reason why
3895eb6f0de0SAdrian Chadd  * non-aggregate frames in an aggregate session are
3896eb6f0de0SAdrian Chadd  * transmitted in-order; they just have to be in-BAW)
3897eb6f0de0SAdrian Chadd  * and then queue a BAR.
3898eb6f0de0SAdrian Chadd  */
3899eb6f0de0SAdrian Chadd static void
3900eb6f0de0SAdrian Chadd ath_tx_aggr_retry_unaggr(struct ath_softc *sc, struct ath_buf *bf)
3901eb6f0de0SAdrian Chadd {
3902eb6f0de0SAdrian Chadd 	struct ieee80211_node *ni = bf->bf_node;
3903eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
3904eb6f0de0SAdrian Chadd 	int tid = bf->bf_state.bfs_tid;
3905eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
3906eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
3907eb6f0de0SAdrian Chadd 
3908375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
3909eb6f0de0SAdrian Chadd 
3910eb6f0de0SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid);
3911eb6f0de0SAdrian Chadd 
3912eb6f0de0SAdrian Chadd 	/*
3913eb6f0de0SAdrian Chadd 	 * If the buffer is marked as busy, we can't directly
3914eb6f0de0SAdrian Chadd 	 * reuse it. Instead, try to clone the buffer.
3915eb6f0de0SAdrian Chadd 	 * If the clone is successful, recycle the old buffer.
3916eb6f0de0SAdrian Chadd 	 * If the clone is unsuccessful, set bfs_retries to max
3917eb6f0de0SAdrian Chadd 	 * to force the next bit of code to free the buffer
3918eb6f0de0SAdrian Chadd 	 * for us.
3919eb6f0de0SAdrian Chadd 	 */
3920eb6f0de0SAdrian Chadd 	if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) &&
3921eb6f0de0SAdrian Chadd 	    (bf->bf_flags & ATH_BUF_BUSY)) {
3922eb6f0de0SAdrian Chadd 		struct ath_buf *nbf;
392338962489SAdrian Chadd 		nbf = ath_tx_retry_clone(sc, an, atid, bf);
3924eb6f0de0SAdrian Chadd 		if (nbf)
3925eb6f0de0SAdrian Chadd 			/* bf has been freed at this point */
3926eb6f0de0SAdrian Chadd 			bf = nbf;
3927eb6f0de0SAdrian Chadd 		else
3928eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_retries = SWMAX_RETRIES + 1;
3929eb6f0de0SAdrian Chadd 	}
3930eb6f0de0SAdrian Chadd 
3931eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) {
3932eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES,
3933eb6f0de0SAdrian Chadd 		    "%s: exceeded retries; seqno %d\n",
3934eb6f0de0SAdrian Chadd 		    __func__, SEQNO(bf->bf_state.bfs_seqno));
3935eb6f0de0SAdrian Chadd 		sc->sc_stats.ast_tx_swretrymax++;
3936eb6f0de0SAdrian Chadd 
3937eb6f0de0SAdrian Chadd 		/* Update BAW anyway */
3938eb6f0de0SAdrian Chadd 		if (bf->bf_state.bfs_dobaw) {
3939eb6f0de0SAdrian Chadd 			ath_tx_update_baw(sc, an, atid, bf);
3940eb6f0de0SAdrian Chadd 			if (! bf->bf_state.bfs_addedbaw)
3941eb6f0de0SAdrian Chadd 				device_printf(sc->sc_dev,
3942eb6f0de0SAdrian Chadd 				    "%s: wasn't added: seqno %d\n",
3943eb6f0de0SAdrian Chadd 				    __func__, SEQNO(bf->bf_state.bfs_seqno));
3944eb6f0de0SAdrian Chadd 		}
3945eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_dobaw = 0;
3946eb6f0de0SAdrian Chadd 
394788b3d483SAdrian Chadd 		/* Suspend the TX queue and get ready to send the BAR */
394888b3d483SAdrian Chadd 		ath_tx_tid_bar_suspend(sc, atid);
394988b3d483SAdrian Chadd 
395088b3d483SAdrian Chadd 		/* Send the BAR if there are no other frames waiting */
395188b3d483SAdrian Chadd 		if (ath_tx_tid_bar_tx_ready(sc, atid))
395288b3d483SAdrian Chadd 			ath_tx_tid_bar_tx(sc, atid);
395388b3d483SAdrian Chadd 
3954375307d4SAdrian Chadd 		ATH_TX_UNLOCK(sc);
3955eb6f0de0SAdrian Chadd 
3956eb6f0de0SAdrian Chadd 		/* Free buffer, bf is free after this call */
3957eb6f0de0SAdrian Chadd 		ath_tx_default_comp(sc, bf, 0);
3958eb6f0de0SAdrian Chadd 		return;
3959eb6f0de0SAdrian Chadd 	}
3960eb6f0de0SAdrian Chadd 
3961eb6f0de0SAdrian Chadd 	/*
3962eb6f0de0SAdrian Chadd 	 * This increments the retry counter as well as
3963eb6f0de0SAdrian Chadd 	 * sets the retry flag in the ath_buf and packet
3964eb6f0de0SAdrian Chadd 	 * body.
3965eb6f0de0SAdrian Chadd 	 */
3966eb6f0de0SAdrian Chadd 	ath_tx_set_retry(sc, bf);
3967f1bc738eSAdrian Chadd 	sc->sc_stats.ast_tx_swretries++;
3968eb6f0de0SAdrian Chadd 
3969eb6f0de0SAdrian Chadd 	/*
3970eb6f0de0SAdrian Chadd 	 * Insert this at the head of the queue, so it's
3971eb6f0de0SAdrian Chadd 	 * retried before any current/subsequent frames.
3972eb6f0de0SAdrian Chadd 	 */
39733e6cc97fSAdrian Chadd 	ATH_TID_INSERT_HEAD(atid, bf, bf_list);
3974eb6f0de0SAdrian Chadd 	ath_tx_tid_sched(sc, atid);
397588b3d483SAdrian Chadd 	/* Send the BAR if there are no other frames waiting */
397688b3d483SAdrian Chadd 	if (ath_tx_tid_bar_tx_ready(sc, atid))
397788b3d483SAdrian Chadd 		ath_tx_tid_bar_tx(sc, atid);
3978eb6f0de0SAdrian Chadd 
3979375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
3980eb6f0de0SAdrian Chadd }
3981eb6f0de0SAdrian Chadd 
3982eb6f0de0SAdrian Chadd /*
3983eb6f0de0SAdrian Chadd  * Common code for aggregate excessive retry/subframe retry.
3984eb6f0de0SAdrian Chadd  * If retrying, queues buffers to bf_q. If not, frees the
3985eb6f0de0SAdrian Chadd  * buffers.
3986eb6f0de0SAdrian Chadd  *
3987eb6f0de0SAdrian Chadd  * XXX should unify this with ath_tx_aggr_retry_unaggr()
3988eb6f0de0SAdrian Chadd  */
3989eb6f0de0SAdrian Chadd static int
3990eb6f0de0SAdrian Chadd ath_tx_retry_subframe(struct ath_softc *sc, struct ath_buf *bf,
3991eb6f0de0SAdrian Chadd     ath_bufhead *bf_q)
3992eb6f0de0SAdrian Chadd {
3993eb6f0de0SAdrian Chadd 	struct ieee80211_node *ni = bf->bf_node;
3994eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
3995eb6f0de0SAdrian Chadd 	int tid = bf->bf_state.bfs_tid;
3996eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
3997eb6f0de0SAdrian Chadd 
3998375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
3999eb6f0de0SAdrian Chadd 
400021840808SAdrian Chadd 	/* XXX clr11naggr should be done for all subframes */
4001eb6f0de0SAdrian Chadd 	ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
4002eb6f0de0SAdrian Chadd 	ath_hal_set11nburstduration(sc->sc_ah, bf->bf_desc, 0);
4003f1bc738eSAdrian Chadd 
4004eb6f0de0SAdrian Chadd 	/* ath_hal_set11n_virtualmorefrag(sc->sc_ah, bf->bf_desc, 0); */
4005eb6f0de0SAdrian Chadd 
4006eb6f0de0SAdrian Chadd 	/*
4007eb6f0de0SAdrian Chadd 	 * If the buffer is marked as busy, we can't directly
4008eb6f0de0SAdrian Chadd 	 * reuse it. Instead, try to clone the buffer.
4009eb6f0de0SAdrian Chadd 	 * If the clone is successful, recycle the old buffer.
4010eb6f0de0SAdrian Chadd 	 * If the clone is unsuccessful, set bfs_retries to max
4011eb6f0de0SAdrian Chadd 	 * to force the next bit of code to free the buffer
4012eb6f0de0SAdrian Chadd 	 * for us.
4013eb6f0de0SAdrian Chadd 	 */
4014eb6f0de0SAdrian Chadd 	if ((bf->bf_state.bfs_retries < SWMAX_RETRIES) &&
4015eb6f0de0SAdrian Chadd 	    (bf->bf_flags & ATH_BUF_BUSY)) {
4016eb6f0de0SAdrian Chadd 		struct ath_buf *nbf;
401738962489SAdrian Chadd 		nbf = ath_tx_retry_clone(sc, an, atid, bf);
4018eb6f0de0SAdrian Chadd 		if (nbf)
4019eb6f0de0SAdrian Chadd 			/* bf has been freed at this point */
4020eb6f0de0SAdrian Chadd 			bf = nbf;
4021eb6f0de0SAdrian Chadd 		else
4022eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_retries = SWMAX_RETRIES + 1;
4023eb6f0de0SAdrian Chadd 	}
4024eb6f0de0SAdrian Chadd 
4025eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_retries >= SWMAX_RETRIES) {
4026eb6f0de0SAdrian Chadd 		sc->sc_stats.ast_tx_swretrymax++;
4027eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_RETRIES,
4028eb6f0de0SAdrian Chadd 		    "%s: max retries: seqno %d\n",
4029eb6f0de0SAdrian Chadd 		    __func__, SEQNO(bf->bf_state.bfs_seqno));
4030eb6f0de0SAdrian Chadd 		ath_tx_update_baw(sc, an, atid, bf);
4031eb6f0de0SAdrian Chadd 		if (! bf->bf_state.bfs_addedbaw)
4032eb6f0de0SAdrian Chadd 			device_printf(sc->sc_dev,
4033eb6f0de0SAdrian Chadd 			    "%s: wasn't added: seqno %d\n",
4034eb6f0de0SAdrian Chadd 			    __func__, SEQNO(bf->bf_state.bfs_seqno));
4035eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_dobaw = 0;
4036eb6f0de0SAdrian Chadd 		return 1;
4037eb6f0de0SAdrian Chadd 	}
4038eb6f0de0SAdrian Chadd 
4039eb6f0de0SAdrian Chadd 	ath_tx_set_retry(sc, bf);
4040f1bc738eSAdrian Chadd 	sc->sc_stats.ast_tx_swretries++;
4041eb6f0de0SAdrian Chadd 	bf->bf_next = NULL;		/* Just to make sure */
4042eb6f0de0SAdrian Chadd 
404321840808SAdrian Chadd 	/* Clear the aggregate state */
404421840808SAdrian Chadd 	bf->bf_state.bfs_aggr = 0;
404521840808SAdrian Chadd 	bf->bf_state.bfs_ndelim = 0;	/* ??? needed? */
404621840808SAdrian Chadd 	bf->bf_state.bfs_nframes = 1;
404721840808SAdrian Chadd 
4048eb6f0de0SAdrian Chadd 	TAILQ_INSERT_TAIL(bf_q, bf, bf_list);
4049eb6f0de0SAdrian Chadd 	return 0;
4050eb6f0de0SAdrian Chadd }
4051eb6f0de0SAdrian Chadd 
4052eb6f0de0SAdrian Chadd /*
4053eb6f0de0SAdrian Chadd  * error pkt completion for an aggregate destination
4054eb6f0de0SAdrian Chadd  */
4055eb6f0de0SAdrian Chadd static void
4056eb6f0de0SAdrian Chadd ath_tx_comp_aggr_error(struct ath_softc *sc, struct ath_buf *bf_first,
4057eb6f0de0SAdrian Chadd     struct ath_tid *tid)
4058eb6f0de0SAdrian Chadd {
4059eb6f0de0SAdrian Chadd 	struct ieee80211_node *ni = bf_first->bf_node;
4060eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
4061eb6f0de0SAdrian Chadd 	struct ath_buf *bf_next, *bf;
4062eb6f0de0SAdrian Chadd 	ath_bufhead bf_q;
4063eb6f0de0SAdrian Chadd 	int drops = 0;
4064eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
4065eb6f0de0SAdrian Chadd 	ath_bufhead bf_cq;
4066eb6f0de0SAdrian Chadd 
4067eb6f0de0SAdrian Chadd 	TAILQ_INIT(&bf_q);
4068eb6f0de0SAdrian Chadd 	TAILQ_INIT(&bf_cq);
4069eb6f0de0SAdrian Chadd 
4070eb6f0de0SAdrian Chadd 	/*
4071eb6f0de0SAdrian Chadd 	 * Update rate control - all frames have failed.
4072eb6f0de0SAdrian Chadd 	 *
4073eb6f0de0SAdrian Chadd 	 * XXX use the length in the first frame in the series;
4074eb6f0de0SAdrian Chadd 	 * XXX just so things are consistent for now.
4075eb6f0de0SAdrian Chadd 	 */
4076eb6f0de0SAdrian Chadd 	ath_tx_update_ratectrl(sc, ni, bf_first->bf_state.bfs_rc,
4077eb6f0de0SAdrian Chadd 	    &bf_first->bf_status.ds_txstat,
4078eb6f0de0SAdrian Chadd 	    bf_first->bf_state.bfs_pktlen,
4079eb6f0de0SAdrian Chadd 	    bf_first->bf_state.bfs_nframes, bf_first->bf_state.bfs_nframes);
4080eb6f0de0SAdrian Chadd 
4081375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
4082eb6f0de0SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid->tid);
40832d3d4776SAdrian Chadd 	sc->sc_stats.ast_tx_aggr_failall++;
4084eb6f0de0SAdrian Chadd 
4085eb6f0de0SAdrian Chadd 	/* Retry all subframes */
4086eb6f0de0SAdrian Chadd 	bf = bf_first;
4087eb6f0de0SAdrian Chadd 	while (bf) {
4088eb6f0de0SAdrian Chadd 		bf_next = bf->bf_next;
4089eb6f0de0SAdrian Chadd 		bf->bf_next = NULL;	/* Remove it from the aggr list */
40902d3d4776SAdrian Chadd 		sc->sc_stats.ast_tx_aggr_fail++;
4091eb6f0de0SAdrian Chadd 		if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
4092eb6f0de0SAdrian Chadd 			drops++;
4093eb6f0de0SAdrian Chadd 			bf->bf_next = NULL;
4094eb6f0de0SAdrian Chadd 			TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
4095eb6f0de0SAdrian Chadd 		}
4096eb6f0de0SAdrian Chadd 		bf = bf_next;
4097eb6f0de0SAdrian Chadd 	}
4098eb6f0de0SAdrian Chadd 
4099eb6f0de0SAdrian Chadd 	/* Prepend all frames to the beginning of the queue */
4100eb6f0de0SAdrian Chadd 	while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) {
4101eb6f0de0SAdrian Chadd 		TAILQ_REMOVE(&bf_q, bf, bf_list);
41023e6cc97fSAdrian Chadd 		ATH_TID_INSERT_HEAD(tid, bf, bf_list);
4103eb6f0de0SAdrian Chadd 	}
4104eb6f0de0SAdrian Chadd 
410539da9d42SAdrian Chadd 	/*
410639da9d42SAdrian Chadd 	 * Schedule the TID to be re-tried.
410739da9d42SAdrian Chadd 	 */
4108eb6f0de0SAdrian Chadd 	ath_tx_tid_sched(sc, tid);
4109eb6f0de0SAdrian Chadd 
4110eb6f0de0SAdrian Chadd 	/*
4111eb6f0de0SAdrian Chadd 	 * send bar if we dropped any frames
4112eb6f0de0SAdrian Chadd 	 *
4113eb6f0de0SAdrian Chadd 	 * Keep the txq lock held for now, as we need to ensure
4114eb6f0de0SAdrian Chadd 	 * that ni_txseqs[] is consistent (as it's being updated
4115eb6f0de0SAdrian Chadd 	 * in the ifnet TX context or raw TX context.)
4116eb6f0de0SAdrian Chadd 	 */
4117eb6f0de0SAdrian Chadd 	if (drops) {
411888b3d483SAdrian Chadd 		/* Suspend the TX queue and get ready to send the BAR */
411988b3d483SAdrian Chadd 		ath_tx_tid_bar_suspend(sc, tid);
4120eb6f0de0SAdrian Chadd 	}
4121eb6f0de0SAdrian Chadd 
412288b3d483SAdrian Chadd 	/*
412388b3d483SAdrian Chadd 	 * Send BAR if required
412488b3d483SAdrian Chadd 	 */
412588b3d483SAdrian Chadd 	if (ath_tx_tid_bar_tx_ready(sc, tid))
412688b3d483SAdrian Chadd 		ath_tx_tid_bar_tx(sc, tid);
4127f1bc738eSAdrian Chadd 
4128375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
412988b3d483SAdrian Chadd 
4130eb6f0de0SAdrian Chadd 	/* Complete frames which errored out */
4131eb6f0de0SAdrian Chadd 	while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
4132eb6f0de0SAdrian Chadd 		TAILQ_REMOVE(&bf_cq, bf, bf_list);
4133eb6f0de0SAdrian Chadd 		ath_tx_default_comp(sc, bf, 0);
4134eb6f0de0SAdrian Chadd 	}
4135eb6f0de0SAdrian Chadd }
4136eb6f0de0SAdrian Chadd 
4137eb6f0de0SAdrian Chadd /*
4138eb6f0de0SAdrian Chadd  * Handle clean-up of packets from an aggregate list.
4139eb6f0de0SAdrian Chadd  *
4140eb6f0de0SAdrian Chadd  * There's no need to update the BAW here - the session is being
4141eb6f0de0SAdrian Chadd  * torn down.
4142eb6f0de0SAdrian Chadd  */
4143eb6f0de0SAdrian Chadd static void
4144eb6f0de0SAdrian Chadd ath_tx_comp_cleanup_aggr(struct ath_softc *sc, struct ath_buf *bf_first)
4145eb6f0de0SAdrian Chadd {
4146eb6f0de0SAdrian Chadd 	struct ath_buf *bf, *bf_next;
4147eb6f0de0SAdrian Chadd 	struct ieee80211_node *ni = bf_first->bf_node;
4148eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
4149eb6f0de0SAdrian Chadd 	int tid = bf_first->bf_state.bfs_tid;
4150eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
4151eb6f0de0SAdrian Chadd 
4152375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
4153eb6f0de0SAdrian Chadd 
4154eb6f0de0SAdrian Chadd 	/* update incomp */
4155302868d9SAdrian Chadd 	bf = bf_first;
4156eb6f0de0SAdrian Chadd 	while (bf) {
4157eb6f0de0SAdrian Chadd 		atid->incomp--;
4158eb6f0de0SAdrian Chadd 		bf = bf->bf_next;
4159eb6f0de0SAdrian Chadd 	}
4160eb6f0de0SAdrian Chadd 
4161eb6f0de0SAdrian Chadd 	if (atid->incomp == 0) {
4162eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
4163eb6f0de0SAdrian Chadd 		    "%s: TID %d: cleaned up! resume!\n",
4164eb6f0de0SAdrian Chadd 		    __func__, tid);
4165eb6f0de0SAdrian Chadd 		atid->cleanup_inprogress = 0;
4166eb6f0de0SAdrian Chadd 		ath_tx_tid_resume(sc, atid);
4167eb6f0de0SAdrian Chadd 	}
416888b3d483SAdrian Chadd 
416988b3d483SAdrian Chadd 	/* Send BAR if required */
4170f1bc738eSAdrian Chadd 	/* XXX why would we send a BAR when transitioning to non-aggregation? */
4171302868d9SAdrian Chadd 	/*
4172302868d9SAdrian Chadd 	 * XXX TODO: we should likely just tear down the BAR state here,
4173302868d9SAdrian Chadd 	 * rather than sending a BAR.
4174302868d9SAdrian Chadd 	 */
417588b3d483SAdrian Chadd 	if (ath_tx_tid_bar_tx_ready(sc, atid))
417688b3d483SAdrian Chadd 		ath_tx_tid_bar_tx(sc, atid);
4177f1bc738eSAdrian Chadd 
4178375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
4179eb6f0de0SAdrian Chadd 
4180eb6f0de0SAdrian Chadd 	/* Handle frame completion */
4181302868d9SAdrian Chadd 	bf = bf_first;
4182eb6f0de0SAdrian Chadd 	while (bf) {
4183eb6f0de0SAdrian Chadd 		bf_next = bf->bf_next;
4184eb6f0de0SAdrian Chadd 		ath_tx_default_comp(sc, bf, 1);
4185eb6f0de0SAdrian Chadd 		bf = bf_next;
4186eb6f0de0SAdrian Chadd 	}
4187eb6f0de0SAdrian Chadd }
4188eb6f0de0SAdrian Chadd 
4189eb6f0de0SAdrian Chadd /*
4190eb6f0de0SAdrian Chadd  * Handle completion of an set of aggregate frames.
4191eb6f0de0SAdrian Chadd  *
4192eb6f0de0SAdrian Chadd  * Note: the completion handler is the last descriptor in the aggregate,
4193eb6f0de0SAdrian Chadd  * not the last descriptor in the first frame.
4194eb6f0de0SAdrian Chadd  */
4195eb6f0de0SAdrian Chadd static void
4196d4365d16SAdrian Chadd ath_tx_aggr_comp_aggr(struct ath_softc *sc, struct ath_buf *bf_first,
4197d4365d16SAdrian Chadd     int fail)
4198eb6f0de0SAdrian Chadd {
4199eb6f0de0SAdrian Chadd 	//struct ath_desc *ds = bf->bf_lastds;
4200eb6f0de0SAdrian Chadd 	struct ieee80211_node *ni = bf_first->bf_node;
4201eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
4202eb6f0de0SAdrian Chadd 	int tid = bf_first->bf_state.bfs_tid;
4203eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
4204eb6f0de0SAdrian Chadd 	struct ath_tx_status ts;
4205eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
4206eb6f0de0SAdrian Chadd 	ath_bufhead bf_q;
4207eb6f0de0SAdrian Chadd 	ath_bufhead bf_cq;
4208eb6f0de0SAdrian Chadd 	int seq_st, tx_ok;
4209eb6f0de0SAdrian Chadd 	int hasba, isaggr;
4210eb6f0de0SAdrian Chadd 	uint32_t ba[2];
4211eb6f0de0SAdrian Chadd 	struct ath_buf *bf, *bf_next;
4212eb6f0de0SAdrian Chadd 	int ba_index;
4213eb6f0de0SAdrian Chadd 	int drops = 0;
4214eb6f0de0SAdrian Chadd 	int nframes = 0, nbad = 0, nf;
4215eb6f0de0SAdrian Chadd 	int pktlen;
4216eb6f0de0SAdrian Chadd 	/* XXX there's too much on the stack? */
4217b815538dSAdrian Chadd 	struct ath_rc_series rc[ATH_RC_NUM];
4218eb6f0de0SAdrian Chadd 	int txseq;
4219eb6f0de0SAdrian Chadd 
4220eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: called; hwq_depth=%d\n",
4221eb6f0de0SAdrian Chadd 	    __func__, atid->hwq_depth);
4222eb6f0de0SAdrian Chadd 
42230aa5c1bbSAdrian Chadd 	/*
42240aa5c1bbSAdrian Chadd 	 * Take a copy; this may be needed -after- bf_first
42250aa5c1bbSAdrian Chadd 	 * has been completed and freed.
42260aa5c1bbSAdrian Chadd 	 */
42270aa5c1bbSAdrian Chadd 	ts = bf_first->bf_status.ds_txstat;
42280aa5c1bbSAdrian Chadd 
4229f1bc738eSAdrian Chadd 	TAILQ_INIT(&bf_q);
4230f1bc738eSAdrian Chadd 	TAILQ_INIT(&bf_cq);
4231f1bc738eSAdrian Chadd 
4232eb6f0de0SAdrian Chadd 	/* The TID state is kept behind the TXQ lock */
4233375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
4234eb6f0de0SAdrian Chadd 
4235eb6f0de0SAdrian Chadd 	atid->hwq_depth--;
4236eb6f0de0SAdrian Chadd 	if (atid->hwq_depth < 0)
4237eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
4238eb6f0de0SAdrian Chadd 		    __func__, atid->hwq_depth);
4239eb6f0de0SAdrian Chadd 
4240eb6f0de0SAdrian Chadd 	/*
4241f1bc738eSAdrian Chadd 	 * If the TID is filtered, handle completing the filter
4242f1bc738eSAdrian Chadd 	 * transition before potentially kicking it to the cleanup
4243f1bc738eSAdrian Chadd 	 * function.
42440aa5c1bbSAdrian Chadd 	 *
42450aa5c1bbSAdrian Chadd 	 * XXX this is duplicate work, ew.
4246f1bc738eSAdrian Chadd 	 */
4247f1bc738eSAdrian Chadd 	if (atid->isfiltered)
4248f1bc738eSAdrian Chadd 		ath_tx_tid_filt_comp_complete(sc, atid);
4249f1bc738eSAdrian Chadd 
4250f1bc738eSAdrian Chadd 	/*
4251eb6f0de0SAdrian Chadd 	 * Punt cleanup to the relevant function, not our problem now
4252eb6f0de0SAdrian Chadd 	 */
4253eb6f0de0SAdrian Chadd 	if (atid->cleanup_inprogress) {
4254f1bc738eSAdrian Chadd 		if (atid->isfiltered)
4255f1bc738eSAdrian Chadd 			device_printf(sc->sc_dev,
4256f1bc738eSAdrian Chadd 			    "%s: isfiltered=1, normal_comp?\n",
4257f1bc738eSAdrian Chadd 			    __func__);
4258375307d4SAdrian Chadd 		ATH_TX_UNLOCK(sc);
4259eb6f0de0SAdrian Chadd 		ath_tx_comp_cleanup_aggr(sc, bf_first);
4260eb6f0de0SAdrian Chadd 		return;
4261eb6f0de0SAdrian Chadd 	}
4262eb6f0de0SAdrian Chadd 
4263eb6f0de0SAdrian Chadd 	/*
4264f1bc738eSAdrian Chadd 	 * If the frame is filtered, transition to filtered frame
4265f1bc738eSAdrian Chadd 	 * mode and add this to the filtered frame list.
4266f1bc738eSAdrian Chadd 	 *
4267f1bc738eSAdrian Chadd 	 * XXX TODO: figure out how this interoperates with
4268f1bc738eSAdrian Chadd 	 * BAR, pause and cleanup states.
4269f1bc738eSAdrian Chadd 	 */
4270f1bc738eSAdrian Chadd 	if ((ts.ts_status & HAL_TXERR_FILT) ||
4271f1bc738eSAdrian Chadd 	    (ts.ts_status != 0 && atid->isfiltered)) {
4272f1bc738eSAdrian Chadd 		if (fail != 0)
4273f1bc738eSAdrian Chadd 			device_printf(sc->sc_dev,
4274f1bc738eSAdrian Chadd 			    "%s: isfiltered=1, fail=%d\n", __func__, fail);
4275f1bc738eSAdrian Chadd 		ath_tx_tid_filt_comp_aggr(sc, atid, bf_first, &bf_cq);
4276f1bc738eSAdrian Chadd 
4277f1bc738eSAdrian Chadd 		/* Remove from BAW */
4278f1bc738eSAdrian Chadd 		TAILQ_FOREACH_SAFE(bf, &bf_cq, bf_list, bf_next) {
4279f1bc738eSAdrian Chadd 			if (bf->bf_state.bfs_addedbaw)
4280f1bc738eSAdrian Chadd 				drops++;
4281f1bc738eSAdrian Chadd 			if (bf->bf_state.bfs_dobaw) {
4282f1bc738eSAdrian Chadd 				ath_tx_update_baw(sc, an, atid, bf);
4283f1bc738eSAdrian Chadd 				if (! bf->bf_state.bfs_addedbaw)
4284f1bc738eSAdrian Chadd 					device_printf(sc->sc_dev,
4285f1bc738eSAdrian Chadd 					    "%s: wasn't added: seqno %d\n",
4286f1bc738eSAdrian Chadd 					    __func__,
4287f1bc738eSAdrian Chadd 					    SEQNO(bf->bf_state.bfs_seqno));
4288f1bc738eSAdrian Chadd 			}
4289f1bc738eSAdrian Chadd 			bf->bf_state.bfs_dobaw = 0;
4290f1bc738eSAdrian Chadd 		}
4291f1bc738eSAdrian Chadd 		/*
4292f1bc738eSAdrian Chadd 		 * If any intermediate frames in the BAW were dropped when
4293f1bc738eSAdrian Chadd 		 * handling filtering things, send a BAR.
4294f1bc738eSAdrian Chadd 		 */
4295f1bc738eSAdrian Chadd 		if (drops)
4296f1bc738eSAdrian Chadd 			ath_tx_tid_bar_suspend(sc, atid);
4297f1bc738eSAdrian Chadd 
4298f1bc738eSAdrian Chadd 		/*
4299f1bc738eSAdrian Chadd 		 * Finish up by sending a BAR if required and freeing
4300f1bc738eSAdrian Chadd 		 * the frames outside of the TX lock.
4301f1bc738eSAdrian Chadd 		 */
4302f1bc738eSAdrian Chadd 		goto finish_send_bar;
4303f1bc738eSAdrian Chadd 	}
4304f1bc738eSAdrian Chadd 
4305f1bc738eSAdrian Chadd 	/*
4306eb6f0de0SAdrian Chadd 	 * XXX for now, use the first frame in the aggregate for
4307eb6f0de0SAdrian Chadd 	 * XXX rate control completion; it's at least consistent.
4308eb6f0de0SAdrian Chadd 	 */
4309eb6f0de0SAdrian Chadd 	pktlen = bf_first->bf_state.bfs_pktlen;
4310eb6f0de0SAdrian Chadd 
4311eb6f0de0SAdrian Chadd 	/*
4312e9a6408eSAdrian Chadd 	 * Handle errors first!
4313e9a6408eSAdrian Chadd 	 *
4314e9a6408eSAdrian Chadd 	 * Here, handle _any_ error as a "exceeded retries" error.
4315e9a6408eSAdrian Chadd 	 * Later on (when filtered frames are to be specially handled)
4316e9a6408eSAdrian Chadd 	 * it'll have to be expanded.
4317eb6f0de0SAdrian Chadd 	 */
4318e9a6408eSAdrian Chadd #if 0
4319eb6f0de0SAdrian Chadd 	if (ts.ts_status & HAL_TXERR_XRETRY) {
4320e9a6408eSAdrian Chadd #endif
4321e9a6408eSAdrian Chadd 	if (ts.ts_status != 0) {
4322375307d4SAdrian Chadd 		ATH_TX_UNLOCK(sc);
4323eb6f0de0SAdrian Chadd 		ath_tx_comp_aggr_error(sc, bf_first, atid);
4324eb6f0de0SAdrian Chadd 		return;
4325eb6f0de0SAdrian Chadd 	}
4326eb6f0de0SAdrian Chadd 
4327eb6f0de0SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid);
4328eb6f0de0SAdrian Chadd 
4329eb6f0de0SAdrian Chadd 	/*
4330eb6f0de0SAdrian Chadd 	 * extract starting sequence and block-ack bitmap
4331eb6f0de0SAdrian Chadd 	 */
4332eb6f0de0SAdrian Chadd 	/* XXX endian-ness of seq_st, ba? */
4333eb6f0de0SAdrian Chadd 	seq_st = ts.ts_seqnum;
4334eb6f0de0SAdrian Chadd 	hasba = !! (ts.ts_flags & HAL_TX_BA);
4335eb6f0de0SAdrian Chadd 	tx_ok = (ts.ts_status == 0);
4336eb6f0de0SAdrian Chadd 	isaggr = bf_first->bf_state.bfs_aggr;
4337eb6f0de0SAdrian Chadd 	ba[0] = ts.ts_ba_low;
4338eb6f0de0SAdrian Chadd 	ba[1] = ts.ts_ba_high;
4339eb6f0de0SAdrian Chadd 
4340eb6f0de0SAdrian Chadd 	/*
4341eb6f0de0SAdrian Chadd 	 * Copy the TX completion status and the rate control
4342eb6f0de0SAdrian Chadd 	 * series from the first descriptor, as it may be freed
4343eb6f0de0SAdrian Chadd 	 * before the rate control code can get its grubby fingers
4344eb6f0de0SAdrian Chadd 	 * into things.
4345eb6f0de0SAdrian Chadd 	 */
4346eb6f0de0SAdrian Chadd 	memcpy(rc, bf_first->bf_state.bfs_rc, sizeof(rc));
4347eb6f0de0SAdrian Chadd 
4348eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4349d4365d16SAdrian Chadd 	    "%s: txa_start=%d, tx_ok=%d, status=%.8x, flags=%.8x, "
4350d4365d16SAdrian Chadd 	    "isaggr=%d, seq_st=%d, hasba=%d, ba=%.8x, %.8x\n",
4351eb6f0de0SAdrian Chadd 	    __func__, tap->txa_start, tx_ok, ts.ts_status, ts.ts_flags,
4352eb6f0de0SAdrian Chadd 	    isaggr, seq_st, hasba, ba[0], ba[1]);
4353eb6f0de0SAdrian Chadd 
4354b3420862SAdrian Chadd 	/*
4355b3420862SAdrian Chadd 	 * The reference driver doesn't do this; it simply ignores
4356b3420862SAdrian Chadd 	 * this check in its entirety.
4357b3420862SAdrian Chadd 	 *
4358b3420862SAdrian Chadd 	 * I've seen this occur when using iperf to send traffic
4359b3420862SAdrian Chadd 	 * out tid 1 - the aggregate frames are all marked as TID 1,
4360b3420862SAdrian Chadd 	 * but the TXSTATUS has TID=0.  So, let's just ignore this
4361b3420862SAdrian Chadd 	 * check.
4362b3420862SAdrian Chadd 	 */
4363b3420862SAdrian Chadd #if 0
4364eb6f0de0SAdrian Chadd 	/* Occasionally, the MAC sends a tx status for the wrong TID. */
4365eb6f0de0SAdrian Chadd 	if (tid != ts.ts_tid) {
4366eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev, "%s: tid %d != hw tid %d\n",
4367eb6f0de0SAdrian Chadd 		    __func__, tid, ts.ts_tid);
4368eb6f0de0SAdrian Chadd 		tx_ok = 0;
4369eb6f0de0SAdrian Chadd 	}
4370b3420862SAdrian Chadd #endif
4371eb6f0de0SAdrian Chadd 
4372eb6f0de0SAdrian Chadd 	/* AR5416 BA bug; this requires an interface reset */
4373eb6f0de0SAdrian Chadd 	if (isaggr && tx_ok && (! hasba)) {
4374eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev,
4375d4365d16SAdrian Chadd 		    "%s: AR5416 bug: hasba=%d; txok=%d, isaggr=%d, "
4376d4365d16SAdrian Chadd 		    "seq_st=%d\n",
4377eb6f0de0SAdrian Chadd 		    __func__, hasba, tx_ok, isaggr, seq_st);
4378eb6f0de0SAdrian Chadd 		/* XXX TODO: schedule an interface reset */
43790f078d63SJohn Baldwin #ifdef ATH_DEBUG
43806abbbae5SAdrian Chadd 		ath_printtxbuf(sc, bf_first,
43816abbbae5SAdrian Chadd 		    sc->sc_ac2q[atid->ac]->axq_qnum, 0, 0);
43820f078d63SJohn Baldwin #endif
4383eb6f0de0SAdrian Chadd 	}
4384eb6f0de0SAdrian Chadd 
4385eb6f0de0SAdrian Chadd 	/*
4386eb6f0de0SAdrian Chadd 	 * Walk the list of frames, figure out which ones were correctly
4387eb6f0de0SAdrian Chadd 	 * sent and which weren't.
4388eb6f0de0SAdrian Chadd 	 */
4389eb6f0de0SAdrian Chadd 	bf = bf_first;
4390eb6f0de0SAdrian Chadd 	nf = bf_first->bf_state.bfs_nframes;
4391eb6f0de0SAdrian Chadd 
4392eb6f0de0SAdrian Chadd 	/* bf_first is going to be invalid once this list is walked */
4393eb6f0de0SAdrian Chadd 	bf_first = NULL;
4394eb6f0de0SAdrian Chadd 
4395eb6f0de0SAdrian Chadd 	/*
4396eb6f0de0SAdrian Chadd 	 * Walk the list of completed frames and determine
4397eb6f0de0SAdrian Chadd 	 * which need to be completed and which need to be
4398eb6f0de0SAdrian Chadd 	 * retransmitted.
4399eb6f0de0SAdrian Chadd 	 *
4400eb6f0de0SAdrian Chadd 	 * For completed frames, the completion functions need
4401eb6f0de0SAdrian Chadd 	 * to be called at the end of this function as the last
4402eb6f0de0SAdrian Chadd 	 * node reference may free the node.
4403eb6f0de0SAdrian Chadd 	 *
4404eb6f0de0SAdrian Chadd 	 * Finally, since the TXQ lock can't be held during the
4405eb6f0de0SAdrian Chadd 	 * completion callback (to avoid lock recursion),
4406eb6f0de0SAdrian Chadd 	 * the completion calls have to be done outside of the
4407eb6f0de0SAdrian Chadd 	 * lock.
4408eb6f0de0SAdrian Chadd 	 */
4409eb6f0de0SAdrian Chadd 	while (bf) {
4410eb6f0de0SAdrian Chadd 		nframes++;
4411d4365d16SAdrian Chadd 		ba_index = ATH_BA_INDEX(seq_st,
4412d4365d16SAdrian Chadd 		    SEQNO(bf->bf_state.bfs_seqno));
4413eb6f0de0SAdrian Chadd 		bf_next = bf->bf_next;
4414eb6f0de0SAdrian Chadd 		bf->bf_next = NULL;	/* Remove it from the aggr list */
4415eb6f0de0SAdrian Chadd 
4416eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4417eb6f0de0SAdrian Chadd 		    "%s: checking bf=%p seqno=%d; ack=%d\n",
4418eb6f0de0SAdrian Chadd 		    __func__, bf, SEQNO(bf->bf_state.bfs_seqno),
4419eb6f0de0SAdrian Chadd 		    ATH_BA_ISSET(ba, ba_index));
4420eb6f0de0SAdrian Chadd 
4421eb6f0de0SAdrian Chadd 		if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
44222d3d4776SAdrian Chadd 			sc->sc_stats.ast_tx_aggr_ok++;
4423eb6f0de0SAdrian Chadd 			ath_tx_update_baw(sc, an, atid, bf);
4424eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_dobaw = 0;
4425eb6f0de0SAdrian Chadd 			if (! bf->bf_state.bfs_addedbaw)
4426eb6f0de0SAdrian Chadd 				device_printf(sc->sc_dev,
4427eb6f0de0SAdrian Chadd 				    "%s: wasn't added: seqno %d\n",
4428eb6f0de0SAdrian Chadd 				    __func__, SEQNO(bf->bf_state.bfs_seqno));
4429eb6f0de0SAdrian Chadd 			bf->bf_next = NULL;
4430eb6f0de0SAdrian Chadd 			TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
4431eb6f0de0SAdrian Chadd 		} else {
44322d3d4776SAdrian Chadd 			sc->sc_stats.ast_tx_aggr_fail++;
4433eb6f0de0SAdrian Chadd 			if (ath_tx_retry_subframe(sc, bf, &bf_q)) {
4434eb6f0de0SAdrian Chadd 				drops++;
4435eb6f0de0SAdrian Chadd 				bf->bf_next = NULL;
4436eb6f0de0SAdrian Chadd 				TAILQ_INSERT_TAIL(&bf_cq, bf, bf_list);
4437eb6f0de0SAdrian Chadd 			}
4438eb6f0de0SAdrian Chadd 			nbad++;
4439eb6f0de0SAdrian Chadd 		}
4440eb6f0de0SAdrian Chadd 		bf = bf_next;
4441eb6f0de0SAdrian Chadd 	}
4442eb6f0de0SAdrian Chadd 
4443eb6f0de0SAdrian Chadd 	/*
4444eb6f0de0SAdrian Chadd 	 * Now that the BAW updates have been done, unlock
4445eb6f0de0SAdrian Chadd 	 *
4446eb6f0de0SAdrian Chadd 	 * txseq is grabbed before the lock is released so we
4447eb6f0de0SAdrian Chadd 	 * have a consistent view of what -was- in the BAW.
4448eb6f0de0SAdrian Chadd 	 * Anything after this point will not yet have been
4449eb6f0de0SAdrian Chadd 	 * TXed.
4450eb6f0de0SAdrian Chadd 	 */
4451eb6f0de0SAdrian Chadd 	txseq = tap->txa_start;
4452375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
4453eb6f0de0SAdrian Chadd 
4454eb6f0de0SAdrian Chadd 	if (nframes != nf)
4455eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev,
4456eb6f0de0SAdrian Chadd 		    "%s: num frames seen=%d; bf nframes=%d\n",
4457eb6f0de0SAdrian Chadd 		    __func__, nframes, nf);
4458eb6f0de0SAdrian Chadd 
4459eb6f0de0SAdrian Chadd 	/*
4460eb6f0de0SAdrian Chadd 	 * Now we know how many frames were bad, call the rate
4461eb6f0de0SAdrian Chadd 	 * control code.
4462eb6f0de0SAdrian Chadd 	 */
4463eb6f0de0SAdrian Chadd 	if (fail == 0)
4464d4365d16SAdrian Chadd 		ath_tx_update_ratectrl(sc, ni, rc, &ts, pktlen, nframes,
4465d4365d16SAdrian Chadd 		    nbad);
4466eb6f0de0SAdrian Chadd 
4467eb6f0de0SAdrian Chadd 	/*
4468eb6f0de0SAdrian Chadd 	 * send bar if we dropped any frames
4469eb6f0de0SAdrian Chadd 	 */
4470eb6f0de0SAdrian Chadd 	if (drops) {
447188b3d483SAdrian Chadd 		/* Suspend the TX queue and get ready to send the BAR */
4472375307d4SAdrian Chadd 		ATH_TX_LOCK(sc);
447388b3d483SAdrian Chadd 		ath_tx_tid_bar_suspend(sc, atid);
4474375307d4SAdrian Chadd 		ATH_TX_UNLOCK(sc);
4475eb6f0de0SAdrian Chadd 	}
4476eb6f0de0SAdrian Chadd 
447739da9d42SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
447839da9d42SAdrian Chadd 	    "%s: txa_start now %d\n", __func__, tap->txa_start);
447939da9d42SAdrian Chadd 
4480375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
448139da9d42SAdrian Chadd 
448239da9d42SAdrian Chadd 	/* Prepend all frames to the beginning of the queue */
4483eb6f0de0SAdrian Chadd 	while ((bf = TAILQ_LAST(&bf_q, ath_bufhead_s)) != NULL) {
4484eb6f0de0SAdrian Chadd 		TAILQ_REMOVE(&bf_q, bf, bf_list);
44853e6cc97fSAdrian Chadd 		ATH_TID_INSERT_HEAD(atid, bf, bf_list);
4486eb6f0de0SAdrian Chadd 	}
4487eb6f0de0SAdrian Chadd 
448839da9d42SAdrian Chadd 	/*
448939da9d42SAdrian Chadd 	 * Reschedule to grab some further frames.
449039da9d42SAdrian Chadd 	 */
449139da9d42SAdrian Chadd 	ath_tx_tid_sched(sc, atid);
4492eb6f0de0SAdrian Chadd 
449388b3d483SAdrian Chadd 	/*
4494f1bc738eSAdrian Chadd 	 * If the queue is filtered, re-schedule as required.
4495f1bc738eSAdrian Chadd 	 *
4496f1bc738eSAdrian Chadd 	 * This is required as there may be a subsequent TX descriptor
4497f1bc738eSAdrian Chadd 	 * for this end-node that has CLRDMASK set, so it's quite possible
4498f1bc738eSAdrian Chadd 	 * that a filtered frame will be followed by a non-filtered
4499f1bc738eSAdrian Chadd 	 * (complete or otherwise) frame.
4500f1bc738eSAdrian Chadd 	 *
4501f1bc738eSAdrian Chadd 	 * XXX should we do this before we complete the frame?
4502f1bc738eSAdrian Chadd 	 */
4503f1bc738eSAdrian Chadd 	if (atid->isfiltered)
4504f1bc738eSAdrian Chadd 		ath_tx_tid_filt_comp_complete(sc, atid);
4505f1bc738eSAdrian Chadd 
4506f1bc738eSAdrian Chadd finish_send_bar:
4507f1bc738eSAdrian Chadd 
4508f1bc738eSAdrian Chadd 	/*
450988b3d483SAdrian Chadd 	 * Send BAR if required
451088b3d483SAdrian Chadd 	 */
451188b3d483SAdrian Chadd 	if (ath_tx_tid_bar_tx_ready(sc, atid))
451288b3d483SAdrian Chadd 		ath_tx_tid_bar_tx(sc, atid);
451339da9d42SAdrian Chadd 
4514375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
451588b3d483SAdrian Chadd 
4516eb6f0de0SAdrian Chadd 	/* Do deferred completion */
4517eb6f0de0SAdrian Chadd 	while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
4518eb6f0de0SAdrian Chadd 		TAILQ_REMOVE(&bf_cq, bf, bf_list);
4519eb6f0de0SAdrian Chadd 		ath_tx_default_comp(sc, bf, 0);
4520eb6f0de0SAdrian Chadd 	}
4521eb6f0de0SAdrian Chadd }
4522eb6f0de0SAdrian Chadd 
4523eb6f0de0SAdrian Chadd /*
4524eb6f0de0SAdrian Chadd  * Handle completion of unaggregated frames in an ADDBA
4525eb6f0de0SAdrian Chadd  * session.
4526eb6f0de0SAdrian Chadd  *
4527eb6f0de0SAdrian Chadd  * Fail is set to 1 if the entry is being freed via a call to
4528eb6f0de0SAdrian Chadd  * ath_tx_draintxq().
4529eb6f0de0SAdrian Chadd  */
4530eb6f0de0SAdrian Chadd static void
4531eb6f0de0SAdrian Chadd ath_tx_aggr_comp_unaggr(struct ath_softc *sc, struct ath_buf *bf, int fail)
4532eb6f0de0SAdrian Chadd {
4533eb6f0de0SAdrian Chadd 	struct ieee80211_node *ni = bf->bf_node;
4534eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
4535eb6f0de0SAdrian Chadd 	int tid = bf->bf_state.bfs_tid;
4536eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
45370aa5c1bbSAdrian Chadd 	struct ath_tx_status ts;
4538f1bc738eSAdrian Chadd 	int drops = 0;
4539eb6f0de0SAdrian Chadd 
4540eb6f0de0SAdrian Chadd 	/*
45410aa5c1bbSAdrian Chadd 	 * Take a copy of this; filtering/cloning the frame may free the
45420aa5c1bbSAdrian Chadd 	 * bf pointer.
45430aa5c1bbSAdrian Chadd 	 */
45440aa5c1bbSAdrian Chadd 	ts = bf->bf_status.ds_txstat;
45450aa5c1bbSAdrian Chadd 
45460aa5c1bbSAdrian Chadd 	/*
4547eb6f0de0SAdrian Chadd 	 * Update rate control status here, before we possibly
4548eb6f0de0SAdrian Chadd 	 * punt to retry or cleanup.
4549eb6f0de0SAdrian Chadd 	 *
4550eb6f0de0SAdrian Chadd 	 * Do it outside of the TXQ lock.
4551eb6f0de0SAdrian Chadd 	 */
4552875a9451SAdrian Chadd 	if (fail == 0 && ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0))
4553eb6f0de0SAdrian Chadd 		ath_tx_update_ratectrl(sc, ni, bf->bf_state.bfs_rc,
4554eb6f0de0SAdrian Chadd 		    &bf->bf_status.ds_txstat,
4555eb6f0de0SAdrian Chadd 		    bf->bf_state.bfs_pktlen,
45560aa5c1bbSAdrian Chadd 		    1, (ts.ts_status == 0) ? 0 : 1);
4557eb6f0de0SAdrian Chadd 
4558eb6f0de0SAdrian Chadd 	/*
4559eb6f0de0SAdrian Chadd 	 * This is called early so atid->hwq_depth can be tracked.
4560eb6f0de0SAdrian Chadd 	 * This unfortunately means that it's released and regrabbed
4561eb6f0de0SAdrian Chadd 	 * during retry and cleanup. That's rather inefficient.
4562eb6f0de0SAdrian Chadd 	 */
4563375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
4564eb6f0de0SAdrian Chadd 
4565eb6f0de0SAdrian Chadd 	if (tid == IEEE80211_NONQOS_TID)
4566eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev, "%s: TID=16!\n", __func__);
4567eb6f0de0SAdrian Chadd 
4568d4365d16SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX,
4569d4365d16SAdrian Chadd 	    "%s: bf=%p: tid=%d, hwq_depth=%d, seqno=%d\n",
4570d4365d16SAdrian Chadd 	    __func__, bf, bf->bf_state.bfs_tid, atid->hwq_depth,
4571d4365d16SAdrian Chadd 	    SEQNO(bf->bf_state.bfs_seqno));
4572eb6f0de0SAdrian Chadd 
4573eb6f0de0SAdrian Chadd 	atid->hwq_depth--;
4574eb6f0de0SAdrian Chadd 	if (atid->hwq_depth < 0)
4575eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev, "%s: hwq_depth < 0: %d\n",
4576eb6f0de0SAdrian Chadd 		    __func__, atid->hwq_depth);
4577eb6f0de0SAdrian Chadd 
4578eb6f0de0SAdrian Chadd 	/*
4579f1bc738eSAdrian Chadd 	 * If the TID is filtered, handle completing the filter
4580f1bc738eSAdrian Chadd 	 * transition before potentially kicking it to the cleanup
4581f1bc738eSAdrian Chadd 	 * function.
4582f1bc738eSAdrian Chadd 	 */
4583f1bc738eSAdrian Chadd 	if (atid->isfiltered)
4584f1bc738eSAdrian Chadd 		ath_tx_tid_filt_comp_complete(sc, atid);
4585f1bc738eSAdrian Chadd 
4586f1bc738eSAdrian Chadd 	/*
4587eb6f0de0SAdrian Chadd 	 * If a cleanup is in progress, punt to comp_cleanup;
4588eb6f0de0SAdrian Chadd 	 * rather than handling it here. It's thus their
4589eb6f0de0SAdrian Chadd 	 * responsibility to clean up, call the completion
4590eb6f0de0SAdrian Chadd 	 * function in net80211, etc.
4591eb6f0de0SAdrian Chadd 	 */
4592eb6f0de0SAdrian Chadd 	if (atid->cleanup_inprogress) {
4593f1bc738eSAdrian Chadd 		if (atid->isfiltered)
4594f1bc738eSAdrian Chadd 			device_printf(sc->sc_dev,
4595f1bc738eSAdrian Chadd 			    "%s: isfiltered=1, normal_comp?\n",
4596f1bc738eSAdrian Chadd 			    __func__);
4597375307d4SAdrian Chadd 		ATH_TX_UNLOCK(sc);
4598d4365d16SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: cleanup_unaggr\n",
4599d4365d16SAdrian Chadd 		    __func__);
4600eb6f0de0SAdrian Chadd 		ath_tx_comp_cleanup_unaggr(sc, bf);
4601eb6f0de0SAdrian Chadd 		return;
4602eb6f0de0SAdrian Chadd 	}
4603eb6f0de0SAdrian Chadd 
4604eb6f0de0SAdrian Chadd 	/*
4605f1bc738eSAdrian Chadd 	 * XXX TODO: how does cleanup, BAR and filtered frame handling
4606f1bc738eSAdrian Chadd 	 * overlap?
4607f1bc738eSAdrian Chadd 	 *
4608f1bc738eSAdrian Chadd 	 * If the frame is filtered OR if it's any failure but
4609f1bc738eSAdrian Chadd 	 * the TID is filtered, the frame must be added to the
4610f1bc738eSAdrian Chadd 	 * filtered frame list.
4611f1bc738eSAdrian Chadd 	 *
4612f1bc738eSAdrian Chadd 	 * However - a busy buffer can't be added to the filtered
4613f1bc738eSAdrian Chadd 	 * list as it will end up being recycled without having
4614f1bc738eSAdrian Chadd 	 * been made available for the hardware.
4615f1bc738eSAdrian Chadd 	 */
46160aa5c1bbSAdrian Chadd 	if ((ts.ts_status & HAL_TXERR_FILT) ||
46170aa5c1bbSAdrian Chadd 	    (ts.ts_status != 0 && atid->isfiltered)) {
4618f1bc738eSAdrian Chadd 		int freeframe;
4619f1bc738eSAdrian Chadd 
4620f1bc738eSAdrian Chadd 		if (fail != 0)
4621f1bc738eSAdrian Chadd 			device_printf(sc->sc_dev,
4622f1bc738eSAdrian Chadd 			    "%s: isfiltered=1, fail=%d\n",
4623f1bc738eSAdrian Chadd 			    __func__,
4624f1bc738eSAdrian Chadd 			    fail);
4625f1bc738eSAdrian Chadd 		freeframe = ath_tx_tid_filt_comp_single(sc, atid, bf);
4626f1bc738eSAdrian Chadd 		if (freeframe) {
4627f1bc738eSAdrian Chadd 			/* Remove from BAW */
4628f1bc738eSAdrian Chadd 			if (bf->bf_state.bfs_addedbaw)
4629f1bc738eSAdrian Chadd 				drops++;
4630f1bc738eSAdrian Chadd 			if (bf->bf_state.bfs_dobaw) {
4631f1bc738eSAdrian Chadd 				ath_tx_update_baw(sc, an, atid, bf);
4632f1bc738eSAdrian Chadd 				if (! bf->bf_state.bfs_addedbaw)
4633f1bc738eSAdrian Chadd 					device_printf(sc->sc_dev,
4634f1bc738eSAdrian Chadd 					    "%s: wasn't added: seqno %d\n",
4635f1bc738eSAdrian Chadd 					    __func__, SEQNO(bf->bf_state.bfs_seqno));
4636f1bc738eSAdrian Chadd 			}
4637f1bc738eSAdrian Chadd 			bf->bf_state.bfs_dobaw = 0;
4638f1bc738eSAdrian Chadd 		}
4639f1bc738eSAdrian Chadd 
4640f1bc738eSAdrian Chadd 		/*
4641f1bc738eSAdrian Chadd 		 * If the frame couldn't be filtered, treat it as a drop and
4642f1bc738eSAdrian Chadd 		 * prepare to send a BAR.
4643f1bc738eSAdrian Chadd 		 */
4644f1bc738eSAdrian Chadd 		if (freeframe && drops)
4645f1bc738eSAdrian Chadd 			ath_tx_tid_bar_suspend(sc, atid);
4646f1bc738eSAdrian Chadd 
4647f1bc738eSAdrian Chadd 		/*
4648f1bc738eSAdrian Chadd 		 * Send BAR if required
4649f1bc738eSAdrian Chadd 		 */
4650f1bc738eSAdrian Chadd 		if (ath_tx_tid_bar_tx_ready(sc, atid))
4651f1bc738eSAdrian Chadd 			ath_tx_tid_bar_tx(sc, atid);
4652f1bc738eSAdrian Chadd 
4653375307d4SAdrian Chadd 		ATH_TX_UNLOCK(sc);
4654f1bc738eSAdrian Chadd 		/*
4655f1bc738eSAdrian Chadd 		 * If freeframe is set, then the frame couldn't be
4656f1bc738eSAdrian Chadd 		 * cloned and bf is still valid.  Just complete/free it.
4657f1bc738eSAdrian Chadd 		 */
4658f1bc738eSAdrian Chadd 		if (freeframe)
4659f1bc738eSAdrian Chadd 			ath_tx_default_comp(sc, bf, fail);
4660f1bc738eSAdrian Chadd 
4661f1bc738eSAdrian Chadd 
4662f1bc738eSAdrian Chadd 		return;
4663f1bc738eSAdrian Chadd 	}
4664f1bc738eSAdrian Chadd 	/*
4665eb6f0de0SAdrian Chadd 	 * Don't bother with the retry check if all frames
4666eb6f0de0SAdrian Chadd 	 * are being failed (eg during queue deletion.)
4667eb6f0de0SAdrian Chadd 	 */
4668e9a6408eSAdrian Chadd #if 0
4669eb6f0de0SAdrian Chadd 	if (fail == 0 && ts->ts_status & HAL_TXERR_XRETRY) {
4670e9a6408eSAdrian Chadd #endif
46710aa5c1bbSAdrian Chadd 	if (fail == 0 && ts.ts_status != 0) {
4672375307d4SAdrian Chadd 		ATH_TX_UNLOCK(sc);
4673d4365d16SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: retry_unaggr\n",
4674d4365d16SAdrian Chadd 		    __func__);
4675eb6f0de0SAdrian Chadd 		ath_tx_aggr_retry_unaggr(sc, bf);
4676eb6f0de0SAdrian Chadd 		return;
4677eb6f0de0SAdrian Chadd 	}
4678eb6f0de0SAdrian Chadd 
4679eb6f0de0SAdrian Chadd 	/* Success? Complete */
4680eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: TID=%d, seqno %d\n",
4681eb6f0de0SAdrian Chadd 	    __func__, tid, SEQNO(bf->bf_state.bfs_seqno));
4682eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_dobaw) {
4683eb6f0de0SAdrian Chadd 		ath_tx_update_baw(sc, an, atid, bf);
4684eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_dobaw = 0;
4685eb6f0de0SAdrian Chadd 		if (! bf->bf_state.bfs_addedbaw)
4686eb6f0de0SAdrian Chadd 			device_printf(sc->sc_dev,
4687eb6f0de0SAdrian Chadd 			    "%s: wasn't added: seqno %d\n",
4688eb6f0de0SAdrian Chadd 			    __func__, SEQNO(bf->bf_state.bfs_seqno));
4689eb6f0de0SAdrian Chadd 	}
4690eb6f0de0SAdrian Chadd 
469188b3d483SAdrian Chadd 	/*
4692f1bc738eSAdrian Chadd 	 * If the queue is filtered, re-schedule as required.
4693f1bc738eSAdrian Chadd 	 *
4694f1bc738eSAdrian Chadd 	 * This is required as there may be a subsequent TX descriptor
4695f1bc738eSAdrian Chadd 	 * for this end-node that has CLRDMASK set, so it's quite possible
4696f1bc738eSAdrian Chadd 	 * that a filtered frame will be followed by a non-filtered
4697f1bc738eSAdrian Chadd 	 * (complete or otherwise) frame.
4698f1bc738eSAdrian Chadd 	 *
4699f1bc738eSAdrian Chadd 	 * XXX should we do this before we complete the frame?
4700f1bc738eSAdrian Chadd 	 */
4701f1bc738eSAdrian Chadd 	if (atid->isfiltered)
4702f1bc738eSAdrian Chadd 		ath_tx_tid_filt_comp_complete(sc, atid);
4703f1bc738eSAdrian Chadd 
4704f1bc738eSAdrian Chadd 	/*
470588b3d483SAdrian Chadd 	 * Send BAR if required
470688b3d483SAdrian Chadd 	 */
470788b3d483SAdrian Chadd 	if (ath_tx_tid_bar_tx_ready(sc, atid))
470888b3d483SAdrian Chadd 		ath_tx_tid_bar_tx(sc, atid);
470988b3d483SAdrian Chadd 
4710375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
4711eb6f0de0SAdrian Chadd 
4712eb6f0de0SAdrian Chadd 	ath_tx_default_comp(sc, bf, fail);
4713eb6f0de0SAdrian Chadd 	/* bf is freed at this point */
4714eb6f0de0SAdrian Chadd }
4715eb6f0de0SAdrian Chadd 
4716eb6f0de0SAdrian Chadd void
4717eb6f0de0SAdrian Chadd ath_tx_aggr_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
4718eb6f0de0SAdrian Chadd {
4719eb6f0de0SAdrian Chadd 	if (bf->bf_state.bfs_aggr)
4720eb6f0de0SAdrian Chadd 		ath_tx_aggr_comp_aggr(sc, bf, fail);
4721eb6f0de0SAdrian Chadd 	else
4722eb6f0de0SAdrian Chadd 		ath_tx_aggr_comp_unaggr(sc, bf, fail);
4723eb6f0de0SAdrian Chadd }
4724eb6f0de0SAdrian Chadd 
4725eb6f0de0SAdrian Chadd /*
4726eb6f0de0SAdrian Chadd  * Schedule some packets from the given node/TID to the hardware.
4727eb6f0de0SAdrian Chadd  *
4728eb6f0de0SAdrian Chadd  * This is the aggregate version.
4729eb6f0de0SAdrian Chadd  */
4730eb6f0de0SAdrian Chadd void
4731eb6f0de0SAdrian Chadd ath_tx_tid_hw_queue_aggr(struct ath_softc *sc, struct ath_node *an,
4732eb6f0de0SAdrian Chadd     struct ath_tid *tid)
4733eb6f0de0SAdrian Chadd {
4734eb6f0de0SAdrian Chadd 	struct ath_buf *bf;
4735eb6f0de0SAdrian Chadd 	struct ath_txq *txq = sc->sc_ac2q[tid->ac];
4736eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
4737eb6f0de0SAdrian Chadd 	ATH_AGGR_STATUS status;
4738eb6f0de0SAdrian Chadd 	ath_bufhead bf_q;
4739eb6f0de0SAdrian Chadd 
4740eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d\n", __func__, tid->tid);
4741375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
4742eb6f0de0SAdrian Chadd 
4743eb6f0de0SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid->tid);
4744eb6f0de0SAdrian Chadd 
4745eb6f0de0SAdrian Chadd 	if (tid->tid == IEEE80211_NONQOS_TID)
4746eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev, "%s: called for TID=NONQOS_TID?\n",
4747eb6f0de0SAdrian Chadd 		    __func__);
4748eb6f0de0SAdrian Chadd 
4749eb6f0de0SAdrian Chadd 	for (;;) {
4750eb6f0de0SAdrian Chadd 		status = ATH_AGGR_DONE;
4751eb6f0de0SAdrian Chadd 
4752eb6f0de0SAdrian Chadd 		/*
4753eb6f0de0SAdrian Chadd 		 * If the upper layer has paused the TID, don't
4754eb6f0de0SAdrian Chadd 		 * queue any further packets.
4755eb6f0de0SAdrian Chadd 		 *
4756eb6f0de0SAdrian Chadd 		 * This can also occur from the completion task because
4757eb6f0de0SAdrian Chadd 		 * of packet loss; but as its serialised with this code,
4758eb6f0de0SAdrian Chadd 		 * it won't "appear" half way through queuing packets.
4759eb6f0de0SAdrian Chadd 		 */
4760eb6f0de0SAdrian Chadd 		if (tid->paused)
4761eb6f0de0SAdrian Chadd 			break;
4762eb6f0de0SAdrian Chadd 
47633e6cc97fSAdrian Chadd 		bf = ATH_TID_FIRST(tid);
4764eb6f0de0SAdrian Chadd 		if (bf == NULL) {
4765eb6f0de0SAdrian Chadd 			break;
4766eb6f0de0SAdrian Chadd 		}
4767eb6f0de0SAdrian Chadd 
4768eb6f0de0SAdrian Chadd 		/*
4769eb6f0de0SAdrian Chadd 		 * If the packet doesn't fall within the BAW (eg a NULL
4770eb6f0de0SAdrian Chadd 		 * data frame), schedule it directly; continue.
4771eb6f0de0SAdrian Chadd 		 */
4772eb6f0de0SAdrian Chadd 		if (! bf->bf_state.bfs_dobaw) {
4773d4365d16SAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4774d4365d16SAdrian Chadd 			    "%s: non-baw packet\n",
4775eb6f0de0SAdrian Chadd 			    __func__);
47763e6cc97fSAdrian Chadd 			ATH_TID_REMOVE(tid, bf, bf_list);
47772a9f83afSAdrian Chadd 
47782a9f83afSAdrian Chadd 			if (bf->bf_state.bfs_nframes > 1)
47792a9f83afSAdrian Chadd 				device_printf(sc->sc_dev,
47802a9f83afSAdrian Chadd 				    "%s: aggr=%d, nframes=%d\n",
47812a9f83afSAdrian Chadd 				    __func__,
47822a9f83afSAdrian Chadd 				    bf->bf_state.bfs_aggr,
47832a9f83afSAdrian Chadd 				    bf->bf_state.bfs_nframes);
47842a9f83afSAdrian Chadd 
47852a9f83afSAdrian Chadd 			/*
47862a9f83afSAdrian Chadd 			 * This shouldn't happen - such frames shouldn't
47872a9f83afSAdrian Chadd 			 * ever have been queued as an aggregate in the
47882a9f83afSAdrian Chadd 			 * first place.  However, make sure the fields
47892a9f83afSAdrian Chadd 			 * are correctly setup just to be totally sure.
47902a9f83afSAdrian Chadd 			 */
4791eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_aggr = 0;
47922a9f83afSAdrian Chadd 			bf->bf_state.bfs_nframes = 1;
47932a9f83afSAdrian Chadd 
47944e81f27cSAdrian Chadd 			/* Update CLRDMASK just before this frame is queued */
47954e81f27cSAdrian Chadd 			ath_tx_update_clrdmask(sc, tid, bf);
47964e81f27cSAdrian Chadd 
4797eb6f0de0SAdrian Chadd 			ath_tx_do_ratelookup(sc, bf);
4798e2e4a2c2SAdrian Chadd 			ath_tx_calc_duration(sc, bf);
4799e2e4a2c2SAdrian Chadd 			ath_tx_calc_protection(sc, bf);
4800eb6f0de0SAdrian Chadd 			ath_tx_set_rtscts(sc, bf);
4801e2e4a2c2SAdrian Chadd 			ath_tx_rate_fill_rcflags(sc, bf);
4802eb6f0de0SAdrian Chadd 			ath_tx_setds(sc, bf);
4803eb6f0de0SAdrian Chadd 			ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
4804eb6f0de0SAdrian Chadd 
4805eb6f0de0SAdrian Chadd 			sc->sc_aggr_stats.aggr_nonbaw_pkt++;
4806eb6f0de0SAdrian Chadd 
4807eb6f0de0SAdrian Chadd 			/* Queue the packet; continue */
4808eb6f0de0SAdrian Chadd 			goto queuepkt;
4809eb6f0de0SAdrian Chadd 		}
4810eb6f0de0SAdrian Chadd 
4811eb6f0de0SAdrian Chadd 		TAILQ_INIT(&bf_q);
4812eb6f0de0SAdrian Chadd 
4813eb6f0de0SAdrian Chadd 		/*
4814eb6f0de0SAdrian Chadd 		 * Do a rate control lookup on the first frame in the
4815eb6f0de0SAdrian Chadd 		 * list. The rate control code needs that to occur
4816eb6f0de0SAdrian Chadd 		 * before it can determine whether to TX.
4817eb6f0de0SAdrian Chadd 		 * It's inaccurate because the rate control code doesn't
4818eb6f0de0SAdrian Chadd 		 * really "do" aggregate lookups, so it only considers
4819eb6f0de0SAdrian Chadd 		 * the size of the first frame.
4820eb6f0de0SAdrian Chadd 		 */
4821eb6f0de0SAdrian Chadd 		ath_tx_do_ratelookup(sc, bf);
4822eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_rc[3].rix = 0;
4823eb6f0de0SAdrian Chadd 		bf->bf_state.bfs_rc[3].tries = 0;
4824e2e4a2c2SAdrian Chadd 
4825e2e4a2c2SAdrian Chadd 		ath_tx_calc_duration(sc, bf);
4826e2e4a2c2SAdrian Chadd 		ath_tx_calc_protection(sc, bf);
4827e2e4a2c2SAdrian Chadd 
4828e2e4a2c2SAdrian Chadd 		ath_tx_set_rtscts(sc, bf);
4829eb6f0de0SAdrian Chadd 		ath_tx_rate_fill_rcflags(sc, bf);
4830eb6f0de0SAdrian Chadd 
4831eb6f0de0SAdrian Chadd 		status = ath_tx_form_aggr(sc, an, tid, &bf_q);
4832eb6f0de0SAdrian Chadd 
4833eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4834eb6f0de0SAdrian Chadd 		    "%s: ath_tx_form_aggr() status=%d\n", __func__, status);
4835eb6f0de0SAdrian Chadd 
4836eb6f0de0SAdrian Chadd 		/*
4837eb6f0de0SAdrian Chadd 		 * No frames to be picked up - out of BAW
4838eb6f0de0SAdrian Chadd 		 */
4839eb6f0de0SAdrian Chadd 		if (TAILQ_EMPTY(&bf_q))
4840eb6f0de0SAdrian Chadd 			break;
4841eb6f0de0SAdrian Chadd 
4842eb6f0de0SAdrian Chadd 		/*
4843eb6f0de0SAdrian Chadd 		 * This assumes that the descriptor list in the ath_bufhead
4844eb6f0de0SAdrian Chadd 		 * are already linked together via bf_next pointers.
4845eb6f0de0SAdrian Chadd 		 */
4846eb6f0de0SAdrian Chadd 		bf = TAILQ_FIRST(&bf_q);
4847eb6f0de0SAdrian Chadd 
4848e2e4a2c2SAdrian Chadd 		if (status == ATH_AGGR_8K_LIMITED)
4849e2e4a2c2SAdrian Chadd 			sc->sc_aggr_stats.aggr_rts_aggr_limited++;
4850e2e4a2c2SAdrian Chadd 
4851eb6f0de0SAdrian Chadd 		/*
4852eb6f0de0SAdrian Chadd 		 * If it's the only frame send as non-aggregate
4853eb6f0de0SAdrian Chadd 		 * assume that ath_tx_form_aggr() has checked
4854eb6f0de0SAdrian Chadd 		 * whether it's in the BAW and added it appropriately.
4855eb6f0de0SAdrian Chadd 		 */
4856eb6f0de0SAdrian Chadd 		if (bf->bf_state.bfs_nframes == 1) {
4857eb6f0de0SAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4858eb6f0de0SAdrian Chadd 			    "%s: single-frame aggregate\n", __func__);
48594e81f27cSAdrian Chadd 
48604e81f27cSAdrian Chadd 			/* Update CLRDMASK just before this frame is queued */
48614e81f27cSAdrian Chadd 			ath_tx_update_clrdmask(sc, tid, bf);
48624e81f27cSAdrian Chadd 
4863eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_aggr = 0;
486421840808SAdrian Chadd 			bf->bf_state.bfs_ndelim = 0;
4865eb6f0de0SAdrian Chadd 			ath_tx_setds(sc, bf);
4866eb6f0de0SAdrian Chadd 			ath_hal_clr11n_aggr(sc->sc_ah, bf->bf_desc);
4867eb6f0de0SAdrian Chadd 			if (status == ATH_AGGR_BAW_CLOSED)
4868eb6f0de0SAdrian Chadd 				sc->sc_aggr_stats.aggr_baw_closed_single_pkt++;
4869eb6f0de0SAdrian Chadd 			else
4870eb6f0de0SAdrian Chadd 				sc->sc_aggr_stats.aggr_single_pkt++;
4871eb6f0de0SAdrian Chadd 		} else {
4872eb6f0de0SAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
4873d4365d16SAdrian Chadd 			    "%s: multi-frame aggregate: %d frames, "
4874d4365d16SAdrian Chadd 			    "length %d\n",
4875eb6f0de0SAdrian Chadd 			     __func__, bf->bf_state.bfs_nframes,
4876eb6f0de0SAdrian Chadd 			    bf->bf_state.bfs_al);
4877eb6f0de0SAdrian Chadd 			bf->bf_state.bfs_aggr = 1;
4878eb6f0de0SAdrian Chadd 			sc->sc_aggr_stats.aggr_pkts[bf->bf_state.bfs_nframes]++;
4879eb6f0de0SAdrian Chadd 			sc->sc_aggr_stats.aggr_aggr_pkt++;
4880eb6f0de0SAdrian Chadd 
48814e81f27cSAdrian Chadd 			/* Update CLRDMASK just before this frame is queued */
48824e81f27cSAdrian Chadd 			ath_tx_update_clrdmask(sc, tid, bf);
48834e81f27cSAdrian Chadd 
4884eb6f0de0SAdrian Chadd 			/*
4885e2e4a2c2SAdrian Chadd 			 * Calculate the duration/protection as required.
4886e2e4a2c2SAdrian Chadd 			 */
4887e2e4a2c2SAdrian Chadd 			ath_tx_calc_duration(sc, bf);
4888e2e4a2c2SAdrian Chadd 			ath_tx_calc_protection(sc, bf);
4889e2e4a2c2SAdrian Chadd 
4890e2e4a2c2SAdrian Chadd 			/*
4891eb6f0de0SAdrian Chadd 			 * Update the rate and rtscts information based on the
4892eb6f0de0SAdrian Chadd 			 * rate decision made by the rate control code;
4893eb6f0de0SAdrian Chadd 			 * the first frame in the aggregate needs it.
4894eb6f0de0SAdrian Chadd 			 */
4895eb6f0de0SAdrian Chadd 			ath_tx_set_rtscts(sc, bf);
4896eb6f0de0SAdrian Chadd 
4897eb6f0de0SAdrian Chadd 			/*
4898eb6f0de0SAdrian Chadd 			 * Setup the relevant descriptor fields
4899eb6f0de0SAdrian Chadd 			 * for aggregation. The first descriptor
4900eb6f0de0SAdrian Chadd 			 * already points to the rest in the chain.
4901eb6f0de0SAdrian Chadd 			 */
4902eb6f0de0SAdrian Chadd 			ath_tx_setds_11n(sc, bf);
4903eb6f0de0SAdrian Chadd 
4904eb6f0de0SAdrian Chadd 		}
4905eb6f0de0SAdrian Chadd 	queuepkt:
4906eb6f0de0SAdrian Chadd 		/* Set completion handler, multi-frame aggregate or not */
4907eb6f0de0SAdrian Chadd 		bf->bf_comp = ath_tx_aggr_comp;
4908eb6f0de0SAdrian Chadd 
4909eb6f0de0SAdrian Chadd 		if (bf->bf_state.bfs_tid == IEEE80211_NONQOS_TID)
4910eb6f0de0SAdrian Chadd 		    device_printf(sc->sc_dev, "%s: TID=16?\n", __func__);
4911eb6f0de0SAdrian Chadd 
4912eb6f0de0SAdrian Chadd 		/* Punt to txq */
4913eb6f0de0SAdrian Chadd 		ath_tx_handoff(sc, txq, bf);
4914eb6f0de0SAdrian Chadd 
4915eb6f0de0SAdrian Chadd 		/* Track outstanding buffer count to hardware */
4916eb6f0de0SAdrian Chadd 		/* aggregates are "one" buffer */
4917eb6f0de0SAdrian Chadd 		tid->hwq_depth++;
4918eb6f0de0SAdrian Chadd 
4919eb6f0de0SAdrian Chadd 		/*
4920eb6f0de0SAdrian Chadd 		 * Break out if ath_tx_form_aggr() indicated
4921eb6f0de0SAdrian Chadd 		 * there can't be any further progress (eg BAW is full.)
4922eb6f0de0SAdrian Chadd 		 * Checking for an empty txq is done above.
4923eb6f0de0SAdrian Chadd 		 *
4924eb6f0de0SAdrian Chadd 		 * XXX locking on txq here?
4925eb6f0de0SAdrian Chadd 		 */
4926eb6f0de0SAdrian Chadd 		if (txq->axq_aggr_depth >= sc->sc_hwq_limit ||
4927eb6f0de0SAdrian Chadd 		    status == ATH_AGGR_BAW_CLOSED)
4928eb6f0de0SAdrian Chadd 			break;
4929eb6f0de0SAdrian Chadd 	}
4930eb6f0de0SAdrian Chadd }
4931eb6f0de0SAdrian Chadd 
4932eb6f0de0SAdrian Chadd /*
4933eb6f0de0SAdrian Chadd  * Schedule some packets from the given node/TID to the hardware.
4934eb6f0de0SAdrian Chadd  */
4935eb6f0de0SAdrian Chadd void
4936eb6f0de0SAdrian Chadd ath_tx_tid_hw_queue_norm(struct ath_softc *sc, struct ath_node *an,
4937eb6f0de0SAdrian Chadd     struct ath_tid *tid)
4938eb6f0de0SAdrian Chadd {
4939eb6f0de0SAdrian Chadd 	struct ath_buf *bf;
4940eb6f0de0SAdrian Chadd 	struct ath_txq *txq = sc->sc_ac2q[tid->ac];
4941eb6f0de0SAdrian Chadd 
4942eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: node %p: TID %d: called\n",
4943eb6f0de0SAdrian Chadd 	    __func__, an, tid->tid);
4944eb6f0de0SAdrian Chadd 
4945375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
4946eb6f0de0SAdrian Chadd 
4947eb6f0de0SAdrian Chadd 	/* Check - is AMPDU pending or running? then print out something */
4948eb6f0de0SAdrian Chadd 	if (ath_tx_ampdu_pending(sc, an, tid->tid))
4949eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev, "%s: tid=%d, ampdu pending?\n",
4950eb6f0de0SAdrian Chadd 		    __func__, tid->tid);
4951eb6f0de0SAdrian Chadd 	if (ath_tx_ampdu_running(sc, an, tid->tid))
4952eb6f0de0SAdrian Chadd 		device_printf(sc->sc_dev, "%s: tid=%d, ampdu running?\n",
4953eb6f0de0SAdrian Chadd 		    __func__, tid->tid);
4954eb6f0de0SAdrian Chadd 
4955eb6f0de0SAdrian Chadd 	for (;;) {
4956eb6f0de0SAdrian Chadd 
4957eb6f0de0SAdrian Chadd 		/*
4958eb6f0de0SAdrian Chadd 		 * If the upper layers have paused the TID, don't
4959eb6f0de0SAdrian Chadd 		 * queue any further packets.
4960eb6f0de0SAdrian Chadd 		 */
4961eb6f0de0SAdrian Chadd 		if (tid->paused)
4962eb6f0de0SAdrian Chadd 			break;
4963eb6f0de0SAdrian Chadd 
49643e6cc97fSAdrian Chadd 		bf = ATH_TID_FIRST(tid);
4965eb6f0de0SAdrian Chadd 		if (bf == NULL) {
4966eb6f0de0SAdrian Chadd 			break;
4967eb6f0de0SAdrian Chadd 		}
4968eb6f0de0SAdrian Chadd 
49693e6cc97fSAdrian Chadd 		ATH_TID_REMOVE(tid, bf, bf_list);
4970eb6f0de0SAdrian Chadd 
4971eb6f0de0SAdrian Chadd 		/* Sanity check! */
4972eb6f0de0SAdrian Chadd 		if (tid->tid != bf->bf_state.bfs_tid) {
4973eb6f0de0SAdrian Chadd 			device_printf(sc->sc_dev, "%s: bfs_tid %d !="
4974eb6f0de0SAdrian Chadd 			    " tid %d\n",
4975eb6f0de0SAdrian Chadd 			    __func__, bf->bf_state.bfs_tid, tid->tid);
4976eb6f0de0SAdrian Chadd 		}
4977eb6f0de0SAdrian Chadd 		/* Normal completion handler */
4978eb6f0de0SAdrian Chadd 		bf->bf_comp = ath_tx_normal_comp;
4979eb6f0de0SAdrian Chadd 
49800c54de88SAdrian Chadd 		/*
49810c54de88SAdrian Chadd 		 * Override this for now, until the non-aggregate
49820c54de88SAdrian Chadd 		 * completion handler correctly handles software retransmits.
49830c54de88SAdrian Chadd 		 */
49840c54de88SAdrian Chadd 		bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
49850c54de88SAdrian Chadd 
49864e81f27cSAdrian Chadd 		/* Update CLRDMASK just before this frame is queued */
49874e81f27cSAdrian Chadd 		ath_tx_update_clrdmask(sc, tid, bf);
49884e81f27cSAdrian Chadd 
4989eb6f0de0SAdrian Chadd 		/* Program descriptors + rate control */
4990eb6f0de0SAdrian Chadd 		ath_tx_do_ratelookup(sc, bf);
4991e2e4a2c2SAdrian Chadd 		ath_tx_calc_duration(sc, bf);
4992e2e4a2c2SAdrian Chadd 		ath_tx_calc_protection(sc, bf);
4993eb6f0de0SAdrian Chadd 		ath_tx_set_rtscts(sc, bf);
4994e2e4a2c2SAdrian Chadd 		ath_tx_rate_fill_rcflags(sc, bf);
4995eb6f0de0SAdrian Chadd 		ath_tx_setds(sc, bf);
4996eb6f0de0SAdrian Chadd 
4997eb6f0de0SAdrian Chadd 		/* Track outstanding buffer count to hardware */
4998eb6f0de0SAdrian Chadd 		/* aggregates are "one" buffer */
4999eb6f0de0SAdrian Chadd 		tid->hwq_depth++;
5000eb6f0de0SAdrian Chadd 
5001eb6f0de0SAdrian Chadd 		/* Punt to hardware or software txq */
5002eb6f0de0SAdrian Chadd 		ath_tx_handoff(sc, txq, bf);
5003eb6f0de0SAdrian Chadd 	}
5004eb6f0de0SAdrian Chadd }
5005eb6f0de0SAdrian Chadd 
5006eb6f0de0SAdrian Chadd /*
5007eb6f0de0SAdrian Chadd  * Schedule some packets to the given hardware queue.
5008eb6f0de0SAdrian Chadd  *
5009eb6f0de0SAdrian Chadd  * This function walks the list of TIDs (ie, ath_node TIDs
5010eb6f0de0SAdrian Chadd  * with queued traffic) and attempts to schedule traffic
5011eb6f0de0SAdrian Chadd  * from them.
5012eb6f0de0SAdrian Chadd  *
5013eb6f0de0SAdrian Chadd  * TID scheduling is implemented as a FIFO, with TIDs being
5014eb6f0de0SAdrian Chadd  * added to the end of the queue after some frames have been
5015eb6f0de0SAdrian Chadd  * scheduled.
5016eb6f0de0SAdrian Chadd  */
5017eb6f0de0SAdrian Chadd void
5018eb6f0de0SAdrian Chadd ath_txq_sched(struct ath_softc *sc, struct ath_txq *txq)
5019eb6f0de0SAdrian Chadd {
5020eb6f0de0SAdrian Chadd 	struct ath_tid *tid, *next, *last;
5021eb6f0de0SAdrian Chadd 
5022375307d4SAdrian Chadd 	ATH_TX_LOCK_ASSERT(sc);
5023eb6f0de0SAdrian Chadd 
5024eb6f0de0SAdrian Chadd 	/*
5025eb6f0de0SAdrian Chadd 	 * Don't schedule if the hardware queue is busy.
5026eb6f0de0SAdrian Chadd 	 * This (hopefully) gives some more time to aggregate
5027eb6f0de0SAdrian Chadd 	 * some packets in the aggregation queue.
5028eb6f0de0SAdrian Chadd 	 */
5029eb6f0de0SAdrian Chadd 	if (txq->axq_aggr_depth >= sc->sc_hwq_limit) {
5030eb6f0de0SAdrian Chadd 		sc->sc_aggr_stats.aggr_sched_nopkt++;
5031eb6f0de0SAdrian Chadd 		return;
5032eb6f0de0SAdrian Chadd 	}
5033eb6f0de0SAdrian Chadd 
5034eb6f0de0SAdrian Chadd 	last = TAILQ_LAST(&txq->axq_tidq, axq_t_s);
5035eb6f0de0SAdrian Chadd 
5036eb6f0de0SAdrian Chadd 	TAILQ_FOREACH_SAFE(tid, &txq->axq_tidq, axq_qelem, next) {
5037eb6f0de0SAdrian Chadd 		/*
5038eb6f0de0SAdrian Chadd 		 * Suspend paused queues here; they'll be resumed
5039eb6f0de0SAdrian Chadd 		 * once the addba completes or times out.
5040eb6f0de0SAdrian Chadd 		 */
5041eb6f0de0SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, paused=%d\n",
5042eb6f0de0SAdrian Chadd 		    __func__, tid->tid, tid->paused);
5043eb6f0de0SAdrian Chadd 		ath_tx_tid_unsched(sc, tid);
5044eb6f0de0SAdrian Chadd 		if (tid->paused) {
5045eb6f0de0SAdrian Chadd 			continue;
5046eb6f0de0SAdrian Chadd 		}
5047eb6f0de0SAdrian Chadd 		if (ath_tx_ampdu_running(sc, tid->an, tid->tid))
5048eb6f0de0SAdrian Chadd 			ath_tx_tid_hw_queue_aggr(sc, tid->an, tid);
5049eb6f0de0SAdrian Chadd 		else
5050eb6f0de0SAdrian Chadd 			ath_tx_tid_hw_queue_norm(sc, tid->an, tid);
5051eb6f0de0SAdrian Chadd 
5052eb6f0de0SAdrian Chadd 		/* Not empty? Re-schedule */
5053eb6f0de0SAdrian Chadd 		if (tid->axq_depth != 0)
5054eb6f0de0SAdrian Chadd 			ath_tx_tid_sched(sc, tid);
5055eb6f0de0SAdrian Chadd 
5056eb6f0de0SAdrian Chadd 		/* Give the software queue time to aggregate more packets */
5057eb6f0de0SAdrian Chadd 		if (txq->axq_aggr_depth >= sc->sc_hwq_limit) {
5058eb6f0de0SAdrian Chadd 			break;
5059eb6f0de0SAdrian Chadd 		}
5060eb6f0de0SAdrian Chadd 
5061eb6f0de0SAdrian Chadd 		/*
5062eb6f0de0SAdrian Chadd 		 * If this was the last entry on the original list, stop.
5063eb6f0de0SAdrian Chadd 		 * Otherwise nodes that have been rescheduled onto the end
5064eb6f0de0SAdrian Chadd 		 * of the TID FIFO list will just keep being rescheduled.
5065eb6f0de0SAdrian Chadd 		 */
5066eb6f0de0SAdrian Chadd 		if (tid == last)
5067eb6f0de0SAdrian Chadd 			break;
5068eb6f0de0SAdrian Chadd 	}
5069eb6f0de0SAdrian Chadd }
5070eb6f0de0SAdrian Chadd 
5071eb6f0de0SAdrian Chadd /*
5072eb6f0de0SAdrian Chadd  * TX addba handling
5073eb6f0de0SAdrian Chadd  */
5074eb6f0de0SAdrian Chadd 
5075eb6f0de0SAdrian Chadd /*
5076eb6f0de0SAdrian Chadd  * Return net80211 TID struct pointer, or NULL for none
5077eb6f0de0SAdrian Chadd  */
5078eb6f0de0SAdrian Chadd struct ieee80211_tx_ampdu *
5079eb6f0de0SAdrian Chadd ath_tx_get_tx_tid(struct ath_node *an, int tid)
5080eb6f0de0SAdrian Chadd {
5081eb6f0de0SAdrian Chadd 	struct ieee80211_node *ni = &an->an_node;
5082eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
5083eb6f0de0SAdrian Chadd 
5084eb6f0de0SAdrian Chadd 	if (tid == IEEE80211_NONQOS_TID)
5085eb6f0de0SAdrian Chadd 		return NULL;
5086eb6f0de0SAdrian Chadd 
50872aa563dfSAdrian Chadd 	tap = &ni->ni_tx_ampdu[tid];
5088eb6f0de0SAdrian Chadd 	return tap;
5089eb6f0de0SAdrian Chadd }
5090eb6f0de0SAdrian Chadd 
5091eb6f0de0SAdrian Chadd /*
5092eb6f0de0SAdrian Chadd  * Is AMPDU-TX running?
5093eb6f0de0SAdrian Chadd  */
5094eb6f0de0SAdrian Chadd static int
5095eb6f0de0SAdrian Chadd ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an, int tid)
5096eb6f0de0SAdrian Chadd {
5097eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
5098eb6f0de0SAdrian Chadd 
5099eb6f0de0SAdrian Chadd 	if (tid == IEEE80211_NONQOS_TID)
5100eb6f0de0SAdrian Chadd 		return 0;
5101eb6f0de0SAdrian Chadd 
5102eb6f0de0SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid);
5103eb6f0de0SAdrian Chadd 	if (tap == NULL)
5104eb6f0de0SAdrian Chadd 		return 0;	/* Not valid; default to not running */
5105eb6f0de0SAdrian Chadd 
5106eb6f0de0SAdrian Chadd 	return !! (tap->txa_flags & IEEE80211_AGGR_RUNNING);
5107eb6f0de0SAdrian Chadd }
5108eb6f0de0SAdrian Chadd 
5109eb6f0de0SAdrian Chadd /*
5110eb6f0de0SAdrian Chadd  * Is AMPDU-TX negotiation pending?
5111eb6f0de0SAdrian Chadd  */
5112eb6f0de0SAdrian Chadd static int
5113eb6f0de0SAdrian Chadd ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an, int tid)
5114eb6f0de0SAdrian Chadd {
5115eb6f0de0SAdrian Chadd 	struct ieee80211_tx_ampdu *tap;
5116eb6f0de0SAdrian Chadd 
5117eb6f0de0SAdrian Chadd 	if (tid == IEEE80211_NONQOS_TID)
5118eb6f0de0SAdrian Chadd 		return 0;
5119eb6f0de0SAdrian Chadd 
5120eb6f0de0SAdrian Chadd 	tap = ath_tx_get_tx_tid(an, tid);
5121eb6f0de0SAdrian Chadd 	if (tap == NULL)
5122eb6f0de0SAdrian Chadd 		return 0;	/* Not valid; default to not pending */
5123eb6f0de0SAdrian Chadd 
5124eb6f0de0SAdrian Chadd 	return !! (tap->txa_flags & IEEE80211_AGGR_XCHGPEND);
5125eb6f0de0SAdrian Chadd }
5126eb6f0de0SAdrian Chadd 
5127eb6f0de0SAdrian Chadd /*
5128eb6f0de0SAdrian Chadd  * Is AMPDU-TX pending for the given TID?
5129eb6f0de0SAdrian Chadd  */
5130eb6f0de0SAdrian Chadd 
5131eb6f0de0SAdrian Chadd 
5132eb6f0de0SAdrian Chadd /*
5133eb6f0de0SAdrian Chadd  * Method to handle sending an ADDBA request.
5134eb6f0de0SAdrian Chadd  *
5135eb6f0de0SAdrian Chadd  * We tap this so the relevant flags can be set to pause the TID
5136eb6f0de0SAdrian Chadd  * whilst waiting for the response.
5137eb6f0de0SAdrian Chadd  *
5138eb6f0de0SAdrian Chadd  * XXX there's no timeout handler we can override?
5139eb6f0de0SAdrian Chadd  */
5140eb6f0de0SAdrian Chadd int
5141eb6f0de0SAdrian Chadd ath_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
5142eb6f0de0SAdrian Chadd     int dialogtoken, int baparamset, int batimeout)
5143eb6f0de0SAdrian Chadd {
5144eb6f0de0SAdrian Chadd 	struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
51452aa563dfSAdrian Chadd 	int tid = tap->txa_tid;
5146eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
5147eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
5148eb6f0de0SAdrian Chadd 
5149eb6f0de0SAdrian Chadd 	/*
5150eb6f0de0SAdrian Chadd 	 * XXX danger Will Robinson!
5151eb6f0de0SAdrian Chadd 	 *
5152eb6f0de0SAdrian Chadd 	 * Although the taskqueue may be running and scheduling some more
5153eb6f0de0SAdrian Chadd 	 * packets, these should all be _before_ the addba sequence number.
5154eb6f0de0SAdrian Chadd 	 * However, net80211 will keep self-assigning sequence numbers
5155eb6f0de0SAdrian Chadd 	 * until addba has been negotiated.
5156eb6f0de0SAdrian Chadd 	 *
5157eb6f0de0SAdrian Chadd 	 * In the past, these packets would be "paused" (which still works
5158eb6f0de0SAdrian Chadd 	 * fine, as they're being scheduled to the driver in the same
5159eb6f0de0SAdrian Chadd 	 * serialised method which is calling the addba request routine)
5160eb6f0de0SAdrian Chadd 	 * and when the aggregation session begins, they'll be dequeued
5161eb6f0de0SAdrian Chadd 	 * as aggregate packets and added to the BAW. However, now there's
5162eb6f0de0SAdrian Chadd 	 * a "bf->bf_state.bfs_dobaw" flag, and this isn't set for these
5163eb6f0de0SAdrian Chadd 	 * packets. Thus they never get included in the BAW tracking and
5164eb6f0de0SAdrian Chadd 	 * this can cause the initial burst of packets after the addba
5165eb6f0de0SAdrian Chadd 	 * negotiation to "hang", as they quickly fall outside the BAW.
5166eb6f0de0SAdrian Chadd 	 *
5167eb6f0de0SAdrian Chadd 	 * The "eventual" solution should be to tag these packets with
5168eb6f0de0SAdrian Chadd 	 * dobaw. Although net80211 has given us a sequence number,
5169eb6f0de0SAdrian Chadd 	 * it'll be "after" the left edge of the BAW and thus it'll
5170eb6f0de0SAdrian Chadd 	 * fall within it.
5171eb6f0de0SAdrian Chadd 	 */
5172375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
5173d3a6425bSAdrian Chadd 	/*
5174d3a6425bSAdrian Chadd 	 * This is a bit annoying.  Until net80211 HT code inherits some
5175d3a6425bSAdrian Chadd 	 * (any) locking, we may have this called in parallel BUT only
5176d3a6425bSAdrian Chadd 	 * one response/timeout will be called.  Grr.
5177d3a6425bSAdrian Chadd 	 */
5178d3a6425bSAdrian Chadd 	if (atid->addba_tx_pending == 0) {
5179eb6f0de0SAdrian Chadd 		ath_tx_tid_pause(sc, atid);
5180d3a6425bSAdrian Chadd 		atid->addba_tx_pending = 1;
5181d3a6425bSAdrian Chadd 	}
5182375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
5183eb6f0de0SAdrian Chadd 
5184eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
5185eb6f0de0SAdrian Chadd 	    "%s: called; dialogtoken=%d, baparamset=%d, batimeout=%d\n",
5186eb6f0de0SAdrian Chadd 	    __func__, dialogtoken, baparamset, batimeout);
5187eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
5188eb6f0de0SAdrian Chadd 	    "%s: txa_start=%d, ni_txseqs=%d\n",
5189eb6f0de0SAdrian Chadd 	    __func__, tap->txa_start, ni->ni_txseqs[tid]);
5190eb6f0de0SAdrian Chadd 
5191eb6f0de0SAdrian Chadd 	return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
5192eb6f0de0SAdrian Chadd 	    batimeout);
5193eb6f0de0SAdrian Chadd }
5194eb6f0de0SAdrian Chadd 
5195eb6f0de0SAdrian Chadd /*
5196eb6f0de0SAdrian Chadd  * Handle an ADDBA response.
5197eb6f0de0SAdrian Chadd  *
5198eb6f0de0SAdrian Chadd  * We unpause the queue so TX'ing can resume.
5199eb6f0de0SAdrian Chadd  *
5200eb6f0de0SAdrian Chadd  * Any packets TX'ed from this point should be "aggregate" (whether
5201eb6f0de0SAdrian Chadd  * aggregate or not) so the BAW is updated.
5202eb6f0de0SAdrian Chadd  *
5203eb6f0de0SAdrian Chadd  * Note! net80211 keeps self-assigning sequence numbers until
5204eb6f0de0SAdrian Chadd  * ampdu is negotiated. This means the initially-negotiated BAW left
5205eb6f0de0SAdrian Chadd  * edge won't match the ni->ni_txseq.
5206eb6f0de0SAdrian Chadd  *
5207eb6f0de0SAdrian Chadd  * So, being very dirty, the BAW left edge is "slid" here to match
5208eb6f0de0SAdrian Chadd  * ni->ni_txseq.
5209eb6f0de0SAdrian Chadd  *
5210eb6f0de0SAdrian Chadd  * What likely SHOULD happen is that all packets subsequent to the
5211eb6f0de0SAdrian Chadd  * addba request should be tagged as aggregate and queued as non-aggregate
5212eb6f0de0SAdrian Chadd  * frames; thus updating the BAW. For now though, I'll just slide the
5213eb6f0de0SAdrian Chadd  * window.
5214eb6f0de0SAdrian Chadd  */
5215eb6f0de0SAdrian Chadd int
5216eb6f0de0SAdrian Chadd ath_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
5217eb6f0de0SAdrian Chadd     int status, int code, int batimeout)
5218eb6f0de0SAdrian Chadd {
5219eb6f0de0SAdrian Chadd 	struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
52202aa563dfSAdrian Chadd 	int tid = tap->txa_tid;
5221eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
5222eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
5223eb6f0de0SAdrian Chadd 	int r;
5224eb6f0de0SAdrian Chadd 
5225eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
5226eb6f0de0SAdrian Chadd 	    "%s: called; status=%d, code=%d, batimeout=%d\n", __func__,
5227eb6f0de0SAdrian Chadd 	    status, code, batimeout);
5228eb6f0de0SAdrian Chadd 
5229eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
5230eb6f0de0SAdrian Chadd 	    "%s: txa_start=%d, ni_txseqs=%d\n",
5231eb6f0de0SAdrian Chadd 	    __func__, tap->txa_start, ni->ni_txseqs[tid]);
5232eb6f0de0SAdrian Chadd 
5233eb6f0de0SAdrian Chadd 	/*
5234eb6f0de0SAdrian Chadd 	 * Call this first, so the interface flags get updated
5235eb6f0de0SAdrian Chadd 	 * before the TID is unpaused. Otherwise a race condition
5236eb6f0de0SAdrian Chadd 	 * exists where the unpaused TID still doesn't yet have
5237eb6f0de0SAdrian Chadd 	 * IEEE80211_AGGR_RUNNING set.
5238eb6f0de0SAdrian Chadd 	 */
5239eb6f0de0SAdrian Chadd 	r = sc->sc_addba_response(ni, tap, status, code, batimeout);
5240eb6f0de0SAdrian Chadd 
5241375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
5242d3a6425bSAdrian Chadd 	atid->addba_tx_pending = 0;
5243eb6f0de0SAdrian Chadd 	/*
5244eb6f0de0SAdrian Chadd 	 * XXX dirty!
5245eb6f0de0SAdrian Chadd 	 * Slide the BAW left edge to wherever net80211 left it for us.
5246eb6f0de0SAdrian Chadd 	 * Read above for more information.
5247eb6f0de0SAdrian Chadd 	 */
5248eb6f0de0SAdrian Chadd 	tap->txa_start = ni->ni_txseqs[tid];
5249eb6f0de0SAdrian Chadd 	ath_tx_tid_resume(sc, atid);
5250375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
5251eb6f0de0SAdrian Chadd 	return r;
5252eb6f0de0SAdrian Chadd }
5253eb6f0de0SAdrian Chadd 
5254eb6f0de0SAdrian Chadd 
5255eb6f0de0SAdrian Chadd /*
5256eb6f0de0SAdrian Chadd  * Stop ADDBA on a queue.
52578405fe86SAdrian Chadd  *
52588405fe86SAdrian Chadd  * This can be called whilst BAR TX is currently active on the queue,
52598405fe86SAdrian Chadd  * so make sure this is unblocked before continuing.
5260eb6f0de0SAdrian Chadd  */
5261eb6f0de0SAdrian Chadd void
5262eb6f0de0SAdrian Chadd ath_addba_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
5263eb6f0de0SAdrian Chadd {
5264eb6f0de0SAdrian Chadd 	struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
52652aa563dfSAdrian Chadd 	int tid = tap->txa_tid;
5266eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
5267eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
5268eb6f0de0SAdrian Chadd 
5269eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: called\n", __func__);
5270eb6f0de0SAdrian Chadd 
52718405fe86SAdrian Chadd 	/*
52728405fe86SAdrian Chadd 	 * Pause TID traffic early, so there aren't any races
52738405fe86SAdrian Chadd 	 * Unblock the pending BAR held traffic, if it's currently paused.
52748405fe86SAdrian Chadd 	 */
5275375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
5276eb6f0de0SAdrian Chadd 	ath_tx_tid_pause(sc, atid);
52778405fe86SAdrian Chadd 	if (atid->bar_wait) {
52788405fe86SAdrian Chadd 		/*
52798405fe86SAdrian Chadd 		 * bar_unsuspend() expects bar_tx == 1, as it should be
52808405fe86SAdrian Chadd 		 * called from the TX completion path.  This quietens
52818405fe86SAdrian Chadd 		 * the warning.  It's cleared for us anyway.
52828405fe86SAdrian Chadd 		 */
52838405fe86SAdrian Chadd 		atid->bar_tx = 1;
52848405fe86SAdrian Chadd 		ath_tx_tid_bar_unsuspend(sc, atid);
52858405fe86SAdrian Chadd 	}
5286375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
5287eb6f0de0SAdrian Chadd 
5288eb6f0de0SAdrian Chadd 	/* There's no need to hold the TXQ lock here */
5289eb6f0de0SAdrian Chadd 	sc->sc_addba_stop(ni, tap);
5290eb6f0de0SAdrian Chadd 
5291eb6f0de0SAdrian Chadd 	/*
52924dfd4507SAdrian Chadd 	 * ath_tx_tid_cleanup will resume the TID if possible, otherwise
5293eb6f0de0SAdrian Chadd 	 * it'll set the cleanup flag, and it'll be unpaused once
5294eb6f0de0SAdrian Chadd 	 * things have been cleaned up.
5295eb6f0de0SAdrian Chadd 	 */
52964dfd4507SAdrian Chadd 	ath_tx_tid_cleanup(sc, an, tid);
5297eb6f0de0SAdrian Chadd }
5298eb6f0de0SAdrian Chadd 
5299eb6f0de0SAdrian Chadd /*
5300eb6f0de0SAdrian Chadd  * Note: net80211 bar_timeout() doesn't call this function on BAR failure;
5301eb6f0de0SAdrian Chadd  * it simply tears down the aggregation session. Ew.
5302eb6f0de0SAdrian Chadd  *
5303eb6f0de0SAdrian Chadd  * It however will call ieee80211_ampdu_stop() which will call
5304eb6f0de0SAdrian Chadd  * ic->ic_addba_stop().
5305eb6f0de0SAdrian Chadd  *
5306eb6f0de0SAdrian Chadd  * XXX This uses a hard-coded max BAR count value; the whole
5307eb6f0de0SAdrian Chadd  * XXX BAR TX success or failure should be better handled!
5308eb6f0de0SAdrian Chadd  */
5309eb6f0de0SAdrian Chadd void
5310eb6f0de0SAdrian Chadd ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
5311eb6f0de0SAdrian Chadd     int status)
5312eb6f0de0SAdrian Chadd {
5313eb6f0de0SAdrian Chadd 	struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
53142aa563dfSAdrian Chadd 	int tid = tap->txa_tid;
5315eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
5316eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
5317eb6f0de0SAdrian Chadd 	int attempts = tap->txa_attempts;
5318eb6f0de0SAdrian Chadd 
53190e22ed0eSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
5320e60c4fc2SAdrian Chadd 	    "%s: called; tap=%p, atid=%p, txa_tid=%d, atid->tid=%d, status=%d, attempts=%d\n",
53210e22ed0eSAdrian Chadd 	    __func__,
5322e60c4fc2SAdrian Chadd 	    tap,
5323e60c4fc2SAdrian Chadd 	    atid,
5324e60c4fc2SAdrian Chadd 	    tap->txa_tid,
5325e60c4fc2SAdrian Chadd 	    atid->tid,
53260e22ed0eSAdrian Chadd 	    status,
53270e22ed0eSAdrian Chadd 	    attempts);
5328eb6f0de0SAdrian Chadd 
5329eb6f0de0SAdrian Chadd 	/* Note: This may update the BAW details */
5330eb6f0de0SAdrian Chadd 	sc->sc_bar_response(ni, tap, status);
5331eb6f0de0SAdrian Chadd 
5332eb6f0de0SAdrian Chadd 	/* Unpause the TID */
5333eb6f0de0SAdrian Chadd 	/*
5334eb6f0de0SAdrian Chadd 	 * XXX if this is attempt=50, the TID will be downgraded
5335eb6f0de0SAdrian Chadd 	 * XXX to a non-aggregate session. So we must unpause the
5336eb6f0de0SAdrian Chadd 	 * XXX TID here or it'll never be done.
5337088d8b81SAdrian Chadd 	 *
5338088d8b81SAdrian Chadd 	 * Also, don't call it if bar_tx/bar_wait are 0; something
5339088d8b81SAdrian Chadd 	 * has beaten us to the punch? (XXX figure out what?)
5340eb6f0de0SAdrian Chadd 	 */
5341eb6f0de0SAdrian Chadd 	if (status == 0 || attempts == 50) {
5342375307d4SAdrian Chadd 		ATH_TX_LOCK(sc);
5343088d8b81SAdrian Chadd 		if (atid->bar_tx == 0 || atid->bar_wait == 0)
5344088d8b81SAdrian Chadd 			device_printf(sc->sc_dev,
5345088d8b81SAdrian Chadd 			    "%s: huh? bar_tx=%d, bar_wait=%d\n",
5346088d8b81SAdrian Chadd 			    __func__,
5347088d8b81SAdrian Chadd 			    atid->bar_tx, atid->bar_wait);
5348088d8b81SAdrian Chadd 		else
534988b3d483SAdrian Chadd 			ath_tx_tid_bar_unsuspend(sc, atid);
5350375307d4SAdrian Chadd 		ATH_TX_UNLOCK(sc);
5351eb6f0de0SAdrian Chadd 	}
5352eb6f0de0SAdrian Chadd }
5353eb6f0de0SAdrian Chadd 
5354eb6f0de0SAdrian Chadd /*
5355eb6f0de0SAdrian Chadd  * This is called whenever the pending ADDBA request times out.
5356eb6f0de0SAdrian Chadd  * Unpause and reschedule the TID.
5357eb6f0de0SAdrian Chadd  */
5358eb6f0de0SAdrian Chadd void
5359eb6f0de0SAdrian Chadd ath_addba_response_timeout(struct ieee80211_node *ni,
5360eb6f0de0SAdrian Chadd     struct ieee80211_tx_ampdu *tap)
5361eb6f0de0SAdrian Chadd {
5362eb6f0de0SAdrian Chadd 	struct ath_softc *sc = ni->ni_ic->ic_ifp->if_softc;
53632aa563dfSAdrian Chadd 	int tid = tap->txa_tid;
5364eb6f0de0SAdrian Chadd 	struct ath_node *an = ATH_NODE(ni);
5365eb6f0de0SAdrian Chadd 	struct ath_tid *atid = &an->an_tid[tid];
5366eb6f0de0SAdrian Chadd 
5367eb6f0de0SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
5368eb6f0de0SAdrian Chadd 	    "%s: called; resuming\n", __func__);
5369eb6f0de0SAdrian Chadd 
5370375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
5371d3a6425bSAdrian Chadd 	atid->addba_tx_pending = 0;
5372375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
5373d3a6425bSAdrian Chadd 
5374eb6f0de0SAdrian Chadd 	/* Note: This updates the aggregate state to (again) pending */
5375eb6f0de0SAdrian Chadd 	sc->sc_addba_response_timeout(ni, tap);
5376eb6f0de0SAdrian Chadd 
5377eb6f0de0SAdrian Chadd 	/* Unpause the TID; which reschedules it */
5378375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
5379eb6f0de0SAdrian Chadd 	ath_tx_tid_resume(sc, atid);
5380375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
5381eb6f0de0SAdrian Chadd }
53823fdfc330SAdrian Chadd 
53830eb81626SAdrian Chadd /*
53840eb81626SAdrian Chadd  * Check if a node is asleep or not.
53850eb81626SAdrian Chadd  */
5386548a605dSAdrian Chadd int
53870eb81626SAdrian Chadd ath_tx_node_is_asleep(struct ath_softc *sc, struct ath_node *an)
53880eb81626SAdrian Chadd {
53890eb81626SAdrian Chadd 
53900eb81626SAdrian Chadd 	ATH_NODE_LOCK_ASSERT(an);
53910eb81626SAdrian Chadd 
53920eb81626SAdrian Chadd 	return (an->an_is_powersave);
53930eb81626SAdrian Chadd }
53940eb81626SAdrian Chadd 
53950eb81626SAdrian Chadd /*
53960eb81626SAdrian Chadd  * Mark a node as currently "in powersaving."
53970eb81626SAdrian Chadd  * This suspends all traffic on the node.
53980eb81626SAdrian Chadd  *
53990eb81626SAdrian Chadd  * This must be called with the node/tx locks free.
54000eb81626SAdrian Chadd  *
54010eb81626SAdrian Chadd  * XXX TODO: the locking silliness below is due to how the node
54020eb81626SAdrian Chadd  * locking currently works.  Right now, the node lock is grabbed
54030eb81626SAdrian Chadd  * to do rate control lookups and these are done with the TX
54040eb81626SAdrian Chadd  * queue lock held.  This means the node lock can't be grabbed
54050eb81626SAdrian Chadd  * first here or a LOR will occur.
54060eb81626SAdrian Chadd  *
54070eb81626SAdrian Chadd  * Eventually (hopefully!) the TX path code will only grab
54080eb81626SAdrian Chadd  * the TXQ lock when transmitting and the ath_node lock when
54090eb81626SAdrian Chadd  * doing node/TID operations.  There are other complications -
54100eb81626SAdrian Chadd  * the sched/unsched operations involve walking the per-txq
54110eb81626SAdrian Chadd  * 'active tid' list and this requires both locks to be held.
54120eb81626SAdrian Chadd  */
54130eb81626SAdrian Chadd void
54140eb81626SAdrian Chadd ath_tx_node_sleep(struct ath_softc *sc, struct ath_node *an)
54150eb81626SAdrian Chadd {
54160eb81626SAdrian Chadd 	struct ath_tid *atid;
54170eb81626SAdrian Chadd 	struct ath_txq *txq;
54180eb81626SAdrian Chadd 	int tid;
54190eb81626SAdrian Chadd 
54200eb81626SAdrian Chadd 	ATH_NODE_UNLOCK_ASSERT(an);
54210eb81626SAdrian Chadd 
54220eb81626SAdrian Chadd 	/*
54230eb81626SAdrian Chadd 	 * It's possible that a parallel call to ath_tx_node_wakeup()
54240eb81626SAdrian Chadd 	 * will unpause these queues.
54250eb81626SAdrian Chadd 	 *
54260eb81626SAdrian Chadd 	 * The node lock can't just be grabbed here, as there's places
54270eb81626SAdrian Chadd 	 * in the driver where the node lock is grabbed _within_ a
54280eb81626SAdrian Chadd 	 * TXQ lock.
54290eb81626SAdrian Chadd 	 * So, we do this delicately and unwind state if needed.
54300eb81626SAdrian Chadd 	 *
54310eb81626SAdrian Chadd 	 * + Pause all the queues
54320eb81626SAdrian Chadd 	 * + Grab the node lock
54330eb81626SAdrian Chadd 	 * + If the queue is already asleep, unpause and quit
54340eb81626SAdrian Chadd 	 * + else just mark as asleep.
54350eb81626SAdrian Chadd 	 *
54360eb81626SAdrian Chadd 	 * A parallel sleep() call will just pause and then
54370eb81626SAdrian Chadd 	 * find they're already paused, so undo it.
54380eb81626SAdrian Chadd 	 *
54390eb81626SAdrian Chadd 	 * A parallel wakeup() call will check if asleep is 1
54400eb81626SAdrian Chadd 	 * and if it's not (ie, it's 0), it'll treat it as already
54410eb81626SAdrian Chadd 	 * being awake. If it's 1, it'll mark it as 0 and then
54420eb81626SAdrian Chadd 	 * unpause everything.
54430eb81626SAdrian Chadd 	 *
54440eb81626SAdrian Chadd 	 * (Talk about a delicate hack.)
54450eb81626SAdrian Chadd 	 */
54460eb81626SAdrian Chadd 
54470eb81626SAdrian Chadd 	/* Suspend all traffic on the node */
5448375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
54490eb81626SAdrian Chadd 	for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) {
54500eb81626SAdrian Chadd 		atid = &an->an_tid[tid];
54510eb81626SAdrian Chadd 		txq = sc->sc_ac2q[atid->ac];
54520eb81626SAdrian Chadd 
54530eb81626SAdrian Chadd 		ath_tx_tid_pause(sc, atid);
54540eb81626SAdrian Chadd 	}
5455375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
54560eb81626SAdrian Chadd 
54570eb81626SAdrian Chadd 	ATH_NODE_LOCK(an);
54580eb81626SAdrian Chadd 
54590eb81626SAdrian Chadd 	/* In case of concurrency races from net80211.. */
54600eb81626SAdrian Chadd 	if (an->an_is_powersave == 1) {
54610eb81626SAdrian Chadd 		ATH_NODE_UNLOCK(an);
54620eb81626SAdrian Chadd 		device_printf(sc->sc_dev,
54630eb81626SAdrian Chadd 		    "%s: an=%p: node was already asleep\n",
54640eb81626SAdrian Chadd 		    __func__, an);
5465375307d4SAdrian Chadd 		ATH_TX_LOCK(sc);
54660eb81626SAdrian Chadd 		for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) {
54670eb81626SAdrian Chadd 			atid = &an->an_tid[tid];
54680eb81626SAdrian Chadd 			txq = sc->sc_ac2q[atid->ac];
54690eb81626SAdrian Chadd 
54700eb81626SAdrian Chadd 			ath_tx_tid_resume(sc, atid);
54710eb81626SAdrian Chadd 		}
5472375307d4SAdrian Chadd 		ATH_TX_UNLOCK(sc);
54730eb81626SAdrian Chadd 		return;
54740eb81626SAdrian Chadd 	}
54750eb81626SAdrian Chadd 
54760eb81626SAdrian Chadd 	/* Mark node as in powersaving */
54770eb81626SAdrian Chadd 	an->an_is_powersave = 1;
54780eb81626SAdrian Chadd 
54790eb81626SAdrian Chadd 	ATH_NODE_UNLOCK(an);
54800eb81626SAdrian Chadd }
54810eb81626SAdrian Chadd 
54820eb81626SAdrian Chadd /*
54830eb81626SAdrian Chadd  * Mark a node as currently "awake."
54840eb81626SAdrian Chadd  * This resumes all traffic to the node.
54850eb81626SAdrian Chadd  */
54860eb81626SAdrian Chadd void
54870eb81626SAdrian Chadd ath_tx_node_wakeup(struct ath_softc *sc, struct ath_node *an)
54880eb81626SAdrian Chadd {
54890eb81626SAdrian Chadd 	struct ath_tid *atid;
54900eb81626SAdrian Chadd 	struct ath_txq *txq;
54910eb81626SAdrian Chadd 	int tid;
54920eb81626SAdrian Chadd 
54930eb81626SAdrian Chadd 	ATH_NODE_UNLOCK_ASSERT(an);
54940eb81626SAdrian Chadd 	ATH_NODE_LOCK(an);
54950eb81626SAdrian Chadd 
54960eb81626SAdrian Chadd 	/* In case of concurrency races from net80211.. */
54970eb81626SAdrian Chadd 	if (an->an_is_powersave == 0) {
54980eb81626SAdrian Chadd 		ATH_NODE_UNLOCK(an);
54990eb81626SAdrian Chadd 		device_printf(sc->sc_dev,
55000eb81626SAdrian Chadd 		    "%s: an=%p: node was already awake\n",
55010eb81626SAdrian Chadd 		    __func__, an);
55020eb81626SAdrian Chadd 		return;
55030eb81626SAdrian Chadd 	}
55040eb81626SAdrian Chadd 
55050eb81626SAdrian Chadd 	/* Mark node as awake */
55060eb81626SAdrian Chadd 	an->an_is_powersave = 0;
55070eb81626SAdrian Chadd 
55080eb81626SAdrian Chadd 	ATH_NODE_UNLOCK(an);
55090eb81626SAdrian Chadd 
5510375307d4SAdrian Chadd 	ATH_TX_LOCK(sc);
55110eb81626SAdrian Chadd 	for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) {
55120eb81626SAdrian Chadd 		atid = &an->an_tid[tid];
55130eb81626SAdrian Chadd 		txq = sc->sc_ac2q[atid->ac];
55140eb81626SAdrian Chadd 
55150eb81626SAdrian Chadd 		ath_tx_tid_resume(sc, atid);
55160eb81626SAdrian Chadd 	}
5517375307d4SAdrian Chadd 	ATH_TX_UNLOCK(sc);
55180eb81626SAdrian Chadd }
55190eb81626SAdrian Chadd 
55203fdfc330SAdrian Chadd static int
55213fdfc330SAdrian Chadd ath_legacy_dma_txsetup(struct ath_softc *sc)
55223fdfc330SAdrian Chadd {
55233fdfc330SAdrian Chadd 
55243fdfc330SAdrian Chadd 	/* nothing new needed */
55253fdfc330SAdrian Chadd 	return (0);
55263fdfc330SAdrian Chadd }
55273fdfc330SAdrian Chadd 
55283fdfc330SAdrian Chadd static int
55293fdfc330SAdrian Chadd ath_legacy_dma_txteardown(struct ath_softc *sc)
55303fdfc330SAdrian Chadd {
55313fdfc330SAdrian Chadd 
55323fdfc330SAdrian Chadd 	/* nothing new needed */
55333fdfc330SAdrian Chadd 	return (0);
55343fdfc330SAdrian Chadd }
55353fdfc330SAdrian Chadd 
55363fdfc330SAdrian Chadd void
55373fdfc330SAdrian Chadd ath_xmit_setup_legacy(struct ath_softc *sc)
55383fdfc330SAdrian Chadd {
55391006fc0cSAdrian Chadd 	/*
55401006fc0cSAdrian Chadd 	 * For now, just set the descriptor length to sizeof(ath_desc);
55411006fc0cSAdrian Chadd 	 * worry about extracting the real length out of the HAL later.
55421006fc0cSAdrian Chadd 	 */
55431006fc0cSAdrian Chadd 	sc->sc_tx_desclen = sizeof(struct ath_desc);
5544bb327d28SAdrian Chadd 	sc->sc_tx_statuslen = sizeof(struct ath_desc);
55451006fc0cSAdrian Chadd 	sc->sc_tx_nmaps = 1;	/* only one buffer per TX desc */
55463fdfc330SAdrian Chadd 
55473fdfc330SAdrian Chadd 	sc->sc_tx.xmit_setup = ath_legacy_dma_txsetup;
55483fdfc330SAdrian Chadd 	sc->sc_tx.xmit_teardown = ath_legacy_dma_txteardown;
5549f8418db5SAdrian Chadd 	sc->sc_tx.xmit_attach_comp_func = ath_legacy_attach_comp_func;
5550746bab5bSAdrian Chadd 
5551746bab5bSAdrian Chadd 	sc->sc_tx.xmit_dma_restart = ath_legacy_tx_dma_restart;
5552746bab5bSAdrian Chadd 	sc->sc_tx.xmit_handoff = ath_legacy_xmit_handoff;
5553788e6aa9SAdrian Chadd 
5554788e6aa9SAdrian Chadd 	sc->sc_tx.xmit_drain = ath_legacy_tx_drain;
55553fdfc330SAdrian Chadd }
5556