xref: /freebsd/sys/dev/ath/if_ath_tdma.c (revision e3665aee04d3127ed2bc6f243480fc660657ab70)
1a35dae8dSAdrian Chadd /*-
2a35dae8dSAdrian Chadd  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3a35dae8dSAdrian Chadd  * All rights reserved.
4a35dae8dSAdrian Chadd  *
5a35dae8dSAdrian Chadd  * Redistribution and use in source and binary forms, with or without
6a35dae8dSAdrian Chadd  * modification, are permitted provided that the following conditions
7a35dae8dSAdrian Chadd  * are met:
8a35dae8dSAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
9a35dae8dSAdrian Chadd  *    notice, this list of conditions and the following disclaimer,
10a35dae8dSAdrian Chadd  *    without modification.
11a35dae8dSAdrian Chadd  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12a35dae8dSAdrian Chadd  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13a35dae8dSAdrian Chadd  *    redistribution must be conditioned upon including a substantially
14a35dae8dSAdrian Chadd  *    similar Disclaimer requirement for further binary redistribution.
15a35dae8dSAdrian Chadd  *
16a35dae8dSAdrian Chadd  * NO WARRANTY
17a35dae8dSAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18a35dae8dSAdrian Chadd  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19a35dae8dSAdrian Chadd  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20a35dae8dSAdrian Chadd  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21a35dae8dSAdrian Chadd  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22a35dae8dSAdrian Chadd  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23a35dae8dSAdrian Chadd  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24a35dae8dSAdrian Chadd  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25a35dae8dSAdrian Chadd  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26a35dae8dSAdrian Chadd  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27a35dae8dSAdrian Chadd  * THE POSSIBILITY OF SUCH DAMAGES.
28a35dae8dSAdrian Chadd  */
29a35dae8dSAdrian Chadd 
30a35dae8dSAdrian Chadd #include <sys/cdefs.h>
31a35dae8dSAdrian Chadd __FBSDID("$FreeBSD$");
32a35dae8dSAdrian Chadd 
33a35dae8dSAdrian Chadd /*
34a35dae8dSAdrian Chadd  * Driver for the Atheros Wireless LAN controller.
35a35dae8dSAdrian Chadd  *
36a35dae8dSAdrian Chadd  * This software is derived from work of Atsushi Onoe; his contribution
37a35dae8dSAdrian Chadd  * is greatly appreciated.
38a35dae8dSAdrian Chadd  */
39a35dae8dSAdrian Chadd 
40a35dae8dSAdrian Chadd #include "opt_inet.h"
41a35dae8dSAdrian Chadd #include "opt_ath.h"
42a35dae8dSAdrian Chadd /*
43a35dae8dSAdrian Chadd  * This is needed for register operations which are performed
44a35dae8dSAdrian Chadd  * by the driver - eg, calls to ath_hal_gettsf32().
45a35dae8dSAdrian Chadd  *
46a35dae8dSAdrian Chadd  * It's also required for any AH_DEBUG checks in here, eg the
47a35dae8dSAdrian Chadd  * module dependencies.
48a35dae8dSAdrian Chadd  */
49a35dae8dSAdrian Chadd #include "opt_ah.h"
50a35dae8dSAdrian Chadd #include "opt_wlan.h"
51a35dae8dSAdrian Chadd 
52a35dae8dSAdrian Chadd #include <sys/param.h>
53a35dae8dSAdrian Chadd #include <sys/systm.h>
54a35dae8dSAdrian Chadd #include <sys/sysctl.h>
55a35dae8dSAdrian Chadd #include <sys/mbuf.h>
56a35dae8dSAdrian Chadd #include <sys/malloc.h>
57a35dae8dSAdrian Chadd #include <sys/lock.h>
58a35dae8dSAdrian Chadd #include <sys/mutex.h>
59a35dae8dSAdrian Chadd #include <sys/kernel.h>
60a35dae8dSAdrian Chadd #include <sys/socket.h>
61a35dae8dSAdrian Chadd #include <sys/sockio.h>
62a35dae8dSAdrian Chadd #include <sys/errno.h>
63a35dae8dSAdrian Chadd #include <sys/callout.h>
64a35dae8dSAdrian Chadd #include <sys/bus.h>
65a35dae8dSAdrian Chadd #include <sys/endian.h>
66a35dae8dSAdrian Chadd #include <sys/kthread.h>
67a35dae8dSAdrian Chadd #include <sys/taskqueue.h>
68a35dae8dSAdrian Chadd #include <sys/priv.h>
69a35dae8dSAdrian Chadd #include <sys/module.h>
70a35dae8dSAdrian Chadd #include <sys/ktr.h>
71a35dae8dSAdrian Chadd #include <sys/smp.h>	/* for mp_ncpus */
72a35dae8dSAdrian Chadd 
73a35dae8dSAdrian Chadd #include <machine/bus.h>
74a35dae8dSAdrian Chadd 
75a35dae8dSAdrian Chadd #include <net/if.h>
7676039bc8SGleb Smirnoff #include <net/if_var.h>
77a35dae8dSAdrian Chadd #include <net/if_dl.h>
78a35dae8dSAdrian Chadd #include <net/if_media.h>
79a35dae8dSAdrian Chadd #include <net/if_types.h>
80a35dae8dSAdrian Chadd #include <net/if_arp.h>
81a35dae8dSAdrian Chadd #include <net/ethernet.h>
82a35dae8dSAdrian Chadd #include <net/if_llc.h>
83a35dae8dSAdrian Chadd 
84a35dae8dSAdrian Chadd #include <net80211/ieee80211_var.h>
85a35dae8dSAdrian Chadd #include <net80211/ieee80211_regdomain.h>
86a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_SUPERG
87a35dae8dSAdrian Chadd #include <net80211/ieee80211_superg.h>
88a35dae8dSAdrian Chadd #endif
89a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
90a35dae8dSAdrian Chadd #include <net80211/ieee80211_tdma.h>
91a35dae8dSAdrian Chadd #endif
92a35dae8dSAdrian Chadd 
93a35dae8dSAdrian Chadd #include <net/bpf.h>
94a35dae8dSAdrian Chadd 
95a35dae8dSAdrian Chadd #ifdef INET
96a35dae8dSAdrian Chadd #include <netinet/in.h>
97a35dae8dSAdrian Chadd #include <netinet/if_ether.h>
98a35dae8dSAdrian Chadd #endif
99a35dae8dSAdrian Chadd 
100a35dae8dSAdrian Chadd #include <dev/ath/if_athvar.h>
101a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_devid.h>		/* XXX for softled */
102a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_diagcodes.h>
103a35dae8dSAdrian Chadd 
104a35dae8dSAdrian Chadd #include <dev/ath/if_ath_debug.h>
105a35dae8dSAdrian Chadd #include <dev/ath/if_ath_misc.h>
106a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tsf.h>
107a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tx.h>
108a35dae8dSAdrian Chadd #include <dev/ath/if_ath_sysctl.h>
109a35dae8dSAdrian Chadd #include <dev/ath/if_ath_led.h>
110a35dae8dSAdrian Chadd #include <dev/ath/if_ath_keycache.h>
111a35dae8dSAdrian Chadd #include <dev/ath/if_ath_rx.h>
112a35dae8dSAdrian Chadd #include <dev/ath/if_ath_beacon.h>
113a35dae8dSAdrian Chadd #include <dev/ath/if_athdfs.h>
114a35dae8dSAdrian Chadd 
115a35dae8dSAdrian Chadd #ifdef ATH_TX99_DIAG
116a35dae8dSAdrian Chadd #include <dev/ath/ath_tx99/ath_tx99.h>
117a35dae8dSAdrian Chadd #endif
118a35dae8dSAdrian Chadd 
1194bda23f9SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
1204bda23f9SAdrian Chadd #include <dev/ath/if_ath_alq.h>
1214bda23f9SAdrian Chadd #endif
1224bda23f9SAdrian Chadd 
123a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
124a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tdma.h>
125a35dae8dSAdrian Chadd 
126a35dae8dSAdrian Chadd static void	ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt,
127a35dae8dSAdrian Chadd 		    u_int32_t bintval);
128a35dae8dSAdrian Chadd static void	ath_tdma_bintvalsetup(struct ath_softc *sc,
129a35dae8dSAdrian Chadd 		    const struct ieee80211_tdma_state *tdma);
130a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */
131a35dae8dSAdrian Chadd 
132a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
133a35dae8dSAdrian Chadd static void
134a35dae8dSAdrian Chadd ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval)
135a35dae8dSAdrian Chadd {
136a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
137a35dae8dSAdrian Chadd 	HAL_BEACON_TIMERS bt;
138a35dae8dSAdrian Chadd 
139a35dae8dSAdrian Chadd 	bt.bt_intval = bintval | HAL_BEACON_ENA;
140a35dae8dSAdrian Chadd 	bt.bt_nexttbtt = nexttbtt;
141a35dae8dSAdrian Chadd 	bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep;
142a35dae8dSAdrian Chadd 	bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep;
143a35dae8dSAdrian Chadd 	bt.bt_nextatim = nexttbtt+1;
144a35dae8dSAdrian Chadd 	/* Enables TBTT, DBA, SWBA timers by default */
145a35dae8dSAdrian Chadd 	bt.bt_flags = 0;
1464bda23f9SAdrian Chadd #if 0
1474bda23f9SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
1484bda23f9SAdrian Chadd 	    "%s: intval=%d (0x%08x) nexttbtt=%u (0x%08x), nextdba=%u (0x%08x), nextswba=%u (0x%08x),nextatim=%u (0x%08x)\n",
1494bda23f9SAdrian Chadd 	    __func__,
1504bda23f9SAdrian Chadd 	    bt.bt_intval,
1514bda23f9SAdrian Chadd 	    bt.bt_intval,
1524bda23f9SAdrian Chadd 	    bt.bt_nexttbtt,
1534bda23f9SAdrian Chadd 	    bt.bt_nexttbtt,
1544bda23f9SAdrian Chadd 	    bt.bt_nextdba,
1554bda23f9SAdrian Chadd 	    bt.bt_nextdba,
1564bda23f9SAdrian Chadd 	    bt.bt_nextswba,
1574bda23f9SAdrian Chadd 	    bt.bt_nextswba,
1584bda23f9SAdrian Chadd 	    bt.bt_nextatim,
1594bda23f9SAdrian Chadd 	    bt.bt_nextatim);
1604bda23f9SAdrian Chadd #endif
1614bda23f9SAdrian Chadd 
162584295fcSAdrian Chadd #ifdef	ATH_DEBUG_ALQ
1634bda23f9SAdrian Chadd 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET)) {
1644bda23f9SAdrian Chadd 		struct if_ath_alq_tdma_timer_set t;
1654bda23f9SAdrian Chadd 		t.bt_intval = htobe32(bt.bt_intval);
1664bda23f9SAdrian Chadd 		t.bt_nexttbtt = htobe32(bt.bt_nexttbtt);
1674bda23f9SAdrian Chadd 		t.bt_nextdba = htobe32(bt.bt_nextdba);
1684bda23f9SAdrian Chadd 		t.bt_nextswba = htobe32(bt.bt_nextswba);
1694bda23f9SAdrian Chadd 		t.bt_nextatim = htobe32(bt.bt_nextatim);
1704bda23f9SAdrian Chadd 		t.bt_flags = htobe32(bt.bt_flags);
1714bda23f9SAdrian Chadd 		t.sc_tdmadbaprep = htobe32(sc->sc_tdmadbaprep);
1724bda23f9SAdrian Chadd 		t.sc_tdmaswbaprep = htobe32(sc->sc_tdmaswbaprep);
1734bda23f9SAdrian Chadd 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET,
1744bda23f9SAdrian Chadd 		    sizeof(t), (char *) &t);
1754bda23f9SAdrian Chadd 	}
176584295fcSAdrian Chadd #endif
1774bda23f9SAdrian Chadd 
1784bda23f9SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
1794bda23f9SAdrian Chadd 	    "%s: nexttbtt=%u (0x%08x), nexttbtt tsf=%lld (0x%08llx)\n",
1804bda23f9SAdrian Chadd 	    __func__,
1814bda23f9SAdrian Chadd 	    bt.bt_nexttbtt,
1824bda23f9SAdrian Chadd 	    bt.bt_nexttbtt,
1834bda23f9SAdrian Chadd 	    (long long) ( ((u_int64_t) (bt.bt_nexttbtt)) << 10),
1844bda23f9SAdrian Chadd 	    (long long) ( ((u_int64_t) (bt.bt_nexttbtt)) << 10));
185a35dae8dSAdrian Chadd 	ath_hal_beaconsettimers(ah, &bt);
186a35dae8dSAdrian Chadd }
187a35dae8dSAdrian Chadd 
188a35dae8dSAdrian Chadd /*
189a35dae8dSAdrian Chadd  * Calculate the beacon interval.  This is periodic in the
190a35dae8dSAdrian Chadd  * superframe for the bss.  We assume each station is configured
191a35dae8dSAdrian Chadd  * identically wrt transmit rate so the guard time we calculate
192a35dae8dSAdrian Chadd  * above will be the same on all stations.  Note we need to
193a35dae8dSAdrian Chadd  * factor in the xmit time because the hardware will schedule
194a35dae8dSAdrian Chadd  * a frame for transmit if the start of the frame is within
195a35dae8dSAdrian Chadd  * the burst time.  When we get hardware that properly kills
196a35dae8dSAdrian Chadd  * frames in the PCU we can reduce/eliminate the guard time.
197a35dae8dSAdrian Chadd  *
198a35dae8dSAdrian Chadd  * Roundup to 1024 is so we have 1 TU buffer in the guard time
199a35dae8dSAdrian Chadd  * to deal with the granularity of the nexttbtt timer.  11n MAC's
200a35dae8dSAdrian Chadd  * with 1us timer granularity should allow us to reduce/eliminate
201a35dae8dSAdrian Chadd  * this.
202a35dae8dSAdrian Chadd  */
203a35dae8dSAdrian Chadd static void
204a35dae8dSAdrian Chadd ath_tdma_bintvalsetup(struct ath_softc *sc,
205a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_state *tdma)
206a35dae8dSAdrian Chadd {
207a35dae8dSAdrian Chadd 	/* copy from vap state (XXX check all vaps have same value?) */
208a35dae8dSAdrian Chadd 	sc->sc_tdmaslotlen = tdma->tdma_slotlen;
209a35dae8dSAdrian Chadd 
210a35dae8dSAdrian Chadd 	sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) *
211a35dae8dSAdrian Chadd 		tdma->tdma_slotcnt, 1024);
212a35dae8dSAdrian Chadd 	sc->sc_tdmabintval >>= 10;		/* TSF -> TU */
213a35dae8dSAdrian Chadd 	if (sc->sc_tdmabintval & 1)
214a35dae8dSAdrian Chadd 		sc->sc_tdmabintval++;
215a35dae8dSAdrian Chadd 
216a35dae8dSAdrian Chadd 	if (tdma->tdma_slot == 0) {
217a35dae8dSAdrian Chadd 		/*
218a35dae8dSAdrian Chadd 		 * Only slot 0 beacons; other slots respond.
219a35dae8dSAdrian Chadd 		 */
220a35dae8dSAdrian Chadd 		sc->sc_imask |= HAL_INT_SWBA;
221a35dae8dSAdrian Chadd 		sc->sc_tdmaswba = 0;		/* beacon immediately */
222a35dae8dSAdrian Chadd 	} else {
223a35dae8dSAdrian Chadd 		/* XXX all vaps must be slot 0 or slot !0 */
224a35dae8dSAdrian Chadd 		sc->sc_imask &= ~HAL_INT_SWBA;
225a35dae8dSAdrian Chadd 	}
226a35dae8dSAdrian Chadd }
227a35dae8dSAdrian Chadd 
228a35dae8dSAdrian Chadd /*
229a35dae8dSAdrian Chadd  * Max 802.11 overhead.  This assumes no 4-address frames and
230a35dae8dSAdrian Chadd  * the encapsulation done by ieee80211_encap (llc).  We also
231a35dae8dSAdrian Chadd  * include potential crypto overhead.
232a35dae8dSAdrian Chadd  */
233a35dae8dSAdrian Chadd #define	IEEE80211_MAXOVERHEAD \
234a35dae8dSAdrian Chadd 	(sizeof(struct ieee80211_qosframe) \
235a35dae8dSAdrian Chadd 	 + sizeof(struct llc) \
236a35dae8dSAdrian Chadd 	 + IEEE80211_ADDR_LEN \
237a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_IVLEN \
238a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_KIDLEN \
239a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_CRCLEN \
240a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_MICLEN \
241a35dae8dSAdrian Chadd 	 + IEEE80211_CRC_LEN)
242a35dae8dSAdrian Chadd 
243a35dae8dSAdrian Chadd /*
244a35dae8dSAdrian Chadd  * Setup initially for tdma operation.  Start the beacon
245a35dae8dSAdrian Chadd  * timers and enable SWBA if we are slot 0.  Otherwise
246a35dae8dSAdrian Chadd  * we wait for slot 0 to arrive so we can sync up before
247a35dae8dSAdrian Chadd  * starting to transmit.
248a35dae8dSAdrian Chadd  */
249a35dae8dSAdrian Chadd void
250a35dae8dSAdrian Chadd ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap)
251a35dae8dSAdrian Chadd {
252a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
253a35dae8dSAdrian Chadd 	struct ifnet *ifp = sc->sc_ifp;
254a35dae8dSAdrian Chadd 	struct ieee80211com *ic = ifp->if_l2com;
255a35dae8dSAdrian Chadd 	const struct ieee80211_txparam *tp;
256a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_state *tdma = NULL;
257a35dae8dSAdrian Chadd 	int rix;
258a35dae8dSAdrian Chadd 
259a35dae8dSAdrian Chadd 	if (vap == NULL) {
260a35dae8dSAdrian Chadd 		vap = TAILQ_FIRST(&ic->ic_vaps);   /* XXX */
261a35dae8dSAdrian Chadd 		if (vap == NULL) {
262a35dae8dSAdrian Chadd 			if_printf(ifp, "%s: no vaps?\n", __func__);
263a35dae8dSAdrian Chadd 			return;
264a35dae8dSAdrian Chadd 		}
265a35dae8dSAdrian Chadd 	}
266a35dae8dSAdrian Chadd 	/* XXX should take a locked ref to iv_bss */
267a35dae8dSAdrian Chadd 	tp = vap->iv_bss->ni_txparms;
268a35dae8dSAdrian Chadd 	/*
269a35dae8dSAdrian Chadd 	 * Calculate the guard time for each slot.  This is the
270a35dae8dSAdrian Chadd 	 * time to send a maximal-size frame according to the
271a35dae8dSAdrian Chadd 	 * fixed/lowest transmit rate.  Note that the interface
272a35dae8dSAdrian Chadd 	 * mtu does not include the 802.11 overhead so we must
273a35dae8dSAdrian Chadd 	 * tack that on (ath_hal_computetxtime includes the
274a35dae8dSAdrian Chadd 	 * preamble and plcp in it's calculation).
275a35dae8dSAdrian Chadd 	 */
276a35dae8dSAdrian Chadd 	tdma = vap->iv_tdma;
277a35dae8dSAdrian Chadd 	if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
278a35dae8dSAdrian Chadd 		rix = ath_tx_findrix(sc, tp->ucastrate);
279a35dae8dSAdrian Chadd 	else
280a35dae8dSAdrian Chadd 		rix = ath_tx_findrix(sc, tp->mcastrate);
281dd6a574eSAdrian Chadd 
282dd6a574eSAdrian Chadd 	/*
283dd6a574eSAdrian Chadd 	 * If the chip supports enforcing TxOP on transmission,
284dd6a574eSAdrian Chadd 	 * we can just delete the guard window.  It isn't at all required.
285dd6a574eSAdrian Chadd 	 */
286dd6a574eSAdrian Chadd 	if (sc->sc_hasenforcetxop) {
287dd6a574eSAdrian Chadd 		sc->sc_tdmaguard = 0;
288dd6a574eSAdrian Chadd 	} else {
289a35dae8dSAdrian Chadd 		/* XXX short preamble assumed */
290dd6a574eSAdrian Chadd 		/* XXX non-11n rate assumed */
291a35dae8dSAdrian Chadd 		sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,
292a35dae8dSAdrian Chadd 			ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE);
293dd6a574eSAdrian Chadd 	}
294a35dae8dSAdrian Chadd 
295a35dae8dSAdrian Chadd 	ath_hal_intrset(ah, 0);
296a35dae8dSAdrian Chadd 
297a35dae8dSAdrian Chadd 	ath_beaconq_config(sc);			/* setup h/w beacon q */
298a35dae8dSAdrian Chadd 	if (sc->sc_setcca)
299a35dae8dSAdrian Chadd 		ath_hal_setcca(ah, AH_FALSE);	/* disable CCA */
300a35dae8dSAdrian Chadd 	ath_tdma_bintvalsetup(sc, tdma);	/* calculate beacon interval */
301a35dae8dSAdrian Chadd 	ath_tdma_settimers(sc, sc->sc_tdmabintval,
302a35dae8dSAdrian Chadd 		sc->sc_tdmabintval | HAL_BEACON_RESET_TSF);
303a35dae8dSAdrian Chadd 	sc->sc_syncbeacon = 0;
304a35dae8dSAdrian Chadd 
305a35dae8dSAdrian Chadd 	sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER;
306a35dae8dSAdrian Chadd 	sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER;
307a35dae8dSAdrian Chadd 
308a35dae8dSAdrian Chadd 	ath_hal_intrset(ah, sc->sc_imask);
309a35dae8dSAdrian Chadd 
310a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u "
311a35dae8dSAdrian Chadd 	    "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__,
312a35dae8dSAdrian Chadd 	    tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt,
313a35dae8dSAdrian Chadd 	    tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval,
314a35dae8dSAdrian Chadd 	    sc->sc_tdmadbaprep);
3154bda23f9SAdrian Chadd 
3164bda23f9SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
3174bda23f9SAdrian Chadd 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG)) {
3184bda23f9SAdrian Chadd 		struct if_ath_alq_tdma_timer_config t;
3194bda23f9SAdrian Chadd 
3204bda23f9SAdrian Chadd 		t.tdma_slot = htobe32(tdma->tdma_slot);
3214bda23f9SAdrian Chadd 		t.tdma_slotlen = htobe32(tdma->tdma_slotlen);
3224bda23f9SAdrian Chadd 		t.tdma_slotcnt = htobe32(tdma->tdma_slotcnt);
3234bda23f9SAdrian Chadd 		t.tdma_bintval = htobe32(tdma->tdma_bintval);
3244bda23f9SAdrian Chadd 		t.tdma_guard = htobe32(sc->sc_tdmaguard);
3254bda23f9SAdrian Chadd 		t.tdma_scbintval = htobe32(sc->sc_tdmabintval);
3264bda23f9SAdrian Chadd 		t.tdma_dbaprep = htobe32(sc->sc_tdmadbaprep);
3274bda23f9SAdrian Chadd 
3284bda23f9SAdrian Chadd 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG,
3294bda23f9SAdrian Chadd 		    sizeof(t), (char *) &t);
3304bda23f9SAdrian Chadd 	}
3314bda23f9SAdrian Chadd #endif	/* ATH_DEBUG_ALQ */
332a35dae8dSAdrian Chadd }
333a35dae8dSAdrian Chadd 
334a35dae8dSAdrian Chadd /*
335a35dae8dSAdrian Chadd  * Update tdma operation.  Called from the 802.11 layer
336a35dae8dSAdrian Chadd  * when a beacon is received from the TDMA station operating
337a35dae8dSAdrian Chadd  * in the slot immediately preceding us in the bss.  Use
338a35dae8dSAdrian Chadd  * the rx timestamp for the beacon frame to update our
339a35dae8dSAdrian Chadd  * beacon timers so we follow their schedule.  Note that
340a35dae8dSAdrian Chadd  * by using the rx timestamp we implicitly include the
341a35dae8dSAdrian Chadd  * propagation delay in our schedule.
342821311eaSAdrian Chadd  *
343821311eaSAdrian Chadd  * XXX TODO: since the changes for the AR5416 and later chips
344821311eaSAdrian Chadd  * involved changing the TSF/TU calculations, we need to make
345821311eaSAdrian Chadd  * sure that various calculations wrap consistently.
346821311eaSAdrian Chadd  *
347821311eaSAdrian Chadd  * A lot of the problems stemmed from the calculations wrapping
348821311eaSAdrian Chadd  * at 65,535 TU.  Since a lot of the math is still being done in
349821311eaSAdrian Chadd  * TU, please audit it to ensure that when the TU values programmed
350821311eaSAdrian Chadd  * into the timers wrap at (2^31)-1 TSF, all the various terms
351821311eaSAdrian Chadd  * wrap consistently.
352a35dae8dSAdrian Chadd  */
353a35dae8dSAdrian Chadd void
354a35dae8dSAdrian Chadd ath_tdma_update(struct ieee80211_node *ni,
355a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_param *tdma, int changed)
356a35dae8dSAdrian Chadd {
357a35dae8dSAdrian Chadd #define	TSF_TO_TU(_h,_l) \
358a35dae8dSAdrian Chadd 	((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
359a35dae8dSAdrian Chadd #define	TU_TO_TSF(_tu)	(((u_int64_t)(_tu)) << 10)
360a35dae8dSAdrian Chadd 	struct ieee80211vap *vap = ni->ni_vap;
361a35dae8dSAdrian Chadd 	struct ieee80211com *ic = ni->ni_ic;
362a35dae8dSAdrian Chadd 	struct ath_softc *sc = ic->ic_ifp->if_softc;
363a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
364a35dae8dSAdrian Chadd 	const HAL_RATE_TABLE *rt = sc->sc_currates;
365e6f1a34aSAdrian Chadd 	u_int64_t tsf, rstamp, nextslot, nexttbtt, nexttbtt_full;
366a35dae8dSAdrian Chadd 	u_int32_t txtime, nextslottu;
367a35dae8dSAdrian Chadd 	int32_t tudelta, tsfdelta;
368a35dae8dSAdrian Chadd 	const struct ath_rx_status *rs;
369a35dae8dSAdrian Chadd 	int rix;
370a35dae8dSAdrian Chadd 
371a35dae8dSAdrian Chadd 	sc->sc_stats.ast_tdma_update++;
372a35dae8dSAdrian Chadd 
373a35dae8dSAdrian Chadd 	/*
374a35dae8dSAdrian Chadd 	 * Check for and adopt configuration changes.
375a35dae8dSAdrian Chadd 	 */
376a35dae8dSAdrian Chadd 	if (changed != 0) {
377a35dae8dSAdrian Chadd 		const struct ieee80211_tdma_state *ts = vap->iv_tdma;
378a35dae8dSAdrian Chadd 
379a35dae8dSAdrian Chadd 		ath_tdma_bintvalsetup(sc, ts);
380a35dae8dSAdrian Chadd 		if (changed & TDMA_UPDATE_SLOTLEN)
381a35dae8dSAdrian Chadd 			ath_wme_update(ic);
382a35dae8dSAdrian Chadd 
383a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_TDMA,
384a35dae8dSAdrian Chadd 		    "%s: adopt slot %u slotcnt %u slotlen %u us "
385a35dae8dSAdrian Chadd 		    "bintval %u TU\n", __func__,
386a35dae8dSAdrian Chadd 		    ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen,
387a35dae8dSAdrian Chadd 		    sc->sc_tdmabintval);
388a35dae8dSAdrian Chadd 
389a35dae8dSAdrian Chadd 		/* XXX right? */
390a35dae8dSAdrian Chadd 		ath_hal_intrset(ah, sc->sc_imask);
391a35dae8dSAdrian Chadd 		/* NB: beacon timers programmed below */
392a35dae8dSAdrian Chadd 	}
393a35dae8dSAdrian Chadd 
394a35dae8dSAdrian Chadd 	/* extend rx timestamp to 64 bits */
395a35dae8dSAdrian Chadd 	rs = sc->sc_lastrs;
396a35dae8dSAdrian Chadd 	tsf = ath_hal_gettsf64(ah);
397a35dae8dSAdrian Chadd 	rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
398a35dae8dSAdrian Chadd 	/*
399a35dae8dSAdrian Chadd 	 * The rx timestamp is set by the hardware on completing
400a35dae8dSAdrian Chadd 	 * reception (at the point where the rx descriptor is DMA'd
401a35dae8dSAdrian Chadd 	 * to the host).  To find the start of our next slot we
402a35dae8dSAdrian Chadd 	 * must adjust this time by the time required to send
403a35dae8dSAdrian Chadd 	 * the packet just received.
404a35dae8dSAdrian Chadd 	 */
405a35dae8dSAdrian Chadd 	rix = rt->rateCodeToIndex[rs->rs_rate];
406dd6a574eSAdrian Chadd 
407dd6a574eSAdrian Chadd 	/*
408dd6a574eSAdrian Chadd 	 * To calculate the packet duration for legacy rates, we
409dd6a574eSAdrian Chadd 	 * only need the rix and preamble.
410dd6a574eSAdrian Chadd 	 *
411dd6a574eSAdrian Chadd 	 * For 11n non-aggregate frames, we also need the channel
412dd6a574eSAdrian Chadd 	 * width and short/long guard interval.
413dd6a574eSAdrian Chadd 	 *
414dd6a574eSAdrian Chadd 	 * For 11n aggregate frames, the required hacks are a little
415dd6a574eSAdrian Chadd 	 * more subtle.  You need to figure out the frame duration
416dd6a574eSAdrian Chadd 	 * for each frame, including the delimiters.  However, when
417dd6a574eSAdrian Chadd 	 * a frame isn't received successfully, we won't hear it
418dd6a574eSAdrian Chadd 	 * (unless you enable reception of CRC errored frames), so
419dd6a574eSAdrian Chadd 	 * your duration calculation is going to be off.
420dd6a574eSAdrian Chadd 	 *
421dd6a574eSAdrian Chadd 	 * However, we can assume that the beacon frames won't be
422dd6a574eSAdrian Chadd 	 * transmitted as aggregate frames, so we should be okay.
423dd6a574eSAdrian Chadd 	 * Just add a check to ensure that we aren't handed something
424dd6a574eSAdrian Chadd 	 * bad.
425dd6a574eSAdrian Chadd 	 *
426dd6a574eSAdrian Chadd 	 * For ath_hal_pkt_txtime() - for 11n rates, shortPreamble is
427dd6a574eSAdrian Chadd 	 * actually short guard interval. For legacy rates,
428dd6a574eSAdrian Chadd 	 * it's short preamble.
429dd6a574eSAdrian Chadd 	 */
430dd6a574eSAdrian Chadd 	txtime = ath_hal_pkt_txtime(ah, rt, rs->rs_datalen,
431dd6a574eSAdrian Chadd 	    rix,
432dd6a574eSAdrian Chadd 	    !! (rs->rs_flags & HAL_RX_2040),
433dd6a574eSAdrian Chadd 	    (rix & 0x80) ?
434dd6a574eSAdrian Chadd 	      (! (rs->rs_flags & HAL_RX_GI)) : rt->info[rix].shortPreamble);
435a35dae8dSAdrian Chadd 	/* NB: << 9 is to cvt to TU and /2 */
436a35dae8dSAdrian Chadd 	nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9);
4374bda23f9SAdrian Chadd 
438e6f1a34aSAdrian Chadd 	/*
439e6f1a34aSAdrian Chadd 	 * For 802.11n chips: nextslottu needs to be the full TSF space,
440e6f1a34aSAdrian Chadd 	 * not just 0..65535 TU.
441e6f1a34aSAdrian Chadd 	 */
442e6f1a34aSAdrian Chadd 	nextslottu = TSF_TO_TU(nextslot>>32, nextslot);
443a35dae8dSAdrian Chadd 	/*
444a35dae8dSAdrian Chadd 	 * Retrieve the hardware NextTBTT in usecs
445a35dae8dSAdrian Chadd 	 * and calculate the difference between what the
446a35dae8dSAdrian Chadd 	 * other station thinks and what we have programmed.  This
447a35dae8dSAdrian Chadd 	 * lets us figure how to adjust our timers to match.  The
448a35dae8dSAdrian Chadd 	 * adjustments are done by pulling the TSF forward and possibly
449a35dae8dSAdrian Chadd 	 * rewriting the beacon timers.
450a35dae8dSAdrian Chadd 	 */
451ddee9211SAdrian Chadd 	/*
452ddee9211SAdrian Chadd 	 * The logic here assumes the nexttbtt counter is in TSF
453ddee9211SAdrian Chadd 	 * but the prr-11n NICs are in TU.  The HAL shifts them
454ddee9211SAdrian Chadd 	 * to TSF but there's two important differences:
455ddee9211SAdrian Chadd 	 *
456ddee9211SAdrian Chadd 	 * + The TU->TSF values have 0's for the low 9 bits, and
457ddee9211SAdrian Chadd 	 * + The counter wraps at TU_TO_TSF(HAL_BEACON_PERIOD + 1) for
458ddee9211SAdrian Chadd 	 *   the pre-11n NICs, but not for the 11n NICs.
459ddee9211SAdrian Chadd 	 *
460ddee9211SAdrian Chadd 	 * So for now, just make sure the nexttbtt value we get
461ddee9211SAdrian Chadd 	 * matches the second issue or once nexttbtt exceeds this
462ddee9211SAdrian Chadd 	 * value, tsfdelta ends up becoming very negative and all
463ddee9211SAdrian Chadd 	 * of the adjustments get very messed up.
464ddee9211SAdrian Chadd 	 */
465e6f1a34aSAdrian Chadd 
466e6f1a34aSAdrian Chadd 	/*
467e6f1a34aSAdrian Chadd 	 * We need to track the full nexttbtt rather than having it
468e6f1a34aSAdrian Chadd 	 * truncated at HAL_BEACON_PERIOD, as programming the
469e6f1a34aSAdrian Chadd 	 * nexttbtt (and related) registers for the 11n chips is
470e6f1a34aSAdrian Chadd 	 * actually going to take the full 32 bit space, rather than
471e6f1a34aSAdrian Chadd 	 * just 0..65535 TU.
472e6f1a34aSAdrian Chadd 	 */
473e6f1a34aSAdrian Chadd 	nexttbtt_full = ath_hal_getnexttbtt(ah);
474e6f1a34aSAdrian Chadd 	nexttbtt = nexttbtt_full % (TU_TO_TSF(HAL_BEACON_PERIOD + 1));
475a35dae8dSAdrian Chadd 	tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD + 1)) - nexttbtt);
476a35dae8dSAdrian Chadd 
477a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
4787c783791SAdrian Chadd 	    "rs->rstamp %llu rstamp %llu tsf %llu txtime %d, nextslot %llu, "
4797c783791SAdrian Chadd 	    "nextslottu %d, nextslottume %d\n",
480*e3665aeeSAdrian Chadd 	    (unsigned long long) rs->rs_tstamp,
481*e3665aeeSAdrian Chadd 	    (unsigned long long) rstamp,
482*e3665aeeSAdrian Chadd 	    (unsigned long long) tsf, txtime,
483*e3665aeeSAdrian Chadd 	    (unsigned long long) nextslot,
484*e3665aeeSAdrian Chadd 	    nextslottu, TSF_TO_TU(nextslot >> 32, nextslot));
4857c783791SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA,
4867c783791SAdrian Chadd 	    "  beacon tstamp: %llu (0x%016llx)\n",
487*e3665aeeSAdrian Chadd 	    (unsigned long long) le64toh(ni->ni_tstamp.tsf),
488*e3665aeeSAdrian Chadd 	    (unsigned long long) le64toh(ni->ni_tstamp.tsf));
4897c783791SAdrian Chadd 
4907c783791SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
4914bda23f9SAdrian Chadd 	    "nexttbtt %llu (0x%08llx) tsfdelta %d avg +%d/-%d\n",
492*e3665aeeSAdrian Chadd 	    (unsigned long long) nexttbtt,
4934bda23f9SAdrian Chadd 	    (long long) nexttbtt,
4944bda23f9SAdrian Chadd 	    tsfdelta,
495a35dae8dSAdrian Chadd 	    TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam));
496a35dae8dSAdrian Chadd 
497a35dae8dSAdrian Chadd 	if (tsfdelta < 0) {
498a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
499a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta);
500a35dae8dSAdrian Chadd 		tsfdelta = -tsfdelta % 1024;
501a35dae8dSAdrian Chadd 		nextslottu++;
502a35dae8dSAdrian Chadd 	} else if (tsfdelta > 0) {
503a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta);
504a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
505a35dae8dSAdrian Chadd 		tsfdelta = 1024 - (tsfdelta % 1024);
506a35dae8dSAdrian Chadd 		nextslottu++;
507a35dae8dSAdrian Chadd 	} else {
508a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
509a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
510a35dae8dSAdrian Chadd 	}
511e6f1a34aSAdrian Chadd 	tudelta = nextslottu - TSF_TO_TU(nexttbtt_full >> 32, nexttbtt_full);
512a35dae8dSAdrian Chadd 
5137c783791SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
5147c783791SAdrian Chadd 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE)) {
5157c783791SAdrian Chadd 		struct if_ath_alq_tdma_beacon_state t;
5167c783791SAdrian Chadd 		t.rx_tsf = htobe64(rstamp);
5177c783791SAdrian Chadd 		t.beacon_tsf = htobe64(le64toh(ni->ni_tstamp.tsf));
5187c783791SAdrian Chadd 		t.tsf64 = htobe64(tsf);
5197c783791SAdrian Chadd 		t.nextslot_tsf = htobe64(nextslot);
5207c783791SAdrian Chadd 		t.nextslot_tu = htobe32(nextslottu);
5217c783791SAdrian Chadd 		t.txtime = htobe32(txtime);
5227c783791SAdrian Chadd 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE,
5237c783791SAdrian Chadd 		    sizeof(t), (char *) &t);
5247c783791SAdrian Chadd 	}
5257c783791SAdrian Chadd 
5267c783791SAdrian Chadd 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC)) {
5277c783791SAdrian Chadd 		struct if_ath_alq_tdma_slot_calc t;
5287c783791SAdrian Chadd 
5297c783791SAdrian Chadd 		t.nexttbtt = htobe64(nexttbtt_full);
5307c783791SAdrian Chadd 		t.next_slot = htobe64(nextslot);
5317c783791SAdrian Chadd 		t.tsfdelta = htobe32(tsfdelta);
5327c783791SAdrian Chadd 		t.avg_plus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltap));
5337c783791SAdrian Chadd 		t.avg_minus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltam));
5347c783791SAdrian Chadd 
5357c783791SAdrian Chadd 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC,
5367c783791SAdrian Chadd 		    sizeof(t), (char *) &t);
5377c783791SAdrian Chadd 	}
5387c783791SAdrian Chadd #endif
5397c783791SAdrian Chadd 
540a35dae8dSAdrian Chadd 	/*
541a35dae8dSAdrian Chadd 	 * Copy sender's timetstamp into tdma ie so they can
542a35dae8dSAdrian Chadd 	 * calculate roundtrip time.  We submit a beacon frame
543a35dae8dSAdrian Chadd 	 * below after any timer adjustment.  The frame goes out
544a35dae8dSAdrian Chadd 	 * at the next TBTT so the sender can calculate the
545a35dae8dSAdrian Chadd 	 * roundtrip by inspecting the tdma ie in our beacon frame.
546a35dae8dSAdrian Chadd 	 *
547a35dae8dSAdrian Chadd 	 * NB: This tstamp is subtlely preserved when
548a35dae8dSAdrian Chadd 	 *     IEEE80211_BEACON_TDMA is marked (e.g. when the
549a35dae8dSAdrian Chadd 	 *     slot position changes) because ieee80211_add_tdma
550a35dae8dSAdrian Chadd 	 *     skips over the data.
551a35dae8dSAdrian Chadd 	 */
552a35dae8dSAdrian Chadd 	memcpy(ATH_VAP(vap)->av_boff.bo_tdma +
553a35dae8dSAdrian Chadd 		__offsetof(struct ieee80211_tdma_param, tdma_tstamp),
554a35dae8dSAdrian Chadd 		&ni->ni_tstamp.data, 8);
555a35dae8dSAdrian Chadd #if 0
556a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
557a35dae8dSAdrian Chadd 	    "tsf %llu nextslot %llu (%d, %d) nextslottu %u nexttbtt %llu (%d)\n",
558a35dae8dSAdrian Chadd 	    (unsigned long long) tsf, (unsigned long long) nextslot,
559a35dae8dSAdrian Chadd 	    (int)(nextslot - tsf), tsfdelta, nextslottu, nexttbtt, tudelta);
560a35dae8dSAdrian Chadd #endif
561a35dae8dSAdrian Chadd 	/*
562a35dae8dSAdrian Chadd 	 * Adjust the beacon timers only when pulling them forward
563a35dae8dSAdrian Chadd 	 * or when going back by less than the beacon interval.
564a35dae8dSAdrian Chadd 	 * Negative jumps larger than the beacon interval seem to
565a35dae8dSAdrian Chadd 	 * cause the timers to stop and generally cause instability.
566a35dae8dSAdrian Chadd 	 * This basically filters out jumps due to missed beacons.
567a35dae8dSAdrian Chadd 	 */
568a35dae8dSAdrian Chadd 	if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) {
5694bda23f9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
5704bda23f9SAdrian Chadd 		    "%s: calling ath_tdma_settimers; nextslottu=%d, bintval=%d\n",
5714bda23f9SAdrian Chadd 		    __func__,
5724bda23f9SAdrian Chadd 		    nextslottu,
5734bda23f9SAdrian Chadd 		    sc->sc_tdmabintval);
574a35dae8dSAdrian Chadd 		ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval);
575a35dae8dSAdrian Chadd 		sc->sc_stats.ast_tdma_timers++;
576a35dae8dSAdrian Chadd 	}
577a35dae8dSAdrian Chadd 	if (tsfdelta > 0) {
57884dd5933SAdrian Chadd 		uint64_t tsf;
57984dd5933SAdrian Chadd 
58084dd5933SAdrian Chadd 		/* XXX should just teach ath_hal_adjusttsf() to do this */
58184dd5933SAdrian Chadd 		tsf = ath_hal_gettsf64(ah);
58284dd5933SAdrian Chadd 		ath_hal_settsf64(ah, tsf + tsfdelta);
5834bda23f9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
5844bda23f9SAdrian Chadd 		    "%s: calling ath_hal_adjusttsf: TSF=%llu, tsfdelta=%d\n",
5854bda23f9SAdrian Chadd 		    __func__,
586*e3665aeeSAdrian Chadd 		    (unsigned long long) tsf,
5874bda23f9SAdrian Chadd 		    tsfdelta);
5884bda23f9SAdrian Chadd 
5894bda23f9SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
5904bda23f9SAdrian Chadd 		if (if_ath_alq_checkdebug(&sc->sc_alq,
5914bda23f9SAdrian Chadd 		    ATH_ALQ_TDMA_TSF_ADJUST)) {
5924bda23f9SAdrian Chadd 			struct if_ath_alq_tdma_tsf_adjust t;
5934bda23f9SAdrian Chadd 
5944bda23f9SAdrian Chadd 			t.tsfdelta = htobe32(tsfdelta);
595821311eaSAdrian Chadd 			t.tsf64_old = htobe64(tsf);
596821311eaSAdrian Chadd 			t.tsf64_new = htobe64(tsf + tsfdelta);
5974bda23f9SAdrian Chadd 			if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TSF_ADJUST,
5984bda23f9SAdrian Chadd 			    sizeof(t), (char *) &t);
5994bda23f9SAdrian Chadd 		}
6004bda23f9SAdrian Chadd #endif	/* ATH_DEBUG_ALQ */
601a35dae8dSAdrian Chadd 		sc->sc_stats.ast_tdma_tsf++;
602a35dae8dSAdrian Chadd 	}
603a35dae8dSAdrian Chadd 	ath_tdma_beacon_send(sc, vap);		/* prepare response */
604a35dae8dSAdrian Chadd #undef TU_TO_TSF
605a35dae8dSAdrian Chadd #undef TSF_TO_TU
606a35dae8dSAdrian Chadd }
607a35dae8dSAdrian Chadd 
608a35dae8dSAdrian Chadd /*
609a35dae8dSAdrian Chadd  * Transmit a beacon frame at SWBA.  Dynamic updates
610a35dae8dSAdrian Chadd  * to the frame contents are done as needed.
611a35dae8dSAdrian Chadd  */
612a35dae8dSAdrian Chadd void
613a35dae8dSAdrian Chadd ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap)
614a35dae8dSAdrian Chadd {
615a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
616a35dae8dSAdrian Chadd 	struct ath_buf *bf;
617a35dae8dSAdrian Chadd 	int otherant;
618a35dae8dSAdrian Chadd 
619a35dae8dSAdrian Chadd 	/*
620a35dae8dSAdrian Chadd 	 * Check if the previous beacon has gone out.  If
621a35dae8dSAdrian Chadd 	 * not don't try to post another, skip this period
622a35dae8dSAdrian Chadd 	 * and wait for the next.  Missed beacons indicate
623a35dae8dSAdrian Chadd 	 * a problem and should not occur.  If we miss too
624a35dae8dSAdrian Chadd 	 * many consecutive beacons reset the device.
625a35dae8dSAdrian Chadd 	 */
626a35dae8dSAdrian Chadd 	if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
627a35dae8dSAdrian Chadd 		sc->sc_bmisscount++;
628a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
629a35dae8dSAdrian Chadd 			"%s: missed %u consecutive beacons\n",
630a35dae8dSAdrian Chadd 			__func__, sc->sc_bmisscount);
631a35dae8dSAdrian Chadd 		if (sc->sc_bmisscount >= ath_bstuck_threshold)
632a35dae8dSAdrian Chadd 			taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
633a35dae8dSAdrian Chadd 		return;
634a35dae8dSAdrian Chadd 	}
635a35dae8dSAdrian Chadd 	if (sc->sc_bmisscount != 0) {
636a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
637a35dae8dSAdrian Chadd 			"%s: resume beacon xmit after %u misses\n",
638a35dae8dSAdrian Chadd 			__func__, sc->sc_bmisscount);
639a35dae8dSAdrian Chadd 		sc->sc_bmisscount = 0;
640a35dae8dSAdrian Chadd 	}
641a35dae8dSAdrian Chadd 
642a35dae8dSAdrian Chadd 	/*
643a35dae8dSAdrian Chadd 	 * Check recent per-antenna transmit statistics and flip
644a35dae8dSAdrian Chadd 	 * the default antenna if noticeably more frames went out
645a35dae8dSAdrian Chadd 	 * on the non-default antenna.
646a35dae8dSAdrian Chadd 	 * XXX assumes 2 anntenae
647a35dae8dSAdrian Chadd 	 */
648a35dae8dSAdrian Chadd 	if (!sc->sc_diversity) {
649a35dae8dSAdrian Chadd 		otherant = sc->sc_defant & 1 ? 2 : 1;
650a35dae8dSAdrian Chadd 		if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
651a35dae8dSAdrian Chadd 			ath_setdefantenna(sc, otherant);
652a35dae8dSAdrian Chadd 		sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
653a35dae8dSAdrian Chadd 	}
654a35dae8dSAdrian Chadd 
655a35dae8dSAdrian Chadd 	bf = ath_beacon_generate(sc, vap);
656b837332dSAdrian Chadd 	/* XXX We don't do cabq traffic, but just for completeness .. */
657b837332dSAdrian Chadd 	ATH_TXQ_LOCK(sc->sc_cabq);
658b837332dSAdrian Chadd 	ath_beacon_cabq_start(sc);
659b837332dSAdrian Chadd 	ATH_TXQ_UNLOCK(sc->sc_cabq);
660b837332dSAdrian Chadd 
661a35dae8dSAdrian Chadd 	if (bf != NULL) {
662a35dae8dSAdrian Chadd 		/*
663a35dae8dSAdrian Chadd 		 * Stop any current dma and put the new frame on the queue.
664a35dae8dSAdrian Chadd 		 * This should never fail since we check above that no frames
665a35dae8dSAdrian Chadd 		 * are still pending on the queue.
666a35dae8dSAdrian Chadd 		 */
667b837332dSAdrian Chadd 		if ((! sc->sc_isedma) &&
668b837332dSAdrian Chadd 		    (! ath_hal_stoptxdma(ah, sc->sc_bhalq))) {
669a35dae8dSAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_ANY,
670a35dae8dSAdrian Chadd 				"%s: beacon queue %u did not stop?\n",
671a35dae8dSAdrian Chadd 				__func__, sc->sc_bhalq);
672a35dae8dSAdrian Chadd 			/* NB: the HAL still stops DMA, so proceed */
673a35dae8dSAdrian Chadd 		}
674a35dae8dSAdrian Chadd 		ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
675a35dae8dSAdrian Chadd 		ath_hal_txstart(ah, sc->sc_bhalq);
676a35dae8dSAdrian Chadd 
677a35dae8dSAdrian Chadd 		sc->sc_stats.ast_be_xmit++;		/* XXX per-vap? */
678a35dae8dSAdrian Chadd 
679a35dae8dSAdrian Chadd 		/*
680a35dae8dSAdrian Chadd 		 * Record local TSF for our last send for use
681a35dae8dSAdrian Chadd 		 * in arbitrating slot collisions.
682a35dae8dSAdrian Chadd 		 */
683a35dae8dSAdrian Chadd 		/* XXX should take a locked ref to iv_bss */
684a35dae8dSAdrian Chadd 		vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);
685a35dae8dSAdrian Chadd 	}
686a35dae8dSAdrian Chadd }
687a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */
688