xref: /freebsd/sys/dev/ath/if_ath_tdma.c (revision ddee921170a290ea51cdffb57680c8dc0b4341c8)
1a35dae8dSAdrian Chadd /*-
2a35dae8dSAdrian Chadd  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3a35dae8dSAdrian Chadd  * All rights reserved.
4a35dae8dSAdrian Chadd  *
5a35dae8dSAdrian Chadd  * Redistribution and use in source and binary forms, with or without
6a35dae8dSAdrian Chadd  * modification, are permitted provided that the following conditions
7a35dae8dSAdrian Chadd  * are met:
8a35dae8dSAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
9a35dae8dSAdrian Chadd  *    notice, this list of conditions and the following disclaimer,
10a35dae8dSAdrian Chadd  *    without modification.
11a35dae8dSAdrian Chadd  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12a35dae8dSAdrian Chadd  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13a35dae8dSAdrian Chadd  *    redistribution must be conditioned upon including a substantially
14a35dae8dSAdrian Chadd  *    similar Disclaimer requirement for further binary redistribution.
15a35dae8dSAdrian Chadd  *
16a35dae8dSAdrian Chadd  * NO WARRANTY
17a35dae8dSAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18a35dae8dSAdrian Chadd  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19a35dae8dSAdrian Chadd  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20a35dae8dSAdrian Chadd  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21a35dae8dSAdrian Chadd  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22a35dae8dSAdrian Chadd  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23a35dae8dSAdrian Chadd  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24a35dae8dSAdrian Chadd  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25a35dae8dSAdrian Chadd  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26a35dae8dSAdrian Chadd  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27a35dae8dSAdrian Chadd  * THE POSSIBILITY OF SUCH DAMAGES.
28a35dae8dSAdrian Chadd  */
29a35dae8dSAdrian Chadd 
30a35dae8dSAdrian Chadd #include <sys/cdefs.h>
31a35dae8dSAdrian Chadd __FBSDID("$FreeBSD$");
32a35dae8dSAdrian Chadd 
33a35dae8dSAdrian Chadd /*
34a35dae8dSAdrian Chadd  * Driver for the Atheros Wireless LAN controller.
35a35dae8dSAdrian Chadd  *
36a35dae8dSAdrian Chadd  * This software is derived from work of Atsushi Onoe; his contribution
37a35dae8dSAdrian Chadd  * is greatly appreciated.
38a35dae8dSAdrian Chadd  */
39a35dae8dSAdrian Chadd 
40a35dae8dSAdrian Chadd #include "opt_inet.h"
41a35dae8dSAdrian Chadd #include "opt_ath.h"
42a35dae8dSAdrian Chadd /*
43a35dae8dSAdrian Chadd  * This is needed for register operations which are performed
44a35dae8dSAdrian Chadd  * by the driver - eg, calls to ath_hal_gettsf32().
45a35dae8dSAdrian Chadd  *
46a35dae8dSAdrian Chadd  * It's also required for any AH_DEBUG checks in here, eg the
47a35dae8dSAdrian Chadd  * module dependencies.
48a35dae8dSAdrian Chadd  */
49a35dae8dSAdrian Chadd #include "opt_ah.h"
50a35dae8dSAdrian Chadd #include "opt_wlan.h"
51a35dae8dSAdrian Chadd 
52a35dae8dSAdrian Chadd #include <sys/param.h>
53a35dae8dSAdrian Chadd #include <sys/systm.h>
54a35dae8dSAdrian Chadd #include <sys/sysctl.h>
55a35dae8dSAdrian Chadd #include <sys/mbuf.h>
56a35dae8dSAdrian Chadd #include <sys/malloc.h>
57a35dae8dSAdrian Chadd #include <sys/lock.h>
58a35dae8dSAdrian Chadd #include <sys/mutex.h>
59a35dae8dSAdrian Chadd #include <sys/kernel.h>
60a35dae8dSAdrian Chadd #include <sys/socket.h>
61a35dae8dSAdrian Chadd #include <sys/sockio.h>
62a35dae8dSAdrian Chadd #include <sys/errno.h>
63a35dae8dSAdrian Chadd #include <sys/callout.h>
64a35dae8dSAdrian Chadd #include <sys/bus.h>
65a35dae8dSAdrian Chadd #include <sys/endian.h>
66a35dae8dSAdrian Chadd #include <sys/kthread.h>
67a35dae8dSAdrian Chadd #include <sys/taskqueue.h>
68a35dae8dSAdrian Chadd #include <sys/priv.h>
69a35dae8dSAdrian Chadd #include <sys/module.h>
70a35dae8dSAdrian Chadd #include <sys/ktr.h>
71a35dae8dSAdrian Chadd #include <sys/smp.h>	/* for mp_ncpus */
72a35dae8dSAdrian Chadd 
73a35dae8dSAdrian Chadd #include <machine/bus.h>
74a35dae8dSAdrian Chadd 
75a35dae8dSAdrian Chadd #include <net/if.h>
76a35dae8dSAdrian Chadd #include <net/if_dl.h>
77a35dae8dSAdrian Chadd #include <net/if_media.h>
78a35dae8dSAdrian Chadd #include <net/if_types.h>
79a35dae8dSAdrian Chadd #include <net/if_arp.h>
80a35dae8dSAdrian Chadd #include <net/ethernet.h>
81a35dae8dSAdrian Chadd #include <net/if_llc.h>
82a35dae8dSAdrian Chadd 
83a35dae8dSAdrian Chadd #include <net80211/ieee80211_var.h>
84a35dae8dSAdrian Chadd #include <net80211/ieee80211_regdomain.h>
85a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_SUPERG
86a35dae8dSAdrian Chadd #include <net80211/ieee80211_superg.h>
87a35dae8dSAdrian Chadd #endif
88a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
89a35dae8dSAdrian Chadd #include <net80211/ieee80211_tdma.h>
90a35dae8dSAdrian Chadd #endif
91a35dae8dSAdrian Chadd 
92a35dae8dSAdrian Chadd #include <net/bpf.h>
93a35dae8dSAdrian Chadd 
94a35dae8dSAdrian Chadd #ifdef INET
95a35dae8dSAdrian Chadd #include <netinet/in.h>
96a35dae8dSAdrian Chadd #include <netinet/if_ether.h>
97a35dae8dSAdrian Chadd #endif
98a35dae8dSAdrian Chadd 
99a35dae8dSAdrian Chadd #include <dev/ath/if_athvar.h>
100a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_devid.h>		/* XXX for softled */
101a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_diagcodes.h>
102a35dae8dSAdrian Chadd 
103a35dae8dSAdrian Chadd #include <dev/ath/if_ath_debug.h>
104a35dae8dSAdrian Chadd #include <dev/ath/if_ath_misc.h>
105a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tsf.h>
106a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tx.h>
107a35dae8dSAdrian Chadd #include <dev/ath/if_ath_sysctl.h>
108a35dae8dSAdrian Chadd #include <dev/ath/if_ath_led.h>
109a35dae8dSAdrian Chadd #include <dev/ath/if_ath_keycache.h>
110a35dae8dSAdrian Chadd #include <dev/ath/if_ath_rx.h>
111a35dae8dSAdrian Chadd #include <dev/ath/if_ath_beacon.h>
112a35dae8dSAdrian Chadd #include <dev/ath/if_athdfs.h>
113a35dae8dSAdrian Chadd 
114a35dae8dSAdrian Chadd #ifdef ATH_TX99_DIAG
115a35dae8dSAdrian Chadd #include <dev/ath/ath_tx99/ath_tx99.h>
116a35dae8dSAdrian Chadd #endif
117a35dae8dSAdrian Chadd 
118a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
119a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tdma.h>
120a35dae8dSAdrian Chadd 
121a35dae8dSAdrian Chadd static void	ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt,
122a35dae8dSAdrian Chadd 		    u_int32_t bintval);
123a35dae8dSAdrian Chadd static void	ath_tdma_bintvalsetup(struct ath_softc *sc,
124a35dae8dSAdrian Chadd 		    const struct ieee80211_tdma_state *tdma);
125a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */
126a35dae8dSAdrian Chadd 
127a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
128a35dae8dSAdrian Chadd static void
129a35dae8dSAdrian Chadd ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval)
130a35dae8dSAdrian Chadd {
131a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
132a35dae8dSAdrian Chadd 	HAL_BEACON_TIMERS bt;
133a35dae8dSAdrian Chadd 
134a35dae8dSAdrian Chadd 	bt.bt_intval = bintval | HAL_BEACON_ENA;
135a35dae8dSAdrian Chadd 	bt.bt_nexttbtt = nexttbtt;
136a35dae8dSAdrian Chadd 	bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep;
137a35dae8dSAdrian Chadd 	bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep;
138a35dae8dSAdrian Chadd 	bt.bt_nextatim = nexttbtt+1;
139a35dae8dSAdrian Chadd 	/* Enables TBTT, DBA, SWBA timers by default */
140a35dae8dSAdrian Chadd 	bt.bt_flags = 0;
141a35dae8dSAdrian Chadd 	ath_hal_beaconsettimers(ah, &bt);
142a35dae8dSAdrian Chadd }
143a35dae8dSAdrian Chadd 
144a35dae8dSAdrian Chadd /*
145a35dae8dSAdrian Chadd  * Calculate the beacon interval.  This is periodic in the
146a35dae8dSAdrian Chadd  * superframe for the bss.  We assume each station is configured
147a35dae8dSAdrian Chadd  * identically wrt transmit rate so the guard time we calculate
148a35dae8dSAdrian Chadd  * above will be the same on all stations.  Note we need to
149a35dae8dSAdrian Chadd  * factor in the xmit time because the hardware will schedule
150a35dae8dSAdrian Chadd  * a frame for transmit if the start of the frame is within
151a35dae8dSAdrian Chadd  * the burst time.  When we get hardware that properly kills
152a35dae8dSAdrian Chadd  * frames in the PCU we can reduce/eliminate the guard time.
153a35dae8dSAdrian Chadd  *
154a35dae8dSAdrian Chadd  * Roundup to 1024 is so we have 1 TU buffer in the guard time
155a35dae8dSAdrian Chadd  * to deal with the granularity of the nexttbtt timer.  11n MAC's
156a35dae8dSAdrian Chadd  * with 1us timer granularity should allow us to reduce/eliminate
157a35dae8dSAdrian Chadd  * this.
158a35dae8dSAdrian Chadd  */
159a35dae8dSAdrian Chadd static void
160a35dae8dSAdrian Chadd ath_tdma_bintvalsetup(struct ath_softc *sc,
161a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_state *tdma)
162a35dae8dSAdrian Chadd {
163a35dae8dSAdrian Chadd 	/* copy from vap state (XXX check all vaps have same value?) */
164a35dae8dSAdrian Chadd 	sc->sc_tdmaslotlen = tdma->tdma_slotlen;
165a35dae8dSAdrian Chadd 
166a35dae8dSAdrian Chadd 	sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) *
167a35dae8dSAdrian Chadd 		tdma->tdma_slotcnt, 1024);
168a35dae8dSAdrian Chadd 	sc->sc_tdmabintval >>= 10;		/* TSF -> TU */
169a35dae8dSAdrian Chadd 	if (sc->sc_tdmabintval & 1)
170a35dae8dSAdrian Chadd 		sc->sc_tdmabintval++;
171a35dae8dSAdrian Chadd 
172a35dae8dSAdrian Chadd 	if (tdma->tdma_slot == 0) {
173a35dae8dSAdrian Chadd 		/*
174a35dae8dSAdrian Chadd 		 * Only slot 0 beacons; other slots respond.
175a35dae8dSAdrian Chadd 		 */
176a35dae8dSAdrian Chadd 		sc->sc_imask |= HAL_INT_SWBA;
177a35dae8dSAdrian Chadd 		sc->sc_tdmaswba = 0;		/* beacon immediately */
178a35dae8dSAdrian Chadd 	} else {
179a35dae8dSAdrian Chadd 		/* XXX all vaps must be slot 0 or slot !0 */
180a35dae8dSAdrian Chadd 		sc->sc_imask &= ~HAL_INT_SWBA;
181a35dae8dSAdrian Chadd 	}
182a35dae8dSAdrian Chadd }
183a35dae8dSAdrian Chadd 
184a35dae8dSAdrian Chadd /*
185a35dae8dSAdrian Chadd  * Max 802.11 overhead.  This assumes no 4-address frames and
186a35dae8dSAdrian Chadd  * the encapsulation done by ieee80211_encap (llc).  We also
187a35dae8dSAdrian Chadd  * include potential crypto overhead.
188a35dae8dSAdrian Chadd  */
189a35dae8dSAdrian Chadd #define	IEEE80211_MAXOVERHEAD \
190a35dae8dSAdrian Chadd 	(sizeof(struct ieee80211_qosframe) \
191a35dae8dSAdrian Chadd 	 + sizeof(struct llc) \
192a35dae8dSAdrian Chadd 	 + IEEE80211_ADDR_LEN \
193a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_IVLEN \
194a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_KIDLEN \
195a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_CRCLEN \
196a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_MICLEN \
197a35dae8dSAdrian Chadd 	 + IEEE80211_CRC_LEN)
198a35dae8dSAdrian Chadd 
199a35dae8dSAdrian Chadd /*
200a35dae8dSAdrian Chadd  * Setup initially for tdma operation.  Start the beacon
201a35dae8dSAdrian Chadd  * timers and enable SWBA if we are slot 0.  Otherwise
202a35dae8dSAdrian Chadd  * we wait for slot 0 to arrive so we can sync up before
203a35dae8dSAdrian Chadd  * starting to transmit.
204a35dae8dSAdrian Chadd  */
205a35dae8dSAdrian Chadd void
206a35dae8dSAdrian Chadd ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap)
207a35dae8dSAdrian Chadd {
208a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
209a35dae8dSAdrian Chadd 	struct ifnet *ifp = sc->sc_ifp;
210a35dae8dSAdrian Chadd 	struct ieee80211com *ic = ifp->if_l2com;
211a35dae8dSAdrian Chadd 	const struct ieee80211_txparam *tp;
212a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_state *tdma = NULL;
213a35dae8dSAdrian Chadd 	int rix;
214a35dae8dSAdrian Chadd 
215a35dae8dSAdrian Chadd 	if (vap == NULL) {
216a35dae8dSAdrian Chadd 		vap = TAILQ_FIRST(&ic->ic_vaps);   /* XXX */
217a35dae8dSAdrian Chadd 		if (vap == NULL) {
218a35dae8dSAdrian Chadd 			if_printf(ifp, "%s: no vaps?\n", __func__);
219a35dae8dSAdrian Chadd 			return;
220a35dae8dSAdrian Chadd 		}
221a35dae8dSAdrian Chadd 	}
222a35dae8dSAdrian Chadd 	/* XXX should take a locked ref to iv_bss */
223a35dae8dSAdrian Chadd 	tp = vap->iv_bss->ni_txparms;
224a35dae8dSAdrian Chadd 	/*
225a35dae8dSAdrian Chadd 	 * Calculate the guard time for each slot.  This is the
226a35dae8dSAdrian Chadd 	 * time to send a maximal-size frame according to the
227a35dae8dSAdrian Chadd 	 * fixed/lowest transmit rate.  Note that the interface
228a35dae8dSAdrian Chadd 	 * mtu does not include the 802.11 overhead so we must
229a35dae8dSAdrian Chadd 	 * tack that on (ath_hal_computetxtime includes the
230a35dae8dSAdrian Chadd 	 * preamble and plcp in it's calculation).
231a35dae8dSAdrian Chadd 	 */
232a35dae8dSAdrian Chadd 	tdma = vap->iv_tdma;
233a35dae8dSAdrian Chadd 	if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
234a35dae8dSAdrian Chadd 		rix = ath_tx_findrix(sc, tp->ucastrate);
235a35dae8dSAdrian Chadd 	else
236a35dae8dSAdrian Chadd 		rix = ath_tx_findrix(sc, tp->mcastrate);
237a35dae8dSAdrian Chadd 	/* XXX short preamble assumed */
238a35dae8dSAdrian Chadd 	sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,
239a35dae8dSAdrian Chadd 		ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE);
240a35dae8dSAdrian Chadd 
241a35dae8dSAdrian Chadd 	ath_hal_intrset(ah, 0);
242a35dae8dSAdrian Chadd 
243a35dae8dSAdrian Chadd 	ath_beaconq_config(sc);			/* setup h/w beacon q */
244a35dae8dSAdrian Chadd 	if (sc->sc_setcca)
245a35dae8dSAdrian Chadd 		ath_hal_setcca(ah, AH_FALSE);	/* disable CCA */
246a35dae8dSAdrian Chadd 	ath_tdma_bintvalsetup(sc, tdma);	/* calculate beacon interval */
247a35dae8dSAdrian Chadd 	ath_tdma_settimers(sc, sc->sc_tdmabintval,
248a35dae8dSAdrian Chadd 		sc->sc_tdmabintval | HAL_BEACON_RESET_TSF);
249a35dae8dSAdrian Chadd 	sc->sc_syncbeacon = 0;
250a35dae8dSAdrian Chadd 
251a35dae8dSAdrian Chadd 	sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER;
252a35dae8dSAdrian Chadd 	sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER;
253a35dae8dSAdrian Chadd 
254a35dae8dSAdrian Chadd 	ath_hal_intrset(ah, sc->sc_imask);
255a35dae8dSAdrian Chadd 
256a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u "
257a35dae8dSAdrian Chadd 	    "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__,
258a35dae8dSAdrian Chadd 	    tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt,
259a35dae8dSAdrian Chadd 	    tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval,
260a35dae8dSAdrian Chadd 	    sc->sc_tdmadbaprep);
261a35dae8dSAdrian Chadd }
262a35dae8dSAdrian Chadd 
263a35dae8dSAdrian Chadd /*
264a35dae8dSAdrian Chadd  * Update tdma operation.  Called from the 802.11 layer
265a35dae8dSAdrian Chadd  * when a beacon is received from the TDMA station operating
266a35dae8dSAdrian Chadd  * in the slot immediately preceding us in the bss.  Use
267a35dae8dSAdrian Chadd  * the rx timestamp for the beacon frame to update our
268a35dae8dSAdrian Chadd  * beacon timers so we follow their schedule.  Note that
269a35dae8dSAdrian Chadd  * by using the rx timestamp we implicitly include the
270a35dae8dSAdrian Chadd  * propagation delay in our schedule.
271a35dae8dSAdrian Chadd  */
272a35dae8dSAdrian Chadd void
273a35dae8dSAdrian Chadd ath_tdma_update(struct ieee80211_node *ni,
274a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_param *tdma, int changed)
275a35dae8dSAdrian Chadd {
276a35dae8dSAdrian Chadd #define	TSF_TO_TU(_h,_l) \
277a35dae8dSAdrian Chadd 	((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
278a35dae8dSAdrian Chadd #define	TU_TO_TSF(_tu)	(((u_int64_t)(_tu)) << 10)
279a35dae8dSAdrian Chadd 	struct ieee80211vap *vap = ni->ni_vap;
280a35dae8dSAdrian Chadd 	struct ieee80211com *ic = ni->ni_ic;
281a35dae8dSAdrian Chadd 	struct ath_softc *sc = ic->ic_ifp->if_softc;
282a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
283a35dae8dSAdrian Chadd 	const HAL_RATE_TABLE *rt = sc->sc_currates;
284a35dae8dSAdrian Chadd 	u_int64_t tsf, rstamp, nextslot, nexttbtt;
285a35dae8dSAdrian Chadd 	u_int32_t txtime, nextslottu;
286a35dae8dSAdrian Chadd 	int32_t tudelta, tsfdelta;
287a35dae8dSAdrian Chadd 	const struct ath_rx_status *rs;
288a35dae8dSAdrian Chadd 	int rix;
289a35dae8dSAdrian Chadd 
290a35dae8dSAdrian Chadd 	sc->sc_stats.ast_tdma_update++;
291a35dae8dSAdrian Chadd 
292a35dae8dSAdrian Chadd 	/*
293a35dae8dSAdrian Chadd 	 * Check for and adopt configuration changes.
294a35dae8dSAdrian Chadd 	 */
295a35dae8dSAdrian Chadd 	if (changed != 0) {
296a35dae8dSAdrian Chadd 		const struct ieee80211_tdma_state *ts = vap->iv_tdma;
297a35dae8dSAdrian Chadd 
298a35dae8dSAdrian Chadd 		ath_tdma_bintvalsetup(sc, ts);
299a35dae8dSAdrian Chadd 		if (changed & TDMA_UPDATE_SLOTLEN)
300a35dae8dSAdrian Chadd 			ath_wme_update(ic);
301a35dae8dSAdrian Chadd 
302a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_TDMA,
303a35dae8dSAdrian Chadd 		    "%s: adopt slot %u slotcnt %u slotlen %u us "
304a35dae8dSAdrian Chadd 		    "bintval %u TU\n", __func__,
305a35dae8dSAdrian Chadd 		    ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen,
306a35dae8dSAdrian Chadd 		    sc->sc_tdmabintval);
307a35dae8dSAdrian Chadd 
308a35dae8dSAdrian Chadd 		/* XXX right? */
309a35dae8dSAdrian Chadd 		ath_hal_intrset(ah, sc->sc_imask);
310a35dae8dSAdrian Chadd 		/* NB: beacon timers programmed below */
311a35dae8dSAdrian Chadd 	}
312a35dae8dSAdrian Chadd 
313a35dae8dSAdrian Chadd 	/* extend rx timestamp to 64 bits */
314a35dae8dSAdrian Chadd 	rs = sc->sc_lastrs;
315a35dae8dSAdrian Chadd 	tsf = ath_hal_gettsf64(ah);
316a35dae8dSAdrian Chadd 	rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
317a35dae8dSAdrian Chadd 	/*
318a35dae8dSAdrian Chadd 	 * The rx timestamp is set by the hardware on completing
319a35dae8dSAdrian Chadd 	 * reception (at the point where the rx descriptor is DMA'd
320a35dae8dSAdrian Chadd 	 * to the host).  To find the start of our next slot we
321a35dae8dSAdrian Chadd 	 * must adjust this time by the time required to send
322a35dae8dSAdrian Chadd 	 * the packet just received.
323a35dae8dSAdrian Chadd 	 */
324a35dae8dSAdrian Chadd 	rix = rt->rateCodeToIndex[rs->rs_rate];
325a35dae8dSAdrian Chadd 	txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix,
326a35dae8dSAdrian Chadd 	    rt->info[rix].shortPreamble);
327a35dae8dSAdrian Chadd 	/* NB: << 9 is to cvt to TU and /2 */
328a35dae8dSAdrian Chadd 	nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9);
329a35dae8dSAdrian Chadd 	nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD;
330a35dae8dSAdrian Chadd 
331a35dae8dSAdrian Chadd 	/*
332a35dae8dSAdrian Chadd 	 * Retrieve the hardware NextTBTT in usecs
333a35dae8dSAdrian Chadd 	 * and calculate the difference between what the
334a35dae8dSAdrian Chadd 	 * other station thinks and what we have programmed.  This
335a35dae8dSAdrian Chadd 	 * lets us figure how to adjust our timers to match.  The
336a35dae8dSAdrian Chadd 	 * adjustments are done by pulling the TSF forward and possibly
337a35dae8dSAdrian Chadd 	 * rewriting the beacon timers.
338a35dae8dSAdrian Chadd 	 */
339*ddee9211SAdrian Chadd 	/*
340*ddee9211SAdrian Chadd 	 * The logic here assumes the nexttbtt counter is in TSF
341*ddee9211SAdrian Chadd 	 * but the prr-11n NICs are in TU.  The HAL shifts them
342*ddee9211SAdrian Chadd 	 * to TSF but there's two important differences:
343*ddee9211SAdrian Chadd 	 *
344*ddee9211SAdrian Chadd 	 * + The TU->TSF values have 0's for the low 9 bits, and
345*ddee9211SAdrian Chadd 	 * + The counter wraps at TU_TO_TSF(HAL_BEACON_PERIOD + 1) for
346*ddee9211SAdrian Chadd 	 *   the pre-11n NICs, but not for the 11n NICs.
347*ddee9211SAdrian Chadd 	 *
348*ddee9211SAdrian Chadd 	 * So for now, just make sure the nexttbtt value we get
349*ddee9211SAdrian Chadd 	 * matches the second issue or once nexttbtt exceeds this
350*ddee9211SAdrian Chadd 	 * value, tsfdelta ends up becoming very negative and all
351*ddee9211SAdrian Chadd 	 * of the adjustments get very messed up.
352*ddee9211SAdrian Chadd 	 */
353*ddee9211SAdrian Chadd 	nexttbtt = ath_hal_getnexttbtt(ah) % (TU_TO_TSF(HAL_BEACON_PERIOD + 1));
354a35dae8dSAdrian Chadd 	tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD + 1)) - nexttbtt);
355a35dae8dSAdrian Chadd 
356a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
357a35dae8dSAdrian Chadd 	    "tsfdelta %d avg +%d/-%d\n", tsfdelta,
358a35dae8dSAdrian Chadd 	    TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam));
359a35dae8dSAdrian Chadd 
360a35dae8dSAdrian Chadd 	if (tsfdelta < 0) {
361a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
362a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta);
363a35dae8dSAdrian Chadd 		tsfdelta = -tsfdelta % 1024;
364a35dae8dSAdrian Chadd 		nextslottu++;
365a35dae8dSAdrian Chadd 	} else if (tsfdelta > 0) {
366a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta);
367a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
368a35dae8dSAdrian Chadd 		tsfdelta = 1024 - (tsfdelta % 1024);
369a35dae8dSAdrian Chadd 		nextslottu++;
370a35dae8dSAdrian Chadd 	} else {
371a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
372a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
373a35dae8dSAdrian Chadd 	}
374a35dae8dSAdrian Chadd 	tudelta = nextslottu - TSF_TO_TU(nexttbtt >> 32, nexttbtt);
375a35dae8dSAdrian Chadd 
376a35dae8dSAdrian Chadd 	/*
377a35dae8dSAdrian Chadd 	 * Copy sender's timetstamp into tdma ie so they can
378a35dae8dSAdrian Chadd 	 * calculate roundtrip time.  We submit a beacon frame
379a35dae8dSAdrian Chadd 	 * below after any timer adjustment.  The frame goes out
380a35dae8dSAdrian Chadd 	 * at the next TBTT so the sender can calculate the
381a35dae8dSAdrian Chadd 	 * roundtrip by inspecting the tdma ie in our beacon frame.
382a35dae8dSAdrian Chadd 	 *
383a35dae8dSAdrian Chadd 	 * NB: This tstamp is subtlely preserved when
384a35dae8dSAdrian Chadd 	 *     IEEE80211_BEACON_TDMA is marked (e.g. when the
385a35dae8dSAdrian Chadd 	 *     slot position changes) because ieee80211_add_tdma
386a35dae8dSAdrian Chadd 	 *     skips over the data.
387a35dae8dSAdrian Chadd 	 */
388a35dae8dSAdrian Chadd 	memcpy(ATH_VAP(vap)->av_boff.bo_tdma +
389a35dae8dSAdrian Chadd 		__offsetof(struct ieee80211_tdma_param, tdma_tstamp),
390a35dae8dSAdrian Chadd 		&ni->ni_tstamp.data, 8);
391a35dae8dSAdrian Chadd #if 0
392a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
393a35dae8dSAdrian Chadd 	    "tsf %llu nextslot %llu (%d, %d) nextslottu %u nexttbtt %llu (%d)\n",
394a35dae8dSAdrian Chadd 	    (unsigned long long) tsf, (unsigned long long) nextslot,
395a35dae8dSAdrian Chadd 	    (int)(nextslot - tsf), tsfdelta, nextslottu, nexttbtt, tudelta);
396a35dae8dSAdrian Chadd #endif
397a35dae8dSAdrian Chadd 	/*
398a35dae8dSAdrian Chadd 	 * Adjust the beacon timers only when pulling them forward
399a35dae8dSAdrian Chadd 	 * or when going back by less than the beacon interval.
400a35dae8dSAdrian Chadd 	 * Negative jumps larger than the beacon interval seem to
401a35dae8dSAdrian Chadd 	 * cause the timers to stop and generally cause instability.
402a35dae8dSAdrian Chadd 	 * This basically filters out jumps due to missed beacons.
403a35dae8dSAdrian Chadd 	 */
404a35dae8dSAdrian Chadd 	if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) {
405a35dae8dSAdrian Chadd 		ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval);
406a35dae8dSAdrian Chadd 		sc->sc_stats.ast_tdma_timers++;
407a35dae8dSAdrian Chadd 	}
408a35dae8dSAdrian Chadd 	if (tsfdelta > 0) {
409a35dae8dSAdrian Chadd 		ath_hal_adjusttsf(ah, tsfdelta);
410a35dae8dSAdrian Chadd 		sc->sc_stats.ast_tdma_tsf++;
411a35dae8dSAdrian Chadd 	}
412a35dae8dSAdrian Chadd 	ath_tdma_beacon_send(sc, vap);		/* prepare response */
413a35dae8dSAdrian Chadd #undef TU_TO_TSF
414a35dae8dSAdrian Chadd #undef TSF_TO_TU
415a35dae8dSAdrian Chadd }
416a35dae8dSAdrian Chadd 
417a35dae8dSAdrian Chadd /*
418a35dae8dSAdrian Chadd  * Transmit a beacon frame at SWBA.  Dynamic updates
419a35dae8dSAdrian Chadd  * to the frame contents are done as needed.
420a35dae8dSAdrian Chadd  */
421a35dae8dSAdrian Chadd void
422a35dae8dSAdrian Chadd ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap)
423a35dae8dSAdrian Chadd {
424a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
425a35dae8dSAdrian Chadd 	struct ath_buf *bf;
426a35dae8dSAdrian Chadd 	int otherant;
427a35dae8dSAdrian Chadd 
428a35dae8dSAdrian Chadd 	/*
429a35dae8dSAdrian Chadd 	 * Check if the previous beacon has gone out.  If
430a35dae8dSAdrian Chadd 	 * not don't try to post another, skip this period
431a35dae8dSAdrian Chadd 	 * and wait for the next.  Missed beacons indicate
432a35dae8dSAdrian Chadd 	 * a problem and should not occur.  If we miss too
433a35dae8dSAdrian Chadd 	 * many consecutive beacons reset the device.
434a35dae8dSAdrian Chadd 	 */
435a35dae8dSAdrian Chadd 	if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
436a35dae8dSAdrian Chadd 		sc->sc_bmisscount++;
437a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
438a35dae8dSAdrian Chadd 			"%s: missed %u consecutive beacons\n",
439a35dae8dSAdrian Chadd 			__func__, sc->sc_bmisscount);
440a35dae8dSAdrian Chadd 		if (sc->sc_bmisscount >= ath_bstuck_threshold)
441a35dae8dSAdrian Chadd 			taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
442a35dae8dSAdrian Chadd 		return;
443a35dae8dSAdrian Chadd 	}
444a35dae8dSAdrian Chadd 	if (sc->sc_bmisscount != 0) {
445a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
446a35dae8dSAdrian Chadd 			"%s: resume beacon xmit after %u misses\n",
447a35dae8dSAdrian Chadd 			__func__, sc->sc_bmisscount);
448a35dae8dSAdrian Chadd 		sc->sc_bmisscount = 0;
449a35dae8dSAdrian Chadd 	}
450a35dae8dSAdrian Chadd 
451a35dae8dSAdrian Chadd 	/*
452a35dae8dSAdrian Chadd 	 * Check recent per-antenna transmit statistics and flip
453a35dae8dSAdrian Chadd 	 * the default antenna if noticeably more frames went out
454a35dae8dSAdrian Chadd 	 * on the non-default antenna.
455a35dae8dSAdrian Chadd 	 * XXX assumes 2 anntenae
456a35dae8dSAdrian Chadd 	 */
457a35dae8dSAdrian Chadd 	if (!sc->sc_diversity) {
458a35dae8dSAdrian Chadd 		otherant = sc->sc_defant & 1 ? 2 : 1;
459a35dae8dSAdrian Chadd 		if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
460a35dae8dSAdrian Chadd 			ath_setdefantenna(sc, otherant);
461a35dae8dSAdrian Chadd 		sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
462a35dae8dSAdrian Chadd 	}
463a35dae8dSAdrian Chadd 
464a35dae8dSAdrian Chadd 	bf = ath_beacon_generate(sc, vap);
465a35dae8dSAdrian Chadd 	if (bf != NULL) {
466a35dae8dSAdrian Chadd 		/*
467a35dae8dSAdrian Chadd 		 * Stop any current dma and put the new frame on the queue.
468a35dae8dSAdrian Chadd 		 * This should never fail since we check above that no frames
469a35dae8dSAdrian Chadd 		 * are still pending on the queue.
470a35dae8dSAdrian Chadd 		 */
471a35dae8dSAdrian Chadd 		if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
472a35dae8dSAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_ANY,
473a35dae8dSAdrian Chadd 				"%s: beacon queue %u did not stop?\n",
474a35dae8dSAdrian Chadd 				__func__, sc->sc_bhalq);
475a35dae8dSAdrian Chadd 			/* NB: the HAL still stops DMA, so proceed */
476a35dae8dSAdrian Chadd 		}
477a35dae8dSAdrian Chadd 		ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
478a35dae8dSAdrian Chadd 		ath_hal_txstart(ah, sc->sc_bhalq);
479a35dae8dSAdrian Chadd 
480a35dae8dSAdrian Chadd 		sc->sc_stats.ast_be_xmit++;		/* XXX per-vap? */
481a35dae8dSAdrian Chadd 
482a35dae8dSAdrian Chadd 		/*
483a35dae8dSAdrian Chadd 		 * Record local TSF for our last send for use
484a35dae8dSAdrian Chadd 		 * in arbitrating slot collisions.
485a35dae8dSAdrian Chadd 		 */
486a35dae8dSAdrian Chadd 		/* XXX should take a locked ref to iv_bss */
487a35dae8dSAdrian Chadd 		vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);
488a35dae8dSAdrian Chadd 	}
489a35dae8dSAdrian Chadd }
490a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */
491