xref: /freebsd/sys/dev/ath/if_ath_tdma.c (revision b837332d0a4090781a3d7b01a092e164dd2a24ca)
1a35dae8dSAdrian Chadd /*-
2a35dae8dSAdrian Chadd  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3a35dae8dSAdrian Chadd  * All rights reserved.
4a35dae8dSAdrian Chadd  *
5a35dae8dSAdrian Chadd  * Redistribution and use in source and binary forms, with or without
6a35dae8dSAdrian Chadd  * modification, are permitted provided that the following conditions
7a35dae8dSAdrian Chadd  * are met:
8a35dae8dSAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
9a35dae8dSAdrian Chadd  *    notice, this list of conditions and the following disclaimer,
10a35dae8dSAdrian Chadd  *    without modification.
11a35dae8dSAdrian Chadd  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12a35dae8dSAdrian Chadd  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13a35dae8dSAdrian Chadd  *    redistribution must be conditioned upon including a substantially
14a35dae8dSAdrian Chadd  *    similar Disclaimer requirement for further binary redistribution.
15a35dae8dSAdrian Chadd  *
16a35dae8dSAdrian Chadd  * NO WARRANTY
17a35dae8dSAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18a35dae8dSAdrian Chadd  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19a35dae8dSAdrian Chadd  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20a35dae8dSAdrian Chadd  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21a35dae8dSAdrian Chadd  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22a35dae8dSAdrian Chadd  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23a35dae8dSAdrian Chadd  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24a35dae8dSAdrian Chadd  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25a35dae8dSAdrian Chadd  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26a35dae8dSAdrian Chadd  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27a35dae8dSAdrian Chadd  * THE POSSIBILITY OF SUCH DAMAGES.
28a35dae8dSAdrian Chadd  */
29a35dae8dSAdrian Chadd 
30a35dae8dSAdrian Chadd #include <sys/cdefs.h>
31a35dae8dSAdrian Chadd __FBSDID("$FreeBSD$");
32a35dae8dSAdrian Chadd 
33a35dae8dSAdrian Chadd /*
34a35dae8dSAdrian Chadd  * Driver for the Atheros Wireless LAN controller.
35a35dae8dSAdrian Chadd  *
36a35dae8dSAdrian Chadd  * This software is derived from work of Atsushi Onoe; his contribution
37a35dae8dSAdrian Chadd  * is greatly appreciated.
38a35dae8dSAdrian Chadd  */
39a35dae8dSAdrian Chadd 
40a35dae8dSAdrian Chadd #include "opt_inet.h"
41a35dae8dSAdrian Chadd #include "opt_ath.h"
42a35dae8dSAdrian Chadd /*
43a35dae8dSAdrian Chadd  * This is needed for register operations which are performed
44a35dae8dSAdrian Chadd  * by the driver - eg, calls to ath_hal_gettsf32().
45a35dae8dSAdrian Chadd  *
46a35dae8dSAdrian Chadd  * It's also required for any AH_DEBUG checks in here, eg the
47a35dae8dSAdrian Chadd  * module dependencies.
48a35dae8dSAdrian Chadd  */
49a35dae8dSAdrian Chadd #include "opt_ah.h"
50a35dae8dSAdrian Chadd #include "opt_wlan.h"
51a35dae8dSAdrian Chadd 
52a35dae8dSAdrian Chadd #include <sys/param.h>
53a35dae8dSAdrian Chadd #include <sys/systm.h>
54a35dae8dSAdrian Chadd #include <sys/sysctl.h>
55a35dae8dSAdrian Chadd #include <sys/mbuf.h>
56a35dae8dSAdrian Chadd #include <sys/malloc.h>
57a35dae8dSAdrian Chadd #include <sys/lock.h>
58a35dae8dSAdrian Chadd #include <sys/mutex.h>
59a35dae8dSAdrian Chadd #include <sys/kernel.h>
60a35dae8dSAdrian Chadd #include <sys/socket.h>
61a35dae8dSAdrian Chadd #include <sys/sockio.h>
62a35dae8dSAdrian Chadd #include <sys/errno.h>
63a35dae8dSAdrian Chadd #include <sys/callout.h>
64a35dae8dSAdrian Chadd #include <sys/bus.h>
65a35dae8dSAdrian Chadd #include <sys/endian.h>
66a35dae8dSAdrian Chadd #include <sys/kthread.h>
67a35dae8dSAdrian Chadd #include <sys/taskqueue.h>
68a35dae8dSAdrian Chadd #include <sys/priv.h>
69a35dae8dSAdrian Chadd #include <sys/module.h>
70a35dae8dSAdrian Chadd #include <sys/ktr.h>
71a35dae8dSAdrian Chadd #include <sys/smp.h>	/* for mp_ncpus */
72a35dae8dSAdrian Chadd 
73a35dae8dSAdrian Chadd #include <machine/bus.h>
74a35dae8dSAdrian Chadd 
75a35dae8dSAdrian Chadd #include <net/if.h>
76a35dae8dSAdrian Chadd #include <net/if_dl.h>
77a35dae8dSAdrian Chadd #include <net/if_media.h>
78a35dae8dSAdrian Chadd #include <net/if_types.h>
79a35dae8dSAdrian Chadd #include <net/if_arp.h>
80a35dae8dSAdrian Chadd #include <net/ethernet.h>
81a35dae8dSAdrian Chadd #include <net/if_llc.h>
82a35dae8dSAdrian Chadd 
83a35dae8dSAdrian Chadd #include <net80211/ieee80211_var.h>
84a35dae8dSAdrian Chadd #include <net80211/ieee80211_regdomain.h>
85a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_SUPERG
86a35dae8dSAdrian Chadd #include <net80211/ieee80211_superg.h>
87a35dae8dSAdrian Chadd #endif
88a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
89a35dae8dSAdrian Chadd #include <net80211/ieee80211_tdma.h>
90a35dae8dSAdrian Chadd #endif
91a35dae8dSAdrian Chadd 
92a35dae8dSAdrian Chadd #include <net/bpf.h>
93a35dae8dSAdrian Chadd 
94a35dae8dSAdrian Chadd #ifdef INET
95a35dae8dSAdrian Chadd #include <netinet/in.h>
96a35dae8dSAdrian Chadd #include <netinet/if_ether.h>
97a35dae8dSAdrian Chadd #endif
98a35dae8dSAdrian Chadd 
99a35dae8dSAdrian Chadd #include <dev/ath/if_athvar.h>
100a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_devid.h>		/* XXX for softled */
101a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_diagcodes.h>
102a35dae8dSAdrian Chadd 
103a35dae8dSAdrian Chadd #include <dev/ath/if_ath_debug.h>
104a35dae8dSAdrian Chadd #include <dev/ath/if_ath_misc.h>
105a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tsf.h>
106a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tx.h>
107a35dae8dSAdrian Chadd #include <dev/ath/if_ath_sysctl.h>
108a35dae8dSAdrian Chadd #include <dev/ath/if_ath_led.h>
109a35dae8dSAdrian Chadd #include <dev/ath/if_ath_keycache.h>
110a35dae8dSAdrian Chadd #include <dev/ath/if_ath_rx.h>
111a35dae8dSAdrian Chadd #include <dev/ath/if_ath_beacon.h>
112a35dae8dSAdrian Chadd #include <dev/ath/if_athdfs.h>
113a35dae8dSAdrian Chadd 
114a35dae8dSAdrian Chadd #ifdef ATH_TX99_DIAG
115a35dae8dSAdrian Chadd #include <dev/ath/ath_tx99/ath_tx99.h>
116a35dae8dSAdrian Chadd #endif
117a35dae8dSAdrian Chadd 
1184bda23f9SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
1194bda23f9SAdrian Chadd #include <dev/ath/if_ath_alq.h>
1204bda23f9SAdrian Chadd #endif
1214bda23f9SAdrian Chadd 
122a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
123a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tdma.h>
124a35dae8dSAdrian Chadd 
125a35dae8dSAdrian Chadd static void	ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt,
126a35dae8dSAdrian Chadd 		    u_int32_t bintval);
127a35dae8dSAdrian Chadd static void	ath_tdma_bintvalsetup(struct ath_softc *sc,
128a35dae8dSAdrian Chadd 		    const struct ieee80211_tdma_state *tdma);
129a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */
130a35dae8dSAdrian Chadd 
131a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
132a35dae8dSAdrian Chadd static void
133a35dae8dSAdrian Chadd ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval)
134a35dae8dSAdrian Chadd {
135a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
136a35dae8dSAdrian Chadd 	HAL_BEACON_TIMERS bt;
137a35dae8dSAdrian Chadd 
138a35dae8dSAdrian Chadd 	bt.bt_intval = bintval | HAL_BEACON_ENA;
139a35dae8dSAdrian Chadd 	bt.bt_nexttbtt = nexttbtt;
140a35dae8dSAdrian Chadd 	bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep;
141a35dae8dSAdrian Chadd 	bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep;
142a35dae8dSAdrian Chadd 	bt.bt_nextatim = nexttbtt+1;
143a35dae8dSAdrian Chadd 	/* Enables TBTT, DBA, SWBA timers by default */
144a35dae8dSAdrian Chadd 	bt.bt_flags = 0;
1454bda23f9SAdrian Chadd #if 0
1464bda23f9SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
1474bda23f9SAdrian Chadd 	    "%s: intval=%d (0x%08x) nexttbtt=%u (0x%08x), nextdba=%u (0x%08x), nextswba=%u (0x%08x),nextatim=%u (0x%08x)\n",
1484bda23f9SAdrian Chadd 	    __func__,
1494bda23f9SAdrian Chadd 	    bt.bt_intval,
1504bda23f9SAdrian Chadd 	    bt.bt_intval,
1514bda23f9SAdrian Chadd 	    bt.bt_nexttbtt,
1524bda23f9SAdrian Chadd 	    bt.bt_nexttbtt,
1534bda23f9SAdrian Chadd 	    bt.bt_nextdba,
1544bda23f9SAdrian Chadd 	    bt.bt_nextdba,
1554bda23f9SAdrian Chadd 	    bt.bt_nextswba,
1564bda23f9SAdrian Chadd 	    bt.bt_nextswba,
1574bda23f9SAdrian Chadd 	    bt.bt_nextatim,
1584bda23f9SAdrian Chadd 	    bt.bt_nextatim);
1594bda23f9SAdrian Chadd #endif
1604bda23f9SAdrian Chadd 
161584295fcSAdrian Chadd #ifdef	ATH_DEBUG_ALQ
1624bda23f9SAdrian Chadd 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET)) {
1634bda23f9SAdrian Chadd 		struct if_ath_alq_tdma_timer_set t;
1644bda23f9SAdrian Chadd 		t.bt_intval = htobe32(bt.bt_intval);
1654bda23f9SAdrian Chadd 		t.bt_nexttbtt = htobe32(bt.bt_nexttbtt);
1664bda23f9SAdrian Chadd 		t.bt_nextdba = htobe32(bt.bt_nextdba);
1674bda23f9SAdrian Chadd 		t.bt_nextswba = htobe32(bt.bt_nextswba);
1684bda23f9SAdrian Chadd 		t.bt_nextatim = htobe32(bt.bt_nextatim);
1694bda23f9SAdrian Chadd 		t.bt_flags = htobe32(bt.bt_flags);
1704bda23f9SAdrian Chadd 		t.sc_tdmadbaprep = htobe32(sc->sc_tdmadbaprep);
1714bda23f9SAdrian Chadd 		t.sc_tdmaswbaprep = htobe32(sc->sc_tdmaswbaprep);
1724bda23f9SAdrian Chadd 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET,
1734bda23f9SAdrian Chadd 		    sizeof(t), (char *) &t);
1744bda23f9SAdrian Chadd 	}
175584295fcSAdrian Chadd #endif
1764bda23f9SAdrian Chadd 
1774bda23f9SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
1784bda23f9SAdrian Chadd 	    "%s: nexttbtt=%u (0x%08x), nexttbtt tsf=%lld (0x%08llx)\n",
1794bda23f9SAdrian Chadd 	    __func__,
1804bda23f9SAdrian Chadd 	    bt.bt_nexttbtt,
1814bda23f9SAdrian Chadd 	    bt.bt_nexttbtt,
1824bda23f9SAdrian Chadd 	    (long long) ( ((u_int64_t) (bt.bt_nexttbtt)) << 10),
1834bda23f9SAdrian Chadd 	    (long long) ( ((u_int64_t) (bt.bt_nexttbtt)) << 10));
184a35dae8dSAdrian Chadd 	ath_hal_beaconsettimers(ah, &bt);
185a35dae8dSAdrian Chadd }
186a35dae8dSAdrian Chadd 
187a35dae8dSAdrian Chadd /*
188a35dae8dSAdrian Chadd  * Calculate the beacon interval.  This is periodic in the
189a35dae8dSAdrian Chadd  * superframe for the bss.  We assume each station is configured
190a35dae8dSAdrian Chadd  * identically wrt transmit rate so the guard time we calculate
191a35dae8dSAdrian Chadd  * above will be the same on all stations.  Note we need to
192a35dae8dSAdrian Chadd  * factor in the xmit time because the hardware will schedule
193a35dae8dSAdrian Chadd  * a frame for transmit if the start of the frame is within
194a35dae8dSAdrian Chadd  * the burst time.  When we get hardware that properly kills
195a35dae8dSAdrian Chadd  * frames in the PCU we can reduce/eliminate the guard time.
196a35dae8dSAdrian Chadd  *
197a35dae8dSAdrian Chadd  * Roundup to 1024 is so we have 1 TU buffer in the guard time
198a35dae8dSAdrian Chadd  * to deal with the granularity of the nexttbtt timer.  11n MAC's
199a35dae8dSAdrian Chadd  * with 1us timer granularity should allow us to reduce/eliminate
200a35dae8dSAdrian Chadd  * this.
201a35dae8dSAdrian Chadd  */
202a35dae8dSAdrian Chadd static void
203a35dae8dSAdrian Chadd ath_tdma_bintvalsetup(struct ath_softc *sc,
204a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_state *tdma)
205a35dae8dSAdrian Chadd {
206a35dae8dSAdrian Chadd 	/* copy from vap state (XXX check all vaps have same value?) */
207a35dae8dSAdrian Chadd 	sc->sc_tdmaslotlen = tdma->tdma_slotlen;
208a35dae8dSAdrian Chadd 
209a35dae8dSAdrian Chadd 	sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) *
210a35dae8dSAdrian Chadd 		tdma->tdma_slotcnt, 1024);
211a35dae8dSAdrian Chadd 	sc->sc_tdmabintval >>= 10;		/* TSF -> TU */
212a35dae8dSAdrian Chadd 	if (sc->sc_tdmabintval & 1)
213a35dae8dSAdrian Chadd 		sc->sc_tdmabintval++;
214a35dae8dSAdrian Chadd 
215a35dae8dSAdrian Chadd 	if (tdma->tdma_slot == 0) {
216a35dae8dSAdrian Chadd 		/*
217a35dae8dSAdrian Chadd 		 * Only slot 0 beacons; other slots respond.
218a35dae8dSAdrian Chadd 		 */
219a35dae8dSAdrian Chadd 		sc->sc_imask |= HAL_INT_SWBA;
220a35dae8dSAdrian Chadd 		sc->sc_tdmaswba = 0;		/* beacon immediately */
221a35dae8dSAdrian Chadd 	} else {
222a35dae8dSAdrian Chadd 		/* XXX all vaps must be slot 0 or slot !0 */
223a35dae8dSAdrian Chadd 		sc->sc_imask &= ~HAL_INT_SWBA;
224a35dae8dSAdrian Chadd 	}
225a35dae8dSAdrian Chadd }
226a35dae8dSAdrian Chadd 
227a35dae8dSAdrian Chadd /*
228a35dae8dSAdrian Chadd  * Max 802.11 overhead.  This assumes no 4-address frames and
229a35dae8dSAdrian Chadd  * the encapsulation done by ieee80211_encap (llc).  We also
230a35dae8dSAdrian Chadd  * include potential crypto overhead.
231a35dae8dSAdrian Chadd  */
232a35dae8dSAdrian Chadd #define	IEEE80211_MAXOVERHEAD \
233a35dae8dSAdrian Chadd 	(sizeof(struct ieee80211_qosframe) \
234a35dae8dSAdrian Chadd 	 + sizeof(struct llc) \
235a35dae8dSAdrian Chadd 	 + IEEE80211_ADDR_LEN \
236a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_IVLEN \
237a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_KIDLEN \
238a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_CRCLEN \
239a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_MICLEN \
240a35dae8dSAdrian Chadd 	 + IEEE80211_CRC_LEN)
241a35dae8dSAdrian Chadd 
242a35dae8dSAdrian Chadd /*
243a35dae8dSAdrian Chadd  * Setup initially for tdma operation.  Start the beacon
244a35dae8dSAdrian Chadd  * timers and enable SWBA if we are slot 0.  Otherwise
245a35dae8dSAdrian Chadd  * we wait for slot 0 to arrive so we can sync up before
246a35dae8dSAdrian Chadd  * starting to transmit.
247a35dae8dSAdrian Chadd  */
248a35dae8dSAdrian Chadd void
249a35dae8dSAdrian Chadd ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap)
250a35dae8dSAdrian Chadd {
251a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
252a35dae8dSAdrian Chadd 	struct ifnet *ifp = sc->sc_ifp;
253a35dae8dSAdrian Chadd 	struct ieee80211com *ic = ifp->if_l2com;
254a35dae8dSAdrian Chadd 	const struct ieee80211_txparam *tp;
255a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_state *tdma = NULL;
256a35dae8dSAdrian Chadd 	int rix;
257a35dae8dSAdrian Chadd 
258a35dae8dSAdrian Chadd 	if (vap == NULL) {
259a35dae8dSAdrian Chadd 		vap = TAILQ_FIRST(&ic->ic_vaps);   /* XXX */
260a35dae8dSAdrian Chadd 		if (vap == NULL) {
261a35dae8dSAdrian Chadd 			if_printf(ifp, "%s: no vaps?\n", __func__);
262a35dae8dSAdrian Chadd 			return;
263a35dae8dSAdrian Chadd 		}
264a35dae8dSAdrian Chadd 	}
265a35dae8dSAdrian Chadd 	/* XXX should take a locked ref to iv_bss */
266a35dae8dSAdrian Chadd 	tp = vap->iv_bss->ni_txparms;
267a35dae8dSAdrian Chadd 	/*
268a35dae8dSAdrian Chadd 	 * Calculate the guard time for each slot.  This is the
269a35dae8dSAdrian Chadd 	 * time to send a maximal-size frame according to the
270a35dae8dSAdrian Chadd 	 * fixed/lowest transmit rate.  Note that the interface
271a35dae8dSAdrian Chadd 	 * mtu does not include the 802.11 overhead so we must
272a35dae8dSAdrian Chadd 	 * tack that on (ath_hal_computetxtime includes the
273a35dae8dSAdrian Chadd 	 * preamble and plcp in it's calculation).
274a35dae8dSAdrian Chadd 	 */
275a35dae8dSAdrian Chadd 	tdma = vap->iv_tdma;
276a35dae8dSAdrian Chadd 	if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
277a35dae8dSAdrian Chadd 		rix = ath_tx_findrix(sc, tp->ucastrate);
278a35dae8dSAdrian Chadd 	else
279a35dae8dSAdrian Chadd 		rix = ath_tx_findrix(sc, tp->mcastrate);
280a35dae8dSAdrian Chadd 	/* XXX short preamble assumed */
281a35dae8dSAdrian Chadd 	sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,
282a35dae8dSAdrian Chadd 		ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE);
283a35dae8dSAdrian Chadd 
284a35dae8dSAdrian Chadd 	ath_hal_intrset(ah, 0);
285a35dae8dSAdrian Chadd 
286a35dae8dSAdrian Chadd 	ath_beaconq_config(sc);			/* setup h/w beacon q */
287a35dae8dSAdrian Chadd 	if (sc->sc_setcca)
288a35dae8dSAdrian Chadd 		ath_hal_setcca(ah, AH_FALSE);	/* disable CCA */
289a35dae8dSAdrian Chadd 	ath_tdma_bintvalsetup(sc, tdma);	/* calculate beacon interval */
290a35dae8dSAdrian Chadd 	ath_tdma_settimers(sc, sc->sc_tdmabintval,
291a35dae8dSAdrian Chadd 		sc->sc_tdmabintval | HAL_BEACON_RESET_TSF);
292a35dae8dSAdrian Chadd 	sc->sc_syncbeacon = 0;
293a35dae8dSAdrian Chadd 
294a35dae8dSAdrian Chadd 	sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER;
295a35dae8dSAdrian Chadd 	sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER;
296a35dae8dSAdrian Chadd 
297a35dae8dSAdrian Chadd 	ath_hal_intrset(ah, sc->sc_imask);
298a35dae8dSAdrian Chadd 
299a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u "
300a35dae8dSAdrian Chadd 	    "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__,
301a35dae8dSAdrian Chadd 	    tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt,
302a35dae8dSAdrian Chadd 	    tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval,
303a35dae8dSAdrian Chadd 	    sc->sc_tdmadbaprep);
3044bda23f9SAdrian Chadd 
3054bda23f9SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
3064bda23f9SAdrian Chadd 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG)) {
3074bda23f9SAdrian Chadd 		struct if_ath_alq_tdma_timer_config t;
3084bda23f9SAdrian Chadd 
3094bda23f9SAdrian Chadd 		t.tdma_slot = htobe32(tdma->tdma_slot);
3104bda23f9SAdrian Chadd 		t.tdma_slotlen = htobe32(tdma->tdma_slotlen);
3114bda23f9SAdrian Chadd 		t.tdma_slotcnt = htobe32(tdma->tdma_slotcnt);
3124bda23f9SAdrian Chadd 		t.tdma_bintval = htobe32(tdma->tdma_bintval);
3134bda23f9SAdrian Chadd 		t.tdma_guard = htobe32(sc->sc_tdmaguard);
3144bda23f9SAdrian Chadd 		t.tdma_scbintval = htobe32(sc->sc_tdmabintval);
3154bda23f9SAdrian Chadd 		t.tdma_dbaprep = htobe32(sc->sc_tdmadbaprep);
3164bda23f9SAdrian Chadd 
3174bda23f9SAdrian Chadd 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG,
3184bda23f9SAdrian Chadd 		    sizeof(t), (char *) &t);
3194bda23f9SAdrian Chadd 	}
3204bda23f9SAdrian Chadd #endif	/* ATH_DEBUG_ALQ */
321a35dae8dSAdrian Chadd }
322a35dae8dSAdrian Chadd 
323a35dae8dSAdrian Chadd /*
324a35dae8dSAdrian Chadd  * Update tdma operation.  Called from the 802.11 layer
325a35dae8dSAdrian Chadd  * when a beacon is received from the TDMA station operating
326a35dae8dSAdrian Chadd  * in the slot immediately preceding us in the bss.  Use
327a35dae8dSAdrian Chadd  * the rx timestamp for the beacon frame to update our
328a35dae8dSAdrian Chadd  * beacon timers so we follow their schedule.  Note that
329a35dae8dSAdrian Chadd  * by using the rx timestamp we implicitly include the
330a35dae8dSAdrian Chadd  * propagation delay in our schedule.
331821311eaSAdrian Chadd  *
332821311eaSAdrian Chadd  * XXX TODO: since the changes for the AR5416 and later chips
333821311eaSAdrian Chadd  * involved changing the TSF/TU calculations, we need to make
334821311eaSAdrian Chadd  * sure that various calculations wrap consistently.
335821311eaSAdrian Chadd  *
336821311eaSAdrian Chadd  * A lot of the problems stemmed from the calculations wrapping
337821311eaSAdrian Chadd  * at 65,535 TU.  Since a lot of the math is still being done in
338821311eaSAdrian Chadd  * TU, please audit it to ensure that when the TU values programmed
339821311eaSAdrian Chadd  * into the timers wrap at (2^31)-1 TSF, all the various terms
340821311eaSAdrian Chadd  * wrap consistently.
341a35dae8dSAdrian Chadd  */
342a35dae8dSAdrian Chadd void
343a35dae8dSAdrian Chadd ath_tdma_update(struct ieee80211_node *ni,
344a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_param *tdma, int changed)
345a35dae8dSAdrian Chadd {
346a35dae8dSAdrian Chadd #define	TSF_TO_TU(_h,_l) \
347a35dae8dSAdrian Chadd 	((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
348a35dae8dSAdrian Chadd #define	TU_TO_TSF(_tu)	(((u_int64_t)(_tu)) << 10)
349a35dae8dSAdrian Chadd 	struct ieee80211vap *vap = ni->ni_vap;
350a35dae8dSAdrian Chadd 	struct ieee80211com *ic = ni->ni_ic;
351a35dae8dSAdrian Chadd 	struct ath_softc *sc = ic->ic_ifp->if_softc;
352a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
353a35dae8dSAdrian Chadd 	const HAL_RATE_TABLE *rt = sc->sc_currates;
354e6f1a34aSAdrian Chadd 	u_int64_t tsf, rstamp, nextslot, nexttbtt, nexttbtt_full;
355a35dae8dSAdrian Chadd 	u_int32_t txtime, nextslottu;
356a35dae8dSAdrian Chadd 	int32_t tudelta, tsfdelta;
357a35dae8dSAdrian Chadd 	const struct ath_rx_status *rs;
358a35dae8dSAdrian Chadd 	int rix;
359a35dae8dSAdrian Chadd 
360a35dae8dSAdrian Chadd 	sc->sc_stats.ast_tdma_update++;
361a35dae8dSAdrian Chadd 
362a35dae8dSAdrian Chadd 	/*
363a35dae8dSAdrian Chadd 	 * Check for and adopt configuration changes.
364a35dae8dSAdrian Chadd 	 */
365a35dae8dSAdrian Chadd 	if (changed != 0) {
366a35dae8dSAdrian Chadd 		const struct ieee80211_tdma_state *ts = vap->iv_tdma;
367a35dae8dSAdrian Chadd 
368a35dae8dSAdrian Chadd 		ath_tdma_bintvalsetup(sc, ts);
369a35dae8dSAdrian Chadd 		if (changed & TDMA_UPDATE_SLOTLEN)
370a35dae8dSAdrian Chadd 			ath_wme_update(ic);
371a35dae8dSAdrian Chadd 
372a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_TDMA,
373a35dae8dSAdrian Chadd 		    "%s: adopt slot %u slotcnt %u slotlen %u us "
374a35dae8dSAdrian Chadd 		    "bintval %u TU\n", __func__,
375a35dae8dSAdrian Chadd 		    ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen,
376a35dae8dSAdrian Chadd 		    sc->sc_tdmabintval);
377a35dae8dSAdrian Chadd 
378a35dae8dSAdrian Chadd 		/* XXX right? */
379a35dae8dSAdrian Chadd 		ath_hal_intrset(ah, sc->sc_imask);
380a35dae8dSAdrian Chadd 		/* NB: beacon timers programmed below */
381a35dae8dSAdrian Chadd 	}
382a35dae8dSAdrian Chadd 
383a35dae8dSAdrian Chadd 	/* extend rx timestamp to 64 bits */
384a35dae8dSAdrian Chadd 	rs = sc->sc_lastrs;
385a35dae8dSAdrian Chadd 	tsf = ath_hal_gettsf64(ah);
386a35dae8dSAdrian Chadd 	rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
387a35dae8dSAdrian Chadd 	/*
388a35dae8dSAdrian Chadd 	 * The rx timestamp is set by the hardware on completing
389a35dae8dSAdrian Chadd 	 * reception (at the point where the rx descriptor is DMA'd
390a35dae8dSAdrian Chadd 	 * to the host).  To find the start of our next slot we
391a35dae8dSAdrian Chadd 	 * must adjust this time by the time required to send
392a35dae8dSAdrian Chadd 	 * the packet just received.
393a35dae8dSAdrian Chadd 	 */
394a35dae8dSAdrian Chadd 	rix = rt->rateCodeToIndex[rs->rs_rate];
395a35dae8dSAdrian Chadd 	txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix,
396a35dae8dSAdrian Chadd 	    rt->info[rix].shortPreamble);
397a35dae8dSAdrian Chadd 	/* NB: << 9 is to cvt to TU and /2 */
398a35dae8dSAdrian Chadd 	nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9);
3994bda23f9SAdrian Chadd 
400e6f1a34aSAdrian Chadd 	/*
401e6f1a34aSAdrian Chadd 	 * For 802.11n chips: nextslottu needs to be the full TSF space,
402e6f1a34aSAdrian Chadd 	 * not just 0..65535 TU.
403e6f1a34aSAdrian Chadd 	 */
404e6f1a34aSAdrian Chadd 	nextslottu = TSF_TO_TU(nextslot>>32, nextslot);
405a35dae8dSAdrian Chadd 	/*
406a35dae8dSAdrian Chadd 	 * Retrieve the hardware NextTBTT in usecs
407a35dae8dSAdrian Chadd 	 * and calculate the difference between what the
408a35dae8dSAdrian Chadd 	 * other station thinks and what we have programmed.  This
409a35dae8dSAdrian Chadd 	 * lets us figure how to adjust our timers to match.  The
410a35dae8dSAdrian Chadd 	 * adjustments are done by pulling the TSF forward and possibly
411a35dae8dSAdrian Chadd 	 * rewriting the beacon timers.
412a35dae8dSAdrian Chadd 	 */
413ddee9211SAdrian Chadd 	/*
414ddee9211SAdrian Chadd 	 * The logic here assumes the nexttbtt counter is in TSF
415ddee9211SAdrian Chadd 	 * but the prr-11n NICs are in TU.  The HAL shifts them
416ddee9211SAdrian Chadd 	 * to TSF but there's two important differences:
417ddee9211SAdrian Chadd 	 *
418ddee9211SAdrian Chadd 	 * + The TU->TSF values have 0's for the low 9 bits, and
419ddee9211SAdrian Chadd 	 * + The counter wraps at TU_TO_TSF(HAL_BEACON_PERIOD + 1) for
420ddee9211SAdrian Chadd 	 *   the pre-11n NICs, but not for the 11n NICs.
421ddee9211SAdrian Chadd 	 *
422ddee9211SAdrian Chadd 	 * So for now, just make sure the nexttbtt value we get
423ddee9211SAdrian Chadd 	 * matches the second issue or once nexttbtt exceeds this
424ddee9211SAdrian Chadd 	 * value, tsfdelta ends up becoming very negative and all
425ddee9211SAdrian Chadd 	 * of the adjustments get very messed up.
426ddee9211SAdrian Chadd 	 */
427e6f1a34aSAdrian Chadd 
428e6f1a34aSAdrian Chadd 	/*
429e6f1a34aSAdrian Chadd 	 * We need to track the full nexttbtt rather than having it
430e6f1a34aSAdrian Chadd 	 * truncated at HAL_BEACON_PERIOD, as programming the
431e6f1a34aSAdrian Chadd 	 * nexttbtt (and related) registers for the 11n chips is
432e6f1a34aSAdrian Chadd 	 * actually going to take the full 32 bit space, rather than
433e6f1a34aSAdrian Chadd 	 * just 0..65535 TU.
434e6f1a34aSAdrian Chadd 	 */
435e6f1a34aSAdrian Chadd 	nexttbtt_full = ath_hal_getnexttbtt(ah);
436e6f1a34aSAdrian Chadd 	nexttbtt = nexttbtt_full % (TU_TO_TSF(HAL_BEACON_PERIOD + 1));
437a35dae8dSAdrian Chadd 	tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD + 1)) - nexttbtt);
438a35dae8dSAdrian Chadd 
439a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
4407c783791SAdrian Chadd 	    "rs->rstamp %llu rstamp %llu tsf %llu txtime %d, nextslot %llu, "
4417c783791SAdrian Chadd 	    "nextslottu %d, nextslottume %d\n",
4427c783791SAdrian Chadd 	    (unsigned long long) rs->rs_tstamp, rstamp, tsf, txtime,
4437c783791SAdrian Chadd 	    nextslot, nextslottu, TSF_TO_TU(nextslot >> 32, nextslot));
4447c783791SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA,
4457c783791SAdrian Chadd 	    "  beacon tstamp: %llu (0x%016llx)\n",
4467c783791SAdrian Chadd 	    le64toh(ni->ni_tstamp.tsf),
4477c783791SAdrian Chadd 	    le64toh(ni->ni_tstamp.tsf));
4487c783791SAdrian Chadd 
4497c783791SAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
4504bda23f9SAdrian Chadd 	    "nexttbtt %llu (0x%08llx) tsfdelta %d avg +%d/-%d\n",
4514bda23f9SAdrian Chadd 	    nexttbtt,
4524bda23f9SAdrian Chadd 	    (long long) nexttbtt,
4534bda23f9SAdrian Chadd 	    tsfdelta,
454a35dae8dSAdrian Chadd 	    TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam));
455a35dae8dSAdrian Chadd 
456a35dae8dSAdrian Chadd 	if (tsfdelta < 0) {
457a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
458a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta);
459a35dae8dSAdrian Chadd 		tsfdelta = -tsfdelta % 1024;
460a35dae8dSAdrian Chadd 		nextslottu++;
461a35dae8dSAdrian Chadd 	} else if (tsfdelta > 0) {
462a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta);
463a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
464a35dae8dSAdrian Chadd 		tsfdelta = 1024 - (tsfdelta % 1024);
465a35dae8dSAdrian Chadd 		nextslottu++;
466a35dae8dSAdrian Chadd 	} else {
467a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
468a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
469a35dae8dSAdrian Chadd 	}
470e6f1a34aSAdrian Chadd 	tudelta = nextslottu - TSF_TO_TU(nexttbtt_full >> 32, nexttbtt_full);
471a35dae8dSAdrian Chadd 
4727c783791SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
4737c783791SAdrian Chadd 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE)) {
4747c783791SAdrian Chadd 		struct if_ath_alq_tdma_beacon_state t;
4757c783791SAdrian Chadd 		t.rx_tsf = htobe64(rstamp);
4767c783791SAdrian Chadd 		t.beacon_tsf = htobe64(le64toh(ni->ni_tstamp.tsf));
4777c783791SAdrian Chadd 		t.tsf64 = htobe64(tsf);
4787c783791SAdrian Chadd 		t.nextslot_tsf = htobe64(nextslot);
4797c783791SAdrian Chadd 		t.nextslot_tu = htobe32(nextslottu);
4807c783791SAdrian Chadd 		t.txtime = htobe32(txtime);
4817c783791SAdrian Chadd 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE,
4827c783791SAdrian Chadd 		    sizeof(t), (char *) &t);
4837c783791SAdrian Chadd 	}
4847c783791SAdrian Chadd 
4857c783791SAdrian Chadd 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC)) {
4867c783791SAdrian Chadd 		struct if_ath_alq_tdma_slot_calc t;
4877c783791SAdrian Chadd 
4887c783791SAdrian Chadd 		t.nexttbtt = htobe64(nexttbtt_full);
4897c783791SAdrian Chadd 		t.next_slot = htobe64(nextslot);
4907c783791SAdrian Chadd 		t.tsfdelta = htobe32(tsfdelta);
4917c783791SAdrian Chadd 		t.avg_plus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltap));
4927c783791SAdrian Chadd 		t.avg_minus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltam));
4937c783791SAdrian Chadd 
4947c783791SAdrian Chadd 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC,
4957c783791SAdrian Chadd 		    sizeof(t), (char *) &t);
4967c783791SAdrian Chadd 	}
4977c783791SAdrian Chadd #endif
4987c783791SAdrian Chadd 
499a35dae8dSAdrian Chadd 	/*
500a35dae8dSAdrian Chadd 	 * Copy sender's timetstamp into tdma ie so they can
501a35dae8dSAdrian Chadd 	 * calculate roundtrip time.  We submit a beacon frame
502a35dae8dSAdrian Chadd 	 * below after any timer adjustment.  The frame goes out
503a35dae8dSAdrian Chadd 	 * at the next TBTT so the sender can calculate the
504a35dae8dSAdrian Chadd 	 * roundtrip by inspecting the tdma ie in our beacon frame.
505a35dae8dSAdrian Chadd 	 *
506a35dae8dSAdrian Chadd 	 * NB: This tstamp is subtlely preserved when
507a35dae8dSAdrian Chadd 	 *     IEEE80211_BEACON_TDMA is marked (e.g. when the
508a35dae8dSAdrian Chadd 	 *     slot position changes) because ieee80211_add_tdma
509a35dae8dSAdrian Chadd 	 *     skips over the data.
510a35dae8dSAdrian Chadd 	 */
511a35dae8dSAdrian Chadd 	memcpy(ATH_VAP(vap)->av_boff.bo_tdma +
512a35dae8dSAdrian Chadd 		__offsetof(struct ieee80211_tdma_param, tdma_tstamp),
513a35dae8dSAdrian Chadd 		&ni->ni_tstamp.data, 8);
514a35dae8dSAdrian Chadd #if 0
515a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
516a35dae8dSAdrian Chadd 	    "tsf %llu nextslot %llu (%d, %d) nextslottu %u nexttbtt %llu (%d)\n",
517a35dae8dSAdrian Chadd 	    (unsigned long long) tsf, (unsigned long long) nextslot,
518a35dae8dSAdrian Chadd 	    (int)(nextslot - tsf), tsfdelta, nextslottu, nexttbtt, tudelta);
519a35dae8dSAdrian Chadd #endif
520a35dae8dSAdrian Chadd 	/*
521a35dae8dSAdrian Chadd 	 * Adjust the beacon timers only when pulling them forward
522a35dae8dSAdrian Chadd 	 * or when going back by less than the beacon interval.
523a35dae8dSAdrian Chadd 	 * Negative jumps larger than the beacon interval seem to
524a35dae8dSAdrian Chadd 	 * cause the timers to stop and generally cause instability.
525a35dae8dSAdrian Chadd 	 * This basically filters out jumps due to missed beacons.
526a35dae8dSAdrian Chadd 	 */
527a35dae8dSAdrian Chadd 	if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) {
5284bda23f9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
5294bda23f9SAdrian Chadd 		    "%s: calling ath_tdma_settimers; nextslottu=%d, bintval=%d\n",
5304bda23f9SAdrian Chadd 		    __func__,
5314bda23f9SAdrian Chadd 		    nextslottu,
5324bda23f9SAdrian Chadd 		    sc->sc_tdmabintval);
533a35dae8dSAdrian Chadd 		ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval);
534a35dae8dSAdrian Chadd 		sc->sc_stats.ast_tdma_timers++;
535a35dae8dSAdrian Chadd 	}
536a35dae8dSAdrian Chadd 	if (tsfdelta > 0) {
53784dd5933SAdrian Chadd 		uint64_t tsf;
53884dd5933SAdrian Chadd 
53984dd5933SAdrian Chadd 		/* XXX should just teach ath_hal_adjusttsf() to do this */
54084dd5933SAdrian Chadd 		tsf = ath_hal_gettsf64(ah);
54184dd5933SAdrian Chadd 		ath_hal_settsf64(ah, tsf + tsfdelta);
5424bda23f9SAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
5434bda23f9SAdrian Chadd 		    "%s: calling ath_hal_adjusttsf: TSF=%llu, tsfdelta=%d\n",
5444bda23f9SAdrian Chadd 		    __func__,
5454fd97455SAdrian Chadd 		    tsf,
5464bda23f9SAdrian Chadd 		    tsfdelta);
5474bda23f9SAdrian Chadd 
5484bda23f9SAdrian Chadd #ifdef	ATH_DEBUG_ALQ
5494bda23f9SAdrian Chadd 		if (if_ath_alq_checkdebug(&sc->sc_alq,
5504bda23f9SAdrian Chadd 		    ATH_ALQ_TDMA_TSF_ADJUST)) {
5514bda23f9SAdrian Chadd 			struct if_ath_alq_tdma_tsf_adjust t;
5524bda23f9SAdrian Chadd 
5534bda23f9SAdrian Chadd 			t.tsfdelta = htobe32(tsfdelta);
554821311eaSAdrian Chadd 			t.tsf64_old = htobe64(tsf);
555821311eaSAdrian Chadd 			t.tsf64_new = htobe64(tsf + tsfdelta);
5564bda23f9SAdrian Chadd 			if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TSF_ADJUST,
5574bda23f9SAdrian Chadd 			    sizeof(t), (char *) &t);
5584bda23f9SAdrian Chadd 		}
5594bda23f9SAdrian Chadd #endif	/* ATH_DEBUG_ALQ */
560a35dae8dSAdrian Chadd 		sc->sc_stats.ast_tdma_tsf++;
561a35dae8dSAdrian Chadd 	}
562a35dae8dSAdrian Chadd 	ath_tdma_beacon_send(sc, vap);		/* prepare response */
563a35dae8dSAdrian Chadd #undef TU_TO_TSF
564a35dae8dSAdrian Chadd #undef TSF_TO_TU
565a35dae8dSAdrian Chadd }
566a35dae8dSAdrian Chadd 
567a35dae8dSAdrian Chadd /*
568a35dae8dSAdrian Chadd  * Transmit a beacon frame at SWBA.  Dynamic updates
569a35dae8dSAdrian Chadd  * to the frame contents are done as needed.
570a35dae8dSAdrian Chadd  */
571a35dae8dSAdrian Chadd void
572a35dae8dSAdrian Chadd ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap)
573a35dae8dSAdrian Chadd {
574a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
575a35dae8dSAdrian Chadd 	struct ath_buf *bf;
576a35dae8dSAdrian Chadd 	int otherant;
577a35dae8dSAdrian Chadd 
578a35dae8dSAdrian Chadd 	/*
579a35dae8dSAdrian Chadd 	 * Check if the previous beacon has gone out.  If
580a35dae8dSAdrian Chadd 	 * not don't try to post another, skip this period
581a35dae8dSAdrian Chadd 	 * and wait for the next.  Missed beacons indicate
582a35dae8dSAdrian Chadd 	 * a problem and should not occur.  If we miss too
583a35dae8dSAdrian Chadd 	 * many consecutive beacons reset the device.
584a35dae8dSAdrian Chadd 	 */
585a35dae8dSAdrian Chadd 	if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
586a35dae8dSAdrian Chadd 		sc->sc_bmisscount++;
587a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
588a35dae8dSAdrian Chadd 			"%s: missed %u consecutive beacons\n",
589a35dae8dSAdrian Chadd 			__func__, sc->sc_bmisscount);
590a35dae8dSAdrian Chadd 		if (sc->sc_bmisscount >= ath_bstuck_threshold)
591a35dae8dSAdrian Chadd 			taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
592a35dae8dSAdrian Chadd 		return;
593a35dae8dSAdrian Chadd 	}
594a35dae8dSAdrian Chadd 	if (sc->sc_bmisscount != 0) {
595a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
596a35dae8dSAdrian Chadd 			"%s: resume beacon xmit after %u misses\n",
597a35dae8dSAdrian Chadd 			__func__, sc->sc_bmisscount);
598a35dae8dSAdrian Chadd 		sc->sc_bmisscount = 0;
599a35dae8dSAdrian Chadd 	}
600a35dae8dSAdrian Chadd 
601a35dae8dSAdrian Chadd 	/*
602a35dae8dSAdrian Chadd 	 * Check recent per-antenna transmit statistics and flip
603a35dae8dSAdrian Chadd 	 * the default antenna if noticeably more frames went out
604a35dae8dSAdrian Chadd 	 * on the non-default antenna.
605a35dae8dSAdrian Chadd 	 * XXX assumes 2 anntenae
606a35dae8dSAdrian Chadd 	 */
607a35dae8dSAdrian Chadd 	if (!sc->sc_diversity) {
608a35dae8dSAdrian Chadd 		otherant = sc->sc_defant & 1 ? 2 : 1;
609a35dae8dSAdrian Chadd 		if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
610a35dae8dSAdrian Chadd 			ath_setdefantenna(sc, otherant);
611a35dae8dSAdrian Chadd 		sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
612a35dae8dSAdrian Chadd 	}
613a35dae8dSAdrian Chadd 
614a35dae8dSAdrian Chadd 	bf = ath_beacon_generate(sc, vap);
615*b837332dSAdrian Chadd 	/* XXX We don't do cabq traffic, but just for completeness .. */
616*b837332dSAdrian Chadd 	ATH_TXQ_LOCK(sc->sc_cabq);
617*b837332dSAdrian Chadd 	ath_beacon_cabq_start(sc);
618*b837332dSAdrian Chadd 	ATH_TXQ_UNLOCK(sc->sc_cabq);
619*b837332dSAdrian Chadd 
620a35dae8dSAdrian Chadd 	if (bf != NULL) {
621a35dae8dSAdrian Chadd 		/*
622a35dae8dSAdrian Chadd 		 * Stop any current dma and put the new frame on the queue.
623a35dae8dSAdrian Chadd 		 * This should never fail since we check above that no frames
624a35dae8dSAdrian Chadd 		 * are still pending on the queue.
625a35dae8dSAdrian Chadd 		 */
626*b837332dSAdrian Chadd 		if ((! sc->sc_isedma) &&
627*b837332dSAdrian Chadd 		    (! ath_hal_stoptxdma(ah, sc->sc_bhalq))) {
628a35dae8dSAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_ANY,
629a35dae8dSAdrian Chadd 				"%s: beacon queue %u did not stop?\n",
630a35dae8dSAdrian Chadd 				__func__, sc->sc_bhalq);
631a35dae8dSAdrian Chadd 			/* NB: the HAL still stops DMA, so proceed */
632a35dae8dSAdrian Chadd 		}
633a35dae8dSAdrian Chadd 		ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
634a35dae8dSAdrian Chadd 		ath_hal_txstart(ah, sc->sc_bhalq);
635a35dae8dSAdrian Chadd 
636a35dae8dSAdrian Chadd 		sc->sc_stats.ast_be_xmit++;		/* XXX per-vap? */
637a35dae8dSAdrian Chadd 
638a35dae8dSAdrian Chadd 		/*
639a35dae8dSAdrian Chadd 		 * Record local TSF for our last send for use
640a35dae8dSAdrian Chadd 		 * in arbitrating slot collisions.
641a35dae8dSAdrian Chadd 		 */
642a35dae8dSAdrian Chadd 		/* XXX should take a locked ref to iv_bss */
643a35dae8dSAdrian Chadd 		vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);
644a35dae8dSAdrian Chadd 	}
645a35dae8dSAdrian Chadd }
646a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */
647