xref: /freebsd/sys/dev/ath/if_ath_tdma.c (revision a35dae8d873458c6a77828c51fc80e33037aeb10)
1*a35dae8dSAdrian Chadd /*-
2*a35dae8dSAdrian Chadd  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3*a35dae8dSAdrian Chadd  * All rights reserved.
4*a35dae8dSAdrian Chadd  *
5*a35dae8dSAdrian Chadd  * Redistribution and use in source and binary forms, with or without
6*a35dae8dSAdrian Chadd  * modification, are permitted provided that the following conditions
7*a35dae8dSAdrian Chadd  * are met:
8*a35dae8dSAdrian Chadd  * 1. Redistributions of source code must retain the above copyright
9*a35dae8dSAdrian Chadd  *    notice, this list of conditions and the following disclaimer,
10*a35dae8dSAdrian Chadd  *    without modification.
11*a35dae8dSAdrian Chadd  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12*a35dae8dSAdrian Chadd  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13*a35dae8dSAdrian Chadd  *    redistribution must be conditioned upon including a substantially
14*a35dae8dSAdrian Chadd  *    similar Disclaimer requirement for further binary redistribution.
15*a35dae8dSAdrian Chadd  *
16*a35dae8dSAdrian Chadd  * NO WARRANTY
17*a35dae8dSAdrian Chadd  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18*a35dae8dSAdrian Chadd  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19*a35dae8dSAdrian Chadd  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20*a35dae8dSAdrian Chadd  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21*a35dae8dSAdrian Chadd  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22*a35dae8dSAdrian Chadd  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23*a35dae8dSAdrian Chadd  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24*a35dae8dSAdrian Chadd  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25*a35dae8dSAdrian Chadd  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26*a35dae8dSAdrian Chadd  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27*a35dae8dSAdrian Chadd  * THE POSSIBILITY OF SUCH DAMAGES.
28*a35dae8dSAdrian Chadd  */
29*a35dae8dSAdrian Chadd 
30*a35dae8dSAdrian Chadd #include <sys/cdefs.h>
31*a35dae8dSAdrian Chadd __FBSDID("$FreeBSD$");
32*a35dae8dSAdrian Chadd 
33*a35dae8dSAdrian Chadd /*
34*a35dae8dSAdrian Chadd  * Driver for the Atheros Wireless LAN controller.
35*a35dae8dSAdrian Chadd  *
36*a35dae8dSAdrian Chadd  * This software is derived from work of Atsushi Onoe; his contribution
37*a35dae8dSAdrian Chadd  * is greatly appreciated.
38*a35dae8dSAdrian Chadd  */
39*a35dae8dSAdrian Chadd 
40*a35dae8dSAdrian Chadd #include "opt_inet.h"
41*a35dae8dSAdrian Chadd #include "opt_ath.h"
42*a35dae8dSAdrian Chadd /*
43*a35dae8dSAdrian Chadd  * This is needed for register operations which are performed
44*a35dae8dSAdrian Chadd  * by the driver - eg, calls to ath_hal_gettsf32().
45*a35dae8dSAdrian Chadd  *
46*a35dae8dSAdrian Chadd  * It's also required for any AH_DEBUG checks in here, eg the
47*a35dae8dSAdrian Chadd  * module dependencies.
48*a35dae8dSAdrian Chadd  */
49*a35dae8dSAdrian Chadd #include "opt_ah.h"
50*a35dae8dSAdrian Chadd #include "opt_wlan.h"
51*a35dae8dSAdrian Chadd 
52*a35dae8dSAdrian Chadd #include <sys/param.h>
53*a35dae8dSAdrian Chadd #include <sys/systm.h>
54*a35dae8dSAdrian Chadd #include <sys/sysctl.h>
55*a35dae8dSAdrian Chadd #include <sys/mbuf.h>
56*a35dae8dSAdrian Chadd #include <sys/malloc.h>
57*a35dae8dSAdrian Chadd #include <sys/lock.h>
58*a35dae8dSAdrian Chadd #include <sys/mutex.h>
59*a35dae8dSAdrian Chadd #include <sys/kernel.h>
60*a35dae8dSAdrian Chadd #include <sys/socket.h>
61*a35dae8dSAdrian Chadd #include <sys/sockio.h>
62*a35dae8dSAdrian Chadd #include <sys/errno.h>
63*a35dae8dSAdrian Chadd #include <sys/callout.h>
64*a35dae8dSAdrian Chadd #include <sys/bus.h>
65*a35dae8dSAdrian Chadd #include <sys/endian.h>
66*a35dae8dSAdrian Chadd #include <sys/kthread.h>
67*a35dae8dSAdrian Chadd #include <sys/taskqueue.h>
68*a35dae8dSAdrian Chadd #include <sys/priv.h>
69*a35dae8dSAdrian Chadd #include <sys/module.h>
70*a35dae8dSAdrian Chadd #include <sys/ktr.h>
71*a35dae8dSAdrian Chadd #include <sys/smp.h>	/* for mp_ncpus */
72*a35dae8dSAdrian Chadd 
73*a35dae8dSAdrian Chadd #include <machine/bus.h>
74*a35dae8dSAdrian Chadd 
75*a35dae8dSAdrian Chadd #include <net/if.h>
76*a35dae8dSAdrian Chadd #include <net/if_dl.h>
77*a35dae8dSAdrian Chadd #include <net/if_media.h>
78*a35dae8dSAdrian Chadd #include <net/if_types.h>
79*a35dae8dSAdrian Chadd #include <net/if_arp.h>
80*a35dae8dSAdrian Chadd #include <net/ethernet.h>
81*a35dae8dSAdrian Chadd #include <net/if_llc.h>
82*a35dae8dSAdrian Chadd 
83*a35dae8dSAdrian Chadd #include <net80211/ieee80211_var.h>
84*a35dae8dSAdrian Chadd #include <net80211/ieee80211_regdomain.h>
85*a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_SUPERG
86*a35dae8dSAdrian Chadd #include <net80211/ieee80211_superg.h>
87*a35dae8dSAdrian Chadd #endif
88*a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
89*a35dae8dSAdrian Chadd #include <net80211/ieee80211_tdma.h>
90*a35dae8dSAdrian Chadd #endif
91*a35dae8dSAdrian Chadd 
92*a35dae8dSAdrian Chadd #include <net/bpf.h>
93*a35dae8dSAdrian Chadd 
94*a35dae8dSAdrian Chadd #ifdef INET
95*a35dae8dSAdrian Chadd #include <netinet/in.h>
96*a35dae8dSAdrian Chadd #include <netinet/if_ether.h>
97*a35dae8dSAdrian Chadd #endif
98*a35dae8dSAdrian Chadd 
99*a35dae8dSAdrian Chadd #include <dev/ath/if_athvar.h>
100*a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_devid.h>		/* XXX for softled */
101*a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_diagcodes.h>
102*a35dae8dSAdrian Chadd 
103*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_debug.h>
104*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_misc.h>
105*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tsf.h>
106*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tx.h>
107*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_sysctl.h>
108*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_led.h>
109*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_keycache.h>
110*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_rx.h>
111*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_beacon.h>
112*a35dae8dSAdrian Chadd #include <dev/ath/if_athdfs.h>
113*a35dae8dSAdrian Chadd 
114*a35dae8dSAdrian Chadd #ifdef ATH_TX99_DIAG
115*a35dae8dSAdrian Chadd #include <dev/ath/ath_tx99/ath_tx99.h>
116*a35dae8dSAdrian Chadd #endif
117*a35dae8dSAdrian Chadd 
118*a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
119*a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tdma.h>
120*a35dae8dSAdrian Chadd 
121*a35dae8dSAdrian Chadd static void	ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt,
122*a35dae8dSAdrian Chadd 		    u_int32_t bintval);
123*a35dae8dSAdrian Chadd static void	ath_tdma_bintvalsetup(struct ath_softc *sc,
124*a35dae8dSAdrian Chadd 		    const struct ieee80211_tdma_state *tdma);
125*a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */
126*a35dae8dSAdrian Chadd 
127*a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA
128*a35dae8dSAdrian Chadd static void
129*a35dae8dSAdrian Chadd ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval)
130*a35dae8dSAdrian Chadd {
131*a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
132*a35dae8dSAdrian Chadd 	HAL_BEACON_TIMERS bt;
133*a35dae8dSAdrian Chadd 
134*a35dae8dSAdrian Chadd 	bt.bt_intval = bintval | HAL_BEACON_ENA;
135*a35dae8dSAdrian Chadd 	bt.bt_nexttbtt = nexttbtt;
136*a35dae8dSAdrian Chadd 	bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep;
137*a35dae8dSAdrian Chadd 	bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep;
138*a35dae8dSAdrian Chadd 	bt.bt_nextatim = nexttbtt+1;
139*a35dae8dSAdrian Chadd 	/* Enables TBTT, DBA, SWBA timers by default */
140*a35dae8dSAdrian Chadd 	bt.bt_flags = 0;
141*a35dae8dSAdrian Chadd 	ath_hal_beaconsettimers(ah, &bt);
142*a35dae8dSAdrian Chadd }
143*a35dae8dSAdrian Chadd 
144*a35dae8dSAdrian Chadd /*
145*a35dae8dSAdrian Chadd  * Calculate the beacon interval.  This is periodic in the
146*a35dae8dSAdrian Chadd  * superframe for the bss.  We assume each station is configured
147*a35dae8dSAdrian Chadd  * identically wrt transmit rate so the guard time we calculate
148*a35dae8dSAdrian Chadd  * above will be the same on all stations.  Note we need to
149*a35dae8dSAdrian Chadd  * factor in the xmit time because the hardware will schedule
150*a35dae8dSAdrian Chadd  * a frame for transmit if the start of the frame is within
151*a35dae8dSAdrian Chadd  * the burst time.  When we get hardware that properly kills
152*a35dae8dSAdrian Chadd  * frames in the PCU we can reduce/eliminate the guard time.
153*a35dae8dSAdrian Chadd  *
154*a35dae8dSAdrian Chadd  * Roundup to 1024 is so we have 1 TU buffer in the guard time
155*a35dae8dSAdrian Chadd  * to deal with the granularity of the nexttbtt timer.  11n MAC's
156*a35dae8dSAdrian Chadd  * with 1us timer granularity should allow us to reduce/eliminate
157*a35dae8dSAdrian Chadd  * this.
158*a35dae8dSAdrian Chadd  */
159*a35dae8dSAdrian Chadd static void
160*a35dae8dSAdrian Chadd ath_tdma_bintvalsetup(struct ath_softc *sc,
161*a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_state *tdma)
162*a35dae8dSAdrian Chadd {
163*a35dae8dSAdrian Chadd 	/* copy from vap state (XXX check all vaps have same value?) */
164*a35dae8dSAdrian Chadd 	sc->sc_tdmaslotlen = tdma->tdma_slotlen;
165*a35dae8dSAdrian Chadd 
166*a35dae8dSAdrian Chadd 	sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) *
167*a35dae8dSAdrian Chadd 		tdma->tdma_slotcnt, 1024);
168*a35dae8dSAdrian Chadd 	sc->sc_tdmabintval >>= 10;		/* TSF -> TU */
169*a35dae8dSAdrian Chadd 	if (sc->sc_tdmabintval & 1)
170*a35dae8dSAdrian Chadd 		sc->sc_tdmabintval++;
171*a35dae8dSAdrian Chadd 
172*a35dae8dSAdrian Chadd 	if (tdma->tdma_slot == 0) {
173*a35dae8dSAdrian Chadd 		/*
174*a35dae8dSAdrian Chadd 		 * Only slot 0 beacons; other slots respond.
175*a35dae8dSAdrian Chadd 		 */
176*a35dae8dSAdrian Chadd 		sc->sc_imask |= HAL_INT_SWBA;
177*a35dae8dSAdrian Chadd 		sc->sc_tdmaswba = 0;		/* beacon immediately */
178*a35dae8dSAdrian Chadd 	} else {
179*a35dae8dSAdrian Chadd 		/* XXX all vaps must be slot 0 or slot !0 */
180*a35dae8dSAdrian Chadd 		sc->sc_imask &= ~HAL_INT_SWBA;
181*a35dae8dSAdrian Chadd 	}
182*a35dae8dSAdrian Chadd }
183*a35dae8dSAdrian Chadd 
184*a35dae8dSAdrian Chadd /*
185*a35dae8dSAdrian Chadd  * Max 802.11 overhead.  This assumes no 4-address frames and
186*a35dae8dSAdrian Chadd  * the encapsulation done by ieee80211_encap (llc).  We also
187*a35dae8dSAdrian Chadd  * include potential crypto overhead.
188*a35dae8dSAdrian Chadd  */
189*a35dae8dSAdrian Chadd #define	IEEE80211_MAXOVERHEAD \
190*a35dae8dSAdrian Chadd 	(sizeof(struct ieee80211_qosframe) \
191*a35dae8dSAdrian Chadd 	 + sizeof(struct llc) \
192*a35dae8dSAdrian Chadd 	 + IEEE80211_ADDR_LEN \
193*a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_IVLEN \
194*a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_KIDLEN \
195*a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_CRCLEN \
196*a35dae8dSAdrian Chadd 	 + IEEE80211_WEP_MICLEN \
197*a35dae8dSAdrian Chadd 	 + IEEE80211_CRC_LEN)
198*a35dae8dSAdrian Chadd 
199*a35dae8dSAdrian Chadd /*
200*a35dae8dSAdrian Chadd  * Setup initially for tdma operation.  Start the beacon
201*a35dae8dSAdrian Chadd  * timers and enable SWBA if we are slot 0.  Otherwise
202*a35dae8dSAdrian Chadd  * we wait for slot 0 to arrive so we can sync up before
203*a35dae8dSAdrian Chadd  * starting to transmit.
204*a35dae8dSAdrian Chadd  */
205*a35dae8dSAdrian Chadd void
206*a35dae8dSAdrian Chadd ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap)
207*a35dae8dSAdrian Chadd {
208*a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
209*a35dae8dSAdrian Chadd 	struct ifnet *ifp = sc->sc_ifp;
210*a35dae8dSAdrian Chadd 	struct ieee80211com *ic = ifp->if_l2com;
211*a35dae8dSAdrian Chadd 	const struct ieee80211_txparam *tp;
212*a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_state *tdma = NULL;
213*a35dae8dSAdrian Chadd 	int rix;
214*a35dae8dSAdrian Chadd 
215*a35dae8dSAdrian Chadd 	if (vap == NULL) {
216*a35dae8dSAdrian Chadd 		vap = TAILQ_FIRST(&ic->ic_vaps);   /* XXX */
217*a35dae8dSAdrian Chadd 		if (vap == NULL) {
218*a35dae8dSAdrian Chadd 			if_printf(ifp, "%s: no vaps?\n", __func__);
219*a35dae8dSAdrian Chadd 			return;
220*a35dae8dSAdrian Chadd 		}
221*a35dae8dSAdrian Chadd 	}
222*a35dae8dSAdrian Chadd 	/* XXX should take a locked ref to iv_bss */
223*a35dae8dSAdrian Chadd 	tp = vap->iv_bss->ni_txparms;
224*a35dae8dSAdrian Chadd 	/*
225*a35dae8dSAdrian Chadd 	 * Calculate the guard time for each slot.  This is the
226*a35dae8dSAdrian Chadd 	 * time to send a maximal-size frame according to the
227*a35dae8dSAdrian Chadd 	 * fixed/lowest transmit rate.  Note that the interface
228*a35dae8dSAdrian Chadd 	 * mtu does not include the 802.11 overhead so we must
229*a35dae8dSAdrian Chadd 	 * tack that on (ath_hal_computetxtime includes the
230*a35dae8dSAdrian Chadd 	 * preamble and plcp in it's calculation).
231*a35dae8dSAdrian Chadd 	 */
232*a35dae8dSAdrian Chadd 	tdma = vap->iv_tdma;
233*a35dae8dSAdrian Chadd 	if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
234*a35dae8dSAdrian Chadd 		rix = ath_tx_findrix(sc, tp->ucastrate);
235*a35dae8dSAdrian Chadd 	else
236*a35dae8dSAdrian Chadd 		rix = ath_tx_findrix(sc, tp->mcastrate);
237*a35dae8dSAdrian Chadd 	/* XXX short preamble assumed */
238*a35dae8dSAdrian Chadd 	sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,
239*a35dae8dSAdrian Chadd 		ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE);
240*a35dae8dSAdrian Chadd 
241*a35dae8dSAdrian Chadd 	ath_hal_intrset(ah, 0);
242*a35dae8dSAdrian Chadd 
243*a35dae8dSAdrian Chadd 	ath_beaconq_config(sc);			/* setup h/w beacon q */
244*a35dae8dSAdrian Chadd 	if (sc->sc_setcca)
245*a35dae8dSAdrian Chadd 		ath_hal_setcca(ah, AH_FALSE);	/* disable CCA */
246*a35dae8dSAdrian Chadd 	ath_tdma_bintvalsetup(sc, tdma);	/* calculate beacon interval */
247*a35dae8dSAdrian Chadd 	ath_tdma_settimers(sc, sc->sc_tdmabintval,
248*a35dae8dSAdrian Chadd 		sc->sc_tdmabintval | HAL_BEACON_RESET_TSF);
249*a35dae8dSAdrian Chadd 	sc->sc_syncbeacon = 0;
250*a35dae8dSAdrian Chadd 
251*a35dae8dSAdrian Chadd 	sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER;
252*a35dae8dSAdrian Chadd 	sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER;
253*a35dae8dSAdrian Chadd 
254*a35dae8dSAdrian Chadd 	ath_hal_intrset(ah, sc->sc_imask);
255*a35dae8dSAdrian Chadd 
256*a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u "
257*a35dae8dSAdrian Chadd 	    "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__,
258*a35dae8dSAdrian Chadd 	    tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt,
259*a35dae8dSAdrian Chadd 	    tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval,
260*a35dae8dSAdrian Chadd 	    sc->sc_tdmadbaprep);
261*a35dae8dSAdrian Chadd }
262*a35dae8dSAdrian Chadd 
263*a35dae8dSAdrian Chadd /*
264*a35dae8dSAdrian Chadd  * Update tdma operation.  Called from the 802.11 layer
265*a35dae8dSAdrian Chadd  * when a beacon is received from the TDMA station operating
266*a35dae8dSAdrian Chadd  * in the slot immediately preceding us in the bss.  Use
267*a35dae8dSAdrian Chadd  * the rx timestamp for the beacon frame to update our
268*a35dae8dSAdrian Chadd  * beacon timers so we follow their schedule.  Note that
269*a35dae8dSAdrian Chadd  * by using the rx timestamp we implicitly include the
270*a35dae8dSAdrian Chadd  * propagation delay in our schedule.
271*a35dae8dSAdrian Chadd  */
272*a35dae8dSAdrian Chadd void
273*a35dae8dSAdrian Chadd ath_tdma_update(struct ieee80211_node *ni,
274*a35dae8dSAdrian Chadd 	const struct ieee80211_tdma_param *tdma, int changed)
275*a35dae8dSAdrian Chadd {
276*a35dae8dSAdrian Chadd #define	TSF_TO_TU(_h,_l) \
277*a35dae8dSAdrian Chadd 	((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
278*a35dae8dSAdrian Chadd #define	TU_TO_TSF(_tu)	(((u_int64_t)(_tu)) << 10)
279*a35dae8dSAdrian Chadd 	struct ieee80211vap *vap = ni->ni_vap;
280*a35dae8dSAdrian Chadd 	struct ieee80211com *ic = ni->ni_ic;
281*a35dae8dSAdrian Chadd 	struct ath_softc *sc = ic->ic_ifp->if_softc;
282*a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
283*a35dae8dSAdrian Chadd 	const HAL_RATE_TABLE *rt = sc->sc_currates;
284*a35dae8dSAdrian Chadd 	u_int64_t tsf, rstamp, nextslot, nexttbtt;
285*a35dae8dSAdrian Chadd 	u_int32_t txtime, nextslottu;
286*a35dae8dSAdrian Chadd 	int32_t tudelta, tsfdelta;
287*a35dae8dSAdrian Chadd 	const struct ath_rx_status *rs;
288*a35dae8dSAdrian Chadd 	int rix;
289*a35dae8dSAdrian Chadd 
290*a35dae8dSAdrian Chadd 	sc->sc_stats.ast_tdma_update++;
291*a35dae8dSAdrian Chadd 
292*a35dae8dSAdrian Chadd 	/*
293*a35dae8dSAdrian Chadd 	 * Check for and adopt configuration changes.
294*a35dae8dSAdrian Chadd 	 */
295*a35dae8dSAdrian Chadd 	if (changed != 0) {
296*a35dae8dSAdrian Chadd 		const struct ieee80211_tdma_state *ts = vap->iv_tdma;
297*a35dae8dSAdrian Chadd 
298*a35dae8dSAdrian Chadd 		ath_tdma_bintvalsetup(sc, ts);
299*a35dae8dSAdrian Chadd 		if (changed & TDMA_UPDATE_SLOTLEN)
300*a35dae8dSAdrian Chadd 			ath_wme_update(ic);
301*a35dae8dSAdrian Chadd 
302*a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_TDMA,
303*a35dae8dSAdrian Chadd 		    "%s: adopt slot %u slotcnt %u slotlen %u us "
304*a35dae8dSAdrian Chadd 		    "bintval %u TU\n", __func__,
305*a35dae8dSAdrian Chadd 		    ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen,
306*a35dae8dSAdrian Chadd 		    sc->sc_tdmabintval);
307*a35dae8dSAdrian Chadd 
308*a35dae8dSAdrian Chadd 		/* XXX right? */
309*a35dae8dSAdrian Chadd 		ath_hal_intrset(ah, sc->sc_imask);
310*a35dae8dSAdrian Chadd 		/* NB: beacon timers programmed below */
311*a35dae8dSAdrian Chadd 	}
312*a35dae8dSAdrian Chadd 
313*a35dae8dSAdrian Chadd 	/* extend rx timestamp to 64 bits */
314*a35dae8dSAdrian Chadd 	rs = sc->sc_lastrs;
315*a35dae8dSAdrian Chadd 	tsf = ath_hal_gettsf64(ah);
316*a35dae8dSAdrian Chadd 	rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
317*a35dae8dSAdrian Chadd 	/*
318*a35dae8dSAdrian Chadd 	 * The rx timestamp is set by the hardware on completing
319*a35dae8dSAdrian Chadd 	 * reception (at the point where the rx descriptor is DMA'd
320*a35dae8dSAdrian Chadd 	 * to the host).  To find the start of our next slot we
321*a35dae8dSAdrian Chadd 	 * must adjust this time by the time required to send
322*a35dae8dSAdrian Chadd 	 * the packet just received.
323*a35dae8dSAdrian Chadd 	 */
324*a35dae8dSAdrian Chadd 	rix = rt->rateCodeToIndex[rs->rs_rate];
325*a35dae8dSAdrian Chadd 	txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix,
326*a35dae8dSAdrian Chadd 	    rt->info[rix].shortPreamble);
327*a35dae8dSAdrian Chadd 	/* NB: << 9 is to cvt to TU and /2 */
328*a35dae8dSAdrian Chadd 	nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9);
329*a35dae8dSAdrian Chadd 	nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD;
330*a35dae8dSAdrian Chadd 
331*a35dae8dSAdrian Chadd 	/*
332*a35dae8dSAdrian Chadd 	 * Retrieve the hardware NextTBTT in usecs
333*a35dae8dSAdrian Chadd 	 * and calculate the difference between what the
334*a35dae8dSAdrian Chadd 	 * other station thinks and what we have programmed.  This
335*a35dae8dSAdrian Chadd 	 * lets us figure how to adjust our timers to match.  The
336*a35dae8dSAdrian Chadd 	 * adjustments are done by pulling the TSF forward and possibly
337*a35dae8dSAdrian Chadd 	 * rewriting the beacon timers.
338*a35dae8dSAdrian Chadd 	 */
339*a35dae8dSAdrian Chadd 	nexttbtt = ath_hal_getnexttbtt(ah);
340*a35dae8dSAdrian Chadd 	tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD + 1)) - nexttbtt);
341*a35dae8dSAdrian Chadd 
342*a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
343*a35dae8dSAdrian Chadd 	    "tsfdelta %d avg +%d/-%d\n", tsfdelta,
344*a35dae8dSAdrian Chadd 	    TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam));
345*a35dae8dSAdrian Chadd 
346*a35dae8dSAdrian Chadd 	if (tsfdelta < 0) {
347*a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
348*a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta);
349*a35dae8dSAdrian Chadd 		tsfdelta = -tsfdelta % 1024;
350*a35dae8dSAdrian Chadd 		nextslottu++;
351*a35dae8dSAdrian Chadd 	} else if (tsfdelta > 0) {
352*a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta);
353*a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
354*a35dae8dSAdrian Chadd 		tsfdelta = 1024 - (tsfdelta % 1024);
355*a35dae8dSAdrian Chadd 		nextslottu++;
356*a35dae8dSAdrian Chadd 	} else {
357*a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
358*a35dae8dSAdrian Chadd 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
359*a35dae8dSAdrian Chadd 	}
360*a35dae8dSAdrian Chadd 	tudelta = nextslottu - TSF_TO_TU(nexttbtt >> 32, nexttbtt);
361*a35dae8dSAdrian Chadd 
362*a35dae8dSAdrian Chadd 	/*
363*a35dae8dSAdrian Chadd 	 * Copy sender's timetstamp into tdma ie so they can
364*a35dae8dSAdrian Chadd 	 * calculate roundtrip time.  We submit a beacon frame
365*a35dae8dSAdrian Chadd 	 * below after any timer adjustment.  The frame goes out
366*a35dae8dSAdrian Chadd 	 * at the next TBTT so the sender can calculate the
367*a35dae8dSAdrian Chadd 	 * roundtrip by inspecting the tdma ie in our beacon frame.
368*a35dae8dSAdrian Chadd 	 *
369*a35dae8dSAdrian Chadd 	 * NB: This tstamp is subtlely preserved when
370*a35dae8dSAdrian Chadd 	 *     IEEE80211_BEACON_TDMA is marked (e.g. when the
371*a35dae8dSAdrian Chadd 	 *     slot position changes) because ieee80211_add_tdma
372*a35dae8dSAdrian Chadd 	 *     skips over the data.
373*a35dae8dSAdrian Chadd 	 */
374*a35dae8dSAdrian Chadd 	memcpy(ATH_VAP(vap)->av_boff.bo_tdma +
375*a35dae8dSAdrian Chadd 		__offsetof(struct ieee80211_tdma_param, tdma_tstamp),
376*a35dae8dSAdrian Chadd 		&ni->ni_tstamp.data, 8);
377*a35dae8dSAdrian Chadd #if 0
378*a35dae8dSAdrian Chadd 	DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
379*a35dae8dSAdrian Chadd 	    "tsf %llu nextslot %llu (%d, %d) nextslottu %u nexttbtt %llu (%d)\n",
380*a35dae8dSAdrian Chadd 	    (unsigned long long) tsf, (unsigned long long) nextslot,
381*a35dae8dSAdrian Chadd 	    (int)(nextslot - tsf), tsfdelta, nextslottu, nexttbtt, tudelta);
382*a35dae8dSAdrian Chadd #endif
383*a35dae8dSAdrian Chadd 	/*
384*a35dae8dSAdrian Chadd 	 * Adjust the beacon timers only when pulling them forward
385*a35dae8dSAdrian Chadd 	 * or when going back by less than the beacon interval.
386*a35dae8dSAdrian Chadd 	 * Negative jumps larger than the beacon interval seem to
387*a35dae8dSAdrian Chadd 	 * cause the timers to stop and generally cause instability.
388*a35dae8dSAdrian Chadd 	 * This basically filters out jumps due to missed beacons.
389*a35dae8dSAdrian Chadd 	 */
390*a35dae8dSAdrian Chadd 	if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) {
391*a35dae8dSAdrian Chadd 		ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval);
392*a35dae8dSAdrian Chadd 		sc->sc_stats.ast_tdma_timers++;
393*a35dae8dSAdrian Chadd 	}
394*a35dae8dSAdrian Chadd 	if (tsfdelta > 0) {
395*a35dae8dSAdrian Chadd 		ath_hal_adjusttsf(ah, tsfdelta);
396*a35dae8dSAdrian Chadd 		sc->sc_stats.ast_tdma_tsf++;
397*a35dae8dSAdrian Chadd 	}
398*a35dae8dSAdrian Chadd 	ath_tdma_beacon_send(sc, vap);		/* prepare response */
399*a35dae8dSAdrian Chadd #undef TU_TO_TSF
400*a35dae8dSAdrian Chadd #undef TSF_TO_TU
401*a35dae8dSAdrian Chadd }
402*a35dae8dSAdrian Chadd 
403*a35dae8dSAdrian Chadd /*
404*a35dae8dSAdrian Chadd  * Transmit a beacon frame at SWBA.  Dynamic updates
405*a35dae8dSAdrian Chadd  * to the frame contents are done as needed.
406*a35dae8dSAdrian Chadd  */
407*a35dae8dSAdrian Chadd void
408*a35dae8dSAdrian Chadd ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap)
409*a35dae8dSAdrian Chadd {
410*a35dae8dSAdrian Chadd 	struct ath_hal *ah = sc->sc_ah;
411*a35dae8dSAdrian Chadd 	struct ath_buf *bf;
412*a35dae8dSAdrian Chadd 	int otherant;
413*a35dae8dSAdrian Chadd 
414*a35dae8dSAdrian Chadd 	/*
415*a35dae8dSAdrian Chadd 	 * Check if the previous beacon has gone out.  If
416*a35dae8dSAdrian Chadd 	 * not don't try to post another, skip this period
417*a35dae8dSAdrian Chadd 	 * and wait for the next.  Missed beacons indicate
418*a35dae8dSAdrian Chadd 	 * a problem and should not occur.  If we miss too
419*a35dae8dSAdrian Chadd 	 * many consecutive beacons reset the device.
420*a35dae8dSAdrian Chadd 	 */
421*a35dae8dSAdrian Chadd 	if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
422*a35dae8dSAdrian Chadd 		sc->sc_bmisscount++;
423*a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
424*a35dae8dSAdrian Chadd 			"%s: missed %u consecutive beacons\n",
425*a35dae8dSAdrian Chadd 			__func__, sc->sc_bmisscount);
426*a35dae8dSAdrian Chadd 		if (sc->sc_bmisscount >= ath_bstuck_threshold)
427*a35dae8dSAdrian Chadd 			taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
428*a35dae8dSAdrian Chadd 		return;
429*a35dae8dSAdrian Chadd 	}
430*a35dae8dSAdrian Chadd 	if (sc->sc_bmisscount != 0) {
431*a35dae8dSAdrian Chadd 		DPRINTF(sc, ATH_DEBUG_BEACON,
432*a35dae8dSAdrian Chadd 			"%s: resume beacon xmit after %u misses\n",
433*a35dae8dSAdrian Chadd 			__func__, sc->sc_bmisscount);
434*a35dae8dSAdrian Chadd 		sc->sc_bmisscount = 0;
435*a35dae8dSAdrian Chadd 	}
436*a35dae8dSAdrian Chadd 
437*a35dae8dSAdrian Chadd 	/*
438*a35dae8dSAdrian Chadd 	 * Check recent per-antenna transmit statistics and flip
439*a35dae8dSAdrian Chadd 	 * the default antenna if noticeably more frames went out
440*a35dae8dSAdrian Chadd 	 * on the non-default antenna.
441*a35dae8dSAdrian Chadd 	 * XXX assumes 2 anntenae
442*a35dae8dSAdrian Chadd 	 */
443*a35dae8dSAdrian Chadd 	if (!sc->sc_diversity) {
444*a35dae8dSAdrian Chadd 		otherant = sc->sc_defant & 1 ? 2 : 1;
445*a35dae8dSAdrian Chadd 		if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
446*a35dae8dSAdrian Chadd 			ath_setdefantenna(sc, otherant);
447*a35dae8dSAdrian Chadd 		sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
448*a35dae8dSAdrian Chadd 	}
449*a35dae8dSAdrian Chadd 
450*a35dae8dSAdrian Chadd 	bf = ath_beacon_generate(sc, vap);
451*a35dae8dSAdrian Chadd 	if (bf != NULL) {
452*a35dae8dSAdrian Chadd 		/*
453*a35dae8dSAdrian Chadd 		 * Stop any current dma and put the new frame on the queue.
454*a35dae8dSAdrian Chadd 		 * This should never fail since we check above that no frames
455*a35dae8dSAdrian Chadd 		 * are still pending on the queue.
456*a35dae8dSAdrian Chadd 		 */
457*a35dae8dSAdrian Chadd 		if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
458*a35dae8dSAdrian Chadd 			DPRINTF(sc, ATH_DEBUG_ANY,
459*a35dae8dSAdrian Chadd 				"%s: beacon queue %u did not stop?\n",
460*a35dae8dSAdrian Chadd 				__func__, sc->sc_bhalq);
461*a35dae8dSAdrian Chadd 			/* NB: the HAL still stops DMA, so proceed */
462*a35dae8dSAdrian Chadd 		}
463*a35dae8dSAdrian Chadd 		ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
464*a35dae8dSAdrian Chadd 		ath_hal_txstart(ah, sc->sc_bhalq);
465*a35dae8dSAdrian Chadd 
466*a35dae8dSAdrian Chadd 		sc->sc_stats.ast_be_xmit++;		/* XXX per-vap? */
467*a35dae8dSAdrian Chadd 
468*a35dae8dSAdrian Chadd 		/*
469*a35dae8dSAdrian Chadd 		 * Record local TSF for our last send for use
470*a35dae8dSAdrian Chadd 		 * in arbitrating slot collisions.
471*a35dae8dSAdrian Chadd 		 */
472*a35dae8dSAdrian Chadd 		/* XXX should take a locked ref to iv_bss */
473*a35dae8dSAdrian Chadd 		vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);
474*a35dae8dSAdrian Chadd 	}
475*a35dae8dSAdrian Chadd }
476*a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */
477