1a35dae8dSAdrian Chadd /*- 2a35dae8dSAdrian Chadd * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3a35dae8dSAdrian Chadd * All rights reserved. 4a35dae8dSAdrian Chadd * 5a35dae8dSAdrian Chadd * Redistribution and use in source and binary forms, with or without 6a35dae8dSAdrian Chadd * modification, are permitted provided that the following conditions 7a35dae8dSAdrian Chadd * are met: 8a35dae8dSAdrian Chadd * 1. Redistributions of source code must retain the above copyright 9a35dae8dSAdrian Chadd * notice, this list of conditions and the following disclaimer, 10a35dae8dSAdrian Chadd * without modification. 11a35dae8dSAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12a35dae8dSAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13a35dae8dSAdrian Chadd * redistribution must be conditioned upon including a substantially 14a35dae8dSAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 15a35dae8dSAdrian Chadd * 16a35dae8dSAdrian Chadd * NO WARRANTY 17a35dae8dSAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18a35dae8dSAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19a35dae8dSAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20a35dae8dSAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21a35dae8dSAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22a35dae8dSAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23a35dae8dSAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24a35dae8dSAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25a35dae8dSAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26a35dae8dSAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27a35dae8dSAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 28a35dae8dSAdrian Chadd */ 29a35dae8dSAdrian Chadd 30a35dae8dSAdrian Chadd #include <sys/cdefs.h> 31a35dae8dSAdrian Chadd __FBSDID("$FreeBSD$"); 32a35dae8dSAdrian Chadd 33a35dae8dSAdrian Chadd /* 34a35dae8dSAdrian Chadd * Driver for the Atheros Wireless LAN controller. 35a35dae8dSAdrian Chadd * 36a35dae8dSAdrian Chadd * This software is derived from work of Atsushi Onoe; his contribution 37a35dae8dSAdrian Chadd * is greatly appreciated. 38a35dae8dSAdrian Chadd */ 39a35dae8dSAdrian Chadd 40a35dae8dSAdrian Chadd #include "opt_inet.h" 41a35dae8dSAdrian Chadd #include "opt_ath.h" 42a35dae8dSAdrian Chadd /* 43a35dae8dSAdrian Chadd * This is needed for register operations which are performed 44a35dae8dSAdrian Chadd * by the driver - eg, calls to ath_hal_gettsf32(). 45a35dae8dSAdrian Chadd * 46a35dae8dSAdrian Chadd * It's also required for any AH_DEBUG checks in here, eg the 47a35dae8dSAdrian Chadd * module dependencies. 48a35dae8dSAdrian Chadd */ 49a35dae8dSAdrian Chadd #include "opt_ah.h" 50a35dae8dSAdrian Chadd #include "opt_wlan.h" 51a35dae8dSAdrian Chadd 52a35dae8dSAdrian Chadd #include <sys/param.h> 53a35dae8dSAdrian Chadd #include <sys/systm.h> 54a35dae8dSAdrian Chadd #include <sys/sysctl.h> 55a35dae8dSAdrian Chadd #include <sys/mbuf.h> 56a35dae8dSAdrian Chadd #include <sys/malloc.h> 57a35dae8dSAdrian Chadd #include <sys/lock.h> 58a35dae8dSAdrian Chadd #include <sys/mutex.h> 59a35dae8dSAdrian Chadd #include <sys/kernel.h> 60a35dae8dSAdrian Chadd #include <sys/socket.h> 61a35dae8dSAdrian Chadd #include <sys/sockio.h> 62a35dae8dSAdrian Chadd #include <sys/errno.h> 63a35dae8dSAdrian Chadd #include <sys/callout.h> 64a35dae8dSAdrian Chadd #include <sys/bus.h> 65a35dae8dSAdrian Chadd #include <sys/endian.h> 66a35dae8dSAdrian Chadd #include <sys/kthread.h> 67a35dae8dSAdrian Chadd #include <sys/taskqueue.h> 68a35dae8dSAdrian Chadd #include <sys/priv.h> 69a35dae8dSAdrian Chadd #include <sys/module.h> 70a35dae8dSAdrian Chadd #include <sys/ktr.h> 71a35dae8dSAdrian Chadd #include <sys/smp.h> /* for mp_ncpus */ 72a35dae8dSAdrian Chadd 73a35dae8dSAdrian Chadd #include <machine/bus.h> 74a35dae8dSAdrian Chadd 75a35dae8dSAdrian Chadd #include <net/if.h> 76a35dae8dSAdrian Chadd #include <net/if_dl.h> 77a35dae8dSAdrian Chadd #include <net/if_media.h> 78a35dae8dSAdrian Chadd #include <net/if_types.h> 79a35dae8dSAdrian Chadd #include <net/if_arp.h> 80a35dae8dSAdrian Chadd #include <net/ethernet.h> 81a35dae8dSAdrian Chadd #include <net/if_llc.h> 82a35dae8dSAdrian Chadd 83a35dae8dSAdrian Chadd #include <net80211/ieee80211_var.h> 84a35dae8dSAdrian Chadd #include <net80211/ieee80211_regdomain.h> 85a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_SUPERG 86a35dae8dSAdrian Chadd #include <net80211/ieee80211_superg.h> 87a35dae8dSAdrian Chadd #endif 88a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA 89a35dae8dSAdrian Chadd #include <net80211/ieee80211_tdma.h> 90a35dae8dSAdrian Chadd #endif 91a35dae8dSAdrian Chadd 92a35dae8dSAdrian Chadd #include <net/bpf.h> 93a35dae8dSAdrian Chadd 94a35dae8dSAdrian Chadd #ifdef INET 95a35dae8dSAdrian Chadd #include <netinet/in.h> 96a35dae8dSAdrian Chadd #include <netinet/if_ether.h> 97a35dae8dSAdrian Chadd #endif 98a35dae8dSAdrian Chadd 99a35dae8dSAdrian Chadd #include <dev/ath/if_athvar.h> 100a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101a35dae8dSAdrian Chadd #include <dev/ath/ath_hal/ah_diagcodes.h> 102a35dae8dSAdrian Chadd 103a35dae8dSAdrian Chadd #include <dev/ath/if_ath_debug.h> 104a35dae8dSAdrian Chadd #include <dev/ath/if_ath_misc.h> 105a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tsf.h> 106a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tx.h> 107a35dae8dSAdrian Chadd #include <dev/ath/if_ath_sysctl.h> 108a35dae8dSAdrian Chadd #include <dev/ath/if_ath_led.h> 109a35dae8dSAdrian Chadd #include <dev/ath/if_ath_keycache.h> 110a35dae8dSAdrian Chadd #include <dev/ath/if_ath_rx.h> 111a35dae8dSAdrian Chadd #include <dev/ath/if_ath_beacon.h> 112a35dae8dSAdrian Chadd #include <dev/ath/if_athdfs.h> 113a35dae8dSAdrian Chadd 114a35dae8dSAdrian Chadd #ifdef ATH_TX99_DIAG 115a35dae8dSAdrian Chadd #include <dev/ath/ath_tx99/ath_tx99.h> 116a35dae8dSAdrian Chadd #endif 117a35dae8dSAdrian Chadd 118*4bda23f9SAdrian Chadd #ifdef ATH_DEBUG_ALQ 119*4bda23f9SAdrian Chadd #include <dev/ath/if_ath_alq.h> 120*4bda23f9SAdrian Chadd #endif 121*4bda23f9SAdrian Chadd 122a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA 123a35dae8dSAdrian Chadd #include <dev/ath/if_ath_tdma.h> 124a35dae8dSAdrian Chadd 125a35dae8dSAdrian Chadd static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, 126a35dae8dSAdrian Chadd u_int32_t bintval); 127a35dae8dSAdrian Chadd static void ath_tdma_bintvalsetup(struct ath_softc *sc, 128a35dae8dSAdrian Chadd const struct ieee80211_tdma_state *tdma); 129a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */ 130a35dae8dSAdrian Chadd 131a35dae8dSAdrian Chadd #ifdef IEEE80211_SUPPORT_TDMA 132a35dae8dSAdrian Chadd static void 133a35dae8dSAdrian Chadd ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval) 134a35dae8dSAdrian Chadd { 135a35dae8dSAdrian Chadd struct ath_hal *ah = sc->sc_ah; 136a35dae8dSAdrian Chadd HAL_BEACON_TIMERS bt; 137a35dae8dSAdrian Chadd 138a35dae8dSAdrian Chadd bt.bt_intval = bintval | HAL_BEACON_ENA; 139a35dae8dSAdrian Chadd bt.bt_nexttbtt = nexttbtt; 140a35dae8dSAdrian Chadd bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep; 141a35dae8dSAdrian Chadd bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep; 142a35dae8dSAdrian Chadd bt.bt_nextatim = nexttbtt+1; 143a35dae8dSAdrian Chadd /* Enables TBTT, DBA, SWBA timers by default */ 144a35dae8dSAdrian Chadd bt.bt_flags = 0; 145*4bda23f9SAdrian Chadd #if 0 146*4bda23f9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 147*4bda23f9SAdrian Chadd "%s: intval=%d (0x%08x) nexttbtt=%u (0x%08x), nextdba=%u (0x%08x), nextswba=%u (0x%08x),nextatim=%u (0x%08x)\n", 148*4bda23f9SAdrian Chadd __func__, 149*4bda23f9SAdrian Chadd bt.bt_intval, 150*4bda23f9SAdrian Chadd bt.bt_intval, 151*4bda23f9SAdrian Chadd bt.bt_nexttbtt, 152*4bda23f9SAdrian Chadd bt.bt_nexttbtt, 153*4bda23f9SAdrian Chadd bt.bt_nextdba, 154*4bda23f9SAdrian Chadd bt.bt_nextdba, 155*4bda23f9SAdrian Chadd bt.bt_nextswba, 156*4bda23f9SAdrian Chadd bt.bt_nextswba, 157*4bda23f9SAdrian Chadd bt.bt_nextatim, 158*4bda23f9SAdrian Chadd bt.bt_nextatim); 159*4bda23f9SAdrian Chadd #endif 160*4bda23f9SAdrian Chadd 161*4bda23f9SAdrian Chadd if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET)) { 162*4bda23f9SAdrian Chadd struct if_ath_alq_tdma_timer_set t; 163*4bda23f9SAdrian Chadd t.bt_intval = htobe32(bt.bt_intval); 164*4bda23f9SAdrian Chadd t.bt_nexttbtt = htobe32(bt.bt_nexttbtt); 165*4bda23f9SAdrian Chadd t.bt_nextdba = htobe32(bt.bt_nextdba); 166*4bda23f9SAdrian Chadd t.bt_nextswba = htobe32(bt.bt_nextswba); 167*4bda23f9SAdrian Chadd t.bt_nextatim = htobe32(bt.bt_nextatim); 168*4bda23f9SAdrian Chadd t.bt_flags = htobe32(bt.bt_flags); 169*4bda23f9SAdrian Chadd t.sc_tdmadbaprep = htobe32(sc->sc_tdmadbaprep); 170*4bda23f9SAdrian Chadd t.sc_tdmaswbaprep = htobe32(sc->sc_tdmaswbaprep); 171*4bda23f9SAdrian Chadd if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET, 172*4bda23f9SAdrian Chadd sizeof(t), (char *) &t); 173*4bda23f9SAdrian Chadd } 174*4bda23f9SAdrian Chadd 175*4bda23f9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 176*4bda23f9SAdrian Chadd "%s: nexttbtt=%u (0x%08x), nexttbtt tsf=%lld (0x%08llx)\n", 177*4bda23f9SAdrian Chadd __func__, 178*4bda23f9SAdrian Chadd bt.bt_nexttbtt, 179*4bda23f9SAdrian Chadd bt.bt_nexttbtt, 180*4bda23f9SAdrian Chadd (long long) ( ((u_int64_t) (bt.bt_nexttbtt)) << 10), 181*4bda23f9SAdrian Chadd (long long) ( ((u_int64_t) (bt.bt_nexttbtt)) << 10)); 182a35dae8dSAdrian Chadd ath_hal_beaconsettimers(ah, &bt); 183a35dae8dSAdrian Chadd } 184a35dae8dSAdrian Chadd 185a35dae8dSAdrian Chadd /* 186a35dae8dSAdrian Chadd * Calculate the beacon interval. This is periodic in the 187a35dae8dSAdrian Chadd * superframe for the bss. We assume each station is configured 188a35dae8dSAdrian Chadd * identically wrt transmit rate so the guard time we calculate 189a35dae8dSAdrian Chadd * above will be the same on all stations. Note we need to 190a35dae8dSAdrian Chadd * factor in the xmit time because the hardware will schedule 191a35dae8dSAdrian Chadd * a frame for transmit if the start of the frame is within 192a35dae8dSAdrian Chadd * the burst time. When we get hardware that properly kills 193a35dae8dSAdrian Chadd * frames in the PCU we can reduce/eliminate the guard time. 194a35dae8dSAdrian Chadd * 195a35dae8dSAdrian Chadd * Roundup to 1024 is so we have 1 TU buffer in the guard time 196a35dae8dSAdrian Chadd * to deal with the granularity of the nexttbtt timer. 11n MAC's 197a35dae8dSAdrian Chadd * with 1us timer granularity should allow us to reduce/eliminate 198a35dae8dSAdrian Chadd * this. 199a35dae8dSAdrian Chadd */ 200a35dae8dSAdrian Chadd static void 201a35dae8dSAdrian Chadd ath_tdma_bintvalsetup(struct ath_softc *sc, 202a35dae8dSAdrian Chadd const struct ieee80211_tdma_state *tdma) 203a35dae8dSAdrian Chadd { 204a35dae8dSAdrian Chadd /* copy from vap state (XXX check all vaps have same value?) */ 205a35dae8dSAdrian Chadd sc->sc_tdmaslotlen = tdma->tdma_slotlen; 206a35dae8dSAdrian Chadd 207a35dae8dSAdrian Chadd sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) * 208a35dae8dSAdrian Chadd tdma->tdma_slotcnt, 1024); 209a35dae8dSAdrian Chadd sc->sc_tdmabintval >>= 10; /* TSF -> TU */ 210a35dae8dSAdrian Chadd if (sc->sc_tdmabintval & 1) 211a35dae8dSAdrian Chadd sc->sc_tdmabintval++; 212a35dae8dSAdrian Chadd 213a35dae8dSAdrian Chadd if (tdma->tdma_slot == 0) { 214a35dae8dSAdrian Chadd /* 215a35dae8dSAdrian Chadd * Only slot 0 beacons; other slots respond. 216a35dae8dSAdrian Chadd */ 217a35dae8dSAdrian Chadd sc->sc_imask |= HAL_INT_SWBA; 218a35dae8dSAdrian Chadd sc->sc_tdmaswba = 0; /* beacon immediately */ 219a35dae8dSAdrian Chadd } else { 220a35dae8dSAdrian Chadd /* XXX all vaps must be slot 0 or slot !0 */ 221a35dae8dSAdrian Chadd sc->sc_imask &= ~HAL_INT_SWBA; 222a35dae8dSAdrian Chadd } 223a35dae8dSAdrian Chadd } 224a35dae8dSAdrian Chadd 225a35dae8dSAdrian Chadd /* 226a35dae8dSAdrian Chadd * Max 802.11 overhead. This assumes no 4-address frames and 227a35dae8dSAdrian Chadd * the encapsulation done by ieee80211_encap (llc). We also 228a35dae8dSAdrian Chadd * include potential crypto overhead. 229a35dae8dSAdrian Chadd */ 230a35dae8dSAdrian Chadd #define IEEE80211_MAXOVERHEAD \ 231a35dae8dSAdrian Chadd (sizeof(struct ieee80211_qosframe) \ 232a35dae8dSAdrian Chadd + sizeof(struct llc) \ 233a35dae8dSAdrian Chadd + IEEE80211_ADDR_LEN \ 234a35dae8dSAdrian Chadd + IEEE80211_WEP_IVLEN \ 235a35dae8dSAdrian Chadd + IEEE80211_WEP_KIDLEN \ 236a35dae8dSAdrian Chadd + IEEE80211_WEP_CRCLEN \ 237a35dae8dSAdrian Chadd + IEEE80211_WEP_MICLEN \ 238a35dae8dSAdrian Chadd + IEEE80211_CRC_LEN) 239a35dae8dSAdrian Chadd 240a35dae8dSAdrian Chadd /* 241a35dae8dSAdrian Chadd * Setup initially for tdma operation. Start the beacon 242a35dae8dSAdrian Chadd * timers and enable SWBA if we are slot 0. Otherwise 243a35dae8dSAdrian Chadd * we wait for slot 0 to arrive so we can sync up before 244a35dae8dSAdrian Chadd * starting to transmit. 245a35dae8dSAdrian Chadd */ 246a35dae8dSAdrian Chadd void 247a35dae8dSAdrian Chadd ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap) 248a35dae8dSAdrian Chadd { 249a35dae8dSAdrian Chadd struct ath_hal *ah = sc->sc_ah; 250a35dae8dSAdrian Chadd struct ifnet *ifp = sc->sc_ifp; 251a35dae8dSAdrian Chadd struct ieee80211com *ic = ifp->if_l2com; 252a35dae8dSAdrian Chadd const struct ieee80211_txparam *tp; 253a35dae8dSAdrian Chadd const struct ieee80211_tdma_state *tdma = NULL; 254a35dae8dSAdrian Chadd int rix; 255a35dae8dSAdrian Chadd 256a35dae8dSAdrian Chadd if (vap == NULL) { 257a35dae8dSAdrian Chadd vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */ 258a35dae8dSAdrian Chadd if (vap == NULL) { 259a35dae8dSAdrian Chadd if_printf(ifp, "%s: no vaps?\n", __func__); 260a35dae8dSAdrian Chadd return; 261a35dae8dSAdrian Chadd } 262a35dae8dSAdrian Chadd } 263a35dae8dSAdrian Chadd /* XXX should take a locked ref to iv_bss */ 264a35dae8dSAdrian Chadd tp = vap->iv_bss->ni_txparms; 265a35dae8dSAdrian Chadd /* 266a35dae8dSAdrian Chadd * Calculate the guard time for each slot. This is the 267a35dae8dSAdrian Chadd * time to send a maximal-size frame according to the 268a35dae8dSAdrian Chadd * fixed/lowest transmit rate. Note that the interface 269a35dae8dSAdrian Chadd * mtu does not include the 802.11 overhead so we must 270a35dae8dSAdrian Chadd * tack that on (ath_hal_computetxtime includes the 271a35dae8dSAdrian Chadd * preamble and plcp in it's calculation). 272a35dae8dSAdrian Chadd */ 273a35dae8dSAdrian Chadd tdma = vap->iv_tdma; 274a35dae8dSAdrian Chadd if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 275a35dae8dSAdrian Chadd rix = ath_tx_findrix(sc, tp->ucastrate); 276a35dae8dSAdrian Chadd else 277a35dae8dSAdrian Chadd rix = ath_tx_findrix(sc, tp->mcastrate); 278a35dae8dSAdrian Chadd /* XXX short preamble assumed */ 279a35dae8dSAdrian Chadd sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates, 280a35dae8dSAdrian Chadd ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE); 281a35dae8dSAdrian Chadd 282a35dae8dSAdrian Chadd ath_hal_intrset(ah, 0); 283a35dae8dSAdrian Chadd 284a35dae8dSAdrian Chadd ath_beaconq_config(sc); /* setup h/w beacon q */ 285a35dae8dSAdrian Chadd if (sc->sc_setcca) 286a35dae8dSAdrian Chadd ath_hal_setcca(ah, AH_FALSE); /* disable CCA */ 287a35dae8dSAdrian Chadd ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */ 288a35dae8dSAdrian Chadd ath_tdma_settimers(sc, sc->sc_tdmabintval, 289a35dae8dSAdrian Chadd sc->sc_tdmabintval | HAL_BEACON_RESET_TSF); 290a35dae8dSAdrian Chadd sc->sc_syncbeacon = 0; 291a35dae8dSAdrian Chadd 292a35dae8dSAdrian Chadd sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER; 293a35dae8dSAdrian Chadd sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER; 294a35dae8dSAdrian Chadd 295a35dae8dSAdrian Chadd ath_hal_intrset(ah, sc->sc_imask); 296a35dae8dSAdrian Chadd 297a35dae8dSAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u " 298a35dae8dSAdrian Chadd "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__, 299a35dae8dSAdrian Chadd tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt, 300a35dae8dSAdrian Chadd tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval, 301a35dae8dSAdrian Chadd sc->sc_tdmadbaprep); 302*4bda23f9SAdrian Chadd 303*4bda23f9SAdrian Chadd #ifdef ATH_DEBUG_ALQ 304*4bda23f9SAdrian Chadd if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG)) { 305*4bda23f9SAdrian Chadd struct if_ath_alq_tdma_timer_config t; 306*4bda23f9SAdrian Chadd 307*4bda23f9SAdrian Chadd t.tdma_slot = htobe32(tdma->tdma_slot); 308*4bda23f9SAdrian Chadd t.tdma_slotlen = htobe32(tdma->tdma_slotlen); 309*4bda23f9SAdrian Chadd t.tdma_slotcnt = htobe32(tdma->tdma_slotcnt); 310*4bda23f9SAdrian Chadd t.tdma_bintval = htobe32(tdma->tdma_bintval); 311*4bda23f9SAdrian Chadd t.tdma_guard = htobe32(sc->sc_tdmaguard); 312*4bda23f9SAdrian Chadd t.tdma_scbintval = htobe32(sc->sc_tdmabintval); 313*4bda23f9SAdrian Chadd t.tdma_dbaprep = htobe32(sc->sc_tdmadbaprep); 314*4bda23f9SAdrian Chadd 315*4bda23f9SAdrian Chadd if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG, 316*4bda23f9SAdrian Chadd sizeof(t), (char *) &t); 317*4bda23f9SAdrian Chadd } 318*4bda23f9SAdrian Chadd #endif /* ATH_DEBUG_ALQ */ 319a35dae8dSAdrian Chadd } 320a35dae8dSAdrian Chadd 321a35dae8dSAdrian Chadd /* 322a35dae8dSAdrian Chadd * Update tdma operation. Called from the 802.11 layer 323a35dae8dSAdrian Chadd * when a beacon is received from the TDMA station operating 324a35dae8dSAdrian Chadd * in the slot immediately preceding us in the bss. Use 325a35dae8dSAdrian Chadd * the rx timestamp for the beacon frame to update our 326a35dae8dSAdrian Chadd * beacon timers so we follow their schedule. Note that 327a35dae8dSAdrian Chadd * by using the rx timestamp we implicitly include the 328a35dae8dSAdrian Chadd * propagation delay in our schedule. 329a35dae8dSAdrian Chadd */ 330a35dae8dSAdrian Chadd void 331a35dae8dSAdrian Chadd ath_tdma_update(struct ieee80211_node *ni, 332a35dae8dSAdrian Chadd const struct ieee80211_tdma_param *tdma, int changed) 333a35dae8dSAdrian Chadd { 334a35dae8dSAdrian Chadd #define TSF_TO_TU(_h,_l) \ 335a35dae8dSAdrian Chadd ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10)) 336a35dae8dSAdrian Chadd #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10) 337a35dae8dSAdrian Chadd struct ieee80211vap *vap = ni->ni_vap; 338a35dae8dSAdrian Chadd struct ieee80211com *ic = ni->ni_ic; 339a35dae8dSAdrian Chadd struct ath_softc *sc = ic->ic_ifp->if_softc; 340a35dae8dSAdrian Chadd struct ath_hal *ah = sc->sc_ah; 341a35dae8dSAdrian Chadd const HAL_RATE_TABLE *rt = sc->sc_currates; 342e6f1a34aSAdrian Chadd u_int64_t tsf, rstamp, nextslot, nexttbtt, nexttbtt_full; 343a35dae8dSAdrian Chadd u_int32_t txtime, nextslottu; 344a35dae8dSAdrian Chadd int32_t tudelta, tsfdelta; 345a35dae8dSAdrian Chadd const struct ath_rx_status *rs; 346a35dae8dSAdrian Chadd int rix; 347a35dae8dSAdrian Chadd 348a35dae8dSAdrian Chadd sc->sc_stats.ast_tdma_update++; 349a35dae8dSAdrian Chadd 350a35dae8dSAdrian Chadd /* 351a35dae8dSAdrian Chadd * Check for and adopt configuration changes. 352a35dae8dSAdrian Chadd */ 353a35dae8dSAdrian Chadd if (changed != 0) { 354a35dae8dSAdrian Chadd const struct ieee80211_tdma_state *ts = vap->iv_tdma; 355a35dae8dSAdrian Chadd 356a35dae8dSAdrian Chadd ath_tdma_bintvalsetup(sc, ts); 357a35dae8dSAdrian Chadd if (changed & TDMA_UPDATE_SLOTLEN) 358a35dae8dSAdrian Chadd ath_wme_update(ic); 359a35dae8dSAdrian Chadd 360a35dae8dSAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA, 361a35dae8dSAdrian Chadd "%s: adopt slot %u slotcnt %u slotlen %u us " 362a35dae8dSAdrian Chadd "bintval %u TU\n", __func__, 363a35dae8dSAdrian Chadd ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen, 364a35dae8dSAdrian Chadd sc->sc_tdmabintval); 365a35dae8dSAdrian Chadd 366a35dae8dSAdrian Chadd /* XXX right? */ 367a35dae8dSAdrian Chadd ath_hal_intrset(ah, sc->sc_imask); 368a35dae8dSAdrian Chadd /* NB: beacon timers programmed below */ 369a35dae8dSAdrian Chadd } 370a35dae8dSAdrian Chadd 371a35dae8dSAdrian Chadd /* extend rx timestamp to 64 bits */ 372a35dae8dSAdrian Chadd rs = sc->sc_lastrs; 373a35dae8dSAdrian Chadd tsf = ath_hal_gettsf64(ah); 374a35dae8dSAdrian Chadd rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 375a35dae8dSAdrian Chadd /* 376a35dae8dSAdrian Chadd * The rx timestamp is set by the hardware on completing 377a35dae8dSAdrian Chadd * reception (at the point where the rx descriptor is DMA'd 378a35dae8dSAdrian Chadd * to the host). To find the start of our next slot we 379a35dae8dSAdrian Chadd * must adjust this time by the time required to send 380a35dae8dSAdrian Chadd * the packet just received. 381a35dae8dSAdrian Chadd */ 382a35dae8dSAdrian Chadd rix = rt->rateCodeToIndex[rs->rs_rate]; 383a35dae8dSAdrian Chadd txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix, 384a35dae8dSAdrian Chadd rt->info[rix].shortPreamble); 385a35dae8dSAdrian Chadd /* NB: << 9 is to cvt to TU and /2 */ 386a35dae8dSAdrian Chadd nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9); 387*4bda23f9SAdrian Chadd 388e6f1a34aSAdrian Chadd /* 389e6f1a34aSAdrian Chadd * For 802.11n chips: nextslottu needs to be the full TSF space, 390e6f1a34aSAdrian Chadd * not just 0..65535 TU. 391e6f1a34aSAdrian Chadd */ 392e6f1a34aSAdrian Chadd nextslottu = TSF_TO_TU(nextslot>>32, nextslot); 393*4bda23f9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 394*4bda23f9SAdrian Chadd "rs->rstamp %llu rstamp %llu tsf %llu txtime %d, nextslot %llu, nextslottu %d, nextslottume %d\n", 395*4bda23f9SAdrian Chadd (unsigned long long) rs->rs_tstamp, rstamp, tsf, txtime, nextslot, nextslottu, TSF_TO_TU(nextslot >> 32, nextslot)); 396*4bda23f9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA, 397*4bda23f9SAdrian Chadd " beacon tstamp: %llu (0x%016llx)\n", 398*4bda23f9SAdrian Chadd le64toh(ni->ni_tstamp.tsf), 399*4bda23f9SAdrian Chadd le64toh(ni->ni_tstamp.tsf)); 400*4bda23f9SAdrian Chadd 401*4bda23f9SAdrian Chadd #ifdef ATH_DEBUG_ALQ 402*4bda23f9SAdrian Chadd if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE)) { 403*4bda23f9SAdrian Chadd struct if_ath_alq_tdma_beacon_state t; 404*4bda23f9SAdrian Chadd t.rx_tsf = htobe64(rstamp); 405*4bda23f9SAdrian Chadd t.beacon_tsf = htobe64(le64toh(ni->ni_tstamp.tsf)); 406*4bda23f9SAdrian Chadd t.tsf64 = htobe64(tsf); 407*4bda23f9SAdrian Chadd t.nextslot_tsf = htobe64(nextslot); 408*4bda23f9SAdrian Chadd t.nextslot_tu = htobe32(nextslottu); 409*4bda23f9SAdrian Chadd t.txtime = htobe32(txtime); 410*4bda23f9SAdrian Chadd if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE, 411*4bda23f9SAdrian Chadd sizeof(t), (char *) &t); 412*4bda23f9SAdrian Chadd } 413*4bda23f9SAdrian Chadd #endif 414a35dae8dSAdrian Chadd 415a35dae8dSAdrian Chadd /* 416a35dae8dSAdrian Chadd * Retrieve the hardware NextTBTT in usecs 417a35dae8dSAdrian Chadd * and calculate the difference between what the 418a35dae8dSAdrian Chadd * other station thinks and what we have programmed. This 419a35dae8dSAdrian Chadd * lets us figure how to adjust our timers to match. The 420a35dae8dSAdrian Chadd * adjustments are done by pulling the TSF forward and possibly 421a35dae8dSAdrian Chadd * rewriting the beacon timers. 422a35dae8dSAdrian Chadd */ 423ddee9211SAdrian Chadd /* 424ddee9211SAdrian Chadd * The logic here assumes the nexttbtt counter is in TSF 425ddee9211SAdrian Chadd * but the prr-11n NICs are in TU. The HAL shifts them 426ddee9211SAdrian Chadd * to TSF but there's two important differences: 427ddee9211SAdrian Chadd * 428ddee9211SAdrian Chadd * + The TU->TSF values have 0's for the low 9 bits, and 429ddee9211SAdrian Chadd * + The counter wraps at TU_TO_TSF(HAL_BEACON_PERIOD + 1) for 430ddee9211SAdrian Chadd * the pre-11n NICs, but not for the 11n NICs. 431ddee9211SAdrian Chadd * 432ddee9211SAdrian Chadd * So for now, just make sure the nexttbtt value we get 433ddee9211SAdrian Chadd * matches the second issue or once nexttbtt exceeds this 434ddee9211SAdrian Chadd * value, tsfdelta ends up becoming very negative and all 435ddee9211SAdrian Chadd * of the adjustments get very messed up. 436ddee9211SAdrian Chadd */ 437e6f1a34aSAdrian Chadd 438e6f1a34aSAdrian Chadd /* 439e6f1a34aSAdrian Chadd * We need to track the full nexttbtt rather than having it 440e6f1a34aSAdrian Chadd * truncated at HAL_BEACON_PERIOD, as programming the 441e6f1a34aSAdrian Chadd * nexttbtt (and related) registers for the 11n chips is 442e6f1a34aSAdrian Chadd * actually going to take the full 32 bit space, rather than 443e6f1a34aSAdrian Chadd * just 0..65535 TU. 444e6f1a34aSAdrian Chadd */ 445e6f1a34aSAdrian Chadd nexttbtt_full = ath_hal_getnexttbtt(ah); 446e6f1a34aSAdrian Chadd nexttbtt = nexttbtt_full % (TU_TO_TSF(HAL_BEACON_PERIOD + 1)); 447a35dae8dSAdrian Chadd tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD + 1)) - nexttbtt); 448a35dae8dSAdrian Chadd 449a35dae8dSAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 450*4bda23f9SAdrian Chadd "nexttbtt %llu (0x%08llx) tsfdelta %d avg +%d/-%d\n", 451*4bda23f9SAdrian Chadd nexttbtt, 452*4bda23f9SAdrian Chadd (long long) nexttbtt, 453*4bda23f9SAdrian Chadd tsfdelta, 454a35dae8dSAdrian Chadd TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam)); 455a35dae8dSAdrian Chadd 456*4bda23f9SAdrian Chadd #ifdef ATH_DEBUG_ALQ 457*4bda23f9SAdrian Chadd if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC)) { 458*4bda23f9SAdrian Chadd struct if_ath_alq_tdma_slot_calc t; 459*4bda23f9SAdrian Chadd 460*4bda23f9SAdrian Chadd t.nexttbtt = htobe64(nexttbtt_full); 461*4bda23f9SAdrian Chadd t.next_slot = htobe64(nextslot); 462*4bda23f9SAdrian Chadd t.tsfdelta = htobe32(tsfdelta); 463*4bda23f9SAdrian Chadd t.avg_plus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltap)); 464*4bda23f9SAdrian Chadd t.avg_minus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltam)); 465*4bda23f9SAdrian Chadd 466*4bda23f9SAdrian Chadd if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC, 467*4bda23f9SAdrian Chadd sizeof(t), (char *) &t); 468*4bda23f9SAdrian Chadd } 469*4bda23f9SAdrian Chadd #endif 470*4bda23f9SAdrian Chadd 471a35dae8dSAdrian Chadd if (tsfdelta < 0) { 472a35dae8dSAdrian Chadd TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 473a35dae8dSAdrian Chadd TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta); 474a35dae8dSAdrian Chadd tsfdelta = -tsfdelta % 1024; 475a35dae8dSAdrian Chadd nextslottu++; 476a35dae8dSAdrian Chadd } else if (tsfdelta > 0) { 477a35dae8dSAdrian Chadd TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta); 478a35dae8dSAdrian Chadd TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 479a35dae8dSAdrian Chadd tsfdelta = 1024 - (tsfdelta % 1024); 480a35dae8dSAdrian Chadd nextslottu++; 481a35dae8dSAdrian Chadd } else { 482a35dae8dSAdrian Chadd TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0); 483a35dae8dSAdrian Chadd TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0); 484a35dae8dSAdrian Chadd } 485e6f1a34aSAdrian Chadd tudelta = nextslottu - TSF_TO_TU(nexttbtt_full >> 32, nexttbtt_full); 486a35dae8dSAdrian Chadd 487a35dae8dSAdrian Chadd /* 488a35dae8dSAdrian Chadd * Copy sender's timetstamp into tdma ie so they can 489a35dae8dSAdrian Chadd * calculate roundtrip time. We submit a beacon frame 490a35dae8dSAdrian Chadd * below after any timer adjustment. The frame goes out 491a35dae8dSAdrian Chadd * at the next TBTT so the sender can calculate the 492a35dae8dSAdrian Chadd * roundtrip by inspecting the tdma ie in our beacon frame. 493a35dae8dSAdrian Chadd * 494a35dae8dSAdrian Chadd * NB: This tstamp is subtlely preserved when 495a35dae8dSAdrian Chadd * IEEE80211_BEACON_TDMA is marked (e.g. when the 496a35dae8dSAdrian Chadd * slot position changes) because ieee80211_add_tdma 497a35dae8dSAdrian Chadd * skips over the data. 498a35dae8dSAdrian Chadd */ 499a35dae8dSAdrian Chadd memcpy(ATH_VAP(vap)->av_boff.bo_tdma + 500a35dae8dSAdrian Chadd __offsetof(struct ieee80211_tdma_param, tdma_tstamp), 501a35dae8dSAdrian Chadd &ni->ni_tstamp.data, 8); 502a35dae8dSAdrian Chadd #if 0 503a35dae8dSAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 504a35dae8dSAdrian Chadd "tsf %llu nextslot %llu (%d, %d) nextslottu %u nexttbtt %llu (%d)\n", 505a35dae8dSAdrian Chadd (unsigned long long) tsf, (unsigned long long) nextslot, 506a35dae8dSAdrian Chadd (int)(nextslot - tsf), tsfdelta, nextslottu, nexttbtt, tudelta); 507a35dae8dSAdrian Chadd #endif 508a35dae8dSAdrian Chadd /* 509a35dae8dSAdrian Chadd * Adjust the beacon timers only when pulling them forward 510a35dae8dSAdrian Chadd * or when going back by less than the beacon interval. 511a35dae8dSAdrian Chadd * Negative jumps larger than the beacon interval seem to 512a35dae8dSAdrian Chadd * cause the timers to stop and generally cause instability. 513a35dae8dSAdrian Chadd * This basically filters out jumps due to missed beacons. 514a35dae8dSAdrian Chadd */ 515a35dae8dSAdrian Chadd if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) { 516*4bda23f9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 517*4bda23f9SAdrian Chadd "%s: calling ath_tdma_settimers; nextslottu=%d, bintval=%d\n", 518*4bda23f9SAdrian Chadd __func__, 519*4bda23f9SAdrian Chadd nextslottu, 520*4bda23f9SAdrian Chadd sc->sc_tdmabintval); 521a35dae8dSAdrian Chadd ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval); 522a35dae8dSAdrian Chadd sc->sc_stats.ast_tdma_timers++; 523a35dae8dSAdrian Chadd } 524a35dae8dSAdrian Chadd if (tsfdelta > 0) { 52584dd5933SAdrian Chadd uint64_t tsf; 52684dd5933SAdrian Chadd 52784dd5933SAdrian Chadd /* XXX should just teach ath_hal_adjusttsf() to do this */ 52884dd5933SAdrian Chadd tsf = ath_hal_gettsf64(ah); 52984dd5933SAdrian Chadd ath_hal_settsf64(ah, tsf + tsfdelta); 530*4bda23f9SAdrian Chadd DPRINTF(sc, ATH_DEBUG_TDMA_TIMER, 531*4bda23f9SAdrian Chadd "%s: calling ath_hal_adjusttsf: TSF=%llu, tsfdelta=%d\n", 532*4bda23f9SAdrian Chadd __func__, 533*4bda23f9SAdrian Chadd tsf_1, 534*4bda23f9SAdrian Chadd tsfdelta); 535*4bda23f9SAdrian Chadd 536*4bda23f9SAdrian Chadd #ifdef ATH_DEBUG_ALQ 537*4bda23f9SAdrian Chadd if (if_ath_alq_checkdebug(&sc->sc_alq, 538*4bda23f9SAdrian Chadd ATH_ALQ_TDMA_TSF_ADJUST)) { 539*4bda23f9SAdrian Chadd struct if_ath_alq_tdma_tsf_adjust t; 540*4bda23f9SAdrian Chadd 541*4bda23f9SAdrian Chadd t.tsfdelta = htobe32(tsfdelta); 542*4bda23f9SAdrian Chadd t.tsf64_old = htobe64(tsf_1); 543*4bda23f9SAdrian Chadd t.tsf64_new = htobe64(tsf_1 + tsfdelta); 544*4bda23f9SAdrian Chadd if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TSF_ADJUST, 545*4bda23f9SAdrian Chadd sizeof(t), (char *) &t); 546*4bda23f9SAdrian Chadd } 547*4bda23f9SAdrian Chadd #endif /* ATH_DEBUG_ALQ */ 548a35dae8dSAdrian Chadd sc->sc_stats.ast_tdma_tsf++; 549a35dae8dSAdrian Chadd } 550a35dae8dSAdrian Chadd ath_tdma_beacon_send(sc, vap); /* prepare response */ 551a35dae8dSAdrian Chadd #undef TU_TO_TSF 552a35dae8dSAdrian Chadd #undef TSF_TO_TU 553a35dae8dSAdrian Chadd } 554a35dae8dSAdrian Chadd 555a35dae8dSAdrian Chadd /* 556a35dae8dSAdrian Chadd * Transmit a beacon frame at SWBA. Dynamic updates 557a35dae8dSAdrian Chadd * to the frame contents are done as needed. 558a35dae8dSAdrian Chadd */ 559a35dae8dSAdrian Chadd void 560a35dae8dSAdrian Chadd ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap) 561a35dae8dSAdrian Chadd { 562a35dae8dSAdrian Chadd struct ath_hal *ah = sc->sc_ah; 563a35dae8dSAdrian Chadd struct ath_buf *bf; 564a35dae8dSAdrian Chadd int otherant; 565a35dae8dSAdrian Chadd 566a35dae8dSAdrian Chadd /* 567a35dae8dSAdrian Chadd * Check if the previous beacon has gone out. If 568a35dae8dSAdrian Chadd * not don't try to post another, skip this period 569a35dae8dSAdrian Chadd * and wait for the next. Missed beacons indicate 570a35dae8dSAdrian Chadd * a problem and should not occur. If we miss too 571a35dae8dSAdrian Chadd * many consecutive beacons reset the device. 572a35dae8dSAdrian Chadd */ 573a35dae8dSAdrian Chadd if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 574a35dae8dSAdrian Chadd sc->sc_bmisscount++; 575a35dae8dSAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON, 576a35dae8dSAdrian Chadd "%s: missed %u consecutive beacons\n", 577a35dae8dSAdrian Chadd __func__, sc->sc_bmisscount); 578a35dae8dSAdrian Chadd if (sc->sc_bmisscount >= ath_bstuck_threshold) 579a35dae8dSAdrian Chadd taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask); 580a35dae8dSAdrian Chadd return; 581a35dae8dSAdrian Chadd } 582a35dae8dSAdrian Chadd if (sc->sc_bmisscount != 0) { 583a35dae8dSAdrian Chadd DPRINTF(sc, ATH_DEBUG_BEACON, 584a35dae8dSAdrian Chadd "%s: resume beacon xmit after %u misses\n", 585a35dae8dSAdrian Chadd __func__, sc->sc_bmisscount); 586a35dae8dSAdrian Chadd sc->sc_bmisscount = 0; 587a35dae8dSAdrian Chadd } 588a35dae8dSAdrian Chadd 589a35dae8dSAdrian Chadd /* 590a35dae8dSAdrian Chadd * Check recent per-antenna transmit statistics and flip 591a35dae8dSAdrian Chadd * the default antenna if noticeably more frames went out 592a35dae8dSAdrian Chadd * on the non-default antenna. 593a35dae8dSAdrian Chadd * XXX assumes 2 anntenae 594a35dae8dSAdrian Chadd */ 595a35dae8dSAdrian Chadd if (!sc->sc_diversity) { 596a35dae8dSAdrian Chadd otherant = sc->sc_defant & 1 ? 2 : 1; 597a35dae8dSAdrian Chadd if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 598a35dae8dSAdrian Chadd ath_setdefantenna(sc, otherant); 599a35dae8dSAdrian Chadd sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 600a35dae8dSAdrian Chadd } 601a35dae8dSAdrian Chadd 602a35dae8dSAdrian Chadd bf = ath_beacon_generate(sc, vap); 603a35dae8dSAdrian Chadd if (bf != NULL) { 604a35dae8dSAdrian Chadd /* 605a35dae8dSAdrian Chadd * Stop any current dma and put the new frame on the queue. 606a35dae8dSAdrian Chadd * This should never fail since we check above that no frames 607a35dae8dSAdrian Chadd * are still pending on the queue. 608a35dae8dSAdrian Chadd */ 609a35dae8dSAdrian Chadd if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 610a35dae8dSAdrian Chadd DPRINTF(sc, ATH_DEBUG_ANY, 611a35dae8dSAdrian Chadd "%s: beacon queue %u did not stop?\n", 612a35dae8dSAdrian Chadd __func__, sc->sc_bhalq); 613a35dae8dSAdrian Chadd /* NB: the HAL still stops DMA, so proceed */ 614a35dae8dSAdrian Chadd } 615a35dae8dSAdrian Chadd ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 616a35dae8dSAdrian Chadd ath_hal_txstart(ah, sc->sc_bhalq); 617a35dae8dSAdrian Chadd 618a35dae8dSAdrian Chadd sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */ 619a35dae8dSAdrian Chadd 620a35dae8dSAdrian Chadd /* 621a35dae8dSAdrian Chadd * Record local TSF for our last send for use 622a35dae8dSAdrian Chadd * in arbitrating slot collisions. 623a35dae8dSAdrian Chadd */ 624a35dae8dSAdrian Chadd /* XXX should take a locked ref to iv_bss */ 625a35dae8dSAdrian Chadd vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah); 626a35dae8dSAdrian Chadd } 627a35dae8dSAdrian Chadd } 628a35dae8dSAdrian Chadd #endif /* IEEE80211_SUPPORT_TDMA */ 629